diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u535xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u535xx.h index 8e77eab269..3e1c310691 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u535xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u535xx.h @@ -11,10 +11,9 @@ * - Setup behavior of Floating Point Unit * - Setup Interrupt Target * - ******************************************************************************/ -/** - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * Portions Copyright (c) 2023 STMicroelectronics, all rights reserved + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,13 +21,14 @@ * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. + ****************************************************************************** */ #ifndef PARTITION_STM32U535XX_H diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u545xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u545xx.h index a1b41c0c18..2c808e82fe 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u545xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u545xx.h @@ -11,10 +11,9 @@ * - Setup behavior of Floating Point Unit * - Setup Interrupt Target * - ******************************************************************************/ -/** - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * Portions Copyright (c) 2023 STMicroelectronics, all rights reserved + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,13 +21,14 @@ * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. + ****************************************************************************** */ #ifndef PARTITION_STM32U545XX_H diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u575xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u575xx.h index 07c0ade428..84d78df249 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u575xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u575xx.h @@ -11,10 +11,9 @@ * - Setup behavior of Floating Point Unit * - Setup Interrupt Target * - ******************************************************************************/ -/** - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * Portions Copyright (c) 2021 STMicroelectronics, all rights reserved + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,13 +21,14 @@ * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. + ****************************************************************************** */ #ifndef PARTITION_STM32U575XX_H diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u585xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u585xx.h index 56a302a12b..42d313f7b0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u585xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u585xx.h @@ -11,10 +11,9 @@ * - Setup behavior of Floating Point Unit * - Setup Interrupt Target * - ******************************************************************************/ -/** - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * Portions Copyright (c) 2021 STMicroelectronics, all rights reserved + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,13 +21,14 @@ * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. + ****************************************************************************** */ #ifndef PARTITION_STM32U585XX_H diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h index f9da0df15d..338dc7b4b0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h @@ -11,10 +11,9 @@ * - Setup behavior of Floating Point Unit * - Setup Interrupt Target * - ******************************************************************************/ -/** - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * Portions Copyright (c) 2022 STMicroelectronics, all rights reserved + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,13 +21,14 @@ * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. + ****************************************************************************** */ #ifndef PARTITION_STM32U595XX_H diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u599xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u599xx.h index 0345cc3521..2ef210bdc1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u599xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u599xx.h @@ -11,10 +11,9 @@ * - Setup behavior of Floating Point Unit * - Setup Interrupt Target * - ******************************************************************************/ -/** - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * Portions Copyright (c) 2022 STMicroelectronics, all rights reserved + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,13 +21,14 @@ * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. + ****************************************************************************** */ #ifndef PARTITION_STM32U599XX_H diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5a5xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5a5xx.h index f35205d389..5af5fc24de 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5a5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5a5xx.h @@ -11,10 +11,9 @@ * - Setup behavior of Floating Point Unit * - Setup Interrupt Target * - ******************************************************************************/ -/** - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * Portions Copyright (c) 2022 STMicroelectronics, all rights reserved + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,13 +21,14 @@ * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. + ****************************************************************************** */ #ifndef PARTITION_STM32U5A5XX_H diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5a9xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5a9xx.h index 2cc2221d01..1473f9751f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5a9xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5a9xx.h @@ -11,10 +11,9 @@ * - Setup behavior of Floating Point Unit * - Setup Interrupt Target * - ******************************************************************************/ -/** - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * Portions Copyright (c) 2022 STMicroelectronics, all rights reserved + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,13 +21,14 @@ * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. + ****************************************************************************** */ #ifndef PARTITION_STM32U5A9XX_H diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h index 36e09bbb10..b2b84c4f9c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h @@ -11,10 +11,9 @@ * - Setup behavior of Floating Point Unit * - Setup Interrupt Target * - ******************************************************************************/ -/** - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * Portions Copyright (c) 2022 STMicroelectronics, all rights reserved + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,13 +21,14 @@ * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. + ****************************************************************************** */ #ifndef PARTITION_STM32U5F7XX_H diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f9xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f9xx.h index 3c52690c44..e0c9ab3ce5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f9xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f9xx.h @@ -11,10 +11,9 @@ * - Setup behavior of Floating Point Unit * - Setup Interrupt Target * - ******************************************************************************/ -/** - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * Portions Copyright (c) 2022 STMicroelectronics, all rights reserved + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,13 +21,14 @@ * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. + ****************************************************************************** */ #ifndef PARTITION_STM32U5F9XX_H diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5g7xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5g7xx.h index 72d1f95084..05609c04f8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5g7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5g7xx.h @@ -11,10 +11,9 @@ * - Setup behavior of Floating Point Unit * - Setup Interrupt Target * - ******************************************************************************/ -/** - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * Portions Copyright (c) 2022 STMicroelectronics, all rights reserved + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,13 +21,14 @@ * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. + ****************************************************************************** */ #ifndef PARTITION_STM32U5G7XX_H diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5g9xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5g9xx.h index 0b40501daf..a0ba7aee6c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5g9xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5g9xx.h @@ -11,10 +11,9 @@ * - Setup behavior of Floating Point Unit * - Setup Interrupt Target * - ******************************************************************************/ -/** - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * Portions Copyright (c) 2022 STMicroelectronics, all rights reserved + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,13 +21,14 @@ * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. + ****************************************************************************** */ #ifndef PARTITION_STM32U5G9XX_H diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h index 0c27bfb044..4c1c81abc7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h @@ -337,7 +337,7 @@ typedef struct __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - uint32_t RESERVED; + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; @@ -587,11 +587,6 @@ typedef struct __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ - uint32_t RESERVED2[240]; /*!< Reserved, Address offset: 0x30-0x3EC */ - __IO uint32_t HWCFGR; /*!< ICACHE HW configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< ICACHE version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ICACHE IP identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ICACHE size identification register, Address offset: 0x3FC */ } ICACHE_TypeDef; /** @@ -1096,19 +1091,18 @@ typedef struct */ typedef struct { - __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ - __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ - __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ - __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ - __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ - __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ - __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ - __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ - uint32_t RESERVED2[16];/*!< RESERVED2, Address offset: 0x30 - 0x6C */ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ } SYSCFG_TypeDef; /** @@ -4649,7 +4643,7 @@ typedef struct #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) -#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ @@ -4778,6 +4772,26 @@ typedef struct #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ #define RNG_SR_SEIS RNG_SR_SEIS_Msk +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9U) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12U) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15U) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + /******************** Bits definition for RNG_HTCR register *******************/ #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ @@ -7450,7 +7464,7 @@ typedef struct /* FLASH */ /* */ /******************************************************************************/ -#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycles */ #define FLASH_SIZE_DEFAULT 0x80000U /*!< Flash memory default size */ #define FLASH_BLOCKBASED_NB_REG (1U) /*!< 1 Block-based register for each Flash bank */ @@ -10400,27 +10414,27 @@ typedef struct /******************* Bit definition for TIM_CCR1 register *******************/ #define TIM_CCR1_CCR1_Pos (0U) -#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ +#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */ #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!Release Notes for  STM32U5xx C

Update History

- +

Main Changes

+

CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

+
    +
  • Add Bits definition for RNG_NSCR register for RNG noise source control
    • +
  • Rename RTC_CR_ALRAOCLR to RTC_CR_ALRAFCLR definition
    • +
  • Rename RTC_CR_ALRBOCLR to RTC_CR_ALRBFCLR definition
    • +
  • Remove SYSCFG_UCPD_CC1ENRXFILTER and SYSCFG_UCPD_CC2ENRXFILTER defines
    • +
  • Remove COMP2 dependency in “stm32u545xx.h” and “stm32u545xx.h” files by removing TIM1_AF1_BKCMP2E, TIM1_AF1_BKCMP2P, TIM1_AF2_BK2CMP2E and TIM1_AF2_BK2CMP2P defines
    • +
  • Remove PWR_PDCRI register in “stm32u545xx.h” and “stm32u545xx.h” files by removing PWR_PDCRI_PD0, PWR_PDCRI_PD1, PWR_PDCRI_PD2, PWR_PDCRI_PD3, PWR_PDCRI_PD4, PWR_PDCRI_PD5, PWR_PDCRI_PD6 and PWR_PDCRI_PD0 defines
    • +
  • Update partition_stm32u5XXxx.h files headers
    • +
  • Fix wrong declaration of g_pfnVectors size in GCC startup_stm32u5XXxx.s files
    • +
  • Update linker files to properly mark sections readonly for GCC12
    • +
+

Backward Compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Update STM32U5A5xx devices list with STM32U5A5QII3Q under “stm32u5xx.h” file
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -46,7 +68,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Support of new STM32U5F9xx, STM32U5G9xx, STM32U5F7xx and STM32U5G7xx devices: @@ -56,7 +78,7 @@

    Main Changes

  • Add linker files for EWARM and STM32CubeIDE toolchains of STM32U5F9xx/STM32U5G9xx/STM32U5F7xx/STM32U5G7xx devices
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -65,7 +87,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Support of stm32u535xx and stm32u545xx devices: @@ -118,7 +140,7 @@

    Main Changes

  • Rename ADC4_PW_VREFSECSMP to ADC4_PWRR_VREFSECSMP
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -127,7 +149,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

  • CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
      @@ -157,7 +179,7 @@

      Main Changes

      -

      Main Changes

      +

      Main Changes

      • Rename OTG_FS_BASE_NS to USB_OTG_FS_BASE_NS define
      • Rename OTG_FS_BASE_S to USB_OTG_FS_BASE_S define
        • @@ -169,7 +191,7 @@

        Main Changes

        -

        Main Changes

        +

        Main Changes

        • First official release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
        diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH.ld index 840ea9ff30..c72c0b7e86 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH.ld @@ -80,26 +80,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -107,7 +107,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_ns.ld index bde8009dae..6e456b6753 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_ns.ld @@ -79,26 +79,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -106,7 +106,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_s.ld index aba6adb2ab..801e17b555 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_FLASH_s.ld @@ -80,26 +80,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -107,7 +107,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM.ld index f6a04bfd72..f21cecf0be 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM.ld @@ -80,26 +80,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -107,7 +107,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_ns.ld index 1d96839737..5f94a00bf3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_ns.ld @@ -80,26 +80,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -107,7 +107,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_s.ld index 6e6f053ce3..7d1b0f7bc7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U535xx_RAM_s.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH.ld index 6e94d06a58..e71a045604 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH.ld @@ -80,26 +80,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -107,7 +107,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_ns.ld index 1392e52dc4..72cfba3ca1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_ns.ld @@ -79,26 +79,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -106,7 +106,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_s.ld index f88dcfff8d..08e106564b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_FLASH_s.ld @@ -80,26 +80,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -107,7 +107,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM.ld index 37aff418eb..5380959ba3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM.ld @@ -80,26 +80,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -107,7 +107,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_ns.ld index e7def1859f..f08d2e677c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_ns.ld @@ -80,26 +80,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -107,7 +107,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_s.ld index aff3396c4e..49f0d35367 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U545xx_RAM_s.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld index 0f41473408..3393c8bf9f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld @@ -87,13 +87,15 @@ SECTIONS . = ALIGN(8); } >ROM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(8); } >ROM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); __exidx_start = .; *(.ARM.exidx*) @@ -101,7 +103,7 @@ SECTIONS . = ALIGN(8); } >ROM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -110,7 +112,7 @@ SECTIONS . = ALIGN(8); } >ROM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__init_array_start = .); @@ -120,7 +122,7 @@ SECTIONS . = ALIGN(8); } >ROM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_ns.ld index 1f057c8022..e45a87c5d1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_ns.ld @@ -87,13 +87,15 @@ SECTIONS . = ALIGN(8); } >ROM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(8); } >ROM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); __exidx_start = .; *(.ARM.exidx*) @@ -101,7 +103,7 @@ SECTIONS . = ALIGN(8); } >ROM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -110,7 +112,7 @@ SECTIONS . = ALIGN(8); } >ROM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__init_array_start = .); @@ -120,7 +122,7 @@ SECTIONS . = ALIGN(8); } >ROM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_s.ld index 82baf2407e..40a828a252 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_FLASH_s.ld @@ -88,13 +88,15 @@ SECTIONS . = ALIGN(8); } >ROM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(8); } >ROM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); __exidx_start = .; *(.ARM.exidx*) @@ -102,7 +104,7 @@ SECTIONS . = ALIGN(8); } >ROM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -111,7 +113,7 @@ SECTIONS . = ALIGN(8); } >ROM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__init_array_start = .); @@ -121,7 +123,7 @@ SECTIONS . = ALIGN(8); } >ROM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM.ld index 3b8efd1c8c..c4a2af226d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM.ld @@ -85,13 +85,15 @@ SECTIONS . = ALIGN(8); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(8); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); __exidx_start = .; *(.ARM.exidx*) @@ -99,7 +101,7 @@ SECTIONS . = ALIGN(8); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -108,7 +110,7 @@ SECTIONS . = ALIGN(8); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__init_array_start = .); @@ -118,7 +120,7 @@ SECTIONS . = ALIGN(8); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_ns.ld index a3139943e0..2b006d447e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_ns.ld @@ -85,13 +85,15 @@ SECTIONS . = ALIGN(8); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(8); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); __exidx_start = .; *(.ARM.exidx*) @@ -99,7 +101,7 @@ SECTIONS . = ALIGN(8); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -108,7 +110,7 @@ SECTIONS . = ALIGN(8); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__init_array_start = .); @@ -118,7 +120,7 @@ SECTIONS . = ALIGN(8); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_s.ld index ceaf578d79..d54ffd24bc 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U575xx_RAM_s.ld @@ -86,13 +86,15 @@ SECTIONS . = ALIGN(8); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(8); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); __exidx_start = .; *(.ARM.exidx*) @@ -100,7 +102,7 @@ SECTIONS . = ALIGN(8); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -109,7 +111,7 @@ SECTIONS . = ALIGN(8); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__init_array_start = .); @@ -119,7 +121,7 @@ SECTIONS . = ALIGN(8); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH.ld index c69c687196..7bfff4f4b8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH.ld @@ -87,13 +87,15 @@ SECTIONS . = ALIGN(8); } >ROM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(8); } >ROM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); __exidx_start = .; *(.ARM.exidx*) @@ -101,7 +103,7 @@ SECTIONS . = ALIGN(8); } >ROM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -110,7 +112,7 @@ SECTIONS . = ALIGN(8); } >ROM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__init_array_start = .); @@ -120,7 +122,7 @@ SECTIONS . = ALIGN(8); } >ROM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_ns.ld index e44bef897c..8c6c94b55a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_ns.ld @@ -87,13 +87,15 @@ SECTIONS . = ALIGN(8); } >ROM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(8); } >ROM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); __exidx_start = .; *(.ARM.exidx*) @@ -101,7 +103,7 @@ SECTIONS . = ALIGN(8); } >ROM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -110,7 +112,7 @@ SECTIONS . = ALIGN(8); } >ROM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__init_array_start = .); @@ -120,7 +122,7 @@ SECTIONS . = ALIGN(8); } >ROM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_s.ld index b4fab0f0ed..70782a7271 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_FLASH_s.ld @@ -88,13 +88,15 @@ SECTIONS . = ALIGN(8); } >ROM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(8); } >ROM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); __exidx_start = .; *(.ARM.exidx*) @@ -102,7 +104,7 @@ SECTIONS . = ALIGN(8); } >ROM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -111,7 +113,7 @@ SECTIONS . = ALIGN(8); } >ROM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__init_array_start = .); @@ -121,7 +123,7 @@ SECTIONS . = ALIGN(8); } >ROM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM.ld index 28cf4d2f0c..5d802538fc 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM.ld @@ -85,13 +85,15 @@ SECTIONS . = ALIGN(8); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(8); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); __exidx_start = .; *(.ARM.exidx*) @@ -99,7 +101,7 @@ SECTIONS . = ALIGN(8); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -108,7 +110,7 @@ SECTIONS . = ALIGN(8); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__init_array_start = .); @@ -118,7 +120,7 @@ SECTIONS . = ALIGN(8); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_ns.ld index 3205da726a..047c640eb2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_ns.ld @@ -85,13 +85,15 @@ SECTIONS . = ALIGN(8); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(8); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); __exidx_start = .; *(.ARM.exidx*) @@ -99,7 +101,7 @@ SECTIONS . = ALIGN(8); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -108,7 +110,7 @@ SECTIONS . = ALIGN(8); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__init_array_start = .); @@ -118,7 +120,7 @@ SECTIONS . = ALIGN(8); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_s.ld index 69dc7c1f1c..1302e9fbe8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U585xx_RAM_s.ld @@ -86,13 +86,15 @@ SECTIONS . = ALIGN(8); } >RAM - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(8); } >RAM - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(8); __exidx_start = .; *(.ARM.exidx*) @@ -100,7 +102,7 @@ SECTIONS . = ALIGN(8); } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -109,7 +111,7 @@ SECTIONS . = ALIGN(8); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__init_array_start = .); @@ -119,7 +121,7 @@ SECTIONS . = ALIGN(8); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(8); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH.ld index 735241182d..643befe6a1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_ns.ld index d93a08cdd6..8c191d6e74 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_ns.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_s.ld index 0019047d8f..aa02d21efb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_FLASH_s.ld @@ -82,26 +82,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -109,7 +109,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM.ld index 0f3bef7f62..cad9a002fe 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_ns.ld index e497da9885..48cd502e37 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_ns.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_s.ld index 3908060eb6..db39f0db47 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U595xx_RAM_s.ld @@ -82,26 +82,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -109,7 +109,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH.ld index 3be1f1a75b..38155f460c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_ns.ld index f207971f3d..aeff9959fd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_ns.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_s.ld index 8713d67340..407171a909 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_FLASH_s.ld @@ -82,26 +82,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -109,7 +109,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM.ld index 791d8c4a92..ca59355c44 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_ns.ld index 4a2b8d13b2..881f517c51 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_ns.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_s.ld index 27b4c18410..2face12bec 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U599xx_RAM_s.ld @@ -82,26 +82,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -109,7 +109,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH.ld index 705ba6ff9c..eb60f5cde5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_ns.ld index a5be43cae6..d1701b100c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_ns.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_s.ld index 82bf929248..a23797ccf3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_FLASH_s.ld @@ -82,26 +82,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -109,7 +109,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM.ld index 4a4451e7e8..eb64b0fab4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_ns.ld index 40763c5467..dbe26e1415 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_ns.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_s.ld index 9c8dd9b9d8..ca8c9ab27a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A9xx_RAM_s.ld @@ -82,26 +82,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -109,7 +109,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH.ld index 98d399145e..c7286bd5f9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_ns.ld index 6308d6c2c6..cce9afa7ff 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_ns.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_s.ld index 08e928905d..ed059605a2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_FLASH_s.ld @@ -82,26 +82,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -109,7 +109,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM.ld index ab48667406..95c5c2616a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_ns.ld index 92e59cfc56..68ff41c003 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_ns.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_s.ld index beef9f491a..360af3c8dd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F7xx_RAM_s.ld @@ -82,26 +82,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -109,7 +109,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH.ld index 2db8de309e..019958c1bb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_ns.ld index 652945ca28..39268b20e8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_ns.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_s.ld index b9763f2fb7..6efd7ecfaf 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_FLASH_s.ld @@ -82,26 +82,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -109,7 +109,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM.ld index 9effdc18ad..4b29003ad5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_ns.ld index 2ffbefa28f..fe10e21230 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_ns.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_s.ld index 6e89a06147..23bfbb24c0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5F9xx_RAM_s.ld @@ -82,26 +82,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -109,7 +109,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH.ld index c999420af7..7763098984 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_ns.ld index ccfba58526..968b831346 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_ns.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_s.ld index fb045bda16..6e0517c440 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_FLASH_s.ld @@ -82,26 +82,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -109,7 +109,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM.ld index 8d94012a6b..30507f4eca 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_ns.ld index b0a3f1e7e5..66e8148ab7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_ns.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_s.ld index d6cf5315af..1961207118 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G7xx_RAM_s.ld @@ -82,26 +82,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -109,7 +109,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH.ld index ab67f57297..da9f1c5940 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_ns.ld index 3ecb7c72df..594c1e30ad 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_ns.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_s.ld index 523742f8b1..8e8708875c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_s.ld @@ -82,26 +82,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >FLASH - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -109,7 +109,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM.ld index a594af1402..fb56881fd5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_ns.ld index 69850d6363..4a93304254 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_ns.ld @@ -81,26 +81,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -108,7 +108,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_s.ld index 8c501493ad..6320c1e7b0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_s.ld @@ -82,26 +82,26 @@ SECTIONS *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ } >RAM - .ARM.extab : + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM - .ARM : + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) @@ -109,7 +109,7 @@ SECTIONS PROVIDE_HIDDEN (__init_array_end = .); } >RAM - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u535xx.s b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u535xx.s index 00f17eefdb..80aa951a9a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u535xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u535xx.s @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - * Copyright (c) ${year} STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -124,7 +124,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -270,6 +269,8 @@ g_pfnVectors: .word FMAC_IRQHandler .word LSECSSD_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u545xx.s b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u545xx.s index cbcba6c809..ff2e215f24 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u545xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u545xx.s @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - * Copyright (c) ${year} STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -124,7 +124,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -270,6 +269,8 @@ g_pfnVectors: .word FMAC_IRQHandler .word LSECSSD_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u575xx.s b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u575xx.s index c5892fe20d..b4bb118311 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u575xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u575xx.s @@ -123,7 +123,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -270,6 +269,8 @@ g_pfnVectors: .word FMAC_IRQHandler .word LSECSSD_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u585xx.s b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u585xx.s index b0f12aae7d..d509e8a941 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u585xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u585xx.s @@ -123,7 +123,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -270,6 +269,8 @@ g_pfnVectors: .word FMAC_IRQHandler .word LSECSSD_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u595xx.s b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u595xx.s index 9fc96ce1b1..1ba915471c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u595xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u595xx.s @@ -123,7 +123,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -276,6 +275,8 @@ g_pfnVectors: .word I2C6_EV_IRQHandler .word HSPI1_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u599xx.s b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u599xx.s index 355f1ea671..1c803633d5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u599xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u599xx.s @@ -123,7 +123,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -283,6 +282,8 @@ g_pfnVectors: .word DSI_IRQHandler .word DCACHE2_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5a5xx.s b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5a5xx.s index b8a1f325b4..3016a5e149 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5a5xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5a5xx.s @@ -123,7 +123,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -276,6 +275,8 @@ g_pfnVectors: .word I2C6_EV_IRQHandler .word HSPI1_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5a9xx.s b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5a9xx.s index cf3f13bb27..c88a1236cd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5a9xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5a9xx.s @@ -123,7 +123,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -283,6 +282,8 @@ g_pfnVectors: .word DSI_IRQHandler .word DCACHE2_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5f7xx.s b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5f7xx.s index 8a6f73c5ae..c61c791653 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5f7xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5f7xx.s @@ -123,7 +123,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -285,6 +284,8 @@ g_pfnVectors: .word GFXTIM_IRQHandler .word JPEG_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5f9xx.s b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5f9xx.s index 7fffbeebc3..b07944d002 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5f9xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5f9xx.s @@ -123,7 +123,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -285,6 +284,8 @@ g_pfnVectors: .word GFXTIM_IRQHandler .word JPEG_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5g7xx.s b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5g7xx.s index 45ae98b2c5..dc39a58ef6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5g7xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5g7xx.s @@ -123,7 +123,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -285,6 +284,8 @@ g_pfnVectors: .word GFXTIM_IRQHandler .word JPEG_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5g9xx.s b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5g9xx.s index d995215601..f227a48907 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5g9xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/startup_stm32u5g9xx.s @@ -123,7 +123,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -285,6 +284,8 @@ g_pfnVectors: .word GFXTIM_IRQHandler .word JPEG_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 1dbd16b735..e33baf123b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -16,7 +16,7 @@ * STM32L4: 1.7.3 * STM32L5: 1.0.6 * STM32MP1: 1.6.0 - * STM32U5: 1.3.1 + * STM32U5: 1.4.0 * STM32WB: 1.12.0 * STM32WBA: 1.2.0 * STM32WL: 1.2.0 diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index b57ca782a2..d10f6f6f89 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -275,7 +275,7 @@ extern "C" { #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5) +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif @@ -548,6 +548,16 @@ extern "C" { #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ /** * @} @@ -1239,10 +1249,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) +#if defined(STM32H5) || defined(STM32H7RS) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 */ +#endif /* STM32H5 || STM32H7RS */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1254,10 +1264,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1595,6 +1605,8 @@ extern "C" { #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + /** * @} */ @@ -1987,12 +1999,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS */ /** * @} @@ -2307,8 +2319,8 @@ extern "C" { #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -2341,8 +2353,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ @@ -2399,8 +2411,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ @@ -2417,7 +2429,7 @@ extern "C" { __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif +#endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) @@ -3642,8 +3654,12 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) + defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3745,9 +3761,10 @@ extern "C" { #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 - +#if !defined(STM32U0) #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 @@ -3893,7 +3910,7 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3930,7 +3947,8 @@ extern "C" { #if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ defined (STM32H7) || \ - defined (STM32L0) || defined (STM32L1) + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) #define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG #endif @@ -4215,6 +4233,9 @@ extern "C" { #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h index 376c4fee27..08fef12a8b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h @@ -81,7 +81,6 @@ extern HAL_TickFreqTypeDef uwTickFreq; */ - /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants * @{ */ @@ -231,6 +230,10 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define SYSCFG_OTG_HS_PHY_UNDERRESET 0x00000000U /*!< PHY under reset */ #define SYSCFG_OTG_HS_PHY_ENABLE SYSCFG_OTGHSPHYCR_EN /*!< PHY enabled */ +/** + * @} + */ + /** @defgroup SYSCFG_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current * @{ */ @@ -271,6 +274,7 @@ extern HAL_TickFreqTypeDef uwTickFreq; /** * @} */ + #endif /* SYSCFG_OTGHSPHYCR_EN */ /** * @} @@ -681,13 +685,14 @@ extern HAL_TickFreqTypeDef uwTickFreq; /** * @} */ + /* Exported functions --------------------------------------------------------*/ -/** @addtogroup HAL_Exported_Functions +/** @addtogroup HAL_Exported_Functions HAL Exported Functions * @{ */ -/** @addtogroup HAL_Exported_Functions_Group1 +/** @addtogroup HAL_Exported_Functions_Group1 HAL Initialization and de-initialization Functions * @{ */ @@ -702,7 +707,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); * @} */ -/** @addtogroup HAL_Exported_Functions_Group2 +/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions * @{ */ @@ -726,7 +731,7 @@ uint32_t HAL_GetUIDw2(void); * @} */ -/** @addtogroup HAL_Exported_Functions_Group3 +/** @addtogroup HAL_Exported_Functions_Group3 HAL Debug functions * @{ */ @@ -740,7 +745,7 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); * @} */ -/** @addtogroup HAL_Exported_Functions_Group4 +/** @addtogroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions * @{ */ @@ -762,6 +767,8 @@ void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent); #endif /* SYSCFG_OTGHSPHYCR_EN */ void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); +void HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection(void); +void HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection(void); void HAL_SYSCFG_EnableSRAMCached(void); void HAL_SYSCFG_DisableSRAMCached(void); void HAL_SYSCFG_EnableVddCompensationCell(void); @@ -778,7 +785,7 @@ void HAL_SYSCFG_DisableVddHSPICompensationCell(void); * @} */ -/** @addtogroup HAL_Exported_Functions_Group5 +/** @addtogroup HAL_Exported_Functions_Group5 HAL SYSCFG lock management functions * @{ */ @@ -792,7 +799,7 @@ HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** @addtogroup HAL_Exported_Functions_Group6 +/** @addtogroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions * @{ */ @@ -818,10 +825,6 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri * @} */ -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_comp.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_comp.h index ce1aa45d65..7220ae1737 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_comp.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_comp.h @@ -535,10 +535,10 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) /** * @brief Disable the COMP2 EXTI line rising & falling edge trigger. @@ -753,11 +753,11 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /* Exported functions --------------------------------------------------------*/ -/** @addtogroup COMP_Exported_Functions +/** @addtogroup COMP_Exported_Functions COMP Exported Functions * @{ */ -/** @addtogroup COMP_Exported_Functions_Group1 +/** @addtogroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions * @{ */ @@ -778,7 +778,7 @@ HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COM */ /* IO operation functions *****************************************************/ -/** @addtogroup COMP_Exported_Functions_Group2 +/** @addtogroup COMP_Exported_Functions_Group2 Start-Stop operation functions * @{ */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp); @@ -789,7 +789,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); */ /* Peripheral Control functions ************************************************/ -/** @addtogroup COMP_Exported_Functions_Group3 +/** @addtogroup COMP_Exported_Functions_Group3 Peripheral Control functions * @{ */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); @@ -801,7 +801,7 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); */ /* Peripheral State functions **************************************************/ -/** @addtogroup COMP_Exported_Functions_Group4 +/** @addtogroup COMP_Exported_Functions_Group4 Peripheral State functions * @{ */ HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_conf_template.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_conf_template.h index d112223f25..8cc35d2100 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_conf_template.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_conf_template.h @@ -8,7 +8,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021-2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -144,7 +144,7 @@ extern "C" { vary depending on the variations in voltage and temperature.*/ #if !defined (LSI_STARTUP_TIMEOUT) -#define LSI_STARTUP_TIMEOUT 130UL /*!< Time out for LSI start up, in ms */ +#define LSI_STARTUP_TIMEOUT 130UL /*!< Time out for LSI start up, in us */ #endif /* LSI_STARTUP_TIMEOUT */ /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h index 835236a61e..0e0e4fd4bd 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h @@ -153,7 +153,7 @@ typedef struct * @{ */ #define MPU_ACCESS_NOT_SHAREABLE 0U -#define MPU_ACCESS_OUTER_SHAREABLE 1U +#define MPU_ACCESS_OUTER_SHAREABLE 2U #define MPU_ACCESS_INNER_SHAREABLE 3U /** * @} @@ -272,17 +272,22 @@ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +uint32_t HAL_SYSTICK_GetCLKSourceConfig(void); void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_Callback(void); void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit); void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* MPU_NS Control functions ***********************************************/ void HAL_MPU_Enable_NS(uint32_t MPU_Control); void HAL_MPU_Disable_NS(void); +void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber); +void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber); void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit); void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); #endif /* __ARM_FEATURE_CMSE */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h index 7309044f72..72153b44e9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h @@ -251,174 +251,174 @@ typedef struct __DMA_HandleTypeDef * @{ */ /* GPDMA1 requests */ -#define GPDMA1_REQUEST_ADC1 (0U) /*!< GPDMA1 HW request is ADC1 */ -#define GPDMA1_REQUEST_ADC4 (1U) /*!< GPDMA1 HW request is ADC4 */ -#define GPDMA1_REQUEST_DAC1_CH1 (2U) /*!< GPDMA1 HW request is DAC1_CH1 */ -#define GPDMA1_REQUEST_DAC1_CH2 (3U) /*!< GPDMA1 HW request is DAC1_CH2 */ -#define GPDMA1_REQUEST_TIM6_UP (4U) /*!< GPDMA1 HW request is TIM6_UP */ -#define GPDMA1_REQUEST_TIM7_UP (5U) /*!< GPDMA1 HW request is TIM7_UP */ -#define GPDMA1_REQUEST_SPI1_RX (6U) /*!< GPDMA1 HW request is SPI1_RX */ -#define GPDMA1_REQUEST_SPI1_TX (7U) /*!< GPDMA1 HW request is SPI1_TX */ -#define GPDMA1_REQUEST_SPI2_RX (8U) /*!< GPDMA1 HW request is SPI2_RX */ -#define GPDMA1_REQUEST_SPI2_TX (9U) /*!< GPDMA1 HW request is SPI2_TX */ -#define GPDMA1_REQUEST_SPI3_RX (10U) /*!< GPDMA1 HW request is SPI3_RX */ -#define GPDMA1_REQUEST_SPI3_TX (11U) /*!< GPDMA1 HW request is SPI3_TX */ -#define GPDMA1_REQUEST_I2C1_RX (12U) /*!< GPDMA1 HW request is I2C1_RX */ -#define GPDMA1_REQUEST_I2C1_TX (13U) /*!< GPDMA1 HW request is I2C1_TX */ -#define GPDMA1_REQUEST_I2C1_EVC (14U) /*!< GPDMA1 HW request is I2C1_EVC */ -#define GPDMA1_REQUEST_I2C2_RX (15U) /*!< GPDMA1 HW request is I2C2_RX */ -#define GPDMA1_REQUEST_I2C2_TX (16U) /*!< GPDMA1 HW request is I2C2_TX */ -#define GPDMA1_REQUEST_I2C2_EVC (17U) /*!< GPDMA1 HW request is I2C2_EVC */ -#define GPDMA1_REQUEST_I2C3_RX (18U) /*!< GPDMA1 HW request is I2C3_RX */ -#define GPDMA1_REQUEST_I2C3_TX (19U) /*!< GPDMA1 HW request is I2C3_TX */ -#define GPDMA1_REQUEST_I2C3_EVC (20U) /*!< GPDMA1 HW request is I2C3_EVC */ -#define GPDMA1_REQUEST_I2C4_RX (21U) /*!< GPDMA1 HW request is I2C4_RX */ -#define GPDMA1_REQUEST_I2C4_TX (22U) /*!< GPDMA1 HW request is I2C4_TX */ -#define GPDMA1_REQUEST_I2C4_EVC (23U) /*!< GPDMA1 HW request is I2C4_EVC */ -#define GPDMA1_REQUEST_USART1_RX (24U) /*!< GPDMA1 HW request is USART1_RX */ -#define GPDMA1_REQUEST_USART1_TX (25U) /*!< GPDMA1 HW request is USART1_TX */ +#define GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */ +#define GPDMA1_REQUEST_ADC4 1U /*!< GPDMA1 HW request is ADC4 */ +#define GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW request is DAC1_CH1 */ +#define GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW request is DAC1_CH2 */ +#define GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW request is TIM6_UP */ +#define GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW request is TIM7_UP */ +#define GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW request is SPI1_RX */ +#define GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW request is SPI1_TX */ +#define GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW request is SPI2_RX */ +#define GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW request is SPI2_TX */ +#define GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW request is SPI3_RX */ +#define GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW request is SPI3_TX */ +#define GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW request is I2C1_RX */ +#define GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW request is I2C1_TX */ +#define GPDMA1_REQUEST_I2C1_EVC 14U /*!< GPDMA1 HW request is I2C1_EVC */ +#define GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW request is I2C2_RX */ +#define GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW request is I2C2_TX */ +#define GPDMA1_REQUEST_I2C2_EVC 17U /*!< GPDMA1 HW request is I2C2_EVC */ +#define GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW request is I2C3_RX */ +#define GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW request is I2C3_TX */ +#define GPDMA1_REQUEST_I2C3_EVC 20U /*!< GPDMA1 HW request is I2C3_EVC */ +#define GPDMA1_REQUEST_I2C4_RX 21U /*!< GPDMA1 HW request is I2C4_RX */ +#define GPDMA1_REQUEST_I2C4_TX 22U /*!< GPDMA1 HW request is I2C4_TX */ +#define GPDMA1_REQUEST_I2C4_EVC 23U /*!< GPDMA1 HW request is I2C4_EVC */ +#define GPDMA1_REQUEST_USART1_RX 24U /*!< GPDMA1 HW request is USART1_RX */ +#define GPDMA1_REQUEST_USART1_TX 25U /*!< GPDMA1 HW request is USART1_TX */ #if defined(USART2) -#define GPDMA1_REQUEST_USART2_RX (26U) /*!< GPDMA1 HW request is USART2_RX */ -#define GPDMA1_REQUEST_USART2_TX (27U) /*!< GPDMA1 HW request is USART2_TX */ +#define GPDMA1_REQUEST_USART2_RX 26U /*!< GPDMA1 HW request is USART2_RX */ +#define GPDMA1_REQUEST_USART2_TX 27U /*!< GPDMA1 HW request is USART2_TX */ #endif /* USART2 */ -#define GPDMA1_REQUEST_USART3_RX (28U) /*!< GPDMA1 HW request is USART3_RX */ -#define GPDMA1_REQUEST_USART3_TX (29U) /*!< GPDMA1 HW request is USART3_TX */ -#define GPDMA1_REQUEST_UART4_RX (30U) /*!< GPDMA1 HW request is UART4_RX */ -#define GPDMA1_REQUEST_UART4_TX (31U) /*!< GPDMA1 HW request is UART4_TX */ -#define GPDMA1_REQUEST_UART5_RX (32U) /*!< GPDMA1 HW request is UART5_RX */ -#define GPDMA1_REQUEST_UART5_TX (33U) /*!< GPDMA1 HW request is UART5_TX */ -#define GPDMA1_REQUEST_LPUART1_RX (34U) /*!< GPDMA1 HW request is LPUART1_RX */ -#define GPDMA1_REQUEST_LPUART1_TX (35U) /*!< GPDMA1 HW request is LPUART1_TX */ -#define GPDMA1_REQUEST_SAI1_A (36U) /*!< GPDMA1 HW request is SAI1_A */ -#define GPDMA1_REQUEST_SAI1_B (37U) /*!< GPDMA1 HW request is SAI1_B */ +#define GPDMA1_REQUEST_USART3_RX 28U /*!< GPDMA1 HW request is USART3_RX */ +#define GPDMA1_REQUEST_USART3_TX 29U /*!< GPDMA1 HW request is USART3_TX */ +#define GPDMA1_REQUEST_UART4_RX 30U /*!< GPDMA1 HW request is UART4_RX */ +#define GPDMA1_REQUEST_UART4_TX 31U /*!< GPDMA1 HW request is UART4_TX */ +#define GPDMA1_REQUEST_UART5_RX 32U /*!< GPDMA1 HW request is UART5_RX */ +#define GPDMA1_REQUEST_UART5_TX 33U /*!< GPDMA1 HW request is UART5_TX */ +#define GPDMA1_REQUEST_LPUART1_RX 34U /*!< GPDMA1 HW request is LPUART1_RX */ +#define GPDMA1_REQUEST_LPUART1_TX 35U /*!< GPDMA1 HW request is LPUART1_TX */ +#define GPDMA1_REQUEST_SAI1_A 36U /*!< GPDMA1 HW request is SAI1_A */ +#define GPDMA1_REQUEST_SAI1_B 37U /*!< GPDMA1 HW request is SAI1_B */ #if defined(SAI2) -#define GPDMA1_REQUEST_SAI2_A (38U) /*!< GPDMA1 HW request is SAI2_A */ -#define GPDMA1_REQUEST_SAI2_B (39U) /*!< GPDMA1 HW request is SAI2_B */ +#define GPDMA1_REQUEST_SAI2_A 38U /*!< GPDMA1 HW request is SAI2_A */ +#define GPDMA1_REQUEST_SAI2_B 39U /*!< GPDMA1 HW request is SAI2_B */ #endif /* SAI2 */ -#define GPDMA1_REQUEST_OCTOSPI1 (40U) /*!< GPDMA1 HW request is OCTOSPI1 */ +#define GPDMA1_REQUEST_OCTOSPI1 40U /*!< GPDMA1 HW request is OCTOSPI1 */ #if defined(OCTOSPI2) -#define GPDMA1_REQUEST_OCTOSPI2 (41U) /*!< GPDMA1 HW request is OCTOSPI2 */ +#define GPDMA1_REQUEST_OCTOSPI2 41U /*!< GPDMA1 HW request is OCTOSPI2 */ #endif /* OCTOSPI2 */ -#define GPDMA1_REQUEST_TIM1_CH1 (42U) /*!< GPDMA1 HW request is TIM1_CH1 */ -#define GPDMA1_REQUEST_TIM1_CH2 (43U) /*!< GPDMA1 HW request is TIM1_CH2 */ -#define GPDMA1_REQUEST_TIM1_CH3 (44U) /*!< GPDMA1 HW request is TIM1_CH3 */ -#define GPDMA1_REQUEST_TIM1_CH4 (45U) /*!< GPDMA1 HW request is TIM1_CH4 */ -#define GPDMA1_REQUEST_TIM1_UP (46U) /*!< GPDMA1 HW request is TIM1_UP */ -#define GPDMA1_REQUEST_TIM1_TRIG (47U) /*!< GPDMA1 HW request is TIM1_TRIG */ -#define GPDMA1_REQUEST_TIM1_COM (48U) /*!< GPDMA1 HW request is TIM1_COM */ -#define GPDMA1_REQUEST_TIM8_CH1 (49U) /*!< GPDMA1 HW request is TIM8_CH1 */ -#define GPDMA1_REQUEST_TIM8_CH2 (50U) /*!< GPDMA1 HW request is TIM8_CH2 */ -#define GPDMA1_REQUEST_TIM8_CH3 (51U) /*!< GPDMA1 HW request is TIM8_CH3 */ -#define GPDMA1_REQUEST_TIM8_CH4 (52U) /*!< GPDMA1 HW request is TIM8_CH4 */ -#define GPDMA1_REQUEST_TIM8_UP (53U) /*!< GPDMA1 HW request is TIM8_UP */ -#define GPDMA1_REQUEST_TIM8_TRIG (54U) /*!< GPDMA1 HW request is TIM8_TRIG */ -#define GPDMA1_REQUEST_TIM8_COM (55U) /*!< GPDMA1 HW request is TIM8_COM */ -#define GPDMA1_REQUEST_TIM2_CH1 (56U) /*!< GPDMA1 HW request is TIM2_CH1 */ -#define GPDMA1_REQUEST_TIM2_CH2 (57U) /*!< GPDMA1 HW request is TIM2_CH2 */ -#define GPDMA1_REQUEST_TIM2_CH3 (58U) /*!< GPDMA1 HW request is TIM2_CH3 */ -#define GPDMA1_REQUEST_TIM2_CH4 (59U) /*!< GPDMA1 HW request is TIM2_CH4 */ -#define GPDMA1_REQUEST_TIM2_UP (60U) /*!< GPDMA1 HW request is TIM2_UP */ -#define GPDMA1_REQUEST_TIM3_CH1 (61U) /*!< GPDMA1 HW request is TIM3_CH1 */ -#define GPDMA1_REQUEST_TIM3_CH2 (62U) /*!< GPDMA1 HW request is TIM3_CH2 */ -#define GPDMA1_REQUEST_TIM3_CH3 (63U) /*!< GPDMA1 HW request is TIM3_CH3 */ -#define GPDMA1_REQUEST_TIM3_CH4 (64U) /*!< GPDMA1 HW request is TIM3_CH4 */ -#define GPDMA1_REQUEST_TIM3_UP (65U) /*!< GPDMA1 HW request is TIM3_UP */ -#define GPDMA1_REQUEST_TIM3_TRIG (66U) /*!< GPDMA1 HW request is TIM3_TRIG */ -#define GPDMA1_REQUEST_TIM4_CH1 (67U) /*!< GPDMA1 HW request is TIM4_CH1 */ -#define GPDMA1_REQUEST_TIM4_CH2 (68U) /*!< GPDMA1 HW request is TIM4_CH2 */ -#define GPDMA1_REQUEST_TIM4_CH3 (69U) /*!< GPDMA1 HW request is TIM4_CH3 */ -#define GPDMA1_REQUEST_TIM4_CH4 (70U) /*!< GPDMA1 HW request is TIM4_CH4 */ -#define GPDMA1_REQUEST_TIM4_UP (71U) /*!< GPDMA1 HW request is TIM4_UP */ -#define GPDMA1_REQUEST_TIM5_CH1 (72U) /*!< GPDMA1 HW request is TIM5_CH1 */ -#define GPDMA1_REQUEST_TIM5_CH2 (73U) /*!< GPDMA1 HW request is TIM5_CH2 */ -#define GPDMA1_REQUEST_TIM5_CH3 (74U) /*!< GPDMA1 HW request is TIM5_CH3 */ -#define GPDMA1_REQUEST_TIM5_CH4 (75U) /*!< GPDMA1 HW request is TIM5_CH4 */ -#define GPDMA1_REQUEST_TIM5_UP (76U) /*!< GPDMA1 HW request is TIM5_UP */ -#define GPDMA1_REQUEST_TIM5_TRIG (77U) /*!< GPDMA1 HW request is TIM5_TRIG */ -#define GPDMA1_REQUEST_TIM15_CH1 (78U) /*!< GPDMA1 HW request is TIM15_CH1 */ -#define GPDMA1_REQUEST_TIM15_UP (79U) /*!< GPDMA1 HW request is TIM15_UP */ -#define GPDMA1_REQUEST_TIM15_TRIG (80U) /*!< GPDMA1 HW request is TIM15_TRIG */ -#define GPDMA1_REQUEST_TIM15_COM (81U) /*!< GPDMA1 HW request is TIM15_COM */ -#define GPDMA1_REQUEST_TIM16_CH1 (82U) /*!< GPDMA1 HW request is TIM16_CH1 */ -#define GPDMA1_REQUEST_TIM16_UP (83U) /*!< GPDMA1 HW request is TIM16_UP */ -#define GPDMA1_REQUEST_TIM17_CH1 (84U) /*!< GPDMA1 HW request is TIM17_CH1 */ -#define GPDMA1_REQUEST_TIM17_UP (85U) /*!< GPDMA1 HW request is TIM17_UP */ -#define GPDMA1_REQUEST_DCMI_PSSI (86U) /*!< GPDMA1 HW request is DCMI_PSSI */ -#define GPDMA1_REQUEST_AES_IN (87U) /*!< GPDMA1 HW request is AES_IN */ -#define GPDMA1_REQUEST_AES_OUT (88U) /*!< GPDMA1 HW request is AES_OUT */ -#define GPDMA1_REQUEST_HASH_IN (89U) /*!< GPDMA1 HW request is HASH_IN */ +#define GPDMA1_REQUEST_TIM1_CH1 42U /*!< GPDMA1 HW request is TIM1_CH1 */ +#define GPDMA1_REQUEST_TIM1_CH2 43U /*!< GPDMA1 HW request is TIM1_CH2 */ +#define GPDMA1_REQUEST_TIM1_CH3 44U /*!< GPDMA1 HW request is TIM1_CH3 */ +#define GPDMA1_REQUEST_TIM1_CH4 45U /*!< GPDMA1 HW request is TIM1_CH4 */ +#define GPDMA1_REQUEST_TIM1_UP 46U /*!< GPDMA1 HW request is TIM1_UP */ +#define GPDMA1_REQUEST_TIM1_TRIG 47U /*!< GPDMA1 HW request is TIM1_TRIG */ +#define GPDMA1_REQUEST_TIM1_COM 48U /*!< GPDMA1 HW request is TIM1_COM */ +#define GPDMA1_REQUEST_TIM8_CH1 49U /*!< GPDMA1 HW request is TIM8_CH1 */ +#define GPDMA1_REQUEST_TIM8_CH2 50U /*!< GPDMA1 HW request is TIM8_CH2 */ +#define GPDMA1_REQUEST_TIM8_CH3 51U /*!< GPDMA1 HW request is TIM8_CH3 */ +#define GPDMA1_REQUEST_TIM8_CH4 52U /*!< GPDMA1 HW request is TIM8_CH4 */ +#define GPDMA1_REQUEST_TIM8_UP 53U /*!< GPDMA1 HW request is TIM8_UP */ +#define GPDMA1_REQUEST_TIM8_TRIG 54U /*!< GPDMA1 HW request is TIM8_TRIG */ +#define GPDMA1_REQUEST_TIM8_COM 55U /*!< GPDMA1 HW request is TIM8_COM */ +#define GPDMA1_REQUEST_TIM2_CH1 56U /*!< GPDMA1 HW request is TIM2_CH1 */ +#define GPDMA1_REQUEST_TIM2_CH2 57U /*!< GPDMA1 HW request is TIM2_CH2 */ +#define GPDMA1_REQUEST_TIM2_CH3 58U /*!< GPDMA1 HW request is TIM2_CH3 */ +#define GPDMA1_REQUEST_TIM2_CH4 59U /*!< GPDMA1 HW request is TIM2_CH4 */ +#define GPDMA1_REQUEST_TIM2_UP 60U /*!< GPDMA1 HW request is TIM2_UP */ +#define GPDMA1_REQUEST_TIM3_CH1 61U /*!< GPDMA1 HW request is TIM3_CH1 */ +#define GPDMA1_REQUEST_TIM3_CH2 62U /*!< GPDMA1 HW request is TIM3_CH2 */ +#define GPDMA1_REQUEST_TIM3_CH3 63U /*!< GPDMA1 HW request is TIM3_CH3 */ +#define GPDMA1_REQUEST_TIM3_CH4 64U /*!< GPDMA1 HW request is TIM3_CH4 */ +#define GPDMA1_REQUEST_TIM3_UP 65U /*!< GPDMA1 HW request is TIM3_UP */ +#define GPDMA1_REQUEST_TIM3_TRIG 66U /*!< GPDMA1 HW request is TIM3_TRIG */ +#define GPDMA1_REQUEST_TIM4_CH1 67U /*!< GPDMA1 HW request is TIM4_CH1 */ +#define GPDMA1_REQUEST_TIM4_CH2 68U /*!< GPDMA1 HW request is TIM4_CH2 */ +#define GPDMA1_REQUEST_TIM4_CH3 69U /*!< GPDMA1 HW request is TIM4_CH3 */ +#define GPDMA1_REQUEST_TIM4_CH4 70U /*!< GPDMA1 HW request is TIM4_CH4 */ +#define GPDMA1_REQUEST_TIM4_UP 71U /*!< GPDMA1 HW request is TIM4_UP */ +#define GPDMA1_REQUEST_TIM5_CH1 72U /*!< GPDMA1 HW request is TIM5_CH1 */ +#define GPDMA1_REQUEST_TIM5_CH2 73U /*!< GPDMA1 HW request is TIM5_CH2 */ +#define GPDMA1_REQUEST_TIM5_CH3 74U /*!< GPDMA1 HW request is TIM5_CH3 */ +#define GPDMA1_REQUEST_TIM5_CH4 75U /*!< GPDMA1 HW request is TIM5_CH4 */ +#define GPDMA1_REQUEST_TIM5_UP 76U /*!< GPDMA1 HW request is TIM5_UP */ +#define GPDMA1_REQUEST_TIM5_TRIG 77U /*!< GPDMA1 HW request is TIM5_TRIG */ +#define GPDMA1_REQUEST_TIM15_CH1 78U /*!< GPDMA1 HW request is TIM15_CH1 */ +#define GPDMA1_REQUEST_TIM15_UP 79U /*!< GPDMA1 HW request is TIM15_UP */ +#define GPDMA1_REQUEST_TIM15_TRIG 80U /*!< GPDMA1 HW request is TIM15_TRIG */ +#define GPDMA1_REQUEST_TIM15_COM 81U /*!< GPDMA1 HW request is TIM15_COM */ +#define GPDMA1_REQUEST_TIM16_CH1 82U /*!< GPDMA1 HW request is TIM16_CH1 */ +#define GPDMA1_REQUEST_TIM16_UP 83U /*!< GPDMA1 HW request is TIM16_UP */ +#define GPDMA1_REQUEST_TIM17_CH1 84U /*!< GPDMA1 HW request is TIM17_CH1 */ +#define GPDMA1_REQUEST_TIM17_UP 85U /*!< GPDMA1 HW request is TIM17_UP */ +#define GPDMA1_REQUEST_DCMI_PSSI 86U /*!< GPDMA1 HW request is DCMI_PSSI */ +#define GPDMA1_REQUEST_AES_IN 87U /*!< GPDMA1 HW request is AES_IN */ +#define GPDMA1_REQUEST_AES_OUT 88U /*!< GPDMA1 HW request is AES_OUT */ +#define GPDMA1_REQUEST_HASH_IN 89U /*!< GPDMA1 HW request is HASH_IN */ #if defined(UCPD1) -#define GPDMA1_REQUEST_UCPD1_TX (90U) /*!< GPDMA1 HW request is UCPD1_TX */ -#define GPDMA1_REQUEST_UCPD1_RX (91U) /*!< GPDMA1 HW request is UCPD1_RX */ +#define GPDMA1_REQUEST_UCPD1_TX 90U /*!< GPDMA1 HW request is UCPD1_TX */ +#define GPDMA1_REQUEST_UCPD1_RX 91U /*!< GPDMA1 HW request is UCPD1_RX */ #endif /* UCPD1 */ -#define GPDMA1_REQUEST_MDF1_FLT0 (92U) /*!< GPDMA1 HW request is MDF1_FLT0 */ -#define GPDMA1_REQUEST_MDF1_FLT1 (93U) /*!< GPDMA1 HW request is MDF1_FLT1 */ -#define GPDMA1_REQUEST_MDF1_FLT2 (94U) /*!< GPDMA1 HW request is MDF1_FLT2 */ -#define GPDMA1_REQUEST_MDF1_FLT3 (95U) /*!< GPDMA1 HW request is MDF1_FLT3 */ -#define GPDMA1_REQUEST_MDF1_FLT4 (96U) /*!< GPDMA1 HW request is MDF1_FLT4 */ -#define GPDMA1_REQUEST_MDF1_FLT5 (97U) /*!< GPDMA1 HW request is MDF1_FLT5 */ -#define GPDMA1_REQUEST_ADF1_FLT0 (98U) /*!< GPDMA1 HW request is ADF1_FLT0 */ -#define GPDMA1_REQUEST_FMAC_READ (99U) /*!< GPDMA1 HW request is FMAC_READ */ -#define GPDMA1_REQUEST_FMAC_WRITE (100U) /*!< GPDMA1 HW request is FMAC_WRITE */ -#define GPDMA1_REQUEST_CORDIC_READ (101U) /*!< GPDMA1 HW request is CORDIC_READ */ -#define GPDMA1_REQUEST_CORDIC_WRITE (102U) /*!< GPDMA1 HW request is CORDIC_WRITE */ -#define GPDMA1_REQUEST_SAES_IN (103U) /*!< GPDMA1 HW request is SAES_IN */ -#define GPDMA1_REQUEST_SAES_OUT (104U) /*!< GPDMA1 HW request is SAES_OUT */ -#define GPDMA1_REQUEST_LPTIM1_IC1 (105U) /*!< GPDMA1 HW request is LPTIM1_IC1 */ -#define GPDMA1_REQUEST_LPTIM1_IC2 (106U) /*!< GPDMA1 HW request is LPTIM1_IC2 */ -#define GPDMA1_REQUEST_LPTIM1_UE (107U) /*!< GPDMA1 HW request is LPTIM1_UE */ -#define GPDMA1_REQUEST_LPTIM2_IC1 (108U) /*!< GPDMA1 HW request is LPTIM2_IC1 */ -#define GPDMA1_REQUEST_LPTIM2_IC2 (109U) /*!< GPDMA1 HW request is LPTIM2_IC2 */ -#define GPDMA1_REQUEST_LPTIM2_UE (110U) /*!< GPDMA1 HW request is LPTIM2_UE */ -#define GPDMA1_REQUEST_LPTIM3_IC1 (111U) /*!< GPDMA1 HW request is LPTIM3_IC1 */ -#define GPDMA1_REQUEST_LPTIM3_IC2 (112U) /*!< GPDMA1 HW request is LPTIM3_IC2 */ -#define GPDMA1_REQUEST_LPTIM3_UE (113U) /*!< GPDMA1 HW request is LPTIM3_UE */ +#define GPDMA1_REQUEST_MDF1_FLT0 92U /*!< GPDMA1 HW request is MDF1_FLT0 */ +#define GPDMA1_REQUEST_MDF1_FLT1 93U /*!< GPDMA1 HW request is MDF1_FLT1 */ +#define GPDMA1_REQUEST_MDF1_FLT2 94U /*!< GPDMA1 HW request is MDF1_FLT2 */ +#define GPDMA1_REQUEST_MDF1_FLT3 95U /*!< GPDMA1 HW request is MDF1_FLT3 */ +#define GPDMA1_REQUEST_MDF1_FLT4 96U /*!< GPDMA1 HW request is MDF1_FLT4 */ +#define GPDMA1_REQUEST_MDF1_FLT5 97U /*!< GPDMA1 HW request is MDF1_FLT5 */ +#define GPDMA1_REQUEST_ADF1_FLT0 98U /*!< GPDMA1 HW request is ADF1_FLT0 */ +#define GPDMA1_REQUEST_FMAC_READ 99U /*!< GPDMA1 HW request is FMAC_READ */ +#define GPDMA1_REQUEST_FMAC_WRITE 100U /*!< GPDMA1 HW request is FMAC_WRITE */ +#define GPDMA1_REQUEST_CORDIC_READ 101U /*!< GPDMA1 HW request is CORDIC_READ */ +#define GPDMA1_REQUEST_CORDIC_WRITE 102U /*!< GPDMA1 HW request is CORDIC_WRITE */ +#define GPDMA1_REQUEST_SAES_IN 103U /*!< GPDMA1 HW request is SAES_IN */ +#define GPDMA1_REQUEST_SAES_OUT 104U /*!< GPDMA1 HW request is SAES_OUT */ +#define GPDMA1_REQUEST_LPTIM1_IC1 105U /*!< GPDMA1 HW request is LPTIM1_IC1 */ +#define GPDMA1_REQUEST_LPTIM1_IC2 106U /*!< GPDMA1 HW request is LPTIM1_IC2 */ +#define GPDMA1_REQUEST_LPTIM1_UE 107U /*!< GPDMA1 HW request is LPTIM1_UE */ +#define GPDMA1_REQUEST_LPTIM2_IC1 108U /*!< GPDMA1 HW request is LPTIM2_IC1 */ +#define GPDMA1_REQUEST_LPTIM2_IC2 109U /*!< GPDMA1 HW request is LPTIM2_IC2 */ +#define GPDMA1_REQUEST_LPTIM2_UE 110U /*!< GPDMA1 HW request is LPTIM2_UE */ +#define GPDMA1_REQUEST_LPTIM3_IC1 111U /*!< GPDMA1 HW request is LPTIM3_IC1 */ +#define GPDMA1_REQUEST_LPTIM3_IC2 112U /*!< GPDMA1 HW request is LPTIM3_IC2 */ +#define GPDMA1_REQUEST_LPTIM3_UE 113U /*!< GPDMA1 HW request is LPTIM3_UE */ #if defined (HSPI1_BASE) -#define GPDMA1_REQUEST_HSPI1 (114U) /*!< GPDMA1 HW request is HSPI1 */ -#endif /* defined (HSPI1_BASE) */ +#define GPDMA1_REQUEST_HSPI1 114U /*!< GPDMA1 HW request is HSPI1 */ +#endif /* HSPI1_BASE */ #if defined (I2C5) -#define GPDMA1_REQUEST_I2C5_RX (115U) /*!< GPDMA1 HW request is I2C5_RX */ -#define GPDMA1_REQUEST_I2C5_TX (116U) /*!< GPDMA1 HW request is I2C5_TX */ -#define GPDMA1_REQUEST_I2C5_EVC (117U) /*!< GPDMA1 HW request is I2C5_EVC */ -#endif /* defined (I2C5) */ +#define GPDMA1_REQUEST_I2C5_RX 115U /*!< GPDMA1 HW request is I2C5_RX */ +#define GPDMA1_REQUEST_I2C5_TX 116U /*!< GPDMA1 HW request is I2C5_TX */ +#define GPDMA1_REQUEST_I2C5_EVC 117U /*!< GPDMA1 HW request is I2C5_EVC */ +#endif /* I2C5 */ #if defined (I2C6) -#define GPDMA1_REQUEST_I2C6_RX (118U) /*!< GPDMA1 HW request is I2C6_RX */ -#define GPDMA1_REQUEST_I2C6_TX (119U) /*!< GPDMA1 HW request is I2C6_TX */ -#define GPDMA1_REQUEST_I2C6_EVC (120U) /*!< GPDMA1 HW request is I2C6_EVC */ -#endif /* defined (I2C6) */ +#define GPDMA1_REQUEST_I2C6_RX 118U /*!< GPDMA1 HW request is I2C6_RX */ +#define GPDMA1_REQUEST_I2C6_TX 119U /*!< GPDMA1 HW request is I2C6_TX */ +#define GPDMA1_REQUEST_I2C6_EVC 120U /*!< GPDMA1 HW request is I2C6_EVC */ +#endif /* I2C6 */ #if defined (USART6) -#define GPDMA1_REQUEST_USART6_RX (121U) /*!< GPDMA1 HW request is USART6_RX */ -#define GPDMA1_REQUEST_USART6_TX (122U) /*!< GPDMA1 HW request is USART6_TX */ -#endif /* defined (USART6) */ +#define GPDMA1_REQUEST_USART6_RX 121U /*!< GPDMA1 HW request is USART6_RX */ +#define GPDMA1_REQUEST_USART6_TX 122U /*!< GPDMA1 HW request is USART6_TX */ +#endif /* USART6 */ #if defined (ADC2) -#define GPDMA1_REQUEST_ADC2 (123U) /*!< GPDMA1 HW request is ADC2 */ -#endif /* defined (ADC2) */ +#define GPDMA1_REQUEST_ADC2 123U /*!< GPDMA1 HW request is ADC2 */ +#endif /* ADC2 */ #if defined (JPEG) -#define GPDMA1_REQUEST_JPEG_RX (124U) /*!< GPDMA1 HW request is JPEG_TX */ -#define GPDMA1_REQUEST_JPEG_TX (125U) /*!< GPDMA1 HW request is JPEG_RX */ -#endif /* defined (JPEG) */ +#define GPDMA1_REQUEST_JPEG_RX 124U /*!< GPDMA1 HW request is JPEG_TX */ +#define GPDMA1_REQUEST_JPEG_TX 125U /*!< GPDMA1 HW request is JPEG_RX */ +#endif /* JPEG */ /* LPDMA1 requests */ -#define LPDMA1_REQUEST_LPUART1_RX (0U) /*!< LPDMA1 HW request is LPUART1_RX */ -#define LPDMA1_REQUEST_LPUART1_TX (1U) /*!< LPDMA1 HW request is LPUART1_TX */ -#define LPDMA1_REQUEST_SPI3_RX (2U) /*!< LPDMA1 HW request is SPI3_RX */ -#define LPDMA1_REQUEST_SPI3_TX (3U) /*!< LPDMA1 HW request is SPI3_TX */ -#define LPDMA1_REQUEST_I2C3_RX (4U) /*!< LPDMA1 HW request is I2C3_RX */ -#define LPDMA1_REQUEST_I2C3_TX (5U) /*!< LPDMA1 HW request is I2C3_TX */ -#define LPDMA1_REQUEST_I2C3_EVC (6U) /*!< LPDMA1 HW request is I2C3_EVC */ -#define LPDMA1_REQUEST_ADC4 (7U) /*!< LPDMA1 HW request is ADC4 */ -#define LPDMA1_REQUEST_DAC1_CH1 (8U) /*!< LPDMA1 HW request is DAC1_CH1 */ -#define LPDMA1_REQUEST_DAC1_CH2 (9U) /*!< LPDMA1 HW request is DAC1_CH2 */ -#define LPDMA1_REQUEST_ADF1_FLT0 (10U) /*!< LPDMA1 HW request is ADF1_FLT0 */ -#define LPDMA1_REQUEST_LPTIM1_IC1 (11U) /*!< LPDMA1 HW request is LPTIM1_IC1 */ -#define LPDMA1_REQUEST_LPTIM1_IC2 (12U) /*!< LPDMA1 HW request is LPTIM1_IC2 */ -#define LPDMA1_REQUEST_LPTIM1_UE (13U) /*!< LPDMA1 HW request is LPTIM1_UE */ -#define LPDMA1_REQUEST_LPTIM3_IC1 (14U) /*!< LPDMA1 HW request is LPTIM3_IC1 */ -#define LPDMA1_REQUEST_LPTIM3_IC2 (15U) /*!< LPDMA1 HW request is LPTIM3_IC2 */ -#define LPDMA1_REQUEST_LPTIM3_UE (16U) /*!< LPDMA1 HW request is LPTIM3_UE */ +#define LPDMA1_REQUEST_LPUART1_RX 0U /*!< LPDMA1 HW request is LPUART1_RX */ +#define LPDMA1_REQUEST_LPUART1_TX 1U /*!< LPDMA1 HW request is LPUART1_TX */ +#define LPDMA1_REQUEST_SPI3_RX 2U /*!< LPDMA1 HW request is SPI3_RX */ +#define LPDMA1_REQUEST_SPI3_TX 3U /*!< LPDMA1 HW request is SPI3_TX */ +#define LPDMA1_REQUEST_I2C3_RX 4U /*!< LPDMA1 HW request is I2C3_RX */ +#define LPDMA1_REQUEST_I2C3_TX 5U /*!< LPDMA1 HW request is I2C3_TX */ +#define LPDMA1_REQUEST_I2C3_EVC 6U /*!< LPDMA1 HW request is I2C3_EVC */ +#define LPDMA1_REQUEST_ADC4 7U /*!< LPDMA1 HW request is ADC4 */ +#define LPDMA1_REQUEST_DAC1_CH1 8U /*!< LPDMA1 HW request is DAC1_CH1 */ +#define LPDMA1_REQUEST_DAC1_CH2 9U /*!< LPDMA1 HW request is DAC1_CH2 */ +#define LPDMA1_REQUEST_ADF1_FLT0 10U /*!< LPDMA1 HW request is ADF1_FLT0 */ +#define LPDMA1_REQUEST_LPTIM1_IC1 11U /*!< LPDMA1 HW request is LPTIM1_IC1 */ +#define LPDMA1_REQUEST_LPTIM1_IC2 12U /*!< LPDMA1 HW request is LPTIM1_IC2 */ +#define LPDMA1_REQUEST_LPTIM1_UE 13U /*!< LPDMA1 HW request is LPTIM1_UE */ +#define LPDMA1_REQUEST_LPTIM3_IC1 14U /*!< LPDMA1 HW request is LPTIM3_IC1 */ +#define LPDMA1_REQUEST_LPTIM3_IC2 15U /*!< LPDMA1 HW request is LPTIM3_IC2 */ +#define LPDMA1_REQUEST_LPTIM3_UE 16U /*!< LPDMA1 HW request is LPTIM3_UE */ /* Software request */ -#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ +#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ /** * @} */ @@ -770,7 +770,7 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState); @@ -890,12 +890,12 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \ (((INSTANCE)->SMISR & (GLOBAL_FLAG))) -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \ (((INSTANCE)->MISR & (GLOBAL_FLAG))) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma2d.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma2d.h index 0c527072b5..48eba8a5ab 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma2d.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma2d.h @@ -517,9 +517,9 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h index 6f6eff8c95..af230a52b5 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h @@ -150,7 +150,7 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t SrcSecure; /*!< Specifies the source security attribute */ uint32_t DestSecure; /*!< Specifies the destination security attribute */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ } DMA_NodeConfTypeDef; @@ -236,10 +236,10 @@ typedef struct __DMA_QListTypeDef destination data width */ #define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width => Packed at the destination data width - (Available only for GPDMA) */ + (Not available on LPDMA) */ #define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width => Unpacked at the destination data width - (Available only for GPDMA) */ + (Not available on LPDMA) */ /** * @} */ @@ -284,129 +284,129 @@ typedef struct __DMA_QListTypeDef * @{ */ /* GPDMA1 triggers */ -#define GPDMA1_TRIGGER_EXTI_LINE0 (0U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */ -#define GPDMA1_TRIGGER_EXTI_LINE1 (1U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */ -#define GPDMA1_TRIGGER_EXTI_LINE2 (2U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */ -#define GPDMA1_TRIGGER_EXTI_LINE3 (3U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */ -#define GPDMA1_TRIGGER_EXTI_LINE4 (4U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */ -#define GPDMA1_TRIGGER_EXTI_LINE5 (5U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */ -#define GPDMA1_TRIGGER_EXTI_LINE6 (6U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */ -#define GPDMA1_TRIGGER_EXTI_LINE7 (7U) /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */ -#define GPDMA1_TRIGGER_TAMP_TRG1 (8U) /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */ -#define GPDMA1_TRIGGER_TAMP_TRG2 (9U) /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */ -#define GPDMA1_TRIGGER_TAMP_TRG3 (10U) /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */ -#define GPDMA1_TRIGGER_LPTIM1_CH1 (11U) /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ -#define GPDMA1_TRIGGER_LPTIM1_CH2 (12U) /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ -#define GPDMA1_TRIGGER_LPTIM2_CH1 (13U) /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ -#define GPDMA1_TRIGGER_LPTIM2_CH2 (14U) /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ -#define GPDMA1_TRIGGER_LPTIM4_OUT (15U) /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */ -#define GPDMA1_TRIGGER_COMP1_OUT (16U) /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ +#define GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */ +#define GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */ +#define GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */ +#define GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */ +#define GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */ +#define GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */ +#define GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */ +#define GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */ +#define GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */ +#define GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */ +#define GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */ +#define GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ +#define GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ +#define GPDMA1_TRIGGER_LPTIM4_OUT 15U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */ +#define GPDMA1_TRIGGER_COMP1_OUT 16U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ #if defined(COMP2) -#define GPDMA1_TRIGGER_COMP2_OUT (17U) /*!< GPDMA1 HW Trigger signal is COMP2_OUT */ +#define GPDMA1_TRIGGER_COMP2_OUT 17U /*!< GPDMA1 HW Trigger signal is COMP2_OUT */ #endif /* COMP2 */ -#define GPDMA1_TRIGGER_RTC_ALRA_TRG (18U) /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */ -#define GPDMA1_TRIGGER_RTC_ALRB_TRG (19U) /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */ -#define GPDMA1_TRIGGER_RTC_WUT_TRG (20U) /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */ -#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF (22U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF (23U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF (24U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF (25U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF (26U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF (27U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF (28U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF (29U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH8_TCF (30U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH9_TCF (31U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH10_TCF (32U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH11_TCF (33U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH12_TCF (34U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH13_TCF (35U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH14_TCF (36U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH15_TCF (37U) /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ -#define GPDMA1_TRIGGER_LPDMA1_CH0_TCF (38U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ -#define GPDMA1_TRIGGER_LPDMA1_CH1_TCF (39U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ -#define GPDMA1_TRIGGER_LPDMA1_CH2_TCF (40U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ -#define GPDMA1_TRIGGER_LPDMA1_CH3_TCF (41U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ -#define GPDMA1_TRIGGER_TIM2_TRGO (42U) /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ -#define GPDMA1_TRIGGER_TIM15_TRGO (43U) /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ +#define GPDMA1_TRIGGER_RTC_ALRA_TRG 18U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */ +#define GPDMA1_TRIGGER_RTC_ALRB_TRG 19U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */ +#define GPDMA1_TRIGGER_RTC_WUT_TRG 20U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */ +#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 28U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH8_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH9_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH10_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH11_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH12_TCF 34U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH13_TCF 35U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH14_TCF 36U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH15_TCF 37U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ +#define GPDMA1_TRIGGER_LPDMA1_CH0_TCF 38U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ +#define GPDMA1_TRIGGER_LPDMA1_CH1_TCF 39U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ +#define GPDMA1_TRIGGER_LPDMA1_CH2_TCF 40U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ +#define GPDMA1_TRIGGER_LPDMA1_CH3_TCF 41U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ +#define GPDMA1_TRIGGER_TIM2_TRGO 42U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ +#define GPDMA1_TRIGGER_TIM15_TRGO 43U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ #if defined (TIM3_TRGO_TRIGGER_SUPPORT) -#define GPDMA1_TRIGGER_TIM3_TRGO (44U) /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ -#endif /* defined (TRIGGER_TIM3_TRGO_SUPPORT) */ +#define GPDMA1_TRIGGER_TIM3_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ +#endif /* TIM3_TRGO_TRIGGER_SUPPORT */ #if defined (TIM4_TRGO_TRIGGER_SUPPORT) -#define GPDMA1_TRIGGER_TIM4_TRGO (45U) /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ -#endif /* defined (TRIGGER_TIM4_TRGO_SUPPORT) */ +#define GPDMA1_TRIGGER_TIM4_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ +#endif /* TIM4_TRGO_TRIGGER_SUPPORT */ #if defined (TIM5_TRGO_TRIGGER_SUPPORT) -#define GPDMA1_TRIGGER_TIM5_TRGO (46U) /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ -#endif /* defined (TRIGGER_TIM5_TRGO_SUPPORT) */ +#define GPDMA1_TRIGGER_TIM5_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ +#endif /* TIM5_TRGO_TRIGGER_SUPPORT */ #if defined (LTDC) -#define GPDMA1_TRIGGER_LTDC_LI (47U) /*!< GPDMA1 HW Trigger signal is LTDC_LI */ -#endif /* defined (LTDC) */ +#define GPDMA1_TRIGGER_LTDC_LI 47U /*!< GPDMA1 HW Trigger signal is LTDC_LI */ +#endif /* LTDC */ #if defined (DSI) -#define GPDMA1_TRIGGER_DSI_TE (48U) /*!< GPDMA1 HW Trigger signal is DSI_TE */ -#define GPDMA1_TRIGGER_DSI_ER (49U) /*!< GPDMA1 HW Trigger signal is DSI_ER */ -#endif /* defined (DSI) */ +#define GPDMA1_TRIGGER_DSI_TE 48U /*!< GPDMA1 HW Trigger signal is DSI_TE */ +#define GPDMA1_TRIGGER_DSI_ER 49U /*!< GPDMA1 HW Trigger signal is DSI_ER */ +#endif /* DSI */ #if defined (DMA2D_TRIGGER_SUPPORT) -#define GPDMA1_TRIGGER_DMA2D_TC (50U) /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ -#define GPDMA1_TRIGGER_DMA2D_CTC (51U) /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ -#define GPDMA1_TRIGGER_DMA2D_TW (52U) /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ -#endif /* defined (DMA2D_TRIGGER_SUPPORT) */ +#define GPDMA1_TRIGGER_DMA2D_TC 50U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ +#define GPDMA1_TRIGGER_DMA2D_CTC 51U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ +#define GPDMA1_TRIGGER_DMA2D_TW 52U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ +#endif /* DMA2D_TRIGGER_SUPPORT */ #if defined (GPU2D) -#define GPDMA1_TRIGGER_GPU2D_FLAG0 (53U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */ -#define GPDMA1_TRIGGER_GPU2D_FLAG1 (54U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */ -#define GPDMA1_TRIGGER_GPU2D_FLAG2 (55U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */ -#define GPDMA1_TRIGGER_GPU2D_FLAG3 (56U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */ -#endif /* defined (GPU2D) */ -#define GPDMA1_TRIGGER_ADC4_AWD1 (57U) /*!< GPDMA1 HW Trigger signal is ADC4_AWD1 */ -#define GPDMA1_TRIGGER_ADC1_AWD1 (58U) /*!< GPDMA1 HW Trigger signal is ADC1_AWD1 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG0 53U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG1 54U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG2 55U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG3 56U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */ +#endif /* GPU2D */ +#define GPDMA1_TRIGGER_ADC4_AWD1 57U /*!< GPDMA1 HW Trigger signal is ADC4_AWD1 */ +#define GPDMA1_TRIGGER_ADC1_AWD1 58U /*!< GPDMA1 HW Trigger signal is ADC1_AWD1 */ #if defined (GFXTIM) -#define GPDMA1_TRIGGER_GFXTIM_EVT3 (59U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT3 */ -#define GPDMA1_TRIGGER_GFXTIM_EVT2 (60U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT2 */ -#define GPDMA1_TRIGGER_GFXTIM_EVT1 (61U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT1 */ -#define GPDMA1_TRIGGER_GFXTIM_EVT0 (62U) /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT0 */ -#endif /* defined (GFXTIM) */ +#define GPDMA1_TRIGGER_GFXTIM_EVT3 59U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT3 */ +#define GPDMA1_TRIGGER_GFXTIM_EVT2 60U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT2 */ +#define GPDMA1_TRIGGER_GFXTIM_EVT1 61U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT1 */ +#define GPDMA1_TRIGGER_GFXTIM_EVT0 62U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT0 */ +#endif /* GFXTIM */ #if defined (JPEG) -#define GPDMA1_TRIGGER_JPEG_EOC (63U) /*!< GPDMA1 HW Trigger signal is JPEG_EOC */ -#define GPDMA1_TRIGGER_JPEG_IFNF (64U) /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */ -#define GPDMA1_TRIGGER_JPEG_IFT (65U) /*!< GPDMA1 HW Trigger signal is JPEG_IFT */ -#define GPDMA1_TRIGGER_JPEG_OFNE (66U) /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */ -#define GPDMA1_TRIGGER_JPEG_OFT (67U) /*!< GPDMA1 HW Trigger signal is JPEG_OFT */ -#endif /* defined (JPEG) */ +#define GPDMA1_TRIGGER_JPEG_EOC 63U /*!< GPDMA1 HW Trigger signal is JPEG_EOC */ +#define GPDMA1_TRIGGER_JPEG_IFNF 64U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */ +#define GPDMA1_TRIGGER_JPEG_IFT 65U /*!< GPDMA1 HW Trigger signal is JPEG_IFT */ +#define GPDMA1_TRIGGER_JPEG_OFNE 66U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */ +#define GPDMA1_TRIGGER_JPEG_OFT 67U /*!< GPDMA1 HW Trigger signal is JPEG_OFT */ +#endif /* JPEG */ /* LPDMA1 triggers */ -#define LPDMA1_TRIGGER_EXTI_LINE0 (0U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE0 */ -#define LPDMA1_TRIGGER_EXTI_LINE1 (1U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE1 */ -#define LPDMA1_TRIGGER_EXTI_LINE2 (2U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE2 */ -#define LPDMA1_TRIGGER_EXTI_LINE3 (3U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE3 */ -#define LPDMA1_TRIGGER_EXTI_LINE4 (4U) /*!< LPDMA1 HW Trigger signal is EXTI_LINE4 */ -#define LPDMA1_TRIGGER_TAMP_TRG1 (5U) /*!< LPDMA1 HW Trigger signal is TAMP_TRG1 */ -#define LPDMA1_TRIGGER_TAMP_TRG2 (6U) /*!< LPDMA1 HW Trigger signal is TAMP_TRG2 */ -#define LPDMA1_TRIGGER_TAMP_TRG3 (7U) /*!< LPDMA1 HW Trigger signal is TAMP_TRG3 */ -#define LPDMA1_TRIGGER_LPTIM1_CH1 (8U) /*!< LPDMA1 HW Trigger signal is LPTIM1_CH1 */ -#define LPDMA1_TRIGGER_LPTIM1_CH2 (9U) /*!< LPDMA1 HW Trigger signal is LPTIM1_CH2 */ -#define LPDMA1_TRIGGER_LPTIM3_CH1 (10U) /*!< LPDMA1 HW Trigger signal is LPTIM3_CH1 */ -#define LPDMA1_TRIGGER_LPTIM4_OUT (11U) /*!< LPDMA1 HW Trigger signal is LPTIM4_OUT */ -#define LPDMA1_TRIGGER_COMP1_OUT (12U) /*!< LPDMA1 HW Trigger signal is COMP1_OUT */ +#define LPDMA1_TRIGGER_EXTI_LINE0 0U /*!< LPDMA1 HW Trigger signal is EXTI_LINE0 */ +#define LPDMA1_TRIGGER_EXTI_LINE1 1U /*!< LPDMA1 HW Trigger signal is EXTI_LINE1 */ +#define LPDMA1_TRIGGER_EXTI_LINE2 2U /*!< LPDMA1 HW Trigger signal is EXTI_LINE2 */ +#define LPDMA1_TRIGGER_EXTI_LINE3 3U /*!< LPDMA1 HW Trigger signal is EXTI_LINE3 */ +#define LPDMA1_TRIGGER_EXTI_LINE4 4U /*!< LPDMA1 HW Trigger signal is EXTI_LINE4 */ +#define LPDMA1_TRIGGER_TAMP_TRG1 5U /*!< LPDMA1 HW Trigger signal is TAMP_TRG1 */ +#define LPDMA1_TRIGGER_TAMP_TRG2 6U /*!< LPDMA1 HW Trigger signal is TAMP_TRG2 */ +#define LPDMA1_TRIGGER_TAMP_TRG3 7U /*!< LPDMA1 HW Trigger signal is TAMP_TRG3 */ +#define LPDMA1_TRIGGER_LPTIM1_CH1 8U /*!< LPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define LPDMA1_TRIGGER_LPTIM1_CH2 9U /*!< LPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define LPDMA1_TRIGGER_LPTIM3_CH1 10U /*!< LPDMA1 HW Trigger signal is LPTIM3_CH1 */ +#define LPDMA1_TRIGGER_LPTIM4_OUT 11U /*!< LPDMA1 HW Trigger signal is LPTIM4_OUT */ +#define LPDMA1_TRIGGER_COMP1_OUT 12U /*!< LPDMA1 HW Trigger signal is COMP1_OUT */ #if defined(COMP2) -#define LPDMA1_TRIGGER_COMP2_OUT (13U) /*!< LPDMA1 HW Trigger signal is COMP2_OUT */ +#define LPDMA1_TRIGGER_COMP2_OUT 13U /*!< LPDMA1 HW Trigger signal is COMP2_OUT */ #endif /* COMP2 */ -#define LPDMA1_TRIGGER_RTC_ALRA_TRG (14U) /*!< LPDMA1 HW Trigger signal is RTC_ALRA_TRG */ -#define LPDMA1_TRIGGER_RTC_ALRB_TRG (15U) /*!< LPDMA1 HW Trigger signal is RTC_ALRB_TRG */ -#define LPDMA1_TRIGGER_RTC_WUT_TRG (16U) /*!< LPDMA1 HW Trigger signal is RTC_WUT_TRG */ -#define LPDMA1_TRIGGER_ADC4_AWD1 (17U) /*!< LPDMA1 HW Trigger signal is ADC4_AWD1 */ -#define LPDMA1_TRIGGER_LPDMA1_CH0_TCF (18U) /*!< LPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ -#define LPDMA1_TRIGGER_LPDMA1_CH1_TCF (19U) /*!< LPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ -#define LPDMA1_TRIGGER_LPDMA1_CH2_TCF (20U) /*!< LPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ -#define LPDMA1_TRIGGER_LPDMA1_CH3_TCF (21U) /*!< LPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH0_TCF (22U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH1_TCF (23U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH4_TCF (24U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH5_TCF (25U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH6_TCF (26U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH7_TCF (27U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH12_TCF (28U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH13_TCF (29U) /*!< LPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ -#define LPDMA1_TRIGGER_TIM2_TRGO (30U) /*!< LPDMA1 HW Trigger signal is TIM2_TRGO */ -#define LPDMA1_TRIGGER_TIM15_TRGO (31U) /*!< LPDMA1 HW Trigger signal is TIM15_TRGO */ +#define LPDMA1_TRIGGER_RTC_ALRA_TRG 14U /*!< LPDMA1 HW Trigger signal is RTC_ALRA_TRG */ +#define LPDMA1_TRIGGER_RTC_ALRB_TRG 15U /*!< LPDMA1 HW Trigger signal is RTC_ALRB_TRG */ +#define LPDMA1_TRIGGER_RTC_WUT_TRG 16U /*!< LPDMA1 HW Trigger signal is RTC_WUT_TRG */ +#define LPDMA1_TRIGGER_ADC4_AWD1 17U /*!< LPDMA1 HW Trigger signal is ADC4_AWD1 */ +#define LPDMA1_TRIGGER_LPDMA1_CH0_TCF 18U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH1_TCF 19U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH2_TCF 20U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ +#define LPDMA1_TRIGGER_LPDMA1_CH3_TCF 21U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH12_TCF 28U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ +#define LPDMA1_TRIGGER_GPDMA1_CH13_TCF 29U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ +#define LPDMA1_TRIGGER_TIM2_TRGO 30U /*!< LPDMA1 HW Trigger signal is TIM2_TRGO */ +#define LPDMA1_TRIGGER_TIM15_TRGO 31U /*!< LPDMA1 HW Trigger signal is TIM15_TRGO */ /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gfxtim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gfxtim.h index d1d4ed45b0..8b57275e74 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gfxtim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gfxtim.h @@ -27,6 +27,8 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32u5xx_hal_def.h" +#if defined (GFXTIM) + /** @addtogroup STM32U5xx_HAL_Driver * @{ */ @@ -827,7 +829,7 @@ HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Config(GFXTIM_HandleTypeDef *hgfxtim, HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Start(GFXTIM_HandleTypeDef *hgfxtim); HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Stop(GFXTIM_HandleTypeDef *hgfxtim); HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Reset(GFXTIM_HandleTypeDef *hgfxtim); -HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_GetCounter(GFXTIM_HandleTypeDef *hgfxtim, uint32_t AbsoluteTime, +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_GetCounter(const GFXTIM_HandleTypeDef *hgfxtim, uint32_t AbsoluteTime, uint32_t *pValue); HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_SetFrameCompare(GFXTIM_HandleTypeDef *hgfxtim, uint32_t Value); HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_SetLineCompare(GFXTIM_HandleTypeDef *hgfxtim, @@ -854,7 +856,7 @@ HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Stop(GFXTIM_HandleTypeDef *hgfxtim, u HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_ForceReload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer); HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_SetReload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer, uint32_t Value); -HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_GetCounter(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer, +HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_GetCounter(const GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer, uint32_t *pValue); void HAL_GFXTIM_RelativeTimer_RFC1RCallback(GFXTIM_HandleTypeDef *hgfxtim); void HAL_GFXTIM_RelativeTimer_RFC2RCallback(GFXTIM_HandleTypeDef *hgfxtim); @@ -918,6 +920,8 @@ HAL_GFXTIM_StateTypeDef HAL_GFXTIM_GetState(const GFXTIM_HandleTypeDef *hgfxtim) * @} */ +#endif /* GFXTIM */ + #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio.h index da12432b5d..61cdc0e63a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio.h @@ -278,6 +278,23 @@ typedef enum #define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_SINGLE_PIN(__PIN__) (((__PIN__) == GPIO_PIN_0) ||\ + ((__PIN__) == GPIO_PIN_1) ||\ + ((__PIN__) == GPIO_PIN_2) ||\ + ((__PIN__) == GPIO_PIN_3) ||\ + ((__PIN__) == GPIO_PIN_4) ||\ + ((__PIN__) == GPIO_PIN_5) ||\ + ((__PIN__) == GPIO_PIN_6) ||\ + ((__PIN__) == GPIO_PIN_7) ||\ + ((__PIN__) == GPIO_PIN_8) ||\ + ((__PIN__) == GPIO_PIN_9) ||\ + ((__PIN__) == GPIO_PIN_10) ||\ + ((__PIN__) == GPIO_PIN_11) ||\ + ((__PIN__) == GPIO_PIN_12) ||\ + ((__PIN__) == GPIO_PIN_13) ||\ + ((__PIN__) == GPIO_PIN_14) ||\ + ((__PIN__) == GPIO_PIN_15)) + #define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h index cb2749f839..aea5c97da7 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h @@ -386,12 +386,15 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); /** @defgroup HCD_ENDP_Kind HCD Endpoint Kind * @{ */ -#define HCD_SNG_BUF 0U -#define HCD_DBL_BUF 1U +#define HCD_SNG_BUF 0U +#define HCD_DBL_BUF 1U /** * @} */ +/* Powerdown exit count */ +#define HCD_PDWN_EXIT_CNT 0x100U + /* Set Channel */ #define HCD_SET_CHANNEL USB_DRD_SET_CHEP @@ -522,13 +525,14 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); __STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(HCD_TypeDef *Instance, uint16_t bChNum) { uint32_t HostCoreSpeed; + uint32_t ep_reg = USB_DRD_GET_CHEP(Instance, bChNum); __IO uint32_t count = 10U; /* Get Host core Speed */ HostCoreSpeed = USB_GetHostSpeed(Instance); /* Count depends on device LS */ - if (HostCoreSpeed == USB_DRD_SPEED_LS) + if ((HostCoreSpeed == USB_DRD_SPEED_LS) || ((ep_reg & USB_CHEP_LSEP) == USB_CHEP_LSEP)) { count = (70U * (HAL_RCC_GetHCLKFreq() / 1000000U)) / 100U; } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c.h index c86834b6da..d37fb0e2aa 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c.h @@ -118,8 +118,6 @@ typedef enum HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception process is ongoing */ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ } HAL_I2C_StateTypeDef; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h index 53d0d08033..1f124b5a7d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h @@ -27,6 +27,7 @@ extern "C" { /* Includes -----------------------------------------------------------------*/ #include "stm32u5xx_hal_def.h" +#if defined(ICACHE) /** @addtogroup STM32U5xx_HAL_Driver * @{ */ @@ -284,6 +285,7 @@ HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region); /** * @} */ +#endif /* ICACHE */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_iwdg.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_iwdg.h index 2f67918fa5..1b81856542 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_iwdg.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_iwdg.h @@ -154,7 +154,7 @@ typedef void (*pIWDG_CallbackTypeDef)(IWDG_HandleTypeDef *hppp); /*!< pointer t /** * @brief Reload IWDG counter with value defined in the reload register - * (write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers disabled). + * (write access to IWDG_PR, IWDG_RLR, IWDG_WINR, IWDG_EWCR registers disabled). * @param __HANDLE__ IWDG handle * @retval None */ @@ -223,14 +223,14 @@ void HAL_IWDG_EarlyWakeupCallback(IWDG_HandleTypeDef *hiwdg); */ /** - * @brief Enable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers. + * @brief Enable write access to IWDG_PR, IWDG_RLR, IWDG_WINR, IWDG_EWCR registers. * @param __HANDLE__ IWDG handle * @retval None */ #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) /** - * @brief Disable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers. + * @brief Disable write access to IWDG_PR, IWDG_RLR, IWDG_WINR, IWDG_EWCR registers. * @param __HANDLE__ IWDG handle * @retval None */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_jpeg.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_jpeg.h index 5d176ca285..57b257e620 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_jpeg.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_jpeg.h @@ -482,7 +482,7 @@ HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg * @{ */ /* Encoding/Decoding Configuration functions ********************************/ -HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf); +HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, const JPEG_ConfTypeDef *pConf); HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo); HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg); HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h index d663aa9420..0a6423dde0 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h @@ -396,7 +396,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ #define LPTIM_INPUT2SOURCE_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */ +#if defined(COMP2) #define LPTIM_INPUT2SOURCE_COMP2 LPTIM_CFGR2_IN2SEL_0 /*!< For LPTIM1 and LPTIM2 */ +#endif /* COMP2 */ /** * @} */ @@ -519,7 +521,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ #define LPTIM_IC1SOURCE_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2 and LPTIM3 */ #define LPTIM_IC1SOURCE_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< For LPTIM1, LPTIM2 and LPTIM3 */ +#if defined(COMP2) #define LPTIM_IC1SOURCE_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< For LPTIM1, LPTIM2 and LPTIM3 */ +#endif /* COMP2 */ #define LPTIM_IC2SOURCE_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2 and LPTIM3 */ #define LPTIM_IC2SOURCE_LSI LPTIM_CFGR2_IC2SEL_0 /*!< For LPTIM1 */ #define LPTIM_IC2SOURCE_LSE LPTIM_CFGR2_IC2SEL_1 /*!< For LPTIM1 */ @@ -1073,9 +1077,6 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\ - ((__AUTORELOAD__) <= 0x0000FFFFUL)) - #define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) #define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ @@ -1109,12 +1110,20 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) +#if defined(COMP2) #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ ((((__INSTANCE__) == LPTIM1) || \ ((__INSTANCE__) == LPTIM2)) && \ (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2))) +#else +#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) || \ + ((__INSTANCE__) == LPTIM2)) && \ + (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO))) +#endif /* COMP2 */ +#if defined(COMP2) #define IS_LPTIM_IC1_SOURCE(__INSTANCE__, __SOURCE__) \ ((((__INSTANCE__) == LPTIM1) || \ ((__INSTANCE__) == LPTIM2)|| \ @@ -1122,6 +1131,14 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); (((__SOURCE__) == LPTIM_IC1SOURCE_GPIO) || \ ((__SOURCE__) == LPTIM_IC1SOURCE_COMP1) || \ ((__SOURCE__) == LPTIM_IC1SOURCE_COMP2))) +#else +#define IS_LPTIM_IC1_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) || \ + ((__INSTANCE__) == LPTIM2)|| \ + ((__INSTANCE__) == LPTIM3)) && \ + (((__SOURCE__) == LPTIM_IC1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_IC1SOURCE_COMP1))) +#endif /* COMP2 */ #define IS_LPTIM_IC2_SOURCE(__INSTANCE__, __SOURCE__) \ ((((__INSTANCE__) == LPTIM1) && \ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ltdc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ltdc.h index febd6829ad..ed247691f7 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ltdc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ltdc.h @@ -592,7 +592,8 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, u HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize, + uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); @@ -625,8 +626,8 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 * @{ */ /* Peripheral State functions *************************************************/ -HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc); -uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc); +uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc); /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc.h index d23b0bd489..892676b7a0 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc.h @@ -122,7 +122,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< MMC locking object */ - const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ uint32_t TxXferSize; /*!< MMC Tx Transfer size */ @@ -136,6 +136,8 @@ typedef struct __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ + __IO uint16_t RPMBErrorCode; /*!< MMC RPMB Area Error codes */ + HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ uint32_t CSD[4U]; /*!< MMC card specific data table */ @@ -273,45 +275,55 @@ typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc); /** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition * @{ */ -#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ -#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ -#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ -#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ -#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ -#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ -#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ -#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ -#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ +#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ /*!< number of transferred bytes does not match the block length */ -#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ -#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ -#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ -#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ +#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ /*!< command or if there was an attempt to access a locked card */ -#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ -#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ -#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ -#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ -#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ -#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ -#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ -#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ -#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ -#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ -#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ +#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ /*!< of erase sequence command was received */ -#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ -#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ -#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ -#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ -#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ -#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ -#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ -#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ -#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +/*!< response results after operating with RPMB partition */ +#define HAL_MMC_ERROR_RPMB_OPERATION_OK 0x0000U /*!< Operation OK */ +#define HAL_MMC_ERROR_RPMB_GENERAL_FAILURE 0x0001U /*!< General failure */ +#define HAL_MMC_ERROR_RPMB_AUTHENTICATION_FAILURE 0x0002U /*!< Authentication failure */ +#define HAL_MMC_ERROR_RPMB_COUNTER_FAILURE 0x0003U /*!< Counter failure */ +#define HAL_MMC_ERROR_RPMB_ADDRESS_FAILURE 0x0004U /*!< Address failure */ +#define HAL_MMC_ERROR_RPMB_WRITE_FAILURE 0x0005U /*!< Write failure */ +#define HAL_MMC_ERROR_RPMB_READ_FAILURE 0x0006U /*!< Read failure */ +#define HAL_MMC_ERROR_RPMB_KEY_NOT_YET_PROG 0x0007U /*!< Authentication Key not yet programmed */ +#define HAL_MMC_ERROR_RPMB_COUNTER_EXPIRED 0x0080U /*!< Write Counter has expired i.e. reached its max value */ #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) -#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ #endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ /** * @} @@ -396,6 +408,19 @@ typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc); * @} */ +/** @defgroup MMC_Exported_Constansts_Group7 MMC Partitions types + * @{ + */ +typedef uint32_t HAL_MMC_PartitionTypeDef; + +#define HAL_MMC_USER_AREA_PARTITION 0x00000000U /*!< User area partition */ +#define HAL_MMC_BOOT_PARTITION1 0x00000100U /*!< Boot partition 1 */ +#define HAL_MMC_BOOT_PARTITION2 0x00000200U /*!< Boot partition 2 */ +#define HAL_MMC_RPMB_PARTITION 0x00000300U /*!< RPMB partition */ +/** + * @} + */ + /** * @} */ @@ -683,6 +708,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca */ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode); +HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition); /** * @} */ @@ -704,6 +730,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC */ HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc); uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetRPMBError(const MMC_HandleTypeDef *hmmc); /** * @} */ @@ -737,6 +764,29 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc); /** * @} */ + +/** @defgroup MMC_Exported_Functions_Group9 Replay Protected Memory Block management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, + uint32_t Timeout); +uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout); +uint32_t HAL_MMC_RPMB_GetWriteCounter_IT(MMC_HandleTypeDef *hmmc, uint8_t *pNonce); +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC); +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC, + uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC); + +/** + * @} + */ + /* Private types -------------------------------------------------------------*/ /** @defgroup MMC_Private_Types MMC Private Types * @{ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nand.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nand.h index 6341389f1c..040e1ecd7b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nand.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nand.h @@ -24,6 +24,7 @@ extern "C" { #endif +#if defined(FMC_BANK3) /* Includes ------------------------------------------------------------------*/ #include "stm32u5xx_ll_fmc.h" @@ -368,6 +369,7 @@ uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand); * @} */ +#endif /* FMC_BANK3 */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nor.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nor.h index e28f95b234..469ce91d3a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nor.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nor.h @@ -24,6 +24,7 @@ extern "C" { #endif +#if defined(FMC_BANK1) /* Includes ------------------------------------------------------------------*/ #include "stm32u5xx_ll_fmc.h" @@ -316,6 +317,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @} */ +#endif /* FMC_BANK1 */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_opamp.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_opamp.h index d6a0467e8b..2fa1e1397f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_opamp.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_opamp.h @@ -213,8 +213,8 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); * @{ */ #define OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED 0x00000000U /*!< OPAMP power mode normal speed normal */ -#define OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED OPAMP_CSR_HSM /*!< OPAMP power mode normal speed high */ #define OPAMP_POWERMODE_LOWPOWER_NORMALSPEED OPAMP_CSR_OPALPM /*!< OPAMP power mode low-power speed normal */ +#define OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED OPAMP_CSR_HSM /*!< OPAMP power mode normal speed high */ #define OPAMP_POWERMODE_LOWPOWER_HIGHSPEED (OPAMP_CSR_OPALPM | OPAMP_CSR_HSM) /*!< OPAMP power mode low-power speed high */ /** @@ -295,7 +295,6 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h index cfdf121fc7..b63abb7675 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h @@ -656,7 +656,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); */ #if defined (OCTOSPIM) -/** @defgroup OSPIM_IOPort OSPI IO Manager IO Port +/** @defgroup OSPI_IO_Manger_IOPort OSPI IO Manager IO Port * @{ */ #define HAL_OSPIM_IOPORT_NONE ((uint32_t)0x00000000U) /*!< IOs not used */ @@ -788,12 +788,12 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup OSPI_Exported_Functions +/** @addtogroup OSPI_Exported_Functions OSPI Exported Functions * @{ */ /* Initialization/de-initialization functions ********************************/ -/** @addtogroup OSPI_Exported_Functions_Group1 +/** @addtogroup OSPI_Exported_Functions_Group1 Initialization/de-initialization functions * @{ */ HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi); @@ -806,7 +806,7 @@ void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi); */ /* IO operation functions *****************************************************/ -/** @addtogroup OSPI_Exported_Functions_Group2 +/** @addtogroup OSPI_Exported_Functions_Group2 Input and Output operation functions * @{ */ /* OSPI IRQ handler function */ @@ -862,7 +862,7 @@ HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL */ /* Peripheral Control and State functions ************************************/ -/** @addtogroup OSPI_Exported_Functions_Group3 +/** @addtogroup OSPI_Exported_Functions_Group3 Peripheral Control and State functions * @{ */ HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi); @@ -879,7 +879,7 @@ uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi); #if defined (OCTOSPIM) /* OSPI IO Manager configuration function ************************************/ -/** @addtogroup OSPI_Exported_Functions_Group4 +/** @addtogroup OSPI_Exported_Functions_Group4 IO Manager configuration function * @{ */ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h index 561dfa872a..62741b5ec5 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h @@ -362,7 +362,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); #if defined (USB_OTG_FS) || defined (USB_OTG_HS) -HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode); +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode); #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pka.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pka.h index 5a043062b7..c131012493 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pka.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pka.h @@ -147,6 +147,21 @@ typedef struct const uint8_t *primeOrder; /*!< pointer to order of the curve */ } PKA_ECCMulInTypeDef; +typedef struct +{ + uint32_t primeOrderSize; /*!< Number of element in primeOrder array */ + uint32_t scalarMulSize; /*!< Number of element in scalarMul array */ + uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */ + uint32_t coefSign; /*!< Curve coefficient a sign */ + const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */ + const uint8_t *coefB; /*!< pointer to curve coefficient b */ + const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */ + const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */ + const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */ + const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */ + const uint8_t *primeOrder; /*!< pointer to order of the curve */ +} PKA_ECCMulExInTypeDef; + typedef struct { uint32_t modulusSize; /*!< Number of element in coefA, coefB, modulus, pointX and pointY arrays */ @@ -572,6 +587,8 @@ uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka); HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout); HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in); void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out); HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pssi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pssi.h index f923d1dcce..5d4e328317 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pssi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pssi.h @@ -53,12 +53,18 @@ extern "C" { */ typedef struct { - uint32_t DataWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */ - uint32_t BusWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */ - uint32_t ControlSignal; /* !< Configures Data enable and Data ready */ - uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity */ - uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity */ - uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity */ + uint32_t DataWidth; /* !< Configures the data width. + This parameter can be a value of @ref PSSI_DATA_WIDTH. */ + uint32_t BusWidth; /* !< Configures the parallel bus width. + This parameter can be a value of @ref PSSI_BUS_WIDTH. */ + uint32_t ControlSignal; /* !< Configures Data enable and Data ready. + This parameter can be a value of @ref ControlSignal_Configuration. */ + uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity. + This parameter can be a value of @ref Clock_Polarity. */ + uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity. + This parameter can be a value of @ref Data_Enable_Polarity. */ + uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity. + This parameter can be a value of @ref Ready_Polarity. */ } PSSI_InitTypeDef; @@ -216,7 +222,7 @@ typedef enum /** * @} */ -/** @defgroup Reday_Polarity Reday Polarity +/** @defgroup Ready_Polarity Ready Polarity * @{ */ #define HAL_PSSI_RDYPOL_ACTIVE_LOW 0x0U /*!< Active Low */ @@ -230,8 +236,6 @@ typedef enum */ #define HAL_PSSI_FALLING_EDGE 0x0U /*!< Fallling Edge */ #define HAL_PSSI_RISING_EDGE 0x1U /*!< Rising Edge */ - - /** * @} */ @@ -432,6 +436,7 @@ typedef enum #define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW ) || \ ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH )) + /** * @} */ @@ -486,7 +491,7 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi); /* Peripheral State functions ***************************************************/ HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi); -uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi); +uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi); /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr.h index 672cfc2335..c44722dc9d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr.h @@ -105,8 +105,9 @@ typedef struct /** @defgroup PWR_Sleep_Mode_Entry PWR Sleep Mode Entry * @{ */ -#define PWR_SLEEPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Sleep mode */ -#define PWR_SLEEPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR (0x03U) /** * @} */ @@ -114,8 +115,9 @@ typedef struct /** @defgroup PWR_Stop_Mode_Entry PWR Stop Mode Entry * @{ */ -#define PWR_STOPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Stop mode */ -#define PWR_STOPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFE_NO_EVT_CLEAR (0x03U) /** * @} */ @@ -702,12 +704,14 @@ typedef struct ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) /* Sleep mode entry check macro */ -#define IS_PWR_SLEEP_ENTRY(ENTRY) \ - (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\ + ((ENTRY) == PWR_SLEEPENTRY_WFE) ||\ + ((ENTRY) == PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)) /* Stop mode entry check macro */ -#define IS_PWR_STOP_ENTRY(ENTRY) \ - (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\ + ((ENTRY) == PWR_STOPENTRY_WFE) ||\ + ((ENTRY) == PWR_STOPENTRY_WFE_NO_EVT_CLEAR)) /* PWR items check macro */ #define IS_PWR_ITEMS_ATTRIBUTES(ITEM) \ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h index ecf0ef49f2..394d30d5f3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h @@ -324,8 +324,6 @@ typedef struct */ - - /** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output * @{ */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc_ex.h index 76955dc4ab..dc7bf097c2 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc_ex.h @@ -311,7 +311,7 @@ typedef struct @ref RCCEx_CRS_ErrorLimitDefault */ uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. - This parameter must be a number between 0 and 0x3F or a value of + This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ } RCC_CRSInitTypeDef; @@ -1029,7 +1029,7 @@ typedef struct /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault * @{ */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to +#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h index 7341fc1edb..a01303c1ba 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h @@ -62,6 +62,8 @@ typedef struct value of @ref RNG_Ex_Auto_Reset */ uint32_t HealthTest; /*!< RNG health test control must be a value between 0x0FFCABFF and 0x00005200 */ + uint32_t NoiseSource; /*!< RNG noise source control(Oscillator Enable signals) + must be a value between 0x0 and 0x0003FFFF */ } RNG_ConfigTypeDef; /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc_ex.h index bd0100dd35..0514e64f8b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc_ex.h @@ -997,7 +997,7 @@ typedef struct * @arg @ref RTC_FLAG_WUTF * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CWUTF)) +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG(RTC->SCR, RTC_SCR_CWUTF)) /** * @} @@ -1086,8 +1086,8 @@ typedef struct * @retval None */ #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)( \ - ((__FLAG__) == RTC_FLAG_TSF) ? (SET_BIT(RTC->SCR, RTC_SCR_CTSF)):\ - ((__FLAG__) == RTC_FLAG_TSOVF) ? (SET_BIT(RTC->SCR, RTC_SCR_CTSOVF)):\ + ((__FLAG__) == RTC_FLAG_TSF) ? (WRITE_REG(RTC->SCR, RTC_SCR_CTSF)):\ + ((__FLAG__) == RTC_FLAG_TSOVF) ? (WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF)):\ (0U)) /* Dummy action because is an invalid parameter value */ /** @@ -1445,9 +1445,9 @@ typedef struct */ #define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & (RTC_MISR_SSRUMF)) != 0U) ? 1U : 0U) /** - * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @brief Check whether the specified RTC SSRU interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. + * @param __INTERRUPT__ specifies the RTC SSRU interrupt sources to check. * This parameter can be: * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval The state of __INTERRUPT__ (TRUE or FALSE) @@ -1465,14 +1465,14 @@ typedef struct #define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->SR, RTC_SR_SSRUF) == RTC_SR_SSRUF)) /** - * @brief Clear the RTC Wake Up timer's pending flags. + * @brief Clear the RTC SSRU's pending flags. * @param __HANDLE__ specifies the RTC handle. * @param __FLAG__ specifies the RTC SSRU Flag to clear. * This parameter can be: * @arg @ref RTC_FLAG_SSRUF * @retval None */ -#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CSSRUF)) +#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG(RTC->SCR, RTC_SCR_CSSRUF)) /** * @} */ @@ -1658,7 +1658,6 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_Privil #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT)) - #define IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smbus.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smbus.h index da6299fdeb..e100c028e9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smbus.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smbus.h @@ -100,8 +100,6 @@ typedef struct #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h index b6fea7baf1..707bb07494 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h @@ -168,8 +168,8 @@ typedef struct #if defined(SPI_TRIG_GRP2) #define IS_SPI_TRIG_SOURCE(__INSTANCE__, __SOURCE__) ((IS_SPI_GRP2_INSTANCE(__INSTANCE__)) ? \ - IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) : \ - IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__)) + IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) : \ + IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__)) #endif /* SPI_TRIG_GRP2 */ #define IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SPI_GRP1_GPDMA_CH0_TCF_TRG ) || \ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sram.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sram.h index ac2f7fdb94..5cf9ca82cb 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sram.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sram.h @@ -24,6 +24,7 @@ extern "C" { #endif +#if defined(FMC_BANK1) /* Includes ------------------------------------------------------------------*/ #include "stm32u5xx_ll_fmc.h" @@ -222,6 +223,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram); * @} */ +#endif /* FMC_BANK1 */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h index 68bf074854..e5919c183d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h @@ -474,7 +474,9 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */ #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ #define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */ +#if defined(COMP2) #define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */ +#endif /* COMP2 */ /** * @} */ @@ -1065,8 +1067,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ -#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ -#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ #define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */ #define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */ /** @@ -1844,10 +1846,16 @@ mode. /** @defgroup TIM_Private_Macros TIM Private Macros * @{ */ +#if defined(COMP2) #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) +#else +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) +#endif /* COMP2 */ #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ ((__BASE__) == TIM_DMABASE_CR2) || \ @@ -2086,8 +2094,8 @@ mode. ((__MODE__) == TIM_OCMODE_PWM2) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ ((__MODE__) == TIM_OCMODE_ACTIVE) || \ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim_ex.h index e45a20e25b..b800440aca 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim_ex.h @@ -108,7 +108,9 @@ typedef struct */ #define TIM_TIM1_ETR_GPIO 0x00000000UL /*!< TIM1_ETR is not connected to I/O */ #define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */ +#if defined(COMP2) #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 output */ +#endif /* COMP2 */ #define TIM_TIM1_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to MSIK */ #define TIM_TIM1_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM1_ETR is connected to HSI */ #define TIM_TIM1_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to MSI */ @@ -128,7 +130,9 @@ typedef struct #define TIM_TIM2_ETR_GPIO 0x00000000UL /*!< TIM2_ETR is not connected to I/O */ #define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */ +#if defined(COMP2) #define TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM2_ETR is connected to COMP2 output */ +#endif /* COMP2 */ #define TIM_TIM2_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to MSIK */ #define TIM_TIM2_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to HSI */ #define TIM_TIM2_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to MSIS */ @@ -150,7 +154,9 @@ typedef struct #define TIM_TIM3_ETR_GPIO 0x00000000UL /*!< TIM3_ETR is not connected to I/O */ #define TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 output */ +#if defined(COMP2) #define TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM3_ETR is connected to COMP2 output */ +#endif /* COMP2 */ #define TIM_TIM3_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to MSIK */ #define TIM_TIM3_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM3_ETR is connected to HSI */ #define TIM_TIM3_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to MSIS */ @@ -173,7 +179,9 @@ typedef struct #define TIM_TIM4_ETR_GPIO 0x00000000UL /*!< TIM4_ETR is not connected to I/O */ #define TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM4_ETR is connected to COMP1 output */ +#if defined(COMP2) #define TIM_TIM4_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM4_ETR is connected to COMP2 output */ +#endif /* COMP2 */ #define TIM_TIM4_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to MSIK */ #define TIM_TIM4_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM4_ETR is connected to HSI */ #define TIM_TIM4_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to MSIS */ @@ -198,7 +206,9 @@ typedef struct #define TIM_TIM5_ETR_GPIO 0x00000000UL /*!< TIM5_ETR is not connected to I/O */ #define TIM_TIM5_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to COMP1 output */ +#if defined(COMP2) #define TIM_TIM5_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to COMP2 output */ +#endif /* COMP2 */ #define TIM_TIM5_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to MSIK */ #define TIM_TIM5_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM5_ETR is connected to HSI */ #define TIM_TIM5_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to MSIS */ @@ -218,7 +228,9 @@ typedef struct #define TIM_TIM8_ETR_GPIO 0x00000000UL /*!< TIM8_ETR is not connected to I/O */ #define TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 output */ +#if defined(COMP2) #define TIM_TIM8_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 output */ +#endif /* COMP2 */ #define TIM_TIM8_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to MSIK */ #define TIM_TIM8_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM8_ETR is connected to HSI */ #define TIM_TIM8_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to MSIS */ @@ -253,7 +265,9 @@ typedef struct */ #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */ +#if defined(COMP2) #define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */ +#endif /* COMP2 */ #define TIM_BREAKINPUTSOURCE_MDF1 0x00000008U /*!< The analog watchdog output of the MDF1 peripheral is connected to the break input */ /** * @} @@ -282,53 +296,79 @@ typedef struct */ #define TIM_TIM1_TI1_GPIO 0x00000000UL /*!< TIM1_TI1 is connected to GPIO */ #define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 OUT */ +#if defined(COMP2) #define TIM_TIM1_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1_TI1 is connected to COMP2 OUT */ +#endif /* COMP2 */ #define TIM_TIM2_TI1_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */ #define TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to COMP1 OUT */ +#if defined(COMP2) #define TIM_TIM2_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to COMP2 OUT */ +#endif /* COMP2 */ #define TIM_TIM2_TI2_GPIO 0x00000000UL /*!< TIM2_TI2 is connected to GPIO */ #define TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to COMP1 OUT */ +#if defined(COMP2) #define TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to COMP2 OUT */ +#endif /* COMP2 */ #define TIM_TIM2_TI4_GPIO 0x00000000UL /*!< TIM2_TI4 is connected to GPIO */ #define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 OUT */ +#if defined(COMP2) #define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2_TI4 is connected to COMP2 OUT */ +#endif /* COMP2 */ #define TIM_TIM3_TI1_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */ #define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to COMP1 OUT */ +#if defined(COMP2) #define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP2 OUT */ +#endif /* COMP2 */ #define TIM_TIM3_TI2_GPIO 0x00000000UL /*!< TIM3_TI2 is connected to GPIO */ #define TIM_TIM3_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to COMP1 OUT */ +#if defined(COMP2) #define TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to COMP2 OUT */ +#endif /* COMP2 */ #define TIM_TIM4_TI1_GPIO 0x00000000UL /*!< TIM4_TI1 is connected to GPIO */ #define TIM_TIM4_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4_TI1 is connected to COMP1 OUT */ +#if defined(COMP2) #define TIM_TIM4_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4_TI1 is connected to COMP2 OUT */ +#endif /* COMP2 */ #define TIM_TIM4_TI2_GPIO 0x00000000UL /*!< TIM4_TI2 is connected to GPIO */ #define TIM_TIM4_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM4_TI2 is connected to COMP1 OUT */ +#if defined(COMP2) #define TIM_TIM4_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM4_TI2 is connected to COMP2 OUT */ +#endif /* COMP2 */ #define TIM_TIM5_TI1_GPIO 0x00000000UL /*!< TIM5_TI1 is connected to GPIO */ #define TIM_TIM5_TI1_LSI TIM_TISEL_TI1SEL_0 /*!< TIM5_TI1 is connected to LSI */ #define TIM_TIM5_TI1_LSE TIM_TISEL_TI1SEL_1 /*!< TIM5_TI1 is connected to LSE */ #define TIM_TIM5_TI1_RTC_WKUP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5_TI1 is connected to RTC Wakeup */ #define TIM_TIM5_TI1_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM5_COMP1 is connected to COMP1 OUT */ +#if defined(COMP2) #define TIM_TIM5_TI1_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM5_COMP2 is connected to COMP2 OUT */ +#endif /* COMP2 */ #define TIM_TIM5_TI2_GPIO 0x00000000UL /*!< TIM5_TI2 is connected to GPIO */ #define TIM_TIM5_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM5_TI2 is connected to COMP1 OUT */ +#if defined(COMP2) #define TIM_TIM5_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM5_TI2 is connected to COMP2 OUT */ +#endif /* COMP2 */ #define TIM_TIM8_TI1_GPIO 0x00000000UL /*!< TIM8_TI1 is connected to GPIO */ #define TIM_TIM8_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM8_TI1 is connected to COMP1 OUT */ +#if defined(COMP2) #define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM8_TI1 is connected to COMP2 OUT */ +#endif /* COMP2 */ #define TIM_TIM15_TI1_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */ #define TIM_TIM15_TI1_LSE TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to LSE */ #define TIM_TIM15_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to COMP1 OUT */ +#if defined(COMP2) #define TIM_TIM15_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to COMP2 OUT */ +#endif /* COMP2 */ #define TIM_TIM15_TI2_GPIO 0x00000000UL /*!< TIM15_TI2 is connected to GPIO */ +#if defined(COMP2) #define TIM_TIM15_TI2_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM15_TI2 is connected to COMP2 OUT */ +#endif /* COMP2 */ #define TIM_TIM16_TI1_GPIO 0x00000000UL /*!< TIM16_TI1 is connected to GPIO */ #define TIM_TIM16_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16_TI1 is connected to MCO */ @@ -530,10 +570,16 @@ typedef struct #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) +#if defined(COMP2) #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_MDF1)) +#else +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_MDF1)) +#endif /* COMP2 */ #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h index 25831420f3..fd29060dd7 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h @@ -66,7 +66,7 @@ typedef struct uint32_t TriggerSelection; /*!< Specifies which trigger will activate the Transmission automatically. This parameter can be a value of @ref UARTEx_Autonomous_Trigger_selection - or @ref LPUARTEx_Autonomous_Trigger_selection.*/ + or @ref UARTEx_Low_Power_Autonomous_Trigger_selection.*/ uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity. This parameter can be a value of @ref UARTEx_Autonomous_Trigger_Polarity */ @@ -193,7 +193,7 @@ typedef struct * @} */ -/** @defgroup LPUARTEx_Autonomous_Trigger_selection LPUARTEx Autonomous trigger selection +/** @defgroup UARTEx_Low_Power_Autonomous_Trigger_selection UARTEx Low Power Autonomous trigger selection * @brief LPUART Autonomous Trigger selection * @{ */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h index 1b76114249..8014fe488d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h @@ -781,7 +781,8 @@ typedef struct */ #if defined(OCTOSPIM) -/** @defgroup XSPIM_IOPort XSPI IO Manager IO Port + +/** @defgroup XSPI_IO_Manger_IOPort XSPI IO Port * @{ */ #define HAL_XSPIM_IOPORT_NONE (0x00000000U) /*!< IOs not used */ @@ -936,12 +937,12 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup XSPI_Exported_Functions +/** @addtogroup XSPI_Exported_Functions XSPI Exported Functions * @{ */ /* Initialization/de-initialization functions ********************************/ -/** @addtogroup XSPI_Exported_Functions_Group1 +/** @addtogroup XSPI_Exported_Functions_Group1 Initialization/de-initialization functions * @{ */ HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi); @@ -954,7 +955,7 @@ void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi); */ /* IO operation functions *****************************************************/ -/** @addtogroup XSPI_Exported_Functions_Group2 +/** @addtogroup XSPI_Exported_Functions_Group2 Input and Output operation functions * @{ */ /* XSPI IRQ handler function */ @@ -1015,7 +1016,7 @@ HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL */ /* Peripheral Control and State functions ************************************/ -/** @addtogroup XSPI_Exported_Functions_Group3 +/** @addtogroup XSPI_Exported_Functions_Group3 Peripheral Control and State functions * @{ */ HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi); @@ -1035,10 +1036,10 @@ uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi); #if defined(OCTOSPIM) /* XSPI IO Manager configuration function ************************************/ -/** @addtogroup XSPI_Exported_Functions_Group4 +/** @addtogroup XSPI_Exported_Functions_Group4 IO Manager configuration function * @{ */ -HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout); /** * @} @@ -1046,11 +1047,9 @@ HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *hxspi, XSPIM_CfgTypeD #endif /* OCTOSPIM */ /* XSPI Delay Block functions ************************************/ -#if defined(OCTOSPIM) /** @addtogroup XSPI_Exported_Functions_Group5 Delay Block function * @{ */ -#endif /* OCTOSPIM */ HAL_StatusTypeDef HAL_XSPI_DLYB_SetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg); HAL_StatusTypeDef HAL_XSPI_DLYB_GetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg); @@ -1063,7 +1062,7 @@ HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi, #if defined(HSPI_CALFCR_FINE) /* XSPI high-speed interface and calibration functions ***********************/ -/** @addtogroup XSPI_Exported_Functions_Group6 +/** @addtogroup XSPI_Exported_Functions_Group6 High-speed interface and calibration functions * @{ */ HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h index 061e116698..78afbdd4f3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h @@ -21,8 +21,9 @@ [..] The LL CORTEX driver contains a set of generic APIs that can be used by user: - (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick - functions + (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick with + HCLK source or @ref LL_Init1msTick_HCLK_Div8, @ref LL_Init1msTick_LSI or + @ref LL_Init1msTick_LSE with external source (+) Low power mode configuration (SCB register of Cortex-MCU) (+) API to access to MCU info (CPUID register) (+) API to enable fault handler (SHCSR accesses) @@ -74,10 +75,15 @@ extern "C" { /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source * @{ */ -#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick +#define LL_SYSTICK_CLKSOURCE_EXTERNAL 0x00000000U /*!< External clock source selected as SysTick clock source */ #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source */ +/** Legacy definitions for backward compatibility purpose + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 LL_SYSTICK_CLKSOURCE_EXTERNAL +/** + */ /** * @} */ @@ -149,7 +155,7 @@ extern "C" { * @{ */ #define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) -#define LL_MPU_ACCESS_OUTER_SHAREABLE (1U << MPU_RBAR_SH_Pos) +#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) #define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /** * @} @@ -227,7 +233,7 @@ __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) * @brief Configures the SysTick clock source * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK * @retval None */ @@ -247,7 +253,7 @@ __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) * @brief Get the SysTick clock source * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK */ __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) @@ -783,9 +789,6 @@ __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, u /* Set region index */ WRITE_REG(MPU->RNR, Region); - /* Set base address */ - MPU->RBAR |= Attributes; - /* Set region base address and region access attributes */ WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crs.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crs.h index 163d6f1c85..678c2e7992 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crs.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crs.h @@ -290,7 +290,7 @@ __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) * @brief Set HSI48 oscillator smooth trimming * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming - * @param Value a number between Min_Data = 0 and Max_Data = 63 + * @param Value a number between Min_Data = 0 and Max_Data = 127 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT * @retval None */ @@ -302,7 +302,7 @@ __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) /** * @brief Get HSI48 oscillator smooth trimming * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming - * @retval a number between Min_Data = 0 and Max_Data = 63 + * @retval a number between Min_Data = 0 and Max_Data = 127 */ __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) { @@ -451,7 +451,7 @@ __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n * CFGR SYNCPOL LL_CRS_ConfigSynchronization - * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 + * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 127 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 * @param Settings This parameter can be a combination of the following values: diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dcache.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dcache.h index 406f9088f1..8d6ca6aaf5 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dcache.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dcache.h @@ -405,44 +405,44 @@ __STATIC_INLINE void LL_DCACHE_ResetMonitors(DCACHE_TypeDef *DCACHEx, uint32_t M /** * @brief Get the Read Hit monitor Value - * @rmtoll RHMONR LL_DCACHE_Monitor_GetReadHitValue + * @rmtoll RHMONR RHITMON LL_DCACHE_Monitor_GetReadHitValue * @param DCACHEx DCACHE instance * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadHitValue(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadHitValue(const DCACHE_TypeDef *DCACHEx) { return DCACHEx->RHMONR; } /** * @brief Get the Read Miss monitor Value - * @rmtoll RMMONR LL_DCACHE_Monitor_GetReadMissValue + * @rmtoll RMMONR RMISSMON LL_DCACHE_Monitor_GetReadMissValue * @param DCACHEx DCACHE instance * @retval Value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadMissValue(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadMissValue(const DCACHE_TypeDef *DCACHEx) { return DCACHEx->RMMONR; } /** * @brief Get the Write Hit monitor Value - * @rmtoll WHMONR LL_DCACHE_Monitor_GetWriteHitValue + * @rmtoll WHMONR WHITMON LL_DCACHE_Monitor_GetWriteHitValue * @param DCACHEx DCACHE instance * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteHitValue(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteHitValue(const DCACHE_TypeDef *DCACHEx) { return DCACHEx->WHMONR; } /** * @brief Get the Write Miss monitor Value - * @rmtoll WMMONR LL_DCACHE_Monitor_GetWriteMissValue + * @rmtoll WMMONR WMISSMON LL_DCACHE_Monitor_GetWriteMissValue * @param DCACHEx DCACHE instance * @retval Value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteMissValue(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteMissValue(const DCACHE_TypeDef *DCACHEx) { return DCACHEx->WMMONR; } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dlyb.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dlyb.h index 5b1774c9df..cb98f2fd44 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dlyb.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dlyb.h @@ -32,6 +32,7 @@ extern "C" { */ #if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED) +#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_OCTOSPI1) || defined (DLYB_OCTOSPI2) /* Exported types ------------------------------------------------------------*/ /** @defgroup DLYB_LL DLYB @@ -128,6 +129,7 @@ uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_c * @} */ +#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 || DLYB_OCTOSPI1 || DLYB_OCTOSPI2 */ #endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */ /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h index a082b7249b..18bd575f08 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h @@ -384,7 +384,7 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t DestSecure; /*!< This field specify the destination secure. This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */ @@ -407,7 +407,7 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t SrcSecure; /*!< This field specify the source secure. This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */ @@ -590,14 +590,14 @@ typedef struct */ typedef struct { - __IO uint32_t LinkRegisters[8]; + __IO uint32_t LinkRegisters[8U]; } LL_DMA_LinkNodeTypeDef; /** * @} */ -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* USE_FULL_LL_DRIVER */ /* Exported constants --------------------------------------------------------*/ @@ -626,7 +626,7 @@ typedef struct #define LL_DMA_CHANNEL_15 (0x0FU) #if defined (USE_FULL_LL_DRIVER) #define LL_DMA_CHANNEL_ALL (0x10U) -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* USE_FULL_LL_DRIVER */ /** * @} */ @@ -646,7 +646,7 @@ typedef struct /** * @} */ -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* USE_FULL_LL_DRIVER */ /** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level * @{ @@ -922,7 +922,7 @@ typedef struct /** * @} */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type * @{ @@ -962,174 +962,174 @@ typedef struct * @{ */ /* GPDMA1 Hardware Requests */ -#define LL_GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW Request is ADC1 */ -#define LL_GPDMA1_REQUEST_ADC4 1U /*!< GPDMA1 HW Request is ADC4 */ -#define LL_GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW Request is DAC1_CH1 */ -#define LL_GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW Request is DAC1_CH2 */ -#define LL_GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW Request is TIM6_UP */ -#define LL_GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW Request is TIM7_UP */ -#define LL_GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW Request is SPI1_RX */ -#define LL_GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW Request is SPI1_TX */ -#define LL_GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW Request is SPI2_RX */ -#define LL_GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW Request is SPI2_TX */ -#define LL_GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW Request is SPI3_RX */ -#define LL_GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW Request is SPI3_TX */ -#define LL_GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW Request is I2C1_RX */ -#define LL_GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW Request is I2C1_TX */ -#define LL_GPDMA1_REQUEST_I2C1_EVC 14U /*!< GPDMA1 HW Request is I2C1_EVC */ -#define LL_GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW Request is I2C2_RX */ -#define LL_GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW Request is I2C2_TX */ -#define LL_GPDMA1_REQUEST_I2C2_EVC 17U /*!< GPDMA1 HW Request is I2C2_EVC */ -#define LL_GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW Request is I2C3_RX */ -#define LL_GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW Request is I2C3_TX */ -#define LL_GPDMA1_REQUEST_I2C3_EVC 20U /*!< GPDMA1 HW Request is I2C3_EVC */ -#define LL_GPDMA1_REQUEST_I2C4_RX 21U /*!< GPDMA1 HW Request is I2C4_RX */ -#define LL_GPDMA1_REQUEST_I2C4_TX 22U /*!< GPDMA1 HW Request is I2C4_TX */ -#define LL_GPDMA1_REQUEST_I2C4_EVC 23U /*!< GPDMA1 HW Request is I2C4_EVC */ -#define LL_GPDMA1_REQUEST_USART1_RX 24U /*!< GPDMA1 HW Request is USART1_RX */ -#define LL_GPDMA1_REQUEST_USART1_TX 25U /*!< GPDMA1 HW Request is USART1_TX */ +#define LL_GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW Request is ADC1 */ +#define LL_GPDMA1_REQUEST_ADC4 1U /*!< GPDMA1 HW Request is ADC4 */ +#define LL_GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW Request is DAC1_CH1 */ +#define LL_GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW Request is DAC1_CH2 */ +#define LL_GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW Request is TIM6_UP */ +#define LL_GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW Request is TIM7_UP */ +#define LL_GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW Request is SPI1_RX */ +#define LL_GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW Request is SPI1_TX */ +#define LL_GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW Request is SPI2_RX */ +#define LL_GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW Request is SPI2_TX */ +#define LL_GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW Request is SPI3_RX */ +#define LL_GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW Request is SPI3_TX */ +#define LL_GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW Request is I2C1_RX */ +#define LL_GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW Request is I2C1_TX */ +#define LL_GPDMA1_REQUEST_I2C1_EVC 14U /*!< GPDMA1 HW Request is I2C1_EVC */ +#define LL_GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW Request is I2C2_RX */ +#define LL_GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW Request is I2C2_TX */ +#define LL_GPDMA1_REQUEST_I2C2_EVC 17U /*!< GPDMA1 HW Request is I2C2_EVC */ +#define LL_GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW Request is I2C3_RX */ +#define LL_GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW Request is I2C3_TX */ +#define LL_GPDMA1_REQUEST_I2C3_EVC 20U /*!< GPDMA1 HW Request is I2C3_EVC */ +#define LL_GPDMA1_REQUEST_I2C4_RX 21U /*!< GPDMA1 HW Request is I2C4_RX */ +#define LL_GPDMA1_REQUEST_I2C4_TX 22U /*!< GPDMA1 HW Request is I2C4_TX */ +#define LL_GPDMA1_REQUEST_I2C4_EVC 23U /*!< GPDMA1 HW Request is I2C4_EVC */ +#define LL_GPDMA1_REQUEST_USART1_RX 24U /*!< GPDMA1 HW Request is USART1_RX */ +#define LL_GPDMA1_REQUEST_USART1_TX 25U /*!< GPDMA1 HW Request is USART1_TX */ #if defined(USART2) -#define LL_GPDMA1_REQUEST_USART2_RX 26U /*!< GPDMA1 HW Request is USART2_RX */ -#define LL_GPDMA1_REQUEST_USART2_TX 27U /*!< GPDMA1 HW Request is USART2_TX */ +#define LL_GPDMA1_REQUEST_USART2_RX 26U /*!< GPDMA1 HW Request is USART2_RX */ +#define LL_GPDMA1_REQUEST_USART2_TX 27U /*!< GPDMA1 HW Request is USART2_TX */ #endif /* USART2 */ -#define LL_GPDMA1_REQUEST_USART3_RX 28U /*!< GPDMA1 HW Request is USART3_RX */ -#define LL_GPDMA1_REQUEST_USART3_TX 29U /*!< GPDMA1 HW Request is USART3_TX */ -#define LL_GPDMA1_REQUEST_UART4_RX 30U /*!< GPDMA1 HW Request is UART4_RX */ -#define LL_GPDMA1_REQUEST_UART4_TX 31U /*!< GPDMA1 HW Request is UART4_TX */ -#define LL_GPDMA1_REQUEST_UART5_RX 32U /*!< GPDMA1 HW Request is UART5_RX */ -#define LL_GPDMA1_REQUEST_UART5_TX 33U /*!< GPDMA1 HW Request is UART5_TX */ -#define LL_GPDMA1_REQUEST_LPUART1_RX 34U /*!< GPDMA1 HW Request is LPUART1_RX */ -#define LL_GPDMA1_REQUEST_LPUART1_TX 35U /*!< GPDMA1 HW Request is LPUART1_TX */ -#define LL_GPDMA1_REQUEST_SAI1_A 36U /*!< GPDMA1 HW Request is SAI1_A */ -#define LL_GPDMA1_REQUEST_SAI1_B 37U /*!< GPDMA1 HW Request is SAI1_B */ +#define LL_GPDMA1_REQUEST_USART3_RX 28U /*!< GPDMA1 HW Request is USART3_RX */ +#define LL_GPDMA1_REQUEST_USART3_TX 29U /*!< GPDMA1 HW Request is USART3_TX */ +#define LL_GPDMA1_REQUEST_UART4_RX 30U /*!< GPDMA1 HW Request is UART4_RX */ +#define LL_GPDMA1_REQUEST_UART4_TX 31U /*!< GPDMA1 HW Request is UART4_TX */ +#define LL_GPDMA1_REQUEST_UART5_RX 32U /*!< GPDMA1 HW Request is UART5_RX */ +#define LL_GPDMA1_REQUEST_UART5_TX 33U /*!< GPDMA1 HW Request is UART5_TX */ +#define LL_GPDMA1_REQUEST_LPUART1_RX 34U /*!< GPDMA1 HW Request is LPUART1_RX */ +#define LL_GPDMA1_REQUEST_LPUART1_TX 35U /*!< GPDMA1 HW Request is LPUART1_TX */ +#define LL_GPDMA1_REQUEST_SAI1_A 36U /*!< GPDMA1 HW Request is SAI1_A */ +#define LL_GPDMA1_REQUEST_SAI1_B 37U /*!< GPDMA1 HW Request is SAI1_B */ #if defined(SAI2) -#define LL_GPDMA1_REQUEST_SAI2_A 38U /*!< GPDMA1 HW Request is SAI2_A */ -#define LL_GPDMA1_REQUEST_SAI2_B 39U /*!< GPDMA1 HW Request is SAI2_B */ +#define LL_GPDMA1_REQUEST_SAI2_A 38U /*!< GPDMA1 HW Request is SAI2_A */ +#define LL_GPDMA1_REQUEST_SAI2_B 39U /*!< GPDMA1 HW Request is SAI2_B */ #endif /* SAI2 */ -#define LL_GPDMA1_REQUEST_OCTOSPI1 40U /*!< GPDMA1 HW Request is OCTOSPI1 */ +#define LL_GPDMA1_REQUEST_OCTOSPI1 40U /*!< GPDMA1 HW Request is OCTOSPI1 */ #if defined(OCTOSPI2) -#define LL_GPDMA1_REQUEST_OCTOSPI2 41U /*!< GPDMA1 HW Request is OCTOSPI2 */ +#define LL_GPDMA1_REQUEST_OCTOSPI2 41U /*!< GPDMA1 HW Request is OCTOSPI2 */ #endif /* OCTOSPI2 */ -#define LL_GPDMA1_REQUEST_TIM1_CH1 42U /*!< GPDMA1 HW Request is TIM1_CH1 */ -#define LL_GPDMA1_REQUEST_TIM1_CH2 43U /*!< GPDMA1 HW Request is TIM1_CH2 */ -#define LL_GPDMA1_REQUEST_TIM1_CH3 44U /*!< GPDMA1 HW Request is TIM1_CH3 */ -#define LL_GPDMA1_REQUEST_TIM1_CH4 45U /*!< GPDMA1 HW Request is TIM1_CH4 */ -#define LL_GPDMA1_REQUEST_TIM1_UP 46U /*!< GPDMA1 HW Request is TIM1_UP */ -#define LL_GPDMA1_REQUEST_TIM1_TRIG 47U /*!< GPDMA1 HW Request is TIM1_TRIG */ -#define LL_GPDMA1_REQUEST_TIM1_COM 48U /*!< GPDMA1 HW Request is TIM1_COM */ -#define LL_GPDMA1_REQUEST_TIM8_CH1 49U /*!< GPDMA1 HW Request is TIM8_CH1 */ -#define LL_GPDMA1_REQUEST_TIM8_CH2 50U /*!< GPDMA1 HW Request is TIM8_CH2 */ -#define LL_GPDMA1_REQUEST_TIM8_CH3 51U /*!< GPDMA1 HW Request is TIM8_CH3 */ -#define LL_GPDMA1_REQUEST_TIM8_CH4 52U /*!< GPDMA1 HW Request is TIM8_CH4 */ -#define LL_GPDMA1_REQUEST_TIM8_UP 53U /*!< GPDMA1 HW Request is TIM8_UP */ -#define LL_GPDMA1_REQUEST_TIM8_TRIG 54U /*!< GPDMA1 HW Request is TIM8_TRIG */ -#define LL_GPDMA1_REQUEST_TIM8_COM 55U /*!< GPDMA1 HW Request is TIM8_COM */ -#define LL_GPDMA1_REQUEST_TIM2_CH1 56U /*!< GPDMA1 HW Request is TIM2_CH1 */ -#define LL_GPDMA1_REQUEST_TIM2_CH2 57U /*!< GPDMA1 HW Request is TIM2_CH2 */ -#define LL_GPDMA1_REQUEST_TIM2_CH3 58U /*!< GPDMA1 HW Request is TIM2_CH3 */ -#define LL_GPDMA1_REQUEST_TIM2_CH4 59U /*!< GPDMA1 HW Request is TIM2_CH4 */ -#define LL_GPDMA1_REQUEST_TIM2_UP 60U /*!< GPDMA1 HW Request is TIM2_UP */ -#define LL_GPDMA1_REQUEST_TIM3_CH1 61U /*!< GPDMA1 HW Request is TIM3_CH1 */ -#define LL_GPDMA1_REQUEST_TIM3_CH2 62U /*!< GPDMA1 HW Request is TIM3_CH2 */ -#define LL_GPDMA1_REQUEST_TIM3_CH3 63U /*!< GPDMA1 HW Request is TIM3_CH3 */ -#define LL_GPDMA1_REQUEST_TIM3_CH4 64U /*!< GPDMA1 HW Request is TIM3_CH4 */ -#define LL_GPDMA1_REQUEST_TIM3_UP 65U /*!< GPDMA1 HW Request is TIM3_UP */ -#define LL_GPDMA1_REQUEST_TIM3_TRIG 66U /*!< GPDMA1 HW Request is TIM3_TRIG */ -#define LL_GPDMA1_REQUEST_TIM4_CH1 67U /*!< GPDMA1 HW Request is TIM4_CH1 */ -#define LL_GPDMA1_REQUEST_TIM4_CH2 68U /*!< GPDMA1 HW Request is TIM4_CH2 */ -#define LL_GPDMA1_REQUEST_TIM4_CH3 69U /*!< GPDMA1 HW Request is TIM4_CH3 */ -#define LL_GPDMA1_REQUEST_TIM4_CH4 70U /*!< GPDMA1 HW Request is TIM4_CH4 */ -#define LL_GPDMA1_REQUEST_TIM4_UP 71U /*!< GPDMA1 HW Request is TIM4_UP */ -#define LL_GPDMA1_REQUEST_TIM5_CH1 72U /*!< GPDMA1 HW Request is TIM5_CH1 */ -#define LL_GPDMA1_REQUEST_TIM5_CH2 73U /*!< GPDMA1 HW Request is TIM5_CH2 */ -#define LL_GPDMA1_REQUEST_TIM5_CH3 74U /*!< GPDMA1 HW Request is TIM5_CH3 */ -#define LL_GPDMA1_REQUEST_TIM5_CH4 75U /*!< GPDMA1 HW Request is TIM5_CH4 */ -#define LL_GPDMA1_REQUEST_TIM5_UP 76U /*!< GPDMA1 HW Request is TIM5_UP */ -#define LL_GPDMA1_REQUEST_TIM5_TRIG 77U /*!< GPDMA1 HW Request is TIM5_TRIG */ -#define LL_GPDMA1_REQUEST_TIM15_CH1 78U /*!< GPDMA1 HW Request is TIM15_CH1 */ -#define LL_GPDMA1_REQUEST_TIM15_UP 79U /*!< GPDMA1 HW Request is TIM15_UP */ -#define LL_GPDMA1_REQUEST_TIM15_TRIG 80U /*!< GPDMA1 HW Request is TIM15_TRIG */ -#define LL_GPDMA1_REQUEST_TIM15_COM 81U /*!< GPDMA1 HW Request is TIM15_COM */ -#define LL_GPDMA1_REQUEST_TIM16_CH1 82U /*!< GPDMA1 HW Request is TIM16_CH1 */ -#define LL_GPDMA1_REQUEST_TIM16_UP 83U /*!< GPDMA1 HW Request is TIM16_UP */ -#define LL_GPDMA1_REQUEST_TIM17_CH1 84U /*!< GPDMA1 HW Request is TIM17_CH1 */ -#define LL_GPDMA1_REQUEST_TIM17_UP 85U /*!< GPDMA1 HW Request is TIM17_UP */ -#define LL_GPDMA1_REQUEST_DCMI_PSSI 86U /*!< GPDMA1 HW Request is DCMI_PSSI */ -#define LL_GPDMA1_REQUEST_AES_IN 87U /*!< GPDMA1 HW Request is AES_IN */ -#define LL_GPDMA1_REQUEST_AES_OUT 88U /*!< GPDMA1 HW Request is AES_OUT */ -#define LL_GPDMA1_REQUEST_HASH_IN 89U /*!< GPDMA1 HW Request is HASH_IN */ +#define LL_GPDMA1_REQUEST_TIM1_CH1 42U /*!< GPDMA1 HW Request is TIM1_CH1 */ +#define LL_GPDMA1_REQUEST_TIM1_CH2 43U /*!< GPDMA1 HW Request is TIM1_CH2 */ +#define LL_GPDMA1_REQUEST_TIM1_CH3 44U /*!< GPDMA1 HW Request is TIM1_CH3 */ +#define LL_GPDMA1_REQUEST_TIM1_CH4 45U /*!< GPDMA1 HW Request is TIM1_CH4 */ +#define LL_GPDMA1_REQUEST_TIM1_UP 46U /*!< GPDMA1 HW Request is TIM1_UP */ +#define LL_GPDMA1_REQUEST_TIM1_TRIG 47U /*!< GPDMA1 HW Request is TIM1_TRIG */ +#define LL_GPDMA1_REQUEST_TIM1_COM 48U /*!< GPDMA1 HW Request is TIM1_COM */ +#define LL_GPDMA1_REQUEST_TIM8_CH1 49U /*!< GPDMA1 HW Request is TIM8_CH1 */ +#define LL_GPDMA1_REQUEST_TIM8_CH2 50U /*!< GPDMA1 HW Request is TIM8_CH2 */ +#define LL_GPDMA1_REQUEST_TIM8_CH3 51U /*!< GPDMA1 HW Request is TIM8_CH3 */ +#define LL_GPDMA1_REQUEST_TIM8_CH4 52U /*!< GPDMA1 HW Request is TIM8_CH4 */ +#define LL_GPDMA1_REQUEST_TIM8_UP 53U /*!< GPDMA1 HW Request is TIM8_UP */ +#define LL_GPDMA1_REQUEST_TIM8_TRIG 54U /*!< GPDMA1 HW Request is TIM8_TRIG */ +#define LL_GPDMA1_REQUEST_TIM8_COM 55U /*!< GPDMA1 HW Request is TIM8_COM */ +#define LL_GPDMA1_REQUEST_TIM2_CH1 56U /*!< GPDMA1 HW Request is TIM2_CH1 */ +#define LL_GPDMA1_REQUEST_TIM2_CH2 57U /*!< GPDMA1 HW Request is TIM2_CH2 */ +#define LL_GPDMA1_REQUEST_TIM2_CH3 58U /*!< GPDMA1 HW Request is TIM2_CH3 */ +#define LL_GPDMA1_REQUEST_TIM2_CH4 59U /*!< GPDMA1 HW Request is TIM2_CH4 */ +#define LL_GPDMA1_REQUEST_TIM2_UP 60U /*!< GPDMA1 HW Request is TIM2_UP */ +#define LL_GPDMA1_REQUEST_TIM3_CH1 61U /*!< GPDMA1 HW Request is TIM3_CH1 */ +#define LL_GPDMA1_REQUEST_TIM3_CH2 62U /*!< GPDMA1 HW Request is TIM3_CH2 */ +#define LL_GPDMA1_REQUEST_TIM3_CH3 63U /*!< GPDMA1 HW Request is TIM3_CH3 */ +#define LL_GPDMA1_REQUEST_TIM3_CH4 64U /*!< GPDMA1 HW Request is TIM3_CH4 */ +#define LL_GPDMA1_REQUEST_TIM3_UP 65U /*!< GPDMA1 HW Request is TIM3_UP */ +#define LL_GPDMA1_REQUEST_TIM3_TRIG 66U /*!< GPDMA1 HW Request is TIM3_TRIG */ +#define LL_GPDMA1_REQUEST_TIM4_CH1 67U /*!< GPDMA1 HW Request is TIM4_CH1 */ +#define LL_GPDMA1_REQUEST_TIM4_CH2 68U /*!< GPDMA1 HW Request is TIM4_CH2 */ +#define LL_GPDMA1_REQUEST_TIM4_CH3 69U /*!< GPDMA1 HW Request is TIM4_CH3 */ +#define LL_GPDMA1_REQUEST_TIM4_CH4 70U /*!< GPDMA1 HW Request is TIM4_CH4 */ +#define LL_GPDMA1_REQUEST_TIM4_UP 71U /*!< GPDMA1 HW Request is TIM4_UP */ +#define LL_GPDMA1_REQUEST_TIM5_CH1 72U /*!< GPDMA1 HW Request is TIM5_CH1 */ +#define LL_GPDMA1_REQUEST_TIM5_CH2 73U /*!< GPDMA1 HW Request is TIM5_CH2 */ +#define LL_GPDMA1_REQUEST_TIM5_CH3 74U /*!< GPDMA1 HW Request is TIM5_CH3 */ +#define LL_GPDMA1_REQUEST_TIM5_CH4 75U /*!< GPDMA1 HW Request is TIM5_CH4 */ +#define LL_GPDMA1_REQUEST_TIM5_UP 76U /*!< GPDMA1 HW Request is TIM5_UP */ +#define LL_GPDMA1_REQUEST_TIM5_TRIG 77U /*!< GPDMA1 HW Request is TIM5_TRIG */ +#define LL_GPDMA1_REQUEST_TIM15_CH1 78U /*!< GPDMA1 HW Request is TIM15_CH1 */ +#define LL_GPDMA1_REQUEST_TIM15_UP 79U /*!< GPDMA1 HW Request is TIM15_UP */ +#define LL_GPDMA1_REQUEST_TIM15_TRIG 80U /*!< GPDMA1 HW Request is TIM15_TRIG */ +#define LL_GPDMA1_REQUEST_TIM15_COM 81U /*!< GPDMA1 HW Request is TIM15_COM */ +#define LL_GPDMA1_REQUEST_TIM16_CH1 82U /*!< GPDMA1 HW Request is TIM16_CH1 */ +#define LL_GPDMA1_REQUEST_TIM16_UP 83U /*!< GPDMA1 HW Request is TIM16_UP */ +#define LL_GPDMA1_REQUEST_TIM17_CH1 84U /*!< GPDMA1 HW Request is TIM17_CH1 */ +#define LL_GPDMA1_REQUEST_TIM17_UP 85U /*!< GPDMA1 HW Request is TIM17_UP */ +#define LL_GPDMA1_REQUEST_DCMI_PSSI 86U /*!< GPDMA1 HW Request is DCMI_PSSI */ +#define LL_GPDMA1_REQUEST_AES_IN 87U /*!< GPDMA1 HW Request is AES_IN */ +#define LL_GPDMA1_REQUEST_AES_OUT 88U /*!< GPDMA1 HW Request is AES_OUT */ +#define LL_GPDMA1_REQUEST_HASH_IN 89U /*!< GPDMA1 HW Request is HASH_IN */ #if defined(UCPD1) -#define LL_GPDMA1_REQUEST_UCPD1_TX 90U /*!< GPDMA1 HW Request is UCPD1_TX */ -#define LL_GPDMA1_REQUEST_UCPD1_RX 91U /*!< GPDMA1 HW Request is UCPD1_RX */ +#define LL_GPDMA1_REQUEST_UCPD1_TX 90U /*!< GPDMA1 HW Request is UCPD1_TX */ +#define LL_GPDMA1_REQUEST_UCPD1_RX 91U /*!< GPDMA1 HW Request is UCPD1_RX */ #endif /* UCPD1 */ -#define LL_GPDMA1_REQUEST_MDF1_FLT0 92U /*!< GPDMA1 HW Request is MDF1_FLT0 */ -#define LL_GPDMA1_REQUEST_MDF1_FLT1 93U /*!< GPDMA1 HW Request is MDF1_FLT1 */ -#define LL_GPDMA1_REQUEST_MDF1_FLT2 94U /*!< GPDMA1 HW Request is MDF1_FLT2 */ -#define LL_GPDMA1_REQUEST_MDF1_FLT3 95U /*!< GPDMA1 HW Request is MDF1_FLT3 */ -#define LL_GPDMA1_REQUEST_MDF1_FLT4 96U /*!< GPDMA1 HW Request is MDF1_FLT4 */ -#define LL_GPDMA1_REQUEST_MDF1_FLT5 97U /*!< GPDMA1 HW Request is MDF1_FLT5 */ -#define LL_GPDMA1_REQUEST_ADF1_FLT0 98U /*!< GPDMA1 HW Request is ADF1_FLT0 */ -#define LL_GPDMA1_REQUEST_FMAC_READ 99U /*!< GPDMA1 HW Request is FMAC_READ */ -#define LL_GPDMA1_REQUEST_FMAC_WRITE 100U /*!< GPDMA1 HW Request is FMAC_WRITE */ -#define LL_GPDMA1_REQUEST_CORDIC_READ 101U /*!< GPDMA1 HW Request is CORDIC_READ */ -#define LL_GPDMA1_REQUEST_CORDIC_WRITE 102U /*!< GPDMA1 HW Request is CORDIC_WRITE */ -#define LL_GPDMA1_REQUEST_SAES_IN 103U /*!< GPDMA1 HW Request is SAES_IN */ -#define LL_GPDMA1_REQUEST_SAES_OUT 104U /*!< GPDMA1 HW Request is SAES_OUT */ -#define LL_GPDMA1_REQUEST_LPTIM1_IC1 105U /*!< GPDMA1 HW Request is LPTIM1_IC1 */ -#define LL_GPDMA1_REQUEST_LPTIM1_IC2 106U /*!< GPDMA1 HW Request is LPTIM1_IC2 */ -#define LL_GPDMA1_REQUEST_LPTIM1_UE 107U /*!< GPDMA1 HW Request is LPTIM1_UE */ -#define LL_GPDMA1_REQUEST_LPTIM2_IC1 108U /*!< GPDMA1 HW Request is LPTIM2_IC1 */ -#define LL_GPDMA1_REQUEST_LPTIM2_IC2 109U /*!< GPDMA1 HW Request is LPTIM2_IC2 */ -#define LL_GPDMA1_REQUEST_LPTIM2_UE 110U /*!< GPDMA1 HW Request is LPTIM2_UE */ -#define LL_GPDMA1_REQUEST_LPTIM3_IC1 111U /*!< GPDMA1 HW Request is LPTIM3_IC1 */ -#define LL_GPDMA1_REQUEST_LPTIM3_IC2 112U /*!< GPDMA1 HW Request is LPTIM3_IC2 */ -#define LL_GPDMA1_REQUEST_LPTIM3_UE 113U /*!< GPDMA1 HW Request is LPTIM3_UE */ +#define LL_GPDMA1_REQUEST_MDF1_FLT0 92U /*!< GPDMA1 HW Request is MDF1_FLT0 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT1 93U /*!< GPDMA1 HW Request is MDF1_FLT1 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT2 94U /*!< GPDMA1 HW Request is MDF1_FLT2 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT3 95U /*!< GPDMA1 HW Request is MDF1_FLT3 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT4 96U /*!< GPDMA1 HW Request is MDF1_FLT4 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT5 97U /*!< GPDMA1 HW Request is MDF1_FLT5 */ +#define LL_GPDMA1_REQUEST_ADF1_FLT0 98U /*!< GPDMA1 HW Request is ADF1_FLT0 */ +#define LL_GPDMA1_REQUEST_FMAC_READ 99U /*!< GPDMA1 HW Request is FMAC_READ */ +#define LL_GPDMA1_REQUEST_FMAC_WRITE 100U /*!< GPDMA1 HW Request is FMAC_WRITE */ +#define LL_GPDMA1_REQUEST_CORDIC_READ 101U /*!< GPDMA1 HW Request is CORDIC_READ */ +#define LL_GPDMA1_REQUEST_CORDIC_WRITE 102U /*!< GPDMA1 HW Request is CORDIC_WRITE */ +#define LL_GPDMA1_REQUEST_SAES_IN 103U /*!< GPDMA1 HW Request is SAES_IN */ +#define LL_GPDMA1_REQUEST_SAES_OUT 104U /*!< GPDMA1 HW Request is SAES_OUT */ +#define LL_GPDMA1_REQUEST_LPTIM1_IC1 105U /*!< GPDMA1 HW Request is LPTIM1_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM1_IC2 106U /*!< GPDMA1 HW Request is LPTIM1_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM1_UE 107U /*!< GPDMA1 HW Request is LPTIM1_UE */ +#define LL_GPDMA1_REQUEST_LPTIM2_IC1 108U /*!< GPDMA1 HW Request is LPTIM2_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM2_IC2 109U /*!< GPDMA1 HW Request is LPTIM2_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM2_UE 110U /*!< GPDMA1 HW Request is LPTIM2_UE */ +#define LL_GPDMA1_REQUEST_LPTIM3_IC1 111U /*!< GPDMA1 HW Request is LPTIM3_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM3_IC2 112U /*!< GPDMA1 HW Request is LPTIM3_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM3_UE 113U /*!< GPDMA1 HW Request is LPTIM3_UE */ #if defined (HSPI1_BASE) -#define LL_GPDMA1_REQUEST_HSPI1 114U /*!< GPDMA1 HW request is HSPI1 */ -#endif /* defined (HSPI1_BASE) */ +#define LL_GPDMA1_REQUEST_HSPI1 114U /*!< GPDMA1 HW request is HSPI1 */ +#endif /* HSPI1_BASE */ #if defined (I2C5) -#define LL_GPDMA1_REQUEST_I2C5_RX 115U /*!< GPDMA1 HW request is I2C5_RX */ -#define LL_GPDMA1_REQUEST_I2C5_TX 116U /*!< GPDMA1 HW request is I2C5_TX */ -#define LL_GPDMA1_REQUEST_I2C5_EVC 117U /*!< GPDMA1 HW request is I2C5_EVC */ -#endif /* defined (I2C5) */ +#define LL_GPDMA1_REQUEST_I2C5_RX 115U /*!< GPDMA1 HW request is I2C5_RX */ +#define LL_GPDMA1_REQUEST_I2C5_TX 116U /*!< GPDMA1 HW request is I2C5_TX */ +#define LL_GPDMA1_REQUEST_I2C5_EVC 117U /*!< GPDMA1 HW request is I2C5_EVC */ +#endif /* I2C5 */ #if defined (I2C6) -#define LL_GPDMA1_REQUEST_I2C6_RX 118U /*!< GPDMA1 HW request is I2C6_RX */ -#define LL_GPDMA1_REQUEST_I2C6_TX 119U /*!< GPDMA1 HW request is I2C6_TX */ -#define LL_GPDMA1_REQUEST_I2C6_EVC 120U /*!< GPDMA1 HW request is I2C6_EVC */ -#endif /* defined (I2C6) */ +#define LL_GPDMA1_REQUEST_I2C6_RX 118U /*!< GPDMA1 HW request is I2C6_RX */ +#define LL_GPDMA1_REQUEST_I2C6_TX 119U /*!< GPDMA1 HW request is I2C6_TX */ +#define LL_GPDMA1_REQUEST_I2C6_EVC 120U /*!< GPDMA1 HW request is I2C6_EVC */ +#endif /* I2C6 */ #if defined (USART6) -#define LL_GPDMA1_REQUEST_USART6_RX 121U /*!< GPDMA1 HW request is USART6_RX */ -#define LL_GPDMA1_REQUEST_USART6_TX 122U /*!< GPDMA1 HW request is USART6_TX */ -#endif /* defined (USART6) */ +#define LL_GPDMA1_REQUEST_USART6_RX 121U /*!< GPDMA1 HW request is USART6_RX */ +#define LL_GPDMA1_REQUEST_USART6_TX 122U /*!< GPDMA1 HW request is USART6_TX */ +#endif /* USART6 */ #if defined (ADC2) -#define LL_GPDMA1_REQUEST_ADC2 123U /*!< GPDMA1 HW request is ADC2 */ -#endif /* defined (ADC2) */ +#define LL_GPDMA1_REQUEST_ADC2 123U /*!< GPDMA1 HW request is ADC2 */ +#endif /* ADC2 */ #if defined (JPEG) -#define LL_GPDMA1_REQUEST_JPEG_RX 124U /*!< GPDMA1 HW request is JPEG_TX */ -#define LL_GPDMA1_REQUEST_JPEG_TX 125U /*!< GPDMA1 HW request is JPEG_RX */ -#endif /* defined (JPEG) */ +#define LL_GPDMA1_REQUEST_JPEG_RX 124U /*!< GPDMA1 HW request is JPEG_TX */ +#define LL_GPDMA1_REQUEST_JPEG_TX 125U /*!< GPDMA1 HW request is JPEG_RX */ +#endif /* JPEG */ /* GPDMA1 Hardware Requests aliases */ -#define LL_GPDMA1_REQUEST_DCMI LL_GPDMA1_REQUEST_DCMI_PSSI +#define LL_GPDMA1_REQUEST_DCMI LL_GPDMA1_REQUEST_DCMI_PSSI /* LPDMA1 Hardware Requests */ -#define LL_LPDMA1_REQUEST_LPUART1_RX 0U /*!< LPDMA1 HW Request is LPUART1_RX */ -#define LL_LPDMA1_REQUEST_LPUART1_TX 1U /*!< LPDMA1 HW Request is LPUART1_TX */ -#define LL_LPDMA1_REQUEST_SPI3_RX 2U /*!< LPDMA1 HW Request is SPI3_RX */ -#define LL_LPDMA1_REQUEST_SPI3_TX 3U /*!< LPDMA1 HW Request is SPI3_TX */ -#define LL_LPDMA1_REQUEST_I2C3_RX 4U /*!< LPDMA1 HW Request is I2C3_RX */ -#define LL_LPDMA1_REQUEST_I2C3_TX 5U /*!< LPDMA1 HW Request is I2C3_TX */ -#define LL_LPDMA1_REQUEST_I2C3_EVC 6U /*!< LPDMA1 HW Request is I2C3_EVC */ -#define LL_LPDMA1_REQUEST_ADC4 7U /*!< LPDMA1 HW Request is ADC4 */ -#define LL_LPDMA1_REQUEST_DAC1_CH1 8U /*!< LPDMA1 HW Request is DAC1_CH1 */ -#define LL_LPDMA1_REQUEST_DAC1_CH2 9U /*!< LPDMA1 HW Request is DAC1_CH2 */ -#define LL_LPDMA1_REQUEST_ADF1_FLT0 10U /*!< LPDMA1 HW Request is ADF1_FLT0 */ -#define LL_LPDMA1_REQUEST_LPTIM1_IC1 11U /*!< LPDMA1 HW Request is LPTIM1_IC1 */ -#define LL_LPDMA1_REQUEST_LPTIM1_IC2 12U /*!< LPDMA1 HW Request is LPTIM1_IC2 */ -#define LL_LPDMA1_REQUEST_LPTIM1_UE 13U /*!< LPDMA1 HW Request is LPTIM1_UE */ -#define LL_LPDMA1_REQUEST_LPTIM3_IC1 14U /*!< LPDMA1 HW Request is LPTIM3_IC1 */ -#define LL_LPDMA1_REQUEST_LPTIM3_IC2 15U /*!< LPDMA1 HW Request is LPTIM3_IC2 */ -#define LL_LPDMA1_REQUEST_LPTIM3_UE 16U /*!< LPDMA1 HW Request is LPTIM3_UE */ +#define LL_LPDMA1_REQUEST_LPUART1_RX 0U /*!< LPDMA1 HW Request is LPUART1_RX */ +#define LL_LPDMA1_REQUEST_LPUART1_TX 1U /*!< LPDMA1 HW Request is LPUART1_TX */ +#define LL_LPDMA1_REQUEST_SPI3_RX 2U /*!< LPDMA1 HW Request is SPI3_RX */ +#define LL_LPDMA1_REQUEST_SPI3_TX 3U /*!< LPDMA1 HW Request is SPI3_TX */ +#define LL_LPDMA1_REQUEST_I2C3_RX 4U /*!< LPDMA1 HW Request is I2C3_RX */ +#define LL_LPDMA1_REQUEST_I2C3_TX 5U /*!< LPDMA1 HW Request is I2C3_TX */ +#define LL_LPDMA1_REQUEST_I2C3_EVC 6U /*!< LPDMA1 HW Request is I2C3_EVC */ +#define LL_LPDMA1_REQUEST_ADC4 7U /*!< LPDMA1 HW Request is ADC4 */ +#define LL_LPDMA1_REQUEST_DAC1_CH1 8U /*!< LPDMA1 HW Request is DAC1_CH1 */ +#define LL_LPDMA1_REQUEST_DAC1_CH2 9U /*!< LPDMA1 HW Request is DAC1_CH2 */ +#define LL_LPDMA1_REQUEST_ADF1_FLT0 10U /*!< LPDMA1 HW Request is ADF1_FLT0 */ +#define LL_LPDMA1_REQUEST_LPTIM1_IC1 11U /*!< LPDMA1 HW Request is LPTIM1_IC1 */ +#define LL_LPDMA1_REQUEST_LPTIM1_IC2 12U /*!< LPDMA1 HW Request is LPTIM1_IC2 */ +#define LL_LPDMA1_REQUEST_LPTIM1_UE 13U /*!< LPDMA1 HW Request is LPTIM1_UE */ +#define LL_LPDMA1_REQUEST_LPTIM3_IC1 14U /*!< LPDMA1 HW Request is LPTIM3_IC1 */ +#define LL_LPDMA1_REQUEST_LPTIM3_IC2 15U /*!< LPDMA1 HW Request is LPTIM3_IC2 */ +#define LL_LPDMA1_REQUEST_LPTIM3_UE 16U /*!< LPDMA1 HW Request is LPTIM3_UE */ /** * @} */ @@ -1138,129 +1138,129 @@ typedef struct * @{ */ /* GPDMA1 Hardware Triggers */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger is EXTI_LINE0 */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger is EXTI_LINE1 */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger is EXTI_LINE2 */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger is EXTI_LINE3 */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger is EXTI_LINE4 */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger is EXTI_LINE5 */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger is EXTI_LINE6 */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger is EXTI_LINE7 */ -#define LL_GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger is TAMP_TRG1 */ -#define LL_GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger is TAMP_TRG2 */ -#define LL_GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger is TAMP_TRG3 */ -#define LL_GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger is LPTIM1_CH1 */ -#define LL_GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger is LPTIM1_CH2 */ -#define LL_GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger is LPTIM2_CH1 */ -#define LL_GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger is LPTIM2_CH2 */ -#define LL_GPDMA1_TRIGGER_LPTIM4_OUT 15U /*!< GPDMA1 HW Trigger is LPTIM4_OUT */ -#define LL_GPDMA1_TRIGGER_COMP1_OUT 16U /*!< GPDMA1 HW Trigger is COMP1_OUT */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger is EXTI_LINE0 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger is EXTI_LINE1 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger is EXTI_LINE2 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger is EXTI_LINE3 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger is EXTI_LINE4 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger is EXTI_LINE5 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger is EXTI_LINE6 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger is EXTI_LINE7 */ +#define LL_GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger is TAMP_TRG1 */ +#define LL_GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger is TAMP_TRG2 */ +#define LL_GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger is TAMP_TRG3 */ +#define LL_GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger is LPTIM1_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger is LPTIM1_CH2 */ +#define LL_GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger is LPTIM2_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger is LPTIM2_CH2 */ +#define LL_GPDMA1_TRIGGER_LPTIM4_OUT 15U /*!< GPDMA1 HW Trigger is LPTIM4_OUT */ +#define LL_GPDMA1_TRIGGER_COMP1_OUT 16U /*!< GPDMA1 HW Trigger is COMP1_OUT */ #if defined(COMP2) -#define LL_GPDMA1_TRIGGER_COMP2_OUT 17U /*!< GPDMA1 HW Trigger is COMP2_OUT */ +#define LL_GPDMA1_TRIGGER_COMP2_OUT 17U /*!< GPDMA1 HW Trigger is COMP2_OUT */ #endif /* COMP2 */ -#define LL_GPDMA1_TRIGGER_RTC_ALRA_TRG 18U /*!< GPDMA1 HW Trigger is RTC_ALRA_TRG */ -#define LL_GPDMA1_TRIGGER_RTC_ALRB_TRG 19U /*!< GPDMA1 HW Trigger is RTC_ALRB_TRG */ -#define LL_GPDMA1_TRIGGER_RTC_WUT_TRG 20U /*!< GPDMA1 HW Trigger is RTC_WUT_TRG */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< GPDMA1 HW Trigger is GPDMA1_CH0_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< GPDMA1 HW Trigger is GPDMA1_CH1_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 24U /*!< GPDMA1 HW Trigger is GPDMA1_CH2_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 25U /*!< GPDMA1 HW Trigger is GPDMA1_CH3_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 26U /*!< GPDMA1 HW Trigger is GPDMA1_CH4_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 27U /*!< GPDMA1 HW Trigger is GPDMA1_CH5_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 28U /*!< GPDMA1 HW Trigger is GPDMA1_CH6_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 29U /*!< GPDMA1 HW Trigger is GPDMA1_CH7_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF 30U /*!< GPDMA1 HW Trigger is GPDMA1_CH8_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF 31U /*!< GPDMA1 HW Trigger is GPDMA1_CH9_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF 32U /*!< GPDMA1 HW Trigger is GPDMA1_CH10_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF 33U /*!< GPDMA1 HW Trigger is GPDMA1_CH11_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF 34U /*!< GPDMA1 HW Trigger is GPDMA1_CH12_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF 35U /*!< GPDMA1 HW Trigger is GPDMA1_CH13_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF 36U /*!< GPDMA1 HW Trigger is GPDMA1_CH14_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF 37U /*!< GPDMA1 HW Trigger is GPDMA1_CH15_TCF */ -#define LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF 38U /*!< GPDMA1 HW Trigger is LPDMA1_CH0_TCF */ -#define LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF 39U /*!< GPDMA1 HW Trigger is LPDMA1_CH1_TCF */ -#define LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF 40U /*!< GPDMA1 HW Trigger is LPDMA1_CH2_TCF */ -#define LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF 41U /*!< GPDMA1 HW Trigger is LPDMA1_CH3_TCF */ -#define LL_GPDMA1_TRIGGER_TIM2_TRGO 42U /*!< GPDMA1 HW Trigger is TIM2_TRGO */ -#define LL_GPDMA1_TRIGGER_TIM15_TRGO 43U /*!< GPDMA1 HW Trigger is TIM15_TRGO */ -#define LL_GPDMA1_TRIGGER_ADC4_AWD1 57U /*!< GPDMA1 HW Trigger is ADC4_AWD1 */ -#define LL_GPDMA1_TRIGGER_ADC1_AWD1 58U /*!< GPDMA1 HW Trigger is ADC1_AWD1 */ +#define LL_GPDMA1_TRIGGER_RTC_ALRA_TRG 18U /*!< GPDMA1 HW Trigger is RTC_ALRA_TRG */ +#define LL_GPDMA1_TRIGGER_RTC_ALRB_TRG 19U /*!< GPDMA1 HW Trigger is RTC_ALRB_TRG */ +#define LL_GPDMA1_TRIGGER_RTC_WUT_TRG 20U /*!< GPDMA1 HW Trigger is RTC_WUT_TRG */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< GPDMA1 HW Trigger is GPDMA1_CH0_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< GPDMA1 HW Trigger is GPDMA1_CH1_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 24U /*!< GPDMA1 HW Trigger is GPDMA1_CH2_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 25U /*!< GPDMA1 HW Trigger is GPDMA1_CH3_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 26U /*!< GPDMA1 HW Trigger is GPDMA1_CH4_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 27U /*!< GPDMA1 HW Trigger is GPDMA1_CH5_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 28U /*!< GPDMA1 HW Trigger is GPDMA1_CH6_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 29U /*!< GPDMA1 HW Trigger is GPDMA1_CH7_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF 30U /*!< GPDMA1 HW Trigger is GPDMA1_CH8_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF 31U /*!< GPDMA1 HW Trigger is GPDMA1_CH9_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF 32U /*!< GPDMA1 HW Trigger is GPDMA1_CH10_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF 33U /*!< GPDMA1 HW Trigger is GPDMA1_CH11_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF 34U /*!< GPDMA1 HW Trigger is GPDMA1_CH12_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF 35U /*!< GPDMA1 HW Trigger is GPDMA1_CH13_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF 36U /*!< GPDMA1 HW Trigger is GPDMA1_CH14_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF 37U /*!< GPDMA1 HW Trigger is GPDMA1_CH15_TCF */ +#define LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF 38U /*!< GPDMA1 HW Trigger is LPDMA1_CH0_TCF */ +#define LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF 39U /*!< GPDMA1 HW Trigger is LPDMA1_CH1_TCF */ +#define LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF 40U /*!< GPDMA1 HW Trigger is LPDMA1_CH2_TCF */ +#define LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF 41U /*!< GPDMA1 HW Trigger is LPDMA1_CH3_TCF */ +#define LL_GPDMA1_TRIGGER_TIM2_TRGO 42U /*!< GPDMA1 HW Trigger is TIM2_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM15_TRGO 43U /*!< GPDMA1 HW Trigger is TIM15_TRGO */ +#define LL_GPDMA1_TRIGGER_ADC4_AWD1 57U /*!< GPDMA1 HW Trigger is ADC4_AWD1 */ +#define LL_GPDMA1_TRIGGER_ADC1_AWD1 58U /*!< GPDMA1 HW Trigger is ADC1_AWD1 */ #if defined (TIM3_TRGO_TRIGGER_SUPPORT) -#define LL_GPDMA1_TRIGGER_TIM3_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ -#endif /* defined (TIM3_TRGO_TRIGGER_SUPPORT) */ +#define LL_GPDMA1_TRIGGER_TIM3_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ +#endif /* TIM3_TRGO_TRIGGER_SUPPORT */ #if defined (TIM4_TRGO_TRIGGER_SUPPORT) -#define LL_GPDMA1_TRIGGER_TIM4_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ -#endif /* defined (TIM4_TRGO_TRIGGER_SUPPORT) */ +#define LL_GPDMA1_TRIGGER_TIM4_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ +#endif /* TIM4_TRGO_TRIGGER_SUPPORT */ #if defined (TIM5_TRGO_TRIGGER_SUPPORT) -#define LL_GPDMA1_TRIGGER_TIM5_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ -#endif /* defined (TIM5_TRGO_TRIGGER_SUPPORT) */ +#define LL_GPDMA1_TRIGGER_TIM5_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ +#endif /* TIM5_TRGO_TRIGGER_SUPPORT */ #if defined (LTDC) -#define LL_GPDMA1_TRIGGER_LTDC_LI 47U /*!< GPDMA1 HW Trigger signal is LTDC_LI */ -#endif /* defined (LTDC) */ +#define LL_GPDMA1_TRIGGER_LTDC_LI 47U /*!< GPDMA1 HW Trigger signal is LTDC_LI */ +#endif /* LTDC */ #if defined (DSI) -#define LL_GPDMA1_TRIGGER_DSI_TE 48U /*!< GPDMA1 HW Trigger signal is DSI_TE */ -#define LL_GPDMA1_TRIGGER_DSI_ER 49U /*!< GPDMA1 HW Trigger signal is DSI_ER */ -#endif /* defined (DSI) */ +#define LL_GPDMA1_TRIGGER_DSI_TE 48U /*!< GPDMA1 HW Trigger signal is DSI_TE */ +#define LL_GPDMA1_TRIGGER_DSI_ER 49U /*!< GPDMA1 HW Trigger signal is DSI_ER */ +#endif /* DSI */ #if defined (DMA2D) -#define LL_GPDMA1_TRIGGER_DMA2D_TC 50U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ -#define LL_GPDMA1_TRIGGER_DMA2D_CTC 51U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ -#define LL_GPDMA1_TRIGGER_DMA2D_TW 52U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ -#endif /* defined (DMA2D) */ +#define LL_GPDMA1_TRIGGER_DMA2D_TC 50U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ +#define LL_GPDMA1_TRIGGER_DMA2D_CTC 51U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ +#define LL_GPDMA1_TRIGGER_DMA2D_TW 52U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ +#endif /* DMA2D */ #if defined (GPU2D) -#define LL_GPDMA1_TRIGGER_GPU2D_FLAG0 53U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */ -#define LL_GPDMA1_TRIGGER_GPU2D_FLAG1 54U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */ -#define LL_GPDMA1_TRIGGER_GPU2D_FLAG2 55U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */ -#define LL_GPDMA1_TRIGGER_GPU2D_FLAG3 56U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */ -#endif /* defined (GPU2D) */ +#define LL_GPDMA1_TRIGGER_GPU2D_FLAG0 53U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */ +#define LL_GPDMA1_TRIGGER_GPU2D_FLAG1 54U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */ +#define LL_GPDMA1_TRIGGER_GPU2D_FLAG2 55U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */ +#define LL_GPDMA1_TRIGGER_GPU2D_FLAG3 56U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */ +#endif /* GPU2D */ #if defined (GFXTIM) -#define LL_GPDMA1_TRIGGER_GFXTIM_EVT3 59U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT3 */ -#define LL_GPDMA1_TRIGGER_GFXTIM_EVT2 60U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT2 */ -#define LL_GPDMA1_TRIGGER_GFXTIM_EVT1 61U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT1 */ -#define LL_GPDMA1_TRIGGER_GFXTIM_EVT0 62U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT0 */ -#endif /* defined (GFXTIM) */ +#define LL_GPDMA1_TRIGGER_GFXTIM_EVT3 59U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT3 */ +#define LL_GPDMA1_TRIGGER_GFXTIM_EVT2 60U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT2 */ +#define LL_GPDMA1_TRIGGER_GFXTIM_EVT1 61U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT1 */ +#define LL_GPDMA1_TRIGGER_GFXTIM_EVT0 62U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT0 */ +#endif /* GFXTIM */ #if defined (JPEG) -#define LL_GPDMA1_TRIGGER_JPEG_EOC 63U /*!< GPDMA1 HW Trigger signal is JPEG_EOC */ -#define LL_GPDMA1_TRIGGER_JPEG_IFNF 64U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */ -#define LL_GPDMA1_TRIGGER_JPEG_IFT 65U /*!< GPDMA1 HW Trigger signal is JPEG_IFT */ -#define LL_GPDMA1_TRIGGER_JPEG_OFNE 66U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */ -#define LL_GPDMA1_TRIGGER_JPEG_OFT 67U /*!< GPDMA1 HW Trigger signal is JPEG_OFT */ -#endif /* defined (JPEG) */ +#define LL_GPDMA1_TRIGGER_JPEG_EOC 63U /*!< GPDMA1 HW Trigger signal is JPEG_EOC */ +#define LL_GPDMA1_TRIGGER_JPEG_IFNF 64U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */ +#define LL_GPDMA1_TRIGGER_JPEG_IFT 65U /*!< GPDMA1 HW Trigger signal is JPEG_IFT */ +#define LL_GPDMA1_TRIGGER_JPEG_OFNE 66U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */ +#define LL_GPDMA1_TRIGGER_JPEG_OFT 67U /*!< GPDMA1 HW Trigger signal is JPEG_OFT */ +#endif /* JPEG */ /* LPDMA1 triggers */ -#define LL_LPDMA1_TRIGGER_EXTI_LINE0 0U /*!< LPDMA1 HW Trigger is EXTI_LINE0 */ -#define LL_LPDMA1_TRIGGER_EXTI_LINE1 1U /*!< LPDMA1 HW Trigger is EXTI_LINE1 */ -#define LL_LPDMA1_TRIGGER_EXTI_LINE2 2U /*!< LPDMA1 HW Trigger is EXTI_LINE2 */ -#define LL_LPDMA1_TRIGGER_EXTI_LINE3 3U /*!< LPDMA1 HW Trigger is EXTI_LINE3 */ -#define LL_LPDMA1_TRIGGER_EXTI_LINE4 4U /*!< LPDMA1 HW Trigger is EXTI_LINE4 */ -#define LL_LPDMA1_TRIGGER_TAMP_TRG1 5U /*!< LPDMA1 HW Trigger is TAMP_TRG1 */ -#define LL_LPDMA1_TRIGGER_TAMP_TRG2 6U /*!< LPDMA1 HW Trigger is TAMP_TRG2 */ -#define LL_LPDMA1_TRIGGER_TAMP_TRG3 7U /*!< LPDMA1 HW Trigger is TAMP_TRG3 */ -#define LL_LPDMA1_TRIGGER_LPTIM1_CH1 8U /*!< LPDMA1 HW Trigger is LPTIM1_CH1 */ -#define LL_LPDMA1_TRIGGER_LPTIM1_CH2 9U /*!< LPDMA1 HW Trigger is LPTIM1_CH2 */ -#define LL_LPDMA1_TRIGGER_LPTIM3_CH1 10U /*!< LPDMA1 HW Trigger is LPTIM3_CH1 */ -#define LL_LPDMA1_TRIGGER_LPTIM4_OUT 11U /*!< LPDMA1 HW Trigger is LPTIM4_OUT */ -#define LL_LPDMA1_TRIGGER_COMP1_OUT 12U /*!< LPDMA1 HW Trigger is COMP1_OUT */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE0 0U /*!< LPDMA1 HW Trigger is EXTI_LINE0 */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE1 1U /*!< LPDMA1 HW Trigger is EXTI_LINE1 */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE2 2U /*!< LPDMA1 HW Trigger is EXTI_LINE2 */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE3 3U /*!< LPDMA1 HW Trigger is EXTI_LINE3 */ +#define LL_LPDMA1_TRIGGER_EXTI_LINE4 4U /*!< LPDMA1 HW Trigger is EXTI_LINE4 */ +#define LL_LPDMA1_TRIGGER_TAMP_TRG1 5U /*!< LPDMA1 HW Trigger is TAMP_TRG1 */ +#define LL_LPDMA1_TRIGGER_TAMP_TRG2 6U /*!< LPDMA1 HW Trigger is TAMP_TRG2 */ +#define LL_LPDMA1_TRIGGER_TAMP_TRG3 7U /*!< LPDMA1 HW Trigger is TAMP_TRG3 */ +#define LL_LPDMA1_TRIGGER_LPTIM1_CH1 8U /*!< LPDMA1 HW Trigger is LPTIM1_CH1 */ +#define LL_LPDMA1_TRIGGER_LPTIM1_CH2 9U /*!< LPDMA1 HW Trigger is LPTIM1_CH2 */ +#define LL_LPDMA1_TRIGGER_LPTIM3_CH1 10U /*!< LPDMA1 HW Trigger is LPTIM3_CH1 */ +#define LL_LPDMA1_TRIGGER_LPTIM4_OUT 11U /*!< LPDMA1 HW Trigger is LPTIM4_OUT */ +#define LL_LPDMA1_TRIGGER_COMP1_OUT 12U /*!< LPDMA1 HW Trigger is COMP1_OUT */ #if defined(COMP2) -#define LL_LPDMA1_TRIGGER_COMP2_OUT 13U /*!< LPDMA1 HW Trigger is COMP2_OUT */ +#define LL_LPDMA1_TRIGGER_COMP2_OUT 13U /*!< LPDMA1 HW Trigger is COMP2_OUT */ #endif /* COMP2 */ -#define LL_LPDMA1_TRIGGER_RTC_ALRA_TRG 14U /*!< LPDMA1 HW Trigger is RTC_ALRA_TRG */ -#define LL_LPDMA1_TRIGGER_RTC_ALRB_TRG 15U /*!< LPDMA1 HW Trigger is RTC_ALRB_TRG */ -#define LL_LPDMA1_TRIGGER_RTC_WUT_TRG 16U /*!< LPDMA1 HW Trigger is RTC_WUT_TRG */ -#define LL_LPDMA1_TRIGGER_ADC4_AWD1 17U /*!< LPDMA1 HW Trigger is ADC4_AWD1 */ -#define LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF 18U /*!< LPDMA1 HW Trigger is LPDMA1_CH0_TCF */ -#define LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF 19U /*!< LPDMA1 HW Trigger is LPDMA1_CH1_TCF */ -#define LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF 20U /*!< LPDMA1 HW Trigger is LPDMA1_CH2_TCF */ -#define LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF 21U /*!< LPDMA1 HW Trigger is LPDMA1_CH3_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< LPDMA1 HW Trigger is GPDMA1_CH0_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< LPDMA1 HW Trigger is GPDMA1_CH1_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< LPDMA1 HW Trigger is GPDMA1_CH4_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< LPDMA1 HW Trigger is GPDMA1_CH5_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< LPDMA1 HW Trigger is GPDMA1_CH6_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< LPDMA1 HW Trigger is GPDMA1_CH7_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF 28U /*!< LPDMA1 HW Trigger is GPDMA1_CH12_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF 29U /*!< LPDMA1 HW Trigger is GPDMA1_CH13_TCF */ -#define LL_LPDMA1_TRIGGER_TIM2_TRGO 30U /*!< LPDMA1 HW Trigger is TIM2_TRGO */ -#define LL_LPDMA1_TRIGGER_TIM15_TRGO 31U /*!< LPDMA1 HW Trigger is TIM15_TRGO */ +#define LL_LPDMA1_TRIGGER_RTC_ALRA_TRG 14U /*!< LPDMA1 HW Trigger is RTC_ALRA_TRG */ +#define LL_LPDMA1_TRIGGER_RTC_ALRB_TRG 15U /*!< LPDMA1 HW Trigger is RTC_ALRB_TRG */ +#define LL_LPDMA1_TRIGGER_RTC_WUT_TRG 16U /*!< LPDMA1 HW Trigger is RTC_WUT_TRG */ +#define LL_LPDMA1_TRIGGER_ADC4_AWD1 17U /*!< LPDMA1 HW Trigger is ADC4_AWD1 */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF 18U /*!< LPDMA1 HW Trigger is LPDMA1_CH0_TCF */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF 19U /*!< LPDMA1 HW Trigger is LPDMA1_CH1_TCF */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF 20U /*!< LPDMA1 HW Trigger is LPDMA1_CH2_TCF */ +#define LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF 21U /*!< LPDMA1 HW Trigger is LPDMA1_CH3_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< LPDMA1 HW Trigger is GPDMA1_CH0_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< LPDMA1 HW Trigger is GPDMA1_CH1_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< LPDMA1 HW Trigger is GPDMA1_CH4_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< LPDMA1 HW Trigger is GPDMA1_CH5_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< LPDMA1 HW Trigger is GPDMA1_CH6_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< LPDMA1 HW Trigger is GPDMA1_CH7_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF 28U /*!< LPDMA1 HW Trigger is GPDMA1_CH12_TCF */ +#define LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF 29U /*!< LPDMA1 HW Trigger is GPDMA1_CH13_TCF */ +#define LL_LPDMA1_TRIGGER_TIM2_TRGO 30U /*!< LPDMA1 HW Trigger is TIM2_TRGO */ +#define LL_LPDMA1_TRIGGER_TIM15_TRGO 31U /*!< LPDMA1 HW Trigger is TIM15_TRGO */ /** * @} */ @@ -2104,6 +2104,7 @@ __STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, ui uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC); } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief Check security attribute of the DMA transfer to the destination. @@ -2136,6 +2137,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DM == (DMA_CTR1_DSEC)) ? 1UL : 0UL); } +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** * @brief Enable security attribute of the DMA transfer from the source. * @note This API is used for all available DMA channels. @@ -2195,6 +2197,7 @@ __STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uin uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief Check security attribute of the DMA transfer from the source. @@ -2226,7 +2229,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMA return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC) == (DMA_CTR1_SSEC)) ? 1UL : 0UL); } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief Set destination allocated port. @@ -3051,8 +3053,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_ * @param Configuration This parameter must be a combination of all the following values: * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER - * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_HWREQUEST_BLK - * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_TRIG_POLARITY_RISING or + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_HWREQUEST_BLK + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or * @ref LL_DMA_TRIG_POLARITY_FALLING * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER @@ -4069,7 +4071,7 @@ __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint * @param BlkDataLength Block transfer length Value between 0 to 0x0000FFFF * @param BlkRptCount Block repeat counter - * Value between 0 to 0x00000EFF + * Value between 0 to 0x000007FF *@retval None. */ __STATIC_INLINE void LL_DMA_ConfigBlkCounters(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength, @@ -4261,7 +4263,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32 * @arg @ref LL_DMA_CHANNEL_14 * @arg @ref LL_DMA_CHANNEL_15 * @param BlkRptCount Block repeat counter - * Value between 0 to 0x00000EFF + * Value between 0 to 0x000007FF * @retval None. */ __STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount) @@ -4281,7 +4283,7 @@ __STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_13 * @arg @ref LL_DMA_CHANNEL_14 * @arg @ref LL_DMA_CHANNEL_15 - * @retval Between 0 to 0x00000EFF + * @retval Between 0 to 0x000007FF */ __STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel) { @@ -4753,7 +4755,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *D * @arg @ref LL_DMA_UPDATE_CTR3 (This value is allowed only for 2D addressing channels) * @arg @ref LL_DMA_UPDATE_CBR2 (This value is allowed only for 2D addressing channels) * @arg @ref LL_DMA_UPDATE_CLLR - * @param LinkedListAddrOffset Between 0 to 0x0000FFFC + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. * @retval None. */ __STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate, @@ -5443,7 +5445,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uin * @arg @ref LL_DMA_CHANNEL_13 * @arg @ref LL_DMA_CHANNEL_14 * @arg @ref LL_DMA_CHANNEL_15 - * @param LinkedListAddrOffset Between 0 to 0x0000FFFC + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. * @retval None. */ __STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel, @@ -5574,6 +5576,7 @@ __STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Cha { CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))); } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief Check if DMA channel secure is enabled. @@ -5604,7 +5607,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief Enable the DMA channel privilege attribute. @@ -5723,7 +5725,7 @@ __STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32 { SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))); } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief Check if DMA channel attributes are locked. @@ -6281,7 +6283,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint3 return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @} */ @@ -6952,7 +6954,7 @@ void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32 /** * @} */ -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* USE_FULL_LL_DRIVER */ /** * @} @@ -6962,7 +6964,7 @@ void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32 * @} */ -#endif /* (defined (GPDMA1) || defined (LPDMA1)) */ +#endif /* GPDMA1 || LPDMA1 */ /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma2d.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma2d.h index ef89e0600c..43ef4aa65b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma2d.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma2d.h @@ -940,8 +940,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(const DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor) { - MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \ - OutputColor); + WRITE_REG(DMA2Dx->OCOLR, OutputColor); } /** @@ -1448,7 +1447,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint * @arg @ref LL_DMA2D_CSS_422 * @arg @ref LL_DMA2D_CSS_420 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS)); } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_exti.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_exti.h index bbceea0dff..e021b83b45 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_exti.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_exti.h @@ -241,7 +241,6 @@ typedef struct */ - /* Exported functions --------------------------------------------------------*/ /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions * @{ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h index 489c304719..7df97093a7 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h @@ -38,6 +38,7 @@ extern "C" { /** @addtogroup FMC_LL_Private_Macros * @{ */ +#if defined(FMC_BANK1) #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ ((__BANK__) == FMC_NORSRAM_BANK2) || \ @@ -95,6 +96,8 @@ extern "C" { #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) #define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U)) +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ @@ -118,6 +121,7 @@ extern "C" { #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) +#endif /* FMC_BANK3 */ /** * @} @@ -129,14 +133,23 @@ extern "C" { * @{ */ +#if defined(FMC_BANK1) #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) #define FMC_NAND_TypeDef FMC_Bank3_TypeDef +#endif /* FMC_BANK3 */ +#if defined(FMC_BANK1) #define FMC_NORSRAM_DEVICE FMC_Bank1_R #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) #define FMC_NAND_DEVICE FMC_Bank3_R +#endif /* FMC_BANK3 */ +#if defined(FMC_BANK1) /** * @brief FMC NORSRAM Configuration Structure definition */ @@ -261,7 +274,9 @@ typedef struct uint32_t AccessMode; /*!< Specifies the asynchronous access mode. This parameter can be a value of @ref FMC_Access_Mode */ } FMC_NORSRAM_TimingTypeDef; +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) /** * @brief FMC NAND Configuration Structure definition */ @@ -290,7 +305,9 @@ typedef struct delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ } FMC_NAND_InitTypeDef; +#endif /* FMC_BANK3 */ +#if defined(FMC_BANK3) /** * @brief FMC NAND Timing parameters structure definition */ @@ -321,6 +338,7 @@ typedef struct on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ } FMC_NAND_PCC_TimingTypeDef; +#endif /* FMC_BANK3 */ /** @@ -331,6 +349,7 @@ typedef struct /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants * @{ */ +#if defined(FMC_BANK1) /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller * @{ @@ -515,7 +534,9 @@ typedef struct /** * @} */ +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller * @{ @@ -579,14 +600,17 @@ typedef struct /** * @} */ +#endif /* FMC_BANK3 */ /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition * @{ */ +#if defined(FMC_BANK3) #define FMC_IT_RISING_EDGE (0x00000008U) #define FMC_IT_LEVEL (0x00000010U) #define FMC_IT_FALLING_EDGE (0x00000020U) +#endif /* FMC_BANK3 */ /** * @} */ @@ -594,10 +618,12 @@ typedef struct /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition * @{ */ +#if defined(FMC_BANK3) #define FMC_FLAG_RISING_EDGE (0x00000001U) #define FMC_FLAG_LEVEL (0x00000002U) #define FMC_FLAG_FALLING_EDGE (0x00000004U) #define FMC_FLAG_FEMPT (0x00000040U) +#endif /* FMC_BANK3 */ /** * @} */ @@ -625,6 +651,7 @@ typedef struct * @retval None */ #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN) +#if defined(FMC_BANK1) /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros * @brief macros to handle NOR device enable/disable and read/write operations * @{ @@ -651,7 +678,9 @@ typedef struct /** * @} */ +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros * @brief macros to handle NAND device enable/disable * @{ @@ -675,7 +704,9 @@ typedef struct /** * @} */ +#endif /* FMC_BANK3 */ +#if defined(FMC_BANK3) /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt * @brief macros to handle NAND interrupts * @{ @@ -735,6 +766,7 @@ typedef struct /** * @} */ +#endif /* FMC_BANK3 */ /** @@ -750,6 +782,7 @@ typedef struct * @{ */ +#if defined(FMC_BANK1) /** @defgroup FMC_LL_NORSRAM NOR SRAM * @{ */ @@ -780,7 +813,9 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic /** * @} */ +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) /** @defgroup FMC_LL_NAND NAND * @{ */ @@ -810,6 +845,7 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u /** * @} */ +#endif /* FMC_BANK3 */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_gpio.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_gpio.h index 65e5f608f1..730888c301 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_gpio.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_gpio.h @@ -282,7 +282,8 @@ typedef struct */ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) { - MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)), + (Mode << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))); } /** @@ -316,8 +317,8 @@ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 */ __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->MODER, - (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); + return (uint32_t)(READ_BIT(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))) >> + (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)); } /** @@ -422,8 +423,8 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uin */ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) { - MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)), - (Speed << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)), + (Speed << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))); } /** @@ -459,8 +460,9 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint */ __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, - (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << \ + (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))) >> \ + (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)); } /** @@ -493,7 +495,8 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t */ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) { - MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)), + (Pull << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))); } /** @@ -525,8 +528,9 @@ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 */ __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->PUPDR, - (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); + return (uint32_t)(READ_BIT(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << \ + (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))) >> \ + (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)); } /** @@ -565,8 +569,8 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t */ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)), - (Alternate << (POSITION_VAL(Pin) * 4U))); + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)), + (Alternate << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))); } /** @@ -602,8 +606,8 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uin */ __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->AFR[0], - (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); + return (uint32_t)(READ_BIT(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))) >> + (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)); } /** @@ -642,8 +646,8 @@ __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_ */ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)), - (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)), + (Alternate << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))); } /** @@ -680,8 +684,8 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, ui */ __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->AFR[1], - (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); + return (uint32_t)(READ_BIT(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))) >> + (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)); } /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h index 95125c7da5..1fb6e7336a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h @@ -2305,11 +2305,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ + ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ + (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); + tmp); } /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_icache.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_icache.h index 9e5322b87d..f419b81311 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_icache.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_icache.h @@ -555,6 +555,7 @@ __STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region) /** * @brief Select the memory remapped region base address. + * @note The useful bits depends on RSIZE as described in the Reference Manual. * @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress * @param Region This parameter can be one of the following values: * @arg @ref LL_ICACHE_REGION_0 @@ -567,12 +568,13 @@ __STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region) __STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address) { MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_BASEADDR, (((Address & 0x1FFFFFFFU) >> 21U) & ICACHE_CRRx_BASEADDR)); + ICACHE_CRRx_BASEADDR, ((Address & 0x1FFFFFFFU) >> 21U)); } /** * @brief Get the memory remapped region base address. * @note The base address is the alias in the Code region. + * @note The useful bits depends on RSIZE as described in the Reference Manual. * @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress * @param Region This parameter can be one of the following values: * @arg @ref LL_ICACHE_REGION_0 @@ -584,18 +586,19 @@ __STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Ad __STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region) { return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_BASEADDR)); + ICACHE_CRRx_BASEADDR) << 21U); } /** - * @brief Select the memory remapped region remap address. + * @brief Select the memory remapped region address. + * @note The useful bits depends on RSIZE as described in the Reference Manual. * @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress * @param Region This parameter can be one of the following values: * @arg @ref LL_ICACHE_REGION_0 * @arg @ref LL_ICACHE_REGION_1 * @arg @ref LL_ICACHE_REGION_2 * @arg @ref LL_ICACHE_REGION_3 - * @param Address External memory address + * @param Address Memory address to remap * @retval None */ __STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address) @@ -605,14 +608,15 @@ __STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t A } /** - * @brief Get the memory remapped region base address. + * @brief Get the memory remapped region address. + * @note The useful bits depends on RSIZE as described in the Reference Manual. * @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress * @param Region This parameter can be one of the following values: * @arg @ref LL_ICACHE_REGION_0 * @arg @ref LL_ICACHE_REGION_1 * @arg @ref LL_ICACHE_REGION_2 * @arg @ref LL_ICACHE_REGION_3 - * @retval Address External memory address + * @retval Address Remapped memory address */ __STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region) { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h index 338c4ad067..da22b3e075 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h @@ -94,10 +94,10 @@ static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] = /** Legacy definitions for compatibility purpose @cond 0 */ -#define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1 -#define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2 -#define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1 -#define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2 +#define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1 /* for legacy purpose */ +#define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2 /* for legacy purpose */ +#define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1 /* for legacy purpose */ +#define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2 /* for legacy purpose */ /** @endcond */ @@ -314,7 +314,9 @@ typedef struct #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!RQR, (uint16_t)USART_RQR_RXFRQ); } +/** + * @brief Request a Transmit data FIFO flush + * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This + * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h index 661d8e1d95..b64ce2a80d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h @@ -153,8 +153,8 @@ typedef struct * @{ */ #define LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED 0x00000000U /*!< OPAMP power mode normal speed normal */ -#define LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED OPAMP_CSR_HSM /*!< OPAMP power mode normal speed high */ #define LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED OPAMP_CSR_OPALPM /*!< OPAMP power mode low-power speed normal */ +#define LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED OPAMP_CSR_HSM /*!< OPAMP power mode normal speed high */ #define LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED (OPAMP_CSR_OPALPM | OPAMP_CSR_HSM) /*!< OPAMP power mode low-power speed high */ /** * @} @@ -363,12 +363,9 @@ typedef struct * @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_HIGH * @retval None */ -__STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(const OPAMP_Common_TypeDef *OPAMPxy_COMMON, uint32_t PowerRange) +__STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON, uint32_t PowerRange) { - /* Prevent unused parameter warning */ - (void)(*OPAMPxy_COMMON); - - MODIFY_REG(OPAMP1->CSR, OPAMP_CSR_OPARANGE, PowerRange); + MODIFY_REG(OPAMPxy_COMMON->CSR, OPAMP_CSR_OPARANGE, PowerRange); } /** @@ -383,10 +380,7 @@ __STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(const OPAMP_Common_TypeDef *OP */ __STATIC_INLINE uint32_t LL_OPAMP_GetCommonPowerRange(const OPAMP_Common_TypeDef *OPAMPxy_COMMON) { - /* Prevent unused parameter warning */ - (void)(*OPAMPxy_COMMON); - - return (uint32_t)(READ_BIT(OPAMP1->CSR, OPAMP_CSR_OPARANGE)); + return (uint32_t)(READ_BIT(OPAMPxy_COMMON->CSR, OPAMP_CSR_OPARANGE)); } /** @@ -404,8 +398,8 @@ __STATIC_INLINE uint32_t LL_OPAMP_GetCommonPowerRange(const OPAMP_Common_TypeDef * @param OPAMPx OPAMP instance * @param PowerMode This parameter can be one of the following values: * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED - * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED + * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED * @retval None */ @@ -416,12 +410,12 @@ __STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t Power /** * @brief Get OPAMP power mode. - * @rmtoll CSR OPALPM & HSM LL_OPAMP_GetPowerMode + * @rmtoll CSR OPALPM & HSM LL_OPAMP_GetPowerMode * @param OPAMPx OPAMP instance * @retval Returned value can be one of the following values: * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED - * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED + * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED */ __STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(const OPAMP_TypeDef *OPAMPx) @@ -725,14 +719,14 @@ __STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(const OPAMP_TypeDef *OP * differential pair NMOS or PMOS, corresponding to the selected * power mode. * @rmtoll OTR TRIMOFFSETN LL_OPAMP_SetTrimmingValue - * OTR TRIMOFFSETP LL_OPAMP_SetTrimmingValue - * LPOTR TRIMLPOFFSETN LL_OPAMP_SetTrimmingValue - * LPOTR TRIMLPOFFSETP LL_OPAMP_SetTrimmingValue + * @rmtoll OTR TRIMOFFSETP LL_OPAMP_SetTrimmingValue + * @rmtoll LPOTR TRIMLPOFFSETN LL_OPAMP_SetTrimmingValue + * @rmtoll LPOTR TRIMLPOFFSETP LL_OPAMP_SetTrimmingValue * @param OPAMPx OPAMP instance * @param PowerMode This parameter can be one of the following values: * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED - * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED + * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED * @param TransistorsDiffPair This parameter can be one of the following values: * @arg @ref LL_OPAMP_TRIMMING_NMOS @@ -761,14 +755,14 @@ __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef *OPAMPx, uint32_t P * differential pair NMOS or PMOS, corresponding to the selected * power mode. * @rmtoll OTR TRIMOFFSETN LL_OPAMP_GetTrimmingValue - * OTR TRIMOFFSETP LL_OPAMP_GetTrimmingValue - * LPOTR TRIMLPOFFSETN LL_OPAMP_GetTrimmingValue - * LPOTR TRIMLPOFFSETP LL_OPAMP_GetTrimmingValue + * @rmtoll OTR TRIMOFFSETP LL_OPAMP_GetTrimmingValue + * @rmtoll LPOTR TRIMLPOFFSETN LL_OPAMP_GetTrimmingValue + * @rmtoll LPOTR TRIMLPOFFSETP LL_OPAMP_GetTrimmingValue * @param OPAMPx OPAMP instance * @param PowerMode This parameter can be one of the following values: * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED - * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED + * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED * @param TransistorsDiffPair This parameter can be one of the following values: * @arg @ref LL_OPAMP_TRIMMING_NMOS diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pwr.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pwr.h index 701a16b6a9..8b7fe9fdae 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pwr.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pwr.h @@ -252,8 +252,8 @@ extern "C" { #define LL_PWR_SRAM6_STOP_PAGE8_RETENTION (PWR_CR5_SRAM6PDS8) /*!< SRAM6 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ #define LL_PWR_SRAM6_STOP_FULL_RETENTION (PWR_CR5_SRAM6PDS1 | PWR_CR5_SRAM6PDS2 | PWR_CR5_SRAM6PDS3 | \ PWR_CR5_SRAM6PDS4 | PWR_CR5_SRAM6PDS5 | PWR_CR5_SRAM6PDS6 | \ - PWR_CR5_SRAM6PDS7 | PWR_CR5_SRAM6PDS8) - /*!< SRAM6 pages (1 to 8) retention in Stop modes (Stop 0, 1, 2, 3) */ + PWR_CR5_SRAM6PDS7 | \ + PWR_CR5_SRAM6PDS8) /*!< SRAM6 pages (1 to 8) retention in Stop modes (Stop 0, 1, 2, 3) */ /** * @} */ @@ -557,13 +557,13 @@ extern "C" { #define LL_PWR_WAKEUP_PIN8_SEC PWR_SECCFGR_WUP8SEC /*!< Wake up pin 8 secure mode */ #define LL_PWR_LPM_NSEC 0U /*!< Low-power modes nsecure mode */ -#define LL_PWR_LPM_SEC PWR_SECCFGR_WUP8SEC /*!< Low-power modes secure mode */ +#define LL_PWR_LPM_SEC PWR_SECCFGR_LPMSEC /*!< Low-power modes secure mode */ #define LL_PWR_VDM_NSEC 0U /*!< Voltage detection and monitoring nsecure mode */ -#define LL_PWR_VDM_SEC PWR_SECCFGR_WUP8SEC /*!< Voltage detection and monitoring secure mode */ +#define LL_PWR_VDM_SEC PWR_SECCFGR_VDMSEC /*!< Voltage detection and monitoring secure mode */ #define LL_PWR_VB_NSEC 0U /*!< Backup domain nsecure mode */ -#define LL_PWR_VB_SEC PWR_SECCFGR_WUP8SEC /*!< Backup domain secure mode */ +#define LL_PWR_VB_SEC PWR_SECCFGR_VBSEC /*!< Backup domain secure mode */ #define LL_PWR_APC_NSEC 0U /*!< Pull-up/pull-down nsecure mode */ -#define LL_PWR_APC_SEC PWR_SECCFGR_WUP8SEC /*!< Pull-up/pull-down secure mode */ +#define LL_PWR_APC_SEC PWR_SECCFGR_APCSEC /*!< Pull-up/pull-down secure mode */ /** * @} */ @@ -1918,8 +1918,8 @@ __STATIC_INLINE void LL_PWR_EnableVddUSB(void) { SET_BIT(PWR->SVMCR, PWR_SVMCR_USV); } -/* alias */ -#define LL_PWR_EnableVDDUSB LL_PWR_EnableVddUSB +#define LL_PWR_EnableVDDUSB LL_PWR_EnableVddUSB /* for legacy purpose */ + /** * @brief Disable the independent USB supply. * @rmtoll SVMCR USV LL_PWR_DisableVDDUSB @@ -1929,8 +1929,8 @@ __STATIC_INLINE void LL_PWR_DisableVddUSB(void) { CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV); } -/* alias */ -#define LL_PWR_DisableVDDUSB LL_PWR_DisableVddUSB +#define LL_PWR_DisableVDDUSB LL_PWR_DisableVddUSB /* for legacy purpose */ + /** * @brief Check if the independent USB supply is enabled. * @rmtoll SVMCR USV LL_PWR_IsEnabledVddUSB @@ -1940,8 +1940,8 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) { return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_USV) == (PWR_SVMCR_USV)) ? 1UL : 0UL); } -/* alias */ -#define LL_PWR_IsEnabledVDDUSB LL_PWR_IsEnabledVddUSB +#define LL_PWR_IsEnabledVDDUSB LL_PWR_IsEnabledVddUSB /* for legacy purpose */ + /** * @brief Enable the independent I/Os supply. * @rmtoll SVMCR IO2SV LL_PWR_EnableVddIO2 @@ -1951,8 +1951,8 @@ __STATIC_INLINE void LL_PWR_EnableVddIO2(void) { SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV); } -/* alias */ -#define LL_PWR_EnableVDDIO2 LL_PWR_EnableVddIO2 +#define LL_PWR_EnableVDDIO2 LL_PWR_EnableVddIO2 /* for legacy purpose */ + /** * @brief Disable the independent I/Os supply. * @rmtoll SVMCR IO2SV LL_PWR_DisableVddIO2 @@ -1962,8 +1962,8 @@ __STATIC_INLINE void LL_PWR_DisableVddIO2(void) { CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV); } -/* alias */ -#define LL_PWR_DisableVDDIO2 LL_PWR_DisableVddIO2 +#define LL_PWR_DisableVDDIO2 LL_PWR_DisableVddIO2 /* for legacy purpose */ + /** * @brief Check if the independent I/Os supply is enabled. * @rmtoll SVMCR IO2SV LL_PWR_IsEnabledVddIO2 @@ -1973,8 +1973,8 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) { return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV) == (PWR_SVMCR_IO2SV)) ? 1UL : 0UL); } -/* alias */ -#define LL_PWR_IsEnabledVDDIO2 LL_PWR_IsEnabledVddIO2 +#define LL_PWR_IsEnabledVDDIO2 LL_PWR_IsEnabledVddIO2 /* for legacy purpose */ + /** * @brief Enable the independent analog supply. * @rmtoll SVMCR ASV LL_PWR_EnableVddA @@ -1984,8 +1984,8 @@ __STATIC_INLINE void LL_PWR_EnableVddA(void) { SET_BIT(PWR->SVMCR, PWR_SVMCR_ASV); } -/* alias */ -#define LL_PWR_EnableVDDA LL_PWR_EnableVddA +#define LL_PWR_EnableVDDA LL_PWR_EnableVddA /* for legacy purpose */ + /** * @brief Disable the independent analog supply. * @rmtoll SVMCR ASV LL_PWR_DisableVddA @@ -1995,8 +1995,8 @@ __STATIC_INLINE void LL_PWR_DisableVddA(void) { CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_ASV); } -/* alias */ -#define LL_PWR_DisableVDDA LL_PWR_DisableVddA +#define LL_PWR_DisableVDDA LL_PWR_DisableVddA /* for legacy purpose */ + /** * @brief Check if the independent analog supply is enabled. * @rmtoll SVMCR ASV LL_PWR_IsEnabledVddA @@ -2006,8 +2006,8 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddA(void) { return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_ASV) == (PWR_SVMCR_ASV)) ? 1UL : 0UL); } -/* alias */ -#define LL_PWR_IsEnabledVDDA LL_PWR_IsEnabledVddA +#define LL_PWR_IsEnabledVDDA LL_PWR_IsEnabledVddA /* for legacy purpose */ + /** * @brief Enable the independent USB supply monitor. * @rmtoll SVMCR UVMEN LL_PWR_EnableVddUSBMonitor @@ -2017,8 +2017,8 @@ __STATIC_INLINE void LL_PWR_EnableVddUSBMonitor(void) { SET_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN); } -/* alias */ -#define LL_PWR_EnableVDDUSBMonitor LL_PWR_EnableVddUSBMonitor +#define LL_PWR_EnableVDDUSBMonitor LL_PWR_EnableVddUSBMonitor /* for legacy purpose */ + /** * @brief Disable the independent USB supply monitor. * @rmtoll SVMCR UVMEN LL_PWR_DisableVddUSBMonitor @@ -2028,8 +2028,8 @@ __STATIC_INLINE void LL_PWR_DisableVddUSBMonitor(void) { CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN); } -/* alias */ -#define LL_PWR_DisableVDDUSBMonitor LL_PWR_DisableVddUSBMonitor +#define LL_PWR_DisableVDDUSBMonitor LL_PWR_DisableVddUSBMonitor /* for legacy purpose */ + /** * @brief Check if the independent USB supply monitor is enabled. * @rmtoll SVMCR UVMEN LL_PWR_IsEnabledVddUSBMonitor @@ -2039,8 +2039,8 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSBMonitor(void) { return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN) == (PWR_SVMCR_UVMEN)) ? 1UL : 0UL); } -/* alias */ -#define LL_PWR_IsEnabledVDDUSBMonitor LL_PWR_IsEnabledVddUSBMonitor +#define LL_PWR_IsEnabledVDDUSBMonitor LL_PWR_IsEnabledVddUSBMonitor /* for legacy purpose */ + /** * @brief Enable the independent I/Os supply monitor. * @rmtoll SVMCR IO2VMEN LL_PWR_EnableVddIO2Monitor @@ -2050,8 +2050,8 @@ __STATIC_INLINE void LL_PWR_EnableVddIO2Monitor(void) { SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN); } -/* alias */ -#define LL_PWR_EnableVDDIO2Monitor LL_PWR_EnableVddIO2Monitor +#define LL_PWR_EnableVDDIO2Monitor LL_PWR_EnableVddIO2Monitor /* for legacy purpose */ + /** * @brief Disable the independent I/Os supply monitor. * @rmtoll SVMCR IO2VMEN LL_PWR_DisableVddIO2Monitor @@ -2061,8 +2061,8 @@ __STATIC_INLINE void LL_PWR_DisableVddIO2Monitor(void) { CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN); } -/* alias */ -#define LL_PWR_DisableVDDIO2Monitor LL_PWR_DisableVddIO2Monitor +#define LL_PWR_DisableVDDIO2Monitor LL_PWR_DisableVddIO2Monitor /* for legacy purpose */ + /** * @brief Check if the independent I/Os supply monitor is enabled. * @rmtoll SVMCR IO2VMEN LL_PWR_IsEnabledVddIO2Monitor @@ -2072,8 +2072,8 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2Monitor(void) { return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN) == (PWR_SVMCR_IO2VMEN)) ? 1UL : 0UL); } -/* alias */ -#define LL_PWR_IsEnabledVDDIO2Monitor LL_PWR_IsEnabledVddIO2Monitor +#define LL_PWR_IsEnabledVDDIO2Monitor LL_PWR_IsEnabledVddIO2Monitor /* for legacy purpose */ + /** * @brief Enable the independent analog supply monitor 1. * @rmtoll SVMCR AVM1EN LL_PWR_EnableVddAMonitor1 @@ -2083,8 +2083,8 @@ __STATIC_INLINE void LL_PWR_EnableVddAMonitor1(void) { SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN); } -/* alias */ -#define LL_PWR_EnableVDDAMonitor1 LL_PWR_EnableVddAMonitor1 +#define LL_PWR_EnableVDDAMonitor1 LL_PWR_EnableVddAMonitor1 /* for legacy purpose */ + /** * @brief Disable the independent analog supply monitor 1. * @rmtoll SVMCR AVM1EN LL_PWR_DisableVddAMonitor1 @@ -2094,8 +2094,8 @@ __STATIC_INLINE void LL_PWR_DisableVddAMonitor1(void) { CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN); } -/* alias */ -#define LL_PWR_DisableVDDAMonitor1 LL_PWR_DisableVddAMonitor1 +#define LL_PWR_DisableVDDAMonitor1 LL_PWR_DisableVddAMonitor1 /* for legacy purpose */ + /** * @brief Check if the independent analog supply monitor 1 is enabled. * @rmtoll SVMCR AVM1EN LL_PWR_IsEnabledVddAMonitor1 @@ -2105,8 +2105,8 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddAMonitor1(void) { return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN) == (PWR_SVMCR_AVM1EN)) ? 1UL : 0UL); } -/* alias */ -#define LL_PWR_IsEnabledVDDAMonitor1 LL_PWR_IsEnabledVddAMonitor1 +#define LL_PWR_IsEnabledVDDAMonitor1 LL_PWR_IsEnabledVddAMonitor1 /* for legacy purpose */ + /** * @brief Enable the independent analog supply monitor 2. * @rmtoll SVMCR AVM2EN LL_PWR_EnableVddAMonitor2 @@ -2116,8 +2116,8 @@ __STATIC_INLINE void LL_PWR_EnableVddAMonitor2(void) { SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN); } -/* alias */ -#define LL_PWR_EnableVDDAMonitor2 LL_PWR_EnableVddAMonitor2 +#define LL_PWR_EnableVDDAMonitor2 LL_PWR_EnableVddAMonitor2 /* for legacy purpose */ + /** * @brief Disable the independent analog supply monitor 2. * @rmtoll SVMCR AVM2EN LL_PWR_DisableVddAMonitor2 @@ -2127,8 +2127,8 @@ __STATIC_INLINE void LL_PWR_DisableVddAMonitor2(void) { CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN); } -/* alias */ -#define LL_PWR_DisableVDDAMonitor2 LL_PWR_DisableVddAMonitor2 +#define LL_PWR_DisableVDDAMonitor2 LL_PWR_DisableVddAMonitor2 /* for legacy purpose */ + /** * @brief Check if the independent analog supply monitor 2 is enabled. * @rmtoll SVMCR AVM2EN LL_PWR_IsEnabledVddAMonitor2 @@ -2138,8 +2138,8 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddAMonitor2(void) { return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN) == (PWR_SVMCR_AVM2EN)) ? 1UL : 0UL); } -/* alias */ -#define LL_PWR_IsEnabledVDDAMonitor2 LL_PWR_IsEnabledVddAMonitor2 +#define LL_PWR_IsEnabledVDDAMonitor2 LL_PWR_IsEnabledVddAMonitor2 /* for legacy purpose */ + /** * @brief Enable the wake up pin_x. * @rmtoll WUCR1 WUPENx LL_PWR_EnableWakeUpPin diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h index 6621b95259..6a62949c2c 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h @@ -230,7 +230,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) { - CLEAR_BIT(RNGx->CR, RNG_CR_CED); + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -241,7 +242,8 @@ __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) { - SET_BIT(RNGx->CR, RNG_CR_CED); + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -331,7 +333,7 @@ __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx) __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx) { MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST); - CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);; + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -442,7 +444,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider) { - MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, (Divider << RNG_CR_CLKDIV_Pos) | RNG_CR_CONDRST); + MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST); CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rtc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rtc.h index 7647b9905b..dbf9eb3f02 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rtc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rtc.h @@ -1489,7 +1489,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma /** * @brief Get time format (AM or PM notation) - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1523,7 +1523,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) /** * @brief Get Hours in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1558,7 +1558,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) /** * @brief Get Minutes in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1593,7 +1593,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) /** * @brief Get Seconds in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1644,7 +1644,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, /** * @brief Get time (hour, minute and second) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1792,7 +1792,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) /** * @brief Get Year in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format * @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n @@ -1826,7 +1826,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) /** * @brief Get Week day - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay * @param RTCx RTC Instance @@ -1873,7 +1873,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) /** * @brief Get Month in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format * @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n @@ -1915,7 +1915,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) /** * @brief Get Day in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format * @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n @@ -1978,7 +1978,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin /** * @brief Get date (WeekDay, Day, Month and Year) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, * and __LL_RTC_GET_DAY are available to get independently each parameter. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h index 4622f374e1..70cd548f29 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h @@ -572,9 +572,11 @@ typedef struct * @{ */ #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) +#define SDMMC_TRANSFER_MODE_SDIO SDMMC_DCTRL_DTMODE_0 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ + ((MODE) == SDMMC_TRANSFER_MODE_SDIO) || \ ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) /** * @} @@ -1102,6 +1104,7 @@ uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount); /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_spi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_spi.h index 3879bba83e..028747fd32 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_spi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_spi.h @@ -923,7 +923,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx) */ __STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll) { - MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll); + MODIFY_REG(SPIx->CR1, SPI_CR1_TCRCINI, TXCRCInitAll); } /** @@ -1241,7 +1241,8 @@ __STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx) * @brief Set Baudrate Prescaler * @note This configuration can not be changed when SPI is enabled. * SPI BaudRate = fPCLK/Pescaler. - * @rmtoll CFG1 MBR BPASS LL_SPI_SetBaudRatePrescaler + * @rmtoll CFG1 MBR LL_SPI_SetBaudRatePrescaler\n + * CFG1 BPASS LL_SPI_SetBaudRatePrescaler * @param SPIx SPI Instance * @param Baudrate This parameter can be one of the following values: * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS @@ -1262,7 +1263,8 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau /** * @brief Get Baudrate Prescaler - * @rmtoll CFG1 MBR BPASS LL_SPI_GetBaudRatePrescaler + * @rmtoll CFG1 MBR LL_SPI_GetBaudRatePrescaler\n + * CFG1 BPASS LL_SPI_GetBaudRatePrescaler * @param SPIx SPI Instance * @retval Returned value can be one of the following values: * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h index 6639ad2dbf..45b5f811d6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h @@ -623,7 +623,6 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) } - /** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management * @{ */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h index 3a02cae0a7..4780f66494 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h @@ -767,6 +767,15 @@ typedef struct */ #endif /* USE_FULL_LL_DRIVER */ +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 /* for legacy purpose */ +#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 /* for legacy purpose */ +/** +@endcond + */ + /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode * @{ */ @@ -782,8 +791,8 @@ typedef struct #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*! 62U) \ + if ((wCount) == 0U) \ { \ - USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + (pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if ((wCount) <= 62U) \ + { \ + USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ - if ((wCount) == 0U) \ - { \ - (pdwReg) |= USB_CNTRX_BLSIZE; \ - } \ - else \ - { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ - } \ + USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ } \ } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ @@ -1094,41 +1098,41 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); -HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); -void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup); -uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup); +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx); uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx); -uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); -uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq); -HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state); +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, @@ -1137,12 +1141,12 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); -uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #if defined (USB_DRD_FS) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_utils.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_utils.h index b947b796a4..cbce427797 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_utils.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_utils.h @@ -165,6 +165,7 @@ typedef struct * @{ */ #define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP72_SMPS 0x00000001U /*!< WLCSP72 with internal SMPS package type */ #define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */ #define LL_UTILS_PACKAGETYPE_UFBGA132 0x00000003U /*!< UFBGA132 package type */ #define LL_UTILS_PACKAGETYPE_LQFP144 0x00000004U /*!< LQFP144 package type */ @@ -177,9 +178,10 @@ typedef struct #define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x0000000CU /*!< LQFP144 with internal SMPS package type */ #define LL_UTILS_PACKAGETYPE_LQFP48_SMPS 0x0000000DU /*!< LQFP48 with internal SMPS package type */ #define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS 0x0000000FU /*!< UFBGA169 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_WLCSP144 0x00000010U /*!< WLCSP144 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA144 0x00000011U /*!< UFBGA144 package type */ -#define LL_UTILS_PACKAGETYPE_WLCSP144_SMPS 0x00000018U /*!< WLCSP144 with internal SMPS package t */ +#define LL_UTILS_PACKAGETYPE_UFBGA64 0x00000012U /*!< UFBGA64 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA100 0x00000013U /*!< UFBGA100 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_DSI_SMPS 0x00000014U /*!< LQFP100 DSI with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_DSI_SMPS 0x00000015U /*!< LQFP144 DSI with internal SMPS package type */ #define LL_UTILS_PACKAGETYPE_UFBGA144_SMPS 0x00000019U /*!< UFBGA144 with internal SMPS package type */ #define LL_UTILS_PACKAGETYPE_WLCSP208_SMPS 0x0000001BU /*!< WLCSP208 with internal SMPS package type */ #define LL_UTILS_PACKAGETYPE_TFBGA216_SMPS 0x0000001CU /*!< TFBGA216 with internal SMPS package type */ @@ -298,6 +300,9 @@ __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) } void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_Init1msTick_HCLK_Div8(uint32_t HCLKFrequency); +void LL_Init1msTick_LSE(void); +void LL_Init1msTick_LSI(void); void LL_mDelay(uint32_t Delay); /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html index d335e141ee..9ef2d27baa 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html @@ -40,15 +40,209 @@

        Purpose

        Update History

        - +

        Main Changes

          +
        • HAL and LL drivers Maintenance Release for STM32U535xx/STM32U545xx, STM32U575xx/STM32U585xx, STM32U599xx/STM32U5A9xx, STM32U595xx/STM32U5A5xx, STM32U5F9xx/STM32U5G9xx and STM32U5F7xx/STM32U5G7xx devices
          • +
        • Add the HAL MMC replay protected memory block management feature
          • +
        • The HAL and LL drivers provided within this package are MISRA-C, Coverity and MCU ASTYLE compliant, and have been reviewed with a static analysis tool to eliminate possible run-time errors
          • +
        +

        HAL Drivers updates

        +
          +
        • HAL CORDIC driver +
            +
          • Fix incorrect word ‘surcharged’ in functions headers
            • +
          • +
        • HAL CORTEX driver +
            +
          • Fix MPU_ACCESS_OUTER_SHAREABLE and LL_MPU_ACCESS_OUTER_SHAREABLE definitions
            • +
          • Add HAL_SYSTICK_GetCLKSourceConfig, HAL_MPU_EnableRegion, HAL_MPU_DisableRegion, HAL_MPU_EnableRegion_NS and HAL_MPU_DisableRegion_NS functions
            • +
          • +
        • HAL FMAC driver +
            +
          • Fix incorrect word ‘surcharged’ in functions headers
            • +
          • +
        • HAL DSI driver +
            +
          • Align DSI Initialization sequence to the recommended ‘Programming procedure overview’ part to avoid DSI read LCD controller register 0x0A error
            • +
          • +
        • HAL GPIO driver +
            +
          • Remove IS_GPIO_SINGLE_PIN define
            • +
          • +
        • HAL ICACHE driver +
            +
          • Update HAL_ICACHE_DeInit to set registers to reset value
            • +
          • Update HAL_ICACHE_Invalidate() to prevent launching an invalidation if one has already been launched
            • +
          • +
        • HAL I2C driver +
            +
          • Update HAL_I2C_Mem_Write_IT API to initialize XferSize at 0
            • +
          • Update I2C_Slave_ISR_IT, I2C_Slave_ISR_DMA and I2C_ITSlaveCplt to prevent the call of HAL_I2C_ListenCpltCallback twice
            • +
          • Update I2C_WaitOnRXNEFlagUntilTimeout to check I2C_FLAG_AF independently from I2C_FLAG_RXNE
            • +
          • Remove the unusable code in HAL_I2C_IsDeviceReady function
            • +
          • Update HAL_I2C_Slave_Transmit to check if the received NACK is the good one
            • +
          • +
        • HAL driver +
            +
          • Add HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection and HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection functions
            • +
          • +
        • HAL LPTIM driver +
            +
          • Removed references to COMP2 for STM32U535xx/STM32U545xx devices
            • +
          • Remove IS_LPTIM_AUTORELOAD define
            • +
          • +
        • HAL MMC driver +
            +
          • Add the replay protected memory block management defines: +
              +
            • HAL_MMC_ERROR_RPMB_OPERATION_OK
              +
              • +
            • HAL_MMC_ERROR_RPMB_GENERAL_FAILURE
              +
              • +
            • HAL_MMC_ERROR_RPMB_AUTHENTICATION_FAILURE
              +
              • +
            • HAL_MMC_ERROR_RPMB_COUNTER_FAILURE
              +
              • +
            • HAL_MMC_ERROR_RPMB_ADDRESS_FAILURE
              +
              • +
            • HAL_MMC_ERROR_RPMB_WRITE_FAILURE
              +
              • +
            • HAL_MMC_ERROR_RPMB_READ_FAILURE
              +
              • +
            • HAL_MMC_ERROR_RPMB_KEY_NOT_YET_PROG
              +
              • +
            • HAL_MMC_ERROR_RPMB_COUNTER_EXPIRED
              • +
            • HAL_MMC_RPMB_ProgramAuthenticationKey
              • +
            • HAL_MMC_RPMB_ProgramAuthenticationKey_IT
              • +
            • HAL_MMC_RPMB_GetWriteCounter
              • +
            • HAL_MMC_RPMB_GetWriteCounter_IT
              • +
            • HAL_MMC_RPMB_WriteBlocks
              +
              • +
            • HAL_MMC_RPMB_WriteBlocks_IT
              • +
            • HAL_MMC_RPMB_ReadBlocks
              • +
            • HAL_MMC_RPMB_ReadBlocks_IT
              • +
            • MMC_RPMB_KEYMAC_POSITION
              +
              • +
            • MMC_RPMB_DATA_POSITION
              +
              • +
            • MMC_RPMB_NONCE_POSITION
              +
              • +
            • MMC_RPMB_WRITE_COUNTER_POSITION
              • +
            • +
          • Add HAL_MMC_SwitchPartition and HAL_MMC_GetRPMBError functions
            • +
          • Add the MMC partitions type defines: +
              +
            • HAL_MMC_USER_AREA_PARTITION
              • +
            • HAL_MMC_BOOT_PARTITION1
              +
              • +
            • HAL_MMC_BOOT_PARTITION2
              +
              • +
            • HAL_MMC_RPMB_PARTITION
              • +
            • +
          • +
        • HAL PKA driver +
            +
          • Add PKA_ECCMulExInTypeDef operation structure definition
            • +
          • Add HAL_PKA_ECCMulEx and HAL_PKA_ECCMulEx_IT functions
            • +
          • +
        • HAL PSSI driver +
            +
          • Replace hdmatx by hdmarx in HAL_PSSI_Receive_DMA() function
            • +
          • +
        • HAL PWR driver +
            +
          • Add PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR and PWR_STOPENTRY_WFE_NO_EVT_CLEAR defines
            • +
          • +
        • HAL RCC driver +
            +
          • Update HAL_RCC_NMI_IRQHandler, clear flag before callback
            • +
          • +
        • HAL RNG driver +
            +
          • Add RNG noise source control
            • +
          • +
        • HAL SAI driver +
            +
          • Improve audio quality to avoid potential glitch
            • +
          • Fix incorrect word ‘surcharged’ in functions headers
            • +
          • +
        • HAL SMBUS driver +
            +
          • Remove HAL_SMBUS_STATE_TIMEOUT and HAL_SMBUS_STATE_ERROR defines
            • +
          • +
        • HAL TIM driver +
            +
          • Rename TIM_OCMODE_ASSYMETRIC_PWM1 to TIM_OCMODE_ASYMMETRIC_PWM1 define
            • +
          • Rename TIM_OCMODE_ASSYMETRIC_PWM2 to TIM_OCMODE_ASYMMETRIC_PWM2 define
            • +
          • Removed references to COMP2 for STM32U535xx/STM32U545xxxx devices
            • +
          • +
        • HAL UART driver +
            +
          • Fix incorrect gState check in HAL_UART_RegisterRxEventCallback and HAL_UART_UnRegisterRxEventCallback to allow user Rx Event Callback registration when a transmit is ongoing
            • +
          • +
        • HAL USB driver +
            +
          • Add HCD_PDWN_EXIT_CNT define
            • +
          • +
        +

        LL Drivers updates

        +
          +
        • LL CORTEX driver +
            +
          • Rename LL_SYSTICK_CLKSOURCE_HCLK_DIV8 to LL_SYSTICK_CLKSOURCE_EXTERNAL
            • +
          • +
        • LL I2C driver +
            +
          • Update LL_I2C_HandleTranfer function to prevent undefined behavior of volatile usage before updating the CR2 register
            • +
          • +
        • LL PWR driver +
            +
          • Rename PWR_SECCFGR_WUP8SEC to PWR_SECCFGR_LPMSEC define
            • +
          • Rename PWR_SECCFGR_WUP8SEC to PWR_SECCFGR_VDMSEC define
            • +
          • Rename PWR_SECCFGR_WUP8SEC to PWR_SECCFGR_VBSEC define
            • +
          • Rename PWR_SECCFGR_WUP8SEC to PWR_SECCFGR_APCSEC define
            • +
          • +
        • LL TIM driver +
            +
          • Rename LL_TIM_OCMODE_ASSYMETRIC_PWM1 to LL_TIM_OCMODE_ASYMMETRIC_PWM1 define
            • +
          • Rename LL_TIM_OCMODE_ASSYMETRIC_PWM2 to LL_TIM_OCMODE_ASYMMETRIC_PWM2 define
            • +
          • +
        • LL USB driver +
            +
          • Add HAL_USB_TIMEOUT and HAL_USB_CURRENT_MODE_MAX_DELAY_MS defines
            • +
          • Prevent masking NAK IT during start split transfer
            • +
          • +
        • LL UTILS driver +
            +
          • Add LL_UTILS_PACKAGETYPE_WLCSP72_SMPS and LL_UTILS_PACKAGETYPE_LQFP144_DSI_SMPS defines
            • +
          • Add LL_Init1msTick_HCLK_Div8, LL_Init1msTick_LSE and LL_Init1msTick_LSI functions
            • +
          • Rename LL_UTILS_PACKAGETYPE_WLCSP144 to LL_UTILS_PACKAGETYPE_UFBGA64 define
            • +
          • Rename LL_UTILS_PACKAGETYPE_UFBGA144 to LL_UTILS_PACKAGETYPE_UFBGA100 define
            • +
          • Rename LL_UTILS_PACKAGETYPE_WLCSP144_SMPS to LL_UTILS_PACKAGETYPE_LQFP100_DSI_SMPS define
            • +
          • +
        +

        Known Limitations

        +
          +
        • N/A
          • +
        +

        Backward compatibility

        +
          +
        • N/A
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
        • HAL and LL drivers Maintenance Release for STM32U5XX devices
        • Update ADC HAL and LL drivers to fix known defects and add implementation enhancements
        • The HAL and LL drivers provided within this package are MISRA-C, MCU ASTYLE and CodeSonar compliant, and have been reviewed with a static analysis tool to eliminate possible run-time errors
        -

        HAL Drivers updates

        +

        HAL Drivers updates

        • HAL ADC driver
            @@ -59,18 +253,18 @@

            HAL Drivers updates

          • Enhance calibration procedure implementation
        -

        LL Drivers updates

        +

        LL Drivers updates

        • LL ADC driver
          • Add new Helper macro for differential mode raw data to voltage conversion
        -

        Known Limitations

        +

        Known Limitations

        • N/A
        -

        Backward compatibility

        +

        Backward compatibility

        • N/A
        @@ -79,14 +273,14 @@

        Backward compatibility

        -

        Main Changes

        +

        Main Changes

        • HAL and LL drivers official Release for STM32U5F7xx/STM32U5G7xx, STM32U5F9xx/STM32U5G9xx, STM32U535xx/STM32U545xx, STM32U575xx/STM32U585xx, STM32U595xx/STM32U5A5xx and STM32U599xx/STM32U5A9xx devices
        • Add 2 new HAL drivers : GFXTIM and JPEG highlighting the graphics aspect of STM32U5F7/STM32U5G7/STM32U5F9/STM32U5G9 devices
        • The HAL and LL drivers provided within this package are MISRA-C, MCU ASTYLE and CodeSonar compliant, and have been reviewed with a static analysis tool to eliminate possible run-time errors
        • General updates to fix known defects and implementation enhancements
        -

        HAL Drivers updates

        +

        HAL Drivers updates

        • HAL CRYP driver
            @@ -124,7 +318,7 @@

            HAL Drivers updates

          • Add IS_TIM_CCX_CHANNEL define
        -

        LL Drivers updates

        +

        LL Drivers updates

        • LL PWR driver
            @@ -169,11 +363,11 @@

            LL Drivers updates

        Note: HAL/LL Backward compatibility ensured by legacy defines.

        -

        Known Limitations

        +

        Known Limitations

        • N/A
        -

        Backward compatibility

        +

        Backward compatibility

        • N/A
        @@ -182,12 +376,12 @@

        Backward compatibility

        -

        Main Changes

        +

        Main Changes

        • HAL and LL drivers Official Release for STM32U535xx / STM32U545xx, STM32U575xx / STM32U585xx, STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices.
        • Update STM32U545xx_User_Manual, STM32U585xx_User_Manual and STM32U5A9xx_User_Manual CHM User Manuals
        -

        HAL Drivers updates

        +

        HAL Drivers updates

        • HAL ADC driver
            @@ -340,7 +534,7 @@

            HAL Drivers updates

          • Add HAL_HCD_HC_SetHubInfo and HAL_HCD_HC_ClearHubInfo macros
        -

        LL Drivers updates

        +

        LL Drivers updates

        • LL ADC driver
            @@ -382,11 +576,11 @@

            LL Drivers updates

        Note: HAL/LL Backward compatibility ensured by legacy defines.

        -

        Known Limitations

        +

        Known Limitations

        • N/A
        -

        Backward compatibility

        +

        Backward compatibility

        • N/A
        @@ -395,7 +589,7 @@

        Backward compatibility

        -

        Main Changes

        +

        Main Changes

        • HAL and LL drivers Maintenance Release for STM32U575xx / STM32U585xx devices and new support of STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices
        • Add New LTDC, GFXMMU, DSI, GPU2D HAL drivers highlighting the graphics aspect of STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices
          • @@ -404,7 +598,7 @@

          Main Changes

        • General updates to fix known defects and implementation enhancements
        • The HAL and LL drivers provided within this package are MISRA-C, MCU ASTYLE and CodeSonar compliant, and have been reviewed with a static analysis tool to eliminate possible run-time errors
        -

        HAL Drivers updates

        +

        HAL Drivers updates

        • All the HAL drivers are updated to support both STM32U575/STM32U585 and STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices
        • HAL ADC driver @@ -542,7 +736,7 @@

          HAL Drivers updates

        • Rework HAL_USART_DMAResume() function in order to use DMA instead of USART to resume data transfer
      -

      LL Drivers updates

      +

      LL Drivers updates

      • All the LL drivers are updated to support both STM32U575/STM32U585 and STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices
      • LL ADC driver @@ -572,6 +766,10 @@

        LL Drivers updates

        • Add __LL_OPAMP_COMMON_INSTANCE macro
        • +
      • LL LPUART driver +
          +
        • Add LL_LPUART_RequestTxDataFlush macro
          • +
      • LL RCC driver
        • Add the following functions: @@ -599,6 +797,11 @@

          LL Drivers updates

        • Rename the static API RCC_PLL3_GetFreqDomain_HSPI to RCC_PLL3_GetFreqDomain_HSPI_LTDC
        • Rename LL_RCC_USART6_CLKSOURCE_PCLK2 to LL_RCC_USART6_CLKSOURCE_PCLK1
        • +
      • LL SDMMC driver +
          +
        • Add SDMMC_TRANSFER_MODE_SDIO define
          • +
        • Add SDMMC_CmdBlockCount function
          • +
      • LL RTC driver
        • Add LL_RTC_IsActiveFlag_ITAMP7() function
          • @@ -613,11 +816,11 @@

          LL Drivers updates

      Backward compatibility ensured by legacy defines

      -

      Known Limitations

      +

      Known Limitations

      • N/A
      -

      Backward compatibility

      +

      Backward compatibility

      • N/A
      @@ -626,11 +829,11 @@

      Backward compatibility

      -

      Main Changes

      +

      Main Changes

      • Patch release V1.0.2 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
      -

      LL Drivers updates

      +

      LL Drivers updates

      • LL DAC driver
          @@ -642,11 +845,11 @@

          LL Drivers updates

      • Backward compatibility ensured by legacy defines
      -

      Known Limitations

      +

      Known Limitations

      • N/A
      -

      Backward compatibility

      +

      Backward compatibility

      • N/A
      @@ -655,11 +858,11 @@

      Backward compatibility

      -

      Main Changes

      +

      Main Changes

      • Patch release V1.0.1 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
      -

      HAL Drivers updates

      +

      HAL Drivers updates

      • HAL ADC driver
          @@ -697,18 +900,18 @@

          HAL Drivers updates

        • Fix setting Flash latency from MSIRange in Oscillator Configuration
      -

      LL Drivers updates

      +

      LL Drivers updates

      • LL I2C driver
        • Add LL_I2C_EnableFastModePlus, LL_I2C_DisableFastModePlus and LL_I2C_IsEnabledFastModePlus APIs
      -

      Known Limitations

      +

      Known Limitations

      • N/A
      -

      Backward compatibility

      +

      Backward compatibility

      • N/A
      @@ -717,11 +920,11 @@

      Backward compatibility

      -

      Main Changes

      +

      Main Changes

      • First official release of HAL and LL drivers for STM32U575xx / STM32U585xx devices
      -

      Known Limitations

      +

      Known Limitations

      • N/A
      diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c index 9c640570c5..512e1441e4 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c @@ -52,10 +52,10 @@ * @{ */ /** - * @brief STM32U5xx HAL Driver version number 1.4.0 + * @brief STM32U5xx HAL Driver version number 1.5.0 */ #define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32U5xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32U5xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ #define __STM32U5xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\ @@ -88,7 +88,7 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ * @{ */ -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions +/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and de-initialization Functions * @brief Initialization and de-initialization functions * @verbatim @@ -129,8 +129,8 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ * @note HAL_Init() function is called at the beginning of program after reset and before * the clock configuration. * - * @note In the default implementation the System Timer (Systick) is used as source of time base. - * The Systick configuration is based on MSI clock, as MSI is the clock + * @note In the default implementation the System Timer (SysTick) is used as source of time base. + * The SysTick configuration is based on MSI clock, as MSI is the clock * used after a system Reset and the NVIC configuration is set to Priority group 4. * Once done, time base tick starts incrementing: the tick variable counter is incremented * each 1ms in the SysTick_Handler() interrupt handler. @@ -150,6 +150,9 @@ HAL_StatusTypeDef HAL_Init(void) /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; + /* Select HCLK as SysTick clock source */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { @@ -233,29 +236,57 @@ __weak void HAL_MspDeInit(void) */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + uint32_t ticknumber = 0U; + uint32_t systicksel; + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ if ((uint32_t)uwTickFreq == 0UL) { return HAL_ERROR; } - /* Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) + /* Check Clock source to calculate the tickNumber */ + if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) == SysTick_CTRL_CLKSOURCE_Msk) { - return HAL_ERROR; + /* HCLK selected as SysTick clock source */ + ticknumber = SystemCoreClock / (1000UL / (uint32_t)uwTickFreq); } - - /* Configure the SysTick IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + else { - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - uwTickPrio = TickPriority; + systicksel = HAL_SYSTICK_GetCLKSourceConfig(); + switch (systicksel) + { + /* HCLK_DIV8 selected as SysTick clock source */ + case SYSTICK_CLKSOURCE_HCLK_DIV8: + /* Calculate tick value */ + ticknumber = (SystemCoreClock / (8000UL / (uint32_t)uwTickFreq)); + break; + /* LSI selected as SysTick clock source */ + case SYSTICK_CLKSOURCE_LSI: + /* Calculate tick value */ + ticknumber = (LSI_VALUE / (1000UL / (uint32_t)uwTickFreq)); + break; + /* LSE selected as SysTick clock source */ + case SYSTICK_CLKSOURCE_LSE: + /* Calculate tick value */ + ticknumber = (LSE_VALUE / (1000UL / (uint32_t)uwTickFreq)); + break; + default: + /* Nothing to do */ + break; + } } - else + + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(ticknumber) > 0U) { return HAL_ERROR; } + /* Configure the SysTick IRQ priority */ + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + /* Return function status */ return HAL_OK; } @@ -264,7 +295,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @} */ -/** @defgroup HAL_Group2 HAL Control functions +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions * @brief HAL Control functions * @verbatim @@ -291,7 +322,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @brief This function is called to increment a global variable "uwTick" * used as application time base. * @note In the default implementation, this variable is incremented each 1ms - * in Systick ISR. + * in SysTick ISR. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None @@ -648,6 +679,26 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } +/** + * @brief Enable the I/O analog switch voltage selection + * + * @retval None + */ +void HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); +} + +/** + * @brief Disable the I/O analog switch voltage selection + * + * @retval None + */ +void HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); +} + #if defined(SYSCFG_CFGR1_SRAMCACHED) /** * @brief Enable the Cacheability of internal SRAMx by DCACHE2 diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c index c9a1397da0..02cc0433eb 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c @@ -70,9 +70,9 @@ once the ADC is enabled */ /* and CPU clock frequencies. */ /* Example of profile low frequency : ADC frequency minimum 140kHz (cf */ /* datasheet for ADC4), CPU frequency 160MHz. */ -/* Calibration time max = 25502 / fADC (refer to datasheet) */ -/* = 29M CPU cycles */ -#define ADC_CALIBRATION_TIMEOUT (29000000U) /*!< ADC calibration time-out value */ +/* Calibration time max = 31849 / fADC (refer to datasheet) */ +/* = 36M CPU cycles */ +#define ADC_CALIBRATION_TIMEOUT (36400000U) /*!< ADC calibration time-out value */ /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c index 4850535545..d3b051c7e6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c @@ -1141,7 +1141,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic) /*Call registered callback*/ hcordic->CalculateCpltCallback(hcordic); #else - /*Call legacy weak (surcharged) callback*/ + /*Call legacy weak callback*/ HAL_CORDIC_CalculateCpltCallback(hcordic); #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ } @@ -1282,7 +1282,7 @@ static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma) /*Call registered callback*/ hcordic->CalculateCpltCallback(hcordic); #else - /*Call legacy weak (surcharged) callback*/ + /*Call legacy weak callback*/ HAL_CORDIC_CalculateCpltCallback(hcordic); #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ } @@ -1311,7 +1311,7 @@ static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma) /*Call registered callback*/ hcordic->CalculateCpltCallback(hcordic); #else - /*Call legacy weak (surcharged) callback*/ + /*Call legacy weak callback*/ HAL_CORDIC_CalculateCpltCallback(hcordic); #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ } @@ -1336,7 +1336,7 @@ static void CORDIC_DMAError(DMA_HandleTypeDef *hdma) /*Call registered callback*/ hcordic->ErrorCallback(hcordic); #else - /*Call legacy weak (surcharged) callback*/ + /*Call legacy weak callback*/ HAL_CORDIC_ErrorCallback(hcordic); #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c index 63238cf78e..5f684d795f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c @@ -273,7 +273,23 @@ void HAL_NVIC_SystemReset(void) */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { - return SysTick_Config(TicksNumb); + if ((TicksNumb - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + /* Reload value impossible */ + return (1UL); + } + + /* Set reload register */ + WRITE_REG(SysTick->LOAD, (uint32_t)(TicksNumb - 1UL)); + + /* Load the SysTick Counter Value */ + WRITE_REG(SysTick->VAL, 0UL); + + /* Enable SysTick IRQ and SysTick Timer */ + SET_BIT(SysTick->CTRL, (SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk)); + + /* Function successful */ + return (0UL); } /** * @} @@ -436,6 +452,52 @@ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) } } +/** + * @brief Get the SysTick clock source configuration. + * @retval SysTick clock source that can be one of the following values: + * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + */ +uint32_t HAL_SYSTICK_GetCLKSourceConfig(void) +{ + uint32_t systick_source; + uint32_t systick_rcc_source; + + /* Read SysTick->CTRL register for internal or external clock source */ + if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) != 0U) + { + /* Internal clock source */ + systick_source = SYSTICK_CLKSOURCE_HCLK; + } + else + { + /* External clock source, check the selected one in RCC */ + systick_rcc_source = READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL); + + switch (systick_rcc_source) + { + case (0x00000000U): + systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8; + break; + + case (RCC_CCIPR1_SYSTICKSEL_0): + systick_source = SYSTICK_CLKSOURCE_LSI; + break; + + case (RCC_CCIPR1_SYSTICKSEL_1): + systick_source = SYSTICK_CLKSOURCE_LSE; + break; + + default: + systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8; + break; + } + } + return systick_source; +} + /** * @brief Handle SYSTICK interrupt request. * @retval None @@ -555,6 +617,82 @@ void HAL_MPU_Disable_NS(void) } #endif /* __ARM_FEATURE_CMSE */ +/** + * @brief Enable the MPU Region. + * @retval None + * @param RegionNumber Specifies the index of the region to enable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable the non-secure MPU Region. + * @retval None + * @param RegionNumber Specifies the index of the region to enable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + */ +void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU_NS->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /*__ARM_FEATURE_CMSE*/ + +/** + * @brief Disable the MPU Region. + * @retval None + * @param RegionNumber Specifies the index of the region to disable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Disable the non-secure MPU Region. + * @retval None + * @param RegionNumber Specifies the index of the region to disable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + */ +void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU_NS->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /*__ARM_FEATURE_CMSE*/ + /** * @brief Initialize and configure the Region and the memory to be protected. * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains @@ -622,6 +760,9 @@ static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const #endif /* __ARM_FEATURE_CMSE */ assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number)); assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable)); + assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission)); + assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable)); /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */ __DMB(); @@ -629,29 +770,20 @@ static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const /* Set the Region number */ MPUx->RNR = pMPU_RegionInit->Number; - if (pMPU_RegionInit->Enable != MPU_REGION_DISABLE) - { - /* Check the parameters */ - assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission)); - assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable)); - - MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) | - ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) | - ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) | - ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); - - MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) | - ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | - ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); - } - else - { - MPUx->RLAR = 0U; - MPUx->RBAR = 0U; - } + /* Disable the Region */ + CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); + + MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) | + ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) | + ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) | + ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); + + MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) | + ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | + ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); } + static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit) { __IO uint32_t *p_mair; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c index 0539c0dd85..06ed059349 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c @@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) __HAL_CRC_DR_RESET(hcrc); /* Reset IDR register content */ - CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); + CLEAR_REG(hcrc->Instance->IDR); /* DeInit the low level hardware */ HAL_CRC_MspDeInit(hcrc); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c index 5f70344450..58db907051 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c @@ -22,7 +22,7 @@ ********************************************************************************************************************** @verbatim ====================================================================================================================== - ############### How to use this driver ############### + ##### How to use this driver ##### ====================================================================================================================== [..] @@ -95,8 +95,7 @@ (++) can be a value of DMA_Transfer_Event_Mode (+) Mode : Specifies the transfer mode for the DMA channel - (++) can be a value of DMA_Transfer_Mode - + (++) can be DMA_NORMAL *** Polling mode IO operation *** ================================= @@ -217,7 +216,7 @@ static void DMA_Init(DMA_HandleTypeDef const *const hdma); * @verbatim ====================================================================================================================== - ############### Initialization and de-initialization functions ############### + ##### Initialization and de-initialization functions ##### ====================================================================================================================== [..] This section provides functions allowing to initialize and de-initialize the DMA channel in normal mode. @@ -251,7 +250,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); - if ((hdma->Init.Direction == DMA_MEMORY_TO_PERIPH) || (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)) + if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) { assert_param(IS_DMA_REQUEST(hdma->Init.Request)); } @@ -378,7 +377,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Clear secure attribute */ CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | @@ -422,7 +421,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### IO operation functions ############### + ##### IO operation functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -891,14 +890,14 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Global Interrupt Flag management *********************************************************************************/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U)) #else if (global_active_flag_ns == 0U) -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ { return; /* the global interrupt flag for the current channel is down , nothing to do */ } @@ -995,19 +994,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) /* Reset the channel internal state and reset the FIFO */ hdma->Instance->CCR |= DMA_CCR_RESET; - /* Wait one clock cycle to ensure that the reset of DMA channel is done before checking the enable bit */ - __NOP(); - - if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_ERROR; - } - else - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - } + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; /* Check DMA channel transfer mode */ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) @@ -1099,19 +1087,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) /* Reset the channel internal state and reset the FIFO */ hdma->Instance->CCR |= DMA_CCR_RESET; - /* Wait one clock cycle to ensure that the reset of DMA channel is done before checking the enable bit */ - __NOP(); - - if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_ERROR; - } - else - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - } + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; /* Check DMA channel transfer mode */ if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) @@ -1308,7 +1285,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, * @verbatim ====================================================================================================================== - ############### State and Errors functions ############### + ##### State and Errors functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -1354,7 +1331,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma) * @verbatim ====================================================================================================================== - ############### DMA Attributes functions ############### + ##### DMA Attributes functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -1461,7 +1438,7 @@ HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC); } } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ return HAL_OK; } @@ -1495,7 +1472,6 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co /* Get DMA channel privilege attribute */ attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Get DMA channel security attribute */ attributes |= ((p_dma_instance->SECCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC; @@ -1505,7 +1481,6 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co /* Get DMA channel destination security attribute */ attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC; -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* return value */ *pChannelAttributes = attributes; @@ -1542,7 +1517,7 @@ HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const h return HAL_OK; } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief Get the security and privilege attribute lock state of a DMA channel. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma2d.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma2d.c index 9379fbbf2b..92df0abed5 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma2d.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma2d.c @@ -323,7 +323,7 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) /* Before aborting any DMA2D transfer or CLUT loading, check first whether or not DMA2D clock is enabled */ - if (__HAL_RCC_DMA2D_IS_CLK_ENABLED()) + if (__HAL_RCC_DMA2D_IS_CLK_ENABLED() == 1U) { /* Abort DMA2D transfer if any */ if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START) @@ -1013,7 +1013,8 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, + uint32_t LayerIdx) { /* Check the parameters */ assert_param(IS_DMA2D_LAYER(LayerIdx)); @@ -1067,7 +1068,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLU * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx) { /* Check the parameters */ @@ -1770,7 +1771,7 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) */ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { - DMA2D_LayerCfgTypeDef *pLayerCfg; + const DMA2D_LayerCfgTypeDef *pLayerCfg; uint32_t regMask; uint32_t regValue; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c index 97aaa535d1..b8c6ac1ff6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c @@ -25,7 +25,7 @@ ********************************************************************************************************************** @verbatim ====================================================================================================================== - ############### How to use this driver ############### + ##### How to use this driver ##### ====================================================================================================================== [..] Alternatively to the normal programming mode, a DMA channel can be programmed by a list of transfers, known as @@ -581,7 +581,7 @@ static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList); * @verbatim ====================================================================================================================== - ############### Linked-List Initialization and De-Initialization Functions ############### + ##### Linked-List Initialization and De-Initialization Functions ##### ====================================================================================================================== [..] This section provides functions allowing to initialize and de-initialize the DMA channel in linked-list mode. @@ -676,7 +676,6 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) /* Get DMA instance */ DMA_TypeDef *p_dma_instance; - /* Get tick number */ uint32_t tickstart = HAL_GetTick(); @@ -693,7 +692,6 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) /* Get DMA instance */ p_dma_instance = GET_DMA_INSTANCE(hdma); - /* Disable the selected DMA Channel */ __HAL_DMA_DISABLE(hdma); @@ -738,7 +736,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Clear secure attribute */ CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | @@ -790,7 +788,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### Linked-List IO Operation Functions ############### + ##### Linked-List IO Operation Functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -956,7 +954,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### Linked-List Management Functions ############### + ##### Linked-List Management Functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -1103,7 +1101,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNod #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->SrcSecure)); assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->DestSecure)); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Build the DMA channel node */ DMA_List_BuildNode(pNodeConfig, pNode); @@ -3223,7 +3221,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### Data handling, repeated block and trigger configuration functions ############### + ##### Data handling, repeated block and trigger configuration functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -3450,7 +3448,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, * @verbatim ====================================================================================================================== - ############### Suspend and resume operation functions ############### + ##### Suspend and resume operation functions ##### ====================================================================================================================== [..] This section provides functions allowing to : @@ -3613,7 +3611,7 @@ HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### Fifo status function ############### + ##### Fifo status function ##### ====================================================================================================================== [..] This section provides function allowing to get DMA channel FIFO level. @@ -3735,7 +3733,7 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, { pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC; } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Add parameters related to DMA configuration */ if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) @@ -3970,7 +3968,7 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, { pNodeConfig->DestSecure = DMA_CHANNEL_DEST_NSEC; } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*********************************************************************************** CTR1 fields values are updated */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dsi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dsi.c index 58bb66f4b8..435e9506f7 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dsi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dsi.c @@ -130,7 +130,7 @@ all callbacks are set to the corresponding weak functions: examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_DSI_Init() + reset to the legacy weak (overridden) functions in the HAL_DSI_Init() and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -463,13 +463,6 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI ((PLLInit->PLLIDF) << DSI_WRPCR_PLL_IDF_Pos) | \ ((PLLInit->PLLODF) << DSI_WRPCR_PLL_ODF_Pos)); - /************************ Set D-PHY Band Control registers ******************************/ - /* Set Band Control Frequency and LPX Offset */ - DSI_ConfigBandControl(hdsi); - - /* Set PLL Tuning */ - DSI_SetWrapperPLLTuning(hdsi, PLLInit); - /* Enable the DSI PLL */ __HAL_DSI_PLL_ENABLE(hdsi); @@ -490,24 +483,60 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI } } - /*************************** Set the PHY parameters ***************************/ + __HAL_DSI_ENABLE(hdsi); + + /************************ Set the DSI clock parameters ************************/ + /* Set the TX escape clock division factor */ + hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; + hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; + /*************************** Set the PHY parameters ***************************/ /* D-PHY clock and digital enable*/ - hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); + hdsi->Instance->PCTLR |= DSI_PCTLR_DEN; + + /************************ Set D-PHY Band Control registers ******************************/ + /* Set Band Control Frequency and LPX Offset */ + DSI_ConfigBandControl(hdsi); + + /* Set PLL Tuning */ + DSI_SetWrapperPLLTuning(hdsi, PLLInit); + + hdsi->Instance->PCTLR |= DSI_PCTLR_CKE; - /* Clock lane configuration */ - hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); - hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); /* Configure the number of active data lanes */ hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; - /************************ Set the DSI clock parameters ************************/ + /* Get tick */ + tickstart = HAL_GetTick(); + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | DSI_PSR_PSSC)) + { + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); - /* Set the TX escape clock division factor */ - hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; - hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; + return HAL_TIMEOUT; + } + } + } + else + { + while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | \ + DSI_PSR_PSS1 | DSI_PSR_PSSC)) + { + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } /****************************** Error management *****************************/ @@ -517,6 +546,12 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI hdsi->Instance->IER[1U] = 0U; hdsi->ErrorMsk = 0U; + __HAL_DSI_DISABLE(hdsi); + + /* Clock lane configuration */ + hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); + hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); + /* Initialize the error code */ hdsi->ErrorCode = HAL_DSI_ERROR_NONE; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c index 4eabe7c6a3..b0dcc8edee 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c @@ -253,7 +253,7 @@ static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, * @{ */ static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan); -static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, +static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, const uint8_t *pTxData, uint32_t BufferIndex); /** * @} @@ -3460,7 +3460,7 @@ static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan) * @param BufferIndex index of the buffer to be configured. * @retval none */ -static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, +static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, const uint8_t *pTxData, uint32_t BufferIndex) { uint32_t TxElementW1; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c index b64e538bde..5d437fa35d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c @@ -166,7 +166,7 @@ [..] Use function HAL_FMAC_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID. This function allows to reset following callbacks: @@ -182,10 +182,10 @@ [..] By default, after the HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples GetDataCallback(), OutputDataReadyCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_FMAC_Init() + reset to the legacy weak functions in the HAL_FMAC_Init() and HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_FMAC_Init() and HAL_FMAC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -202,7 +202,7 @@ [..] When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gfxtim.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gfxtim.c index bd09894ed9..f9602cd40b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gfxtim.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gfxtim.c @@ -625,7 +625,7 @@ HAL_StatusTypeDef HAL_GFXTIM_ClockGenerator_Config(GFXTIM_HandleTypeDef *hgfxtim pClockGeneratorConfig->LineClockSrc | pClockGeneratorConfig->FCCHwReloadSrc | pClockGeneratorConfig->FCCClockSrc | pClockGeneratorConfig->FrameClockSrc); - /* Set Tearing Effect (TE) , synchronization signals sources (HSYNC and VSYNC) and debug output config */ + /* Set debug output config for Line and frame clocks */ MODIFY_REG(hgfxtim->Instance->CR, GFXTIM_CR_LCCOE | GFXTIM_CR_FCCOE, pClockGeneratorConfig->LineClockCalib | pClockGeneratorConfig->FrameClockCalib); @@ -892,7 +892,7 @@ HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Reset(GFXTIM_HandleTypeDef *hgfxtim) * @param pValue Absolute time value * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_GetCounter(GFXTIM_HandleTypeDef *hgfxtim, uint32_t AbsoluteTime, +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_GetCounter(const GFXTIM_HandleTypeDef *hgfxtim, uint32_t AbsoluteTime, uint32_t *pValue) { HAL_StatusTypeDef status = HAL_OK; @@ -911,16 +911,16 @@ HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_GetCounter(GFXTIM_HandleTypeDef *hgfx { switch (AbsoluteTime) { - case GFXTIM_ABSOLUTE_GLOBAL_TIME: - *pValue = READ_REG(hgfxtim->Instance->ATR); - break; - case GFXTIM_ABSOLUTE_FRAME_TIME: - *pValue = READ_REG(hgfxtim->Instance->AFCR); - break; - default: - /* GFXTIM_ABSOLUTE_LINE_TIME */ - *pValue = READ_REG(hgfxtim->Instance->ALCR); - break; + case GFXTIM_ABSOLUTE_GLOBAL_TIME: + *pValue = READ_REG(hgfxtim->Instance->ATR); + break; + case GFXTIM_ABSOLUTE_FRAME_TIME: + *pValue = READ_REG(hgfxtim->Instance->AFCR); + break; + default: + /* GFXTIM_ABSOLUTE_LINE_TIME */ + *pValue = READ_REG(hgfxtim->Instance->ALCR); + break; } } else @@ -995,13 +995,13 @@ HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_SetLineCompare(GFXTIM_HandleTypeDef * { switch (AbsoluteLineComparator) { - case GFXTIM_ABSOLUTE_LINE_COMPARE1: - WRITE_REG(hgfxtim->Instance->ALCC1R, Value); - break; + case GFXTIM_ABSOLUTE_LINE_COMPARE1: + WRITE_REG(hgfxtim->Instance->ALCC1R, Value); + break; default: - /* GFXTIM_ABSOLUTE_LINE_COMPARE2 */ - WRITE_REG(hgfxtim->Instance->ALCC2R, Value); - break; + /* GFXTIM_ABSOLUTE_LINE_COMPARE2 */ + WRITE_REG(hgfxtim->Instance->ALCC2R, Value); + break; } } else @@ -1354,7 +1354,7 @@ HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_SetReload(GFXTIM_HandleTypeDef *hgfxt * @param pValue pointer to a relative frame counter value * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_GetCounter(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer, +HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_GetCounter(const GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer, uint32_t *pValue) { HAL_StatusTypeDef status = HAL_OK; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c index ab482de361..7208911bec 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c @@ -246,8 +246,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) /* Configure IO Direction mode (Alternate) */ tmp = p_gpio->MODER; - tmp &= ~(GPIO_MODER_MODE0 << (pin_position * 2U)); - tmp |= ((GPIO_MODE_AF_PP & 0x0FUL) << (pin_position * 2U)); + tmp &= ~(GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); + tmp |= ((GPIO_MODE_AF_PP & 0x0FUL) << (pin_position * GPIO_MODER_MODE1_Pos)); p_gpio->MODER = tmp; } else if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) @@ -259,14 +259,14 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) /* Configure Alternate function mapped with the current IO */ tmp = GPIOx->AFR[position >> 3U]; - tmp &= ~(0x0FUL << ((position & 0x07U) * 4U)); - tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * 4U)); + tmp &= ~(0x0FUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); + tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); GPIOx->AFR[position >> 3U] = tmp; /* Configure IO Direction mode (Alternate) */ tmp = p_gpio->MODER; - tmp &= ~(GPIO_MODER_MODE0 << (pin_position * 2U)); - tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * 2U)); + tmp &= ~(GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); + tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * GPIO_MODER_MODE1_Pos)); p_gpio->MODER = tmp; } else @@ -276,8 +276,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ tmp = p_gpio->MODER; - tmp &= ~(GPIO_MODER_MODE0 << (pin_position * 2U)); - tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * 2U)); + tmp &= ~(GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); + tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * GPIO_MODER_MODE1_Pos)); p_gpio->MODER = tmp; } @@ -290,8 +290,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) /* Configure the IO Speed */ tmp = p_gpio->OSPEEDR; - tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * 2U)); - tmp |= (pGPIO_Init->Speed << (pin_position * 2U)); + tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * GPIO_OSPEEDR_OSPEED1_Pos)); + tmp |= (pGPIO_Init->Speed << (pin_position * GPIO_OSPEEDR_OSPEED1_Pos)); p_gpio->OSPEEDR = tmp; /* Configure the IO Output Type */ @@ -308,8 +308,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) /* Activate the Pull-up or Pull down resistor for the current IO */ tmp = p_gpio->PUPDR; - tmp &= ~(GPIO_PUPDR_PUPD0 << (pin_position * 2U)); - tmp |= ((pGPIO_Init->Pull) << (pin_position * 2U)); + tmp &= ~(GPIO_PUPDR_PUPD0 << (pin_position * GPIO_PUPDR_PUPD1_Pos)); + tmp |= ((pGPIO_Init->Pull) << (pin_position * GPIO_PUPDR_PUPD1_Pos)); p_gpio->PUPDR = tmp; } @@ -318,8 +318,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) { tmp = EXTI->EXTICR[position >> 2U]; - tmp &= ~((0x0FUL) << (8U * (position & 0x03U))); - tmp |= (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U))); + tmp &= ~((0x0FUL) << (EXTI_EXTICR1_EXTI1_Pos * (position & 0x03U))); + tmp |= (GPIO_GET_INDEX(GPIOx) << (EXTI_EXTICR1_EXTI1_Pos * (position & 0x03U))); EXTI->EXTICR[position >> 2U] = tmp; /* Clear Rising Falling edge configuration */ @@ -428,19 +428,19 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO in Analog Mode */ - p_gpio->MODER |= (GPIO_MODER_MODE0 << (pin_position * 2U)); + p_gpio->MODER |= (GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); /* Configure the default Alternate Function in current IO */ - p_gpio->AFR[pin_position >> 3U] &= ~(0x0FUL << ((pin_position & 0x07U) * 4U)); + p_gpio->AFR[pin_position >> 3U] &= ~(0x0FUL << ((pin_position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); /* Configure the default value for IO Speed */ - p_gpio->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * 2U)); + p_gpio->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * GPIO_OSPEEDR_OSPEED1_Pos)); /* Configure the default value IO Output Type */ p_gpio->OTYPER &= ~(GPIO_OTYPER_OT0 << pin_position); /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - p_gpio->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (pin_position * 2U)); + p_gpio->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (pin_position * GPIO_PUPDR_PUPD1_Pos)); } position++; @@ -916,7 +916,7 @@ HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uin /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin) && (GPIO_Pin != GPIO_PIN_ALL)); + assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin)); /* Check null pointer */ if (pPinAttributes == NULL) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c index e59b2237ac..067f1133d5 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c @@ -1836,8 +1836,11 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB { uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; + uint8_t tmp1; + uint8_t tmp2; + uint8_t tmp3; - for (buffercounter = 0U; buffercounter < Size; buffercounter += 4U) + for (buffercounter = 0U; buffercounter < (Size / 4U); buffercounter++) { /* Write input data 4 bytes at a time */ HASH->DIN = *(uint32_t *)inputaddr; @@ -1845,10 +1848,10 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter + 4U) < Size)) + if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && (((buffercounter * 4U) + 4U) < Size)) { /* wait for flag BUSY not set before Wait for DINIS = 1*/ - if (buffercounter >= 64U) + if ((buffercounter * 4U) >= 64U) { if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { @@ -1869,14 +1872,14 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB /* Save current reading and writing locations of Input and Output buffers */ hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hhash->HashInCount = Size - (buffercounter + 4U); + hhash->HashInCount = Size - ((buffercounter * 4U) + 4U); } else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) { /* Save current reading and writing locations of Input and Output buffers */ hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hhash->HashKeyCount = Size - (buffercounter + 4U); + hhash->HashKeyCount = Size - ((buffercounter * 4U) + 4U); } else { @@ -1895,6 +1898,50 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB } /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */ /* At this point, all the data have been entered to the Peripheral: exit */ + + if ((Size % 4U) != 0U) + { + if (hhash->Init.DataType == HASH_DATATYPE_16B) + { + /* Write remaining input data */ + + if ((Size % 4U) <= 2U) + { + HASH->DIN = (uint32_t) * (uint16_t *)inputaddr; + } + if ((Size % 4U) == 3U) + { + HASH->DIN = *(uint32_t *)inputaddr; + } + + } + else if ((hhash->Init.DataType == HASH_DATATYPE_8B) + || (hhash->Init.DataType == HASH_DATATYPE_1B)) /* byte swap or bit swap or */ + { + /* Write remaining input data */ + if ((Size % 4U) == 1U) + { + HASH->DIN = (uint32_t) * (uint8_t *)inputaddr; + } + if ((Size % 4U) == 2U) + { + HASH->DIN = (uint32_t) * (uint16_t *)inputaddr; + } + if ((Size % 4U) == 3U) + { + tmp1 = *(uint8_t *)inputaddr; + tmp2 = *(((uint8_t *)inputaddr) + 1U); + tmp3 = *(((uint8_t *)inputaddr) + 2U); + HASH->DIN = ((uint32_t)tmp1) | ((uint32_t)tmp2 << 8U) | ((uint32_t)tmp3 << 16U); + } + } + else + { + HASH->DIN = *(uint32_t *)inputaddr; + } + } + + return HAL_OK; } @@ -2942,13 +2989,13 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u } } /* if (polling_step == 1) */ else - { + { /* otherwise, carry on in interrupt-mode */ hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data to be fed to the Peripheral */ hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at the next interruption */ - } + } /* Process Unlock */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c index 4f1749c928..009b208791 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c @@ -110,9 +110,9 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); */ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) { -#if defined (STM32U575xx) || defined (STM32U585xx) - USB_OTG_GlobalTypeDef *USBx; -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ +#if defined (USB_OTG_FS) + const USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ /* Check the HCD handle allocation */ if (hhcd == NULL) @@ -123,9 +123,9 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) /* Check the parameters */ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); -#if defined (STM32U575xx) || defined (STM32U585xx) +#if defined (USB_OTG_FS) USBx = hhcd->Instance; -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ +#endif /* defined (USB_OTG_FS) */ if (hhcd->State == HAL_HCD_STATE_RESET) { @@ -154,24 +154,38 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) } hhcd->State = HAL_HCD_STATE_BUSY; -#if defined (STM32U575xx) || defined (STM32U585xx) + +#if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ - if ((USBx->CID & (0x1U << 14)) == 0U) + if (USBx == USB_OTG_FS) { hhcd->Init.dma_enable = 0U; } -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ +#endif /* defined (USB_OTG_FS) */ + /* Disable the Interrupts */ __HAL_HCD_DISABLE(hhcd); /* Init the Core (common init.) */ - (void)USB_CoreInit(hhcd->Instance, hhcd->Init); + if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } - /* Force Host Mode*/ - (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE); + /* Force Host Mode */ + if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } /* Init Host */ - (void)USB_HostInit(hhcd->Instance, hhcd->Init); + if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } hhcd->State = HAL_HCD_STATE_READY; @@ -1255,7 +1269,7 @@ HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_nu */ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1574,7 +1588,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) */ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; uint32_t num_packets; @@ -1809,7 +1823,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) */ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t pktsts; uint32_t pktcnt; @@ -1875,7 +1889,7 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) */ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0; __IO uint32_t hprt0_dup; @@ -2073,9 +2087,6 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) /* Init Host */ (void)USB_HostInit(hhcd->Instance, hhcd->Init); - /* Deactivate the power down */ - hhcd->Instance->CNTR &= ~USB_CNTR_PDWN; - hhcd->State = HAL_HCD_STATE_READY; /* Host Port State */ @@ -2123,6 +2134,27 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, __HAL_LOCK(hhcd); + if (ch_num > 16U) + { + __HAL_UNLOCK(hhcd); + return HAL_ERROR; + } + + if (((epnum & 0xFU)== 0U) && ((hhcd->ep0_PmaAllocState & 0xF000U) != 0U)) + { + hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[0U].pmaadress; + hhcd->hc[ch_num & 0xFU].pmaaddr0 = hhcd->hc[0U].pmaaddr0; + hhcd->hc[ch_num & 0xFU].pmaaddr1 = hhcd->hc[0U].pmaaddr1; + + hhcd->phy_chin_state[0U] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + + hhcd->phy_chout_state[0U] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + } + /* Check if the logical channel are already allocated */ used_channel = HAL_HCD_Check_usedChannel(hhcd, ch_num); @@ -2135,6 +2167,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, /* No free Channel available, return error */ if (hhcd->hc[ch_num & 0xFU].phy_ch_num == HCD_FREE_CH_NOT_FOUND) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } @@ -2171,6 +2204,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } @@ -2189,6 +2223,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } @@ -2206,22 +2241,28 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } else { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } else { + /* This is a dual EP0 PMA allocation */ + hhcd->ep0_PmaAllocState |= (0x1U << 12); + /* PMA Dynamic Allocation for EP0 OUT direction */ hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR; status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U); if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } @@ -2231,6 +2272,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } @@ -2256,6 +2298,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (status == HAL_ERROR) { + __HAL_UNLOCK(hhcd); return HAL_ERROR; } } @@ -2634,8 +2677,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { uint8_t phy_chnum; - uint8_t chnum; - uint32_t epch_reg; + uint8_t ch_dir; uint32_t wIstr = USB_ReadInterrupts(hhcd->Instance); /* Port Change Detected (Connection/Disconnection) */ @@ -2653,50 +2695,21 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) /* Correct Transaction Detected -------*/ if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR) { - /* Handle Host channel Interrupt */ - for (phy_chnum = 0U; phy_chnum < hhcd->Init.Host_channels; phy_chnum++) - { - if ((HCD_GET_CHANNEL(hhcd->Instance, phy_chnum) & USB_CH_VTRX) != 0U) - { - /* Get Logical channel to check if the channel is already opened */ - chnum = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 1U); - - if (chnum != HCD_LOGICAL_CH_NOT_OPENED) - { - /* Call Channel_IN_IRQ() */ - HCD_HC_IN_IRQHandler(hhcd, chnum); - } - else - { - /*Channel was not closed correctly still have interrupt */ - epch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum); - epch_reg = (epch_reg & (USB_CHEP_REG_MASK & (~USB_CH_ERRRX) & (~USB_CH_VTRX))) | - (USB_CH_VTTX | USB_CH_ERRTX); - - HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, epch_reg); - } - } + /* Get Physical channel */ + phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd); - if ((HCD_GET_CHANNEL(hhcd->Instance, phy_chnum) & USB_CH_VTTX) != 0U) - { - /* Get Logical channel to check if the channel is already opened */ - chnum = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 0U); + /* Get channel direction */ + ch_dir = (uint8_t)__HAL_HCD_GET_CHDIR(hhcd); - if (chnum != HCD_LOGICAL_CH_NOT_OPENED) - { - /*Call Channel_OUT_IRQ()*/ - HCD_HC_OUT_IRQHandler(hhcd, chnum); - } - else - { - /* Clear Error & unwanted VTTX or Channel was not closed correctly */ - epch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum); - epch_reg = (epch_reg & (USB_CHEP_REG_MASK & (~USB_CH_ERRTX) & (~USB_CH_VTTX))) | - (USB_CH_VTRX | USB_CH_ERRRX); - - HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, epch_reg); - } - } + if (ch_dir == CH_OUT_DIR) + { + /* Call Channel_OUT_IRQ() */ + HCD_HC_OUT_IRQHandler(hhcd, phy_chnum); + } + else + { + /* Call Channel_IN_IRQ() */ + HCD_HC_IN_IRQHandler(hhcd, phy_chnum); } return; @@ -3196,16 +3209,21 @@ transfers. */ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) { + __IO uint32_t count = HCD_PDWN_EXIT_CNT; + __HAL_LOCK(hhcd); - /*Set the PullDown on the PHY */ - hhcd->Instance->BCDR |= USB_BCDR_DPPD; + /* Remove PowerDown */ + hhcd->Instance->CNTR &= ~USB_CNTR_PDWN; - /* Clear Reset */ - hhcd->Instance->CNTR &= ~USB_CNTR_USBRST; + /* Few cycles to ensure exit from powerdown */ + while (count > 0U) + { + count--; + } - /*Remove PowerDown */ - hhcd->Instance->CNTR &= ~USB_CNTR_PDWN; + /* Clear Reset */ + hhcd->Instance->CNTR &= ~USB_CNTR_USBRST; __HAL_UNLOCK(hhcd); @@ -3251,7 +3269,7 @@ HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd) /* wait for Suspend Ready */ while ((hhcd->Instance->CNTR & USB_CNTR_SUSPRDY) == 0U) { - if (++count > 0xFFFFFFU) + if (++count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -3486,7 +3504,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) { /* manage multiple Xfer */ - hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; /* check if we need to free user buffer */ if ((regvalue & USB_CH_DTOG_RX) != 0U) @@ -3525,7 +3543,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, else { /* Transfer complete state */ - hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; hhcd->hc[ch_num & 0xFU].state = HC_XFRC; hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; @@ -3547,7 +3565,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) { /* manage multiple Xfer */ - hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; /* check if we need to free user buffer */ if ((regvalue & USB_CH_DTOG_RX) == 0U) @@ -3588,7 +3606,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, else { /* Transfer complete state */ - hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; hhcd->hc[ch_num & 0xFU].state = HC_XFRC; hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; @@ -3762,16 +3780,17 @@ static void inline HCD_HC_IN_ISO(HCD_HandleTypeDef *hhcd, uint8_t ch_num, /** * @brief Handle Host Channel IN interrupt requests. * @param hhcd HCD handle - * @param ch_num Channel number - * This parameter can be a value from 1 to 15 + * @param chnum Channel number + * This parameter can be a value from 1 to 8 * @retval none */ -static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { uint16_t received_bytes; - uint8_t phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd); + uint8_t phy_chnum = chnum; + uint8_t ch_num = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 1U); - /*Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control and status */ + /* Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control and status */ uint32_t ch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum); /* Manage Correct Transaction */ @@ -3837,6 +3856,12 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num) hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY; hhcd->hc[ch_num & 0xFU].ErrCnt = 0U; hhcd->hc[ch_num & 0xFU].state = HC_NAK; + + if (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR) + { + /* Close the channel */ + HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS); + } } /* manage STALL Response */ else if ((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_STALL) @@ -3906,16 +3931,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num) * @brief Handle Host Channel OUT interrupt requests. * @param hhcd HCD handle * @param chnum Channel number - * This parameter can be a value from 1 to 15 + * This parameter can be a value from 1 to 8 * @retval none */ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - uint16_t data_xfr; __IO uint32_t WregCh; + uint16_t data_xfr; + uint8_t phy_chnum = chnum; - /* Get Physical Channel number */ - uint32_t phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd); + /* Get Virtual Channel number */ + uint8_t ch_num = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 0U); /* Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control &status */ uint32_t ch_reg = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum); @@ -3953,8 +3979,8 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ /* Transfer complete state */ - hhcd->hc[chnum & 0xFU].state = HC_XFRC; - hhcd->hc[chnum & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; } /*Clear Correct Transfer */ @@ -3962,9 +3988,9 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /*TX COMPLETE*/ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } @@ -3975,36 +4001,36 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + phy_chnum)->TXBD & 0x03FF0000U) >> 16U); - if (hhcd->hc[chnum & 0xFU].xfer_len >= data_xfr) + if (hhcd->hc[ch_num & 0xFU].xfer_len >= data_xfr) { - hhcd->hc[chnum & 0xFU].xfer_len -= data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_len -= data_xfr; } else { - hhcd->hc[chnum & 0xFU].xfer_len = 0U; + hhcd->hc[ch_num & 0xFU].xfer_len = 0U; } /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */ - if (hhcd->hc[chnum & 0xFU].xfer_len != 0U) + if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) { /* manage multiple Xfer */ - hhcd->hc[chnum & 0xFU].xfer_buff += data_xfr; - hhcd->hc[chnum & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_buff += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; /* start a new transfer */ - (void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[chnum & 0xFU]); + (void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num & 0xFU]); } else { /* Transfer complete */ - hhcd->hc[chnum & 0xFU].xfer_count += data_xfr; - hhcd->hc[chnum & 0xFU].state = HC_XFRC; - hhcd->hc[chnum & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; - if ((hhcd->hc[chnum & 0xFU].ep_type == EP_TYPE_BULK) || - (hhcd->hc[chnum & 0xFU].ep_type == EP_TYPE_INTR)) + if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || + (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) { - hhcd->hc[chnum & 0xFU].toggle_out ^= 1U; + hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; } } } @@ -4013,9 +4039,9 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_NAK)) { /* Update Channel status */ - hhcd->hc[chnum & 0xFU].state = HC_NAK; - hhcd->hc[chnum & 0xFU].urb_state = URB_NOTREADY; - hhcd->hc[chnum & 0xFU].ErrCnt = 0U; + hhcd->hc[ch_num & 0xFU].state = HC_NAK; + hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY; + hhcd->hc[ch_num & 0xFU].ErrCnt = 0U; /* Get Channel register value */ WregCh = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum); @@ -4026,28 +4052,28 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /* Update channel register Value */ HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, WregCh); - if (hhcd->hc[chnum & 0xFU].doublebuffer == 0U) + if (hhcd->hc[ch_num & 0xFU].doublebuffer == 0U) { #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } } /* Check STALL Response */ else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_STALL) { - (void) HAL_HCD_HC_Halt(hhcd, (uint8_t)chnum); - hhcd->hc[chnum & 0xFU].state = HC_STALL; - hhcd->hc[chnum & 0xFU].urb_state = URB_STALL; + (void) HAL_HCD_HC_Halt(hhcd, (uint8_t)ch_num); + hhcd->hc[ch_num & 0xFU].state = HC_STALL; + hhcd->hc[ch_num & 0xFU].urb_state = URB_STALL; } #if (USE_USB_DOUBLE_BUFFER == 1U) /* Check double buffer ACK in case of bulk transaction */ else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_ACK_DBUF) { /* Double buffer management Bulk Out */ - (void) HCD_HC_OUT_BulkDb(hhcd, chnum, (uint8_t)phy_chnum, ch_reg); + (void) HCD_HC_OUT_BulkDb(hhcd, ch_num, (uint8_t)phy_chnum, ch_reg); } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ else @@ -4058,38 +4084,38 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((ch_reg & USB_CH_TX_STTX) != USB_CH_TX_NAK) { #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } HCD_CLEAR_TX_CH_CTR(hhcd->Instance, phy_chnum); - } /* end no isochronous */ + } /* End no isochronous */ } /*------ Manage Transaction Error------*/ else { - hhcd->hc[chnum & 0xFU].ErrCnt++; - if (hhcd->hc[chnum & 0xFU].ErrCnt > 3U) + hhcd->hc[ch_num & 0xFU].ErrCnt++; + if (hhcd->hc[ch_num & 0xFU].ErrCnt > 3U) { HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS); - hhcd->hc[chnum & 0xFU].urb_state = URB_ERROR; + hhcd->hc[ch_num & 0xFU].urb_state = URB_ERROR; } else { - hhcd->hc[chnum & 0xFU].urb_state = URB_NOTREADY; + hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY; } - hhcd->hc[chnum & 0xFU].state = HC_XACTERR; + hhcd->hc[ch_num & 0xFU].state = HC_XACTERR; - /*Clear ERR_TX*/ + /* Clear ERR_TX */ HCD_CLEAR_TX_CH_ERR(hhcd->Instance, phy_chnum); #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } } @@ -4525,7 +4551,7 @@ HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num, /* Get a FreePMA Address */ pma_addr0 = HAL_HCD_GetFreePMA(hhcd, mps); - /* if there is no free space to allocate */ + /* If there is no free space to allocate */ if (pma_addr0 == 0xFFFFU) { return HAL_ERROR; @@ -4540,7 +4566,8 @@ HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num, if (hc->ep_num == 0U) { - hhcd->ep0_PmaAllocState = ch_num; + hhcd->ep0_PmaAllocState &= 0xFFF0U; + hhcd->ep0_PmaAllocState |= ch_num; hhcd->ep0_PmaAllocState |= (1U << 8); } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c index a6d02d7f87..31582a2dd2 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c @@ -90,7 +90,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -156,7 +156,7 @@ HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() @@ -214,7 +214,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -1363,6 +1363,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData uint32_t Timeout) { uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1389,14 +1391,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - /* Preload TX data if no stretch enable */ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) { @@ -1410,6 +1404,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->XferCount--; } + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); @@ -1421,6 +1427,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1433,6 +1443,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1456,31 +1470,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until AF flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + + tmpXferCount = hi2c->XferCount; + if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + { + /* Reset ErrorCode to NONE */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } } + else + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } - return HAL_ERROR; + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { @@ -2911,6 +2942,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ + hi2c->XferSize = 0U; hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; @@ -3512,22 +3544,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials == Trials) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - /* Increment Trials */ I2C_Trials++; } while (I2C_Trials < Trials); @@ -4834,7 +4850,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) } /** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value @@ -4843,7 +4859,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { - if (hi2c->Mode == HAL_I2C_MODE_MASTER) + HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -5509,9 +5527,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); } - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5940,9 +5957,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } - - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -6544,14 +6560,14 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hi2c->XferOptions; HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Disable Interrupts and Store Previous state */ - if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (tmpstate == HAL_I2C_STATE_LISTEN)) + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; @@ -6561,6 +6577,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; } + else if (tmpstate == HAL_I2C_STATE_LISTEN) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_NONE; + } else { /* Do nothing */ @@ -6629,6 +6650,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -7217,6 +7289,12 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { @@ -7328,16 +7406,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + status = HAL_ERROR; } /* Check if a STOPF is detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) { /* Check if an RXNE is pending */ /* Store Last receive data if any */ @@ -7345,19 +7425,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { /* Return HAL_OK */ /* The Reading of data from RXDR will be done in caller function */ - return HAL_OK; + status = HAL_OK; } - else + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -7371,12 +7446,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; } } /* Check for the Timeout */ - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) { @@ -7386,11 +7465,11 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; } } } - return HAL_OK; + return status; } /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c index 4b423e08c5..f0741fcceb 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c @@ -45,30 +45,35 @@ The ICACHE HAL driver can be used as follows: (#) Optionally configure the Instruction Cache mode with - @ref HAL_ICACHE_ConfigAssociativityMode() if the default configuration + HAL_ICACHE_ConfigAssociativityMode() if the default configuration does not suit the application requirements. (#) Enable and disable the Instruction Cache with respectively - @ref HAL_ICACHE_Enable() and @ref HAL_ICACHE_Disable(). - Use @ref HAL_ICACHE_IsEnabled() to get the Instruction Cache status. + HAL_ICACHE_Enable() and HAL_ICACHE_Disable(). + Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status. + To ensure a deterministic cache behavior after power on, system reset or after + a call to @ref HAL_ICACHE_Disable(), the application must call + @ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset + or cache disable, an automatic cache invalidation procedure is launched and the + cache is bypassed until the operation completes. (#) Initiate the cache maintenance invalidation procedure with either - @ref HAL_ICACHE_Invalidate() (blocking mode) or @ref HAL_ICACHE_Invalidate_IT() + HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT() (interrupt mode). When interrupt mode is used, the callback function - @ref HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate - procedure is complete. The function @ref HAL_ICACHE_WaitForInvalidateComplete() + HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate + procedure is complete. The function HAL_ICACHE_WaitForInvalidateComplete() may be called to wait for the end of the invalidate procedure automatically - initiated when disabling the Instruction Cache with @ref HAL_ICACHE_Disable(). + initiated when disabling the Instruction Cache with HAL_ICACHE_Disable(). The cache operation is bypassed during the invalidation procedure. (#) Use the performance monitoring counters for Hit and Miss with the following - functions: @ref HAL_ICACHE_Monitor_Start(), @ref HAL_ICACHE_Monitor_Stop(), - @ref HAL_ICACHE_Monitor_Reset(), @ref HAL_ICACHE_Monitor_GetHitValue() and - @ref HAL_ICACHE_Monitor_GetMissValue() + functions: HAL_ICACHE_Monitor_Start(), HAL_ICACHE_Monitor_Stop(), + HAL_ICACHE_Monitor_Reset(), HAL_ICACHE_Monitor_GetHitValue() and + HAL_ICACHE_Monitor_GetMissValue() (#) Enable and disable up to four regions to remap input address from external memories to the internal Code region for execution with - @ref HAL_ICACHE_EnableRemapRegion() and @ref HAL_ICACHE_DisableRemapRegion() + HAL_ICACHE_EnableRemapRegion() and HAL_ICACHE_DisableRemapRegion() @endverbatim */ @@ -84,7 +89,7 @@ * @brief HAL ICACHE module driver * @{ */ -#ifdef HAL_ICACHE_MODULE_ENABLED +#if defined(ICACHE) && defined (HAL_ICACHE_MODULE_ENABLED) /* Private typedef -----------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -183,32 +188,32 @@ HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode) /** * @brief DeInitialize the Instruction Cache. - * @retval HAL status (HAL_OK/HAL_TIMEOUT) + * @retval HAL status (HAL_OK) */ HAL_StatusTypeDef HAL_ICACHE_DeInit(void) { - HAL_StatusTypeDef status; + /* Reset interrupt enable value */ + WRITE_REG(ICACHE->IER, 0U); - /* Disable cache with reset value for 2-ways set associative mode */ + /* Clear any pending flags */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); + + /* Disable cache then set default associative mode value */ + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL); /* Stop monitor and reset monitor values */ - (void)HAL_ICACHE_Monitor_Stop(ICACHE_MONITOR_HIT_MISS); - (void)HAL_ICACHE_Monitor_Reset(ICACHE_MONITOR_HIT_MISS); + CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS); + SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); + CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); - /* No remapped regions */ - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_0); - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_1); - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_2); - (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_3); + /* Reset regions configuration values */ + WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); - /* Wait for end of invalidate cache procedure */ - status = HAL_ICACHE_WaitForInvalidateComplete(); - - /* Clear any pending flags */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); - - return status; + return HAL_OK; } /** @@ -281,22 +286,15 @@ HAL_StatusTypeDef HAL_ICACHE_Invalidate(void) { HAL_StatusTypeDef status; - /* Check no ongoing operation */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) - { - status = HAL_ERROR; - } - else + /* Check if no ongoing operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U) { - /* Make sure BSYENDF is reset before to start cache invalidation */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - /* Launch cache invalidation */ SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); - - status = HAL_ICACHE_WaitForInvalidateComplete(); } + status = HAL_ICACHE_WaitForInvalidateComplete(); + return status; } @@ -642,7 +640,7 @@ HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region) * @} */ -#endif /* HAL_ICACHE_MODULE_ENABLED */ +#endif /* ICACHE && HAL_ICACHE_MODULE_ENABLED */ /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c index 4dbf8f7b40..6f6cac1fcc 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c @@ -78,7 +78,7 @@ (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI clock is forced ON and IWDG counter starts counting down. (++) Enable write access to configuration registers: - IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR. + IWDG_PR, IWDG_RLR, IWDG_WINR, IWDG_EWCR. (++) Configure the IWDG prescaler and counter reload value. This reload value will be loaded in the IWDG counter each time the watchdog is reloaded, then the IWDG will start counting down from this value. @@ -216,7 +216,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) /* Enable IWDG. LSI is turned on automatically */ __HAL_IWDG_START(hiwdg); - /* Enable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers by writing + /* Enable write access to IWDG_PR, IWDG_RLR, IWDG_WINR, IWDG_EWCR registers by writing 0x5555 in KR */ IWDG_ENABLE_WRITE_ACCESS(hiwdg); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_jpeg.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_jpeg.c index 60df3c1b3b..73de85eb06 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_jpeg.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_jpeg.c @@ -452,12 +452,12 @@ static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeD JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable); static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable); -static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, +static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(const JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, const __IO uint32_t *DCTableAddress); -static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, +static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(const JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, const __IO uint32_t *ACTableAddress); static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg); -static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg); +static void JPEG_Set_Huff_DHTMem(const JPEG_HandleTypeDef *hjpeg); static uint32_t JPEG_Set_Quantization_Mem(const JPEG_HandleTypeDef *hjpeg, const uint8_t *QTable, __IO uint32_t *QTableAddress); static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg); @@ -1126,7 +1126,7 @@ HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg * the encoding configuration * @retval HAL status */ -HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf) +HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, const JPEG_ConfTypeDef *pConf) { uint32_t error; uint32_t numberMCU; @@ -2713,7 +2713,7 @@ static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeD * @param DCTableAddress Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1. * @retval HAL status */ -static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, +static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(const JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, const __IO uint32_t *DCTableAddress) { HAL_StatusTypeDef error; @@ -2776,7 +2776,7 @@ static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCH * @param ACTableAddress Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1. * @retval HAL status */ -static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, +static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(const JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, const __IO uint32_t *ACTableAddress) { HAL_StatusTypeDef error; @@ -2895,12 +2895,12 @@ static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg) * the configuration information for JPEG module * @retval None */ -static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg) +static void JPEG_Set_Huff_DHTMem(const JPEG_HandleTypeDef *hjpeg) { - JPEG_ACHuffTableTypeDef *HuffTableAC0 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACLUM_HuffTable; - JPEG_ACHuffTableTypeDef *HuffTableAC1 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACCHROM_HuffTable; - JPEG_DCHuffTableTypeDef *HuffTableDC0 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCLUM_HuffTable; - JPEG_DCHuffTableTypeDef *HuffTableDC1 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCCHROM_HuffTable; + const JPEG_ACHuffTableTypeDef *HuffTableAC0 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACLUM_HuffTable; + const JPEG_ACHuffTableTypeDef *HuffTableAC1 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACCHROM_HuffTable; + const JPEG_DCHuffTableTypeDef *HuffTableDC0 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCLUM_HuffTable; + const JPEG_DCHuffTableTypeDef *HuffTableDC1 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCCHROM_HuffTable; uint32_t value; uint32_t index; __IO uint32_t *address; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ltdc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ltdc.c index f5c1a72385..5aa13bc818 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ltdc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ltdc.c @@ -916,11 +916,12 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize, + uint32_t LayerIdx) { uint32_t tmp; uint32_t counter; - uint32_t *pcolorlut = pCLUT; + const uint32_t *pcolorlut = pCLUT; /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); @@ -2092,7 +2093,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 * the configuration information for the LTDC. * @retval HAL state */ -HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc) { return hltdc->State; } @@ -2103,7 +2104,7 @@ HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) * the configuration information for the LTDC. * @retval LTDC Error Code */ -uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) +uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc) { return hltdc->ErrorCode; } @@ -2154,9 +2155,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); tmp2 = (pLayerCfg->Alpha0 << 24U); - LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | - LTDC_LxDCCR_DCALPHA); - LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); + WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->DCCR, (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2)); /* Specifies the constant alpha value */ LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); @@ -2167,8 +2166,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); /* Configure the color frame buffer start address */ - LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); - LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); + WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CFBAR, pLayerCfg->FBStartAdress); if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c index 23558b5f4b..634c867967 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c @@ -56,7 +56,6 @@ (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization - *** MMC Card Initialization and configuration *** ================================================ [..] @@ -93,6 +92,7 @@ (#) Select the corresponding MMC Card according to the address read with the step 2. (#) Configure the MMC Card in wide bus mode: 4-bits data. + (#) Select the MMC Card partition using HAL_MMC_SwitchPartition() *** MMC Card Read operation *** ============================== @@ -169,6 +169,64 @@ (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register. Some of the CID parameters are useful for card initialization and identification. + *** MMC Card Reply Protected Memory Block (RPMB) Key Programming operation *** + ============================== + [..] + (+) You can program the authentication key of RPMB area in polling mode by using function + HAL_MMC_RPMB_ProgramAuthenticationKey(). + This function is only used once during the life of an MMC card. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + (+) You can program the authentication key of RPMB area in Interrupt mode by using function + HAL_MMC_RPMB_ProgramAuthenticationKey_IT(). + This function is only used once during the life of an MMC card. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + + *** MMC Card Reply Protected Memory Block (RPMB) write counter operation *** + ============================== + [..] + (+) You can get the write counter value of RPMB area in polling mode by using function + HAL_MMC_RPMB_GetWriteCounter(). + (+) You can get the write counter value of RPMB area in Interrupt mode by using function + HAL_MMC_RPMB_GetWriteCounter_IT(). + + *** MMC Card Reply Protected Memory Block (RPMB) write operation *** + ============================== + [..] + (+) You can write to the RPMB area of MMC card in polling mode by using function + HAL_MMC_WriteBlocks(). + This function supports the one, two, or thirty two blocks write operation + (with 512-bytes block length). + You can choose the number of blocks at the multiple block read operation by adjusting + the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + (+) You can write to the RPMB area of MMC card in Interrupt mode by using function + HAL_MMC_WriteBlocks_IT(). + This function supports the one, two, or thirty two blocks write operation + (with 512-bytes block length). + You can choose the number of blocks at the multiple block read operation by adjusting + the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + + *** MMC Card Reply Protected Memory Block (RPMB) read operation *** + ============================== + [..] + (+) You can read from the RPMB area of MMC card in polling mode by using function + HAL_MMC_RPMB_ReadBlocks(). + The block size should be chosen as multiple of 512 bytes. + You can choose the number of blocks by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for MMC card state. + (+) You can read from the RPMB area of MMC card in Interrupt mode by using function + HAL_MMC_RPMB_ReadBlocks_IT(). + The block size should be chosen as multiple of 512 bytes. + You can choose the number of blocks by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for MMC card state. + *** MMC HAL driver macros list *** ================================== [..] @@ -290,6 +348,11 @@ #define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */ #define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */ +/* The Data elements' postitions in the frame Frame for RPMB area */ +#define MMC_RPMB_KEYMAC_POSITION 196U +#define MMC_RPMB_DATA_POSITION 228U +#define MMC_RPMB_NONCE_POSITION 484U +#define MMC_RPMB_WRITE_COUNTER_POSITION 500U /** * @} */ @@ -536,7 +599,6 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) return HAL_OK; } - /** * @brief Initializes the MMC MSP. * @param hmmc: Pointer to MMC handle @@ -3524,7 +3586,6 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc) * @{ */ - /** * @brief Initializes the mmc card. * @param hmmc: Pointer to MMC handle @@ -3608,7 +3669,6 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) hmmc->ErrorCode |= errorstate; } - /* Get Extended CSD parameters */ if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK) { @@ -3858,7 +3918,6 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) tmp = hmmc->pRxBuffPtr; - if (hmmc->RxXferSize >= SDMMC_FIFO_SIZE) { /* Read data from SDMMC Rx FIFO */ @@ -4239,6 +4298,1554 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3 return errorstate; } +/** + * @brief Used to select the partition. + * @param hmmc: Pointer to MMC handle + * @param Partition: Partition type + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition) +{ + uint32_t errorstate; + uint32_t response = 0U; + uint32_t count; + uint32_t tickstart = HAL_GetTick(); + uint32_t arg = Partition | 0x03B30000U; + + /* Check the state of the driver */ + if (hmmc->State == HAL_MMC_STATE_READY) + { + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Index : 179 - Value : partition */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, arg); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT) + { + errorstate = HAL_MMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Manage errors */ + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + + if (errorstate != HAL_MMC_ERROR_TIMEOUT) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + else + { + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Allows to program the authentication key within the RPMB partition + * @param hmmc: Pointer to MMC handle + * @param pKey: pointer to the authentication key (32 bytes) + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint32_t dataremaining; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + const uint8_t *rtempbuff; + uint8_t *tempbuff; + + tail_pack[11] = 0x01; + + if (NULL == pKey) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x80000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + rtempbuff = zero_pack; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_KEYMAC_POSITION) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_KEYMAC_POSITION) + { + rtempbuff = pKey; + } + else if ((byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) && \ + (byte_count >= MMC_RPMB_DATA_POSITION)) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packet */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + byte_count = 0; + + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + /* Check result of operation */ + if ((tail_pack[9] != 0x00U) || (tail_pack[10] != 0x01U)) + { + hmmc->RPMBErrorCode |= tail_pack[9]; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to get the value of write counter within the RPMB partition. + * @param hmmc: Pointer to MMC handle + * @param Nonce: pointer to the value of nonce (16 bytes) + * @param Timeout: Specify timeout value + * @retval write counter value. + */ +uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint32_t dataremaining; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + uint8_t echo_nonce[16] = {0}; + uint8_t *tempbuff = zero_pack; + + tail_pack[11] = 0x02; + + if (NULL == pNonce) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Send Request Packet */ + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*tempbuff); + tempbuff++; + byte_count++; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + byte_count++; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + byte_count++; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = (uint8_t *)pNonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packt */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + + byte_count = 0; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = echo_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + for (uint8_t i = 0; i < 16U; i++) + { + if (pNonce[i] != echo_nonce[i]) + { + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + } + + return ((uint32_t)tail_pack[3] | ((uint32_t)tail_pack[2] << 8) | ((uint32_t)tail_pack[1] << 16) | \ + ((uint32_t)tail_pack[0] << 24)); + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } +} + +/** + * @brief Allows to write block(s) to a specified address in the RPMB partition. The Data + * transfer is managed by polling mode. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @param pMAC: Pointer to the authentication MAC buffer + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout) +{ + + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint32_t dataremaining; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + uint8_t echo_nonce[16] = {0}; + const uint8_t local_nonce[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x00, 0x01, 0x02, + 0x03, 0x04, 0x00, 0x01, 0x02, 0x03, 0x04, 0x08 + }; + const uint8_t *rtempbuff; + uint8_t *tempbuff; + uint32_t arg = 0x80000000U; + uint32_t offset = 0; + + if ((NumberOfBlocks != 0x1U) && (NumberOfBlocks != 0x2U) && (NumberOfBlocks != 0x20U)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if ((NULL == pData) || (NULL == pMAC)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + tail_pack[11] = 0x02; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send Request Packet */ + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + rtempbuff = zero_pack; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + rtempbuff = local_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packt */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + + byte_count = 0; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = echo_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + for (uint8_t i = 0; i < 16U; i++) + { + if (local_nonce[i] != echo_nonce[i]) + { + return HAL_ERROR; + } + } + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } + tail_pack[11] = 0x03; + tail_pack[10] = 0x00; + tail_pack[7] = (uint8_t)(NumberOfBlocks) & 0xFFU; + tail_pack[6] = (uint8_t)(NumberOfBlocks >> 8) & 0xFFU; + tail_pack[5] = (uint8_t)(BlockAdd) & 0xFFU; + tail_pack[4] = (uint8_t)(BlockAdd >> 8) & 0xFFU; + + rtempbuff = zero_pack; + byte_count = 0; + arg |= NumberOfBlocks; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send Request Packet */ + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count == MMC_RPMB_KEYMAC_POSITION) + { + rtempbuff = pMAC; + } + if (byte_count == MMC_RPMB_DATA_POSITION) + { + rtempbuff = &pData[offset]; + } + if ((byte_count >= MMC_RPMB_NONCE_POSITION) && \ + (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION)) + { + rtempbuff = zero_pack; + } + if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else if (byte_count == MMC_BLOCKSIZE) + { + offset += (uint32_t)256U; + byte_count = 0; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Response Packet */ + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + + { + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + byte_count = 0; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + /* Check result of operation */ + if (((tail_pack[9] & (uint8_t)0xFEU) != 0x00U) || (tail_pack[10] != 0x03U)) + { + hmmc->RPMBErrorCode |= tail_pack[9]; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to read block(s) to a specified address in the RPMB partition. The Data + * transfer is managed by polling mode. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @param pNonce: Pointer to the buffer that will contain the nonce to transmit + * @param pMAC: Pointer to the authentication MAC buffer + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC, + uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + uint8_t echo_nonce[16] = {0}; + uint32_t dataremaining; + const uint8_t *rtempbuff; + uint8_t *tempbuff; + uint32_t arg = 0; + uint32_t offset = 0; + + arg |= NumberOfBlocks; + + tail_pack[11] = 0x04; + tail_pack[10] = 0x00; + tail_pack[7] = 0x00; + tail_pack[6] = 0x00; + tail_pack[5] = (uint8_t)(BlockAdd) & 0xFFU; + tail_pack[4] = (uint8_t)(BlockAdd >> 8) & 0xFFU; + tail_pack[3] = 0x00; + tail_pack[2] = 0x00; + tail_pack[1] = 0x00; + tail_pack[0] = 0x00; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 1); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send Request Packet */ + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + rtempbuff = zero_pack; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + rtempbuff = pNonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packet */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + byte_count = 0; + + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_KEYMAC_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_KEYMAC_POSITION) + { + tempbuff = (uint8_t *)pMAC; + } + else if (byte_count == MMC_RPMB_DATA_POSITION) + { + tempbuff = &pData[offset]; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = echo_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else if (byte_count == MMC_BLOCKSIZE) + { + byte_count = 0; + offset += (uint32_t)256U; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + for (uint8_t i = 0; i < 16U; i++) + { + if (pNonce[i] != echo_nonce[i]) + { + return HAL_ERROR; + } + } + + /* Check result of operation */ + if ((tail_pack[9] != 0x00U) || (tail_pack[10] != 0x04U)) + { + hmmc->RPMBErrorCode |= tail_pack[9]; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + + /** * @brief Read DMA Linked list node Transfer completed callbacks * @param hmmc: MMC handle diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c index 47adcccffd..416c295792 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c @@ -109,6 +109,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32u5xx_hal.h" +#if defined(FMC_BANK3) /** @addtogroup STM32U5xx_HAL_Driver * @{ @@ -2228,3 +2229,5 @@ uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand) /** * @} */ + +#endif /* FMC_BANK3 */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nor.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nor.c index 705dab2a1e..36d83a84c9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nor.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nor.c @@ -106,6 +106,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32u5xx_hal.h" +#if defined(FMC_BANK1) /** @addtogroup STM32U5xx_HAL_Driver * @{ @@ -1639,3 +1640,5 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /** * @} */ + +#endif /* FMC_BANK1 */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_opamp.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_opamp.c index a074f89a86..f37b3bc2af 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_opamp.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_opamp.c @@ -408,7 +408,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) /* Set the power supply range to high for performance purpose */ /* The OPAMP_CSR_OPARANGE is common configuration for all OPAMPs */ /* bit OPAMP_CSR_OPARANGE applies for both OPAMPs */ - MODIFY_REG(OPAMP1->CSR, OPAMP_CSR_OPARANGE, OPAMP_CSR_OPARANGE); + MODIFY_REG(OPAMP12_COMMON->CSR, OPAMP_CSR_OPARANGE, OPAMP_CSR_OPARANGE); /* Update the OPAMP state*/ if (hopamp->State == HAL_OPAMP_STATE_RESET) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c index cfb782c70e..45621b97bb 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c @@ -131,9 +131,9 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { -#if defined (STM32U575xx) || defined (STM32U585xx) - USB_OTG_GlobalTypeDef *USBx; -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ +#if defined (USB_OTG_FS) + const USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ @@ -145,9 +145,9 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); -#if defined (STM32U575xx) || defined (STM32U585xx) +#if defined (USB_OTG_FS) USBx = hpcd->Instance; -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ +#endif /* defined (USB_OTG_FS) */ if (hpcd->State == HAL_PCD_STATE_RESET) { @@ -184,13 +184,13 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; -#if defined (STM32U575xx) || defined (STM32U585xx) +#if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ - if ((USBx->CID & (0x1U << 14)) == 0U) + if (USBx == USB_OTG_FS) { hpcd->Init.dma_enable = 0U; } -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ +#endif /* defined (USB_OTG_FS) */ /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); @@ -202,8 +202,12 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) return HAL_ERROR; } - /* Force Device Mode*/ - (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); + /* Force Device Mode */ + if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) @@ -2286,9 +2290,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) * @param testmode USB Device high speed test mode * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode) +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; switch (testmode) @@ -2390,9 +2394,9 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { USB_OTG_EPTypeDef *ep; - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; if (hpcd->Init.dma_enable == 1U) @@ -2501,9 +2505,9 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; if ((gSNPSiD > USB_OTG_CORE_ID_300A) && diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c index aabc78133d..a4a9f4ac5d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c @@ -180,7 +180,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /* Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ - USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN; + USBx->GCCFG &= ~USB_OTG_GCCFG_DCDEN; HAL_Delay(50U); USBx->GCCFG |= USB_OTG_GCCFG_PDEN; HAL_Delay(50U); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c index 019fd16077..52374e7d42 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c @@ -309,6 +309,7 @@ HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode); void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in); void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in); void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in); +void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in); void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in); void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in); void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in); @@ -727,6 +728,7 @@ HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_Ca (++) HAL_PKA_ECCMulFastMode() (++) HAL_PKA_ECCMul_GetResult(); + (++) HAL_PKA_ECCMulEx() (++) HAL_PKA_ECCDoubleBaseLadder() (++) HAL_PKA_ECCDoubleBaseLadder_GetResult(); (++) HAL_PKA_ECCProjective2Affine() @@ -771,6 +773,7 @@ HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_Ca (++) HAL_PKA_ECCMulFastMode_IT(); (++) HAL_PKA_ECCMul_GetResult(); + (++) HAL_PKA_ECCMulEx_IT(); (++) HAL_PKA_ECCDoubleBaseLadder_IT() (++) HAL_PKA_ECCDoubleBaseLadder_GetResult(); (++) HAL_PKA_ECCProjective2Affine_IT() @@ -903,6 +906,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModE return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT); } + /** * @brief Retrieve operation result. * @param hpka PKA handle @@ -1151,6 +1155,40 @@ HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); } +/** + * @brief ECC scalar multiplication extended in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMulEx_Set(hpka, in); + + modulussize = in->modulusSize; + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); +} + +/** + * @brief ECC scalar multiplication extended in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMulEx_Set(hpka, in); + + modulussize = in->modulusSize; + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); +} /** * @brief Retrieve operation result. * @param hpka PKA handle @@ -1704,13 +1742,11 @@ void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka) void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) { uint32_t mode = PKA_GetMode(hpka); - FlagStatus addErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR); - FlagStatus ramErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR); - FlagStatus procEndFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_PROCEND); - FlagStatus operErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_OPERR); + uint32_t itsource = READ_REG(hpka->Instance->CR); + uint32_t flag = READ_REG(hpka->Instance->SR); /* Address error interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_ADDRERR) == SET) && (addErrFlag == SET)) + if (((itsource & PKA_IT_ADDRERR) == PKA_IT_ADDRERR) && ((flag & PKA_FLAG_ADDRERR) == PKA_FLAG_ADDRERR)) { hpka->ErrorCode |= HAL_PKA_ERROR_ADDRERR; @@ -1719,7 +1755,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) } /* RAM access error interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_RAMERR) == SET) && (ramErrFlag == SET)) + if (((itsource & PKA_IT_RAMERR) == PKA_IT_RAMERR) && ((flag & PKA_FLAG_RAMERR) == PKA_FLAG_RAMERR)) { hpka->ErrorCode |= HAL_PKA_ERROR_RAMERR; @@ -1728,7 +1764,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) } /* OPERATION access error interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_FLAG_OPERR) == SET) && (operErrFlag == SET)) + if (((itsource & PKA_IT_OPERR) == PKA_IT_OPERR) && ((flag & PKA_FLAG_OPERR) == PKA_FLAG_OPERR)) { hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; @@ -1792,7 +1828,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) } /* End Of Operation interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_PROCEND) == SET) && (procEndFlag == SET)) + if (((itsource & PKA_IT_PROCEND) == PKA_IT_PROCEND) && ((flag & PKA_FLAG_PROCEND) == PKA_FLAG_PROCEND)) { /* Clear PROCEND flag */ __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_PROCEND); @@ -2591,7 +2627,50 @@ void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in) PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize); __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL)); } +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in) +{ + /* Get the prime order n length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder)); + + /* Get the modulus length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus)); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)); + /* Move the input parameters coefficient b to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters scalar multiplier k to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], in->pointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters curve prime order N to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL)); +} /** * @brief Set input parameters. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pssi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pssi.c index d8cf07b84c..23073f6ca0 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pssi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pssi.c @@ -53,7 +53,6 @@ (#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API. - (#) For PSSI IO operations, two operation modes are available within this driver : *** Polling mode IO operation *** @@ -651,8 +650,8 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u HAL_PSSI_DISABLE(hpssi); /* Configure transfer parameters */ - hpssi->Instance->CR |= PSSI_CR_OUTEN_OUTPUT | - ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL); + MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL), + (PSSI_CR_OUTEN_OUTPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL))); #if defined(HAL_DMA_MODULE_ENABLED) /* DMA Disable */ @@ -804,8 +803,8 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui /* Disable the selected PSSI peripheral */ HAL_PSSI_DISABLE(hpssi); /* Configure transfer parameters */ - hpssi->Instance->CR |= PSSI_CR_OUTEN_INPUT | - ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL); + MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL), + (PSSI_CR_OUTEN_INPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL))); #if defined(HAL_DMA_MODULE_ENABLED) /* DMA Disable */ @@ -1122,7 +1121,7 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat if (hpssi->hdmarx != NULL) { /* Configure BusWidth */ - if (hpssi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE) + if (hpssi->hdmarx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE) { MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, PSSI_CR_DMA_ENABLE | ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U)); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c index 879016a076..a7a6fbda3e 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c @@ -297,8 +297,11 @@ void HAL_PWR_DisableBkUpAccess(void) The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode() function. - (++) PWR_SLEEPENTRY_WFI: enter Sleep mode with WFI instruction. - (++) PWR_SLEEPENTRY_WFE: enter Sleep mode with WFE instruction. + (++) PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction. + (++) PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and + clear of pending events before. + (++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE instruction and + no clear of pending event before. -@@- The Regulator parameter is not used for the STM32U5 family and is kept as parameter just to maintain compatibility with other families. @@ -326,8 +329,11 @@ void HAL_PWR_DisableBkUpAccess(void) with : (++) StopEntry: - (+++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction. - (+++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction. + (+++) PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + (+++) PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and + clear of pending events before. + (+++) PWR_STOPENTRY_WFE_NO_EVT_CLEAR: Enter STOP mode with WFE instruction and + no clear of pending event before. -@@- The Regulator parameter is not used for the STM32U5 family and is kept as parameter just to maintain compatibility with other families. @@ -522,13 +528,11 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) * products. * @param SleepEntry : Specifies if Sleep mode is entered with WFI or WFE * instruction. - * This parameter can be one of the following values : - * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep mode with Wait - * For Interrupt request. - * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep mode with Wait - * For Event request. - * @note When WFI entry is used, ticks interrupt must be disabled to avoid - * unexpected CPU wake up. + * @arg PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction. + * @arg PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and + * clear of pending events before. + * @arg PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR : Enter SLEEP mode with WFE instruction and + * no clear of pending event before. * @retval None. */ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry) @@ -549,9 +553,14 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry) } else { - /* Wait For Event Request */ - __SEV(); - __WFE(); + if (SleepEntry != PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + + /* Request Wait For Event */ __WFE(); } } @@ -580,10 +589,12 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry) * @param StopEntry : Specifies if Stop mode is entered with WFI or WFE * instruction. * This parameter can be one of the following values : - * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait - * For Interrupt request. - * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait - * For Event request. + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and + * clear of pending events before. + * @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and + * no clear of pending event before. + * @note In System STOP mode, all I/O pins keep the same state as in Run mode. * @retval None. */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t StopEntry) @@ -607,9 +618,14 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t StopEntry) } else { - /* Wait For Event Request */ - __SEV(); - __WFE(); + if (StopEntry != PWR_STOPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + + /* Request Wait For Event */ __WFE(); } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c index 616c5104e1..0dc86b9ab2 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c @@ -2399,7 +2399,7 @@ void HAL_PWREx_DisableSRAM4FastWakeUp(void) * @verbatim =============================================================================== - ##### I/O Pull-Up Pull-Down Configuration Functions ##### + ##### IO Pull-Up Pull-Down Configuration Functions ##### =============================================================================== [..] In Standby and Shutdown mode, pull up and pull down can be configured to diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c index 35bd46775f..1b47d2327d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c @@ -361,21 +361,6 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) { uint32_t tickstart; - /* Increasing the CPU frequency */ - if (FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) - { - return HAL_ERROR; - } - - } - tickstart = HAL_GetTick(); /* Set MSION bit */ @@ -507,17 +492,15 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) SystemCoreClock = MSI_VALUE; /* Decreasing the number of wait states because of lower CPU frequency */ - if (FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) - { - return HAL_ERROR; - } + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + { + return HAL_ERROR; } /* Adapt Systick interrupt period */ @@ -1242,9 +1225,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruc __HAL_RCC_PWR_CLK_DISABLE(); } - /* Enable PLL System Clock output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); - /* Enable the main PLL */ __HAL_RCC_PLL_ENABLE(); @@ -1258,6 +1238,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruc return HAL_TIMEOUT; } } + + /* Enable PLL System Clock output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); + } else { @@ -2043,11 +2027,11 @@ void HAL_RCC_NMI_IRQHandler(void) /* Check RCC CSSF interrupt flag */ if (__HAL_RCC_GET_IT(RCC_IT_CSS)) { - /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CSSCallback(); - /* Clear RCC CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); } } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc_ex.c index 41512bd169..cdb4d86f31 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc_ex.c @@ -331,7 +331,7 @@ #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) -#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) +#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) @@ -1265,7 +1265,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe } - /** * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c index 292d1854d4..bfcbe13eee 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c @@ -233,7 +233,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Get tick */ tickstart = HAL_GetTick(); /* Check if data register contains valid random data */ - while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { @@ -674,8 +674,6 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t /* Update the error code and status */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; status = HAL_ERROR; - /* Clear bit DRDY */ - CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY); } else /* No seed error */ { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c index 89cdff0045..adeb1b3bbb 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c @@ -129,6 +129,9 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigT /* RNG health test control in accordance with NIST */ WRITE_REG(hrng->Instance->HTCR, pConf->HealthTest); + /* RNG noise source control in accordance with NIST */ + WRITE_REG(hrng->Instance->NSCR, pConf->NoiseSource); + /* Writing bit CONDRST=0*/ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); /* Get tick */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c index 88fbebdd27..96999b17f9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c @@ -1487,12 +1487,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) { /* Configure the Alarm A output clear */ - SET_BIT(RTC->CR, RTC_CR_ALRAOCLR); + SET_BIT(RTC->CR, RTC_CR_ALRAFCLR); } else { /* Disable the Alarm A output clear */ - CLEAR_BIT(RTC->CR, RTC_CR_ALRAOCLR); + CLEAR_BIT(RTC->CR, RTC_CR_ALRAFCLR); } /* Configure the Alarm state: Enable Alarm */ SET_BIT(RTC->CR, RTC_CR_ALRAE); @@ -1519,12 +1519,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) { /* Configure the Alarm B output clear */ - SET_BIT(RTC->CR, RTC_CR_ALRBOCLR); + SET_BIT(RTC->CR, RTC_CR_ALRBFCLR); } else { /* Disable the Alarm B output clear */ - CLEAR_BIT(RTC->CR, RTC_CR_ALRBOCLR); + CLEAR_BIT(RTC->CR, RTC_CR_ALRBFCLR); } /* Configure the Alarm state: Enable Alarm */ SET_BIT(RTC->CR, RTC_CR_ALRBE); @@ -1692,12 +1692,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) { /* Configure the Alarm A output clear */ - SET_BIT(RTC->CR, RTC_CR_ALRAOCLR); + SET_BIT(RTC->CR, RTC_CR_ALRAFCLR); } else { /* Disable the Alarm A output clear*/ - CLEAR_BIT(RTC->CR, RTC_CR_ALRAOCLR); + CLEAR_BIT(RTC->CR, RTC_CR_ALRAFCLR); } /* Configure the Alarm interrupt */ @@ -1725,12 +1725,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) { /* Configure the Alarm B Output clear */ - SET_BIT(RTC->CR, RTC_CR_ALRBOCLR); + SET_BIT(RTC->CR, RTC_CR_ALRBFCLR); } else { /* Disable the Alarm B Output clear */ - CLEAR_BIT(RTC->CR, RTC_CR_ALRBOCLR); + CLEAR_BIT(RTC->CR, RTC_CR_ALRBFCLR); } /* Configure the Alarm interrupt */ @@ -1738,7 +1738,6 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } - hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc_ex.c index b125b32b50..c3212591e6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc_ex.c @@ -656,7 +656,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t */ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart; /* Process Locked */ __HAL_LOCK(hrtc); @@ -669,32 +668,6 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /* In case of interrupt mode is used, the interrupt source must disabled */ CLEAR_BIT(RTC->CR, (RTC_CR_WUTE | RTC_CR_WUTIE)); - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* New check to avoid false timeout detection in case of preemption */ - if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) - { - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - else - { - break; - } - } - } - /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sai.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sai.c index 88bc4ce85a..832dd9884b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sai.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sai.c @@ -171,7 +171,7 @@ [..] Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. [..] @@ -186,10 +186,10 @@ [..] By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak functions: examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SAI_Init + reset to the legacy weak functions in the HAL_SAI_Init and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -206,7 +206,7 @@ [..] When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim */ @@ -1394,6 +1394,12 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; @@ -1425,12 +1431,6 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) } } - /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - status = HAL_ERROR; - } - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -1456,6 +1456,12 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Check SAI DMA is enabled or not */ if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { @@ -1495,12 +1501,6 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) hsai->Instance->IMR = 0; hsai->Instance->CLRFR = 0xFFFFFFFFU; - /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - status = HAL_ERROR; - } - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c index 50b80b4ae2..594045c1b8 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c @@ -56,7 +56,6 @@ (#) At this stage, you can perform SD read/write/erase operations after SD card initialization - *** SD Card Initialization and configuration *** ================================================ [..] @@ -604,7 +603,6 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) return HAL_OK; } - /** * @brief Initializes the SD MSP. * @param hsd: Pointer to SD handle @@ -1307,7 +1305,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Enable transfer interrupts */ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); - return HAL_OK; } else @@ -1374,7 +1371,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *p config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE(hsd->Instance); hsd->Instance->IDMABASER = (uint32_t) pData ; @@ -2321,7 +2317,6 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT status = HAL_ERROR; } - return status; } @@ -2362,6 +2357,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t SDMMC_InitTypeDef Init; uint32_t errorstate; uint32_t sdmmc_clk; + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ @@ -2932,7 +2928,6 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) return HAL_OK; } - /** * @brief Abort the current transfer and disable the SD (IT mode). * @param hsd: pointer to a SD_HandleTypeDef structure that contains @@ -2990,7 +2985,6 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) * @{ */ - /** * @brief Initializes the sd card. * @param hsd: Pointer to SD handle @@ -3497,7 +3491,6 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) } } - /** * @brief Finds the SD card SCR register value. * @param hsd: Pointer to SD handle @@ -3552,7 +3545,6 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) index++; } - if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; @@ -3709,7 +3701,6 @@ uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode) (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); - errorstate = SDMMC_CmdSwitch(hsd->Instance, SwitchSpeedMode); if (errorstate != HAL_SD_ERROR_NONE) { @@ -3727,7 +3718,6 @@ uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode) } loop ++; } - if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c index 782eb687eb..dc0b588985 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c @@ -2490,7 +2490,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; } - MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg); + WRITE_REG(hsmartcard->Instance->RTOR, tmpreg); /*-------------------------- USART BRR Configuration -----------------------*/ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus.c index 788393f115..7cbe69b9a3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus.c @@ -1007,8 +1007,15 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) { - hsmbus->XferSize--; - hsmbus->XferCount--; + if (hsmbus->XferSize > 0U) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else + { + return HAL_ERROR; + } } } @@ -2618,8 +2625,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } - /* Flush TX register */ - SMBUS_Flush_TXDR(hsmbus); + if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) + { + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + } /* Store current volatile hsmbus->ErrorCode, misra rule */ tmperror = hsmbus->ErrorCode; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus_ex.c index ce0724b63a..2dcfd46455 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus_ex.c @@ -6,6 +6,9 @@ * This file provides firmware functions to manage the following * functionalities of SMBUS Extended peripheral: * + Extended features functions + * + WakeUp Mode Functions + * + FastModePlus Functions + * + Autonomous Mode Functions * ****************************************************************************** * @attention diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c index 498141290d..58e66052ef 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c @@ -111,9 +111,8 @@ using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() or HAL_SPI_Init() function. - When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or not defined, + the callback registering feature is not available and weak callbacks are used. SuspendCallback restriction: SuspendCallback is called only when MasterReceiverAutoSusp is enabled and @@ -152,7 +151,6 @@ * @{ */ #define SPI_DEFAULT_TIMEOUT 100UL -#define MAX_FIFO_LENGTH 16UL /** * @} */ @@ -568,6 +566,8 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) * the configuration information for the specified SPI. * @param CallbackID ID of the callback to be registered * @param pCallback pointer to the Callback function + * @note The HAL_SPI_RegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET + * to register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, @@ -582,8 +582,6 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call return HAL_ERROR; } - /* Lock the process */ - __HAL_LOCK(hspi); if (HAL_SPI_STATE_READY == hspi->State) { @@ -672,8 +670,6 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hspi); return status; } @@ -683,15 +679,14 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call * @param hspi Pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI. * @param CallbackID ID of the callback to be unregistered + * @note The HAL_SPI_UnRegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET + * to un-register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; - /* Lock the process */ - __HAL_LOCK(hspi); - if (HAL_SPI_STATE_READY == hspi->State) { switch (CallbackID) @@ -779,8 +774,6 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hspi); return status; } #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -837,31 +830,26 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData #endif /* __GNUC__ */ uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -919,11 +907,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -963,11 +952,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1012,11 +1002,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1032,16 +1023,19 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { return HAL_ERROR; } - return errorcode; + else + { + return HAL_OK; + } } /** @@ -1056,7 +1050,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; #if defined (__GNUC__) __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); #endif /* __GNUC__ */ @@ -1064,26 +1057,22 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1141,11 +1130,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1176,11 +1166,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1207,11 +1198,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1232,16 +1224,20 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { return HAL_ERROR; } - return errorcode; + else + { + return HAL_OK; + } } /** @@ -1257,22 +1253,19 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - HAL_StatusTypeDef errorcode = HAL_OK; #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); #endif /* __GNUC__ */ uint32_t tickstart; + uint32_t fifo_length; uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1281,18 +1274,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1310,6 +1302,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Set Full-Duplex mode */ SPI_2LINES(hspi); + /* Initialize FIFO length */ + if (IS_SPI_FULL_INSTANCE(hspi->Instance)) + { + fifo_length = SPI_HIGHEND_FIFO_SIZE; + } + else + { + fifo_length = SPI_LOWEND_FIFO_SIZE; + } + /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -1324,10 +1326,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Transmit and Receive data in 32 Bit mode */ if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) { + /* Adapt fifo length to 32bits data width */ + fifo_length = (fifo_length / 4UL); + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) { /* Check TXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL)) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) { *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); @@ -1350,11 +1356,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1362,10 +1369,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Transmit and Receive data in 16 Bit mode */ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { + /* Adapt fifo length to 16bits data width */ + fifo_length = (fifo_length / 2UL); + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) { /* Check the TXP flag */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP) && (initial_TxXferCount > 0UL)) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) { #if defined (__GNUC__) *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); @@ -1396,11 +1407,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1411,7 +1423,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) { /* Check the TXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL)) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) { *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); @@ -1434,11 +1447,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; return HAL_TIMEOUT; } } @@ -1453,16 +1467,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { return HAL_ERROR; } - return errorcode; + else + { + return HAL_OK; + } } /** @@ -1475,28 +1492,22 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1540,6 +1551,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); + /* Enable EOT, TXP, FRE, MODF and UDR interrupts */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); @@ -1549,8 +1563,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); } - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -1563,28 +1576,22 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1632,6 +1639,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); + /* Enable EOT, RXP, OVR, FRE and MODF interrupts */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); @@ -1641,9 +1651,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); } - /* Unlock the process */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -1658,9 +1666,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; uint32_t tmp_TxXferCount; - #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); #endif /* __GNUC__ */ @@ -1668,23 +1674,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1755,6 +1757,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint } } + /* Unlock the process */ + __HAL_UNLOCK(hspi); + /* Enable EOT, DXP, UDR, OVR, FRE and MODF interrupts */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); @@ -1764,9 +1769,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); } - /* Unlock the process */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } @@ -1782,28 +1785,24 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint */ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode; + HAL_StatusTypeDef status; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1834,9 +1833,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE))) { /* Restriction the DMA data received is not allowed in this mode */ - errorcode = HAL_ERROR; __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } /* Adjust XferCount according to DMA alignment / Data size */ @@ -1905,39 +1903,30 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p /* Set DMA destination address */ hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR; - errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmatx); + status = HAL_DMAEx_List_Start_IT(hspi->hdmatx); } else { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + status = HAL_ERROR; } } else { - errorcode = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, - hspi->TxXferCount); + status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount); } /* Check status */ - if (errorcode != HAL_OK) + if (status != HAL_OK) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + return HAL_ERROR; } /* Set the number of data at current transfer */ @@ -1967,7 +1956,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p /* Unlock the process */ __HAL_UNLOCK(hspi); - return errorcode; + + return HAL_OK; } /** @@ -1981,28 +1971,27 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode; + HAL_StatusTypeDef status; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -2032,9 +2021,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) { /* Restriction the DMA data received is not allowed in this mode */ - errorcode = HAL_ERROR; __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } /* Clear RXDMAEN bit */ @@ -2103,39 +2091,30 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set DMA destination address */ hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr; - errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmarx); + status = HAL_DMAEx_List_Start_IT(hspi->hdmarx); } else { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + status = HAL_ERROR; } } else { - errorcode = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, - hspi->RxXferCount); + status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount); } /* Check status */ - if (errorcode != HAL_OK) + if (status != HAL_OK) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + return HAL_ERROR; } /* Set the number of data at current transfer */ @@ -2165,7 +2144,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Unlock the process */ __HAL_UNLOCK(hspi); - return errorcode; + + return HAL_OK; } /** @@ -2181,28 +2161,24 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - HAL_StatusTypeDef errorcode; + HAL_StatusTypeDef status; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Lock the process */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) { - errorcode = HAL_ERROR; - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } + /* Lock the process */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -2229,10 +2205,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) { /* Restriction the DMA data received is not allowed in this mode */ - errorcode = HAL_ERROR; /* Unlock the process */ __HAL_UNLOCK(hspi); - return errorcode; + return HAL_ERROR; } /* Adjust XferCount according to DMA alignment / Data size */ @@ -2307,39 +2282,30 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin /* Set DMA destination address */ hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr; - errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmarx); + status = HAL_DMAEx_List_Start_IT(hspi->hdmarx); } else { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + status = HAL_ERROR; } } else { - errorcode = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, - hspi->RxXferCount); + status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount); } /* Check status */ - if (errorcode != HAL_OK) + if (status != HAL_OK) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + return HAL_ERROR; } /* Enable Rx DMA Request */ @@ -2381,39 +2347,33 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin /* Set DMA destination address */ hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR; - errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmatx); + status = HAL_DMAEx_List_Start_IT(hspi->hdmatx); } else { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + status = HAL_ERROR; } } else { - errorcode = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, - hspi->TxXferCount); + status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount); } /* Check status */ - if (errorcode != HAL_OK) + if (status != HAL_OK) { + /* Abort Rx DMA Channel already started */ + (void)HAL_DMA_Abort(hspi->hdmarx); + /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; /* Unlock the process */ __HAL_UNLOCK(hspi); - hspi->State = HAL_SPI_STATE_READY; - errorcode = HAL_ERROR; - return errorcode; + return HAL_ERROR; } if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) && (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)) @@ -2442,7 +2402,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin /* Unlock the process */ __HAL_UNLOCK(hspi); - return errorcode; + + return HAL_OK; } /** @@ -2487,8 +2448,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } - while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); /* Request a Suspend transfer */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); @@ -2500,8 +2460,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } - while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); /* Clear SUSP flag */ __HAL_SPI_CLEAR_SUSPFLAG(hspi); @@ -2513,8 +2472,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } - while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); } /* Disable the SPI DMA Tx request if enabled */ @@ -2570,12 +2528,12 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) hspi->ErrorCode = HAL_SPI_ERROR_NONE; } - /* Unlock the process */ - __HAL_UNLOCK(hspi); - /* Restore hspi->state to ready */ hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + return errorcode; } @@ -2621,8 +2579,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } - while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); /* Request a Suspend transfer */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); @@ -2634,8 +2591,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } - while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); /* Clear SUSP flag */ __HAL_SPI_CLEAR_SUSPFLAG(hspi); @@ -2647,8 +2603,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } - while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); } /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized @@ -2840,7 +2795,6 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) handled = 1UL; } - if (handled != 0UL) { return; @@ -3321,7 +3275,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) hspi->TxHalfCpltCallback(hspi); @@ -3338,7 +3293,8 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRA */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) hspi->RxHalfCpltCallback(hspi); @@ -3355,7 +3311,8 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) hspi->TxRxHalfCpltCallback(hspi); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sram.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sram.c index 3e894f8c43..608f284e3b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sram.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sram.c @@ -115,6 +115,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32u5xx_hal.h" +#if defined(FMC_BANK1) /** @addtogroup STM32U5xx_HAL_Driver * @{ @@ -1233,3 +1234,5 @@ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) /** * @} */ + +#endif /* FMC_BANK1 */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c index b588ff7404..97eadff426 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c @@ -5583,7 +5583,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } case TIM_CLEARINPUTSOURCE_COMP1: +#if defined(COMP2) case TIM_CLEARINPUTSOURCE_COMP2: +#endif /* COMP2 */ { /* Clear the OCREF clear selection bit */ CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); @@ -7295,6 +7297,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; + + /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ + if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) + { + /* Clear the update flag */ + CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); + } } /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c index 229321b334..afe917be16 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c @@ -2308,6 +2308,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos; break; } +#if defined(COMP2) case TIM_BREAKINPUTSOURCE_COMP2: { bkin_enable_mask = TIM1_AF1_BKCMP2E; @@ -2316,6 +2317,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos; break; } +#endif /* COMP2 */ case TIM_BREAKINPUTSOURCE_MDF1: { bkin_enable_mask = TIM1_AF1_BKDF1BK0E; @@ -2387,25 +2389,25 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @param htim TIM handle. * @param Remap specifies the TIM remapping source. * For TIM1, the parameter can take one of the following values: - * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO - * @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1 output - * @arg TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2 output - * @arg TIM_TIM1_ETR_HSI TIM1 ETR is connected to HSI - * @arg TIM_TIM1_ETR_MSIS TIM1_ETR is connected to MSIS - * @arg TIM_TIM1_ETR_ADC2_AWD2 TIM1_ETR is connected to ADC2 AWD2 (*) - * @arg TIM_TIM1_ETR_ADC2_AWD3 TIM1_ETR is connected to ADC2 AWD3 (*) - * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1 - * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2 - * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3 - * @arg TIM_TIM1_ETR_ADC4_AWD1 TIM1 ETR is connected to ADC4 AWD1 - * @arg TIM_TIM1_ETR_ADC4_AWD2 TIM1 ETR is connected to ADC4 AWD2 - * @arg TIM_TIM1_ETR_ADC4_AWD3 TIM1 ETR is connected to ADC4 AWD3 - * @arg TIM_TIM1_ETR_ADC2_AWD1 TIM1_ETR is connected to ADC2 AWD1 (*) + * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO + * @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1 output + * @arg TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2 output (*) + * @arg TIM_TIM1_ETR_HSI TIM1 ETR is connected to HSI + * @arg TIM_TIM1_ETR_MSIS TIM1_ETR is connected to MSIS + * @arg TIM_TIM1_ETR_ADC2_AWD2 TIM1_ETR is connected to ADC2 AWD2 (*) + * @arg TIM_TIM1_ETR_ADC2_AWD3 TIM1_ETR is connected to ADC2 AWD3 (*) + * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3 + * @arg TIM_TIM1_ETR_ADC4_AWD1 TIM1 ETR is connected to ADC4 AWD1 + * @arg TIM_TIM1_ETR_ADC4_AWD2 TIM1 ETR is connected to ADC4 AWD2 + * @arg TIM_TIM1_ETR_ADC4_AWD3 TIM1 ETR is connected to ADC4 AWD3 + * @arg TIM_TIM1_ETR_ADC2_AWD1 TIM1_ETR is connected to ADC2 AWD1 (*) * * For TIM2, the parameter can take one of the following values: * @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO * @arg TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1 output - * @arg TIM_TIM2_ETR_COMP2 TIM2 ETR is connected to COMP2 output + * @arg TIM_TIM2_ETR_COMP2 TIM2 ETR is connected to COMP2 output (*) * @arg TIM_TIM2_ETR_MSIK TIM2 ETR is connected to MSIK * @arg TIM_TIM2_ETR_HSI TIM2 ETR is connected to HSI * @arg TIM_TIM2_ETR_MSIS TIM2_ETR is connected to MSIS @@ -2422,7 +2424,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * For TIM3, the parameter can take one of the following values: * @arg TIM_TIM3_ETR_GPIO TIM3 ETR is connected to GPIO * @arg TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1 output - * @arg TIM_TIM3_ETR_COMP2 TIM3 ETR is connected to COMP2 output + * @arg TIM_TIM3_ETR_COMP2 TIM3 ETR is connected to COMP2 output (*) * @arg TIM_TIM3_ETR_MSIK TIM3 ETR is connected to MSIK * @arg TIM_TIM3_ETR_HSI TIM3 ETR is connected to HSI * @arg TIM_TIM3_ETR_MSIS TIM3_ETR is connected to MSIS @@ -2438,42 +2440,42 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM3_ETR_LTDC_HSYNC TIM3_ETR is connected to LTDC HSYNC (*) * * For TIM4, the parameter can take one of the following values: - * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO - * @arg TIM_TIM4_ETR_COMP1 TIM4 ETR is connected to COMP1 output - * @arg TIM_TIM4_ETR_COMP2 TIM4 ETR is connected to COMP2 output - * @arg TIM_TIM4_ETR_MSIK TIM4 ETR is connected to MSIK - * @arg TIM_TIM4_ETR_HSI TIM4 ETR is connected to HSI - * @arg TIM_TIM4_ETR_MSIS TIM4_ETR is connected to MSIS - * @arg TIM_TIM4_ETR_DCMI_VSYNC TIM4_ETR is connected to DCMI VSYNC (*) - * @arg TIM_TIM4_ETR_LTDC_VSYNC TIM4_ETR is connected to LTDC_VSYNC (*) - * @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin - * @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin - * @arg TIM_TIM4_ETR_DSI_TE TIM2_ETR is connected to DSI_TE (*) - * @arg TIM_TIM4_ETR_ADC2_AWD1 TIM4_ETR is connected to ADC2 AWD1 (*) - * @arg TIM_TIM4_ETR_ADC2_AWD2 TIM4_ETR is connected to ADC2 AWD2 (*) - * @arg TIM_TIM4_ETR_ADC2_AWD3 TIM4_ETR is connected to ADC2 AWD3 (*) - * @arg TIM_TIM4_ETR_DCMI_HSYNC TIM4_ETR is connected to DCMI HSYNC (*) - * @arg TIM_TIM4_ETR_LTDC_HSYNC TIM4_ETR is connected to LTDC HSYNC (*) + * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO + * @arg TIM_TIM4_ETR_COMP1 TIM4 ETR is connected to COMP1 output + * @arg TIM_TIM4_ETR_COMP2 TIM4 ETR is connected to COMP2 output (*) + * @arg TIM_TIM4_ETR_MSIK TIM4 ETR is connected to MSIK + * @arg TIM_TIM4_ETR_HSI TIM4 ETR is connected to HSI + * @arg TIM_TIM4_ETR_MSIS TIM4_ETR is connected to MSIS + * @arg TIM_TIM4_ETR_DCMI_VSYNC TIM4_ETR is connected to DCMI VSYNC (*) + * @arg TIM_TIM4_ETR_LTDC_VSYNC TIM4_ETR is connected to LTDC_VSYNC (*) + * @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin + * @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin + * @arg TIM_TIM4_ETR_DSI_TE TIM2_ETR is connected to DSI_TE (*) + * @arg TIM_TIM4_ETR_ADC2_AWD1 TIM4_ETR is connected to ADC2 AWD1 (*) + * @arg TIM_TIM4_ETR_ADC2_AWD2 TIM4_ETR is connected to ADC2 AWD2 (*) + * @arg TIM_TIM4_ETR_ADC2_AWD3 TIM4_ETR is connected to ADC2 AWD3 (*) + * @arg TIM_TIM4_ETR_DCMI_HSYNC TIM4_ETR is connected to DCMI HSYNC (*) + * @arg TIM_TIM4_ETR_LTDC_HSYNC TIM4_ETR is connected to LTDC HSYNC (*) * * For TIM5, the parameter can take one of the following values: - * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO - * @arg TIM_TIM5_ETR_COMP1 TIM5 ETR is connected to COMP1 output - * @arg TIM_TIM5_ETR_COMP2 TIM5 ETR is connected to COMP2 output - * @arg TIM_TIM5_ETR_MSIK TIM5 ETR is connected to MSIK - * @arg TIM_TIM5_ETR_HSI TIM5 ETR is connected to HSI - * @arg TIM_TIM5_ETR_MSIS TIM5_ETR is connected to MSIS - * @arg TIM_TIM5_ETR_DCMI_VSYNC TIM5_ETR is connected to DCMI VSYNC (*) - * @arg TIM_TIM5_ETR_LTDC_VSYNC TIM5_ETR is connected to LTDC_VSYNC (*) - * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin - * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin - * @arg TIM_TIM5_ETR_DSI_TE TIM5_ETR is connected to DSI_TE (*) - * @arg TIM_TIM5_ETR_DCMI_HSYNC TIM5_ETR is connected to DCMI HSYNC (*) - * @arg TIM_TIM5_ETR_LTDC_HSYNC TIM5_ETR is connected to LTDC HSYNC (*) + * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO + * @arg TIM_TIM5_ETR_COMP1 TIM5 ETR is connected to COMP1 output + * @arg TIM_TIM5_ETR_COMP2 TIM5 ETR is connected to COMP2 output (*) + * @arg TIM_TIM5_ETR_MSIK TIM5 ETR is connected to MSIK + * @arg TIM_TIM5_ETR_HSI TIM5 ETR is connected to HSI + * @arg TIM_TIM5_ETR_MSIS TIM5_ETR is connected to MSIS + * @arg TIM_TIM5_ETR_DCMI_VSYNC TIM5_ETR is connected to DCMI VSYNC (*) + * @arg TIM_TIM5_ETR_LTDC_VSYNC TIM5_ETR is connected to LTDC_VSYNC (*) + * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin + * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin + * @arg TIM_TIM5_ETR_DSI_TE TIM5_ETR is connected to DSI_TE (*) + * @arg TIM_TIM5_ETR_DCMI_HSYNC TIM5_ETR is connected to DCMI HSYNC (*) + * @arg TIM_TIM5_ETR_LTDC_HSYNC TIM5_ETR is connected to LTDC HSYNC (*) * * For TIM8, the parameter can take one of the following values: * @arg TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO * @arg TIM_TIM8_ETR_COMP1 TIM8 ETR is connected to COMP1 output - * @arg TIM_TIM8_ETR_COMP2 TIM8 ETR is connected to COMP2 output + * @arg TIM_TIM8_ETR_COMP2 TIM8 ETR is connected to COMP2 output (*) * @arg TIM_TIM8_ETR_MSIK TIM8 ETR is connected to MSIK * @arg TIM_TIM8_ETR_HSI TIM8 ETR is connected to HSI * @arg TIM_TIM8_ETR_MSIS TIM8_ETR is connected to MSIS @@ -2516,62 +2518,62 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @arg TIM_CHANNEL_4: TIM Channel 4 * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows: * For TIM1, the parameter is one of the following values: - * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO - * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output - * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output + * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO + * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output + * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output (*) * * For TIM2, the parameter is one of the following values: - * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO - * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output - * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to COMP1 output - * @arg TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO - * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output - * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP1 output - * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO - * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output - * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output + * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO + * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output + * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to COMP2 output (*) + * @arg TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO + * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output + * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP2 output (*) + * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO + * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output + * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output (*) * * For TIM3, the parameter is one of the following values: - * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO - * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output - * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output - * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO - * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output - * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP1 output + * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO + * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output + * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output (*) + * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO + * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output + * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP2 output (*) * * For TIM4, the parameter is one of the following values: - * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO - * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output - * @arg TIM_TIM4_TI1_COMP2: TIM4 TI1 is connected to COMP2 output - * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO - * @arg TIM_TIM4_TI2_COMP1: TIM4 TI2 is connected to COMP1 output - * @arg TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to COMP2 output + * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO + * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output + * @arg TIM_TIM4_TI1_COMP2: TIM4 TI1 is connected to COMP2 output (*) + * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO + * @arg TIM_TIM4_TI2_COMP1: TIM4 TI2 is connected to COMP1 output + * @arg TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to COMP2 output (*) * * For TIM5, the parameter is one of the following values: - * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO - * @arg TIM_TIM5_TI1_LSI: TIM5 TI1 is connected to LSI - * @arg TIM_TIM5_TI1_LSE: TIM5 TI1 is connected to LSE - * @arg TIM_TIM5_TI1_RTC_WKUP: TIM5 TI1 is connected to RTC wakeup interrupt - * @arg TIM_TIM5_TI1_COMP1: TIM5 TI1 is connected to COMP1 output - * @arg TIM_TIM5_TI1_COMP2: TIM5 TI1 is connected to COMP2 output - * @arg TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to GPIO - * @arg TIM_TIM5_TI2_COMP1: TIM5 TI2 is connected to COMP1 output - * @arg TIM_TIM5_TI2_COMP2: TIM5 TI2 is connected to COMP2 output + * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO + * @arg TIM_TIM5_TI1_LSI: TIM5 TI1 is connected to LSI + * @arg TIM_TIM5_TI1_LSE: TIM5 TI1 is connected to LSE + * @arg TIM_TIM5_TI1_RTC_WKUP: TIM5 TI1 is connected to RTC wakeup interrupt + * @arg TIM_TIM5_TI1_COMP1: TIM5 TI1 is connected to COMP1 output + * @arg TIM_TIM5_TI1_COMP2: TIM5 TI1 is connected to COMP2 output (*) + * @arg TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to GPIO + * @arg TIM_TIM5_TI2_COMP1: TIM5 TI2 is connected to COMP1 output + * @arg TIM_TIM5_TI2_COMP2: TIM5 TI2 is connected to COMP2 output (*) * * For TIM8, the parameter is one of the following values: - * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO - * @arg TIM_TIM8_TI1_COMP1: TIM8 TI1 is connected to COMP1 output - * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output + * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO + * @arg TIM_TIM8_TI1_COMP1: TIM8 TI1 is connected to COMP1 output + * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output (*) * * For TIM15, the parameter is one of the following values: * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE - * @arg TIM_TIM15_TI1_COMP1: TIM8 TI1 is connected to COMP1 output - * @arg TIM_TIM15_TI1_COMP2: TIM8 TI1 is connected to COMP2 output + * @arg TIM_TIM15_TI1_COMP1: TIM15 TI1 is connected to COMP1 output + * @arg TIM_TIM15_TI1_COMP2: TIM15 TI1 is connected to COMP2 output (*) * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO * @arg TIM_TIM15_TI2_TIM2: TIM15 TI2 is connected to TIM2 CH2 * @arg TIM_TIM15_TI2_TIM3: TIM15 TI2 is connected to TIM3 CH2 - * @arg TIM_TIM15_TI2_COMP2: TIM8 TI1 is connected to COMP2 output + * @arg TIM_TIM15_TI2_COMP2: TIM15 TI2 is connected to COMP2 output (*) * * For TIM16, the parameter can have the following values: * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_timebase_tim_template.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_timebase_tim_template.c index e635411dc6..afae38cfda 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_timebase_tim_template.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_timebase_tim_template.c @@ -114,6 +114,11 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) Status = HAL_TIM_Base_Init(&TimHandle); if (Status == HAL_OK) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) + /* Register callback */ + HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Start the TIM time Base generation in interrupt mode */ Status = HAL_TIM_Base_Start_IT(&TimHandle); if (Status == HAL_OK) @@ -134,9 +139,6 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) } } } -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) - HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Return function Status */ return Status; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c index f52f0538a0..e1a10962ca 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c @@ -965,10 +965,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = pCallback; } @@ -979,9 +976,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); - return status; } @@ -995,10 +989,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ } @@ -1009,8 +1000,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); return status; } @@ -3465,7 +3454,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ return HAL_TIMEOUT; } - if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c index 997f4742b5..3b52eeb352 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c @@ -2535,7 +2535,7 @@ HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSP */ /** - * @brief Abort the current transmission. + * @brief Abort the current operation, return to the indirect mode. * @param hxspi : XSPI handle * @retval HAL status */ @@ -2588,12 +2588,18 @@ HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) if (status == HAL_OK) { + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); + hxspi->State = HAL_XSPI_STATE_READY; } } } else { + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); + hxspi->State = HAL_XSPI_STATE_READY; } } @@ -2607,7 +2613,7 @@ HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) } /** - * @brief Abort the current transmission (non-blocking function) + * @brief Abort the current operation, return to the indirect mode. (non-blocking function) * @param hxspi : XSPI handle * @retval HAL status */ @@ -2671,9 +2677,15 @@ HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi) /* Perform an abort of the XSPI */ SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); + + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); } else { + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); + hxspi->State = HAL_XSPI_STATE_READY; /* Abort callback */ @@ -2894,7 +2906,7 @@ uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi) * @param Timeout : Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout) +HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout) { HAL_StatusTypeDef status = HAL_OK; uint32_t instance; @@ -3440,9 +3452,6 @@ static void XSPI_DMACplt(DMA_HandleTypeDef *hdma) /* Disable the DMA transfer on the XSPI side */ CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); - /* Disable the DMA channel */ - __HAL_DMA_DISABLE(hdma); - /* Enable the XSPI transfer complete Interrupt */ HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_adc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_adc.c index 385d3ede35..3c8234f78b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_adc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_adc.c @@ -521,11 +521,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *pADCx) /* Disable ADC instance if not already disabled. */ if (LL_ADC_IsEnabled(pADCx) == 1UL) { - /* Set ADC group regular trigger source to SW start to ensure to not */ - /* have an external trigger event occurring during the conversion stop */ - /* ADC disable process. */ - LL_ADC_REG_SetTriggerSource(pADCx, LL_ADC_REG_TRIG_SOFTWARE); - /* Stop potential ADC conversion on going on ADC group regular. */ if (LL_ADC_REG_IsConversionOngoing(pADCx) != 0UL) { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dlyb.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dlyb.c index 723723c70f..1459562d11 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dlyb.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dlyb.c @@ -61,6 +61,7 @@ */ #if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED) +#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_OCTOSPI1) || defined (DLYB_OCTOSPI2) /** @cond 0 @@ -206,14 +207,14 @@ uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_c pdlyb_cfg->Units = i ; /* Disable the length sampling */ - DLYBx->CR = DLYB_CR_SEN; + CLEAR_BIT(DLYBx->CR, DLYB_CR_SEN); return (uint32_t)SUCCESS; } } /* Disable the length sampling */ - DLYBx->CR = DLYB_CR_SEN; + CLEAR_BIT(DLYBx->CR, DLYB_CR_SEN); return (uint32_t)ERROR; @@ -230,6 +231,7 @@ uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_c /** * @} */ +#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 || DLYB_OCTOSPI1 || DLYB_OCTOSPI2 */ #endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */ /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c index da0e14a18b..5b074bcdac 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c @@ -231,7 +231,8 @@ #define IS_LL_DMA_CHANNEL_DEST_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_DEST_NSEC) || \ ((__VALUE__) == LL_DMA_CHANNEL_DEST_SEC)) -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @} */ @@ -356,7 +357,7 @@ uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LL_DMA_DisableChannelSecure(DMAx, Channel); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ } return (uint32_t)status; @@ -784,7 +785,7 @@ void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct) /* Set DMA_InitNodeStruct fields to default values */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) DMA_InitNodeStruct->DestSecure = LL_DMA_CHANNEL_DEST_NSEC; -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ DMA_InitNodeStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0; DMA_InitNodeStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE; DMA_InitNodeStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE; @@ -793,7 +794,7 @@ void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct) DMA_InitNodeStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) DMA_InitNodeStruct->SrcSecure = LL_DMA_CHANNEL_SRC_NSEC; -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ DMA_InitNodeStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0; DMA_InitNodeStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE; DMA_InitNodeStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD; @@ -866,7 +867,7 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) assert_param(IS_LL_DMA_CHANNEL_SRC_SEC(DMA_InitNodeStruct->SrcSecure)); assert_param(IS_LL_DMA_CHANNEL_DEST_SEC(DMA_InitNodeStruct->DestSecure)); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Check trigger polarity */ if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED) @@ -937,7 +938,7 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestSecure | \ DMA_InitNodeStruct->SrcSecure); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Update CTR1 register fields for not LPDMA channels */ if (DMA_InitNodeStruct->NodeType != LL_DMA_LPDMA_LINEAR_NODE) @@ -1178,10 +1179,10 @@ void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t L * @} */ -#endif /* (defined (GPDMA1) || defined (LPDMA1)) */ +#endif /* GPDMA1 || LPDMA1 */ /** * @} */ -#endif /* defined (USE_FULL_LL_DRIVER) */ +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmc.c index e6ea864c11..91b74d507e 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmc.c @@ -75,6 +75,7 @@ /* ----------------------- FMC registers bit mask --------------------------- */ +#if defined(FMC_BANK1) /* --- BCR Register ---*/ /* BCR register clear mask */ @@ -90,6 +91,8 @@ #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD)) +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) /* --- PCR Register ---*/ /* PCR register clear mask */ @@ -107,6 +110,7 @@ #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\ FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ)) +#endif /* FMC_BANK3 */ /** * @} @@ -121,6 +125,7 @@ * @{ */ +#if defined(FMC_BANK1) /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions * @brief NORSRAM Controller functions @@ -376,14 +381,15 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Set FMC_NORSRAM device timing parameters */ - MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | - ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) | - ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | - (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | - (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | - (Timing->AccessMode))); + Device->BTCR[Bank + 1U] = + (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | + (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | + (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) | + (Timing->DataHoldTime << FMC_BTRx_DATAHLD_Pos) | + (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) | + ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) | + ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) | + Timing->AccessMode; /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) @@ -505,7 +511,9 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device /** * @} */ +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions * @brief NAND Controller functions @@ -603,10 +611,10 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos))); + Device->PMEM =(Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | + ((Timing->HoldSetupTime )<< FMC_PMEM_MEMHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); return HAL_OK; } @@ -634,10 +642,10 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos))); + Device->PATT =(Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); return HAL_OK; } @@ -778,6 +786,7 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui /** * @} */ +#endif /* FMC_BANK3 */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_opamp.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_opamp.c index 1d7d3ee7c4..1b0a5d9547 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_opamp.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_opamp.c @@ -54,7 +54,6 @@ ((__POWER_MODE__) == LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED)) - #define IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__) (((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_STANDALONE) ||\ ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_FOLLOWER) ||\ ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA)) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_sdmmc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_sdmmc.c index e907f66fe4..7349f78c37 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_sdmmc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_sdmmc.c @@ -530,6 +530,30 @@ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) return errorstate; } +/** + * @brief Send the Data Block number command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)BlockCount; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCK_COUNT; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCK_COUNT, SDMMC_CMDTIMEOUT); + + return errorstate; +} + /** * @brief Send the Read Single Block command and check the response * @param SDMMCx: Pointer to SDMMC register base diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c index fca7473c54..43623683e8 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c @@ -77,8 +77,8 @@ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2) \ || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \ || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT)) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c index de741fa691..4c841c9349 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c @@ -253,9 +253,9 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTy do { - HAL_Delay(1U); - ms++; - } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U)); + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); } else if (mode == USB_DEVICE_MODE) { @@ -263,16 +263,16 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTy do { - HAL_Delay(1U); - ms++; - } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U)); + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); } else { return HAL_ERROR; } - if (ms == 50U) + if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) { return HAL_ERROR; } @@ -475,7 +475,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -489,7 +489,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -512,7 +512,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -526,7 +526,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -546,7 +546,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -562,7 +562,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ -uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; uint8_t speed; @@ -591,7 +591,7 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -629,7 +629,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -668,7 +668,7 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -715,7 +715,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -929,7 +929,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { __IO uint32_t count = 0U; HAL_StatusTypeDef ret = HAL_OK; @@ -993,7 +993,7 @@ HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef * 1 : DMA feature used * @retval HAL status */ -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1024,7 +1024,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, * @param len Number of bytes to read * @retval pointer to destination buffer */ -void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { uint32_t USBx_BASE = (uint32_t)USBx; uint8_t *pDest = dest; @@ -1066,7 +1066,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -1097,7 +1097,7 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -1167,7 +1167,7 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 0 to 255 * @retval HAL status */ -HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1182,7 +1182,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1199,7 +1199,7 @@ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1232,7 +1232,7 @@ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) * @param chnum Channel number * @retval USB Channel Interrupt status */ -uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1248,7 +1248,7 @@ uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) * @param USBx Selected device * @retval USB Device OUT EP interrupt status */ -uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1264,7 +1264,7 @@ uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval USB Device IN EP interrupt status */ -uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1282,7 +1282,7 @@ uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ -uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1300,7 +1300,7 @@ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ -uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1334,7 +1334,7 @@ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) * 0 : Host * 1 : Device */ -uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { return ((USBx->GINTSTS) & 0x1U); } @@ -1344,7 +1344,7 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1366,10 +1366,10 @@ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) * @param psetup pointer to setup packet * @retval HAL status */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) { uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); if (gSNPSiD > USB_OTG_CORE_ID_300A) { @@ -1408,7 +1408,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -1422,7 +1422,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -1473,7 +1473,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); #endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - if ((USBx->CID & (0x1U << 14)) != 0U) + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) { if (cfg.speed == USBH_FSLS_SPEED) { @@ -1515,8 +1515,8 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /* Clear any pending interrupts */ USBx->GINTSTS = CLEAR_INTERRUPT_MASK; - - if ((USBx->CID & (0x1U << 14)) != 0U) +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) { /* set Rx FIFO size */ USBx->GRXFSIZ = 0x200U; @@ -1524,6 +1524,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); } else +#endif /* defined (USB_OTG_HS) */ { /* set Rx FIFO size */ USBx->GRXFSIZ = 0x80U; @@ -1555,7 +1556,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c * HCFG_6_MHZ : Low Speed 6 MHz Clock * @retval HAL status */ -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1585,7 +1586,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) * @note (1)The application must wait at least 10 ms * before clearing the reset bit. */ -HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1612,7 +1613,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) * 1 : Activate VBUS * @retval HAL status */ -HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state) { uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0 = 0U; @@ -1718,11 +1719,13 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, } else { - if ((USBx->CID & (0x1U << 14)) != 0U) +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) { USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM; } +#endif /* defined (USB_OTG_HS) */ } break; @@ -1827,12 +1830,13 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe uint16_t num_packets; uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT; - if ((USBx->CID & (0x1U << 14)) != 0U) +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) { /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ if (dma == 1U) { - if ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) + if (((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) && (hc->do_ssplit == 0U)) { USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | @@ -1849,6 +1853,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe } } } +#endif /* defined (USB_OTG_HS) */ if (hc->do_ssplit == 1U) { @@ -2078,7 +2083,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe * @param USBx Selected device * @retval HAL state */ -uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -2092,7 +2097,7 @@ uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 1 to 15 * @retval HAL state */ -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t hcnum = (uint32_t)hc_num; @@ -2176,7 +2181,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) * This parameter can be a value from 1 to 15 * @retval HAL state */ -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t chnum = (uint32_t)ch_num; @@ -2265,7 +2270,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -2283,7 +2288,7 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -3244,14 +3249,14 @@ HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) /* Clear All Pending Interrupt */ USBx->ISTR = 0U; + /* Set the PullDown on the PHY */ + USBx->BCDR |= USB_BCDR_DPPD; + /* Enable Global interrupt */ USBx->CNTR |= (USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM); - /* Remove Reset */ - USBx->CNTR &= ~USB_CNTR_USBRST; - return HAL_OK; } @@ -3367,7 +3372,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, wChRegVal = USB_DRD_GET_CHEP(USBx, phy_ch_num) & USB_CH_T_MASK; - /* initialize host Channel */ + /* Initialize host Channel */ switch (ep_type) { case EP_TYPE_CTRL: @@ -3391,7 +3396,10 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, break; } - wChRegVal &= ~USB_CHEP_DEVADDR; + /* Clear device address, Endpoint number and Low Speed Endpoint fields */ + wChRegVal &= ~(USB_CHEP_DEVADDR | USB_CHEP_ADDR | USB_CHEP_LSEP); + + /* Set device address and Endpoint number associated to the channel */ wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) | ((uint32_t)epnum & 0x0FU)); @@ -3404,7 +3412,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, wChRegVal |= USB_CHEP_LSEP; } - /* Set the dev_address & ep type */ + /* Update the channel register value */ USB_DRD_SET_CHEP(USBx, phy_ch_num, (wChRegVal | USB_CH_VTRX | USB_CH_VTTX)); return ret; @@ -3449,11 +3457,11 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) { (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_ENBALE); - /*Set the Double buffer counter*/ + /* Set the Double buffer counter */ USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len); USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 0U, len); } - else /* switch to single buffer mode */ + else /* Switch to single buffer mode */ { (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_DISABLE); @@ -3461,7 +3469,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len); } } - else /* isochronous */ + else /* Isochronous */ { /* Set the Double buffer counter */ USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len); @@ -3469,12 +3477,12 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) } #endif /* USE_USB_DOUBLE_BUFFER */ - /*Enable host channel */ - USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CHEP_RX_STRX); + /* Enable host channel */ + USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CH_RX_VALID); } else /* Out Channel */ { - /* Multi packet transfer*/ + /* Multi packet transfer */ if (hc->xfer_len > hc->max_packet) { len = hc->max_packet; @@ -3484,13 +3492,13 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) len = hc->xfer_len; } - /* configure and validate Tx endpoint */ + /* Configure and validate Tx endpoint */ if (hc->doublebuffer == 0U) { USB_WritePMA(USBx, hc->xfer_buff, hc->pmaadress, (uint16_t)len); USB_DRD_SET_CHEP_TX_CNT(USBx, phy_ch_num, (uint16_t)len); - /*SET PID SETUP */ + /* SET PID SETUP */ if ((hc->data_pid) == HC_PID_SETUP) { USB_DRD_CHEP_TX_SETUP(USBx, phy_ch_num); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_utils.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_utils.c index 02da47166a..a2a0975d69 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_utils.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_utils.c @@ -42,9 +42,9 @@ * @{ */ #define UTILS_MAX_FREQUENCY_SCALE0 160000000U /*!< Maximum frequency for system clock at power scale0, in Hz */ -#define UTILS_MAX_FREQUENCY_SCALE1 100000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ -#define UTILS_MAX_FREQUENCY_SCALE2 50000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ -#define UTILS_MAX_FREQUENCY_SCALE3 24000000U /*!< Maximum frequency for system clock at power scale3, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE1 110000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE2 55000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE3 25000000U /*!< Maximum frequency for system clock at power scale3, in Hz */ /* Defines used for PLL range */ #define UTILS_PLLVCO_INPUT_MIN 4000000U /*!< Frequency min for PLLVCO input, in Hz */ @@ -160,7 +160,8 @@ static ErrorStatus UTILS_PLL_IsBusy(void); */ /** - * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with HCLK + * as SysTick clock source. * @note When a RTOS is used, it is recommended to avoid changing the Systick * configuration by calling this function, for a delay use rather osDelay RTOS service. * @param HCLKFrequency HCLK frequency in Hz @@ -174,13 +175,58 @@ void LL_Init1msTick(uint32_t HCLKFrequency) } /** - * @brief This function provides accurate delay (in milliseconds) based + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with HCLK/8 + * as SysTick clock source. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param HCLKFrequency HCLK frequency in Hz + * @retval None + */ +void LL_Init1msTick_HCLK_Div8(uint32_t HCLKFrequency) +{ + /* Configure the SysTick to have 1ms time base with HCLK/8 as SysTick clock source */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / 8000U) - 1UL); + SysTick->VAL = 0UL; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with LSE as SysTick clock source. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * LSESYS needs to be enabled to get LSE working as SysTick clock source. + * @retval None + */ +void LL_Init1msTick_LSE(void) +{ + /* Configure the SysTick to have 1ms time base with LSE as SysTick clock source */ + SysTick->LOAD = (uint32_t)((LSE_VALUE / 1000U) - 1UL); + SysTick->VAL = 0UL; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with LSI as SysTick clock source. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @retval None + */ +void LL_Init1msTick_LSI(void) +{ + /* Configure the SysTick to have 1ms time base with LSI as SysTick clock source */ + SysTick->LOAD = (uint32_t)((LSI_VALUE / 1000U) - 1UL); + SysTick->VAL = 0UL; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based * on SysTick counter flag * @note When a RTOS is used, it is recommended to avoid using blocking delay * and use rather osDelay service. * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which * will configure Systick to 1ms - * @param Delay specifies the delay time length, in milliseconds. + * @param Delay specifies the minimum delay time length, in milliseconds. * @retval None */ diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 57a13ebf5b..d96b4b1876 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -16,7 +16,7 @@ * STM32L4: 1.13.4 * STM32L5: 1.0.6 * STM32MP1: 1.6.0 - * STM32U5: 1.4.0 + * STM32U5: 1.5.0 * STM32WB: 1.14.1 * STM32WBA: 1.2.0 * STM32WL: 1.3.0 diff --git a/system/STM32U5xx/stm32u5xx_hal_conf_default.h b/system/STM32U5xx/stm32u5xx_hal_conf_default.h index c0e8d8183b..b927140c45 100644 --- a/system/STM32U5xx/stm32u5xx_hal_conf_default.h +++ b/system/STM32U5xx/stm32u5xx_hal_conf_default.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2021-2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -150,7 +150,7 @@ extern "C" { vary depending on the variations in voltage and temperature.*/ #if !defined (LSI_STARTUP_TIMEOUT) -#define LSI_STARTUP_TIMEOUT 130UL /*!< Time out for LSI start up, in ms */ +#define LSI_STARTUP_TIMEOUT 130UL /*!< Time out for LSI start up, in us */ #endif /* LSI_STARTUP_TIMEOUT */ /** diff --git a/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c b/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c index 7e6e0a8545..d4889033ce 100644 --- a/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c +++ b/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U535CCTx.xml, STM32U535CCUx.xml * STM32U535CETx.xml, STM32U535CEUx.xml * STM32U545CETx.xml, STM32U545CEUx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -331,8 +331,8 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) WEAK const PinMap PinMap_USB_DRD_FS[] = { {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP {PA_13, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE {PA_14, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF {NC, NP, 0} diff --git a/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c b/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c index 5fcb5a4a5a..d486c38a7f 100644 --- a/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U535CCTxQ.xml, STM32U535CCUxQ.xml * STM32U535CETxQ.xml, STM32U535CEUxQ.xml * STM32U545CETxQ.xml, STM32U545CEUxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -315,8 +315,8 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) WEAK const PinMap PinMap_USB_DRD_FS[] = { {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP {PA_13, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE {PA_14, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF {NC, NP, 0} diff --git a/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c b/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c index 7029bea606..de9cea291c 100644 --- a/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U535JEYxQ.xml, STM32U545JEYxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -380,8 +380,8 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) WEAK const PinMap PinMap_USB_DRD_FS[] = { {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP {PA_13, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE {PA_14, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF {NC, NP, 0} diff --git a/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c b/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c index 111e7c4694..41ba053d33 100644 --- a/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535NCYxQ.xml, STM32U535NEYxQ.xml * STM32U545NEYxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -327,8 +327,8 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) WEAK const PinMap PinMap_USB_DRD_FS[] = { {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP {PA_13, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE {PA_14, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF {NC, NP, 0} diff --git a/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c index 0723a5c1de..9b5ccd3c41 100644 --- a/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBIx.xml, STM32U535RCIx.xml * STM32U535REIx.xml, STM32U545REIx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -401,8 +401,8 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) WEAK const PinMap PinMap_USB_DRD_FS[] = { {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP {PA_13, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE {PA_14, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF {PC_9, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE diff --git a/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c index fd4b748f1c..7ba4cd11a6 100644 --- a/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBIxQ.xml, STM32U535RCIxQ.xml * STM32U535REIxQ.xml, STM32U545REIxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -386,8 +386,8 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) WEAK const PinMap PinMap_USB_DRD_FS[] = { {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP {PA_13, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE {PA_14, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF {PC_9, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE diff --git a/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c index fd0124cf6f..c9ce7f9324 100644 --- a/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBTx.xml, STM32U535RCTx.xml * STM32U535RETx.xml, STM32U545RETx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -401,8 +401,8 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) WEAK const PinMap PinMap_USB_DRD_FS[] = { {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP {PA_13, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE {PA_14, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF {PC_9, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE diff --git a/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c index 01f7554346..da1bea589d 100644 --- a/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBTxQ.xml, STM32U535RCTxQ.xml * STM32U535RETxQ.xml, STM32U545RETxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -386,8 +386,8 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) WEAK const PinMap PinMap_USB_DRD_FS[] = { {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP {PA_13, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE {PA_14, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF {PC_9, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE diff --git a/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c index 79dda1dfa5..b39e24ea56 100644 --- a/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCIx.xml, STM32U535VEIx.xml * STM32U545VEIx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -452,8 +452,8 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) WEAK const PinMap PinMap_USB_DRD_FS[] = { {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP {PA_13, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE {PA_14, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF {PC_9, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE diff --git a/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c index 273ea8c267..bcb7fcafba 100644 --- a/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCIxQ.xml, STM32U535VEIxQ.xml * STM32U545VEIxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -447,8 +447,8 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) WEAK const PinMap PinMap_USB_DRD_FS[] = { {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP {PA_13, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE {PA_14, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF {PC_9, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE diff --git a/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c index 1cda066b37..06b808089a 100644 --- a/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCTx.xml, STM32U535VETx.xml * STM32U545VETx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -452,8 +452,8 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) WEAK const PinMap PinMap_USB_DRD_FS[] = { {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP {PA_13, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE {PA_14, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF {PC_9, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE diff --git a/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c index 19717de6f7..96ed815ee2 100644 --- a/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCTxQ.xml, STM32U535VETxQ.xml * STM32U545VETxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" @@ -447,8 +447,8 @@ WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) WEAK const PinMap PinMap_USB_DRD_FS[] = { {PA_8, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF - {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM - {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {PA_11, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB_DRD_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP {PA_13, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE {PA_14, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF {PC_9, USB_DRD_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_NOE diff --git a/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c b/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c index a694abc167..2a57701f52 100644 --- a/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c +++ b/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575AGIx.xml, STM32U575AIIx.xml * STM32U585AIIx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c b/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c index 1a28b54122..0ec5e6cdad 100644 --- a/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575AGIxQ.xml, STM32U575AIIxQ.xml * STM32U585AIIxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c index aa4678ccb7..c09926217c 100644 --- a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c +++ b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U575CGTx.xml, STM32U575CGUx.xml * STM32U575CITx.xml, STM32U575CIUx.xml * STM32U585CITx.xml, STM32U585CIUx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c b/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c index 24006e6157..0dd935cc01 100644 --- a/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U575CGTxQ.xml, STM32U575CGUxQ.xml * STM32U575CITxQ.xml, STM32U575CIUxQ.xml * STM32U585CITxQ.xml, STM32U585CIUxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c b/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c index a51a64d1bb..51da76a189 100644 --- a/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575OGYxQ.xml, STM32U575OIYxQ.xml * STM32U585OIYxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c b/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c index 1b1fce3e63..8c1cbca52e 100644 --- a/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c +++ b/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575QGIx.xml, STM32U575QIIx.xml * STM32U585QIIx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c b/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c index 9b91559d72..9c214d1080 100644 --- a/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575QGIxQ.xml, STM32U575QIIxQ.xml * STM32U585QIIxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c b/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c index 2657b67c59..daccb3201e 100644 --- a/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c +++ b/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575RGTx.xml, STM32U575RITx.xml * STM32U585RITx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c b/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c index e227d38e55..2e7cadf95c 100644 --- a/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575RGTxQ.xml, STM32U575RITxQ.xml * STM32U585RITxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c b/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c index a36cc6b4ae..80d3efb887 100644 --- a/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c +++ b/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575VGTx.xml, STM32U575VITx.xml * STM32U585VITx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c b/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c index 3454a17d4f..de410e0fc8 100644 --- a/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575VGTxQ.xml, STM32U575VITxQ.xml * STM32U585VITxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c b/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c index 4811e4ad5d..494bb5e4fc 100644 --- a/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c +++ b/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575ZGTx.xml, STM32U575ZITx.xml * STM32U585ZITx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c b/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c index d46d303d62..390c9b5007 100644 --- a/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575ZGTxQ.xml, STM32U575ZITxQ.xml * STM32U585ZITxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c b/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c index 786203d4b7..be0e3167d3 100644 --- a/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c +++ b/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595AIHx.xml, STM32U595AJHx.xml * STM32U5A5AJHx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c b/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c index c51b85d0d2..86b79353aa 100644 --- a/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595AIHxQ.xml, STM32U595AJHxQ.xml * STM32U5A5AJHxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c b/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c index 86907ec4bf..ff6315cc95 100644 --- a/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c +++ b/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595QIIx.xml, STM32U595QJIx.xml * STM32U5A5QJIx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c index f573c284ee..d3ef04e5d0 100644 --- a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595QIIxQ.xml, STM32U595QJIxQ.xml * STM32U5A5QIIxQ.xml, STM32U5A5QJIxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c b/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c index bfbe740262..ff243bbeed 100644 --- a/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c +++ b/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595RITx.xml, STM32U595RJTx.xml * STM32U5A5RJTx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c b/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c index 70195bcc2e..be97176779 100644 --- a/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595RITxQ.xml, STM32U595RJTxQ.xml * STM32U5A5RJTxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c b/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c index 92988f3f37..b7f9e69cbe 100644 --- a/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c +++ b/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595VITx.xml, STM32U595VJTx.xml * STM32U599VJTx.xml, STM32U5A5VJTx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c b/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c index 3a39b3073e..12a56b71af 100644 --- a/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U595VITxQ.xml, STM32U595VJTxQ.xml * STM32U599VITxQ.xml, STM32U599VJTxQ.xml * STM32U5A5VJTxQ.xml, STM32U5A9VJTxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c b/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c index 27692d257e..8ab496b4f7 100644 --- a/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c +++ b/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595ZITx.xml, STM32U595ZJTx.xml * STM32U5A5ZJTx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c index f017c4993a..4139a24ab6 100644 --- a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U595ZITxQ.xml, STM32U595ZJTxQ.xml * STM32U599ZITxQ.xml, STM32U599ZJTxQ.xml * STM32U5A5ZJTxQ.xml, STM32U5A9ZJTxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c b/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c index f9800a7414..fecabdb406 100644 --- a/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595ZIYxQ.xml, STM32U595ZJYxQ.xml * STM32U5A5ZJYxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c b/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c index 2fa7095e19..c7633ada6c 100644 --- a/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U599BJYxQ.xml, STM32U5A9BJYxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c b/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c index 4290d0882d..dda44d8850 100644 --- a/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U599NIHxQ.xml, STM32U599NJHxQ.xml * STM32U5A9NJHxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c b/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c index 629fb5dac3..d2e8001888 100644 --- a/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U599ZIYxQ.xml, STM32U599ZJYxQ.xml * STM32U5A9ZJYxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PeripheralPins.c b/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PeripheralPins.c index e62660f63e..25405cda8e 100644 --- a/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PeripheralPins.c +++ b/variants/STM32U5xx/U5F7V(I-J)T_U5G7VJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U5F7VITx.xml, STM32U5F7VJTx.xml * STM32U5G7VJTx.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PeripheralPins.c b/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PeripheralPins.c index 2d33246459..62c4c43a18 100644 --- a/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F7V(I-J)TxQ_U5G7VJTxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U5F7VITxQ.xml, STM32U5F7VJTxQ.xml * STM32U5G7VJTxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c index ac8063373c..9fefaeba4f 100644 --- a/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F9BJYxQ.xml, STM32U5G9BJYxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PeripheralPins.c index 3686c3e5c8..588082845c 100644 --- a/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9NJHxQ_U5G9NJHxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F9NJHxQ.xml, STM32U5G9NJHxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PeripheralPins.c index 11fb3e997b..1f23661238 100644 --- a/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9V(I-J)TxQ_U5G9VJTxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U5F9VITxQ.xml, STM32U5F9VJTxQ.xml * STM32U5G9VJTxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PeripheralPins.c index bc75b79656..3455aa1a05 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9Z(I-J)JxQ_U5G9ZJJxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U5F9ZIJxQ.xml, STM32U5F9ZJJxQ.xml * STM32U5G9ZJJxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PeripheralPins.c index 0e3cd9b767..cdcb62046f 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9Z(I-J)TxQ_U5G9ZJTxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U5F9ZITxQ.xml, STM32U5F9ZJTxQ.xml * STM32U5G9ZJTxQ.xml - * CubeMX DB release 6.0.100 + * CubeMX DB release 6.0.110 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h"