CFS Interrupt Enable in mis or mie CSR

[SteveZ-Cal]

Based on the most updated Data sheet, it seems that

CFS Interrupt

The CFS provides a single high-level-triggered interrupt request signal mapped to the CPU’s fast interrupt channel 1. Once triggered, the interrupt becomes pending (if enabled in the mis CSR) and has to be explicitly cleared again by writing zero to the according mip CSR bit. See section Processor Interrupts for more information.

However, I don’t seem to find mis CSR only the mie CSR, is it a typo?

In addition,

(1) While the address of mie (0x304), mip (0x344), the size corresponding to those two CSRs on vhdl neorv32_package seems to be only 12 bits, while the assumed size is 32 bits, what’s the purpose behind this?

(2) I just want to confirm that we first need to manually set its corresponding bit in mie to 1 before we set cfs_irq to 1; additionally after triggering the cfs_irq, we need to clear it manually by set its corresponding bit in mip to 0.

(3) As for the process of (interpreting address allocation during bootloader file upload) : If I upload (using uart) a simple hello_world_exe.bin at 0x00, since uart0 put bytes by bytes at 0x00, does it actually imply the exact 0x304 byte position on that binary file I just uploaded should be the content of mie?

(4) Follow up (3), if file uploaded at 0x00 is a zephyr file while I boot from 0x20000, generally speaking will neorv32 recognize mie at (0x304)?

[stnolting]

Hey there!

However, I don’t seem to find mis CSR only the mie CSR, is it a typo?

Yes, this is a typo 🙈 I just fixed that: f82b211

(1) While the address of mie (0x304), mip (0x344), the size corresponding to those two CSRs on vhdl neorv32_package seems to be only 12 bits, while the assumed size is 32 bits, what’s the purpose behind this?

What do you mean by "size"? Both CSRs are 32 bits wide but not all of these bits are actually used so they're hardwired to zero.

(2) I just want to confirm that we first need to manually set its corresponding bit in mie to 1 before we set cfs_irq to 1; additionally after triggering the cfs_irq, we need to clear it manually by set its corresponding bit in mip to 0.

That's right.

Each bit in mie enables the corresponding interrupt source. The same bit gets set in mip when the according interrupt source has fired (becomes pending). The fast interrupt requests (FIRQs, like the CFU interrupt) require to be manually acknowledged/cleared by writing zero to the according bit in mip. Otherwise they will keep triggering the interrupt handler over and over again.

(3) As for the process of (interpreting address allocation during bootloader file upload) : If I upload (using uart) a simple hello_world_exe.bin at 0x00, since uart0 put bytes by bytes at 0x00, does it actually imply the exact 0x304 byte position on that binary file I just uploaded should be the content of mie?

(4) Follow up (3), if file uploaded at 0x00 is a zephyr file while I boot from 0x20000, generally speaking will neorv32 recognize mie at (0x304)?

I think there is just a misunderstanding 😉

Memory addresses and CSR (= control and status register) addresses are two separate things. The CSRs are mapped to a "private" 12-bit address space right inside of the CPU core that is only accessible via special CSR instructions. These registers are not memory-mapped and cannot be accessed using load/store operations.

[SteveZ-Cal]

Thank you so much for the reply !! :)

Two more quick follow up question I had:

(1) For CSRs, do we generally set bits in C or VHDL? If it's in C, what would be its corresponding API for it, and If my assumption is correct: (Ex: mip), if I want to clear manually for FIRQ 1, do I need to set CSR_MIP_FIRQ1P = 0 in C?

(2) For CSRs (12-bit), how to interpret the way each bit mapped to the corresponding Name: (Ex: mip), given that there are 16 FIRQ, you need at least 16 bit if it's one hot encoding, while there's only 12-bit. Are they abstracted away by the VHDL?

[stnolting]

Thank you so much for the reply !! :)

You're welcome!

(1) For CSRs, do we generally set bits in C or VHDL? If it's in C, what would be its corresponding API for it, and If my assumption is correct: (Ex: mip), if I want to clear manually for FIRQ 1, do I need to set CSR_MIP_FIRQ1P = 0 in C?

The VHDL code describes the digital circuit behind the CSRs on which the actual application software (C) is based upon. RISC-V defines special instructions to read/write/clear/set those CSRs. The NEORV32 software framework provides some simplified wrappers functions for this that are defined in sw/lib/include/neorv32_cpu.h. Here are some quick links to the Doxygen documentation of those functions:

• 📚 neorv32_cpu_csr_read()
• 📚 neorv32_cpu_csr_write()
• 📚 neorv32_cpu_csr_set()
• 📚 neorv32_cpu_csr_clr()

So if you want to clear CSR_MIP_FIRQ1P in mip you can do

neorv32_cpu_csr_clr(CSR_MIP, 1 << CSR_MIP_FIRQ1P);

(2) For CSRs (12-bit), how to interpret the way each bit mapped to the corresponding Name: (Ex: mip), given that there are 16 FIRQ, you need at least 16 bit if it's one hot encoding, while there's only 12-bit. Are they abstracted away by the VHDL?

I am still not sure what you mean by this "12-bit". 😅

• The mip CSR layout is shown in the according section of the data sheet: mip
• The individual bits / bit indices are defined in sw/lib/include/neorv32_cpu_csr.h and are also described in the according Doxygen section