Is Vivado xsim supposed to work out of the box for the neorv32_tb_simple?

[Sam-Vervaeck]

Hey, I would like to use the neorv32 for my thesis project and I have been going through the user guide and documentation to get it up and running. I am pretty new to using a full rv soc and would like to ask for some clarification on some of the user guide steps.

First some context: I got through chapters 1 and 2 already on my own to setup the toolchain and have blinky running on my fpga. I am using an Arty A7-100T board and based the constraints file on the Digilent online reference file and the Arty A7-35T example file in the neorv32 boards section. I decided on using the neorv32_test_setup_bootloader top file and that worked out. I am using Vivado 2019.1, I cannot change to another version of Vivado.

I wanted to run the core in simulation next to look at the waves for the blinky example. I set neorv32_tb_simple as top. However, when I hit run simulation in Vivado I get an error that xsim_2.c has failed to compile and the elaborate step has therefore failed with errors.

Now to my questions:

1. I noticed there are some files marked by Vivado for containing unsupported VHDL-2008 syntax. I have changed the properties of those files to specify they use VHDL-2008 and not touched the rest. Do I have to do this for the whole rtl folder?
2. Chapter 13 in the user guide seems to indicate the neorv32_tb_simple file should work out of the box? It does indeed contain a clock generation already, so do I need to add anything to it?
3. Is it a bad idea to use Vivado to simulate the neorv32?

Ty for your time and help!

[stnolting]

Hey @Sam-Vervaeck!

I would like to use the neorv32 for my thesis project

Great to hear! :)

I am using Vivado 2019.1, I cannot change to another version of Vivado.

I am using Vivado 2019.2, so that should be fine.

error that xsim_2.c has failed to compile and the elaborate step has therefore failed with errors.

I never saw that error. Maybe an installation / rights issue? But you can synthesize and generate a bitstream, right?

1. I noticed there are some files marked by Vivado for containing unsupported VHDL-2008 syntax. I have changed the properties of those files to specify they use VHDL-2008 and not touched the rest. Do I have to do this for the whole rtl folder?

I don't think so. At least I cannot find any VHDL2008-realted settings in my default project. However, it won't hurt if you enable VHDL2008 support.

2. Chapter 13 in the user guide seems to indicate the neorv32_tb_simple file should work out of the box? It does indeed contain a clock generation already, so do I need to add anything to it?

This testbench provides reset and clock generators, some peripheral and memory stubs and a processor instance with all (most) options enabled. So, no, you could start with this and then customize the configuration of required.

3. Is it a bad idea to use Vivado to simulate the neorv32?

Vivado is quite complex and consumes a lot of processing power. However, it has a very nice simulator that is easy to use. For every day simulation I also prefer simulations using Vivado. 👍

[Sam-Vervaeck]

Could you show that error log?

It is quite long, I made a minimal working testbench example first to see if I would still get the error with only the clock generation in it from your neorv32 simple testbench. I added it to the neorv32 library in Vivado as well:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

library neorv32;
use neorv32.neorv32_package.all;
use neorv32.neorv32_application_image.all; -- this file is generated by the image generator

use std.textio.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity test_tb is
--  Port ( );
end test_tb;

architecture Behavioral of test_tb is

  constant f_clock_c               : natural := 100000000; -- main clock in Hz
  constant t_clock_c        : time := (1 sec) / f_clock_c;

  -- generators --
  signal clk_gen, rst_gen : std_ulogic := '0';

begin

  clk_gen <= not clk_gen after (t_clock_c/2);
  rst_gen <= '0', '1' after 60*(t_clock_c/2);    

end Behavioral;

Running simulation with this file as top still gives me the same error with a shorter log:

launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sam/Documents/thesis/thesis_neorv32/work/work.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'test_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/sam/Documents/thesis/thesis_neorv32/work/work.sim/sim_1/behav/xsim'
xvhdl --relax -prj test_tb_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/home/sam/Documents/thesis/thesis_neorv32/rtl/core/neorv32_package.vhd" into library neorv32
INFO: [VRFC 10-163] Analyzing VHDL file "/home/sam/Documents/thesis/thesis_neorv32/rtl/core/neorv32_application_image.vhd" into library neorv32
INFO: [VRFC 10-163] Analyzing VHDL file "/home/sam/Documents/thesis/thesis_neorv32/rtl/core/neorv32_bootloader_image.vhd" into library neorv32
INFO: [VRFC 10-163] Analyzing VHDL file "/home/sam/Documents/thesis/thesis_neorv32/work/work.srcs/sim_1/new/test_tb.vhd" into library neorv32
INFO: [VRFC 10-3107] analyzing entity 'test_tb'
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/sam/Documents/thesis/thesis_neorv32/work/work.sim/sim_1/behav/xsim'
xelab -wto e25755983cdc4d3ebf38b47c8fcfde88 --debug typical --relax --mt 8 -L neorv32 -L secureip --snapshot test_tb_behav neorv32.test_tb -log elaborate.log
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: /tools/Xilinx/Vivado/2019.1/bin/unwrapped/lnx64.o/xelab -wto e25755983cdc4d3ebf38b47c8fcfde88 --debug typical --relax --mt 8 -L neorv32 -L secureip --snapshot test_tb_behav neorv32.test_tb -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package ieee.math_real
Compiling package neorv32.neorv32_package
Compiling package neorv32.neorv32_application_image
Compiling architecture behavioral of entity neorv32.test_tb
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/test_tb_behav/obj/xsim_1.c.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting... 
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-99] Step results log file:'/home/sam/Documents/thesis/thesis_neorv32/work/work.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/sam/Documents/thesis/thesis_neorv32/work/work.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

I have not yet found a way to have a more verbose error chain from the elaborate step.

[stnolting]

This is what I get through cutecom when I connect after programming the bitstream and pressing the reset button on my Arty.

That is the default build-in bootloader. You can use that to upload your blinky program and then run it: UG: https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart

But your program will only reside in RAM - so it is not permanently there. If you want to "bake in" your custom program and let it boot right after reset you need to change to boot configuration: https://stnolting.github.io/neorv32/ug/#_installing_an_executable_directly_into_memory

Running simulation with this file as top still gives me the same error with a shorter log:

This seems to be an OS issue... Which OS are you using?

Maybe this can help:

• https://support.xilinx.com/s/question/0D52E00006hpLOhSAM/20192-error-xsim-433409-failed-to-compile-generated-c-file-xsimdirtestbenchbehavobjxsim1c?language=en_US
• https://support.xilinx.com/s/question/0D52E00006hphnVSAQ/one-solution-to-error-failed-to-compile-generated-c-file-xsimdir-xsim1c?language=en_US

[Sam-Vervaeck]

That is the default build-in bootloader. You can use that to upload your blinky program and then run it

Ah my bad, I thought chapter 2 from the tutorial was performing this bake in way booting the blinky demo. I'll look at the chapter for baking it in!

Maybe this can help:

I'll check this out and come back to you!

[Sam-Vervaeck]

I used the approm top file and blinky started working with the counting LEDs without problem. I redid the bootloader top file as well and uploaded the blinky binary and that also executed perfectly. So thank you already for all your help with that!

Then I looked at your link, I did not really go into the technical posts they mention and just implemented the solution they propose: installing the libncurses5 package. With that installed my simulation of my working example test bench and your neorv32 simple testbench now starts without problem. So that is both problems solved!

Thank you for your clear communication and time :).

[stnolting]

Great to hear! 👍