diff --git a/M2M/vhdl/i2c/cpu_to_i2c_master.vhd b/M2M/vhdl/i2c/cpu_to_i2c_master.vhd
index ede71f4b..9576db4a 100644
--- a/M2M/vhdl/i2c/cpu_to_i2c_master.vhd
+++ b/M2M/vhdl/i2c/cpu_to_i2c_master.vhd
@@ -85,18 +85,18 @@ begin
       end if;
       start          <= start(2 downto 0) & start(0);
 
-      if cpu_wr_en = '1' and cpu_addr_i = REG_I2C_CONFIG then
+      if cpu_wr_en = '1' and cpu_addr_i(11 downto 0) = REG_I2C_CONFIG(11 downto 0) then
         i2c_addr_o <= cpu_wr_data_i( 7 downto  0);
         num_bytes  <= cpu_wr_data_i(11 downto  8);
         i2c_bus_o  <= to_integer(unsigned(cpu_wr_data_i(15 downto 13)));
         start(0)   <= '1';
       end if;
       if cpu_rd_en = '1' then
-        if cpu_addr_i = REG_I2C_CONFIG then
+        if cpu_addr_i(11 downto 0) = REG_I2C_CONFIG(11 downto 0) then
           cpu_rd_data_o( 7 downto  0) <= i2c_addr_o;
           cpu_rd_data_o(11 downto  8) <= num_bytes;
           cpu_rd_data_o(15 downto 13) <= std_logic_vector(to_unsigned(i2c_bus_o, 3));
-        elsif cpu_addr_i = REG_I2C_STATUS then
+        elsif cpu_addr_i(11 downto 0) = REG_I2C_STATUS(11 downto 0) then
           cpu_rd_data_o(3 downto 0) <= response_i(3) & nack & response_i(1 downto 0);
           nack <= '0';
         end if;
diff --git a/M2M/vhdl/i2c/rtc_master.vhd b/M2M/vhdl/i2c/rtc_master.vhd
index 7cf46e7e..844e42f0 100644
--- a/M2M/vhdl/i2c/rtc_master.vhd
+++ b/M2M/vhdl/i2c/rtc_master.vhd
@@ -88,12 +88,18 @@ architecture synthesis of rtc_master is
 
   constant C_ACTION_LIST_WRITE_R3 : action_list_t := (
     -- This writes to the RTC
-    0 => (WAIT_CMD,      X"F1", X"0001"),   -- Wait until I2C is idle
-    1 => (SHIFT_OUT_CMD, X"00", X"0005"),   -- Prepare to write to RTC
-    2 => (WRITE_CMD,     X"F0", X"08DE"),   -- Send eight bytes from RTC
-    3 => (WAIT_CMD,      X"F1", X"0000"),   -- Wait until I2C command is accepted
-    4 => (WAIT_CMD,      X"F1", X"0001"),   -- Wait until I2C is idle
-    5 => (END_CMD,       X"00", X"0000")
+     0 => (WAIT_CMD,      X"F1", X"0001"),   -- Wait until I2C is idle
+     1 => (WRITE_CMD,     X"00", X"0841"),   -- Prepare to write 0x41 to address 0x08
+     2 => (WRITE_CMD,     X"F0", X"02DE"),   -- Send two bytes to RTC
+     3 => (WAIT_CMD,      X"F1", X"0000"),   -- Wait until I2C command is accepted
+     4 => (WAIT_CMD,      X"F1", X"0001"),   -- Wait until I2C is idle
+     5 => (SHIFT_OUT_CMD, X"00", X"0005"),   -- Prepare to write to RTC
+     6 => (WRITE_CMD,     X"F0", X"08DE"),   -- Send eight bytes to RTC
+     7 => (WAIT_CMD,      X"F1", X"0000"),   -- Wait until I2C command is accepted
+     8 => (WAIT_CMD,      X"F1", X"0001"),   -- Wait until I2C is idle
+     9 => (WRITE_CMD,     X"00", X"0801"),   -- Prepare to write 0x01 to address 0x08
+    10 => (WRITE_CMD,     X"F0", X"02DE"),   -- Send two bytes from RTC
+    11 => (END_CMD,       X"00", X"0000")
    );
 
   -- For the R5 board:
@@ -157,7 +163,23 @@ architecture synthesis of rtc_master is
   pure function post_read(board : string; arg : std_logic_vector) return std_logic_vector is
   begin
     if board = "MEGA65_R3" then
-      return arg(55 downto 0) & X"00";
+      if arg(23) = '1' then
+        -- 24 hour format
+        return (arg(55 downto 0) and X"FFFFFFFF7FFFFF") & X"00";
+      else
+        -- 12 hour format
+        if arg(21) = '1' then
+          -- PM
+          if arg(19 downto 16) < "1000" then
+            return ((arg(55 downto 0) and X"FFFFFFFFDFFFFF") + X"000000120000") & X"00";
+          else
+            return ((arg(55 downto 0) and X"FFFFFFFFDFFFFF") + X"000000080000") & X"00";
+          end if;
+        else
+          -- AM
+          return arg(55 downto 0) & X"00";
+        end if;
+      end if;
     else
       -- Valid for R4 and R5
       return arg(39 downto 32) & arg(63 downto 40) & arg(31 downto 0);