From 87b7c68e11a44ac09091a2569a083f361297cf99 Mon Sep 17 00:00:00 2001 From: sy2002 Date: Sun, 30 Aug 2015 01:01:25 +0200 Subject: [PATCH 1/2] mandelbrot.asm runs on hardware --- demos/mandel.asm | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/demos/mandel.asm b/demos/mandel.asm index d6154985..24d92918 100644 --- a/demos/mandel.asm +++ b/demos/mandel.asm @@ -1,4 +1,6 @@ - .ORG 0x0000 + .ORG 0x8000 + +#define FPGA ; #define POINTER R12 ; From ef661394d3de23b0e0a5e2c6b77896df4d137038 Mon Sep 17 00:00:00 2001 From: sy2002 Date: Sun, 30 Aug 2015 14:43:01 +0200 Subject: [PATCH 2/2] HEUREKA monitor, various tests run on SD card on hardware with 256 registers, 32kB RAM @ 9600 baud --- test_programs/uart.asm | 3 +-- vhdl/block_ram.vhd | 2 +- vhdl/env1.vhd | 50 ++++++++++++++++++++++++++++++++++++++++-- vhdl/env1_globals.vhd | 5 +++-- vhdl/fifo_uart.vhd | 38 ++++++++++++++++++++++---------- 5 files changed, 79 insertions(+), 19 deletions(-) diff --git a/test_programs/uart.asm b/test_programs/uart.asm index d2904212..c72429e1 100644 --- a/test_programs/uart.asm +++ b/test_programs/uart.asm @@ -24,8 +24,7 @@ _IO$GETC_LOOP MOVE @R0, R3 ; read status register MOVE @R1, R8 ; store received character ... MOVE R8, @R12 ; ... and write it to TIL - --MOVE 0, @R0 ; clear read latch - + _IO$SETC_WAIT MOVE @R0, R3 ; read status register AND 0x0002, R3 ; ready to transmit? RBRA _IO$SETC_WAIT, Z ; loop until ready diff --git a/vhdl/block_ram.vhd b/vhdl/block_ram.vhd index 40b7a027..b4474162 100644 --- a/vhdl/block_ram.vhd +++ b/vhdl/block_ram.vhd @@ -33,7 +33,7 @@ end BRAM; architecture beh of BRAM is type bram_t is array (0 to BLOCK_RAM_SIZE - 1) of std_logic_vector(15 downto 0); -signal bram : bram_t := (others => x"baba"); +signal bram : bram_t := (others => x"0000"); signal output : std_logic_vector(15 downto 0); diff --git a/vhdl/env1.vhd b/vhdl/env1.vhd index 60e2586d..04e8d13a 100644 --- a/vhdl/env1.vhd +++ b/vhdl/env1.vhd @@ -151,6 +151,20 @@ port ( ); end component; +component SyTargetCounter is +generic ( + COUNTER_FINISH : integer; + COUNTER_WIDTH : integer range 2 to 32 +); +port ( + clk : in std_logic; + reset : in std_logic; + + cnt : out std_logic_vector(COUNTER_WIDTH - 1 downto 0); + overflow : out std_logic := '0' +); +end component; + signal cpu_addr : std_logic_vector(15 downto 0); signal cpu_data : std_logic_vector(15 downto 0); signal cpu_data_dir : std_logic; @@ -168,6 +182,12 @@ signal til_reg1_enable : std_logic; -- 50 MHz as long as we did not solve the timing issues of the register file signal SLOW_CLOCK : std_logic := '0'; +-- reset generator: either use the button or the initial reset counter +--signal reset_sig : std_logic; +--signal reset_done : std_logic := '0'; +--signal reset_cnt : std_logic_vector(5 downto 0); +--signal reset_overflow : std_logic; + begin -- QNICE CPU @@ -268,7 +288,33 @@ begin if rising_edge(CLK) then SLOW_CLOCK <= not SLOW_CLOCK; end if; - end process; - + end process; + +-- reset_delay : SyTargetCounter +-- generic map +-- ( +-- COUNTER_FINISH => 63, +-- COUNTER_WIDTH => 6 +-- ) +-- port map +-- ( +-- clk => SLOW_CLOCK and not reset_done, +-- reset => RESET_N, +-- cnt => reset_cnt, +-- overflow => reset_overflow +-- ); +-- +-- reset_done_handler : process (reset_overflow, RESET_N) +-- begin +-- if RESET_N = '0' then +-- reset_done <= '0'; +-- else +-- if rising_edge(reset_overflow) then +-- reset_done <= '1'; +-- end if; +-- end if; +-- end process; +-- +-- reset_sig <= reset_cnt(0) or reset_cnt(1) or reset_cnt(2) or reset_cnt(3) or reset_cnt(4) or reset_cnt(5); end beh; diff --git a/vhdl/env1_globals.vhd b/vhdl/env1_globals.vhd index 10ba4ae3..16dfb617 100644 --- a/vhdl/env1_globals.vhd +++ b/vhdl/env1_globals.vhd @@ -15,7 +15,7 @@ constant ROM_SIZE : integer := 2233; -- size of lower register bank: should be 256 -- set to 16 during development for faster synthesis, routing, etc. -constant SHADOW_REGFILE_SIZE : integer := 16; +constant SHADOW_REGFILE_SIZE : integer := 256; -- size of the block RAM in 16bit words: should be 32768 -- set to 256 during development for tracability during simulation @@ -26,10 +26,11 @@ constant BLOCK_RAM_SIZE : integer := 32768; -- UART_DIVISOR = 100,000,000 / (16 x BAUD_RATE) -- 2400 -> 2604 -- 9600 -> 651 +-- 19200 -> 326 -- 115200 -> 54 -- 1562500 -> 4 -- 2083333 -> 3 -constant UART_DIVISOR : natural := 325; -- as long as we are using SLOW_CLOCK with 50 MHz +constant UART_DIVISOR : natural := 326; -- as long as we are using SLOW_CLOCK with 50 MHz constant UART_FIFO_SIZE : natural := 16; end env1_globals; diff --git a/vhdl/fifo_uart.vhd b/vhdl/fifo_uart.vhd index 7a3b752e..3067939c 100644 --- a/vhdl/fifo_uart.vhd +++ b/vhdl/fifo_uart.vhd @@ -67,7 +67,7 @@ end component; -- FIFO type FIFO_RAM is array(0 to FIFO_SIZE - 1) of std_logic_vector(8 downto 0); -signal FIFO : FIFO_RAM; +signal FIFO : FIFO_RAM := (others => "000000000"); signal FIFO_WP : unsigned(integer(ceil(log2(real(FIFO_SIZE)))) - 1 downto 0) := (others => '0'); signal FIFO_RP : unsigned(integer(ceil(log2(real(FIFO_SIZE)))) - 1 downto 0) := (others => '0'); @@ -101,10 +101,14 @@ begin tx => tx ); - uart_rx : process(uart_rx_enable, uart_rx_data, rx_resetvalid, FIFO_RP, FIFO_WP) + uart_rx : process(uart_rx_enable, uart_rx_data, rx_resetvalid, FIFO_RP, FIFO_WP, reset) begin - if rx_resetvalid = '1' then - FIFO(to_integer(FIFO_RP))(8) <= '0'; + if rx_resetvalid = '1' or reset = '1' then + if reset = '1' then + FIFO(0)(8) <= '0'; + else + FIFO(to_integer(FIFO_RP))(8) <= '0'; + end if; else if rising_edge(uart_rx_enable) then FIFO(to_integer(FIFO_WP))(7 downto 0) <= uart_rx_data; @@ -113,23 +117,31 @@ begin end if; end process; - uart_inc_wp : process(uart_rx_enable, FIFO_WP) + uart_inc_wp : process(uart_rx_enable, FIFO_WP, reset) begin - if falling_edge(uart_rx_enable) then - FIFO_WP <= FIFO_WP + 1; + if reset = '1' then + FIFO_WP <= (others => '0'); + else + if falling_edge(uart_rx_enable) then + FIFO_WP <= FIFO_WP + 1; + end if; end if; end process; - uart_inc_rp : process(rx_resetvalid, FIFO_RP) - begin - if falling_edge(rx_resetvalid) then - FIFO_RP <= FIFO_RP + 1; + uart_inc_rp : process(rx_resetvalid, FIFO_RP, reset) + begin + if reset = '1' then + FIFO_RP <= (others => '0'); + else + if falling_edge(rx_resetvalid) then + FIFO_RP <= FIFO_RP + 1; + end if; end if; end process; uart_cts_controller : process (FIFO_RP, FIFO_WP) begin - if abs(signed(FIFO_RP) - signed(FIFO_WP)) > 4 then + if abs(signed(FIFO_RP) - signed(FIFO_WP)) > (FIFO_SIZE / 4) then cts <= '1'; cts_led <= '1'; else @@ -177,5 +189,7 @@ begin end if; end process; + + end beh;