From b150b08bef974b4faa7ef4dfecf1cedeecdefb33 Mon Sep 17 00:00:00 2001
From: sy2002 <code@sy2002.de>
Date: Sun, 8 Nov 2020 21:52:31 +0100
Subject: [PATCH] month update in PORE and monitor and minor documentation
 updates

---
 VERSIONS.txt                 | 2 ++
 doc/MIPS.md                  | 4 ++--
 monitor/qmon.asm             | 2 +-
 pore/boot_message.txt        | 2 +-
 pore/boot_message_mega65.txt | 2 +-
 5 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/VERSIONS.txt b/VERSIONS.txt
index a43b8db8..3228fb45 100644
--- a/VERSIONS.txt
+++ b/VERSIONS.txt
@@ -14,6 +14,8 @@ WIP sift through all issues tagged with V1.7 that tackle ISA changes
   taking two CPU cycles. This leads to an average speed of 13.21 MIPS, which
   is a speed-up of 2% compared to V1.6. The new peak performance is 14.67 MIPS
   which is an improvement of 8% compared to V1.6.
+<plus two more refactorings: non-taken branches in 1 cycle, INCRB/DECRB in
+1 cycle; more speed; see MIPS.md>  
 TODO: <WASM emulator Website needs to name the new speed, and for better
       reading, we should print the speed in bold on the website, as the
       user needs to adjust the emulation speed manually.>
diff --git a/doc/MIPS.md b/doc/MIPS.md
index 3ed5a761..3e6b5f92 100644
--- a/doc/MIPS.md
+++ b/doc/MIPS.md
@@ -4,13 +4,13 @@ QNICE-FPGA Performance Characteristics
 * The system runs with 50 MHz on all currently supported hardware targets.
 
 * The CPU is built around a variable-length state machine. This means that
-  there are instructions that are as short as two clock cycles and others that
+  there are instructions that are as short as one clock cycle and others that
   are in general as long as six clock cycles.
 
 * Slow RAM, ROM and peripheral devices can make the execution even longer, as
   they are able to add wait-states to the CPU's execution.
 
-* It is therefore difficult, to measure "The" CPU performance in MIPS
+* It is therefore difficult, to exactly measure "The" CPU performance in MIPS
   (Million Instructions Per Second). In contrast, it always depends on the
   workload that is being executed.
 
diff --git a/monitor/qmon.asm b/monitor/qmon.asm
index e52a2019..ad93ad26 100644
--- a/monitor/qmon.asm
+++ b/monitor/qmon.asm
@@ -625,7 +625,7 @@ QMON$LOAD_E1C   SUB     IO$HEX_NIBBLES, R10     ; get numeric representation of
 ;* Strings
 ;***************************************************************************************
                 
-QMON$WELCOME    .ASCII_P    "\n\nSimple QNICE-monitor - Version 1.7 (Bernd Ulmann, sy2002, September 2020)\n"
+QMON$WELCOME    .ASCII_P    "\n\nSimple QNICE-monitor - Version 1.7 (Bernd Ulmann, sy2002, November 2020)\n"
 #ifdef RAM_MONITOR
                 .ASCII_P    "Running in RAM!\n"
 #endif
diff --git a/pore/boot_message.txt b/pore/boot_message.txt
index d9142da1..ff636ac6 100644
--- a/pore/boot_message.txt
+++ b/pore/boot_message.txt
@@ -4,4 +4,4 @@ PORE$NEWLINE  .ASCII_W "\n\n"
 
 ; PORE$RESETMSG .ASCII_W "QNICE-FPGA Version 1.7 by sy2002 & MJoergen in September 2020 (GIT #"
 
-PORE$RESETMSG .ASCII_W "QNICE-FPGA V1.7 [WIP] by sy2002 & MJoergen in September 2020 (GIT #
\ No newline at end of file
+PORE$RESETMSG .ASCII_W "QNICE-FPGA V1.7 [WIP] by sy2002 & MJoergen in November 2020 (GIT #
\ No newline at end of file
diff --git a/pore/boot_message_mega65.txt b/pore/boot_message_mega65.txt
index e5f0366f..1bf73b7b 100644
--- a/pore/boot_message_mega65.txt
+++ b/pore/boot_message_mega65.txt
@@ -4,4 +4,4 @@ PORE$NEWLINE  .ASCII_W "\n\n"
 
 ; PORE$RESETMSG .ASCII_W "QNICE-FPGA @ MEGA65 Version 1.7 by sy2002 & MJoergen in September 2020 (GIT #"
 
-PORE$RESETMSG .ASCII_W "QNICE-FPGA @ MEGA65 V1.7 [WIP] by sy2002 & MJoergen in September 2020 (GIT #
\ No newline at end of file
+PORE$RESETMSG .ASCII_W "QNICE-FPGA @ MEGA65 V1.7 [WIP] by sy2002 & MJoergen in November 2020 (GIT #
\ No newline at end of file