Publish version 1.0

Version 1.0 marks the first public release of the rv32emu project,
aligning with the research paper "Accelerating RISC-V Instruction Set
Simulation with Tiered JIT Compilation," [1] which was presented at the
VMIL'24 conference [2].

[1] https://dl.acm.org/doi/10.1145/3689490.3690399
[2] https://2024.splashcon.org/home/vmil-2024

Author: jserv

Makefile

@@ -60,7 +60,7 @@ AR = emar
 endif
 SOFTFLOAT_OUT = $(abspath $(OUT)/softfloat)
 src/softfloat/build/Linux-RISCV-GCC/Makefile:
-	git submodule update --init src/softfloat/
+	git clone https://github.com/sysprog21/berkeley-softfloat-3 src/softfloat --depth=1
 SOFTFLOAT_LIB := $(SOFTFLOAT_OUT)/softfloat.a
 $(SOFTFLOAT_LIB): src/softfloat/build/Linux-RISCV-GCC/Makefile
 	$(MAKE) -C $(dir $<) BUILD_DIR=$(SOFTFLOAT_OUT) CC=$(CC) AR=$(AR)
@@ -120,7 +120,7 @@ ifeq ($(call has, GDBSTUB), 1)
 GDBSTUB_OUT = $(abspath $(OUT)/mini-gdbstub)
 GDBSTUB_COMM = 127.0.0.1:1234
 src/mini-gdbstub/Makefile:
-	git submodule update --init $(dir $@)
+	git clone https://github.com/RinHizakura/mini-gdbstub $(dir $@) --depth=1
 GDBSTUB_LIB := $(GDBSTUB_OUT)/libgdbstub.a
 $(GDBSTUB_LIB): src/mini-gdbstub/Makefile
 	$(MAKE) -C $(dir $<) O=$(dir $@)

mk/artifact.mk

@@ -1,5 +1,3 @@
-ENABLE_PREBUILT ?= 1
-
 CC ?= gcc
 CROSS_COMPILE ?= riscv-none-elf-
 
@@ -36,22 +34,11 @@ SCIMARK2_SHA1 := de278c5b8cef84ab6dda41855052c7bfef919e36
 
 SHELL_HACK := $(shell mkdir -p $(BIN_DIR)/linux-x86-softfp $(BIN_DIR)/riscv32)
 
-ifeq ($(call has, PREBUILT), 1)
-  LATEST_RELEASE := $(shell wget -q https://api.github.com/repos/sysprog21/rv32emu-prebuilt/releases/latest -O- | grep '"tag_name"' | sed -E 's/.*"tag_name": "([^"]+)".*/\1/')
-else
-  # Since rv32emu only supports the dynamic binary translation of integer instruction in tiered compilation currently,
-  # we disable the hardware floating-point and the related SIMD operation of x86.
-  CFLAGS := -m32 -mno-sse -mno-sse2 -msoft-float -O2 -Wno-unused-result -L$(BIN_DIR)
-  LDFLAGS := -lsoft-fp -lm
-
-  CFLAGS_CROSS := -march=rv32im -mabi=ilp32 -O2 -Wno-implicit-function-declaration
-  LDFLAGS_CROSS := -lm -lsemihost
-endif
+LATEST_RELEASE := $(shell wget -q https://api.github.com/repos/sysprog21/rv32emu-prebuilt/releases/latest -O- | grep '"tag_name"' | sed -E 's/.*"tag_name": "([^"]+)".*/\1/')
 
-.PHONY: artifact fetch-checksum scimark2 ieeelib
+.PHONY: artifact fetch-checksum
 
-artifact: fetch-checksum ieeelib scimark2
-ifeq ($(call has, PREBUILT), 1)
+artifact: fetch-checksum
 	$(Q)$(PRINTF) "Checking SHA-1 of prebuilt binaries ... "
 
 	$(Q)$(eval PREBUILT_X86_FILENAME := $(shell cat $(BIN_DIR)/sha1sum-linux-x86-softfp | awk '{  print $$2 };'))
@@ -71,64 +58,9 @@ ifeq ($(call has, PREBUILT), 1)
 	else \
 	    $(call notice, [OK]); \
 	fi
-else
-	git submodule update --init $(addprefix ./tests/,$(foreach tb,$(TEST_SUITES),$(tb)))
-	$(Q)for tb in $(TEST_SUITES); do \
-	    CC=$(CC) CFLAGS="$(CFLAGS)" LDFLAGS="$(LDFLAGS)" BINDIR=$(BIN_DIR)/linux-x86-softfp $(MAKE) -C ./tests/$$tb; \
-	done
-	$(Q)for tb in $(TEST_SUITES); do \
-	    CC=$(CROSS_COMPILE)gcc CFLAGS="$(CFLAGS_CROSS)" LDFLAGS="$(LDFLAGS_CROSS)" BINDIR=$(BIN_DIR)/riscv32 $(MAKE) -C ./tests/$$tb; \
-	done
-
-	$(Q)$(PRINTF) "Building standalone testbenches ...\n"
-	$(Q)for tb in $(TEST_BENCHES); do \
-	    $(CC) $(CFLAGS) -o $(BIN_DIR)/linux-x86-softfp/$$tb ./tests/$$tb.c $(LDFLAGS); \
-	done
-	$(Q)for tb in $(TEST_BENCHES); do \
-	    $(CROSS_COMPILE)gcc $(CFLAGS_CROSS) -o $(BIN_DIR)/riscv32/$$tb ./tests/$$tb.c $(LDFLAGS_CROSS); \
-	done
-
-	git submodule update --init ./tests/doom ./tests/quake
-	$(Q)$(PRINTF) "Building doom ...\n"
-	$(Q)$(MAKE) -C ./tests/doom/src/riscv CROSS=$(CROSS_COMPILE)
-	$(Q)cp ./tests/doom/src/riscv/doom-riscv.elf $(BIN_DIR)/riscv32/doom
-	$(Q)$(PRINTF) "Building quake ...\n"
-	$(Q)cd ./tests/quake && mkdir -p build && cd build && \
-	    cmake -DCMAKE_TOOLCHAIN_FILE=../port/boards/rv32emu/toolchain.cmake \
-	          -DCROSS_COMPILE=$(CROSS_COMPILE) \
-	          -DCMAKE_BUILD_TYPE=RELEASE -DBOARD_NAME=rv32emu .. && \
-	    make
-	$(Q)cp ./tests/quake/build/port/boards/rv32emu/quake $(BIN_DIR)/riscv32/quake
-
-	$(Q)(cd $(BIN_DIR)/linux-x86-softfp; for fd in *; do $(SHA1SUM) "$$fd"; done) >> $(BIN_DIR)/sha1sum-linux-x86-softfp
-	$(Q)(cd $(BIN_DIR)/riscv32; for fd in *; do $(SHA1SUM) "$$fd"; done) >> $(BIN_DIR)/sha1sum-riscv32
-endif
 
 fetch-checksum:
-ifeq ($(call has, PREBUILT), 1)
 	$(Q)$(PRINTF) "Fetching SHA-1 of prebuilt binaries ... "
 	$(Q)wget -q -O $(BIN_DIR)/sha1sum-linux-x86-softfp https://github.com/sysprog21/rv32emu-prebuilt/releases/download/$(LATEST_RELEASE)/sha1sum-linux-x86-softfp
 	$(Q)wget -q -O $(BIN_DIR)/sha1sum-riscv32 https://github.com/sysprog21/rv32emu-prebuilt/releases/download/$(LATEST_RELEASE)/sha1sum-riscv32
 	$(Q)$(call notice, [OK])
-endif
-
-scimark2:
-ifeq ($(call has, PREBUILT), 0)
-	$(Q)$(call prologue,"scimark2")
-	$(Q)$(call download,$(SCIMARK2_URL))
-	$(Q)$(call verify,$(SCIMARK2_SHA1),$(notdir $(SCIMARK2_URL)))
-	$(Q)$(call extract,"./tests/scimark2",$(notdir $(SCIMARK2_URL)))
-	$(Q)$(call epilogue,$(notdir $(SCIMARK2_URL)),$(SHA1_FILE1),$(SHA1_FILE2))
-	$(Q)$(PRINTF) "Building scimark2 ...\n"
-	$(Q)$(MAKE) -C ./tests/scimark2 CC=$(CC) CFLAGS="-m32 -O2"
-	$(Q)cp ./tests/scimark2/scimark2 $(BIN_DIR)/linux-x86-softfp/scimark2
-	$(Q)$(MAKE) -C ./tests/scimark2 clean && $(RM) ./tests/scimark2/scimark2.o
-	$(Q)$(MAKE) -C ./tests/scimark2 CC=$(CROSS_COMPILE)gcc CFLAGS="-march=rv32imf -mabi=ilp32 -O2"
-	$(Q)cp ./tests/scimark2/scimark2 $(BIN_DIR)/riscv32/scimark2
-endif
-
-ieeelib:
-ifeq ($(call has, PREBUILT), 0)
-	git submodule update --init ./src/ieeelib
-	$(Q)$(MAKE) -C ./src/ieeelib CC=$(CC) CFLAGS="$(CFLAGS)" BINDIR=$(BIN_DIR)
-endif

mk/riscv-arch-test.mk

@@ -13,7 +13,7 @@ arch-test: $(BIN) artifact
 ifeq ($(CROSS_COMPILE),)
 	$(error GNU Toolchain for RISC-V is required to build architecture tests. Please check package installation)
 endif
-	git submodule update --init $(dir $(ARCH_TEST_DIR))
+	git clone https://github.com/riscv-non-isa/riscv-arch-test $(dir $(ARCH_TEST_DIR)) --depth=1
 	$(Q)cp $(OUT)/sail_cSim/riscv_sim_RV32 tests/arch-test-target/sail_cSim/riscv_sim_RV32
 	$(Q)python3 -B $(RISCV_TARGET)/setup.py --riscv_device=$(RISCV_DEVICE)
 	$(Q)riscof run --work-dir=$(WORK) \