{"payload":{"header_redesign_enabled":false,"results":[{"id":"419230397","archived":false,"color":"#DAE1C2","followers":5,"has_funding_file":false,"hl_name":"takatz28/FIFO-BIST","hl_trunc_description":"Final project for the class \"Application Specific Integrated Circuit Development\"","language":"SystemVerilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":419230397,"name":"FIFO-BIST","owner_id":27396364,"owner_login":"takatz28","updated_at":"2021-10-21T05:32:19.525Z","has_issues":true}},"sponsorable":false,"topics":["systemverilog","fifo","clock-domain-crossing","built-in-self-test"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":55,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Atakatz28%252FFIFO-BIST%2B%2Blanguage%253ASystemVerilog","metadata":null,"csrf_tokens":{"/takatz28/FIFO-BIST/star":{"post":"6SJjGp1owF4CjzM04pcznCM_9TLvlZbj29IKR9cju6NavcgrpW0YtbgtZ_r9n3WtzUUjL_QrLW_eHBsDKw9-2A"},"/takatz28/FIFO-BIST/unstar":{"post":"8CF81608_-BUHMybzM9rhZku0R-pUDhSkL0KofEefr2CqOKL0YCo_lcxAQDU6dJ1NvuYukUN77VuuczWAqOCAQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"7g8XxNYperOWeW0P-klIv8U759EQq0eNwN185AsUGcgYW-_Old3tN-vd-Lf8xugZdkoHN4TkH2HD2MWwQUJhiQ"}}},"title":"Repository search results"}