{"payload":{"header_redesign_enabled":false,"results":[{"id":"418054847","archived":false,"color":"#DAE1C2","followers":2,"has_funding_file":false,"hl_name":"takatz28/RISCY-Processor","hl_trunc_description":"Final project for the class \"Digital Design with Verilog and SystemVerilog\"","language":"SystemVerilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":418054847,"name":"RISCY-Processor","owner_id":27396364,"owner_login":"takatz28","updated_at":"2021-10-19T18:52:47.832Z","has_issues":true}},"sponsorable":false,"topics":["processor","verilog","systemverilog","risc-processor"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":82,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Atakatz28%252FRISCY-Processor%2B%2Blanguage%253ASystemVerilog","metadata":null,"csrf_tokens":{"/takatz28/RISCY-Processor/star":{"post":"semVB38q2MLDPraah8eP4WApv9hDMAj3NRZMGTR8yHqYHDG9EazI2XA-6CfCVAx3wf8Xf7PazXhe08HfxOhvTw"},"/takatz28/RISCY-Processor/unstar":{"post":"04z6czGj9TgjEwtasJBZqU7c5HuymM47N0DD31pKuW2nWaUK9fry04GjLpCScDxhhHJm0s_zW8m9xy18OBbA6A"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"RQ37trv6d8SfhvLv78TmFK9PUPQcYZsLnuLdRmzdbYK5rel661TDdKu1tIVHjmj8peCcakkDOskzFQSI0jqryA"}}},"title":"Repository search results"}