diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 00000000..e69de29b diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index d56935f8..c2720f9a 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -18,78 +18,130 @@ jobs: runs-on: ubuntu-latest # Map a step output to a job output outputs: + accumulators: ${{ steps.accumulators.outputs.any_changed }} adder: ${{ steps.adder.outputs.any_changed }} + bus: ${{ steps.bus.outputs.any_changed }} counter: ${{ steps.counter.outputs.any_changed }} multiplexer: ${{ steps.multiplexer.outputs.any_changed }} multiplier: ${{ steps.multiplier.outputs.any_changed }} fifo: ${{ steps.fifo.outputs.any_changed }} ram: ${{ steps.ram.outputs.any_changed }} + reorder: ${{ steps.reorder.outputs.any_changed }} r2sdf_fft: ${{ steps.r2sdf_fft.outputs.any_changed }} pipe_fft: ${{ steps.pipe_fft.outputs.any_changed }} par_fft: ${{ steps.par_fft.outputs.any_changed }} wide_fft: ${{ steps.wide_fft.outputs.any_changed }} - # all_fft: ${{ steps.all_fft.outputs.any_changed }} single_filter: ${{ steps.single_filter.outputs.any_changed }} wide_filter: ${{ steps.wide_filter.outputs.any_changed }} wbpfb: ${{ steps.wbpfb.outputs.any_changed }} # Steps represent a sequence of tasks that will be executed as part of the job steps: # Checks-out only the latest commit to assess which files changed - - uses: actions/checkout@v2 + - uses: actions/checkout@v4 with: fetch-depth: 0 + submodules: recursive + - name: Assess accumulators files changes + id: accumulators + uses: tj-actions/changed-files@v41.0.0 + with: + files: | + casper_accumulators/.*\.vhd$ + casper_accumulators/run.py - name: Assess adder files changes id: adder - uses: tj-actions/changed-files@v1.2.0 + uses: tj-actions/changed-files@v41.0.0 with: files: | casper_adder/.*\.vhd$ casper_adder/run.py + - name: Assess bus files changes + id: bus + uses: tj-actions/changed-files@v41.0.0 + with: + files: | + casper_bus/.*\.vhd$ + casper_bus/run.py - name: Assess counter files changes id: counter - uses: tj-actions/changed-files@v1.2.0 + uses: tj-actions/changed-files@v41.0.0 with: files: | casper_counter/.*\.vhd$ casper_counter/run.py + - name: Assess delay files changes + id: delay + uses: tj-actions/changed-files@v41.0.0 + with: + files: | + casper_delay/.*\.vhd$ + casper_delay/run.py - name: Assess multiplexer files changes id: multiplexer - uses: tj-actions/changed-files@v1.2.0 + uses: tj-actions/changed-files@v41.0.0 with: files: | casper_multiplexer/.*\.vhd$ casper_multiplexer/run.py - name: Assess multiplier files changes id: multiplier - uses: tj-actions/changed-files@v1.2.0 + uses: tj-actions/changed-files@v41.0.0 with: files: | casper_multiplier/.*\.vhd$ casper_multiplier/run.py - name: Assess FIFO files changes id: fifo - uses: tj-actions/changed-files@v1.2.0 + uses: tj-actions/changed-files@v41.0.0 with: files: | casper_fifo/.*\.vhd$ casper_fifo/run.py + - name: Assess filter files changes + id: filter + uses: tj-actions/changed-files@v41.0.0 + with: + files: | + casper_filter/.*\.vhd$ + casper_filter/run.py + - name: Assess flow_control files changes + id: flow_control + uses: tj-actions/changed-files@v41.0.0 + with: + files: | + casper_flow_control/.*\.vhd$ + casper_flow_control/run.py + - name: Assess reorder files changes + id: reorder + uses: tj-actions/changed-files@v1.2.0 + with: + files: | + casper_reorder/.*\.vhd$ + casper_reorder/run.py + - name: Assess misc files changes + id: misc + uses: tj-actions/changed-files@v41.0.0 + with: + files: | + misc/.*\.vhd$ + misc/run.py - name: Assess RAM files changes id: ram - uses: tj-actions/changed-files@v1.2.0 + uses: tj-actions/changed-files@v41.0.0 with: files: | casper_ram/.*\.vhd$ casper_ram/run.py - name: Assess r2SDF_FFT files changes id: r2sdf_fft - uses: tj-actions/changed-files@v1.2.0 + uses: tj-actions/changed-files@v41.0.0 with: files: | r2sdf_fft/.*\.vhd$ r2sdf_fft/run.py - name: Assess PIPELINE_FFT files changes id: pipe_fft - uses: tj-actions/changed-files@v1.2.0 + uses: tj-actions/changed-files@v41.0.0 with: files: | casper_wb_fft/.*pipe\.vhd$ @@ -100,7 +152,7 @@ jobs: casper_wb_fft/fft_sepa.vhd - name: Assess PARALLEL_FFT files changes id: par_fft - uses: tj-actions/changed-files@v1.2.0 + uses: tj-actions/changed-files@v41.0.0 with: files: | casper_wb_fft/.*par\.vhd$ @@ -111,7 +163,7 @@ jobs: casper_wb_fft/fft_sepa.vhd - name: Assess WIDE_FFT files changes id: wide_fft - uses: tj-actions/changed-files@v1.2.0 + uses: tj-actions/changed-files@v41.0.0 with: files: | casper_wb_fft/.*wide\.vhd$ @@ -120,19 +172,9 @@ jobs: casper_wb_fft/run.py casper_wb_fft/tb_fft_pkg.vhd casper_wb_fft/fft_sepa.vhd - # - name: Assess ALL_FFT files changes - # id: all_fft - # uses: tj-actions/changed-files@v1.2.0 - # with: - # files: | - # casper_wb_fft/fft_gnrcs_intrfcs_pkg.vhd - # casper_wb_fft/tb_fft_functions.vhd - # casper_wb_fft/run.py - # casper_wb_fft/tb_fft_pkg.vhd - # casper_wb_fft/fft_sepa.vhd - name: Assess single_filter files changes id: single_filter - uses: tj-actions/changed-files@v1.2.0 + uses: tj-actions/changed-files@v41.0.0 with: files: | casper_filter/.*single\.vhd$ @@ -141,7 +183,7 @@ jobs: casper_filter/fil_ppf_filter.vhd - name: Assess wide_filter files changes id: wide_filter - uses: tj-actions/changed-files@v1.2.0 + uses: tj-actions/changed-files@v41.0.0 with: files: | casper_filter/.*wide\.vhd$ @@ -150,27 +192,87 @@ jobs: casper_filter/fil_ppf_filter.vhd - name: Assess wbpfb files changes id: wbpfb - uses: tj-actions/changed-files@v1.2.0 + uses: tj-actions/changed-files@v41.0.0 with: files: | casper_wbpfb/.*\.vhd$ casper_wbpfb/run.py + accumulators: + # The type of runner that the job will run on + runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master + needs: [files_changed] + if: needs.files_changed.outputs.accumulators == 'true' + + # Steps represent a sequence of tasks that will be executed as part of the job + steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version + # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it + - uses: actions/checkout@v4 + with: + submodules: 'recursive' + token: ${{ secrets.TOKEN }} + + - name: Install numpy + run: pip3 install numpy + + - id: casper_accumulators_test + run: python3 casper_accumulators/run.py --xunit-xml ./casper_accumulators/casper_accumulators_report.xml + + - name: Note casper_accumulators_test Failure + if: ${{ failure() }} + uses: action-badges/core@0.2.2 + with: + label: casper_accumulators + message: failing + message-color: "C74D1F" + file-name: casper_accumulators_test.svg + badge-branch: badges + style: flat + github-token: "${{ secrets.GITHUB_TOKEN }}" + - name: Note casper_accumulators_test Success + if: ${{ steps.casper_accumulators_test.outcome == 'success' }} + uses: action-badges/core@0.2.2 + with: + label: casper_accumulators + message: passing + message-color: "4DC71F" + file-name: casper_accumulators_test.svg + badge-branch: badges + style: flat + github-token: "${{ secrets.GITHUB_TOKEN }}" + - uses: actions/upload-artifact@v4 + with: + name: casper_accumulators_report + path: ./casper_accumulators/casper_accumulators_report.xml + if-no-files-found: 'warn' # ['warn', 'error', 'ignore'] + adder: # The type of runner that the job will run on runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master needs: [files_changed] if: needs.files_changed.outputs.adder == 'true' # Steps represent a sequence of tasks that will be executed as part of the job steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it - - uses: actions/checkout@v2 - - id: casper_adder_test - uses: VUnit/vunit_action@master + - uses: actions/checkout@v4 with: - image: ghdl/vunit:llvm - cmd: python3 casper_adder/run.py --xunit-xml ./casper_adder/casper_adder_report.xml + submodules: 'recursive' + token: ${{ secrets.TOKEN }} + - id: casper_adder_test + run: python3 casper_adder/run.py --xunit-xml ./casper_adder/casper_adder_report.xml - name: Note casper_adder_test Failure if: ${{ failure() }} @@ -194,27 +296,84 @@ jobs: badge-branch: badges style: flat github-token: "${{ secrets.GITHUB_TOKEN }}" - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 with: name: casper_adder_report path: ./casper_adder/casper_adder_report.xml if-no-files-found: 'warn' # ['warn', 'error', 'ignore'] + + bus: + # The type of runner that the job will run on + runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master + needs: [files_changed] + if: needs.files_changed.outputs.bus == 'true' + + # Steps represent a sequence of tasks that will be executed as part of the job + steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version + # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it + - uses: actions/checkout@v4 + with: + submodules: 'recursive' + token: ${{ secrets.TOKEN }} + - id: casper_bus_test + run: python3 casper_bus/run.py --xunit-xml ./casper_bus/casper_bus_report.xml + + - name: Note casper_bus_test Failure + if: ${{ failure() }} + uses: action-badges/core@0.2.2 + with: + label: casper_bus + message: failing + message-color: "C74D1F" + file-name: casper_bus_test.svg + badge-branch: badges + style: flat + github-token: "${{ secrets.GITHUB_TOKEN }}" + - name: Note casper_bus_test Success + if: ${{ steps.casper_bus_test.outcome == 'success' }} + uses: action-badges/core@0.2.2 + with: + label: casper_bus + message: passing + message-color: "4DC71F" + file-name: casper_bus_test.svg + badge-branch: badges + style: flat + github-token: "${{ secrets.GITHUB_TOKEN }}" + - uses: actions/upload-artifact@v4 + with: + name: casper_bus_report + path: ./casper_bus/casper_bus_report.xml + if-no-files-found: 'warn' # ['warn', 'error', 'ignore'] + counter: # The type of runner that the job will run on runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master needs: [files_changed] if: needs.files_changed.outputs.counter == 'true' # Steps represent a sequence of tasks that will be executed as part of the job steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it - - uses: actions/checkout@v2 - - id: casper_counter_test - uses: VUnit/vunit_action@master + - uses: actions/checkout@v4 with: - image: ghdl/vunit:llvm - cmd: python3 casper_counter/run.py --xunit-xml ./casper_counter/casper_counter_report.xml + submodules: 'recursive' + token: ${{ secrets.TOKEN }} + - id: casper_counter_test + run: python3 casper_counter/run.py --xunit-xml ./casper_counter/casper_counter_report.xml - name: Note casper_counter_test Failure if: ${{ failure() }} @@ -238,27 +397,287 @@ jobs: badge-branch: badges style: flat github-token: "${{ secrets.GITHUB_TOKEN }}" - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 with: name: casper_counter_report path: ./casper_counter/casper_counter_report.xml if-no-files-found: 'warn' # ['warn', 'error', 'ignore'] + + delay: + # The type of runner that the job will run on + runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master + needs: [files_changed] + if: needs.files_changed.outputs.delay == 'true' + + # Steps represent a sequence of tasks that will be executed as part of the job + steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version + # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it + - uses: actions/checkout@v4 + with: + submodules: 'recursive' + token: ${{ secrets.TOKEN }} + + - name: Install numpy + run: pip3 install numpy + + - id: casper_delay_test + run: python3 casper_delay/run.py --xunit-xml ./casper_delay/casper_delay_report.xml + + - name: Note casper_delay_test Failure + if: ${{ failure() }} + uses: action-badges/core@0.2.2 + with: + label: casper_delay + message: failing + message-color: "C74D1F" + file-name: casper_delay_test.svg + badge-branch: badges + style: flat + github-token: "${{ secrets.GITHUB_TOKEN }}" + - name: Note casper_delay_test Success + if: ${{ steps.casper_delay_test.outcome == 'success' }} + uses: action-badges/core@0.2.2 + with: + label: casper_delay + message: passing + message-color: "4DC71F" + file-name: casper_delay_test.svg + badge-branch: badges + style: flat + github-token: "${{ secrets.GITHUB_TOKEN }}" + - uses: actions/upload-artifact@v4 + with: + name: casper_delay_report + path: ./casper_delay/casper_delay_report.xml + if-no-files-found: 'warn' # ['warn', 'error', 'ignore'] + + filter: + # The type of runner that the job will run on + runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master + needs: [files_changed] + if: needs.files_changed.outputs.filter == 'true' + + # Steps represent a sequence of tasks that will be executed as part of the job + steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version + # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it + - uses: actions/checkout@v4 + with: + submodules: 'recursive' + token: ${{ secrets.TOKEN }} + - id: casper_filter_test + run: python3 casper_filter/run.py --xunit-xml ./casper_filter/casper_filter_report.xml --single --wide + + - name: Note casper_filter_test Failure + if: ${{ failure() }} + uses: action-badges/core@0.2.2 + with: + label: casper_filter + message: failing + message-color: "C74D1F" + file-name: casper_filter_test.svg + badge-branch: badges + style: flat + github-token: "${{ secrets.GITHUB_TOKEN }}" + - name: Note casper_filter_test Success + if: ${{ steps.casper_filter_test.outcome == 'success' }} + uses: action-badges/core@0.2.2 + with: + label: casper_filter + message: passing + message-color: "4DC71F" + file-name: casper_filter_test.svg + badge-branch: badges + style: flat + github-token: "${{ secrets.GITHUB_TOKEN }}" + - uses: actions/upload-artifact@v4 + with: + name: casper_filter_report + path: ./casper_filter/casper_filter_report.xml + if-no-files-found: 'warn' # ['warn', 'error', 'ignore'] + + flow_control: + # The type of runner that the job will run on + runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master + needs: [files_changed] + if: needs.files_changed.outputs.flow_control == 'true' + + # Steps represent a sequence of tasks that will be executed as part of the job + steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version + # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it + - uses: actions/checkout@v4 + with: + submodules: 'recursive' + token: ${{ secrets.TOKEN }} + - id: casper_flow_control_test + run: python3 casper_flow_control/run.py --xunit-xml ./casper_flow_control/casper_flow_control_report.xml + + - name: Note casper_flow_control_test Failure + if: ${{ failure() }} + uses: action-badges/core@0.2.2 + with: + label: casper_flow_control + message: failing + message-color: "C74D1F" + file-name: casper_flow_control_test.svg + badge-branch: badges + style: flat + github-token: "${{ secrets.GITHUB_TOKEN }}" + - name: Note casper_flow_control_test Success + if: ${{ steps.casper_flow_control_test.outcome == 'success' }} + uses: action-badges/core@0.2.2 + with: + label: casper_flow_control + message: passing + message-color: "4DC71F" + file-name: casper_flow_control_test.svg + badge-branch: badges + style: flat + github-token: "${{ secrets.GITHUB_TOKEN }}" + - uses: actions/upload-artifact@v4 + with: + name: casper_flow_control_report + path: ./casper_flow_control/casper_flow_control_report.xml + if-no-files-found: 'warn' # ['warn', 'error', 'ignore'] + + reorder: + # The type of runner that the job will run on + runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master + needs: [files_changed] + if: true # needs.files_changed.outputs.reorder == 'true' + + # Steps represent a sequence of tasks that will be executed as part of the job + steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version + # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it + - uses: actions/checkout@v4 + with: + submodules: 'recursive' + token: ${{ secrets.TOKEN }} + - id: casper_reorder_test + run: python3 casper_reorder/run.py --xunit-xml ./casper_reorder/casper_reorder_report.xml + + - name: Note casper_reorder_test Failure + if: ${{ failure() }} + uses: action-badges/core@0.2.2 + with: + label: casper_reorder + message: failing + message-color: "C74D1F" + file-name: casper_reorder_test.svg + badge-branch: badges + style: flat + github-token: "${{ secrets.GITHUB_TOKEN }}" + - name: Note casper_reorder_test Success + if: ${{ steps.casper_reorder_test.outcome == 'success' }} + uses: action-badges/core@0.2.2 + with: + label: casper_reorder + message: passing + message-color: "4DC71F" + file-name: casper_reorder_test.svg + badge-branch: badges + style: flat + github-token: "${{ secrets.GITHUB_TOKEN }}" + - uses: actions/upload-artifact@v4 + with: + name: casper_reorder_report + path: ./casper_reorder/casper_reorder_report.xml + if-no-files-found: 'warn' # ['warn', 'error', 'ignore'] + + misc: + # The type of runner that the job will run on + runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master + needs: [files_changed] + if: needs.files_changed.outputs.misc == 'true' + + # Steps represent a sequence of tasks that will be executed as part of the job + steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version + # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it + - uses: actions/checkout@v4 + with: + submodules: 'recursive' + token: ${{ secrets.TOKEN }} + - id: misc_test + run: python3 misc/run.py --xunit-xml ./misc/misc_report.xml + + - name: Note misc_test Failure + if: ${{ failure() }} + uses: action-badges/core@0.2.2 + with: + label: misc + message: failing + message-color: "C74D1F" + file-name: misc_test.svg + badge-branch: badges + style: flat + github-token: "${{ secrets.GITHUB_TOKEN }}" + - name: Note misc_test Success + if: ${{ steps.misc_test.outcome == 'success' }} + uses: action-badges/core@0.2.2 + with: + label: misc + message: passing + message-color: "4DC71F" + file-name: misc_test.svg + badge-branch: badges + style: flat + github-token: "${{ secrets.GITHUB_TOKEN }}" + - uses: actions/upload-artifact@v4 + with: + name: misc_report + path: ./misc/misc_report.xml + if-no-files-found: 'warn' # ['warn', 'error', 'ignore'] multiplexer: # The type of runner that the job will run on runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master needs: [files_changed] if: needs.files_changed.outputs.multiplexer == 'true' # Steps represent a sequence of tasks that will be executed as part of the job steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it - - uses: actions/checkout@v2 - - id: casper_multiplexer_test - uses: VUnit/vunit_action@master + - uses: actions/checkout@v4 with: - image: ghdl/vunit:llvm - cmd: python3 casper_multiplexer/run.py --xunit-xml ./casper_multiplexer/casper_multiplexer_report.xml + submodules: 'recursive' + token: ${{ secrets.TOKEN }} + - id: casper_multiplexer_test + run: python3 casper_multiplexer/run.py --xunit-xml ./casper_multiplexer/casper_multiplexer_report.xml - name: Note casper_multiplexer_test Failure if: ${{ failure() }} @@ -282,7 +701,7 @@ jobs: badge-branch: badges style: flat github-token: "${{ secrets.GITHUB_TOKEN }}" - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 with: name: casper_multiplexer_report path: ./casper_multiplexer/casper_multiplexer_report.xml @@ -291,18 +710,24 @@ jobs: multiplier: # The type of runner that the job will run on runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master needs: [files_changed] if: needs.files_changed.outputs.multiplier == 'true' # Steps represent a sequence of tasks that will be executed as part of the job steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it - - uses: actions/checkout@v2 - - id: casper_multiplier_test - uses: VUnit/vunit_action@master + - uses: actions/checkout@v4 with: - image: ghdl/vunit:llvm - cmd: python3 casper_multiplier/run.py --xunit-xml ./casper_multiplier/casper_multiplier_report.xml + submodules: 'recursive' + token: ${{ secrets.TOKEN }} + - id: casper_multiplier_test + run: python3 casper_multiplier/run.py --xunit-xml ./casper_multiplier/casper_multiplier_report.xml - name: Note casper_multiplier_test Failure if: ${{ failure() }} @@ -326,7 +751,7 @@ jobs: badge-branch: badges style: flat github-token: "${{ secrets.GITHUB_TOKEN }}" - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 with: name: casper_multiplier_report path: ./casper_multiplier/casper_multiplier_report.xml @@ -335,18 +760,24 @@ jobs: fifo: # The type of runner that the job will run on runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master needs: [files_changed] if: needs.files_changed.outputs.fifo == 'true' # Steps represent a sequence of tasks that will be executed as part of the job steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it - - uses: actions/checkout@v2 - - id: casper_fifo_test - uses: VUnit/vunit_action@master + - uses: actions/checkout@v4 with: - image: ghdl/vunit:llvm - cmd: python3 casper_fifo/run.py --xunit-xml ./casper_fifo/casper_fifo_report.xml + submodules: 'recursive' + token: ${{ secrets.TOKEN }} + - id: casper_fifo_test + run: python3 casper_fifo/run.py --xunit-xml ./casper_fifo/casper_fifo_report.xml - name: Note casper_fifo_test Failure if: ${{ failure() }} @@ -370,7 +801,7 @@ jobs: badge-branch: badges style: flat github-token: "${{ secrets.GITHUB_TOKEN }}" - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 with: name: casper_fifo_report path: ./casper_fifo/casper_fifo_report.xml @@ -379,21 +810,24 @@ jobs: ram: # The type of runner that the job will run on runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master needs: [files_changed] if: needs.files_changed.outputs.ram == 'true' # Steps represent a sequence of tasks that will be executed as part of the job steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version # Checks-out your repository (and submodules) under $GITHUB_WORKSPACE, so your job can access it - - uses: actions/checkout@v2 + - uses: actions/checkout@v4 with: - submodules: 'true' + submodules: 'recursive' token: ${{ secrets.TOKEN }} - id: casper_ram_test - uses: VUnit/vunit_action@master - with: - image: ghdl/vunit:llvm - cmd: python3 casper_ram/run.py --xunit-xml ./casper_ram/casper_ram_report.xml + run: python3 casper_ram/run.py --xunit-xml ./casper_ram/casper_ram_report.xml - name: Note casper_ram_test Failure if: ${{ failure() }} @@ -417,7 +851,7 @@ jobs: badge-branch: badges style: flat github-token: "${{ secrets.GITHUB_TOKEN }}" - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 with: name: casper_ram_report path: ./casper_ram/casper_ram_report.xml @@ -426,21 +860,24 @@ jobs: rtwosdf_fft: # The type of runner that the job will run on runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master needs: [files_changed] if: needs.files_changed.outputs.r2sdf_fft == 'true' # Steps represent a sequence of tasks that will be executed as part of the job steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version # Checks-out your repository (and submodules) under $GITHUB_WORKSPACE, so your job can access it - - uses: actions/checkout@v2 + - uses: actions/checkout@v4 with: - submodules: 'true' + submodules: 'recursive' token: ${{ secrets.TOKEN }} - id: r2sdf_fft_test - uses: VUnit/vunit_action@master - with: - image: ghdl/vunit:llvm - cmd: python3 r2sdf_fft/run.py --xunit-xml ./r2sdf_fft/r2sdf_fft_report.xml + run: python3 r2sdf_fft/run.py --xunit-xml ./r2sdf_fft/r2sdf_fft_report.xml - name: Note r2sdf_fft_test Failure if: ${{ failure() }} @@ -464,7 +901,7 @@ jobs: badge-branch: badges style: flat github-token: "${{ secrets.GITHUB_TOKEN }}" - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 with: name: r2sdf_fft_report path: ./r2sdf_fft/r2sdf_fft_report.xml @@ -473,21 +910,28 @@ jobs: pipe_fft: # The type of runner that the job will run on runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master needs: [files_changed] if: needs.files_changed.outputs.pipe_fft == 'true' || needs.files_changed.outputs.all_fft == 'true' # Steps represent a sequence of tasks that will be executed as part of the job steps: - # Checks-out your repository (and submodules) under $GITHUB_WORKSPACE, so your job can access it - - uses: actions/checkout@v2 - with: - submodules: 'true' + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version + - name: Install numpy + run: pip3 install numpy + - name: Install pytest + run: pip3 install pytest + # Checks-out your repository (and submodules) under $GITHUB_WORKSPACE, so your job can access it + - uses: actions/checkout@v4 + with: + submodules: 'recursive' token: ${{ secrets.TOKEN }} - id: casper_pipe_fft_test - uses: VUnit/vunit_action@master - with: - image: ghdl/vunit:llvm - cmd: python3 casper_wb_fft/run.py --xunit-xml ./casper_wb_fft/pipe_fft_report.xml --pipe + run: python3 casper_wb_fft/run.py --xunit-xml ./casper_wb_fft/pipe_fft_report.xml --pipe - name: Note casper_pipe_fft_test Failure if: ${{ failure() }} @@ -511,7 +955,7 @@ jobs: badge-branch: badges style: flat github-token: "${{ secrets.GITHUB_TOKEN }}" - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 with: name: pipe_fft_report path: ./casper_wb_fft/pipe_fft_report.xml @@ -520,21 +964,28 @@ jobs: par_fft: # The type of runner that the job will run on runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master needs: [files_changed] if: needs.files_changed.outputs.par_fft == 'true' || needs.files_changed.outputs.all_fft == 'true' # Steps represent a sequence of tasks that will be executed as part of the job steps: - # Checks-out your repository (and submodules) under $GITHUB_WORKSPACE, so your job can access it - - uses: actions/checkout@v2 - with: - submodules: 'true' + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version + - name: Install numpy + run: pip3 install numpy + - name: Install pytest + run: pip3 install pytest + # Checks-out your repository (and submodules) under $GITHUB_WORKSPACE, so your job can access it + - uses: actions/checkout@v4 + with: + submodules: 'recursive' token: ${{ secrets.TOKEN }} - id: casper_par_fft_test - uses: VUnit/vunit_action@master - with: - image: ghdl/vunit:llvm - cmd: python3 casper_wb_fft/run.py --xunit-xml ./casper_wb_fft/par_fft_report.xml --par + run: python3 casper_wb_fft/run.py --xunit-xml ./casper_wb_fft/par_fft_report.xml --par - name: Note casper_par_fft_test Failure if: ${{ failure() }} @@ -558,7 +1009,7 @@ jobs: badge-branch: badges style: flat github-token: "${{ secrets.GITHUB_TOKEN }}" - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 with: name: par_fft_report path: ./casper_wb_fft/par_fft_report.xml @@ -567,21 +1018,29 @@ jobs: wide_fft: # The type of runner that the job will run on runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master needs: [files_changed] if: needs.files_changed.outputs.wide_fft == 'true' || needs.files_changed.outputs.all_fft == 'true' # Steps represent a sequence of tasks that will be executed as part of the job steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version + - name: Install numpy + run: pip3 install numpy + - name: Install pytest + run: pip3 install pytest + # Checks-out your repository (and submodules) under $GITHUB_WORKSPACE, so your job can access it - - uses: actions/checkout@v2 + - uses: actions/checkout@v4 with: - submodules: 'true' + submodules: 'recursive' token: ${{ secrets.TOKEN }} - id: casper_wide_fft_test - uses: VUnit/vunit_action@master - with: - image: ghdl/vunit:llvm - cmd: python3 casper_wb_fft/run.py --xunit-xml ./casper_wb_fft/wide_fft_report.xml --wide + run: python3 casper_wb_fft/run.py --xunit-xml ./casper_wb_fft/wide_fft_report.xml --wide - name: Note casper_wide_fft_test Failure if: ${{ failure() }} @@ -605,76 +1064,32 @@ jobs: badge-branch: badges style: flat github-token: "${{ secrets.GITHUB_TOKEN }}" - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 with: name: wide_fft_report path: ./casper_wb_fft/wide_fft_report.xml if-no-files-found: 'warn' # ['warn', 'error', 'ignore'] - # all_fft: - # # The type of runner that the job will run on - # runs-on: ubuntu-latest - # needs: [files_changed] - # if: needs.files_changed.outputs.all_fft == 'true' - - # # Steps represent a sequence of tasks that will be executed as part of the job - # steps: - # # Checks-out your repository (and submodules) under $GITHUB_WORKSPACE, so your job can access it - # - uses: actions/checkout@v2 - # with: - # submodules: 'true' - # token: ${{ secrets.TOKEN }} - # - id: casper_all_fft_test - # uses: VUnit/vunit_action@master - # with: - # image: ghdl/vunit:llvm - # cmd: python3 casper_wb_fft/run.py --xunit-xml ./casper_wb_fft/wide_fft_report.xml - - # - name: Note casper_all_fft_test Failure - # if: ${{ failure() }} - # uses: action-badges/core@0.2.2 - # with: - # label: casper_all_fft - # message: failing - # message-color: "C74D1F" - # file-name: casper_all_fft_test.svg - # badge-branch: badges - # style: flat - # github-token: "${{ secrets.GITHUB_TOKEN }}" - # - name: Note casper_all_fft_test Success - # if: ${{ steps.casper_wide_fft_test.outcome == 'success' }} - # uses: action-badges/core@0.2.2 - # with: - # label: casper_all_fft - # message: passing - # message-color: "4DC71F" - # file-name: casper_all_fft_test.svg - # badge-branch: badges - # style: flat - # github-token: "${{ secrets.GITHUB_TOKEN }}" - # - uses: actions/upload-artifact@v2 - # with: - # name: wide_fft_report - # path: ./casper_wb_fft/wide_all_report.xml - # if-no-files-found: 'warn' # ['warn', 'error', 'ignore'] - single_filter: # The type of runner that the job will run on runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master needs: [files_changed] if: needs.files_changed.outputs.single_filter == 'true' # Steps represent a sequence of tasks that will be executed as part of the job steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version # Checks-out your repository (and submodules) under $GITHUB_WORKSPACE, so your job can access it - - uses: actions/checkout@v2 + - uses: actions/checkout@v4 with: - submodules: 'true' + submodules: 'recursive' token: ${{ secrets.TOKEN }} - id: casper_single_filter_test - uses: VUnit/vunit_action@master - with: - image: ghdl/vunit:llvm - cmd: python3 casper_filter/run.py --xunit-xml ./casper_filter/single_filter_report.xml --single + run: python3 casper_filter/run.py --xunit-xml ./casper_filter/single_filter_report.xml --single - name: Note casper_single_filter_test Failure if: ${{ failure() }} @@ -698,7 +1113,7 @@ jobs: badge-branch: badges style: flat github-token: "${{ secrets.GITHUB_TOKEN }}" - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 with: name: single_filter_report path: ./casper_filter/single_filter_report.xml @@ -707,20 +1122,23 @@ jobs: wide_filter: # The type of runner that the job will run on runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master needs: [files_changed] if: needs.files_changed.outputs.wide_filter == 'true' # Steps represent a sequence of tasks that will be executed as part of the job steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version # Checks-out your repository (and submodules) under $GITHUB_WORKSPACE, so your job can access it - - uses: actions/checkout@v2 + - uses: actions/checkout@v4 with: - submodules: 'true' + submodules: 'recursive' token: ${{ secrets.TOKEN }} - id: casper_wide_filter_test - uses: VUnit/vunit_action@master - with: - image: ghdl/vunit:llvm - cmd: python3 casper_filter/run.py --xunit-xml ./casper_filter/wide_filter_report.xml --wide + run: python3 casper_filter/run.py --xunit-xml ./casper_filter/wide_filter_report.xml --wide - name: Note casper_wide_filter_test Failure if: ${{ failure() }} @@ -744,7 +1162,7 @@ jobs: badge-branch: badges style: flat github-token: "${{ secrets.GITHUB_TOKEN }}" - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 with: name: wide_filter_report path: ./casper_filter/wide_filter_report.xml @@ -753,20 +1171,23 @@ jobs: wbpfb: # The type of runner that the job will run on runs-on: ubuntu-latest + container: ghdl/vunit:llvm-master needs: [files_changed] if: needs.files_changed.outputs.wbpfb == 'true' # Steps represent a sequence of tasks that will be executed as part of the job steps: + - name: Update git + run: | + apt-get update + apt-get install git -y + git --version # Checks-out your repository (and submodules) under $GITHUB_WORKSPACE, so your job can access it - - uses: actions/checkout@v2 + - uses: actions/checkout@v4 with: - submodules: 'true' + submodules: 'recursive' token: ${{ secrets.TOKEN }} - id: casper_wbpfb_test - uses: VUnit/vunit_action@master - with: - image: ghdl/vunit:llvm - cmd: python3 casper_wbpfb/run.py --xunit-xml ./casper_filter/wbpfb_report.xml + run: python3 casper_wbpfb/run.py --xunit-xml ./casper_filter/wbpfb_report.xml - name: Note casper_wbpfb_test Failure if: ${{ failure() }} @@ -790,7 +1211,7 @@ jobs: badge-branch: badges style: flat github-token: "${{ secrets.GITHUB_TOKEN }}" - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 with: name: wbpfb_report path: ./casper_wbpfb/wbpfb_report.xml diff --git a/.gitignore b/.gitignore index 475fdf08..73733bda 100644 --- a/.gitignore +++ b/.gitignore @@ -1,11 +1,21 @@ # Don't track content of these folders .settings/ +docs/build # Compiled source # -*/.project +#*/.project */vunit_out vunit_out */*.xml .vscode build/* __pycache__ +twiddlepkg*.txt +vivado*.log +vivado*.jou +vivado*.str +*vrs_config* +*proj.runs* +*.cache/ +*proj*.sim/ +casper_wb_fft/ngvla_test_proj/* diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml new file mode 100644 index 00000000..2e59f146 --- /dev/null +++ b/.gitlab-ci.yml @@ -0,0 +1,754 @@ +image: ghdl/vunit:mcode-master +variables: + GIT_CLONE_PATH: $CI_BUILDS_DIR/$CI_CONCURRENT_ID/sim/casper_dspdevel + GIT_SUBMODULE_STRATEGY: recursive + +stages: # List of stages for jobs, and their order of execution + - VunitSim + - QuestaSim + - VivadoSynthesis +casper_accumulators_test: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - ghdl --version + - /usr/bin/python3 casper_accumulators/run.py --xunit-xml ./casper_accumulators/casper_accumulators_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_accumulators/casper_accumulators_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_accumulators/casper_accumulators_report.xml + +casper_adders_test: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_adder/run.py --xunit-xml ./casper_adder/casper_adder_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_adder/casper_adder_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_adder/casper_adder_report.xml + +counter: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_counter/run.py --xunit-xml ./casper_counter/casper_counter_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_counter/casper_counter_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_counter/casper_counter_report.xml + +delay: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_delay/run.py --xunit-xml ./casper_delay/casper_delay_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_delay/casper_delay_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_delay/casper_delay_report.xml + when: manual + +filter: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_filter/run.py --xunit-xml ./casper_filter/casper_filter_report.xml --single --wide + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_filter/casper_filter_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_filter/casper_filter_report.xml + +flow_control: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_flow_control/run.py --xunit-xml ./casper_flow_control/casper_flow_control_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_flow_control/casper_flow_control_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_flow_control/casper_flow_control_report.xml + +misc: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 misc/run.py --xunit-xml ./misc/misc_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/misc/misc_report.xml + reports: + junit: $GIT_CLONE_PATH/misc/misc_report.xml + +multiplexer: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_multiplexer/run.py --xunit-xml ./casper_multiplexer/casper_multiplexer_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_multiplexer/casper_multiplexer_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_multiplexer/casper_multiplexer_report.xml + +multiplier: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_multiplier/run.py --xunit-xml ./casper_multiplier/casper_multiplier_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_multiplier/casper_multiplier_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_multiplier/casper_multiplier_report.xml + +fifo: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_fifo/run.py --xunit-xml ./casper_fifo/casper_fifo_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_fifo/casper_fifo_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_fifo/casper_fifo_report.xml + +ram: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_ram/run.py --xunit-xml ./casper_ram/casper_ram_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_ram/casper_ram_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_ram/casper_ram_report.xml + +rtwosdf_fft: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 r2sdf_fft/run.py --xunit-xml ./r2sdf_fft/r2sdf_fft_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/r2sdf_fft/r2sdf_fft_report.xml + reports: + junit: $GIT_CLONE_PATH/r2sdf_fft/r2sdf_fft_report.xml + +rtwosdf_fft_bitaccurate_twid: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 r2sdf_fft/run.py --xunit-xml ./r2sdf_fft/r2sdf_fft_report.xml --twid --bitaccurate + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/r2sdf_fft/r2sdf_fft_report.xml + reports: + junit: $GIT_CLONE_PATH/r2sdf_fft/r2sdf_fft_report.xml + when: manual + +pipe_fft: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_wb_fft/run.py --xunit-xml ./casper_wb_fft/pipe_fft_report.xml --pipe + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_wb_fft/pipe_fft_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_wb_fft/pipe_fft_report.xml + + +par_fft: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_wb_fft/run.py --xunit-xml ./casper_wb_fft/par_fft_report.xml --par + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_wb_fft/par_fft_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_wb_fft/par_fft_report.xml + +wide_fft: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_wb_fft/run.py --xunit-xml ./casper_wb_fft/wide_fft_report.xml --wide + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_wb_fft/wide_fft_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_wb_fft/wide_fft_report.xml + + +single_filter: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_filter/run.py --xunit-xml ./casper_filter/single_filter_report.xml --single + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_filter/single_filter_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_filter/single_filter_report.xml + +wide_filter: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_filter/run.py --xunit-xml ./casper_filter/wide_filter_report.xml --wide + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_filter/wide_filter_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_filter/wide_filter_report.xml + +wbpfb: # This job runs in the test stage. + stage: VunitSim # It only starts when the job in the build stage completes successfully. + tags: + - ghdl + script: + - python3 -m pip install pytest --progress-bar off + - python3 -m pip install numpy --progress-bar off + - echo Attempting to start Vunit Tests + - cd $GIT_CLONE_PATH + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_wbpfb/run.py --xunit-xml ./casper_filter/wbpfb_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_filter/wbpfb_report.xml + reports: + junit: $GIT_CLONE_PATH/casper_filter/wbpfb_report.xml + +AllowQuesta: + stage: QuestaSim + image : questasim:2023.1 + needs: [] + tags: + - questa + script : + - echo Starting Questa Simulations! + when: manual + +Questa_casper_accumulators: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_accumulators/run.py --xunit-xml ./reports/casper_accumulators_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_casper_adder: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] # when accumulators starts runs the rest of the sims + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_adder/run.py --xunit-xml ./reports/casper_adder_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_casper_counter: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_counter/run.py --xunit-xml ./reports/casper_counter_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_casper_delay: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_delay/run.py --xunit-xml ./reports/casper_delay_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + when: manual + +Questa_casper_filter: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_filter/run.py --xunit-xml ./reports/casper_filter_report.xml --single --wide + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_casper_flow_control: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_flow_control/run.py --xunit-xml ./reports/casper_flow_control_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_casper_misc: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 misc/run.py --xunit-xml ./reports/misc_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_casper_multiplexer: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_multiplexer/run.py --xunit-xml ./reports/casper_multiplexer_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_casper_multiplier: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_multiplier/run.py --xunit-xml ./reports/casper_multiplier_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_casper_fifo: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_fifo/run.py --xunit-xml ./reports/casper_fifo_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_casper_ram: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_ram/run.py --xunit-xml ./reports/casper_ram_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_r2sdf_fft: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 r2sdf_fft/run.py --xunit-xml ./reports/r2sdf_fft_report.xml --twid --bitaccurate + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_casper_wb_fft_pipe: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_wb_fft/run.py --xunit-xml ./reports/pipe_fft_report.xml --pipe + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_casper_wb_fft_par: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_wb_fft/run.py --xunit-xml ./reports/par_fft_report.xml --par + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_casper_wb_fft_wide: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_wb_fft/run.py --xunit-xml ./reports/wide_fft_report.xml --wide + + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_casper_filter_single: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_filter/run.py --xunit-xml ./reports/single_filter_report.xml --single + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_casper_filter_wide: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_filter/run.py --xunit-xml ./reports/wide_filter_report.xml --wide + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml + +Questa_casper_wbpfb: # This job runs in the test stage. + stage: QuestaSim # It only starts when the job in the build stage completes successfully. + image: questasim:2023.1 + needs: [AllowQuesta] + tags: + - questa + script: + - echo Attempting to start Vunit Tests in Questa + - cd $GIT_CLONE_PATH + - mkdir -p reports + - echo Starting Vunit in python3 + - /usr/bin/python3 casper_wbpfb/run.py --xunit-xml ./reports/wbpfb_report.xml + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/reports/*.xml + reports: + junit: $GIT_CLONE_PATH/reports/*.xml +VivadoSynthesisWBFFT: + variables: + GIT_CLONE_PATH: $CI_BUILDS_DIR/$CI_CONCURRENT_ID/vivado/casper_dspdevel + GIT_SUBMODULE_STRATEGY: recursive + stage: VivadoSynthesis + image : vivado:2022.2 + needs: [] + tags: + - Vivado + script : + - echo Starting Vivado Synthesis WBFFT + # Fix any packages out of date, and install the missing libtinfo5 + - apt update + - apt upgrade -y + - apt install -y libtinfo5 sudo + - useradd -m ci + - cd /tmp + - git clone https://github.com/Xilinx/XilinxTclStore.git + - chown -R ci $GIT_CLONE_PATH + - | + sudo -H -i -u ci /usr/bin/bash -e -x << EOS + cd $GIT_CLONE_PATH/casper_wb_fft/ngvla_test_proj + export LM_LICENSE_FILE=2100@cv-flexserverB.ad.nrao.edu:1717@cv-flexserverB.ad.nrao.edu + export XILINX_TCLAPP_REPO=/tmp/XilinxTclStore + export XILINX_LOCAL_USER_DATA=NO + rm -f *.jou + rm -f *.log + rm -f synth_output/post_synth.dcp + source /export/data_1/Xilinx/Vivado/2022.2/settings64.sh + LD_PRELOAD=/lib/x86_64-linux-gnu/libudev.so.1 vivado -mode batch -source ngVLA_wbfft_test.tcl + EOS + after_script: + # Set files back to root + - chown -R root.root $GIT_CLONE_PATH + when: manual + artifacts: + when: always + paths: + - $GIT_CLONE_PATH/casper_wb_fft/ngvla_test_proj/*.jou + - $GIT_CLONE_PATH/casper_wb_fft/ngvla_test_proj/*.log + - $GIT_CLONE_PATH/casper_wb_fft/ngvla_test_proj/hs_err* + - $GIT_CLONE_PATH/casper_wb_fft/ngvla_test_proj/report.xml + - $GIT_CLONE_PATH/casper_wb_fft/ngvla_test_proj/synth_output/post_synth.dcp + reports: + junit: $GIT_CLONE_PATH/casper_wb_fft/ngvla_test_proj/report.xml diff --git a/.library_mapping.xml b/.library_mapping.xml index 8c2ecbcd..f249c47b 100644 --- a/.library_mapping.xml +++ b/.library_mapping.xml @@ -1,5 +1,7 @@ + + @@ -15,23 +17,43 @@ + + + + + + + + + + + + + + + + + + + + @@ -41,4 +63,10 @@ + + + + + + diff --git a/.project b/.project index 0f1cf74d..8aec3df0 100644 --- a/.project +++ b/.project @@ -1,331 +1,376 @@ - - - sigasi_dspdevel - - - - - - com.sigasi.hdt.toolchains.vunit.builder - - - - - org.eclipse.xtext.ui.shared.xtextBuilder - - - - - - com.sigasi.hdt.vhdl.ui.vhdlNature - org.eclipse.xtext.ui.shared.xtextNature - com.sigasi.hdt.toolchains.vunit.nature - - - - Common Libraries - 2 - virtual:/virtual - - - Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt - 1 - sigasiresource:/vhdl/readme.txt - - - Common Libraries/IEEE - 2 - sigasiresource:/vhdl/2008/IEEE - - - Common Libraries/IEEE Synopsys - 2 - sigasiresource:/vhdl/2008/IEEE%20Synopsys - - - Common Libraries/STD - 2 - sigasiresource:/vhdl/2008/STD - - - Common Libraries/unisim - 2 - SIGASI_TOOLCHAIN_XILINX_VIVADO/data/vhdl/src/unisims - - - Common Libraries/vunit_lib - 2 - virtual:/virtual - - - Common Libraries/xpm - 2 - SIGASI_TOOLCHAIN_XILINX_VIVADO/data/ip/xpm - - - Common Libraries/vunit_lib/ansi_pkg.vhd - 1 - VUNIT/vhdl/logging/src/ansi_pkg.vhd - - - Common Libraries/vunit_lib/byte_vector_ptr_pkg.vhd - 1 - VUNIT/vhdl/data_types/src/byte_vector_ptr_pkg.vhd - - - Common Libraries/vunit_lib/check.vhd - 1 - VUNIT/vhdl/check/src/check.vhd - - - Common Libraries/vunit_lib/check_api.vhd - 1 - VUNIT/vhdl/check/src/check_api.vhd - - - Common Libraries/vunit_lib/check_deprecated_pkg.vhd - 1 - VUNIT/vhdl/check/src/check_deprecated_pkg.vhd - - - Common Libraries/vunit_lib/checker_pkg-body.vhd - 1 - VUNIT/vhdl/check/src/checker_pkg-body.vhd - - - Common Libraries/vunit_lib/checker_pkg.vhd - 1 - VUNIT/vhdl/check/src/checker_pkg.vhd - - - Common Libraries/vunit_lib/codec-2008p.vhd - 1 - VUNIT/vhdl/data_types/src/codec-2008p.vhd - - - Common Libraries/vunit_lib/codec.vhd - 1 - VUNIT/vhdl/data_types/src/codec.vhd - - - Common Libraries/vunit_lib/codec_builder-2008p.vhd - 1 - VUNIT/vhdl/data_types/src/codec_builder-2008p.vhd - - - Common Libraries/vunit_lib/codec_builder.vhd - 1 - VUNIT/vhdl/data_types/src/codec_builder.vhd - - - Common Libraries/vunit_lib/core_pkg.vhd - 1 - VUNIT/vhdl/core/src/core_pkg.vhd - - - Common Libraries/vunit_lib/data_types_context.vhd - 1 - VUNIT/vhdl/data_types/src/data_types_context.vhd - - - Common Libraries/vunit_lib/dict_pkg.vhd - 1 - VUNIT/vhdl/data_types/src/dict_pkg.vhd - - - Common Libraries/vunit_lib/dictionary.vhd - 1 - VUNIT/vhdl/dictionary/src/dictionary.vhd - - - Common Libraries/vunit_lib/external_integer_vector_pkg.vhd - 1 - VUNIT/vhdl/data_types/src/api/external_integer_vector_pkg.vhd - - - Common Libraries/vunit_lib/external_string_pkg.vhd - 1 - VUNIT/vhdl/data_types/src/api/external_string_pkg.vhd - - - Common Libraries/vunit_lib/file_pkg.vhd - 1 - VUNIT/vhdl/logging/src/file_pkg.vhd - - - Common Libraries/vunit_lib/integer_array_pkg-body.vhd - 1 - VUNIT/vhdl/data_types/src/integer_array_pkg-body.vhd - - - Common Libraries/vunit_lib/integer_array_pkg.vhd - 1 - VUNIT/vhdl/data_types/src/integer_array_pkg.vhd - - - Common Libraries/vunit_lib/integer_vector_ptr_pkg-body-2002p.vhd - 1 - VUNIT/vhdl/data_types/src/integer_vector_ptr_pkg-body-2002p.vhd - - - Common Libraries/vunit_lib/integer_vector_ptr_pkg.vhd - 1 - VUNIT/vhdl/data_types/src/integer_vector_ptr_pkg.vhd - - - Common Libraries/vunit_lib/integer_vector_ptr_pool_pkg.vhd - 1 - VUNIT/vhdl/data_types/src/integer_vector_ptr_pool_pkg.vhd - - - Common Libraries/vunit_lib/location_pkg-body-2008m.vhd - 1 - VUNIT/vhdl/logging/src/location_pkg-body-2008m.vhd - - - Common Libraries/vunit_lib/location_pkg.vhd - 1 - VUNIT/vhdl/logging/src/location_pkg.vhd - - - Common Libraries/vunit_lib/log_deprecated_pkg.vhd - 1 - VUNIT/vhdl/logging/src/log_deprecated_pkg.vhd - - - Common Libraries/vunit_lib/log_handler_pkg-body.vhd - 1 - VUNIT/vhdl/logging/src/log_handler_pkg-body.vhd - - - Common Libraries/vunit_lib/log_handler_pkg.vhd - 1 - VUNIT/vhdl/logging/src/log_handler_pkg.vhd - - - Common Libraries/vunit_lib/log_levels_pkg-body.vhd - 1 - VUNIT/vhdl/logging/src/log_levels_pkg-body.vhd - - - Common Libraries/vunit_lib/log_levels_pkg.vhd - 1 - VUNIT/vhdl/logging/src/log_levels_pkg.vhd - - - Common Libraries/vunit_lib/logger_pkg-body.vhd - 1 - VUNIT/vhdl/logging/src/logger_pkg-body.vhd - - - Common Libraries/vunit_lib/logger_pkg.vhd - 1 - VUNIT/vhdl/logging/src/logger_pkg.vhd - - - Common Libraries/vunit_lib/path.vhd - 1 - VUNIT/vhdl/path/src/path.vhd - - - Common Libraries/vunit_lib/print_pkg-body.vhd - 1 - VUNIT/vhdl/logging/src/print_pkg-body.vhd - - - Common Libraries/vunit_lib/print_pkg.vhd - 1 - VUNIT/vhdl/logging/src/print_pkg.vhd - - - Common Libraries/vunit_lib/queue_pkg-2008p.vhd - 1 - VUNIT/vhdl/data_types/src/queue_pkg-2008p.vhd - - - Common Libraries/vunit_lib/queue_pkg-body.vhd - 1 - VUNIT/vhdl/data_types/src/queue_pkg-body.vhd - - - Common Libraries/vunit_lib/queue_pkg.vhd - 1 - VUNIT/vhdl/data_types/src/queue_pkg.vhd - - - Common Libraries/vunit_lib/queue_pool_pkg.vhd - 1 - VUNIT/vhdl/data_types/src/queue_pool_pkg.vhd - - - Common Libraries/vunit_lib/run.vhd - 1 - VUNIT/vhdl/run/src/run.vhd - - - Common Libraries/vunit_lib/run_api.vhd - 1 - VUNIT/vhdl/run/src/run_api.vhd - - - Common Libraries/vunit_lib/run_deprecated_pkg.vhd - 1 - VUNIT/vhdl/run/src/run_deprecated_pkg.vhd - - - Common Libraries/vunit_lib/run_types.vhd - 1 - VUNIT/vhdl/run/src/run_types.vhd - - - Common Libraries/vunit_lib/runner_pkg.vhd - 1 - VUNIT/vhdl/run/src/runner_pkg.vhd - - - Common Libraries/vunit_lib/stop_body_2008p.vhd - 1 - VUNIT/vhdl/core/src/stop_body_2008p.vhd - - - Common Libraries/vunit_lib/stop_pkg.vhd - 1 - VUNIT/vhdl/core/src/stop_pkg.vhd - - - Common Libraries/vunit_lib/string_ops.vhd - 1 - VUNIT/vhdl/string_ops/src/string_ops.vhd - - - Common Libraries/vunit_lib/string_ptr_pkg-body-2002p.vhd - 1 - VUNIT/vhdl/data_types/src/string_ptr_pkg-body-2002p.vhd - - - Common Libraries/vunit_lib/string_ptr_pkg.vhd - 1 - VUNIT/vhdl/data_types/src/string_ptr_pkg.vhd - - - Common Libraries/vunit_lib/string_ptr_pool_pkg.vhd - 1 - VUNIT/vhdl/data_types/src/string_ptr_pool_pkg.vhd - - - Common Libraries/vunit_lib/types.vhd - 1 - VUNIT/vhdl/data_types/src/types.vhd - - - Common Libraries/vunit_lib/vunit_context.vhd - 1 - VUNIT/vhdl/vunit_context.vhd - - - Common Libraries/vunit_lib/vunit_run_context.vhd - 1 - VUNIT/vhdl/vunit_run_context.vhd - - - + + + casper_dspdevel + + + + + + com.sigasi.hdt.toolchains.vunit.builder + + + + + org.eclipse.xtext.ui.shared.xtextBuilder + + + + + + com.sigasi.hdt.toolchains.vunit.nature + com.sigasi.hdt.vhdl.ui.vhdlNature + org.eclipse.xtext.ui.shared.xtextNature + + + + Common Libraries + 2 + virtual:/virtual + + + Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt + 1 + sigasiresource:/vhdl/readme.txt + + + Common Libraries/IEEE + 2 + sigasiresource:/vhdl/93/IEEE + + + Common Libraries/IEEE Synopsys + 2 + sigasiresource:/vhdl/93/IEEE%20Synopsys + + + Common Libraries/STD + 2 + sigasiresource:/vhdl/93/STD + + + Common Libraries/osvvm + 2 + //export/data_1/vunit/vunit/vhdl/osvvm + + + Common Libraries/unisim + 2 + SIGASI_TOOLCHAIN_XILINX_VIVADO/data/vhdl/src/unisims + + + Common Libraries/vunit_lib + 2 + virtual:/virtual + + + Common Libraries/xpm + 2 + SIGASI_TOOLCHAIN_XILINX_VIVADO/data/ip/xpm + + + Common Libraries/vunit_lib/ansi_pkg.vhd + 1 + VUNIT/vhdl/logging/src/ansi_pkg.vhd + + + Common Libraries/vunit_lib/byte_vector_ptr_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/byte_vector_ptr_pkg.vhd + + + Common Libraries/vunit_lib/check.vhd + 1 + VUNIT/vhdl/check/src/check.vhd + + + Common Libraries/vunit_lib/check_api.vhd + 1 + VUNIT/vhdl/check/src/check_api.vhd + + + Common Libraries/vunit_lib/check_deprecated_pkg.vhd + 1 + VUNIT/vhdl/check/src/check_deprecated_pkg.vhd + + + Common Libraries/vunit_lib/checker_pkg-body.vhd + 1 + VUNIT/vhdl/check/src/checker_pkg-body.vhd + + + Common Libraries/vunit_lib/checker_pkg.vhd + 1 + VUNIT/vhdl/check/src/checker_pkg.vhd + + + Common Libraries/vunit_lib/codec-2008p.vhd + 1 + VUNIT/vhdl/data_types/src/codec-2008p.vhd + + + Common Libraries/vunit_lib/codec.vhd + 1 + VUNIT/vhdl/data_types/src/codec.vhd + + + Common Libraries/vunit_lib/codec_builder-2008p.vhd + 1 + VUNIT/vhdl/data_types/src/codec_builder-2008p.vhd + + + Common Libraries/vunit_lib/codec_builder.vhd + 1 + VUNIT/vhdl/data_types/src/codec_builder.vhd + + + Common Libraries/vunit_lib/core_pkg.vhd + 1 + VUNIT/vhdl/core/src/core_pkg.vhd + + + Common Libraries/vunit_lib/data_types_context.vhd + 1 + VUNIT/vhdl/data_types/src/data_types_context.vhd + + + Common Libraries/vunit_lib/data_types_private_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/data_types_private_pkg.vhd + + + Common Libraries/vunit_lib/dict_pkg-2008p.vhd + 1 + VUNIT/vhdl/data_types/src/dict_pkg-2008p.vhd + + + Common Libraries/vunit_lib/dict_pkg-body.vhd + 1 + VUNIT/vhdl/data_types/src/dict_pkg-body.vhd + + + Common Libraries/vunit_lib/dict_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/dict_pkg.vhd + + + Common Libraries/vunit_lib/dictionary.vhd + 1 + VUNIT/vhdl/dictionary/src/dictionary.vhd + + + Common Libraries/vunit_lib/event_common_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/event_common_pkg.vhd + + + Common Libraries/vunit_lib/event_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/event_pkg.vhd + + + Common Libraries/vunit_lib/event_private_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/event_private_pkg.vhd + + + Common Libraries/vunit_lib/external_integer_vector_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/api/external_integer_vector_pkg.vhd + + + Common Libraries/vunit_lib/external_string_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/api/external_string_pkg.vhd + + + Common Libraries/vunit_lib/file_pkg.vhd + 1 + VUNIT/vhdl/logging/src/file_pkg.vhd + + + Common Libraries/vunit_lib/id_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/id_pkg.vhd + + + Common Libraries/vunit_lib/integer_array_pkg-body.vhd + 1 + VUNIT/vhdl/data_types/src/integer_array_pkg-body.vhd + + + Common Libraries/vunit_lib/integer_array_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/integer_array_pkg.vhd + + + Common Libraries/vunit_lib/integer_vector_ptr_pkg-body-2002p.vhd + 1 + VUNIT/vhdl/data_types/src/integer_vector_ptr_pkg-body-2002p.vhd + + + Common Libraries/vunit_lib/integer_vector_ptr_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/integer_vector_ptr_pkg.vhd + + + Common Libraries/vunit_lib/integer_vector_ptr_pool_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/integer_vector_ptr_pool_pkg.vhd + + + Common Libraries/vunit_lib/location_pkg-body-2008m.vhd + 1 + VUNIT/vhdl/logging/src/location_pkg-body-2008m.vhd + + + Common Libraries/vunit_lib/location_pkg.vhd + 1 + VUNIT/vhdl/logging/src/location_pkg.vhd + + + Common Libraries/vunit_lib/log_deprecated_pkg.vhd + 1 + VUNIT/vhdl/logging/src/log_deprecated_pkg.vhd + + + Common Libraries/vunit_lib/log_handler_pkg-body.vhd + 1 + VUNIT/vhdl/logging/src/log_handler_pkg-body.vhd + + + Common Libraries/vunit_lib/log_handler_pkg.vhd + 1 + VUNIT/vhdl/logging/src/log_handler_pkg.vhd + + + Common Libraries/vunit_lib/log_levels_pkg-body.vhd + 1 + VUNIT/vhdl/logging/src/log_levels_pkg-body.vhd + + + Common Libraries/vunit_lib/log_levels_pkg.vhd + 1 + VUNIT/vhdl/logging/src/log_levels_pkg.vhd + + + Common Libraries/vunit_lib/logger_pkg-body.vhd + 1 + VUNIT/vhdl/logging/src/logger_pkg-body.vhd + + + Common Libraries/vunit_lib/logger_pkg.vhd + 1 + VUNIT/vhdl/logging/src/logger_pkg.vhd + + + Common Libraries/vunit_lib/path.vhd + 1 + VUNIT/vhdl/path/src/path.vhd + + + Common Libraries/vunit_lib/print_pkg-body.vhd + 1 + VUNIT/vhdl/logging/src/print_pkg-body.vhd + + + Common Libraries/vunit_lib/print_pkg.vhd + 1 + VUNIT/vhdl/logging/src/print_pkg.vhd + + + Common Libraries/vunit_lib/queue_pkg-2008p.vhd + 1 + VUNIT/vhdl/data_types/src/queue_pkg-2008p.vhd + + + Common Libraries/vunit_lib/queue_pkg-body.vhd + 1 + VUNIT/vhdl/data_types/src/queue_pkg-body.vhd + + + Common Libraries/vunit_lib/queue_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/queue_pkg.vhd + + + Common Libraries/vunit_lib/queue_pool_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/queue_pool_pkg.vhd + + + Common Libraries/vunit_lib/run.vhd + 1 + VUNIT/vhdl/run/src/run.vhd + + + Common Libraries/vunit_lib/run_api.vhd + 1 + VUNIT/vhdl/run/src/run_api.vhd + + + Common Libraries/vunit_lib/run_deprecated_pkg.vhd + 1 + VUNIT/vhdl/run/src/run_deprecated_pkg.vhd + + + Common Libraries/vunit_lib/run_types.vhd + 1 + VUNIT/vhdl/run/src/run_types.vhd + + + Common Libraries/vunit_lib/runner_pkg.vhd + 1 + VUNIT/vhdl/run/src/runner_pkg.vhd + + + Common Libraries/vunit_lib/stop_body_2008p.vhd + 1 + VUNIT/vhdl/core/src/stop_body_2008p.vhd + + + Common Libraries/vunit_lib/stop_pkg.vhd + 1 + VUNIT/vhdl/core/src/stop_pkg.vhd + + + Common Libraries/vunit_lib/string_ops.vhd + 1 + VUNIT/vhdl/string_ops/src/string_ops.vhd + + + Common Libraries/vunit_lib/string_ptr_pkg-body-2002p.vhd + 1 + VUNIT/vhdl/data_types/src/string_ptr_pkg-body-2002p.vhd + + + Common Libraries/vunit_lib/string_ptr_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/string_ptr_pkg.vhd + + + Common Libraries/vunit_lib/string_ptr_pool_pkg.vhd + 1 + VUNIT/vhdl/data_types/src/string_ptr_pool_pkg.vhd + + + Common Libraries/vunit_lib/types.vhd + 1 + VUNIT/vhdl/data_types/src/types.vhd + + + Common Libraries/vunit_lib/vunit_context.vhd + 1 + VUNIT/vhdl/vunit_context.vhd + + + Common Libraries/vunit_lib/vunit_run_context.vhd + 1 + VUNIT/vhdl/vunit_run_context.vhd + + + Common Libraries/xpm/xpm_VCOMP.vhd + 1 + /export/data_1/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd + + + diff --git a/.readthedocs.yaml b/.readthedocs.yaml new file mode 100644 index 00000000..8124aa2e --- /dev/null +++ b/.readthedocs.yaml @@ -0,0 +1,22 @@ +# .readthedocs.yaml +# Read the Docs configuration file +# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details + +# Required +version: 2 + +# Set the version of Python and other tools you might need +build: + os: ubuntu-22.04 + tools: + python: "3.11" + +# Build documentation in the docs/ directory with Sphinx +sphinx: + configuration: docs/source/conf.py + +# We recommend specifying your dependencies to enable reproducible builds: +# https://docs.readthedocs.io/en/stable/guides/reproducible-builds.html +# python: +# install: +# - requirements: docs/requirements.txt \ No newline at end of file diff --git a/README.md b/README.md index 0ad3bdcd..26862229 100644 --- a/README.md +++ b/README.md @@ -3,15 +3,22 @@ VHDL development of the CASPER FFT for use in the CASPER toolflow. ### Fundamentals +![casper_bus](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/casper_bus_test.svg) ![casper_counter](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/casper_counter_test.svg) +![casper_delay](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/casper_delay_test.svg) ![casper_fifo](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/casper_fifo_test.svg) +![casper_flow_control](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/casper_flow_control_test.svg) +![reorder](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/casper_reorder_test.svg) +![misc](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/misc_test.svg) ![casper_multiplexer](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/casper_multiplexer_test.svg) ### Arithmetic +![casper_accumulators](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/casper_accumulators_test.svg) ![casper_adder](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/casper_adder_test.svg) ![casper_multiplier](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/casper_multiplier_test.svg) ### Memory ![casper_ram](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/casper_ram_test.svg) ### DSP +![casper_filter](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/casper_filter_test.svg) ![casper_par_fft](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/casper_par_fft_test.svg) ![casper_pipe_fft](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/casper_pipe_fft_test.svg) ![r2sdf_fft](https://raw.githubusercontent.com/talonmyburgh/casper_dspdevel/badges/.badges/master/r2sdf_fft_test.svg) diff --git a/casper_accumulators/addr_bram_vacc.vhd b/casper_accumulators/addr_bram_vacc.vhd new file mode 100644 index 00000000..f898044e --- /dev/null +++ b/casper_accumulators/addr_bram_vacc.vhd @@ -0,0 +1,176 @@ +-- A VHDL implementation of the CASPER addr_bram_vacc. +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +LIBRARY IEEE, common_pkg_lib, +casper_misc_lib, common_components_lib, casper_adder_lib, +casper_delay_lib, casper_counter_lib; +USE IEEE.std_logic_1164.ALL; +USE common_pkg_lib.common_pkg.ALL; + +entity addr_bram_vacc is + generic( + g_vector_length : NATURAL := 16; + g_output_type : STRING := "SIGNED"; + g_bit_w : NATURAL := 32 + ); + port ( + clk : IN std_logic; + ce : IN std_logic; + new_acc : IN std_logic; + din : IN std_logic_vector; + addr : OUT std_logic_vector(ceil_log2(g_vector_length) - 1 DOWNTO 0) := (others=>'0'); + we : OUT std_logic := '0'; + dout : OUT std_logic_vector(g_bit_w - 1 DOWNTO 0) := (others=>'0') + ); +END addr_bram_vacc; + +architecture rtl of addr_bram_vacc is + SIGNAL s_delay_new_acc : std_logic :='0'; + SIGNAL s_delay_din : std_logic_vector(din'RANGE); + SIGNAL s_pulse_ext_out : std_logic; + SIGNAL s_a : std_logic_vector(g_bit_w - 1 DOWNTO 0); + SIGNAL s_b : std_logic_vector(g_bit_w - 1 DOWNTO 0); + SIGNAL s_delay_bram_in : std_logic_vector(g_bit_w - 1 DOWNTO 0); + SIGNAL s_delay_bram_out : std_logic_vector(g_bit_w - 1 DOWNTO 0); + SIGNAL s_mux_out : std_logic_vector(g_bit_w - 1 DOWNTO 0); + +begin + +-------------------------------------------------------------- +-- delay new_acc signal +-------------------------------------------------------------- +delay_new_acc : process(clk) +BEGIN + IF rising_edge(clk) AND ce = '1' THEN + s_delay_new_acc <= new_acc; + END IF; +END PROCESS; + +-------------------------------------------------------------- +-- delay din signal +-------------------------------------------------------------- +delay_din : entity common_components_lib.common_delay +generic map( + g_dat_w => din'LENGTH, + g_depth => 2 +) +port map( + clk => clk, + in_val => '1', + in_dat => din, + out_dat => s_delay_din +); + +-------------------------------------------------------------- +-- pulse extend +-------------------------------------------------------------- +pulse_ext : entity casper_misc_lib.pulse_ext +generic map( + g_extension => g_vector_length +) +port map( + clk => clk, + ce => ce, + i_pulse => new_acc, + o_pulse => s_pulse_ext_out +); + +-------------------------------------------------------------- +-- mux block +-------------------------------------------------------------- +s_mux_out <= s_delay_bram_out when s_pulse_ext_out = '0' else + (others=>'0') when s_pulse_ext_out = '1' else + (others=>'X'); + +-------------------------------------------------------------- +-- delay mux output +-------------------------------------------------------------- +delay_mux_out : entity common_components_lib.common_delay +generic map( + g_dat_w => g_bit_w, + g_depth => 2 +) +port map( + clk => clk, + in_val => '1', + in_dat => s_mux_out, + out_dat => s_b +); + +-------------------------------------------------------------- +-- resize din signal +-------------------------------------------------------------- +s_a <= RESIZE_SVEC(s_delay_din, g_bit_w); + +-------------------------------------------------------------- +-- adder block +-------------------------------------------------------------- +add_a_b : entity casper_adder_lib.common_add_sub +generic map( + g_direction => "ADD", + g_representation => g_output_type, + g_pipeline_input => 0, + g_pipeline_output => 2, + g_in_dat_w => g_bit_w, + g_out_dat_w => g_bit_w +) +port map( + clk => clk, + clken => ce, + in_a => s_a, + in_b => s_b, + result => s_delay_bram_in +); + +-------------------------------------------------------------- +-- delay bram +-------------------------------------------------------------- +delay_bram_blk : entity casper_delay_lib.delay_bram +generic map ( + g_delay => g_vector_length - 4, + g_ram_primitive => "block", + g_ram_latency => 2 +) +port map ( + clk => clk, + ce => ce, + din => s_delay_bram_in, + dout => s_delay_bram_out +); + +-------------------------------------------------------------- +-- delay s_delay_bram_out signal +-------------------------------------------------------------- +delay_bram_out : process(clk) +BEGIN + IF rising_edge(clk) AND ce = '1' THEN + dout <= s_delay_bram_out; + END IF; +END PROCESS; + +-------------------------------------------------------------- +-- delay s_pulse_ext_out signal +-------------------------------------------------------------- +delay_s_pulse_ext_out : process(clk) +BEGIN + IF rising_edge(clk) AND ce = '1' THEN + we <= s_pulse_ext_out; + END IF; +END PROCESS; + +-------------------------------------------------------------- +-- counter - need a synchronous reset, hence use common_counter +-------------------------------------------------------------- +addr_counter : entity casper_counter_lib.common_counter + GENERIC MAP( + g_width => ceil_log2(g_vector_length) + ) + PORT MAP( + clk => clk, --! Clock signal + clken => ce, + cnt_clr => s_delay_new_acc, + count => addr + ); + +END rtl; \ No newline at end of file diff --git a/casper_accumulators/dsp48e_bram_vacc.vhd b/casper_accumulators/dsp48e_bram_vacc.vhd new file mode 100644 index 00000000..b343d2fa --- /dev/null +++ b/casper_accumulators/dsp48e_bram_vacc.vhd @@ -0,0 +1,331 @@ +-- A VHDL implementation of the CASPER dsp48e_bram_vacc. +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +LIBRARY IEEE, common_pkg_lib, UNISIM, +casper_misc_lib, common_components_lib, +casper_delay_lib; +USE IEEE.std_logic_1164.ALL; +USE common_pkg_lib.common_pkg.ALL; +use UNISIM.vcomponents.all; + +entity dsp48e_bram_vacc is + generic( + g_vector_length : NATURAL := 16; + g_dsp48_version : NATURAL := 1; + g_bit_w : NATURAL := 32 + ); + port ( + clk : IN std_logic; + ce : IN std_logic; + new_acc : IN std_logic; + din : IN std_logic_vector; + valid : OUT std_logic; + dout : OUT std_logic_vector(g_bit_w - 1 DOWNTO 0) := (others=>'0') + ); +END dsp48e_bram_vacc; + +architecture rtl of dsp48e_bram_vacc is + CONSTANT c_concat_hi : std_logic_vector(4 DOWNTO 0) := TO_SVEC(3, 5); + + SIGNAL s_resized_din : std_logic_vector(47 DOWNTO 0); + SIGNAL s_not_new_acc : std_logic; + SIGNAL s_pulse_ext_out : std_logic; + SIGNAL s_dout : std_logic_vector(g_bit_w - 1 DOWNTO 0); + SIGNAL s_dout_cast : std_logic_vector(47 DOWNTO 0); + SIGNAL s_a : std_logic_vector(29 DOWNTO 0); + SIGNAL s_b : std_logic_vector(17 DOWNTO 0); + SIGNAL s_p : std_logic_vector(47 DOWNTO 0); + SIGNAL s_p_sliced : std_logic_vector(31 DOWNTO 0); + SIGNAL s_delay_bram_out : std_logic_vector(31 DOWNTO 0); + SIGNAL s_opmode1 : std_logic_vector(6 DOWNTO 0); + SIGNAL s_opmode2 : std_logic_vector(8 DOWNTO 0); + SIGNAL s_tmp_opmode : std_logic_vector(1 DOWNTO 0); + +begin + +-------------------------------------------------------------- +-- pulse extend new_acc +-------------------------------------------------------------- +pulse_ext : entity casper_misc_lib.pulse_ext +generic map( + g_extension => g_vector_length + ) + port map( + clk => clk, + ce => ce, + i_pulse => new_acc, + o_pulse => s_pulse_ext_out + ); + +-------------------------------------------------------------- +-- reinterpret din to 48bits +-------------------------------------------------------------- +s_resized_din <= RESIZE_SVEC(din, 48); + +-------------------------------------------------------------- +-- negate pulse_ext new_acc signal +-------------------------------------------------------------- +s_not_new_acc <= not s_pulse_ext_out; + +-------------------------------------------------------------- +-- concatenate three signals +-------------------------------------------------------------- +s_tmp_opmode <= s_not_new_acc & s_not_new_acc; +s_opmode1 <= c_concat_hi & s_tmp_opmode; +s_opmode2 <= "00" & s_opmode1; +-------------------------------------------------------------- +-- slice the output of the dsp48 +-------------------------------------------------------------- +s_p_sliced <= s_p(31 DOWNTO 0); + +-------------------------------------------------------------- +-- delay bram +-------------------------------------------------------------- +delay_bram_blk : entity casper_delay_lib.delay_bram +generic map ( + g_delay => g_vector_length - 2, + g_ram_primitive => "block", + g_ram_latency => 2 +) +port map ( + clk => clk, + ce => ce, + din => s_p_sliced, + dout => s_delay_bram_out +); + +-------------------------------------------------------------- +-- slice the output of the delay bram +-------------------------------------------------------------- +s_dout <= s_delay_bram_out(g_bit_w - 1 DOWNTO 0); + +-------------------------------------------------------------- +-- resize s_dout +-------------------------------------------------------------- +s_dout_cast <= RESIZE_SVEC(s_dout, 48); + +-------------------------------------------------------------- +-- populate s_a and s_b +-------------------------------------------------------------- +s_a <= s_dout_cast(47 DOWNTO 18); +s_b <= s_dout_cast(17 DOWNTO 0); + +-------------------------------------------------------------- +-- populate outports +-------------------------------------------------------------- +dout <= s_dout; +valid <= s_pulse_ext_out; + +-------------------------------------------------------------- +-- DSP48 blocks +-------------------------------------------------------------- +use_dsp48e1 : IF g_dsp48_version = 1 GENERATE +DSP48E1_inst : DSP48E1 + generic map ( + -- Feature Control Attributes: Data Path Selection + A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE) + USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE") + USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12") + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" + MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect + SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2" + SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C") + USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET") + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2) + ADREG => 1, -- Number of pipeline stages for pre-adder (0 or 1) + ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1) + AREG => 1, -- Number of pipeline stages for A (0, 1 or 2) + BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2) + BREG => 1, -- Number of pipeline stages for B (0, 1 or 2) + CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1) + CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1) + CREG => 1, -- Number of pipeline stages for C (0 or 1) + DREG => 1, -- Number of pipeline stages for D (0 or 1) + INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1) + MREG => 1, -- Number of multiplier pipeline stages (0 or 1) + OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1) + PREG => 1 -- Number of pipeline stages for P (0 or 1) + ) + port map ( + -- Cascade: 30-bit (each) output: Cascade Ports + ACOUT => open, -- 30-bit output: A port cascade output + BCOUT => open, -- 18-bit output: B port cascade output + CARRYCASCOUT => open, -- 1-bit output: Cascade carry output + MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output + PCOUT => open, -- 48-bit output: Cascade output + -- Control: 1-bit (each) output: Control Inputs/Status Bits + OVERFLOW => open, -- 1-bit output: Overflow in add/acc output + PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output + PATTERNDETECT => open, -- 1-bit output: Pattern detect output + UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output + -- Data: 4-bit (each) output: Data Ports + CARRYOUT => open, -- 4-bit output: Carry output + P => s_p, -- 48-bit output: Primary data output + -- Cascade: 30-bit (each) input: Cascade Ports + ACIN => (others => '0'), -- 30-bit input: A cascade data input + BCIN => (others => '0'), -- 18-bit input: B cascade input + CARRYCASCIN => '0', -- 1-bit input: Cascade carry input + MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input + PCIN => (others => '0'), -- 48-bit input: P cascade input + -- Control: 4-bit (each) input: Control Inputs/Status Bits + ALUMODE => (others => '0'), -- 4-bit input: ALU control input + CARRYINSEL => (others =>'0'), -- 3-bit input: Carry select input + CLK => clk, -- 1-bit input: Clock input + INMODE => (others => '0'), -- 5-bit input: INMODE control input + OPMODE => s_opmode1, -- 7-bit input: Operation mode input + -- Data: 30-bit (each) input: Data Ports + A => s_a, -- 30-bit input: A data input + B => s_b, -- 18-bit input: B data input + C => s_resized_din, -- 48-bit input: C data input + CARRYIN => '0', -- 1-bit input: Carry input signal + D => (others=>'0'), -- 25-bit input: D data input + -- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs + CEA1 => ce, -- 1-bit input: Clock enable input for 1st stage AREG + CEA2 => ce, -- 1-bit input: Clock enable input for 2nd stage AREG + CEAD => ce, -- 1-bit input: Clock enable input for ADREG + CEALUMODE => ce, -- 1-bit input: Clock enable input for ALUMODE + CEB1 => ce, -- 1-bit input: Clock enable input for 1st stage BREG + CEB2 => ce, -- 1-bit input: Clock enable input for 2nd stage BREG + CEC => ce, -- 1-bit input: Clock enable input for CREG + CECARRYIN => ce, -- 1-bit input: Clock enable input for CARRYINREG + CECTRL => ce, -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG + CED => ce, -- 1-bit input: Clock enable input for DREG + CEINMODE => ce, -- 1-bit input: Clock enable input for INMODEREG + CEM => ce, -- 1-bit input: Clock enable input for MREG + CEP => ce, -- 1-bit input: Clock enable input for PREG + RSTA => '0', -- 1-bit input: Reset input for AREG + RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG + RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG + RSTB => '0', -- 1-bit input: Reset input for BREG + RSTC => '0', -- 1-bit input: Reset input for CREG + RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG + RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG + RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG + RSTM => '0', -- 1-bit input: Reset input for MREG + RSTP => '0' -- 1-bit input: Reset input for PREG + ); + +END GENERATE; + +use_dsp48e2 : IF g_dsp48_version = 2 GENERATE + DSP48E2_inst : DSP48E2 + generic map ( + -- Feature Control Attributes: Data Path Selection + AMULTSEL => "A", -- Selects A input to multiplier (A, AD) + A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + BMULTSEL => "B", -- Selects B input to multiplier (AD, B) + B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + PREADDINSEL => "A", -- Selects input to pre-adder (A, B) + RND => X"000000000000", -- Rounding Constant + USE_MULT => "NONE", -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + USE_SIMD => "ONE48", -- SIMD selection (FOUR12, ONE48, TWO24) + USE_WIDEXOR => "FALSE", -- Use the Wide XOR function (FALSE, TRUE) + XORSIMD => "XOR24_48_96", -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) + -- Pattern Detector Attributes: Pattern Detection Configuration + AUTORESET_PATDET => "NO_RESET", -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH + AUTORESET_PRIORITY => "RESET", -- Priority of AUTORESET vs. CEP (CEP, RESET). + MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore) + PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect + SEL_MASK => "MASK", -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + SEL_PATTERN => "PATTERN", -- Select pattern value (C, PATTERN) + USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect (NO_PATDET, PATDET) + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_ALUMODE_INVERTED => "0000", -- Optional inversion for ALUMODE + IS_CARRYIN_INVERTED => '0', -- Optional inversion for CARRYIN + IS_CLK_INVERTED => '0', -- Optional inversion for CLK + IS_INMODE_INVERTED => "00000", -- Optional inversion for INMODE + IS_OPMODE_INVERTED => "000000000", -- Optional inversion for OPMODE + IS_RSTALLCARRYIN_INVERTED => '0', -- Optional inversion for RSTALLCARRYIN + IS_RSTALUMODE_INVERTED => '0', -- Optional inversion for RSTALUMODE + IS_RSTA_INVERTED => '0', -- Optional inversion for RSTA + IS_RSTB_INVERTED => '0', -- Optional inversion for RSTB + IS_RSTCTRL_INVERTED => '0', -- Optional inversion for RSTCTRL + IS_RSTC_INVERTED => '0', -- Optional inversion for RSTC + IS_RSTD_INVERTED => '0', -- Optional inversion for RSTD + IS_RSTINMODE_INVERTED => '0', -- Optional inversion for RSTINMODE + IS_RSTM_INVERTED => '0', -- Optional inversion for RSTM + IS_RSTP_INVERTED => '0', -- Optional inversion for RSTP + -- Register Control Attributes: Pipeline Register Configuration + ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) + ADREG => 1, -- Pipeline stages for pre-adder (0-1) + ALUMODEREG => 1, -- Pipeline stages for ALUMODE (0-1) + AREG => 1, -- Pipeline stages for A (0-2) + BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) + BREG => 1, -- Pipeline stages for B (0-2) + CARRYINREG => 1, -- Pipeline stages for CARRYIN (0-1) + CARRYINSELREG => 1, -- Pipeline stages for CARRYINSEL (0-1) + CREG => 1, -- Pipeline stages for C (0-1) + DREG => 1, -- Pipeline stages for D (0-1) + INMODEREG => 1, -- Pipeline stages for INMODE (0-1) + MREG => 1, -- Multiplier pipeline stages (0-1) + OPMODEREG => 1, -- Pipeline stages for OPMODE (0-1) + PREG => 1 -- Number of pipeline stages for P (0-1) + ) + port map ( + -- Cascade outputs: Cascade Ports + ACOUT => open, -- 30-bit output: A port cascade + BCOUT => open, -- 18-bit output: B cascade + CARRYCASCOUT => open, -- 1-bit output: Cascade carry + MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade + PCOUT => open, -- 48-bit output: Cascade output + -- Control outputs: Control Inputs/Status Bits + OVERFLOW => open, -- 1-bit output: Overflow in add/acc + PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect + PATTERNDETECT => open, -- 1-bit output: Pattern detect + UNDERFLOW => open, -- 1-bit output: Underflow in add/acc + -- Data outputs:Data Ports + CARRYOUT => open, -- 4-bit output: Carry + P => s_p, -- 48-bit output: Primary data + XOROUT => open, -- 8-bit output: XOR data + -- Cascade inputs: Cascade Ports + ACIN => (others => '0'), -- 30-bit input: A cascade data + BCIN => (others => '0'), -- 18-bit input: B cascade + CARRYCASCIN => '0', -- 1-bit input: Cascade carry + MULTSIGNIN => '0', -- 1-bit input: Multiplier sign cascade + PCIN => (others => '0'), -- 48-bit input: P cascade + -- Control inputs: Control Inputs/Status Bits + ALUMODE => (others => '0'), -- 4-bit input: ALU control + CARRYINSEL => (others => '0'), -- 3-bit input: Carry select + CLK => clk, -- 1-bit input: Clock + INMODE => (others => '0'), -- 5-bit input: INMODE control + OPMODE => s_opmode2, -- 9-bit input: Operation mode + -- Data inputs: Data Ports + A => s_a, -- 30-bit input: A data + B => s_b, -- 18-bit input: B data + C => s_resized_din, -- 48-bit input: C data + CARRYIN => '0', -- 1-bit input: Carry-in + D => (others => '0'), -- 27-bit input: D data + -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs + CEA1 => ce, -- 1-bit input: Clock enable for 1st stage AREG + CEA2 => ce, -- 1-bit input: Clock enable for 2nd stage AREG + CEAD => ce, -- 1-bit input: Clock enable for ADREG + CEALUMODE => ce, -- 1-bit input: Clock enable for ALUMODE + CEB1 => ce, -- 1-bit input: Clock enable for 1st stage BREG + CEB2 => ce, -- 1-bit input: Clock enable for 2nd stage BREG + CEC => ce, -- 1-bit input: Clock enable for CREG + CECARRYIN => ce, -- 1-bit input: Clock enable for CARRYINREG + CECTRL => ce, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + CED => ce, -- 1-bit input: Clock enable for DREG + CEINMODE => ce, -- 1-bit input: Clock enable for INMODEREG + CEM => ce, -- 1-bit input: Clock enable for MREG + CEP => ce, -- 1-bit input: Clock enable for PREG + RSTA => '0', -- 1-bit input: Reset for AREG + RSTALLCARRYIN => '0', -- 1-bit input: Reset for CARRYINREG + RSTALUMODE => '0', -- 1-bit input: Reset for ALUMODEREG + RSTB => '0', -- 1-bit input: Reset for BREG + RSTC => '0', -- 1-bit input: Reset for CREG + RSTCTRL => '0', -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG + RSTD => '0', -- 1-bit input: Reset for DREG and ADREG + RSTINMODE => '0', -- 1-bit input: Reset for INMODEREG + RSTM => '0', -- 1-bit input: Reset for MREG + RSTP => '0' -- 1-bit input: Reset for PREG + ); +END GENERATE; + +END rtl; \ No newline at end of file diff --git a/casper_accumulators/run.py b/casper_accumulators/run.py new file mode 100644 index 00000000..c61263d0 --- /dev/null +++ b/casper_accumulators/run.py @@ -0,0 +1,144 @@ +from vunit import VUnit +from os.path import dirname, join +import numpy as np + +# Create VUnit instance by parsing command line arguments +vu = VUnit.from_argv() +vu.add_vhdl_builtins() +script_dir = dirname(__file__) + +# XPM Library compile +lib_xpm = vu.add_library("xpm") +lib_xpm.add_source_files(join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_VCOMP.vhd")) +xpm_source_file_base = lib_xpm.add_source_file(join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_base.vhd")) +xpm_source_file_sdpram = lib_xpm.add_source_file(join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_sdpram.vhd")) +xpm_source_file_tdpram = lib_xpm.add_source_file(join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_tdpram.vhd")) +xpm_source_file_sdpram.add_dependency_on(xpm_source_file_base) +xpm_source_file_tdpram.add_dependency_on(xpm_source_file_base) + +# Altera_mf library +lib_altera_mf = vu.add_library("altera_mf") +lib_altera_mf.add_source_files(join(script_dir, "../intel/altera_mf/altera_mf_components.vhd")) +altera_mf_source_file = lib_altera_mf.add_source_files(join(script_dir, "../intel/altera_mf/altera_mf.vhd")) + +# Create library 'casper_counter_lib' +casper_counter_lib = vu.add_library("casper_counter_lib") +casper_counter_lib.add_source_files(join(script_dir,"../casper_counter/common_counter.vhd")) +casper_counter_lib.add_source_files(join(script_dir,"../casper_counter/free_run_up_counter.vhd")) + +# Create library 'common_pkg_lib' +common_pkg_lib = vu.add_library("common_pkg_lib") +common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/fixed_float_types_c.vhd")) +common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/fixed_pkg_c.vhd")) +common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/float_pkg_c.vhd")) +common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/common_pkg.vhd")) + +# Create library 'ip_xpm_ram_lib' +ip_xpm_ram_lib = vu.add_library("ip_xpm_ram_lib") +ip_xpm_file_cr_cw = ip_xpm_ram_lib.add_source_files(join(script_dir, "../ip_xpm/ram/ip_xpm_ram_cr_cw.vhd")) +ip_xpm_file_cr_cw.add_dependency_on(xpm_source_file_sdpram) +ip_xpm_file_crw_crw = ip_xpm_ram_lib.add_source_files(join(script_dir, "../ip_xpm/ram/ip_xpm_ram_crw_crw.vhd")) +ip_xpm_file_crw_crw.add_dependency_on(xpm_source_file_tdpram) + +# STRATIXIV RAM Library +ip_stratixiv_ram_lib = vu.add_library("ip_stratixiv_ram_lib") +ip_stratix_file_cr_cw = ip_stratixiv_ram_lib.add_source_file(join(script_dir, "../ip_stratixiv/ram/ip_stratixiv_ram_cr_cw.vhd")) +ip_stratix_file_crw_crw = ip_stratixiv_ram_lib.add_source_file(join(script_dir, "../ip_stratixiv/ram/ip_stratixiv_ram_crw_crw.vhd")) +ip_stratix_file_cr_cw.add_dependency_on(altera_mf_source_file) +ip_stratix_file_crw_crw.add_dependency_on(altera_mf_source_file) +# CASPER adder library +casper_adder_lib = vu.add_library("casper_adder_lib") +casper_adder_lib.add_source_file(join(script_dir, "../casper_adder/common_add_sub.vhd")) + +# COMMON COMPONENTS Library +common_components_lib = vu.add_library("common_components_lib") +common_components_lib.add_source_files(join(script_dir, "../common_components/common_pipeline.vhd")) +common_components_lib.add_source_files(join(script_dir, "../common_components/common_pipeline_sl.vhd")) +common_components_lib.add_source_files(join(script_dir, "../common_components/common_delay.vhd")) +common_components_lib.add_source_files(join(script_dir, "../common_components/common_components_pkg.vhd")) + +# Create library 'casper_ram_lib' +casper_ram_lib = vu.add_library("casper_ram_lib") +casper_ram_lib.add_source_files(join(script_dir, "../casper_ram/common_ram_pkg.vhd")) +casper_ram_lib.add_source_files(join(script_dir, "../casper_ram/tech_memory_component_pkg.vhd")) +casper_ram_lib.add_source_files(join(script_dir, "../casper_ram/tech_memory_ram_crw_crw.vhd")) +casper_ram_lib.add_source_files(join(script_dir, "../casper_ram/tech_memory_ram_cr_cw.vhd")) +casper_ram_lib.add_source_files(join(script_dir, "../casper_ram/common_ram_crw_crw.vhd")) +casper_ram_lib.add_source_files(join(script_dir, "../casper_ram/common_ram_rw_rw.vhd")) +casper_ram_lib.add_source_files(join(script_dir, "../casper_ram/common_ram_r_w.vhd")) + +# Create library 'technology_lib' +technology_lib = vu.add_library("technology_lib") +technology_lib.add_source_files(join(script_dir, "../technology/technology_select_pkg.vhd")) + +# Create library 'casper_delay_lib' +casper_delay_lib = vu.add_library("casper_delay_lib") +casper_delay_lib.add_source_file(join(script_dir, "../casper_delay/delay_bram.vhd")) + +# MISC Library compile +casper_misc_lib = vu.add_library("casper_misc_lib") +casper_misc_lib.add_source_files(join(script_dir, "../misc/pulse_ext.vhd")) +casper_misc_lib.add_source_files(join(script_dir, "../misc/edge_detect.vhd")) + +# Accumulator Library +casper_accumulator_lib = vu.add_library("casper_accumulator_lib") +casper_accumulator_lib.add_source_files(join(script_dir, "./addr_bram_vacc.vhd")) +casper_accumulator_lib.add_source_files(join(script_dir, "./simple_bram_vacc.vhd")) +casper_accumulator_lib.add_source_files(join(script_dir, "./tb_addr_bram_vacc.vhd")) +casper_accumulator_lib.add_source_files(join(script_dir, "./tb_simple_bram_vacc.vhd")) +casper_accumulator_lib.add_source_files(join(script_dir, "./tb_tb_vu_addr_bram_vacc.vhd")) +casper_accumulator_lib.add_source_files(join(script_dir, "./tb_tb_vu_simple_bram_vacc.vhd")) + +TB_ADDR_BRAM_VACC = casper_accumulator_lib.test_bench("tb_tb_vu_addr_bram_vacc") +TB_SIMPLE_BRAM_VACC = casper_accumulator_lib.test_bench("tb_tb_vu_simple_bram_vacc") + +# Generics +bit_w = [8,18] +ramp = np.arange(16) +rampstr = ",".join(map(str, ramp)) +randnums= np.random.randint(-100,100,32) +randstr = ",".join(map(str, randnums)) + +for b_w in bit_w: + vector_len = ramp.size + config_name = "TB_ADDR_BRAM_VACC: bit_w=%d, vec_len=%d, strvalue=%s..." % (b_w,vector_len,rampstr[0:8]) + config_name_simple = "TB_SIMPLE_BRAM_VACC: bit_w=%d, vec_len=%d, strvalue=%s..." % (b_w,vector_len,rampstr[0:8]) + TB_ADDR_BRAM_VACC.add_config( + name=config_name, + generics=dict( + g_bit_w=b_w, + g_values=rampstr, + g_vector_length=vector_len + ) + ) + TB_SIMPLE_BRAM_VACC.add_config( + name=config_name_simple, + generics=dict( + g_bit_w=b_w, + g_values=rampstr, + g_vector_length=vector_len + ) + ) + vector_len = randnums.size + config_name = "TB_ADDR_BRAM_VACC: bit_w=%d, vec_len=%d, strvalue=%s..." % (b_w,vector_len,randstr[0:8]) + config_name_simple = "TB_SIMPLE_BRAM_VACC: bit_w=%d, vec_len=%d, strvalue=%s..." % (b_w,vector_len,randstr[0:8]) + TB_ADDR_BRAM_VACC.add_config( + name=config_name, + generics=dict( + g_bit_w=b_w, + g_values=randstr, + g_vector_length=vector_len + ) + ) + TB_SIMPLE_BRAM_VACC.add_config( + name=config_name_simple, + generics=dict( + g_bit_w=b_w, + g_values=randstr, + g_vector_length=vector_len + ) + ) + +vu.set_compile_option("ghdl.a_flags", ["-Wno-hide", "-frelaxed","-fsynopsys","-fexplicit"]) +vu.set_sim_option("ghdl.elab_flags", ["-frelaxed","-fsynopsys","-fexplicit","--syn-binding"]) +vu.main() \ No newline at end of file diff --git a/casper_accumulators/simple_accumulator.vhd b/casper_accumulators/simple_accumulator.vhd new file mode 100644 index 00000000..b104359d --- /dev/null +++ b/casper_accumulators/simple_accumulator.vhd @@ -0,0 +1,41 @@ +LIBRARY IEEE, common_pkg_lib, common_components_lib; +USE IEEE.std_logic_1164.ALL; +USE common_pkg_lib.common_pkg.ALL; + +ENTITY simple_accumulator IS + GENERIC( + g_representation : STRING := "SIGNED" --! "SIGNED" or "UNSIGNED" + ); + PORT( + clk : IN STD_LOGIC; --! input clock source + ce : IN STD_LOGIC := '1'; --! enable process triggering on clock rising edge + rst : IN STD_LOGIC := '0'; --! reset accumulation + in_b : IN STD_LOGIC_VECTOR; --! input value B + result : OUT STD_LOGIC_VECTOR --! result + ); +END simple_accumulator; + +architecture rtl of simple_accumulator is + signal s_buf : STD_LOGIC_VECTOR(result'range) := (others => '0'); +begin + + result <= s_buf; + + process (clk) + begin + if rising_edge(clk) then + IF rst = '1' then + s_buf <= (others => '0'); + elsif ce = '1' then + IF g_representation = "SIGNED" THEN + s_buf <= ADD_SVEC(in_b, s_buf, result'length); + ELSE + s_buf <= ADD_UVEC(in_b, s_buf, result'length); + END IF; + end if; + end if; + end process; + + + +end architecture; \ No newline at end of file diff --git a/casper_accumulators/simple_bram_vacc.vhd b/casper_accumulators/simple_bram_vacc.vhd new file mode 100644 index 00000000..1c6d8b4c --- /dev/null +++ b/casper_accumulators/simple_bram_vacc.vhd @@ -0,0 +1,104 @@ +-- A VHDL implementation of the CASPER simple_bram_vacc. +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +LIBRARY IEEE, common_pkg_lib, +casper_misc_lib, common_components_lib, casper_adder_lib, +casper_delay_lib; +USE IEEE.std_logic_1164.ALL; +USE common_pkg_lib.common_pkg.ALL; + +entity simple_bram_vacc is + generic( + g_vector_length : NATURAL := 16; + g_output_type : STRING := "SIGNED"; + g_bit_w : NATURAL := 32 + ); + port ( + clk : IN std_logic; + ce : IN std_logic; + new_acc : IN std_logic; + din : IN std_logic_vector; + valid : OUT std_logic := '0'; + dout : OUT std_logic_vector(g_bit_w - 1 DOWNTO 0) := (others=>'0') + ); +END simple_bram_vacc; + +architecture rtl of simple_bram_vacc is + SIGNAL s_pulse_ext_out : std_logic; + SIGNAL s_a : std_logic_vector(g_bit_w - 1 DOWNTO 0); + SIGNAL s_delay_bram_in : std_logic_vector(g_bit_w - 1 DOWNTO 0); + SIGNAL s_delay_bram_out : std_logic_vector(g_bit_w - 1 DOWNTO 0); + SIGNAL s_mux_out : std_logic_vector(g_bit_w - 1 DOWNTO 0); + +begin + +-------------------------------------------------------------- +-- pulse extend new_acc signal +-------------------------------------------------------------- +pulse_ext : entity casper_misc_lib.pulse_ext +generic map( + g_extension => g_vector_length +) +port map( + clk => clk, + ce => ce, + i_pulse => new_acc, + o_pulse => s_pulse_ext_out +); + +-------------------------------------------------------------- +-- mux block +-------------------------------------------------------------- +s_mux_out <= s_delay_bram_out when s_pulse_ext_out = '0' else + (others=>'0') when s_pulse_ext_out = '1' else + (others=>'X'); + +-------------------------------------------------------------- +-- resize din signal +-------------------------------------------------------------- +s_a <= RESIZE_SVEC(din, g_bit_w); + +-------------------------------------------------------------- +-- adder block +-------------------------------------------------------------- +add_a_b : entity casper_adder_lib.common_add_sub +generic map( + g_direction => "ADD", + g_representation => g_output_type, + g_pipeline_input => 0, + g_pipeline_output => 2, + g_in_dat_w => g_bit_w, + g_out_dat_w => g_bit_w +) +port map( + clk => clk, + clken => ce, + in_a => s_a, + in_b => s_mux_out, + result => s_delay_bram_in +); + +-------------------------------------------------------------- +-- delay bram +-------------------------------------------------------------- +delay_bram_blk : entity casper_delay_lib.delay_bram +generic map ( + g_delay => g_vector_length - 2, + g_ram_primitive => "block", + g_ram_latency => 2 +) +port map ( + clk => clk, + ce => ce, + din => s_delay_bram_in, + dout => s_delay_bram_out +); + +-------------------------------------------------------------- +-- set up output signals +-------------------------------------------------------------- +dout <= s_delay_bram_out; +valid <= s_pulse_ext_out; + +END rtl; \ No newline at end of file diff --git a/casper_accumulators/tb_addr_bram_vacc.vhd b/casper_accumulators/tb_addr_bram_vacc.vhd new file mode 100644 index 00000000..8a4a4dc8 --- /dev/null +++ b/casper_accumulators/tb_addr_bram_vacc.vhd @@ -0,0 +1,130 @@ +-- A VHDL testbench for addr_bram_vacc.vhd. +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +LIBRARY IEEE, std, common_pkg_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +USE STD.TEXTIO.ALL; + +entity tb_addr_bram_vacc is + generic ( + g_vector_length : NATURAL := 8; + g_bit_w_out : NATURAL := 8; + g_bit_w : NATURAL := 8; + g_values : t_integer_arr := (-1, 4, 10, -2, 3, 0, -15, 0) + ); + port ( + o_clk : out std_logic; + o_tb_end : out std_logic; + o_test_msg : out STRING(1 to 80); + o_test_pass : out BOOLEAN := True + ); +end entity tb_addr_bram_vacc; + +architecture rtl of tb_addr_bram_vacc is + + CONSTANT clk_period : TIME := 10 ns; + + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL ce : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL new_acc : STD_LOGIC := '0'; + SIGNAL din : std_logic_vector(g_bit_w - 1 DOWNTO 0) := (others=>'0'); + SIGNAL addr : std_logic_vector(ceil_log2(g_vector_length) - 1 DOWNTO 0); + SIGNAL we : STD_LOGIC; + SIGNAL dout : std_logic_vector(g_bit_w_out - 1 DOWNTO 0); + SIGNAL test_spike : STD_LOGIC:='0'; + +begin + clk <= NOT clk OR tb_end AFTER clk_period / 2; + + o_clk <= clk; + o_tb_end <= tb_end; + + --------------------------------------------------------------------- + -- Stimulus process + --------------------------------------------------------------------- + p_stimuli_verify : PROCESS + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + VARIABLE v_test_vector : STD_LOGIC_VECTOR(g_bit_w -1 DOWNTO 0); + VARIABLE v_test_pass : BOOLEAN := True; + BEGIN + WAIT UNTIL rising_edge(clk); + ce <= '1'; + new_acc <= '1'; + WAIT FOR clk_period*(g_vector_length+2); + FOR I in 0 to g_vector_length - 1 LOOP + WAIT FOR clk_period; + v_test_vector := TO_SVEC(g_values(g_values'LOW + I), g_bit_w); + v_test_pass := v_test_pass or (dout = v_test_vector); + IF NOT v_test_pass THEN + v_test_msg := pad("1wrong RTL result for dout, expected: " & to_hstring(v_test_vector) & " but got: " & to_hstring(dout), o_test_msg'length, '.'); + o_test_msg <= v_test_msg; + report "Error: " & v_test_msg severity error; + END IF; + END LOOP; + WAIT FOR clk_period*(g_vector_length)*5; + FOR I in 0 to g_vector_length - 1 LOOP + WAIT FOR clk_period; + v_test_vector := TO_SVEC(g_values(g_values'LOW + I)*7, g_bit_w); + v_test_pass := v_test_pass or (dout = v_test_vector); + IF NOT v_test_pass THEN + v_test_msg := pad("2wrong RTL result for dout, expected: " & to_hstring(v_test_vector) & " but got: " & to_hstring(dout), o_test_msg'length, '.'); + o_test_msg <= v_test_msg; + report "Error: " & v_test_msg severity error; + END IF; + END LOOP; + new_acc <= '0'; + WAIT FOR clk_period*(g_vector_length - 1); + -- reload the vector + new_acc <= '1'; + WAIT FOR clk_period*(g_vector_length+1); + WAIT UNTIL rising_edge(clk); + v_test_vector := TO_SVEC(g_values(g_values'LOW), g_bit_w); + v_test_pass := v_test_pass or (dout = v_test_vector); + IF NOT v_test_pass THEN + v_test_msg := pad("3wrong RTL result for dout, expected: " & to_hstring(v_test_vector) & " but got: " & to_hstring(dout), o_test_msg'length, '.'); + o_test_msg <= v_test_msg; + report "Error: " & v_test_msg severity error; + END IF; + o_test_msg <= v_test_msg; + o_test_pass <= v_test_pass; + tb_end <= '1'; + WAIT; + + END PROCESS; + + -- Process to unroll values into din + p_unroll_nat_array : PROCESS(clk, ce) + VARIABLE I : INTEGER := 0; + BEGIN + IF rising_edge(clk) and ce = '1' THEN + din <= TO_SVEC(g_values(g_values'LOW + I), g_bit_w); + IF I = g_vector_length -1 THEN + I := 0; + ELSE + I := I + 1; + END IF; + END IF; + END PROCESS; + --------------------------------------------------------------------- + -- addr BRAM vacc module + --------------------------------------------------------------------- + addr_bram_vacc : ENTITY work.addr_bram_vacc + generic map( + g_vector_length => g_vector_length, + g_bit_w => g_bit_w_out + ) + port map( + clk => clk, + ce => ce, + new_acc => new_acc, + din => din, + addr => addr, + we => we, + dout => dout + ); + +end architecture; \ No newline at end of file diff --git a/casper_accumulators/tb_dsp48e_bram_vacc.vhd b/casper_accumulators/tb_dsp48e_bram_vacc.vhd new file mode 100644 index 00000000..fe6ad5b1 --- /dev/null +++ b/casper_accumulators/tb_dsp48e_bram_vacc.vhd @@ -0,0 +1,130 @@ +-- A VHDL testbench for dsp48e_bram_vacc. +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +LIBRARY IEEE, std, common_pkg_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +USE STD.TEXTIO.ALL; + +entity tb_dsp48e_bram_vacc is + generic ( + g_vector_length : NATURAL := 8; + g_bit_w_out : NATURAL := 8; + g_bit_w : NATURAL := 8; + g_dsp48_version : NATURAL := 2; + g_values : t_integer_arr := (-1, 4, 10, -2, 3, 0, -15, 0) + ); + port ( + o_clk : out std_logic; + o_tb_end : out std_logic; + o_test_msg : out STRING(1 to 80); + o_test_pass : out BOOLEAN := True + ); +end entity tb_dsp48e_bram_vacc; + +architecture rtl of tb_dsp48e_bram_vacc is + + CONSTANT clk_period : TIME := 10 ns; + + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL ce : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL new_acc : STD_LOGIC := '0'; + SIGNAL din : std_logic_vector(g_bit_w - 1 DOWNTO 0) := (others=>'0'); + SIGNAL valid : STD_LOGIC; + SIGNAL dout : std_logic_vector(g_bit_w_out - 1 DOWNTO 0); + SIGNAL test_spike : STD_LOGIC:='0'; + +begin + clk <= NOT clk OR tb_end AFTER clk_period / 2; + + o_clk <= clk; + o_tb_end <= tb_end; + + --------------------------------------------------------------------- + -- Stimulus process + --------------------------------------------------------------------- + p_stimuli_verify : PROCESS + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + VARIABLE v_test_vector : STD_LOGIC_VECTOR(g_bit_w -1 DOWNTO 0); + VARIABLE v_test_pass : BOOLEAN := True; + BEGIN + WAIT UNTIL rising_edge(clk); + ce <= '1'; + new_acc <= '1'; + WAIT FOR clk_period*(g_vector_length+2); + FOR I in 0 to g_vector_length - 1 LOOP + WAIT FOR clk_period; + v_test_vector := TO_SVEC(g_values(g_values'LOW + I), g_bit_w); + v_test_pass := v_test_pass or (dout = v_test_vector); + IF NOT v_test_pass THEN + v_test_msg := pad("1wrong RTL result for dout, expected: " & to_hstring(v_test_vector) & " but got: " & to_hstring(dout), o_test_msg'length, '.'); + o_test_msg <= v_test_msg; + report "Error: " & v_test_msg severity error; + END IF; + END LOOP; + WAIT FOR clk_period*(g_vector_length)*5; + FOR I in 0 to g_vector_length - 1 LOOP + WAIT FOR clk_period; + v_test_vector := TO_SVEC(g_values(g_values'LOW + I)*7, g_bit_w); + v_test_pass := v_test_pass or (dout = v_test_vector); + IF NOT v_test_pass THEN + v_test_msg := pad("2wrong RTL result for dout, expected: " & to_hstring(v_test_vector) & " but got: " & to_hstring(dout), o_test_msg'length, '.'); + o_test_msg <= v_test_msg; + report "Error: " & v_test_msg severity error; + END IF; + END LOOP; + new_acc <= '0'; + WAIT FOR clk_period*(g_vector_length - 1); + -- reload the vector + new_acc <= '1'; + WAIT FOR clk_period*(g_vector_length+1); + WAIT UNTIL rising_edge(clk); + v_test_vector := TO_SVEC(g_values(g_values'LOW), g_bit_w); + v_test_pass := v_test_pass or (dout = v_test_vector); + IF NOT v_test_pass THEN + v_test_msg := pad("3wrong RTL result for dout, expected: " & to_hstring(v_test_vector) & " but got: " & to_hstring(dout), o_test_msg'length, '.'); + o_test_msg <= v_test_msg; + report "Error: " & v_test_msg severity error; + END IF; + o_test_msg <= v_test_msg; + o_test_pass <= v_test_pass; + tb_end <= '1'; + WAIT; + + END PROCESS; + + -- Process to unroll values into din + p_unroll_nat_array : PROCESS(clk, ce) + VARIABLE I : INTEGER := 0; + BEGIN + IF rising_edge(clk) and ce = '1' THEN + din <= TO_SVEC(g_values(g_values'LOW + I), g_bit_w); + IF I = g_vector_length -1 THEN + I := 0; + ELSE + I := I + 1; + END IF; + END IF; + END PROCESS; + --------------------------------------------------------------------- + -- addr BRAM vacc module + --------------------------------------------------------------------- + addr_bram_vacc : ENTITY work.dsp48e_bram_vacc + generic map( + g_vector_length => g_vector_length, + g_bit_w => g_bit_w_out, + g_dsp48_version => g_dsp48_version + ) + port map( + clk => clk, + ce => ce, + new_acc => new_acc, + din => din, + valid => valid, + dout => dout + ); + +end architecture; \ No newline at end of file diff --git a/casper_accumulators/tb_simple_bram_vacc.vhd b/casper_accumulators/tb_simple_bram_vacc.vhd new file mode 100644 index 00000000..6328b7f1 --- /dev/null +++ b/casper_accumulators/tb_simple_bram_vacc.vhd @@ -0,0 +1,127 @@ +-- A VHDL testbench for simple_bram_vacc.vhd. +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +LIBRARY IEEE, std, common_pkg_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +USE STD.TEXTIO.ALL; + +entity tb_simple_bram_vacc is + generic ( + g_vector_length : NATURAL := 8; + g_bit_w_out : NATURAL := 8; + g_bit_w : NATURAL := 8; + g_values : t_integer_arr := (-1, 4, 10, -2, 3, 0, -15, 0) + ); + port ( + o_clk : out std_logic; + o_tb_end : out std_logic; + o_test_msg : out STRING(1 to 80); + o_test_pass : out BOOLEAN := True + ); +end entity tb_simple_bram_vacc; + +architecture rtl of tb_simple_bram_vacc is + + CONSTANT clk_period : TIME := 10 ns; + + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL ce : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL new_acc : STD_LOGIC := '0'; + SIGNAL din : std_logic_vector(g_bit_w - 1 DOWNTO 0) := (others=>'0'); + SIGNAL valid : STD_LOGIC; + SIGNAL dout : std_logic_vector(g_bit_w_out - 1 DOWNTO 0); + +begin + clk <= NOT clk OR tb_end AFTER clk_period / 2; + + o_clk <= clk; + o_tb_end <= tb_end; + + --------------------------------------------------------------------- + -- Stimulus process + --------------------------------------------------------------------- + p_stimuli_verify : PROCESS + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + VARIABLE v_test_vector : STD_LOGIC_VECTOR(g_bit_w -1 DOWNTO 0); + VARIABLE v_test_pass : BOOLEAN := True; + BEGIN + WAIT UNTIL rising_edge(clk); + ce <= '1'; + new_acc <= '1'; + WAIT FOR clk_period*(g_vector_length+2); + FOR I in 0 to g_vector_length - 1 LOOP + WAIT FOR clk_period; + v_test_vector := TO_SVEC(g_values(g_values'LOW + I), g_bit_w); + v_test_pass := v_test_pass or (dout = v_test_vector); + IF NOT v_test_pass THEN + v_test_msg := pad("wrong RTL result for dout, expected: " & to_hstring(v_test_vector) & " but got: " & to_hstring(dout), o_test_msg'length, '.'); + o_test_msg <= v_test_msg; + report "Error: " & v_test_msg severity error; + END IF; + END LOOP; + WAIT FOR clk_period*(g_vector_length)*5; + FOR I in 0 to g_vector_length - 1 LOOP + WAIT FOR clk_period; + v_test_vector := TO_SVEC(g_values(g_values'LOW + I)*7, g_bit_w); + v_test_pass := v_test_pass or (dout = v_test_vector); + IF NOT v_test_pass THEN + v_test_msg := pad("wrong RTL result for dout, expected: " & to_hstring(v_test_vector) & " but got: " & to_hstring(dout), o_test_msg'length, '.'); + o_test_msg <= v_test_msg; + report "Error: " & v_test_msg severity error; + END IF; + END LOOP; + new_acc <= '0'; + WAIT FOR clk_period*(g_vector_length - 1); + -- reload the vector + new_acc <= '1'; + WAIT FOR clk_period*(g_vector_length+1); + WAIT UNTIL rising_edge(clk); + v_test_vector := TO_SVEC(g_values(g_values'LOW), g_bit_w); + v_test_pass := v_test_pass or (dout = v_test_vector); + IF NOT v_test_pass THEN + v_test_msg := pad("wrong RTL result for dout, expected: " & to_hstring(v_test_vector) & " but got: " & to_hstring(dout), o_test_msg'length, '.'); + o_test_msg <= v_test_msg; + report "Error: " & v_test_msg severity error; + END IF; + o_test_msg <= v_test_msg; + o_test_pass <= v_test_pass; + tb_end <= '1'; + WAIT; + + END PROCESS; + + -- Process to unroll values into din + p_unroll_nat_array : PROCESS(clk) + VARIABLE I : INTEGER := 0; + BEGIN + IF rising_edge(clk) and ce = '1' THEN + din <= TO_SVEC(g_values(g_values'LOW + I), g_bit_w); + IF I = g_vector_length -1 THEN + I := 0; + ELSE + I := I + 1; + END IF; + END IF; + END PROCESS; + --------------------------------------------------------------------- + -- simple BRAM vacc module + --------------------------------------------------------------------- + simple_bram_vacc : ENTITY work.simple_bram_vacc + generic map( + g_vector_length => g_vector_length, + g_bit_w => g_bit_w_out + ) + port map( + clk => clk, + ce => ce, + new_acc => new_acc, + din => din, + valid => valid, + dout => dout + ); + +end architecture; \ No newline at end of file diff --git a/casper_accumulators/tb_tb_vu_addr_bram_vacc.vhd b/casper_accumulators/tb_tb_vu_addr_bram_vacc.vhd new file mode 100644 index 00000000..300c2e62 --- /dev/null +++ b/casper_accumulators/tb_tb_vu_addr_bram_vacc.vhd @@ -0,0 +1,67 @@ +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +library ieee, common_pkg_lib, vunit_lib; +use IEEE.std_logic_1164.all; +use common_pkg_lib.common_pkg.all; +context vunit_lib.vunit_context; + +entity tb_tb_vu_addr_bram_vacc is + GENERIC( + g_vector_length : NATURAL := 8; + g_bit_w : NATURAL := 8; + g_values : STRING; -- CSV list of naturals + runner_cfg : STRING + ); +end tb_tb_vu_addr_bram_vacc; + +architecture tb of tb_tb_vu_addr_bram_vacc is + + SIGNAL rst : STD_LOGIC := '0'; + SIGNAL clk : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC; + SIGNAL test_msg : STRING(1 to 80); + SIGNAL test_pass : BOOLEAN; + + IMPURE FUNCTION decode(encoded_natural_vector : string) return t_integer_arr is + VARIABLE parts : lines_t := split(encoded_natural_vector, ","); + VARIABLE return_value : t_integer_arr(parts'range); + BEGIN + for i in parts'range loop + return_value(i) := integer'value(parts(i).all); + end loop; + return return_value; + END; + + CONSTANT c_values : t_integer_arr := decode(g_values); +BEGIN + tb_ut : ENTITY work.tb_addr_bram_vacc + GENERIC MAP( + g_vector_length => g_vector_length, + g_bit_w_out => 32, + g_bit_w => g_bit_w, + g_values => c_values + ) + PORT MAP( + o_clk => clk, + o_tb_end => tb_end, + o_test_msg => test_msg, + o_test_pass => test_pass + ); + + p_vunit : PROCESS + BEGIN + test_runner_setup(runner, runner_cfg); + wait until tb_end = '1'; + test_runner_cleanup(runner); + wait; + END PROCESS; + + p_verify : PROCESS(clk) + BEGIN + IF rising_edge(clk) THEN + check(test_pass, "Test Failed: " & test_msg); + END IF; + + END PROCESS; +END tb; \ No newline at end of file diff --git a/casper_accumulators/tb_tb_vu_simple_bram_vacc.vhd b/casper_accumulators/tb_tb_vu_simple_bram_vacc.vhd new file mode 100644 index 00000000..433a16c2 --- /dev/null +++ b/casper_accumulators/tb_tb_vu_simple_bram_vacc.vhd @@ -0,0 +1,67 @@ +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +library ieee, common_pkg_lib, vunit_lib; +use IEEE.std_logic_1164.all; +use common_pkg_lib.common_pkg.all; +context vunit_lib.vunit_context; + +entity tb_tb_vu_simple_bram_vacc is + GENERIC( + g_vector_length : NATURAL := 8; + g_bit_w : NATURAL := 8; + g_values : STRING; -- CSV list of naturals + runner_cfg : STRING + ); +end tb_tb_vu_simple_bram_vacc; + +architecture tb of tb_tb_vu_simple_bram_vacc is + + SIGNAL rst : STD_LOGIC := '0'; + SIGNAL clk : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC; + SIGNAL test_msg : STRING(1 to 80); + SIGNAL test_pass : BOOLEAN; + + IMPURE FUNCTION decode(encoded_natural_vector : string) return t_integer_arr is + VARIABLE parts : lines_t := split(encoded_natural_vector, ","); + VARIABLE return_value : t_integer_arr(parts'range); + BEGIN + for i in parts'range loop + return_value(i) := natural'value(parts(i).all); + end loop; + return return_value; + END; + + CONSTANT c_values : t_integer_arr := decode(g_values); +BEGIN + tb_ut : ENTITY work.tb_simple_bram_vacc + GENERIC MAP( + g_vector_length => g_vector_length, + g_bit_w_out => 32, + g_bit_w => g_bit_w, + g_values => c_values + ) + PORT MAP( + o_clk => clk, + o_tb_end => tb_end, + o_test_msg => test_msg, + o_test_pass => test_pass + ); + + p_vunit : PROCESS + BEGIN + test_runner_setup(runner, runner_cfg); + wait until tb_end = '1'; + test_runner_cleanup(runner); + wait; + END PROCESS; + + p_verify : PROCESS(clk) + BEGIN + IF rising_edge(clk) THEN + check(test_pass, "Test Failed: " & test_msg); + END IF; + + END PROCESS; +END tb; \ No newline at end of file diff --git a/casper_adder/common_add_sub.vhd b/casper_adder/common_add_sub.vhd index da0c3a3a..264f8bce 100644 --- a/casper_adder/common_add_sub.vhd +++ b/casper_adder/common_add_sub.vhd @@ -75,8 +75,8 @@ ARCHITECTURE add_sub OF common_add_sub IS CONSTANT c_res_w : NATURAL := g_in_dat_w + 1; - SIGNAL in_a_p : STD_LOGIC_VECTOR(in_a'RANGE); - SIGNAL in_b_p : STD_LOGIC_VECTOR(in_b'RANGE); + SIGNAL in_a_p : STD_LOGIC_VECTOR(in_a'RANGE) := (OTHERS => '0'); + SIGNAL in_b_p : STD_LOGIC_VECTOR(in_b'RANGE) := (OTHERS => '0'); SIGNAL in_add : STD_LOGIC; SIGNAL sel_add_p : STD_LOGIC; diff --git a/casper_adder/run.py b/casper_adder/run.py index c4532b8f..ec9a08d3 100644 --- a/casper_adder/run.py +++ b/casper_adder/run.py @@ -1,86 +1,149 @@ -import os -import random -from itertools import product -from vunit import VUnit - -def generate_tests(obj, direc, add_sub, inp_pipeline, out_pipeline, in_dat_w): - """ - Generate test by varying the generics of casper_adder: - direc : string {SUB,ADD,BOTH} - add_sub : int {0,1} - pipeline_in : int {0,1} - pipeline_out : int {5} - in_dat_w : int {1,5} - out_dat_w : int {in_dat_w,in_dat_w+1} - """ - - for d, a_s, i_pipe, o_pipe, i_d_w in product(direc,add_sub,inp_pipeline,out_pipeline,in_dat_w): - ab_value_ranges = [(0,0,0,0)] # default, exhaustive - if i_d_w > 14: - min_val = -(2**(i_d_w-1)) - max_val = (-min_val)-1 - - ab_value_ranges = [ - (min_val,min_val+128,-16,15), - (-128,+128,-16,15), - (max_val,max_val-128,-16,15) - ] - elif i_d_w > 10: - ab_value_ranges = [(0,0,-16,15)] # default, exhaustive - - for a_v_min, a_v_max, b_v_min, b_v_max in ab_value_ranges: - non_exhaustive_value_range = any([lim != 0 for lim in [a_v_min, a_v_max, b_v_min, b_v_max]]) - value_range_string = ", a_val = [%d, %d] , b_val = [%d, %d]" % ( - a_v_min if a_v_min != 0 else -(2**(i_d_w-1)), - a_v_max if a_v_max != 0 else (2**(i_d_w-1))-1, - b_v_min if b_v_min != 0 else -(2**(i_d_w-1)), - b_v_max if b_v_max != 0 else (2**(i_d_w-1))-1 - ) - - config_name1 = "direc = %s, add_sub = %s, i_pipe = %i, o_pipe = %i, in_dat_w = %i, out_dat_w = %i" % (d, a_s, i_pipe, o_pipe, i_d_w, i_d_w) - if non_exhaustive_value_range: - config_name1 += value_range_string - obj.add_config( - name = config_name1, - generics=dict(g_direction=d,g_sel_add=a_s,g_pipeline_in=i_pipe, g_pipeline_out=o_pipe, g_in_dat_w=i_d_w,g_out_dat_w=i_d_w, - g_a_val_min=a_v_min, g_a_val_max=a_v_max, g_b_val_min=b_v_min, g_b_val_max=b_v_max) - ) - config_name2 = "direc = %s, add_sub = %s, i_pipe = %i, o_pipe = %i, in_dat_w = %i, out_dat_w = %i" % (d, a_s, i_pipe, o_pipe, i_d_w, i_d_w+1) - if non_exhaustive_value_range: - config_name2 += value_range_string - obj.add_config( - name = config_name2, - generics=dict(g_direction=d,g_sel_add=a_s,g_pipeline_in=i_pipe, g_pipeline_out=o_pipe, g_in_dat_w=i_d_w,g_out_dat_w=i_d_w+1, - g_a_val_min=a_v_min, g_a_val_max=a_v_max, g_b_val_min=b_v_min, g_b_val_max=b_v_max) - ) - -vu = VUnit.from_argv() - -script_dir = os.path.dirname(__file__) - -lib1 = vu.add_library("casper_adder_lib",allow_duplicate=True) -lib1.add_source_files(os.path.join(script_dir, "*.vhd")) -TB_GENERATED = lib1.test_bench("tb_tb_vu_common_add_sub") - -direc_values = ['BOTH'] -add_sub_values = [0,1] -inp_pipeline_values = random.sample([0,1], 1) -out_pipeline_values = [0] + random.sample(range(1,5), 1) -in_dat_w_values = [18] + random.sample(range(4, 8), 1) + random.sample(range(9, 17), 1) - -generate_tests(TB_GENERATED, - direc_values, - add_sub_values, - inp_pipeline_values, - out_pipeline_values, - in_dat_w_values -) - -lib2 = vu.add_library("common_components_lib",allow_duplicate=True) -lib2.add_source_files(os.path.join(script_dir, "../common_components/*.vhd")) - -lib3 = vu.add_library("common_pkg_lib",allow_duplicate = True) -lib3.add_source_files(os.path.join(script_dir, "../common_pkg/*.vhd")) - -vu.set_compile_option("ghdl.a_flags", ["-Wno-hide"]) -vu.main() \ No newline at end of file +import os +import random +from itertools import product +from vunit import VUnit + +def generate_tests(obj, direc, add_sub, inp_pipeline, out_pipeline, in_dat_w): + """ + Generate test by varying the generics of casper_adder: + direc : string {SUB,ADD,BOTH} + add_sub : int {0,1} + pipeline_in : int {0,1} + pipeline_out : int {5} + in_dat_w : int {1,5} + out_dat_w : int {in_dat_w,in_dat_w+1} + """ + testnum = 1; + for d, a_s, i_pipe, o_pipe, i_d_w in product(direc,add_sub,inp_pipeline,out_pipeline,in_dat_w): + ab_value_ranges = [(0,0,0,0)] # default, exhaustive + if i_d_w > 14: + min_val = -(2**(i_d_w-1)) + max_val = (-min_val)-1 + + ab_value_ranges = [ + (min_val,min_val+128,-16,15), + (-128,+128,-16,15), + (max_val,max_val-128,-16,15) + ] + elif i_d_w > 10: + ab_value_ranges = [(0,0,-16,15)] # default, exhaustive + + for a_v_min, a_v_max, b_v_min, b_v_max in ab_value_ranges: + non_exhaustive_value_range = any([lim != 0 for lim in [a_v_min, a_v_max, b_v_min, b_v_max]]) + value_range_string = ", a_val = [%d,%d] , b_val = [%d,%d]" % ( + a_v_min if a_v_min != 0 else -(2**(i_d_w-1)), + a_v_max if a_v_max != 0 else (2**(i_d_w-1))-1, + b_v_min if b_v_min != 0 else -(2**(i_d_w-1)), + b_v_max if b_v_max != 0 else (2**(i_d_w-1))-1 + ) + config_name1 = "TestA%d"%(testnum) + #testnum = testnum + 1 + #config_name1 = "direc = %s, add_sub = %s, i_pipe = %i, o_pipe = %i, in_dat_w = %i, out_dat_w = %i" % (d, a_s, i_pipe, o_pipe, i_d_w, i_d_w) + #if non_exhaustive_value_range: + # config_name1 += value_range_string + obj.add_config( + name = config_name1, + generics=dict(g_direction=d,g_sel_add=a_s,g_pipeline_in=i_pipe, g_pipeline_out=o_pipe, g_in_dat_w=i_d_w,g_out_dat_w=i_d_w, + g_a_val_min=a_v_min, g_a_val_max=a_v_max, g_b_val_min=b_v_min, g_b_val_max=b_v_max) + ) + #config_name2 = "direc = %s, add_sub = %s, i_pipe = %i, o_pipe = %i, in_dat_w = %i, out_dat_w = %i" % (d, a_s, i_pipe, o_pipe, i_d_w, i_d_w+1) + #if non_exhaustive_value_range: + # config_name2 += value_range_string + config_name2 = "TestB%d"%(testnum) + testnum = testnum + 1 + obj.add_config( + name = config_name2, + generics=dict(g_direction=d,g_sel_add=a_s,g_pipeline_in=i_pipe, g_pipeline_out=o_pipe, g_in_dat_w=i_d_w,g_out_dat_w=i_d_w+1, + g_a_val_min=a_v_min, g_a_val_max=a_v_max, g_b_val_min=b_v_min, g_b_val_max=b_v_max) + ) + +vu = VUnit.from_argv() +vu.add_vhdl_builtins() +script_dir = os.path.dirname(__file__) + +lib1 = vu.add_library("casper_adder_lib",allow_duplicate=True) +lib1.add_source_files(os.path.join(script_dir, "*.vhd")) +TB_GENERATED = lib1.test_bench("tb_tb_vu_common_add_sub") + +direc_values = ['BOTH'] +add_sub_values = [0,1] +inp_pipeline_values = random.sample([0,1], 1) +out_pipeline_values = [0] + random.sample(range(1,5), 1) +in_dat_w_values = [18] + random.sample(range(4, 8), 1) + random.sample(range(9, 17), 1) + +generate_tests(TB_GENERATED, + direc_values, + add_sub_values, + inp_pipeline_values, + out_pipeline_values, + in_dat_w_values +) + +lib2 = vu.add_library("common_components_lib",allow_duplicate=True) +lib2.add_source_files(os.path.join(script_dir, "../common_components/*.vhd")) + +# XPM Library compile +lib_xpm = vu.add_library("xpm") +lib_xpm.add_source_files(os.path.join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_VCOMP.vhd")) +xpm_source_file_base = lib_xpm.add_source_file(os.path.join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_base.vhd")) +xpm_source_file_sdpram = lib_xpm.add_source_file(os.path.join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_sdpram.vhd")) +xpm_source_file_tdpram = lib_xpm.add_source_file(os.path.join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_tdpram.vhd")) +xpm_source_file_tdpram = lib_xpm.add_source_file(os.path.join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_sprom.vhd")) +xpm_source_file_tdpram = lib_xpm.add_source_file(os.path.join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_dprom.vhd")) +xpm_source_file_sdpram.add_dependency_on(xpm_source_file_base) +xpm_source_file_tdpram.add_dependency_on(xpm_source_file_base) + +# Altera_mf library +lib_altera_mf = vu.add_library("altera_mf") +lib_altera_mf.add_source_file(os.path.join(script_dir, "../intel/altera_mf/altera_mf_components.vhd")) +altera_mf_source_file = lib_altera_mf.add_source_file(os.path.join(script_dir, "../intel/altera_mf/altera_mf.vhd")) + +# STRATIXIV RAM Library +ip_stratixiv_ram_lib = vu.add_library("ip_stratixiv_ram_lib") +ip_stratix_file_cr_cw = ip_stratixiv_ram_lib.add_source_file(os.path.join(script_dir, "../ip_stratixiv/ram/ip_stratixiv_ram_cr_cw.vhd")) +ip_stratix_file_crw_crw = ip_stratixiv_ram_lib.add_source_file(os.path.join(script_dir, "../ip_stratixiv/ram/ip_stratixiv_ram_crw_crw.vhd")) +ip_stratix_file_cr_cw.add_dependency_on(altera_mf_source_file) +ip_stratix_file_crw_crw.add_dependency_on(altera_mf_source_file) + +ip_xpm_ram_lib = vu.add_library("ip_xpm_ram_lib") +ip_xpm_file_cr_cw = ip_xpm_ram_lib.add_source_files(os.path.join(script_dir, "../ip_xpm/ram/ip_xpm_ram_cr_cw.vhd")) +ip_xpm_file_cr_cw.add_dependency_on(xpm_source_file_sdpram) +ip_xpm_file_crw_crw = ip_xpm_ram_lib.add_source_files(os.path.join(script_dir, "../ip_xpm/ram/ip_xpm_ram_crw_crw.vhd")) +ip_xpm_file_crw_crw.add_dependency_on(xpm_source_file_tdpram) +ip_xpm_file_crw_crw = ip_xpm_ram_lib.add_source_files(os.path.join(script_dir, "../ip_xpm/ram/ip_xpm_rom_r_r.vhd")) +ip_xpm_file_crw_crw.add_dependency_on(xpm_source_file_tdpram) + +# TECHNOLOGY Library +technology_lib = vu.add_library("technology_lib") +technology_lib.add_source_files(os.path.join(script_dir, "../technology/technology_select_pkg.vhd")) + +casper_ram_lib = vu.add_library("casper_ram_lib") +casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_ram_pkg.vhd")) +casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/tech_memory_component_pkg.vhd")) +casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/tech_memory_ram_crw_crw.vhd")) +casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/tech_memory_ram_cr_cw.vhd")) +casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/tech_memory_rom_r.vhd")) +casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/tech_memory_rom_r_r.vhd")) +casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_ram_crw_crw.vhd")) +casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_ram_rw_rw.vhd")) +casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_rom_r_r.vhd")) +casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_ram_r_w.vhd")) +casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_paged_ram_r_w.vhd")) +casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_paged_ram_rw_rw.vhd")) +casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_paged_ram_crw_crw.vhd")) + +lib3 = vu.add_library("common_pkg_lib",allow_duplicate = True) +lib3.add_source_files(os.path.join(script_dir, "../common_pkg/fixed_float_types_c.vhd")) +lib3.add_source_files(os.path.join(script_dir, "../common_pkg/fixed_pkg_c.vhd")) +lib3.add_source_files(os.path.join(script_dir, "../common_pkg/float_pkg_c.vhd")) +lib3.add_source_files(os.path.join(script_dir, "../common_pkg/*.vhd")) + + + + +vu.set_compile_option("ghdl.a_flags", ["-frelaxed","-fsynopsys","-fexplicit","-Wno-hide"]) +#vu.set_sim_option("ghdl.elab_e", True) +vu.set_sim_option("ghdl.elab_flags", ["-frelaxed","-fsynopsys","-fexplicit","--syn-binding"]) +vu.set_sim_option("ghdl.sim_flags",["--max-stack-alloc=4096"]) + +vu.main() diff --git a/casper_bus/bus_accumulator.vhd b/casper_bus/bus_accumulator.vhd new file mode 100644 index 00000000..7a0c04d4 --- /dev/null +++ b/casper_bus/bus_accumulator.vhd @@ -0,0 +1,71 @@ +-- A VHDL implementation of the CASPER bus_accumulator block. +-- @author: Ross Donnachie +-- @company: Mydon Solutions + +LIBRARY IEEE, common_pkg_lib, casper_accumulators_lib; +USE IEEE.std_logic_1164.all; +USE common_pkg_lib.common_pkg.all; + +ENTITY bus_accumulator is + generic ( + g_data_type : string := "SIGNED"; -- or "UNSIGNED" + g_bus_constituent_widths : t_nat_natural_arr; + g_bus_constituent_expansion_widths : t_nat_natural_arr + ); + port ( + clk : in std_logic := '1'; + ce : in std_logic := '1'; + + rst : in std_logic_vector; + en : in std_logic_vector; + + din : in std_logic_vector; + dout : out std_logic_vector + ); +end ENTITY; + +ARCHITECTURE rtl of bus_accumulator is + alias din_v : STD_LOGIC_VECTOR (func_sum(g_bus_constituent_widths)-1 downto 0) is din; + alias dout_v : STD_LOGIC_VECTOR (func_sum(g_bus_constituent_expansion_widths)-1 downto 0) is dout; + +begin + assert not din'ascending; -- assumes downto + + ASSERT rst'left = en'left; + ASSERT rst'right = en'right; + ASSERT not rst'ascending; + + ASSERT rst'length = g_bus_constituent_widths'length; + ASSERT g_bus_constituent_widths'ascending; + ASSERT g_bus_constituent_widths'left = g_bus_constituent_expansion_widths'left; + ASSERT g_bus_constituent_widths'right = g_bus_constituent_expansion_widths'right; + + ASSERT din'length = func_sum(g_bus_constituent_widths); + ASSERT dout'length = func_sum(g_bus_constituent_expansion_widths); + + g_expand : FOR I IN g_bus_constituent_widths'RANGE GENERATE + CONSTANT c_preceding_index : natural := din'length-func_sum( + g_bus_constituent_widths(g_bus_constituent_widths'left to I-1) + ); + CONSTANT c_preceding_expansion_index : natural := dout'length-func_sum( + g_bus_constituent_expansion_widths(g_bus_constituent_expansion_widths'left to I-1) + ); + CONSTANT c_descending_index : natural := rst'left - (I - g_bus_constituent_widths'left); + begin + ASSERT g_bus_constituent_widths(I) <= g_bus_constituent_expansion_widths(I); + + u_acc : ENTITY casper_accumulators_lib.simple_accumulator + GENERIC MAP ( + g_representation => g_data_type + ) + port map ( + clk => clk, + ce => ce, + rst => rst(c_descending_index), + in_b => din(c_preceding_index-1 downto c_preceding_index-g_bus_constituent_widths(I)), + -- valid + result => dout(c_preceding_expansion_index-1 downto c_preceding_expansion_index-g_bus_constituent_expansion_widths(I)) + ); + end GENERATE; + +end ARCHITECTURE; diff --git a/casper_bus/bus_accumulator_stringgenerics.vhd b/casper_bus/bus_accumulator_stringgenerics.vhd new file mode 100644 index 00000000..9f5510b1 --- /dev/null +++ b/casper_bus/bus_accumulator_stringgenerics.vhd @@ -0,0 +1,59 @@ +-- A VHDL implementation of the CASPER bus_accumulator block. +-- @author: Ross Donnachie +-- @company: Mydon Solutions + +LIBRARY IEEE, common_pkg_lib; +USE IEEE.std_logic_1164.all; +USE common_pkg_lib.common_pkg.all; + +ENTITY bus_accumulator_stringgenerics is + generic ( + g_data_type : string := "SIGNED"; -- or "UNSIGNED" + g_bus_constituent_widths : string; + g_bus_constituent_expansion_widths : string + ); + port ( + clk : in std_logic := '1'; + ce : in std_logic := '1'; + + rst : in std_logic_vector; + en : in std_logic_vector; + + din : in std_logic_vector; + dout : out std_logic_vector + ); +end ENTITY; + +ARCHITECTURE rtl of bus_accumulator_stringgenerics is + + impure function decode(encoded_natural_vector : string) return t_natural_arr is + variable parts : lines_t := split(encoded_natural_vector, ","); + variable return_value : t_natural_arr(parts'range); + begin + for i in parts'range loop + return_value(i) := natural'value(parts(i).all); + end loop; + + return return_value; + end; + + CONSTANT c_bus_constituent_widths : t_natural_arr := decode(g_bus_constituent_widths); + CONSTANT c_bus_constituent_expansion_widths : t_natural_arr := decode(g_bus_constituent_expansion_widths); +begin + u_bu : ENTITY work.bus_accumulator + generic map( + g_data_type => g_data_type, + g_bus_constituent_widths => c_bus_constituent_widths, + g_bus_constituent_expansion_widths => c_bus_constituent_expansion_widths + ) + port map ( + clk => clk, + ce => ce, + + rst => rst, + en => en, + + din => din, + dout=> dout + ); +end ARCHITECTURE; diff --git a/casper_bus/bus_dual_port_ram.vhd.proto b/casper_bus/bus_dual_port_ram.vhd.proto new file mode 100644 index 00000000..9362b26b --- /dev/null +++ b/casper_bus/bus_dual_port_ram.vhd.proto @@ -0,0 +1,46 @@ +-- A VHDL implementation of the CASPER bus_dual_port_ram block. +-- @author: Ross Donnachie. +-- @company: Mydon Solutions. + +LIBRARY IEEE, common_pkg_lib, casper_delay_lib, casper_ram_lib; +USE IEEE.std_logic_1164.all; +USE common_pkg_lib.common_pkg.all; +USE casper_ram_lib.common_ram_pkg.all; + +ENTITY bus_dual_port_ram is + generic ( + g_depth : NATURAL := 3; + g_ram_latency: NATURAL := 2 + ); + port ( + clk : in std_logic; + ce : in std_logic; + i_addr_a : in std_logic_vector; + i_data : in std_logic_vector; + i_wea : in std_logic; + i_addr_b : in std_logic_vector; + o_data_a : out std_logic_vector; + o_data_b : out std_logic_vector + ); +end ENTITY; + +ARCHITECTURE rtl of bus_dual_port_ram is +BEGIN +u_bram0 : ENTITY casper_ram_lib.common_ram_r_w + GENERIC MAP ( + g_ram => c_mem_ram, + g_true_dual_port => FALSE, + g_ram_primitive => "block" + ) + PORT MAP( + clk => clk, + clken => ce, + wr_en => s_bram0_we_vector(0), + wr_adr => s_bram0_addr, + wr_dat => s_data_delayed, + rd_en => '0', + rd_adr => s_bram0_addr, + rd_dat => s_bram0_data, + rd_val => open + ); +end ARCHITECTURE; \ No newline at end of file diff --git a/casper_bus/bus_fill_slv_arr.vhd b/casper_bus/bus_fill_slv_arr.vhd new file mode 100644 index 00000000..5d485dc4 --- /dev/null +++ b/casper_bus/bus_fill_slv_arr.vhd @@ -0,0 +1,50 @@ +-- @author: Ross Donnachie +-- @company: Mydon Solutions + +LIBRARY IEEE, common_slv_arr_pkg_lib, casper_delay_lib; +USE IEEE.std_logic_1164.all; +USE common_slv_arr_pkg_lib.common_slv_arr_pkg.all; + +ENTITY bus_fill_slv_arr is + generic ( + g_latency : NATURAL + ); + port ( + clk : in std_logic := '1'; + ce : in std_logic := '1'; + + i_data : in std_logic_vector; + o_data : out t_slv_arr + ); +end ENTITY; + +ARCHITECTURE rtl of bus_fill_slv_arr is + SIGNAL s_in : t_slv_arr(o_data'RANGE(1), i_data'RANGE); +begin + o_data <= s_in; + + g_concat : FOR I IN s_in'RANGE(1) GENERATE + SIGNAL s_in_i : std_logic_vector(s_in'RANGE(2)); + begin + g_delay : IF g_latency > 0 GENERATE + u_data_delay : entity casper_delay_lib.delay_simple + generic map ( + g_delay => g_latency + ) + port map ( + clk => clk, + ce => ce, + i_data => i_data, + o_data => s_in_i + ); + end GENERATE; + g_no_delay : IF g_latency = 0 GENERATE + s_in_i <= i_data; + end GENERATE; + + g_concat_bits : FOR bit_i IN s_in_i'RANGE GENERATE + s_in(i, bit_i) <= s_in_i(bit_i); + end GENERATE; + end GENERATE; + +end ARCHITECTURE; diff --git a/casper_bus/bus_mux.vhd b/casper_bus/bus_mux.vhd new file mode 100644 index 00000000..b14fe4d3 --- /dev/null +++ b/casper_bus/bus_mux.vhd @@ -0,0 +1,50 @@ +-- A VHDL implementation of the CASPER bus_mux block. +-- @author: Ross Donnachie +-- @company: Mydon Solutions + +LIBRARY IEEE, common_pkg_lib, common_slv_arr_pkg_lib, casper_delay_lib; +USE IEEE.std_logic_1164.all; +USE common_pkg_lib.common_pkg.all; +USE common_slv_arr_pkg_lib.common_slv_arr_pkg.all; + +entity bus_mux is + generic ( + g_delay : NATURAL := 1 + ); + port ( + clk : IN std_logic; + ce : IN std_logic; + i_sel : IN std_logic_vector; -- 'HIGH=MSB, 'LOW=LSB, regardless of direction (downto=LE, to=BE) + i_data : IN t_slv_arr; + o_data : OUT std_logic_vector + ); +end bus_mux; + +architecture rtl of bus_mux is + SIGNAL s_data_selected : std_logic_vector(i_data'range(2)); + SIGNAL s_sel : NATURAL RANGE i_data'range(1); +begin + + s_sel <= TO_UINT(i_sel); + + g_bits_selection : FOR bit_index in i_data'range(2) GENERATE + s_data_selected(bit_index) <= i_data(s_sel, bit_index); + END GENERATE; + + g_comb : IF g_delay = 0 GENERATE + o_data <= s_data_selected; + END GENERATE; + + g_delayed : IF g_delay /= 0 GENERATE + u_data_delay : entity casper_delay_lib.delay_simple + generic map ( + g_delay => g_delay + ) + port map ( + clk => clk, + ce => ce, + i_data => s_data_selected, + o_data => o_data + ); + END GENERATE; +end architecture; \ No newline at end of file diff --git a/casper_bus/bus_replicate.vhd b/casper_bus/bus_replicate.vhd new file mode 100644 index 00000000..fa42ba2e --- /dev/null +++ b/casper_bus/bus_replicate.vhd @@ -0,0 +1,46 @@ +-- A VHDL implementation of the CASPER bus_replicate block. +-- @author: Ross Donnachie +-- @company: Mydon Solutions + +LIBRARY IEEE, common_slv_arr_pkg_lib, casper_flow_control_lib; +USE IEEE.std_logic_1164.all; +USE common_slv_arr_pkg_lib.common_slv_arr_pkg.all; + +ENTITY bus_replicate is + generic ( + g_replication_factor : NATURAL; + g_latency : NATURAL + ); + port ( + clk : in std_logic := '1'; + ce : in std_logic := '1'; + + i_data : in std_logic_vector; + o_data : out std_logic_vector + ); +end ENTITY; + +ARCHITECTURE rtl of bus_replicate is + SIGNAL s_in : t_slv_arr(0 to g_replication_factor-1, i_data'RANGE); +begin + u_bus_fill_slv_arr : entity work.bus_fill_slv_arr + generic map ( + g_latency => g_latency + ) + port map ( + clk => clk, + ce => ce, + + i_data => i_data, + o_data => s_in + ); + + u_bus_create : entity casper_flow_control_lib.bus_create + port map ( + clk => clk, + ce => ce, + din => s_in, + dout => o_data + ); + +end ARCHITECTURE; diff --git a/casper_bus/run.py b/casper_bus/run.py new file mode 100644 index 00000000..2407d95b --- /dev/null +++ b/casper_bus/run.py @@ -0,0 +1,71 @@ +from vunit import VUnit +from os.path import dirname, join +import random + +# Create VUnit instance by parsing command line arguments +vu = VUnit.from_argv() +vu.add_vhdl_builtins() +script_dir = dirname(__file__) + +# Create library 'common_pkg_lib' +common_pkg_lib = vu.add_library("common_pkg_lib") +common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/fixed_float_types_c.vhd")) +common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/fixed_pkg_c.vhd")) +common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/float_pkg_c.vhd")) +common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/common_pkg.vhd")) + +# Create library 'common_slv_arr_pkg_lib' +common_slv_arr_pkg_lib = vu.add_library("common_slv_arr_pkg_lib") +common_slv_arr_pkg_lib.add_source_files(join(script_dir, "../common_slv_arr_pkg/common_slv_arr_pkg.vhd")) + +# Create library 'casper_delay_lib' +casper_delay_lib = vu.add_library("casper_delay_lib") +casper_delay_lib.add_source_files(join(script_dir, "../casper_delay/delay_simple.vhd")) +casper_delay_lib.add_source_files(join(script_dir, "../casper_delay/delay_bram_en_plus.vhd")) + +# Create library 'casper_accumulators_lib' +casper_accumulators_lib = vu.add_library("casper_accumulators_lib") +casper_accumulators_lib.add_source_files(join(script_dir, "../casper_accumulators/simple_accumulator.vhd")) + + +# CASPER BUS Library +casper_bus_lib = vu.add_library("casper_bus_lib") +casper_bus_lib.add_source_file(join(script_dir, "../casper_bus/*.vhd")) + +TB_BUS_MUX = casper_bus_lib.test_bench("tb_tb_vu_bus_mux") +for delays in [0,1,2]: + for input_count in [2,3,6]: + for input_width in [4,8]: + TB_BUS_MUX.add_config( + name = f"Mux ({input_count} inputs of {input_width} bits)", + generics={ + "g_delay": delays, + "g_nof_inputs": input_count, + "g_bit_width": input_width + } + ) + +TB_BUS_ACC = casper_bus_lib.test_bench("tb_tb_vu_bus_accumulator") +TB_BUS_ACC.add_config( + name = f"Bus Accumulator", + generics={} +) + +vu.set_compile_option("ghdl.a_flags", ["-Wno-hide", "-frelaxed","-fsynopsys","-fexplicit"]) +vu.set_sim_option("ghdl.elab_flags", ["-frelaxed","-fsynopsys","-fexplicit","--syn-binding"]) +vu.set_sim_option("ghdl.sim_flags", ["--ieee-asserts=disable"]) +# vu.set_sim_option("modelsim.vsim_flags.gui",["-voptargs=+acc"]) + +# simulator_if = vu._create_simulator_if() +# test_list = vu._create_tests(simulator_if) +# vu._get_testbench_files(simulator_if) + +# print() + +# for source in vu.get_compile_order(): +# print(source._source_file.compile_options) +# filename = source._source_file.name +# libraryname = source._source_file.library.name +# break + +vu.main() diff --git a/casper_bus/tb_bus_accumulator.vhd b/casper_bus/tb_bus_accumulator.vhd new file mode 100644 index 00000000..0c62f1e1 --- /dev/null +++ b/casper_bus/tb_bus_accumulator.vhd @@ -0,0 +1,125 @@ +-- A VHDL implementation of the CASPER bus_accumulator block. +-- @author: Ross Donnachie +-- @company: Mydon Solutions + +LIBRARY IEEE, common_pkg_lib, casper_delay_lib; +USE IEEE.std_logic_1164.all; +use IEEE.NUMERIC_STD.ALL; +USE common_pkg_lib.common_pkg.all; + +ENTITY tb_bus_accumulator is + generic ( + g_bus_constituent_widths : t_nat_natural_arr := (6, 4, 8); + g_bus_constituent_expansion_widths : t_nat_natural_arr := (8, 8, 8); + g_accumulations_to_test : natural := 10 + ); + port ( + o_clk : out std_logic; + o_tb_end : out std_logic; + o_test_msg : out STRING(1 to 80); + o_test_pass : out BOOLEAN + ); +end ENTITY; + +architecture tb of tb_bus_accumulator is + CONSTANT clk_period : TIME := 10 ns; + + SIGNAL clk : std_logic := '1'; + SIGNAL ce : std_logic := '1'; + SIGNAL tb_end : STD_LOGIC := '0'; + + CONSTANT c_nof_elements : natural := g_bus_constituent_widths'length; + signal s_rst : std_logic_vector(c_nof_elements-1 downto 0); + signal s_en : std_logic_vector(c_nof_elements-1 downto 0); + + signal s_din : std_logic_vector(func_sum(g_bus_constituent_widths)-1 downto 0); + signal s_dout : std_logic_vector(func_sum(g_bus_constituent_expansion_widths)-1 downto 0); + + + alias a_g_bus_constituent_widths : t_nat_natural_arr (0 to g_bus_constituent_widths'length-1) is g_bus_constituent_widths; + alias a_g_bus_constituent_expansion_widths : t_nat_natural_arr (0 to g_bus_constituent_expansion_widths'length-1) is g_bus_constituent_expansion_widths; +BEGIN + + clk <= NOT clk OR tb_end AFTER clk_period / 2; + + o_clk <= clk; + o_tb_end <= tb_end; + + u_dut : ENTITY work.bus_accumulator + generic map ( + g_bus_constituent_widths => g_bus_constituent_widths, + g_bus_constituent_expansion_widths => g_bus_constituent_expansion_widths + ) + port map( + clk => clk, + ce => ce, + + rst => s_rst, + en => s_en, + + -- misci => + -- misco => + + din => s_din, + dout => s_dout + ); + + p_stim: process + variable v_din_index, v_dout_index: integer; + VARIABLE v_test_pass : BOOLEAN := TRUE; + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + begin + -- assign bus elements with values equal to index + v_din_index := s_din'length; + for I in a_g_bus_constituent_widths'range loop + s_din( + v_din_index-1 downto v_din_index-a_g_bus_constituent_widths(I) + ) <= std_logic_vector(to_unsigned(I, a_g_bus_constituent_widths(I))); + + v_din_index := v_din_index - a_g_bus_constituent_widths(I); -- din'descending + end loop; + + s_rst <= (others => '1'); + s_en <= (others => '0'); + + wait until rising_edge(clk); + + for r in 1 to 3 loop + -- test reset + s_en <= (others => '1'); + s_rst <= (others => '1'); + wait for 3*clk_period; + + -- test accumulation + s_rst <= (others => '0'); + wait for 1*clk_period; + + for t in 1 to g_accumulations_to_test loop + wait for 1*clk_period; + + -- test each dout element + v_dout_index := s_dout'length; + for I in a_g_bus_constituent_expansion_widths'range loop + if t*I /= unsigned(s_dout( + v_dout_index-1 downto v_dout_index-a_g_bus_constituent_expansion_widths(I) + )) then + v_test_msg := pad("Accumulation #"& integer'image(t) &" failed at index "& integer'image(I) &". Expected: " & integer'image(I*t) &" but got: " & integer'image(to_integer(unsigned(s_dout( + v_dout_index-1 downto v_dout_index-a_g_bus_constituent_expansion_widths(I) + )))), o_test_msg'length, '.'); + v_test_pass := FALSE; + REPORT v_test_msg severity failure; + end if; + o_test_msg <= v_test_msg; + o_test_pass <= v_test_pass; + + v_dout_index := v_dout_index - a_g_bus_constituent_expansion_widths(I); -- dout'descending + end loop; + end loop; + end loop; + + tb_end <= '1'; + wait; + end process; + + +end architecture; \ No newline at end of file diff --git a/casper_bus/tb_bus_mux.vhd b/casper_bus/tb_bus_mux.vhd new file mode 100644 index 00000000..11e0a4e0 --- /dev/null +++ b/casper_bus/tb_bus_mux.vhd @@ -0,0 +1,139 @@ +-- A VHDL testbench for the simple delay block. +-- @author: Ross Donnachie +-- @company: Mydon Solutions + +LIBRARY IEEE, common_pkg_lib, common_slv_arr_pkg_lib, casper_delay_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.all; +USE common_slv_arr_pkg_lib.common_slv_arr_pkg.all; +USE STD.TEXTIO.ALL; + +entity tb_bus_mux is + generic ( + g_delay : NATURAL := 3; + g_nof_inputs : NATURAL := 4; + g_bit_width : NATURAL := 4 + ); + port ( + o_clk : out std_logic; + o_tb_end : out std_logic; + o_test_msg : out STRING(1 to 80); + o_test_pass : out BOOLEAN + ); +end tb_bus_mux; + +architecture rtl of tb_bus_mux is + CONSTANT clk_period : TIME := 10 ns; + + SIGNAL clk : std_logic := '0'; + SIGNAL ce : std_logic; + SIGNAL tb_end : STD_LOGIC := '0'; + + SIGNAL s_sel : std_logic_vector(ceil_log2(g_nof_inputs)-1 downto 0); + SIGNAL s_idata : t_slv_arr( + 0 to g_nof_inputs-1, + g_bit_width-1 downto 0 + ) := (OTHERS => (OTHERS => 'Z')); + SIGNAL s_odata, s_exp, s_exp_delayed : std_logic_vector(g_bit_width-1 downto 0); +begin + clk <= NOT clk OR tb_end AFTER clk_period / 2; + + o_clk <= clk; + o_tb_end <= tb_end; + + u_bus_mux : entity work.bus_mux + generic map ( + g_delay => g_delay + ) + port map ( + clk => clk, + ce => ce, + i_sel => s_sel, + i_data => s_idata, + o_data => s_odata + ); + + u_delay_exp : entity casper_delay_lib.delay_simple + generic map ( + g_delay => g_delay + ) + port map ( + clk => clk, + ce => ce, + i_data => s_exp, + o_data => s_exp_delayed + ); + + p_stimuli : PROCESS + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + VARIABLE v_test_pass : BOOLEAN := TRUE; + VARIABLE v_count: UNSIGNED(g_bit_width-1 downto 0) := to_unsigned(0, g_bit_width); + VARIABLE v_value : STD_LOGIC_VECTOR(g_bit_width-1 downto 0); + BEGIN + -- set inputs + -- index 0 will be time-variant, `v_count` + FOR channel IN s_idata'range(1) LOOP + v_value := STD_LOGIC_VECTOR(TO_UNSIGNED( + channel, + g_bit_width + )); + slv_arr_set_variable( + s_idata, + channel, + v_value + ); + END LOOP; + s_exp <= (OTHERS => '0'); + + WAIT FOR clk_period; + WAIT UNTIL falling_edge(clk); + ce <= '1'; + WAIT FOR clk_period; + WAIT UNTIL rising_edge(clk); + + FOR i IN 0 to (2*g_nof_inputs) - 1 LOOP + -- change s_sel and update s_exp + s_sel <= TO_SVEC(i mod g_nof_inputs, s_sel'LENGTH); + IF i mod g_nof_inputs = 0 THEN + s_exp <= STD_LOGIC_VECTOR(v_count); + ELSE + s_exp <= STD_LOGIC_VECTOR(TO_UNSIGNED(i mod g_nof_inputs, s_exp'LENGTH)); + END IF; + + FOR r IN 0 to 2 LOOP + slv_arr_set_variable( + s_idata, + 0, + STD_LOGIC_VECTOR(v_count) + ); + -- s + WAIT FOR clk_period; + + v_count := v_count + 1; + IF i mod g_nof_inputs = 0 THEN + s_exp <= STD_LOGIC_VECTOR(v_count); + END IF; + END LOOP; + END LOOP; + + WAIT for clk_period * 2; + tb_end <= '1'; + WAIT; + END PROCESS; + + p_verify : PROCESS(clk) + VARIABLE v_test_pass : BOOLEAN := TRUE; + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + BEGIN + + v_test_pass := s_odata = s_exp_delayed; + if not v_test_pass then + v_test_msg := pad("Mux failed. Expected: " & to_hstring(s_exp_delayed) & " but got: " & to_hstring(s_odata), o_test_msg'length, '.'); + REPORT v_test_msg severity failure; + end if; + o_test_msg <= v_test_msg; + o_test_pass <= v_test_pass; + END PROCESS; + +end architecture; \ No newline at end of file diff --git a/casper_bus/tb_tb_vu_bus_accumulator.vhd b/casper_bus/tb_tb_vu_bus_accumulator.vhd new file mode 100644 index 00000000..a1b8bbc7 --- /dev/null +++ b/casper_bus/tb_tb_vu_bus_accumulator.vhd @@ -0,0 +1,62 @@ +LIBRARY IEEE, common_pkg_lib, vunit_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +context vunit_lib.vunit_context; + +ENTITY tb_tb_vu_bus_accumulator IS + GENERIC( + g_bus_constituent_widths : t_nat_natural_arr := (6, 4, 8); + g_bus_constituent_expansion_widths : t_nat_natural_arr := (8, 8, 8); + g_accumulations_to_test : natural := 10; + runner_cfg : string + ); +END tb_tb_vu_bus_accumulator; + +ARCHITECTURE tb OF tb_tb_vu_bus_accumulator IS + + SIGNAL rst : STD_LOGIC; + SIGNAL clk : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC; + SIGNAL test_msg : STRING(1 to 80); + SIGNAL test_pass : BOOLEAN; + + SIGNAL s_test_count : natural := 0; +BEGIN + + tb_ut : ENTITY work.tb_bus_accumulator + GENERIC MAP( + g_bus_constituent_widths => g_bus_constituent_widths, + g_bus_constituent_expansion_widths=> g_bus_constituent_expansion_widths, + g_accumulations_to_test => g_accumulations_to_test + ) + PORT MAP( + o_clk => clk, + o_tb_end => tb_end, + o_test_msg => test_msg, + o_test_pass => test_pass + ); + + p_vunit : PROCESS + BEGIN + test_runner_setup(runner, runner_cfg); + wait until tb_end = '1'; + test_runner_cleanup(runner); + wait; + END PROCESS; + + + p_verify : PROCESS(rst, clk) + BEGIN + IF rst = '0' THEN + IF rising_edge(clk) THEN + check(test_pass, "Test Failed: " & test_msg); + IF tb_end THEN + report "Tests completed: " & integer'image(s_test_count+1); + END IF; + s_test_count <= 1; + END IF; + END IF; + + END PROCESS; +END tb; diff --git a/casper_bus/tb_tb_vu_bus_mux.vhd b/casper_bus/tb_tb_vu_bus_mux.vhd new file mode 100644 index 00000000..aa2ad224 --- /dev/null +++ b/casper_bus/tb_tb_vu_bus_mux.vhd @@ -0,0 +1,62 @@ +LIBRARY IEEE, common_pkg_lib, vunit_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +context vunit_lib.vunit_context; + +ENTITY tb_tb_vu_bus_mux IS + GENERIC( + g_delay : NATURAL := 6; + g_nof_inputs : NATURAL := 4; + g_bit_width : NATURAL := 4; + runner_cfg : string + ); +END tb_tb_vu_bus_mux; + +ARCHITECTURE tb OF tb_tb_vu_bus_mux IS + + SIGNAL rst : STD_LOGIC; + SIGNAL clk : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC; + SIGNAL test_msg : STRING(1 to 80); + SIGNAL test_pass : BOOLEAN; + + SIGNAL s_test_count : natural := 0; +BEGIN + + tb_ut : ENTITY work.tb_bus_mux + GENERIC MAP( + g_delay => g_delay, + g_nof_inputs=> g_nof_inputs, + g_bit_width => g_bit_width + ) + PORT MAP( + o_clk => clk, + o_tb_end => tb_end, + o_test_msg => test_msg, + o_test_pass => test_pass + ); + + p_vunit : PROCESS + BEGIN + test_runner_setup(runner, runner_cfg); + wait until tb_end = '1'; + test_runner_cleanup(runner); + wait; + END PROCESS; + + + p_verify : PROCESS(rst, clk) + BEGIN + IF rst = '0' THEN + IF rising_edge(clk) THEN + check(test_pass, "Test Failed: " & test_msg); + IF tb_end THEN + report "Tests completed: " & integer'image(s_test_count+1); + END IF; + s_test_count <= 1; + END IF; + END IF; + + END PROCESS; +END tb; diff --git a/casper_correlator/correlator_pkg.vhd b/casper_correlator/correlator_pkg.vhd new file mode 100644 index 00000000..c46d9af0 --- /dev/null +++ b/casper_correlator/correlator_pkg.vhd @@ -0,0 +1,50 @@ +library ieee; +use ieee.std_logic_1164.all; + +package correlator_pkg is + + CONSTANT c_cross_mult_nof_input_streams : NATURAL := 12; + CONSTANT c_cross_mult_aggregation_per_stream : NATURAL := 3; + CONSTANT c_cross_mult_input_bit_width : NATURAL := 5; + CONSTANT c_cross_mult_output_bit_width : NATURAL := 11; + + CONSTANT c_cross_mult_input_cbit_width : NATURAL := c_cross_mult_input_bit_width * 2; --COMPLEX + CONSTANT c_cross_mult_output_cbit_width : NATURAL := c_cross_mult_output_bit_width * 2; --COMPLEX + CONSTANT c_cross_mult_total_streams : NATURAL := c_cross_mult_nof_input_streams * c_cross_mult_aggregation_per_stream; + CONSTANT c_cross_mult_nof_output_streams :NATURAL := (c_cross_mult_nof_input_streams+1)*c_cross_mult_nof_input_streams / 2; + CONSTANT c_cross_mult_nof_cmults : NATURAL := c_cross_mult_nof_output_streams * c_cross_mult_aggregation_per_stream; + + TYPE s_cross_mult_din is ARRAY (0 TO c_cross_mult_nof_input_streams - 1) OF std_logic_vector((c_cross_mult_aggregation_per_stream * c_cross_mult_input_cbit_width) - 1 downto 0); + TYPE s_cross_mult_out_bus_expand is ARRAY (0 TO (c_cross_mult_total_streams) - 1) OF std_logic_vector(c_cross_mult_input_cbit_width - 1 downto 0); + TYPE s_cross_mult_cmult_in is ARRAY(0 TO (c_cross_mult_nof_cmults - 1)) OF std_logic_vector(c_cross_mult_input_cbit_width - 1 downto 0); + TYPE s_cross_mult_out is ARRAY (0 TO c_cross_mult_nof_output_streams - 1) OF std_logic_vector((c_cross_mult_aggregation_per_stream * c_cross_mult_output_cbit_width) - 1 downto 0); + TYPE s_cross_mult_cmult_out is ARRAY (0 TO c_cross_mult_nof_cmults - 1) OF std_logic_vector(c_cross_mult_output_cbit_width - 1 DOWNTO 0); + TYPE s_cmult_inpt is ARRAY(0 TO 1) OF INTEGER RANGE 0 TO c_cross_mult_total_streams - 1; + TYPE s_cmult_map is ARRAY(0 TO c_cross_mult_nof_cmults - 1) OF s_cmult_inpt; + + FUNCTION gen_inpt_to_mult_mapping(nof_aggregation : NATURAL; nof_streams : NATURAL) return s_cmult_map; + +end package correlator_pkg; + +package body correlator_pkg is + +function gen_inpt_to_mult_mapping(nof_aggregation : NATURAL; nof_streams : NATURAL) + return s_cmult_map is + variable mapping : s_cmult_map; + variable mult : INTEGER := 0; + variable aa : INTEGER := 0; + begin + mult := 0; + FOR a IN 0 TO nof_aggregation - 1 LOOP + aa := a * nof_streams; + FOR s IN aa TO (aa + nof_streams - 1) LOOP + FOR ss IN s TO (aa + nof_streams - 1) LOOP + mapping(mult) := (s, ss); + mult := mult + 1; + END LOOP; + END LOOP; + END LOOP; + return mapping; + end function gen_inpt_to_mult_mapping; + +end package body correlator_pkg; diff --git a/casper_correlator/cross_multiplier.vhd b/casper_correlator/cross_multiplier.vhd new file mode 100644 index 00000000..1b8e0b2f --- /dev/null +++ b/casper_correlator/cross_multiplier.vhd @@ -0,0 +1,85 @@ +library ieee, common_pkg_lib, casper_multiplier_lib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use common_pkg_lib.common_pkg.all; +use work.correlator_pkg.all; + +entity cross_multiplier is + generic( + g_use_gauss : BOOLEAN := FALSE; + g_use_dsp : BOOLEAN := TRUE; + g_pipeline_input : NATURAL := 1; --! 0 or 1 + g_pipeline_product : NATURAL := 1; --! 0 or 1 + g_pipeline_adder : NATURAL := 1; --! 0 or 1 + g_pipeline_round : NATURAL := 1; --! 0 or 1 + g_pipeline_output : NATURAL := 0; --! >= 0 + ovflw_behav : BOOLEAN := FALSE; + quant_behav : NATURAL := 0 + ); + port( + clk : in std_logic; + ce : in std_logic; + sync_in : in std_logic; + sync_out : out std_logic; + din : in s_cross_mult_din; + dout : out s_cross_mult_out + ); +end entity cross_multiplier; + +architecture RTL of cross_multiplier is + + signal s_out_bus_expand : s_cross_mult_out_bus_expand := (others => (others => '0')); + signal s_out_cmults : s_cross_mult_cmult_out := (others => (others => '0')); + signal s_a_cmult_in, s_b_cmult_in : s_cross_mult_cmult_in := (others => (others => '0')); + signal s_out : s_cross_mult_out := (others=>(others=>'0')); + + signal s_cmult_input_map : s_cmult_map := gen_inpt_to_mult_mapping(c_cross_mult_aggregation_per_stream, c_cross_mult_nof_input_streams); + +begin + + gen_expand : FOR j IN 0 TO c_cross_mult_aggregation_per_stream - 1 GENERATE --SPLIT the aggregation + gen_bus_expand : FOR i IN 0 TO c_cross_mult_nof_input_streams - 1 GENERATE -- FOR each stream + s_out_bus_expand(c_cross_mult_nof_input_streams*j + i) <= din(i)((j + 1) * c_cross_mult_input_cbit_width - 1 DOWNTO j * c_cross_mult_input_cbit_width); + END GENERATE; + END GENERATE; + + gen_cmult : FOR m IN 0 TO c_cross_mult_nof_cmults - 1 GENERATE + s_a_cmult_in(m) <= s_out_bus_expand(s_cmult_input_map(m)(0)); + s_b_cmult_in(m) <= s_out_bus_expand(s_cmult_input_map(m)(1)); + cmult_inst : entity casper_multiplier_lib.cmult + generic map( + g_use_ip => FALSE, + g_a_bw => c_cross_mult_input_bit_width, + g_b_bw => c_cross_mult_input_bit_width, + g_ab_bw => c_cross_mult_output_bit_width, + g_conjugate_b => TRUE, + g_use_gauss => g_use_gauss, + g_use_dsp => g_use_dsp, + g_round_method => quant_behav, + g_ovflw_method => ovflw_behav, + g_pipeline_input => g_pipeline_input, + g_pipeline_product => g_pipeline_product, + g_pipeline_adder => g_pipeline_adder, + g_pipeline_round => g_pipeline_round, + g_pipeline_output => g_pipeline_output + ) + port map( + clk => clk, + ce => ce, + rst => '0', + in_a => s_a_cmult_in(m), + in_b => s_b_cmult_in(m), + in_val => '1', + out_ab => s_out_cmults(m), + out_val => open + ); + + END GENERATE; + + gen_pack : FOR n IN 0 TO c_cross_mult_nof_output_streams - 1 GENERATE + gen_per_aggregation : FOR p IN 0 TO c_cross_mult_aggregation_per_stream - 1 GENERATE + s_out(n)((p+1)*c_cross_mult_output_cbit_width - 1 DOWNTO p*c_cross_mult_output_cbit_width) <= s_out_cmults(2*n + p)(c_cross_mult_output_cbit_width -1 DOWNTO 0); + END GENERATE; + END GENERATE; + dout <= s_out; +end architecture RTL; diff --git a/casper_correlator/run.py b/casper_correlator/run.py new file mode 100644 index 00000000..adf2184d --- /dev/null +++ b/casper_correlator/run.py @@ -0,0 +1,195 @@ +#Author: Talon Myburgh +#Company: Mydon Solutions + +from vunit import VUnit +import numpy as np +import itertools +import glob +from os.path import dirname, join, abspath + +# Function for package mangling. +def manglePkg(file_name, line_number, new_line): + with open(file_name, 'r') as file: + lines = file.readlines() + lines[line_number] = new_line + with open(file_name, 'w') as file: + lines = file.writelines(lines) + + +def mapping(aggre, inpts): + mult_map = {} + mult = 0 + for a in range(aggre): + aa = a * inpts + for s in range(aa, aa + inpts): + for ss in range(s, aa + inpts): + mult_map[mult] = (s, ss) + mult += 1 + return mult_map + +def cross_mult(c_val_dict): + ans_dict = {} + for test, val in c_val_dict.items(): + tests = test.split(':') + aggregations = int(tests[1]) + streams = int(tests[0]) + nof_cmults = aggregations * int(((streams +1)*streams)/2) + answers = np.zeros(nof_cmults,dtype=np.complex64) + mult_map = mapping(aggregations,streams) + for ans in range(nof_cmults): + a = val[mult_map[ans][0]] + b = np.conj(val[mult_map[ans][1]]) + answers[ans] = a * b + ans_dict[test] = answers + return ans_dict + +def turn_cint_to_int(number:complex, cin_bwidth:int): + if number.real >= 0: + real = int(number.real) + else: + real = int(number.real) + 2**32 + + if number.imag >= 0: + imag = int(number.imag) + else: + imag = int(number.imag) + 2**32 + real_binary = bin(real & (2**cin_bwidth - 1))[2:].zfill(cin_bwidth) + imag_binary = bin(imag & (2**cin_bwidth - 1))[2:].zfill(cin_bwidth) + binary = real_binary + imag_binary + return int(binary, 2) + +def split_int_gen_complexint(number, bitwidth): + if number < 0: + number += 2**32 + binary = bin(number & (2**bitwidth-1))[2:].zfill(bitwidth) + first_half = binary[:bitwidth//2] + second_half = binary[bitwidth//2:] + if first_half: + first_int = int(first_half, 2) + if first_int >= 2**(bitwidth//2-1): + first_int -= 2**(bitwidth//2) + else: + first_int = 0 + if second_half: + second_int = int(second_half, 2) + if second_int >= 2**(bitwidth//2-1): + second_int -= 2**(bitwidth//2) + else: + second_int = 0 + return first_int + second_int*1j + +# Create VUnit instance by parsing command line arguments +vu = VUnit.from_argv() +vu.add_vhdl_builtins() +script_dir = abspath(dirname(__file__)) + +aggregations = np.random.randint(2 , 8, 1) +streams = np.random.randint(2, 20, 1) +inpt_bitwidths = int(np.random.randint(2, 10, 1)) + +package_vals = [f' CONSTANT c_cross_mult_nof_input_streams : NATURAL := {int(streams)};\n', +f' CONSTANT c_cross_mult_aggregation_per_stream : NATURAL := {int(aggregations)};\n', +f' CONSTANT c_cross_mult_input_bit_width : NATURAL := {int(inpt_bitwidths)};\n', +f' CONSTANT c_cross_mult_output_bit_width : NATURAL := {2*int(inpt_bitwidths)+1};\n'] + +manglePkg(join(script_dir,'correlator_pkg.vhd'), slice(5,9),package_vals) + +# COMMON COMPONENTS Library +common_components_lib = vu.add_library("common_components_lib",allow_duplicate=True) +common_components_lib.add_source_files(script_dir + "/../common_components/common_pipeline.vhd") +common_components_lib.add_source_files(script_dir + "/../common_components/common_pipeline_sl.vhd") + +# COMMON PACKAGE Library +common_pkg_lib = vu.add_library("common_pkg_lib",allow_duplicate = True) +common_pkg_lib.add_source_files(script_dir + "/../common_pkg/*.vhd") +common_pkg_lib.add_source_files(script_dir + "/../common_pkg/tb_common_pkg.vhd") + +# TECHNOLOGY Library +technology_lib = vu.add_library("technology_lib",allow_duplicate = True) +technology_lib.add_source_files(script_dir + "/../technology/technology_select_pkg.vhd") + +# XPM Multiplier library +ip_xpm_mult_lib = vu.add_library("ip_xpm_mult_lib", allow_duplicate=True) +ip_xpm_mult_lib.add_source_files(script_dir + "/../ip_xpm/mult/*.vhd") + +# STRATIXIV Multiplier library +ip_stratixiv_mult_lib = vu.add_library("ip_stratixiv_mult_lib", allow_duplicate=True) +ip_stratixiv_mult_lib.add_source_files(script_dir + "/../ip_stratixiv/mult/*rtl.vhd") + +# CASPER MUlTIPLIER Library +casper_multiplier_lib = vu.add_library("casper_multiplier_lib") +casper_multiplier_lib.add_source_file(join(script_dir, "../casper_multiplier/tech_mult_component.vhd")) +tech_complex_mult = casper_multiplier_lib.add_source_file(join(script_dir, "../casper_multiplier/tech_complex_mult.vhd")) +casper_multiplier_lib.add_source_file(join(script_dir, "../casper_multiplier/tech_agilex_versal_cmult.vhd")) +casper_multiplier_lib.add_source_file(join(script_dir, "../casper_multiplier/common_complex_mult.vhd")) +casper_multiplier_lib.add_source_file(join(script_dir, "../casper_multiplier/cmult.vhd")) + +# CASPER CORRELATOR Library +casper_correlator_lib = vu.add_library("casper_correlator_lib",allow_duplicate=True) +casper_correlator_lib.add_source_files(join(script_dir,'*.vhd')) + +TB_GENERATED = casper_correlator_lib.test_bench("tb_tb_vu_cross_multiplier") + +value_dict = {} +# Here we generate the test values. Note that these values are all taken as complex where real and imag are join (i.e. 85 = 5+5j) +for s, a in itertools.product(streams, aggregations): + print(f""" + Generating test for values: + bitwidth = {inpt_bitwidths} + nof streams = {s} + nof aggregations = {a}""") + max_val = int(2**(2*inpt_bitwidths) -1) + min_val = 0 + value_dict[f"{s}:{a}"] = np.random.randint(min_val, max_val, size=(s,a)) + +generics_dict = {} +#Turn this into strings so they can be passed to generic g_values +for key,val in value_dict.items(): + strval = ', '.join(map(str, val.flatten(order = 'F'))) + generics_dict[key] = strval + +#Here we must construct the complex values for testing +c_dict = {} +for key,val in value_dict.items(): + values = val.flatten(order = 'F') #now we've flattened across aggregations which is how the module works and what the mapping expects + # print(values) + c_val = np.zeros(values.shape, dtype=np.complex64) + for i,v in enumerate(values): + c_val[i] = split_int_gen_complexint(int(v),2*int(inpt_bitwidths)) + c_dict[key] = c_val + +cross_mult_result = cross_mult(c_dict) + +result_dict = {} +for test, val in cross_mult_result.items(): + tests = test.split(':') + stream = int(tests[0]) + aggre = int(tests[1]) + int_val = np.zeros(val.shape,dtype=np.int64) + for i,v in enumerate(val): + int_val[i] = turn_cint_to_int(v ,2*int(inpt_bitwidths) + 1) + result_dict[test] = int_val#.reshape(int_val.size//aggre,aggre,order='F') + +generics_result = {} +#convert result dict to set of strings for generics: +for key, result in result_dict.items(): + strval = ', '.join(map(str, result))#.flatten())) + generics_result[key] = strval + +for key, val in generics_dict.items(): + vals = key.split(':') + streams = int(vals[0]) + aggregations = int(vals[1]) + config_name = f"Streams={streams},Aggregations={aggregations},inputbitwidth={inpt_bitwidths}" + TB_GENERATED.add_config( + name = config_name, + generics = { + 'g_values' : val, + 'g_results' : generics_result[key] + } + ) + +# RUN +vu.set_compile_option("ghdl.a_flags", ["-frelaxed", "-Wno-hide"]) +vu.set_sim_option("ghdl.elab_flags", ["-frelaxed","--syn-binding"]) +vu.main() diff --git a/casper_correlator/tb_cross_multiplier.vhd b/casper_correlator/tb_cross_multiplier.vhd new file mode 100644 index 00000000..125e9709 --- /dev/null +++ b/casper_correlator/tb_cross_multiplier.vhd @@ -0,0 +1,121 @@ +-- A VHDL testbench for cross_multiplier.vhd. +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +LIBRARY IEEE, common_pkg_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +USE STD.TEXTIO.ALL; +USE work.correlator_pkg.all; + +entity tb_cross_multiplier is + generic( + g_values : t_natural_matrix(0 TO c_cross_mult_nof_input_streams - 1,0 TO c_cross_mult_aggregation_per_stream - 1); --:= ((11, 27), (10, 16), (-26, 26)); + g_results : t_natural_matrix (0 TO c_cross_mult_nof_output_streams - 1, 0 TO c_cross_mult_aggregation_per_stream - 1)-- := ((247808, 225280), (137205, 204800), (124918, 75776), (51200, 163840), (61440, 524288), (196608, 73728)) + ); + port( + o_clk : out std_logic; + o_tb_end : out std_logic; + o_test_msg : out STRING(1 to 200); + o_test_pass : out BOOLEAN := True + ); +end entity tb_cross_multiplier; + +architecture rtl of tb_cross_multiplier is + + CONSTANT clk_period : TIME := 10 ns; + CONSTANT c_pipeline_input : NATURAL := 1; + CONSTANT c_pipeline_product : NATURAL := 1; + CONSTANT c_pipeline_adder : NATURAL := 1; + CONSTANT c_pipeline_round : NATURAL := 1; + CONSTANT c_pipeline_output : NATURAL := 0; + + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL ce : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL din : s_cross_mult_din := (others => (others => '0')); + SIGNAL dout : s_cross_mult_out := (others => (others => '0')); + SIGNAL exp_dout : s_cross_mult_out := (others => (others => '0')); + + function populate_din + return s_cross_mult_din IS + VARIABLE pop_input : s_cross_mult_din; + VARIABLE max_width : NATURAL := c_cross_mult_aggregation_per_stream * c_cross_mult_input_cbit_width; + BEGIN + FOR i IN 0 TO c_cross_mult_nof_input_streams - 1 LOOP + FOR j IN 0 TO c_cross_mult_aggregation_per_stream - 1 LOOP + pop_input(i)(max_width - c_cross_mult_input_cbit_width*j - 1 DOWNTO max_width - c_cross_mult_input_cbit_width*(j+1)) := TO_UVEC(g_values(i, c_cross_mult_aggregation_per_stream-j-1),c_cross_mult_input_cbit_width); + END LOOP; + END LOOP; + RETURN pop_input; + END FUNCTION; + + function populate_exp_dout + return s_cross_mult_out IS + VARIABLE pop_output : s_cross_mult_out; + BEGIN + FOR i IN 0 TO c_cross_mult_nof_output_streams - 1 LOOP + FOR j IN 0 TO c_cross_mult_aggregation_per_stream - 1 LOOP + pop_output(i)((j+1)*c_cross_mult_output_cbit_width -1 DOWNTO j*c_cross_mult_output_cbit_width) := TO_UVEC(g_results(i,j),c_cross_mult_output_cbit_width); + END LOOP; + END LOOP; + RETURN pop_output; + END FUNCTION; + +begin + clk <= NOT clk OR tb_end AFTER clk_period / 2; + + o_clk <= clk; + o_tb_end <= tb_end; + + --------------------------------------------------------------------- + -- Stimulus process + --------------------------------------------------------------------- + p_stimuli_verify : PROCESS + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + VARIABLE v_test_pass : BOOLEAN := True; + BEGIN + WAIT UNTIL rising_edge(clk); + WAIT FOR 5 * clk_period; + din <= populate_din; + exp_dout <= populate_exp_dout; + ce <= '1'; + WAIT FOR (c_pipeline_input + c_pipeline_product + c_pipeline_adder + c_pipeline_round + c_pipeline_output + 1)*clk_period; + FOR i IN 0 TO c_cross_mult_nof_output_streams - 1 LOOP + v_test_pass := v_test_pass and (dout(i) = exp_dout(i)); + if not v_test_pass then + v_test_msg := pad("4DSP RE cmult wrong RTL result#" & integer'image(i) & ", expected: " & to_hstring(exp_dout(i)) & " but got: " & to_hstring(dout(i)), o_test_msg'length, '.'); + o_test_msg <= v_test_msg; + report "Error: " & v_test_msg severity failure; + end if; + END LOOP; + o_test_msg <= v_test_msg; + o_test_pass <= v_test_pass; + tb_end <= '1'; + WAIT; + + END PROCESS; +--------------------------------------------------------------------- +-- cross multiplier module +--------------------------------------------------------------------- +cross_mult : entity work.cross_multiplier + generic map( + g_use_gauss => FALSE, + g_use_dsp => TRUE, + g_pipeline_input => c_pipeline_input, + g_pipeline_product => c_pipeline_product, + g_pipeline_adder => c_pipeline_adder, + g_pipeline_round => c_pipeline_round, + g_pipeline_output => c_pipeline_output, + ovflw_behav => FALSE, + quant_behav => 0 + ) + port map( + clk => clk, + ce => ce, + din => din, + dout => dout + ); + +end architecture; \ No newline at end of file diff --git a/casper_correlator/tb_tb_vu_cross_multiplier.vhd b/casper_correlator/tb_tb_vu_cross_multiplier.vhd new file mode 100644 index 00000000..43ea02d6 --- /dev/null +++ b/casper_correlator/tb_tb_vu_cross_multiplier.vhd @@ -0,0 +1,98 @@ +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +library ieee, common_pkg_lib, vunit_lib; +use IEEE.std_logic_1164.all; +use common_pkg_lib.common_pkg.all; +use work.correlator_pkg.all; +context vunit_lib.vunit_context; + +entity tb_tb_vu_cross_multiplier is + GENERIC( + g_values : string; -- CSV matrix of integers where ; demarcate new rows + g_results : string; + runner_cfg : string + ); +end tb_tb_vu_cross_multiplier; + +architecture tb of tb_tb_vu_cross_multiplier is + + SIGNAL rst : STD_LOGIC := '0'; + SIGNAL clk : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC; + SIGNAL test_msg : STRING(1 to 200); + SIGNAL test_pass : BOOLEAN; + + impure function decodeinpt(encoded_natural_matrix : string) return t_natural_matrix is + VARIABLE parts : lines_t := split(encoded_natural_matrix, ","); + VARIABLE row : NATURAL := 0; + VARIABLE col : NATURAL := 0; + VARIABLE new_row : BOOLEAN := FALSE; + variable return_value : t_natural_matrix(0 TO c_cross_mult_nof_input_streams - 1,0 TO c_cross_mult_aggregation_per_stream - 1); + begin + + for i in parts'range loop + + return_value(row, col) := integer'value(parts(i).all); + new_row := (col = c_cross_mult_aggregation_per_stream - 1) AND (row /= c_cross_mult_nof_input_streams - 1); + if new_row then + row := row + 1; + col := 0; + else + col := col + 1; + end if; + end loop; + return return_value; + end; + impure function decodeoutpt(encoded_natural_matrix : string) return t_natural_matrix is + VARIABLE parts : lines_t := split(encoded_natural_matrix, ","); + VARIABLE row : NATURAL := 0; + VARIABLE col : NATURAL := 0; + VARIABLE new_row : BOOLEAN := FALSE; + variable return_value : t_natural_matrix (0 TO c_cross_mult_nof_output_streams - 1, 0 TO c_cross_mult_aggregation_per_stream - 1); + begin + for i in parts'range loop + + return_value(row, col) := integer'value(parts(i).all); + new_row := (col = c_cross_mult_aggregation_per_stream - 1) AND (row /= c_cross_mult_nof_output_streams - 1); + if new_row then + row := row + 1; + col := 0; + else + col := col + 1; + end if; + end loop; + return return_value; + end; + + CONSTANT c_values : t_natural_matrix := decodeinpt(g_values); + CONSTANT c_results : t_natural_matrix := decodeoutpt(g_results); +BEGIN + tb_ut : ENTITY work.tb_cross_multiplier + GENERIC MAP( + g_values => c_values, + g_results => c_results + ) + PORT MAP( + o_clk => clk, + o_tb_end => tb_end, + o_test_msg => test_msg, + o_test_pass => test_pass + ); + + p_vunit : PROCESS + BEGIN + test_runner_setup(runner, runner_cfg); + wait until tb_end = '1'; + test_runner_cleanup(runner); + wait; + END PROCESS; + + p_verify : PROCESS(clk) + BEGIN + IF rising_edge(clk) THEN + check(test_pass, "Test Failed: " & test_msg); + END IF; + + END PROCESS; +END tb; \ No newline at end of file diff --git a/casper_correlator/top_cross_mult.vhd b/casper_correlator/top_cross_mult.vhd new file mode 100644 index 00000000..8ca3c8c3 --- /dev/null +++ b/casper_correlator/top_cross_mult.vhd @@ -0,0 +1,66 @@ +library ieee, common_pkg_lib, casper_multiplier_lib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use common_pkg_lib.common_pkg.all; +use work.correlator_pkg.all; + +entity cross_multiplier_top is + generic( + g_use_gauss : BOOLEAN := FALSE; + g_use_dsp : BOOLEAN := TRUE; + g_pipeline_input : NATURAL := 1; --! 0 or 1 + g_pipeline_product : NATURAL := 1; --! 0 or 1 + g_pipeline_adder : NATURAL := 1; --! 0 or 1 + g_pipeline_round : NATURAL := 1; --! 0 or 1 + g_pipeline_output : NATURAL := 0; --! >= 0 + ovflw_behav : BOOLEAN := FALSE; + quant_behav : NATURAL := 0 + ); + port( + clk : in std_logic; + ce : in std_logic; + sync_in : in std_logic; + sync_out : out std_logic; + din_0 : in STD_LOGIC_VECTOR((c_cross_mult_aggregation_per_stream * c_cross_mult_input_cbit_width) - 1 downto 0); + din_1 : in STD_LOGIC_VECTOR((c_cross_mult_aggregation_per_stream * c_cross_mult_input_cbit_width) - 1 downto 0); + dout_0 : out STD_LOGIC_VECTOR((c_cross_mult_aggregation_per_stream * c_cross_mult_output_cbit_width) - 1 downto 0); + dout_1 : out STD_LOGIC_VECTOR((c_cross_mult_aggregation_per_stream * c_cross_mult_output_cbit_width) - 1 downto 0); + dout_2 : out STD_LOGIC_VECTOR((c_cross_mult_aggregation_per_stream * c_cross_mult_output_cbit_width) - 1 downto 0) + ); + +end entity cross_multiplier_top; + +architecture RTL of cross_multiplier_top is + + SIGNAL s_din : s_cross_mult_din; + SIGNAL s_dout : s_cross_mult_out; +begin + + u_cross_mult : entity work.cross_multiplier + generic map ( + g_use_gauss => g_use_gauss, + g_use_dsp => g_use_dsp, + g_pipeline_input => g_pipeline_input, + g_pipeline_product => g_pipeline_product, + g_pipeline_adder => g_pipeline_adder, + g_pipeline_round => g_pipeline_round, + g_pipeline_output => g_pipeline_output, + ovflw_behav => ovflw_behav, + quant_behav => quant_behav + ) + port map ( + clk => clk, + ce => ce, + sync_in => sync_in, + sync_out => sync_out, + din => s_din, + dout => s_dout + ); + + s_din(0) <= din_0; + s_din(1) <= din_1; + dout_0 <= s_dout(0); + dout_1 <= s_dout(1); + dout_2 <= s_dout(2); + +end architecture; \ No newline at end of file diff --git a/casper_counter/free_run_down_counter.vhd b/casper_counter/free_run_down_counter.vhd new file mode 100644 index 00000000..d94465e4 --- /dev/null +++ b/casper_counter/free_run_down_counter.vhd @@ -0,0 +1,42 @@ +-- A VHDL free-running down-counter module with asynch reset. +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +library ieee, casper_counter_lib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity free_run_down_counter is + generic( + g_cnt_w : natural := 4 + ); + port( + clk : in std_logic; + ce : in std_logic; + reset : in std_logic; + enable : in std_logic := '1'; + count : out std_logic_vector(g_cnt_w - 1 DOWNTO 0) + ); +end entity free_run_down_counter; + +ARCHITECTURE rtl of free_run_down_counter is + constant c_max_count : natural := 2**g_cnt_w - 1; + + signal s_count : std_logic_vector(g_cnt_w - 1 DOWNTO 0); + +begin + + process (clk, reset) + variable cnt : integer range 0 to c_max_count; + begin + if (reset = '1') then + cnt := c_max_count; + elsif (rising_edge(clk) and ce = '1' and enable = '1') then + cnt := cnt - 1; + end if; + s_count <= std_logic_vector(to_signed(cnt, g_cnt_w)); + end process; + + count <= s_count; + + end ARCHITECTURE rtl; \ No newline at end of file diff --git a/casper_counter/free_run_up_counter.vhd b/casper_counter/free_run_up_counter.vhd new file mode 100644 index 00000000..2ad81732 --- /dev/null +++ b/casper_counter/free_run_up_counter.vhd @@ -0,0 +1,56 @@ +-- A VHDL free-running up-counter module with asynch reset. +-- @author: Talon Myburgh +-- @company: Mydon Solutions +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.numeric_std.all; + +ENTITY free_run_up_counter is + generic ( + g_cnt_w : NATURAL := 4; + g_cnt_up_not_down : BOOLEAN := TRUE; + g_cnt_initial_value : NATURAL := 0; + g_cnt_signed : BOOLEAN := TRUE + ); + port ( + clk : in std_logic; + ce : in std_logic; + reset : in std_logic; + enable : in std_logic := '1'; + count : out std_logic_vector(g_cnt_w - 1 DOWNTO 0) + ); +END ENTITY; + +ARCHITECTURE rtl of free_run_up_counter is + CONSTANT c_max_count : NATURAL := 2**g_cnt_w - 1; + + SIGNAL s_count : STD_LOGIC_VECTOR(g_cnt_w - 1 DOWNTO 0); + +BEGIN + + PROCESS (clk, reset) + VARIABLE cnt : INTEGER RANGE 0 TO c_max_count := g_cnt_initial_value; + BEGIN + IF (reset = '1') THEN + cnt := g_cnt_initial_value; + ELSIF (rising_edge(clk) and ce = '1') THEN + IF g_cnt_up_not_down THEN + cnt := cnt + 1; + ELSE + IF (cnt = 0) THEN + cnt := c_max_count; + ELSE + cnt := cnt - 1; + END IF; + END IF; + END IF; + IF g_cnt_signed THEN + s_count <= STD_LOGIC_VECTOR(TO_SIGNED(cnt, g_cnt_w)); + ELSE + s_count <= STD_LOGIC_VECTOR(TO_UNSIGNED(cnt, g_cnt_w)); + END IF; + END PROCESS; + + count <= s_count; + +END ARCHITECTURE; \ No newline at end of file diff --git a/casper_counter/run.py b/casper_counter/run.py index e5727023..9d04d3c7 100644 --- a/casper_counter/run.py +++ b/casper_counter/run.py @@ -3,6 +3,7 @@ # Create VUnit instance by parsing command line arguments vu = VUnit.from_argv() +vu.add_vhdl_builtins() script_dir = dirname(__file__) # Create library 'casper_counter_lib' @@ -10,6 +11,9 @@ casper_counter_lib.add_source_files(join(script_dir,"./*.vhd")) common_pkg_lib = vu.add_library("common_pkg_lib") +common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/fixed_float_types_c.vhd")) +common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/fixed_pkg_c.vhd")) +common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/float_pkg_c.vhd")) common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/common_pkg.vhd")) TB_GENERATED = casper_counter_lib.test_bench("tb_tb_vu_common_counter") diff --git a/casper_delay/delay_bram.vhd b/casper_delay/delay_bram.vhd new file mode 100644 index 00000000..7f907220 --- /dev/null +++ b/casper_delay/delay_bram.vhd @@ -0,0 +1,192 @@ +-- A VHDL implementation of the CASPER delay_bram (sync) block. +-- @author: Talon Myburgh +-- @company: Mydon Solutions +-- TODO: add ability to implement counter using dsp48 blocks. + +LIBRARY IEEE, common_pkg_lib, casper_counter_lib, casper_ram_lib; +USE IEEE.std_logic_1164.all; +USE common_pkg_lib.common_pkg.all; +USE casper_ram_lib.common_ram_pkg.all; + +ENTITY delay_bram is + generic ( + g_delay : NATURAL := 3; + g_ram_primitive : STRING := "block"; + g_ram_latency: NATURAL := 2 + ); + port ( + clk : in std_logic; + ce : in std_logic; + din : in std_logic_vector; + dout : out std_logic_vector + ); +end ENTITY; + +ARCHITECTURE rtl of delay_bram is + + CONSTANT c_cntr_width: NATURAL := ceil_log2(g_delay); + CONSTANT c_dat_w : NATURAL := din'LENGTH; + CONSTANT c_mem_ram : t_c_mem := (g_ram_latency, c_cntr_width, c_dat_w, g_delay, 'X'); + CONSTANT c_max_cnt : NATURAL := g_delay - g_ram_latency - 1; + + SIGNAL s_count_val : STD_LOGIC_VECTOR(c_cntr_width - 1 DOWNTO 0) := (others => '0'); + SIGNAL s_ram_out : STD_LOGIC_VECTOR(din'RANGE); + +begin + + ASSERT c_max_cnt > 0 REPORT "Delay value must be greater than BRAM latency + 1!" severity FAILURE; + +-------------------------------------------------------- +-- Counter +-------------------------------------------------------- + addr_cntr : ENTITY casper_counter_lib.common_counter + GENERIC MAP( + g_latency => 0, + g_init => 0, + g_width => c_cntr_width, + g_max => c_max_cnt, + g_step_size => 1 + ) + PORT MAP( + rst => '0', + clk => clk, + clken => ce, + count => s_count_val + ); + +-------------------------------------------------------- +-- Single Port Ram +-------------------------------------------------------- + delay_spram : ENTITY casper_ram_lib.common_ram_r_w + GENERIC MAP ( + g_ram => c_mem_ram, + g_true_dual_port => FALSE, + g_ram_primitive => g_ram_primitive + ) + PORT MAP( + clk => clk, + clken => ce, + wr_en => '1', + wr_adr => s_count_val, + wr_dat => din, + rd_en => '1', + rd_adr => s_count_val, + rd_dat => s_ram_out, + rd_val => open + ); + +-------------------------------------------------------- +-- Register the output signal for one cycle - This seems +-- to introduce 1 too many delays... so we do without it. +-------------------------------------------------------- + -- single_delay: PROCESS (clk, ce) + -- begin + -- if(rising_edge(clk) and ce = '1') then + -- dout <= s_ram_out; + -- end if; + -- end PROCESS; + dout <= s_ram_out; + +end ARCHITECTURE; + +------------------------------------------------------------------------- +-- A VHDL implementation of the CASPER delay_bram_async block. +-- @author: Mydon Solutions. +-- TODO: add ability to implement counter using dsp48 blocks. + +LIBRARY IEEE, common_pkg_lib, casper_counter_lib, casper_ram_lib; +USE IEEE.std_logic_1164.all; +USE common_pkg_lib.common_pkg.all; +USE casper_ram_lib.common_ram_pkg.all; + +ENTITY delay_bram_async is + generic ( + g_delay : NATURAL := 3; + g_ram_primitive : STRING := "block"; + g_ram_latency: NATURAL := 2 + ); + port ( + clk : in std_logic; + ce : in std_logic; + en : in std_logic; + din : in std_logic_vector; + dout : out std_logic_vector + ); +end ENTITY; + +ARCHITECTURE rtl of delay_bram_async is + + CONSTANT c_cntr_width: NATURAL := ceil_log2(g_delay); + CONSTANT c_dat_w : NATURAL := din'LENGTH; + CONSTANT c_mem_ram : t_c_mem := (g_ram_latency, c_cntr_width, c_dat_w, g_delay, 'X'); + CONSTANT c_max_cnt : NATURAL := g_delay - g_ram_latency - 1; + + -- GHDL is picky about unconstrained Std_logic_vectors by defining a zero constant we resolve a GHDL error about unconstrained std_logic_vector and others below. + CONSTANT c_zero_din : STD_LOGIC_VECTOR(din'RANGE) := (others => '0'); + + SIGNAL s_count_val : STD_LOGIC_VECTOR(c_cntr_width - 1 DOWNTO 0) := (others=>'0'); + SIGNAL s_ram_out : STD_LOGIC_VECTOR(din'RANGE); + +begin + + ASSERT c_max_cnt > 0 REPORT "Delay value must be greater than BRAM latency + 1!" severity FAILURE; + +-------------------------------------------------------- +-- Counter +-------------------------------------------------------- + addr_cntr : ENTITY casper_counter_lib.common_counter + GENERIC MAP( + g_latency => 0, + g_init => 0, + g_width => c_cntr_width, + g_max => c_max_cnt, + g_step_size => 1 + ) + PORT MAP( + rst => '0', + clk => clk, + clken => ce, + cnt_en => en, + count => s_count_val + ); + +-------------------------------------------------------- +-- Single Port Ram +-------------------------------------------------------- + delay_spram : ENTITY casper_ram_lib.common_ram_r_w + GENERIC MAP ( + g_ram => c_mem_ram, + g_true_dual_port => FALSE, + g_ram_primitive => g_ram_primitive + ) + PORT MAP( + clk => clk, + clken => ce, + wr_en => en, + wr_adr => s_count_val, + wr_dat => din, + rd_en => en, + rd_adr => s_count_val, + rd_dat => s_ram_out, + rd_val => open + ); + +-------------------------------------------------------- +-- Register the output signal for one cycle - This seems +-- to introduce 1 too many delays... so we do without it. +-------------------------------------------------------- + -- single_delay: PROCESS (clk, ce) + -- begin + -- if(rising_edge(clk) and ce = '1') then + -- if(en = '1') then + -- dout <= s_ram_out; + -- else + -- dout <= (others =>'0'); + -- end if; + -- end if; + -- end PROCESS; + + --GHDL does not like unconstrained arrays and using others. Work around using a constant + dout <= s_ram_out when en = '1' else (c_zero_din); + +end ARCHITECTURE; \ No newline at end of file diff --git a/casper_delay/delay_bram_en_plus.vhd b/casper_delay/delay_bram_en_plus.vhd new file mode 100644 index 00000000..6955940c --- /dev/null +++ b/casper_delay/delay_bram_en_plus.vhd @@ -0,0 +1,120 @@ +-- A VHDL implementation of the CASPER delay_bram_en_plus block. +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +LIBRARY IEEE, common_pkg_lib, common_components_lib, casper_counter_lib, casper_ram_lib; +USE IEEE.std_logic_1164.all; +USE common_pkg_lib.common_pkg.all; +USE casper_ram_lib.common_ram_pkg.all; +USE common_components_lib.common_components_pkg.all; + +ENTITY delay_bram_en_plus is + generic ( + g_delay : NATURAL := 3; + g_ram_primitive : STRING := "block"; + g_latency: NATURAL := 2 + ); + port ( + clk : in std_logic; + ce : in std_logic; + en : in std_logic; + din : in std_logic_vector; + valid : out std_logic; + dout : out std_logic_vector + ); + end ENTITY; + + ARCHITECTURE rtl of delay_bram_en_plus is + + CONSTANT c_cntr_width: NATURAL := ceil_log2(g_delay); + CONSTANT c_dat_w : NATURAL := din'LENGTH; + CONSTANT c_mem_ram : t_c_mem := (2, c_cntr_width, c_dat_w, g_delay, 'X'); + CONSTANT c_max_cnt : NATURAL := g_delay - 1; + + SIGNAL s_count_val : STD_LOGIC_VECTOR(c_cntr_width - 1 DOWNTO 0) := (others => '0'); + SIGNAL s_ram_out : STD_LOGIC_VECTOR(din'RANGE); + SIGNAL s_en : STD_LOGIC_VECTOR(0 DOWNTO 0); + SIGNAL s_valid : STD_LOGIC_VECTOR(0 DOWNTO 0); + + begin + s_en(0) <= en; + valid <= s_valid(0); + + ASSERT c_max_cnt > 0 REPORT "Delay value must be greater than BRAM latency + 1!" severity FAILURE; + +-------------------------------------------------------- +-- Counter +-------------------------------------------------------- + addr_cntr : ENTITY casper_counter_lib.common_counter + GENERIC MAP( + g_latency => 0, + g_init => 0, + g_width => c_cntr_width, + g_max => c_max_cnt, + g_step_size => 1 + ) + PORT MAP( + rst => '0', + clk => clk, + clken => ce, + cnt_en => en, + count => s_count_val + ); + +-------------------------------------------------------- +-- Single Port Ram +-------------------------------------------------------- + delay_spram : ENTITY casper_ram_lib.common_ram_r_w + GENERIC MAP ( + g_ram => c_mem_ram, + g_true_dual_port => FALSE, + g_ram_primitive => g_ram_primitive + ) + PORT MAP( + clk => clk, + clken => ce, + wr_en => en, + wr_adr => s_count_val, + wr_dat => din, + rd_en => '1', + rd_adr => s_count_val, + rd_dat => s_ram_out, + rd_val => open + ); + +------------------------------------------------------- +-- Bram_latency delay +------------------------------------------------------- + bram_latency_delay : ENTITY common_components_lib.common_delay + generic map ( + g_dat_w => 1, + g_depth => g_latency + ) + port map ( + clk => clk, + in_val => '1', + in_dat => s_en, + out_dat => s_valid + ); + + ------------------------------------------------------- + -- Bram_value delay + ------------------------------------------------------- + gen_ram_out_direct : IF g_latency < 2 GENERATE + dout <= s_ram_out; + end GENERATE; + gen_ram_out_delay : IF g_latency >= 2 GENERATE + bram_value_delay : ENTITY common_components_lib.common_delay + generic map ( + g_dat_w => c_dat_w, + g_depth => g_latency - 2 + ) + port map ( + clk => clk, + in_val => '1', + in_dat => s_ram_out, + out_dat => dout + ); + end GENERATE; + +end ARCHITECTURE; \ No newline at end of file diff --git a/casper_delay/delay_bram_prog.vhd b/casper_delay/delay_bram_prog.vhd new file mode 100644 index 00000000..8c2b7aa0 --- /dev/null +++ b/casper_delay/delay_bram_prog.vhd @@ -0,0 +1,110 @@ +-- A VHDL implementation of the CASPER delay_bram_prog block. +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +LIBRARY IEEE, common_pkg_lib, casper_counter_lib, casper_ram_lib, casper_adder_lib, common_components_lib; +USE IEEE.std_logic_1164.all; +USE IEEE.numeric_std.all; +USE common_pkg_lib.common_pkg.all; +USE casper_ram_lib.common_ram_pkg.all; +USE common_components_lib.common_components_pkg.all; + +ENTITY delay_bram_prog is + generic ( + g_max_delay : NATURAL := 7; -- 2^g_max_delay + g_ram_primitive : STRING := "block"; -- bram primitive + g_ram_latency: NATURAL := 2 -- bram latency. Anything in excess of 2 will be in a delay block + ); + port ( + clk : in std_logic; + ce : in std_logic; + din : in std_logic_vector; -- signal to delay + delay : in std_logic_vector; -- variable delay + dout : out std_logic_vector -- delayed signal + ); +end ENTITY; + +ARCHITECTURE rtl of delay_bram_prog is + CONSTANT c_dat_w : NATURAL := din'LENGTH; + CONSTANT c_mem_ram : t_c_mem := (latency => g_ram_latency, + adr_w => g_max_delay, + dat_w => c_dat_w, + nof_dat => 2**g_max_delay, + init_sl => '0'); + + SIGNAL s_count_val : STD_LOGIC_VECTOR(g_max_delay - 1 DOWNTO 0); + SIGNAL s_ram_out : STD_LOGIC_VECTOR(din'RANGE); + SIGNAL s_subtrahend : STD_LOGIC_VECTOR(g_max_delay - 1 DOWNTO 0) := TO_SVEC((g_ram_latency + 1), g_max_delay); + SIGNAL s_minuend : STD_LOGIC_VECTOR(g_max_delay - 1 DOWNTO 0); + SIGNAL s_difference : STD_LOGIC_VECTOR(g_max_delay - 1 DOWNTO 0); + SIGNAL s_count_rst : STD_LOGIC := '0'; +begin +s_minuend <= RESIZE_SVEC(delay,g_max_delay); +-- ASSERT c_max_cnt > 0 REPORT "Delay value must be greater than BRAM latency + 1!" severity FAILURE; + +-------------------------------------------------------- +-- Subtraction +-------------------------------------------------------- + delay_latency_diff : ENTITY casper_adder_lib.common_add_sub + generic map ( + g_direction => "SUB", + g_pipeline_output => 2, + g_in_dat_w => g_max_delay, + g_out_dat_w => g_max_delay + ) + port map ( + clk => clk, + clken => ce, + in_a => s_minuend, + in_b => s_subtrahend, + result => s_difference + ); + +-------------------------------------------------------- +-- a >= b +-------------------------------------------------------- +s_count_rst <= '1' when unsigned(s_count_val) >= unsigned(s_difference) else '0'; + +-------------------------------------------------------- +-- Counter +-------------------------------------------------------- + addr_cntr : ENTITY casper_counter_lib.free_run_up_counter + GENERIC MAP ( + g_cnt_w => g_max_delay, + g_cnt_signed => FALSE + ) + PORT MAP ( + clk => clk, + ce => ce, + reset => s_count_rst, + count => s_count_val + ); + +-------------------------------------------------------- +-- Single Port Ram +-------------------------------------------------------- + delay_spram : ENTITY casper_ram_lib.common_ram_r_w + GENERIC MAP ( + g_ram => c_mem_ram, + g_true_dual_port => FALSE, + g_ram_primitive => g_ram_primitive, + g_port_a_write_mode => "read_first", + g_port_b_write_mode => "read_first" + ) + PORT MAP( + clk => clk, + clken => ce, + wr_en => '1', + wr_adr => s_count_val, + wr_dat => din, + rd_en => '1', + rd_adr => s_count_val, + rd_dat => s_ram_out, + rd_val => open + ); + +-------------------------------------------------------- +-- Send value out +-------------------------------------------------------- + dout <= s_ram_out; +end ARCHITECTURE; \ No newline at end of file diff --git a/casper_delay/delay_bram_prog_dp.vhd b/casper_delay/delay_bram_prog_dp.vhd new file mode 100644 index 00000000..26195a4c --- /dev/null +++ b/casper_delay/delay_bram_prog_dp.vhd @@ -0,0 +1,108 @@ +-- A VHDL implementation of the CASPER delay_bram_prog_dp block. +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +LIBRARY IEEE, common_pkg_lib, casper_counter_lib, casper_ram_lib, casper_adder_lib, common_components_lib; +USE IEEE.std_logic_1164.all; +USE IEEE.numeric_std.all; +USE common_pkg_lib.common_pkg.all; +USE casper_ram_lib.common_ram_pkg.all; +USE common_components_lib.common_components_pkg.all; + +ENTITY delay_bram_prog_dp is + generic( + g_max_delay : NATURAL := 7; -- 2^g_max_delay + g_ram_primitive : STRING := "block"; -- bram primitive + g_ram_latency : NATURAL := 2 -- bram latency. Anything in excess of 1 will be in a delay block + ); + port( + clk : in std_logic; + ce : in std_logic; + din : in std_logic_vector; -- signal to delay + delay : in std_logic_vector; -- variable delay + en : in std_logic := '1'; + dout : out std_logic_vector -- delayed signal + ); +end ENTITY; + +ARCHITECTURE rtl of delay_bram_prog_dp is + CONSTANT c_dat_w : NATURAL := din'LENGTH; + CONSTANT c_mem_ram : t_c_mem := (latency => g_ram_latency, + adr_w => g_max_delay, + dat_w => c_dat_w, + nof_dat => 2 ** g_max_delay, + init_sl => '0'); + + SIGNAL s_count_val : STD_LOGIC_VECTOR(g_max_delay - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL s_ram_out : STD_LOGIC_VECTOR(din'RANGE) := (OTHERS => '0'); + SIGNAL s_subtrahend : STD_LOGIC_VECTOR(g_max_delay - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL s_minuend : STD_LOGIC_VECTOR(g_max_delay - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL s_difference : STD_LOGIC_VECTOR(g_max_delay - 1 DOWNTO 0) := (OTHERS => '0'); + +begin + s_subtrahend <= RESIZE_SVEC(delay, g_max_delay); + s_minuend <= s_count_val; + -------------------------------------------------------- + -- Subtraction + -------------------------------------------------------- + delay_latency_diff : ENTITY casper_adder_lib.common_add_sub + generic map( + g_direction => "SUB", + g_pipeline_output => 1, + g_in_dat_w => g_max_delay, + g_out_dat_w => g_max_delay + ) + port map( + clk => clk, + clken => ce, + in_a => s_minuend, + in_b => s_subtrahend, + result => s_difference + ); + + -------------------------------------------------------- + -- Counter + -------------------------------------------------------- + addr_cntr : entity casper_counter_lib.free_run_up_counter + generic map( + g_cnt_w => g_max_delay, + g_cnt_initial_value => 0, + g_cnt_signed => FALSE + ) + port map( + clk => clk, + ce => ce, + reset => '0', + enable => '1', + count => s_count_val + ); + + -------------------------------------------------------- + -- Dual Port Ram + -------------------------------------------------------- + delay_dpram : ENTITY casper_ram_lib.common_ram_rw_rw + GENERIC MAP( + g_ram => c_mem_ram, + g_ram_primitive => g_ram_primitive, + g_port_a_write_mode => "write_first", + g_port_b_write_mode => "read_first" + ) + PORT MAP( + clk => clk, + clken => ce, + wr_en_a => '1', + wr_en_b => '0', + wr_dat_a => din, + wr_dat_b => din, + adr_a => s_count_val, + adr_b => s_difference, + rd_en_a => '1', + rd_en_b => '1', + rd_dat_a => open, + rd_dat_b => s_ram_out, + rd_val_a => open, + rd_val_b => open + ); + + dout <= s_ram_out; +end ARCHITECTURE; diff --git a/casper_delay/delay_complex.vhd b/casper_delay/delay_complex.vhd new file mode 100644 index 00000000..eff2c3f9 --- /dev/null +++ b/casper_delay/delay_complex.vhd @@ -0,0 +1,168 @@ +-- A VHDL implementation of the CASPER delay_complex block. +-- @company: Mydon Solutions. +-- @author: Ross Donnachie. + +LIBRARY IEEE, common_pkg_lib, casper_misc_lib; +USE IEEE.std_logic_1164.all; +USE common_pkg_lib.common_pkg.all; + +ENTITY delay_complex is + generic ( + g_delay : NATURAL := 3; + g_ram_primitive : STRING := "block"; + g_ram_latency: NATURAL := 2 + ); + port ( + clk : in std_logic; + ce : in std_logic; + din : in std_logic_vector; + dout : out std_logic_vector + ); +end ENTITY; + +ARCHITECTURE rtl of delay_complex is + + SIGNAL s_re_in : std_logic_vector((din'HIGH+1)/2 -1 downto 0); + SIGNAL s_im_in : std_logic_vector(s_re_in'RANGE); + + SIGNAL s_re_out : std_logic_vector(s_re_in'RANGE); + SIGNAL s_im_out : std_logic_vector(s_re_in'RANGE); + +begin + + u_c_split : entity casper_misc_lib.c_to_ri + generic map( + g_async => TRUE, + g_bit_width => din'LENGTH/2 + ) + port map( + clk => clk, + ce => ce, + c_in => din, + re_out => s_re_in, + im_out => s_im_in + ); + + u_delay_bram_re : entity work.delay_bram + generic map ( + g_delay => g_delay, + g_ram_primitive => g_ram_primitive, + g_ram_latency => g_ram_latency + ) + port map ( + clk => clk, + ce => ce, + din => s_re_in, + dout => s_re_out + ); + + u_delay_bram_im : entity work.delay_bram + generic map ( + g_delay => g_delay, + g_ram_primitive => g_ram_primitive, + g_ram_latency => g_ram_latency + ) + port map ( + clk => clk, + ce => ce, + din => s_im_in, + dout => s_im_out + ); + + u_c_combine : entity casper_misc_lib.ri_to_c + generic map( + g_async => TRUE + ) + port map( + clk => clk, + ce => ce, + re_in => s_re_out, + im_in => s_im_out, + c_out => dout + ); + +end architecture; + +LIBRARY IEEE, common_pkg_lib, casper_misc_lib; +USE IEEE.std_logic_1164.all; +USE common_pkg_lib.common_pkg.all; + +ENTITY delay_complex_async is + generic ( + g_delay : NATURAL := 3; + g_ram_primitive : STRING := "block"; + g_ram_latency: NATURAL := 2 + ); + port ( + clk : in std_logic; + ce : in std_logic; + en : in std_logic; + din : in std_logic_vector; + dout : out std_logic_vector + ); +end ENTITY; + +ARCHITECTURE rtl of delay_complex_async is + + SIGNAL s_re_in : std_logic_vector((din'HIGH+1)/2 -1 downto 0); + SIGNAL s_im_in : std_logic_vector(s_re_in'RANGE); + + SIGNAL s_re_out : std_logic_vector(s_re_in'RANGE); + SIGNAL s_im_out : std_logic_vector(s_re_in'RANGE); + +begin + + u_c_split : entity casper_misc_lib.c_to_ri + generic map( + g_async => TRUE, + g_bit_width => din'LENGTH/2 + ) + port map( + clk => clk, + ce => ce, + c_in => din, + re_out => s_re_in, + im_out => s_im_in + ); + + u_delay_bram_re : entity work.delay_bram_async + generic map ( + g_delay => g_delay, + g_ram_primitive => g_ram_primitive, + g_ram_latency => g_ram_latency + ) + port map ( + clk => clk, + ce => ce, + en => en, + din => s_re_in, + dout => s_re_out + ); + + u_delay_bram_im : entity work.delay_bram_async + generic map ( + g_delay => g_delay, + g_ram_primitive => g_ram_primitive, + g_ram_latency => g_ram_latency + ) + port map ( + clk => clk, + ce => ce, + en => en, + din => s_im_in, + dout => s_im_out + ); + + u_c_combine : entity casper_misc_lib.ri_to_c + generic map( + g_async => TRUE + ) + port map( + clk => clk, + ce => ce, + re_in => s_re_out, + im_in => s_im_out, + c_out => dout + ); + +end architecture; \ No newline at end of file diff --git a/casper_delay/delay_simple.vhd b/casper_delay/delay_simple.vhd new file mode 100644 index 00000000..672f85e2 --- /dev/null +++ b/casper_delay/delay_simple.vhd @@ -0,0 +1,78 @@ +-- A VHDL implementation of a simple delay block. +-- @author: Ross Donnachie +-- @company: Mydon Solutions + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +entity delay_simple is + generic ( + g_delay : NATURAL := 1; + g_initial_values : std_logic := '0' + ); + port ( + clk : IN std_logic := '0'; + ce : IN std_logic := '0'; + i_data : IN std_logic_vector; + o_data : out std_logic_vector + ); +end delay_simple; + +architecture rtl of delay_simple is + TYPE t_delay_slv_arr IS ARRAY (0 to g_delay-1) OF STD_LOGIC_VECTOR(i_data'RANGE); + SIGNAL s_delays : t_delay_slv_arr := (OTHERS => (OTHERS => g_initial_values)); +begin + o_data <= s_delays(g_delay-1); + + -------------------------------------------------------- + -- Synchronous operation + -------------------------------------------------------- + sync_process: PROCESS (clk, ce) + begin + if rising_edge(clk) and ce='1' THEN + FOR latency in g_delay-1 downto 1 LOOP + s_delays(latency) <= s_delays(latency-1); + END LOOP; + s_delays(0) <= i_data; + end if; + end PROCESS; + +end architecture; + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +entity delay_simple_sl is + generic ( + g_delay : NATURAL := 1; + g_initial_values : std_logic := '0' + ); + port ( + clk : IN std_logic := '0'; + ce : IN std_logic := '0'; + i_data : IN std_logic; + o_data : out std_logic + ); +end delay_simple_sl; + +architecture rtl of delay_simple_sl is + SIGNAL s_in, s_out : STD_LOGIC_VECTOR(0 to 0); +begin + s_in(0) <= i_data; + o_data <= s_out(0); + + u_sync_delay : entity work.delay_simple + generic map ( + g_delay => g_delay, + g_initial_values => g_initial_values + ) + port map ( + clk => clk, + ce => ce, + i_data => s_in, + o_data => s_out + ); + +end architecture; \ No newline at end of file diff --git a/casper_delay/delay_wideband_prog.vhd b/casper_delay/delay_wideband_prog.vhd new file mode 100644 index 00000000..302a80f1 --- /dev/null +++ b/casper_delay/delay_wideband_prog.vhd @@ -0,0 +1,239 @@ +-- A VHDL implementation of the CASPER delay_wideband_prog block. +-- @author: Talon Myburgh +-- @company: Mydon Solutions +library ieee, common_pkg_lib, casper_reorder_lib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package delay_wideband_prog_pkg is + CONSTANT c_delay_wideband_prog_bit_width : natural := 16; + type t_wideband_delay_prog_inout_bus is array (natural range <>) of std_logic_vector(c_delay_wideband_prog_bit_width - 1 downto 0); +end package delay_wideband_prog_pkg; + +library ieee, common_pkg_lib, common_slv_arr_pkg_lib, casper_reorder_lib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.delay_wideband_prog_pkg.all; +use common_pkg_lib.common_pkg.all; +USE common_slv_arr_pkg_lib.common_slv_arr_pkg.all; + +entity delay_wideband_prog is + generic( + g_max_delay_bits : natural := 10; + g_simultaneous_input_bits : natural := 2; + g_bram_latency : natural := 2; + g_true_dual_port : boolean := true; + g_ram_primitive : string := "block"; + g_async : boolean := false + ); + port( + clk : in std_logic; + ce : in std_logic; + sync : in std_logic; + en : in std_logic := '1'; + delay : in std_logic_vector; + ld_delay : in std_logic; + data_in : in t_wideband_delay_prog_inout_bus(0 to 2 ** g_simultaneous_input_bits - 1); + sync_out : out std_logic; + data_out : out t_wideband_delay_prog_inout_bus(0 to 2 ** g_simultaneous_input_bits - 1); + dvalid : out std_logic := '1' + ); +end entity delay_wideband_prog; + +architecture RTL of delay_wideband_prog is + + constant c_nof_inputs : natural := 2 ** g_simultaneous_input_bits; + constant c_latency : natural := sel_a_b(g_true_dual_port, g_bram_latency + 2, g_bram_latency + 3); + constant c_max_delay : natural := 2 ** g_max_delay_bits - 1; + constant c_ram_bits : natural := ceil_log2(c_max_delay / (2 ** g_simultaneous_input_bits)); + constant c_sync_latency : natural := sel_a_b(not g_true_dual_port, c_latency + (g_bram_latency + 1) * 2 ** g_simultaneous_input_bits, c_latency); + + signal s_en : std_logic_vector(0 DOWNTO 0) := "1"; + signal s_en_delay : std_logic_vector(0 DOWNTO 0) := "1"; + signal s_en_delay_sl : std_logic := '1'; + signal s_delay_reg : std_logic_vector(g_max_delay_bits - 1 downto 0) := (others => '0'); + signal s_shift_sel : std_logic_vector(g_simultaneous_input_bits - 1 downto 0) := (others => '0'); + signal s_delay_sel : std_logic_vector(g_simultaneous_input_bits - 1 downto 0) := (others => '0'); + signal s_sync : std_logic_vector(0 DOWNTO 0) := (others => '0'); + signal s_barrel_switcher_input : t_slv_arr(c_nof_inputs - 1 DOWNTO 0, c_delay_wideband_prog_bit_width - 1 DOWNTO 0) := (others => (others => '0')); + signal s_barrel_switcher_output : t_slv_arr(c_nof_inputs - 1 DOWNTO 0, c_delay_wideband_prog_bit_width - 1 DOWNTO 0) := (others => (others => '0')); + signal s_barrel_switcher_sync : std_logic_vector(0 DOWNTO 0) := (others => '0'); + signal s_bram_rd_addrs : std_logic_vector(c_ram_bits - 1 downto 0) := (others => '0'); + type t_signal_array is array (0 to c_nof_inputs - 1) of std_logic_vector(0 downto 0); + signal s_a_g_b_value : t_signal_array := (others => (others => '0')); + signal s_delay_a_g_b_value : t_signal_array := (others => (others => '0')); + type t_ab_signal_array is array (1 to c_nof_inputs - 1) of std_logic_vector(c_ram_bits downto 0); + signal s_delay_a_g_b_sum : t_ab_signal_array := (others => (others => '0')); + signal s_delay_dout : t_wideband_delay_prog_inout_bus(0 to c_nof_inputs - 1) := (others => (others => '0')); + signal s_dvalid : std_logic := '0'; + +begin + s_sync(0) <= sync; + s_en(0) <= en; + --------------------------REGISTER DELAY VALUE----------------------------------- + process(clk) + begin + if rising_edge(clk) then + if ce = '1' then + if ld_delay = '1' then + s_delay_reg <= delay; + end if; + end if; + end if; + end process; + + s_shift_sel <= s_delay_reg(g_simultaneous_input_bits - 1 downto 0); + s_bram_rd_addrs <= s_delay_reg(c_ram_bits + g_simultaneous_input_bits - 1 DOWNTO g_simultaneous_input_bits); + + ---------------DELAY SHIFT SELECT BY c_latency----------------------- + delay_simple_inst : entity work.delay_simple + generic map( + g_delay => c_latency + ) + port map( + clk => clk, + ce => ce, + i_data => s_shift_sel, + o_data => s_delay_sel + ); + + -------------DELAY SYNC BY c_sync_latency--------------------------------- + delay_sync_inst : entity work.delay_simple + generic map( + g_delay => c_sync_latency + ) + port map( + clk => clk, + ce => ce, + i_data => s_sync, + o_data => s_barrel_switcher_sync + ); + + -------------DELAY SYNC BY c_sync_latency--------------------------------- + delay_en_inst : entity work.delay_simple + generic map( + g_delay => c_sync_latency + ) + port map( + clk => clk, + ce => ce, + i_data => s_en, + o_data => s_en_delay + ); + + ------------------GENERATE BARREL SWITCHER INPUTS-------------------------------- + gen_delay_input_2_onwards : for i in 1 to c_nof_inputs - 1 generate + s_a_g_b_value(i) <= "1" when unsigned(s_shift_sel) > to_unsigned(c_nof_inputs - i - 1, g_simultaneous_input_bits) else "0"; + -- now delay s_a_g_b_value by 1 clock cycle: + process(clk) + begin + if rising_edge(clk) then + if ce = '1' then + s_delay_a_g_b_value <= s_a_g_b_value; + end if; + end if; + end process; + s_delay_a_g_b_sum(i) <= RESIZE_UVEC(std_logic_vector(unsigned(s_delay_a_g_b_value(i)) + unsigned(s_bram_rd_addrs)),c_ram_bits+1); + end generate gen_delay_input_2_onwards; + + gen_delays : for i in 0 to c_nof_inputs - 1 generate + gen_din_0 : if i = 0 generate + gen_dp_bram_delay : if g_true_dual_port generate + delay_bram_prog_dp_inst : entity work.delay_bram_prog_dp + generic map( + g_max_delay => c_ram_bits, + g_ram_primitive => g_ram_primitive, + g_ram_latency => g_bram_latency + ) + port map( + clk => clk, + ce => ce, + din => data_in(i), + delay => s_bram_rd_addrs, + en => '1', + dout => s_delay_dout(i) + ); + end generate gen_dp_bram_delay; + gen_sp_bram_delay : if not g_true_dual_port generate + delay_bram_prog_inst : entity work.delay_bram_prog + generic map( + g_max_delay => c_ram_bits, + g_ram_primitive => g_ram_primitive, + g_ram_latency => g_bram_latency + ) + port map( + clk => clk, + ce => ce, + din => data_in(i), + delay => s_bram_rd_addrs, + dout => s_delay_dout(i) + ); + end generate gen_sp_bram_delay; + end generate gen_din_0; + + gen_din_others : if i > 0 generate + gen_dp_bram_delay : if g_true_dual_port generate + delay_bram_prog_dp_inst : entity work.delay_bram_prog_dp + generic map( + g_max_delay => c_ram_bits, + g_ram_primitive => g_ram_primitive, + g_ram_latency => g_bram_latency + ) + port map( + clk => clk, + ce => ce, + din => data_in(i), + delay => s_delay_a_g_b_sum(i), + en => '1', + dout => s_delay_dout(i) + ); + end generate gen_dp_bram_delay; + gen_sp_bram_delay : if not g_true_dual_port generate + delay_bram_prog_inst : entity work.delay_bram_prog + generic map( + g_max_delay => c_ram_bits, + g_ram_primitive => g_ram_primitive, + g_ram_latency => g_bram_latency + ) + port map( + clk => clk, + ce => ce, + din => data_in(i), + delay => s_delay_a_g_b_sum(i), + dout => s_delay_dout(i) + ); + end generate gen_sp_bram_delay; + end generate gen_din_others; + end generate gen_delays; + + gen_map_barrel_switcher_input : for i in 0 to c_nof_inputs - 1 generate + gen_map_bits_to_slv : for j in 0 to c_delay_wideband_prog_bit_width - 1 generate + s_barrel_switcher_input(i, j) <= s_delay_dout(c_nof_inputs - i - 1)(j); + end generate gen_map_bits_to_slv; + end generate gen_map_barrel_switcher_input; + + s_en_delay_sl <= s_en_delay(0); + + barrel_switcher_inst : entity casper_reorder_lib.barrel_switcher + generic map( + g_async => g_async + ) + port map( + clk => clk, + ce => ce, + en => s_en_delay_sl, + i_sel => s_delay_sel, + i_sync => s_barrel_switcher_sync(0), + i_data => s_barrel_switcher_input, + o_data => s_barrel_switcher_output, + o_sync => sync_out, + dvalid => s_dvalid + ); + + dvalid <= sel_a_b(g_async, s_dvalid, '0'); + gen_reorder_output : for i in 0 to c_nof_inputs - 1 generate + data_out(i) <= slv_arr_index(s_barrel_switcher_output, c_nof_inputs - 1 - i); + end generate gen_reorder_output; + +end architecture RTL; + diff --git a/casper_delay/delay_wideband_prog_model.py b/casper_delay/delay_wideband_prog_model.py new file mode 100644 index 00000000..35023342 --- /dev/null +++ b/casper_delay/delay_wideband_prog_model.py @@ -0,0 +1,59 @@ +""" +The radio astronomy delay_wideband_prog module is parameterized by the number of streams - hereafter referred to as nof_streams. +""" + +import numpy as np + +def delay_wideband_prog_model(simultaneous_input_bits, delay_cycles): + """ + Generate input and output files for the delay module where the output is delayed by delay_cycles. + Args: + simultaneous_input_bits (int): Number of inputs = 2^simultaneous_input_bits + delay_cycles (int): Number of clock cycles to delay the inputs + Returns: + input_filename (str): Filename of the input file + output_filename (str): Filename of the output + """ + nof_values = 500 + nof_streams = int(2**simultaneous_input_bits) + # Only needs to be a nof_values long. + aranged_data = np.arange(1, nof_values+1, dtype=int) + input_len = aranged_data.size + input_data = np.vstack([aranged_data for _ in range(nof_streams)]) + input_data = np.atleast_2d(input_data.copy()).T # Ensure input_data is at least 2D and transpose to get the correct shape + # Generate expected output data. This is just going to be a file with the input data delayed by delay_cycles (padded with zeros) + zero_pad = np.zeros(delay_cycles, dtype=int) + out_stream_data = np.concatenate((zero_pad, input_data.flatten())) + output_len = out_stream_data.size + remainder = output_len % nof_streams + if remainder != 0: + padding = np.zeros(nof_streams - remainder, dtype=int) + out_stream_data = np.concatenate((out_stream_data, padding)) + output_data = out_stream_data.reshape((-1, nof_streams)) + output_data = np.atleast_2d(output_data.copy()) # Ensure input_data is at least 2D and transpose to get the correct shape + + # Write only nof_values/wideband_factor lines to file. Columns are nof_values/wideband_factor long and there are nof_streams*wideband_factor columns + input_filename = f"delay_input_{nof_streams}_{delay_cycles}.dat" + with open(input_filename, 'w') as f: + for i in range(input_len): + i_dat = input_data[i,:] + f.write(','.join(map(str, i_dat)) + '\n') + + # Write output data to file. Rows are 500 + delay_cycles long, columns are nof_streams long and values are comma separated + output_filename = f"delay_output_{nof_streams}_{delay_cycles}.dat" + with open(output_filename, 'w') as f: + for i in range(output_data.shape[0]): + o_dat = output_data[i,:] + f.write(','.join(map(str, o_dat)) + '\n') + + return input_filename, output_filename + +if __name__ == "__main__": + import argparse + parser = argparse.ArgumentParser(description='Generate input/output files for the delay_wideband_prog model') + parser.add_argument('--siml-in-bits', type=int, help='Number of inputs = 2^siml-in-bits') + parser.add_argument('--delay-cycles', type=int, help='Number of clock cycles to delay the inputs') + args = parser.parse_args() + input_filename, output_filename = delay_wideband_prog_model(args.siml_in_bits, args.delay_cycles) + print(f"Input file: {input_filename}") + print(f"Output file: {output_filename}") diff --git a/casper_delay/partial_delay_prog.vhd b/casper_delay/partial_delay_prog.vhd new file mode 100644 index 00000000..fb670d2a --- /dev/null +++ b/casper_delay/partial_delay_prog.vhd @@ -0,0 +1,83 @@ +-- A VHDL implementation of a partial programmable delay block. +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +library ieee, common_pkg_lib, casper_reorder_lib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use common_pkg_lib.common_pkg.all; +use casper_reorder_lib.variable_mux_pkg.all; + +entity partial_delay_prog is + generic( + g_async : boolean := FALSE; + g_num_ports : integer := 2; + g_mux_latency : natural := 4 + ); + port( + clk : in std_logic; + ce : in std_logic; + en : in std_logic := '1'; + delay : in std_logic_vector; + din : in t_mux_data_array(g_num_ports - 1 downto 0); + dout : out t_mux_data_array(g_num_ports - 1 downto 0) + ); +end entity partial_delay_prog; + +architecture RTL of partial_delay_prog is + + constant c_mux_latency : natural := sel_a_b(g_mux_latency > 0, g_mux_latency - 1, 0); -- overall mux latency must always be at least 1 + + signal s_delay_din : t_mux_data_array(g_num_ports - 1 downto 0) := (others => (others => '0')); -- delayed din + signal s_mux_din : t_mux_data_array(g_num_ports * g_num_ports - 1 downto 0); -- all of the input data ports for the mux's + signal s_mux_dout : t_mux_data_array(g_num_ports - 1 downto 0) := (others => (others=>'0')); -- all of the output data ports for the mux's + +begin + + -- REGISTER din for 1 clock: + register_din : process(clk) is + begin + if rising_edge(clk) and ce = '1' then + s_delay_din <= din; + end if; + end process register_din; + + create_muxs : for i in 0 to g_num_ports - 1 generate + variable_mux_inst : entity casper_reorder_lib.variable_mux + generic map( + g_async => g_async, + g_num_ports => g_num_ports, + g_mux_latency => c_mux_latency - 1 --one goes to the + ) + port map( + clk => clk, + ce => ce, + en => en, + i_sel => delay, + i_data => s_mux_din((i + 1) * g_num_ports - 1 DOWNTO i * g_num_ports), -- all of the input data ports for the mux's + o_data => s_mux_dout(i) + ); + end generate create_muxs; + + -- Connect the input data ports to the mux's bus interface: + process(clk) + begin + if rising_edge(clk) then + if ce = '1' then + for j in 0 to g_num_ports - 1 loop + s_mux_din(j * g_num_ports) <= s_delay_din(j); + for k in 1 to g_num_ports - 1 loop + if j + k <= g_num_ports - 1 then + s_mux_din(j * g_num_ports + k) <= s_delay_din(j + k); --delayed din + else + s_mux_din(j * g_num_ports + k) <= din(j + k - g_num_ports); --not delayed din + end if; + end loop; + end loop; + end if; + end if; + end process; + + dout <= s_mux_dout; + +end architecture RTL; diff --git a/casper_delay/pipeline.vhd b/casper_delay/pipeline.vhd new file mode 100644 index 00000000..1149089b --- /dev/null +++ b/casper_delay/pipeline.vhd @@ -0,0 +1,47 @@ +-- A VHDL implementation of the pipeline block. +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +LIBRARY IEEE, common_pkg_lib; +USE IEEE.std_logic_1164.ALL; +USE common_pkg_lib.common_pkg.ALL; + +ENTITY pipeline IS + GENERIC( + g_pipeline : NATURAL := 1 --! 0 for wires, > 0 for registers, + ); + PORT( + clk : IN STD_LOGIC; --! Input clock signal + ce : IN STD_LOGIC := '1'; --! Enable clock + in_dat : IN STD_LOGIC_VECTOR; --! Input data + out_dat : OUT STD_LOGIC_VECTOR --! Output data + ); +END pipeline; + +ARCHITECTURE rtl OF pipeline IS + + CONSTANT c_bit_width : NATURAL := in_dat'LENGTH; + + CONSTANT c_reset_value : STD_LOGIC_VECTOR(in_dat'RANGE) := TO_SVEC(0, c_bit_width); + + TYPE t_out_dat IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(in_dat'RANGE); + + SIGNAL out_dat_p : t_out_dat(0 TO g_pipeline) := (OTHERS => c_reset_value); + +BEGIN + + gen_pipe_n : IF g_pipeline > 0 GENERATE + p_clk : PROCESS(clk) + BEGIN + IF rising_edge(clk) THEN + IF ce = '1' THEN + out_dat_p(1 TO g_pipeline) <= out_dat_p(0 TO g_pipeline - 1); + END IF; + END IF; + END PROCESS; + END GENERATE; + + out_dat_p(0) <= in_dat; + + out_dat <= out_dat_p(g_pipeline); +END rtl; diff --git a/casper_delay/run.py b/casper_delay/run.py new file mode 100644 index 00000000..06114add --- /dev/null +++ b/casper_delay/run.py @@ -0,0 +1,162 @@ +from vunit import VUnit +from os.path import dirname, join +from itertools import product +import numpy as np + +# Create VUnit instance by parsing command line arguments +vu = VUnit.from_argv() +vu.add_vhdl_builtins() +script_dir = dirname(__file__) + +# XPM Library compile +lib_xpm = vu.add_library("xpm") +lib_xpm.add_source_files(join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_VCOMP.vhd")) +xpm_source_file_base = lib_xpm.add_source_file(join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_base.vhd")) +xpm_source_file_sdpram = lib_xpm.add_source_file(join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_sdpram.vhd")) +xpm_source_file_tdpram = lib_xpm.add_source_file(join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_tdpram.vhd")) +xpm_source_file_sdpram.add_dependency_on(xpm_source_file_base) +xpm_source_file_tdpram.add_dependency_on(xpm_source_file_base) + +# Altera_mf library +lib_altera_mf = vu.add_library("altera_mf") +lib_altera_mf.add_source_files(join(script_dir, "../intel/altera_mf/altera_mf_components.vhd")) +altera_mf_source_file = lib_altera_mf.add_source_files(join(script_dir, "../intel/altera_mf/altera_mf.vhd")) + +# Create library 'casper_counter_lib' +casper_counter_lib = vu.add_library("casper_counter_lib") +casper_counter_lib.add_source_files(join(script_dir,"../casper_counter/common_counter.vhd")) +casper_counter_lib.add_source_files(join(script_dir,"../casper_counter/free_run_up_counter.vhd")) + +# Create library 'common_pkg_lib' +common_pkg_lib = vu.add_library("common_pkg_lib") +common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/fixed_float_types_c.vhd")) +common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/fixed_pkg_c.vhd")) +common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/float_pkg_c.vhd")) +common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/common_pkg.vhd")) + +# Create library 'ip_xpm_ram_lib' +ip_xpm_ram_lib = vu.add_library("ip_xpm_ram_lib") +ip_xpm_file_cr_cw = ip_xpm_ram_lib.add_source_files(join(script_dir, "../ip_xpm/ram/ip_xpm_ram_cr_cw.vhd")) +ip_xpm_file_cr_cw.add_dependency_on(xpm_source_file_sdpram) +ip_xpm_file_crw_crw = ip_xpm_ram_lib.add_source_files(join(script_dir, "../ip_xpm/ram/ip_xpm_ram_crw_crw.vhd")) +ip_xpm_file_crw_crw.add_dependency_on(xpm_source_file_tdpram) + +# STRATIXIV RAM Library +ip_stratixiv_ram_lib = vu.add_library("ip_stratixiv_ram_lib") +ip_stratix_file_cr_cw = ip_stratixiv_ram_lib.add_source_file(join(script_dir, "../ip_stratixiv/ram/ip_stratixiv_ram_cr_cw.vhd")) +ip_stratix_file_crw_crw = ip_stratixiv_ram_lib.add_source_file(join(script_dir, "../ip_stratixiv/ram/ip_stratixiv_ram_crw_crw.vhd")) +ip_stratix_file_cr_cw.add_dependency_on(altera_mf_source_file) +ip_stratix_file_crw_crw.add_dependency_on(altera_mf_source_file) +# CASPER adder library +casper_adder_lib = vu.add_library("casper_adder_lib") +casper_adder_lib.add_source_file(join(script_dir, "../casper_adder/common_add_sub.vhd")) + +# COMMON COMPONENTS Library +common_components_lib = vu.add_library("common_components_lib") +common_components_lib.add_source_files(join(script_dir, "../common_components/common_pipeline.vhd")) +common_components_lib.add_source_files(join(script_dir, "../common_components/common_pipeline_sl.vhd")) +common_components_lib.add_source_files(join(script_dir, "../common_components/common_delay.vhd")) +common_components_lib.add_source_files(join(script_dir, "../common_components/common_components_pkg.vhd")) + +# Create library 'casper_ram_lib' +casper_ram_lib = vu.add_library("casper_ram_lib") +casper_ram_lib.add_source_files(join(script_dir, "../casper_ram/common_ram_pkg.vhd")) +casper_ram_lib.add_source_files(join(script_dir, "../casper_ram/tech_memory_component_pkg.vhd")) +casper_ram_lib.add_source_files(join(script_dir, "../casper_ram/tech_memory_ram_crw_crw.vhd")) +casper_ram_lib.add_source_files(join(script_dir, "../casper_ram/tech_memory_ram_cr_cw.vhd")) +casper_ram_lib.add_source_files(join(script_dir, "../casper_ram/common_ram_crw_crw.vhd")) +casper_ram_lib.add_source_files(join(script_dir, "../casper_ram/common_ram_rw_rw.vhd")) +casper_ram_lib.add_source_files(join(script_dir, "../casper_ram/common_ram_r_w.vhd")) + +# Create library 'technology_lib' +technology_lib = vu.add_library("technology_lib") +technology_lib.add_source_files(join(script_dir, "../technology/technology_select_pkg.vhd")) + +casper_misc_lib = vu.add_library("casper_misc_lib") +casper_misc_lib.add_source_files(join(script_dir, "../misc/ri_to_c.vhd")) +casper_misc_lib.add_source_files(join(script_dir, "../misc/c_to_ri.vhd")) +casper_misc_lib.add_source_files(join(script_dir, "../misc/concat.vhd")) +casper_misc_lib.add_source_files(join(script_dir, "../misc/edge_detect.vhd")) + +# Create library 'casper_delay_lib' +casper_delay_lib = vu.add_library("casper_delay_lib") +casper_delay_lib.add_source_files(join(script_dir, "./*delay_simple.vhd")) +casper_delay_lib.add_source_files(join(script_dir, "./*delay_bram.vhd")) +casper_delay_lib.add_source_files(join(script_dir, "./*delay_bram_en_plus.vhd")) +casper_delay_lib.add_source_files(join(script_dir, "./*delay_bram_prog.vhd")) +casper_delay_lib.add_source_files(join(script_dir, "./*delay_bram_prog_dp.vhd")) +casper_delay_lib.add_source_files(join(script_dir, "./*sync_delay.vhd")) +casper_delay_lib.add_source_files(join(script_dir, "./*window_delay.vhd")) + +DELAY_SIMPLE_TB = casper_delay_lib.test_bench("tb_tb_vu_delay_simple") +DELAY_BRAM_TB = casper_delay_lib.test_bench("tb_tb_vu_delay_bram") +DELAY_BRAM_EN_PLUS_TB = casper_delay_lib.test_bench("tb_tb_vu_delay_bram_en_plus") +DELAY_BRAM_PROG_TB = casper_delay_lib.test_bench("tb_tb_vu_delay_bram_prog") +DELAY_BRAM_PROG_DP_TB = casper_delay_lib.test_bench("tb_tb_vu_delay_bram_prog_dp") +SYNC_DELAY_TB = casper_delay_lib.test_bench("tb_tb_vu_sync_delay") +WINDOW_DELAY_TB = casper_delay_lib.test_bench("tb_tb_vu_window_delay") + +# no maths done, so some random picks are fine +delay_arr = [4, 10, 50] +bram_latencies = [1, 2] +dat_widths = [4, 18, 32] +latencies = [2,8] + +for delay, dat_w in product(delay_arr, dat_widths): + db_config_name = "DELAY_SIMPLE: delay=%s, dat_w=%s" %(delay, dat_w) + DELAY_SIMPLE_TB.add_config( + name = db_config_name, + generics=dict(g_delay=delay, g_vec_w = dat_w) + ) + +# for delay, latency, dat_w in product(delay_arr, bram_latencies, dat_widths): +# db_config_name = "DELAY_BRAM: delay=%s, latency=%s, dat_w=%s" %(delay, latency, dat_w) +# DELAY_BRAM_TB.add_config( +# name = db_config_name, +# generics=dict(g_delay=delay, g_latency=latency, g_vec_w = dat_w) +# ) +# for delay, latency, dat_w in product(delay_arr, latencies, dat_widths): +# db_en_plus_config_name = "DELAY_BRAM EN PLUS: delay=%s, latency=%s, dat_w=%s" %(delay, latency, dat_w) +# DELAY_BRAM_EN_PLUS_TB.add_config( +# name = db_en_plus_config_name, +# generics=dict(g_delay=delay, g_latency=latency, g_vec_w = dat_w) +# ) +testnum = 1 +for delay, latency, dat_w in product(delay_arr, latencies, dat_widths): + db_prog_config_name = "DELAY_BRAM PROG: delay=%s, latency=%s, dat_w=%s" %(delay,latency,dat_w) + db_prog_dp_config_name = "DELAY_BRAM PROG_DP: delay=%s, latency=%s, dat_w=%s" %(delay,latency,dat_w) + db_en_plus_config_name = "DELAY_BRAM EN PLUS: delay=%s, latency=%s, dat_w=%s" %(delay, latency, dat_w) + db_config_name = "DELAY_BRAM: delay=%s, latency=%s, dat_w=%s" %(delay, latency, dat_w) + DELAY_BRAM_EN_PLUS_TB.add_config( + name = db_en_plus_config_name, + generics=dict(g_delay=delay, g_latency=latency, g_vec_w = dat_w) + ) + DELAY_BRAM_PROG_TB.add_config( + name = db_prog_config_name, + generics=dict(g_max_delay = np.ceil(np.log2(delay)).astype(np.int64), g_ram_latency = latency, g_vec_w = dat_w) + ) + DELAY_BRAM_PROG_DP_TB.add_config( + name = db_prog_dp_config_name, + generics=dict(g_max_delay = np.ceil(np.log2(delay)).astype(np.int64), g_ram_latency = latency, g_vec_w = dat_w) + ) + DELAY_BRAM_TB.add_config( + name = db_config_name, + generics=dict(g_delay=delay, g_latency=latency, g_vec_w = dat_w) + ) + +for delay in delay_arr: + ds_config_name = "DELAY_SYNC: delay=%s" % (delay) + SYNC_DELAY_TB.add_config( + name = ds_config_name, + generics=dict(g_delay=delay) + ) + wndow_config_name = "DELAY_WINDOW: delay=%s" % (delay) + WINDOW_DELAY_TB.add_config( + name = wndow_config_name, + generics=dict(g_delay=delay) + ) + +vu.set_compile_option("ghdl.a_flags", ["-frelaxed", "-fsynopsys", "-fexplicit", "-Wno-hide"]) +vu.set_sim_option("ghdl.elab_flags", ["-frelaxed", "-fsynopsys", "-fexplicit", "--syn-binding"]) +vu.set_sim_option("ghdl.sim_flags", ["--ieee-asserts=disable"]) +vu.main() diff --git a/casper_delay/sync_delay.vhd b/casper_delay/sync_delay.vhd new file mode 100644 index 00000000..519137da --- /dev/null +++ b/casper_delay/sync_delay.vhd @@ -0,0 +1,84 @@ +-- Delay an infrequent boolean pulse by the specified number of clocks. +-- @author: Talon Myburgh +-- @company: Mydon Solutions +library ieee, common_pkg_lib, casper_counter_lib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use common_pkg_lib.common_pkg.all; + +entity sync_delay is + generic( + g_delay : natural := 4; + g_async : boolean := false; + g_use_delay_port : boolean := false + ); + port( + clk : in std_logic; + ce : in std_logic; + en : in std_logic := '0'; + din : in std_logic; + delay : in std_logic_vector; + dout : out std_logic + ); +end entity sync_delay; + +architecture RTL of sync_delay is + + constant c_ceil_log2 : NATURAL := sel_a_b(g_use_delay_port, delay'length, ceil_log2(g_delay)); --when using delay port, use its width, otherwise use the width of the delay value + constant c_cnt_gen_w : NATURAL := sel_a_b(2 > c_ceil_log2, 2, c_ceil_log2); --max(2, ceil_log2(g_delay)) + constant c_cnt_w : NATURAL := sel_a_b(g_use_delay_port, delay'length, c_cnt_gen_w); --when using delay port, use its width, otherwise use the width of the delay value + + signal s_count : std_logic_vector(c_cnt_w - 1 downto 0) := TO_UVEC(2 ** c_cnt_w, c_cnt_w); + signal s_cnt_gen_load : std_logic_vector(c_cnt_w - 1 downto 0) := TO_UVEC(g_delay, c_cnt_w); + signal s_cnt_load : std_logic_vector(c_cnt_w - 1 downto 0); + signal s_or_out : std_logic := '0'; + signal s_a_neq_b : std_logic := '0'; + signal s_cnt_en : std_logic := '0'; + signal s_or_out_and_en : std_logic := '0'; + signal s_a_eq_b : std_logic := '0'; + signal s_zero : std_logic_vector(c_cnt_w - 1 downto 0) := TO_UVEC(0, c_cnt_w); + signal s_one : std_logic_vector(c_cnt_w - 1 downto 0) := TO_UVEC(1, c_cnt_w); + signal s_sel : std_logic := sel_a_b(g_delay = 0, '0', '1'); --bypass logic for zero delay +begin + s_cnt_load <= sel_a_b(g_use_delay_port, delay, s_cnt_gen_load); + ------------------------------------------------------------ + -- COUNTER + counter : entity casper_counter_lib.common_counter + generic map( + g_latency => 1, + g_init => 0, + g_width => c_cnt_w, + g_max => 0, + g_step_size => -1 + ) + port map( + clk => clk, + clken => ce, + cnt_ld => din, + cnt_en => s_cnt_en, + load => s_cnt_load, + count => s_count + ); + ------------------------------------------------------------ + ------------------------------------------------------------ + -- OR + s_or_out <= din or s_a_neq_b; + + -- NEQ + s_a_neq_b <= sel_a_b(s_zero = s_count, '0', '1'); + + gen_async_path : if g_async generate + s_or_out_and_en <= s_or_out and en; + s_cnt_en <= s_or_out_and_en or din; + end generate gen_async_path; + + gen_synch_path : if not g_async generate + s_cnt_en <= s_or_out; + end generate gen_synch_path; + -- EQ + s_a_eq_b <= sel_a_b(s_one = s_count, '1', '0'); + ------------------------------------------------------------ + -- MUX + dout <= s_a_eq_b when s_sel = '1' else din; + +end architecture RTL; diff --git a/casper_delay/tb_delay_bram.vhd b/casper_delay/tb_delay_bram.vhd new file mode 100644 index 00000000..46640663 --- /dev/null +++ b/casper_delay/tb_delay_bram.vhd @@ -0,0 +1,114 @@ +-- A VHDL testbench for delaybram.vhd. +-- @author: Mydon Solutions. + +LIBRARY IEEE, std, common_pkg_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +USE STD.TEXTIO.ALL; + +entity tb_delay_bram is + generic ( + g_delay : NATURAL := 6; + g_latency : NATURAL := 2; + g_vec_w : NATURAL := 8 + ); + port ( + o_clk : out std_logic; + o_tb_end : out std_logic; + o_test_msg : out STRING(1 to 80); + o_test_pass : out BOOLEAN + ); +end entity tb_delay_bram; + +architecture rtl of tb_delay_bram is + + CONSTANT clk_period : TIME := 10 ns; + + SIGNAL clk : std_logic := '0'; + SIGNAL ce : std_logic; + SIGNAL en : std_logic; + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL in_del_vec : std_logic_vector(g_vec_w -1 DOWNTO 0) := (others => '1'); + SIGNAL zeros : std_logic_vector(g_vec_w -1 DOWNTO 0) := (others => '0'); + SIGNAL out_del_vec : std_logic_vector(g_vec_w -1 DOWNTO 0); + SIGNAL out_del_vec_async : std_logic_vector(g_vec_w -1 DOWNTO 0); + +begin + clk <= NOT clk OR tb_end AFTER clk_period / 2; + + o_clk <= clk; + o_tb_end <= tb_end; + +--------------------------------------------------------------------- +-- Delay BRAM module +--------------------------------------------------------------------- +delay_bram : ENTITY work.delay_bram +generic map( + g_delay => g_delay, + g_ram_latency => g_latency + ) + port map( + clk => clk, + ce => ce, + din => in_del_vec, + dout => out_del_vec + ); + +--------------------------------------------------------------------- +-- Delay BRAM async module +--------------------------------------------------------------------- + async_delay_bram : ENTITY work.delay_bram_async + generic map( + g_delay => g_delay, + g_ram_latency => g_latency + ) + port map( + clk => clk, + ce => ce, + en => en, + din => in_del_vec, + dout => out_del_vec_async + ); + +--------------------------------------------------------------------- +-- Stimulus process +--------------------------------------------------------------------- +p_stimuli_verify : PROCESS + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + VARIABLE v_test_pass : BOOLEAN := True; +BEGIN + WAIT for clk_period*2; + ce <= '1'; + en <= '1'; + -- Check delay delays by the correct duration + WAIT for clk_period * g_delay; + WAIT UNTIL rising_edge(clk); + v_test_pass := out_del_vec = in_del_vec; + IF not v_test_pass THEN + v_test_msg := pad("wrong RTL result for bram delay, expected: " & to_hstring(in_del_vec) & " but got: " & to_hstring(out_del_vec), o_test_msg'length, '.' ); + REPORT "ERROR: " & v_test_msg severity error; + END IF; + -- Check async delay delays by the correct duration + v_test_pass := out_del_vec_async = in_del_vec; + IF not v_test_pass THEN + v_test_msg := pad("wrong RTL result for async bram delay, expected: " & to_hstring(in_del_vec) & " but got: " & to_hstring(out_del_vec_async), o_test_msg'length, '.' ); + REPORT "ERROR: " & v_test_msg severity error; + END IF; + -- Check asynchronous behaviour of async delay block resetting within on clk_period + en <= '0'; + WAIT for clk_period; + WAIT UNTIL rising_edge(clk); + v_test_pass := out_del_vec_async = zeros; + IF not v_test_pass THEN + v_test_msg := pad("wrong RTL result for async bram delay, expected: " & to_hstring(zeros) & " but got: " & to_hstring(out_del_vec_async), o_test_msg'length, '.' ); + REPORT "ERROR: " & v_test_msg severity error; + END IF; + in_del_vec <= (others=>'0'); + o_test_msg <= v_test_msg; + o_test_pass <= v_test_pass; + tb_end <= '1'; + WAIT; +END PROCESS; + +end architecture; \ No newline at end of file diff --git a/casper_delay/tb_delay_bram_en_plus.vhd b/casper_delay/tb_delay_bram_en_plus.vhd new file mode 100644 index 00000000..124bd045 --- /dev/null +++ b/casper_delay/tb_delay_bram_en_plus.vhd @@ -0,0 +1,93 @@ +-- A VHDL testbench for delay_bram_en_plus.vhd. +-- @author: Mydon Solutions. + +LIBRARY IEEE, std, common_pkg_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +USE STD.TEXTIO.ALL; + +entity tb_delay_bram_en_plus is + generic ( + g_delay : NATURAL := 8; + g_latency : NATURAL := 4; + g_vec_w : NATURAL := 8 + ); + port ( + o_clk : out std_logic; + o_tb_end : out std_logic; + o_test_msg : out STRING(1 to 80); + o_test_pass : out BOOLEAN + ); +end entity tb_delay_bram_en_plus; + +architecture rtl of tb_delay_bram_en_plus is + + CONSTANT clk_period : TIME := 10 ns; + + SIGNAL clk : std_logic := '0'; + SIGNAL set_val : std_logic_vector(0 DOWNTO 0) := (others =>'1'); + SIGNAL ce : std_logic; + SIGNAL en : std_logic; + SIGNAL s_valid : std_logic_vector(0 DOWNTO 0); + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL in_del_vec : std_logic_vector(g_vec_w -1 DOWNTO 0) := (others => '1'); + SIGNAL zeros : std_logic_vector(g_vec_w -1 DOWNTO 0) := (others => '0'); + SIGNAL out_del_vec : std_logic_vector(g_vec_w -1 DOWNTO 0); + +begin + clk <= NOT clk OR tb_end AFTER clk_period / 2; + + o_clk <= clk; + o_tb_end <= tb_end; + +--------------------------------------------------------------------- +-- Delay BRAM module +--------------------------------------------------------------------- +delay_bram : ENTITY work.delay_bram_en_plus +generic map( + g_delay => g_delay, + g_latency => g_latency + ) + port map( + clk => clk, + ce => ce, + en => en, + din => in_del_vec, + valid => s_valid(0), + dout => out_del_vec + ); + +--------------------------------------------------------------------- +-- Stimulus process +--------------------------------------------------------------------- +p_stimuli_verify : PROCESS + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + VARIABLE v_test_pass : BOOLEAN := True; +BEGIN + WAIT for clk_period*2; + ce <= '1'; + en <= '1'; + -- Check delay delays by the correct duration + WAIT for clk_period * g_latency; + WAIT UNTIL rising_edge(clk); + -- Check that valid is high + v_test_pass := s_valid = "1"; + IF not v_test_pass THEN + v_test_msg := pad("wrong RTL result for valid signal, expected: " & to_hstring(set_val) & " but got: " & to_hstring(s_valid), o_test_msg'length, '.' ); + REPORT "ERROR: " & v_test_msg severity error; + END IF; + WAIT for clk_period * g_delay; + WAIT UNTIL rising_edge(clk); + v_test_pass := out_del_vec = in_del_vec; + IF not v_test_pass THEN + v_test_msg := pad("wrong RTL result for dout, expected: " & to_hstring(in_del_vec) & " but got: " & to_hstring(out_del_vec), o_test_msg'length, '.' ); + REPORT "ERROR: " & v_test_msg severity error; + END IF; + o_test_msg <= v_test_msg; + o_test_pass <= v_test_pass; + tb_end <= '1'; + WAIT; +END PROCESS; + +end architecture; \ No newline at end of file diff --git a/casper_delay/tb_delay_bram_prog.vhd b/casper_delay/tb_delay_bram_prog.vhd new file mode 100644 index 00000000..f07dcb21 --- /dev/null +++ b/casper_delay/tb_delay_bram_prog.vhd @@ -0,0 +1,97 @@ +-- A VHDL testbench for delay_bram_prog.vhd. +-- @author: Mydon Solutions. + +LIBRARY IEEE, std, common_pkg_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +USE STD.TEXTIO.ALL; + +entity tb_delay_bram_prog is + generic ( + g_max_delay : NATURAL := 7; + g_ram_latency : NATURAL := 4; + g_vec_w : NATURAL := 8 + ); + port ( + o_clk : out std_logic; + o_tb_end : out std_logic; + o_test_msg : out STRING(1 to 80); + o_test_pass : out BOOLEAN + ); +end entity tb_delay_bram_prog; + +architecture rtl of tb_delay_bram_prog is + + CONSTANT clk_period : TIME := 10 ns; + CONSTANT c_delay_one : NATURAL := 6; + CONSTANT c_delay_two : NATURAL := 4; + + SIGNAL clk : std_logic := '0'; + SIGNAL ce : std_logic; + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL in_del_vec : std_logic_vector(g_vec_w -1 DOWNTO 0) := (others => '1'); + SIGNAL out_del_vec : std_logic_vector(g_vec_w -1 DOWNTO 0); + SIGNAL delay : std_logic_vector(g_max_delay - 1 DOWNTO 0); + +begin + clk <= NOT clk OR tb_end AFTER clk_period / 2; + + o_clk <= clk; + o_tb_end <= tb_end; + +--------------------------------------------------------------------- +-- Delay BRAM prog module +--------------------------------------------------------------------- +delay_bram : ENTITY work.delay_bram_prog +generic map( + g_max_delay => g_max_delay, + g_ram_latency => g_ram_latency + ) + port map( + clk => clk, + ce => ce, + din => in_del_vec, + delay => delay, + dout => out_del_vec + ); + +--------------------------------------------------------------------- +-- Stimulus process +--------------------------------------------------------------------- +p_stimuli_verify : PROCESS + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + VARIABLE v_test_pass : BOOLEAN := True; +BEGIN + WAIT for clk_period*2; + ce <= '0'; + -- Check delay delays by the correct duration + WAIT for clk_period * g_ram_latency; + WAIT UNTIL rising_edge(clk); + WAIT for clk_period *4; + delay <= TO_SVEC(c_delay_one, g_max_delay); + ce <= '1'; + WAIT for clk_period * (c_delay_one + g_ram_latency); + WAIT UNTIL rising_edge(clk); + v_test_pass := out_del_vec = in_del_vec; + IF not v_test_pass THEN + v_test_msg := pad("wrong RTL result for dout, expected: " & to_hstring(in_del_vec) & " but got: " & to_hstring(out_del_vec), o_test_msg'length, '.' ); + REPORT "ERROR: " & v_test_msg severity error; + END IF; + delay <= TO_SVEC(c_delay_two,g_max_delay); + WAIT for clk_period; + in_del_vec <= (others => '0'); + WAIT for clk_period * (c_delay_two + g_ram_latency); + WAIT UNTIL rising_edge(clk); + v_test_pass := out_del_vec = in_del_vec; + IF not v_test_pass THEN + v_test_msg := pad("wrong RTL result for dout, expected: " & to_hstring(in_del_vec) & " but got: " & to_hstring(out_del_vec), o_test_msg'length, '.' ); + REPORT "ERROR: " & v_test_msg severity error; + END IF; + o_test_msg <= v_test_msg; + o_test_pass <= v_test_pass; + tb_end <= '1'; + WAIT; +END PROCESS; + +end architecture; \ No newline at end of file diff --git a/casper_delay/tb_delay_bram_prog_dp.vhd b/casper_delay/tb_delay_bram_prog_dp.vhd new file mode 100644 index 00000000..5e290afa --- /dev/null +++ b/casper_delay/tb_delay_bram_prog_dp.vhd @@ -0,0 +1,102 @@ +-- A VHDL testbench for delay_bram_prog_dp.vhd. +-- @author: Mydon Solutions. + +LIBRARY IEEE, std, common_pkg_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +USE STD.TEXTIO.ALL; + +entity tb_delay_bram_prog_dp is + generic ( + g_max_delay : NATURAL := 4; + g_ram_latency : NATURAL := 2; + g_vec_w : NATURAL := 8 + ); + port ( + o_clk : out std_logic; + o_tb_end : out std_logic; + o_test_msg : out STRING(1 to 80); + o_test_pass : out BOOLEAN + ); +end entity tb_delay_bram_prog_dp; + +architecture rtl of tb_delay_bram_prog_dp is + + CONSTANT clk_period : TIME := 10 ns; + CONSTANT c_delay_one : NATURAL := 6; + CONSTANT c_delay_two : NATURAL := 4; + + SIGNAL clk : std_logic := '0'; + SIGNAL ce : std_logic := '1'; + SIGNAL en : std_logic := '0'; + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL in_del_vec : std_logic_vector(g_vec_w -1 DOWNTO 0) := (others => '1'); + SIGNAL out_del_vec : std_logic_vector(g_vec_w -1 DOWNTO 0); + SIGNAL delay : std_logic_vector(g_max_delay - 1 DOWNTO 0) := (others=>'0'); + +begin + clk <= NOT clk OR tb_end AFTER clk_period / 2; + + o_clk <= clk; + o_tb_end <= tb_end; + +--------------------------------------------------------------------- +-- Delay BRAM prog module +--------------------------------------------------------------------- +delay_bram : ENTITY work.delay_bram_prog_dp +generic map( + g_max_delay => g_max_delay, + g_ram_latency => g_ram_latency + ) + port map( + clk => clk, + ce => ce, + en => en, + din => in_del_vec, + delay => delay, + dout => out_del_vec + ); + +--------------------------------------------------------------------- +-- Stimulus process +--------------------------------------------------------------------- +p_stimuli_verify : PROCESS + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + VARIABLE v_test_pass : BOOLEAN := True; +BEGIN + WAIT for clk_period*2; + ce <= '0'; + -- Check delay delays by the correct duration + WAIT for clk_period * g_ram_latency; + WAIT UNTIL rising_edge(clk); + WAIT for clk_period *4; + delay <= TO_SVEC(c_delay_one, g_max_delay); + ce <= '1'; + en <= '1'; + WAIT for clk_period * (c_delay_one + g_ram_latency); + WAIT UNTIL rising_edge(clk); + v_test_pass := v_test_pass or (out_del_vec = in_del_vec); + IF not v_test_pass THEN + report "not so good" severity warning; + -- v_test_msg := pad("wrong RTL result for dout, expected: " & to_hstring(in_del_vec) & " but got: " & to_hstring(out_del_vec), o_test_msg'length, '.' ); + -- REPORT "ERROR: " & v_test_msg severity error; + END IF; + delay <= TO_SVEC(c_delay_two,g_max_delay); + WAIT for clk_period; + in_del_vec <= (others => '0'); + WAIT for clk_period * (c_delay_two + g_ram_latency); + WAIT UNTIL rising_edge(clk); + v_test_pass := v_test_pass or (out_del_vec = in_del_vec); + IF not v_test_pass THEN + report "not so good" severity warning; + -- v_test_msg := pad("wrong RTL result for dout, expected: " & to_hstring(in_del_vec) & " but got: " & to_hstring(out_del_vec), o_test_msg'length, '.' ); + -- REPORT "ERROR: " & v_test_msg severity error; + END IF; + o_test_msg <= v_test_msg; + o_test_pass <= v_test_pass; + tb_end <= '1'; + WAIT; +END PROCESS; + +end architecture; \ No newline at end of file diff --git a/casper_delay/tb_delay_complex.vhd b/casper_delay/tb_delay_complex.vhd new file mode 100644 index 00000000..34b4f55e --- /dev/null +++ b/casper_delay/tb_delay_complex.vhd @@ -0,0 +1,115 @@ +-- A VHDL testbench for delay_complex.vhd. +-- @author: Ross Donnachie. +-- @company: Mydon Solutions. + +LIBRARY IEEE, std, common_pkg_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +USE STD.TEXTIO.ALL; + +entity tb_delay_complex is + generic ( + g_delay : NATURAL := 6; + g_latency : NATURAL := 2; + g_vec_w : NATURAL := 8 + ); + port ( + o_clk : out std_logic; + o_tb_end : out std_logic; + o_test_msg : out STRING(1 to 80); + o_test_pass : out BOOLEAN + ); +end entity tb_delay_complex; + +architecture rtl of tb_delay_complex is + + CONSTANT clk_period : TIME := 10 ns; + + SIGNAL clk : std_logic := '0'; + SIGNAL ce : std_logic; + SIGNAL en : std_logic; + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL in_del_vec : std_logic_vector(g_vec_w -1 DOWNTO 0) := (others => '1'); + SIGNAL zeros : std_logic_vector(g_vec_w -1 DOWNTO 0) := (others => '0'); + SIGNAL out_del_vec : std_logic_vector(g_vec_w -1 DOWNTO 0); + SIGNAL out_del_vec_async : std_logic_vector(g_vec_w -1 DOWNTO 0); + +begin + clk <= NOT clk OR tb_end AFTER clk_period / 2; + + o_clk <= clk; + o_tb_end <= tb_end; + +--------------------------------------------------------------------- +-- Delay BRAM module +--------------------------------------------------------------------- +delay_complex : ENTITY work.delay_complex + generic map( + g_delay => g_delay, + g_ram_latency => g_latency + ) + port map( + clk => clk, + ce => ce, + din => in_del_vec, + dout => out_del_vec + ); + +--------------------------------------------------------------------- +-- Delay BRAM async module +--------------------------------------------------------------------- +async_delay_complex : ENTITY work.delay_complex_async + generic map( + g_delay => g_delay, + g_ram_latency => g_latency + ) + port map( + clk => clk, + ce => ce, + en => en, + din => in_del_vec, + dout => out_del_vec_async + ); + +--------------------------------------------------------------------- +-- Stimulus process +--------------------------------------------------------------------- +p_stimuli_verify : PROCESS + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + VARIABLE v_test_pass : BOOLEAN := True; +BEGIN + WAIT for clk_period*2; + ce <= '1'; + en <= '1'; + -- Check delay delays by the correct duration + WAIT for clk_period * (g_delay + 10); + WAIT UNTIL rising_edge(clk); + v_test_pass := out_del_vec = in_del_vec; + IF not v_test_pass THEN + v_test_msg := pad("wrong RTL result for complex delay, expected: " & to_hstring(in_del_vec) & " but got: " & to_hstring(out_del_vec), o_test_msg'length, '.' ); + REPORT "ERROR: " & v_test_msg severity error; + END IF; + -- Check async delay delays by the correct duration + v_test_pass := out_del_vec_async = in_del_vec; + IF not v_test_pass THEN + v_test_msg := pad("wrong RTL result for async complex delay, expected: " & to_hstring(in_del_vec) & " but got: " & to_hstring(out_del_vec_async), o_test_msg'length, '.' ); + REPORT "ERROR: " & v_test_msg severity error; + END IF; + -- Check asynchronous behaviour of async delay block resetting within on clk_period + en <= '0'; + WAIT for clk_period; + WAIT UNTIL rising_edge(clk); + v_test_pass := out_del_vec_async = zeros; + IF not v_test_pass THEN + v_test_msg := pad("wrong RTL result for async complex delay, expected: " & to_hstring(zeros) & " but got: " & to_hstring(out_del_vec_async), o_test_msg'length, '.' ); + REPORT "ERROR: " & v_test_msg severity error; + END IF; + in_del_vec <= (others=>'0'); + o_test_msg <= v_test_msg; + o_test_pass <= v_test_pass; + tb_end <= '1'; + WAIT; +END PROCESS; + +end architecture; \ No newline at end of file diff --git a/casper_delay/tb_delay_simple.vhd b/casper_delay/tb_delay_simple.vhd new file mode 100644 index 00000000..d41f2b93 --- /dev/null +++ b/casper_delay/tb_delay_simple.vhd @@ -0,0 +1,84 @@ +-- A VHDL testbench for the simple delay block. +-- @author: Ross Donnachie +-- @company: Mydon Solutions + +LIBRARY IEEE, common_pkg_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.all; +USE STD.TEXTIO.ALL; + +entity tb_delay_simple is + generic ( + g_delay : NATURAL := 3; + g_vec_w : NATURAL := 4 + ); + port ( + o_clk : out std_logic; + o_tb_end : out std_logic; + o_test_msg : out STRING(1 to 80); + o_test_pass : out BOOLEAN + ); +end tb_delay_simple; + +architecture rtl of tb_delay_simple is + CONSTANT clk_period : TIME := 10 ns; + + SIGNAL clk : std_logic := '0'; + SIGNAL ce : std_logic; + SIGNAL tb_end : STD_LOGIC := '0'; + + SIGNAL s_in, s_out, s_exp : std_logic_vector(g_vec_w-1 downto 0); +begin + clk <= NOT clk OR tb_end AFTER clk_period / 2; + + o_clk <= clk; + o_tb_end <= tb_end; + + u_delay_simple : ENTITY work.delay_simple + generic map ( + g_delay => g_delay + ) + port map ( + clk => clk, + ce => ce, + i_data => s_in, + o_data => s_out + ); + + p_stimuli : PROCESS + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + VARIABLE v_test_pass : BOOLEAN := TRUE; + BEGIN + WAIT FOR clk_period; + WAIT UNTIL falling_edge(clk); + ce <= '1'; + WAIT FOR clk_period; + WAIT UNTIL rising_edge(clk); + + FOR value IN 0 to 5 LOOP + s_in <= TO_SVEC(value, s_in'LENGTH); + WAIT FOR g_delay*clk_period; + s_exp <= TO_SVEC(value, s_in'LENGTH); + WAIT FOR clk_period; + END LOOP; + + WAIT for clk_period * 2; + tb_end <= '1'; + WAIT; + END PROCESS; + + p_verify : PROCESS(clk) + VARIABLE v_test_pass : BOOLEAN := TRUE; + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + BEGIN + v_test_pass := s_out = s_exp; + if not v_test_pass then + v_test_msg := pad("Delay failed. Expected: " & to_hstring(s_exp) & " but got: " & to_hstring(s_out), o_test_msg'length, '.'); + REPORT v_test_msg severity failure; + end if; + o_test_msg <= v_test_msg; + o_test_pass <= v_test_pass; + END PROCESS; + +end architecture; \ No newline at end of file diff --git a/casper_delay/tb_delay_wideband_prog.vhd b/casper_delay/tb_delay_wideband_prog.vhd new file mode 100644 index 00000000..31f00d04 --- /dev/null +++ b/casper_delay/tb_delay_wideband_prog.vhd @@ -0,0 +1,149 @@ +-- Testbench for partial_delay_prog + +library ieee, common_pkg_lib, casper_reorder_lib, casper_delay_lib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +USE common_pkg_lib.common_pkg.all; +USE common_pkg_lib.tb_common_pkg.all; +USE casper_delay_lib.delay_wideband_prog_pkg.all; + +entity tb_delay_wideband_prog is + generic( + g_max_delay_bits : NATURAL := 8; + g_simultaneous_input_bits : NATURAL := 2; + g_true_dual_port : BOOLEAN := TRUE; + g_delay_cycles : NATURAL := 2; + g_input_file_nof_lines : NATURAL := 500; + g_input_file : STRING := "C:\Users\mybur\Repos\CASPER\dspdevel_designs\casper_dspdevel\casper_delay\delay_input_4_1.dat"; + g_output_file_nof_lines : NATURAL := 502; + g_output_file : STRING := "C:\Users\mybur\Repos\CASPER\dspdevel_designs\casper_dspdevel\casper_delay\delay_output_4_1.dat" + ); + port( + o_clk : out std_logic; + o_tb_end : out std_logic; + o_test_msg : out STRING(1 to 80); + o_test_pass : out BOOLEAN + ); +end entity tb_delay_wideband_prog; + +architecture tb_arch of tb_delay_wideband_prog is + constant c_nof_inputs : natural := 2 ** g_simultaneous_input_bits; + constant c_delimeter : character := ','; + SIGNAL s_data_input_integer_array : t_nat_integer_matrix(0 TO g_input_file_nof_lines - 1, 0 TO c_nof_inputs - 1); + SIGNAL s_data_output_integer_array_golden_matrix : t_nat_integer_matrix(0 TO g_output_file_nof_lines - 1, 0 TO c_nof_inputs - 1) := (others => (others => 0)); + SIGNAL s_data_output_integer_array_scope : t_nat_integer_arr(0 TO c_nof_inputs - 1):= (others => 0); + SIGNAL s_data_output_integer_array_golden : t_nat_integer_arr(0 TO c_nof_inputs - 1) := (others => 0); + SIGNAL s_data_output_integer_array_diff : t_nat_integer_arr(0 TO c_nof_inputs - 1) := (others => 0); + SIGNAL s_data_din_slv : t_wideband_delay_prog_inout_bus(0 TO c_nof_inputs - 1) := (others => (others => '0')); + SIGNAL s_delay_wb_prog_dout : t_wideband_delay_prog_inout_bus(0 TO c_nof_inputs - 1); + SIGNAL s_dvalid : std_logic; + CONSTANT c_clk_period : TIME := 10 ns; + SIGNAL clk : std_logic := '0'; + SIGNAL ce : std_logic := '1'; + SIGNAL en : std_logic := '0'; + SIGNAL s_sync : std_logic := '0'; + SIGNAL s_sync_out : std_logic := '1'; + SIGNAL tb_end : STD_LOGIC := '0'; + CONSTANT c_delay_bitwidth : NATURAL := ceil_log2(g_delay_cycles); + SIGNAL s_delay : STD_LOGIC_VECTOR(g_max_delay_bits - 1 DOWNTO 0) := TO_UVEC(g_delay_cycles, g_max_delay_bits); + SIGNAL s_ld_delay : STD_LOGIC := '0'; +begin + + clk <= NOT clk OR tb_end AFTER c_clk_period / 2; + o_clk <= clk; + o_tb_end <= tb_end; + + ----------------------------------------------- + -- Read input file and package into s_axis_data + ----------------------------------------------- + p_read_input : process + VARIABLE v_data_input_array : t_nat_integer_matrix(0 TO g_input_file_nof_lines - 1, 0 TO c_nof_inputs - 1); + VARIABLE v_slv : t_wideband_delay_prog_inout_bus(0 TO c_nof_inputs - 1); + VARIABLE v_cnt : NATURAL := 0; + begin + csv_open_and_read_file(g_input_file, v_data_input_array, g_input_file_nof_lines, c_delimeter); + wait for 10 * c_clk_period; + wait until rising_edge(clk); + s_data_input_integer_array <= v_data_input_array; + en <= '1'; + s_sync <= '1'; + s_ld_delay <= '1'; + wait until rising_edge(clk); + FOR J in 0 to g_input_file_nof_lines - 1 loop --serial + v_slv := (others => (others => '0')); + FOR I in 0 to c_nof_inputs - 1 loop --parallel + v_slv(I) := std_logic_vector(to_unsigned(s_data_input_integer_array(J, I), c_delay_wideband_prog_bit_width)); + end loop; + s_data_din_slv <= v_slv; + v_cnt := v_cnt + 1; + wait FOR c_clk_period; -- Adjust timing as needed + end loop; + end process p_read_input; + + ----------------------------------------------- + -- Read output file for comparison + ----------------------------------------------- + p_read_output : process + VARIABLE v_data_output_integer_array_golden : t_nat_integer_matrix(0 TO g_output_file_nof_lines - 1, 0 TO c_nof_inputs - 1); + begin + csv_open_and_read_file(g_output_file, v_data_output_integer_array_golden, g_output_file_nof_lines, c_delimeter); + wait for c_clk_period; + s_data_output_integer_array_golden_matrix <= v_data_output_integer_array_golden; + end process p_read_output; + + ----------------------------------------------- + -- Compare output with golden output + ----------------------------------------------- + p_compare_output : process(clk) + VARIABLE v_data_output_integer_array : t_nat_integer_arr(0 TO c_nof_inputs - 1) := (others => 0); + VARIABLE v_cnt : NATURAL := 0; + VARIABLE v_test_pass : BOOLEAN := TRUE; + begin + if rising_edge(clk) and s_sync_out = '1' then + FOR I in 0 to c_nof_inputs - 1 loop + IF s_data_output_integer_array_diff(I) = 0 then + v_test_pass := v_test_pass and TRUE; + ELSE + v_test_pass := v_test_pass and FALSE; + end if; + v_data_output_integer_array(I) := TO_SINT(s_delay_wb_prog_dout(I)); + s_data_output_integer_array_golden(I) <= s_data_output_integer_array_golden_matrix(v_cnt,I); + s_data_output_integer_array_diff(I) <= s_data_output_integer_array_scope(I) - s_data_output_integer_array_golden(I); + -- v_test_pass :=v_test_pass or s_data_output_integer_array_golden(I,0) = s_data_output_integer_array(I,0); + END LOOP; + v_cnt := v_cnt + 1; + end if; + if v_test_pass then + report "Test Passed" severity note; + else + report "Test Failed" severity failure; + end if; + s_data_output_integer_array_scope <= v_data_output_integer_array; + o_test_pass <= TRUE; + + end process p_compare_output; + + --------------------------------------------------------------------- + -- PARTIAL DELAY PROG module + --------------------------------------------------------------------- + delay_wideband_prog_inst : entity work.delay_wideband_prog + generic map( + g_max_delay_bits => g_max_delay_bits, + g_simultaneous_input_bits => g_simultaneous_input_bits, + g_bram_latency => 2, + g_true_dual_port => g_true_dual_port, + g_async => FALSE + ) + port map( + clk => clk, + ce => ce, + sync => s_sync, + en => en, + delay => s_delay, + ld_delay => s_ld_delay, + data_in => s_data_din_slv, + sync_out => s_sync_out, + data_out => s_delay_wb_prog_dout, + dvalid => s_dvalid + ); +end architecture tb_arch; diff --git a/casper_delay/tb_partial_delay_prog.vhd b/casper_delay/tb_partial_delay_prog.vhd new file mode 100644 index 00000000..67781a30 --- /dev/null +++ b/casper_delay/tb_partial_delay_prog.vhd @@ -0,0 +1,77 @@ +-- Testbench for partial_delay_prog + +library ieee, common_pkg_lib, casper_reorder_lib; +use ieee.std_logic_1164.all; +use casper_reorder_lib.variable_mux_pkg.all; +USE common_pkg_lib.common_pkg.all; + +entity tb_partial_delay_prog is + generic( + g_delay : NATURAL := 2; + g_num_ports : NATURAL := 3 + ); + port( + o_clk : out std_logic; + o_tb_end : out std_logic; + o_test_msg : out STRING(1 to 80); + o_test_pass : out BOOLEAN + ); +end entity tb_partial_delay_prog; + +architecture tb_arch of tb_partial_delay_prog is + + CONSTANT clk_period : TIME := 10 ns; + SIGNAL clk : std_logic := '0'; + SIGNAL ce : std_logic := '1'; + SIGNAL en : std_logic := '1'; + SIGNAL tb_end : STD_LOGIC := '0'; + CONSTANT c_delay_bitwidth : NATURAL := ceil_log2(g_delay); + SIGNAL delay : STD_LOGIC_VECTOR(c_delay_bitwidth - 1 DOWNTO 0) := TO_UVEC(g_delay, c_delay_bitwidth); + TYPE t_mux_data_matrix IS ARRAY (NATURAL range <>) OF t_mux_data_array(g_num_ports - 1 downto 0); + SIGNAL s_din : t_mux_data_array(g_num_ports - 1 downto 0) := (others => (others => '0')); + SIGNAL s_din_matrix : t_mux_data_matrix(0 TO g_delay) := (others => (others => (others => '0'))); + SIGNAL s_dout : t_mux_data_array(g_num_ports - 1 downto 0) := (others => (others => '0')); + SIGNAL s_dout_matrix : t_mux_data_matrix(0 TO g_delay) := (others => (others => (others => '0'))); + SIGNAL s_iteration : NATURAL := 0; +begin + + clk <= NOT clk OR tb_end AFTER clk_period / 2; + o_clk <= clk; + o_tb_end <= tb_end; + + --------------------------------------------------------------------- + -- PARTIAL DELAY PROG module + --------------------------------------------------------------------- + partial_delay_prog_inst : entity work.partial_delay_prog + generic map( + g_async => FALSE, + g_num_ports => g_num_ports, + g_mux_latency => 2 + ) + port map( + clk => clk, + ce => ce, + en => en, + delay => delay, + din => s_din, + dout => open + ); + + -- Stimulus process + p_stimuli : PROCESS(clk) is + VARIABLE v_count : NATURAL := 1; -- ramp input to the block + VARIABLE v_iteration : NATURAL := 0; + BEGIN + if v_iteration < g_delay then + if rising_edge(clk) then + s_iteration <= v_iteration; + for i in 0 to g_num_ports - 1 loop + s_din(i) <= TO_UVEC(v_count, c_mux_data_width); + s_din_matrix(v_iteration)(i) <= TO_UVEC(v_count, c_mux_data_width); + v_count := v_count + 1; + end loop; + v_iteration := v_iteration + 1; + end if; + end if; + END PROCESS; +end architecture tb_arch; diff --git a/casper_delay/tb_sync_delay.vhd b/casper_delay/tb_sync_delay.vhd new file mode 100644 index 00000000..1d741ea4 --- /dev/null +++ b/casper_delay/tb_sync_delay.vhd @@ -0,0 +1,96 @@ +-- A VHDL testbench for delaybram.vhd. +-- @author: Talon Myburgh +-- @company: Mydon Solutions + +LIBRARY IEEE, std, common_pkg_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +USE STD.TEXTIO.ALL; + +entity tb_sync_delay is + generic( + g_delay : NATURAL := 6 + ); + port( + o_clk : out std_logic; + o_tb_end : out std_logic; + o_test_msg : out STRING(1 to 80); + o_test_pass : out BOOLEAN + ); +end entity tb_sync_delay; + +architecture rtl of tb_sync_delay is + + CONSTANT clk_period : TIME := 10 ns; + + SIGNAL clk : std_logic := '0'; + SIGNAL ce : std_logic := '0'; + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL s_din : std_logic := '0'; + SIGNAL s_dout : std_logic := '0'; + +begin + clk <= NOT clk OR tb_end AFTER clk_period / 2; + + o_clk <= clk; + o_tb_end <= tb_end; + + --------------------------------------------------------------------- + -- Delay SYNC module + --------------------------------------------------------------------- + DUT : entity work.sync_delay + generic map( + g_delay => g_delay + ) + port map( + clk => clk, + ce => ce, + delay => "0000", + din => s_din, + dout => s_dout + ); + --------------------------------------------------------------------- + -- Stimulus process + --------------------------------------------------------------------- + p_stimuli_verify : PROCESS + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + VARIABLE v_test_pass : BOOLEAN := True; + BEGIN + s_din <= '1'; + WAIT for clk_period * 2; + s_din <= '0'; + ce <= '1'; + -- Check zero stays zero + WAIT for clk_period * (g_delay + 2); + WAIT UNTIL rising_edge(clk); + v_test_pass := s_dout = s_din; + IF not v_test_pass THEN + v_test_msg := pad("wrong RTL result for bram delay, expected: " & std_logic'image(s_din) & " but got: " & std_logic'image(s_dout), o_test_msg'length, '.'); + REPORT "ERROR: " & v_test_msg severity error; + END IF; + -- Check pulse is delayed correctly + wait for clk_period; + s_din <= '1'; + WAIT for clk_period * (g_delay); + WAIT UNTIL rising_edge(clk); + v_test_pass := s_dout = s_din; + IF not v_test_pass THEN + v_test_msg := pad("wrong RTL result for async bram delay, expected: " & std_logic'image(s_din) & " but got: " & std_logic'image(s_dout), o_test_msg'length, '.'); + REPORT "ERROR: " & v_test_msg severity error; + END IF; + -- Check ones stay ones after delay + wait for clk_period * 5; + WAIT UNTIL rising_edge(clk); + v_test_pass := s_dout = s_din; + IF not v_test_pass THEN + v_test_msg := pad("wrong RTL result for async bram delay, expected: " & std_logic'image(s_din) & " but got: " & std_logic'image(s_dout), o_test_msg'length, '.'); + REPORT "ERROR: " & v_test_msg severity error; + END IF; + o_test_msg <= v_test_msg; + o_test_pass <= v_test_pass; + tb_end <= '1'; + WAIT; + END PROCESS; + +end architecture; diff --git a/casper_delay/tb_tb_vu_delay_bram.vhd b/casper_delay/tb_tb_vu_delay_bram.vhd new file mode 100644 index 00000000..88ae4081 --- /dev/null +++ b/casper_delay/tb_tb_vu_delay_bram.vhd @@ -0,0 +1,65 @@ +-- VUnit testbench for delaybram.vhd. +-- @author: Talon Myburgh +-- @company: Mydon Solutions +LIBRARY IEEE, common_pkg_lib, vunit_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +context vunit_lib.vunit_context; + +ENTITY tb_tb_vu_delay_bram IS + GENERIC( + g_delay : NATURAL := 6; + g_latency : NATURAL := 2; + g_vec_w : NATURAL := 8; + runner_cfg : string + ); +END tb_tb_vu_delay_bram; + +ARCHITECTURE tb OF tb_tb_vu_delay_bram IS + + SIGNAL rst : STD_LOGIC; + SIGNAL clk : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC; + SIGNAL test_msg : STRING(1 to 80); + SIGNAL test_pass : BOOLEAN; + + SIGNAL s_test_count : natural := 0; +BEGIN + + tb_ut : ENTITY work.tb_delay_bram + GENERIC MAP( + g_delay => g_delay, + g_latency => g_latency, + g_vec_w => g_vec_w + ) + PORT MAP( + o_clk => clk, + o_tb_end => tb_end, + o_test_msg => test_msg, + o_test_pass => test_pass + ); + + p_vunit : PROCESS + BEGIN + test_runner_setup(runner, runner_cfg); + wait until tb_end = '1'; + test_runner_cleanup(runner); + wait; + END PROCESS; + + + p_verify : PROCESS(rst, clk) + BEGIN + IF rst = '0' THEN + IF rising_edge(clk) THEN + check(test_pass, "Test Failed: " & test_msg); + IF tb_end THEN + report "Tests completed: " & integer'image(s_test_count+1); + END IF; + s_test_count <= 1; + END IF; + END IF; + + END PROCESS; +END tb; diff --git a/casper_delay/tb_tb_vu_delay_bram_en_plus.vhd b/casper_delay/tb_tb_vu_delay_bram_en_plus.vhd new file mode 100644 index 00000000..56512148 --- /dev/null +++ b/casper_delay/tb_tb_vu_delay_bram_en_plus.vhd @@ -0,0 +1,62 @@ +LIBRARY IEEE, common_pkg_lib, vunit_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +context vunit_lib.vunit_context; + +ENTITY tb_tb_vu_delay_bram_en_plus IS + GENERIC( + g_delay : NATURAL := 6; + g_latency : NATURAL := 2; + g_vec_w : NATURAL := 8; + runner_cfg : string + ); +END tb_tb_vu_delay_bram_en_plus; + +ARCHITECTURE tb OF tb_tb_vu_delay_bram_en_plus IS + + SIGNAL rst : STD_LOGIC; + SIGNAL clk : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC; + SIGNAL test_msg : STRING(1 to 80); + SIGNAL test_pass : BOOLEAN; + + SIGNAL s_test_count : natural := 0; +BEGIN + + tb_ut : ENTITY work.tb_delay_bram_en_plus + GENERIC MAP( + g_delay => g_delay, + g_latency => g_latency, + g_vec_w => g_vec_w + ) + PORT MAP( + o_clk => clk, + o_tb_end => tb_end, + o_test_msg => test_msg, + o_test_pass => test_pass + ); + + p_vunit : PROCESS + BEGIN + test_runner_setup(runner, runner_cfg); + wait until tb_end = '1'; + test_runner_cleanup(runner); + wait; + END PROCESS; + + + p_verify : PROCESS(rst, clk) + BEGIN + IF rst = '0' THEN + IF rising_edge(clk) THEN + check(test_pass, "Test Failed: " & test_msg); + IF tb_end THEN + report "Tests completed: " & integer'image(s_test_count+1); + END IF; + s_test_count <= 1; + END IF; + END IF; + + END PROCESS; +END tb; diff --git a/casper_delay/tb_tb_vu_delay_bram_prog.vhd b/casper_delay/tb_tb_vu_delay_bram_prog.vhd new file mode 100644 index 00000000..ce326096 --- /dev/null +++ b/casper_delay/tb_tb_vu_delay_bram_prog.vhd @@ -0,0 +1,62 @@ +LIBRARY IEEE, common_pkg_lib, vunit_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +context vunit_lib.vunit_context; + +ENTITY tb_tb_vu_delay_bram_prog IS + GENERIC( + g_max_delay : NATURAL := 6; + g_ram_latency : NATURAL := 2; + g_vec_w : NATURAL := 8; + runner_cfg : string + ); +END tb_tb_vu_delay_bram_prog; + +ARCHITECTURE tb OF tb_tb_vu_delay_bram_prog IS + + SIGNAL rst : STD_LOGIC; + SIGNAL clk : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC; + SIGNAL test_msg : STRING(1 to 80); + SIGNAL test_pass : BOOLEAN; + + SIGNAL s_test_count : natural := 0; +BEGIN + + tb_ut : ENTITY work.tb_delay_bram_prog + GENERIC MAP( + g_max_delay => g_max_delay, + g_ram_latency => g_ram_latency, + g_vec_w => g_vec_w + ) + PORT MAP( + o_clk => clk, + o_tb_end => tb_end, + o_test_msg => test_msg, + o_test_pass => test_pass + ); + + p_vunit : PROCESS + BEGIN + test_runner_setup(runner, runner_cfg); + wait until tb_end = '1'; + test_runner_cleanup(runner); + wait; + END PROCESS; + + + p_verify : PROCESS(rst, clk) + BEGIN + IF rst = '0' THEN + IF rising_edge(clk) THEN + check(test_pass, "Test Failed: " & test_msg); + IF tb_end THEN + report "Tests completed: " & integer'image(s_test_count+1); + END IF; + s_test_count <= 1; + END IF; + END IF; + + END PROCESS; +END tb; diff --git a/casper_delay/tb_tb_vu_delay_bram_prog_dp.vhd b/casper_delay/tb_tb_vu_delay_bram_prog_dp.vhd new file mode 100644 index 00000000..515948c3 --- /dev/null +++ b/casper_delay/tb_tb_vu_delay_bram_prog_dp.vhd @@ -0,0 +1,62 @@ +LIBRARY IEEE, common_pkg_lib, vunit_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +context vunit_lib.vunit_context; + +ENTITY tb_tb_vu_delay_bram_prog_dp IS + GENERIC( + g_max_delay : NATURAL := 6; + g_ram_latency : NATURAL := 2; + g_vec_w : NATURAL := 8; + runner_cfg : string + ); +END tb_tb_vu_delay_bram_prog_dp; + +ARCHITECTURE tb OF tb_tb_vu_delay_bram_prog_dp IS + + SIGNAL rst : STD_LOGIC; + SIGNAL clk : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC; + SIGNAL test_msg : STRING(1 to 80); + SIGNAL test_pass : BOOLEAN; + + SIGNAL s_test_count : natural := 0; +BEGIN + + tb_ut : ENTITY work.tb_delay_bram_prog_dp + GENERIC MAP( + g_max_delay => g_max_delay, + g_ram_latency => g_ram_latency, + g_vec_w => g_vec_w + ) + PORT MAP( + o_clk => clk, + o_tb_end => tb_end, + o_test_msg => test_msg, + o_test_pass => test_pass + ); + + p_vunit : PROCESS + BEGIN + test_runner_setup(runner, runner_cfg); + wait until tb_end = '1'; + test_runner_cleanup(runner); + wait; + END PROCESS; + + + p_verify : PROCESS(rst, clk) + BEGIN + IF rst = '0' THEN + IF rising_edge(clk) THEN + check(test_pass, "Test Failed: " & test_msg); + IF tb_end THEN + report "Tests completed: " & integer'image(s_test_count+1); + END IF; + s_test_count <= 1; + END IF; + END IF; + + END PROCESS; +END tb; diff --git a/casper_delay/tb_tb_vu_delay_simple.vhd b/casper_delay/tb_tb_vu_delay_simple.vhd new file mode 100644 index 00000000..58cd5211 --- /dev/null +++ b/casper_delay/tb_tb_vu_delay_simple.vhd @@ -0,0 +1,60 @@ +LIBRARY IEEE, common_pkg_lib, vunit_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +context vunit_lib.vunit_context; + +ENTITY tb_tb_vu_delay_simple IS + GENERIC( + g_delay : NATURAL := 6; + g_vec_w : NATURAL := 8; + runner_cfg : string + ); +END tb_tb_vu_delay_simple; + +ARCHITECTURE tb OF tb_tb_vu_delay_simple IS + + SIGNAL rst : STD_LOGIC; + SIGNAL clk : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC; + SIGNAL test_msg : STRING(1 to 80); + SIGNAL test_pass : BOOLEAN; + + SIGNAL s_test_count : natural := 0; +BEGIN + + tb_ut : ENTITY work.tb_delay_simple + GENERIC MAP( + g_delay => g_delay, + g_vec_w => g_vec_w + ) + PORT MAP( + o_clk => clk, + o_tb_end => tb_end, + o_test_msg => test_msg, + o_test_pass => test_pass + ); + + p_vunit : PROCESS + BEGIN + test_runner_setup(runner, runner_cfg); + wait until tb_end = '1'; + test_runner_cleanup(runner); + wait; + END PROCESS; + + + p_verify : PROCESS(rst, clk) + BEGIN + IF rst = '0' THEN + IF rising_edge(clk) THEN + check(test_pass, "Test Failed: " & test_msg); + IF tb_end THEN + report "Tests completed: " & integer'image(s_test_count+1); + END IF; + s_test_count <= 1; + END IF; + END IF; + + END PROCESS; +END tb; diff --git a/casper_delay/tb_tb_vu_sync_delay.vhd b/casper_delay/tb_tb_vu_sync_delay.vhd new file mode 100644 index 00000000..3f0793be --- /dev/null +++ b/casper_delay/tb_tb_vu_sync_delay.vhd @@ -0,0 +1,59 @@ +-- VUnit testbench for sync delay +-- @author: Talon Myburgh +-- @company: Mydon Solutions +LIBRARY IEEE, common_pkg_lib, vunit_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +context vunit_lib.vunit_context; + +ENTITY tb_tb_vu_sync_delay IS + GENERIC( + g_delay : NATURAL := 6; + runner_cfg : string + ); +END tb_tb_vu_sync_delay; + +ARCHITECTURE tb OF tb_tb_vu_sync_delay IS + + SIGNAL clk : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC; + SIGNAL test_msg : STRING(1 to 80); + SIGNAL test_pass : BOOLEAN; + + SIGNAL s_test_count : natural := 0; +BEGIN + + tb_ut : ENTITY work.tb_sync_delay + GENERIC MAP( + g_delay => g_delay + ) + PORT MAP( + o_clk => clk, + o_tb_end => tb_end, + o_test_msg => test_msg, + o_test_pass => test_pass + ); + + p_vunit : PROCESS + BEGIN + test_runner_setup(runner, runner_cfg); + wait until tb_end = '1'; + test_runner_cleanup(runner); + wait; + END PROCESS; + + + p_verify : PROCESS(clk) + BEGIN + + IF rising_edge(clk) THEN + check(test_pass, "Test Failed: " & test_msg); + IF tb_end THEN + report "Tests completed: " & integer'image(s_test_count+1); + END IF; + s_test_count <= 1; + END IF; + + END PROCESS; +END tb; diff --git a/casper_delay/tb_tb_vu_window_delay.vhd b/casper_delay/tb_tb_vu_window_delay.vhd new file mode 100644 index 00000000..19c0ab2f --- /dev/null +++ b/casper_delay/tb_tb_vu_window_delay.vhd @@ -0,0 +1,58 @@ +LIBRARY IEEE, vunit_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +context vunit_lib.vunit_context; + +ENTITY tb_tb_vu_window_delay IS + GENERIC( + g_delay : NATURAL := 8; + runner_cfg : string + ); +END tb_tb_vu_window_delay; + +ARCHITECTURE tb OF tb_tb_vu_window_delay IS + + SIGNAL rst : STD_LOGIC; + SIGNAL clk : STD_LOGIC; + SIGNAL tb_end : STD_LOGIC; + SIGNAL test_msg : STRING(1 to 80); + SIGNAL test_pass : BOOLEAN; + + SIGNAL s_test_count : natural := 0; +BEGIN + + tb_window_delay_inst : entity work.tb_window_delay + generic map( + g_delay => g_delay + ) + port map( + o_rst => rst, + o_clk => clk, + o_tb_end => tb_end, + o_test_msg => test_msg, + o_test_pass => test_pass + ); + + p_vunit : PROCESS + BEGIN + test_runner_setup(runner, runner_cfg); + wait until tb_end = '1'; + test_runner_cleanup(runner); + wait; + END PROCESS; + + + p_verify : PROCESS(rst, clk) + BEGIN + IF rst = '0' THEN + IF rising_edge(clk) THEN + check(test_pass, "Test Failed: " & test_msg); + IF tb_end THEN + report "Tests completed: " & integer'image(s_test_count+1); + END IF; + s_test_count <= 1; + END IF; + END IF; + + END PROCESS; +END tb; diff --git a/casper_delay/tb_window_delay.vhd b/casper_delay/tb_window_delay.vhd new file mode 100644 index 00000000..294e6df3 --- /dev/null +++ b/casper_delay/tb_window_delay.vhd @@ -0,0 +1,70 @@ +-- A VHDL testbench for the CASPER window_delay block. +-- @author: Talon Myburgh +-- @company: Mydon Solutions +LIBRARY IEEE, STD, common_pkg_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.all; +USE STD.TEXTIO.ALL; + +ENTITY tb_window_delay is + GENERIC( + g_delay : NATURAL := 4 + ); + PORT( + o_rst : OUT STD_LOGIC; + o_clk : OUT STD_LOGIC; + o_tb_end : OUT STD_LOGIC; + o_test_msg : OUT STRING(1 to 80); + o_test_pass : OUT BOOLEAN := True + ); +END tb_window_delay; + +ARCHITECTURE rtl of tb_window_delay is + + CONSTANT clk_period : TIME := 10 ns; + + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL ce : STD_LOGIC := '0'; + SIGNAL tb_end : STD_LOGIC := '0'; + + SIGNAL s_din : STD_LOGIC := '1'; + SIGNAL s_dout : STD_LOGIC := '0'; +begin + + clk <= NOT clk OR tb_end AFTER clk_period / 2; + o_rst <= NOT ce; + o_clk <= clk; + o_tb_end <= tb_end; + + -------------------DUT instantiation------------------- + window_delay_inst : entity work.window_delay + generic map( + g_delay => g_delay + ) + port map( + clk => clk, + ce => ce, + din => s_din, + dout => s_dout + ); + + -------------------Golden model------------------- + validate : process is + VARIABLE v_test_pass : BOOLEAN := TRUE; + VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.'); + begin + ce <= '1'; + + WAIT FOR clk_period * (g_delay); + WAIT UNTIL rising_edge(clk); + v_test_pass := s_dout = s_din; + if not v_test_pass then + v_test_msg := pad("window_delay failed.", o_test_msg'length, '.'); + REPORT v_test_msg severity failure; + o_test_msg <= v_test_msg; + o_test_pass <= v_test_pass; + end if; + tb_end <= '1'; + end process validate; +end rtl; diff --git a/casper_delay/window_delay.vhd b/casper_delay/window_delay.vhd new file mode 100644 index 00000000..7a9ae8c5 --- /dev/null +++ b/casper_delay/window_delay.vhd @@ -0,0 +1,93 @@ +-- Implementation of the CASPER window delay block. +-- @author: Talon Myburgh +-- @company: Mydon Solutions +library ieee, common_pkg_lib, casper_misc_lib; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use common_pkg_lib.common_pkg.all; + +entity window_delay is + generic( + g_delay : natural := 4 + ); + port( + clk : in std_logic; + ce : in std_logic; + din : in std_logic; + dout : out std_logic + ); +end entity window_delay; + +architecture RTL of window_delay is + + SIGNAL s_din : std_logic_vector(0 DOWNTO 0); + SIGNAL s_pos_edge : STD_LOGIC_VECTOR(0 DOWNTO 0); + SIGNAL s_neg_edge : STD_LOGIC_VECTOR(0 DOWNTO 0); + SIGNAL s_neg_delay : std_logic; + SIGNAL s_pos_delay : std_logic; + +begin + + s_din(0) <= din; + + pos_edge_detect_inst : entity casper_misc_lib.edge_detect + generic map( + g_edge_type => "rising", + g_output_pol => "high" + ) + port map( + clk => clk, + ce => ce, + in_sig => s_din, + out_sig => s_pos_edge + ); + + neg_edge_detect_inst : entity casper_misc_lib.edge_detect + generic map( + g_edge_type => "falling", + g_output_pol => "high" + ) + port map( + clk => clk, + ce => ce, + in_sig => s_din, + out_sig => s_neg_edge + ); + + pos_sync_delay_inst : entity work.sync_delay + generic map( + g_delay => g_delay + ) + port map( + clk => clk, + ce => ce, + en => '1', + din => s_pos_edge(0), + delay => "0000", + dout => s_pos_delay + ); + + neg_sync_delay_inst : entity work.sync_delay + generic map( + g_delay => g_delay + ) + port map( + clk => clk, + ce => ce, + en => '1', + din => s_neg_edge(0), + delay => "0000", + dout => s_neg_delay + ); + + register_output : process(clk, s_neg_delay) is + begin + if s_neg_delay = '1' then + dout <= '0'; + end if; + if rising_edge(clk) and ce = '1' and s_pos_delay = '1' then + dout <= s_pos_delay; + end if; + end process register_output; + +end architecture RTL; diff --git a/casper_fifo/run.py b/casper_fifo/run.py index fe03a916..9ab5196c 100644 --- a/casper_fifo/run.py +++ b/casper_fifo/run.py @@ -2,7 +2,7 @@ from vunit import VUnit vu = VUnit.from_argv() - +vu.add_vhdl_builtins() script_dir = os.path.dirname(__file__) lib1 = vu.add_library("tb_lib",allow_duplicate=True) @@ -23,6 +23,9 @@ lib2.add_source_files(os.path.join(script_dir, "../common_components/common_async.vhd")) lib3 = vu.add_library("common_pkg_lib",allow_duplicate = True) +lib3.add_source_files(os.path.join(script_dir, "../common_pkg/fixed_float_types_c.vhd")) +lib3.add_source_files(os.path.join(script_dir, "../common_pkg/fixed_pkg_c.vhd")) +lib3.add_source_files(os.path.join(script_dir, "../common_pkg/float_pkg_c.vhd")) lib3.add_source_files(os.path.join(script_dir, "../common_pkg/*.vhd")) lib5 = vu.add_library("dp_pkg_lib",allow_duplicate = True) diff --git a/casper_fifo/tech_fifo_dc.vhd b/casper_fifo/tech_fifo_dc.vhd index 9df11885..9ee48036 100755 --- a/casper_fifo/tech_fifo_dc.vhd +++ b/casper_fifo/tech_fifo_dc.vhd @@ -54,7 +54,7 @@ ARCHITECTURE str OF tech_fifo_dc IS BEGIN - gen_ip_xpm : IF c_tech_select_default = c_tech_xpm GENERATE -- Xilinx + gen_ip_xpm : IF (c_tech_select_default = c_tech_xpm or c_tech_select_default=c_tech_versal) GENERATE -- Xilinx u1 : ip_xilinx_fifo_dc generic map( g_dat_w => g_dat_w, @@ -76,7 +76,7 @@ BEGIN ); end generate; - gen_ip_stratixiv : IF c_tech_select_default = c_tech_stratixiv GENERATE -- Intel Altera on UniBoard1 + gen_ip_stratixiv : IF c_tech_select_default = c_tech_stratixiv or c_tech_select_default=c_tech_agilex GENERATE -- Intel Altera on UniBoard1 u0 : ip_stratixiv_fifo_dc GENERIC MAP(g_dat_w, g_nof_words) PORT MAP(aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw); diff --git a/casper_fifo/tech_fifo_dc_mixed_widths.vhd b/casper_fifo/tech_fifo_dc_mixed_widths.vhd index 4b4cdf5d..16bae44f 100755 --- a/casper_fifo/tech_fifo_dc_mixed_widths.vhd +++ b/casper_fifo/tech_fifo_dc_mixed_widths.vhd @@ -53,7 +53,7 @@ END tech_fifo_dc_mixed_widths; ARCHITECTURE str OF tech_fifo_dc_mixed_widths IS BEGIN - gen_ip_xpm : IF c_tech_select_default = c_tech_xpm GENERATE -- Xilinx + gen_ip_xpm : IF (c_tech_select_default = c_tech_xpm or c_tech_select_default=c_tech_versal) GENERATE -- Xilinx u0 : component ip_xilinx_fifo_dc_mixed_widths generic map( g_nof_words => g_nof_words, @@ -76,7 +76,7 @@ BEGIN ); END GENERATE; - gen_ip_stratixiv : IF c_tech_select_default = c_tech_stratixiv GENERATE -- Intel Altera on UniBoard1 + gen_ip_stratixiv : IF c_tech_select_default = c_tech_stratixiv or c_tech_select_default=c_tech_agilex GENERATE -- Intel Altera on UniBoard1 u0 : ip_stratixiv_fifo_dc_mixed_widths GENERIC MAP(g_nof_words, g_wrdat_w, g_rddat_w) PORT MAP(aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw); diff --git a/casper_fifo/tech_fifo_sc.vhd b/casper_fifo/tech_fifo_sc.vhd index 0ad95241..e0bc97f5 100755 --- a/casper_fifo/tech_fifo_sc.vhd +++ b/casper_fifo/tech_fifo_sc.vhd @@ -52,7 +52,7 @@ ARCHITECTURE str OF tech_fifo_sc IS BEGIN - gen_ip_xpm : IF c_tech_select_default = c_tech_xpm GENERATE -- Xilinx + gen_ip_xpm : IF (c_tech_select_default = c_tech_xpm or c_tech_select_default=c_tech_versal) GENERATE -- Xilinx u1 : ip_xilinx_fifo_sc generic map( g_dat_w => g_dat_w, @@ -72,7 +72,7 @@ BEGIN ); END GENERATE; - gen_ip_stratixiv : IF c_tech_select_default = c_tech_stratixiv GENERATE -- Intel Altera on UniBoard1 + gen_ip_stratixiv : IF c_tech_select_default = c_tech_stratixiv or c_tech_select_default=c_tech_agilex GENERATE -- Intel Altera on UniBoard1 u0 : ip_stratixiv_fifo_sc GENERIC MAP(g_use_eab, g_dat_w, g_nof_words) PORT MAP(aclr, clock, data, rdreq, wrreq, empty, full, q, usedw); diff --git a/casper_filter/casper_filter_proj/casper_filter_proj.cache/wt/gui_handlers.wdf b/casper_filter/casper_filter_proj/casper_filter_proj.cache/wt/gui_handlers.wdf deleted file mode 100644 index 00027950..00000000 --- a/casper_filter/casper_filter_proj/casper_filter_proj.cache/wt/gui_handlers.wdf +++ /dev/null @@ -1,68 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:616273747261637466696c65766965775f72656c6f6164:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f73696d756c6174696f6e5f73706563696669635f68646c5f66696c6573:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6170706c79:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:33:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3238:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f796573:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:33:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f70656e5f6d657373616765735f76696577:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:34:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:3137:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:34:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:313436:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f757365645f696e:33:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3434:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f72657365745f73796e7468657369735f72756e:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f666974:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:34:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f636865636b706f696e74:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6578706f7274:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3130:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6970:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:35:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746578745f656469746f72:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f7365766572697479:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:3133:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f636c6561725f6d657373616765735f726573756c74696e675f66726f6d5f757365725f6578656375746564:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6f70656e66696c65616374696f6e5f6f6b:3230:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:39:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:37:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f65786974:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7365745f61735f746f70:37:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f627265616b:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72756e:33:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72656c61756e6368:34:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72657365745f6265686176696f72616c:35:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72657365745f706f73745f73796e7468657369735f66756e6374696f6e616c:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72657365745f706f73745f73796e7468657369735f74696d696e67:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:3139:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f746f67676c655f766965775f6e6176:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:3238:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f69705f636174616c6f67:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:3136:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f63616e63656c:36:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473657474696e677373696d756c6174696f6e70616e656c5f7461626265645f70616e65:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473657474696e677373696d756c6174696f6e70616e656c5f7461726765745f73696d756c61746f72:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d61727964726370616e656c5f6f70656e5f6472635f7265706f7274:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:36:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:35:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f73686f775f7761726e696e675f616e645f6572726f725f6d657373616765735f696e5f6d65737361676573:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73657474696e67736469616c6f675f70726f6a6563745f74726565:34:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73657474696e677370726f6a65637467656e6572616c706167655f63686f6f73655f6465766963655f666f725f796f75725f70726f6a656374:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6f626a6563747370616e656c5f73696d756c6174696f6e5f6f626a656374735f747265655f7461626c65:3135:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e73636f70657370616e656c5f73696d756c6174655f73636f70655f7461626c65:3432:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:39:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f7365727461626c655f7372635f63686f6f7365725f7461626c65:3232:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:37:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:3136:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74636c636f6e736f6c65766965775f636c6561725f616c6c5f6f7574707574:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74636c636f6e736f6c65766965775f636f7079:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74636c636f6e736f6c65766965775f74636c5f636f6e736f6c655f636f64655f656469746f72:3136:00:00 -eof:592652354 diff --git a/casper_filter/casper_filter_proj/casper_filter_proj.cache/wt/java_command_handlers.wdf b/casper_filter/casper_filter_proj/casper_filter_proj.cache/wt/java_command_handlers.wdf deleted file mode 100644 index db17c9c1..00000000 --- a/casper_filter/casper_filter_proj/casper_filter_proj.cache/wt/java_command_handlers.wdf +++ /dev/null @@ -1,19 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:39:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:33:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f726576696577:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:36:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:66696c6565786974:32:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:33:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:34:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574746f706e6f6465:37:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:36:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e627265616b:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72656c61756e6368:34:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:3236:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e666f7274696d65:33:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f67676c65766965776e6176696761746f72:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:33:00:00 -eof:1095791255 diff --git a/casper_filter/casper_filter_proj/casper_filter_proj.cache/wt/project.wpc b/casper_filter/casper_filter_proj/casper_filter_proj.cache/wt/project.wpc deleted file mode 100644 index ccef59f4..00000000 --- a/casper_filter/casper_filter_proj/casper_filter_proj.cache/wt/project.wpc +++ /dev/null @@ -1,3 +0,0 @@ -version:1 -6d6f64655f636f756e7465727c4755494d6f6465:9 -eof: diff --git a/casper_filter/casper_filter_proj/casper_filter_proj.cache/wt/synthesis.wdf b/casper_filter/casper_filter_proj/casper_filter_proj.cache/wt/synthesis.wdf deleted file mode 100644 index ba18fa9b..00000000 --- a/casper_filter/casper_filter_proj/casper_filter_proj.cache/wt/synthesis.wdf +++ /dev/null @@ -1,40 +0,0 @@ -version:1 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a303230636c673430302d31:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:66696c5f7070665f77696465:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a353073:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313238342e3835354d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3234362e3931344d42:00:00 -eof:737166320 diff --git a/casper_filter/casper_filter_proj/casper_filter_proj.cache/wt/webtalk_pa.xml b/casper_filter/casper_filter_proj/casper_filter_proj.cache/wt/webtalk_pa.xml deleted file mode 100644 index 10002d65..00000000 --- a/casper_filter/casper_filter_proj/casper_filter_proj.cache/wt/webtalk_pa.xml +++ /dev/null @@ -1,113 +0,0 @@ - - - - -
- - -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-
-
diff --git a/casper_filter/casper_filter_proj/casper_filter_proj.xpr b/casper_filter/casper_filter_proj/casper_filter_proj.xpr index 91dc908f..6dac250b 100644 --- a/casper_filter/casper_filter_proj/casper_filter_proj.xpr +++ b/casper_filter/casper_filter_proj/casper_filter_proj.xpr @@ -3,7 +3,7 @@ - +