[P3] Vector computation operations idx

[tancheng]

For now, the vectorized FU's operands are fixed for 0 and 1:

VectorCGRA/fu/vector/VectorAdderComboRTL.py

Lines 66 to 69 in d3953a5

	@update
	def update_signal():
	s.recv_in[0].rdy @= s.Fu[0].recv_in[0].rdy
	s.recv_in[1].rdy @= s.Fu[0].recv_in[1].rdy

Instead, we should follow the same strategy as the scalar FUs:

VectorCGRA/fu/single/AdderRTL.py

Lines 30 to 38 in d3953a5

	s.in0 = Wire(FuInType)
	s.in1 = Wire(FuInType)
	idx_nbits = clog2(num_inports)
	s.in0_idx = Wire(idx_nbits)
	s.in1_idx = Wire(idx_nbits)
	s.in0_idx //= s.in0[0:idx_nbits]
	s.in1_idx //= s.in1[0:idx_nbits]

VectorCGRA/fu/single/AdderRTL.py

Lines 70 to 80 in d3953a5

	if s.recv_opt.val:
	if s.recv_opt.msg.operation == OPT_ADD:
	s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_in[s.in1_idx].msg.payload
	s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \
	s.recv_in[s.in1_idx].msg.predicate & \
	s.reached_vector_factor
	s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val
	s.send_out[0].val @= s.recv_all_val
	s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy
	s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy
	s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy