[P3] MemUnit is not fusible

[tancheng]

When performing pattern fusion into single FU, e.g., MAC is mul+add in single cycle, MemUnit is not able to be fused with other operations for now. Because the ports towards/from the data memory is forced to be dangling here:

VectorCGRA/fu/basic/TwoSeqCombo.py

Lines 90 to 97 in 9c1d72e

	def update_mem():
	s.to_mem_waddr.val @= b1(0)
	s.to_mem_wdata.val @= b1(0)
	s.to_mem_wdata.msg @= s.const_zero
	s.to_mem_waddr.msg @= AddrType(0)
	s.to_mem_raddr.msg @= AddrType(0)
	s.to_mem_raddr.val @= b1(0)
	s.from_mem_rdata.rdy @= b1(0)

Need to provide a MUX or OR to make them be correctly exposed in tile:

VectorCGRA/tile/TileRTL.py

Lines 171 to 181 in 9c1d72e

	if FuList[i] == MemUnitRTL:
	s.to_mem_raddr //= s.element.to_mem_raddr[i]
	s.from_mem_rdata //= s.element.from_mem_rdata[i]
	s.to_mem_waddr //= s.element.to_mem_waddr[i]
	s.to_mem_wdata //= s.element.to_mem_wdata[i]
	else:
	s.element.to_mem_raddr[i].rdy //= 0
	s.element.from_mem_rdata[i].val //= 0
	s.element.from_mem_rdata[i].msg //= DataType()
	s.element.to_mem_waddr[i].rdy //= 0
	s.element.to_mem_wdata[i].rdy //= 0