[P1] Questions on the integration tests

[ShangkunLi]

Hi~ @tancheng, I am a bit confused about the routing and fu xbar settings.

VectorCGRA/cgra/test/CgraRTL_fir_2x2_test.py

Line 445 in 8316500

TileInType(4), TileInType(0), TileInType(0), TileInType(0)],

According to the mapping result, the tile0 should take input from northeast and output to the FuInport[0] right? But why did you use TileInType(4) here to denote input from northeast? This is not consistent with the definition:

VectorCGRA/lib/util/common.py

Line 15 in 8316500

PORT_INDEX_NORTHEAST = 5

[ShangkunLi]

Solved~ Thanks~

[tancheng]

Right, that 4 is for the result of add from east. 6 happens on the next inst.

@ycc-21 can you help replace the number with PORT as you did in https://github.com/tancheng/VectorCGRA/pull/251/changes#diff-ff35ee24abf069e41d8b299107bd36df8ab727fe68023ad5c38da938545bd868? It seems some parts are missing.

VectorCGRA/cgra/test/CgraRTL_fir_2x2_test.py

Line 445 in 8316500

TileInType(4), TileInType(0), TileInType(0), TileInType(0)],

[ycc-21]

Right, that 4 is for the result of add from east. 6 happens on the next inst.

@ycc-21 can you help replace the number with PORT as you did in https://github.com/tancheng/VectorCGRA/pull/251/changes#diff-ff35ee24abf069e41d8b299107bd36df8ab727fe68023ad5c38da938545bd868? It seems some parts are missing.

VectorCGRA/cgra/test/CgraRTL_fir_2x2_test.py

Line 445 in 8316500

TileInType(4), TileInType(0), TileInType(0), TileInType(0)],
When ctrl_addr = 0, tile0 only starts executing after receiving data from the east, so it is TileInType(4). Similarly, when ctrl_addr = 1, tile0 only starts executing after receiving data from the northeast. I can change all TileInType() in the test to TileInType(PORT_XX) before February 6th (the school's final exam week).

[ShangkunLi]

Hi~ @tancheng,

I have another question regarding the integration test.

How does the current RTL/FU support stroing a value in a register for multiple cycles?

My configuration is:

  # Corresponding DFG:
  # 
  #       0(loop_count)---------┐
  #        /       \            |
  #     1(+,ld)  2(+,ld)  6(extract_pred)
  #        \       /            |
  #         \     /          7(not)
  #          3(x)               |
  #           |                 |
  #    ┌---> 4(+)               |
  #    |    /                   |
  # 5(phi_const) ----- 8(grant_predicate)
  #                             |
  #                          9(ret)
  #
  # Corresponding mapping (II = 3):
  '''
       ↑ Y
       |
  (0,1)|  Tile 2   Tile 3
       |
  (0,0)|  Tile 0   Tile 1
       +-----------------→ X
        (0,0)    (1,0)

  Tile 0: 0(loop_count), 1(+,ld)
  Tile 1: 6(extract_pred), 7(not)
  Tile 2: 4(+), 2(+,ld), 3(x)
  Tile 3: 8(grant_predicate), 9(ret), 5(phi_const)
  =============================
  cycle 0:
  [   4(+)   →   8(grant_pred)]
       ↑              ↺
  [0(loop_cnt) →      🔳      ]
       ↺
  =============================
  cycle 1:
  [ 2(+,ld)        9(ret)     ]
      ↑↺             
  [ 1(+,ld)    6(extract_pred)]
                     ↺
  =============================
  cycle 2:
  [  3(x)   ←   5(phi_const)  ]
       ↺             ↑↺
  [   🔳            7(not)    ]

  =============================
  '''

Here, the output of 4(+) is passed to tile3 in cycle 0; it is supposed to be stored in tile3's register during cycle 1. And in cycle 2, consumed by 5(phi_const).

[tancheng]

The second row of routing config indicates the data going towards the FU:

VectorCGRA/cgra/test/CgraRTL_fir_2x2_test.py

Line 445 in 8316500

TileInType(4), TileInType(0), TileInType(0), TileInType(0)],

And instead of directly consumed by FU, it needs to be stored inside the register, so we can use

VectorCGRA/cgra/test/CgraRTL_fir_2x2_test.py

Line 511 in 8316500

write_reg_from = [b2(0), b2(2), b2(0), b2(0)],

And set it as write_reg_from = [b2(1), b2(0), b2(0), b2(0)], (assuming it is from the north inport.) reference