diff --git a/.gitlab/ci/build.yml b/.gitlab/ci/build.yml index df6a07fda451..53c6cc376f60 100644 --- a/.gitlab/ci/build.yml +++ b/.gitlab/ci/build.yml @@ -245,17 +245,11 @@ build_docker: stage: host_test needs: [] image: espressif/docker-builder:1 - tags: - - build_docker_amd64_brno + tags: [shiny, dind] variables: DOCKER_TMP_IMAGE_NAME: "idf_tmp_image" script: - - export LOCAL_CI_REPOSITORY_URL=$CI_REPOSITORY_URL - - if [ -n "$LOCAL_GITLAB_HTTPS_HOST" ]; then export LOCAL_CI_REPOSITORY_URL="https://gitlab-ci-token:${CI_JOB_TOKEN}@${LOCAL_GITLAB_HTTPS_HOST}/${CI_PROJECT_PATH}"; fi - - if [ -n "$LOCAL_GIT_MIRROR" ]; then export LOCAL_CI_REPOSITORY_URL="${LOCAL_GIT_MIRROR}/${CI_PROJECT_PATH}"; fi - - echo "Using repository at $LOCAL_CI_REPOSITORY_URL" - - export DOCKER_BUILD_ARGS="--build-arg IDF_CLONE_URL=${LOCAL_CI_REPOSITORY_URL} --build-arg IDF_CLONE_BRANCH_OR_TAG=${CI_COMMIT_REF_NAME} --build-arg IDF_CHECKOUT_REF=${CI_COMMIT_TAG:-$PIPELINE_COMMIT_SHA}" - # Build + - export DOCKER_BUILD_ARGS="--build-arg IDF_CLONE_URL=${CI_REPOSITORY_URL} --build-arg IDF_CLONE_BRANCH_OR_TAG=${CI_COMMIT_REF_NAME} --build-arg IDF_CHECKOUT_REF=${CI_COMMIT_TAG:-$CI_COMMIT_SHA} --build-arg IDF_CLONE_SHALLOW=1 --build-arg IDF_GITHUB_ASSETS=${INTERNAL_GITHUB_ASSETS}" - docker build --tag ${DOCKER_TMP_IMAGE_NAME} ${DOCKER_BUILD_ARGS} tools/docker/ # We can't mount $PWD/examples/get-started/blink into the container, see https://gitlab.com/gitlab-org/gitlab-ce/issues/41227. # The workaround mentioned there works, but leaves around directories which need to be cleaned up manually. diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index eac8afa6e361..2a3c98846feb 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -24,6 +24,8 @@ repos: .*.pb-c.c| .*.yuv| .*.rgb| + .*.gray| + .*COPYING.*| docs/sphinx-known-warnings\.txt )$ - id: end-of-file-fixer diff --git a/CMakeLists.txt b/CMakeLists.txt index b4dbce1bc235..e3d48d0cf1fa 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,12 +1,12 @@ cmake_minimum_required(VERSION 3.16) -project(esp-idf C CXX ASM) if(CMAKE_CURRENT_LIST_DIR STREQUAL CMAKE_SOURCE_DIR) message(FATAL_ERROR "Current directory '${CMAKE_CURRENT_LIST_DIR}' is not buildable. " - "Change directories to one of the example projects in '${CMAKE_CURRENT_LIST_DIR}/examples' and try " - "again.") + "Change directories to one of the example projects in '${CMAKE_CURRENT_LIST_DIR}/examples' and try again.") endif() +project(esp-idf C CXX ASM) + # Variables compile_options, c_compile_options, cxx_compile_options, compile_definitions, link_options shall # not be unset as they may already contain flags, set by toolchain-TARGET.cmake files. diff --git a/components/bootloader/subproject/main/CMakeLists.txt b/components/bootloader/subproject/main/CMakeLists.txt index fa832f63b718..1984dc6dae07 100644 --- a/components/bootloader/subproject/main/CMakeLists.txt +++ b/components/bootloader/subproject/main/CMakeLists.txt @@ -5,6 +5,11 @@ set(target_folder "${target}") idf_build_get_property(target IDF_TARGET) set(scripts "ld/${target_folder}/bootloader.ld") +if(CONFIG_ESP32P4_REV_MIN_300) + set(scripts "ld/${target_folder}/bootloader.rev3.ld") +else() + set(scripts "ld/${target_folder}/bootloader.ld") +endif() list(APPEND scripts "ld/${target_folder}/bootloader.rom.ld") target_linker_script(${COMPONENT_LIB} INTERFACE "${scripts}") diff --git a/components/bootloader/subproject/main/ld/esp32p4/bootloader.rev3.ld b/components/bootloader/subproject/main/ld/esp32p4/bootloader.rev3.ld new file mode 100644 index 000000000000..b61b725c2c2e --- /dev/null +++ b/components/bootloader/subproject/main/ld/esp32p4/bootloader.rev3.ld @@ -0,0 +1,324 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/** + * Simplified memory map for the bootloader. + * Make sure the bootloader can load into main memory without overwriting itself. + * + * ESP32-P4 ROM static data usage is as follows: + * - 0x4ff296b8 - 0x4ff3afc0: Shared buffers, used in UART/USB/SPI download mode only + * - 0x4ff3afc0 - 0x4ff3fba4: CPU1 stack, can be reclaimed as heap after RTOS startup + * - 0x4ff3fba4 - 0x4ff40000: ROM .bss and .data (not easily reclaimable) + * + * The 2nd stage bootloader can take space up to the end of ROM shared + * buffers area (0x4087c610). + */ + +/* We consider 0x4087c610 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg, + * and work out iram_seg and iram_loader_seg addresses from there, backwards. + */ + +/* These lengths can be adjusted, if necessary: */ +bootloader_usable_dram_end = 0x4ffbcfc0; +bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */ +bootloader_dram_seg_len = 0x5000; +bootloader_iram_loader_seg_len = 0x7000; +bootloader_iram_seg_len = 0x2D00; + +/* Start of the lower region is determined by region size and the end of the higher region */ +bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead; +bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len; +bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len; +bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len; + +MEMORY +{ + iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len + iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len + dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len +} + +/* The app may use RAM for static allocations up to the start of iram_loader_seg. + * If you have changed something above and this assert fails: + * 1. Check what the new value of bootloader_iram_loader_seg start is. + * 2. Update the value in this assert. + * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32p4/memory.ld.in to the same value. + */ +ASSERT(bootloader_iram_loader_seg_start == 0x4FFAEFC0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END"); + +/* Default entry point: */ +ENTRY(call_start_cpu0); + +SECTIONS +{ + + .iram_loader.text : + { + . = ALIGN (16); + _loader_text_start = ABSOLUTE(.); + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ + *liblog.a:(.literal .text .literal.* .text.*) + *libgcc.a:(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) + *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) + *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) + *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*) + *libspi_flash.a:*.*(.literal .text .literal.* .text.*) + *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libhal.a:cache_hal.*(.literal .text .literal.* .text.*) + *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) + *libhal.a:key_mgr_hal.*(.literal.key_mgr_hal_set_key_usage .text.key_mgr_hal_set_key_usage) + *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) + *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) + *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) + *libefuse.a:*.*(.literal .text .literal.* .text.*) + *libriscv.a:rv_utils.*(.literal .text .literal.* .text.*) + *(.fini.literal) + *(.fini) + *(.gnu.version) + _loader_text_end = ABSOLUTE(.); + } > iram_loader_seg + + .iram.text : + { + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + } > iram_seg + + + /* Shared RAM */ + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _dram_start = ABSOLUTE(.); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + } > dram_seg + + .dram0.bootdesc : ALIGN(0x10) + { + _data_start = ABSOLUTE(.); + *(.data_bootloader_desc .data_bootloader_desc.*) /* Should be the first. Bootloader version info. DO NOT PUT ANYTHING BEFORE IT! */ + } > dram_seg + + .dram0.data : + { + *(.dram1 .dram1.*) /* catch stray DRAM_ATTR */ + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + _data_end = ABSOLUTE(.); + } > dram_seg + + .dram0.rodata : + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + *(.sdata2 .sdata2.* .srodata .srodata.*) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + *(.eh_frame_hdr) + *(.eh_frame) + . = (. + 3) & ~ 3; + /* C++ constructor and destructor tables, properly ordered: */ + __init_array_start = ABSOLUTE(.); + KEEP (*crtbegin.*(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __init_array_end = ABSOLUTE(.); + KEEP (*crtbegin.*(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _rodata_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + _dram_end = ABSOLUTE(.); + } > dram_seg + + .iram.text : + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.iram .iram.*) /* catch stray IRAM_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + + /** CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + + _text_end = ABSOLUTE(.); + _etext = .; + } > iram_seg + + .riscv.attributes 0: { *(.riscv.attributes) } + + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_pubtypes 0 : { *(.debug_pubtypes) } + /* DWARF 3 */ + .debug_ranges 0 : { *(.debug_ranges) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* GNU DWARF 2 extensions */ + .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) } + .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) } + /* DWARF 4 */ + .debug_types 0 : { *(.debug_types) } + /* DWARF 5 */ + .debug_addr 0 : { *(.debug_addr) } + .debug_line_str 0 : { *(.debug_line_str) } + .debug_loclists 0 : { *(.debug_loclists) } + .debug_macro 0 : { *(.debug_macro) } + .debug_names 0 : { *(.debug_names) } + .debug_rnglists 0 : { *(.debug_rnglists) } + .debug_str_offsets 0 : { *(.debug_str_offsets) } + + .comment 0 : { *(.comment) } + .note.GNU-stack 0: { *(.note.GNU-stack) } + + /** + * Discarding .rela.* sections results in the following mapping: + * .rela.text.* -> .text.* + * .rela.data.* -> .data.* + * And so forth... + */ + /DISCARD/ : { *(.rela.*) } + + /** + * This section is not included in the binary image; it is only present in the ELF file. + * It is used to keep certain symbols in the ELF file. + */ + .noload 0 (INFO) : + { + _noload_keep_in_elf_start = ABSOLUTE(.); + KEEP(*(.noload_keep_in_elf .noload_keep_in_elf.*)) + _noload_keep_in_elf_end = ABSOLUTE(.); + } +} + + +/** + * Appendix: Memory Usage of ROM bootloader + * + * 0x4ffa96b8 ------------------> _dram0_0_start + * | | + * | | + * | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h + * | | + * | | + * 0x4ffbafc0 ------------------> __stack_sentry + * | | + * | | 2. Startup pro cpu stack (freed when IDF app is running) + * | | + * 0x4ffbcfc0 ------------------> __stack (pro cpu) + * | | + * | | Startup app cpu stack + * | | + * 0x4ffbefc0 ------------------> __stack_app (app cpu) + * | | + * | | + * | | 3. Shared memory only used in startup code or nonos/early boot* + * | | (can be freed when IDF runs) + * | | + * | | + * 0x4ffbfbb0 ------------------> _dram0_rtos_reserved_start + * | | + * | | + * | | 4. Shared memory used in startup code and when IDF runs + * | | + * | | + * 0x4ffbffa4 ------------------> _dram0_rtos_reserved_end + * | | + * 0x4ffbffc8 ------------------> _data_start_interface + * | | + * | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible) + * | | + * 0x4ffc0000 ------------------> _data_end_interface + */ diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c index e50dcff87e1e..864ac9f37d7f 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -267,6 +267,15 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr) case ESP_IMAGE_FLASH_SIZE_16MB: size = 16; break; + case ESP_IMAGE_FLASH_SIZE_32MB: + size = 32; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + size = 64; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + size = 128; + break; default: size = 2; } @@ -345,6 +354,15 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr) case ESP_IMAGE_FLASH_SIZE_16MB: str = "16MB"; break; + case ESP_IMAGE_FLASH_SIZE_32MB: + str = "32MB"; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + str = "64MB"; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + str = "128MB"; + break; default: str = "2MB"; break; diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c index fa4f3c5a3c2c..e70e9e0f91b5 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -128,6 +128,15 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr) case ESP_IMAGE_FLASH_SIZE_16MB: size = 16; break; + case ESP_IMAGE_FLASH_SIZE_32MB: + size = 32; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + size = 64; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + size = 128; + break; default: size = 2; } @@ -204,6 +213,15 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr) case ESP_IMAGE_FLASH_SIZE_16MB: str = "16MB"; break; + case ESP_IMAGE_FLASH_SIZE_32MB: + str = "32MB"; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + str = "64MB"; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + str = "128MB"; + break; default: str = "2MB"; break; diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c index f537240bd93d..7433d7670ab7 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -139,6 +139,15 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr) case ESP_IMAGE_FLASH_SIZE_16MB: size = 16; break; + case ESP_IMAGE_FLASH_SIZE_32MB: + size = 32; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + size = 64; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + size = 128; + break; default: size = 2; } @@ -215,6 +224,15 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr) case ESP_IMAGE_FLASH_SIZE_16MB: str = "16MB"; break; + case ESP_IMAGE_FLASH_SIZE_32MB: + str = "32MB"; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + str = "64MB"; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + str = "128MB"; + break; default: str = "2MB"; break; diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c index a876c0417364..b02cb18b5fe5 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -117,6 +117,15 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr) case ESP_IMAGE_FLASH_SIZE_16MB: size = 16; break; + case ESP_IMAGE_FLASH_SIZE_32MB: + size = 32; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + size = 64; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + size = 128; + break; default: size = 2; } @@ -193,6 +202,15 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr) case ESP_IMAGE_FLASH_SIZE_16MB: str = "16MB"; break; + case ESP_IMAGE_FLASH_SIZE_32MB: + str = "32MB"; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + str = "64MB"; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + str = "128MB"; + break; default: str = "2MB"; break; diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c index 62ec88274177..d9090ee28d2b 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -102,6 +102,15 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr) case ESP_IMAGE_FLASH_SIZE_16MB: size = 16; break; + case ESP_IMAGE_FLASH_SIZE_32MB: + size = 32; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + size = 64; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + size = 128; + break; default: size = 2; } @@ -178,6 +187,15 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr) case ESP_IMAGE_FLASH_SIZE_16MB: str = "16MB"; break; + case ESP_IMAGE_FLASH_SIZE_32MB: + str = "32MB"; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + str = "64MB"; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + str = "128MB"; + break; default: str = "2MB"; break; diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c index 5cb2c2404765..07a246d20b64 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -114,6 +114,15 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr) case ESP_IMAGE_FLASH_SIZE_16MB: size = 16; break; + case ESP_IMAGE_FLASH_SIZE_32MB: + size = 32; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + size = 64; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + size = 128; + break; default: size = 2; } @@ -188,6 +197,15 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr) case ESP_IMAGE_FLASH_SIZE_16MB: str = "16MB"; break; + case ESP_IMAGE_FLASH_SIZE_32MB: + str = "32MB"; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + str = "64MB"; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + str = "128MB"; + break; default: str = "2MB"; break; diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c index b0f1ff411f89..e131afcbec6e 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -109,6 +109,15 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr) case ESP_IMAGE_FLASH_SIZE_16MB: size = 16; break; + case ESP_IMAGE_FLASH_SIZE_32MB: + size = 32; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + size = 64; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + size = 128; + break; default: size = 2; } @@ -185,6 +194,15 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr) case ESP_IMAGE_FLASH_SIZE_16MB: str = "16MB"; break; + case ESP_IMAGE_FLASH_SIZE_32MB: + str = "32MB"; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + str = "64MB"; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + str = "128MB"; + break; default: str = "2MB"; break; diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c index 78a53b4a6c30..d3e7fdd8d9d1 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c @@ -224,6 +224,7 @@ static void bootloader_spi_flash_resume(void) esp_err_t bootloader_init_spi_flash(void) { + bootloader_init_mspi_clock(); bootloader_init_flash_configure(); bootloader_spi_flash_resume(); bootloader_flash_unlock(); diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c index 8099aa495533..377c85548f4b 100644 --- a/components/bootloader_support/src/bootloader_clock_init.c +++ b/components/bootloader_support/src/bootloader_clock_init.c @@ -34,7 +34,11 @@ __attribute__((weak)) void bootloader_clock_configure(void) esp_rom_output_tx_wait_idle(0); /* Set CPU to a higher certain frequency. Keep other clocks unmodified. */ +#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 + int cpu_freq_mhz = 100; +#else int cpu_freq_mhz = CPU_CLK_FREQ_MHZ_BTLD; +#endif #if CONFIG_IDF_TARGET_ESP32 /* On ESP32 rev 0, switching to 80/160 MHz if clock was previously set to diff --git a/components/bootloader_support/src/bootloader_common_loader.c b/components/bootloader_support/src/bootloader_common_loader.c index c06b2dfb7bb3..066ffa0a19c1 100644 --- a/components/bootloader_support/src/bootloader_common_loader.c +++ b/components/bootloader_support/src/bootloader_common_loader.c @@ -241,7 +241,11 @@ rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void) #ifdef BOOTLOADER_BUILD #if ESP_ROM_HAS_LP_ROM +#if CONFIG_IDF_TARGET_ESP32P4 + #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_LOW + CONFIG_P4_REV3_MSPI_WORKAROUND_SIZE) +#else #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_LOW) +#endif #else /* Since the structure containing the retain_mem_t is aligned on 8 by the linker, make sure we align this * structure size here too */ diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c index b22c5df42996..bb2c1ccb6419 100644 --- a/components/bootloader_support/src/esp_image_format.c +++ b/components/bootloader_support/src/esp_image_format.c @@ -352,6 +352,11 @@ static esp_err_t verify_image_header(uint32_t src_addr, const esp_image_header_t } #ifdef BOOTLOADER_BUILD +#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 +#define ROM_STACK_START (SOC_ROM_STACK_START_REV2) +#else +#define ROM_STACK_START (SOC_ROM_STACK_START) +#endif /* Check the region load_addr - load_end doesn't overlap any memory used by the bootloader, registers, or other invalid memory */ static bool verify_load_addresses(int segment_index, intptr_t load_addr, intptr_t load_end, bool print_error, bool no_recurse) @@ -371,7 +376,7 @@ static bool verify_load_addresses(int segment_index, intptr_t load_addr, intptr_ if (esp_ptr_in_dram(load_addr_p) && esp_ptr_in_dram(load_inclusive_end_p)) { /* Writing to DRAM */ /* Check if we're clobbering the stack */ intptr_t sp = (intptr_t)esp_cpu_get_sp(); - if (bootloader_util_regions_overlap(sp - STACK_LOAD_HEADROOM, SOC_ROM_STACK_START, + if (bootloader_util_regions_overlap(sp - STACK_LOAD_HEADROOM, ROM_STACK_START, load_addr, load_end)) { reason = "overlaps bootloader stack"; goto invalid; diff --git a/components/bt/CMakeLists.txt b/components/bt/CMakeLists.txt index 44ee5b340c71..170fba3a9d74 100644 --- a/components/bt/CMakeLists.txt +++ b/components/bt/CMakeLists.txt @@ -723,6 +723,7 @@ if(CONFIG_BT_ENABLED) host/nimble/nimble/nimble/host/util/include host/nimble/nimble/nimble/host/store/ram/include host/nimble/nimble/nimble/host/store/config/include + host/nimble/nimble/nimble/host/services/ras/include ) list(APPEND srcs "host/nimble/nimble/nimble/transport/src/transport.c" @@ -743,6 +744,8 @@ if(CONFIG_BT_ENABLED) "host/nimble/nimble/nimble/host/services/hid/src/ble_svc_hid.c" "host/nimble/nimble/nimble/host/services/sps/src/ble_svc_sps.c" "host/nimble/nimble/nimble/host/services/cte/src/ble_svc_cte.c" + "host/nimble/nimble/nimble/host/services/ras/src/ble_svc_ras.c" + "host/nimble/nimble/nimble/host/src/ble_cs.c" "host/nimble/nimble/nimble/host/src/ble_hs_conn.c" "host/nimble/nimble/nimble/host/src/ble_store_util.c" "host/nimble/nimble/nimble/host/src/ble_sm.c" @@ -931,6 +934,22 @@ set(bt_priv_requires esp_gdbstub ) +if(CONFIG_BLE_COMPRESSED_LOG_ENABLE) + set(BT_ROOT_PATH "${CMAKE_CURRENT_SOURCE_DIR}") + # When log compression is enabled, selected logs are replaced + # by auto-generated macros that emit pre-encoded data. + # This eliminates the original format strings, reducing firmware size and + # removing runtime formatting overhead, so logs are produced faster and + # with less system impact. + add_subdirectory(common/ble_log/extension/log_compression) + if(LOG_COMPRESSION_TARGET) + set(srcs ${LOG_COMPRESS_SRCS}) + set(include_dirs ${LOG_COMPRESS_INCLUDE_DIRS}) + else() + list(APPEND include_dirs ${LOG_COMPRESS_INCLUDE_DIRS}) + endif() +endif() + idf_component_register(SRCS "${srcs}" INCLUDE_DIRS "${include_dirs}" PRIV_INCLUDE_DIRS "${priv_include_dirs}" @@ -938,6 +957,12 @@ idf_component_register(SRCS "${srcs}" PRIV_REQUIRES "${bt_priv_requires}" LDFRAGMENTS "${ldscripts}") +if(CONFIG_BLE_COMPRESSED_LOG_ENABLE) + if(LOG_COMPRESSION_TARGET) + add_dependencies(${COMPONENT_LIB} ${LOG_COMPRESSION_TARGET}) + endif() +endif() + if(CONFIG_BT_ENABLED) target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-implicit-fallthrough -Wno-unused-const-variable) if(CONFIG_IDF_TARGET_ESP32) diff --git a/components/bt/common/Kconfig.in b/components/bt/common/Kconfig.in index fcd6ec849616..4bcfaa79cea1 100644 --- a/components/bt/common/Kconfig.in +++ b/components/bt/common/Kconfig.in @@ -255,3 +255,9 @@ config BT_BLE_LOG_UHCI_OUT_UART_IO_NUM_TX default 0 help IO number for UART TX port + +config BT_LE_USED_MEM_STATISTICS_ENABLED + bool "Enable used memory statistics" + default n + help + Used in internal tests only. Enable used memory statistics. diff --git a/components/bt/common/ble_log/Kconfig.in b/components/bt/common/ble_log/Kconfig.in index fe1a1a58ecfb..dfbd47117831 100644 --- a/components/bt/common/ble_log/Kconfig.in +++ b/components/bt/common/ble_log/Kconfig.in @@ -166,4 +166,8 @@ if BLE_LOG_ENABLED help GPIO number for UART TX endif + + menu "Settings of BLE Log Compression" + source "$IDF_PATH/components/bt/common/ble_log/extension/log_compression/Kconfig.in" + endmenu endif diff --git a/components/bt/common/ble_log/ble_log_spi_out.c b/components/bt/common/ble_log/ble_log_spi_out.c index a5434f9677ad..2a96fec6a3c0 100644 --- a/components/bt/common/ble_log/ble_log_spi_out.c +++ b/components/bt/common/ble_log/ble_log_spi_out.c @@ -89,6 +89,10 @@ SPI_OUT_HCI_QUEUE_SIZE +\ SPI_OUT_MESH_QUEUE_SIZE) +#if SPI_OUT_LL_ENABLED && CONFIG_SOC_ESP_NIMBLE_CONTROLLER +#include "os/os_mbuf.h" +#endif /* SPI_OUT_LL_ENABLED && CONFIG_SOC_ESP_NIMBLE_CONTROLLER */ + // Private typedefs typedef struct { // CRITICAL: 0 for available, 1 for need queue (ISR), 2 for in queue @@ -156,6 +160,7 @@ enum { LL_LOG_FLAG_ISR, LL_LOG_FLAG_HCI, LL_LOG_FLAG_RAW, + LL_LOG_FLAG_OMDATA, LL_LOG_FLAG_HCI_UPSTREAM, }; @@ -205,7 +210,7 @@ static inline void spi_out_log_cb_append_trans(spi_out_log_cb_t *log_cb); static inline void spi_out_log_cb_flush_trans(spi_out_log_cb_t *log_cb); static bool spi_out_log_cb_write(spi_out_log_cb_t *log_cb, const uint8_t *addr, uint16_t len, const uint8_t *addr_append, uint16_t len_append, uint8_t source, - bool with_checksum); + bool with_checksum, bool omdata); static void spi_out_log_cb_write_loss(spi_out_log_cb_t *log_cb); static void spi_out_log_cb_dump(spi_out_log_cb_t *log_cb); @@ -582,7 +587,7 @@ IRAM_ATTR static inline void spi_out_log_cb_flush_trans(spi_out_log_cb_t *log_cb // Return value: Need append IRAM_ATTR static bool spi_out_log_cb_write(spi_out_log_cb_t *log_cb, const uint8_t *addr, uint16_t len, const uint8_t *addr_append, uint16_t len_append, uint8_t source, - bool with_checksum) + bool with_checksum, bool omdata) { spi_out_trans_cb_t *trans_cb = log_cb->trans_cb[log_cb->trans_cb_idx]; @@ -598,7 +603,16 @@ IRAM_ATTR static bool spi_out_log_cb_write(spi_out_log_cb_t *log_cb, const uint8 memcpy(buf, (const uint8_t *)&head, SPI_OUT_FRAME_HEAD_LEN); memcpy(buf + SPI_OUT_FRAME_HEAD_LEN, addr, len); if (len_append && addr_append) { - memcpy(buf + SPI_OUT_FRAME_HEAD_LEN + len, addr_append, len_append); +#if SPI_OUT_LL_ENABLED && CONFIG_SOC_ESP_NIMBLE_CONTROLLER + if (omdata) { + os_mbuf_copydata((struct os_mbuf *)addr_append, 0, + len_append, buf + SPI_OUT_FRAME_HEAD_LEN + len); + } + else +#endif /* SPI_OUT_LL_ENABLED && CONFIG_SOC_ESP_NIMBLE_CONTROLLER */ + { + memcpy(buf + SPI_OUT_FRAME_HEAD_LEN + len, addr_append, len_append); + } } uint32_t checksum = 0; @@ -628,7 +642,7 @@ IRAM_ATTR static void spi_out_log_cb_write_loss(spi_out_log_cb_t *log_cb) .lost_bytes_cnt = log_cb->lost_bytes_cnt, }; spi_out_log_cb_write(log_cb, (const uint8_t *)&payload, sizeof(loss_payload_t), - NULL, 0, BLE_LOG_SPI_OUT_SOURCE_LOSS, true); + NULL, 0, BLE_LOG_SPI_OUT_SOURCE_LOSS, true, false); log_cb->lost_frame_cnt = 0; log_cb->lost_bytes_cnt = 0; @@ -756,9 +770,9 @@ static void spi_out_write_hex(spi_out_log_cb_t *log_cb, uint8_t source, if (with_ts) { uint32_t os_ts = pdTICKS_TO_MS(xTaskGetTickCount()); need_append |= spi_out_log_cb_write(log_cb, (const uint8_t *)&os_ts, - sizeof(uint32_t), addr, len, source, true); + sizeof(uint32_t), addr, len, source, true, false); } else { - need_append |= spi_out_log_cb_write(log_cb, addr, len, NULL, 0, source, true); + need_append |= spi_out_log_cb_write(log_cb, addr, len, NULL, 0, source, true, false); } } if (need_append) { @@ -1157,11 +1171,12 @@ IRAM_ATTR void ble_log_spi_out_ll_write(uint32_t len, const uint8_t *addr, uint3 log_cb = ll_task_log_cb; source = BLE_LOG_SPI_OUT_SOURCE_ESP; } + bool omdata = flag & BIT(LL_LOG_FLAG_OMDATA); bool need_append; if (spi_out_log_cb_check_trans(log_cb, (uint16_t)(len + len_append), &need_append)) { need_append |= spi_out_log_cb_write(log_cb, addr, (uint16_t)len, addr_append, - (uint16_t)len_append, source, true); + (uint16_t)len_append, source, true, omdata); } if (need_append) { if (in_isr) { @@ -1288,7 +1303,7 @@ IRAM_ATTR void ble_log_spi_out_le_audio_write(const uint8_t *addr, uint16_t len) bool need_append; if (spi_out_log_cb_check_trans(log_cb, len, &need_append)) { need_append |= spi_out_log_cb_write(log_cb, addr, len, NULL, 0, - BLE_LOG_SPI_OUT_SOURCE_LE_AUDIO, false); + BLE_LOG_SPI_OUT_SOURCE_LE_AUDIO, false, false); } if (need_append) { spi_out_log_cb_append_trans(log_cb); @@ -1350,12 +1365,13 @@ int ble_log_spi_out_hci_write(uint8_t source, const uint8_t *addr, uint16_t len) return -1; } - if (source == BLE_LOG_SPI_OUT_SOURCE_HCI_UPSTREAM) { #if SPI_OUT_LL_ENABLED + if (source == BLE_LOG_SPI_OUT_SOURCE_HCI_UPSTREAM) { ble_log_spi_out_ll_write(len, addr, 0, NULL, BIT(LL_LOG_FLAG_HCI_UPSTREAM)); -#endif // SPI_OUT_LL_ENABLED } - if (source == BLE_LOG_SPI_OUT_SOURCE_HCI_DOWNSTREAM) { + if (source == BLE_LOG_SPI_OUT_SOURCE_HCI_DOWNSTREAM) +#endif /* SPI_OUT_LL_ENABLED */ + { spi_out_log_cb_t *log_cb; bool fallback = false; if (!spi_out_get_task_mapping(LOG_MODULE_TASK_MAP(hci), diff --git a/components/bt/common/ble_log/ble_log_uhci_out.c b/components/bt/common/ble_log/ble_log_uhci_out.c index 1ab447eee39f..d905615488fa 100644 --- a/components/bt/common/ble_log/ble_log_uhci_out.c +++ b/components/bt/common/ble_log/ble_log_uhci_out.c @@ -39,6 +39,10 @@ #define UHCI_OUT_LL_QUEUE_SIZE (3 * UHCI_OUT_PING_PONG_BUF_CNT) #define UHCI_OUT_QUEUE_SIZE (UHCI_OUT_USER_QUEUE_SIZE + UHCI_OUT_LL_QUEUE_SIZE) +#if CONFIG_SOC_ESP_NIMBLE_CONTROLLER +#include "os/os_mbuf.h" +#endif /* CONFIG_SOC_ESP_NIMBLE_CONTROLLER */ + // Private typedefs typedef struct { // This flag is for multithreading, must be a word, do not modify @@ -95,7 +99,8 @@ enum { LL_LOG_FLAG_ISR, LL_LOG_FLAG_HCI, LL_LOG_FLAG_RAW, - LL_LOG_FLAG_SYNC + LL_LOG_FLAG_OMDATA, + LL_LOG_FLAG_HCI_UPSTREAM, }; enum { @@ -136,7 +141,7 @@ static inline bool uhci_out_log_cb_check_trans(uhci_out_log_cb_t *log_cb, uint16 static inline void uhci_out_log_cb_append_trans(uhci_out_log_cb_t *log_cb); static inline void uhci_out_log_cb_flush_trans(uhci_out_log_cb_t *log_cb); static bool uhci_out_log_cb_write(uhci_out_log_cb_t *log_cb, const uint8_t *addr, uint16_t len, - const uint8_t *addr_append, uint16_t len_append, uint8_t source); + const uint8_t *addr_append, uint16_t len_append, uint8_t source, bool omdata); static void uhci_out_log_cb_write_loss(uhci_out_log_cb_t *log_cb); static void uhci_out_log_cb_dump(uhci_out_log_cb_t *log_cb); @@ -318,7 +323,7 @@ IRAM_ATTR static inline void uhci_out_log_cb_flush_trans(uhci_out_log_cb_t *log_ // Return value: Need append IRAM_ATTR static bool uhci_out_log_cb_write(uhci_out_log_cb_t *log_cb, const uint8_t *addr, uint16_t len, - const uint8_t *addr_append, uint16_t len_append, uint8_t source) + const uint8_t *addr_append, uint16_t len_append, uint8_t source, bool omdata) { uhci_out_trans_cb_t *trans_cb = log_cb->trans_cb[log_cb->trans_cb_idx]; @@ -334,7 +339,16 @@ IRAM_ATTR static bool uhci_out_log_cb_write(uhci_out_log_cb_t *log_cb, const uin memcpy(buf, (const uint8_t *)&head, UHCI_OUT_FRAME_HEAD_LEN); memcpy(buf + UHCI_OUT_FRAME_HEAD_LEN, addr, len); if (len_append && addr_append) { - memcpy(buf + UHCI_OUT_FRAME_HEAD_LEN + len, addr_append, len_append); +#if CONFIG_SOC_ESP_NIMBLE_CONTROLLER + if (omdata) { + os_mbuf_copydata((struct os_mbuf *)addr_append, 0, + len_append, buf + UHCI_OUT_FRAME_HEAD_LEN + len); + } + else +#endif /* CONFIG_SOC_ESP_NIMBLE_CONTROLLER */ + { + memcpy(buf + UHCI_OUT_FRAME_HEAD_LEN + len, addr_append, len_append); + } } uint32_t checksum = 0; @@ -365,7 +379,7 @@ IRAM_ATTR static void uhci_out_log_cb_write_loss(uhci_out_log_cb_t *log_cb) .lost_bytes_cnt = log_cb->lost_bytes_cnt, }; uhci_out_log_cb_write(log_cb, (const uint8_t *)&payload, sizeof(loss_payload_t), - NULL, 0, BLE_LOG_UHCI_OUT_SOURCE_LOSS); + NULL, 0, BLE_LOG_UHCI_OUT_SOURCE_LOSS, false); log_cb->lost_frame_cnt = 0; log_cb->lost_bytes_cnt = 0; @@ -676,12 +690,13 @@ IRAM_ATTR void ble_log_uhci_out_ll_write(uint32_t len, const uint8_t *addr, uint log_cb = ll_task_log_cb; source = BLE_LOG_UHCI_OUT_SOURCE_ESP; } + bool omdata = flag & BIT(LL_LOG_FLAG_OMDATA); bool need_append; uint16_t frame_len = len + len_append + UHCI_OUT_FRAME_OVERHEAD; if (uhci_out_log_cb_check_trans(log_cb, frame_len, &need_append)) { need_append |= uhci_out_log_cb_write(log_cb, addr, len, addr_append, - len_append, source); + len_append, source, omdata); } ll_last_write_ts = in_isr?\ diff --git a/components/bt/common/ble_log/extension/log_compression/CMakeLists.txt b/components/bt/common/ble_log/extension/log_compression/CMakeLists.txt new file mode 100644 index 000000000000..967b0e9b8eca --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/CMakeLists.txt @@ -0,0 +1,202 @@ + +set(LOG_COMPRESSED_MODULE "") +set(LOG_COMPRESSED_MODULE_CODE_PATH "") +set(LOG_COMPRESSED_SRCS_DIR "${CMAKE_BINARY_DIR}/ble_log/.compressed_srcs") + +# default config value for ble mesh module +set(BLE_MESH_CODE_PATH "") +set(BLE_MESH_LOG_INDEX_HEADER "\"\"") +set(BLE_MESH_TAGS "") +set(BLE_MESH_TAGS_PRESERVE "") + +# default config value for host module +set(HOST_CODE_PATH "") +set(HOST_LOG_INDEX_HEADER "\"\"") +set(BLE_HOST_TAGS "") +set(BLE_HOST_TAGS_PRESERVE "") + +if(CONFIG_BLE_MESH_COMPRESSED_LOG_ENABLE) + list(APPEND LOG_COMPRESSED_MODULE "BLE_MESH") + if(NOT EXISTS "${CMAKE_BINARY_DIR}/ble_log/include/mesh_log_index.h") + file(WRITE "${CMAKE_BINARY_DIR}/ble_log/include/mesh_log_index.h" "") + endif() + list(APPEND LOG_COMPRESSED_MODULE_CODE_PATH "esp_ble_mesh") + + # update config file + set(BLE_MESH_CODE_PATH "esp_ble_mesh") + set(BLE_MESH_LOG_INDEX_HEADER "mesh_log_index.h") + # update BLE_MESH_TAGS and BLE_MESH_TAGS_PRESERVE + include(${CMAKE_CURRENT_LIST_DIR}/cmake/ble_mesh_log_tags.cmake) + +endif() +if(CONFIG_BLE_HOST_COMPRESSED_LOG_ENABLE AND CONFIG_BT_BLUEDROID_ENABLED) + list(APPEND LOG_COMPRESSED_MODULE "BLE_HOST") + list(APPEND LOG_COMPRESSED_MODULE_CODE_PATH "host/bluedroid/stack") + if(NOT EXISTS "${CMAKE_BINARY_DIR}/ble_log/include/host_log_index.h") + file(WRITE "${CMAKE_BINARY_DIR}/ble_log/include/host_log_index.h" "") + endif() + + set(HOST_CODE_PATH "host/bluedroid/stack") + set(HOST_LOG_INDEX_HEADER "host_log_index.h") + include(${CMAKE_CURRENT_LIST_DIR}/cmake/ble_host_bluedroid_tags.cmake) +endif() +if(LOG_COMPRESSED_MODULE) + list(APPEND srcs "common/ble_log/extension/log_compression/ble_log_compression.c") + list(APPEND include_dirs "${CMAKE_BINARY_DIR}/ble_log/include") + if(NOT CMAKE_VERSION VERSION_LESS 3.15.0) + set(Python3_FIND_STRATEGY LOCATION) + find_package(Python3 COMPONENTS Interpreter) + if(Python3_Interpreter_FOUND) + set(BLE_PYTHON_EXECUTABLE ${Python3_EXECUTABLE}) + endif() + else() + find_package(PythonInterp 3) + if(PYTHONINTERP_FOUND) + set(BLE_PYTHON_EXECUTABLE ${PYTHON_EXECUTABLE}) + endif() + endif() + + if(BLE_PYTHON_EXECUTABLE) + set(PYTHON_SCRIPT ${BT_ROOT_PATH}/common/ble_log/extension/log_compression/scripts/ble_log_compress.py) + + set(compressed_srcs "") + set(uncompressed_srcs "") + set(compressed_srcs_with_abs_path "") + + execute_process(COMMAND ${BLE_PYTHON_EXECUTABLE} + ${BT_ROOT_PATH}/common/ble_log/extension/log_compression/scripts/env_check.py + RESULT_VARIABLE result + OUTPUT_VARIABLE out + ERROR_VARIABLE err + ) + + if(NOT ${result} EQUAL 0) + message(WARNING "${err}") + message(WARNING "Exit this log compression due to failure of environment check") + set(LOG_COMPRESS_INCLUDE_DIRS ${include_dirs} PARENT_SCOPE) + set(LOG_COMPRESSION_TARGET "" PARENT_SCOPE) + return() + endif() + + set(CONFIG_FILE_PATH "${CMAKE_BINARY_DIR}/ble_log/module_info.yml") + if(NOT EXISTS "${CONFIG_FILE_PATH}") + file(WRITE "${CMAKE_BINARY_DIR}/ble_log/module_info.yml") + endif() + set(YML_IN "${BT_ROOT_PATH}/common/ble_log/extension/log_compression/scripts/configs/module_info.yml.in") + configure_file(${YML_IN} ${CONFIG_FILE_PATH} @ONLY) + + string(REPLACE ";" "|" MODULE_CODE_PATH "${LOG_COMPRESSED_MODULE_CODE_PATH}") + set(MATCH_PATTERN "(${MODULE_CODE_PATH}).+\\.c") + foreach(src ${srcs}) + if(src MATCHES ${MATCH_PATTERN}) + set(dest "${LOG_COMPRESSED_SRCS_DIR}/${src}") + file(WRITE "${dest}" "") + list(APPEND compressed_srcs ${src}) + list(APPEND compressed_srcs_with_abs_path "${dest}") + else() + list(APPEND uncompressed_srcs ${src}) + endif() + endforeach() + string(REPLACE "|" ";" LOG_COMPRESSED_MODULE_CODE_PATH "${MODULE_CODE_PATH}") + + # Some header files of NIMBLE are not added to include_dirs, + # but rely on relative path searches. This will cause the header + # files to be found due to the change in the source code location + # after using the log compression scheme. + # Therefore, these paths are added to include_dirs here to avoid + # unfinished compilation errors. + if(CONFIG_BT_NIMBLE_ENABLED) + list(APPEND include_dirs + "host/nimble/nimble/nimble/host/src" + "host/nimble/nimble/nimble/host/store/config/src") + endif() + + add_custom_target(ble_log_compression ALL + COMMAND ${BLE_PYTHON_EXECUTABLE} ${PYTHON_SCRIPT} + compress + --compressed_srcs_path "${LOG_COMPRESSED_SRCS_DIR}" + --build_path "${CMAKE_BINARY_DIR}" + --module "'${LOG_COMPRESSED_MODULE}'" + --bt_path "${BT_ROOT_PATH}" + --srcs "'${compressed_srcs}'" + DEPENDS ${compressed_srcs_with_abs_path} ${PYTHON_SCRIPT} + COMMENT "Log compression is being performed, please wait..." + WORKING_DIRECTORY ${BT_ROOT_PATH} + USES_TERMINAL + ) + + function(add_flags_if_in_list file file_list compile_flags) + set(PROCESSED OFF PARENT_SCOPE) + foreach(item IN LISTS file_list) + if(item STREQUAL file) + set_source_files_properties("${LOG_COMPRESSED_SRCS_DIR}/${file}" + PROPERTIES + GENERATED TRUE + COMPILE_FLAGS "${compile_flags}" + OBJECT_DEPENDS "${CMAKE_CURRENT_BINARY_DIR}/ble_log_compression" + ) + set(PROCESSED ON PARENT_SCOPE) + break() + endif() + endforeach() + endfunction() + + foreach(src ${compressed_srcs}) + set(PROCESSED OFF) + if(CONFIG_BT_BLUEDROID_ENABLED) + set(files_with_compile_flags + "host/bluedroid/bta/gatt/bta_gattc_act.c" + "host/bluedroid/bta/gatt/bta_gattc_cache.c" + "host/bluedroid/btc/profile/std/gatt/btc_gatt_util.c" + "host/bluedroid/btc/profile/std/gatt/btc_gatts.c") + add_flags_if_in_list("${src}" + "${files_with_compile_flags}" + "-Wno-address-of-packed-member") + + if(NOT CMAKE_BUILD_EARLY_EXPANSION) + set(jump_table_opts "-fjump-tables") + if(NOT (CMAKE_C_COMPILER_ID MATCHES "Clang") ) + set(jump_table_opts "${jump_table_opts} -ftree-switch-conversion") + endif() + set(files_with_compile_flags + "host/bluedroid/bta/hf_ag/bta_ag_cmd.c" + "host/bluedroid/btc/profile/std/gap/btc_gap_ble.c" + ) + add_flags_if_in_list("${src}" + "${files_with_compile_flags}" + "${jump_table_opts}") + endif() + + if(CMAKE_C_COMPILER_ID MATCHES "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER 15.0) + set(files_with_compile_flags "host/bluedroid/device/controller.c") + add_flags_if_in_list("${src}" + "${files_with_compile_flags}" + "-Wno-unterminated-string-initialization") + endif() + endif() + if(CONFIG_BT_NIMBLE_ENABLED) + if(CONFIG_BT_NIMBLE_MESH) + message(ERROR "The current log compression scheme does not support NIMBLE MESH") + endif() + endif() + if(NOT PROCESSED) + set_source_files_properties("${LOG_COMPRESSED_SRCS_DIR}/${src}" + PROPERTIES GENERATED TRUE + OBJECT_DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/ble_log_compression + ) + endif() + endforeach() + + set(LOG_COMPRESSION_TARGET ble_log_compression PARENT_SCOPE) + # set(LOG_COMPRESSION_TARGET "" PARENT_SCOPE) + set(LOG_COMPRESS_SRCS "${compressed_srcs_with_abs_path};${uncompressed_srcs}" PARENT_SCOPE) + list(APPEND include_dirs "common/ble_log/extension/log_compression/include") + set(LOG_COMPRESS_INCLUDE_DIRS ${include_dirs} PARENT_SCOPE) + else() + set(LOG_COMPRESSION_TARGET "" PARENT_SCOPE) + message("Python 3 used for log compressing not found") + endif() +else() + set(LOG_COMPRESSION_TARGET "" PARENT_SCOPE) + message(STATUS "No module enabled for log compress") +endif() diff --git a/components/bt/common/ble_log/extension/log_compression/Kconfig.in b/components/bt/common/ble_log/extension/log_compression/Kconfig.in new file mode 100644 index 000000000000..100a1dd8bd2c --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/Kconfig.in @@ -0,0 +1,692 @@ + +config BLE_COMPRESSED_LOG_ENABLE + bool "Enable BLE log compression(Preview, Please read help information)" + default n + help + Compress BLE logs during application build to reduce flash usage + and improve output speed. When enabled, log data from Bluetooth + Low Energy components will be compressed before storage, + optimizing both memory footprint and transmission efficiency. + + Note: This library depends on additional Python packages. It will + function correctly only after these dependencies are installed; + refer to: + "components/bt/common/ble_log/log_compression/README.en.md" + for installation instructions. + +if BLE_COMPRESSED_LOG_ENABLE + menuconfig BLE_MESH_COMPRESSED_LOG_ENABLE + bool "Enable BLE Mesh log compression(Preview)" + depends on BLE_COMPRESSED_LOG_ENABLE + depends on BLE_MESH + default n + help + Apply compression to ESP-BLE-MESH protocol stack logs. Requires + base BLE compression to be enabled. Specifically optimizes log + storage and transmission for ble mesh. + + Note: This library depends on additional Python packages. It will + function correctly only after these dependencies are installed; + refer to: + "components/bt/common/ble_log/log_compression/README.en.md" + for installation instructions. + + If the required packages are not installed, the log-compression + mechanism will remain disabled even when this Config is enabled. + + config BLE_MESH_COMPRESSED_LOG_BUFFER_LEN + int "BLE Mesh log buffer length" + depends on BLE_MESH_COMPRESSED_LOG_ENABLE + default 400 + help + Maximum output length for a single log + + if BLE_MESH_COMPRESSED_LOG_ENABLE + menu "Select the stack log tag to be compressed" + config BLE_MESH_STACK_ERR_LOG_COMPRESSION + bool "Compress ERROR log of ESP-BLE-MESH" + default y + help + The error log in the BLE-MESH component will be compressed + config BLE_MESH_STACK_ERR_LOG_PRESERVE + bool "Keep the original error log statement" + depends on BLE_MESH_STACK_ERR_LOG_COMPRESSION + default y + help + When this option is enabled, the log data will be output + through both the compressed log interface and the original + UART interface at the same time, meaning that the log + statements will appear on both paths. However, please note + that this dual-output approach introduces additional code + and string constants, which will increase the size of the + firmware binary file. When this option is disabled, the + logs will no longer be printed through the original UART + output path; instead, they will only be output through the + compressed log interface. As the code and strings related + to the original UART output are omitted, the size of the + firmware binary file can be effectively reduced. + + config BLE_MESH_STACK_WARN_LOG_COMPRESSION + bool "Compress warn log of ESP-BLE-MESH" + default y + help + The warn log in the BLE-MESH component will be compressed + config BLE_MESH_STACK_WARN_LOG_PRESERVE + bool "Keep the original warn log statement" + depends on BLE_MESH_STACK_WARN_LOG_COMPRESSION + default y + help + Please refer to the help information in BLE_MESH_STACK_ERR_LOG_PRESERVE + config BLE_MESH_STACK_INFO_LOG_COMPRESSION + bool "Compress info log of ESP-BLE-MESH" + default y + help + The info log in the BLE-MESH component will be compressed + config BLE_MESH_STACK_INFO_LOG_PRESERVE + bool "Keep the original info log statement" + depends on BLE_MESH_STACK_INFO_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_MESH_STACK_ERR_LOG_PRESERVE + config BLE_MESH_STACK_DEBUG_LOG_COMPRESSION + bool "Compress debug log of ESP-BLE-MESH" + default y + help + The debug log in the BLE-MESH component will be compressed + config BLE_MESH_STACK_DEBUG_LOG_PRESERVE + bool "Keep the original debug log statement" + depends on BLE_MESH_STACK_DEBUG_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_MESH_STACK_ERR_LOG_PRESERVE + endmenu + menu "Select the net buf log tag to be compressed" + config BLE_MESH_NET_BUF_ERR_LOG_COMPRESSION + bool "Compress ERROR log of ESP-BLE-MESH" + default y + help + The error log in the BLE-MESH component will be compressed + config BLE_MESH_NET_BUF_ERR_LOG_PRESERVE + bool "Keep the original error log statement" + depends on BLE_MESH_NET_BUF_ERR_LOG_COMPRESSION + default y + help + When this option is enabled, the log data will be output + through both the compressed log interface and the original + UART interface at the same time, meaning that the log + statements will appear on both paths. However, please note + that this dual-output approach introduces additional code + and string constants, which will increase the size of the + firmware binary file. When this option is disabled, the + logs will no longer be printed through the original UART + output path; instead, they will only be output through the + compressed log interface. As the code and strings related + to the original UART output are omitted, the size of the + firmware binary file can be effectively reduced. + config BLE_MESH_NET_BUF_WARN_LOG_COMPRESSION + bool "Compress warn log of ESP-BLE-MESH" + default y + help + The warn log in the BLE-MESH component will be compressed + config BLE_MESH_NET_BUF_WARN_LOG_PRESERVE + bool "Keep the original warn log statement" + depends on BLE_MESH_NET_BUF_WARN_LOG_COMPRESSION + default y + help + Please refer to the help information in BLE_MESH_NET_BUF_ERR_LOG_PRESERVE + config BLE_MESH_NET_BUF_INFO_LOG_COMPRESSION + bool "Compress info log of ESP-BLE-MESH" + default y + help + The info log in the BLE-MESH component will be compressed + config BLE_MESH_NET_BUF_INFO_LOG_PRESERVE + bool "Keep the original info log statement" + depends on BLE_MESH_NET_BUF_INFO_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_MESH_NET_BUF_ERR_LOG_PRESERVE + config BLE_MESH_NET_BUF_DEBUG_LOG_COMPRESSION + bool "Compress debug log of ESP-BLE-MESH" + default y + help + The debug log in the BLE-MESH component will be compressed + config BLE_MESH_NET_BUF_DEBUG_LOG_PRESERVE + bool "Keep the original debug log statement" + depends on BLE_MESH_NET_BUF_DEBUG_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_MESH_NET_BUF_ERR_LOG_PRESERVE + endmenu + endif + + menuconfig BLE_HOST_COMPRESSED_LOG_ENABLE + bool "Enable BLE Host log compression(Preview, only Bluedroid Host for now)" + depends on BLE_COMPRESSED_LOG_ENABLE + depends on BT_BLUEDROID_ENABLED + default n + help + Apply compression to host logs. Requires + base BLE compression to be enabled. Specifically optimizes log + storage and transmission. + + Note: This library depends on additional Python packages. It will + function correctly only after these dependencies are installed; + refer to: + "components/bt/common/ble_log/log_compression/README.en.md" + for installation instructions. + + config BLE_HOST_COMPRESSED_LOG_BUFFER_LEN + int "Host log buffer length" + depends on BLE_HOST_COMPRESSED_LOG_ENABLE + default 300 + help + Maximum output length for a single log + + if BLE_HOST_COMPRESSED_LOG_ENABLE + menu "Select the BTM layer log tag to be compressed" + config BLE_BLUEDROID_BTM_ERROR_LOG_COMPRESSION + bool "Compress error log of Bluedroid host" + default y + help + The error log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_BTM_ERROR_LOG_PRESERVE + bool "Keep the original error log statement" + depends on BLE_BLUEDROID_BTM_ERROR_LOG_COMPRESSION + default y + help + When this option is enabled, the log data will be output + through both the compressed log interface and the original + UART interface at the same time, meaning that the log + statements will appear on both paths. However, please note + that this dual-output approach introduces additional code + and string constants, which will increase the size of the + firmware binary file. When this option is disabled, the + logs will no longer be printed through the original UART + output path; instead, they will only be output through the + compressed log interface. As the code and strings related + to the original UART output are omitted, the size of the + firmware binary file can be effectively reduced. + + config BLE_BLUEDROID_BTM_WARNING_LOG_COMPRESSION + bool "Compress warning log of Bluedroid host" + default y + help + The warning log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_BTM_WARNING_LOG_PRESERVE + bool "Keep the original warning log statement" + depends on BLE_BLUEDROID_BTM_WARNING_LOG_COMPRESSION + default y + help + Please refer to the help information in BLE_BLUEDROID_BTM_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_BTM_API_LOG_COMPRESSION + bool "Compress api log of Bluedroid host" + default y + help + The api log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_BTM_API_LOG_PRESERVE + bool "Keep the original api log statement" + depends on BLE_BLUEDROID_BTM_API_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_BTM_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_BTM_EVENT_LOG_COMPRESSION + bool "Compress event log of Bluedroid host" + default y + help + The event log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_BTM_EVENT_LOG_PRESERVE + bool "Keep the original event log statement" + depends on BLE_BLUEDROID_BTM_EVENT_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_BTM_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_BTM_DEBUG_LOG_COMPRESSION + bool "Compress debug log of Bluedroid host" + default y + help + The debug log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_BTM_DEBUG_LOG_PRESERVE + bool "Keep the original debug log statement" + depends on BLE_BLUEDROID_BTM_DEBUG_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_BTM_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_BTM_VERBOSE_LOG_COMPRESSION + bool "Compress verbose log of Bluedroid host" + default y + help + The verbose log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_BTM_VERBOSE_LOG_PRESERVE + bool "Keep the original verbose log statement" + depends on BLE_BLUEDROID_BTM_VERBOSE_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_BTM_ERROR_LOG_PRESERVE + + endmenu + menu "Select the LA2CAP layer log tag to be compressed" + config BLE_BLUEDROID_L2CAP_ERROR_LOG_COMPRESSION + bool "Compress error log of Bluedroid host" + default y + help + The error log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_L2CAP_ERROR_LOG_PRESERVE + bool "Keep the original error log statement" + depends on BLE_BLUEDROID_L2CAP_ERROR_LOG_COMPRESSION + default y + help + When this option is enabled, the log data will be output + through both the compressed log interface and the original + UART interface at the same time, meaning that the log + statements will appear on both paths. However, please note + that this dual-output approach introduces additional code + and string constants, which will increase the size of the + firmware binary file. When this option is disabled, the + logs will no longer be printed through the original UART + output path; instead, they will only be output through the + compressed log interface. As the code and strings related + to the original UART output are omitted, the size of the + firmware binary file can be effectively reduced. + + config BLE_BLUEDROID_L2CAP_WARNING_LOG_COMPRESSION + bool "Compress warning log of Bluedroid host" + default y + help + The warning log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_L2CAP_WARNING_LOG_PRESERVE + bool "Keep the original warning log statement" + depends on BLE_BLUEDROID_L2CAP_WARNING_LOG_COMPRESSION + default y + help + Please refer to the help information in BLE_BLUEDROID_L2CAP_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_L2CAP_API_LOG_COMPRESSION + bool "Compress api log of Bluedroid host" + default y + help + The api log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_L2CAP_API_LOG_PRESERVE + bool "Keep the original api log statement" + depends on BLE_BLUEDROID_L2CAP_API_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_L2CAP_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_L2CAP_EVENT_LOG_COMPRESSION + bool "Compress event log of Bluedroid host" + default y + help + The event log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_L2CAP_EVENT_LOG_PRESERVE + bool "Keep the original event log statement" + depends on BLE_BLUEDROID_L2CAP_EVENT_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_L2CAP_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_L2CAP_DEBUG_LOG_COMPRESSION + bool "Compress debug log of Bluedroid host" + default y + help + The debug log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_L2CAP_DEBUG_LOG_PRESERVE + bool "Keep the original debug log statement" + depends on BLE_BLUEDROID_L2CAP_DEBUG_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_L2CAP_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_L2CAP_VERBOSE_LOG_COMPRESSION + bool "Compress verbose log of Bluedroid host" + default y + help + The verbose log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_L2CAP_VERBOSE_LOG_PRESERVE + bool "Keep the original verbose log statement" + depends on BLE_BLUEDROID_L2CAP_VERBOSE_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_L2CAP_ERROR_LOG_PRESERVE + endmenu + menu "Select the GAP layer log tag to be compressed" + config BLE_BLUEDROID_GAP_ERROR_LOG_COMPRESSION + bool "Compress error log of Bluedroid host" + default y + help + The error log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_GAP_ERROR_LOG_PRESERVE + bool "Keep the original error log statement" + depends on BLE_BLUEDROID_GAP_ERROR_LOG_COMPRESSION + default y + help + When this option is enabled, the log data will be output + through both the compressed log interface and the original + UART interface at the same time, meaning that the log + statements will appear on both paths. However, please note + that this dual-output approach introduces additional code + and string constants, which will increase the size of the + firmware binary file. When this option is disabled, the + logs will no longer be printed through the original UART + output path; instead, they will only be output through the + compressed log interface. As the code and strings related + to the original UART output are omitted, the size of the + firmware binary file can be effectively reduced. + + config BLE_BLUEDROID_GAP_WARNING_LOG_COMPRESSION + bool "Compress warning log of Bluedroid host" + default y + help + The warning log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_GAP_WARNING_LOG_PRESERVE + bool "Keep the original warning log statement" + depends on BLE_BLUEDROID_GAP_WARNING_LOG_COMPRESSION + default y + help + Please refer to the help information in BLE_BLUEDROID_GAP_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_GAP_API_LOG_COMPRESSION + bool "Compress api log of Bluedroid host" + default y + help + The api log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_GAP_API_LOG_PRESERVE + bool "Keep the original api log statement" + depends on BLE_BLUEDROID_GAP_API_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_GAP_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_GAP_EVENT_LOG_COMPRESSION + bool "Compress event log of Bluedroid host" + default y + help + The event log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_GAP_EVENT_LOG_PRESERVE + bool "Keep the original event log statement" + depends on BLE_BLUEDROID_GAP_EVENT_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_GAP_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_GAP_DEBUG_LOG_COMPRESSION + bool "Compress debug log of Bluedroid host" + default y + help + The debug log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_GAP_DEBUG_LOG_PRESERVE + bool "Keep the original debug log statement" + depends on BLE_BLUEDROID_GAP_DEBUG_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_GAP_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_GAP_VERBOSE_LOG_COMPRESSION + bool "Compress verbose log of Bluedroid host" + default y + help + The verbose log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_GAP_VERBOSE_LOG_PRESERVE + bool "Keep the original verbose log statement" + depends on BLE_BLUEDROID_GAP_VERBOSE_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_GAP_ERROR_LOG_PRESERVE + endmenu + menu "Select the GATT layer log tag to be compressed" + config BLE_BLUEDROID_GATT_ERROR_LOG_COMPRESSION + bool "Compress error log of Bluedroid host" + default y + help + The error log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_GATT_ERROR_LOG_PRESERVE + bool "Keep the original error log statement" + depends on BLE_BLUEDROID_GATT_ERROR_LOG_COMPRESSION + default y + help + When this option is enabled, the log data will be output + through both the compressed log interface and the original + UART interface at the same time, meaning that the log + statements will appear on both paths. However, please note + that this dual-output approach introduces additional code + and string constants, which will increase the size of the + firmware binary file. When this option is disabled, the + logs will no longer be printed through the original UART + output path; instead, they will only be output through the + compressed log interface. As the code and strings related + to the original UART output are omitted, the size of the + firmware binary file can be effectively reduced. + + config BLE_BLUEDROID_GATT_WARNING_LOG_COMPRESSION + bool "Compress warning log of Bluedroid host" + default y + help + The warning log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_GATT_WARNING_LOG_PRESERVE + bool "Keep the original warning log statement" + depends on BLE_BLUEDROID_GATT_WARNING_LOG_COMPRESSION + default y + help + Please refer to the help information in BLE_BLUEDROID_GATT_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_GATT_API_LOG_COMPRESSION + bool "Compress api log of Bluedroid host" + default y + help + The api log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_GATT_API_LOG_PRESERVE + bool "Keep the original api log statement" + depends on BLE_BLUEDROID_GATT_API_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_GATT_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_GATT_EVENT_LOG_COMPRESSION + bool "Compress event log of Bluedroid host" + default y + help + The event log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_GATT_EVENT_LOG_PRESERVE + bool "Keep the original event log statement" + depends on BLE_BLUEDROID_GATT_EVENT_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_GATT_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_GATT_DEBUG_LOG_COMPRESSION + bool "Compress debug log of Bluedroid host" + default y + help + The debug log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_GATT_DEBUG_LOG_PRESERVE + bool "Keep the original debug log statement" + depends on BLE_BLUEDROID_GATT_DEBUG_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_GATT_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_GATT_VERBOSE_LOG_COMPRESSION + bool "Compress verbose log of Bluedroid host" + default y + help + The verbose log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_GATT_VERBOSE_LOG_PRESERVE + bool "Keep the original verbose log statement" + depends on BLE_BLUEDROID_GATT_VERBOSE_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_GATT_ERROR_LOG_PRESERVE + endmenu + menu "Select the SMP layer log tag to be compressed" + config BLE_BLUEDROID_SMP_ERROR_LOG_COMPRESSION + bool "Compress error log of Bluedroid host" + default y + help + The error log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_SMP_ERROR_LOG_PRESERVE + bool "Keep the original error log statement" + depends on BLE_BLUEDROID_SMP_ERROR_LOG_COMPRESSION + default y + help + When this option is enabled, the log data will be output + through both the compressed log interface and the original + UART interface at the same time, meaning that the log + statements will appear on both paths. However, please note + that this dual-output approach introduces additional code + and string constants, which will increase the size of the + firmware binary file. When this option is disabled, the + logs will no longer be printed through the original UART + output path; instead, they will only be output through the + compressed log interface. As the code and strings related + to the original UART output are omitted, the size of the + firmware binary file can be effectively reduced. + + config BLE_BLUEDROID_SMP_WARNING_LOG_COMPRESSION + bool "Compress warning log of Bluedroid host" + default y + help + The warning log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_SMP_WARNING_LOG_PRESERVE + bool "Keep the original warning log statement" + depends on BLE_BLUEDROID_SMP_WARNING_LOG_COMPRESSION + default y + help + Please refer to the help information in BLE_BLUEDROID_SMP_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_SMP_API_LOG_COMPRESSION + bool "Compress api log of Bluedroid host" + default y + help + The api log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_SMP_API_LOG_PRESERVE + bool "Keep the original api log statement" + depends on BLE_BLUEDROID_SMP_API_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_SMP_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_SMP_EVENT_LOG_COMPRESSION + bool "Compress event log of Bluedroid host" + default y + help + The event log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_SMP_EVENT_LOG_PRESERVE + bool "Keep the original event log statement" + depends on BLE_BLUEDROID_SMP_EVENT_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_SMP_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_SMP_DEBUG_LOG_COMPRESSION + bool "Compress debug log of Bluedroid host" + default y + help + The debug log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_SMP_DEBUG_LOG_PRESERVE + bool "Keep the original debug log statement" + depends on BLE_BLUEDROID_SMP_DEBUG_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_SMP_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_SMP_VERBOSE_LOG_COMPRESSION + bool "Compress verbose log of Bluedroid host" + default y + help + The verbose log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_SMP_VERBOSE_LOG_PRESERVE + bool "Keep the original verbose log statement" + depends on BLE_BLUEDROID_SMP_VERBOSE_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_SMP_ERROR_LOG_PRESERVE + endmenu + menu "Select the APPL layer log tag to be compressed" + config BLE_BLUEDROID_APPL_ERROR_LOG_COMPRESSION + bool "Compress error log of Bluedroid host" + default y + help + The error log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_APPL_ERROR_LOG_PRESERVE + bool "Keep the original error log statement" + depends on BLE_BLUEDROID_APPL_ERROR_LOG_COMPRESSION + default y + help + When this option is enabled, the log data will be output + through both the compressed log interface and the original + UART interface at the same time, meaning that the log + statements will appear on both paths. However, please note + that this dual-output approach introduces additional code + and string constants, which will increase the size of the + firmware binary file. When this option is disabled, the + logs will no longer be printed through the original UART + output path; instead, they will only be output through the + compressed log interface. As the code and strings related + to the original UART output are omitted, the size of the + firmware binary file can be effectively reduced. + + config BLE_BLUEDROID_APPL_WARNING_LOG_COMPRESSION + bool "Compress warning log of Bluedroid host" + default y + help + The warning log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_APPL_WARNING_LOG_PRESERVE + bool "Keep the original warning log statement" + depends on BLE_BLUEDROID_APPL_WARNING_LOG_COMPRESSION + default y + help + Please refer to the help information in BLE_BLUEDROID_APPL_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_APPL_API_LOG_COMPRESSION + bool "Compress api log of Bluedroid host" + default y + help + The api log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_APPL_API_LOG_PRESERVE + bool "Keep the original api log statement" + depends on BLE_BLUEDROID_APPL_API_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_APPL_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_APPL_EVENT_LOG_COMPRESSION + bool "Compress event log of Bluedroid host" + default y + help + The event log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_APPL_EVENT_LOG_PRESERVE + bool "Keep the original event log statement" + depends on BLE_BLUEDROID_APPL_EVENT_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_APPL_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_APPL_DEBUG_LOG_COMPRESSION + bool "Compress debug log of Bluedroid host" + default y + help + The debug log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_APPL_DEBUG_LOG_PRESERVE + bool "Keep the original debug log statement" + depends on BLE_BLUEDROID_APPL_DEBUG_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_APPL_ERROR_LOG_PRESERVE + + config BLE_BLUEDROID_APPL_VERBOSE_LOG_COMPRESSION + bool "Compress verbose log of Bluedroid host" + default y + help + The verbose log in the Bluedroid host component will be compressed + config BLE_BLUEDROID_APPL_VERBOSE_LOG_PRESERVE + bool "Keep the original verbose log statement" + depends on BLE_BLUEDROID_APPL_VERBOSE_LOG_COMPRESSION + default n + help + Please refer to the help information in BLE_BLUEDROID_APPL_ERROR_LOG_PRESERVE + endmenu + endif +endif diff --git a/components/bt/common/ble_log/extension/log_compression/README.cn.md b/components/bt/common/ble_log/extension/log_compression/README.cn.md new file mode 100644 index 000000000000..3f8e00e9deee --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/README.cn.md @@ -0,0 +1,100 @@ +## BLE 日志压缩方案 （Preview） + +### 一、概述 + +本方案通过在编译阶段扫描 BLE 协议栈相关组件的代码，将日志语句中的格式化字符串和参数转换为纯二进制数据，从而提升日志输出效率并减少协议栈所占用的 Flash 空间。 + +目前，该方案已支持对 BLE-MESH 和 BLE-HOST-BLUEDROID 组件的日志压缩。 + +### 二、使用方法 +该功能依赖额外的 Python 库，请按以下步骤安装所需环境。 + +#### 步骤一：验证 ESP-IDF 虚拟环境 +请确保在 ESP-IDF 的 Python 虚拟环境中执行后续操作。可通过以下命令验证当前环境是否已激活： +```bash +idf.py --version +``` +若提示 `command not found`，则表示未激活 ESP-IDF 虚拟环境。 + +请参考官方文档配置并激活环境： +[ESP-IDF 环境设置指南](https://docs.espressif.com/projects/esp-idf/zh_CN/latest/esp32/get-started/linux-macos-setup.html#get-started-linux-macos-first-steps) + +激活后再次执行 `idf.py --version`，若显示版本信息则表明环境已就绪。 + +#### 步骤二：清理缓存文件 +安装日志压缩所需的依赖后，删除之前构建生成的 build 文件夹（如有）。之后重新构建应用程序即可。 + + +### 步骤三：配置 Menuconfig + +使用命令`idf.py menuconfig`打开menuconfig, 以开启`BLE-MESH`组件的日志压缩为例： + +通过路径`(Top) → Component config → Bluetooth → Common Options → BLE Log → Enable BLE Log Module (Experimental) → Settings of BLE Log Compression->Enable BLE Mesh log compression(Preview)`开启`BLE-MESH`组件的日志压缩功能。 + +在`Enable BLE Mesh log compression(Preview)`目录中有三个配置项目可供设置： +1. `BLE Mesh log buffer length` 通过该配置项来配置单条日志可能出现的最大长度。 +2. `Select the stack log tag to be compressed` : 选择期待压缩的BLE-Mesh协议栈日志级别。 +3. `Select the net buf log tag to be compressed`: 选择期待压缩的BLE-Mesh协议栈中Net_buf相关日志级别。 + +在 BLE-Mesh 组件中，日志按级别分为四类：`BT_ERR`、`BT_WARN`、`BT_INFO`、`BT_DBG`. + + 若启用`Compress ERROR log of ESP-BLE-MESH`选项，系统将对 `BT_ERR` 级别日志进行压缩传输。 + 若同时勾选“保留原始错误日志语句”，则 `BT_ERR` 日志会同时通过压缩通道和原串口通道输出；双通道会增加 bin 体积，并延长单次日志的总输出时间（压缩传输耗时 + 串口耗时）。 + +默认策略： +- ERROR 与 WARN → 压缩通道 + 串口通道（双通道） +- INFO 与 DEBUG → 仅压缩通道（串口不再输出） + +因此，在默认配置下，即使开启 BLE-Mesh 的 INFO 级日志，终端也不会打印任何 INFO 内容——它们已被重定向到压缩接口，不再经过串口。 + +### 步骤四：构建应用程序 + +当开启配置项后，使用命令`idf.py build`构建应用程序，请注意构建过程中是否会有警告日志出现，比如出现以下日志时： +```txt +CMake Warning at esp/esp-idf/components/bt/common/ble_log/log_compression/CMakeLists.txt:46 (message): + tree_sitter import failed, please check whether the package is installed + correctly,Please refer to the + file: esp/esp-idf/components/bt/common/ble_log/log_compression/README + for installation instructions. +``` +该警告表示依赖未正确安装，日志压缩构建失败，系统将自动回退至普通编译模式。请重新执行步骤一至步骤四。 + +若日志压缩成功，终端将显示如下信息： +``` +[0/1285] Log compression is being performed, please wait... +Log compression underway, please wait... +Found module BLE_MESH for compression +Found 111 source files in module BLE_MESH requiring compression +3055 ble log(s) compressed +Header file for compressed logs generated +``` +出现该信息表明压缩日志构建成功，其中输出的文件数目和日志数目可能会随版本变更而略有不同。 + +构建成功后，将在 `build/ble_log/` 目录下生成如下结构：： +``` +build/ble_log/ +├── ble_log_database +│ └── BLE_MESH_logs.json +├── ble_script_log_{timestamp}.log +├── .compressed_srcs +│ └── esp_ble_mesh +├── include +│ └── mesh_log_index.h +└── module_info.yml +``` +- `.compressed_srcs`: 压缩处理后的C代码文件。 +- `mesh_log_index.h`: 生成的日志宏头文件。 +- `BLE_MESH_logs.json`: 每条日志的详细信息。 +- `ble_script_log_{timestamp}.log`: 压缩日志在运行过程中产生的日志。 +- `module_info.yml`: 压缩日志对各个模块的配置文件。 + +**注意：这些为自动生成文件，请勿手动修改。** + +### 步骤五、接收日志 +开启日志压缩后， 被压缩组件在默认配置下， 除`ERR`、`WARN`级别的日志外，其余级别的日志将会被重定向到压缩日志接口进行输出，接收日志的方法请参考BLE Log模块的说明文档：[BLE Log Module](../../README.md) + +### 步骤六、解析压缩的日志 +使用日志压缩方案的目的是为了更快的帮助用户解决协议栈的问题， 解析脚本当前还未公布，因此出现问题后，请将生成的日志文件(.bin)和当前IDF的commit提交给 Espressif BLE 团队，由 Espressif BLE 团队负责解析。 + +## 常见问题解决 +1. 如果出现编码后的日志导致编译错误或者找不到宏定义，请删除`build`文件夹后重新构建，如果问题持续存在，请将问题反馈给 Espressif BLE 团队。 \ No newline at end of file diff --git a/components/bt/common/ble_log/extension/log_compression/README.en.md b/components/bt/common/ble_log/extension/log_compression/README.en.md new file mode 100644 index 000000000000..6678d3e0963e --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/README.en.md @@ -0,0 +1,113 @@ +## BLE Log Compression Scheme (Preview) + +### 1、Overview + +This scheme scans the code of BLE stack-related components during the compilation phase, converting formatted strings and parameters in log statements into pure binary data. This improves log output efficiency and reduces the Flash footprint of the protocol stack. + +Currently, the scheme supports log compression for both `BLE-MESH` and `BLE-HOST-BLUEDROID` components. + +--- + +### 2、How to Use +This feature requires additional Python libraries. Please follow the steps below to set up the environment. + +### Step 1: Verify ESP-IDF Virtual Environment +Ensure all subsequent steps are performed within the ESP-IDF Python virtual environment. + +Verify activation by running: +```bash +idf.py --version +``` + +If the output shows `idf.py: command not found`, the virtual environment is not active. + +Refer to the official documentation to configure and activate the environment: +[ESP-IDF Setup Guide](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/get-started/linux-macos-setup.html) + +After activation, run `idf.py --version` again. A version number confirms successful setup. + +#### Step 2: Clean Build Cache +It is recommended to delete the existing build folder (if any) and rebuild the application to ensure a clean environment. + +### Step 3: Configure via Menuconfig + +Run `idf.py menuconfig` and navigate to the following path to enable `BLE-MESH` log compression: + +```(Top) → Component config → Bluetooth → Common Options → BLE Log → Enable BLE Log Module (Experimental) → Settings of BLE Log Compression->Enable BLE Mesh log compression(Preview)```. + +There are three configuration items under this submenu: + +- BLE Mesh log buffer length: Sets the maximum length of a single log entry. + +- Select the stack log tag to be compressed: Select the protocol stack log expect to compress. + +- Select the net buf log tag to be compressed: Select the log of the net_buf part of the protocol stack that expect to compress. + +For example, In the BLE-Mesh component, logs are classified into four levels: `BT_ERR`, `BT_WARN`, `BT_INFO`, and `BT_DBG`. + +Enabling `Compress ERROR logs of ESP-BLE-MESH` causes BT_ERR logs to be transmitted via the compression path. +If `Keep the original error log statement` is also checked, `BT_ERR` logs will be emitted through both the compressed channel and the legacy UART channel. +This dual-path approach increases binary size and extends the total log-output time (compression transmission latency + UART latency). + +Default policy: + + - ERROR & WARN → compressed + UART (dual path) + - INFO & DEBUG → compressed only (UART disabled) + +Consequently, under the default configuration, even when BLE-Mesh INFO-level logging is turned on, no INFO messages appear on the terminal—they are redirected to the compressed interface and no longer pass through the serial port. + +### Step 4: Build the Application + +After configuration, build the application with: +```bash +idf.py build +``` + +Watch for any warnings during the build process. For example: +```txt +CMake Warning at esp/esp-idf/components/bt/common/ble_log/log_compression/CMakeLists.txt:46 (message): + tree_sitter import failed, please check whether the package is installed + correctly,Please refer to the + file: esp/esp-idf/components/bt/common/ble_log/log_compression/README + for installation instructions. +``` +This indicates that the dependencies were not installed correctly, and log compression has failed—falling back to a normal build. Please repeat Steps 1–4. + +If log compression is successful, you will see output similar to: +``` +[0/1285] Log compression is being performed, please wait... +Log compression underway, please wait... +Found module BLE_MESH for compression +Found 111 source files in module BLE_MESH requiring compression +3055 ble log(s) compressed +Header file for compressed logs generated +``` +After a successful build, the following structure will be generated under `build/ble_log/`: +``` +build/ble_log/ +├── ble_log_database +│ └── BLE_MESH_logs.json +├── ble_script_log_{timestamp}.log +├── .compressed_srcs +│ └── esp_ble_mesh +├── include +│ └── mesh_log_index.h +└── module_info.yml +``` +- `.compressed_srcs`: Compressed C source files. +- `mesh_log_index.h`: Generated header file containing log macros. +- `BLE_MESH_logs.json`: Detailed information for each log entry. +- `ble_script_log_{timestamp}.log`: Log generated by the compression script. +- `module_info.yml`: Configuration file for compressed logging across modules. + +**Do not modify these auto-generated files.** + +### Step 5: Receive Logs +With log compression enabled and under the default configuration, all log levels except ERR and WARN generated by the compressed component will be redirected to the compression-log interface for output. Please refer to the BLE Log module’s documentation for how to receive these logs: [BLE Log module](../../README.md). + +### Step 6: Decode compressed Logs +The purpose of the log-compression scheme is to help users identify protocol-stack issues more quickly. +As the parsing script has not yet been released, please submit the generated log file (.bin) along with the current IDF commit hash to the Espressif BLE team, who will handle the analysis. + +## Frequently Asked Questions +1. If encoded logs cause compilation errors or missing macro definitions, delete the build folder and rebuild. If the issue persists, please report it to the Espressif BLE team. \ No newline at end of file diff --git a/components/bt/common/ble_log/extension/log_compression/ble_log_compression.c b/components/bt/common/ble_log/extension/log_compression/ble_log_compression.c new file mode 100644 index 000000000000..382c33a2cfce --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/ble_log_compression.c @@ -0,0 +1,263 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include + +// Private includes +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "sdkconfig.h" +#include "ble_log_util.h" +#include "log_compression/utils.h" + +#if CONFIG_BLE_COMPRESSED_LOG_ENABLE + +#define BUF_NAME(name, idx) name##_buffer##idx +#define BUF_MGMT_NAME(name) name##_log_buffer_mgmt + +#define DECL_BUF_OP(name, len, idx) \ + static uint8_t BUF_NAME(name, idx)[len]; + +#define INIT_MAP_OP(name, _, buffer_idx) \ + {.busy = 0, \ + .idx = 0, \ + .buffer = BUF_NAME(name, buffer_idx), \ + .len = sizeof(BUF_NAME(name, buffer_idx))}, + +#define DECLARE_BUFFERS(NAME, BUF_LEN, BUF_CNT) \ + FOR_EACH_IDX(DECL_BUF_OP, NAME, BUF_LEN, GEN_INDEX(BUF_CNT)); + +#define INIT_BUFFER_MGMT(NAME, BUF_CNT) \ + ble_cp_log_buffer_mgmt_t BUF_MGMT_NAME(NAME)[BUF_CNT] = { \ + FOR_EACH_IDX(INIT_MAP_OP, NAME, 0, GEN_INDEX(BUF_CNT)) \ + }; + +#if CONFIG_BLE_MESH_COMPRESSED_LOG_ENABLE +DECLARE_BUFFERS(mesh, CONFIG_BLE_MESH_COMPRESSED_LOG_BUFFER_LEN, LOG_CP_MAX_LOG_BUFFER_USED_SIMU); +INIT_BUFFER_MGMT(mesh, LOG_CP_MAX_LOG_BUFFER_USED_SIMU); +char * mesh_last_task_handle = NULL; +#endif + +#if CONFIG_BLE_HOST_COMPRESSED_LOG_ENABLE +DECLARE_BUFFERS(host, CONFIG_BLE_HOST_COMPRESSED_LOG_BUFFER_LEN, LOG_CP_MAX_LOG_BUFFER_USED_SIMU); +INIT_BUFFER_MGMT(host, LOG_CP_MAX_LOG_BUFFER_USED_SIMU); +char * host_last_task_handle = NULL; +#endif + +/* The maximum number of supported parameters is 64 */ +#define LOG_HEADER(log_type, info) ((log_type << 6) | (info & 0x3f)) + +int ble_compressed_log_cb_get(uint8_t source, ble_cp_log_buffer_mgmt_t **mgmt) +{ + ble_cp_log_buffer_mgmt_t *buffer_mgmt = NULL; + char ** last_handle = NULL; + char * cur_handle = pcTaskGetName(NULL); + + switch (source) + { +#if CONFIG_BLE_MESH_COMPRESSED_LOG_ENABLE + case BLE_COMPRESSED_LOG_OUT_SOURCE_MESH: + buffer_mgmt = BUF_MGMT_NAME(mesh); + last_handle = &mesh_last_task_handle; + break; +#endif +#if CONFIG_BLE_HOST_COMPRESSED_LOG_ENABLE + case BLE_COMPRESSED_LOG_OUT_SOURCE_HOST: + buffer_mgmt = BUF_MGMT_NAME(host); + last_handle = &host_last_task_handle; + break; +#endif + default: + assert(0 && "Unsupported log source"); + break; + } + + for (int i = 0; i < LOG_CP_MAX_LOG_BUFFER_USED_SIMU; i++) { + if (ble_log_cas_acquire(&(buffer_mgmt[i].busy))) { + *mgmt = &buffer_mgmt[i]; + ble_log_cp_push_u8(*mgmt, source); + if (*last_handle == NULL || + *last_handle != cur_handle) { + ble_log_cp_push_u8(*mgmt, LOG_HEADER(LOG_TYPE_INFO, LOG_TYPE_INFO_TASK_SWITCH)); + *last_handle = cur_handle; + } + return 0; + } + } + + return -1; +} + +static inline int ble_compressed_log_buffer_free(ble_cp_log_buffer_mgmt_t *mgmt) +{ +#if BLE_LOG_CP_CONTENT_CHECK_ENBALE + memset(mgmt->buffer, BLE_LOG_CP_CONTENT_CHECK_VAL, mgmt->idx); +#endif + mgmt->idx = 0; + ble_log_cas_release(&mgmt->busy); + return 0; +} + +int ble_log_compressed_hex_print(uint8_t source, uint32_t log_index, size_t args_cnt, ...) +{ + ble_cp_log_buffer_mgmt_t *mgmt = NULL; + uint8_t arg_type = 0; + va_list args; + + ble_compressed_log_cb_get(source, &mgmt); + + if (args_cnt == 0) { + ble_log_cp_push_u8(mgmt, LOG_HEADER(LOG_TYPE_HEX_ARGS, 0)); + ble_log_cp_push_u16(mgmt, log_index); + ble_compressed_log_output(source, mgmt->buffer, mgmt->idx); + ble_compressed_log_buffer_free(mgmt); + return 0; + } + + va_start(args, args_cnt); + + ble_log_cp_push_u8(mgmt, LOG_HEADER(LOG_TYPE_HEX_ARGS, args_cnt)); + ble_log_cp_push_u16(mgmt, log_index); + uint8_t size_info_idx = mgmt->idx; + uint8_t *cur = &(mgmt->buffer)[mgmt->idx]; + uint8_t size_info = 0; + + for (size_t i = 0; i < args_cnt; i++) { + if (i % 2) { + arg_type = va_arg(args, size_t); + ble_log_cp_push_u8(mgmt, size_info|arg_type); + size_info = 0; + cur++; + } else { + arg_type = va_arg(args, size_t); + if (i == args_cnt - 1) { + ble_log_cp_push_u8(mgmt, arg_type); + } else { + size_info = arg_type << 4; + } + } + if (arg_type >= ARG_SIZE_TYPE_MAX) { + printf("Found invalid arg type %08lx type %d", log_index, arg_type); + assert(0); + } + } + + cur = &(mgmt->buffer)[size_info_idx]; + + for (size_t i = 0; i < args_cnt; i++) { + if (i % 2) { + arg_type = (*cur) & 0x0f; + cur++; + } else { + arg_type = (*cur) >> 4; + } + switch(arg_type) { + case ARG_SIZE_TYPE_U32: + uint32_t u32v = va_arg(args, size_t); + if (likely(u32v)) { + if (u32v <= 0xff) { + ble_log_cp_push_u8(mgmt, 3); + ble_log_cp_push_u8(mgmt, u32v); + ble_log_cp_update_half_byte(mgmt, size_info_idx + i/2, ARG_SIZE_TYPE_LZU32, !(i%2)); + break; + } else if (u32v <= 0xffff) { + ble_log_cp_push_u8(mgmt, 2); + ble_log_cp_push_u16(mgmt, u32v); + ble_log_cp_update_half_byte(mgmt, size_info_idx + i/2, ARG_SIZE_TYPE_LZU32, !(i%2)); + break; + } else { + ble_log_cp_push_u32(mgmt, u32v); + } + } else { + ble_log_cp_update_half_byte(mgmt, size_info_idx + i/2, ARG_SIZE_TYPE_AZU32, !(i%2)); + } + break; + case ARG_SIZE_TYPE_U64: + uint64_t u64v = va_arg(args, uint64_t); + if (likely(u64v)) { + if (unlikely(u64v >> 48)) { + ble_log_cp_push_u64(mgmt, u64v); + } else { + uint32_t tmpv = 0; + uint8_t lz = 0; + if (likely(u64v <= UINT32_MAX)) { + tmpv = (uint32_t)u64v; + lz = 4; + } else { + tmpv = u64v >> 32; + } + lz += __builtin_clz(tmpv) / 8; + ble_log_cp_push_u8(mgmt, lz); + switch (8-lz) { + case 5: + ble_log_cp_push_u32(mgmt, (uint32_t)u64v); + [[fallthrough]]; + case 1: + ble_log_cp_push_u8(mgmt, (uint8_t)tmpv); + break; + case 6: + ble_log_cp_push_u32(mgmt, (uint32_t)u64v); + [[fallthrough]]; + case 2: + ble_log_cp_push_u16(mgmt, (uint16_t)tmpv); + break; + case 7: + ble_log_cp_push_u32(mgmt, (uint32_t)u64v); + [[fallthrough]]; + case 3: + ble_log_cp_push_u8(mgmt, (uint8_t)tmpv); + ble_log_cp_push_u16(mgmt, (uint16_t)(tmpv >> 8)); + break; + default: + assert(0); + break; + } + ble_log_cp_update_half_byte(mgmt, size_info_idx + i/2, ARG_SIZE_TYPE_LZU64, !(i%2)); + } + } else { + ble_log_cp_update_half_byte(mgmt, size_info_idx + i/2, ARG_SIZE_TYPE_AZU64, !(i%2)); + } + break; + case ARG_SIZE_TYPE_STR: + char *str_p = (char *)va_arg(args, char *); + ble_log_cp_push_buf(mgmt, (const uint8_t *)str_p, strlen(str_p) + 1); + break; + default: + printf("Invalid size %d\n", arg_type); + assert(0); + break; + } + } + + ble_compressed_log_output(source, mgmt->buffer, mgmt->idx); + ble_compressed_log_buffer_free(mgmt); + va_end(args); + return 0; +} + +int ble_log_compressed_hex_print_buf(uint8_t source, uint32_t log_index, uint8_t buf_idx, const uint8_t *buf, size_t len) +{ + ble_cp_log_buffer_mgmt_t *mgmt = NULL; + + ble_compressed_log_cb_get(source, &mgmt); + + if (buf == NULL && len != 0) { + ble_log_cp_push_u8(mgmt, LOG_HEADER(LOG_TYPE_INFO, LOG_TYPE_INFO_NULL_BUF)); + ble_log_cp_push_u16(mgmt, log_index); + ble_compressed_log_output(source, mgmt->buffer, mgmt->idx); + ble_compressed_log_buffer_free(mgmt); + return 0; + } + + ble_log_cp_push_u8(mgmt, LOG_HEADER(LOG_TYPE_HEX_BUF, buf_idx)); + ble_log_cp_push_u16(mgmt, log_index); + ble_log_cp_push_buf(mgmt, buf, len); + ble_compressed_log_output(source, mgmt->buffer, mgmt->idx); + ble_compressed_log_buffer_free(mgmt); + return 0; +} +#endif /* CONFIG_BLE_COMPRESSED_LOG_ENABLE */ diff --git a/components/bt/common/ble_log/extension/log_compression/cmake/ble_host_bluedroid_tags.cmake b/components/bt/common/ble_log/extension/log_compression/cmake/ble_host_bluedroid_tags.cmake new file mode 100644 index 000000000000..0a0de9b997e6 --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/cmake/ble_host_bluedroid_tags.cmake @@ -0,0 +1,160 @@ +set(_BLE_HOST_TAG_MAP + # BTM Layer + CONFIG_BLE_BLUEDROID_BTM_ERROR_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_BTM_ERROR_LOG_PRESERVE + BTM_TRACE_ERROR + + CONFIG_BLE_BLUEDROID_BTM_WARNING_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_BTM_WARNING_LOG_PRESERVE + BTM_TRACE_WARNING + + CONFIG_BLE_BLUEDROID_BTM_API_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_BTM_API_LOG_PRESERVE + BTM_TRACE_API + + CONFIG_BLE_BLUEDROID_BTM_EVENT_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_BTM_EVENT_LOG_PRESERVE + BTM_TRACE_EVENT + + CONFIG_BLE_BLUEDROID_BTM_DEBUG_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_BTM_DEBUG_LOG_PRESERVE + BTM_TRACE_DEBUG + + CONFIG_BLE_BLUEDROID_BTM_VERBOSE_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_BTM_VERBOSE_LOG_PRESERVE + BTM_TRACE_VERBOSE + + # L2CAP Layer + CONFIG_BLE_BLUEDROID_L2CAP_ERROR_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_L2CAP_ERROR_LOG_PRESERVE + L2CAP_TRACE_ERROR + + CONFIG_BLE_BLUEDROID_L2CAP_WARNING_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_L2CAP_WARNING_LOG_PRESERVE + L2CAP_TRACE_WARNING + + CONFIG_BLE_BLUEDROID_L2CAP_API_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_L2CAP_API_LOG_PRESERVE + L2CAP_TRACE_API + + CONFIG_BLE_BLUEDROID_L2CAP_EVENT_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_L2CAP_EVENT_LOG_PRESERVE + L2CAP_TRACE_EVENT + + CONFIG_BLE_BLUEDROID_L2CAP_DEBUG_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_L2CAP_DEBUG_LOG_PRESERVE + L2CAP_TRACE_DEBUG + + CONFIG_BLE_BLUEDROID_L2CAP_VERBOSE_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_L2CAP_VERBOSE_LOG_PRESERVE + L2CAP_TRACE_VERBOSE + + # GAP Layer + CONFIG_BLE_BLUEDROID_GAP_ERROR_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_GAP_ERROR_LOG_PRESERVE + GAP_TRACE_ERROR + + CONFIG_BLE_BLUEDROID_GAP_WARNING_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_GAP_WARNING_LOG_PRESERVE + GAP_TRACE_WARNING + + CONFIG_BLE_BLUEDROID_GAP_API_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_GAP_API_LOG_PRESERVE + GAP_TRACE_API + + CONFIG_BLE_BLUEDROID_GAP_EVENT_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_GAP_EVENT_LOG_PRESERVE + GAP_TRACE_EVENT + + CONFIG_BLE_BLUEDROID_GAP_DEBUG_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_GAP_DEBUG_LOG_PRESERVE + GAP_TRACE_DEBUG + + CONFIG_BLE_BLUEDROID_GAP_VERBOSE_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_GAP_VERBOSE_LOG_PRESERVE + GAP_TRACE_VERBOSE + + # GATT Layer + CONFIG_BLE_BLUEDROID_GATT_ERROR_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_GATT_ERROR_LOG_PRESERVE + GATT_TRACE_ERROR + + CONFIG_BLE_BLUEDROID_GATT_WARNING_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_GATT_WARNING_LOG_PRESERVE + GATT_TRACE_WARNING + + CONFIG_BLE_BLUEDROID_GATT_API_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_GATT_API_LOG_PRESERVE + GATT_TRACE_API + + CONFIG_BLE_BLUEDROID_GATT_EVENT_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_GATT_EVENT_LOG_PRESERVE + GATT_TRACE_EVENT + + CONFIG_BLE_BLUEDROID_GATT_DEBUG_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_GATT_DEBUG_LOG_PRESERVE + GATT_TRACE_DEBUG + + CONFIG_BLE_BLUEDROID_GATT_VERBOSE_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_GATT_VERBOSE_LOG_PRESERVE + GATT_TRACE_VERBOSE + + # SMP Layer + CONFIG_BLE_BLUEDROID_SMP_ERROR_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_SMP_ERROR_LOG_PRESERVE + SMP_TRACE_ERROR + + CONFIG_BLE_BLUEDROID_SMP_WARNING_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_SMP_WARNING_LOG_PRESERVE + SMP_TRACE_WARNING + + CONFIG_BLE_BLUEDROID_SMP_API_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_SMP_API_LOG_PRESERVE + SMP_TRACE_API + + CONFIG_BLE_BLUEDROID_SMP_EVENT_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_SMP_EVENT_LOG_PRESERVE + SMP_TRACE_EVENT + + CONFIG_BLE_BLUEDROID_SMP_DEBUG_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_SMP_DEBUG_LOG_PRESERVE + SMP_TRACE_DEBUG + + CONFIG_BLE_BLUEDROID_SMP_VERBOSE_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_SMP_VERBOSE_LOG_PRESERVE + SMP_TRACE_VERBOSE + + # APPL Layer + CONFIG_BLE_BLUEDROID_APPL_ERROR_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_APPL_ERROR_LOG_PRESERVE + APPL_TRACE_ERROR + + CONFIG_BLE_BLUEDROID_APPL_WARNING_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_APPL_WARNING_LOG_PRESERVE + APPL_TRACE_WARNING + + CONFIG_BLE_BLUEDROID_APPL_API_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_APPL_API_LOG_PRESERVE + APPL_TRACE_API + + CONFIG_BLE_BLUEDROID_APPL_EVENT_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_APPL_EVENT_LOG_PRESERVE + APPL_TRACE_EVENT + + CONFIG_BLE_BLUEDROID_APPL_DEBUG_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_APPL_DEBUG_LOG_PRESERVE + APPL_TRACE_DEBUG + + CONFIG_BLE_BLUEDROID_APPL_VERBOSE_LOG_COMPRESSION + CONFIG_BLE_BLUEDROID_APPL_VERBOSE_LOG_PRESERVE + APPL_TRACE_VERBOSE + +) + +include(${CMAKE_CURRENT_LIST_DIR}/tag_table_function.cmake) + +set(BLE_HOST_TAGS "") +set(BLE_HOST_TAGS_PRESERVE "") +tag_table_to_lists(_BLE_HOST_TAG_MAP BLE_HOST_TAGS BLE_HOST_TAGS_PRESERVE) +set(BLE_HOST_TAGS "${BLE_HOST_TAGS}" PARENT_SCOPE) +set(BLE_HOST_TAGS_PRESERVE "${BLE_HOST_TAGS_PRESERVE}" PARENT_SCOPE) diff --git a/components/bt/common/ble_log/extension/log_compression/cmake/ble_mesh_log_tags.cmake b/components/bt/common/ble_log/extension/log_compression/cmake/ble_mesh_log_tags.cmake new file mode 100644 index 000000000000..6cfa11425bb6 --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/cmake/ble_mesh_log_tags.cmake @@ -0,0 +1,41 @@ +set(_BLE_MESH_TAG_MAP + CONFIG_BLE_MESH_STACK_ERR_LOG_COMPRESSION + CONFIG_BLE_MESH_STACK_ERR_LOG_PRESERVE + BT_ERR + + CONFIG_BLE_MESH_STACK_WARN_LOG_COMPRESSION + CONFIG_BLE_MESH_STACK_WARN_LOG_PRESERVE + BT_WARN + + CONFIG_BLE_MESH_STACK_INFO_LOG_COMPRESSION + CONFIG_BLE_MESH_STACK_INFO_LOG_PRESERVE + BT_INFO + + CONFIG_BLE_MESH_STACK_DEBUG_LOG_COMPRESSION + CONFIG_BLE_MESH_STACK_DEBUG_LOG_PRESERVE + BT_DBG + + CONFIG_BLE_MESH_NET_BUF_ERR_LOG_COMPRESSION + CONFIG_BLE_MESH_NET_BUF_ERR_LOG_PRESERVE + NET_BUF_ERR + + CONFIG_BLE_MESH_NET_BUF_WARN_LOG_COMPRESSION + CONFIG_BLE_MESH_NET_BUF_WARN_LOG_PRESERVE + NET_BUF_WARN + + CONFIG_BLE_MESH_NET_BUF_INFO_LOG_COMPRESSION + CONFIG_BLE_MESH_NET_BUF_INFO_LOG_PRESERVE + NET_BUF_INFO + + CONFIG_BLE_MESH_NET_BUF_DEBUG_LOG_COMPRESSION + CONFIG_BLE_MESH_NET_BUF_DEBUG_LOG_PRESERVE + NET_BUF_DBG +) + +include(${CMAKE_CURRENT_LIST_DIR}/tag_table_function.cmake) + +set(BLE_MESH_TAGS "") +set(BLE_MESH_TAGS_PRESERVE "") +tag_table_to_lists(_BLE_MESH_TAG_MAP BLE_MESH_TAGS BLE_MESH_TAGS_PRESERVE) +set(BLE_MESH_TAGS "${BLE_MESH_TAGS}" PARENT_SCOPE) +set(BLE_MESH_TAGS_PRESERVE "${BLE_MESH_TAGS_PRESERVE}" PARENT_SCOPE) diff --git a/components/bt/common/ble_log/extension/log_compression/cmake/tag_table_function.cmake b/components/bt/common/ble_log/extension/log_compression/cmake/tag_table_function.cmake new file mode 100644 index 000000000000..a92724cbb006 --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/cmake/tag_table_function.cmake @@ -0,0 +1,33 @@ +# Usage： +# set(MY_TABLE CONFIG_FOO_ON CONFIG_FOO_KEEP TAG_FOO ...) +# tag_table_to_lists(MY_TABLE OUT_TAGS OUT_PRESERVE) +function(tag_table_to_lists TABLE_NAME OUT_TAGS OUT_PRESERVE) + set(_tags "") + set(_preserve "") + set(_map ${${TABLE_NAME}}) + + list(LENGTH _map _len) + math(EXPR _stop "${_len} - 1") + + foreach(i RANGE 0 ${_stop} 3) + math(EXPR _i1 "${i} + 1") + math(EXPR _i2 "${i} + 2") + + list(GET _map ${i} _comp) + list(GET _map ${_i1} _pres) + list(GET _map ${_i2} _tag) + + if(${_comp}) + list(APPEND _tags "${_tag}") + if(${_pres}) + list(APPEND _preserve "${_tag}") + endif() + endif() + endforeach() + + list(JOIN _tags ", " _tags_str) + list(JOIN _preserve ", " _preserve_str) + + set(${OUT_TAGS} "${_tags_str}" PARENT_SCOPE) + set(${OUT_PRESERVE} "${_preserve_str}" PARENT_SCOPE) +endfunction() diff --git a/components/bt/common/ble_log/extension/log_compression/include/log_compression/utils.h b/components/bt/common/ble_log/extension/log_compression/include/log_compression/utils.h new file mode 100644 index 000000000000..5365939e0ecc --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/include/log_compression/utils.h @@ -0,0 +1,189 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _BLE_LOG_COMPRESSION_UTILS_H +#define _BLE_LOG_COMPRESSION_UTILS_H + +#include "ble_log.h" + +#define CONCAT(a, b) a##b +#define _CONCAT(a, b) CONCAT(a, b) + +#define _0 0 +#define _1 1 +#define _2 2 +#define _3 3 +#define _4 4 +#define _5 5 +#define _6 6 +#define _7 7 +#define _8 8 +#define _9 9 + +#define __COUNT_ARGS(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _n, X...) _n +#define COUNT_ARGS(X...) __COUNT_ARGS(, ##X, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) + +#define FOR_EACH_IDX(macro, name, len, ...) \ + _CONCAT(_FOR_EACH_, COUNT_ARGS(__VA_ARGS__))(macro, name, len, __VA_ARGS__) + +#define _FOR_EACH_0(m, n, l, ...) +#define _FOR_EACH_1(m, n, l, i1, ...) m(n, l, i1) +#define _FOR_EACH_2(m, n, l, i1, ...) m(n, l, i1) _FOR_EACH_1(m, n, l, __VA_ARGS__) +#define _FOR_EACH_3(m, n, l, i1, ...) m(n, l, i1) _FOR_EACH_2(m, n, l, __VA_ARGS__) +#define _FOR_EACH_4(m, n, l, i1, ...) m(n, l, i1) _FOR_EACH_3(m, n, l, __VA_ARGS__) +#define _FOR_EACH_5(m, n, l, i1, ...) m(n, l, i1) _FOR_EACH_4(m, n, l, __VA_ARGS__) + +#define _GEN_INDEX_0() +#define _GEN_INDEX_1() _0 +#define _GEN_INDEX_2() _0, _1 +#define _GEN_INDEX_3() _0, _1, _2 +#define _GEN_INDEX_4() _0, _1, _2, _3 +#define _GEN_INDEX_5() _0, _1, _2, _3, _4 +#define GEN_INDEX(n) _CONCAT(_GEN_INDEX_, n)() + + +enum { + BLE_COMPRESSED_LOG_OUT_SOURCE_HOST, + BLE_COMPRESSED_LOG_OUT_SOURCE_MESH, +}; + +enum { + ARG_SIZE_TYPE_U32, /* argument type with 4 bytes */ + ARG_SIZE_TYPE_STR, /* argument type with strings */ + ARG_SIZE_TYPE_U64, /* argument type with 8 bytes */ + ARG_SIZE_TYPE_LZU32, /* argument type with 4 bytes but with leading zeros */ + ARG_SIZE_TYPE_LZU64, /* argument type with 8 bytes but with leading zeros */ + ARG_SIZE_TYPE_AZU32, /* argument type with 4 bytes but all zeros */ + ARG_SIZE_TYPE_AZU64, /* argument type with 8 bytes but all zeros */ + ARG_SIZE_TYPE_MAX, +}; + +/* The maximum number of buffers used simultaneously */ +#define LOG_CP_MAX_LOG_BUFFER_USED_SIMU 3 + +#define LOG_TYPE_ZERO_ARGS 0 +#define LOG_TYPE_HEX_ARGS 1 +#define LOG_TYPE_HEX_BUF 2 +/* This type of message is used to update log information, + * such as there is currently a new task log */ +#define LOG_TYPE_INFO 3 + +#define LOG_TYPE_INFO_TASK_ID_UPDATE 0 +#define LOG_TYPE_INFO_NULL_BUF 1 +#define LOG_TYPE_INFO_TASK_SWITCH 2 + +typedef struct { + volatile bool busy; + uint8_t *buffer; + uint16_t idx; + uint16_t len; +} ble_cp_log_buffer_mgmt_t; + +#define CONTENT_CHECK(idx, buf, except_val, len) +#define LENGTH_CHECK(idx, pbuffer_mgmt) do ( if(unlikely((idx) > (pbuffer_mgmt->len))) assert(0 && "Maximum log buffer length exceeded");) while(0) + +#define BLE_LOG_CP_CONTENT_CHECK_ENBALE 0 +#define BLE_LOG_CP_CONTENT_CHECK_VAL 0x00 + +static inline int ble_log_cp_buffer_safe_check(ble_cp_log_buffer_mgmt_t *pbuf_mgmt, uint16_t write_len) +{ + if ((pbuf_mgmt->idx + write_len) > pbuf_mgmt->len) { + printf("Maximum length of buffer(%p) idx %d write_len %d exceed\n", pbuf_mgmt, pbuf_mgmt->idx, write_len); + return -1; + } +#if BLE_LOG_CP_CONTENT_CHECK_ENBALE + for (int i = pbuf_mgmt->idx; i < pbuf_mgmt->idx + write_len; i++) { + if (pbuf_mgmt->buffer[i] != BLE_LOG_CP_CONTENT_CHECK_VAL) { + printf("The value(%02x) in the buffer does not match the expected(%02x)\n", pbuf_mgmt->buffer[i], BLE_LOG_CP_CONTENT_CHECK_VAL); + return -1; + } + } +#endif + return 0; +} + +static inline int ble_log_cp_push_u8(ble_cp_log_buffer_mgmt_t *pbuf_mgmt, uint8_t val) +{ + if (ble_log_cp_buffer_safe_check(pbuf_mgmt, 1)) { + return -1; + } + pbuf_mgmt->buffer[pbuf_mgmt->idx] = val; + pbuf_mgmt->idx++; + return 0; +} + +static inline int ble_log_cp_push_u16(ble_cp_log_buffer_mgmt_t *pbuf_mgmt, uint16_t val) +{ + if (ble_log_cp_buffer_safe_check(pbuf_mgmt, 2)) { + return -1; + } + uint16_t *p = (uint16_t *)&(pbuf_mgmt->buffer[pbuf_mgmt->idx]); + *p = val; + pbuf_mgmt->idx+=2; + return 0; +} + +static inline int ble_log_cp_push_u32(ble_cp_log_buffer_mgmt_t *pbuf_mgmt, uint32_t val) +{ + if (ble_log_cp_buffer_safe_check(pbuf_mgmt, 4)) { + return -1; + } + uint32_t *p = (uint32_t *)&(pbuf_mgmt->buffer[pbuf_mgmt->idx]); + *p = val; + pbuf_mgmt->idx+=4; + return 0; +} + +static inline int ble_log_cp_push_u64(ble_cp_log_buffer_mgmt_t *pbuf_mgmt, uint64_t val) +{ + if (ble_log_cp_buffer_safe_check(pbuf_mgmt, 8)) { + return -1; + } + uint64_t *p = (uint64_t *)&(pbuf_mgmt->buffer[pbuf_mgmt->idx]); + *p = val; + pbuf_mgmt->idx+=8; + return 0; +} + +static inline int ble_log_cp_push_buf(ble_cp_log_buffer_mgmt_t *pbuf_mgmt, const uint8_t *buf, uint16_t len) +{ + if (ble_log_cp_buffer_safe_check(pbuf_mgmt, len)) { + return -1; + } + uint8_t *p = (uint8_t *)&(pbuf_mgmt->buffer[pbuf_mgmt->idx]); + memcpy(p, buf, len); + pbuf_mgmt->idx+=len; + return 0; +} + +static inline int ble_log_cp_update_half_byte(ble_cp_log_buffer_mgmt_t *pbuf_mgmt, + uint16_t idx, uint8_t new_data, uint8_t high) +{ + if (pbuf_mgmt->idx <= idx) { + return -1; + } + uint8_t old_val = pbuf_mgmt->buffer[idx]; + if (high) { + pbuf_mgmt->buffer[idx] = (old_val & 0x0f) | (new_data << 4); + } else { + pbuf_mgmt->buffer[idx] = (old_val & 0xf0) | (new_data & 0x0f); + } + return 0; +} + +static inline int ble_log_cp_buffer_print(ble_cp_log_buffer_mgmt_t *pbuf_mgmt) +{ + for (size_t i = 0; i < pbuf_mgmt->idx; i++) { + printf("%02x ", pbuf_mgmt->buffer[i]); + } + printf("\n"); + return 0; +} + +static inline int ble_compressed_log_output(uint8_t source, uint8_t *data, uint16_t len) +{ + return ble_log_write_hex(BLE_LOG_SRC_ENCODE, data, len); +} +#endif /* _BLE_LOG_COMPRESSION_UTILS_H */ diff --git a/components/bt/common/ble_log/extension/log_compression/scripts/LogDBManager.py b/components/bt/common/ble_log/extension/log_compression/scripts/LogDBManager.py new file mode 100644 index 000000000000..2f70e637043a --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/scripts/LogDBManager.py @@ -0,0 +1,439 @@ +# SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +# ruff: noqa: UP007 +""" +Log Database Manager +==================== +Manages the storage and retrieval of compressed log metadata using a multiprocessing-safe database. +""" +import atexit +import hashlib +import json +import logging +import os +import tempfile +import threading +from collections.abc import Mapping +from pathlib import Path +from types import TracebackType +from typing import Any +from typing import Union + +LOGGER = logging.getLogger('log_db_manager') + + +class LogDBManager: + """Manages log compression metadata in a multiprocessing-safe manner.""" + + # Operation result codes + SUCCESS = 0 + LOG_EXISTS = 1 + OPERATION_FAILED = 2 + + SOURCE_LOG_UPDATE_FULL = 0 + SOURCE_LOG_UPDATE_PARTIAL = 1 + SOURCE_LOG_UPDATE_NONE = 2 + + def __init__(self, data_dir: str, sources: Mapping[str, str], logger: Union[logging.Logger, None] = None): + """ + Initialize the log database manager. + + Args: + data_dir: Directory for database files + sources: List of log sources/modules + logger: Optional logger instance + """ + self.logger = logger or LOGGER + self.data_dir = Path(data_dir) + self.sources = [s.upper() for s in sources.keys()] + self.source_cfg = sources + self.sources_exist: dict[str, bool] = {s.upper(): False for s in sources.keys()} + self.sources_updated: dict[str, int] = {s.upper(): 0 for s in sources.keys()} + + # Create database directory + self.data_dir.mkdir(parents=True, exist_ok=True) + + # Setup multiprocessing infrastructure + self.shared_data: dict[str, Any] = dict() + self.locks: dict[str, Any] = dict() + self.global_lock = threading.Lock() + + # Initialize sources + self._initialize_sources() + + self._closed = False + self.stop_event = threading.Event() + atexit.register(self.safe_close) + + self.logger.info(f'LogDB initialized for {len(self.sources)} sources in {self.data_dir}') + + def _initialize_sources(self) -> None: + """Initialize database structures for all sources.""" + with self.global_lock: + for source in self.sources: + # Create source-specific structures + self.shared_data[source] = dict( + { + 'config': '', + 'files': dict(), # file_path -> {src_hash, compressed_hash} + 'logs': dict(), # log_id -> log_data + 'index': dict(), # unique_key -> log_id + 'max_id': 0, + } + ) + + # Create source-specific lock + self.locks[source] = threading.Lock() + + # Load existing data + self._load_source(source) + + def _source_file_path(self, source: str) -> Path: + """Get file path for a source's database file.""" + return self.data_dir / f'{source}_logs.json' + + def _file_hash(self, file_path: Union[str, Path]) -> str: + """Compute SHA256 hash of a file's contents.""" + hasher = hashlib.sha256() + file_path = Path(file_path) + try: + with file_path.open('rb') as f: + while chunk := f.read(8192): + hasher.update(chunk) + return hasher.hexdigest() + except OSError as e: + self.logger.error(f'Failed to compute hash for {file_path}: {e}') + return '' + + def is_config_updated(self, source: str) -> bool: + return bool(self.source_cfg[source] != self.shared_data[source]['config']) + + def is_file_processed(self, source: str, src_path: Union[str, Path], compressed_path: Union[str, Path]) -> bool: + """ + Check if a file has already been processed. + + Args: + source: Log source/module + src_path: Original source file path + compressed_path: Compressed version path + + Returns: + True if file has been processed, False otherwise + """ + source = source.upper() + if source not in self.shared_data: + self.logger.error(f'Unknown source: {source}') + return False + + src_hash = self._file_hash(src_path) + compressed_hash = self._file_hash(compressed_path) if Path(compressed_path).exists() else '' + + with self.locks[source]: + files = self.shared_data[source]['files'] + file_info = files.get(str(src_path)) + + # Check if file is registered and hashes match + if file_info: + if file_info.get('src_hash') == src_hash and file_info.get('compressed_hash') == compressed_hash: + return True + + # Update hashes if changed + file_info['src_hash'] = src_hash + if compressed_hash: + file_info['compressed_hash'] = compressed_hash + return False + + # New file + files[str(src_path)] = dict({'src_hash': src_hash, 'compressed_hash': compressed_hash}) + return False + + def mark_file_processed(self, source: str, src_path: Union[str, Path], compressed_path: Union[str, Path]) -> None: + """ + Mark a file as successfully processed. + + Args: + source: Log source/module + src_path: Original source file path + compressed_path: Compressed version path + """ + source = source.upper() + if source not in self.shared_data: + return + + src_hash = self._file_hash(src_path) + compressed_hash = self._file_hash(compressed_path) + + with self.locks[source]: + files = self.shared_data[source]['files'] + file_info = files.get(str(src_path), dict()) + file_info.update({'src_hash': src_hash, 'compressed_hash': compressed_hash}) + files[str(src_path)] = file_info + + def _load_source(self, source: str) -> None: + """Load source data from JSON file.""" + db_file = self._source_file_path(source) + + # Create empty database if not exists + if not db_file.exists(): + with db_file.open('w') as f: + json.dump({'config': '', 'files': {}, 'logs': {}}, f) + return + + try: + with db_file.open('r') as f: + data = json.load(f) + except (OSError, json.JSONDecodeError) as e: + self.logger.error(f'Error loading {source} database: {e}') + return + + files = {} + logs = {} + indexes = {} + + with self.locks[source]: + source_db = self.shared_data[source] + + # Load config + source_db['config'] = data.get('config', '') + + # Load files + source_db['files'].clear() + for path, info in data.get('files', {}).items(): + files[path] = dict(info) + + source_db['files'].update(files) + + # Load logs + source_db['logs'].clear() + source_db['index'].clear() + max_id = 0 + + for log_id, log_data in data.get('logs', {}).items(): + log_id = int(log_id) + logs[log_id] = dict(log_data) + unique_key = self._log_unique_key(log_data) + indexes[unique_key] = log_id + if log_id > max_id: + max_id = log_id + source_db['logs'].update(logs) + source_db['index'].update(indexes) + source_db['max_id'] = max_id + self.sources_updated[source] = len(logs) + self.sources_exist[source] = bool(data.get('logs')) + + self.logger.info(f'Loaded {len(data.get("logs", {}))} logs for {source}') + + def _save_source(self, source: str) -> bool: + """Save source data to JSON file using atomic write.""" + db_file = self._source_file_path(source) + + # Prepare data + with self.locks[source]: + source_db = self.shared_data[source] + config = self.source_cfg[source] + files_data = {path: dict(info) for path, info in source_db['files'].items()} + logs_data = {log_id: dict(data) for log_id, data in source_db['logs'].items()} + + data = {'config': config, 'files': files_data, 'logs': logs_data} + + # Atomic write + tmp_path = None + try: + with tempfile.NamedTemporaryFile(mode='w', dir=self.data_dir, delete=False) as tmp_file: + json.dump(data, tmp_file, indent=2) + tmp_path = tmp_file.name + + # Replace original file + os.replace(tmp_path, db_file) + return True + except (OSError, TypeError) as e: + self.logger.error(f'Error saving {source} database: {e}') + if tmp_path and Path(tmp_path).exists(): + Path(tmp_path).unlink() + return False + + def _log_unique_key(self, log_data: dict) -> tuple: + """ + Create a unique key for a log entry. + + Args: + log_data: Log entry dictionary + + Returns: + Unique key tuple + """ + return (log_data['tag'], log_data['format'], log_data['caller'], log_data['file'], log_data['line_number']) + + def add_log( + self, + source: str, + log_tag: str, + log_format: str, + log_line_number: int, + hexify: bool, + caller_func: str, + caller_line: int, + file_name: str, + ) -> tuple[int, int]: + """ + Add a new log entry to the database if it doesn't exist. + + Args: + source: Log source/module + log_tag: Log tag + log_format: Log format string + log_line_number: Log Line number + hexify: Whether the log can be hexified + caller_func: Calling function name + caller_line: Calling function line number + file_name: Source file name + + Returns: + Tuple (result_code, log_id) + """ + if self._closed: + return self.OPERATION_FAILED, 0 + + source = source.upper() + if source not in self.shared_data: + self.logger.error(f'Unknown source: {source}') + return self.OPERATION_FAILED, 0 + + log_data = { + 'tag': log_tag, + 'format': log_format, + 'line_number': log_line_number, + 'hexify': hexify, + 'caller': caller_func, + 'caller_line': caller_line, + 'file': file_name, + } + + unique_key = self._log_unique_key(log_data) + + with self.locks[source]: + source_db = self.shared_data[source] + + # Check if log exists + if unique_key in source_db['index']: + existing_id = source_db['index'][unique_key] + return self.LOG_EXISTS, existing_id + + # Create new log entry + new_id = source_db['max_id'] + 1 + log_data['id'] = new_id + + source_db['logs'][new_id] = dict(log_data) + source_db['index'][unique_key] = new_id + source_db['max_id'] = new_id + + self.logger.info(f'Added new log [{source}]: ID={new_id}, Tag={log_tag}') + return self.SUCCESS, new_id + + def remove_log(self, source: str, log_id: int) -> bool: + """ + Remove a log entry from the database. + + Args: + source: Log source/module + log_id: ID of log to remove + + Returns: + True if successful, False otherwise + """ + source = source.upper() + if source not in self.shared_data: + return False + + with self.locks[source]: + source_db = self.shared_data[source] + + if log_id not in source_db['logs']: + return False + + # Remove from indexes + log_data = dict(source_db['logs'][log_id]) + unique_key = self._log_unique_key(log_data) + + if unique_key in source_db['index']: + del source_db['index'][unique_key] + del source_db['logs'][log_id] + + if log_id == source_db['max_id']: + source_db['max_id'] = max(source_db['logs'].keys()) if source_db['logs'] else 0 + + return True + + def source_update_state(self, source: str) -> int: + if self.is_config_updated(source): + return self.SOURCE_LOG_UPDATE_FULL + if self.sources_updated[source] == len(self.shared_data[source]['logs']): + return self.SOURCE_LOG_UPDATE_NONE + elif self.sources_updated[source] == 0 and len(self.shared_data[source]['logs']) != 0: + return self.SOURCE_LOG_UPDATE_FULL + else: + return self.SOURCE_LOG_UPDATE_PARTIAL + + def save_source(self, source: str) -> bool: + """Save a single source's data to file.""" + return self._save_source(source.upper()) + + def save_all(self) -> int: + """Save all sources' data to files.""" + self.logger.debug('Saving all sources...') + success_count = 0 + + for source in self.sources: + if (not self.is_config_updated(source)) and self.sources_updated[source] == len( + self.shared_data[source]['logs'] + ): + self.logger.info(f'{source} has not updated data') + continue + if self._save_source(source): + success_count += 1 + + self.logger.info(f'Saved {success_count}/{len(self.sources)} sources') + return success_count + + def safe_close(self) -> None: + """Safe close method that handles atexit callbacks.""" + if not self._closed: + try: + self.close() + except Exception as e: + # Log to stderr as logging may be shutdown + print(f'Error during safe_close: {e}', flush=True) + + def close(self) -> None: + """Cleanup resources.""" + if self._closed: + return + + self._closed = True + + try: + if not self.stop_event.is_set(): + self.stop_event.set() + except Exception: + pass + + self.logger.info('Closing database manager...') + self.stop_event.set() + + # Final save + self.logger.info('Performing final save...') + self.save_all() + + # Shutdown manager + self.logger.info('Database manager closed') + + def __enter__(self) -> 'LogDBManager': + return self + + def __exit__( + self, + exc_type: Union[type[BaseException], None], + exc_val: Union[BaseException, None], + exc_tb: Union[TracebackType, None], + ) -> None: + self.close() diff --git a/components/bt/common/ble_log/extension/log_compression/scripts/ble_log_compress.py b/components/bt/common/ble_log/extension/log_compression/scripts/ble_log_compress.py new file mode 100644 index 000000000000..da1f4493b68d --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/scripts/ble_log_compress.py @@ -0,0 +1,963 @@ +# SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +# The current project needs to support environments before Python 3.9, +# and UP007 will prohibit the use of Tuple, Union, etc. +# ruff: noqa: UP007 +# The current project needs to support environments before Python 3.9, +# Therefore, it is necessary to prohibit UP006 from automatically +# changing the annotation type +# ruff: noqa: UP006 +# ruff: noqa: UP035 +""" +BLE Log Compression Utility +=========================== +This script processes Bluetooth source files to compress logging statements. +""" +import argparse +import enum +import logging +import os +import re +import shutil +import sys +import textwrap +import traceback +from datetime import datetime +from pathlib import Path +from typing import Any +from typing import Dict +from typing import List +from typing import Tuple +from typing import Union + +import tree_sitter_c as tsc +import yaml +from c_format_parse import parse_format_string +from inttypes_map import TYPES_MACRO_MAP +from LogDBManager import LogDBManager + +try: + import importlib.metadata as meta + + _TS_VER = tuple(map(int, meta.version('tree-sitter').split('.')[:2])) +except Exception: + _TS_VER = (0, 20) + +if _TS_VER >= (0, 21): + from tree_sitter import Language + from tree_sitter import Node + from tree_sitter import Parser + from tree_sitter import Query + from tree_sitter import Tree + + if _TS_VER >= (0, 25): + from tree_sitter import QueryCursor +else: + from tree_sitter import Language + from tree_sitter import Parser + from tree_sitter import Tree + +# Initialize logger +LOGGER = logging.getLogger('ble_log_compression') + +# Global parser instances +C_LANGUAGE: Union[Language, None] = None +CLANG_PARSER: Union[Parser, None] = None + +# Log source enumeration +SOURCE_ENUM_MAP = { + 'BLE_HOST': 0, + 'BLE_MESH': 1, +} + +# Functions that require hex formatting +HEX_FUNCTIONS = ['bt_hex'] # Used in Mesh and Audio modules + +# C keywords to exclude from function names +C_KEYWORDS = { + 'auto', + 'break', + 'case', + 'char', + 'const', + 'continue', + 'default', + 'do', + 'double', + 'else', + 'enum', + 'extern', + 'float', + 'for', + 'goto', + 'if', + 'int', + 'long', + 'register', + 'return', + 'short', + 'signed', + 'sizeof', + 'static', + 'struct', + 'switch', + 'typedef', + 'union', + 'unsigned', + 'void', + 'volatile', + 'while', +} + +FUNC_MACROS = {'__func__', '__FUNCTION__'} + +LINE_MACROS = { + '__LINE__', +} + +BLUEDROID_LOG_MODE_LEVEL_GET = { + 'BTM': 'btm_cb.trace_level', + 'L2CAP': 'l2cb.l2cap_trace_level', + 'GAP': 'gap_cb.trace_level', + 'GATT': 'gatt_cb.trace_level', + 'SMP': 'smp_cb.trace_level', + 'APPL': 'appl_trace_level', +} + + +class ARG_SIZE_TYPE(enum.IntEnum): + U32 = 0 + STR = 1 + U64 = 2 + LZU32 = 3 + LZU64 = 4 + AZU32 = 5 + AZU64 = 6 + + +def TsInit() -> Tuple[Language, Parser]: + if _TS_VER > (0, 21): + lang = Language(tsc.language()) + parser = Parser(lang) + return lang, parser + else: + lang = Language(tsc.language(), 'c') + parser = Parser() + parser.set_language(lang) + return lang, parser + + +def TsQueryByTree(language: Language, tree: Tree, query_str: str) -> Dict[str, List[Node]]: + if _TS_VER == (0, 21): + captures_res = language.query(query_str).captures(tree.root_node) + elif _TS_VER > (0, 21) and _TS_VER < (0, 25): + captures_res = Query(language, (query_str)).captures(tree.root_node) + else: + captures_res = QueryCursor(Query(language, (query_str))).captures(tree.root_node) + + captures: Dict[str, List[Node]] = {} + if isinstance(captures_res, list): + for node, node_type in captures_res: + if node_type not in captures: + captures[node_type] = [] + captures[node_type].append(node) + else: + captures = captures_res + return captures + + +class LogCompressor: + """Main class for BLE log compression.""" + + def __init__(self) -> None: + self.bt_component_path = Path() + self.build_dir = Path() + self.bt_compressed_srcs_path = Path() + self.config: dict[str, Any] = {} + self.module_info: dict[str, Any] = {} + + def init_parser(self) -> Parser: + """Initialize tree-sitter parser for C.""" + global C_LANGUAGE, CLANG_PARSER + + C_LANGUAGE, CLANG_PARSER = TsInit() + + return CLANG_PARSER + + def extract_log_calls(self, code_content: bytes, log_tags: list[str]) -> list[dict]: + """ + Extract log statements from C source code. + + Args: + code_content: Source code as bytes + log_tags: List of log tags to search for + + Returns: + List of dictionaries containing log information + """ + parser = self.init_parser() + tree = parser.parse(code_content) + function_map = self._get_function_boundaries(tree) + return self._find_log_statements(tree, log_tags, function_map) + + def _get_function_boundaries(self, tree: Tree) -> list[tuple[str, int, int, int]]: + """ + Identify function boundaries in the AST. + + Returns: + List of tuples (function_name, start_byte, end_byte, line_number) + """ + function_query = """ + [ + (function_declarator + (identifier) @func_name + ) + (declaration + (function_declarator + (identifier) @func_decls + ) + ) + ] + """ + captures: dict[str, list[Node]] = TsQueryByTree(C_LANGUAGE, tree, function_query) + + # Filter valid function names + func_names = [ + node + for node in captures.get('func_name', []) + if node not in captures.get('func_decls', []) and node.text.decode('utf-8') not in C_KEYWORDS + ] + + # Sort by start byte + func_names.sort(key=lambda node: node.start_byte) + boundaries = [] + + for i, node in enumerate(func_names): + func_name = node.text.decode('utf-8') + start_byte = node.start_byte + end_byte = func_names[i + 1].start_byte if i < len(func_names) - 1 else len(tree.root_node.text) + line_number = node.start_point[0] + 1 + boundaries.append((func_name, start_byte, end_byte, line_number)) + + return boundaries + + def _find_log_statements( + self, tree: Tree, log_tags: list[str], function_boundaries: list[tuple[str, int, int, int]] + ) -> list[dict]: + """ + Find log statements in the AST. + + Args: + tree: Parsed AST tree + log_tags: List of log tags to search for + function_boundaries: Function boundaries list + + Returns: + List of log information dictionaries + """ + # Build pattern for matching log tags + tag_pattern = '|'.join(log_tags) + log_query = f""" + (expression_statement + (call_expression + function: (identifier) @fname + arguments: (argument_list) @args + (#match? @fname "^({tag_pattern})$") + ) @log_stmt + ) + """ + captures: dict[str, list[Node]] = TsQueryByTree(C_LANGUAGE, tree, log_query) + log_nodes = captures.get('log_stmt', []) + + # It is necessary to ensure that the nodes + # are sorted according to the starting bytes, + # because only the nodes are ordered can ensure + # that the subsequent calculation offset is correct. + log_nodes.sort(key=lambda node: node.start_byte) + logs = [] + + for node in log_nodes: + try: + log_info = self._process_log_node(node, function_boundaries) + if log_info: + logs.append(log_info) + except Exception as e: + LOGGER.error(f'Error processing log node: {e}\n{traceback.format_exc()}') + raise + + return logs + + def _process_log_node(self, node: Node, function_boundaries: list[tuple[str, int, int, int]]) -> Union[dict, None]: + """ + Process a log AST node and extract information. + + Args: + node: Log statement AST node + function_boundaries: Function boundaries list + + Returns: + Log information dictionary or None if invalid + """ + # Extract basic information + tag_node = node.child_by_field_name('function') + if not tag_node: + return None + + tag = tag_node.text.decode('utf-8') + + args_node = node.child_by_field_name('arguments') + if not args_node or args_node.type != 'argument_list': + return None + + # Initialize log info + log_info = { + 'tag': (tag, tag_node.start_byte, tag_node.end_byte), + 'line_number': node.start_point[0] + 1, + 'arguments': [], + 'hexify': True, + } + + # Process format string (first argument) + valid_arg_childrn: list[Node] = [n for n in args_node.named_children if n.type != 'comment'] + fmt_node = valid_arg_childrn[0] if len(valid_arg_childrn) > 0 else None + if not fmt_node: + return None + + if fmt_node.type == 'concatenated_string': + log_fmt = self._process_concatenated_string(fmt_node) + elif fmt_node.type == 'string_literal': + log_fmt = fmt_node.text.decode('utf-8')[1:-1] # Remove quotes + else: + return None + + log_info['arguments'].append((f'"{log_fmt}"', fmt_node.start_byte, fmt_node.end_byte)) + + # Parse format tokens + tokens = parse_format_string(f'"{log_fmt}"') + tokens_tuple_map: list[int] = [] + for idx, tk in enumerate(tokens): + if isinstance(tk, tuple): + tokens_tuple_map.append(idx) + + arguments: list[Node] = valid_arg_childrn[1:] + + if len(arguments) != len(tokens_tuple_map): + raise SyntaxError(f'LogSyntaxError:{node.text.decode("utf-8")}') + + # Process each argument + for i, (token, arg_node) in enumerate(zip([t for t in tokens if isinstance(t, tuple)], arguments)): + arg_text = arg_node.text.decode('utf-8') + log_info['arguments'].append((arg_text, arg_node.start_byte, arg_node.end_byte)) + + # Check if argument can be hexified + # if not self._can_be_hexified(token, arg_node): + # log_info['hexify'] = False + + # Handle special identifiers + if arg_text in FUNC_MACROS: + token_list = list(token) + token_list[6] = '@func' # Modify conversion char to special marker + tokens[tokens_tuple_map[i]] = tuple(token_list) + elif arg_text in LINE_MACROS: + token_list = list(token) + token_list[6] = '@line' + tokens[tokens_tuple_map[i]] = tuple(token_list) + + # Handle hex functions + if ( + arg_node.type == 'call_expression' + and arg_node.child_by_field_name('function') + and arg_node.child_by_field_name('function').text.decode('utf-8') in HEX_FUNCTIONS + ): + # Extract arguments of the hex function + hex_args = arg_node.child_by_field_name('arguments') + if hex_args and hex_args.named_child_count >= 2: + buf_node = hex_args.named_children[0] + len_node = hex_args.named_children[1] + token_list = list(token) + token_list[6] = f'@hex_func@{buf_node.text.decode("utf-8")}@{len_node.text.decode("utf-8")}' + tokens[tokens_tuple_map[i]] = tuple(token_list) + + log_info['argu_tokens'] = tokens + + # Find calling function + caller_info = self._find_calling_function(node.start_byte, function_boundaries) + if not caller_info: + return None + + log_info.update(caller_info) + return log_info + + def _process_concatenated_string(self, node: Node) -> str: + """Process a concatenated string node into a single string.""" + parts = [] + for child in node.named_children: + if child.type == 'identifier': + identifier = child.text.decode('utf-8') + if identifier in TYPES_MACRO_MAP: + parts.append(TYPES_MACRO_MAP[identifier]) + else: + raise ValueError(f'Unknown format macro: {identifier}') + elif child.type == 'string_literal': + parts.append(child.text.decode('utf-8')[1:-1]) # Remove quotes + else: + raise ValueError(f'Unsupported node in concatenated string: {child.type}') + return ''.join(parts) + + def _can_be_hexified(self, token: tuple[int, int, str, str, str, str, str], node: Node) -> bool: + """Determine if a node can be represented in hex format.""" + if token[-1] != 's': + return True + + if node.type == 'identifier' and node.text.decode('utf-8') in FUNC_MACROS: + return True + + if ( + node.type == 'call_expression' + and node.child_by_field_name('function') + and node.child_by_field_name('function').text.decode('utf-8') in HEX_FUNCTIONS + ): + return True + + return False + + def _find_calling_function( + self, log_start: int, function_boundaries: list[tuple[str, int, int, int]] + ) -> Union[dict, None]: + """ + Find the function containing the log statement. + + Args: + log_start: Start byte of the log statement + function_boundaries: List of function boundaries + + Returns: + Dictionary with caller information or None if not found + """ + for name, start, end, line in function_boundaries: + if start <= log_start < end: + return {'caller_name': name, 'caller_line_number': line} + return None + + def generate_compressed_macro( + self, source: str, log_idx: int, tag: str, print_fmt: Union[str, None], log_info: dict + ) -> str: + """ + Generate a compressed log macro definition. + + Args: + source: Log source module + log_idx: Unique log index + tag: Original log tag + print_fmt: Simplified format string + log_info: Log information dictionary + + Returns: + Macro definition string + """ + if not log_idx: + return '' + + def generate_mesh_log_prefix(source: str, tag: str, print_statm: str) -> str: + level = tag.split('_')[-1] + mod = tag.split('_')[0] + if level == 'ERR': + level = 'ERROR' + log_level = 'BLE_MESH_LOG_LEVEL_ERROR' + elif level == 'WARN': + level = 'WARN' + log_level = 'BLE_MESH_LOG_LEVEL_WARN' + elif level == 'INFO': + level = 'INFO' + log_level = 'BLE_MESH_LOG_LEVEL_INFO' + elif level == 'DBG': + level = 'DEBUG' + log_level = 'BLE_MESH_LOG_LEVEL_DEBUG' + else: + LOGGER.error(f'Invalid log level {level}') + return '' + if mod == 'NET': + used_log_levl = 'BLE_MESH_NET_BUF_LOG_LEVEL' + used_log_mod = 'BLE_MESH_NET_BUF' + else: + used_log_levl = 'BLE_MESH_LOG_LEVEL' + used_log_mod = 'BLE_MESH' + return ( + f'{{do {{ if (({used_log_levl} >= {log_level}) &&' + f' BLE_MESH_LOG_LEVEL_CHECK({used_log_mod}, {level})) {print_statm};}} while (0);}}\\\n' + ) + + def generate_bluedroid_log_prefix(source: str, tag: str, print_statm: str) -> str: + tag_info = tag.split('_') + mod = tag_info[0] + + return ( + f'{{if ({BLUEDROID_LOG_MODE_LEVEL_GET[mod]} >= BT_TRACE_LEVEL_{tag_info[-1]} &&' + f' BT_LOG_LEVEL_CHECK({mod}, {tag_info[-1]})) {print_statm};}}\\\n' + ) + + def generate_log_lvl_prefix(source: str, tag: str, print_statm: str) -> str: + if source == 'BLE_MESH': + return ' ' + generate_mesh_log_prefix(source, tag, print_statm) + elif source == 'BLE_HOST': # only bluedroid host supported for now + return ' ' + generate_bluedroid_log_prefix(source, tag, print_statm) + else: + LOGGER.error(f'Unknown source {source}') + return '' + + source_value = SOURCE_ENUM_MAP.get(source.upper()) + if source_value is None: + raise ValueError(f'Invalid source: {source}') + + macro = f'#define {tag}_{log_idx}(fmt, ...) {{\\\n' + + if log_info['hexify']: + # Count of arguments that are not special (__func__, __LINE__, etc.) + arg_tokens = [t for t in log_info['argu_tokens'] if isinstance(t, tuple)] + arg_count = len(arg_tokens) + arguments = [] + sizes = [] + hex_func: list[str] = [] + + LOGGER.info(f'{arg_tokens}:{[a[0] for a in log_info["arguments"]]}') + + for token, argument in zip( + arg_tokens, + [a[0] for a in log_info['arguments'][1:]], + ): + # Skip special tokens + if token[6] in ('@func', '@line'): + arg_count -= 1 + continue + + # Handle hex function + if token[6].startswith('@hex_func'): + if not hex_func: + hex_func = [] + hex_func.append(token[6]) + arg_count -= 1 + continue + + arguments.append(argument) + + if token[6] == 'f' or token[5] == 'll': # float or long long + sizes.append(f'{int(ARG_SIZE_TYPE.U64)}') + elif token[6] == 's': + sizes.append(f'{int(ARG_SIZE_TYPE.STR)}') + else: + sizes.append(f'{int(ARG_SIZE_TYPE.U32)}') + + if arg_count > 0: + size_str = ', '.join(sizes) + arg_str = ', '.join(arguments).replace('\n', '') + macro += generate_log_lvl_prefix( + source, + tag, + (f'BLE_LOG_COMPRESSED_HEX_PRINT({source_value}, {log_idx}, {arg_count}, {size_str}, {arg_str})'), + ) + + for idx, item in enumerate(hex_func): + # hex_func format: @hex_func@buf@len + parts = item.split('@') + if len(parts) >= 4: + buf = parts[2] + buf_len = parts[3] + macro += generate_log_lvl_prefix( + source, + tag, + (f'BLE_LOG_COMPRESSED_HEX_PRINT_BUF({source_value}, {log_idx}, {idx}, {buf}, {buf_len})'), + ) + else: + macro += generate_log_lvl_prefix( + source, tag, f'BLE_LOG_COMPRESSED_HEX_PRINT_WITH_ZERO_ARGUMENTS({source_value}, {log_idx})' + ) + for idx, item in enumerate(hex_func): + # hex_func format: @hex_func@buf@len + parts = item.split('@') + if len(parts) >= 4: + buf = parts[2] + buf_len = parts[3] + macro += generate_log_lvl_prefix( + source, + tag, + (f'BLE_LOG_COMPRESSED_HEX_PRINT_BUF({source_value}, {log_idx}, {idx}, {buf}, {buf_len})'), + ) + if ( + 'tags_with_preserve' in self.module_info[source] + and tag in self.module_info[source]['tags_with_preserve'] + ): + macro += f' {tag}(fmt, ##__VA_ARGS__);\\\n' + else: + # Non-hexified log + print_fmt = print_fmt or 'NULL' + macro += f' BLE_LOG_COMPRESSED_PRINT({source_value}, {log_idx}, "{print_fmt}", ##__VA_ARGS__); \\\n' + + macro += '}\n' + return macro + + def compress_file(self, file_info: tuple[str, str]) -> list[tuple[str, int, str]]: + """ + Process a single file for log compression. + + Args: + file_info: Tuple of (module_name, file_path) + + Returns: + List of generated macros (module, log_id, macro) + """ + module, file_path = file_info + generated_macros = [] + + try: + with open(file_path, 'rb') as f: + content = f.read() + + new_content = bytearray(content) + logs = self.extract_log_calls(content, self.module_info[module]['tags']) + LOGGER.info(f'Processing {file_path} - found {len(logs)} logs') + offset = 0 # Track cumulative changes due to tag replacements + + for log in logs: + tag = log['tag'][0] + + # Extract existing index if present + if match := re.fullmatch(r'(.+)_([0-9A-F]{8})', tag): + tag_base = match.group(1) + file_index = match.group(2) + else: + tag_base = tag + file_index = None + + # Generate simplified format string + no_buf_fmt: str = '' + simple_fmt_list: list[str] = [] + hex_buffer_cnt = 0 + for token in log['argu_tokens']: + if isinstance(token, tuple): + if '@func' in token[6] or '@line' in token[6]: + continue + if '@hex_func' in token[6]: + simple_fmt_list.append(f'@hex_buffer{hex_buffer_cnt}') + no_buf_fmt += f'@hex_buffer{hex_buffer_cnt}' + hex_buffer_cnt += 1 + continue + simple_fmt_list.append(token[2]) + no_buf_fmt += token[2] + else: + no_buf_fmt += token + simple_fmt_str = ' '.join(simple_fmt_list) if simple_fmt_list else None + + # Add to database + result, db_index = self.db_manager.add_log( + source=module, + log_tag=tag_base, + log_format=no_buf_fmt if log['hexify'] else log['arguments'][0][0], + log_line_number=log['line_number'], + hexify=log['hexify'], + caller_func=log['caller_name'], + caller_line=log['caller_line_number'], + file_name=os.path.basename(file_path), + ) + + LOGGER.info(f'Got log tag {tag}, generated or quired idx {db_index}') + + if result == LogDBManager.SUCCESS: + LOGGER.info(f'Added new log: {db_index} - {tag_base}') + elif result == LogDBManager.LOG_EXISTS: + if file_index: + if int(file_index, 16) != db_index: + LOGGER.info(f'Updating index: {file_index} -> {db_index}') + else: + LOGGER.info(f'duplicate index: {file_index} == {db_index}') + continue + else: + LOGGER.info(f'Recovery log index {db_index}') + else: + LOGGER.error(f'Database error for log: {tag_base}') + continue + + # Update tag in content + new_tag_bytes = f'{tag_base}_{db_index}'.encode() + tag_start, tag_end = log['tag'][1], log['tag'][2] + new_content[offset + tag_start: offset + tag_end] = new_tag_bytes + offset += len(new_tag_bytes) - (tag_end - tag_start) + + # Generate macro if this is a new log or index changed + if result == LogDBManager.SUCCESS or file_index or self.db_manager.is_config_updated(module): + macro = self.generate_compressed_macro(module, db_index, tag_base, simple_fmt_str, log) + generated_macros.append((module, db_index, macro)) + + # Write updated content + with open(file_path, 'wb') as f_out: + f_out.write(new_content) + + except Exception as e: + LOGGER.error(f'Error processing {file_path}: {e}\n{traceback.format_exc()}') + raise + + return generated_macros + + def prepare_source_files(self, srcs: list[str]) -> None: + """ + Prepare source files for processing. + + Args: + srcs: List of source file paths + """ + for module, info in self.module_info.items(): + code_dirs = '|'.join(info['code_path']) + pattern = re.compile(f'({code_dirs}).*\\.c$') + info['files_to_process'] = [] + compressed_file_cnt = 0 + total_cnt = 0 + for src in srcs: + if pattern.match(src): + src_path = self.bt_component_path / src + dest_path = self.bt_compressed_srcs_path / src + temp_path = f'{dest_path}.tmp' + total_cnt += 1 + # Skip if already processed + if self.db_manager.is_file_processed( + module, src_path, temp_path + ) and not self.db_manager.is_config_updated(module): + compressed_file_cnt += 1 + continue + + # Ensure directory exists + os.makedirs(os.path.dirname(temp_path), exist_ok=True) + shutil.copy2(src_path, temp_path) + info['files_to_process'].append(temp_path) + LOGGER.info(f'Prepared: {src}') + LOGGER.info(f'Compressed cnt {compressed_file_cnt} {total_cnt}') + if compressed_file_cnt == total_cnt: + print( + f'All source files in module {module} have been compressed\n', flush=True, end='', file=sys.stdout + ) + else: + print( + f'Found {len(info["files_to_process"])} source files in module {module} requiring compression\n', + flush=True, + end='', + file=sys.stdout, + ) + LOGGER.info('Source file preparation complete') + + def generate_log_index_header(self, module: str, macros: list[tuple[int, str]]) -> None: + """ + Generate or update the log index header file. + + Args: + module: Module name + macros: List of (log_id, macro_definition) + """ + # header_path = self.bt_component_path / self.module_info[module]['log_index_path'] + header_path = self.build_dir / Path('ble_log') / Path('include') / self.module_info[module]['log_index_file'] + # Create directory if needed + header_path.parent.mkdir(parents=True, exist_ok=True) + + update_state = self.db_manager.source_update_state(source=module) + if update_state == self.db_manager.SOURCE_LOG_UPDATE_NONE: + return + elif update_state == self.db_manager.SOURCE_LOG_UPDATE_FULL: + # Header template + header_content = ( + textwrap.dedent(f""" + /* + * SPDX-FileCopyrightText: {datetime.now().year} Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + #ifndef __{module.upper()}_INTERNAL_LOG_INDEX_H + #define __{module.upper()}_INTERNAL_LOG_INDEX_H + + #include + #include + + // Compression function declarations + extern int ble_log_compressed_hex_print + (uint32_t source, uint32_t log_index, size_t args_size_cnt, ...); + extern int ble_log_compressed_hex_print_buf + (uint8_t source, uint32_t log_index, uint8_t buf_idx, const uint8_t *buf, size_t len); + + // Compression macros + #define BLE_LOG_COMPRESSED_HEX_PRINT(source, log_index, args_cnt, ...) \\ + ble_log_compressed_hex_print(source, log_index, args_cnt, ##__VA_ARGS__) + #define BLE_LOG_COMPRESSED_HEX_PRINT_BUF(source, log_index, buf_idx, buf, len) \\ + ble_log_compressed_hex_print_buf(source, log_index, buf_idx, (const uint8_t *)buf, len) + #define BLE_LOG_COMPRESSED_HEX_PRINT_WITH_ZERO_ARGUMENTS(source, log_index) \\ + ble_log_compressed_hex_print(source, log_index, 0) + """).strip() + + '\n\n' + ) + # Add sorted macros + for log_id, macro_def in sorted(macros, key=lambda x: x[0]): + header_content += macro_def + '\n' + + header_content += f'#endif // __{module.upper()}_INTERNAL_LOG_INDEX_H\n' + + with open(header_path, 'w') as f: + f.write(header_content) + else: + append_content = '' + log_idx_set: dict[int, int] = dict() + for log_id, macro_def in sorted(macros, key=lambda x: x[0]): + append_content += macro_def + '\n' + log_idx_set[log_id] = 1 + with open(header_path, encoding='utf-8') as f: + lines = f.readlines() + log_idx_pattern = re.compile(r'#define .+(\d+)\(fmt,') + for idx, line in enumerate(lines): + if line.strip().startswith('#define'): + res = log_idx_pattern.match(line) + if res: + li = int(res.group(1)) + if li in log_idx_set: + raise ValueError( + f'The generated log index{li} andlog_index in the header file have duplicates' + ) + + if line.strip().startswith('#endif'): + break + else: + raise RuntimeError('#endif not found') + lines.insert(idx, append_content) + with open(header_path, 'w', encoding='utf-8') as f: + f.writelines(lines) + LOGGER.info(f'Generated log index header: {header_path}') + + def load_config(self, config_path: str, module_names: list[str]) -> None: + """ + Load and validate log configuration. + + Args: + config_path: Path to configuration file + module_names: List of module names to load + """ + with open(config_path, encoding='utf-8') as f: + config = yaml.safe_load(f) + + # Extract global config + log_config = config.get('log_config', {}) + for key, value in log_config.items(): + if key != 'modules': + self.config[key] = value + + # Extract module configs + modules = log_config.get('modules', {}) + for module in module_names: + if module in modules: + self.module_info[module] = modules[module] + print(f'Found module {module} for compression\n', flush=True, end='', file=sys.stdout) + else: + LOGGER.warning(f"Skipping module '{module}' - config not found") + + def main(self) -> int: + """Main entry point for the compression utility.""" + parser = argparse.ArgumentParser(description='BLE Log Compression Utility') + subparsers = parser.add_subparsers(dest='command', required=True) + + compress_parser = subparsers.add_parser('compress') + compress_parser.add_argument('--srcs', required=True, help='Semicolon-separated source file paths') + compress_parser.add_argument('--bt_path', required=True, help='Bluetooth component root path') + compress_parser.add_argument('--module', required=True, help='Semicolon-separated module names') + compress_parser.add_argument('--build_path', required=True, help='Build output directory') + compress_parser.add_argument('--compressed_srcs_path', required=True, help='Directory for processed sources') + + args = parser.parse_args() + + # Setup paths + self.bt_component_path = Path(args.bt_path) + self.build_dir = Path(args.build_path) + self.bt_compressed_srcs_path = Path(args.compressed_srcs_path) + + # Create directories + (self.build_dir / 'ble_log').mkdir(parents=True, exist_ok=True) + self.bt_compressed_srcs_path.mkdir(parents=True, exist_ok=True) + + # Configure logging + log_file = self.build_dir / 'ble_log' / f'ble_script_log_{datetime.now().strftime("%y%m%d_%H%M%S")}.log' + logging.basicConfig( + level=logging.INFO, + format='%(asctime)s - %(name)s - %(levelname)s - %(message)s', + handlers=[logging.FileHandler(log_file, mode='w')], + ) + + # Load configuration + modules = args.module.split(';') + config_path = self.build_dir / 'ble_log/module_info.yml' + self.load_config(str(config_path), modules) + + # Initialize database + db_path = self.build_dir / self.config.get('db_path', 'log_db') + db_manager = LogDBManager( + data_dir=str(db_path), + sources={source: str(config) for source, config in self.module_info.items()}, + logger=LOGGER, + ) + + self.db_manager = db_manager + + # Prepare source files + src_list = args.srcs.split(';') + self.prepare_source_files(src_list) + + # Collect files to process + files_to_process = [] + for module, info in self.module_info.items(): + files_to_process.extend([(module, path) for path in info['files_to_process']]) + + if not files_to_process: + LOGGER.info('No files to process') + print('No source files require compression; exiting log compression\n', flush=True, end='', file=sys.stdout) + for root, _, files in os.walk(self.bt_compressed_srcs_path): + for name in files: + if name.endswith('.tmp'): + file_src = os.path.join(root, name) + dst_path = os.path.join(root, name[: -len('.tmp')]) + shutil.copy2(file_src, dst_path) + LOGGER.info(f'Recovery src {file_src} dst {dst_path}') + db_manager.close() + return 0 + + all_macros: dict[str, list[tuple[int, str]]] = {} + files_to_process.sort(key=lambda x: x[1]) + try: + compressed_log_count = 0 + for needs_compressed_file in files_to_process: + file_macros = self.compress_file(needs_compressed_file) + compressed_log_count += len(file_macros) + for module, log_id, macro in file_macros: + all_macros.setdefault(module, []).append((log_id, macro)) + print(f'{compressed_log_count} ble log(s) compressed\n', flush=True, end='', file=sys.stdout) + except Exception as e: + LOGGER.error(f'Processing failed: {e}') + db_manager.close() + return 1 + + # Generate headers + for module, macros in all_macros.items(): + self.generate_log_index_header(module, macros) + print('Header file for compressed logs generated\n', flush=True, end='', file=sys.stdout) + + # Mark files as processed + for module, info in self.module_info.items(): + for temp_path in info['files_to_process']: + src_path = self.bt_component_path / os.path.relpath(temp_path[:-4], self.bt_compressed_srcs_path) + db_manager.mark_file_processed(module, src_path, temp_path) + for root, _, files in os.walk(self.bt_compressed_srcs_path): + for name in files: + if name.endswith('.tmp'): + file_src = os.path.join(root, name) + dst_path = os.path.join(root, name[: -len('.tmp')]) + shutil.copy2(file_src, dst_path) + LOGGER.info(f'Recovery src {file_src} dst {dst_path}') + db_manager.close() + LOGGER.info('Compression completed successfully') + return 0 + + +if __name__ == '__main__': + print('Log compression underway, please wait...\n', flush=True, end='', file=sys.stdout) + compressor = LogCompressor() + exit(compressor.main()) diff --git a/components/bt/common/ble_log/extension/log_compression/scripts/c_format_parse.py b/components/bt/common/ble_log/extension/log_compression/scripts/c_format_parse.py new file mode 100644 index 000000000000..71600d37da0a --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/scripts/c_format_parse.py @@ -0,0 +1,267 @@ +# SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +# ruff: noqa: UP007 +""" +Format String Parser +==================== +Parses C-style format strings and handles argument formatting for log compression. +""" +import struct +from typing import Union + + +def parse_format_string(format_str: str) -> list[Union[str, tuple[int, int, str, str, str, str, str]]]: + """ + Parse a format string into tokens. + + Args: + format_str: C-style format string + + Returns: + List of tokens (strings or format spec tuples) + """ + tokens: list[Union[str, tuple[int, int, str, str, str, str, str]]] = [] + i = 0 + n = len(format_str) + + while i < n: + if format_str[i] == '%': + start = i + i += 1 + + # Handle escaped % + if i < n and format_str[i] == '%': + tokens.append('%') + i += 1 + continue + + # Parse flags + flags = '' + while i < n and format_str[i] in '-+ #0': + flags += format_str[i] + i += 1 + + # Parse width + width = '' + while i < n and format_str[i].isdigit(): + width += format_str[i] + i += 1 + + # Parse precision + precision = '' + if i < n and format_str[i] == '.': + i += 1 + while i < n and format_str[i].isdigit(): + precision += format_str[i] + i += 1 + + # Parse length modifier + length = '' + if i < n and format_str[i] in 'zhl': + length += format_str[i] + i += 1 + # Handle double length (e.g., ll) + if i < n and format_str[i] == 'l' and length == 'l': + length += 'l' + i += 1 + + if i < n and format_str[i] in 'diuoxXfcsplL': + conv_char = format_str[i] + i += 1 + full_spec = format_str[start:i] + tokens.append((start, i, full_spec, flags, width, length, conv_char)) + else: + tokens.append(format_str[start:i]) + else: + # Regular text + start = i + while i < n and format_str[i] != '%': + i += 1 + tokens.append(format_str[start:i]) + + return tokens + + +def format_integer(value: int, conv_char: str, flags: str, width: str, length_mod: str) -> str: + """ + Format an integer value according to format specifiers. + + Args: + value: Integer value + conv_char: Conversion character (d, i, u, o, x, X) + flags: Format flags + width: Minimum width + length_mod: Length modifier + + Returns: + Formatted string + """ + # Determine base + base = 10 + uppercase = False + if conv_char in 'xX': + base = 16 + uppercase = conv_char == 'X' + elif conv_char == 'o': + base = 8 + + # Generate number string + if base == 16: + num_str = format(value, 'X' if uppercase else 'x') + elif base == 8: + num_str = format(value, 'o') + else: # decimal + num_str = str(value) + + # Add prefix + prefix = '' + if '#' in flags and value != 0: + if base == 16: + prefix = '0X' if uppercase else '0x' + elif base == 8: + prefix = '0' + + # Apply width and padding + total_len = len(prefix) + len(num_str) + width_val = int(width) if width else 0 + + if width_val > total_len: + padding = width_val - total_len + if '0' in flags and '-' not in flags: + num_str = num_str.zfill(padding + len(num_str)) + else: + pad_char = ' ' * padding + if '-' in flags: + num_str = prefix + num_str + pad_char + prefix = '' + else: + num_str = pad_char + prefix + num_str + prefix = '' + + return prefix + num_str + + +def parse_compressed_arguments(byte_sequence: bytes, format_str: str) -> str: + """ + Parse compressed log arguments into formatted string. + + Args: + byte_sequence: Compressed argument bytes + format_str: Original format string + + Returns: + Formatted log string + + Raises: + ValueError: If the input is invalid + """ + if len(byte_sequence) < 2: + raise ValueError('Insufficient bytes for header') + + # Parse header + header = (byte_sequence[0] << 8) | byte_sequence[1] + type_flag = (header >> 15) & 0x01 + arg_count = header & 0x7FFF + + if type_flag != 1: + raise ValueError(f'Unsupported type flag: {type_flag}') + + # Parse size list + size_bytes_needed = (arg_count + 1) // 2 + if len(byte_sequence) < 2 + size_bytes_needed: + raise ValueError('Insufficient bytes for size list') + + size_bytes = byte_sequence[2: 2 + size_bytes_needed] + arg_sizes = [] + + for i in range(arg_count): + byte_index = i // 2 + if i % 2 == 0: + size = (size_bytes[byte_index] >> 4) & 0x0F + else: + size = size_bytes[byte_index] & 0x0F + arg_sizes.append(size) + + # Parse arguments + args = [] + pos = 2 + size_bytes_needed + + for size in arg_sizes: + if pos + size > len(byte_sequence): + raise ValueError('Insufficient bytes for arguments') + + args.append(byte_sequence[pos: pos + size]) + pos += size + + # Parse format string + tokens = parse_format_string(format_str) + output = [] + arg_index = 0 + + for token in tokens: + if isinstance(token, tuple): + start, end, flags, width, precision, length_mod, conv_char = token + + if conv_char == '%': + output.append('%') + else: + if arg_index >= len(args): + raise ValueError('Not enough arguments for format string') + + arg_bytes = args[arg_index] + arg_index += 1 + + # Character type + if conv_char == 'c': + # Pad to 4 bytes for unpacking + padded = arg_bytes.ljust(4, b'\x00') + char_code = struct.unpack('>I', padded)[0] + output.append(chr(char_code)) + + # Pointer type + elif conv_char == 'p': + ptr_value = int.from_bytes(arg_bytes, 'big', signed=False) + output.append(hex(ptr_value)) + + # Floating point types + elif conv_char in 'fFeEgGaA': + if len(arg_bytes) == 4: + float_value = struct.unpack('>f', arg_bytes)[0] + elif len(arg_bytes) == 8: + float_value = struct.unpack('>d', arg_bytes)[0] + else: + raise ValueError(f'Unsupported float size: {len(arg_bytes)} bytes') + output.append(str(float_value)) + + # Integer types + elif conv_char in 'diuoxX': + signed = conv_char in 'di' + + # Determine expected size + if length_mod == 'll': + expected_size = 8 + elif length_mod in ('l', 'z', 'j', 't') or conv_char == 'p': + expected_size = 4 + else: + expected_size = len(arg_bytes) + + # Pad to expected size + if len(arg_bytes) < expected_size: + if signed and arg_bytes and (arg_bytes[0] & 0x80): + # Sign extension for negative numbers + pad = b'\xff' * (expected_size - len(arg_bytes)) + else: + pad = b'\x00' * (expected_size - len(arg_bytes)) + arg_bytes = pad + arg_bytes + elif len(arg_bytes) > expected_size: + arg_bytes = arg_bytes[:expected_size] + + # Convert to integer + int_value = int.from_bytes(arg_bytes, 'big', signed=signed) + output.append(format_integer(int_value, conv_char, flags, width, length_mod)) + else: + raise ValueError(f'Unsupported conversion: {conv_char}') + else: + output.append(token) + + return ''.join(output) diff --git a/components/bt/common/ble_log/extension/log_compression/scripts/configs/module_info.yml.in b/components/bt/common/ble_log/extension/log_compression/scripts/configs/module_info.yml.in new file mode 100644 index 000000000000..853dcd474865 --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/scripts/configs/module_info.yml.in @@ -0,0 +1,17 @@ +log_config: + db_path: "ble_log/ble_log_database" + + modules: + BLE_MESH: + description: "BLE Mesh" + code_path: [@BLE_MESH_CODE_PATH@] + log_index_file: @BLE_MESH_LOG_INDEX_HEADER@ + tags: [@BLE_MESH_TAGS@] + tags_with_preserve: [@BLE_MESH_TAGS_PRESERVE@] + + BLE_HOST: + description: "BLE Host" + code_path: [@HOST_CODE_PATH@] + log_index_file: @HOST_LOG_INDEX_HEADER@ + tags: [@BLE_HOST_TAGS@] + tags_with_preserve: [@BLE_HOST_TAGS_PRESERVE@] diff --git a/components/bt/common/ble_log/extension/log_compression/scripts/env_check.py b/components/bt/common/ble_log/extension/log_compression/scripts/env_check.py new file mode 100644 index 000000000000..9358f298ab85 --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/scripts/env_check.py @@ -0,0 +1,139 @@ +# SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +try: + import tree_sitter_c +except ModuleNotFoundError: + tree_sitter_c = None +try: + import tree_sitter +except ModuleNotFoundError: + tree_sitter = None +import platform +import sys +from importlib.metadata import version +from pathlib import Path + +from ble_log_compress import TsInit +from ble_log_compress import TsQueryByTree + +IDF_PATH = Path(Path(__file__).resolve().parent / Path('../../../../../../')).resolve() + +TEST_C_STR = b""" +void test_func(void); +int main(void) { + printf("Hello world\n"); + return 0; +} +""" + +TEST_FUNCTION_QUERY = """ +[ + (function_declarator + (identifier) @func_name + ) + (declaration + (function_declarator + (identifier) @func_decls + ) + ) +] +""" +TEST_LOG_QUERY = """ +(expression_statement + (call_expression + function: (identifier) @fname + arguments: (argument_list) @args + (#match? @fname "^(printf)$") + ) @log_stmt +) +""" + + +def check_py_version(min_version: str = '3.8.0') -> None: + cur_str = platform.python_version() + cur_tuple = tuple(map(int, cur_str.split('.'))) + min_tuple = tuple(map(int, min_version.split('.'))) + + if min_tuple > cur_tuple: + print( + ('Please use Python 3.8 or above'), + file=sys.stderr, + ) + exit(1) + + +def validate() -> None: + if tree_sitter is None: + print( + ( + 'tree_sitter import failed, please check whether the package is installed correctly,' + 'Please refer to the file:' + f'{IDF_PATH}/components/bt/common/ble_log/log_compression/scripts/install.en.md' + ' for installation instructions.' + ), + file=sys.stderr, + ) + exit(1) + if tree_sitter_c is None: + print( + ( + 'tree_sitter_c import failed, ' + 'please check whether the package is installed correctly,' + 'Please refer to the file:' + f'{IDF_PATH}/components/bt/common/ble_log/log_compression/scripts/install.en.md' + ' for installation instructions.' + ), + file=sys.stderr, + ) + exit(1) + + +def test_parse() -> None: + try: + lang, parser = TsInit() + tree = parser.parse(TEST_C_STR) + captures = TsQueryByTree(lang, tree, TEST_LOG_QUERY) + + assert len(captures.keys()) == 3 + assert len(captures.values()) == 3 + assert 'log_stmt' in captures.keys() + assert 'fname' in captures.keys() + assert 'args' in captures.keys() + assert captures['log_stmt'][0].type == 'call_expression' + assert captures['log_stmt'][0].start_point == (3, 4) + assert captures['log_stmt'][0].end_point == (4, 2) + + captures = TsQueryByTree(lang, tree, TEST_FUNCTION_QUERY) + print(captures, file=sys.stderr) + assert len(captures.keys()) == 2 + assert len(captures.values()) == 2 + assert 'func_decls' in captures.keys() + assert 'func_name' in captures.keys() + assert len(captures['func_name']) == 2 + assert len(captures['func_decls']) == 1 + assert captures['func_name'][0].type == 'identifier' + assert captures['func_name'][0].start_point == (1, 5) + assert captures['func_name'][0].end_point == (1, 14) + + except Exception: + print( + ( + f'Code parsing error,' + f'please provide the following information to Espressif to help you solve the problem' + f'tree-sitter version: {version(tree_sitter)} ' + f'tree-sitter-c version: {version(tree_sitter_c)} ' + f'python version: {platform.python_version()} ', + f'os_system: {platform.system()} ', + f'os_release: {platform.release()} ', + f'os_version: {platform.version()} ', + f'machine: {platform.machine()}', + ), + file=sys.stderr, + ) + exit(1) + + +check_py_version() +validate() +test_parse() +exit(0) diff --git a/components/bt/common/ble_log/extension/log_compression/scripts/inttypes_map.py b/components/bt/common/ble_log/extension/log_compression/scripts/inttypes_map.py new file mode 100644 index 000000000000..9e95a18cffef --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/scripts/inttypes_map.py @@ -0,0 +1,166 @@ +# SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +""" +用于适配标准化打印 +file_path: /usr/include/inttypes.h +""" + +__PRI64_PREFIX = 'll' +__PRIPTR_PREFIX = '' + +TYPES_MACRO_MAP = { + 'PRId8': 'd', + 'PRId16': 'd', + 'PRId32': 'd', + 'PRId64': __PRI64_PREFIX + 'd', + 'PRIdLEAST8': 'd', + 'PRIdLEAST16': 'd', + 'PRIdLEAST32': 'd', + 'PRIdLEAST64': __PRI64_PREFIX + 'd', + 'PRIdFAST8': 'd', + 'PRIdFAST16': __PRIPTR_PREFIX + 'd', + 'PRIdFAST32': __PRIPTR_PREFIX + 'd', + 'PRIdFAST64': __PRI64_PREFIX + 'd', + 'PRIi8': 'i', + 'PRIi16': 'i', + 'PRIi32': 'i', + 'PRIi64': __PRI64_PREFIX + 'i', + 'PRIiLEAST8': 'i', + 'PRIiLEAST16': 'i', + 'PRIiLEAST32': 'i', + 'PRIiLEAST64': __PRI64_PREFIX + 'i', + 'PRIiFAST8': 'i', + 'PRIiFAST16': __PRIPTR_PREFIX + 'i', + 'PRIiFAST32': __PRIPTR_PREFIX + 'i', + 'PRIiFAST64': __PRI64_PREFIX + 'i', + 'PRIo8': 'o', + 'PRIo16': 'o', + 'PRIo32': 'o', + 'PRIo64': __PRI64_PREFIX + 'o', + 'PRIoLEAST8': 'o', + 'PRIoLEAST16': 'o', + 'PRIoLEAST32': 'o', + 'PRIoLEAST64': __PRI64_PREFIX + 'o', + 'PRIoFAST8': 'o', + 'PRIoFAST16': __PRIPTR_PREFIX + 'o', + 'PRIoFAST32': __PRIPTR_PREFIX + 'o', + 'PRIoFAST64': __PRI64_PREFIX + 'o', + 'PRIu8': 'u', + 'PRIu16': 'u', + 'PRIu32': 'u', + 'PRIu64': __PRI64_PREFIX + 'u', + 'PRIuLEAST8': 'u', + 'PRIuLEAST16': 'u', + 'PRIuLEAST32': 'u', + 'PRIuLEAST64': __PRI64_PREFIX + 'u', + 'PRIuFAST8': 'u', + 'PRIuFAST16': __PRIPTR_PREFIX + 'u', + 'PRIuFAST32': __PRIPTR_PREFIX + 'u', + 'PRIuFAST64': __PRI64_PREFIX + 'u', + 'PRIx8': 'x', + 'PRIx16': 'x', + 'PRIx32': 'x', + 'PRIx64': __PRI64_PREFIX + 'x', + 'PRIxLEAST8': 'x', + 'PRIxLEAST16': 'x', + 'PRIxLEAST32': 'x', + 'PRIxLEAST64': __PRI64_PREFIX + 'x', + 'PRIxFAST8': 'x', + 'PRIxFAST16': __PRIPTR_PREFIX + 'x', + 'PRIxFAST32': __PRIPTR_PREFIX + 'x', + 'PRIxFAST64': __PRI64_PREFIX + 'x', + 'PRIX8': 'X', + 'PRIX16': 'X', + 'PRIX32': 'X', + 'PRIX64': __PRI64_PREFIX + 'X', + 'PRIXLEAST8': 'X', + 'PRIXLEAST16': 'X', + 'PRIXLEAST32': 'X', + 'PRIXLEAST64': __PRI64_PREFIX + 'X', + 'PRIXFAST8': 'X', + 'PRIXFAST16': __PRIPTR_PREFIX + 'X', + 'PRIXFAST32': __PRIPTR_PREFIX + 'X', + 'PRIXFAST64': __PRI64_PREFIX + 'X', + 'PRIdMAX': __PRI64_PREFIX + 'd', + 'PRIiMAX': __PRI64_PREFIX + 'i', + 'PRIoMAX': __PRI64_PREFIX + 'o', + 'PRIuMAX': __PRI64_PREFIX + 'u', + 'PRIxMAX': __PRI64_PREFIX + 'x', + 'PRIXMAX': __PRI64_PREFIX + 'X', + 'PRIdPTR': __PRIPTR_PREFIX + 'd', + 'PRIiPTR': __PRIPTR_PREFIX + 'i', + 'PRIoPTR': __PRIPTR_PREFIX + 'o', + 'PRIuPTR': __PRIPTR_PREFIX + 'u', + 'PRIxPTR': __PRIPTR_PREFIX + 'x', + 'PRIXPTR': __PRIPTR_PREFIX + 'X', + 'SCNd8': 'hhd', + 'SCNd16': 'hd', + 'SCNd32': 'd', + 'SCNd64': __PRI64_PREFIX + 'd', + 'SCNdLEAST8': 'hhd', + 'SCNdLEAST16': 'hd', + 'SCNdLEAST32': 'd', + 'SCNdLEAST64': __PRI64_PREFIX + 'd', + 'SCNdFAST8': 'hhd', + 'SCNdFAST16': __PRIPTR_PREFIX + 'd', + 'SCNdFAST32': __PRIPTR_PREFIX + 'd', + 'SCNdFAST64': __PRI64_PREFIX + 'd', + 'SCNi8': 'hhi', + 'SCNi16': 'hi', + 'SCNi32': 'i', + 'SCNi64': __PRI64_PREFIX + 'i', + 'SCNiLEAST8': 'hhi', + 'SCNiLEAST16': 'hi', + 'SCNiLEAST32': 'i', + 'SCNiLEAST64': __PRI64_PREFIX + 'i', + 'SCNiFAST8': 'hhi', + 'SCNiFAST16': __PRIPTR_PREFIX + 'i', + 'SCNiFAST32': __PRIPTR_PREFIX + 'i', + 'SCNiFAST64': __PRI64_PREFIX + 'i', + 'SCNu8': 'hhu', + 'SCNu16': 'hu', + 'SCNu32': 'u', + 'SCNu64': __PRI64_PREFIX + 'u', + 'SCNuLEAST8': 'hhu', + 'SCNuLEAST16': 'hu', + 'SCNuLEAST32': 'u', + 'SCNuLEAST64': __PRI64_PREFIX + 'u', + 'SCNuFAST8': 'hhu', + 'SCNuFAST16': __PRIPTR_PREFIX + 'u', + 'SCNuFAST32': __PRIPTR_PREFIX + 'u', + 'SCNuFAST64': __PRI64_PREFIX + 'u', + 'SCNo8': 'hho', + 'SCNo16': 'ho', + 'SCNo32': 'o', + 'SCNo64': __PRI64_PREFIX + 'o', + 'SCNoLEAST8': 'hho', + 'SCNoLEAST16': 'ho', + 'SCNoLEAST32': 'o', + 'SCNoLEAST64': __PRI64_PREFIX + 'o', + 'SCNoFAST8': 'hho', + 'SCNoFAST16': __PRIPTR_PREFIX + 'o', + 'SCNoFAST32': __PRIPTR_PREFIX + 'o', + 'SCNoFAST64': __PRI64_PREFIX + 'o', + 'SCNx8': 'hhx', + 'SCNx16': 'hx', + 'SCNx32': 'x', + 'SCNx64': __PRI64_PREFIX + 'x', + 'SCNxLEAST8': 'hhx', + 'SCNxLEAST16': 'hx', + 'SCNxLEAST32': 'x', + 'SCNxLEAST64': __PRI64_PREFIX + 'x', + 'SCNxFAST8': 'hhx', + 'SCNxFAST16': __PRIPTR_PREFIX + 'x', + 'SCNxFAST32': __PRIPTR_PREFIX + 'x', + 'SCNxFAST64': __PRI64_PREFIX + 'x', + 'SCNdMAX': __PRI64_PREFIX + 'd', + 'SCNiMAX': __PRI64_PREFIX + 'i', + 'SCNoMAX': __PRI64_PREFIX + 'o', + 'SCNuMAX': __PRI64_PREFIX + 'u', + 'SCNxMAX': __PRI64_PREFIX + 'x', + 'SCNdPTR': __PRIPTR_PREFIX + 'd', + 'SCNiPTR': __PRIPTR_PREFIX + 'i', + 'SCNoPTR': __PRIPTR_PREFIX + 'o', + 'SCNuPTR': __PRIPTR_PREFIX + 'u', + 'SCNxPTR': __PRIPTR_PREFIX + 'x', +} diff --git a/components/bt/common/ble_log/extension/log_compression/scripts/requirements.txt b/components/bt/common/ble_log/extension/log_compression/scripts/requirements.txt new file mode 100644 index 000000000000..419023a59092 --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/scripts/requirements.txt @@ -0,0 +1,6 @@ +tree_sitter~=0.21; python_version == "3.8" +tree_sitter_c~=0.21; python_version == "3.8" +tree_sitter>=0.23,<=0.23.2; python_version == "3.9" +tree_sitter_c>=0.23,<0.23.5; python_version == "3.9" +tree-sitter~=0.25; python_version >= "3.10" +tree-sitter-c~=0.24; python_version >= "3.10" diff --git a/components/bt/common/ble_log/include/ble_log/ble_log_spi_out.h b/components/bt/common/ble_log/include/ble_log/ble_log_spi_out.h index bcf80398bbbc..f1e485fa7d4b 100644 --- a/components/bt/common/ble_log/include/ble_log/ble_log_spi_out.h +++ b/components/bt/common/ble_log/include/ble_log/ble_log_spi_out.h @@ -61,5 +61,4 @@ void ble_log_spi_out_le_audio_write(const uint8_t *addr, uint16_t len); int ble_log_spi_out_host_write(uint8_t source, const char *prefix, const char *format, ...); int ble_log_spi_out_hci_write(uint8_t source, const uint8_t *addr, uint16_t len); int ble_log_spi_out_mesh_write(const char *prefix, const char *format, ...); - #endif // __BT_SPI_OUT_H__ diff --git a/components/bt/common/ble_log/src/ble_log_lbm.c b/components/bt/common/ble_log/src/ble_log_lbm.c index 109589a9470b..5078f2bad7dc 100644 --- a/components/bt/common/ble_log/src/ble_log_lbm.c +++ b/components/bt/common/ble_log/src/ble_log_lbm.c @@ -12,6 +12,10 @@ #include "ble_log_lbm.h" #include "ble_log_rt.h" +#if CONFIG_SOC_ESP_NIMBLE_CONTROLLER +#include "os/os_mbuf.h" +#endif /* CONFIG_SOC_ESP_NIMBLE_CONTROLLER */ + /* VARIABLE */ BLE_LOG_STATIC volatile uint32_t lbm_ref_count = 0; BLE_LOG_STATIC bool lbm_inited = false; @@ -25,7 +29,7 @@ BLE_LOG_STATIC void ble_log_lbm_release(ble_log_lbm_t *lbm); BLE_LOG_STATIC void ble_log_lbm_write_trans(ble_log_prph_trans_t **trans, ble_log_src_t src_code, const uint8_t *addr, uint16_t len, - const uint8_t *addr_append, uint16_t len_append); + const uint8_t *addr_append, uint16_t len_append, bool omdata); #if CONFIG_BLE_LOG_ENH_STAT_ENABLED BLE_LOG_STATIC void ble_log_stat_mgr_update(ble_log_src_t src_code, uint32_t len, bool lost); #endif /* CONFIG_BLE_LOG_ENH_STAT_ENABLED */ @@ -84,7 +88,7 @@ void ble_log_lbm_release(ble_log_lbm_t *lbm) BLE_LOG_IRAM_ATTR BLE_LOG_STATIC void ble_log_lbm_write_trans(ble_log_prph_trans_t **trans, ble_log_src_t src_code, const uint8_t *addr, uint16_t len, - const uint8_t *addr_append, uint16_t len_append) + const uint8_t *addr_append, uint16_t len_append, bool omdata) { /* Preparation before writing */ uint8_t *buf = (*trans)->buf + (*trans)->pos; @@ -102,7 +106,16 @@ void ble_log_lbm_write_trans(ble_log_prph_trans_t **trans, ble_log_src_t src_cod BLE_LOG_MEMCPY(buf + BLE_LOG_FRAME_HEAD_LEN, addr, len); } if (len_append) { - BLE_LOG_MEMCPY(buf + BLE_LOG_FRAME_HEAD_LEN + len, addr_append, len_append); +#if CONFIG_SOC_ESP_NIMBLE_CONTROLLER + if (omdata) { + os_mbuf_copydata((struct os_mbuf *)addr_append, 0, + len_append, buf + BLE_LOG_FRAME_HEAD_LEN + len); + } + else +#endif /* CONFIG_SOC_ESP_NIMBLE_CONTROLLER */ + { + BLE_LOG_MEMCPY(buf + BLE_LOG_FRAME_HEAD_LEN + len, addr_append, len_append); + } } /* Data integrity check */ @@ -429,7 +442,7 @@ bool ble_log_write_hex(ble_log_src_t src_code, const uint8_t *addr, size_t len) xTaskGetTickCountFromISR(): xTaskGetTickCount()); ble_log_lbm_write_trans(trans, src_code, (const uint8_t *)&os_ts, - sizeof(uint32_t), addr, len); + sizeof(uint32_t), addr, len, false); /* Release */ ble_log_lbm_release(lbm); @@ -467,6 +480,7 @@ void ble_log_write_hex_ll(uint32_t len, const uint8_t *addr, src_code = BLE_LOG_SRC_LL_TASK; use_ll_task = true; } + bool omdata = flag & BIT(BLE_LOG_LL_FLAG_OMDATA); if (!lbm_enabled) { goto exit; @@ -489,7 +503,7 @@ void ble_log_write_hex_ll(uint32_t len, const uint8_t *addr, } /* Write transport */ - ble_log_lbm_write_trans(trans, src_code, addr, len, addr_append, len_append); + ble_log_lbm_write_trans(trans, src_code, addr, len, addr_append, len_append, omdata); ble_log_lbm_release(lbm); BLE_LOG_REF_COUNT_RELEASE(&lbm_ref_count); diff --git a/components/bt/common/ble_log/src/internal_include/ble_log_lbm.h b/components/bt/common/ble_log/src/internal_include/ble_log_lbm.h index c3d79a671413..8f0e34ded06c 100644 --- a/components/bt/common/ble_log/src/internal_include/ble_log_lbm.h +++ b/components/bt/common/ble_log/src/internal_include/ble_log_lbm.h @@ -158,6 +158,7 @@ enum { BLE_LOG_LL_FLAG_ISR, BLE_LOG_LL_FLAG_HCI, BLE_LOG_LL_FLAG_RAW, + BLE_LOG_LL_FLAG_OMDATA, BLE_LOG_LL_FLAG_HCI_UPSTREAM, }; #endif /* CONFIG_BLE_LOG_LL_ENABLED */ diff --git a/components/bt/common/btc/core/btc_manage.c b/components/bt/common/btc/core/btc_manage.c index e65e10798833..4b63f1efbabe 100644 --- a/components/bt/common/btc/core/btc_manage.c +++ b/components/bt/common/btc/core/btc_manage.c @@ -8,19 +8,20 @@ #include "btc/btc_task.h" #include "osi/thread.h" -#if BTC_DYNAMIC_MEMORY == FALSE -void *btc_profile_cb_tab[BTC_PID_NUM] = {}; -#else +#if BTC_DYNAMIC_MEMORY == TRUE void **btc_profile_cb_tab; +#else +void *btc_profile_cb_tab[BTC_PID_NUM] = {}; #endif void esp_profile_cb_reset(void) { - #if BTC_DYNAMIC_MEMORY == TRUE - if (btc_profile_cb_tab == NULL) { +#if BTC_DYNAMIC_MEMORY == TRUE + void *p = btc_profile_cb_tab; + if (p == NULL) { return; } - #endif +#endif int i; @@ -31,11 +32,12 @@ void esp_profile_cb_reset(void) int btc_profile_cb_set(btc_pid_t profile_id, void *cb) { - #if BTC_DYNAMIC_MEMORY == TRUE - if (btc_profile_cb_tab == NULL) { +#if BTC_DYNAMIC_MEMORY == TRUE + void *p = btc_profile_cb_tab; + if (p == NULL) { return -1; } - #endif +#endif if (profile_id < 0 || profile_id >= BTC_PID_NUM) { return -1; @@ -48,11 +50,12 @@ int btc_profile_cb_set(btc_pid_t profile_id, void *cb) void *btc_profile_cb_get(btc_pid_t profile_id) { - #if BTC_DYNAMIC_MEMORY == TRUE - if (btc_profile_cb_tab == NULL) { +#if BTC_DYNAMIC_MEMORY == TRUE + void *p = btc_profile_cb_tab; + if (p == NULL) { return NULL; } - #endif +#endif if (profile_id < 0 || profile_id >= BTC_PID_NUM) { return NULL; diff --git a/components/bt/common/hci_log/bt_hci_log.c b/components/bt/common/hci_log/bt_hci_log.c index 74c63f444892..fa3de907d64b 100644 --- a/components/bt/common/hci_log/bt_hci_log.c +++ b/components/bt/common/hci_log/bt_hci_log.c @@ -140,7 +140,7 @@ static char IRAM_ATTR *bt_data_type_to_str(uint8_t data_type) } #endif -void bt_hci_log_record_hex(bt_hci_log_t *p_hci_log_ctl, uint8_t *hex, uint8_t hex_len) +void bt_hci_log_record_hex(bt_hci_log_t *p_hci_log_ctl, uint8_t *hex, uint16_t hex_len) { uint8_t hci_log_char; uint8_t *g_hci_log_buffer; @@ -205,7 +205,7 @@ void bt_hci_log_record_string(bt_hci_log_t *p_hci_log_ctl, char *string) } } -esp_err_t IRAM_ATTR bt_hci_log_record_data(bt_hci_log_t *p_hci_log_ctl, char *str, uint8_t data_type, uint8_t *data, uint8_t data_len) +esp_err_t IRAM_ATTR bt_hci_log_record_data(bt_hci_log_t *p_hci_log_ctl, char *str, uint8_t data_type, uint8_t *data, uint16_t data_len) { osi_mutex_t mutex_lock; uint8_t *g_hci_log_buffer; @@ -331,7 +331,7 @@ void bt_hci_log_record_hci_enable(bool enable) enable_hci_log_flag = enable; } -esp_err_t IRAM_ATTR bt_hci_log_record_hci_data(uint8_t data_type, uint8_t *data, uint8_t data_len) +esp_err_t IRAM_ATTR bt_hci_log_record_hci_data(uint8_t data_type, uint8_t *data, uint16_t data_len) { if (!enable_hci_log_flag) return ESP_OK; return bt_hci_log_record_data(&g_bt_hci_log_data_ctl, NULL, data_type, data, data_len); diff --git a/components/bt/common/hci_log/include/hci_log/bt_hci_log.h b/components/bt/common/hci_log/include/hci_log/bt_hci_log.h index 2c11729f5d2d..4646862194c9 100644 --- a/components/bt/common/hci_log/include/hci_log/bt_hci_log.h +++ b/components/bt/common/hci_log/include/hci_log/bt_hci_log.h @@ -87,7 +87,7 @@ esp_err_t bt_hci_log_deinit(void); * @return ESP_OK - success, other - failed * */ -esp_err_t bt_hci_log_record_hci_data(uint8_t data_type, uint8_t *data, uint8_t data_len); +esp_err_t bt_hci_log_record_hci_data(uint8_t data_type, uint8_t *data, uint16_t data_len); /** * diff --git a/components/bt/controller/esp32c2/Kconfig.in b/components/bt/controller/esp32c2/Kconfig.in index 016baf511c96..9dd21b161edc 100644 --- a/components/bt/controller/esp32c2/Kconfig.in +++ b/components/bt/controller/esp32c2/Kconfig.in @@ -458,10 +458,12 @@ config BT_LE_LL_DUP_SCAN_LIST_COUNT config BT_LE_LL_SCA int "BLE Sleep clock accuracy" - range 0 500 + range 0 3000 default 60 help Sleep clock accuracy of our device (in ppm) + The Bluetooth LE spec requires a Sleep Clock Accuracy (SCA) of < ±500 ppm. + This options allows for a larger value to enable the use of less accurate clock sources. config BT_LE_LL_PEER_SCA_SET_ENABLE bool "Enable to set constant peer SCA" diff --git a/components/bt/controller/esp32c2/bt.c b/components/bt/controller/esp32c2/bt.c index 7b335387ab24..c9b227a5f7a1 100644 --- a/components/bt/controller/esp32c2/bt.c +++ b/components/bt/controller/esp32c2/bt.c @@ -575,7 +575,7 @@ struct ext_funcs_t ext_funcs_ro = { ._esp_intr_alloc = esp_intr_alloc_wrapper, ._esp_intr_free = esp_intr_free_wrapper, ._malloc = bt_osi_mem_malloc_internal, - ._free = bt_osi_mem_free, + ._free = bt_osi_mem_free_internal, ._task_create = task_create_wrapper, ._task_delete = task_delete_wrapper, ._osi_assert = osi_assert_wrapper, @@ -749,7 +749,7 @@ void controller_wakeup_cb(void *arg) #if CONFIG_FREERTOS_USE_TICKLESS_IDLE static bool esp_bt_check_wakeup_by_bt(void) { - return (esp_sleep_get_wakeup_causes() & ESP_SLEEP_WAKEUP_BT); + return (esp_sleep_get_wakeup_causes() & BIT(ESP_SLEEP_WAKEUP_BT)); } #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE diff --git a/components/bt/controller/esp32c3/bt.c b/components/bt/controller/esp32c3/bt.c index 0d9e995af114..d975c0e2107e 100644 --- a/components/bt/controller/esp32c3/bt.c +++ b/components/bt/controller/esp32c3/bt.c @@ -60,6 +60,7 @@ #include "esp_partition.h" #include "hal/wdt_hal.h" #endif // CONFIG_BT_CTRL_LE_LOG_STORAGE_EN +#include "esp_rom_gpio.h" #if CONFIG_BT_ENABLED /* Macro definition @@ -2401,4 +2402,9 @@ static void * coex_schm_curr_phase_get_wrapper(void) #endif } +void btdm_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv) +{ + esp_rom_gpio_connect_out_signal(gpio, signal_idx, out_inv, oen_inv); +} + #endif /* CONFIG_BT_ENABLED */ diff --git a/components/bt/controller/esp32c5/Kconfig.in b/components/bt/controller/esp32c5/Kconfig.in index 2982b6da8eb6..074b065377a2 100644 --- a/components/bt/controller/esp32c5/Kconfig.in +++ b/components/bt/controller/esp32c5/Kconfig.in @@ -479,10 +479,12 @@ config BT_LE_LL_DUP_SCAN_LIST_COUNT config BT_LE_LL_SCA int "BLE Sleep clock accuracy" - range 0 500 + range 0 3000 default 60 help Sleep clock accuracy of our device (in ppm) + The Bluetooth LE spec requires a Sleep Clock Accuracy (SCA) of < ±500 ppm. + This options allows for a larger value to enable the use of less accurate clock sources. config BT_LE_LL_PEER_SCA_SET_ENABLE bool "Enable to set constant peer SCA" diff --git a/components/bt/controller/esp32c5/bt.c b/components/bt/controller/esp32c5/bt.c index 90d2db2ec04c..6ac6c2a05612 100644 --- a/components/bt/controller/esp32c5/bt.c +++ b/components/bt/controller/esp32c5/bt.c @@ -467,7 +467,7 @@ struct ext_funcs_t ext_funcs_ro = { ._esp_intr_alloc = esp_intr_alloc_wrapper, ._esp_intr_free = esp_intr_free_wrapper, ._malloc = bt_osi_mem_malloc_internal, - ._free = bt_osi_mem_free, + ._free = bt_osi_mem_free_internal, ._task_create = task_create_wrapper, ._task_delete = task_delete_wrapper, ._osi_assert = osi_assert_wrapper, diff --git a/components/bt/controller/esp32c6/Kconfig.in b/components/bt/controller/esp32c6/Kconfig.in index 29072a1432cd..93ba37845426 100644 --- a/components/bt/controller/esp32c6/Kconfig.in +++ b/components/bt/controller/esp32c6/Kconfig.in @@ -552,10 +552,12 @@ config BT_LE_LL_DUP_SCAN_LIST_COUNT config BT_LE_LL_SCA int "BLE Sleep clock accuracy" - range 0 500 + range 0 3000 default 60 help Sleep clock accuracy of our device (in ppm) + The Bluetooth LE spec requires a Sleep Clock Accuracy (SCA) of < ±500 ppm. + This options allows for a larger value to enable the use of less accurate clock sources. config BT_LE_LL_PEER_SCA_SET_ENABLE bool "Enable to set constant peer SCA" @@ -913,3 +915,65 @@ endmenu config BT_LE_DTM_ENABLED bool "Enable Direct Test Mode (DTM) feature" default n + +menu "Scheduling Priority Level Config" + choice BT_LE_ADV_SCHED_PRIO_LEVEL + prompt "The Adv scheduling priority level" + default BT_LE_ADV_SCHED_PRIO_LOW_LEVEL + help + The Adv scheduling priority level is used for arbitration when internal scheduling conflicts. + config BT_LE_ADV_SCHED_PRIO_LOW_LEVEL + bool "low priority level" + config BT_LE_ADV_SCHED_PRIO_MID_LEVEL + bool "medium priority level" + config BT_LE_ADV_SCHED_PRIO_HIGH_LEVEL + bool "high priority level" + endchoice + + config BT_LE_DFT_ADV_SCHED_PRIO_LEVEL + int + default 0 if BT_LE_ADV_SCHED_PRIO_LOW_LEVEL + default 1 if BT_LE_ADV_SCHED_PRIO_MID_LEVEL + default 2 if BT_LE_ADV_SCHED_PRIO_HIGH_LEVEL + default 0 + + choice BT_LE_PERIODIC_ADV_SCHED_PRIO_LEVEL + prompt "The Periodic Adv scheduling priority level" + default BT_LE_PERIODIC_ADV_SCHED_PRIO_MID_LEVEL + help + The Periodic Adv scheduling priority level is used for arbitration when internal scheduling conflicts. + config BT_LE_PERIODIC_ADV_SCHED_PRIO_LOW_LEVEL + bool "low priority level" + config BT_LE_PERIODIC_ADV_SCHED_PRIO_MID_LEVEL + bool "medium priority level" + config BT_LE_PERIODIC_ADV_SCHED_PRIO_HIGH_LEVEL + bool "high priority level" + endchoice + + config BT_LE_DFT_PERIODIC_ADV_SCHED_PRIO_LEVEL + int + default 0 if BT_LE_PERIODIC_ADV_SCHED_PRIO_LOW_LEVEL + default 1 if BT_LE_PERIODIC_ADV_SCHED_PRIO_MID_LEVEL + default 2 if BT_LE_PERIODIC_ADV_SCHED_PRIO_HIGH_LEVEL + default 1 + + choice BT_LE_SYNC_SCHED_PRIO_LEVEL + prompt "The Sync scheduling priority level" + default BT_LE_SYNC_SCHED_PRIO_MID_LEVEL + help + The SYNC scheduling priority level is used for arbitration when internal scheduling conflicts. + config BT_LE_SYNC_SCHED_PRIO_LOW_LEVEL + bool "low priority level" + config BT_LE_SYNC_SCHED_PRIO_MID_LEVEL + bool "medium priority level" + config BT_LE_SYNC_SCHED_PRIO_HIGH_LEVEL + bool "high priority level" + endchoice + + config BT_LE_DFT_SYNC_SCHED_PRIO_LEVEL + int + default 0 if BT_LE_SYNC_SCHED_PRIO_LOW_LEVEL + default 1 if BT_LE_SYNC_SCHED_PRIO_MID_LEVEL + default 2 if BT_LE_SYNC_SCHED_PRIO_HIGH_LEVEL + default 1 +endmenu diff --git a/components/bt/controller/esp32c6/bt.c b/components/bt/controller/esp32c6/bt.c index 351474d6dcbd..0b7825de344a 100644 --- a/components/bt/controller/esp32c6/bt.c +++ b/components/bt/controller/esp32c6/bt.c @@ -553,7 +553,7 @@ struct ext_funcs_t ext_funcs_ro = { ._esp_intr_alloc = esp_intr_alloc_wrapper, ._esp_intr_free = esp_intr_free_wrapper, ._malloc = bt_osi_mem_malloc_internal, - ._free = bt_osi_mem_free, + ._free = bt_osi_mem_free_internal, ._task_create = task_create_wrapper, ._task_delete = task_delete_wrapper, ._osi_assert = osi_assert_wrapper, @@ -796,7 +796,7 @@ IRAM_ATTR void controller_wakeup_cb(void *arg) #if CONFIG_FREERTOS_USE_TICKLESS_IDLE static bool esp_bt_check_wakeup_by_bt(void) { - return (esp_sleep_get_wakeup_causes() & ESP_SLEEP_WAKEUP_BT); + return (esp_sleep_get_wakeup_causes() & BIT(ESP_SLEEP_WAKEUP_BT)); } static esp_err_t sleep_modem_ble_mac_retention_init(void *arg) diff --git a/components/bt/controller/esp32c6/esp_bt_cfg.h b/components/bt/controller/esp32c6/esp_bt_cfg.h index 07a3acdb5eb7..2586976c90d5 100644 --- a/components/bt/controller/esp32c6/esp_bt_cfg.h +++ b/components/bt/controller/esp32c6/esp_bt_cfg.h @@ -300,6 +300,7 @@ extern "C" { #define RUN_BQB_TEST (0) #define RUN_QA_TEST (0) #define NIMBLE_DISABLE_SCAN_BACKOFF (0) +#define BT_LL_CTRL_PRIO_LVL_CFG ((CONFIG_BT_LE_DFT_SYNC_SCHED_PRIO_LEVEL << 4) | (CONFIG_BT_LE_DFT_PERIODIC_ADV_SCHED_PRIO_LEVEL << 2) | CONFIG_BT_LE_DFT_ADV_SCHED_PRIO_LEVEL) #ifdef __cplusplus } diff --git a/components/bt/controller/esp32h2/Kconfig.in b/components/bt/controller/esp32h2/Kconfig.in index 6d6e38af5a76..17a1d9abf2ce 100644 --- a/components/bt/controller/esp32h2/Kconfig.in +++ b/components/bt/controller/esp32h2/Kconfig.in @@ -546,10 +546,12 @@ config BT_LE_LL_DUP_SCAN_LIST_COUNT config BT_LE_LL_SCA int "BLE Sleep clock accuracy" - range 0 500 + range 0 3000 default 60 help Sleep clock accuracy of our device (in ppm) + The Bluetooth LE spec requires a Sleep Clock Accuracy (SCA) of < ±500 ppm. + This options allows for a larger value to enable the use of less accurate clock sources. config BT_LE_LL_PEER_SCA_SET_ENABLE bool "Enable to set constant peer SCA" @@ -917,3 +919,65 @@ endmenu config BT_LE_DTM_ENABLED bool "Enable Direct Test Mode (DTM) feature" default n + +menu "Scheduling Priority Level Config" + choice BT_LE_ADV_SCHED_PRIO_LEVEL + prompt "The Adv scheduling priority level" + default BT_LE_ADV_SCHED_PRIO_LOW_LEVEL + help + The Adv scheduling priority level is used for arbitration when internal scheduling conflicts. + config BT_LE_ADV_SCHED_PRIO_LOW_LEVEL + bool "low priority level" + config BT_LE_ADV_SCHED_PRIO_MID_LEVEL + bool "medium priority level" + config BT_LE_ADV_SCHED_PRIO_HIGH_LEVEL + bool "high priority level" + endchoice + + config BT_LE_DFT_ADV_SCHED_PRIO_LEVEL + int + default 0 if BT_LE_ADV_SCHED_PRIO_LOW_LEVEL + default 1 if BT_LE_ADV_SCHED_PRIO_MID_LEVEL + default 2 if BT_LE_ADV_SCHED_PRIO_HIGH_LEVEL + default 0 + + choice BT_LE_PERIODIC_ADV_SCHED_PRIO_LEVEL + prompt "The Periodic Adv scheduling priority level" + default BT_LE_PERIODIC_ADV_SCHED_PRIO_MID_LEVEL + help + The Periodic Adv scheduling priority level is used for arbitration when internal scheduling conflicts. + config BT_LE_PERIODIC_ADV_SCHED_PRIO_LOW_LEVEL + bool "low priority level" + config BT_LE_PERIODIC_ADV_SCHED_PRIO_MID_LEVEL + bool "medium priority level" + config BT_LE_PERIODIC_ADV_SCHED_PRIO_HIGH_LEVEL + bool "high priority level" + endchoice + + config BT_LE_DFT_PERIODIC_ADV_SCHED_PRIO_LEVEL + int + default 0 if BT_LE_PERIODIC_ADV_SCHED_PRIO_LOW_LEVEL + default 1 if BT_LE_PERIODIC_ADV_SCHED_PRIO_MID_LEVEL + default 2 if BT_LE_PERIODIC_ADV_SCHED_PRIO_HIGH_LEVEL + default 1 + + choice BT_LE_SYNC_SCHED_PRIO_LEVEL + prompt "The Sync scheduling priority level" + default BT_LE_SYNC_SCHED_PRIO_MID_LEVEL + help + The SYNC scheduling priority level is used for arbitration when internal scheduling conflicts. + config BT_LE_SYNC_SCHED_PRIO_LOW_LEVEL + bool "low priority level" + config BT_LE_SYNC_SCHED_PRIO_MID_LEVEL + bool "medium priority level" + config BT_LE_SYNC_SCHED_PRIO_HIGH_LEVEL + bool "high priority level" + endchoice + + config BT_LE_DFT_SYNC_SCHED_PRIO_LEVEL + int + default 0 if BT_LE_SYNC_SCHED_PRIO_LOW_LEVEL + default 1 if BT_LE_SYNC_SCHED_PRIO_MID_LEVEL + default 2 if BT_LE_SYNC_SCHED_PRIO_HIGH_LEVEL + default 1 +endmenu diff --git a/components/bt/controller/esp32h2/bt.c b/components/bt/controller/esp32h2/bt.c index 8533a1aa9938..4daa9d3fbeba 100644 --- a/components/bt/controller/esp32h2/bt.c +++ b/components/bt/controller/esp32h2/bt.c @@ -545,7 +545,7 @@ struct ext_funcs_t ext_funcs_ro = { ._esp_intr_alloc = esp_intr_alloc_wrapper, ._esp_intr_free = esp_intr_free_wrapper, ._malloc = bt_osi_mem_malloc_internal, - ._free = bt_osi_mem_free, + ._free = bt_osi_mem_free_internal, ._task_create = task_create_wrapper, ._task_delete = task_delete_wrapper, ._osi_assert = osi_assert_wrapper, @@ -764,7 +764,7 @@ IRAM_ATTR void controller_wakeup_cb(void *arg) #ifdef CONFIG_FREERTOS_USE_TICKLESS_IDLE static bool esp_bt_check_wakeup_by_bt(void) { - return (esp_sleep_get_wakeup_causes() & ESP_SLEEP_WAKEUP_BT); + return (esp_sleep_get_wakeup_causes() & BIT(ESP_SLEEP_WAKEUP_BT)); } static esp_err_t sleep_modem_ble_mac_retention_init(void *arg) diff --git a/components/bt/controller/esp32h2/esp_bt_cfg.h b/components/bt/controller/esp32h2/esp_bt_cfg.h index 4734737c5a4c..e79eb742e2dd 100644 --- a/components/bt/controller/esp32h2/esp_bt_cfg.h +++ b/components/bt/controller/esp32h2/esp_bt_cfg.h @@ -297,7 +297,7 @@ extern "C" { #define RUN_BQB_TEST (0) #define RUN_QA_TEST (0) #define NIMBLE_DISABLE_SCAN_BACKOFF (0) - +#define BT_LL_CTRL_PRIO_LVL_CFG ((CONFIG_BT_LE_DFT_SYNC_SCHED_PRIO_LEVEL << 4) | (CONFIG_BT_LE_DFT_PERIODIC_ADV_SCHED_PRIO_LEVEL << 2) | CONFIG_BT_LE_DFT_ADV_SCHED_PRIO_LEVEL) #ifdef __cplusplus } #endif diff --git a/components/bt/controller/lib_esp32 b/components/bt/controller/lib_esp32 index 0d1d45e93d45..45910ee1e502 160000 --- a/components/bt/controller/lib_esp32 +++ b/components/bt/controller/lib_esp32 @@ -1 +1 @@ -Subproject commit 0d1d45e93d45f838df531285799295475de74c1e +Subproject commit 45910ee1e50236e9d7219429666d7be7965427aa diff --git a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib index 204545445378..c82c623de457 160000 --- a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib +++ b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib @@ -1 +1 @@ -Subproject commit 204545445378b2704e3311911373aac326892597 +Subproject commit c82c623de457e1b06cf0dad5c963d023dbb6fe76 diff --git a/components/bt/controller/lib_esp32c3_family b/components/bt/controller/lib_esp32c3_family index 0c68809d62e4..42c965137ecc 160000 --- a/components/bt/controller/lib_esp32c3_family +++ b/components/bt/controller/lib_esp32c3_family @@ -1 +1 @@ -Subproject commit 0c68809d62e432427de97b5294f6619307f62f40 +Subproject commit 42c965137ecc3c6cf3d38ecece7ce71ffc461353 diff --git a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib index 56d7454a97d4..1495595b82f5 160000 --- a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib +++ b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib @@ -1 +1 @@ -Subproject commit 56d7454a97d4d5bce43ee611e69d293c269f5d4a +Subproject commit 1495595b82f5423d12b325960ae89bc604ebdcd4 diff --git a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib index a8a87adbd005..9cfbeb5f1637 160000 --- a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib +++ b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib @@ -1 +1 @@ -Subproject commit a8a87adbd005ffaed05051b9a1b1809bfbdc700d +Subproject commit 9cfbeb5f163788174073da19b3cd09c4d00cc860 diff --git a/components/bt/esp_ble_mesh/common/include/mesh/trace.h b/components/bt/esp_ble_mesh/common/include/mesh/trace.h index 48f604f1c2e2..6a851c6f9347 100644 --- a/components/bt/esp_ble_mesh/common/include/mesh/trace.h +++ b/components/bt/esp_ble_mesh/common/include/mesh/trace.h @@ -13,6 +13,9 @@ #include "esp_log.h" #include "mesh/utils.h" #include "esp_rom_sys.h" +#if CONFIG_BLE_MESH_COMPRESSED_LOG_ENABLE +#include "mesh_log_index.h" +#endif #ifdef __cplusplus extern "C" { diff --git a/components/bt/host/bluedroid/api/esp_bt_main.c b/components/bt/host/bluedroid/api/esp_bt_main.c index 2058e86c6505..420ea826b874 100644 --- a/components/bt/host/bluedroid/api/esp_bt_main.c +++ b/components/bt/host/bluedroid/api/esp_bt_main.c @@ -18,20 +18,11 @@ #include "hci_log/bt_hci_log.h" #include "bt_common.h" -static bool bd_already_enable = false; -static bool bd_already_init = false; +static esp_bluedroid_status_t s_bt_host_state = ESP_BLUEDROID_STATUS_UNINITIALIZED; esp_bluedroid_status_t esp_bluedroid_get_status(void) { - if (bd_already_init) { - if (bd_already_enable) { - return ESP_BLUEDROID_STATUS_ENABLED; - } else { - return ESP_BLUEDROID_STATUS_INITIALIZED; - } - } else { - return ESP_BLUEDROID_STATUS_UNINITIALIZED; - } + return s_bt_host_state; } esp_err_t esp_bluedroid_enable(void) @@ -39,12 +30,12 @@ esp_err_t esp_bluedroid_enable(void) btc_msg_t msg; future_t **future_p; - if (!bd_already_init) { + if (s_bt_host_state == ESP_BLUEDROID_STATUS_UNINITIALIZED) { LOG_ERROR("Bludroid not initialised\n"); return ESP_ERR_INVALID_STATE; } - if (bd_already_enable) { + if (s_bt_host_state == ESP_BLUEDROID_STATUS_ENABLED) { LOG_ERROR("Bluedroid already enabled\n"); return ESP_ERR_INVALID_STATE; } @@ -70,8 +61,7 @@ esp_err_t esp_bluedroid_enable(void) return ESP_FAIL; } - bd_already_enable = true; - + s_bt_host_state = ESP_BLUEDROID_STATUS_ENABLED; return ESP_OK; } @@ -80,15 +70,18 @@ esp_err_t esp_bluedroid_disable(void) btc_msg_t msg; future_t **future_p; - if (!bd_already_enable) { + if (s_bt_host_state != ESP_BLUEDROID_STATUS_ENABLED) { LOG_ERROR("Bluedroid already disabled\n"); return ESP_ERR_INVALID_STATE; } + s_bt_host_state = ESP_BLUEDROID_STATUS_DISABLING; + future_p = btc_main_get_future_p(BTC_MAIN_DISABLE_FUTURE); *future_p = future_new(); if (*future_p == NULL) { LOG_ERROR("Bluedroid disable failed\n"); + s_bt_host_state = ESP_BLUEDROID_STATUS_ENABLED; return ESP_ERR_NO_MEM; } @@ -98,16 +91,17 @@ esp_err_t esp_bluedroid_disable(void) if (btc_transfer_context(&msg, NULL, 0, NULL, NULL) != BT_STATUS_SUCCESS) { LOG_ERROR("Bluedroid disable failed\n"); + s_bt_host_state = ESP_BLUEDROID_STATUS_ENABLED; return ESP_FAIL; } if (future_await(*future_p) == FUTURE_FAIL) { LOG_ERROR("Bluedroid disable failed\n"); + s_bt_host_state = ESP_BLUEDROID_STATUS_ENABLED; return ESP_FAIL; } - bd_already_enable = false; - + s_bt_host_state = ESP_BLUEDROID_STATUS_INITIALIZED; return ESP_OK; } @@ -135,7 +129,7 @@ esp_err_t esp_bluedroid_init_with_cfg(esp_bluedroid_config_t *cfg) } #endif - if (bd_already_init) { + if (s_bt_host_state != ESP_BLUEDROID_STATUS_UNINITIALIZED) { LOG_ERROR("Bluedroid already initialised\n"); return ESP_ERR_INVALID_STATE; } @@ -180,28 +174,28 @@ esp_err_t esp_bluedroid_init_with_cfg(esp_bluedroid_config_t *cfg) return ESP_FAIL; } - bd_already_init = true; - #if (BT_HCI_LOG_INCLUDED == TRUE) bt_hci_log_init(); #endif // (BT_HCI_LOG_INCLUDED == TRUE) + s_bt_host_state = ESP_BLUEDROID_STATUS_INITIALIZED; + return ESP_OK; } - esp_err_t esp_bluedroid_deinit(void) { btc_msg_t msg; future_t **future_p; - if (!bd_already_init) { + if (s_bt_host_state == ESP_BLUEDROID_STATUS_UNINITIALIZED) { LOG_ERROR("Bluedroid already de-initialised\n"); return ESP_ERR_INVALID_STATE; } - if (bd_already_enable) { - LOG_ERROR("Bludroid already enabled, do disable first\n"); + if (s_bt_host_state == ESP_BLUEDROID_STATUS_ENABLED || + s_bt_host_state == ESP_BLUEDROID_STATUS_DISABLING) { + LOG_ERROR("Bludroid still enabled or stopping, disable first\n"); return ESP_ERR_INVALID_STATE; } @@ -234,8 +228,7 @@ esp_err_t esp_bluedroid_deinit(void) bt_hci_log_deinit(); #endif // (BT_HCI_LOG_INCLUDED == TRUE) - bd_already_init = false; - + s_bt_host_state = ESP_BLUEDROID_STATUS_UNINITIALIZED; return ESP_OK; } diff --git a/components/bt/host/bluedroid/api/esp_gap_ble_api.c b/components/bt/host/bluedroid/api/esp_gap_ble_api.c index 42724d2245e7..3c3a48e5b937 100644 --- a/components/bt/host/bluedroid/api/esp_gap_ble_api.c +++ b/components/bt/host/bluedroid/api/esp_gap_ble_api.c @@ -805,6 +805,28 @@ esp_err_t esp_ble_create_sc_oob_data(void) return (btc_transfer_context(&msg, NULL, 0, NULL, NULL) == BT_STATUS_SUCCESS ? ESP_OK : ESP_FAIL); } + +esp_err_t esp_ble_gap_get_local_irk(uint8_t local_irk[16]) +{ + if (local_irk == NULL) { + ESP_LOGE(__func__, "local_irk is NULL"); + return ESP_ERR_INVALID_ARG; + } + + if (esp_bluedroid_get_status() != ESP_BLUEDROID_STATUS_ENABLED) { + ESP_LOGE(__func__, "Bluedroid is not enabled"); + return ESP_ERR_INVALID_STATE; + } + + /* Use BTM API to safely retrieve local IRK */ + if (BTM_GetLocalIRK(local_irk)) { + ESP_LOGD(__func__, "Local IRK retrieved successfully"); + return ESP_OK; + } else { + ESP_LOGW(__func__, "Local IRK not available"); + return ESP_ERR_INVALID_STATE; + } +} #endif /* #if (SMP_INCLUDED == TRUE) */ esp_err_t esp_ble_gap_disconnect(esp_bd_addr_t remote_device) @@ -1795,6 +1817,24 @@ esp_err_t esp_ble_gap_set_sch_len(uint8_t role, uint32_t len) return esp_ble_gap_vendor_command_send(&vs_cmd); } #endif // CONFIG_SOC_BLE_MULTI_CONN_OPTIMIZATION + +esp_err_t esp_ble_gap_set_scan_chan_map(uint8_t state, uint8_t chan_map[5]) +{ + esp_ble_vendor_cmd_params_t vs_cmd; + uint8_t cmd_param[6]; + + if (chan_map == NULL) { + return ESP_ERR_INVALID_ARG; + } + + cmd_param[0] = state; + memcpy(&cmd_param[1], chan_map, 5); + vs_cmd.opcode = 0xFD19; + vs_cmd.param_len = 6; + vs_cmd.p_param_buf = cmd_param; + + return esp_ble_gap_vendor_command_send(&vs_cmd); +} #endif // (BLE_VENDOR_HCI_EN == TRUE) #if (BLE_FEAT_POWER_CONTROL_EN == TRUE) diff --git a/components/bt/host/bluedroid/api/include/api/esp_bt_main.h b/components/bt/host/bluedroid/api/include/api/esp_bt_main.h index 4a00afd130a9..185ea42cd1d4 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_bt_main.h +++ b/components/bt/host/bluedroid/api/include/api/esp_bt_main.h @@ -20,9 +20,10 @@ extern "C" { * @brief Bluetooth stack status type, to indicate whether the bluetooth stack is ready. */ typedef enum { - ESP_BLUEDROID_STATUS_UNINITIALIZED = 0, /*!< Bluetooth not initialized */ - ESP_BLUEDROID_STATUS_INITIALIZED, /*!< Bluetooth initialized but not enabled */ - ESP_BLUEDROID_STATUS_ENABLED /*!< Bluetooth initialized and enabled */ + ESP_BLUEDROID_STATUS_UNINITIALIZED = 0, /*!< Bluetooth stack is not initialized */ + ESP_BLUEDROID_STATUS_INITIALIZED, /*!< Bluetooth stack is initialized but not yet enabled */ + ESP_BLUEDROID_STATUS_ENABLED, /*!< Bluetooth stack is fully initialized and enabled */ + ESP_BLUEDROID_STATUS_DISABLING /*!< Bluetooth stack is in the process of being disabled */ } esp_bluedroid_status_t; /** diff --git a/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h b/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h index 021967d1285e..fee2d4823cda 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h +++ b/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h @@ -248,6 +248,7 @@ typedef enum { ESP_GAP_BLE_READ_CHANNEL_MAP_COMPLETE_EVT, /*!< When BLE channel map result is received, the event comes */ ESP_GAP_BLE_SET_COMMON_FACTOR_CMPL_EVT, /*!< When set the common factor complete, the event comes */ ESP_GAP_BLE_SET_SCH_LEN_CMPL_EVT, /*!< When set the scheduling length complete, the event comes */ + ESP_GAP_BLE_SET_SCAN_CHAN_MAP_CMPL_EVT, /*!< When set the channel map for scanning complete, the event comes */ ESP_GAP_BLE_EVT_MAX, /*!< when maximum advertising event complete, the event comes */ } esp_gap_ble_cb_event_t; @@ -1625,7 +1626,7 @@ typedef union { * @brief ESP_GAP_BLE_PERIODIC_ADV_SYNC_ESTAB_EVT */ struct ble_periodic_adv_sync_estab_param { - uint8_t status; /*!< periodic advertising sync status */ + esp_bt_status_t status; /*!< periodic advertising sync status */ uint16_t sync_handle; /*!< periodic advertising sync handle */ uint8_t sid; /*!< periodic advertising sid */ esp_ble_addr_type_t adv_addr_type; /*!< periodic advertising address type */ @@ -1762,6 +1763,12 @@ typedef union { struct ble_set_sch_len_cmpl_evt_param { esp_bt_status_t status; /*!< Indicate scheduling length set operation success status */ } set_sch_len_cmpl; /*!< Event parameter of ESP_GAP_BLE_SET_SCH_LEN_CMPL_EVT */ + /** + * @brief ESP_GAP_BLE_SET_SCAN_CHAN_MAP_CMPL_EVT + */ + struct ble_set_scan_chan_map_cmpl_evt_param { + esp_bt_status_t status; /*!< Indicate channel map for scanning set operation success status */ + } set_scan_chan_map_cmpl; /*!< Event parameter of ESP_GAP_BLE_SET_SCAN_CHAN_MAP_CMPL_EVT */ #endif // #if (BLE_VENDOR_HCI_EN == TRUE) #if (BLE_FEAT_POWER_CONTROL_EN == TRUE) /** @@ -2081,6 +2088,7 @@ esp_err_t esp_ble_gap_set_resolvable_private_address_timeout(uint16_t rpa_timeou * */ esp_err_t esp_ble_gap_add_device_to_resolving_list(esp_bd_addr_t peer_addr, uint8_t addr_type, uint8_t *peer_irk); + /** * @brief This function clears the random address for the application * @@ -2486,6 +2494,28 @@ esp_err_t esp_ble_sc_oob_req_reply(esp_bd_addr_t bd_addr, uint8_t p_c[16], uint8 * */ esp_err_t esp_ble_create_sc_oob_data(void); + +/** + * @brief Get the local Identity Resolving Key (IRK). + * + * @note This API retrieves the local IRK stored in the device's security database. + * The IRK is used by the controller to generate and resolve Resolvable Private Addresses (RPA). + * The IRK length is always 16 bytes (ESP_BT_OCTET16_LEN). + * + * @note Usage Restrictions: Do NOT call this API during a disconnection event or while + * a BLE disconnection is in progress. Calling this API during disconnection may lead + * to undefined behavior or accessing invalid information. + * + * @param[out] local_irk: Buffer to hold the 16-byte IRK. The array notation [16] explicitly + * indicates the required buffer size (ESP_BT_OCTET16_LEN). + * + * @return + * - ESP_OK : success + * - ESP_ERR_INVALID_ARG : local_irk is NULL + * - ESP_ERR_INVALID_STATE : BLE stack not initialized or IRK not available + */ +esp_err_t esp_ble_gap_get_local_irk(uint8_t local_irk[16]); + #endif /* #if (SMP_INCLUDED == TRUE) */ /** @@ -3144,6 +3174,28 @@ esp_err_t esp_ble_gap_set_common_factor(uint32_t common_factor); */ esp_err_t esp_ble_gap_set_sch_len(uint8_t role, uint32_t len); +/** + * @brief This function is used to Set the channel map for LE scanning or initiating state. + * + * @note - This function must be called before starting scanning or initiating. + * - At least one channel should be marked as used. + * + * @param[in] state: The LE state for which the channel map is applied. + * - 0 : Scanning state + * - 1 : Initiating state + * @param[in] chan_map: A 5-byte array representing the channel usage bit mask. + * Each bit corresponds to one channel from channel 0 to channel 39. + * The least significant bit of chan_map[0] corresponds to channel 0. + * The most significant bit of chan_map[4] corresponds to channel 39. + * - Bit = 1 : channel is used + * - Bit = 0 : channel is not used + * + * @return + * - ESP_OK : success + * - other : failed + */ +esp_err_t esp_ble_gap_set_scan_chan_map(uint8_t state, uint8_t chan_map[5]); + /** * @brief This function is used to read the current and maximum transmit power levels of the local Controller. * diff --git a/components/bt/host/bluedroid/bta/av/bta_av_act.c b/components/bt/host/bluedroid/bta/av/bta_av_act.c index 1fd59a044d48..23c1638bca35 100644 --- a/components/bt/host/bluedroid/bta/av/bta_av_act.c +++ b/components/bt/host/bluedroid/bta/av/bta_av_act.c @@ -685,11 +685,18 @@ static tAVRC_STS bta_av_chk_notif_evt_id(tAVRC_MSG_VENDOR *p_vendor) { tAVRC_STS status = BTA_AV_STS_NO_RSP; UINT16 u16; - UINT8 *p = p_vendor->p_vendor_data + 2; + UINT8 *p = NULL; + + if (!p_vendor || !p_vendor->p_vendor_data || + (p_vendor->vendor_len != AVRC_REGISTER_NOTIFICATION_CMD_SIZE)) { + return AVRC_STS_INTERNAL_ERR; + } + + p = p_vendor->p_vendor_data + AVRC_CMD_PARAM_LENGTH_OFFSET; BE_STREAM_TO_UINT16 (u16, p); /* double check the fixed length */ - if ((u16 != 5) || (p_vendor->vendor_len != 9)) { + if (u16 != 5) { status = AVRC_STS_INTERNAL_ERR; } else { /* make sure the event_id is valid */ @@ -722,6 +729,12 @@ tBTA_AV_EVT bta_av_proc_meta_cmd(tAVRC_RESPONSE *p_rc_rsp, tBTA_AV_RC_MSG *p_ms #if (AVRC_METADATA_INCLUDED == TRUE) + if (!p_vendor || !p_vendor->p_vendor_data || (p_vendor->vendor_len == 0)) { + evt = 0; + p_rc_rsp->rsp.status = AVRC_STS_BAD_CMD; + return evt; + } + pdu = *(p_vendor->p_vendor_data); p_rc_rsp->pdu = pdu; *p_ctype = AVRC_RSP_REJ; @@ -741,12 +754,16 @@ tBTA_AV_EVT bta_av_proc_meta_cmd(tAVRC_RESPONSE *p_rc_rsp, tBTA_AV_RC_MSG *p_ms switch (pdu) { case AVRC_PDU_GET_CAPABILITIES: /* process GetCapabilities command without reporting the event to app */ + if (p_vendor->vendor_len != AVRC_GET_CAPABILITIES_CMD_SIZE) { + p_rc_rsp->get_caps.status = AVRC_STS_INTERNAL_ERR; + break; + } evt = 0; - u8 = *(p_vendor->p_vendor_data + 4); - p = p_vendor->p_vendor_data + 2; + u8 = *(p_vendor->p_vendor_data + AVRC_CMD_PARAM_VALUE_OFFSET); + p = p_vendor->p_vendor_data + AVRC_CMD_PARAM_LENGTH_OFFSET; p_rc_rsp->get_caps.capability_id = u8; BE_STREAM_TO_UINT16 (u16, p); - if ((u16 != 1) || (p_vendor->vendor_len != 5)) { + if (u16 != 1) { p_rc_rsp->get_caps.status = AVRC_STS_INTERNAL_ERR; } else { p_rc_rsp->get_caps.status = AVRC_STS_NO_ERROR; diff --git a/components/bt/host/bluedroid/btc/profile/std/avrc/btc_avrc.c b/components/bt/host/bluedroid/btc/profile/std/avrc/btc_avrc.c index d39fcca508e2..e6613039e9b9 100644 --- a/components/bt/host/bluedroid/btc/profile/std/avrc/btc_avrc.c +++ b/components/bt/host/bluedroid/btc/profile/std/avrc/btc_avrc.c @@ -582,13 +582,18 @@ static void handle_rc_disconnect (tBTA_AV_RC_CLOSE *p_rc_close) static void handle_rc_attributes_rsp (tAVRC_MSG_VENDOR *vendor_msg) { - uint8_t attr_count = vendor_msg->p_vendor_data[4]; + uint8_t attr_count = 0; int attr_index = 5; int attr_length = 0; uint32_t attr_id = 0; + if (!vendor_msg || !vendor_msg->p_vendor_data || + (vendor_msg->vendor_len < AVRC_GET_ELEMENT_ATTR_RSP_SIZE_MIN)) { + return; + } + //Check if there are any attributes - if (attr_count < 1) { + if ((attr_count = vendor_msg->p_vendor_data[AVRC_RSP_PARAM_VALUE_OFFSET]) < 1) { return; } @@ -596,8 +601,16 @@ static void handle_rc_attributes_rsp (tAVRC_MSG_VENDOR *vendor_msg) memset(¶m[0], 0, sizeof(esp_avrc_ct_cb_param_t) * attr_count); for (int i = 0; i < attr_count; i++) { + if (vendor_msg->vendor_len < attr_index + 8) { + return; + } + attr_length = (int) vendor_msg->p_vendor_data[7 + attr_index] | vendor_msg->p_vendor_data[6 + attr_index] << 8; + if (vendor_msg->vendor_len < attr_index + attr_length + 8) { + return; + } + //Received attribute text is not null terminated, so it's useful to know it's length param[i].meta_rsp.attr_length = attr_length; param[i].meta_rsp.attr_text = &vendor_msg->p_vendor_data[8 + attr_index]; @@ -620,30 +633,52 @@ static void handle_rc_notification_rsp (tAVRC_MSG_VENDOR *vendor_msg) esp_avrc_ct_cb_param_t param; memset(¶m, 0, sizeof(esp_avrc_ct_cb_param_t)); - param.change_ntf.event_id = vendor_msg->p_vendor_data[4]; + if (!vendor_msg || !vendor_msg->p_vendor_data || + (vendor_msg->vendor_len < AVRC_REGISTER_NOTIFICATION_RSP_SIZE_MIN)) { + return; + } + + param.change_ntf.event_id = vendor_msg->p_vendor_data[AVRC_RSP_PARAM_VALUE_OFFSET]; - uint8_t *data = &vendor_msg->p_vendor_data[5]; + uint8_t *data = &vendor_msg->p_vendor_data[AVRC_RSP_PARAM_VALUE_OFFSET + 1]; if (!btc_avrc_ct_rn_evt_supported(param.change_ntf.event_id)) { BTC_TRACE_WARNING("%s unsupported notification on CT, event id 0x%x", __FUNCTION__, param.change_ntf.event_id); return; } + + bool notif = false; switch (param.change_ntf.event_id) { case ESP_AVRC_RN_PLAY_STATUS_CHANGE: - BE_STREAM_TO_UINT8(param.change_ntf.event_parameter.playback, data); + if (vendor_msg->vendor_len >= AVRC_RN_PLAY_STATUS_CHANGE_EVT_SIZE) { + BE_STREAM_TO_UINT8(param.change_ntf.event_parameter.playback, data); + notif = true; + } break; case ESP_AVRC_RN_TRACK_CHANGE: - memcpy(param.change_ntf.event_parameter.elm_id, data, 8); + if (vendor_msg->vendor_len >= AVRC_RN_TRACK_CHANGE_EVT_SIZE) { + memcpy(param.change_ntf.event_parameter.elm_id, data, 8); + notif = true; + } break; case ESP_AVRC_RN_PLAY_POS_CHANGED: - BE_STREAM_TO_UINT32(param.change_ntf.event_parameter.play_pos, data); + if (vendor_msg->vendor_len >= AVRC_RN_PLAY_POS_CHANGED_EVT_SIZE) { + BE_STREAM_TO_UINT32(param.change_ntf.event_parameter.play_pos, data); + notif = true; + } break; case ESP_AVRC_RN_BATTERY_STATUS_CHANGE: - BE_STREAM_TO_UINT8(param.change_ntf.event_parameter.batt, data); + if (vendor_msg->vendor_len >= AVRC_RN_BATTERY_STATUS_CHANGE_EVT_SIZE) { + BE_STREAM_TO_UINT8(param.change_ntf.event_parameter.batt, data); + notif = true; + } break; case ESP_AVRC_RN_VOLUME_CHANGE: - BE_STREAM_TO_UINT8(param.change_ntf.event_parameter.volume, data); + if (vendor_msg->vendor_len >= AVRC_RN_VOLUME_CHANGE_EVT_SIZE) { + BE_STREAM_TO_UINT8(param.change_ntf.event_parameter.volume, data); + notif = true; + } break; // for non-parameter event response case ESP_AVRC_RN_TRACK_REACHED_END: @@ -661,7 +696,10 @@ static void handle_rc_notification_rsp (tAVRC_MSG_VENDOR *vendor_msg) param.change_ntf.event_id); break; } - btc_avrc_ct_cb_to_app(ESP_AVRC_CT_CHANGE_NOTIFY_EVT, ¶m); + + if (notif) { + btc_avrc_ct_cb_to_app(ESP_AVRC_CT_CHANGE_NOTIFY_EVT, ¶m); + } } static void handle_rc_get_caps_rsp (tAVRC_GET_CAPS_RSP *rsp) @@ -840,7 +878,7 @@ static void handle_rc_metamsg_rsp (tBTA_AV_META_MSG *p_meta_msg) tAVRC_RESPONSE avrc_response = {0}; tAVRC_STS status; tAVRC_MSG_VENDOR *vendor_msg = &p_meta_msg->p_msg->vendor; - BTC_TRACE_DEBUG("%s: opcode %d, pdu 0x%x, code %d", __FUNCTION__, p_meta_msg->p_msg->hdr.opcode, vendor_msg->p_vendor_data[0], + BTC_TRACE_DEBUG("%s: opcode %d, pdu 0x%x, code %d", __FUNCTION__, p_meta_msg->p_msg->hdr.opcode, vendor_msg->p_vendor_data[AVRC_RSP_OPCODE_OFFSET], p_meta_msg->code); if ( p_meta_msg->p_msg->hdr.opcode != AVRC_OP_VENDOR) { return; @@ -856,7 +894,7 @@ static void handle_rc_metamsg_rsp (tBTA_AV_META_MSG *p_meta_msg) // handle GET_ELEMENT_ATTR response if (p_meta_msg->code == AVRC_RSP_IMPL_STBL && - vendor_msg->p_vendor_data[0] == AVRC_PDU_GET_ELEMENT_ATTR) { + vendor_msg->p_vendor_data[AVRC_RSP_OPCODE_OFFSET] == AVRC_PDU_GET_ELEMENT_ATTR) { handle_rc_attributes_rsp(vendor_msg); return; } diff --git a/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c b/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c index 28173655834c..b74ffa00f1a7 100644 --- a/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c +++ b/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c @@ -1104,7 +1104,7 @@ static void btc_ble_5_gap_callback(tBTA_DM_BLE_5_GAP_EVENT event, } case BTA_DM_BLE_5_GAP_PHY_UPDATE_COMPLETE_EVT: msg.act = ESP_GAP_BLE_PHY_UPDATE_COMPLETE_EVT; - param.phy_update.status = btc_btm_status_to_esp_status(params->phy_update.status); + param.phy_update.status = btc_hci_to_esp_status(params->phy_update.status); memcpy(param.phy_update.bda, params->phy_update.addr, BD_ADDR_LEN); param.phy_update.tx_phy = params->phy_update.tx_phy; param.phy_update.rx_phy = params->phy_update.rx_phy; @@ -1169,7 +1169,7 @@ static void btc_ble_5_gap_callback(tBTA_DM_BLE_5_GAP_EVENT event, } case BTA_DM_BLE_5_GAP_PERIODIC_ADV_SYNC_ESTAB_EVT: { msg.act = ESP_GAP_BLE_PERIODIC_ADV_SYNC_ESTAB_EVT; - param.periodic_adv_sync_estab.status = btc_btm_status_to_esp_status(params->sync_estab.status); + param.periodic_adv_sync_estab.status = btc_hci_to_esp_status(params->sync_estab.status); param.periodic_adv_sync_estab.sync_handle = params->sync_estab.sync_handle; param.periodic_adv_sync_estab.sid = params->sync_estab.sid; param.periodic_adv_sync_estab.adv_addr_type = params->sync_estab.adv_addr_type; @@ -1204,7 +1204,7 @@ static void btc_ble_5_gap_callback(tBTA_DM_BLE_5_GAP_EVENT event, break; case BTA_BLE_GAP_PERIODIC_ADV_SYNC_TRANS_RECV_EVT: msg.act = ESP_GAP_BLE_PERIODIC_ADV_SYNC_TRANS_RECV_EVT; - param.past_received.status = btc_btm_status_to_esp_status(params->past_recv.status); + param.past_received.status = btc_hci_to_esp_status(params->past_recv.status); memcpy(param.past_received.bda, params->past_recv.addr, sizeof(BD_ADDR)); param.past_received.service_data = params->past_recv.service_data; param.past_received.sync_handle = params->past_recv.sync_handle; @@ -1452,6 +1452,10 @@ static void btc_ble_vendor_hci_cmd_complete_callback(tBTA_VSC_CMPL *p_param) msg.act = ESP_GAP_BLE_SET_SCH_LEN_CMPL_EVT; param.set_sch_len_cmpl.status = p_param->p_param_buf[0]; break; + case 0xFD19: + msg.act = ESP_GAP_BLE_SET_SCAN_CHAN_MAP_CMPL_EVT; + param.set_scan_chan_map_cmpl.status = btc_hci_to_esp_status(p_param->p_param_buf[0]); + break; default: param.vendor_cmd_cmpl.opcode = p_param->opcode; param.vendor_cmd_cmpl.param_len = p_param->param_len; diff --git a/components/bt/host/bluedroid/common/include/common/bt_trace.h b/components/bt/host/bluedroid/common/include/common/bt_trace.h index 58435d8f6aed..a2bb9dd4487f 100644 --- a/components/bt/host/bluedroid/common/include/common/bt_trace.h +++ b/components/bt/host/bluedroid/common/include/common/bt_trace.h @@ -24,6 +24,9 @@ #include "bluedroid_user_config.h" #include "stack/bt_types.h" #include "bt_common.h" +#if CONFIG_BLE_HOST_COMPRESSED_LOG_ENABLE +#include "host_log_index.h" +#endif #if (BT_BLE_LOG_SPI_OUT_HOST_ENABLED && !CLASSIC_BT_INCLUDED) #include "ble_log/ble_log_spi_out.h" diff --git a/components/bt/host/bluedroid/hci/hci_hal_h4.c b/components/bt/host/bluedroid/hci/hci_hal_h4.c index ef874844edae..5baf97fc0810 100644 --- a/components/bt/host/bluedroid/hci/hci_hal_h4.c +++ b/components/bt/host/bluedroid/hci/hci_hal_h4.c @@ -25,6 +25,7 @@ #include "hci/hci_trans_int.h" #include "osi/thread.h" #include "osi/pkt_queue.h" +#include "esp_bt_main.h" #if (BLE_ADV_REPORT_FLOW_CONTROL == TRUE) #include "osi/mutex.h" #include "osi/alarm.h" @@ -645,6 +646,11 @@ static int host_recv_pkt_cb(uint8_t *data, uint16_t len) fixed_queue_enqueue(hci_hal_env.rx_q, pkt, FIXED_QUEUE_MAX_TIMEOUT); } } else { + if (esp_bluedroid_get_status() != ESP_BLUEDROID_STATUS_ENABLED) { + // Prevent race condition during host deinit/disable + // Host not ready, dropped advertising report + return 0; + } #if (BLE_42_SCAN_EN == TRUE) #if !BLE_ADV_REPORT_FLOW_CONTROL // drop the packets if pkt_queue length goes beyond upper limit diff --git a/components/bt/host/bluedroid/stack/avrc/avrc_api.c b/components/bt/host/bluedroid/stack/avrc/avrc_api.c index 9972bbfde425..f7e31022d0da 100644 --- a/components/bt/host/bluedroid/stack/avrc/avrc_api.c +++ b/components/bt/host/bluedroid/stack/avrc/avrc_api.c @@ -545,7 +545,22 @@ static void avrc_msg_cback(UINT8 handle, UINT8 label, UINT8 cr, p_data = (UINT8 *)(p_pkt + 1) + p_pkt->offset; memset(&msg, 0, sizeof(tAVRC_MSG) ); - { + + if (p_pkt->layer_specific == AVCT_DATA_BROWSE) { + // opcode = AVRC_OP_BROWSE; + // msg.browse.hdr.ctype = cr; + // msg.browse.p_browse_data = p_data; + // msg.browse.browse_len = p_pkt->len; + // msg.browse.p_browse_pkt = p_pkt; + AVRC_TRACE_ERROR("BROWSE CHANNEL NOT SUPPORTED NOW!"); + osi_free(p_pkt); + return; + } else { + if (p_pkt->len < AVRC_AVC_HDR_SIZE) { + AVRC_TRACE_WARNING("Bad message length:%d (< %d)", p_pkt->len, AVRC_AVC_HDR_SIZE); + osi_free(p_pkt); + return; + } msg.hdr.ctype = p_data[0] & AVRC_CTYPE_MASK; AVRC_TRACE_DEBUG("avrc_msg_cback handle:%d, ctype:%d, offset:%d, len: %d", handle, msg.hdr.ctype, p_pkt->offset, p_pkt->len); @@ -578,6 +593,14 @@ static void avrc_msg_cback(UINT8 handle, UINT8 label, UINT8 cr, p_drop_msg = "auto respond"; #endif } else { + if (p_pkt->len < AVRC_OP_UNIT_INFO_RSP_LEN) { + AVRC_TRACE_WARNING("Bad message length:%d (< %d)", p_pkt->len, AVRC_OP_UNIT_INFO_RSP_LEN); + drop = TRUE; +#if (BT_USE_TRACES == TRUE) + p_drop_msg = "UNIT_INFO_RSP too short"; +#endif + break; + } /* parse response */ p_data += 4; /* 3 bytes: ctype, subunit*, opcode + octet 3 (is 7)*/ msg.unit.unit_type = (*p_data & AVRC_SUBTYPE_MASK) >> AVRC_SUBTYPE_SHIFT; @@ -594,7 +617,7 @@ static void avrc_msg_cback(UINT8 handle, UINT8 label, UINT8 cr, p_rsp_data = avrc_get_data_ptr(p_rsp); *p_rsp_data = AVRC_RSP_IMPL_STBL; /* check & set the offset. set response code, set (subunit_type & subunit_id), - set AVRC_OP_SUB_INFO, set (page & extention code) */ + set AVRC_OP_SUB_INFO, set (page & extension code) */ p_rsp_data += 4; /* Panel subunit & id=0 */ *p_rsp_data++ = (AVRC_SUB_PANEL << AVRC_SUBTYPE_SHIFT); @@ -606,6 +629,14 @@ static void avrc_msg_cback(UINT8 handle, UINT8 label, UINT8 cr, p_drop_msg = "auto responded"; #endif } else { + if (p_pkt->len < AVRC_OP_SUB_UNIT_INFO_RSP_LEN) { + AVRC_TRACE_WARNING("Bad message length:%d (< %d)", p_pkt->len, AVRC_OP_SUB_UNIT_INFO_RSP_LEN); + drop = TRUE; +#if (BT_USE_TRACES == TRUE) + p_drop_msg = "UNIT_INFO_RSP too short"; +#endif + break; + } /* parse response */ p_data += AVRC_AVC_HDR_SIZE; /* 3 bytes: ctype, subunit*, opcode */ msg.sub.page = (*p_data++ >> AVRC_SUB_PAGE_SHIFT) & AVRC_SUB_PAGE_MASK; diff --git a/components/bt/host/bluedroid/stack/avrc/avrc_opt.c b/components/bt/host/bluedroid/stack/avrc/avrc_opt.c index 6f0663c08ad3..cd933df73ea8 100644 --- a/components/bt/host/bluedroid/stack/avrc/avrc_opt.c +++ b/components/bt/host/bluedroid/stack/avrc/avrc_opt.c @@ -48,17 +48,28 @@ ******************************************************************************/ static BT_HDR *avrc_vendor_msg(tAVRC_MSG_VENDOR *p_msg) { - BT_HDR *p_cmd; + BT_HDR *p_cmd = NULL; UINT8 *p_data; - assert(p_msg != NULL); +/* + A vendor dependent command consists of at least of: + - A BT_HDR, plus + - AVCT_MSG_OFFSET, plus + - 3 bytes for ctype, subunit_type and op_vendor, plus + - 3 bytes for company_id +*/ +#define AVRC_MIN_VENDOR_CMD_LEN (BT_HDR_SIZE + AVCT_MSG_OFFSET + AVRC_VENDOR_HDR_SIZE) + + if (!p_msg) { + return NULL; + } #if AVRC_METADATA_INCLUDED == TRUE - assert(AVRC_META_CMD_BUF_SIZE > (AVRC_MIN_CMD_LEN + p_msg->vendor_len)); - if ((p_cmd = (BT_HDR *) osi_malloc(AVRC_META_CMD_BUF_SIZE)) != NULL) + if ((AVRC_META_CMD_BUF_SIZE > AVRC_MIN_VENDOR_CMD_LEN + p_msg->vendor_len) && + ((p_cmd = (BT_HDR *) osi_malloc(AVRC_META_CMD_BUF_SIZE)) != NULL)) #else - assert(AVRC_CMD_BUF_SIZE > (AVRC_MIN_CMD_LEN + p_msg->vendor_len)); - if ((p_cmd = (BT_HDR *) osi_malloc(AVRC_CMD_BUF_SIZE)) != NULL) + if ((AVRC_CMD_BUF_SIZE > (AVRC_MIN_VENDOR_CMD_LEN + p_msg->vendor_len)) && + (p_cmd = (BT_HDR *) osi_malloc(AVRC_CMD_BUF_SIZE)) != NULL) #endif { p_cmd->offset = AVCT_MSG_OFFSET; diff --git a/components/bt/host/bluedroid/stack/avrc/avrc_pars_tg.c b/components/bt/host/bluedroid/stack/avrc/avrc_pars_tg.c index fe04ca8f326d..a5fed6b2b021 100644 --- a/components/bt/host/bluedroid/stack/avrc/avrc_pars_tg.c +++ b/components/bt/host/bluedroid/stack/avrc/avrc_pars_tg.c @@ -56,7 +56,7 @@ static tAVRC_STS avrc_pars_vendor_cmd(tAVRC_MSG_VENDOR *p_msg, tAVRC_COMMAND *p_ if (p_msg->vendor_len == 0) { return AVRC_STS_NO_ERROR; } - if (p_msg->p_vendor_data == NULL) { + if ((p_msg->p_vendor_data == NULL) || (p_msg->vendor_len < AVRC_CMD_FIXED_SIZE)) { return AVRC_STS_INTERNAL_ERR; } diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c b/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c index b063aefd9b94..faf2e1848f0a 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c +++ b/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c @@ -2063,7 +2063,6 @@ UINT8 *BTM_CheckAdvData( UINT8 *p_adv, UINT16 adv_data_len, UINT8 type, UINT8 *p UINT8 *p = p_adv; UINT8 length; UINT8 adv_type; - BTM_TRACE_API("BTM_CheckAdvData type=0x%02X", type); STREAM_TO_UINT8(length, p); @@ -4870,4 +4869,16 @@ bool btm_ble_adv_pkt_post(pkt_linked_item_t *pkt) } #endif // #if (BLE_42_SCAN_EN == TRUE) +#if (SMP_INCLUDED == TRUE) +/* Retrieve local IRK safely */ +bool BTM_GetLocalIRK(uint8_t *irk) +{ + if (!irk) { + return false; + } + + memcpy(irk, btm_cb.devcb.id_keys.irk, sizeof(btm_cb.devcb.id_keys.irk)); + return true; +} +#endif // (SMP_INCLUDED == TRUE) #endif /* BLE_INCLUDED */ diff --git a/components/bt/host/bluedroid/stack/btm/btm_inq.c b/components/bt/host/bluedroid/stack/btm/btm_inq.c index ed84167982e8..4456140df93f 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_inq.c +++ b/components/bt/host/bluedroid/stack/btm/btm_inq.c @@ -2450,7 +2450,7 @@ UINT8 *BTM_CheckEirData( UINT8 *p_eir, UINT8 type, UINT8 *p_length ) /* Break loop if eir data is in an incorrect format, as it may lead to memory overflow */ - if ( p >= p_eir + HCI_EXT_INQ_RESPONSE_LEN ) { + if ( p >= p_eir + HCI_EXT_INQ_RESPONSE_LEN - 1 ) { break; } diff --git a/components/bt/host/bluedroid/stack/gatt/gatt_main.c b/components/bt/host/bluedroid/stack/gatt/gatt_main.c index 53d9be747dec..e5d982371252 100644 --- a/components/bt/host/bluedroid/stack/gatt/gatt_main.c +++ b/components/bt/host/bluedroid/stack/gatt/gatt_main.c @@ -169,7 +169,7 @@ void gatt_free(void) gatt_cb.sign_op_queue = NULL; fixed_queue_free(gatt_cb.srv_chg_clt_q, NULL); gatt_cb.srv_chg_clt_q = NULL; - fixed_queue_free(gatt_cb.pending_new_srv_start_q, NULL); + fixed_queue_free(gatt_cb.pending_new_srv_start_q, osi_free_func); gatt_cb.pending_new_srv_start_q = NULL; list_node_t *p_node = NULL; diff --git a/components/bt/host/bluedroid/stack/include/stack/avrc_defs.h b/components/bt/host/bluedroid/stack/include/stack/avrc_defs.h index 06f73c29695b..54e81793cf83 100644 --- a/components/bt/host/bluedroid/stack/include/stack/avrc_defs.h +++ b/components/bt/host/bluedroid/stack/include/stack/avrc_defs.h @@ -214,6 +214,55 @@ #define AVRC_PDU_ADD_TO_NOW_PLAYING 0x90 #define AVRC_PDU_GENERAL_REJECT 0xA0 +/* Define the length of vendor dependent PDUs +*/ +#define AVRC_CMD_PARAM_LENGTH_OFFSET 2 +#define AVRC_CMD_PARAM_VALUE_OFFSET 4 +#define AVRC_CMD_FIXED_SIZE 4 + +#define AVRC_GET_CAPABILITIES_CMD_SIZE (AVRC_CMD_FIXED_SIZE + 1) +#define AVRC_LIST_PLAYER_APP_ATTR_CMD_SIZE (AVRC_CMD_FIXED_SIZE + 0) +#define AVRC_LIST_PLAYER_APP_VALUES_CMD_SIZE (AVRC_CMD_FIXED_SIZE + 1) +#define AVRC_GET_CUR_PLAYER_APP_VALUE_CMD_SIZE (AVRC_CMD_FIXED_SIZE + 2) +#define AVRC_SET_PLAYER_APP_VALUE_CMD_SIZE (AVRC_CMD_FIXED_SIZE + 3) +#define AVRC_GET_PLAYER_APP_ATTR_TEXT_CMD_SIZE (AVRC_CMD_FIXED_SIZE + 2) +#define AVRC_GET_PLAYER_APP_VALUE_TEXT_CMD_SIZE (AVRC_CMD_FIXED_SIZE + 3) +#define AVRC_INFORM_DISPLAY_CHARSET_CMD_SIZE (AVRC_CMD_FIXED_SIZE + 3) +#define AVRC_INFORM_BATTERY_STAT_OF_CT_CMD_SIZE (AVRC_CMD_FIXED_SIZE + 1) +#define AVRC_GET_ELEMENT_ATTR_CMD_SIZE (AVRC_CMD_FIXED_SIZE + 13) +#define AVRC_GET_PLAY_STATUS_CMD_SIZE (AVRC_CMD_FIXED_SIZE + 0) +#define AVRC_REGISTER_NOTIFICATION_CMD_SIZE (AVRC_CMD_FIXED_SIZE + 5) +#define AVRC_REQUEST_CONTINUATION_RSP_CMD_SIZE (AVRC_CMD_FIXED_SIZE + 1) +#define AVRC_ABORT_CONTINUATION_RSP_CMD_SIZE (AVRC_CMD_FIXED_SIZE + 1) + +/* Define the length of response of vendor dependent PDUs +*/ +#define AVRC_RSP_OPCODE_OFFSET 0 +#define AVRC_RSP_PARAM_LENGTH_OFFSET 2 +#define AVRC_RSP_PARAM_VALUE_OFFSET 4 +#define AVRC_RSP_FIXED_SIZE 4 + +#define AVRC_GET_CAPABILITIES_RSP_SIZE_MIN (AVRC_RSP_FIXED_SIZE + 1) +#define AVRC_LIST_PLAYER_APP_ATTR_RSP_SIZE (AVRC_RSP_FIXED_SIZE + 2) +#define AVRC_LIST_PLAYER_APP_VALUES_RSP_SIZE (AVRC_RSP_FIXED_SIZE + 2) +#define AVRC_GET_CUR_PLAYER_APP_VALUE_RSP_SIZE (AVRC_RSP_FIXED_SIZE + 3) +#define AVRC_SET_PLAYER_APP_VALUE_RSP_SIZE (AVRC_RSP_FIXED_SIZE + 2) +#define AVRC_GET_PLAYER_APP_ATTR_TEXT_RSP_SIZE_MIN (AVRC_RSP_FIXED_SIZE + 6) +#define AVRC_GET_PLAYER_APP_VALUE_TEXT_RSP_SIZE_MIN (AVRC_RSP_FIXED_SIZE + 6) +#define AVRC_INFORM_DISPLAY_CHARSET_RSP_SIZE (AVRC_RSP_FIXED_SIZE + 0) +#define AVRC_INFORM_BATTERY_STAT_OF_CT_RSP_SIZE (AVRC_RSP_FIXED_SIZE + 0) +#define AVRC_GET_ELEMENT_ATTR_RSP_SIZE_MIN (AVRC_RSP_FIXED_SIZE + 1) +#define AVRC_GET_PLAY_STATUS_RSP_SIZE (AVRC_RSP_FIXED_SIZE + 9) +#define AVRC_REGISTER_NOTIFICATION_RSP_SIZE_MIN (AVRC_RSP_FIXED_SIZE + 2) +#define AVRC_RN_PLAY_STATUS_CHANGE_EVT_SIZE (AVRC_REGISTER_NOTIFICATION_RSP_SIZE_MIN) +#define AVRC_RN_TRACK_CHANGE_EVT_SIZE (AVRC_REGISTER_NOTIFICATION_RSP_SIZE_MIN + 7) +#define AVRC_RN_PLAY_POS_CHANGED_EVT_SIZE (AVRC_REGISTER_NOTIFICATION_RSP_SIZE_MIN + 3) +#define AVRC_RN_BATTERY_STATUS_CHANGE_EVT_SIZE (AVRC_REGISTER_NOTIFICATION_RSP_SIZE_MIN) +#define AVRC_RN_SYSTEM_STATUS_CHANGE_EVT_SIZE (AVRC_REGISTER_NOTIFICATION_RSP_SIZE_MIN) +#define AVRC_RN_APP_SETTING_CHANGE_EVT_SIZE (AVRC_REGISTER_NOTIFICATION_RSP_SIZE_MIN + 2) +#define AVRC_RN_VOLUME_CHANGE_EVT_SIZE (AVRC_REGISTER_NOTIFICATION_RSP_SIZE_MIN) +#define AVRC_ABORT_CONTINUATION_RSP_RSP_SIZE (AVRC_RSP_FIXED_SIZE + 0) + /* Define the vendor unique id carried in the pass through data */ #define AVRC_PDU_NEXT_GROUP 0x00 diff --git a/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h b/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h index 7ec384ef1bf1..e696fe65cfbd 100644 --- a/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h +++ b/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h @@ -2561,6 +2561,20 @@ void BTM_BleReadControllerFeatures(tBTM_BLE_CTRL_FEATURES_CBACK *p_vsc_cback); //extern UINT8 *BTM_CheckAdvData( UINT8 *p_adv, UINT16 adv_data_len, UINT8 type, UINT8 *p_length); +/****************************************************************************** +** +** Function BTM_GetLocalIRK +** +** Description Get the local Identity Resolving Key (IRK) from the device control block. +** +** Parameters irk : output buffer (16 bytes) to copy IRK into +** +** Returns true if IRK is available, false otherwise +** +******************************************************************************/ +bool BTM_GetLocalIRK(uint8_t *irk); + + /******************************************************************************* ** ** Function BTM_BleGetCurrentAddress diff --git a/components/bt/host/bluedroid/stack/include/stack/rfcdefs.h b/components/bt/host/bluedroid/stack/include/stack/rfcdefs.h index dcc37bc7287d..b6bda55b1216 100644 --- a/components/bt/host/bluedroid/stack/include/stack/rfcdefs.h +++ b/components/bt/host/bluedroid/stack/include/stack/rfcdefs.h @@ -42,7 +42,7 @@ #define RFCOMM_UIH 0xEF /* -** Defenitions for the TS control frames +** Definitions for the TS control frames */ #define RFCOMM_CTRL_FRAME_LEN 3 #define RFCOMM_MIN_OFFSET 5 /* ctrl 2 , len 1 or 2 bytes, credit 1 byte */ @@ -90,13 +90,6 @@ pf = (*p_data++ & RFCOMM_PF_MASK) >> RFCOMM_PF_OFFSET;\ } -#define RFCOMM_PARSE_LEN_FIELD(ea, length, p_data) \ -{ \ - ea = (*p_data & RFCOMM_EA); \ - length = (*p_data++ >> RFCOMM_SHIFT_LENGTH1); \ - if (!ea) length += (*p_data++ << RFCOMM_SHIFT_LENGTH2); \ -} - #define RFCOMM_FRAME_IS_CMD(initiator, cr) \ (( (initiator) && !(cr)) || (!(initiator) && (cr))) @@ -139,7 +132,7 @@ #define RFCOMM_MSC_FC 0x02 /* Flow control*/ #define RFCOMM_MSC_RTC 0x04 /* Ready to communicate*/ #define RFCOMM_MSC_RTR 0x08 /* Ready to receive*/ -#define RFCOMM_MSC_IC 0x40 /* Incomming call indicator*/ +#define RFCOMM_MSC_IC 0x40 /* Incoming call indicator*/ #define RFCOMM_MSC_DV 0x80 /* Data Valid*/ #define RFCOMM_MSC_SHIFT_BREAK 4 diff --git a/components/bt/host/bluedroid/stack/rfcomm/rfc_ts_frames.c b/components/bt/host/bluedroid/stack/rfcomm/rfc_ts_frames.c index 86ba2550a563..2d06823173f9 100644 --- a/components/bt/host/bluedroid/stack/rfcomm/rfc_ts_frames.c +++ b/components/bt/host/bluedroid/stack/rfcomm/rfc_ts_frames.c @@ -646,7 +646,17 @@ UINT8 rfc_parse_data (tRFC_MCB *p_mcb, MX_FRAME *p_frame, BT_HDR *p_buf) return (RFC_EVENT_BAD_FRAME); } RFCOMM_PARSE_TYPE_FIELD (p_frame->type, p_frame->pf, p_data); - RFCOMM_PARSE_LEN_FIELD (eal, len, p_data); + + eal = *(p_data) & RFCOMM_EA; + len = *(p_data)++ >> RFCOMM_SHIFT_LENGTH1; + if (eal == 0) { + if (p_buf->len > RFCOMM_CTRL_FRAME_LEN) { + len += (*(p_data)++ << RFCOMM_SHIFT_LENGTH2); + } else { + RFCOMM_TRACE_ERROR("Bad Length when EAL = 0: %d", p_buf->len); + return RFC_EVENT_BAD_FRAME; + } + } p_buf->len -= (3 + !ead + !eal + 1); /* Additional 1 for FCS */ p_buf->offset += (3 + !ead + !eal); @@ -670,7 +680,7 @@ UINT8 rfc_parse_data (tRFC_MCB *p_mcb, MX_FRAME *p_frame, BT_HDR *p_buf) /* All control frames that we are sending are sent with P=1, expect */ /* reply with F=1 */ - /* According to TS 07.10 spec ivalid frames are discarded without */ + /* According to TS 07.10 spec invalid frames are discarded without */ /* notification to the sender */ switch (p_frame->type) { case RFCOMM_SABME: @@ -749,6 +759,12 @@ void rfc_process_mx_message (tRFC_MCB *p_mcb, BT_HDR *p_buf) UINT8 ea, cr, mx_len; BOOLEAN is_command; + if (length < 2) { + RFCOMM_TRACE_ERROR("Illegal MX Frame len:%d < 2", length); + osi_free(p_buf); + return; + } + p_rx_frame->ea = *p_data & RFCOMM_EA; p_rx_frame->cr = (*p_data & RFCOMM_CR_MASK) >> RFCOMM_SHIFT_CR; p_rx_frame->type = *p_data++ & ~(RFCOMM_CR_MASK | RFCOMM_EA_MASK); @@ -769,6 +785,11 @@ void rfc_process_mx_message (tRFC_MCB *p_mcb, BT_HDR *p_buf) length--; if (!ea) { + if (length < 1) { + RFCOMM_TRACE_ERROR("Illegal MX Frame len:%d < 1 when ea = 0", length); + osi_free(p_buf); + return; + } mx_len += *p_data++ << RFCOMM_SHIFT_LENGTH2; length --; } @@ -847,6 +868,12 @@ void rfc_process_mx_message (tRFC_MCB *p_mcb, BT_HDR *p_buf) return; case RFCOMM_MX_MSC: + if (length != RFCOMM_MX_MSC_LEN_WITH_BREAK && + length != RFCOMM_MX_MSC_LEN_NO_BREAK) { + RFCOMM_TRACE_ERROR("Illegal MX MSC Frame len:%d", length); + osi_free(p_buf); + return; + } ea = *p_data & RFCOMM_EA; cr = (*p_data & RFCOMM_CR_MASK) >> RFCOMM_SHIFT_CR; diff --git a/components/bt/host/bluedroid/stack/sdp/include/sdpint.h b/components/bt/host/bluedroid/stack/sdp/include/sdpint.h index ab97b70276af..ea7f5d14002f 100644 --- a/components/bt/host/bluedroid/stack/sdp/include/sdpint.h +++ b/components/bt/host/bluedroid/stack/sdp/include/sdpint.h @@ -276,7 +276,7 @@ extern void sdpu_build_n_send_error (tCONN_CB *p_ccb, UINT16 trans_num, UIN extern UINT8 *sdpu_extract_attr_seq (UINT8 *p, UINT16 param_len, tSDP_ATTR_SEQ *p_seq); extern UINT8 *sdpu_extract_uid_seq (UINT8 *p, UINT16 param_len, tSDP_UUID_SEQ *p_seq); -extern UINT8 *sdpu_get_len_from_type (UINT8 *p, UINT8 type, UINT32 *p_len); +extern UINT8 *sdpu_get_len_from_type (UINT8 *p, UINT8 *p_end, UINT8 type, UINT32 *p_len); extern BOOLEAN sdpu_is_base_uuid (UINT8 *p_uuid); extern BOOLEAN sdpu_compare_uuid_arrays (UINT8 *p_uuid1, UINT32 len1, UINT8 *p_uuid2, UINT16 len2); extern BOOLEAN sdpu_compare_bt_uuids (tBT_UUID *p_uuid1, tBT_UUID *p_uuid2); diff --git a/components/bt/host/bluedroid/stack/sdp/sdp_db.c b/components/bt/host/bluedroid/stack/sdp/sdp_db.c index 60dd04a6b947..f9f2f738c6ad 100644 --- a/components/bt/host/bluedroid/stack/sdp/sdp_db.c +++ b/components/bt/host/bluedroid/stack/sdp/sdp_db.c @@ -139,7 +139,11 @@ static BOOLEAN find_uuid_in_seq (UINT8 *p , UINT32 seq_len, UINT8 *p_uuid, while (p < p_end) { type = *p++; - p = sdpu_get_len_from_type (p, type, &len); + p = sdpu_get_len_from_type (p, p_end, type, &len); + if ((p == NULL) || (p + len) > p_end) { + SDP_TRACE_WARNING("bad length\n"); + return (FALSE); + } type = type >> 3; if (type == UUID_DESC_TYPE) { if (sdpu_compare_uuid_arrays (p, len, p_uuid, uuid_len)) { diff --git a/components/bt/host/bluedroid/stack/sdp/sdp_discovery.c b/components/bt/host/bluedroid/stack/sdp/sdp_discovery.c index 31ab11f46f76..e1ffdf726121 100644 --- a/components/bt/host/bluedroid/stack/sdp/sdp_discovery.c +++ b/components/bt/host/bluedroid/stack/sdp/sdp_discovery.c @@ -50,7 +50,7 @@ static void process_service_attr_rsp (tCONN_CB *p_ccb, UINT8 *p_reply); static void process_service_search_attr_rsp (tCONN_CB *p_ccb, UINT8 *p_reply); static UINT8 *save_attr_seq (tCONN_CB *p_ccb, UINT8 *p, UINT8 *p_msg_end); static tSDP_DISC_REC *add_record (tSDP_DISCOVERY_DB *p_db, BD_ADDR p_bda); -static UINT8 *add_attr (UINT8 *p, tSDP_DISCOVERY_DB *p_db, tSDP_DISC_REC *p_rec, +static UINT8 *add_attr (UINT8 *p, UINT8 *p_end, tSDP_DISCOVERY_DB *p_db, tSDP_DISC_REC *p_rec, UINT16 attr_id, tSDP_DISC_ATTR *p_parent_attr, UINT8 nest_level); /* Safety check in case we go crazy */ @@ -333,6 +333,7 @@ static void sdp_copy_raw_data (tCONN_CB *p_ccb, BOOLEAN offset) unsigned int cpy_len; UINT32 list_len; UINT8 *p; + UINT8 *p_end; UINT8 type; #if (SDP_DEBUG_RAW == TRUE) @@ -349,10 +350,22 @@ static void sdp_copy_raw_data (tCONN_CB *p_ccb, BOOLEAN offset) cpy_len = p_ccb->p_db->raw_size - p_ccb->p_db->raw_used; list_len = p_ccb->list_len; p = &p_ccb->rsp_list[0]; + p_end = &p_ccb->rsp_list[0] + list_len; if (offset) { type = *p++; - p = sdpu_get_len_from_type (p, type, &list_len); + cpy_len--; + uint8_t *p_old = p; + p = sdpu_get_len_from_type (p, p_end, type, &list_len); + if ((p == NULL) || (p + list_len) > p_end) { + SDP_TRACE_WARNING("bad length\n"); + return; + } + if ((int)cpy_len < (p - p_old)) { + SDP_TRACE_WARNING("no bytes left for data\n"); + return; + } + cpy_len -= (p - p_old); } if (list_len < cpy_len ) { cpy_len = list_len; @@ -672,7 +685,11 @@ static void process_service_search_attr_rsp (tCONN_CB *p_ccb, UINT8 *p_reply) sdp_disconnect (p_ccb, SDP_ILLEGAL_PARAMETER); return; } - p = sdpu_get_len_from_type (p, type, &seq_len); + p = sdpu_get_len_from_type (p, p + p_ccb->list_len, type, &seq_len); + if (p == NULL || (p + seq_len) > (p + p_ccb->list_len)) { + sdp_disconnect(p_ccb, SDP_ILLEGAL_PARAMETER); + return; + } p_end = &p_ccb->rsp_list[p_ccb->list_len]; @@ -717,8 +734,8 @@ static UINT8 *save_attr_seq (tCONN_CB *p_ccb, UINT8 *p, UINT8 *p_msg_end) return (NULL); } - p = sdpu_get_len_from_type (p, type, &seq_len); - if ((p + seq_len) > p_msg_end) { + p = sdpu_get_len_from_type (p, p_msg_end, type, &seq_len); + if ((p == NULL) || (p + seq_len) > p_msg_end) { SDP_TRACE_WARNING ("SDP - Bad len in attr_rsp %d\n", seq_len); return (NULL); } @@ -735,7 +752,11 @@ static UINT8 *save_attr_seq (tCONN_CB *p_ccb, UINT8 *p, UINT8 *p_msg_end) while (p < p_seq_end) { /* First get the attribute ID */ type = *p++; - p = sdpu_get_len_from_type (p, type, &attr_len); + p = sdpu_get_len_from_type (p, p_msg_end, type, &attr_len); + if ((p == NULL) || (p + attr_len) > p_seq_end) { + SDP_TRACE_WARNING ("SDP - Bad len in attr_rsp %d\n", attr_len); + return (NULL); + } if (((type >> 3) != UINT_DESC_TYPE) || (attr_len != 2)) { SDP_TRACE_WARNING ("SDP - Bad type: 0x%02x or len: %d in attr_rsp\n", type, attr_len); return (NULL); @@ -743,7 +764,7 @@ static UINT8 *save_attr_seq (tCONN_CB *p_ccb, UINT8 *p, UINT8 *p_msg_end) BE_STREAM_TO_UINT16 (attr_id, p); /* Now, add the attribute value */ - p = add_attr (p, p_ccb->p_db, p_rec, attr_id, NULL, 0); + p = add_attr (p, p_seq_end, p_ccb->p_db, p_rec, attr_id, NULL, 0); if (!p) { SDP_TRACE_WARNING ("SDP - DB full add_attr\n"); @@ -809,7 +830,7 @@ tSDP_DISC_REC *add_record (tSDP_DISCOVERY_DB *p_db, BD_ADDR p_bda) ** Returns pointer to next byte in data stream ** *******************************************************************************/ -static UINT8 *add_attr (UINT8 *p, tSDP_DISCOVERY_DB *p_db, tSDP_DISC_REC *p_rec, +static UINT8 *add_attr (UINT8 *p, UINT8 *p_end, tSDP_DISCOVERY_DB *p_db, tSDP_DISC_REC *p_rec, UINT16 attr_id, tSDP_DISC_ATTR *p_parent_attr, UINT8 nest_level) { tSDP_DISC_ATTR *p_attr; @@ -818,14 +839,19 @@ static UINT8 *add_attr (UINT8 *p, tSDP_DISCOVERY_DB *p_db, tSDP_DISC_REC *p_rec, UINT16 attr_type; UINT16 id; UINT8 type; - UINT8 *p_end; + UINT8 *p_attr_end; UINT8 is_additional_list = nest_level & SDP_ADDITIONAL_LIST_MASK; nest_level &= ~(SDP_ADDITIONAL_LIST_MASK); type = *p++; - p = sdpu_get_len_from_type (p, type, &attr_len); + p = sdpu_get_len_from_type (p, p_end, type, &attr_len); + if ((p == NULL) || (p + attr_len > p_end)) { + SDP_TRACE_WARNING ("SDP - Bad len in attr_rsp %d\n", attr_len); + return NULL; + } + p_attr_end = p + attr_len; attr_len &= SDP_DISC_ATTR_LEN_MASK; attr_type = (type >> 3) & 0x0f; @@ -860,17 +886,16 @@ static UINT8 *add_attr (UINT8 *p, tSDP_DISCOVERY_DB *p_db, tSDP_DISC_REC *p_rec, /* Reserve the memory for the attribute now, as we need to add sub-attributes */ p_db->p_free_mem += sizeof (tSDP_DISC_ATTR); p_db->mem_free -= sizeof (tSDP_DISC_ATTR); - p_end = p + attr_len; total_len = 0; /* SDP_TRACE_DEBUG ("SDP - attr nest level:%d(list)", nest_level); */ if (nest_level >= MAX_NEST_LEVELS) { SDP_TRACE_ERROR ("SDP - attr nesting too deep\n"); - return (p_end); + return (p_attr_end); } /* Now, add the list entry */ - p = add_attr (p, p_db, p_rec, ATTR_ID_PROTOCOL_DESC_LIST, p_attr, (UINT8)(nest_level + 1)); + p = add_attr (p, p_end, p_db, p_rec, ATTR_ID_PROTOCOL_DESC_LIST, p_attr, (UINT8)(nest_level + 1)); break; } @@ -943,22 +968,21 @@ static UINT8 *add_attr (UINT8 *p, tSDP_DISCOVERY_DB *p_db, tSDP_DISC_REC *p_rec, /* Reserve the memory for the attribute now, as we need to add sub-attributes */ p_db->p_free_mem += sizeof (tSDP_DISC_ATTR); p_db->mem_free -= sizeof (tSDP_DISC_ATTR); - p_end = p + attr_len; total_len = 0; /* SDP_TRACE_DEBUG ("SDP - attr nest level:%d", nest_level); */ if (nest_level >= MAX_NEST_LEVELS) { SDP_TRACE_ERROR ("SDP - attr nesting too deep\n"); - return (p_end); + return (p_attr_end); } if (is_additional_list != 0 || attr_id == ATTR_ID_ADDITION_PROTO_DESC_LISTS) { nest_level |= SDP_ADDITIONAL_LIST_MASK; } /* SDP_TRACE_DEBUG ("SDP - attr nest level:0x%x(finish)", nest_level); */ - while (p < p_end) { + while (p < p_attr_end) { /* Now, add the list entry */ - p = add_attr (p, p_db, p_rec, 0, p_attr, (UINT8)(nest_level + 1)); + p = add_attr (p, p_end, p_db, p_rec, 0, p_attr, (UINT8)(nest_level + 1)); if (!p) { return (NULL); @@ -978,7 +1002,7 @@ static UINT8 *add_attr (UINT8 *p, tSDP_DISCOVERY_DB *p_db, tSDP_DISC_REC *p_rec, break; default: SDP_TRACE_WARNING ("SDP - bad len in boolean attr: %d\n", attr_len); - return (p + attr_len); + return (p_attr_end); } break; diff --git a/components/bt/host/bluedroid/stack/sdp/sdp_server.c b/components/bt/host/bluedroid/stack/sdp/sdp_server.c index 856aba71d4ac..d6f98197d0e4 100644 --- a/components/bt/host/bluedroid/stack/sdp/sdp_server.c +++ b/components/bt/host/bluedroid/stack/sdp/sdp_server.c @@ -355,6 +355,7 @@ static void process_service_attr_req (tCONN_CB *p_ccb, UINT16 trans_num, /* Free and reallocate buffer */ if (p_ccb->rsp_list) { osi_free(p_ccb->rsp_list); + p_ccb->rsp_list = NULL; } p_ccb->rsp_list = (UINT8 *)osi_malloc(max_list_len); @@ -457,7 +458,7 @@ static void process_service_attr_req (tCONN_CB *p_ccb, UINT16 trans_num, } } } - /* If all the attributes have been accomodated in p_rsp, + /* If all the attributes have been accommodated in p_rsp, reset next_attr_index */ if (xx == attr_seq.num_attr) { p_ccb->cont_info.next_attr_index = 0; @@ -590,6 +591,7 @@ static void process_service_search_attr_req (tCONN_CB *p_ccb, UINT16 trans_num, /* Free and reallocate buffer */ if (p_ccb->rsp_list) { osi_free (p_ccb->rsp_list); + p_ccb->rsp_list = NULL; } p_ccb->rsp_list = (UINT8 *)osi_malloc (max_list_len); @@ -623,6 +625,7 @@ static void process_service_search_attr_req (tCONN_CB *p_ccb, UINT16 trans_num, /* Free and reallocate if the earlier allocated buffer is small */ if (p_ccb->rsp_list) { osi_free (p_ccb->rsp_list); + p_ccb->rsp_list = NULL; } p_ccb->rsp_list = (UINT8 *)osi_malloc (max_list_len); diff --git a/components/bt/host/bluedroid/stack/sdp/sdp_utils.c b/components/bt/host/bluedroid/stack/sdp/sdp_utils.c index cd14158d981c..f354ea3ad357 100644 --- a/components/bt/host/bluedroid/stack/sdp/sdp_utils.c +++ b/components/bt/host/bluedroid/stack/sdp/sdp_utils.c @@ -575,7 +575,7 @@ UINT8 *sdpu_extract_attr_seq (UINT8 *p, UINT16 param_len, tSDP_ATTR_SEQ *p_seq) ** Returns void ** *******************************************************************************/ -UINT8 *sdpu_get_len_from_type (UINT8 *p, UINT8 type, UINT32 *p_len) +UINT8 *sdpu_get_len_from_type (UINT8 *p, UINT8 *p_end, UINT8 type, UINT32 *p_len) { UINT8 u8; UINT16 u16; @@ -598,14 +598,26 @@ UINT8 *sdpu_get_len_from_type (UINT8 *p, UINT8 type, UINT32 *p_len) *p_len = 16; break; case SIZE_IN_NEXT_BYTE: + if (p + 1 > p_end) { + *p_len = 0; + return NULL; + } BE_STREAM_TO_UINT8 (u8, p); *p_len = u8; break; case SIZE_IN_NEXT_WORD: + if (p + 2 > p_end) { + *p_len = 0; + return NULL; + } BE_STREAM_TO_UINT16 (u16, p); *p_len = u16; break; case SIZE_IN_NEXT_LONG: + if (p + 4 > p_end) { + *p_len = 0; + return NULL; + } BE_STREAM_TO_UINT32 (u32, p); *p_len = (UINT16) u32; break; @@ -753,7 +765,7 @@ BOOLEAN sdpu_compare_bt_uuids (tBT_UUID *p_uuid1, tBT_UUID *p_uuid2) ** ** NOTE - it is assumed that BT UUID structures are compressed to the ** smallest possible UUIDs (by removing the base SDP UUID). -** - it is also assumed that the discovery atribute is compressed +** - it is also assumed that the discovery attribute is compressed ** to the smallest possible ** ** Returns TRUE if matched, else FALSE @@ -768,9 +780,9 @@ BOOLEAN sdpu_compare_uuid_with_attr (tBT_UUID *p_btuuid, tSDP_DISC_ATTR *p_attr) return (FALSE); } - if (p_btuuid->len == 2) { + if (p_btuuid->len == LEN_UUID_16) { return (BOOLEAN)(p_btuuid->uu.uuid16 == p_attr->attr_value.v.u16); - } else if (p_btuuid->len == 4) { + } else if (p_btuuid->len == LEN_UUID_32) { return (BOOLEAN)(p_btuuid->uu.uuid32 == p_attr->attr_value.v.u32); } /* coverity[overrun-buffer-arg] */ @@ -781,8 +793,8 @@ BOOLEAN sdpu_compare_uuid_with_attr (tBT_UUID *p_btuuid, tSDP_DISC_ATTR *p_attr) The actual size of tSDP_DISC_ATVAL does not matter. If the array size in tSDP_DISC_ATVAL is increase, we would increase the system RAM usage unnecessarily */ - else if (!memcmp (p_btuuid->uu.uuid128, (void *) p_attr->attr_value.v.array, MAX_UUID_SIZE)) { - return (TRUE); + else if (p_btuuid->len == LEN_UUID_128) { + return (BOOLEAN)(!memcmp(p_btuuid->uu.uuid128, (void *) p_attr->attr_value.v.array, LEN_UUID_128)); } return (FALSE); diff --git a/components/bt/host/bluedroid/stack/smp/smp_act.c b/components/bt/host/bluedroid/stack/smp/smp_act.c index 43b2e476530b..a41fbdd1b17b 100644 --- a/components/bt/host/bluedroid/stack/smp/smp_act.c +++ b/components/bt/host/bluedroid/stack/smp/smp_act.c @@ -1013,6 +1013,14 @@ void smp_proc_enc_info(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) UINT8 *p = (UINT8 *)p_data; SMP_TRACE_DEBUG("%s\n", __func__); + + if (smp_command_has_invalid_parameters(p_cb)) { + tSMP_INT_DATA smp_int_data = {0}; + smp_int_data.reason = SMP_INVALID_PARAMETERS; + smp_sm_event(p_cb, SMP_AUTH_CMPL_EVT, &smp_int_data); + return; + } + STREAM_TO_ARRAY(p_cb->ltk, p, BT_OCTET16_LEN); smp_key_distribution(p_cb, NULL); @@ -1030,6 +1038,11 @@ void smp_proc_master_id(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) SMP_TRACE_DEBUG("%s\np_cb->peer_auth_req = %d,p_cb->loc_auth_req= %d\n", __func__, p_cb->peer_auth_req, p_cb->loc_auth_req); + + if (p_cb->rcvd_cmd_len < 11) { // 1(Code) + 2(EDIV) + 8(Rand) + SMP_TRACE_ERROR("Invalid command length: %d, should be at least 11", p_cb->rcvd_cmd_len); + return; + } smp_update_key_mask (p_cb, SMP_SEC_KEY_TYPE_ENC, TRUE); STREAM_TO_UINT16(le_key.ediv, p); @@ -1052,7 +1065,7 @@ void smp_proc_master_id(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) } /******************************************************************************* -** Function smp_proc_enc_info +** Function smp_proc_id_info ** Description process identity information from peer device *******************************************************************************/ void smp_proc_id_info(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) @@ -1060,6 +1073,14 @@ void smp_proc_id_info(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) UINT8 *p = (UINT8 *)p_data; SMP_TRACE_DEBUG("%s", __func__); + + if (smp_command_has_invalid_parameters(p_cb)) { + tSMP_INT_DATA smp_int_data = {0}; + smp_int_data.reason = SMP_INVALID_PARAMETERS; + smp_sm_event(p_cb, SMP_AUTH_CMPL_EVT, &smp_int_data); + return; + } + STREAM_TO_ARRAY (p_cb->tk, p, BT_OCTET16_LEN); /* reuse TK for IRK */ smp_key_distribution_by_transport(p_cb, NULL); } diff --git a/components/bt/host/nimble/Kconfig.in b/components/bt/host/nimble/Kconfig.in index 6697ac3d77a0..fe9b86d83dc6 100644 --- a/components/bt/host/nimble/Kconfig.in +++ b/components/bt/host/nimble/Kconfig.in @@ -1,315 +1,400 @@ +menu "General" + choice BT_NIMBLE_MEM_ALLOC_MODE + prompt "Memory allocation strategy" + default BT_NIMBLE_MEM_ALLOC_MODE_INTERNAL + help + Allocation strategy for NimBLE host stack. Provides ability to + allocate all required dynamic allocations from: + + - Internal DRAM memory only + - External SPIRAM memory only + - Either internal or external memory based on default malloc() + behavior in ESP-IDF + - Internal IRAM memory wherever applicable else internal DRAM + + config BT_NIMBLE_MEM_ALLOC_MODE_INTERNAL + bool "Internal memory" + + config BT_NIMBLE_MEM_ALLOC_MODE_EXTERNAL + bool "External SPIRAM" + depends on SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC + + config BT_NIMBLE_MEM_ALLOC_MODE_DEFAULT + bool "Default alloc mode" + + config BT_NIMBLE_MEM_ALLOC_MODE_IRAM_8BIT + bool "Internal IRAM" + depends on ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY + help + Allows use of IRAM memory region as 8-bit accessible region. -choice BT_NIMBLE_MEM_ALLOC_MODE - prompt "Memory allocation strategy" - default BT_NIMBLE_MEM_ALLOC_MODE_INTERNAL - help - Allocation strategy for NimBLE host stack, essentially provides ability to - allocate all required dynamic allocations from, - - - Internal DRAM memory only - - External SPIRAM memory only - - Either internal or external memory based on default malloc() - behavior in ESP-IDF - - Internal IRAM memory wherever applicable else internal DRAM - - config BT_NIMBLE_MEM_ALLOC_MODE_INTERNAL - bool "Internal memory" - - config BT_NIMBLE_MEM_ALLOC_MODE_EXTERNAL - bool "External SPIRAM" - depends on SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC - - config BT_NIMBLE_MEM_ALLOC_MODE_DEFAULT - bool "Default alloc mode" - - config BT_NIMBLE_MEM_ALLOC_MODE_IRAM_8BIT - bool "Internal IRAM" - depends on ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY - help - Allows to use IRAM memory region as 8bit accessible region. - - Every unaligned (8bit or 16bit) access will result in an exception - and incur penalty of certain clock cycles per unaligned read/write. - -endchoice #BT_NIMBLE_MEM_ALLOC_MODE - -choice BT_NIMBLE_LOG_LEVEL - prompt "NimBLE Host log verbosity" - depends on BT_NIMBLE_ENABLED - default BT_NIMBLE_LOG_LEVEL_INFO - help - Select NimBLE log level. Please make a note that the selected NimBLE log - verbosity can not exceed the level set in "Component config --> Log output - --> Default log verbosity". - - config BT_NIMBLE_LOG_LEVEL_NONE - bool "No logs" - config BT_NIMBLE_LOG_LEVEL_ERROR - bool "Error logs" - config BT_NIMBLE_LOG_LEVEL_WARNING - bool "Warning logs" - config BT_NIMBLE_LOG_LEVEL_INFO - bool "Info logs" - config BT_NIMBLE_LOG_LEVEL_DEBUG - bool "Debug logs" -endchoice #BT_NIMBLE_LOG_LEVEL - -config BT_NIMBLE_LOG_LEVEL - int - default 0 if BT_NIMBLE_LOG_LEVEL_DEBUG - default 1 if BT_NIMBLE_LOG_LEVEL_INFO - default 2 if BT_NIMBLE_LOG_LEVEL_WARNING - default 3 if BT_NIMBLE_LOG_LEVEL_ERROR - default 4 if BT_NIMBLE_LOG_LEVEL_NONE - -config BT_NIMBLE_MAX_CONNECTIONS - int "Maximum number of concurrent connections" - range 1 2 if IDF_TARGET_ESP32C2 - range 1 70 if IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61 - range 1 35 if IDF_TARGET_ESP32H2 - range 1 9 - default 2 if IDF_TARGET_ESP32C2 - default 3 - depends on BT_NIMBLE_ENABLED - help - Defines maximum number of concurrent BLE connections. For ESP32, user - is expected to configure BTDM_CTRL_BLE_MAX_CONN from controller menu - along with this option. Similarly for ESP32-C3 or ESP32-S3, user is expected to - configure BT_CTRL_BLE_MAX_ACT from controller menu. - For ESP32C2, ESP32C6 and ESP32H2, each connection will take about 1k DRAM. - -config BT_NIMBLE_MAX_BONDS - int "Maximum number of bonds to save across reboots" - default 3 - depends on BT_NIMBLE_ENABLED - help - Defines maximum number of bonds to save for peer security and our security - -config BT_NIMBLE_MAX_CCCDS - int "Maximum number of CCC descriptors to save across reboots" - default 8 - depends on BT_NIMBLE_ENABLED - help - Defines maximum number of CCC descriptors to save - -config BT_NIMBLE_L2CAP_COC_MAX_NUM - int "Maximum number of connection oriented channels" - range 0 9 - depends on BT_NIMBLE_ENABLED - default 0 - help - Defines maximum number of BLE Connection Oriented Channels. When set to (0), BLE COC is not compiled in - -config BT_NIMBLE_L2CAP_ENHANCED_COC - bool "L2CAP Enhanced Connection Oriented Channel" - depends on BT_NIMBLE_ENABLED && (BT_NIMBLE_L2CAP_COC_MAX_NUM >= 1) - default 0 - help - Enable Enhanced Credit Based Flow Control Mode - - -choice BT_NIMBLE_PINNED_TO_CORE_CHOICE - prompt "The CPU core on which NimBLE host will run" - depends on BT_NIMBLE_ENABLED && !FREERTOS_UNICORE - help - The CPU core on which NimBLE host will run. You can choose Core 0 or Core 1. - Cannot specify no-affinity - - config BT_NIMBLE_PINNED_TO_CORE_0 - bool "Core 0 (PRO CPU)" - config BT_NIMBLE_PINNED_TO_CORE_1 - bool "Core 1 (APP CPU)" - depends on !FREERTOS_UNICORE -endchoice - -config BT_NIMBLE_PINNED_TO_CORE - int - depends on BT_NIMBLE_ENABLED - default 0 if BT_NIMBLE_PINNED_TO_CORE_0 - default 1 if BT_NIMBLE_PINNED_TO_CORE_1 - default 0 - -config BT_NIMBLE_HOST_TASK_STACK_SIZE - int "NimBLE Host task stack size" - depends on BT_NIMBLE_ENABLED - default 5120 if BLE_MESH - default 4096 - help - This configures stack size of NimBLE host task - -config BT_NIMBLE_ROLE_CENTRAL - bool "Enable BLE Central role" - depends on BT_NIMBLE_ENABLED - default y - help + Every unaligned (8bit or 16bit) access will result in an + exception and incur penalty of certain clock cycles per + unaligned read/write. + + endchoice #BT_NIMBLE_MEM_ALLOC_MODE + + config BT_NIMBLE_PINNED_TO_CORE + int + depends on BT_NIMBLE_ENABLED + default 0 if BT_NIMBLE_PINNED_TO_CORE_0 + default 1 if BT_NIMBLE_PINNED_TO_CORE_1 + default 0 + + choice BT_NIMBLE_PINNED_TO_CORE_CHOICE + prompt "The CPU core on which NimBLE host will run" + depends on BT_NIMBLE_ENABLED && !FREERTOS_UNICORE + help + The CPU core on which NimBLE host will run. You can choose + Core 0 or Core 1. Cannot specify no-affinity + + config BT_NIMBLE_PINNED_TO_CORE_0 + bool "Core 0 (PRO CPU)" + config BT_NIMBLE_PINNED_TO_CORE_1 + bool "Core 1 (APP CPU)" + depends on !FREERTOS_UNICORE + endchoice + + config BT_NIMBLE_HOST_TASK_STACK_SIZE + int "NimBLE Host task stack size" + depends on BT_NIMBLE_ENABLED + default 5120 if BLE_MESH + default 4096 + help + This configures stack size of NimBLE host task + + config BT_NIMBLE_LEGACY_VHCI_ENABLE + bool + default y if (IDF_TARGET_ESP32 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3) + default n + help + This option is used to distinguish whether a previous version + of VHCI is being used + + +endmenu # General + +menu "Roles and Profiles" + config BT_NIMBLE_ROLE_CENTRAL + bool "Enable BLE Central role" + depends on BT_NIMBLE_ENABLED + default y + help Enables central role -config BT_NIMBLE_ROLE_PERIPHERAL - bool "Enable BLE Peripheral role" - depends on BT_NIMBLE_ENABLED - default y - help + config BT_NIMBLE_ROLE_PERIPHERAL + bool "Enable BLE Peripheral role" + depends on BT_NIMBLE_ENABLED + default y + help Enable peripheral role -config BT_NIMBLE_ROLE_BROADCASTER - bool "Enable BLE Broadcaster role" - depends on BT_NIMBLE_ENABLED - default y - help + config BT_NIMBLE_ROLE_BROADCASTER + bool "Enable BLE Broadcaster role" + depends on BT_NIMBLE_ENABLED + default y + help Enables broadcaster role -config BT_NIMBLE_ROLE_OBSERVER - bool "Enable BLE Observer role" - depends on BT_NIMBLE_ENABLED - default y - help + config BT_NIMBLE_ROLE_OBSERVER + bool "Enable BLE Observer role" + depends on BT_NIMBLE_ENABLED + default y + help Enables observer role -config BT_NIMBLE_GATT_CLIENT - bool "Enable BLE GATT Client support" - depends on BT_NIMBLE_ROLE_CENTRAL - default y - help + config BT_NIMBLE_GATT_CLIENT + bool "Enable BLE GATT Client support" + depends on BT_NIMBLE_ROLE_CENTRAL + default y + help Enables support for GATT Client -config BT_NIMBLE_GATT_SERVER - bool "Enable BLE GATT Server support" - depends on BT_NIMBLE_ROLE_PERIPHERAL - default y - help + config BT_NIMBLE_GATT_SERVER + bool "Enable BLE GATT Server support" + depends on BT_NIMBLE_ROLE_PERIPHERAL + default y + help Enables support for GATT Server -config BT_NIMBLE_NVS_PERSIST - bool "Persist the BLE Bonding keys in NVS" - depends on BT_NIMBLE_ENABLED - default n - help - Enable this flag to make bonding persistent across device reboots +endmenu # Roles and profiles -config BT_NIMBLE_SMP_ID_RESET - bool "Reset device identity when all bonding records are deleted" - default n - help - There are tracking risks associated with using a fixed or static IRK. - If enabled this option, NimBLE will assign a new randomly-generated IRK - when all pairing and bonding records are deleted. This would decrease the ability - of a previously paired peer to be used to determine whether a device - with which it previously shared an IRK is within range. - -menuconfig BT_NIMBLE_SECURITY_ENABLE - bool "Enable BLE SM feature" - depends on BT_NIMBLE_ENABLED - default y - help +menu "Security (SMP)" + menuconfig BT_NIMBLE_SECURITY_ENABLE + bool "Enable BLE SM feature" + depends on BT_NIMBLE_ENABLED + default y + help Enable BLE sm feature -config BT_NIMBLE_SM_LEGACY - bool "Security manager legacy pairing" - depends on BT_NIMBLE_SECURITY_ENABLE - default y - help - Enable security manager legacy pairing - -config BT_NIMBLE_SM_SC - bool "Security manager secure connections (4.2)" - depends on BT_NIMBLE_SECURITY_ENABLE - default y - help - Enable security manager secure connections - -config BT_NIMBLE_SM_SC_DEBUG_KEYS - bool "Use predefined public-private key pair" - default n - depends on BT_NIMBLE_SECURITY_ENABLE && BT_NIMBLE_SM_SC - help - If this option is enabled, SM uses predefined DH key pair as described - in Core Specification, Vol. 3, Part H, 2.3.5.6.1. This allows to - decrypt air traffic easily and thus should only be used for debugging. - -config BT_NIMBLE_LL_CFG_FEAT_LE_ENCRYPTION - bool "Enable LE encryption" - depends on BT_NIMBLE_SECURITY_ENABLE && BT_NIMBLE_ENABLED - default y - help + config BT_NIMBLE_SM_LEGACY + bool "Security manager legacy pairing" + depends on BT_NIMBLE_SECURITY_ENABLE + default y + help + Enable security manager legacy pairing + + config BT_NIMBLE_SM_SC + bool "Security manager secure connections (4.2)" + depends on BT_NIMBLE_SECURITY_ENABLE + default y + help + Enable security manager secure connections + + config BT_NIMBLE_SM_SC_DEBUG_KEYS + bool "Use predefined public-private key pair" + default n + depends on BT_NIMBLE_SECURITY_ENABLE && BT_NIMBLE_SM_SC + help + If this option is enabled, SM uses predefined DH key pair as described + in Core Specification, Vol. 3, Part H, 2.3.5.6.1. This allows to + decrypt air traffic easily and thus should only be used for debugging. + + config BT_NIMBLE_LL_CFG_FEAT_LE_ENCRYPTION + bool "Enable LE encryption" + depends on BT_NIMBLE_SECURITY_ENABLE && BT_NIMBLE_ENABLED + default y + help Enable encryption connection -config BT_NIMBLE_SM_LVL - int "Security level" - depends on BT_NIMBLE_SECURITY_ENABLE - default 0 - help - LE Security Mode 1 Levels: - 1. No Security - 2. Unauthenticated pairing with encryption - 3. Authenticated pairing with encryption - 4. Authenticated LE Secure Connections pairing with encryption using a 128-bit strength encryption key. - -config BT_NIMBLE_SM_SC_ONLY - int "Enable Secure Connections Only Mode" - depends on BT_NIMBLE_SECURITY_ENABLE - default 0 - help - Enable Secure Connections Only Mode - -config BT_NIMBLE_PRINT_ERR_NAME - bool "Enable feature to print Error description" - depends on BT_NIMBLE_ENABLED - default y - help - Enable feature to give useful explanation for HCI errors - -config BT_NIMBLE_DEBUG - bool "Enable extra runtime asserts and host debugging" - default n - depends on BT_NIMBLE_ENABLED - help - This enables extra runtime asserts and host debugging - -config BT_NIMBLE_DYNAMIC_SERVICE - bool "Enable dynamic services" - depends on BT_NIMBLE_ENABLED - help - This enables user to add/remove Gatt services at runtime - - -config BT_NIMBLE_SVC_GAP_DEVICE_NAME - string "BLE GAP default device name" - depends on BT_NIMBLE_ENABLED - default "nimble" - help - The Device Name characteristic shall contain the name of the device as an UTF-8 string. - This name can be changed by using API ble_svc_gap_device_name_set() - -config BT_NIMBLE_GAP_DEVICE_NAME_MAX_LEN - int "Maximum length of BLE device name in octets" - depends on BT_NIMBLE_ENABLED - default 31 - help - Device Name characteristic value shall be 0 to 248 octets in length - -config BT_NIMBLE_ATT_PREFERRED_MTU - int "Preferred MTU size in octets" - depends on BT_NIMBLE_ENABLED - default 256 - help - This is the default value of ATT MTU indicated by the device during an ATT MTU exchange. - This value can be changed using API ble_att_set_preferred_mtu() - -config BT_NIMBLE_ATT_MAX_PREP_ENTRIES - int "Max Prepare write entries" - depends on BT_NIMBLE_ENABLED - default 64 - help - This is the default value of ATT Maximum prepare entries - -config BT_NIMBLE_SVC_GAP_APPEARANCE - hex "External appearance of the device" - depends on BT_NIMBLE_ENABLED - default 0 - help - Standard BLE GAP Appearance value in HEX format e.g. 0x02C0 + config BT_NIMBLE_SM_LVL + int "Security level" + depends on BT_NIMBLE_SECURITY_ENABLE + default 0 + help + LE Security Mode 1 Levels: + 1. No Security + 2. Unauthenticated pairing with encryption + 3. Authenticated pairing with encryption + 4. Authenticated LE Secure Connections pairing with encryption using a 128-bit strength encryption key. + + config BT_NIMBLE_SM_SC_ONLY + int "Enable Secure Connections Only Mode" + depends on BT_NIMBLE_SECURITY_ENABLE + default 0 + help + Enable Secure Connections Only Mode + +endmenu #SMP + +menu "GAP / GATT / Device Settings" + config BT_NIMBLE_RPA_TIMEOUT + int "RPA timeout in seconds" + range 1 41400 + depends on BT_NIMBLE_ENABLED + default 900 + help + Time interval between RPA address change. + + config BT_NIMBLE_WHITELIST_SIZE + int "BLE white list size" + depends on BT_NIMBLE_ENABLED + range 1 31 if SOC_ESP_NIMBLE_CONTROLLER + range 1 15 + default 12 + help + BLE list size + + config BT_NIMBLE_ENABLE_CONN_REATTEMPT + bool "Enable connection reattempts on connection establishment error" + default y if (IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || SOC_ESP_NIMBLE_CONTROLLER) + default n if IDF_TARGET_ESP32 + help + Enable to make the NimBLE host to reattempt GAP connection on connection + establishment failure. + + config BT_NIMBLE_MAX_CONN_REATTEMPT + int "Maximum number connection reattempts" + range 1 255 + default 3 + depends on BT_NIMBLE_ENABLED && BT_NIMBLE_ENABLE_CONN_REATTEMPT + help + Defines maximum number of connection reattempts. + + config BT_NIMBLE_HANDLE_REPEAT_PAIRING_DELETION + bool "Enable stack handling of repeat pairing" + default n + depends on BT_NIMBLE_ENABLED + help + Use this option to let stack internally handle the request for repeat pairing. + Enabling this option will delete the pairing of the device and stack will NOT post any event + to application. If this option is disabled, application will get BLE_GAP_EVENT_REPEAT_PAIRING + event. + + config BT_NIMBLE_HOST_BASED_PRIVACY + bool "Enable host based privacy for random address." + default n + depends on BT_NIMBLE_ENABLED && IDF_TARGET_ESP32 + help + Use this option to do host based Random Private Address resolution. + If this option is disabled then controller based privacy is used. + + config BT_NIMBLE_HOST_ALLOW_CONNECT_WITH_SCAN + bool "Allow Connections with scanning in progress" + depends on BT_NIMBLE_ENABLED && !(IDF_TARGET_ESP32C2) + help + This enables support for user to initiate a new connection with scan in progress + + config BT_NIMBLE_HOST_QUEUE_CONG_CHECK + bool "BLE queue congestion check" + depends on BT_NIMBLE_ENABLED + default n + help + When scanning and scan duplicate is not enabled, if there are a lot of adv packets around + or application layer handling adv packets is slow, it will cause the controller memory + to run out. if enabled, adv packets will be lost when host queue is congested. + + config BT_NIMBLE_MAX_CONNECTIONS + int "Maximum number of concurrent connections" + range 1 2 if IDF_TARGET_ESP32C2 + range 1 70 if IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61 + range 1 35 if IDF_TARGET_ESP32H2 + range 1 9 + default 2 if IDF_TARGET_ESP32C2 + default 3 + depends on BT_NIMBLE_ENABLED + help + Defines maximum number of concurrent BLE connections. For ESP32, user + is expected to configure BTDM_CTRL_BLE_MAX_CONN from controller menu + along with this option. Similarly for ESP32-C3 or ESP32-S3, user is expected to + configure BT_CTRL_BLE_MAX_ACT from controller menu. + For ESP32C2, ESP32C6 and ESP32H2, each connection will take about 1k DRAM. + + config BT_NIMBLE_MAX_BONDS + int "Maximum number of bonds to save across reboots" + default 3 + depends on BT_NIMBLE_ENABLED + help + Defines maximum number of bonds to save for peer security and our security + + config BT_NIMBLE_MAX_CCCDS + int "Maximum number of CCC descriptors to save across reboots" + default 8 + depends on BT_NIMBLE_ENABLED + help + Defines maximum number of CCC descriptors to save + config BT_NIMBLE_NVS_PERSIST + bool "Persist the BLE Bonding keys in NVS" + depends on BT_NIMBLE_ENABLED + default n + help + Enable this flag to make bonding persistent across device reboots + + config BT_NIMBLE_SMP_ID_RESET + bool "Reset device identity when all bonding records are deleted" + default n + help + There are tracking risks associated with using a fixed or static IRK. + If enabled this option, NimBLE will assign a new randomly-generated IRK + when all pairing and bonding records are deleted. This would decrease the ability + of a previously paired peer to be used to determine whether a device + with which it previously shared an IRK is within range. + + config BT_NIMBLE_ATT_PREFERRED_MTU + int "Preferred MTU size in octets" + depends on BT_NIMBLE_ENABLED + default 256 + help + This is the default value of ATT MTU indicated by the device during an ATT MTU exchange. + This value can be changed using API ble_att_set_preferred_mtu() + + config BT_NIMBLE_ATT_MAX_PREP_ENTRIES + int "Max Prepare write entries" + depends on BT_NIMBLE_ENABLED + default 64 + help + This is the default value of ATT Maximum prepare entries + + config BT_NIMBLE_GATT_MAX_PROCS + int "Maximum number of GATT client procedures" + depends on BT_NIMBLE_ENABLED + default 4 + help + Maximum number of GATT client procedures that can be executed. + + config BT_NIMBLE_CRYPTO_STACK_MBEDTLS + bool "Override TinyCrypt with mbedTLS for crypto computations" + default y + depends on BT_NIMBLE_ENABLED + select MBEDTLS_CMAC_C + help + Enable this option to choose mbedTLS instead of TinyCrypt for crypto + computations. + + config BT_NIMBLE_HS_STOP_TIMEOUT_MS + int "BLE host stop timeout in msec" + default 2000 + depends on BT_NIMBLE_ENABLED + help + BLE Host stop procedure timeout in milliseconds. + + + config BT_NIMBLE_USE_ESP_TIMER + bool "Enable Esp Timer for Nimble" + default y + help + Set this option to use Esp Timer which has higher priority timer instead of FreeRTOS timer + + config BT_NIMBLE_BLE_GATT_BLOB_TRANSFER + bool "Blob transfer" + help + This option is used when data to be sent is more than 512 bytes. For peripheral role, + BT_NIMBLE_MSYS_1_BLOCK_COUNT needs to be increased according to the need. + + config BT_NIMBLE_HS_FLOW_CTRL + bool "Enable Host Flow control" + depends on BT_NIMBLE_ENABLED && !SOC_ESP_NIMBLE_CONTROLLER + default y if IDF_TARGET_ESP32 + default n + help + Enable Host Flow control + + config BT_NIMBLE_HS_FLOW_CTRL_ITVL + int "Host Flow control interval" + depends on BT_NIMBLE_HS_FLOW_CTRL + default 1000 + help + Host flow control interval in msecs + + config BT_NIMBLE_HS_FLOW_CTRL_THRESH + int "Host Flow control threshold" + depends on BT_NIMBLE_HS_FLOW_CTRL + default 2 + help + Host flow control threshold, if the number of free buffers are at or + below this threshold, send an immediate number-of-completed-packets + event + + config BT_NIMBLE_HS_FLOW_CTRL_TX_ON_DISCONNECT + bool "Host Flow control on disconnect" + depends on BT_NIMBLE_HS_FLOW_CTRL + default y + help + Enable this option to send number-of-completed-packets event to + controller after disconnection + +endmenu #GAP + +menu "L2CAP" + config BT_NIMBLE_L2CAP_COC_MAX_NUM + int "Maximum number of connection oriented channels" + range 0 9 + depends on BT_NIMBLE_ENABLED + default 0 + help + Defines maximum number of BLE Connection Oriented Channels. When set to (0), BLE COC is not compiled in + + config BT_NIMBLE_L2CAP_ENHANCED_COC + bool "L2CAP Enhanced Connection Oriented Channel" + depends on BT_NIMBLE_ENABLED && (BT_NIMBLE_L2CAP_COC_MAX_NUM >= 1) + default 0 + help + Enable Enhanced Credit Based Flow Control Mode + +endmenu #L2CAP + menu "Memory Settings" config BT_NIMBLE_MSYS_1_BLOCK_COUNT int "MSYS_1 Block Count" @@ -326,19 +411,19 @@ menu "Memory Settings" default 128 if SOC_ESP_NIMBLE_CONTROLLER default 256 if !SOC_ESP_NIMBLE_CONTROLLER help - Dynamic memory size of block 1 + Dynamic memory size of block 1 config BT_NIMBLE_MSYS_2_BLOCK_COUNT int "MSYS_2 Block Count" default 24 help - Dynamic memory count + Dynamic memory count config BT_NIMBLE_MSYS_2_BLOCK_SIZE int "MSYS_2 Block Size" default 320 help - Dynamic memory size of block 2 + Dynamic memory size of block 2 config BT_NIMBLE_MSYS_BUF_FROM_HEAP bool "Get Msys Mbuf from heap" @@ -400,527 +485,251 @@ menu "Memory Settings" default 1 help This is the service data unit buffer count for l2cap coc. +endmenu #Memory -endmenu - -config BT_NIMBLE_GATT_MAX_PROCS - int "Maximum number of GATT client procedures" - depends on BT_NIMBLE_ENABLED - default 4 - help - Maximum number of GATT client procedures that can be executed. - -config BT_NIMBLE_HS_FLOW_CTRL - bool "Enable Host Flow control" - depends on BT_NIMBLE_ENABLED && !SOC_ESP_NIMBLE_CONTROLLER - default y if IDF_TARGET_ESP32 - default n - help - Enable Host Flow control - -config BT_NIMBLE_HS_FLOW_CTRL_ITVL - int "Host Flow control interval" - depends on BT_NIMBLE_HS_FLOW_CTRL - default 1000 - help - Host flow control interval in msecs - -config BT_NIMBLE_HS_FLOW_CTRL_THRESH - int "Host Flow control threshold" - depends on BT_NIMBLE_HS_FLOW_CTRL - default 2 - help - Host flow control threshold, if the number of free buffers are at or - below this threshold, send an immediate number-of-completed-packets - event - -config BT_NIMBLE_HS_FLOW_CTRL_TX_ON_DISCONNECT - bool "Host Flow control on disconnect" - depends on BT_NIMBLE_HS_FLOW_CTRL - default y - help - Enable this option to send number-of-completed-packets event to - controller after disconnection - -config BT_NIMBLE_RPA_TIMEOUT - int "RPA timeout in seconds" - range 1 41400 - depends on BT_NIMBLE_ENABLED - default 900 - help - Time interval between RPA address change. - -menuconfig BT_NIMBLE_MESH - bool "Enable BLE mesh functionality" - select BT_NIMBLE_SM_SC - depends on BT_NIMBLE_ENABLED - default n - help - Enable BLE Mesh example present in upstream mynewt-nimble and not maintained by Espressif. - - IDF maintains ESP-BLE-MESH as the official Mesh solution. Please refer to ESP-BLE-MESH guide at: - `https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/esp-ble-mesh/ble-mesh-index.html` - -config BT_NIMBLE_MESH_PROXY - bool "Enable mesh proxy functionality" - default n - depends on BT_NIMBLE_MESH - help - Enable proxy. This is automatically set whenever NIMBLE_MESH_PB_GATT or - NIMBLE_MESH_GATT_PROXY is set - - -config BT_NIMBLE_MESH_PROV - bool "Enable BLE mesh provisioning" - default y - depends on BT_NIMBLE_MESH - help - Enable mesh provisioning - -config BT_NIMBLE_MESH_PB_ADV - bool "Enable mesh provisioning over advertising bearer" - default y - depends on BT_NIMBLE_MESH_PROV - help - Enable this option to allow the device to be provisioned over - the advertising bearer - - -config BT_NIMBLE_MESH_PB_GATT - bool "Enable mesh provisioning over GATT bearer" - default y - select BT_NIMBLE_MESH_PROXY - depends on BT_NIMBLE_MESH_PROV - help - Enable this option to allow the device to be provisioned over the GATT - bearer - -config BT_NIMBLE_MESH_GATT_PROXY - bool "Enable GATT Proxy functionality" - default y - select BT_NIMBLE_MESH_PROXY - depends on BT_NIMBLE_MESH - help - This option enables support for the Mesh GATT Proxy Service, - i.e. the ability to act as a proxy between a Mesh GATT Client - and a Mesh network - -config BT_NIMBLE_MESH_RELAY - bool "Enable mesh relay functionality" - default n - depends on BT_NIMBLE_MESH - help - Support for acting as a Mesh Relay Node - -config BT_NIMBLE_MESH_LOW_POWER - bool "Enable mesh low power mode" - default n - depends on BT_NIMBLE_MESH - help - Enable this option to be able to act as a Low Power Node - -config BT_NIMBLE_MESH_FRIEND - bool "Enable mesh friend functionality" - default n - depends on BT_NIMBLE_MESH - help - Enable this option to be able to act as a Friend Node - -config BT_NIMBLE_MESH_DEVICE_NAME - string "Set mesh device name" - default "nimble-mesh-node" - depends on BT_NIMBLE_MESH - help - This value defines Bluetooth Mesh device/node name - -config BT_NIMBLE_MESH_NODE_COUNT - int "Set mesh node count" - default 1 - depends on BT_NIMBLE_MESH - help - Defines mesh node count. - -config BT_NIMBLE_MESH_PROVISIONER - bool "Enable BLE mesh provisioner" - default 0 - depends on BT_NIMBLE_MESH - help - Enable mesh provisioner. - -config BT_NIMBLE_CRYPTO_STACK_MBEDTLS - bool "Override TinyCrypt with mbedTLS for crypto computations" - default y - depends on BT_NIMBLE_ENABLED - select MBEDTLS_CMAC_C - help - Enable this option to choose mbedTLS instead of TinyCrypt for crypto - computations. - -config BT_NIMBLE_HS_STOP_TIMEOUT_MS - int "BLE host stop timeout in msec" - default 2000 - depends on BT_NIMBLE_ENABLED - help - BLE Host stop procedure timeout in milliseconds. - -config BT_NIMBLE_HOST_BASED_PRIVACY - bool "Enable host based privacy for random address." - default n - depends on BT_NIMBLE_ENABLED && IDF_TARGET_ESP32 - help - Use this option to do host based Random Private Address resolution. - If this option is disabled then controller based privacy is used. - -config BT_NIMBLE_ENABLE_CONN_REATTEMPT - bool "Enable connection reattempts on connection establishment error" - default y if (IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || SOC_ESP_NIMBLE_CONTROLLER) - default n if IDF_TARGET_ESP32 - help - Enable to make the NimBLE host to reattempt GAP connection on connection - establishment failure. - -config BT_NIMBLE_MAX_CONN_REATTEMPT - int "Maximum number connection reattempts" - range 1 255 - default 3 - depends on BT_NIMBLE_ENABLED && BT_NIMBLE_ENABLE_CONN_REATTEMPT - help - Defines maximum number of connection reattempts. - -config BT_NIMBLE_HANDLE_REPEAT_PAIRING_DELETION - bool "Enable stack handling of repeat pairing" - default n - depends on BT_NIMBLE_ENABLED - help - Use this option to let stack internally handle the request for repeat pairing. - Enabling this option will delete the pairing of the device and stack will NOT post any event - to application. If this option is disabled, application will get BLE_GAP_EVENT_REPEAT_PAIRING - event. - -menuconfig BT_NIMBLE_50_FEATURE_SUPPORT - bool "Enable BLE 5 feature" - depends on BT_NIMBLE_ENABLED && (SOC_BLE_50_SUPPORTED || !BT_CONTROLLER_ENABLED) - default y - help - Enable BLE 5 feature - -if BT_NIMBLE_50_FEATURE_SUPPORT - config BT_NIMBLE_LL_CFG_FEAT_LE_2M_PHY - bool "Enable 2M Phy" - depends on BT_NIMBLE_50_FEATURE_SUPPORT +menu "BLE 5.x Features" + menuconfig BT_NIMBLE_50_FEATURE_SUPPORT + bool "Enable BLE 5 feature" + depends on BT_NIMBLE_ENABLED && (SOC_BLE_50_SUPPORTED || !BT_CONTROLLER_ENABLED) default y help + Enable BLE 5 feature + + if BT_NIMBLE_50_FEATURE_SUPPORT + config BT_NIMBLE_LL_CFG_FEAT_LE_2M_PHY + bool "Enable 2M Phy" + depends on BT_NIMBLE_50_FEATURE_SUPPORT + default y + help Enable 2M-PHY - config BT_NIMBLE_LL_CFG_FEAT_LE_CODED_PHY - bool "Enable coded Phy" - depends on BT_NIMBLE_50_FEATURE_SUPPORT - default y - help + config BT_NIMBLE_LL_CFG_FEAT_LE_CODED_PHY + bool "Enable coded Phy" + depends on BT_NIMBLE_50_FEATURE_SUPPORT + default y + help Enable coded-PHY - config BT_NIMBLE_EXT_ADV - bool "Enable extended advertising" - depends on BT_NIMBLE_50_FEATURE_SUPPORT - default n - help - Enable this option to do extended advertising. Extended advertising - will be supported from BLE 5.0 onwards. - - if BT_NIMBLE_EXT_ADV - config BT_NIMBLE_EXT_ADV_V2 - bool "Enable support for extended adv v2" + config BT_NIMBLE_EXT_ADV + bool "Enable extended advertising" + depends on BT_NIMBLE_50_FEATURE_SUPPORT default n - depends on BT_NIMBLE_EXT_ADV help - Enable this option to use Extended Adv V2 command instead of V1. + Enable this option to do extended advertising. Extended advertising + will be supported from BLE 5.0 onwards. + + if BT_NIMBLE_EXT_ADV + config BT_NIMBLE_EXT_ADV_V2 + bool "Enable support for extended adv v2" + default n + depends on BT_NIMBLE_EXT_ADV + help + Enable this option to use Extended Adv V2 command instead of V1. + + config BT_NIMBLE_MAX_EXT_ADV_INSTANCES + int "Maximum number of extended advertising instances." + range 0 4 + default 1 if BT_NIMBLE_EXT_ADV + default 0 + depends on BT_NIMBLE_EXT_ADV + help + Change this option to set maximum number of extended advertising + instances. Minimum there is always one instance of + advertising. Enter how many more advertising instances you + want. + For ESP32C2, ESP32C6 and ESP32H2, each extended advertising instance + will take about 0.5k DRAM. + + config BT_NIMBLE_EXT_ADV_MAX_SIZE + int "Maximum length of the advertising data." + range 0 1650 + default 1650 if BT_NIMBLE_EXT_ADV + default 0 + depends on BT_NIMBLE_EXT_ADV + help + Defines the length of the extended adv data. The value should not + exceed 1650. - config BT_NIMBLE_MAX_EXT_ADV_INSTANCES - int "Maximum number of extended advertising instances." - range 0 4 - default 1 if BT_NIMBLE_EXT_ADV - default 0 - depends on BT_NIMBLE_EXT_ADV - help - Change this option to set maximum number of extended advertising - instances. Minimum there is always one instance of - advertising. Enter how many more advertising instances you - want. - For ESP32C2, ESP32C6 and ESP32H2, each extended advertising instance - will take about 0.5k DRAM. - - config BT_NIMBLE_EXT_ADV_MAX_SIZE - int "Maximum length of the advertising data." - range 0 1650 - default 1650 if BT_NIMBLE_EXT_ADV - default 0 - depends on BT_NIMBLE_EXT_ADV - help - Defines the length of the extended adv data. The value should not - exceed 1650. + config BT_NIMBLE_ENABLE_PERIODIC_ADV + bool "Enable periodic advertisement." + default y + depends on BT_NIMBLE_EXT_ADV + help + Enable this option to start periodic advertisement. - config BT_NIMBLE_ENABLE_PERIODIC_ADV - bool "Enable periodic advertisement." - default y - depends on BT_NIMBLE_EXT_ADV - help - Enable this option to start periodic advertisement. + config BT_NIMBLE_PERIODIC_ADV_ENH + bool "Periodic adv enhancements(adi support)" + depends on BT_NIMBLE_ENABLE_PERIODIC_ADV + depends on (!BT_CONTROLLER_ENABLED || SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED) + help + Enable the periodic advertising enhancements - config BT_NIMBLE_PERIODIC_ADV_ENH - bool "Periodic adv enhancements(adi support)" - depends on BT_NIMBLE_ENABLE_PERIODIC_ADV && SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED - help - Enable the periodic advertising enhancements + config BT_NIMBLE_PERIODIC_ADV_SYNC_TRANSFER + bool "Enable Transfer Sync Events" + depends on BT_NIMBLE_ENABLE_PERIODIC_ADV + default y + help + This enables controller transfer periodic sync events to host + + config BT_NIMBLE_PERIODIC_ADV_WITH_RESPONSES + bool "Enable Periodic Advertisement with Response (EXPERIMENTAL)" + depends on BT_NIMBLE_ENABLE_PERIODIC_ADV + default n + help + This enables controller PAwR (Periodic Advertisement with Response). + endif - config BT_NIMBLE_PERIODIC_ADV_SYNC_TRANSFER - bool "Enable Transfer Sync Events" - depends on BT_NIMBLE_ENABLE_PERIODIC_ADV + config BT_NIMBLE_EXT_SCAN + bool "Enable extended scanning" + depends on BT_NIMBLE_50_FEATURE_SUPPORT default y help - This enables controller transfer periodic sync events to host + Enable this option to do extended scanning. - config BT_NIMBLE_PERIODIC_ADV_WITH_RESPONSES - bool "Enable Periodic Advertisement with Response (EXPERIMENTAL)" - depends on BT_NIMBLE_ENABLE_PERIODIC_ADV + config BT_NIMBLE_ENABLE_PERIODIC_SYNC + bool "Enable periodic sync" + default y + depends on BT_NIMBLE_EXT_SCAN help - This enables controller PAwR (Periodic Advertisement with Response). - endif - - config BT_NIMBLE_EXT_SCAN - bool "Enable extended scanning" - depends on BT_NIMBLE_50_FEATURE_SUPPORT && BT_NIMBLE_ROLE_OBSERVER - default y - help - Enable this option to do extended scanning. - - config BT_NIMBLE_ENABLE_PERIODIC_SYNC - bool "Enable periodic sync" - default y - depends on BT_NIMBLE_EXT_SCAN - help - Enable this option to receive periodic advertisement. + Enable this option to receive periodic advertisement. + + if BT_NIMBLE_ENABLE_PERIODIC_SYNC + config BT_NIMBLE_MAX_PERIODIC_SYNCS + int "Maximum number of periodic advertising syncs" + range 0 3 if IDF_TARGET_ESP32C2 + range 0 8 + default 1 if BT_NIMBLE_ENABLE_PERIODIC_ADV + default 0 + help + Set this option to set the upper limit for number of periodic sync + connections. This should be less than maximum connections allowed by + controller. + + config BT_NIMBLE_MAX_PERIODIC_ADVERTISER_LIST + int "Maximum number of periodic advertiser list" + depends on SOC_ESP_NIMBLE_CONTROLLER + range 1 5 + default 5 if BT_NIMBLE_50_FEATURE_SUPPORT + help + Set this option to set the upper limit for number of periodic advertiser list. + endif - if BT_NIMBLE_ENABLE_PERIODIC_SYNC - config BT_NIMBLE_MAX_PERIODIC_SYNCS - int "Maximum number of periodic advertising syncs" - range 0 3 if IDF_TARGET_ESP32C2 - range 0 8 - default 1 if BT_NIMBLE_ENABLE_PERIODIC_ADV - default 0 - help - Set this option to set the upper limit for number of periodic sync - connections. This should be less than maximum connections allowed by - controller. - - config BT_NIMBLE_MAX_PERIODIC_ADVERTISER_LIST - int "Maximum number of periodic advertiser list" - depends on SOC_ESP_NIMBLE_CONTROLLER - range 1 5 - default 5 if BT_NIMBLE_50_FEATURE_SUPPORT + config BT_NIMBLE_BLE_POWER_CONTROL + bool "Enable support for BLE Power Control" + depends on BT_NIMBLE_50_FEATURE_SUPPORT && (!BT_CONTROLLER_ENABLED || SOC_BLE_POWER_CONTROL_SUPPORTED) + default n help - Set this option to set the upper limit for number of periodic advertiser list. - endif + Set this option to enable the Power Control feature - config BT_NIMBLE_BLE_POWER_CONTROL - bool "Enable support for BLE Power Control" - depends on BT_NIMBLE_50_FEATURE_SUPPORT && SOC_BLE_POWER_CONTROL_SUPPORTED - default n - help - Set this option to enable the Power Control feature + config BT_NIMBLE_AOA_AOD + bool "Direction Finding" + depends on BT_NIMBLE_50_FEATURE_SUPPORT && (!BT_CONTROLLER_ENABLED || SOC_BLE_CTE_SUPPORTED) + default n + help + Enable support for Connectionless and Connection Oriented Direction Finding - config BT_NIMBLE_AOA_AOD - bool "Direction Finding" - depends on BT_NIMBLE_50_FEATURE_SUPPORT && (BT_CONTROLLER_DISABLED || SOC_BLE_CTE_SUPPORTED) - default n - help - Enable support for Connectionless and Connection Oriented Direction Finding + config BT_NIMBLE_ISO + bool "Isochronous channels" + depends on BT_NIMBLE_50_FEATURE_SUPPORT + help + Enable BLE Isochronous functionality. - config BT_NIMBLE_ISO - bool "Isochronous channels" - depends on BT_NIMBLE_50_FEATURE_SUPPORT - help - Enable BLE Isochronous functionality. + if BT_NIMBLE_ISO + choice BT_NIMBLE_ISO_FLOW_CONTROL + prompt "ISO flow control mode" + default BT_NIMBLE_ISO_NON_STD_FLOW_CTRL + help + ISO flow control mode + + config BT_NIMBLE_ISO_STD_FLOW_CTRL + bool "Standard" + help + ISO standard flow control + + config BT_NIMBLE_ISO_NON_STD_FLOW_CTRL + bool "Non-standard" + help + ISO non-standard flow control + endchoice + + config BT_NIMBLE_ISO_TEST + bool "ISO Test mode" + default y + help + Enable BLE Isochronous Test functionality. - if BT_NIMBLE_ISO - choice BT_NIMBLE_ISO_FLOW_CONTROL - prompt "ISO flow control mode" - default BT_NIMBLE_ISO_NON_STD_FLOW_CTRL - help - ISO flow control mode + config BT_NIMBLE_ISO_BIG + int "Maximum number of BIG" + range 1 2 + default 1 + help + Maximum number of BIG. - config BT_NIMBLE_ISO_STD_FLOW_CTRL - bool "Standard" + config BT_NIMBLE_ISO_BIS + int "Maximum number of BIS" + range 1 3 + default 2 help - ISO standard flow control + Maximum number of BIS. - config BT_NIMBLE_ISO_NON_STD_FLOW_CTRL - bool "Non-standard" + config BT_NIMBLE_ISO_BIS_PER_BIG + int "Maximum number of BIS per BIG" + range 1 3 + default 2 help - ISO non-standard flow control - endchoice + Maximum number of BIS per BIG. - config BT_NIMBLE_ISO_TEST - bool "ISO Test mode" - default y - help - Enable BLE Isochronous Test functionality. + config BT_NIMBLE_ISO_CIG + int "Maximum number of CIG" + range 1 2 + default 1 + help + Maximum number of CIG. - config BT_NIMBLE_ISO_BIG - int "Maximum number of BIG" - range 1 2 - default 1 - help - Maximum number of BIG. + config BT_NIMBLE_ISO_CIS + int "Maximum number of CIS" + range 1 3 + default 2 + help + Maximum number of CIS. - config BT_NIMBLE_ISO_BIS - int "Maximum number of BIS" - range 1 3 - default 2 - help - Maximum number of BIS. + config BT_NIMBLE_ISO_CIS_PER_CIG + int "Maximum number of CIS per CIG" + range 1 3 + default 2 + help + Maximum number of CIS per CIG. - config BT_NIMBLE_ISO_BIS_PER_BIG - int "Maximum number of BIS per BIG" - range 1 3 - default 2 - help - Maximum number of BIS per BIG. + config BT_NIMBLE_ISO_CIS_ESTAB_V2 + bool "LE CIS Established event [v2]" + help + Enable this to support LE CIS Established event [v2]. + endif + endif +endmenu #BLE5.x - config BT_NIMBLE_ISO_CIG - int "Maximum number of CIG" - range 1 2 - default 1 - help - Maximum number of CIG. +menu "BLE 6.x Features" + depends on (SOC_BLE_60_SUPPORTED || BT_CONTROLLER_DISABLED) - config BT_NIMBLE_ISO_CIS - int "Maximum number of CIS" - range 1 3 - default 2 - help - Maximum number of CIS. + menuconfig BT_NIMBLE_60_FEATURE_SUPPORT + bool "Enable BLE 6 feature" + depends on BT_NIMBLE_ENABLED && (SOC_BLE_60_SUPPORTED || BT_CONTROLLER_DISABLED) + default n + help + Enable BLE 6 feature - config BT_NIMBLE_ISO_CIS_PER_CIG - int "Maximum number of CIS per CIG" - range 1 3 - default 2 + if BT_NIMBLE_60_FEATURE_SUPPORT + config BT_NIMBLE_CHANNEL_SOUNDING + bool "ble channel souding feature" + depends on BT_NIMBLE_ENABLED + default n help - Maximum number of CIS per CIG. + Used to enable/disable the channel sounding feature - config BT_NIMBLE_ISO_CIS_ESTAB_V2 - bool "LE CIS Established event [v2]" - help - Enable this to support LE CIS Established event [v2]. endif -endif - -menuconfig BT_NIMBLE_GATT_CACHING - bool "Enable GATT caching" - depends on BT_NIMBLE_ENABLED - select BT_NIMBLE_DYNAMIC_SERVICE - help - Enable GATT caching -config BT_NIMBLE_GATT_CACHING_INCLUDE_SERVICES - bool "Include services in GATT caching" - depends on BT_NIMBLE_GATT_CACHING - default n - help - Enable this option to include *included services* (e.g., services referenced by other services) - in the GATT database cache. Disabling this will skip caching of included service entries. -config BT_NIMBLE_INCL_SVC_DISCOVERY - bool - default y if BT_NIMBLE_GATT_CACHING && BT_NIMBLE_GATT_CACHING_INCLUDE_SERVICES - default n if BT_NIMBLE_GATT_CACHING && !BT_NIMBLE_GATT_CACHING_INCLUDE_SERVICES - default n if !BT_NIMBLE_GATT_CACHING - prompt "Enable Included service discovery" if !BT_NIMBLE_GATT_CACHING - help - Enable this option to start discovery for included service. -config BT_NIMBLE_GATT_CACHING_MAX_CONNS - int "Maximum connections to be cached" - depends on BT_NIMBLE_GATT_CACHING - default BT_NIMBLE_MAX_CONNECTIONS - help - Set this option to set the upper limit on number of connections to be cached. -config BT_NIMBLE_GATT_CACHING_MAX_SVCS - int "Maximum number of services per connection" - depends on BT_NIMBLE_GATT_CACHING - default 64 - help - Set this option to set the upper limit on number of services per connection to be cached. -config BT_NIMBLE_GATT_CACHING_MAX_INCL_SVCS - int "Maximum number of included services per connection" - depends on BT_NIMBLE_GATT_CACHING - default 64 - help - Set this option to set the upper limit on number of included services per connection to be cached. -config BT_NIMBLE_GATT_CACHING_MAX_CHRS - int "Maximum number of characteristics per connection" - depends on BT_NIMBLE_GATT_CACHING - default 64 - help - Set this option to set the upper limit on number of characteristics per connection to be cached. -config BT_NIMBLE_GATT_CACHING_MAX_DSCS - int "Maximum number of descriptors per connection" - depends on BT_NIMBLE_GATT_CACHING - default 64 - help - Set this option to set the upper limit on number of descriptors per connection to be cached. -config BT_NIMBLE_GATT_CACHING_DISABLE_AUTO - bool "Do not start discovery procedure automatically upon receiving Out of Sync" - depends on BT_NIMBLE_GATT_CACHING - default n - help - When client receives ATT out-of-sync error message, it will not automatically start the discovery procedure - to correct the invalid cache. -config BT_NIMBLE_GATT_CACHING_ASSOC_ENABLE - bool "Enable association-based GATT caching" - depends on BT_NIMBLE_GATT_CACHING - default n - help - Enable this option to use associated address caching instead of performing service discovery. - -config BT_NIMBLE_WHITELIST_SIZE - int "BLE white list size" - depends on BT_NIMBLE_ENABLED - range 1 31 if SOC_ESP_NIMBLE_CONTROLLER - range 1 15 - default 12 - help - BLE list size - -config BT_NIMBLE_TEST_THROUGHPUT_TEST - bool "Throughput Test Mode enable" - default n - help - Enable the throughput test mode +endmenu #BLE6.x -config BT_NIMBLE_BLUFI_ENABLE - bool "Enable blufi functionality" - depends on BT_NIMBLE_ENABLED - default n - help - Set this option to enable blufi functionality. - -config BT_NIMBLE_USE_ESP_TIMER - bool "Enable Esp Timer for Nimble" - default y - help - Set this option to use Esp Timer which has higher priority timer instead of FreeRTOS timer - -config BT_NIMBLE_LEGACY_VHCI_ENABLE - bool - default y if (IDF_TARGET_ESP32 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3) - default n - help - This option is used to distinguish whether a previous version of VHCI is being used - -config BT_NIMBLE_BLE_GATT_BLOB_TRANSFER - bool "Blob transfer" - help - This option is used when data to be sent is more than 512 bytes. For peripheral role, - BT_NIMBLE_MSYS_1_BLOCK_COUNT needs to be increased according to the need. - -menu "BLE Services" +menu "Services" depends on BT_NIMBLE_GATT_SERVER config BT_NIMBLE_PROX_SERVICE @@ -1026,56 +835,56 @@ menu "BLE Services" bool "Manufacturer Name" default n help - Enable the DIS characteristic Manufacturer Name String characteristic + Enable the DIS characteristic Manufacturer Name String characteristic config BT_NIMBLE_SVC_DIS_SERIAL_NUMBER depends on BT_NIMBLE_DIS_SERVICE bool "Serial Number" default n help - Enable the DIS Serial Number characteristic + Enable the DIS Serial Number characteristic config BT_NIMBLE_SVC_DIS_HARDWARE_REVISION depends on BT_NIMBLE_DIS_SERVICE bool "Hardware Revision" default n help - Enable the DIS Hardware Revision characteristic + Enable the DIS Hardware Revision characteristic config BT_NIMBLE_SVC_DIS_FIRMWARE_REVISION depends on BT_NIMBLE_DIS_SERVICE bool "Firmware Revision" default n help - Enable the DIS Firmware Revision characteristic + Enable the DIS Firmware Revision characteristic config BT_NIMBLE_SVC_DIS_SOFTWARE_REVISION depends on BT_NIMBLE_DIS_SERVICE bool "Software Revision" default n help - Enable the DIS Software Revision characteristic + Enable the DIS Software Revision characteristic config BT_NIMBLE_SVC_DIS_SYSTEM_ID depends on BT_NIMBLE_DIS_SERVICE bool "System ID" default n help - Enable the DIS System ID characteristic + Enable the DIS System ID characteristic config BT_NIMBLE_SVC_DIS_PNP_ID depends on BT_NIMBLE_DIS_SERVICE bool "PnP ID" default n help - Enable the DIS PnP ID characteristic + Enable the DIS PnP ID characteristic config BT_NIMBLE_SVC_DIS_INCLUDED depends on BT_NIMBLE_DIS_SERVICE bool "DIS as an Included Service" default n help - Use DIS as an included service + Use DIS as an included service menuconfig BT_NIMBLE_GAP_SERVICE bool "GAP Service" @@ -1083,60 +892,66 @@ menu "BLE Services" help Enable GAP Service support - menu "GAP Appearance write permissions" - depends on BT_NIMBLE_GAP_SERVICE - - config BT_NIMBLE_SVC_GAP_APPEAR_WRITE - bool "Write" - default n - help - Enable write permission (BLE_GATT_CHR_F_WRITE) - - config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_ENC - depends on BT_NIMBLE_SVC_GAP_APPEAR_WRITE - bool "Write with encryption" + if BT_NIMBLE_GAP_SERVICE + config BT_NIMBLE_SVC_GAP_DEVICE_NAME + string "BLE GAP default device name" + depends on BT_NIMBLE_ENABLED + default "nimble" help - Enable write with encryption permission (BLE_GATT_CHR_F_WRITE_ENC) + The Device Name characteristic shall contain the name of the device as an UTF-8 string. + This name can be changed by using API ble_svc_gap_device_name_set() - config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHEN - depends on BT_NIMBLE_SVC_GAP_APPEAR_WRITE - bool "Write with authentication" + config BT_NIMBLE_GAP_DEVICE_NAME_MAX_LEN + int "Maximum length of BLE device name in octets" + depends on BT_NIMBLE_ENABLED + default 31 help - Enable write with authentication permission (BLE_GATT_CHR_F_WRITE_AUTHEN) + Device Name characteristic value shall be 0 to 248 octets in length - config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHOR - depends on BT_NIMBLE_SVC_GAP_APPEAR_WRITE - bool "Write with authorisation" - default n + config BT_NIMBLE_SVC_GAP_APPEARANCE + hex "External appearance of the device" + depends on BT_NIMBLE_ENABLED + default 0 help - Enable write with authorisation permission (BLE_GATT_CHR_F_WRITE_AUTHOR) + Standard BLE GAP Appearance value in HEX format e.g. 0x02C0 - config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM + config BT_NIMBLE_SVC_GAP_NAME_WRITE_PERM int - default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE - default 8 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE + default 0 if !BT_NIMBLE_SVC_GAP_NAME_WRITE + default 8 if BT_NIMBLE_SVC_GAP_NAME_WRITE - config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM_ENC + config BT_NIMBLE_SVC_GAP_NAME_WRITE_PERM_ENC int - default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE_ENC - default 4096 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE_ENC + default 0 if !BT_NIMBLE_SVC_GAP_NAME_WRITE_ENC + default 4096 if BT_NIMBLE_SVC_GAP_NAME_WRITE_ENC - config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM_ATHN + config BT_NIMBLE_SVC_GAP_NAME_WRITE_PERM_AUTHEN int - default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHEN - default 8192 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHEN + default 0 if !BT_NIMBLE_SVC_GAP_NAME_WRITE_AUTHEN + default 8192 if BT_NIMBLE_SVC_GAP_NAME_WRITE_AUTHEN - config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM_ATHR + config BT_NIMBLE_SVC_GAP_NAME_WRITE_PERM_AUTHOR int - default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHOR - default 16384 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHOR - endmenu + default 0 if !BT_NIMBLE_SVC_GAP_NAME_WRITE_AUTHOR + default 16384 if BT_NIMBLE_SVC_GAP_NAME_WRITE_AUTHOR - choice BT_NIMBLE_SVC_GAP_CENT_ADDR_RESOLUTION - prompt "GAP Characteristic - Central Address Resolution" - depends on BT_NIMBLE_GAP_SERVICE - default BT_NIMBLE_SVC_GAP_CAR_CHAR_NOT_SUPP - help + config BT_NIMBLE_SVC_GAP_GATT_SECURITY_LEVEL + bool "LE GATT Security Level Characteristic" + default n + help + Enable the LE GATT Security Level Characteristic + + config BT_NIMBLE_SVC_GAP_RPA_ONLY + bool "Resolvable Private Address Only characteristic" + default n + help + Enable the Resolvable Private Address Only characteristic + + choice BT_NIMBLE_SVC_GAP_CENT_ADDR_RESOLUTION + prompt "GAP Characteristic - Central Address Resolution" + depends on BT_NIMBLE_GAP_SERVICE + default BT_NIMBLE_SVC_GAP_CAR_CHAR_NOT_SUPP + help Weather or not Central Address Resolution characteristic is supported on the device, and if supported, weather or not Central Address Resolution is supported. @@ -1153,178 +968,366 @@ menu "BLE Services" config BT_NIMBLE_SVC_GAP_CAR_SUPP bool "Central Address Resolution supported" - endchoice + endchoice - config BT_NIMBLE_SVC_GAP_CENT_ADDR_RESOLUTION - int - default -1 if BT_NIMBLE_SVC_GAP_CAR_CHAR_NOT_SUPP - default 0 if BT_NIMBLE_SVC_GAP_CAR_NOT_SUPP - default 1 if BT_NIMBLE_SVC_GAP_CAR_SUPP - - menu "GAP device name write permissions" - depends on BT_NIMBLE_GAP_SERVICE - config BT_NIMBLE_SVC_GAP_NAME_WRITE - bool "Write" - default n - help - Enable write permission (BLE_GATT_CHR_F_WRITE) + config BT_NIMBLE_SVC_GAP_CENT_ADDR_RESOLUTION + int + default -1 if BT_NIMBLE_SVC_GAP_CAR_CHAR_NOT_SUPP + default 0 if BT_NIMBLE_SVC_GAP_CAR_NOT_SUPP + default 1 if BT_NIMBLE_SVC_GAP_CAR_SUPP - config BT_NIMBLE_SVC_GAP_NAME_WRITE_ENC - depends on BT_NIMBLE_SVC_GAP_NAME_WRITE - bool "Write with encryption" - default n - help - Enable write with encryption permission (BLE_GATT_CHR_F_WRITE_ENC) - config BT_NIMBLE_SVC_GAP_NAME_WRITE_AUTHEN - depends on BT_NIMBLE_SVC_GAP_NAME_WRITE - bool "Write with authentication" - default n - help - Enable write with authentication permission (BLE_GATT_CHR_F_WRITE_AUTHEN) + menu "GAP Appearance write permissions" + depends on BT_NIMBLE_GAP_SERVICE - config BT_NIMBLE_SVC_GAP_NAME_WRITE_AUTHOR - depends on BT_NIMBLE_SVC_GAP_NAME_WRITE - bool "Write with authorisation" - default n - help - Enable write with authorisation permission (BLE_GATT_CHR_F_WRITE_AUTHOR) - endmenu - - menu "Peripheral Preferred Connection Parameters (PPCP) settings" - depends on BT_NIMBLE_GAP_SERVICE - config BT_NIMBLE_SVC_GAP_PPCP_MAX_CONN_INTERVAL - int "PPCP Connection Interval Max (Unit: 1.25 ms)" - depends on BT_NIMBLE_ROLE_PERIPHERAL && BT_NIMBLE_GAP_SERVICE - default 0 - help - Peripheral Preferred Connection Parameter: Connection Interval maximum value - Interval Max = value * 1.25 ms + config BT_NIMBLE_SVC_GAP_APPEAR_WRITE + bool "Write" + default n + help + Enable write permission (BLE_GATT_CHR_F_WRITE) - config BT_NIMBLE_SVC_GAP_PPCP_MIN_CONN_INTERVAL - int "PPCP Connection Interval Min (Unit: 1.25 ms)" - depends on BT_NIMBLE_ROLE_PERIPHERAL && BT_NIMBLE_GAP_SERVICE - default 0 - help - Peripheral Preferred Connection Parameter: Connection Interval minimum value - Interval Min = value * 1.25 ms + config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_ENC + depends on BT_NIMBLE_SVC_GAP_APPEAR_WRITE + bool "Write with encryption" + help + Enable write with encryption permission (BLE_GATT_CHR_F_WRITE_ENC) + + config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHEN + depends on BT_NIMBLE_SVC_GAP_APPEAR_WRITE + bool "Write with authentication" + help + Enable write with authentication permission (BLE_GATT_CHR_F_WRITE_AUTHEN) - config BT_NIMBLE_SVC_GAP_PPCP_SLAVE_LATENCY - int "PPCP Slave Latency" + config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHOR + depends on BT_NIMBLE_SVC_GAP_APPEAR_WRITE + bool "Write with authorisation" + default n + help + Enable write with authorisation permission (BLE_GATT_CHR_F_WRITE_AUTHOR) + + config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM + int + default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE + default 8 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE + + config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM_ENC + int + default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE_ENC + default 4096 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE_ENC + + config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM_ATHN + int + default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHEN + default 8192 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHEN + + config BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM_ATHR + int + default 0 if !BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHOR + default 16384 if BT_NIMBLE_SVC_GAP_APPEAR_WRITE_AUTHOR + endmenu + + menu "GAP device name write permissions" depends on BT_NIMBLE_GAP_SERVICE - default 0 - help - Peripheral Preferred Connection Parameter: Slave Latency + config BT_NIMBLE_SVC_GAP_NAME_WRITE + bool "Write" + default n + help + Enable write permission (BLE_GATT_CHR_F_WRITE) + + config BT_NIMBLE_SVC_GAP_NAME_WRITE_ENC + depends on BT_NIMBLE_SVC_GAP_NAME_WRITE + bool "Write with encryption" + default n + help + Enable write with encryption permission (BLE_GATT_CHR_F_WRITE_ENC) + + config BT_NIMBLE_SVC_GAP_NAME_WRITE_AUTHEN + depends on BT_NIMBLE_SVC_GAP_NAME_WRITE + bool "Write with authentication" + default n + help + Enable write with authentication permission (BLE_GATT_CHR_F_WRITE_AUTHEN) - config BT_NIMBLE_SVC_GAP_PPCP_SUPERVISION_TMO - int "PPCP Supervision Timeout (Uint: 10 ms)" + config BT_NIMBLE_SVC_GAP_NAME_WRITE_AUTHOR + depends on BT_NIMBLE_SVC_GAP_NAME_WRITE + bool "Write with authorisation" + default n + help + Enable write with authorisation permission (BLE_GATT_CHR_F_WRITE_AUTHOR) + endmenu + + menu "Peripheral Preferred Connection Parameters (PPCP) settings" depends on BT_NIMBLE_GAP_SERVICE - default 0 - help - Peripheral Preferred Connection Parameter: Supervision Timeout - Timeout = Value * 10 ms - endmenu + config BT_NIMBLE_SVC_GAP_PPCP_MAX_CONN_INTERVAL + int "PPCP Connection Interval Max (Unit: 1.25 ms)" + depends on BT_NIMBLE_ROLE_PERIPHERAL && BT_NIMBLE_GAP_SERVICE + default 0 + help + Peripheral Preferred Connection Parameter: Connection Interval maximum value + Interval Max = value * 1.25 ms - config BT_NIMBLE_SVC_GAP_NAME_WRITE_PERM - int - default 0 if !BT_NIMBLE_SVC_GAP_NAME_WRITE - default 8 if BT_NIMBLE_SVC_GAP_NAME_WRITE + config BT_NIMBLE_SVC_GAP_PPCP_MIN_CONN_INTERVAL + int "PPCP Connection Interval Min (Unit: 1.25 ms)" + depends on BT_NIMBLE_ROLE_PERIPHERAL && BT_NIMBLE_GAP_SERVICE + default 0 + help + Peripheral Preferred Connection Parameter: Connection Interval minimum value + Interval Min = value * 1.25 ms - config BT_NIMBLE_SVC_GAP_NAME_WRITE_PERM_ENC - int - default 0 if !BT_NIMBLE_SVC_GAP_NAME_WRITE_ENC - default 4096 if BT_NIMBLE_SVC_GAP_NAME_WRITE_ENC + config BT_NIMBLE_SVC_GAP_PPCP_SLAVE_LATENCY + int "PPCP Slave Latency" + depends on BT_NIMBLE_GAP_SERVICE + default 0 + help + Peripheral Preferred Connection Parameter: Slave Latency - config BT_NIMBLE_SVC_GAP_NAME_WRITE_PERM_AUTHEN - int - default 0 if !BT_NIMBLE_SVC_GAP_NAME_WRITE_AUTHEN - default 8192 if BT_NIMBLE_SVC_GAP_NAME_WRITE_AUTHEN + config BT_NIMBLE_SVC_GAP_PPCP_SUPERVISION_TMO + int "PPCP Supervision Timeout (Uint: 10 ms)" + depends on BT_NIMBLE_GAP_SERVICE + default 0 + help + Peripheral Preferred Connection Parameter: Supervision Timeout + Timeout = Value * 10 ms + endmenu - config BT_NIMBLE_SVC_GAP_NAME_WRITE_PERM_AUTHOR - int - default 0 if !BT_NIMBLE_SVC_GAP_NAME_WRITE_AUTHOR - default 16384 if BT_NIMBLE_SVC_GAP_NAME_WRITE_AUTHOR + endif + +endmenu #Service + +menu "Extra Features" + config BT_NIMBLE_DYNAMIC_SERVICE + bool "Enable dynamic services" + depends on BT_NIMBLE_ENABLED + help + This enables user to add/remove Gatt services at runtime + + menuconfig BT_NIMBLE_GATT_CACHING + bool "Enable GATT caching" + depends on BT_NIMBLE_ENABLED + select BT_NIMBLE_DYNAMIC_SERVICE + help + Enable GATT caching + + config BT_NIMBLE_GATT_CACHING_INCLUDE_SERVICES + bool "Include services in GATT caching" + depends on BT_NIMBLE_GATT_CACHING + default n + help + Enable this option to include *included services* (e.g., services referenced by other services) + in the GATT database cache. Disabling this will skip caching of included service entries. + + config BT_NIMBLE_INCL_SVC_DISCOVERY + bool + default y if BT_NIMBLE_GATT_CACHING && BT_NIMBLE_GATT_CACHING_INCLUDE_SERVICES + default n if BT_NIMBLE_GATT_CACHING && !BT_NIMBLE_GATT_CACHING_INCLUDE_SERVICES + default n if !BT_NIMBLE_GATT_CACHING + prompt "Enable Included service discovery" if !BT_NIMBLE_GATT_CACHING + help + Enable this option to start discovery for included service. + + config BT_NIMBLE_GATT_CACHING_MAX_CONNS + int "Maximum connections to be cached" + depends on BT_NIMBLE_GATT_CACHING + default BT_NIMBLE_MAX_CONNECTIONS + help + Set this option to set the upper limit on number of connections to be cached. + + config BT_NIMBLE_GATT_CACHING_MAX_SVCS + int "Maximum number of services per connection" + depends on BT_NIMBLE_GATT_CACHING + default 64 + help + Set this option to set the upper limit on number of services per connection to be cached. + + config BT_NIMBLE_GATT_CACHING_MAX_INCL_SVCS + int "Maximum number of included services per connection" + depends on BT_NIMBLE_GATT_CACHING + default 64 + help + Set this option to set the upper limit on number of included services per connection to be cached. - config BT_NIMBLE_SVC_GAP_GATT_SECURITY_LEVEL - bool "LE GATT Security Level Characteristic" + config BT_NIMBLE_GATT_CACHING_MAX_CHRS + int "Maximum number of characteristics per connection" + depends on BT_NIMBLE_GATT_CACHING + default 64 + help + Set this option to set the upper limit on number of characteristics per connection to be cached. + + config BT_NIMBLE_GATT_CACHING_MAX_DSCS + int "Maximum number of descriptors per connection" + depends on BT_NIMBLE_GATT_CACHING + default 64 + help + Set this option to set the upper limit on number of descriptors per connection to be cached. + + config BT_NIMBLE_GATT_CACHING_DISABLE_AUTO + bool "Do not start discovery procedure automatically upon receiving Out of Sync" + depends on BT_NIMBLE_GATT_CACHING + default n + help + When client receives ATT out-of-sync error message, it will not automatically start the discovery procedure + to correct the invalid cache. + + config BT_NIMBLE_GATT_CACHING_ASSOC_ENABLE + bool "Enable association-based GATT caching" + depends on BT_NIMBLE_GATT_CACHING + default n + help + Enable this option to use associated address caching instead of performing service discovery. + + config BT_NIMBLE_BLUFI_ENABLE + bool "Enable blufi functionality" + depends on BT_NIMBLE_ENABLED + default n + help + Set this option to enable blufi functionality. + + config BT_NIMBLE_ENC_ADV_DATA + bool "Encrypted Advertising Data" + help + This option is used to enable encrypted advertising data. + + config BT_NIMBLE_MAX_EADS + int "Maximum number of EAD devices to save across reboots" + default 10 + depends on BT_NIMBLE_ENABLED && BT_NIMBLE_ENC_ADV_DATA + help + Defines maximum number of encrypted advertising data key material to save + + config BT_NIMBLE_GATTC_PROC_PREEMPTION_PROTECT + bool "Gatt-proc preemption protect check" + depends on BT_NIMBLE_ENABLED + default n + help + When BLE and Wireless protocol/IEEE 802.15.4 operate in coexistence, BLE preemption + can disrupt the GATT context,causing the service discovery callback to not be invoked. + A temporary list is maintained to preserve the GATT context and use it in case of preemption. + + config BT_NIMBLE_GATTC_AUTO_PAIR + bool "Automatically pair upon receiving service request failure" + depends on BT_NIMBLE_ENABLED default n help - Enable the LE GATT Security Level Characteristic + If enabled, when a service request (e.g. read, write) to a server fails, and the ATT + error suggests insufficient security, then the central will initiate pairing and retry + the service request. + + + config BT_NIMBLE_EATT_CHAN_NUM + int "Maximum number of EATT channels" + default 0 + depends on BT_NIMBLE_ENABLED + help + Defines the number of channels EATT bearers can use - config BT_NIMBLE_SVC_GAP_RPA_ONLY - bool "Resolvable Private Address Only characteristic" + config BT_NIMBLE_SUBRATE + bool "Enable Subrate Change" default n + depends on BT_NIMBLE_ENABLED help - Enable the Resolvable Private Address Only characteristic + Enable connection subrate change feature + endmenu -config BT_NIMBLE_VS_SUPPORT - bool "Enable support for VSC and VSE" - help - This option is used to enable support for sending Vendor Specific HCI commands and handling - Vendor Specific HCI Events. - -config BT_NIMBLE_OPTIMIZE_MULTI_CONN - bool "Enable the optimization of multi-connection" - depends on SOC_BLE_MULTI_CONN_OPTIMIZATION - select BT_NIMBLE_VS_SUPPORT - default n - help - This option enables the use of vendor-specific APIs for multi-connections, which can - greatly enhance the stability of coexistence between numerous central and peripheral - devices. It will prohibit the usage of standard APIs. - -config BT_NIMBLE_ENC_ADV_DATA - bool "Encrypted Advertising Data" - help - This option is used to enable encrypted advertising data. - -config BT_NIMBLE_MAX_EADS - int "Maximum number of EAD devices to save across reboots" - default 10 - depends on BT_NIMBLE_ENABLED && BT_NIMBLE_ENC_ADV_DATA - help - Defines maximum number of encrypted advertising data key material to save - -config BT_NIMBLE_HIGH_DUTY_ADV_ITVL - bool "Enable BLE high duty advertising interval feature" - depends on BT_NIMBLE_ENABLED - help - This enable BLE high duty advertising interval feature - -config BT_NIMBLE_HOST_ALLOW_CONNECT_WITH_SCAN - bool "Allow Connections with scanning in progress" - depends on BT_NIMBLE_ENABLED && !(IDF_TARGET_ESP32C2) - help - This enables support for user to initiate a new connection with scan in progress - -config BT_NIMBLE_HOST_QUEUE_CONG_CHECK - bool "BLE queue congestion check" - depends on BT_NIMBLE_ENABLED - default n - help - When scanning and scan duplicate is not enabled, if there are a lot of adv packets around - or application layer handling adv packets is slow, it will cause the controller memory - to run out. if enabled, adv packets will be lost when host queue is congested. - -config BT_NIMBLE_GATTC_PROC_PREEMPTION_PROTECT - bool "Gatt-proc preemption protect check" - depends on BT_NIMBLE_ENABLED - default n - help - When BLE and Wireless protocol/IEEE 802.15.4 operate in coexistence, BLE preemption - can disrupt the GATT context,causing the service discovery callback to not be invoked. - A temporary list is maintained to preserve the GATT context and use it in case of preemption. - -config BT_NIMBLE_GATTC_AUTO_PAIR - bool "Automatically pair upon receiving service request failure" - depends on BT_NIMBLE_ENABLED - default n - help - If enabled, when a service request (e.g. read, write) to a server fails, and the ATT - error suggests insufficient security, then the central will initiate pairing and retry - the service request. +menu "NimBLE Mesh" + menuconfig BT_NIMBLE_MESH + bool "Enable BLE mesh functionality" + select BT_NIMBLE_SM_SC + depends on BT_NIMBLE_ENABLED + default n + help + Enable BLE Mesh example present in upstream mynewt-nimble and not maintained by Espressif. + + IDF maintains ESP-BLE-MESH as the official Mesh solution. Please refer to ESP-BLE-MESH guide at: + `https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/esp-ble-mesh/ble-mesh-index.html` + + config BT_NIMBLE_MESH_PROXY + bool "Enable mesh proxy functionality" + default n + depends on BT_NIMBLE_MESH + help + Enable proxy. This is automatically set whenever NIMBLE_MESH_PB_GATT or + NIMBLE_MESH_GATT_PROXY is set + + + config BT_NIMBLE_MESH_PROV + bool "Enable BLE mesh provisioning" + default y + depends on BT_NIMBLE_MESH + help + Enable mesh provisioning + + config BT_NIMBLE_MESH_PB_ADV + bool "Enable mesh provisioning over advertising bearer" + default y + depends on BT_NIMBLE_MESH_PROV + help + Enable this option to allow the device to be provisioned over + the advertising bearer + + + config BT_NIMBLE_MESH_PB_GATT + bool "Enable mesh provisioning over GATT bearer" + default y + select BT_NIMBLE_MESH_PROXY + depends on BT_NIMBLE_MESH_PROV + help + Enable this option to allow the device to be provisioned over the GATT + bearer + + config BT_NIMBLE_MESH_GATT_PROXY + bool "Enable GATT Proxy functionality" + default y + select BT_NIMBLE_MESH_PROXY + depends on BT_NIMBLE_MESH + help + This option enables support for the Mesh GATT Proxy Service, + i.e. the ability to act as a proxy between a Mesh GATT Client + and a Mesh network + + config BT_NIMBLE_MESH_RELAY + bool "Enable mesh relay functionality" + default n + depends on BT_NIMBLE_MESH + help + Support for acting as a Mesh Relay Node + + config BT_NIMBLE_MESH_LOW_POWER + bool "Enable mesh low power mode" + default n + depends on BT_NIMBLE_MESH + help + Enable this option to be able to act as a Low Power Node + + config BT_NIMBLE_MESH_FRIEND + bool "Enable mesh friend functionality" + default n + depends on BT_NIMBLE_MESH + help + Enable this option to be able to act as a Friend Node + + config BT_NIMBLE_MESH_DEVICE_NAME + string "Set mesh device name" + default "nimble-mesh-node" + depends on BT_NIMBLE_MESH + help + This value defines Bluetooth Mesh device/node name + + config BT_NIMBLE_MESH_NODE_COUNT + int "Set mesh node count" + default 1 + depends on BT_NIMBLE_MESH + help + Defines mesh node count. + + config BT_NIMBLE_MESH_PROVISIONER + bool "Enable BLE mesh provisioner" + default 0 + depends on BT_NIMBLE_MESH + help + Enable mesh provisioner. +endmenu #Mesh menu "Host-controller Transport" config BT_NIMBLE_TRANSPORT_UART @@ -1441,18 +1444,84 @@ menu "Host-controller Transport" default 23 help UART HCI CTS pin -endmenu +endmenu #Transport + +menu "Debugging/Testing" + choice BT_NIMBLE_LOG_LEVEL + prompt "NimBLE Host log verbosity" + depends on BT_NIMBLE_ENABLED + default BT_NIMBLE_LOG_LEVEL_INFO + help + Select NimBLE log level. Note that the selected NimBLE log + verbosity can not exceed the level set in + "Component config --> Log output --> Default log verbosity". + + config BT_NIMBLE_LOG_LEVEL_NONE + bool "No logs" + + config BT_NIMBLE_LOG_LEVEL_ERROR + bool "Error logs" -config BT_NIMBLE_EATT_CHAN_NUM - int "Maximum number of EATT channels" - default 0 - depends on BT_NIMBLE_ENABLED - help - Defines the number of channels EATT bearers can use - -config BT_NIMBLE_SUBRATE - bool "Enable Subrate Change" - default n - depends on BT_NIMBLE_ENABLED - help - Enable connection subrate change feature + config BT_NIMBLE_LOG_LEVEL_WARNING + bool "Warning logs" + + config BT_NIMBLE_LOG_LEVEL_INFO + bool "Info logs" + + config BT_NIMBLE_LOG_LEVEL_DEBUG + bool "Debug logs" + endchoice #BT_NIMBLE_LOG_LEVEL + + config BT_NIMBLE_LOG_LEVEL + int + default 0 if BT_NIMBLE_LOG_LEVEL_DEBUG + default 1 if BT_NIMBLE_LOG_LEVEL_INFO + default 2 if BT_NIMBLE_LOG_LEVEL_WARNING + default 3 if BT_NIMBLE_LOG_LEVEL_ERROR + default 4 if BT_NIMBLE_LOG_LEVEL_NONE + + config BT_NIMBLE_PRINT_ERR_NAME + bool "Enable feature to print Error description" + depends on BT_NIMBLE_ENABLED + default y + help + Enable feature to give useful explanation for HCI errors + + config BT_NIMBLE_DEBUG + bool "Enable extra runtime asserts and host debugging" + default n + depends on BT_NIMBLE_ENABLED + help + This enables extra runtime asserts and host debugging + + config BT_NIMBLE_TEST_THROUGHPUT_TEST + bool "Throughput Test Mode enable" + default n + help + Enable the throughput test mode + +endmenu #Debugging + +menu "Vendor / Optimization" + config BT_NIMBLE_VS_SUPPORT + bool "Enable support for VSC and VSE" + help + This option is used to enable support for sending Vendor Specific HCI commands and handling + Vendor Specific HCI Events. + + config BT_NIMBLE_OPTIMIZE_MULTI_CONN + bool "Enable the optimization of multi-connection" + depends on SOC_BLE_MULTI_CONN_OPTIMIZATION + select BT_NIMBLE_VS_SUPPORT + default n + help + This option enables the use of vendor-specific APIs for multi-connections, which can + greatly enhance the stability of coexistence between numerous central and peripheral + devices. It will prohibit the usage of standard APIs. + + config BT_NIMBLE_HIGH_DUTY_ADV_ITVL + bool "Enable BLE high duty advertising interval feature" + depends on BT_NIMBLE_ENABLED + help + This enable BLE high duty advertising interval feature +endmenu #Vendor diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble index d23b04ec9566..8fd41d86c4ed 160000 --- a/components/bt/host/nimble/nimble +++ b/components/bt/host/nimble/nimble @@ -1 +1 @@ -Subproject commit d23b04ec95668b18f867c2c234bb75a84f64a996 +Subproject commit 8fd41d86c4ed8657e6c97d6da8b3d214622db737 diff --git a/components/bt/host/nimble/port/include/ble_svc_gap_stub.h b/components/bt/host/nimble/port/include/ble_svc_gap_stub.h new file mode 100644 index 000000000000..1fb456f2194d --- /dev/null +++ b/components/bt/host/nimble/port/include/ble_svc_gap_stub.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_log.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define BLE_SVC_GAP_TAG "ble_svc_gap" + +/** + * Stub implementations for GAP service APIs. + * These are compiled when CONFIG_BT_NIMBLE_GAP_SERVICE is disabled. + */ + +static inline void ble_svc_gap_init(void) +{ + ESP_LOGE(BLE_SVC_GAP_TAG, "GAP service not enabled. Enable CONFIG_BT_NIMBLE_GAP_SERVICE to use this API."); +} + +static inline int ble_svc_gap_device_name_set(const char *name) +{ + (void)name; + ESP_LOGE(BLE_SVC_GAP_TAG, "GAP service not enabled. Enable CONFIG_BT_NIMBLE_GAP_SERVICE to use this API."); + return -1; +} + +static inline const char *ble_svc_gap_device_name(void) +{ + ESP_LOGE(BLE_SVC_GAP_TAG, "GAP service not enabled. Enable CONFIG_BT_NIMBLE_GAP_SERVICE to use this API."); + return NULL; +} + +static inline int ble_svc_gap_device_appearance_set(uint16_t appearance) +{ + ESP_LOGE(BLE_SVC_GAP_TAG, "GAP service not enabled. Enable CONFIG_BT_NIMBLE_GAP_SERVICE to use this API."); + return -1; +} + +static inline int ble_svc_gap_device_key_material_set(uint8_t *session_key, uint8_t *iv) +{ + ESP_LOGE(BLE_SVC_GAP_TAG, "GAP service not enabled. Enable CONFIG_BT_NIMBLE_GAP_SERVICE to use this API."); + return -1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/bt/host/nimble/port/include/esp_nimble_cfg.h b/components/bt/host/nimble/port/include/esp_nimble_cfg.h index 06d13b8f309f..620df768e73e 100644 --- a/components/bt/host/nimble/port/include/esp_nimble_cfg.h +++ b/components/bt/host/nimble/port/include/esp_nimble_cfg.h @@ -1804,9 +1804,11 @@ #endif /*** @apache-mynewt-nimble/nimble/host/services/gap */ +#ifdef CONFIG_BT_NIMBLE_GAP_SERVICE #ifndef MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE #define MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE CONFIG_BT_NIMBLE_SVC_GAP_APPEARANCE #endif +#endif #ifndef MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE_WRITE_PERM #if CONFIG_BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM @@ -1819,10 +1821,12 @@ #endif //CONFIG_BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM #endif //MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE_WRITE_PERM +#ifdef CONFIG_BT_NIMBLE_GAP_SERVICE #ifndef MYNEWT_VAL_BLE_SVC_GAP_CENTRAL_ADDRESS_RESOLUTION #define MYNEWT_VAL_BLE_SVC_GAP_CENTRAL_ADDRESS_RESOLUTION \ CONFIG_BT_NIMBLE_SVC_GAP_CENT_ADDR_RESOLUTION #endif +#endif #ifndef CONFIG_BT_NIMBLE_SVC_GAP_DEVICE_NAME #define MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME "nimble" @@ -1830,9 +1834,11 @@ #define MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME CONFIG_BT_NIMBLE_SVC_GAP_DEVICE_NAME #endif +#ifdef CONFIG_BT_NIMBLE_GAP_SERVICE #ifndef MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME_MAX_LENGTH #define MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME_MAX_LENGTH CONFIG_BT_NIMBLE_GAP_DEVICE_NAME_MAX_LEN // According to the specification, the maximum length should be 248 #endif +#endif #ifndef MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME_WRITE_PERM #if CONFIG_BT_NIMBLE_SVC_GAP_NAME_WRITE_PERM @@ -2192,4 +2198,12 @@ #define MYNEWT_VAL_BLE_USED_IN_IDF (1) #endif +#ifndef MYNEWT_VAL_BLE_CHANNEL_SOUNDING +#ifdef CONFIG_BT_NIMBLE_CHANNEL_SOUNDING +#define MYNEWT_VAL_BLE_CHANNEL_SOUNDING (CONFIG_BT_NIMBLE_CHANNEL_SOUNDING) +#else +#define MYNEWT_VAL_BLE_CHANNEL_SOUNDING (0) +#endif +#endif + #endif diff --git a/components/bt/include/esp32c6/include/esp_bt.h b/components/bt/include/esp32c6/include/esp_bt.h index d3c67ad01a5b..7181be6e43e4 100644 --- a/components/bt/include/esp32c6/include/esp_bt.h +++ b/components/bt/include/esp32c6/include/esp_bt.h @@ -156,7 +156,7 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type */ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle); -#define CONFIG_VERSION 0x20250606 +#define CONFIG_VERSION 0x20251022 #define CONFIG_MAGIC 0x5A5AA5A5 /** @@ -234,6 +234,7 @@ typedef struct { int8_t ch39_txpwr; /*!< BLE transmit power (in dBm) used for BLE advertising on channel 39. */ uint8_t adv_rsv_cnt; /*!< BLE adv state machine reserve count number */ uint8_t conn_rsv_cnt; /*!< BLE conn state machine reserve count number */ + uint8_t priority_level_cfg; /*!< The option for priority level configuration */ uint32_t config_magic; /*!< Magic number for configuration validation */ } esp_bt_controller_config_t; @@ -298,6 +299,7 @@ typedef struct { .ch39_txpwr = BLE_LL_TX_PWR_DBM_N, \ .adv_rsv_cnt = BLE_LL_ADV_SM_RESERVE_CNT_N, \ .conn_rsv_cnt = BLE_LL_CONN_SM_RESERVE_CNT_N, \ + .priority_level_cfg = BT_LL_CTRL_PRIO_LVL_CFG, \ .config_magic = CONFIG_MAGIC, \ } #elif CONFIG_IDF_TARGET_ESP32C61 @@ -359,6 +361,7 @@ typedef struct { .ch39_txpwr = BLE_LL_TX_PWR_DBM_N, \ .adv_rsv_cnt = BLE_LL_ADV_SM_RESERVE_CNT_N, \ .conn_rsv_cnt = BLE_LL_CONN_SM_RESERVE_CNT_N, \ + .priority_level_cfg = BT_LL_CTRL_PRIO_LVL_CFG, \ .config_magic = CONFIG_MAGIC, \ } #endif diff --git a/components/bt/include/esp32h2/include/esp_bt.h b/components/bt/include/esp32h2/include/esp_bt.h index 601f5816a37f..b6bb5bfb23bd 100644 --- a/components/bt/include/esp32h2/include/esp_bt.h +++ b/components/bt/include/esp32h2/include/esp_bt.h @@ -161,7 +161,7 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type */ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle); -#define CONFIG_VERSION 0x20250606 +#define CONFIG_VERSION 0x20251022 #define CONFIG_MAGIC 0x5A5AA5A5 /** @@ -236,6 +236,7 @@ typedef struct { int8_t ch39_txpwr; /*!< BLE transmit power (in dBm) used for BLE advertising on channel 39. */ uint8_t adv_rsv_cnt; /*!< BLE adv state machine reserve count number */ uint8_t conn_rsv_cnt; /*!< BLE conn state machine reserve count number */ + uint8_t priority_level_cfg; /*!< The option for priority level configuration */ uint32_t config_magic; /*!< Configuration magic value */ } esp_bt_controller_config_t; @@ -298,6 +299,7 @@ typedef struct { .ch39_txpwr = BLE_LL_TX_PWR_DBM_N, \ .adv_rsv_cnt = BLE_LL_ADV_SM_RESERVE_CNT_N, \ .conn_rsv_cnt = BLE_LL_CONN_SM_RESERVE_CNT_N, \ + .priority_level_cfg = BT_LL_CTRL_PRIO_LVL_CFG, \ .config_magic = CONFIG_MAGIC, \ } diff --git a/components/bt/porting/include/bt_osi_mem.h b/components/bt/porting/include/bt_osi_mem.h index cf5f60956e10..a97165d70784 100644 --- a/components/bt/porting/include/bt_osi_mem.h +++ b/components/bt/porting/include/bt_osi_mem.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,6 +20,12 @@ void *bt_osi_mem_calloc_internal(size_t n, size_t size); void bt_osi_mem_free(void *ptr); +void bt_osi_mem_free_internal(void *ptr); #if CONFIG_BT_LE_MEM_CHECK_ENABLED void bt_osi_mem_count_limit_set(uint16_t count_limit); #endif // CONFIG_BT_LE_MEM_CHECK_ENABLED + +#if CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED +size_t bt_osi_mem_internal_used_size_get(void); +size_t bt_osi_mem_used_size_get(void); +#endif // CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED diff --git a/components/bt/porting/mem/bt_osi_mem.c b/components/bt/porting/mem/bt_osi_mem.c index cbedf8c96d24..306ec8290ef8 100644 --- a/components/bt/porting/mem/bt_osi_mem.c +++ b/components/bt/porting/mem/bt_osi_mem.c @@ -11,6 +11,10 @@ #include static uint8_t log_count; +#if CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED +static size_t controller_mem_used_size = 0; +static size_t host_mem_used_size = 0; +#endif // CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED #if CONFIG_BT_LE_MEM_CHECK_ENABLED static uint16_t mem_count_limit = 0; static uint16_t curr_mem_count; @@ -35,24 +39,37 @@ IRAM_ATTR void *bt_osi_mem_malloc(size_t size) } assert(mem != NULL); } +#if CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED + if(mem) { + host_mem_used_size += heap_caps_get_allocated_size(mem); + } +#endif // CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED return mem; } IRAM_ATTR void *bt_osi_mem_calloc(size_t n, size_t size) { + void *mem = NULL; #ifdef CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_INTERNAL - return heap_caps_calloc(n, size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT); + mem = heap_caps_calloc(n, size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT); #elif CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_EXTERNAL - return heap_caps_calloc(n, size, MALLOC_CAP_SPIRAM|MALLOC_CAP_8BIT); + mem = heap_caps_calloc(n, size, MALLOC_CAP_SPIRAM|MALLOC_CAP_8BIT); #elif CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_IRAM_8BIT - return heap_caps_calloc_prefer(n, size, 2, MALLOC_CAP_INTERNAL|MALLOC_CAP_IRAM_8BIT, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT); + mem = heap_caps_calloc_prefer(n, size, 2, MALLOC_CAP_INTERNAL|MALLOC_CAP_IRAM_8BIT, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT); #else - return calloc(n, size); + mem = calloc(n, size); #endif +#if CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED + if(mem) { + host_mem_used_size += heap_caps_get_allocated_size(mem); + } +#endif // CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED + return mem; } IRAM_ATTR void *bt_osi_mem_malloc_internal(size_t size) { + void *mem_ptr; #if CONFIG_BT_LE_MEM_CHECK_ENABLED if (mem_count_limit) { if (curr_mem_count > mem_count_limit) { @@ -61,11 +78,18 @@ IRAM_ATTR void *bt_osi_mem_malloc_internal(size_t size) curr_mem_count ++; } #endif // CONFIG_BT_LE_MEM_CHECK_ENABLED - return heap_caps_malloc(size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT|MALLOC_CAP_DMA); + mem_ptr = heap_caps_malloc(size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT|MALLOC_CAP_DMA); +#if CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED + if (mem_ptr) { + controller_mem_used_size += heap_caps_get_allocated_size(mem_ptr); + } +#endif // CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED + return mem_ptr; } IRAM_ATTR void *bt_osi_mem_calloc_internal(size_t n, size_t size) { + void *mem_ptr; #if CONFIG_BT_LE_MEM_CHECK_ENABLED if (mem_count_limit) { if (curr_mem_count > mem_count_limit) { @@ -74,11 +98,36 @@ IRAM_ATTR void *bt_osi_mem_calloc_internal(size_t n, size_t size) curr_mem_count ++; } #endif // CONFIG_BT_LE_MEM_CHECK_ENABLED - return heap_caps_calloc(n, size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT|MALLOC_CAP_DMA); + mem_ptr = heap_caps_calloc(n, size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT|MALLOC_CAP_DMA); +#if CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED + if (mem_ptr) { + controller_mem_used_size += heap_caps_get_allocated_size(mem_ptr); + } +#endif // CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED + return mem_ptr; +} + +IRAM_ATTR void bt_osi_mem_free_internal(void *ptr) +{ +#if CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED + if (ptr) { + size_t alloc_size = heap_caps_get_allocated_size(ptr); + // assert(controller_mem_used_size >= alloc_size); + controller_mem_used_size -= alloc_size; + } +#endif // CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED + heap_caps_free(ptr); } IRAM_ATTR void bt_osi_mem_free(void *ptr) { +#if CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED + if (ptr) { + size_t alloc_size = heap_caps_get_allocated_size(ptr); + // assert(host_mem_used_size >= alloc_size); + host_mem_used_size -= alloc_size; + } +#endif // CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED heap_caps_free(ptr); } @@ -89,3 +138,29 @@ void bt_osi_mem_count_limit_set(uint16_t count_limit) curr_mem_count = 0; } #endif // CONFIG_BT_LE_MEM_CHECK_ENABLED + +#if CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED +size_t +bt_osi_mem_internal_used_size_get(void) +{ + return controller_mem_used_size; +} + +size_t +bt_osi_mem_used_size_get(void) +{ + return host_mem_used_size; +} + +uint32_t esp_ble_controller_used_heap_size_get(void) +{ + return bt_osi_mem_internal_used_size_get(); +} + +#if CONFIG_BT_NIMBLE_ENABLED +uint32_t esp_host_used_heap_size_get(void) +{ + return bt_osi_mem_used_size_get(); +} +#endif // CONFIG_BT_NIMBLE_ENABLED +#endif // CONFIG_BT_LE_USED_MEM_STATISTICS_ENABLED diff --git a/components/bt/porting/npl/freertos/src/npl_os_freertos.c b/components/bt/porting/npl/freertos/src/npl_os_freertos.c index 73f425262fea..4103e62042d9 100644 --- a/components/bt/porting/npl/freertos/src/npl_os_freertos.c +++ b/components/bt/porting/npl/freertos/src/npl_os_freertos.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -116,7 +116,7 @@ IRAM_ATTR npl_freertos_event_deinit(struct ble_npl_event *ev) #if OS_MEM_ALLOC os_memblock_put(&ble_freertos_ev_pool,ev->event); #else - bt_osi_mem_free(ev->event); + bt_osi_mem_free_internal(ev->event); #endif ev->event = NULL; } @@ -170,7 +170,7 @@ npl_freertos_eventq_deinit(struct ble_npl_eventq *evq) #if OS_MEM_ALLOC os_memblock_put(&ble_freertos_evq_pool,eventq); #else - bt_osi_mem_free((void *)eventq); + bt_osi_mem_free_internal((void *)eventq); #endif evq->eventq = NULL; } @@ -391,7 +391,7 @@ npl_freertos_mutex_deinit(struct ble_npl_mutex *mu) #if OS_MEM_ALLOC os_memblock_put(&ble_freertos_mutex_pool,mutex); #else - bt_osi_mem_free((void *)mutex); + bt_osi_mem_free_internal((void *)mutex); #endif mu->mutex = NULL; @@ -528,7 +528,7 @@ npl_freertos_sem_deinit(struct ble_npl_sem *sem) #if OS_MEM_ALLOC os_memblock_put(&ble_freertos_sem_pool,semaphore); #else - bt_osi_mem_free((void *)semaphore); + bt_osi_mem_free_internal((void *)semaphore); #endif sem->sem = NULL; @@ -707,7 +707,7 @@ npl_freertos_callout_init(struct ble_npl_callout *co, struct ble_npl_eventq *evq if (esp_timer_create(&create_args, &callout->handle) != ESP_OK) { ble_npl_event_deinit(&callout->ev); - bt_osi_mem_free((void *)callout); + bt_osi_mem_free_internal((void *)callout); co->co = NULL; return -1; } @@ -716,7 +716,7 @@ npl_freertos_callout_init(struct ble_npl_callout *co, struct ble_npl_eventq *evq if (!callout->handle) { ble_npl_event_deinit(&callout->ev); - bt_osi_mem_free((void *)callout); + bt_osi_mem_free_internal((void *)callout); co->co = NULL; return -1; } @@ -764,7 +764,7 @@ npl_freertos_callout_deinit(struct ble_npl_callout *co) #if OS_MEM_ALLOC os_memblock_put(&ble_freertos_co_pool,callout); #else - bt_osi_mem_free((void *)callout); + bt_osi_mem_free_internal((void *)callout); #endif // OS_MEM_ALLOC co->co = NULL; memset(co, 0, sizeof(struct ble_npl_callout)); @@ -1203,27 +1203,27 @@ int npl_freertos_mempool_init(void) return 0; _error: if (ble_freertos_ev_buf) { - bt_osi_mem_free(ble_freertos_ev_buf); + bt_osi_mem_free_internal(ble_freertos_ev_buf); ble_freertos_ev_buf = NULL; } if (ble_freertos_evq_buf) { - bt_osi_mem_free(ble_freertos_evq_buf); + bt_osi_mem_free_internal(ble_freertos_evq_buf); ble_freertos_evq_buf = NULL; } if (ble_freertos_co_buf) { - bt_osi_mem_free(ble_freertos_co_buf); + bt_osi_mem_free_internal(ble_freertos_co_buf); ble_freertos_co_buf = NULL; } if (ble_freertos_sem_buf) { - bt_osi_mem_free(ble_freertos_sem_buf); + bt_osi_mem_free_internal(ble_freertos_sem_buf); ble_freertos_sem_buf = NULL; } if (ble_freertos_mutex_buf) { - bt_osi_mem_free(ble_freertos_mutex_buf); + bt_osi_mem_free_internal(ble_freertos_mutex_buf); ble_freertos_mutex_buf = NULL; } return -1; @@ -1232,23 +1232,23 @@ int npl_freertos_mempool_init(void) void npl_freertos_mempool_deinit(void) { if (ble_freertos_ev_buf) { - bt_osi_mem_free(ble_freertos_ev_buf); + bt_osi_mem_free_internal(ble_freertos_ev_buf); ble_freertos_ev_buf = NULL; } if (ble_freertos_evq_buf) { - bt_osi_mem_free(ble_freertos_evq_buf); + bt_osi_mem_free_internal(ble_freertos_evq_buf); ble_freertos_evq_buf = NULL; } if (ble_freertos_co_buf) { - bt_osi_mem_free(ble_freertos_co_buf); + bt_osi_mem_free_internal(ble_freertos_co_buf); ble_freertos_co_buf = NULL; } if (ble_freertos_sem_buf) { - bt_osi_mem_free(ble_freertos_sem_buf); + bt_osi_mem_free_internal(ble_freertos_sem_buf); ble_freertos_sem_buf = NULL; } if (ble_freertos_mutex_buf) { - bt_osi_mem_free(ble_freertos_mutex_buf); + bt_osi_mem_free_internal(ble_freertos_mutex_buf); ble_freertos_mutex_buf = NULL; } } @@ -1256,7 +1256,7 @@ void npl_freertos_mempool_deinit(void) void npl_freertos_funcs_deinit(void) { if (npl_funcs) { - bt_osi_mem_free(npl_funcs); + bt_osi_mem_free_internal(npl_funcs); } npl_funcs = NULL; } diff --git a/components/driver/test_apps/legacy_pcnt_driver/main/test_legacy_pcnt.c b/components/driver/test_apps/legacy_pcnt_driver/main/test_legacy_pcnt.c index 80bd8657f37a..5083754820a5 100644 --- a/components/driver/test_apps/legacy_pcnt_driver/main/test_legacy_pcnt.c +++ b/components/driver/test_apps/legacy_pcnt_driver/main/test_legacy_pcnt.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -288,7 +288,7 @@ static void count_mode_test(gpio_num_t ctl_io) vTaskDelay(1000 / portTICK_PERIOD_MS); TEST_ESP_OK(pcnt_get_counter_value(PCNT_UNIT_0, &test_counter)); printf("value: %d\n", test_counter); - TEST_ASSERT_INT16_WITHIN(1, test_counter, result[0]); + TEST_ASSERT_INT16_WITHIN(2, test_counter, result[0]); //2, 0, 0, 0 TEST_ESP_OK(pcnt_counter_pause(PCNT_UNIT_0)); @@ -300,7 +300,7 @@ static void count_mode_test(gpio_num_t ctl_io) vTaskDelay(1000 / portTICK_PERIOD_MS); TEST_ESP_OK(pcnt_get_counter_value(PCNT_UNIT_0, &test_counter)); printf("value: %d\n", test_counter); - TEST_ASSERT_INT16_WITHIN(1, test_counter, result[1]); + TEST_ASSERT_INT16_WITHIN(2, test_counter, result[1]); //0,0,0,0 TEST_ESP_OK(pcnt_counter_pause(PCNT_UNIT_0)); @@ -312,7 +312,7 @@ static void count_mode_test(gpio_num_t ctl_io) vTaskDelay(1000 / portTICK_PERIOD_MS); TEST_ESP_OK(pcnt_get_counter_value(PCNT_UNIT_0, &test_counter)); printf("value: %d\n", test_counter); - TEST_ASSERT_INT16_WITHIN(1, test_counter, result[2]); + TEST_ASSERT_INT16_WITHIN(2, test_counter, result[2]); //1,0,1,0 TEST_ESP_OK(pcnt_counter_pause(PCNT_UNIT_0)); @@ -324,7 +324,7 @@ static void count_mode_test(gpio_num_t ctl_io) vTaskDelay(1000 / portTICK_PERIOD_MS); TEST_ESP_OK(pcnt_get_counter_value(PCNT_UNIT_0, &test_counter)); printf("value: %d\n", test_counter); - TEST_ASSERT_INT16_WITHIN(1, test_counter, result[3]); + TEST_ASSERT_INT16_WITHIN(2, test_counter, result[3]); //1,0,0,1 TEST_ESP_OK(pcnt_counter_pause(PCNT_UNIT_0)); @@ -336,7 +336,7 @@ static void count_mode_test(gpio_num_t ctl_io) vTaskDelay(1000 / portTICK_PERIOD_MS); TEST_ESP_OK(pcnt_get_counter_value(PCNT_UNIT_0, &test_counter)); printf("value: %d\n", test_counter); - TEST_ASSERT_INT16_WITHIN(1, test_counter, result[4]); + TEST_ASSERT_INT16_WITHIN(2, test_counter, result[4]); //2,0,0,1 TEST_ESP_OK(pcnt_counter_pause(PCNT_UNIT_0)); @@ -348,7 +348,7 @@ static void count_mode_test(gpio_num_t ctl_io) vTaskDelay(1000 / portTICK_PERIOD_MS); TEST_ESP_OK(pcnt_get_counter_value(PCNT_UNIT_0, &test_counter)); printf("value: %d\n", test_counter); - TEST_ASSERT_INT16_WITHIN(1, test_counter, result[5]); + TEST_ASSERT_INT16_WITHIN(2, test_counter, result[5]); //1,0,2,0 TEST_ESP_OK(pcnt_counter_pause(PCNT_UNIT_0)); @@ -360,7 +360,7 @@ static void count_mode_test(gpio_num_t ctl_io) vTaskDelay(1000 / portTICK_PERIOD_MS); TEST_ESP_OK(pcnt_get_counter_value(PCNT_UNIT_0, &test_counter)); printf("value: %d\n", test_counter); - TEST_ASSERT_INT16_WITHIN(1, test_counter, result[6]); + TEST_ASSERT_INT16_WITHIN(2, test_counter, result[6]); //1,0,0,2 TEST_ESP_OK(pcnt_counter_pause(PCNT_UNIT_0)); @@ -372,7 +372,7 @@ static void count_mode_test(gpio_num_t ctl_io) vTaskDelay(1000 / portTICK_PERIOD_MS); TEST_ESP_OK(pcnt_get_counter_value(PCNT_UNIT_0, &test_counter)); printf("value: %d\n", test_counter); - TEST_ASSERT_INT16_WITHIN(1, test_counter, result[7]); + TEST_ASSERT_INT16_WITHIN(2, test_counter, result[7]); } /* PCNT basic property: @@ -521,24 +521,24 @@ TEST_CASE("PCNT_interrupt_method_test_control_IO_high", "[pcnt][timeout=120]") // test event event_calculate(&event); - TEST_ASSERT_INT_WITHIN(2, event.h_threshold, 2); - TEST_ASSERT_INT_WITHIN(2, event.l_threshold, 2); + TEST_ASSERT_INT_WITHIN(3, event.h_threshold, 2); + TEST_ASSERT_INT_WITHIN(3, event.l_threshold, 2); TEST_ASSERT(event.l_limit == 0); - TEST_ASSERT_INT_WITHIN(2, event.h_limit, 2); - TEST_ASSERT_INT_WITHIN(2, event.zero_times, 2); - TEST_ASSERT_INT_WITHIN(3, event.filter_time, 4); + TEST_ASSERT_INT_WITHIN(3, event.h_limit, 2); + TEST_ASSERT_INT_WITHIN(3, event.zero_times, 2); + TEST_ASSERT_INT_WITHIN(4, event.filter_time, 4); // test interrupt disable TEST_ESP_OK(pcnt_intr_disable(PCNT_UNIT_0)); TEST_ESP_OK(pcnt_counter_clear(PCNT_UNIT_0)); // for the original control io disable interrupt status event_calculate(&event); - TEST_ASSERT_INT_WITHIN(2, event.h_threshold, 2); - TEST_ASSERT_INT_WITHIN(2, event.l_threshold, 2); + TEST_ASSERT_INT_WITHIN(3, event.h_threshold, 2); + TEST_ASSERT_INT_WITHIN(3, event.l_threshold, 2); TEST_ASSERT(event.l_limit == 0); - TEST_ASSERT_INT_WITHIN(2, event.h_limit, 2); - TEST_ASSERT_INT_WITHIN(2, event.zero_times, 2); - TEST_ASSERT_INT_WITHIN(3, event.filter_time, 4); + TEST_ASSERT_INT_WITHIN(3, event.h_limit, 2); + TEST_ASSERT_INT_WITHIN(3, event.zero_times, 2); + TEST_ASSERT_INT_WITHIN(4, event.filter_time, 4); // enable the intr TEST_ESP_OK(pcnt_intr_enable(PCNT_UNIT_0)); @@ -546,24 +546,24 @@ TEST_CASE("PCNT_interrupt_method_test_control_IO_high", "[pcnt][timeout=120]") TEST_ESP_OK(pcnt_counter_clear(PCNT_UNIT_0)); TEST_ESP_OK(pcnt_counter_resume(PCNT_UNIT_0)); event_calculate(&event); - TEST_ASSERT_INT_WITHIN(2, event.h_threshold, 4); - TEST_ASSERT_INT_WITHIN(2, event.l_threshold, 4); + TEST_ASSERT_INT_WITHIN(3, event.h_threshold, 4); + TEST_ASSERT_INT_WITHIN(3, event.l_threshold, 4); TEST_ASSERT(event.l_limit == 0); - TEST_ASSERT_INT_WITHIN(2, event.h_limit, 4); - TEST_ASSERT_INT_WITHIN(2, event.zero_times, 4); - TEST_ASSERT_INT_WITHIN(3, event.filter_time, 10); + TEST_ASSERT_INT_WITHIN(3, event.h_limit, 4); + TEST_ASSERT_INT_WITHIN(3, event.zero_times, 4); + TEST_ASSERT_INT_WITHIN(4, event.filter_time, 10); // disable part of events TEST_ESP_OK(pcnt_event_disable(PCNT_UNIT_0, PCNT_EVT_ZERO)); TEST_ESP_OK(pcnt_event_disable(PCNT_UNIT_0, PCNT_EVT_L_LIM)); TEST_ESP_OK(pcnt_event_disable(PCNT_UNIT_0, PCNT_EVT_THRES_0)); event_calculate(&event); - TEST_ASSERT_INT_WITHIN(2, event.h_threshold, 5); - TEST_ASSERT_INT_WITHIN(2, event.l_threshold, 4); + TEST_ASSERT_INT_WITHIN(3, event.h_threshold, 5); + TEST_ASSERT_INT_WITHIN(3, event.l_threshold, 4); TEST_ASSERT(event.l_limit == 0); - TEST_ASSERT_INT_WITHIN(3, event.h_limit, 6); - TEST_ASSERT_INT_WITHIN(2, event.zero_times, 4); - TEST_ASSERT_INT_WITHIN(3, event.filter_time, 14); + TEST_ASSERT_INT_WITHIN(4, event.h_limit, 6); + TEST_ASSERT_INT_WITHIN(3, event.zero_times, 4); + TEST_ASSERT_INT_WITHIN(4, event.filter_time, 14); // Because this test uses its own ISR, we need to release it with `pcnt_isr_unregister` instead of `pcnt_isr_service_uninstall` TEST_ESP_OK(pcnt_isr_unregister(pcnt_isr_service)); @@ -621,24 +621,24 @@ TEST_CASE("PCNT_interrupt_method_test_control_IO_low", "[pcnt][timeout=120]") // test event event_calculate(&event); - TEST_ASSERT_INT_WITHIN(2, event.h_threshold, 1); - TEST_ASSERT_INT_WITHIN(2, event.l_threshold, 1); - TEST_ASSERT_INT_WITHIN(2, event.l_limit, 1); - TEST_ASSERT_INT_WITHIN(2, event.h_limit, 0); - TEST_ASSERT_INT_WITHIN(2, event.zero_times, 1); - TEST_ASSERT_INT_WITHIN(2, event.filter_time, 2); + TEST_ASSERT_INT_WITHIN(3, event.h_threshold, 1); + TEST_ASSERT_INT_WITHIN(3, event.l_threshold, 1); + TEST_ASSERT_INT_WITHIN(3, event.l_limit, 1); + TEST_ASSERT_INT_WITHIN(3, event.h_limit, 0); + TEST_ASSERT_INT_WITHIN(3, event.zero_times, 1); + TEST_ASSERT_INT_WITHIN(3, event.filter_time, 2); // test interrupt disable TEST_ESP_OK(pcnt_intr_disable(PCNT_UNIT_0)); TEST_ESP_OK(pcnt_counter_clear(PCNT_UNIT_0)); // for the original control io disable interrupt status event_calculate(&event); - TEST_ASSERT_INT_WITHIN(2, event.h_threshold, 1); - TEST_ASSERT_INT_WITHIN(2, event.l_threshold, 1); - TEST_ASSERT_INT_WITHIN(2, event.l_limit, 1); - TEST_ASSERT_INT_WITHIN(2, event.h_limit, 0); - TEST_ASSERT_INT_WITHIN(2, event.zero_times, 1); - TEST_ASSERT_INT_WITHIN(2, event.filter_time, 2); + TEST_ASSERT_INT_WITHIN(3, event.h_threshold, 1); + TEST_ASSERT_INT_WITHIN(3, event.l_threshold, 1); + TEST_ASSERT_INT_WITHIN(3, event.l_limit, 1); + TEST_ASSERT_INT_WITHIN(3, event.h_limit, 0); + TEST_ASSERT_INT_WITHIN(3, event.zero_times, 1); + TEST_ASSERT_INT_WITHIN(3, event.filter_time, 2); // enable the intr pcnt_unit_config(&config); @@ -648,24 +648,24 @@ TEST_CASE("PCNT_interrupt_method_test_control_IO_low", "[pcnt][timeout=120]") TEST_ESP_OK(pcnt_counter_clear(PCNT_UNIT_0)); TEST_ESP_OK(pcnt_counter_resume(PCNT_UNIT_0)); event_calculate(&event); - TEST_ASSERT_INT_WITHIN(2, event.h_threshold, 2); - TEST_ASSERT_INT_WITHIN(2, event.l_threshold, 3); - TEST_ASSERT_INT_WITHIN(2, event.l_limit, 2); - TEST_ASSERT_INT_WITHIN(2, event.h_limit, 0); - TEST_ASSERT_INT_WITHIN(2, event.zero_times, 2); - TEST_ASSERT_INT_WITHIN(2, event.filter_time, 6); + TEST_ASSERT_INT_WITHIN(3, event.h_threshold, 2); + TEST_ASSERT_INT_WITHIN(3, event.l_threshold, 3); + TEST_ASSERT_INT_WITHIN(3, event.l_limit, 2); + TEST_ASSERT_INT_WITHIN(3, event.h_limit, 0); + TEST_ASSERT_INT_WITHIN(3, event.zero_times, 2); + TEST_ASSERT_INT_WITHIN(3, event.filter_time, 6); // disable part of events TEST_ESP_OK(pcnt_event_disable(PCNT_UNIT_0, PCNT_EVT_ZERO)); TEST_ESP_OK(pcnt_event_disable(PCNT_UNIT_0, PCNT_EVT_L_LIM)); TEST_ESP_OK(pcnt_event_disable(PCNT_UNIT_0, PCNT_EVT_THRES_0)); event_calculate(&event); - TEST_ASSERT_INT_WITHIN(2, event.h_threshold, 4); - TEST_ASSERT_INT_WITHIN(2, event.l_threshold, 3); - TEST_ASSERT_INT_WITHIN(2, event.l_limit, 2); - TEST_ASSERT_INT_WITHIN(2, event.h_limit, 0); - TEST_ASSERT_INT_WITHIN(2, event.zero_times, 2); - TEST_ASSERT_INT_WITHIN(2, event.filter_time, 8); + TEST_ASSERT_INT_WITHIN(3, event.h_threshold, 4); + TEST_ASSERT_INT_WITHIN(3, event.l_threshold, 3); + TEST_ASSERT_INT_WITHIN(3, event.l_limit, 2); + TEST_ASSERT_INT_WITHIN(3, event.h_limit, 0); + TEST_ASSERT_INT_WITHIN(3, event.zero_times, 2); + TEST_ASSERT_INT_WITHIN(3, event.filter_time, 8); // Because this test uses its own ISR, we need to release it with `pcnt_isr_unregister` instead of `pcnt_isr_service_uninstall` TEST_ESP_OK(pcnt_isr_unregister(pcnt_isr_service)); diff --git a/components/efuse/esp32c2/esp_efuse_fields.c b/components/efuse/esp32c2/esp_efuse_fields.c index b40c635954e0..5f21fc9b6556 100644 --- a/components/efuse/esp32c2/esp_efuse_fields.c +++ b/components/efuse/esp32c2/esp_efuse_fields.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -46,8 +46,8 @@ esp_err_t esp_efuse_disable_rom_download_mode(void) esp_err_t esp_efuse_enable_rom_secure_download_mode(void) { - if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { - return ESP_ERR_INVALID_STATE; + if (!esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { + return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); } - return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); + return ESP_OK; } diff --git a/components/efuse/esp32c3/esp_efuse_fields.c b/components/efuse/esp32c3/esp_efuse_fields.c index b2765c7cd5d1..6e68229336d7 100644 --- a/components/efuse/esp32c3/esp_efuse_fields.c +++ b/components/efuse/esp32c3/esp_efuse_fields.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -46,8 +46,8 @@ esp_err_t esp_efuse_disable_rom_download_mode(void) esp_err_t esp_efuse_enable_rom_secure_download_mode(void) { - if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { - return ESP_ERR_INVALID_STATE; + if (!esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { + return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); } - return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); + return ESP_OK; } diff --git a/components/efuse/esp32c5/esp_efuse_fields.c b/components/efuse/esp32c5/esp_efuse_fields.c index 853fbf5ae782..a3a97c8459f0 100644 --- a/components/efuse/esp32c5/esp_efuse_fields.c +++ b/components/efuse/esp32c5/esp_efuse_fields.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -48,8 +48,8 @@ esp_err_t esp_efuse_disable_rom_download_mode(void) esp_err_t esp_efuse_enable_rom_secure_download_mode(void) { - if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { - return ESP_ERR_INVALID_STATE; + if (!esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { + return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); } - return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); + return ESP_OK; } diff --git a/components/efuse/esp32c6/esp_efuse_fields.c b/components/efuse/esp32c6/esp_efuse_fields.c index e15d9e754763..c4b3049f6d9e 100644 --- a/components/efuse/esp32c6/esp_efuse_fields.c +++ b/components/efuse/esp32c6/esp_efuse_fields.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -46,8 +46,8 @@ esp_err_t esp_efuse_disable_rom_download_mode(void) esp_err_t esp_efuse_enable_rom_secure_download_mode(void) { - if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { - return ESP_ERR_INVALID_STATE; + if (!esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { + return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); } - return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); + return ESP_OK; } diff --git a/components/efuse/esp32c61/esp_efuse_fields.c b/components/efuse/esp32c61/esp_efuse_fields.c index 8d376b672f15..2d97ae96ff3a 100644 --- a/components/efuse/esp32c61/esp_efuse_fields.c +++ b/components/efuse/esp32c61/esp_efuse_fields.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -48,8 +48,8 @@ esp_err_t esp_efuse_disable_rom_download_mode(void) esp_err_t esp_efuse_enable_rom_secure_download_mode(void) { - if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { - return ESP_ERR_INVALID_STATE; + if (!esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { + return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); } - return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); + return ESP_OK; } diff --git a/components/efuse/esp32h2/esp_efuse_fields.c b/components/efuse/esp32h2/esp_efuse_fields.c index e15d9e754763..c4b3049f6d9e 100644 --- a/components/efuse/esp32h2/esp_efuse_fields.c +++ b/components/efuse/esp32h2/esp_efuse_fields.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -46,8 +46,8 @@ esp_err_t esp_efuse_disable_rom_download_mode(void) esp_err_t esp_efuse_enable_rom_secure_download_mode(void) { - if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { - return ESP_ERR_INVALID_STATE; + if (!esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { + return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); } - return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); + return ESP_OK; } diff --git a/components/efuse/esp32p4/esp_efuse_fields.c b/components/efuse/esp32p4/esp_efuse_fields.c index 5bb0023b07f7..74f6fe22c660 100644 --- a/components/efuse/esp32p4/esp_efuse_fields.c +++ b/components/efuse/esp32p4/esp_efuse_fields.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -47,8 +47,8 @@ esp_err_t esp_efuse_disable_rom_download_mode(void) esp_err_t esp_efuse_enable_rom_secure_download_mode(void) { - if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { - return ESP_ERR_INVALID_STATE; + if (!esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { + return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); } - return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); + return ESP_OK; } diff --git a/components/efuse/esp32s2/esp_efuse_fields.c b/components/efuse/esp32s2/esp_efuse_fields.c index 618286882ab5..332c1c867e1a 100644 --- a/components/efuse/esp32s2/esp_efuse_fields.c +++ b/components/efuse/esp32s2/esp_efuse_fields.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -45,8 +45,8 @@ esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme) esp_err_t esp_efuse_enable_rom_secure_download_mode(void) { - if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { - return ESP_ERR_INVALID_STATE; + if (!esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { + return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); } - return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); + return ESP_OK; } diff --git a/components/efuse/esp32s3/esp_efuse_fields.c b/components/efuse/esp32s3/esp_efuse_fields.c index 22b16bd6ad42..537ee28aadb2 100644 --- a/components/efuse/esp32s3/esp_efuse_fields.c +++ b/components/efuse/esp32s3/esp_efuse_fields.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -45,8 +45,8 @@ esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme) esp_err_t esp_efuse_enable_rom_secure_download_mode(void) { - if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { - return ESP_ERR_INVALID_STATE; + if (!esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { + return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); } - return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); + return ESP_OK; } diff --git a/components/efuse/include/esp_efuse.h b/components/efuse/include/esp_efuse.h index d18348fe4734..fe864dbda9a2 100644 --- a/components/efuse/include/esp_efuse.h +++ b/components/efuse/include/esp_efuse.h @@ -351,11 +351,12 @@ esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme); * * @note If Secure Download mode is already enabled, this function does nothing and returns success. * - * @note Disabling the ROM Download Mode also disables Secure Download Mode. + * @note If UART DL mode is completely disabled then Secure Download mode can not be enabled + * and this API simply returns success. * * @return - * - ESP_OK If the eFuse was successfully burned, or had already been burned. - * - ESP_ERR_INVALID_STATE ROM Download Mode has been disabled via eFuse, so Secure Download mode is unavailable. + * - ESP_OK If the eFuse was successfully burned, or had already been burned, or UART DL mode is already disabled. + * - Other errors If an error occurred while burning ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD. */ esp_err_t esp_efuse_enable_rom_secure_download_mode(void); #endif diff --git a/components/efuse/linux/esp_efuse_fields.c b/components/efuse/linux/esp_efuse_fields.c index dc675d6ab9a3..537ee28aadb2 100644 --- a/components/efuse/linux/esp_efuse_fields.c +++ b/components/efuse/linux/esp_efuse_fields.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -45,8 +45,8 @@ esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme) esp_err_t esp_efuse_enable_rom_secure_download_mode(void) { - if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { - return ESP_ERR_INVALID_STATE; + if (!esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { + return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); } - return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); + return ESP_OK; } diff --git a/components/esp_coex/include/esp_coex_i154.h b/components/esp_coex/include/esp_coex_i154.h index d601205ebe79..f817e901400a 100644 --- a/components/esp_coex/include/esp_coex_i154.h +++ b/components/esp_coex/include/esp_coex_i154.h @@ -6,6 +6,9 @@ #ifndef __COEXIST_I154_H__ #define __COEXIST_I154_H__ +/** + * @brief 802.15.4 coex event + */ typedef enum { IEEE802154_HIGH = 1, IEEE802154_MIDDLE, @@ -14,16 +17,50 @@ typedef enum { IEEE802154_EVENT_MAX, } ieee802154_coex_event_t; +/** + * @brief 802.15.4 coexistence configurations + */ typedef struct { ieee802154_coex_event_t idle; ieee802154_coex_event_t txrx; ieee802154_coex_event_t txrx_at; } esp_ieee802154_coex_config_t; +/** + * @brief Set 802.15.4 tx/rx pti + * @param 802.15.4 coexistence event + */ void esp_coex_ieee802154_txrx_pti_set(ieee802154_coex_event_t event); + +/** + * @brief Set 802.15.4 ack pti + * @param 802.15.4 coexistence event + */ void esp_coex_ieee802154_ack_pti_set(ieee802154_coex_event_t event); + +/** + * @brief Indicate that a coexistence break occurred in 802.15.4 + */ void esp_coex_ieee802154_coex_break_notify(void); + +/** + * @brief Enter the TX stage for 802.15.4 external coexistence handling + */ void esp_coex_ieee802154_extcoex_tx_stage(void); + +/** + * @brief Enter the RX stage for 802.15.4 external coexistence handling + */ void esp_coex_ieee802154_extcoex_rx_stage(void); +/** + * @brief Enable the 802.15.4 status for coexistence + */ +void esp_coex_ieee802154_status_enable(void); + +/** + * @brief Disable the 802.15.4 status for coexistence + */ +void esp_coex_ieee802154_status_disable(void); + #endif diff --git a/components/esp_coex/include/private/esp_coexist_internal.h b/components/esp_coex/include/private/esp_coexist_internal.h index 6e3799487f08..026f1f9fe0ab 100644 --- a/components/esp_coex/include/private/esp_coexist_internal.h +++ b/components/esp_coex/include/private/esp_coexist_internal.h @@ -32,6 +32,8 @@ typedef enum { COEX_SCHM_ST_TYPE_WIFI = 0, COEX_SCHM_ST_TYPE_BLE, COEX_SCHM_ST_TYPE_BT, + COEX_SCHM_ST_TYPE_EXTERNAL_COEX, + COEX_SCHM_ST_TYPE_I154, } coex_schm_st_type_t; #define COEX_STATUS_GET_WIFI_BITMAP (1 << COEX_SCHM_ST_TYPE_WIFI) diff --git a/components/esp_coex/lib b/components/esp_coex/lib index 2d68674e3d52..adb3badffe12 160000 --- a/components/esp_coex/lib +++ b/components/esp_coex/lib @@ -1 +1 @@ -Subproject commit 2d68674e3d522fb025e4666217f9cc1ca2af9399 +Subproject commit adb3badffe1201033d23c0a3ab596faadd673539 diff --git a/components/esp_coex/src/coexist.c b/components/esp_coex/src/coexist.c index a723fd5a73aa..22d482c7e849 100644 --- a/components/esp_coex/src/coexist.c +++ b/components/esp_coex/src/coexist.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -21,6 +21,10 @@ #include "esp_private/esp_modem_clock.h" #endif +#if CONFIG_ESP_COEX_SW_COEXIST_ENABLE && CONFIG_SOC_IEEE802154_SUPPORTED +#include "esp_coex_i154.h" +#endif + #if SOC_EXTERNAL_COEX_ADVANCE #define EXTERNAL_COEX_SIGNAL_I0_IDX EXTERN_ACTIVE_I_IDX #define EXTERNAL_COEX_SIGNAL_I1_IDX EXTERN_PRIORITY_I_IDX @@ -289,7 +293,7 @@ esp_err_t esp_coex_wifi_i154_enable(void) // TODO: Add a scheme for wifi and 154 coex. // Remove this function if FCC-50 closes. coex_enable(); - coex_schm_status_bit_set(1, 1); + esp_coex_ieee802154_status_enable(); return ESP_OK; } #endif diff --git a/components/esp_coex/src/lib_printf.c b/components/esp_coex/src/lib_printf.c index 265874399f2a..deba7289126d 100644 --- a/components/esp_coex/src/lib_printf.c +++ b/components/esp_coex/src/lib_printf.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2016-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -38,13 +38,15 @@ static int lib_printf(const char* tag, const char* format, va_list arg) if (i > 0) { ESP_LOGI(tag, "%s", temp); } - va_end(arg); return len; } int coexist_printf(const char* format, ...) { va_list arg; + /* coverity[uninit_use_in_call] + Event uninit_use_in_call: Using uninitialized value arg when calling __builtin_c23_va_start. + False-positive: arg will be initialized in the function va_start() */ va_start(arg, format); int res = lib_printf("coexist", format, arg); va_end(arg); diff --git a/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr_etm.c b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr_etm.c index ecb473e390e5..47dba582872e 100644 --- a/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr_etm.c +++ b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr_etm.c @@ -153,13 +153,16 @@ TEST_CASE("ana_cmpr etm event", "[ana_cmpr][etm]") esp_rom_delay_us(TEST_TIME_US); gpio_set_level(src_gpio, 1); + // the gptimer should already stopped, so delay any time here is ok + vTaskDelay(10); + uint64_t cnt_us = 0; TEST_ESP_OK(gptimer_get_raw_count(gptimer, &cnt_us)); printf("Count: %" PRIu64 "\n", cnt_us); // gptimer timer should stopped uint64_t cnt_us_again = 0; TEST_ESP_OK(gptimer_get_raw_count(gptimer, &cnt_us_again)); - TEST_ASSERT(cnt_us_again == cnt_us); + TEST_ASSERT_EQUAL(cnt_us, cnt_us_again); test_ana_cmpr_deinit_etm(handles); test_ana_cmpr_deinit(cmpr); diff --git a/components/esp_driver_gpio/src/rtc_io.c b/components/esp_driver_gpio/src/rtc_io.c index 244d3b1282f6..9366b7a19d47 100644 --- a/components/esp_driver_gpio/src/rtc_io.c +++ b/components/esp_driver_gpio/src/rtc_io.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,6 +18,9 @@ #include "hal/rtc_io_hal.h" #include "soc/rtc_io_periph.h" #include "soc/soc_caps.h" +#if SOC_LP_GPIO_MATRIX_SUPPORTED +#include "soc/lp_gpio_pins.h" +#endif static const char __attribute__((__unused__)) *RTCIO_TAG = "RTCIO"; @@ -183,8 +186,14 @@ esp_err_t rtc_gpio_iomux_func_sel(gpio_num_t gpio_num, int func) #if SOC_LP_GPIO_MATRIX_SUPPORTED esp_err_t lp_gpio_connect_in_signal(gpio_num_t gpio_num, uint32_t signal_idx, bool inv) { - ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "LP_IO number error"); - rtcio_hal_matrix_in(rtc_io_number_get(gpio_num), signal_idx, inv); + uint32_t io_num; + if (gpio_num == LP_GPIO_MATRIX_CONST_ZERO_INPUT || gpio_num == LP_GPIO_MATRIX_CONST_ONE_INPUT) { + io_num = gpio_num; + } else { + ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "LP_IO number error"); + io_num = rtc_io_number_get(gpio_num); + } + rtcio_hal_matrix_in(io_num, signal_idx, inv); return ESP_OK; } diff --git a/components/esp_driver_i2c/i2c_common.c b/components/esp_driver_i2c/i2c_common.c index 01c506c55ec5..ac0c38bf460b 100644 --- a/components/esp_driver_i2c/i2c_common.c +++ b/components/esp_driver_i2c/i2c_common.c @@ -445,10 +445,12 @@ esp_err_t i2c_common_deinit_pins(i2c_bus_handle_t handle) esp_gpio_revoke(BIT64(handle->scl_num)); if (handle->is_lp_i2c == false) { - ESP_RETURN_ON_ERROR(gpio_output_disable(handle->sda_num), TAG, "disable i2c pins failed"); + gpio_od_disable(handle->sda_num); + gpio_output_disable(handle->sda_num); esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, i2c_periph_signal[port_id].sda_in_sig, 0); - ESP_RETURN_ON_ERROR(gpio_output_disable(handle->scl_num), TAG, "disable i2c pins failed"); + gpio_od_disable(handle->scl_num); + gpio_output_disable(handle->scl_num); esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, i2c_periph_signal[port_id].scl_in_sig, 0); } #if SOC_LP_I2C_SUPPORTED @@ -456,8 +458,8 @@ esp_err_t i2c_common_deinit_pins(i2c_bus_handle_t handle) ESP_RETURN_ON_ERROR(rtc_gpio_deinit(handle->sda_num), TAG, "deinit rtc gpio failed"); ESP_RETURN_ON_ERROR(rtc_gpio_deinit(handle->scl_num), TAG, "deinit rtc gpio failed"); #if SOC_LP_GPIO_MATRIX_SUPPORTED - lp_gpio_connect_in_signal(LP_GPIO_MATRIX_CONST_ZERO_INPUT, i2c_periph_signal[port_id].scl_in_sig, 0); - lp_gpio_connect_in_signal(LP_GPIO_MATRIX_CONST_ZERO_INPUT, i2c_periph_signal[port_id].sda_in_sig, 0); + ESP_RETURN_ON_ERROR(lp_gpio_connect_in_signal(LP_GPIO_MATRIX_CONST_ZERO_INPUT, i2c_periph_signal[port_id].scl_in_sig, 0), TAG, "failed to connect lp gpio to zero"); + ESP_RETURN_ON_ERROR(lp_gpio_connect_in_signal(LP_GPIO_MATRIX_CONST_ZERO_INPUT, i2c_periph_signal[port_id].sda_in_sig, 0), TAG, "failed to connect lp gpio to zero"); #endif } #endif diff --git a/components/esp_driver_i2c/i2c_master.c b/components/esp_driver_i2c/i2c_master.c index 4cfb10fb284f..6f6bd85c905b 100644 --- a/components/esp_driver_i2c/i2c_master.c +++ b/components/esp_driver_i2c/i2c_master.c @@ -814,7 +814,7 @@ static esp_err_t i2c_master_bus_destroy(i2c_master_bus_handle_t bus_handle) i2c_master_bus_handle_t i2c_master = bus_handle; esp_err_t err = ESP_OK; if (i2c_master->base) { - i2c_common_deinit_pins(i2c_master->base); + ESP_RETURN_ON_ERROR(i2c_common_deinit_pins(i2c_master->base), TAG, "failed to deinit i2c pins"); err = i2c_release_bus_handle(i2c_master->base); } if (err == ESP_OK) { @@ -1218,7 +1218,7 @@ esp_err_t i2c_master_transmit(i2c_master_dev_handle_t i2c_dev, const uint8_t *wr ESP_RETURN_ON_FALSE((write_buffer != NULL) && (write_size > 0), ESP_ERR_INVALID_ARG, TAG, "i2c transmit buffer or size invalid"); i2c_master_transmit_multi_buffer_info_t buffer_info[1] = { - {.write_buffer = (uint8_t*)write_buffer, .buffer_size = write_size}, + {.write_buffer = write_buffer, .buffer_size = write_size}, }; return i2c_master_multi_buffer_transmit(i2c_dev, buffer_info, 1, xfer_timeout_ms); } diff --git a/components/esp_driver_i2c/include/driver/i2c_master.h b/components/esp_driver_i2c/include/driver/i2c_master.h index 528a877ca8ea..c0a09b4253d1 100644 --- a/components/esp_driver_i2c/include/driver/i2c_master.h +++ b/components/esp_driver_i2c/include/driver/i2c_master.h @@ -90,7 +90,7 @@ typedef struct { * @brief I2C master transmit buffer information structure */ typedef struct { - uint8_t *write_buffer; /*!< Pointer to buffer to be written. */ + const uint8_t *write_buffer; /*!< Pointer to buffer to be written. */ size_t buffer_size; /*!< Size of data to be written. */ } i2c_master_transmit_multi_buffer_info_t; diff --git a/components/esp_driver_jpeg/include/driver/jpeg_types.h b/components/esp_driver_jpeg/include/driver/jpeg_types.h index 08ab102951e9..5959e688f6b8 100644 --- a/components/esp_driver_jpeg/include/driver/jpeg_types.h +++ b/components/esp_driver_jpeg/include/driver/jpeg_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,6 +8,8 @@ #include #include "hal/color_types.h" +#include "sdkconfig.h" +#include "soc/soc_caps.h" #ifdef __cplusplus extern "C" { @@ -57,6 +59,10 @@ typedef enum { JPEG_ENCODE_IN_FORMAT_RGB565 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565), /*!< input RGB565 format */ JPEG_ENCODE_IN_FORMAT_GRAY = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< input GRAY format */ JPEG_ENCODE_IN_FORMAT_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< input YUV422 format */ +#if !(CONFIG_ESP_REV_MIN_FULL < 300 && CONFIG_IDF_TARGET_ESP32P4) // Invisible for unsupported chips + JPEG_ENCODE_IN_FORMAT_YUV444 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV444), /*!< input YUV444 format */ + JPEG_ENCODE_IN_FORMAT_YUV420 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV420), /*!< input YUV420 format */ +#endif } jpeg_enc_input_format_t; /** diff --git a/components/esp_driver_jpeg/jpeg_encode.c b/components/esp_driver_jpeg/jpeg_encode.c index e57d62d25aef..8107ea69da34 100644 --- a/components/esp_driver_jpeg/jpeg_encode.c +++ b/components/esp_driver_jpeg/jpeg_encode.c @@ -183,6 +183,16 @@ esp_err_t jpeg_encoder_process(jpeg_encoder_handle_t encoder_engine, const jpeg_ encoder_engine->color_space = JPEG_ENC_SRC_YUV422; best_hb_idx = JPEG_ENC_SRC_YUV422_HB; break; +#if !(CONFIG_ESP_REV_MIN_FULL < 300 && CONFIG_IDF_TARGET_ESP32P4) + case JPEG_ENCODE_IN_FORMAT_YUV444: + encoder_engine->color_space = JPEG_ENC_SRC_YUV444; + best_hb_idx = JPEG_ENC_SRC_YUV444_HB; + break; + case JPEG_ENCODE_IN_FORMAT_YUV420: + encoder_engine->color_space = JPEG_ENC_SRC_YUV420; + best_hb_idx = JPEG_ENC_SRC_YUV420_HB; + break; +#endif default: ESP_LOGE(TAG, "wrong, we don't support encode from such format."); ret = ESP_ERR_NOT_SUPPORTED; diff --git a/components/esp_driver_jpeg/jpeg_param.c b/components/esp_driver_jpeg/jpeg_param.c index eb09925dd5d5..380c2c614e8f 100644 --- a/components/esp_driver_jpeg/jpeg_param.c +++ b/components/esp_driver_jpeg/jpeg_param.c @@ -57,7 +57,9 @@ const uint32_t enc_hb_tbl[JPEG_ENC_BEST_HB_MAX][JPEG_DOWN_SAMPLING_NUM] = { {40, 32, 32, 0}, {0, 64, 0, 0}, {64, 64, 48, 0}, - {0, 0, 0, 128} + {0, 0, 0, 128}, + {40, 0, 0, 0}, + {0, 0, 48, 0}, }; /** diff --git a/components/esp_driver_jpeg/jpeg_parse_marker.c b/components/esp_driver_jpeg/jpeg_parse_marker.c index cafaabc9e326..4dcc607cb2b9 100644 --- a/components/esp_driver_jpeg/jpeg_parse_marker.c +++ b/components/esp_driver_jpeg/jpeg_parse_marker.c @@ -20,6 +20,11 @@ static const char *TAG = "jpeg.decoder"; static uint8_t jpeg_get_char(jpeg_dec_header_info_t *header_info) { + // Check if there are bytes left to read before decrementing buffer_left + if (header_info->buffer_left == 0) { + ESP_LOGE(TAG, "Buffer underflow detected in jpeg_get_char: no more bytes left to read"); + return 0; + } uint8_t c = header_info->buffer_offset[0]; header_info->buffer_offset++; header_info->header_size++; @@ -39,20 +44,26 @@ uint32_t jpeg_get_bytes(jpeg_dec_header_info_t *header_info, uint8_t num_bytes) esp_err_t jpeg_parse_appn_marker(jpeg_dec_header_info_t *header_info) { - uint32_t skip_num = jpeg_get_bytes(header_info, 2); - header_info->buffer_offset += (skip_num - 2); - header_info->header_size += (skip_num - 2); - header_info->buffer_left -= (skip_num - 2); + uint16_t skip_num = jpeg_get_bytes(header_info, 2); + ESP_RETURN_ON_FALSE(skip_num >= 2, ESP_ERR_INVALID_ARG, TAG, "Invalid APPn marker length: %d", skip_num); + uint16_t bytes_to_skip = skip_num - 2; + ESP_RETURN_ON_FALSE(header_info->buffer_left >= bytes_to_skip, ESP_ERR_INVALID_ARG, TAG, "APPn marker data underflow for buffer_left"); + header_info->buffer_offset += bytes_to_skip; + header_info->header_size += bytes_to_skip; + header_info->buffer_left -= bytes_to_skip; return ESP_OK; } esp_err_t jpeg_parse_com_marker(jpeg_dec_header_info_t *header_info) { - uint32_t skip_num = jpeg_get_bytes(header_info, 2); - header_info->buffer_offset += (skip_num - 2); - header_info->header_size += (skip_num - 2); - header_info->buffer_left -= (skip_num - 2); + uint16_t skip_num = jpeg_get_bytes(header_info, 2); + ESP_RETURN_ON_FALSE(skip_num >= 2, ESP_ERR_INVALID_ARG, TAG, "Invalid COM marker length: %d", skip_num); + uint32_t bytes_to_skip = skip_num - 2; + ESP_RETURN_ON_FALSE(header_info->header_size >= bytes_to_skip, ESP_ERR_INVALID_ARG, TAG, "COM marker data underflow for header_size"); + header_info->buffer_offset += bytes_to_skip; + header_info->header_size += bytes_to_skip; + header_info->buffer_left -= bytes_to_skip; return ESP_OK; } @@ -61,21 +72,25 @@ esp_err_t jpeg_parse_dqt_marker(jpeg_dec_header_info_t *header_info) uint32_t n = 0, i = 0, prec = 0; uint32_t temp = 0; - uint32_t length_num = jpeg_get_bytes(header_info, 2); + uint16_t length_num = jpeg_get_bytes(header_info, 2); + ESP_RETURN_ON_FALSE(length_num >= 2, ESP_ERR_INVALID_ARG, TAG, "Invalid DQT marker length: %d", length_num); length_num -= 2; while (length_num) { n = jpeg_get_bytes(header_info, 1); prec = n >> 4; n &= 0x0F; + ESP_RETURN_ON_FALSE(length_num >= 1, ESP_ERR_INVALID_ARG, TAG, "DQT marker length error: %d", length_num); length_num -= 1; // read quantization entries, in zig-zag order for (i = 0; i < 64; i++) { temp = jpeg_get_bytes(header_info, 1); + ESP_RETURN_ON_FALSE(length_num >= 1, ESP_ERR_INVALID_ARG, TAG, "DQT marker length error: %d", length_num); length_num -= 1; if (prec) { temp = (temp << 8) + jpeg_get_bytes(header_info, 1); + ESP_RETURN_ON_FALSE(length_num >= 1, ESP_ERR_INVALID_ARG, TAG, "DQT marker length error: %d", length_num); length_num -= 1; } header_info->qt_tbl[n][zigzag_arr[i]] = temp; @@ -142,7 +157,10 @@ esp_err_t jpeg_parse_sof_marker(jpeg_dec_header_info_t *header_info) esp_err_t jpeg_parse_dht_marker(jpeg_dec_header_info_t *header_info) { // Recording num_left in DHT sector, not including length bytes (2 bytes). - uint32_t num_left = jpeg_get_bytes(header_info, 2) - 2; + uint16_t raw_length = jpeg_get_bytes(header_info, 2); + // Check for integer underflow before subtraction + ESP_RETURN_ON_FALSE(raw_length >= 2, ESP_ERR_INVALID_ARG, TAG, "Invalid DHT marker length: %d", raw_length); + uint16_t num_left = raw_length - 2; while (num_left) { uint32_t np = 0; @@ -159,6 +177,8 @@ esp_err_t jpeg_parse_dht_marker(jpeg_dec_header_info_t *header_info) header_info->huffcode[header_info->huffinfo.type][header_info->huffinfo.id][i] = jpeg_get_bytes(header_info, 1); } + // Check for integer underflow before subtraction + ESP_RETURN_ON_FALSE(num_left >= (JPEG_HUFFMAN_BITS_LEN_TABLE_LEN + np + 1), ESP_ERR_INVALID_ARG, TAG, "DHT marker data underflow after parsing huffcode: %d", num_left); num_left -= (1 + JPEG_HUFFMAN_BITS_LEN_TABLE_LEN + np); } @@ -181,6 +201,7 @@ esp_err_t jpeg_parse_dri_marker(jpeg_dec_header_info_t *header_info) esp_err_t jpeg_parse_sos_marker(jpeg_dec_header_info_t *header_info) { // Got the SOS marker, but need to recover this and feed to 2DDMA. + ESP_RETURN_ON_FALSE(header_info->header_size >= 2, ESP_ERR_INVALID_ARG, TAG, "SOS marker header_size underflow"); header_info->buffer_offset -= 2; header_info->header_size -= 2; header_info->buffer_left += 2; @@ -191,6 +212,7 @@ esp_err_t jpeg_parse_inv_marker(jpeg_dec_header_info_t *header_info) { // Got invalid 0xFFFF, (followed by a valid marker type) // Go one byte back, to skip the first 0xFF + ESP_RETURN_ON_FALSE(header_info->header_size >= 1, ESP_ERR_INVALID_ARG, TAG, "INV marker header_size underflow"); header_info->buffer_offset--; header_info->header_size--; header_info->buffer_left++; diff --git a/components/esp_driver_jpeg/jpeg_private.h b/components/esp_driver_jpeg/jpeg_private.h index aa409ff837e1..56345cfd0545 100644 --- a/components/esp_driver_jpeg/jpeg_private.h +++ b/components/esp_driver_jpeg/jpeg_private.h @@ -131,6 +131,8 @@ typedef enum { JPEG_ENC_SRC_YUV422_HB = 1, // Input YUV422 format JPEG_ENC_SRC_RGB565_HB = 2, // Input RGB565 format JPEG_ENC_SRC_GRAY_HB = 3, // Input GRAY format + JPEG_ENC_SRC_YUV444_HB = 4, // Input YUV444 format + JPEG_ENC_SRC_YUV420_HB = 5, // Input YUV420 format JPEG_ENC_BEST_HB_MAX, } jpeg_enc_format_hb_t; diff --git a/components/esp_driver_mcpwm/src/mcpwm_com.c b/components/esp_driver_mcpwm/src/mcpwm_com.c index 3636aeadef1b..0f8fe2b8902a 100644 --- a/components/esp_driver_mcpwm/src/mcpwm_com.c +++ b/components/esp_driver_mcpwm/src/mcpwm_com.c @@ -262,12 +262,12 @@ esp_err_t mcpwm_set_prescale(mcpwm_group_t *group, uint32_t expect_module_resolu } module_prescale = fit_module_prescale; group_prescale = fit_group_prescale; + ESP_RETURN_ON_FALSE(group_prescale > 0 && group_prescale <= MCPWM_LL_MAX_GROUP_PRESCALE, ESP_ERR_INVALID_STATE, TAG, + "set group prescale failed, group clock cannot match the resolution"); group_resolution_hz = periph_src_clk_hz / group_prescale; } ESP_LOGD(TAG, "group (%d) calc prescale:%"PRIu32", module calc prescale:%"PRIu32"", group_id, group_prescale, module_prescale); - ESP_RETURN_ON_FALSE(group_prescale > 0 && group_prescale <= MCPWM_LL_MAX_GROUP_PRESCALE, ESP_ERR_INVALID_STATE, TAG, - "set group prescale failed, group clock cannot match the resolution"); // check if we need to update the group prescale, group prescale is shared by all mcpwm modules bool prescale_conflict = false; diff --git a/components/esp_driver_parlio/src/parlio_tx.c b/components/esp_driver_parlio/src/parlio_tx.c index f16c4f0edc2b..368de35ee091 100644 --- a/components/esp_driver_parlio/src/parlio_tx.c +++ b/components/esp_driver_parlio/src/parlio_tx.c @@ -223,7 +223,6 @@ static esp_err_t parlio_tx_unit_init_dma(parlio_tx_unit_t *tx_unit, const parlio size_t buffer_alignment = MAX(tx_unit->int_mem_align, tx_unit->ext_mem_align); size_t num_dma_nodes = esp_dma_calculate_node_count(config->max_transfer_size, buffer_alignment, DMA_DESCRIPTOR_BUFFER_MAX_SIZE); gdma_link_list_config_t dma_link_config = { - .buffer_alignment = buffer_alignment, .item_alignment = PARLIO_DMA_DESC_ALIGNMENT, .num_items = num_dma_nodes, }; @@ -469,8 +468,10 @@ static void IRAM_ATTR parlio_tx_do_transaction(parlio_tx_unit_t *tx_unit, parlio } // DMA transfer data based on bytes not bits, so convert the bit length to bytes, round up + size_t buffer_alignment = esp_ptr_internal(t->payload) ? tx_unit->int_mem_align : tx_unit->ext_mem_align; gdma_buffer_mount_config_t mount_config = { .buffer = (void *)t->payload, + .buffer_alignment = buffer_alignment, .length = (t->payload_bits + 7) / 8, .flags = { .mark_eof = true, diff --git a/components/esp_driver_rmt/src/rmt_common.c b/components/esp_driver_rmt/src/rmt_common.c index 066df4f1a420..d01cfc6b34f7 100644 --- a/components/esp_driver_rmt/src/rmt_common.c +++ b/components/esp_driver_rmt/src/rmt_common.c @@ -242,15 +242,9 @@ esp_err_t rmt_select_periph_clock(rmt_channel_handle_t chan, rmt_clock_source_t // if the CPU frequency goes down, the transfer+encoding scheme could be unstable because CPU can't fill the data in time // so, choose ESP_PM_CPU_FREQ_MAX lock for non-dma mode // otherwise, chose lock type based on the clock source + // note, even if the clock source is APB, we still use CPU_FREQ_MAX lock to ensure the stability of the RMT operation. esp_pm_lock_type_t pm_lock_type = chan->dma_chan ? ESP_PM_NO_LIGHT_SLEEP : ESP_PM_CPU_FREQ_MAX; -#if SOC_RMT_SUPPORT_APB - if (clk_src == RMT_CLK_SRC_APB) { - // APB clock frequency can be changed during DFS - pm_lock_type = ESP_PM_APB_FREQ_MAX; - } -#endif // SOC_RMT_SUPPORT_APB - sprintf(chan->pm_lock_name, "rmt_%d_%d", group->group_id, chan->channel_id); // e.g. rmt_0_0 ret = esp_pm_lock_create(pm_lock_type, 0, chan->pm_lock_name, &chan->pm_lock); ESP_RETURN_ON_ERROR(ret, TAG, "create pm lock failed"); diff --git a/components/esp_driver_rmt/src/rmt_rx.c b/components/esp_driver_rmt/src/rmt_rx.c index 32aa19b67e21..86c88603b90e 100644 --- a/components/esp_driver_rmt/src/rmt_rx.c +++ b/components/esp_driver_rmt/src/rmt_rx.c @@ -39,7 +39,7 @@ static void rmt_rx_default_isr(void *args); #if SOC_RMT_SUPPORT_DMA static bool rmt_dma_rx_one_block_cb(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data); -static void rmt_rx_mount_dma_buffer(rmt_rx_channel_t *rx_chan, const void *buffer, size_t buffer_size, size_t per_block_size, size_t last_block_size) +static void rmt_rx_mount_dma_buffer(rmt_rx_channel_t *rx_chan, const void *buffer, size_t buffer_size, size_t mem_alignment, size_t per_block_size, size_t last_block_size) { uint8_t *data = (uint8_t *)buffer; for (int i = 0; i < rx_chan->num_dma_nodes; i++) { @@ -207,8 +207,8 @@ esp_err_t rmt_new_rx_channel(const rmt_rx_channel_config_t *config, rmt_channel_ ESP_RETURN_ON_FALSE(config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "not able to power down in light sleep"); #endif // SOC_RMT_SUPPORT_SLEEP_RETENTION - // malloc channel memory - uint32_t mem_caps = RMT_MEM_ALLOC_CAPS; + // allocate channel memory from internal memory because it contains atomic variable + uint32_t mem_caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT; rx_channel = heap_caps_calloc(1, sizeof(rmt_rx_channel_t), mem_caps); ESP_GOTO_ON_FALSE(rx_channel, ESP_ERR_NO_MEM, err, TAG, "no mem for rx channel"); // gpio is not configured yet @@ -219,7 +219,7 @@ esp_err_t rmt_new_rx_channel(const rmt_rx_channel_config_t *config, rmt_channel_ size_t num_dma_nodes = 0; if (config->flags.with_dma) { // DMA descriptors must be placed in internal SRAM - mem_caps |= MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA; + mem_caps |= MALLOC_CAP_DMA; num_dma_nodes = config->mem_block_symbols * sizeof(rmt_symbol_word_t) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE + 1; num_dma_nodes = MAX(2, num_dma_nodes); // at least 2 DMA nodes for ping-pong rmt_dma_descriptor_t *dma_nodes = heap_caps_aligned_calloc(RMT_DMA_DESC_ALIGN, num_dma_nodes, sizeof(rmt_dma_descriptor_t), mem_caps); @@ -436,7 +436,7 @@ esp_err_t rmt_receive(rmt_channel_handle_t channel, void *buffer, size_t buffer_ size_t per_dma_block_size = buffer_size / rx_chan->num_dma_nodes; per_dma_block_size = ALIGN_DOWN(per_dma_block_size, mem_alignment); size_t last_dma_block_size = buffer_size - per_dma_block_size * (rx_chan->num_dma_nodes - 1); - rmt_rx_mount_dma_buffer(rx_chan, buffer, buffer_size, per_dma_block_size, last_dma_block_size); + rmt_rx_mount_dma_buffer(rx_chan, buffer, buffer_size, mem_alignment, per_dma_block_size, last_dma_block_size); gdma_reset(channel->dma_chan); gdma_start(channel->dma_chan, (intptr_t)rx_chan->dma_nodes); // note, we must use the cached descriptor address to start the DMA } diff --git a/components/esp_driver_rmt/src/rmt_tx.c b/components/esp_driver_rmt/src/rmt_tx.c index 782d8fed6dca..18a6e98d4ad7 100644 --- a/components/esp_driver_rmt/src/rmt_tx.c +++ b/components/esp_driver_rmt/src/rmt_tx.c @@ -272,8 +272,8 @@ esp_err_t rmt_new_tx_channel(const rmt_tx_channel_config_t *config, rmt_channel_ ESP_RETURN_ON_FALSE(config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "not able to power down in light sleep"); #endif // SOC_RMT_SUPPORT_SLEEP_RETENTION - // malloc channel memory - uint32_t mem_caps = RMT_MEM_ALLOC_CAPS; + // allocate channel memory from internal memory because it contains atomic variable + uint32_t mem_caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT; tx_channel = heap_caps_calloc(1, sizeof(rmt_tx_channel_t) + sizeof(rmt_tx_trans_desc_t) * config->trans_queue_depth, mem_caps); ESP_GOTO_ON_FALSE(tx_channel, ESP_ERR_NO_MEM, err, TAG, "no mem for tx channel"); // GPIO configuration is not done yet @@ -281,7 +281,7 @@ esp_err_t rmt_new_tx_channel(const rmt_tx_channel_config_t *config, rmt_channel_ // create DMA descriptors if (config->flags.with_dma) { // DMA descriptors must be placed in internal SRAM - mem_caps |= MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA; + mem_caps |= MALLOC_CAP_DMA; rmt_dma_descriptor_t *dma_nodes = heap_caps_aligned_calloc(RMT_DMA_DESC_ALIGN, RMT_DMA_NODES_PING_PONG, sizeof(rmt_dma_descriptor_t), mem_caps); ESP_GOTO_ON_FALSE(dma_nodes, ESP_ERR_NO_MEM, err, TAG, "no mem for tx DMA nodes"); tx_channel->dma_nodes = dma_nodes; @@ -542,7 +542,7 @@ esp_err_t rmt_transmit(rmt_channel_handle_t channel, rmt_encoder_t *encoder, con ESP_RETURN_ON_FALSE(channel && encoder && payload && payload_bytes && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); ESP_RETURN_ON_FALSE(channel->direction == RMT_CHANNEL_DIRECTION_TX, ESP_ERR_INVALID_ARG, TAG, "invalid channel direction"); #if !SOC_RMT_SUPPORT_TX_LOOP_COUNT - ESP_RETURN_ON_FALSE(config->loop_count <= 0, ESP_ERR_NOT_SUPPORTED, TAG, "loop count is not supported"); + ESP_RETURN_ON_FALSE(config->loop_count <= 1, ESP_ERR_NOT_SUPPORTED, TAG, "loop count is not supported"); #endif // !SOC_RMT_SUPPORT_TX_LOOP_COUNT #if CONFIG_RMT_ISR_IRAM_SAFE // payload is retrieved by the encoder, we should make sure it's still accessible even when the cache is disabled @@ -567,7 +567,8 @@ esp_err_t rmt_transmit(rmt_channel_handle_t channel, rmt_encoder_t *encoder, con t->encoder = encoder; t->payload = payload; t->payload_bytes = payload_bytes; - t->loop_count = config->loop_count; + // treat loop_count == 1 as no loop + t->loop_count = config->loop_count == 1 ? 0 : config->loop_count; t->remain_loop_count = t->loop_count; t->flags.eot_level = config->flags.eot_level; @@ -661,19 +662,21 @@ static size_t IRAM_ATTR rmt_encode_check_result(rmt_tx_channel_t *tx_chan, rmt_t rmt_encode_state_t encode_state = RMT_ENCODING_RESET; rmt_encoder_handle_t encoder = t->encoder; size_t encoded_symbols = encoder->encode(encoder, &tx_chan->base, t->payload, t->payload_bytes, &encode_state); + bool is_mem_full = encode_state & RMT_ENCODING_MEM_FULL; if (encode_state & RMT_ENCODING_COMPLETE) { t->flags.encoding_done = true; // inserting EOF symbol if there's extra space - if (!(encode_state & RMT_ENCODING_MEM_FULL)) { + if (!is_mem_full) { rmt_tx_mark_eof(tx_chan); encoded_symbols += 1; } } - // for loop transaction, the memory block should accommodate all encoded RMT symbols + // for loop transaction, the memory block should accommodate all encoded RMT symbols and an extra EOF symbol if (t->loop_count != 0) { - if (unlikely(encoded_symbols > tx_chan->base.mem_block_num * SOC_RMT_MEM_WORDS_PER_CHANNEL)) { + size_t limit_symbols = tx_chan->base.mem_block_num * SOC_RMT_MEM_WORDS_PER_CHANNEL; + if (unlikely(encoded_symbols > limit_symbols || (encoded_symbols == limit_symbols && is_mem_full))) { ESP_DRAM_LOGE(TAG, "encoding artifacts can't exceed hw memory block for loop transmission"); } } @@ -838,7 +841,7 @@ static esp_err_t rmt_tx_disable(rmt_channel_handle_t channel) #if !SOC_RMT_SUPPORT_ASYNC_STOP // we do a trick to stop the undergoing transmission // stop interrupt, insert EOF marker to the RMT memory, polling the trans_done event - channel->hw_mem_base[0].val = 0; + memset(channel->hw_mem_base, 0, channel->mem_block_num * SOC_RMT_MEM_WORDS_PER_CHANNEL * sizeof(rmt_symbol_word_t)); while (!(rmt_ll_tx_get_interrupt_status_raw(hal->regs, channel_id) & RMT_LL_EVENT_TX_DONE(channel_id))) {} #endif rmt_ll_clear_interrupt_status(hal->regs, RMT_LL_EVENT_TX_MASK(channel_id)); diff --git a/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c b/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c index 4ef56906efde..b6ce80970a30 100644 --- a/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c +++ b/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c @@ -64,6 +64,10 @@ void IRAM_ATTR touch_priv_default_intr_handler(void *arg) touch_base_event_data_t data; touch_ll_get_active_channel_mask(&data.status_mask); int ch_offset = touch_ll_get_current_meas_channel() - TOUCH_MIN_CHAN_ID; + if (ch_offset < 0 || ch_offset >= (int)SOC_TOUCH_SENSOR_NUM) { + /* Not a valid channel */ + return; + } data.chan = g_touch->ch[ch_offset]; /* If the channel is not registered, return directly */ if (!data.chan) { diff --git a/components/esp_driver_touch_sens/test_apps/touch_sens/main/test_touch_sens_common.c b/components/esp_driver_touch_sens/test_apps/touch_sens/main/test_touch_sens_common.c index c5c0adc3ceee..255f979133ef 100644 --- a/components/esp_driver_touch_sens/test_apps/touch_sens/main/test_touch_sens_common.c +++ b/components/esp_driver_touch_sens/test_apps/touch_sens/main/test_touch_sens_common.c @@ -196,3 +196,53 @@ TEST_CASE("touch_sens_active_inactive_test", "[touch]") TEST_ASSERT_EQUAL_INT32(touch_cnt, cb_data.active_count); TEST_ASSERT_EQUAL_INT32(touch_cnt, cb_data.inactive_count); } + +#if SOC_TOUCH_SENSOR_VERSION > 1 +TEST_CASE("touch_sens_current_meas_channel_test", "[touch]") +{ + touch_sensor_handle_t touch = NULL; + touch_channel_handle_t touch_chan = NULL; + + touch_sensor_config_t sens_cfg = TOUCH_SENSOR_DEFAULT_BASIC_CONFIG(TOUCH_SAMPLE_CFG_NUM, s_sample_cfg); + TEST_ESP_OK(touch_sensor_new_controller(&sens_cfg, &touch)); + + /* Configuring the filter */ + touch_sensor_filter_config_t filter_cfg = TOUCH_SENSOR_DEFAULT_FILTER_CONFIG(); + TEST_ESP_OK(touch_sensor_config_filter(touch, &filter_cfg)); + + int err_chan[TOUCH_MAX_CHAN_ID - TOUCH_MIN_CHAN_ID + 1] = {[0 ...(TOUCH_MAX_CHAN_ID - TOUCH_MIN_CHAN_ID)] = -1}; + int scan_times = 100; + uint32_t curr_chan[scan_times]; + /* Loop all channels */ + for (int ch_id = TOUCH_MIN_CHAN_ID; ch_id <= TOUCH_MAX_CHAN_ID; ch_id++) { + /* New a channel */ + TEST_ESP_OK(touch_sensor_new_channel(touch, ch_id, &s_chan_cfg, &touch_chan)); + TEST_ESP_OK(touch_sensor_enable(touch)); + /* Trigger one-shot scanning to update the current measuring channel */ + touch_sensor_trigger_oneshot_scanning(touch, 2000); + + /* Read the current measuring channel for several times */ + for (int i = 0; i < scan_times; i++) { + curr_chan[i] = touch_ll_get_current_meas_channel(); + /* Check if the current measuring channel is the same as the channel id */ + if (curr_chan[i] != ch_id) { + err_chan[ch_id - TOUCH_MIN_CHAN_ID] = curr_chan[i]; + } + } + /* Check if there is any error */ + TEST_ESP_OK(touch_sensor_disable(touch)); + TEST_ESP_OK(touch_sensor_del_channel(touch_chan)); + } + TEST_ESP_OK(touch_sensor_del_controller(touch)); + + /* Check if there is any error in the current measuring channel from any channel */ + bool has_error = false; + for (int i = 0; i < TOUCH_MAX_CHAN_ID - TOUCH_MIN_CHAN_ID + 1; i++) { + if (err_chan[i] >= 0) { + ESP_LOGE("TOUCH_TEST", "actual channel is %d, but current measuring channel reads %d", i + TOUCH_MIN_CHAN_ID, err_chan[i]); + has_error = true; + } + } + TEST_ASSERT_FALSE(has_error); +} +#endif // SOC_TOUCH_SENSOR_VERSION > 1 diff --git a/components/esp_driver_tsens/include/driver/temperature_sensor.h b/components/esp_driver_tsens/include/driver/temperature_sensor.h index fc968dfb0fa0..f918597f3de0 100644 --- a/components/esp_driver_tsens/include/driver/temperature_sensor.h +++ b/components/esp_driver_tsens/include/driver/temperature_sensor.h @@ -46,6 +46,9 @@ typedef struct { .range_min = min, \ .range_max = max, \ .clk_src = TEMPERATURE_SENSOR_CLK_SRC_DEFAULT, \ + .flags = { \ + .allow_pd = 0, \ + }, \ } /** diff --git a/components/esp_driver_tsens/test_apps/temperature_sensor/main/CMakeLists.txt b/components/esp_driver_tsens/test_apps/temperature_sensor/main/CMakeLists.txt index 57b6fd425c69..4b5f0dadd3d5 100644 --- a/components/esp_driver_tsens/test_apps/temperature_sensor/main/CMakeLists.txt +++ b/components/esp_driver_tsens/test_apps/temperature_sensor/main/CMakeLists.txt @@ -1,9 +1,9 @@ set(srcs "test_app_main.c" - "test_temperature_sensor.c" - "test_temperature_phy.c") + "test_temperature_sensor.cpp" + "test_temperature_phy.cpp") if(CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_ETM) - list(APPEND srcs "test_temperature_etm.c") + list(APPEND srcs "test_temperature_etm.cpp") endif() # In order for the cases defined by `TEST_CASE` to be linked into the final elf, diff --git a/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_etm.c b/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_etm.cpp similarity index 83% rename from components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_etm.c rename to components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_etm.cpp index d036d4ef9c41..7f7a402c694f 100644 --- a/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_etm.c +++ b/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_etm.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -21,7 +21,7 @@ // from 0 to 1 on logic analyzer or oscilloscope. TEST_CASE("temperature sensor alarm cause gpio pull up", "[etm]") { - const uint32_t output_gpio = 5; + const gpio_num_t output_gpio = GPIO_NUM_5; // temperature sensor alarm ---> ETM channel A ---> GPIO level to high printf("allocate etm channel\r\n"); esp_etm_channel_config_t etm_config = {}; @@ -30,9 +30,8 @@ TEST_CASE("temperature sensor alarm cause gpio pull up", "[etm]") printf("allocate GPIO etm task\r\n"); esp_etm_task_handle_t gpio_task = NULL; - gpio_etm_task_config_t gpio_task_config = { - .action = GPIO_ETM_TASK_ACTION_SET, - }; + gpio_etm_task_config_t gpio_task_config = {}; + gpio_task_config.actions[0] = GPIO_ETM_TASK_ACTION_SET; TEST_ESP_OK(gpio_new_etm_task(&gpio_task_config, &gpio_task)); // set gpio number for the gpio etm primitives TEST_ESP_OK(gpio_etm_task_add_gpio(gpio_task, output_gpio)); @@ -40,9 +39,14 @@ TEST_CASE("temperature sensor alarm cause gpio pull up", "[etm]") printf("initialize gpio\r\n"); gpio_set_level(output_gpio, 0); gpio_config_t task_gpio_config = { - .intr_type = GPIO_INTR_DISABLE, - .mode = GPIO_MODE_OUTPUT, .pin_bit_mask = 1ULL << output_gpio, + .mode = GPIO_MODE_OUTPUT, + .pull_up_en = GPIO_PULLUP_DISABLE, + .pull_down_en = GPIO_PULLDOWN_DISABLE, + .intr_type = GPIO_INTR_DISABLE, +#if SOC_GPIO_SUPPORT_PIN_HYS_FILTER + .hys_ctrl_mode = GPIO_HYS_SOFT_DISABLE, +#endif }; TEST_ESP_OK(gpio_config(&task_gpio_config)); diff --git a/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_phy.c b/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_phy.cpp similarity index 78% rename from components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_phy.c rename to components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_phy.cpp index 35ab401e2b78..a130ac06057c 100644 --- a/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_phy.c +++ b/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_phy.cpp @@ -41,16 +41,20 @@ struct temperature_sensor_obj_t { static void start_wifi_as_softap(void) { uint8_t ssid_len = strlen(TEST_DEFAULT_SSID); - wifi_config_t w_config = { - .ap.ssid = TEST_DEFAULT_SSID, - .ap.password = TEST_DEFAULT_PWD, - .ap.ssid_len = ssid_len, - .ap.channel = TEST_DEFAULT_CHANNEL, - .ap.authmode = WIFI_AUTH_WPA2_PSK, - .ap.ssid_hidden = false, - .ap.max_connection = 4, - .ap.beacon_interval = 100, - }; + wifi_config_t w_config = {}; // Zero-initialize the structure + + // Assign members + strncpy((char *)w_config.ap.ssid, TEST_DEFAULT_SSID, sizeof(w_config.ap.ssid) - 1); + w_config.ap.ssid[sizeof(w_config.ap.ssid) - 1] = 0; // Ensure null termination + strncpy((char *)w_config.ap.password, TEST_DEFAULT_PWD, sizeof(w_config.ap.password) - 1); + w_config.ap.password[sizeof(w_config.ap.password) - 1] = 0; // Ensure null termination + + w_config.ap.ssid_len = ssid_len; + w_config.ap.channel = TEST_DEFAULT_CHANNEL; + w_config.ap.authmode = WIFI_AUTH_WPA2_PSK; + w_config.ap.ssid_hidden = false; + w_config.ap.max_connection = 4; + w_config.ap.beacon_interval = 100; TEST_ESP_OK(esp_wifi_set_mode(WIFI_MODE_AP)); TEST_ESP_OK(esp_wifi_set_config(WIFI_IF_AP, &w_config)); @@ -72,10 +76,13 @@ static void stop_wifi(void) static void wifi_connect(void) { - wifi_config_t w_config = { - .sta.ssid = TEST_DEFAULT_SSID, - .sta.password = TEST_DEFAULT_PWD, - }; + wifi_config_t w_config = {}; // Zero-initialize the structure + + // Assign members + strncpy((char *)w_config.sta.ssid, TEST_DEFAULT_SSID, sizeof(w_config.sta.ssid) - 1); + w_config.sta.ssid[sizeof(w_config.sta.ssid) - 1] = 0; // Ensure null termination + strncpy((char *)w_config.sta.password, TEST_DEFAULT_PWD, sizeof(w_config.sta.password) - 1); + w_config.sta.password[sizeof(w_config.sta.password) - 1] = 0; // Ensure null termination TEST_ESP_OK(esp_wifi_set_config(WIFI_IF_STA, &w_config)); TEST_ESP_OK(esp_wifi_connect()); diff --git a/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.c b/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.cpp similarity index 99% rename from components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.c rename to components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.cpp index 15b38613c8b6..4fa8069a3ebb 100644 --- a/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.c +++ b/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.cpp @@ -162,7 +162,9 @@ static void test_temperature_sensor_sleep_retention(bool allow_pd) .range_min = 10, .range_max = 50, .clk_src = TEMPERATURE_SENSOR_CLK_SRC_DEFAULT, - .flags.allow_pd = allow_pd, + .flags = { + .allow_pd = allow_pd, + }, }; temperature_sensor_handle_t temp_handle = NULL; TEST_ESP_OK(temperature_sensor_install(&temp_sensor, &temp_handle)); diff --git a/components/esp_driver_uart/include/driver/uhci.h b/components/esp_driver_uart/include/driver/uhci.h index c01af0d9b5aa..fd466ab9249f 100644 --- a/components/esp_driver_uart/include/driver/uhci.h +++ b/components/esp_driver_uart/include/driver/uhci.h @@ -22,8 +22,8 @@ typedef struct { uart_port_t uart_port; /*!< UART port that connect to UHCI controller */ size_t tx_trans_queue_depth; /*!< Depth of internal transfer queue, increase this value can support more transfers pending in the background */ size_t max_transmit_size; /*!< Maximum transfer size in one transaction, in bytes. This decides the number of DMA nodes will be used for each transaction */ - size_t max_receive_internal_mem; /*!< Maximum transfer size in one transaction, in bytes. Each DMA node can point to a maximum of 4096 bytes. This value determines the number of DMA nodes used for each transaction. When your transfer size is large enough, it is recommended to set this value greater than 4096 to facilitate efficient ping-pong operations, such as 10 * 1024. */ - size_t dma_burst_size; /*!< DMA burst size, in bytes */ + size_t max_receive_internal_mem; /*!< Internal DMA usage memory. Each DMA node can point to a maximum of x bytes (depends on chip). This value determines the number of DMA nodes used for each transaction. When your transfer size is large enough, it is recommended to set this value greater than x to facilitate efficient ping-pong operations, such as 2 * x. */ + size_t dma_burst_size; /*!< DMA burst size, in bytes. Set to 0 to disable data burst. Otherwise, use a power of 2. */ size_t max_packet_receive; /*!< Max receive size, auto stop receiving after reach this value, only valid when `length_eof` set true */ struct { diff --git a/components/esp_driver_uart/src/uhci.c b/components/esp_driver_uart/src/uhci.c index 7ee7fdc4b5ac..aa9271913838 100644 --- a/components/esp_driver_uart/src/uhci.c +++ b/components/esp_driver_uart/src/uhci.c @@ -193,7 +193,6 @@ static esp_err_t uhci_gdma_initialize(uhci_controller_handle_t uhci_ctrl, const size_t buffer_alignment = UHCI_MAX(uhci_ctrl->tx_dir.int_mem_align, uhci_ctrl->tx_dir.ext_mem_align); size_t num_dma_nodes = esp_dma_calculate_node_count(config->max_transmit_size, buffer_alignment, DMA_DESCRIPTOR_BUFFER_MAX_SIZE); gdma_link_list_config_t dma_link_config = { - .buffer_alignment = buffer_alignment, .item_alignment = 4, .num_items = num_dma_nodes, }; @@ -203,7 +202,6 @@ static esp_err_t uhci_gdma_initialize(uhci_controller_handle_t uhci_ctrl, const // Initialize DMA RX channel gdma_channel_alloc_config_t rx_alloc_config = { .direction = GDMA_CHANNEL_DIRECTION_RX, - .sibling_chan = uhci_ctrl->tx_dir.dma_chan, #if CONFIG_UHCI_ISR_CACHE_SAFE .flags.isr_cache_safe = true, #endif @@ -215,7 +213,6 @@ static esp_err_t uhci_gdma_initialize(uhci_controller_handle_t uhci_ctrl, const gdma_get_alignment_constraints(uhci_ctrl->rx_dir.dma_chan, &uhci_ctrl->rx_dir.int_mem_align, &uhci_ctrl->rx_dir.ext_mem_align); buffer_alignment = UHCI_MAX(uhci_ctrl->rx_dir.int_mem_align, uhci_ctrl->rx_dir.ext_mem_align); uhci_ctrl->rx_dir.rx_num_dma_nodes = esp_dma_calculate_node_count(config->max_receive_internal_mem, buffer_alignment, DMA_DESCRIPTOR_BUFFER_MAX_SIZE); - dma_link_config.buffer_alignment = buffer_alignment; dma_link_config.num_items = uhci_ctrl->rx_dir.rx_num_dma_nodes; ESP_RETURN_ON_ERROR(gdma_new_link_list(&dma_link_config, &uhci_ctrl->rx_dir.dma_link), TAG, "DMA rx link list alloc failed"); ESP_LOGD(TAG, "rx_dma node number is %d", uhci_ctrl->rx_dir.rx_num_dma_nodes); @@ -263,8 +260,10 @@ static esp_err_t uhci_gdma_deinitialize(uhci_controller_handle_t uhci_ctrl) static void uhci_do_transmit(uhci_controller_handle_t uhci_ctrl, uhci_transaction_desc_t *trans) { uhci_ctrl->tx_dir.cur_trans = trans; + size_t buffer_alignment = esp_ptr_internal(trans->buffer) ? uhci_ctrl->tx_dir.int_mem_align : uhci_ctrl->tx_dir.ext_mem_align; gdma_buffer_mount_config_t mount_config = { .buffer = trans->buffer, + .buffer_alignment = buffer_alignment, .length = trans->buffer_size, .flags = { .mark_eof = true, @@ -319,7 +318,7 @@ esp_err_t uhci_receive(uhci_controller_handle_t uhci_ctrl, uint8_t *read_buffer, for (size_t i = 0; i < node_count; i++) { uhci_ctrl->rx_dir.buffer_size_per_desc_node[i] = base_size; uhci_ctrl->rx_dir.buffer_pointers[i] = read_buffer; - + size_t buffer_alignment = esp_ptr_internal(read_buffer) ? uhci_ctrl->rx_dir.int_mem_align : uhci_ctrl->rx_dir.ext_mem_align; // Distribute the remaining size to the first few nodes if (remaining_size >= max_alignment_needed) { uhci_ctrl->rx_dir.buffer_size_per_desc_node[i] += max_alignment_needed; @@ -328,6 +327,7 @@ esp_err_t uhci_receive(uhci_controller_handle_t uhci_ctrl, uint8_t *read_buffer, mount_configs[i] = (gdma_buffer_mount_config_t) { .buffer = read_buffer, + .buffer_alignment = buffer_alignment, .length = uhci_ctrl->rx_dir.buffer_size_per_desc_node[i], .flags = { .mark_final = false, diff --git a/components/esp_eth/src/spi/w5500/esp_eth_mac_w5500.c b/components/esp_eth/src/spi/w5500/esp_eth_mac_w5500.c index 2f0ea028fe7e..c76ddf7916c4 100644 --- a/components/esp_eth/src/spi/w5500/esp_eth_mac_w5500.c +++ b/components/esp_eth/src/spi/w5500/esp_eth_mac_w5500.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,6 +13,7 @@ #include "esp_attr.h" #include "esp_log.h" #include "esp_check.h" +#include "esp_timer.h" #include "esp_system.h" #include "esp_intr_alloc.h" #include "esp_heap_caps.h" @@ -30,6 +31,8 @@ static const char *TAG = "w5500.mac"; #define W5500_SPI_LOCK_TIMEOUT_MS (50) #define W5500_TX_MEM_SIZE (0x4000) #define W5500_RX_MEM_SIZE (0x4000) +#define W5500_100M_TX_TMO_US (200) +#define W5500_10M_TX_TMO_US (1500) #define W5500_ETH_MAC_RX_BUF_SIZE_AUTO (0) typedef struct { @@ -64,6 +67,7 @@ typedef struct { uint8_t addr[6]; bool packets_remain; uint8_t *rx_buffer; + uint32_t tx_tmo; } emac_w5500_t; static void *w5500_spi_init(const void *spi_config) @@ -245,18 +249,8 @@ static esp_err_t w5500_get_rx_received_size(emac_w5500_t *emac, uint16_t *size) static esp_err_t w5500_write_buffer(emac_w5500_t *emac, const void *buffer, uint32_t len, uint16_t offset) { esp_err_t ret = ESP_OK; - uint32_t remain = len; - const uint8_t *buf = buffer; - offset %= W5500_TX_MEM_SIZE; - if (offset + len > W5500_TX_MEM_SIZE) { - remain = (offset + len) % W5500_TX_MEM_SIZE; - len = W5500_TX_MEM_SIZE - offset; - ESP_GOTO_ON_ERROR(w5500_write(emac, W5500_MEM_SOCK_TX(0, offset), buf, len), err, TAG, "write TX buffer failed"); - offset += len; - buf += len; - } - ESP_GOTO_ON_ERROR(w5500_write(emac, W5500_MEM_SOCK_TX(0, offset), buf, remain), err, TAG, "write TX buffer failed"); + ESP_GOTO_ON_ERROR(w5500_write(emac, W5500_MEM_SOCK_TX(0, offset), buffer, len), err, TAG, "write TX buffer failed"); err: return ret; } @@ -264,18 +258,7 @@ static esp_err_t w5500_write_buffer(emac_w5500_t *emac, const void *buffer, uint static esp_err_t w5500_read_buffer(emac_w5500_t *emac, void *buffer, uint32_t len, uint16_t offset) { esp_err_t ret = ESP_OK; - uint32_t remain = len; - uint8_t *buf = buffer; - offset %= W5500_RX_MEM_SIZE; - if (offset + len > W5500_RX_MEM_SIZE) { - remain = (offset + len) % W5500_RX_MEM_SIZE; - len = W5500_RX_MEM_SIZE - offset; - ESP_GOTO_ON_ERROR(w5500_read(emac, W5500_MEM_SOCK_RX(0, offset), buf, len), err, TAG, "read RX buffer failed"); - offset += len; - buf += len; - } - ESP_GOTO_ON_ERROR(w5500_read(emac, W5500_MEM_SOCK_RX(0, offset), buf, remain), err, TAG, "read RX buffer failed"); - + ESP_GOTO_ON_ERROR(w5500_read(emac, W5500_MEM_SOCK_RX(0, offset), buffer, len), err, TAG, "read RX buffer failed"); err: return ret; } @@ -284,7 +267,6 @@ static esp_err_t w5500_set_mac_addr(emac_w5500_t *emac) { esp_err_t ret = ESP_OK; ESP_GOTO_ON_ERROR(w5500_write(emac, W5500_REG_MAC, emac->addr, 6), err, TAG, "write MAC address register failed"); - err: return ret; } @@ -338,7 +320,8 @@ static esp_err_t w5500_setup_default(emac_w5500_t *emac) esp_err_t ret = ESP_OK; uint8_t reg_value = 16; - // Only SOCK0 can be used as MAC RAW mode, so we give the whole buffer (16KB TX and 16KB RX) to SOCK0 + // Only SOCK0 can be used as MAC RAW mode, so we give the whole buffer (16KB TX and 16KB RX) to SOCK0, which doesn't have any effect for TX though. + // A larger TX buffer doesn't buy us pipelining - each SEND is one frame and must complete before the next. ESP_GOTO_ON_ERROR(w5500_write(emac, W5500_REG_SOCK_RXBUF_SIZE(0), ®_value, sizeof(reg_value)), err, TAG, "set rx buffer size failed"); ESP_GOTO_ON_ERROR(w5500_write(emac, W5500_REG_SOCK_TXBUF_SIZE(0), ®_value, sizeof(reg_value)), err, TAG, "set tx buffer size failed"); reg_value = 0; @@ -490,11 +473,14 @@ static esp_err_t emac_w5500_set_link(esp_eth_mac_t *mac, eth_link_t link) static esp_err_t emac_w5500_set_speed(esp_eth_mac_t *mac, eth_speed_t speed) { esp_err_t ret = ESP_OK; + emac_w5500_t *emac = __containerof(mac, emac_w5500_t, parent); switch (speed) { case ETH_SPEED_10M: + emac->tx_tmo = W5500_10M_TX_TMO_US; ESP_LOGD(TAG, "working in 10Mbps"); break; case ETH_SPEED_100M: + emac->tx_tmo = W5500_100M_TX_TMO_US; ESP_LOGD(TAG, "working in 100Mbps"); break; default: @@ -589,14 +575,16 @@ static esp_err_t emac_w5500_transmit(esp_eth_mac_t *mac, uint8_t *buf, uint32_t ESP_GOTO_ON_ERROR(w5500_send_command(emac, W5500_SCR_SEND, 100), err, TAG, "issue SEND command failed"); // pooling the TX done event - int retry = 0; uint8_t status = 0; - while (!(status & W5500_SIR_SEND)) { - ESP_GOTO_ON_ERROR(w5500_read(emac, W5500_REG_SOCK_IR(0), &status, sizeof(status)), err, TAG, "read SOCK0 IR failed"); - if ((retry++ > 3 && !is_w5500_sane_for_rxtx(emac)) || retry > 10) { + uint64_t start = esp_timer_get_time(); + uint64_t now = 0; + do { + now = esp_timer_get_time(); + if (!is_w5500_sane_for_rxtx(emac) || (now - start) > emac->tx_tmo) { return ESP_FAIL; } - } + ESP_GOTO_ON_ERROR(w5500_read(emac, W5500_REG_SOCK_IR(0), &status, sizeof(status)), err, TAG, "read SOCK0 IR failed"); + } while (!(status & W5500_SIR_SEND)); // clear the event bit status = W5500_SIR_SEND; ESP_GOTO_ON_ERROR(w5500_write(emac, W5500_REG_SOCK_IR(0), &status, sizeof(status)), err, TAG, "write SOCK0 IR failed"); diff --git a/components/esp_eth/test_apps/pytest_esp_eth.py b/components/esp_eth/test_apps/pytest_esp_eth.py index b9d235698d3b..d66f953eaa82 100644 --- a/components/esp_eth/test_apps/pytest_esp_eth.py +++ b/components/esp_eth/test_apps/pytest_esp_eth.py @@ -128,7 +128,7 @@ def ethernet_test(dut: IdfDut) -> None: def ethernet_int_emac_test(dut: IdfDut) -> None: - dut.run_all_single_board_cases(group='esp_emac', timeout=120) + dut.run_all_single_board_cases(group='esp_emac', timeout=240) def ethernet_l2_test(dut: IdfDut) -> None: diff --git a/components/esp_http_client/esp_http_client.c b/components/esp_http_client/esp_http_client.c index cdfa0a3ab757..5a2f90c87a8e 100644 --- a/components/esp_http_client/esp_http_client.c +++ b/components/esp_http_client/esp_http_client.c @@ -191,7 +191,7 @@ static const char *HTTP_METHOD_MAPPING[] = { "REPORT" }; -static esp_err_t esp_http_client_request_send(esp_http_client_handle_t client, int write_len); +esp_err_t esp_http_client_request_send(esp_http_client_handle_t client, int write_len); static esp_err_t esp_http_client_connect(esp_http_client_handle_t client); static esp_err_t esp_http_client_send_post_data(esp_http_client_handle_t client); @@ -614,8 +614,12 @@ static esp_err_t _clear_auth_data(esp_http_client_handle_t client) return ESP_OK; } -static esp_err_t esp_http_client_prepare(esp_http_client_handle_t client) +esp_err_t esp_http_client_prepare(esp_http_client_handle_t client) { + if (client == NULL) { + return ESP_FAIL; + } + client->process_again = 0; client->response->data_process = 0; client->first_line_prepared = false; @@ -1626,8 +1630,12 @@ static int http_client_prepare_first_line(esp_http_client_handle_t client, int w return first_line_len; } -static esp_err_t esp_http_client_request_send(esp_http_client_handle_t client, int write_len) +esp_err_t esp_http_client_request_send(esp_http_client_handle_t client, int write_len) { + if (client == NULL) { + return ESP_FAIL; + } + int first_line_len = 0; if (!client->first_line_prepared) { if ((first_line_len = http_client_prepare_first_line(client, write_len)) < 0) { @@ -1959,3 +1967,15 @@ esp_err_t esp_http_client_get_chunk_length(esp_http_client_handle_t client, int } return ESP_OK; } + +bool esp_http_client_is_persistent_connection(esp_http_client_handle_t client) +{ + if (client == NULL) { + return false; + } + + if (http_should_keep_alive(client->parser)) { + return true; + } + return false; +} diff --git a/components/esp_http_client/include/esp_http_client.h b/components/esp_http_client/include/esp_http_client.h index 1f6c38846796..ffc7b654142a 100644 --- a/components/esp_http_client/include/esp_http_client.h +++ b/components/esp_http_client/include/esp_http_client.h @@ -295,6 +295,33 @@ esp_http_client_handle_t esp_http_client_init(const esp_http_client_config_t *co */ esp_err_t esp_http_client_perform(esp_http_client_handle_t client); +/** + * @brief Prepare HTTP client for a new request + * This function initializes the client state and prepares authentication if needed. + * It should be called before sending a request. + * + * @param[in] client The esp_http_client handle + * + * @return + * - ESP_OK on successful + * - ESP_FAIL on error + */ +esp_err_t esp_http_client_prepare(esp_http_client_handle_t client); + +/** + * @brief Send HTTP request headers and data + * This function sends the HTTP request line, headers, and any post data to the server. + * + * @param[in] client The esp_http_client handle + * @param[in] write_len Length of data to write (for POST/PUT requests) + * + * @return + * - ESP_OK on successful + * - ESP_FAIL on error + * - ESP_ERR_HTTP_WRITE_DATA if write operation fails + */ +esp_err_t esp_http_client_request_send(esp_http_client_handle_t client, int write_len); + /** * @brief Cancel an ongoing HTTP request. This API closes the current socket and opens a new socket with the same esp_http_client context. * @@ -785,6 +812,15 @@ esp_err_t esp_http_client_get_url(esp_http_client_handle_t client, char *url, co */ esp_err_t esp_http_client_get_chunk_length(esp_http_client_handle_t client, int *len); +/** + * @brief Check if persistent connection is supported by the server + * + * @param[in] client The HTTP client handle + * + * @return true if persistent connection is supported, false otherwise + */ +bool esp_http_client_is_persistent_connection(esp_http_client_handle_t client); + #ifdef __cplusplus } #endif diff --git a/components/esp_https_ota/src/esp_https_ota.c b/components/esp_https_ota/src/esp_https_ota.c index 96459fa7fe13..5922b37542f7 100644 --- a/components/esp_https_ota/src/esp_https_ota.c +++ b/components/esp_https_ota/src/esp_https_ota.c @@ -145,7 +145,22 @@ static esp_err_t _http_connect(esp_https_ota_t *https_ota_handle) * is enabled */ int post_len = esp_http_client_get_post_field(https_ota_handle->http_client, &post_data); - err = esp_http_client_open(https_ota_handle->http_client, post_len); + +#if CONFIG_ESP_HTTPS_OTA_ENABLE_PARTIAL_DOWNLOAD + // If support_persistent_connection is enabled and this is a subsequent request, skip connection + if (esp_http_client_is_persistent_connection(https_ota_handle->http_client) && https_ota_handle->state == ESP_HTTPS_OTA_IN_PROGRESS) { + ESP_LOGD(TAG, "Using existing connection for partial download"); + err = esp_http_client_prepare(https_ota_handle->http_client); + if (err != ESP_OK) { + ESP_LOGE(TAG, "Failed to reset HTTP client response state: %s", esp_err_to_name(err)); + return err; + } + err = esp_http_client_request_send(https_ota_handle->http_client, post_len); + } else +#endif + { + err = esp_http_client_open(https_ota_handle->http_client, post_len); + } if (err != ESP_OK) { ESP_LOGE(TAG, "Failed to open HTTP connection: %s", esp_err_to_name(err)); return err; @@ -604,7 +619,10 @@ esp_err_t esp_https_ota_perform(esp_https_ota_handle_t https_ota_handle) } if (handle->partial_http_download) { if (handle->state == ESP_HTTPS_OTA_IN_PROGRESS && handle->image_length > handle->binary_file_len) { - esp_http_client_close(handle->http_client); + // Only close connection if support_persistent_connection is not enabled + if (!esp_http_client_is_persistent_connection(handle->http_client)) { + esp_http_client_close(handle->http_client); + } char *header_val = NULL; int header_size = 0; #if CONFIG_ESP_HTTPS_OTA_DECRYPT_CB diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 889fdc0c77dd..4382022d5ae2 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -34,6 +34,7 @@ if(NOT non_os_build) "sleep_usb.c" "sleep_gpio.c" "sleep_event.c" + "sleep_mspi.c" "regi2c_ctrl.c" "esp_gpio_reserve.c" "sar_periph_ctrl_common.c" diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig index 0c4a8f6aca4e..dba0596f5b70 100644 --- a/components/esp_hw_support/Kconfig +++ b/components/esp_hw_support/Kconfig @@ -292,4 +292,5 @@ menu "Hardware Settings" Otherwise, internal voltage will be set to fix dbias. This is a must for stable mass production. Disable for debugging only. + orsource "./lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround" endmenu diff --git a/components/esp_hw_support/dma/async_memcpy_cp_dma.c b/components/esp_hw_support/dma/async_memcpy_cp_dma.c index 1609a8002c65..add2cec2e510 100644 --- a/components/esp_hw_support/dma/async_memcpy_cp_dma.c +++ b/components/esp_hw_support/dma/async_memcpy_cp_dma.c @@ -216,7 +216,6 @@ static esp_err_t mcp_cpdma_memcpy(async_memcpy_context_t *ctx, void *dst, void * // allocate gdma TX link gdma_link_list_config_t tx_link_cfg = { - .buffer_alignment = 1, // CP_DMA doesn't have alignment requirement for internal memory .item_alignment = 4, // CP_DMA requires 4 bytes alignment for each descriptor .num_items = num_dma_nodes, .flags = { @@ -229,6 +228,7 @@ static esp_err_t mcp_cpdma_memcpy(async_memcpy_context_t *ctx, void *dst, void * gdma_buffer_mount_config_t tx_buf_mount_config[1] = { [0] = { .buffer = src, + .buffer_alignment = 1, // CP_DMA doesn't have alignment requirement for internal memory .length = n, .flags = { .mark_eof = true, // mark the last item as EOF, so the RX channel can also received an EOF list item @@ -240,7 +240,6 @@ static esp_err_t mcp_cpdma_memcpy(async_memcpy_context_t *ctx, void *dst, void * // allocate gdma RX link gdma_link_list_config_t rx_link_cfg = { - .buffer_alignment = 1, // CP_DMA doesn't have alignment requirement for internal memory .item_alignment = 4, // CP_DMA requires 4 bytes alignment for each descriptor .num_items = num_dma_nodes, .flags = { @@ -253,6 +252,7 @@ static esp_err_t mcp_cpdma_memcpy(async_memcpy_context_t *ctx, void *dst, void * gdma_buffer_mount_config_t rx_buf_mount_config[1] = { [0] = { .buffer = dst, + .buffer_alignment = 1, // CP_DMA doesn't have alignment requirement for internal memory .length = n, .flags = { .mark_eof = false, // EOF is set by TX side diff --git a/components/esp_hw_support/dma/async_memcpy_gdma.c b/components/esp_hw_support/dma/async_memcpy_gdma.c index 527e0ff79c57..a6e1047dd465 100644 --- a/components/esp_hw_support/dma/async_memcpy_gdma.c +++ b/components/esp_hw_support/dma/async_memcpy_gdma.c @@ -349,7 +349,6 @@ static esp_err_t mcp_gdma_memcpy(async_memcpy_context_t *ctx, void *dst, void *s buffer_alignment = esp_ptr_internal(src) ? mcp_gdma->tx_int_mem_alignment : mcp_gdma->tx_ext_mem_alignment; num_dma_nodes = esp_dma_calculate_node_count(n, buffer_alignment, MCP_DMA_DESCRIPTOR_BUFFER_MAX_SIZE); gdma_link_list_config_t tx_link_cfg = { - .buffer_alignment = buffer_alignment, .item_alignment = dma_link_item_alignment, .num_items = num_dma_nodes, .flags = { @@ -362,6 +361,7 @@ static esp_err_t mcp_gdma_memcpy(async_memcpy_context_t *ctx, void *dst, void *s gdma_buffer_mount_config_t tx_buf_mount_config[1] = { [0] = { .buffer = src, + .buffer_alignment = buffer_alignment, .length = n, .flags = { .mark_eof = true, // mark the last item as EOF, so the RX channel can also received an EOF list item @@ -389,7 +389,6 @@ static esp_err_t mcp_gdma_memcpy(async_memcpy_context_t *ctx, void *dst, void *s buffer_alignment = esp_ptr_internal(dst) ? mcp_gdma->rx_int_mem_alignment : mcp_gdma->rx_ext_mem_alignment; num_dma_nodes = esp_dma_calculate_node_count(n, buffer_alignment, MCP_DMA_DESCRIPTOR_BUFFER_MAX_SIZE); gdma_link_list_config_t rx_link_cfg = { - .buffer_alignment = buffer_alignment, .item_alignment = dma_link_item_alignment, .num_items = num_dma_nodes + 3, // add 3 extra items for the cache aligned buffers .flags = { @@ -406,6 +405,7 @@ static esp_err_t mcp_gdma_memcpy(async_memcpy_context_t *ctx, void *dst, void *s gdma_buffer_mount_config_t rx_buf_mount_config[3] = {0}; for (int i = 0; i < 3; i++) { rx_buf_mount_config[i].buffer = trans->rx_buf_array.aligned_buffer[i].aligned_buffer; + rx_buf_mount_config[i].buffer_alignment = buffer_alignment; rx_buf_mount_config[i].length = trans->rx_buf_array.aligned_buffer[i].length; } gdma_link_mount_buffers(trans->rx_link_list, 0, rx_buf_mount_config, 3, NULL); diff --git a/components/esp_hw_support/dma/gdma_link.c b/components/esp_hw_support/dma/gdma_link.c index 6a3199ea91f3..d7b020e3612a 100644 --- a/components/esp_hw_support/dma/gdma_link.c +++ b/components/esp_hw_support/dma/gdma_link.c @@ -51,7 +51,6 @@ struct gdma_link_list_item_t { typedef struct gdma_link_list_t { uint32_t num_items; // number of items in the link list size_t item_size; // size of each item - size_t buffer_alignment; // Alignment of each buffer uint8_t *items; // pointer to the link list items uint8_t *items_nc; // pointer to the link list items, non-cached struct { @@ -66,11 +65,6 @@ esp_err_t gdma_new_link_list(const gdma_link_list_config_t *config, gdma_link_li gdma_link_list_t *list = NULL; ESP_RETURN_ON_FALSE(config && ret_list, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); ESP_RETURN_ON_FALSE(config->num_items, ESP_ERR_INVALID_ARG, TAG, "invalid number of items"); - size_t buffer_alignment = config->buffer_alignment; - if (buffer_alignment == 0) { - buffer_alignment = 1; - } - ESP_RETURN_ON_FALSE((buffer_alignment & (buffer_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "invalid buffer alignment: %zu", buffer_alignment); // the link list container is allocated from internal memory list = heap_caps_calloc(1, sizeof(gdma_link_list_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); @@ -109,7 +103,6 @@ esp_err_t gdma_new_link_list(const gdma_link_list_config_t *config, gdma_link_li list->items = items; // calculate the non-cached address list->items_nc = GDMA_CACHE_ADDR_TO_NON_CACHE_ADDR(items); - list->buffer_alignment = buffer_alignment; list->flags.check_owner = config->flags.check_owner; ESP_LOGD(TAG, "new link list @%p, items @%p", list, items); @@ -137,13 +130,13 @@ esp_err_t gdma_del_link_list(gdma_link_list_handle_t list) esp_err_t gdma_link_mount_buffers(gdma_link_list_handle_t list, int start_item_index, const gdma_buffer_mount_config_t *buf_config_array, size_t num_buf, int *end_item_index) { - ESP_RETURN_ON_FALSE(list && buf_config_array && num_buf, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - size_t buffer_alignment = list->buffer_alignment; + if(!list || !buf_config_array || !num_buf) { + return ESP_ERR_INVALID_ARG; + } size_t item_size = list->item_size; uint32_t list_item_capacity = list->num_items; // ensure the start_item_index is between 0 and `list_item_capacity - 1` start_item_index = (start_item_index % list_item_capacity + list_item_capacity) % list_item_capacity; - size_t max_buffer_mount_length = ALIGN_DOWN(GDMA_MAX_BUFFER_SIZE_PER_LINK_ITEM, buffer_alignment); uint32_t begin_item_idx = start_item_index; gdma_link_list_item_t *lli_nc = NULL; @@ -165,13 +158,19 @@ esp_err_t gdma_link_mount_buffers(gdma_link_list_handle_t list, int start_item_i const gdma_buffer_mount_config_t *config = &buf_config_array[bi]; uint8_t *buf = (uint8_t *)config->buffer; size_t len = config->length; + size_t buffer_alignment = config->buffer_alignment; + if (buffer_alignment == 0) { + buffer_alignment = 1; + } // check the buffer alignment + ESP_RETURN_ON_FALSE_ISR((buffer_alignment & (buffer_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "invalid buffer alignment: %"PRIu32"", buffer_alignment); + size_t max_buffer_mount_length = ALIGN_DOWN(GDMA_MAX_BUFFER_SIZE_PER_LINK_ITEM, buffer_alignment); if (!config->flags.bypass_buffer_align_check) { - ESP_RETURN_ON_FALSE(((uintptr_t)buf & (buffer_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "buffer not aligned to %zu", buffer_alignment); + ESP_RETURN_ON_FALSE_ISR(((uintptr_t)buf & (buffer_alignment - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "buffer not aligned to %"PRIu32"", buffer_alignment); } uint32_t num_items_need = (len + max_buffer_mount_length - 1) / max_buffer_mount_length; // check if there are enough link list items - ESP_RETURN_ON_FALSE((begin_item_idx + num_items_need) <= (start_item_index + num_items_avail), ESP_ERR_INVALID_ARG, TAG, "no more space for buffer mounting"); + ESP_RETURN_ON_FALSE_ISR((begin_item_idx + num_items_need) <= (start_item_index + num_items_avail), ESP_ERR_INVALID_ARG, TAG, "no more space for buffer mounting"); begin_item_idx += num_items_need; } @@ -184,6 +183,11 @@ esp_err_t gdma_link_mount_buffers(gdma_link_list_handle_t list, int start_item_i const gdma_buffer_mount_config_t *config = &buf_config_array[bi]; uint8_t *buf = (uint8_t *)config->buffer; size_t len = config->length; + size_t buffer_alignment = config->buffer_alignment; + if (buffer_alignment == 0) { + buffer_alignment = 1; + } + size_t max_buffer_mount_length = ALIGN_DOWN(GDMA_MAX_BUFFER_SIZE_PER_LINK_ITEM, buffer_alignment); // skip zero-length buffer if (len == 0 || buf == NULL) { continue; @@ -221,13 +225,17 @@ esp_err_t gdma_link_mount_buffers(gdma_link_list_handle_t list, int start_item_i uintptr_t gdma_link_get_head_addr(gdma_link_list_handle_t list) { - ESP_RETURN_ON_FALSE(list, 0, TAG, "invalid argument"); + if (!list) { + return 0; + } return (uintptr_t)(list->items); } esp_err_t gdma_link_concat(gdma_link_list_handle_t first_link, int first_link_item_index, gdma_link_list_handle_t second_link, int second_link_item_index) { - ESP_RETURN_ON_FALSE(first_link && second_link, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + if(!(first_link && second_link)) { + return ESP_ERR_INVALID_ARG; + } gdma_link_list_item_t *lli_nc = NULL; // ensure the first_link_item_index is between 0 and `num_items - 1` int num_items = first_link->num_items; @@ -243,7 +251,9 @@ esp_err_t gdma_link_concat(gdma_link_list_handle_t first_link, int first_link_it esp_err_t gdma_link_set_owner(gdma_link_list_handle_t list, int item_index, gdma_lli_owner_t owner) { - ESP_RETURN_ON_FALSE_ISR(list, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + if (!list) { + return ESP_ERR_INVALID_ARG; + } int num_items = list->num_items; // ensure the item_index is between 0 and `num_items - 1` item_index = (item_index % num_items + num_items) % num_items; @@ -254,7 +264,9 @@ esp_err_t gdma_link_set_owner(gdma_link_list_handle_t list, int item_index, gdma esp_err_t gdma_link_get_owner(gdma_link_list_handle_t list, int item_index, gdma_lli_owner_t *owner) { - ESP_RETURN_ON_FALSE_ISR(list && owner, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + if(!list || !owner) { + return ESP_ERR_INVALID_ARG; + } int num_items = list->num_items; // ensure the item_index is between 0 and `num_items - 1` item_index = (item_index % num_items + num_items) % num_items; diff --git a/components/esp_hw_support/dma/include/esp_private/gdma_link.h b/components/esp_hw_support/dma/include/esp_private/gdma_link.h index 7ab326edcca9..79689f6c0955 100644 --- a/components/esp_hw_support/dma/include/esp_private/gdma_link.h +++ b/components/esp_hw_support/dma/include/esp_private/gdma_link.h @@ -24,7 +24,6 @@ typedef struct gdma_link_list_t *gdma_link_list_handle_t; typedef struct { uint32_t num_items; //!< Number of nodes in the link list size_t item_alignment; //!< Alignment of each list item required by the DMA. By default, it's 4 bytes alignment. - size_t buffer_alignment; //!< Alignment of each buffer required by the DMA. By default, it's 1 byte alignment. struct gdma_link_list_flags { uint32_t items_in_ext_mem: 1; //!< Whether the link list items are allocated from external memory uint32_t check_owner: 1; //!< Whether the link list is responsible for checking the ownership when mount data buffers @@ -62,6 +61,7 @@ esp_err_t gdma_del_link_list(gdma_link_list_handle_t list); */ typedef struct { void *buffer; //!< Buffer to be mounted to the DMA link list + size_t buffer_alignment; //!< Alignment of the buffer. By default, it's 1 byte alignment. size_t length; //!< Number of bytes that are expected to be transferred struct gdma_buffer_mount_flags { uint32_t mark_eof: 1; /*!< Whether to mark the list item as the "EOF" item. diff --git a/components/esp_hw_support/include/esp_private/esp_pau.h b/components/esp_hw_support/include/esp_private/esp_pau.h index ba975b7b8ddf..f82d0f7dbbe6 100644 --- a/components/esp_hw_support/include/esp_private/esp_pau.h +++ b/components/esp_hw_support/include/esp_private/esp_pau.h @@ -83,8 +83,10 @@ void pau_regdma_trigger_extra_link_restore(void); * link entry configuration in always-on domain * * @param enable Set true to use always-on domain link configuration instead + * + * @return The origin aon link bypass enable status */ -void pau_regdma_enable_aon_link_entry(bool enable); +bool pau_regdma_enable_aon_link_entry(bool enable); #endif #ifdef __cplusplus diff --git a/components/esp_hw_support/include/esp_private/sleep_cpu.h b/components/esp_hw_support/include/esp_private/sleep_cpu.h index cc2dd35980b3..c65d01a6194c 100644 --- a/components/esp_hw_support/include/esp_private/sleep_cpu.h +++ b/components/esp_hw_support/include/esp_private/sleep_cpu.h @@ -22,7 +22,7 @@ extern "C" { * This file contains declarations of cpu retention related functions in light sleep mode. */ -#if ESP_SLEEP_POWER_DOWN_CPU || SOC_PM_SUPPORT_CPU_PD +#if ESP_SLEEP_POWER_DOWN_CPU || (SOC_PM_SUPPORT_CPU_PD && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3) /** * @brief Whether to allow the cpu power domain to be powered off. * diff --git a/components/esp_hw_support/include/esp_private/sleep_flash.h b/components/esp_hw_support/include/esp_private/sleep_flash.h new file mode 100644 index 000000000000..ab8c95e0986b --- /dev/null +++ b/components/esp_hw_support/include/esp_private/sleep_flash.h @@ -0,0 +1,25 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include +#include "sdkconfig.h" +#include "soc/soc_caps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_IDF_TARGET_ESP32P4 && (CONFIG_ESP_REV_MIN_FULL == 300) +/** + * Workaround for esp32p4 v3 MPSI access failure after power up. + */ +void sleep_flash_p4_rev3_workaround(void); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/include/esp_sleep.h b/components/esp_hw_support/include/esp_sleep.h index dee094ef7ff5..f6713adbb904 100644 --- a/components/esp_hw_support/include/esp_sleep.h +++ b/components/esp_hw_support/include/esp_sleep.h @@ -72,7 +72,7 @@ typedef enum { #if SOC_PM_SUPPORT_RC_FAST_PD ESP_PD_DOMAIN_RC_FAST, //!< Internal Fast oscillator #endif -#if SOC_PM_SUPPORT_CPU_PD +#if SOC_PM_SUPPORT_CPU_PD && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 ESP_PD_DOMAIN_CPU, //!< CPU core #endif #if SOC_PM_SUPPORT_VDDSDIO_PD @@ -139,7 +139,11 @@ enum { ESP_ERR_SLEEP_TOO_SHORT_SLEEP_DURATION = ESP_ERR_INVALID_ARG, }; -#define ESP_SLEEP_POWER_DOWN_CPU (CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP || (SOC_CPU_IN_TOP_DOMAIN && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)) +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 +#define ESP_SLEEP_POWER_DOWN_CPU CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP +#else +#define ESP_SLEEP_POWER_DOWN_CPU CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP +#endif /** * @brief Disable wakeup source diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf index a30384a17b18..b210d0462f6d 100644 --- a/components/esp_hw_support/linker.lf +++ b/components/esp_hw_support/linker.lf @@ -22,6 +22,7 @@ entries: rtc_time (noflash_text) if SOC_PMU_SUPPORTED = y && SOC_LIGHT_SLEEP_SUPPORTED = y: pmu_sleep (noflash) + sleep_mspi (noflash) if SPIRAM_FLASH_LOAD_TO_PSRAM = y: pmu_init (noflash) pmu_param (noflash) diff --git a/components/esp_hw_support/lowpower/CMakeLists.txt b/components/esp_hw_support/lowpower/CMakeLists.txt index 9525e680036c..e6170bcb6283 100644 --- a/components/esp_hw_support/lowpower/CMakeLists.txt +++ b/components/esp_hw_support/lowpower/CMakeLists.txt @@ -5,7 +5,7 @@ endif() set(srcs) if(CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP OR - (CONFIG_SOC_CPU_IN_TOP_DOMAIN AND CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)) + (CONFIG_ESP32P4_SELECTS_REV_LESS_V3 AND CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)) list(APPEND srcs "port/${target}/sleep_cpu.c") if(CONFIG_SOC_PM_CPU_RETENTION_BY_SW) list(APPEND srcs "port/${target}/sleep_cpu_asm.S") @@ -16,6 +16,12 @@ if(CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP OR endif() endif() +if(CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND) + list(APPEND srcs "port/esp32p4/p4_rev3_mspi_workaround.S") + set_property(TARGET ${COMPONENT_LIB} + APPEND PROPERTY INTERFACE_LINK_LIBRARIES "-u p4_rev3_mspi_workaround") +endif() + if(CONFIG_SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD AND CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP) list(APPEND srcs "port/${target}/sleep_mmu.c") endif() diff --git a/components/esp_hw_support/lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround b/components/esp_hw_support/lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround new file mode 100644 index 000000000000..5810818f7999 --- /dev/null +++ b/components/esp_hw_support/lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround @@ -0,0 +1,10 @@ +config P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND + bool + depends on IDF_TARGET_ESP32P4 + default y if ESP32P4_REV_MIN_300 + +config P4_REV3_MSPI_WORKAROUND_SIZE + hex + depends on IDF_TARGET_ESP32P4 + default 0x100 if ESP32P4_REV_MIN_300 + default 0 diff --git a/components/esp_hw_support/lowpower/port/esp32p4/p4_rev3_mspi_workaround.S b/components/esp_hw_support/lowpower/port/esp32p4/p4_rev3_mspi_workaround.S new file mode 100644 index 000000000000..64a105929d2e --- /dev/null +++ b/components/esp_hw_support/lowpower/port/esp32p4/p4_rev3_mspi_workaround.S @@ -0,0 +1,110 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/reg_base.h" + +#define HP_SYSTEM_CORE_ERR_RESP_DIS_REG (DR_REG_HP_SYS_BASE + 0x1a4) + +/* Clock related */ +#define DR_REG_LP_CLKRST_BASE (DR_REG_LPAON_BASE + 0x1000) +#define LP_CLKRST_HPCPU_RESET_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x14) +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL (1 << 15) + +#define HP_SYS_CLKRST_HP_RST_EN0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xc0) +#define HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI (1 << 22) +#define HP_SYS_CLKRST_REG_RST_EN_MSPI_APB (1 << 24) + + +/* SPIMEM related */ +#define DR_REG_FLASH_SPI0_BASE (DR_REG_HPPERIPH0_BASE + 0x8C000) +#define SPI_MEM_C_CACHE_FCTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x3c) +#define SPI_MEM_C_CLOSE_AXI_INF_EN (1 << 31) +#define SPI_MEM_C_AXI_REQ_EN (1 << 0) + +#define SPI_MEM_C_MMU_ITEM_INDEX_REG (DR_REG_FLASH_SPI0_BASE + 0x380) +#define SPI_MEM_C_MMU_ITEM_CONTENT_REG (DR_REG_FLASH_SPI0_BASE + 0x37c) + +.macro REG_SET_BIT addr, value + li a0, \addr + li a1, \value + lw a2, (a0) + or a2, a2, a1 + sw a2, (a0) +.endm + +.macro REG_CLR_BIT addr, value + li a0, \addr + /* Since all our parameters will be constants, we can pre-calculate it at assemble time */ + li a1, ~\value + lw a2, (a0) + and a2, a2, a1 + sw a2, (a0) +.endm + +.macro REG_WRITE addr, value + li a0, \addr + li a1, \value + sw a1, (a0) +.endm + +.macro REG_READ addr + li a0, \addr + lw a1, (a0) +.endm + +.macro DELAY_US us + li t3, (40 * \us) /* CPU @40MHz after reset */ + csrr t0, cycle + add t1, t0, t3 +1: csrr t2, cycle + blt t2, t1, 1b +.endm + +/** + * @brief Workaround for MSPI issues on ESP32-P4 revision 3 + * + * This function implements a workaround for MSPI-related issues on ESP32-P4 revision 3. + * It performs 2 flash dummy reads to stabilize the MSPI functionality before jumping to + * ROM code after deepsleep wakeup. + */ +.global p4_rev3_mspi_workaround +.section .p4_rev3_mspi_workaround.rtc_text,"ax" + +p4_rev3_mspi_workaround: + # Recover the reset vector to HP ROM + REG_SET_BIT LP_CLKRST_HPCPU_RESET_CTRL0_REG, LP_CLKRST_HPCORE0_STAT_VECTOR_SEL + + # Clear the bit to close AXI interface and then set the AXI request enable bit + REG_CLR_BIT SPI_MEM_C_CACHE_FCTRL_REG, SPI_MEM_C_CLOSE_AXI_INF_EN + REG_SET_BIT SPI_MEM_C_CACHE_FCTRL_REG, SPI_MEM_C_AXI_REQ_EN + + # Set 1 mspi mmu entry for axi addr to flash addr + REG_WRITE SPI_MEM_C_MMU_ITEM_INDEX_REG, 0 + REG_WRITE SPI_MEM_C_MMU_ITEM_CONTENT_REG, 0x1000 + + # Disable cpu get error response + REG_WRITE HP_SYSTEM_CORE_ERR_RESP_DIS_REG, 0x7 + + # Perform dummy reads + REG_READ 0x80000000 + # Perform dummy reads again + REG_READ 0x80000080 + + # Delay 1us to wait MSPI read transmission done + DELAY_US 1 + + # Enable cpu get error response + REG_WRITE HP_SYSTEM_CORE_ERR_RESP_DIS_REG, 0 + + # Reset MSPI AXI and APB interfaces + REG_SET_BIT HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI + REG_SET_BIT HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_APB + REG_CLR_BIT HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI + REG_CLR_BIT HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_APB + + # Jump to HP ROM first stage boot code + li a5, 0x4fc00000 + jr a5 diff --git a/components/esp_hw_support/lowpower/port/esp32p4/rvsleep-frames.h b/components/esp_hw_support/lowpower/port/esp32p4/rvsleep-frames.h index 76c88a8d0bf0..bcff56ea419e 100644 --- a/components/esp_hw_support/lowpower/port/esp32p4/rvsleep-frames.h +++ b/components/esp_hw_support/lowpower/port/esp32p4/rvsleep-frames.h @@ -80,6 +80,9 @@ STRUCT_BEGIN STRUCT_FIELD (long, 4, RV_SLP_CTX_MSTATUS, mstatus) /* Machine Status */ STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVEC, mtvec) /* Machine Trap-Vector Base Address */ STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVT, mtvt) +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 + STRUCT_FIELD (long, 4, RV_SLP_CTX_MINTTHRESH, mintthresh) /* Machine intr threshold */ // TODO +#endif STRUCT_FIELD (long, 4, RV_SLP_CTX_MCAUSE, mcause) /* Machine Trap Cause */ STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVAL, mtval) /* Machine Trap Value */ STRUCT_FIELD (long, 4, RV_SLP_CTX_MIE, mie) /* Machine intr enable */ diff --git a/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c b/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c index 79d9da85ec04..33387c0c7204 100644 --- a/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c +++ b/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c @@ -402,7 +402,11 @@ static TCM_IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep, } #endif - return (*goto_sleep)(wakeup_opt, reject_opt, lslp_mem_inf_fpu, dslp); + uint32_t reject = (*goto_sleep)(wakeup_opt, reject_opt, lslp_mem_inf_fpu, dslp); + if (reject) { + restore_mstatus(mstatus); + return reject; + } } #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME else { diff --git a/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu_asm.S b/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu_asm.S index 1ae80231d65d..9018ba9c258c 100644 --- a/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu_asm.S +++ b/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu_asm.S @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ #include "soc/cache_reg.h" #define CACHE_MAP_L1_CACHE_MASK (BIT(0) | BIT(1) | BIT(4)) #define MTVT (0x307) +#define MINTTHRESH (0x347) .section .tcm.data,"aw" .global rv_core_critical_regs_frame @@ -93,6 +94,10 @@ rv_core_critical_regs_save: sw t3, RV_SLP_CTX_MCAUSE(t0) csrr t4, MTVT sw t4, RV_SLP_CTX_MTVT(t0) +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 + csrr t4, MINTTHRESH + sw t4, RV_SLP_CTX_MINTTHRESH(t0) +#endif csrr t1, mtval sw t1, RV_SLP_CTX_MTVAL(t0) csrr t2, mie @@ -177,6 +182,10 @@ rv_core_critical_regs_restore: csrw mstatus, t2 lw t4, RV_SLP_CTX_MTVT(t0) csrw MTVT, t4 +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 + lw t1, RV_SLP_CTX_MINTTHRESH(t0) + csrw MINTTHRESH, t1 +#endif lw t3, RV_SLP_CTX_MTVEC(t0) csrw mtvec, t3 lw t1, RV_SLP_CTX_MCAUSE(t0) diff --git a/components/esp_hw_support/modem_clock.c b/components/esp_hw_support/modem_clock.c index f94c8bab5577..1ec54d520edc 100644 --- a/components/esp_hw_support/modem_clock.c +++ b/components/esp_hw_support/modem_clock.c @@ -18,6 +18,9 @@ #include "hal/efuse_hal.h" #include "hal/clk_tree_ll.h" #include "hal/regi2c_ctrl_ll.h" +#if CONFIG_IDF_TARGET_ESP32H2 +#include "soc/rtc.h" +#endif // CONFIG_IDF_TARGET_ESP32H2 // Please define the frequently called modules in the low bit, // which will improve the execution efficiency @@ -380,7 +383,7 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl if (selected) { rc_clk_en = clk_ll_rc32k_is_enabled(); if (!rc_clk_en) { - clk_ll_rc32k_enable(); + rtc_clk_rc32k_enable(true); } modem_clock_hal_select_ble_rtc_timer_lpclk_source(MODEM_CLOCK_instance()->hal, MODEM_CLOCK_LPCLK_SRC_RC32K); } @@ -393,7 +396,7 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl if (!rc_clk_en) { extern void r_esp_ble_rtc_ticks_delay(uint32_t ticks); r_esp_ble_rtc_ticks_delay(2); - clk_ll_rc32k_disable(); + rtc_clk_rc32k_enable(false); } #endif // CONFIG_IDF_TARGET_ESP32H2 #if SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND diff --git a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support index 46f9a88f302c..f1d582651d78 100644 --- a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support +++ b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support @@ -1,3 +1,15 @@ +comment "NOTE! Support of ESP32-P4 rev. <3.0 and >=3.0 is mutually exclusive" +comment "Read the help text of the option below for explanation" + +config ESP32P4_SELECTS_REV_LESS_V3 + bool "Select ESP32-P4 revisions <3.0 (No >=3.x Support)" + default y + help + Select this option to support ESP32-P4 revisions 0.x and 1.x. + Revisions higher than 3.0 (included) and revisions less than 3.0 + have huge hardware difference. + Revisions higher than 3.0 (included) is not compatible with 0.x and 1.x. + choice ESP32P4_REV_MIN prompt "Minimum Supported ESP32-P4 Revision" default ESP32P4_REV_MIN_1 @@ -10,11 +22,17 @@ choice ESP32P4_REV_MIN this will also help to reduce binary size. config ESP32P4_REV_MIN_0 + depends on ESP32P4_SELECTS_REV_LESS_V3 bool "Rev v0.0" config ESP32P4_REV_MIN_1 + depends on ESP32P4_SELECTS_REV_LESS_V3 bool "Rev v0.1" config ESP32P4_REV_MIN_100 + depends on ESP32P4_SELECTS_REV_LESS_V3 bool "Rev v1.0" + config ESP32P4_REV_MIN_300 + bool "Rev v3.0" + depends on !ESP32P4_SELECTS_REV_LESS_V3 endchoice config ESP32P4_REV_MIN_FULL @@ -22,6 +40,7 @@ config ESP32P4_REV_MIN_FULL default 0 if ESP32P4_REV_MIN_0 default 1 if ESP32P4_REV_MIN_1 default 100 if ESP32P4_REV_MIN_100 + default 300 if ESP32P4_REV_MIN_300 config ESP_REV_MIN_FULL int @@ -32,6 +51,9 @@ config ESP_REV_MIN_FULL # comment "Maximum Supported ESP32-P4 Revision (Rev v1.99)" + depends on ESP32P4_SELECTS_REV_LESS_V3 + comment "Maximum Supported ESP32-P4 Revision (Rev v3.99)" + depends on !ESP32P4_SELECTS_REV_LESS_V3 # Maximum revision that IDF supports. # It can not be changed by user. # Only Espressif can change it when a new version will be supported in IDF. @@ -39,7 +61,8 @@ config ESP_REV_MIN_FULL config ESP32P4_REV_MAX_FULL int - default 199 + default 399 if !ESP32P4_SELECTS_REV_LESS_V3 + default 199 if ESP32P4_SELECTS_REV_LESS_V3 # keep in sync the "Maximum Supported Revision" description with this value config ESP_REV_MAX_FULL @@ -59,6 +82,6 @@ config ESP_EFUSE_BLOCK_REV_MIN_FULL config ESP_EFUSE_BLOCK_REV_MAX_FULL int - default 99 + default 199 comment "Maximum Supported ESP32-P4 eFuse Block Revision (eFuse Block Rev v0.99)" # The revision in the comment must correspond to the default value of ESP_EFUSE_BLOCK_REV_MAX_FULL diff --git a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h index 20875057b14e..d1c59a08844a 100644 --- a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h @@ -8,6 +8,7 @@ #include #include #include +#include "sdkconfig.h" #include "soc/soc.h" #include "soc/clk_tree_defs.h" #include "hal/hal_utils.h" @@ -189,6 +190,7 @@ typedef struct { /** * Default initializer for rtc_clk_config_t */ +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 #define RTC_CLK_CONFIG_DEFAULT() { \ .xtal_freq = CONFIG_XTAL_FREQ, \ .cpu_freq_mhz = 90, \ @@ -200,6 +202,19 @@ typedef struct { .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \ } +#else +#define RTC_CLK_CONFIG_DEFAULT() { \ + .xtal_freq = CONFIG_XTAL_FREQ, \ + .cpu_freq_mhz = 100, \ + .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ + .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ + .clk_rtc_clk_div = 0, \ + .clk_8m_clk_div = 0, \ + .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ + .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ + .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \ +} +#endif /** * Initialize clocks and set CPU frequency diff --git a/components/esp_hw_support/port/esp32p4/pmu_init.c b/components/esp_hw_support/port/esp32p4/pmu_init.c index a223985f57de..fe87b90cea93 100644 --- a/components/esp_hw_support/port/esp32p4/pmu_init.c +++ b/components/esp_hw_support/port/esp32p4/pmu_init.c @@ -17,6 +17,7 @@ #include "pmu_param.h" #include "esp_private/esp_pmu.h" #include "soc/regi2c_dig_reg.h" +#include "soc/lp_system_reg.h" #include "regi2c_ctrl.h" #include "esp_rom_sys.h" #include "soc/rtc.h" @@ -132,6 +133,7 @@ static inline void pmu_power_domain_force_default(pmu_context_t *ctx) PMU_HP_PD_TOP, PMU_HP_PD_CNNT, PMU_HP_PD_HPMEM, + PMU_HP_PD_CPU }; for (uint8_t idx = 0; idx < (sizeof(pmu_hp_domains) / sizeof(pmu_hp_power_domain_t)); idx++) { @@ -173,6 +175,7 @@ static void pmu_hp_system_init_default(pmu_context_t *ctx) pmu_hp_system_param_default(mode, ¶m); pmu_hp_system_init(ctx, mode, ¶m); } + REG_SET_FIELD(LP_SYSTEM_REG_HP_MEM_AUX_CTRL_REG, LP_SYSTEM_REG_HP_MEM_AUX_CTRL, 0x2074); } static inline void pmu_lp_system_param_default(pmu_lp_mode_t mode, pmu_lp_system_param_t *param) @@ -189,6 +192,7 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx) pmu_lp_system_param_default(mode, ¶m); pmu_lp_system_init(ctx, mode, ¶m); } + REG_SET_FIELD(LP_SYSTEM_REG_LP_MEM_AUX_CTRL_REG, LP_SYSTEM_REG_LP_MEM_AUX_CTRL, 0x2074); } void pmu_init(void) diff --git a/components/esp_hw_support/port/esp32p4/pmu_param.c b/components/esp_hw_support/port/esp32p4/pmu_param.c index a099e2b2f133..99b410fdce76 100644 --- a/components/esp_hw_support/port/esp32p4/pmu_param.c +++ b/components/esp_hw_support/port/esp32p4/pmu_param.c @@ -343,7 +343,7 @@ uint32_t get_act_hp_dbias(void) uint32_t hp_cali_dbias = HP_CALI_ACTIVE_DBIAS_DEFAULT; uint32_t blk_version = efuse_hal_blk_version(); uint32_t hp_cali_dbias_efuse = 0; - if (blk_version >= 2) { + if (blk_version >= 2 && blk_version < 100) { hp_cali_dbias_efuse = efuse_ll_get_active_hp_dbias(); } if (hp_cali_dbias_efuse > 0) { @@ -364,7 +364,7 @@ uint32_t get_act_lp_dbias(void) uint32_t lp_cali_dbias = LP_CALI_ACTIVE_DBIAS_DEFAULT; uint32_t blk_version = efuse_hal_blk_version(); uint32_t lp_cali_dbias_efuse = 0; - if (blk_version >= 2) { + if (blk_version >= 2 && blk_version < 100) { lp_cali_dbias_efuse = efuse_ll_get_active_lp_dbias(); } if (lp_cali_dbias_efuse > 0) { diff --git a/components/esp_hw_support/port/esp32p4/pmu_pvt.c b/components/esp_hw_support/port/esp32p4/pmu_pvt.c index 03a07258caff..c9c7ca21a424 100644 --- a/components/esp_hw_support/port/esp32p4/pmu_pvt.c +++ b/components/esp_hw_support/port/esp32p4/pmu_pvt.c @@ -34,7 +34,7 @@ static uint8_t get_lp_hp_gap(void) int8_t lp_hp_gap = 0; uint32_t blk_version = efuse_hal_blk_version(); uint8_t lp_hp_gap_efuse = 0; - if (blk_version >= 2) { + if (blk_version >= 2 && blk_version < 100) { lp_hp_gap_efuse = efuse_ll_get_dbias_vol_gap(); bool gap_flag = lp_hp_gap_efuse >> 4; uint8_t gap_abs_value = lp_hp_gap_efuse & 0xf; @@ -78,7 +78,7 @@ static uint32_t pvt_get_lp_dbias(void) void pvt_auto_dbias_init(void) { uint32_t blk_version = efuse_hal_blk_version(); - if (blk_version >= 2) { + if (blk_version >= 2 && blk_version < 100) { SET_PERI_REG_MASK(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN); SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN); /*config for dbias func*/ @@ -121,7 +121,7 @@ void pvt_auto_dbias_init(void) void pvt_func_enable(bool enable) { uint32_t blk_version = efuse_hal_blk_version(); - if (blk_version >= 2){ + if (blk_version >= 2 && blk_version < 100){ if (enable) { SET_PERI_REG_MASK(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN); diff --git a/components/esp_hw_support/port/esp32p4/pmu_sleep.c b/components/esp_hw_support/port/esp32p4/pmu_sleep.c index a2c694aa0df3..19be8ab13278 100644 --- a/components/esp_hw_support/port/esp32p4/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32p4/pmu_sleep.c @@ -30,6 +30,7 @@ #include "hal/pmu_hal.h" #include "hal/psram_ctrlr_ll.h" #include "hal/lp_sys_ll.h" +#include "hal/lp_clkrst_ll.h" #include "hal/clk_gate_ll.h" #include "esp_private/esp_pmu.h" #include "pmu_param.h" @@ -159,7 +160,9 @@ const pmu_sleep_config_t* pmu_sleep_config_default( ) { pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags); - +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 + power_default.hp_sys.dig_power.cpu_pd_en = (sleep_flags & PMU_SLEEP_PD_CPU) ? 1 : 0; +#endif if (dslp) { config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period); @@ -405,6 +408,10 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, #endif rtc_clk_mpll_disable(); } + } else { +#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND + lp_clkrst_ll_boot_from_lp_ram(true); +#endif } @@ -428,12 +435,16 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, ; } -#if CONFIG_SPIRAM && CONFIG_ESP_LDO_RESERVE_PSRAM - // Enable PSRAM chip power supply after deepsleep request rejected if (dslp) { +#if CONFIG_SPIRAM && CONFIG_ESP_LDO_RESERVE_PSRAM + // Enable PSRAM chip power supply after deepsleep request rejected ldo_ll_enable(LDO_ID2UNIT(CONFIG_ESP_LDO_CHAN_PSRAM_DOMAIN), true); - } #endif +#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND + // Set reset vector back to HP ROM after deepsleep request rejected + lp_clkrst_ll_boot_from_lp_ram(false); +#endif + } return pmu_sleep_finish(dslp); } diff --git a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h index 3b26800a16d5..295c3f818075 100644 --- a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h @@ -34,7 +34,7 @@ extern "C" { // FOR LIGHTSLEEP #define PMU_HP_DRVB_LIGHTSLEEP 0 #define PMU_LP_DRVB_LIGHTSLEEP 0 -#define PMU_HP_XPD_LIGHTSLEEP 1 +#define PMU_HP_XPD_LIGHTSLEEP 0 // Always use DCDC power supply in lightsleep #define PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT 0 #define PMU_HP_DBIAS_LIGHTSLEEP_0V6 1 @@ -118,7 +118,12 @@ typedef union { uint32_t dcdc_switch_pd_en: 1; uint32_t mem_dslp : 1; uint32_t mem_pd_en : 1; +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 uint32_t reserved1 : 6; +#else + uint32_t reserved1 : 5; + uint32_t cpu_pd_en : 1; +#endif uint32_t cnnt_pd_en : 1; uint32_t top_pd_en : 1; }; diff --git a/components/esp_hw_support/port/esp32p4/rtc_clk.c b/components/esp_hw_support/port/esp32p4/rtc_clk.c index 709feb2ec30d..cd4dcda340d1 100644 --- a/components/esp_hw_support/port/esp32p4/rtc_clk.c +++ b/components/esp_hw_support/port/esp32p4/rtc_clk.c @@ -220,6 +220,7 @@ static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t * uint32_t mem_divider = 1; uint32_t sys_divider = 1; // We are not going to change this uint32_t apb_divider = 1; +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 switch (cpu_freq_mhz) { case 360: mem_divider = 2; @@ -240,6 +241,28 @@ static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t * // To avoid such case, we will strictly do abort here. abort(); } +#else + switch (cpu_freq_mhz) { + case 400: + mem_divider = 2; + apb_divider = 2; + break; + case 200: + mem_divider = 1; + apb_divider = 2; + break; + case 100: + mem_divider = 1; + apb_divider = 1; + break; + default: + // Unsupported configuration + // This is dangerous to modify dividers. Hardware could automatically correct the divider, and it won't be + // reflected to the registers. Therefore, you won't even be able to calculate out the real mem_clk, apb_clk freq. + // To avoid such case, we will strictly do abort here. + abort(); + } +#endif // If it's upscaling, the divider of MEM/SYS/APB needs to be increased, to avoid illegal intermediate states, // the clock divider should be updated in the order from the APB_CLK to CPU_CLK. @@ -285,6 +308,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou // Keep default CPLL at 360MHz uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get(); +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 if (freq_mhz <= xtal_freq && freq_mhz != 0) { divider.integer = xtal_freq / freq_mhz; real_freq_mhz = (xtal_freq + divider.integer / 2) / divider.integer; /* round */ @@ -292,7 +316,6 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou // no suitable divider return false; } - source_freq_mhz = xtal_freq; source = SOC_CPU_CLK_SRC_XTAL; } else if (freq_mhz == 90) { @@ -310,6 +333,30 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou source = SOC_CPU_CLK_SRC_CPLL; source_freq_mhz = CLK_LL_PLL_360M_FREQ_MHZ; divider.integer = 1; + } else { + // unsupported frequency + return false; + } +#else + if (freq_mhz <= xtal_freq && freq_mhz != 0) { + divider.integer = xtal_freq / freq_mhz; + real_freq_mhz = (xtal_freq + divider.integer / 2) / divider.integer; /* round */ + if (real_freq_mhz != freq_mhz) { + // no suitable divider + return false; + } + source_freq_mhz = xtal_freq; + source = SOC_CPU_CLK_SRC_XTAL; + } else if (freq_mhz == 100) { + real_freq_mhz = freq_mhz; + source = SOC_CPU_CLK_SRC_CPLL; + source_freq_mhz = CLK_LL_PLL_400M_FREQ_MHZ; + divider.integer = 4; + } else if (freq_mhz == 200) { + real_freq_mhz = freq_mhz; + source = SOC_CPU_CLK_SRC_CPLL; + source_freq_mhz = CLK_LL_PLL_400M_FREQ_MHZ; + divider.integer = 2; } else if (freq_mhz == 400) { // If CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ selects 400MHz, then at app startup stage will need a CPLL calibration to raise its freq from 360MHz to 400MHz real_freq_mhz = freq_mhz; @@ -320,6 +367,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou // unsupported frequency return false; } +#endif *out_config = (rtc_cpu_freq_config_t) { .source = source, .div = divider, diff --git a/components/esp_hw_support/port/pau_regdma.c b/components/esp_hw_support/port/pau_regdma.c index 40696e33e8f4..4c992d342319 100644 --- a/components/esp_hw_support/port/pau_regdma.c +++ b/components/esp_hw_support/port/pau_regdma.c @@ -137,8 +137,10 @@ void IRAM_ATTR pau_regdma_trigger_extra_link_restore(void) } #if SOC_PAU_IN_TOP_DOMAIN -void pau_regdma_enable_aon_link_entry(bool enable) +bool IRAM_ATTR pau_regdma_enable_aon_link_entry(bool enable) { + bool origin_bypass_en = lp_sys_ll_get_pau_aon_bypass(); lp_sys_ll_set_pau_aon_bypass(enable); + return origin_bypass_en; } #endif diff --git a/components/esp_hw_support/port/regdma_link.c b/components/esp_hw_support/port/regdma_link.c index 4b40659a93de..d77c2cc213b8 100644 --- a/components/esp_hw_support/port/regdma_link.c +++ b/components/esp_hw_support/port/regdma_link.c @@ -10,6 +10,7 @@ #include #include +#include "sdkconfig.h" #include "esp_private/regdma_link.h" #include "esp_heap_caps.h" @@ -20,7 +21,11 @@ #define REGDMA_LINK_ADDR_ALIGN (4) +#if CONFIG_IDF_TARGET_ESP32P4 +#define REGDMA_LINK_MEM_TYPE_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION) +#else #define REGDMA_LINK_MEM_TYPE_CAPS (MALLOC_CAP_DMA | MALLOC_CAP_DEFAULT) +#endif void * regdma_link_new_continuous(void *backup, void *buff, int len, void *restore, void *next, bool skip_b, bool skip_r, int id, int module) { diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index c3a6afd22a61..ef51be589989 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -23,6 +23,7 @@ #include "soc/rtc.h" #include "esp_private/sleep_event.h" #include "esp_private/system_internal.h" +#include "esp_private/sleep_retention.h" #include "esp_private/io_mux.h" #include "esp_log.h" #include "esp_newlib.h" @@ -79,6 +80,7 @@ #include "esp_private/sleep_console.h" #include "esp_private/sleep_cpu.h" #include "esp_private/sleep_modem.h" +#include "esp_private/sleep_flash.h" #include "esp_private/sleep_usb.h" #include "esp_private/esp_clk.h" #include "esp_private/esp_task_wdt.h" @@ -1039,12 +1041,18 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t sleep_flags, esp_sleep_mode_ } #endif -#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD +#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP if (sleep_flags & PMU_SLEEP_PD_TOP) { +#if SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD esp_sleep_mmu_retention(true); +#endif +#if CONFIG_IDF_TARGET_ESP32P4 && (CONFIG_ESP_REV_MIN_FULL == 300) + sleep_retention_do_extra_retention(true); +#endif } #endif + #if SOC_PMU_SUPPORTED #if SOC_PM_CPU_RETENTION_BY_SW && ESP_SLEEP_POWER_DOWN_CPU esp_sleep_execute_event_callbacks(SLEEP_EVENT_HW_GOTO_SLEEP, (void *)0); @@ -1064,9 +1072,15 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t sleep_flags, esp_sleep_mode_ result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu, deep_sleep); #endif -#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD +#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP if (sleep_flags & PMU_SLEEP_PD_TOP) { +#if SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD esp_sleep_mmu_retention(false); +#endif +#if CONFIG_IDF_TARGET_ESP32P4 && (CONFIG_ESP_REV_MIN_FULL == 300) + sleep_flash_p4_rev3_workaround(); + sleep_retention_do_extra_retention(false); +#endif } #endif @@ -2540,7 +2554,7 @@ static uint32_t get_power_down_flags(void) } #endif -#if SOC_PM_SUPPORT_CPU_PD && ESP_SLEEP_POWER_DOWN_CPU +#if SOC_PM_SUPPORT_CPU_PD && ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 if ((s_config.domain[ESP_PD_DOMAIN_CPU].pd_option != ESP_PD_OPTION_ON) && cpu_domain_pd_allowed()) { pd_flags |= RTC_SLEEP_PD_CPU; } @@ -2584,7 +2598,7 @@ static uint32_t get_power_down_flags(void) #endif #if SOC_PM_SUPPORT_CNNT_PD - if (s_config.domain[ESP_PD_DOMAIN_CNNT].pd_option != ESP_PD_OPTION_ON) { + if (s_config.domain[ESP_PD_DOMAIN_CNNT].pd_option != ESP_PD_OPTION_ON && top_domain_pd_allowed()) { pd_flags |= PMU_SLEEP_PD_CNNT; } #endif diff --git a/components/esp_hw_support/sleep_mspi.c b/components/esp_hw_support/sleep_mspi.c new file mode 100644 index 000000000000..5f0f8bf3c858 --- /dev/null +++ b/components/esp_hw_support/sleep_mspi.c @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "sdkconfig.h" + +#if CONFIG_IDF_TARGET_ESP32P4 && (CONFIG_ESP_REV_MIN_FULL == 300) +#include "soc/hp_system_reg.h" +#include "hal/mmu_ll.h" +#include "hal/mspi_timing_tuning_ll.h" + +void sleep_flash_p4_rev3_workaround(void) +{ + REG_CLR_BIT(SPI_MEM_C_CACHE_FCTRL_REG, SPI_MEM_C_CLOSE_AXI_INF_EN); + REG_SET_BIT(SPI_MEM_C_CACHE_FCTRL_REG, SPI_MEM_C_AXI_REQ_EN); + REG_SET_FIELD(HP_SYSTEM_CORE_ERR_RESP_DIS_REG, HP_SYSTEM_CORE_ERR_RESP_DIS, 0x7); + REG_WRITE(SPI_MEM_C_MMU_ITEM_INDEX_REG, 0); + uint32_t mmu_backup = mmu_ll_read_entry(MMU_LL_FLASH_MMU_ID, 0); + mmu_ll_write_entry(MMU_LL_FLASH_MMU_ID, 0, 0, MMU_TARGET_FLASH0); + __attribute__((unused)) volatile uint32_t val = 0; + val = REG_READ(0x80000000); + val = REG_READ(0x80000080); + mmu_ll_write_entry(MMU_LL_FLASH_MMU_ID, 0, mmu_backup, MMU_TARGET_FLASH0); + _mspi_timing_ll_reset_mspi(); + _mspi_timing_ll_reset_mspi_apb(); + REG_SET_FIELD(HP_SYSTEM_CORE_ERR_RESP_DIS_REG, HP_SYSTEM_CORE_ERR_RESP_DIS, 0); +} +#endif diff --git a/components/esp_hw_support/sleep_retention.c b/components/esp_hw_support/sleep_retention.c index d7b63cb63fbc..4237d28b616e 100644 --- a/components/esp_hw_support/sleep_retention.c +++ b/components/esp_hw_support/sleep_retention.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -962,7 +962,7 @@ void IRAM_ATTR sleep_retention_do_extra_retention(bool backup_or_restore) return; } #if SOC_PAU_IN_TOP_DOMAIN - pau_regdma_enable_aon_link_entry(false); + bool origin_bypass_en = pau_regdma_enable_aon_link_entry(false); #endif // Set extra linked list head pointer to hardware pau_regdma_set_extra_link_addr(s_retention.lists[s_retention.highpri].entries[EXTRA_LINK_NUM]); @@ -976,6 +976,9 @@ void IRAM_ATTR sleep_retention_do_extra_retention(bool backup_or_restore) } else { pau_regdma_trigger_extra_link_restore(); } +#if SOC_PAU_IN_TOP_DOMAIN + pau_regdma_enable_aon_link_entry(origin_bypass_en); +#endif } #if SOC_PM_RETENTION_SW_TRIGGER_REGDMA diff --git a/components/esp_hw_support/sleep_usb.c b/components/esp_hw_support/sleep_usb.c index 50227d1edac5..a1de41e01353 100644 --- a/components/esp_hw_support/sleep_usb.c +++ b/components/esp_hw_support/sleep_usb.c @@ -16,7 +16,7 @@ #if SOC_USB_OTG_SUPPORTED #if SOC_PM_SUPPORT_CNNT_PD -static bool s_usb_utmi_bus_clock_state, s_usb_utmi_stoppclk_state; +static bool s_usb_utmi_bus_clock_state, s_usb_utmi_stoppclk_state, s_usb_dwc_bvalid_override; void sleep_usb_otg_phy_backup_and_disable(void) { @@ -24,6 +24,9 @@ void sleep_usb_otg_phy_backup_and_disable(void) if (!s_usb_utmi_bus_clock_state) { _usb_utmi_ll_enable_bus_clock(true); } + // Forcing BVALID low to ignore the hardware-detected VBUS BVALID signal to suppress USB leakage. + s_usb_dwc_bvalid_override = usb_dwc_ll_get_bvalid_override(&USB_DWC_HS); + usb_dwc_ll_enable_bvalid_override(&USB_DWC_HS, true); s_usb_utmi_stoppclk_state = usb_dwc_ll_get_stoppclk_st(&USB_DWC_HS); usb_dwc_ll_set_stoppclk(&USB_DWC_HS, true); } @@ -31,6 +34,7 @@ void sleep_usb_otg_phy_backup_and_disable(void) void sleep_usb_otg_phy_restore(void) { _usb_utmi_ll_enable_bus_clock(true); + usb_dwc_ll_enable_bvalid_override(&USB_DWC_HS, s_usb_dwc_bvalid_override); usb_dwc_ll_set_stoppclk(&USB_DWC_HS, s_usb_utmi_stoppclk_state); if (!s_usb_utmi_bus_clock_state) { _usb_utmi_ll_enable_bus_clock(false); diff --git a/components/esp_hw_support/test_apps/dma/main/test_gdma.c b/components/esp_hw_support/test_apps/dma/main/test_gdma.c index 334a84e326d6..6545d361ce9b 100644 --- a/components/esp_hw_support/test_apps/dma/main/test_gdma.c +++ b/components/esp_hw_support/test_apps/dma/main/test_gdma.c @@ -153,7 +153,7 @@ TEST_CASE("GDMA channel allocation", "[GDMA]") } static void test_gdma_config_link_list(gdma_channel_handle_t tx_chan, gdma_channel_handle_t rx_chan, - gdma_link_list_handle_t *tx_link_list, gdma_link_list_handle_t *rx_link_list, size_t sram_alignment, bool dma_link_in_ext_mem) + gdma_link_list_handle_t *tx_link_list, gdma_link_list_handle_t *rx_link_list, bool dma_link_in_ext_mem) { gdma_strategy_config_t strategy = { @@ -173,7 +173,6 @@ static void test_gdma_config_link_list(gdma_channel_handle_t tx_chan, gdma_chann // create DMA link list for TX channel (a singly link with 3 nodes) gdma_link_list_config_t tx_link_list_config = { - .buffer_alignment = 1, .item_alignment = 8, // 8-byte alignment required by the AXI-GDMA .num_items = 3, .flags = { @@ -184,7 +183,6 @@ static void test_gdma_config_link_list(gdma_channel_handle_t tx_chan, gdma_chann TEST_ESP_OK(gdma_new_link_list(&tx_link_list_config, tx_link_list)); // create DMA link list for RX channel gdma_link_list_config_t rx_link_list_config = { - .buffer_alignment = sram_alignment, // RX buffer should be aligned to the cache line size, because we will do cache invalidate later .item_alignment = 8, // 8-byte alignment required by the AXI-GDMA .num_items = 5, .flags = { @@ -215,7 +213,7 @@ static void test_gdma_m2m_transaction(gdma_channel_handle_t tx_chan, gdma_channe gdma_link_list_handle_t tx_link_list = NULL; gdma_link_list_handle_t rx_link_list = NULL; - test_gdma_config_link_list(tx_chan, rx_chan, &tx_link_list, &rx_link_list, sram_alignment, dma_link_in_ext_mem); + test_gdma_config_link_list(tx_chan, rx_chan, &tx_link_list, &rx_link_list, dma_link_in_ext_mem); // allocate the source buffer from SRAM uint8_t *src_data = heap_caps_calloc(1, 128, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); @@ -250,10 +248,12 @@ static void test_gdma_m2m_transaction(gdma_channel_handle_t tx_chan, gdma_channe gdma_buffer_mount_config_t tx_buf_mount_config[] = { [0] = { .buffer = src_data, + .buffer_alignment = 1, .length = 64, }, [1] = { .buffer = src_data + 64, + .buffer_alignment = 1, .length = 64, #if !SOC_DMA_CAN_ACCESS_FLASH .flags = { @@ -265,6 +265,7 @@ static void test_gdma_m2m_transaction(gdma_channel_handle_t tx_chan, gdma_channe #if SOC_DMA_CAN_ACCESS_FLASH [2] = { .buffer = (void *)src_string, + .buffer_alignment = 1, .length = src_string_len, .flags = { .mark_eof = true, @@ -277,6 +278,7 @@ static void test_gdma_m2m_transaction(gdma_channel_handle_t tx_chan, gdma_channe gdma_buffer_mount_config_t rx_buf_mount_config = { .buffer = dst_data, + .buffer_alignment = sram_alignment, // RX buffer should be aligned to the cache line size, because we will do cache invalidate later .length = 256, }; TEST_ESP_OK(gdma_link_mount_buffers(rx_link_list, 0, &rx_buf_mount_config, 1, NULL)); @@ -408,7 +410,7 @@ static void test_gdma_m2m_unaligned_buffer_test(uint8_t *dst_data, uint8_t *src_ gdma_link_list_handle_t tx_link_list = NULL; gdma_link_list_handle_t rx_link_list = NULL; - test_gdma_config_link_list(tx_chan, rx_chan, &tx_link_list, &rx_link_list, sram_alignment, false); + test_gdma_config_link_list(tx_chan, rx_chan, &tx_link_list, &rx_link_list, false); // prepare the source data for (int i = 0; i < data_length; i++) { @@ -422,6 +424,7 @@ static void test_gdma_m2m_unaligned_buffer_test(uint8_t *dst_data, uint8_t *src_ gdma_buffer_mount_config_t tx_buf_mount_config[] = { [0] = { .buffer = src_data, + .buffer_alignment = 1, .length = data_length, .flags = { .mark_eof = true, @@ -437,6 +440,7 @@ static void test_gdma_m2m_unaligned_buffer_test(uint8_t *dst_data, uint8_t *src_ TEST_ESP_OK(esp_dma_split_rx_buffer_to_cache_aligned(dst_data + offset_len, data_length, &align_array, &stash_buffer)); for (int i = 0; i < 3; i++) { rx_aligned_buf_mount_config[i].buffer = align_array.aligned_buffer[i].aligned_buffer; + rx_aligned_buf_mount_config[i].buffer_alignment = sram_alignment; rx_aligned_buf_mount_config[i].length = align_array.aligned_buffer[i].length; } TEST_ESP_OK(gdma_link_mount_buffers(rx_link_list, 0, rx_aligned_buf_mount_config, 3, NULL)); diff --git a/components/esp_lcd/Kconfig b/components/esp_lcd/Kconfig index a53f8514a9d5..9d75e26ee210 100644 --- a/components/esp_lcd/Kconfig +++ b/components/esp_lcd/Kconfig @@ -1,10 +1,4 @@ menu "ESP-Driver:LCD Controller Configurations" - config LCD_ENABLE_DEBUG_LOG - bool "Enable debug log" - default n - help - whether to enable the debug log message for LCD driver. - Note that, this option only controls the LCD driver log, won't affect other drivers. if SOC_LCD_RGB_SUPPORTED config LCD_RGB_ISR_IRAM_SAFE @@ -27,14 +21,37 @@ menu "ESP-Driver:LCD Controller Configurations" endif # SOC_LCD_RGB_SUPPORTED if SOC_MIPI_DSI_SUPPORTED - config LCD_DSI_ISR_IRAM_SAFE - bool "DSI LCD ISR IRAM-Safe" - default n + config LCD_DSI_ISR_HANDLER_IN_IRAM + bool "Place DSI ISR handler in IRAM to reduce latency" + default y + select LCD_DSI_OBJ_FORCE_INTERNAL + help + Place DSI ISR handler in IRAM to reduce latency caused by cache miss. + + config LCD_DSI_ISR_CACHE_SAFE + bool "Allow DSI ISR to execute when cache is disabled" if !SPI_FLASH_AUTO_SUSPEND + select LCD_DSI_ISR_HANDLER_IN_IRAM select DW_GDMA_ISR_IRAM_SAFE # relies on DW_GDMA Full trans done interrupt + default n help - Ensure the LCD interrupt is IRAM-Safe by allowing the interrupt handler to be - executable when the cache is disabled (e.g. SPI Flash write). - If you want the LCD driver to keep flushing the screen even when cache ops disabled, - you can enable this option. Note, this will also increase the IRAM usage. + Enable this option to allow the DSI Interrupt Service Routine (ISR) + to execute even when the cache is disabled. This can be useful in scenarios where the cache + might be turned off, but the DSI functionality is still required to operate correctly. + + config LCD_DSI_OBJ_FORCE_INTERNAL + bool + default n + help + This will ensure the DSI driver object will always be allocated in internal RAM. endif # SOC_MIPI_DSI_SUPPORTED + + config LCD_ENABLE_DEBUG_LOG + bool "Force enable debug log" + default n + help + If enabled, LCD driver component will: + 1. ignore the global logging settings + 2. compile all log messages into the binary + 3. set the runtime log level to VERBOSE + Please enable this option by caution, as it will increase the binary size. endmenu diff --git a/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c b/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c index 8fa35c55dc01..2979a1365a94 100644 --- a/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c +++ b/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c @@ -1,19 +1,12 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "soc/soc_caps.h" -#include "esp_check.h" #include "esp_lcd_mipi_dsi.h" #include "esp_clk_tree.h" -#include "esp_private/esp_clk_tree_common.h" #include "mipi_dsi_priv.h" -static const char *TAG = "lcd.dsi.bus"; - #define MIPI_DSI_DEFAULT_TIMEOUT_CLOCK_FREQ_MHZ 10 // TxClkEsc frequency must be configured between 2 and 20 MHz #define MIPI_DSI_DEFAULT_ESCAPE_CLOCK_FREQ_MHZ 18 @@ -38,25 +31,35 @@ esp_err_t esp_lcd_new_dsi_bus(const esp_lcd_dsi_bus_config_t *bus_config, esp_lc dsi_bus->bus_id = bus_id; // Enable the APB clock for accessing the DSI host and bridge registers - DSI_RCC_ATOMIC() { + PERIPH_RCC_ATOMIC() { mipi_dsi_ll_enable_bus_clock(bus_id, true); mipi_dsi_ll_reset_register(bus_id); } // if the clock source is not assigned, fallback to the default clock source - mipi_dsi_phy_clock_source_t phy_clk_src = bus_config->phy_clk_src; + mipi_dsi_phy_pllref_clock_source_t phy_clk_src = bus_config->phy_clk_src; if (phy_clk_src == 0) { - phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT; +#if CONFIG_IDF_TARGET_ESP32P4 && HAL_CONFIG(CHIP_SUPPORT_MIN_REV) < 300 + phy_clk_src = MIPI_DSI_PHY_PLLREF_CLK_SRC_DEFAULT_LEGACY; +#else + phy_clk_src = MIPI_DSI_PHY_PLLREF_CLK_SRC_DEFAULT; +#endif } - esp_clk_tree_enable_src((soc_module_clk_t)phy_clk_src, true); + ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)phy_clk_src, true), err, TAG, "clock source enable failed"); + + // always use the default clock source for the DSI PHY configuration + ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)MIPI_DSI_PHY_CFG_CLK_SRC_DEFAULT, true), err, TAG, "clock source enable failed"); + // enable the clock source for DSI PHY - DSI_CLOCK_SRC_ATOMIC() { - // set clock source for DSI PHY - mipi_dsi_ll_set_phy_clock_source(bus_id, phy_clk_src); + PERIPH_RCC_ATOMIC() { + // set the DSI PHY configuration clock // the configuration clock is used for all modes except the shutdown mode + mipi_dsi_ll_set_phy_config_clock_source(bus_id, MIPI_DSI_PHY_CFG_CLK_SRC_DEFAULT); mipi_dsi_ll_enable_phy_config_clock(bus_id, true); - // enable the clock for generating the serial clock - mipi_dsi_ll_enable_phy_reference_clock(bus_id, true); + // set the DSI PHY PLL reference clock + mipi_dsi_ll_set_phy_pllref_clock_source(bus_id, phy_clk_src); + mipi_dsi_ll_set_phy_pll_ref_clock_div(bus_id, 1); // no division + mipi_dsi_ll_enable_phy_pllref_clock(bus_id, true); } #if CONFIG_PM_ENABLE @@ -135,12 +138,12 @@ esp_err_t esp_lcd_del_dsi_bus(esp_lcd_dsi_bus_handle_t bus) ESP_RETURN_ON_FALSE(bus, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); int bus_id = bus->bus_id; // disable the clock source for DSI PHY - DSI_CLOCK_SRC_ATOMIC() { - mipi_dsi_ll_enable_phy_reference_clock(bus_id, false); + PERIPH_RCC_ATOMIC() { + mipi_dsi_ll_enable_phy_pllref_clock(bus_id, false); mipi_dsi_ll_enable_phy_config_clock(bus_id, false); } // disable the APB clock for accessing the DSI peripheral registers - DSI_RCC_ATOMIC() { + PERIPH_RCC_ATOMIC() { mipi_dsi_ll_enable_bus_clock(bus_id, false); } if (bus->pm_lock) { @@ -150,3 +153,11 @@ esp_err_t esp_lcd_del_dsi_bus(esp_lcd_dsi_bus_handle_t bus) free(bus); return ESP_OK; } + +#if CONFIG_LCD_ENABLE_DEBUG_LOG +__attribute__((constructor)) +static void mipi_dsi_override_default_log_level(void) +{ + esp_log_level_set(TAG, ESP_LOG_VERBOSE); +} +#endif diff --git a/components/esp_lcd/dsi/esp_lcd_panel_dpi.c b/components/esp_lcd/dsi/esp_lcd_panel_dpi.c index 8372bdd19762..131eac9f2eeb 100644 --- a/components/esp_lcd/dsi/esp_lcd_panel_dpi.c +++ b/components/esp_lcd/dsi/esp_lcd_panel_dpi.c @@ -4,26 +4,17 @@ * SPDX-License-Identifier: Apache-2.0 */ #include -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "freertos/semphr.h" -#include "soc/soc_caps.h" -#include "esp_check.h" #include "esp_lcd_panel_interface.h" #include "esp_lcd_mipi_dsi.h" +#include "esp_intr_alloc.h" #include "esp_clk_tree.h" #include "esp_cache.h" #include "mipi_dsi_priv.h" #include "esp_async_fbcpy.h" #include "esp_memory_utils.h" #include "esp_private/dw_gdma.h" -#include "esp_private/esp_clk_tree_common.h" -#include "hal/cache_hal.h" -#include "hal/cache_ll.h" #include "hal/color_hal.h" -static const char *TAG = "lcd.dsi.dpi"; - typedef struct esp_lcd_dpi_panel_t esp_lcd_dpi_panel_t; static esp_err_t dpi_panel_del(esp_lcd_panel_t *panel); @@ -43,7 +34,8 @@ struct esp_lcd_dpi_panel_t { size_t bits_per_pixel; // Bits per pixel lcd_color_format_t in_color_format; // Input color format lcd_color_format_t out_color_format; // Output color format - dw_gdma_channel_handle_t dma_chan; // DMA channel + dw_gdma_channel_handle_t dma_chan; // DMA channel + intr_handle_t brg_intr; // DSI Bridge interrupt handle dw_gdma_link_list_handle_t link_lists[DPI_PANEL_MAX_FB_NUM]; // DMA link list esp_async_fbcpy_handle_t fbcpy_handle; // Use DMA2D to do frame buffer copy SemaphoreHandle_t draw_sem; // A semaphore used to synchronize the draw operations when DMA2D is used @@ -75,25 +67,13 @@ static bool async_fbcpy_done_cb(esp_async_fbcpy_handle_t mcp, esp_async_fbcpy_ev return need_yield; } -IRAM_ATTR -static bool dma_trans_done_cb(dw_gdma_channel_handle_t chan, const dw_gdma_trans_done_event_data_t *event_data, void *user_data) +bool mipi_dsi_dma_trans_done_cb(dw_gdma_channel_handle_t chan, const dw_gdma_trans_done_event_data_t *event_data, void *user_data) { bool yield_needed = false; esp_lcd_dpi_panel_t *dpi_panel = (esp_lcd_dpi_panel_t *)user_data; - mipi_dsi_hal_context_t *hal = &dpi_panel->bus->hal; uint8_t fb_index = dpi_panel->cur_fb_index; dw_gdma_link_list_handle_t link_list = dpi_panel->link_lists[fb_index]; - // clear the interrupt status - uint32_t error_status = mipi_dsi_brg_ll_get_interrupt_status(hal->bridge); - mipi_dsi_brg_ll_clear_interrupt_status(hal->bridge, error_status); - if (unlikely(error_status & MIPI_DSI_LL_EVENT_UNDERRUN)) { - // when an underrun happens, the LCD display may already becomes blue - // it's too late to recover the display, so we just print an error message - // as a hint to the user that he should optimize the memory bandwidth (with AXI-ICM) - ESP_DRAM_LOGE(TAG, "can't fetch data from external memory fast enough, underrun happens"); - } - // restart the DMA transfer, keep refreshing the LCD dw_gdma_block_markers_t markers = { .is_valid = true, @@ -103,15 +83,40 @@ static bool dma_trans_done_cb(dw_gdma_channel_handle_t chan, const dw_gdma_trans dw_gdma_channel_use_link_list(chan, link_list); dw_gdma_channel_enable_ctrl(chan, true); +#if !MIPI_DSI_BRG_LL_EVENT_VSYNC // the DMA descriptor is large enough to carry a whole frame buffer, so this event can also be treated as a fake "vsync end" if (dpi_panel->on_refresh_done) { if (dpi_panel->on_refresh_done(&dpi_panel->base, NULL, dpi_panel->user_ctx)) { yield_needed = true; } } +#endif return yield_needed; } +void mipi_dsi_bridge_isr_handler(void *args) +{ + esp_lcd_dpi_panel_t* dpi_panel = (esp_lcd_dpi_panel_t *)args; + mipi_dsi_hal_context_t *hal = &dpi_panel->bus->hal; + // clear the interrupt status + uint32_t intr_status = mipi_dsi_brg_ll_get_interrupt_status(hal->bridge); + mipi_dsi_brg_ll_clear_interrupt_status(hal->bridge, intr_status); + + if (intr_status & MIPI_DSI_BRG_LL_EVENT_UNDERRUN) { + // when an underrun happens, the LCD display may already becomes blue + // it's too late to recover the display, so we just print an error message + // as a hint to the user that he should optimize the memory bandwidth (with AXI-ICM) + ESP_DRAM_LOGE(TAG, "can't fetch data from external memory fast enough, underrun happens"); + } + if (intr_status & MIPI_DSI_BRG_LL_EVENT_VSYNC) { + if (dpi_panel->on_refresh_done) { + if (dpi_panel->on_refresh_done(&dpi_panel->base, NULL, dpi_panel->user_ctx)) { + portYIELD_FROM_ISR(); + } + } + } +} + // Please note, errors happened in this function is just propagated to the caller // dpi_panel_del() is actually doing the error handling static esp_err_t dpi_panel_create_dma_link(esp_lcd_dpi_panel_t *dpi_panel) @@ -150,7 +155,7 @@ static esp_err_t dpi_panel_create_dma_link(esp_lcd_dpi_panel_t *dpi_panel) // register DMA ISR callbacks dw_gdma_event_callbacks_t dsi_dma_cbs = { - .on_full_trans_done = dma_trans_done_cb, + .on_full_trans_done = mipi_dsi_dma_trans_done_cb, }; ESP_RETURN_ON_ERROR(dw_gdma_channel_register_event_callbacks(dma_chan, &dsi_dma_cbs, dpi_panel), TAG, "register DMA callbacks failed"); @@ -175,7 +180,10 @@ esp_err_t esp_lcd_new_panel_dpi(esp_lcd_dsi_bus_handle_t bus, const esp_lcd_dpi_ } ESP_RETURN_ON_FALSE(num_fbs <= DPI_PANEL_MAX_FB_NUM, ESP_ERR_INVALID_ARG, TAG, "num_fbs not within [1,%d]", DPI_PANEL_MAX_FB_NUM); - size_t bits_per_pixel = 0; + // by default, use RGB888 as the input color format + lcd_color_format_t in_color_format = LCD_COLOR_FMT_RGB888; + size_t bits_per_pixel = 24; + // the deprecated way to set the pixel format switch (panel_config->pixel_format) { case LCD_COLOR_PIXEL_FORMAT_RGB565: bits_per_pixel = 16; @@ -188,15 +196,17 @@ esp_err_t esp_lcd_new_panel_dpi(esp_lcd_dsi_bus_handle_t bus, const esp_lcd_dpi_ bits_per_pixel = 24; break; } - lcd_color_format_t in_color_format = COLOR_TYPE_ID(COLOR_SPACE_RGB, panel_config->pixel_format); - // if user sets the in_color_format, it can override the pixel format setting + in_color_format = COLOR_TYPE_ID(COLOR_SPACE_RGB, panel_config->pixel_format); + // the recommended way to set the input color format if (panel_config->in_color_format) { + in_color_format = panel_config->in_color_format; + // if user sets the in_color_format, it can override the pixel format setting color_space_pixel_format_t in_color_id = { - .color_type_id = panel_config->in_color_format, + .color_type_id = in_color_format, }; bits_per_pixel = color_hal_pixel_format_get_bit_depth(in_color_id); - in_color_format = panel_config->in_color_format; } + // by default, out_color_format is the same as in_color_format (i.e. no color format conversion) lcd_color_format_t out_color_format = in_color_format; if (panel_config->out_color_format) { out_color_format = panel_config->out_color_format; @@ -216,20 +226,16 @@ esp_err_t esp_lcd_new_panel_dpi(esp_lcd_dsi_bus_handle_t bus, const esp_lcd_dpi_ dpi_panel->num_fbs = num_fbs; // allocate frame buffer from PSRAM - uint32_t cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA); - // DMA doesn't have requirement on the buffer alignment, but the cache does - uint32_t alignment = cache_line_size; size_t fb_size = panel_config->video_timing.h_size * panel_config->video_timing.v_size * bits_per_pixel / 8; - uint8_t *frame_buffer = NULL; for (int i = 0; i < num_fbs; i++) { - frame_buffer = heap_caps_aligned_calloc(alignment, 1, fb_size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT); + uint8_t *frame_buffer = heap_caps_calloc(1, fb_size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT | MALLOC_CAP_DMA); ESP_GOTO_ON_FALSE(frame_buffer, ESP_ERR_NO_MEM, err, TAG, "no memory for frame buffer"); dpi_panel->fbs[i] = frame_buffer; ESP_LOGD(TAG, "fb[%d] @%p", i, frame_buffer); // preset the frame buffer with black color - // the frame buffer address alignment is ensured by `heap_caps_aligned_calloc` + // the frame buffer address alignment is ensured by `heap_caps_calloc` // while the value of the fb_size may not be aligned to the cache line size - // but that's not a problem because the `heap_caps_aligned_calloc` internally allocated a buffer whose size is aligned up to the cache line size + // but that's not a problem because the `heap_caps_calloc` internally allocated a buffer whose size is aligned up to the cache line size ESP_GOTO_ON_ERROR(esp_cache_msync(frame_buffer, fb_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED), err, TAG, "cache write back failed"); } @@ -262,7 +268,7 @@ esp_err_t esp_lcd_new_panel_dpi(esp_lcd_dsi_bus_handle_t bus, const esp_lcd_dpi_ uint32_t dpi_div = mipi_dsi_hal_host_dpi_calculate_divider(hal, dpi_clk_src_freq_hz / 1000 / 1000, panel_config->dpi_clock_freq_mhz); esp_clk_tree_enable_src((soc_module_clk_t)dpi_clk_src, true); // set the clock source, set the divider, and enable the dpi clock - DSI_CLOCK_SRC_ATOMIC() { + PERIPH_RCC_ATOMIC() { mipi_dsi_ll_set_dpi_clock_source(bus_id, dpi_clk_src); mipi_dsi_ll_set_dpi_clock_div(bus_id, dpi_div); mipi_dsi_ll_enable_dpi_clock(bus_id, true); @@ -277,11 +283,19 @@ esp_err_t esp_lcd_new_panel_dpi(esp_lcd_dsi_bus_handle_t bus, const esp_lcd_dpi_ esp_pm_lock_acquire(dpi_panel->pm_lock); #endif + // install interrupt service + int isr_flags = ESP_INTR_FLAG_LOWMED; +#if CONFIG_LCD_DSI_ISR_CACHE_SAFE + isr_flags |= ESP_INTR_FLAG_IRAM; +#endif + ESP_GOTO_ON_ERROR(esp_intr_alloc(soc_mipi_dsi_signals[bus_id].brg_irq_id, isr_flags, mipi_dsi_bridge_isr_handler, + dpi_panel, &dpi_panel->brg_intr), err, TAG, "allocate DSI Bridge interrupt failed"); + // create DMA resources ESP_GOTO_ON_ERROR(dpi_panel_create_dma_link(dpi_panel), err, TAG, "initialize DMA link failed"); mipi_dsi_host_ll_dpi_set_vcid(hal->host, panel_config->virtual_channel); - mipi_dsi_hal_host_dpi_set_color_coding(hal, out_color_format, 0); + mipi_dsi_host_ll_dpi_set_color_coding(hal->host, out_color_format, 0); // these signals define how the DPI interface interacts with the controller mipi_dsi_host_ll_dpi_set_timing_polarity(hal->host, false, false, false, false, false); @@ -319,8 +333,9 @@ esp_err_t esp_lcd_new_panel_dpi(esp_lcd_dsi_bus_handle_t bus, const esp_lcd_dpi_ panel_config->video_timing.vsync_front_porch); mipi_dsi_brg_ll_set_num_pixel_bits(hal->bridge, panel_config->video_timing.h_size * panel_config->video_timing.v_size * bits_per_pixel); mipi_dsi_brg_ll_set_underrun_discard_count(hal->bridge, panel_config->video_timing.h_size); - // set input color space - mipi_dsi_brg_ll_set_input_color_space(hal->bridge, COLOR_SPACE_TYPE(in_color_format)); + // set the in/out color formats in the DSI bridge + mipi_dsi_brg_ll_set_input_color_format(hal->bridge, in_color_format); + mipi_dsi_brg_ll_set_output_color_format(hal->bridge, out_color_format, 0); // use the DW_GDMA as the flow controller mipi_dsi_brg_ll_set_flow_controller(hal->bridge, MIPI_DSI_LL_FLOW_CONTROLLER_DMA); mipi_dsi_brg_ll_set_multi_block_number(hal->bridge, DPI_PANEL_MIN_DMA_NODES_PER_LINK); @@ -350,7 +365,7 @@ static esp_err_t dpi_panel_del(esp_lcd_panel_t *panel) int bus_id = bus->bus_id; mipi_dsi_hal_context_t *hal = &bus->hal; // disable the DPI clock - DSI_CLOCK_SRC_ATOMIC() { + PERIPH_RCC_ATOMIC() { mipi_dsi_ll_enable_dpi_clock(bus_id, false); } // disable the DSI bridge @@ -375,6 +390,9 @@ static esp_err_t dpi_panel_del(esp_lcd_panel_t *panel) if (dpi_panel->draw_sem) { vSemaphoreDeleteWithCaps(dpi_panel->draw_sem); } + if (dpi_panel->brg_intr) { + esp_intr_free(dpi_panel->brg_intr); + } if (dpi_panel->pm_lock) { esp_pm_lock_release(dpi_panel->pm_lock); esp_pm_lock_delete(dpi_panel->pm_lock); @@ -452,9 +470,8 @@ static esp_err_t dpi_panel_init(esp_lcd_panel_t *panel) mipi_dsi_brg_ll_enable_dpi_output(hal->bridge, true); mipi_dsi_brg_ll_update_dpi_config(hal->bridge); - // enable the underrun interrupt, we use this as a signal of bandwidth shortage - // note, we opt to not install a dedicated interrupt handler just for this error condition, instead, we check it in the DMA callback - mipi_dsi_brg_ll_enable_interrupt(hal->bridge, MIPI_DSI_LL_EVENT_UNDERRUN, true); + // always enable the interrupt to detect the underflow condition + mipi_dsi_brg_ll_enable_interrupt(hal->bridge, MIPI_DSI_BRG_LL_EVENT_UNDERRUN, true); return ESP_OK; } @@ -568,6 +585,7 @@ esp_err_t esp_lcd_dpi_panel_set_color_conversion(esp_lcd_panel_handle_t panel, c if (dpi_panel->in_color_format == COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422) && COLOR_SPACE_TYPE(dpi_panel->out_color_format) == LCD_COLOR_SPACE_RGB) { // YUV422->RGB + mipi_dsi_brg_ll_set_input_color_range(hal->bridge, config->in_color_range); mipi_dsi_brg_ll_set_yuv_convert_std(hal->bridge, config->spec.yuv.conv_std); mipi_dsi_brg_ll_set_yuv422_pack_order(hal->bridge, config->spec.yuv.yuv422.in_pack_order); } else { @@ -605,7 +623,7 @@ esp_err_t esp_lcd_dpi_panel_register_event_callbacks(esp_lcd_panel_handle_t pane { ESP_RETURN_ON_FALSE(panel && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); esp_lcd_dpi_panel_t *dpi_panel = __containerof(panel, esp_lcd_dpi_panel_t, base); -#if CONFIG_LCD_DSI_ISR_IRAM_SAFE +#if CONFIG_LCD_DSI_ISR_CACHE_SAFE if (cbs->on_color_trans_done) { ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_color_trans_done), ESP_ERR_INVALID_ARG, TAG, "on_color_trans_done callback not in IRAM"); } @@ -615,10 +633,13 @@ esp_err_t esp_lcd_dpi_panel_register_event_callbacks(esp_lcd_panel_handle_t pane if (user_ctx) { ESP_RETURN_ON_FALSE(esp_ptr_internal(user_ctx), ESP_ERR_INVALID_ARG, TAG, "user context not in internal RAM"); } -#endif // CONFIG_LCD_RGB_ISR_IRAM_SAFE +#endif // CONFIG_LCD_DSI_ISR_CACHE_SAFE dpi_panel->on_color_trans_done = cbs->on_color_trans_done; dpi_panel->on_refresh_done = cbs->on_refresh_done; dpi_panel->user_ctx = user_ctx; + // enable the vsync interrupt if the callback is provided + mipi_dsi_brg_ll_enable_interrupt(dpi_panel->bus->hal.bridge, MIPI_DSI_BRG_LL_EVENT_VSYNC, cbs->on_refresh_done != NULL); + return ESP_OK; } diff --git a/components/esp_lcd/dsi/esp_lcd_panel_io_dbi.c b/components/esp_lcd/dsi/esp_lcd_panel_io_dbi.c index 369776958d8c..9ad7782af570 100644 --- a/components/esp_lcd/dsi/esp_lcd_panel_io_dbi.c +++ b/components/esp_lcd/dsi/esp_lcd_panel_io_dbi.c @@ -1,18 +1,12 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "soc/soc_caps.h" -#include "esp_check.h" #include "esp_lcd_panel_io_interface.h" #include "esp_lcd_mipi_dsi.h" #include "mipi_dsi_priv.h" -static const char *TAG = "lcd.dsi.dbi"; - typedef struct esp_lcd_dbi_io_t esp_lcd_dbi_io_t; struct esp_lcd_dbi_io_t { diff --git a/components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h b/components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h index 497b4329bb0b..1a78873968df 100644 --- a/components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h +++ b/components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h @@ -22,7 +22,7 @@ extern "C" { typedef struct { int bus_id; /*!< Select which DSI controller, index from 0 */ uint8_t num_data_lanes; /*!< Number of data lanes, if set to 0, the driver will fallback to use maximum number of lanes */ - mipi_dsi_phy_clock_source_t phy_clk_src; /*!< MIPI DSI PHY clock source */ + mipi_dsi_phy_pllref_clock_source_t phy_clk_src; /*!< The clock source for the PHY PLL */ uint32_t lane_bit_rate_mbps; /*!< Lane bit rate in Mbps */ } esp_lcd_dsi_bus_config_t; diff --git a/components/esp_lcd/dsi/mipi_dsi_priv.h b/components/esp_lcd/dsi/mipi_dsi_priv.h index bb6fd2fe63c2..3df7513e6072 100644 --- a/components/esp_lcd/dsi/mipi_dsi_priv.h +++ b/components/esp_lcd/dsi/mipi_dsi_priv.h @@ -1,29 +1,33 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -#include "hal/mipi_dsi_hal.h" -#include "hal/mipi_dsi_ll.h" +#include +#include "sdkconfig.h" +#if CONFIG_LCD_ENABLE_DEBUG_LOG +// The local log level must be defined before including esp_log.h +// Set the maximum log level for gptimer driver +#define LOG_LOCAL_LEVEL ESP_LOG_VERBOSE +#endif +#include "soc/mipi_dsi_periph.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" +#include "esp_err.h" +#include "esp_log.h" +#include "esp_check.h" +#include "esp_attr.h" #include "esp_heap_caps.h" #include "esp_private/periph_ctrl.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_pm.h" +#include "hal/mipi_dsi_hal.h" +#include "hal/mipi_dsi_ll.h" -#if SOC_PERIPH_CLK_CTRL_SHARED -#define DSI_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC() -#else -#define DSI_CLOCK_SRC_ATOMIC() -#endif - -#if !SOC_RCC_IS_INDEPENDENT -#define DSI_RCC_ATOMIC() PERIPH_RCC_ATOMIC() -#else -#define DSI_RCC_ATOMIC() -#endif - -#if CONFIG_LCD_DSI_ISR_IRAM_SAFE +#if CONFIG_LCD_DSI_OBJ_FORCE_INTERNAL #define DSI_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) #else #define DSI_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT @@ -32,6 +36,9 @@ #define DPI_PANEL_MAX_FB_NUM 3 // maximum number of frame buffers that can be maintained by the driver #define DPI_PANEL_MIN_DMA_NODES_PER_LINK 1 // NOTE: we assume 1 DMA link item can carry the WHOLE image +///!< Logging settings +#define TAG "lcd.dsi" + #ifdef __cplusplus extern "C" { #endif diff --git a/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c b/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c index a73ba64c25b7..51a7cb82c0ce 100644 --- a/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c +++ b/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c @@ -145,7 +145,6 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc size_t num_dma_nodes = esp_dma_calculate_node_count(max_transfer_bytes, 1, LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE); // create DMA link list gdma_link_list_config_t dma_link_config = { - .buffer_alignment = 1, // no special buffer alignment for LCD TX buffer .item_alignment = 4, // 4 bytes alignment for each DMA descriptor .num_items = num_dma_nodes, .flags = { @@ -721,6 +720,7 @@ static void i2s_lcd_trigger_quick_trans_done_event(esp_lcd_i80_bus_handle_t bus) static uint32_t fake_trigger = 0; gdma_buffer_mount_config_t mount_config = { .buffer = &fake_trigger, + .buffer_alignment = 1, // no special buffer alignment for fake trigger .length = 4, .flags = { .mark_eof = true, // mark the "EOF" flag to trigger I2S EOF interrupt @@ -807,6 +807,7 @@ static IRAM_ATTR void i2s_lcd_default_isr_handler(void *args) // mount data to DMA links gdma_buffer_mount_config_t mount_config = { .buffer = (void *)trans_desc->data, + .buffer_alignment = 1, // no special buffer alignment for LCD TX buffer .length = trans_desc->data_length, .flags = { .mark_eof = true, diff --git a/components/esp_lcd/i80/esp_lcd_panel_io_i80.c b/components/esp_lcd/i80/esp_lcd_panel_io_i80.c index ee392c602c3a..cf74d9aada16 100644 --- a/components/esp_lcd/i80/esp_lcd_panel_io_i80.c +++ b/components/esp_lcd/i80/esp_lcd_panel_io_i80.c @@ -491,9 +491,11 @@ static esp_err_t panel_io_i80_tx_param(esp_lcd_panel_io_t *io, int lcd_cmd, cons trans_desc->data = (param && param_len) ? bus->format_buffer : NULL; trans_desc->data_length = trans_desc->data ? param_len : 0; trans_desc->trans_done_cb = NULL; // no callback for parameter transaction + size_t buffer_alignment = esp_ptr_internal(trans_desc->data) ? bus->int_mem_align : bus->ext_mem_align; // mount data to DMA links gdma_buffer_mount_config_t mount_config = { .buffer = (void *)trans_desc->data, + .buffer_alignment = buffer_alignment, .length = trans_desc->data_length, .flags = { .mark_eof = true, @@ -625,7 +627,6 @@ static esp_err_t lcd_i80_init_dma_link(esp_lcd_i80_bus_handle_t bus, const esp_l size_t num_dma_nodes = esp_dma_calculate_node_count(bus->max_transfer_bytes, buffer_alignment, LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE); // create DMA link list gdma_link_list_config_t dma_link_config = { - .buffer_alignment = buffer_alignment, .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN, .num_items = num_dma_nodes, .flags = { diff --git a/components/esp_lcd/linker.lf b/components/esp_lcd/linker.lf index f66d088f22d6..f69efa92bdaf 100644 --- a/components/esp_lcd/linker.lf +++ b/components/esp_lcd/linker.lf @@ -1,17 +1,29 @@ -[mapping:esp_lcd_gdma] +[mapping:esp_lcd_dsi] +archive: libesp_lcd.a +entries: + if LCD_DSI_ISR_HANDLER_IN_IRAM = y: + esp_lcd_panel_dpi: mipi_dsi_dma_trans_done_cb (noflash) + esp_lcd_panel_dpi: mipi_dsi_bridge_isr_handler (noflash) + +[mapping:esp_lcd_dsi_dma] archive: libesp_hw_support.a entries: - if LCD_RGB_ISR_IRAM_SAFE = y: - gdma: gdma_reset (noflash) - gdma: gdma_start (noflash) - gdma_link: gdma_link_get_head_addr (noflash) - if LCD_DSI_ISR_IRAM_SAFE = y: + if LCD_DSI_ISR_HANDLER_IN_IRAM = y: + # Control dw_gdma function placement granularly dw_gdma: dw_gdma_link_list_get_item (noflash) dw_gdma: dw_gdma_lli_set_block_markers (noflash) dw_gdma: dw_gdma_channel_use_link_list (noflash) dw_gdma: dw_gdma_channel_enable_ctrl (noflash) -[mapping:esp_lcd_hal] +[mapping:esp_lcd_rgb_dma] +archive: libesp_hw_support.a +entries: + if LCD_RGB_ISR_IRAM_SAFE = y: + gdma: gdma_reset (noflash) + gdma: gdma_start (noflash) + gdma_link: gdma_link_get_head_addr (noflash) + +[mapping:esp_lcd_rgb_hal] archive: libhal.a entries: if LCD_RGB_ISR_IRAM_SAFE = y: diff --git a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c index cf639f89fb87..e265fb2b58af 100644 --- a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c +++ b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c @@ -934,7 +934,6 @@ static esp_err_t lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *rgb_panel) size_t buffer_alignment = rgb_panel->int_mem_align; size_t num_dma_nodes_per_bounce_buffer = esp_dma_calculate_node_count(rgb_panel->bb_size, buffer_alignment, LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE); gdma_link_list_config_t link_cfg = { - .buffer_alignment = buffer_alignment, .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN, .num_items = num_dma_nodes_per_bounce_buffer * RGB_LCD_PANEL_BOUNCE_BUF_NUM, .flags = { @@ -946,6 +945,7 @@ static esp_err_t lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *rgb_panel) gdma_buffer_mount_config_t mount_cfgs[RGB_LCD_PANEL_BOUNCE_BUF_NUM] = {0}; for (int i = 0; i < RGB_LCD_PANEL_BOUNCE_BUF_NUM; i++) { mount_cfgs[i].buffer = rgb_panel->bounce_buffer[i]; + mount_cfgs[i].buffer_alignment = buffer_alignment; mount_cfgs[i].length = rgb_panel->bb_size; mount_cfgs[i].flags.mark_eof = true; // we use the DMA EOF interrupt to copy the frame buffer (partially) to the bounce buffer } @@ -954,7 +954,6 @@ static esp_err_t lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *rgb_panel) #if RGB_LCD_NEEDS_SEPARATE_RESTART_LINK // create restart link gdma_link_list_config_t restart_link_cfg = { - .buffer_alignment = buffer_alignment, .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN, .num_items = 1, // the restart link only contains one node .flags = { @@ -964,6 +963,7 @@ static esp_err_t lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *rgb_panel) ESP_RETURN_ON_ERROR(gdma_new_link_list(&restart_link_cfg, &rgb_panel->dma_restart_link), TAG, "create DMA restart link list failed"); gdma_buffer_mount_config_t restart_buffer_mount_cfg = { .buffer = rgb_panel->bounce_buffer[0] + restart_skip_bytes, + .buffer_alignment = buffer_alignment, .length = MIN(LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE, rgb_panel->bb_size) - restart_skip_bytes, }; ESP_RETURN_ON_ERROR(gdma_link_mount_buffers(rgb_panel->dma_restart_link, 0, &restart_buffer_mount_cfg, 1, NULL), @@ -977,7 +977,6 @@ static esp_err_t lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *rgb_panel) size_t buffer_alignment = rgb_panel->flags.fb_in_psram ? rgb_panel->ext_mem_align : rgb_panel->int_mem_align; uint32_t num_dma_nodes = esp_dma_calculate_node_count(rgb_panel->fb_size, buffer_alignment, LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE); gdma_link_list_config_t link_cfg = { - .buffer_alignment = buffer_alignment, .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN, .num_items = num_dma_nodes, .flags = { @@ -995,13 +994,13 @@ static esp_err_t lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *rgb_panel) ESP_RETURN_ON_ERROR(gdma_new_link_list(&link_cfg, &rgb_panel->dma_fb_links[i]), TAG, "create frame buffer DMA link failed"); // mount bounce buffers to the DMA link list mount_cfg.buffer = rgb_panel->fbs[i]; + mount_cfg.buffer_alignment = buffer_alignment; ESP_RETURN_ON_ERROR(gdma_link_mount_buffers(rgb_panel->dma_fb_links[i], 0, &mount_cfg, 1, NULL), TAG, "mount DMA frame buffer failed"); } #if RGB_LCD_NEEDS_SEPARATE_RESTART_LINK // create restart link gdma_link_list_config_t restart_link_cfg = { - .buffer_alignment = buffer_alignment, .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN, .num_items = 1, // the restart link only contains one node .flags = { @@ -1011,6 +1010,7 @@ static esp_err_t lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *rgb_panel) ESP_RETURN_ON_ERROR(gdma_new_link_list(&restart_link_cfg, &rgb_panel->dma_restart_link), TAG, "create DMA restart link list failed"); gdma_buffer_mount_config_t restart_buffer_mount_cfg = { .buffer = rgb_panel->fbs[0] + restart_skip_bytes, + .buffer_alignment = buffer_alignment, .length = MIN(LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE, rgb_panel->fb_size) - restart_skip_bytes, .flags.bypass_buffer_align_check = true, // the restart buffer may doesn't match the buffer alignment but it doesn't really matter in this case }; diff --git a/components/esp_lcd/sdkconfig.rename b/components/esp_lcd/sdkconfig.rename new file mode 100644 index 000000000000..789cff053aaa --- /dev/null +++ b/components/esp_lcd/sdkconfig.rename @@ -0,0 +1,4 @@ +# sdkconfig replacement configurations for deprecated options formatted as +# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION + +CONFIG_LCD_DSI_ISR_IRAM_SAFE CONFIG_LCD_DSI_ISR_CACHE_SAFE diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/CMakeLists.txt b/components/esp_lcd/test_apps/mipi_dsi_lcd/CMakeLists.txt index e895a0deedaf..1a1deb0f1ad9 100644 --- a/components/esp_lcd/test_apps/mipi_dsi_lcd/CMakeLists.txt +++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/CMakeLists.txt @@ -9,6 +9,8 @@ project(mipi_dsi_lcd_panel_test) target_add_binary_data(mipi_dsi_lcd_panel_test.elf "resources/pictures/hello.yuv" BINARY) target_add_binary_data(mipi_dsi_lcd_panel_test.elf "resources/pictures/world.yuv" BINARY) +target_add_binary_data(mipi_dsi_lcd_panel_test.elf "resources/pictures/hello.gray" BINARY) +target_add_binary_data(mipi_dsi_lcd_panel_test.elf "resources/pictures/world.gray" BINARY) if(CONFIG_COMPILER_DUMP_RTL_FILES) add_custom_target(check_test_app_sections ALL diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/CMakeLists.txt b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/CMakeLists.txt index 8ee501adaed3..842c50afd099 100644 --- a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/CMakeLists.txt +++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/CMakeLists.txt @@ -2,7 +2,7 @@ set(srcs "test_app_main.c" "test_mipi_dsi_board.c" "test_mipi_dsi_panel.c") -if(CONFIG_LCD_DSI_ISR_IRAM_SAFE) +if(CONFIG_LCD_DSI_ISR_CACHE_SAFE) list(APPEND srcs "test_mipi_dsi_iram.c") endif() diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_iram.c b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_iram.c index 51299acb8c99..724fd369b1c9 100644 --- a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_iram.c +++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_iram.c @@ -46,7 +46,6 @@ TEST_CASE("MIPI DSI draw bitmap (EK79007) IRAM Safe", "[mipi_dsi]") esp_lcd_dsi_bus_config_t bus_config = { .bus_id = 0, .num_data_lanes = 2, - .phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT, .lane_bit_rate_mbps = 1000, // 1000 Mbps }; TEST_ESP_OK(esp_lcd_new_dsi_bus(&bus_config, &mipi_dsi_bus)); diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c index aa5579c0d349..5719c2ef233a 100644 --- a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c +++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c @@ -28,7 +28,6 @@ TEST_CASE("MIPI DSI Pattern Generator (EK79007)", "[mipi_dsi]") esp_lcd_dsi_bus_config_t bus_config = { .bus_id = 0, .num_data_lanes = 2, - .phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT, .lane_bit_rate_mbps = 1000, // 1000 Mbps }; TEST_ESP_OK(esp_lcd_new_dsi_bus(&bus_config, &mipi_dsi_bus)); @@ -89,7 +88,7 @@ TEST_CASE("MIPI DSI Pattern Generator (EK79007)", "[mipi_dsi]") #define TEST_IMG_SIZE (100 * 100 * sizeof(uint16_t)) -TEST_CASE("MIPI DSI draw bitmap (EK79007)", "[mipi_dsi]") +TEST_CASE("MIPI DSI draw RGB bitmap (EK79007)", "[mipi_dsi]") { esp_lcd_dsi_bus_handle_t mipi_dsi_bus; esp_lcd_panel_io_handle_t mipi_dbi_io; @@ -103,7 +102,6 @@ TEST_CASE("MIPI DSI draw bitmap (EK79007)", "[mipi_dsi]") esp_lcd_dsi_bus_config_t bus_config = { .bus_id = 0, .num_data_lanes = 2, - .phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT, .lane_bit_rate_mbps = 1000, // 1000 Mbps }; TEST_ESP_OK(esp_lcd_new_dsi_bus(&bus_config, &mipi_dsi_bus)); @@ -164,7 +162,7 @@ TEST_CASE("MIPI DSI draw bitmap (EK79007)", "[mipi_dsi]") test_bsp_disable_dsi_phy_power(); } -TEST_CASE("MIPI DSI with multiple frame buffers (EK79007)", "[mipi_dsi]") +TEST_CASE("MIPI DSI use multiple frame buffers (EK79007)", "[mipi_dsi]") { esp_lcd_dsi_bus_handle_t mipi_dsi_bus; esp_lcd_panel_io_handle_t mipi_dbi_io; @@ -175,7 +173,6 @@ TEST_CASE("MIPI DSI with multiple frame buffers (EK79007)", "[mipi_dsi]") esp_lcd_dsi_bus_config_t bus_config = { .bus_id = 0, .num_data_lanes = 2, - .phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT, .lane_bit_rate_mbps = 1000, // 1000 Mbps }; TEST_ESP_OK(esp_lcd_new_dsi_bus(&bus_config, &mipi_dsi_bus)); @@ -244,7 +241,7 @@ TEST_CASE("MIPI DSI with multiple frame buffers (EK79007)", "[mipi_dsi]") test_bsp_disable_dsi_phy_power(); } -TEST_CASE("MIPI DSI draw YUV422 (EK79007)", "[mipi_dsi]") +TEST_CASE("MIPI DSI draw YUV422 image (EK79007)", "[mipi_dsi]") { esp_lcd_dsi_bus_handle_t mipi_dsi_bus; esp_lcd_panel_io_handle_t mipi_dbi_io; @@ -252,13 +249,9 @@ TEST_CASE("MIPI DSI draw YUV422 (EK79007)", "[mipi_dsi]") test_bsp_enable_dsi_phy_power(); - uint8_t *img = malloc(TEST_IMG_SIZE); - TEST_ASSERT_NOT_NULL(img); - esp_lcd_dsi_bus_config_t bus_config = { .bus_id = 0, .num_data_lanes = 2, - .phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT, .lane_bit_rate_mbps = 1000, // 1000 Mbps }; TEST_ESP_OK(esp_lcd_new_dsi_bus(&bus_config, &mipi_dsi_bus)); @@ -289,10 +282,6 @@ TEST_CASE("MIPI DSI draw YUV422 (EK79007)", "[mipi_dsi]") .vsync_pulse_width = MIPI_DSI_LCD_VSYNC, .vsync_front_porch = MIPI_DSI_LCD_VFP, }, - - .flags = { - .use_dma2d = true, - } }; ek79007_vendor_config_t vendor_config = { .mipi_config = { @@ -337,7 +326,88 @@ TEST_CASE("MIPI DSI draw YUV422 (EK79007)", "[mipi_dsi]") TEST_ESP_OK(esp_lcd_panel_del(mipi_dpi_panel)); TEST_ESP_OK(esp_lcd_panel_io_del(mipi_dbi_io)); TEST_ESP_OK(esp_lcd_del_dsi_bus(mipi_dsi_bus)); - free(img); test_bsp_disable_dsi_phy_power(); } + +#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL < 300) + +TEST_CASE("MIPI DSI draw Gray8 image (EK79007)", "[mipi_dsi]") +{ + esp_lcd_dsi_bus_handle_t mipi_dsi_bus; + esp_lcd_panel_io_handle_t mipi_dbi_io; + esp_lcd_panel_handle_t mipi_dpi_panel; + + test_bsp_enable_dsi_phy_power(); + + esp_lcd_dsi_bus_config_t bus_config = { + .bus_id = 0, + .num_data_lanes = 2, + .lane_bit_rate_mbps = 1000, // 1000 Mbps + }; + TEST_ESP_OK(esp_lcd_new_dsi_bus(&bus_config, &mipi_dsi_bus)); + + esp_lcd_dbi_io_config_t dbi_config = { + .virtual_channel = 0, + .lcd_cmd_bits = 8, + .lcd_param_bits = 8, + }; + TEST_ESP_OK(esp_lcd_new_panel_io_dbi(mipi_dsi_bus, &dbi_config, &mipi_dbi_io)); + + esp_lcd_dpi_panel_config_t dpi_config = { + .dpi_clk_src = MIPI_DSI_DPI_CLK_SRC_DEFAULT, + .dpi_clock_freq_mhz = MIPI_DSI_DPI_CLK_MHZ, + .virtual_channel = 0, + + // Gray8 -> RGB888 + .in_color_format = LCD_COLOR_FMT_GRAY8, + .out_color_format = LCD_COLOR_FMT_RGB888, + + .video_timing = { + .h_size = MIPI_DSI_LCD_H_RES, + .v_size = MIPI_DSI_LCD_V_RES, + .hsync_back_porch = MIPI_DSI_LCD_HBP, + .hsync_pulse_width = MIPI_DSI_LCD_HSYNC, + .hsync_front_porch = MIPI_DSI_LCD_HFP, + .vsync_back_porch = MIPI_DSI_LCD_VBP, + .vsync_pulse_width = MIPI_DSI_LCD_VSYNC, + .vsync_front_porch = MIPI_DSI_LCD_VFP, + }, + }; + ek79007_vendor_config_t vendor_config = { + .mipi_config = { + .dsi_bus = mipi_dsi_bus, + .dpi_config = &dpi_config, + }, + }; + esp_lcd_panel_dev_config_t lcd_dev_config = { + .reset_gpio_num = -1, + .rgb_ele_order = LCD_RGB_ELEMENT_ORDER_RGB, + .bits_per_pixel = 24, + .vendor_config = &vendor_config, + }; + TEST_ESP_OK(esp_lcd_new_panel_ek79007(mipi_dbi_io, &lcd_dev_config, &mipi_dpi_panel)); + + TEST_ESP_OK(esp_lcd_panel_reset(mipi_dpi_panel)); + TEST_ESP_OK(esp_lcd_panel_init(mipi_dpi_panel)); + + // YUV images are embedded in the firmware binary + extern const uint8_t image_hello_gray_start[] asm("_binary_hello_gray_start"); + extern const uint8_t image_world_gray_start[] asm("_binary_world_gray_start"); + + printf("Draw Gray8 images\r\n"); + for (int i = 0; i < 4; i++) { + TEST_ESP_OK(esp_lcd_panel_draw_bitmap(mipi_dpi_panel, 0, 0, 320, 320, image_hello_gray_start)); + vTaskDelay(pdMS_TO_TICKS(1000)); + TEST_ESP_OK(esp_lcd_panel_draw_bitmap(mipi_dpi_panel, 0, 0, 320, 320, image_world_gray_start)); + vTaskDelay(pdMS_TO_TICKS(1000)); + } + + TEST_ESP_OK(esp_lcd_panel_del(mipi_dpi_panel)); + TEST_ESP_OK(esp_lcd_panel_io_del(mipi_dbi_io)); + TEST_ESP_OK(esp_lcd_del_dsi_bus(mipi_dsi_bus)); + + test_bsp_disable_dsi_phy_power(); +} + +#endif diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/pytest_mipi_dsi_lcd.py b/components/esp_lcd/test_apps/mipi_dsi_lcd/pytest_mipi_dsi_lcd.py index 7e4dc07e7d12..36c324bb4cdd 100644 --- a/components/esp_lcd/test_apps/mipi_dsi_lcd/pytest_mipi_dsi_lcd.py +++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/pytest_mipi_dsi_lcd.py @@ -9,7 +9,7 @@ @pytest.mark.parametrize( 'config', [ - 'iram_safe', + 'cache_safe', 'release', ], indirect=True, diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/README.md b/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/README.md index 5822bbd7732d..c5214c3efc10 100644 --- a/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/README.md +++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/README.md @@ -1,7 +1,7 @@ -# How to generate the YUV image from the PNG image +# How to get a YUV image from a PNG image ```bash -ffmpeg -i hello.png -pix_fmt yuyv422 hello.yuv +ffmpeg -i hello.png -pix_fmt yuyv422 -f rawvideo hello.yuv ``` ## Supported YUV422 packing order @@ -11,3 +11,9 @@ ffmpeg -i hello.png -pix_fmt yuyv422 hello.yuv | yuyv422 | 3 | 16 | 8-8-8 | | yvyu422 | 3 | 16 | 8-8-8 | | uyvy422 | 3 | 16 | 8-8-8 | + +# How to get a gray8 raw image from a PNG image + +```bash +ffmpeg -i hello.png -vf format=gray -pix_fmt gray -f rawvideo hello.gray +``` diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/pictures/hello.gray b/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/pictures/hello.gray new file mode 100644 index 000000000000..b1454882dd74 --- /dev/null +++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/pictures/hello.gray @@ -0,0 +1 @@ +hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh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\ No newline at end of file diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/sdkconfig.ci.iram_safe b/components/esp_lcd/test_apps/mipi_dsi_lcd/sdkconfig.ci.cache_safe similarity index 84% rename from components/esp_lcd/test_apps/mipi_dsi_lcd/sdkconfig.ci.iram_safe rename to components/esp_lcd/test_apps/mipi_dsi_lcd/sdkconfig.ci.cache_safe index 9d1d9f005f35..981a29a4c31a 100644 --- a/components/esp_lcd/test_apps/mipi_dsi_lcd/sdkconfig.ci.iram_safe +++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/sdkconfig.ci.cache_safe @@ -1,8 +1,9 @@ CONFIG_COMPILER_DUMP_RTL_FILES=y +CONFIG_LCD_DSI_ISR_CACHE_SAFE=y CONFIG_COMPILER_OPTIMIZATION_NONE=y # silent the error check, as the error string are stored in rodata, causing RTL check failure CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y +CONFIG_HAL_ASSERTION_SILENT=y # place non-ISR FreeRTOS functions in Flash CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y -CONFIG_LCD_DSI_ISR_IRAM_SAFE=y diff --git a/components/esp_pm/Kconfig b/components/esp_pm/Kconfig index b4fbae2b2c7f..77902966f156 100644 --- a/components/esp_pm/Kconfig +++ b/components/esp_pm/Kconfig @@ -85,7 +85,7 @@ menu "Power Management" config PM_CHECK_SLEEP_RETENTION_FRAME bool depends on (PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP || \ - (SOC_CPU_IN_TOP_DOMAIN && PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)) + (ESP32P4_SELECTS_REV_LESS_V3 && PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)) default y if IDF_CI_BUILD default n help @@ -108,7 +108,7 @@ menu "Power Management" config PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP bool "Power down CPU in light sleep" - depends on SOC_PM_SUPPORT_CPU_PD + depends on SOC_PM_SUPPORT_CPU_PD && !ESP32P4_SELECTS_REV_LESS_V3 select PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP if ESP32S3_DATA_CACHE_16KB default y help @@ -143,7 +143,9 @@ menu "Power Management" config PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP bool "Power down Digital Peripheral in light sleep (EXPERIMENTAL)" depends on SOC_PM_SUPPORT_TOP_PD && SOC_PAU_SUPPORTED - select PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP if !SOC_CPU_IN_TOP_DOMAIN + depends on !(IDF_TARGET_ESP32P4 && (ESP_REV_MIN_FULL = 300) && SPIRAM) + select PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP if !ESP32P4_SELECTS_REV_LESS_V3 + select ESP_SLEEP_POWER_DOWN_FLASH if (IDF_TARGET_ESP32P4 && (ESP_REV_MIN_FULL = 300)) default n #TODO: enable by default if periph init/deinit management supported (WIFI-5252) help If enabled, digital peripherals will try to powered down in light sleep, then all related peripherals will diff --git a/components/esp_pm/linker.lf b/components/esp_pm/linker.lf index 050349e87667..c03c1b317185 100644 --- a/components/esp_pm/linker.lf +++ b/components/esp_pm/linker.lf @@ -30,7 +30,7 @@ entries: sleep_gpio:gpio_sleep_mode_config_apply (noflash) if SOC_PM_CPU_RETENTION_BY_RTCCNTL = y && (PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP = y || SOC_PM_SUPPORT_TAGMEM_PD = y): sleep_cpu:sleep_enable_cpu_retention (noflash) - if PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP = y || (SOC_CPU_IN_TOP_DOMAIN = y && PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP = y): + if PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP = y || (ESP32P4_SELECTS_REV_LESS_V3 = y && PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP = y): sleep_cpu:cpu_domain_pd_allowed (noflash) if SOC_PM_SUPPORT_TOP_PD = y: sleep_clock:clock_domain_pd_allowed (noflash) diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index d8da4dd6875f..f77a86fa3051 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -101,7 +101,12 @@ if(target STREQUAL "linux") target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-integer-overflow -Wno-shift-count-overflow) endif() else() - target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.ld") + # TODO: IDF-13410. Update to (CONFIG_ESP32P4_REV_MIN_FULL GREATER_EQUAL 200) when chip efuse is correct. + if(CONFIG_ESP32P4_REV_MIN_300) + target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.eco5.ld") + else() + target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.ld") + endif() rom_linker_script("api") if(NOT CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY) if(target STREQUAL "esp32s3" OR target STREQUAL "esp32c3") @@ -110,9 +115,17 @@ else() endif() if(CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB) - rom_linker_script("libgcc") + if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410 + rom_linker_script("eco5.libgcc") + else() + rom_linker_script("libgcc") + endif() else() - rom_linker_script("rvfp") + if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410. + rom_linker_script("eco5.rvfp") + else() + rom_linker_script("rvfp") + endif() endif() endif() @@ -151,6 +164,18 @@ if(BOOTLOADER_BUILD) endif() endif() + if(CONFIG_ESP_ROM_HAS_NEWLIB) + if(target STREQUAL "esp32" OR target STREQUAL "esp32s2") + rom_linker_script("newlib-funcs") + else() + if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410 + rom_linker_script("eco5.newlib") + else() + rom_linker_script("newlib") + endif() + endif() + endif() + else() # Regular app build if(target STREQUAL "esp32") @@ -284,7 +309,11 @@ else() # Regular app build if(CONFIG_ESP_ROM_HAS_NEWLIB AND NOT target STREQUAL "esp32" AND NOT target STREQUAL "esp32s2") # ESP32 and S2 are a bit different, keep them as special cases in the target specific include section - rom_linker_script("newlib") + if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410 + rom_linker_script("eco5.newlib") + else() + rom_linker_script("newlib") + endif() if(CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT AND CONFIG_NEWLIB_NANO_FORMAT) if(NOT CONFIG_ESP_ROM_HAS_NEWLIB_32BIT_TIME AND NOT CONFIG_ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG) diff --git a/components/esp_rom/esp32/ld/esp32.rom.ld b/components/esp_rom/esp32/ld/esp32.rom.ld index 9b14c00e4775..8fd3ab18c10a 100644 --- a/components/esp_rom/esp32/ld/esp32.rom.ld +++ b/components/esp_rom/esp32/ld/esp32.rom.ld @@ -663,6 +663,7 @@ PROVIDE ( ld_acl_clk_isr = 0x40030cf8 ); PROVIDE ( ld_acl_rsw_frm_cbk = 0x40033bb0 ); PROVIDE ( ld_sco_modify = 0x40031778 ); PROVIDE ( lm_cmd_cmp_send = 0x40051838 ); +PROVIDE ( ld_sco_resched_cbk = 0x40031a10 ); PROVIDE ( ld_sco_frm_cbk = 0x400349dc ); PROVIDE ( ld_sco_evt_start_cbk = 0x40031afc ); PROVIDE ( ld_sco_evt_stop_cbk = 0x40031d78 ); @@ -1637,6 +1638,7 @@ PROVIDE ( lc_pwr_incr_ind_handler = 0x400284a8 ); PROVIDE ( lc_pwr_max_ind_handler = 0x40028690 ); PROVIDE ( lc_setup_sync_param_check = 0x4002354c ); PROVIDE ( lc_lmp_rsp_to_flow_spec_handler = 0x400297f0 ); +PROVIDE ( lc_lmp_rsp_to_ind_handler = 0x4002a674 ); PROVIDE ( lc_pca_sscan_clk_ind_handler = 0x4002a38c ); PROVIDE ( lc_op_loc_unsniff_req_handler = 0x40028be0 ); PROVIDE ( lc_op_loc_sniff_req_handler = 0x40028ccc ); diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld index 59bd96d5c56e..a76958638a7b 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld @@ -661,7 +661,7 @@ r_ble_lll_adv_sync_tx_start_cb = 0x400014a8; r_ble_lll_adv_tx_done = 0x400014ac; r_ble_lll_adv_tx_start_cb = 0x400014b0; r_ble_lll_adv_update_rsp_offset = 0x400014b4; -r_ble_lll_aux_scan_cb = 0x400014b8; +//r_ble_lll_aux_scan_cb = 0x400014b8; r_ble_lll_aux_scan_drop = 0x400014bc; r_ble_lll_aux_scan_drop_event_cb = 0x400014c0; r_ble_lll_calc_us_convert_tick_unit = 0x400014c4; @@ -773,7 +773,7 @@ r_ble_lll_rfmgmt_release_ev = 0x40001668; //r_ble_lll_rfmgmt_reset = 0x4000166c; r_ble_lll_rfmgmt_scan_changed = 0x40001670; r_ble_lll_rfmgmt_sched_changed = 0x40001674; -r_ble_lll_rfmgmt_set_sleep_cb = 0x40001678; +//r_ble_lll_rfmgmt_set_sleep_cb = 0x40001678; r_ble_lll_rfmgmt_ticks_to_enabled = 0x4000167c; //r_ble_lll_rfmgmt_timer_exp = 0x40001680; //r_ble_lll_rfmgmt_timer_reschedule = 0x40001684; @@ -825,7 +825,7 @@ r_ble_lll_sched_dtm = 0x40001738; r_ble_lll_sched_env_init = 0x4000173c; r_ble_lll_sched_execute_check = 0x40001740; r_ble_lll_sched_execute_item = 0x40001744; -r_ble_lll_sched_init = 0x40001748; +//r_ble_lll_sched_init = 0x40001748; r_ble_lll_sched_insert_if_empty = 0x4000174c; r_ble_lll_sched_is_overlap = 0x40001750; r_ble_lll_sched_master_new = 0x40001754; @@ -904,7 +904,7 @@ r_ble_phy_sequence_is_running = 0x40001874; r_ble_phy_sequence_is_waiting_rsp = 0x40001878; r_ble_phy_sequence_single_end = 0x4000187c; r_ble_phy_sequence_tx_end_invoke = 0x40001880; -r_ble_phy_sequence_update_conn_ind_params = 0x40001884; +//r_ble_phy_sequence_update_conn_ind_params = 0x40001884; r_ble_phy_set_adv_mode = 0x40001888; r_ble_phy_set_coex_pti = 0x4000188c; r_ble_phy_set_conn_ind_pdu = 0x40001890; diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld index a0d2795b4d67..90154f4b0ebd 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld @@ -533,7 +533,7 @@ r_ble_lll_adv_sync_tx_start_cb = 0x400014a8; r_ble_lll_adv_tx_done = 0x400014ac; r_ble_lll_adv_tx_start_cb = 0x400014b0; r_ble_lll_adv_update_rsp_offset = 0x400014b4; -r_ble_lll_aux_scan_cb = 0x400014b8; +//r_ble_lll_aux_scan_cb = 0x400014b8; r_ble_lll_aux_scan_drop = 0x400014bc; r_ble_lll_aux_scan_drop_event_cb = 0x400014c0; r_ble_lll_calc_us_convert_tick_unit = 0x400014c4; @@ -613,7 +613,7 @@ r_ble_lll_per_adv_coex_dpc_update_on_start = 0x40001640; //r_ble_lll_rfmgmt_release = 0x40001664; r_ble_lll_rfmgmt_scan_changed = 0x40001670; r_ble_lll_rfmgmt_sched_changed = 0x40001674; -r_ble_lll_rfmgmt_set_sleep_cb = 0x40001678; +//r_ble_lll_rfmgmt_set_sleep_cb = 0x40001678; r_ble_lll_rfmgmt_ticks_to_enabled = 0x4000167c; r_ble_lll_rx_pdu_in = 0x40001688; r_ble_lll_rx_pkt_in = 0x4000168c; @@ -715,7 +715,7 @@ r_ble_phy_sequence_is_running = 0x40001874; r_ble_phy_sequence_is_waiting_rsp = 0x40001878; r_ble_phy_sequence_single_end = 0x4000187c; r_ble_phy_sequence_tx_end_invoke = 0x40001880; -r_ble_phy_sequence_update_conn_ind_params = 0x40001884; +//r_ble_phy_sequence_update_conn_ind_params = 0x40001884; r_ble_phy_set_coex_pti = 0x4000188c; r_ble_phy_set_conn_ind_pdu = 0x40001890; r_ble_phy_set_dev_address = 0x40001898; diff --git a/components/esp_rom/esp32p4/esp_rom_caps.h b/components/esp_rom/esp32p4/esp_rom_caps.h index 3ef8fb4a30d9..dbcf8bd05ebd 100644 --- a/components/esp_rom/esp32p4/esp_rom_caps.h +++ b/components/esp_rom/esp32p4/esp_rom_caps.h @@ -24,5 +24,5 @@ #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG (1) // ROM has the printf float bug with newlib nano version #define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information -#define ESP_ROM_CLIC_INT_TYPE_PATCH (1) // ROM api esprv_intc_int_set_type configuring edge type interrupt is invalid +#define ESP_ROM_CLIC_INT_TYPE_PATCH (1) // ROM api esprv_intc_int_set_type configuring edge type interrupt is invalid TODO: IDF-13409 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.ld new file mode 100644 index 000000000000..a60e9d0b0774 --- /dev/null +++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.ld @@ -0,0 +1,614 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32p4.rom.ld for esp32p4 + * + * + * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum 56d78222be1daa0502090a078288f4d5 + * + * Compatible with ROM where ECO version equal or greater to 5. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group common + ***************************************/ + +/* Functions */ +rtc_get_reset_reason = 0x4fc00018; +rtc_get_wakeup_cause = 0x4fc0001c; +pmu_enable_unhold_pads = 0x4fc00020; +ets_printf = 0x4fc00024; +ets_install_putc1 = 0x4fc00028; +ets_install_putc2 = 0x4fc0002c; +ets_install_uart_printf = 0x4fc00030; +ets_install_usb_printf = 0x4fc00034; +ets_get_printf_channel = 0x4fc00038; +ets_delay_us = 0x4fc0003c; +ets_get_cpu_frequency = 0x4fc00040; +ets_update_cpu_frequency = 0x4fc00044; +ets_install_lock = 0x4fc00048; +UartRxString = 0x4fc0004c; +UartGetCmdLn = 0x4fc00050; +uart_tx_one_char = 0x4fc00054; +uart_tx_one_char2 = 0x4fc00058; +uart_tx_one_char3 = 0x4fc0005c; +uart_rx_one_char = 0x4fc00060; +uart_rx_one_char_block = 0x4fc00064; +uart_rx_intr_handler = 0x4fc00068; +uart_rx_readbuff = 0x4fc0006c; +uartAttach = 0x4fc00070; +uart_tx_flush = 0x4fc00074; +uart_tx_wait_idle = 0x4fc00078; +uart_div_modify = 0x4fc0007c; +ets_write_char_uart = 0x4fc00080; +uart_tx_switch = 0x4fc00084; +uart_buff_switch = 0x4fc00088; +roundup2 = 0x4fc0008c; +multofup = 0x4fc00090; +software_reset = 0x4fc00094; +software_reset_cpu = 0x4fc00098; +ets_clk_assist_debug_clock_enable = 0x4fc0009c; +clear_super_wdt_reset_flag = 0x4fc000a0; +disable_default_watchdog = 0x4fc000a4; +ets_set_appcpu_boot_addr = 0x4fc000a8; +send_packet = 0x4fc000ac; +recv_packet = 0x4fc000b0; +GetUartDevice = 0x4fc000b4; +UartDwnLdProc = 0x4fc000b8; +GetSecurityInfoProc = 0x4fc000bc; +Uart_Init = 0x4fc000c0; +ets_set_user_start = 0x4fc000c4; +/* Data (.data, .bss, .rodata) */ +ets_rom_layout_p = 0x4fc1fffc; +ets_ops_table_ptr = 0x4ffbfff4; +g_saved_pc = 0x4ffbfff8; + + +/*************************************** + Group miniz + ***************************************/ + +/* Functions */ +mz_adler32 = 0x4fc000c8; +mz_free = 0x4fc000cc; +tdefl_compress = 0x4fc000d0; +tdefl_compress_buffer = 0x4fc000d4; +tdefl_compress_mem_to_heap = 0x4fc000d8; +tdefl_compress_mem_to_mem = 0x4fc000dc; +tdefl_compress_mem_to_output = 0x4fc000e0; +tdefl_get_adler32 = 0x4fc000e4; +tdefl_get_prev_return_status = 0x4fc000e8; +tdefl_init = 0x4fc000ec; +tdefl_write_image_to_png_file_in_memory = 0x4fc000f0; +tdefl_write_image_to_png_file_in_memory_ex = 0x4fc000f4; +tinfl_decompress = 0x4fc000f8; +tinfl_decompress_mem_to_callback = 0x4fc000fc; +tinfl_decompress_mem_to_heap = 0x4fc00100; +tinfl_decompress_mem_to_mem = 0x4fc00104; + + +/*************************************** + Group spi_extmem_common + ***************************************/ + +/* Functions */ +esp_rom_spi_cmd_config = 0x4fc00108; +esp_rom_spi_cmd_start = 0x4fc0010c; +esp_rom_spi_set_op_mode = 0x4fc00110; +esp_rom_spi_set_dtr_swap_mode = 0x4fc00114; + + +/*************************************** + Group spiflash_legacy + ***************************************/ + +/* Functions */ +esp_rom_spiflash_wait_idle = 0x4fc00118; +esp_rom_spiflash_write_encrypted = 0x4fc0011c; +esp_rom_spiflash_write_encrypted_dest = 0x4fc00120; +esp_rom_spiflash_write_encrypted_enable = 0x4fc00124; +esp_rom_spiflash_write_encrypted_disable = 0x4fc00128; +esp_rom_spiflash_erase_chip = 0x4fc0012c; +_esp_rom_spiflash_erase_sector = 0x4fc00130; +_esp_rom_spiflash_erase_block = 0x4fc00134; +_esp_rom_spiflash_write = 0x4fc00138; +_esp_rom_spiflash_read = 0x4fc0013c; +_esp_rom_spiflash_unlock = 0x4fc00140; +_SPIEraseArea = 0x4fc00144; +_SPI_write_enable = 0x4fc00148; +esp_rom_spiflash_erase_sector = 0x4fc0014c; +esp_rom_spiflash_erase_block = 0x4fc00150; +esp_rom_spiflash_write = 0x4fc00154; +esp_rom_spiflash_read = 0x4fc00158; +esp_rom_spiflash_unlock = 0x4fc0015c; +SPIEraseArea = 0x4fc00160; +SPI_write_enable = 0x4fc00164; +esp_rom_spiflash_config_param = 0x4fc00168; +esp_rom_spiflash_read_user_cmd = 0x4fc0016c; +esp_rom_spiflash_select_qio_pins = 0x4fc00170; +esp_rom_spi_flash_auto_sus_res = 0x4fc00174; +esp_rom_spi_flash_send_resume = 0x4fc00178; +esp_rom_spi_flash_update_id = 0x4fc0017c; +esp_rom_spiflash_config_clk = 0x4fc00180; +esp_rom_spiflash_config_readmode = 0x4fc00184; +esp_rom_spiflash_read_status = 0x4fc00188; +esp_rom_spiflash_read_statushigh = 0x4fc0018c; +esp_rom_spiflash_write_status = 0x4fc00190; +esp_rom_spiflash_write_disable = 0x4fc00194; +spi_cache_mode_switch = 0x4fc00198; +spi_common_set_dummy_output = 0x4fc0019c; +spi_common_set_flash_cs_timing = 0x4fc001a0; +esp_rom_spi_set_address_bit_len = 0x4fc001a4; +SPILock = 0x4fc001a8; +SPIMasterReadModeCnfig = 0x4fc001ac; +SPI_Common_Command = 0x4fc001b0; +SPI_WakeUp = 0x4fc001b4; +SPI_block_erase = 0x4fc001b8; +SPI_chip_erase = 0x4fc001bc; +SPI_init = 0x4fc001c0; +SPI_page_program = 0x4fc001c4; +SPI_read_data = 0x4fc001c8; +SPI_sector_erase = 0x4fc001cc; +SelectSpiFunction = 0x4fc001d0; +SetSpiDrvs = 0x4fc001d4; +Wait_SPI_Idle = 0x4fc001d8; +spi_dummy_len_fix = 0x4fc001dc; +Disable_QMode = 0x4fc001e0; +Enable_QMode = 0x4fc001e4; +spi_flash_attach = 0x4fc001e8; +spi_flash_get_chip_size = 0x4fc001ec; +spi_flash_guard_set = 0x4fc001f0; +spi_flash_guard_get = 0x4fc001f4; +spi_flash_read_encrypted = 0x4fc001f8; +/* Data (.data, .bss, .rodata) */ +rom_spiflash_legacy_funcs = 0x4ffbffec; +rom_spiflash_legacy_data = 0x4ffbffe8; +g_flash_guard_ops = 0x4ffbfff0; + + +/*************************************** + Group hal_systimer + ***************************************/ + +/* Functions */ +systimer_hal_init = 0x4fc00228; +systimer_hal_deinit = 0x4fc0022c; +systimer_hal_set_tick_rate_ops = 0x4fc00230; +systimer_hal_get_counter_value = 0x4fc00234; +systimer_hal_get_time = 0x4fc00238; +systimer_hal_set_alarm_target = 0x4fc0023c; +systimer_hal_set_alarm_period = 0x4fc00240; +systimer_hal_get_alarm_value = 0x4fc00244; +systimer_hal_enable_alarm_int = 0x4fc00248; +systimer_hal_on_apb_freq_update = 0x4fc0024c; +systimer_hal_counter_value_advance = 0x4fc00250; +systimer_hal_enable_counter = 0x4fc00254; +systimer_hal_select_alarm_mode = 0x4fc00258; +systimer_hal_connect_alarm_counter = 0x4fc0025c; +systimer_hal_counter_can_stall_by_cpu = 0x4fc00260; + + +/*************************************** + Group cache + ***************************************/ + +/* Functions */ +Cache_Get_L1_ICache_Line_Size = 0x4fc003c4; +Cache_Get_L1_DCache_Line_Size = 0x4fc003c8; +Cache_Get_L2_Cache_Line_Size = 0x4fc003cc; +Cache_Get_Mode = 0x4fc003d0; +Cache_Set_L2_Cache_Mode = 0x4fc003d4; +Cache_Address_Through_Cache = 0x4fc003d8; +ROM_Boot_Cache_Init = 0x4fc003dc; +Cache_Sync_Addr = 0x4fc003e0; +Cache_Invalidate_Addr = 0x4fc003e4; +Cache_Invalidate_Addr_Gid = 0x4fc003e8; +Cache_Clean_Addr = 0x4fc003ec; +Cache_Clean_Addr_Gid = 0x4fc003f0; +Cache_WriteBack_Addr = 0x4fc003f4; +Cache_WriteBack_Addr_Gid = 0x4fc003f8; +Cache_WriteBack_Invalidate_Addr = 0x4fc003fc; +Cache_WriteBack_Invalidate_Addr_Gid = 0x4fc00400; +Cache_Invalidate_All = 0x4fc00404; +Cache_Invalidate_All_Gid = 0x4fc00408; +Cache_Clean_All = 0x4fc0040c; +Cache_Clean_All_Gid = 0x4fc00410; +Cache_WriteBack_All = 0x4fc00414; +Cache_WriteBack_All_Gid = 0x4fc00418; +Cache_WriteBack_Invalidate_All = 0x4fc0041c; +Cache_WriteBack_Invalidate_All_Gid = 0x4fc00420; +Cache_Mask_All = 0x4fc00424; +Cache_Suspend_L1_CORE0_ICache_Autoload = 0x4fc00428; +Cache_Resume_L1_CORE0_ICache_Autoload = 0x4fc0042c; +Cache_Suspend_L1_CORE1_ICache_Autoload = 0x4fc00430; +Cache_Resume_L1_CORE1_ICache_Autoload = 0x4fc00434; +Cache_Suspend_L1_DCache_Autoload = 0x4fc00438; +Cache_Resume_L1_DCache_Autoload = 0x4fc0043c; +Cache_Suspend_L2_Cache_Autoload = 0x4fc00440; +Cache_Resume_L2_Cache_Autoload = 0x4fc00444; +Cache_Start_L1_CORE0_ICache_Preload = 0x4fc00448; +Cache_L1_CORE0_ICache_Preload_Done = 0x4fc0044c; +Cache_End_L1_CORE0_ICache_Preload = 0x4fc00450; +Cache_Start_L1_CORE1_ICache_Preload = 0x4fc00454; +Cache_L1_CORE1_ICache_Preload_Done = 0x4fc00458; +Cache_End_L1_CORE1_ICache_Preload = 0x4fc0045c; +Cache_Start_L1_DCache_Preload = 0x4fc00460; +Cache_L1_DCache_Preload_Done = 0x4fc00464; +Cache_End_L1_DCache_Preload = 0x4fc00468; +Cache_Start_L2_Cache_Preload = 0x4fc0046c; +Cache_L2_Cache_Preload_Done = 0x4fc00470; +Cache_End_L2_Cache_Preload = 0x4fc00474; +Cache_Config_L1_CORE0_ICache_Autoload = 0x4fc00478; +Cache_Enable_L1_CORE0_ICache_Autoload = 0x4fc0047c; +Cache_Disable_L1_CORE0_ICache_Autoload = 0x4fc00480; +Cache_Config_L1_CORE1_ICache_Autoload = 0x4fc00484; +Cache_Enable_L1_CORE1_ICache_Autoload = 0x4fc00488; +Cache_Disable_L1_CORE1_ICache_Autoload = 0x4fc0048c; +Cache_Config_L1_DCache_Autoload = 0x4fc00490; +Cache_Enable_L1_DCache_Autoload = 0x4fc00494; +Cache_Disable_L1_DCache_Autoload = 0x4fc00498; +Cache_Config_L2_Cache_Autoload = 0x4fc0049c; +Cache_Enable_L2_Cache_Autoload = 0x4fc004a0; +Cache_Disable_L2_Cache_Autoload = 0x4fc004a4; +Cache_Enable_L1_CORE0_ICache_PreLock = 0x4fc004a8; +Cache_Disable_L1_CORE0_ICache_PreLock = 0x4fc004ac; +Cache_Enable_L1_CORE1_ICache_PreLock = 0x4fc004b0; +Cache_Disable_L1_CORE1_ICache_PreLock = 0x4fc004b4; +Cache_Enable_L1_DCache_PreLock = 0x4fc004b8; +Cache_Disable_L1_DCache_PreLock = 0x4fc004bc; +Cache_Enable_L2_Cache_PreLock = 0x4fc004c0; +Cache_Disable_L2_Cache_PreLock = 0x4fc004c4; +Cache_Lock_Addr = 0x4fc004c8; +Cache_Unlock_Addr = 0x4fc004cc; +Cache_Disable_L1_CORE0_ICache = 0x4fc004d0; +Cache_Enable_L1_CORE0_ICache = 0x4fc004d4; +Cache_Suspend_L1_CORE0_ICache = 0x4fc004d8; +Cache_Resume_L1_CORE0_ICache = 0x4fc004dc; +Cache_Disable_L1_CORE1_ICache = 0x4fc004e0; +Cache_Enable_L1_CORE1_ICache = 0x4fc004e4; +Cache_Suspend_L1_CORE1_ICache = 0x4fc004e8; +Cache_Resume_L1_CORE1_ICache = 0x4fc004ec; +Cache_Disable_L1_DCache = 0x4fc004f0; +Cache_Enable_L1_DCache = 0x4fc004f4; +Cache_Suspend_L1_DCache = 0x4fc004f8; +Cache_Resume_L1_DCache = 0x4fc004fc; +Cache_Disable_L2_Cache = 0x4fc00500; +Cache_Enable_L2_Cache = 0x4fc00504; +Cache_Suspend_L2_Cache = 0x4fc00508; +Cache_Resume_L2_Cache = 0x4fc0050c; +Cache_FLASH_MMU_Init = 0x4fc00510; +Cache_PSRAM_MMU_Init = 0x4fc00514; +Cache_FLASH_MMU_Set = 0x4fc00518; +Cache_FLASH_MMU_Set_Secure = 0x4fc0051c; +Cache_PSRAM_MMU_Set = 0x4fc00520; +Cache_PSRAM_MMU_Set_Secure = 0x4fc00524; +Cache_Count_Flash_Pages = 0x4fc00528; +Cache_Flash_To_SPIRAM_Copy = 0x4fc0052c; +Cache_Set_IDROM_MMU_Size = 0x4fc00530; +flash2spiram_instruction_offset = 0x4fc00534; +flash2spiram_rodata_offset = 0x4fc00538; +flash_instr_rodata_start_page = 0x4fc0053c; +flash_instr_rodata_end_page = 0x4fc00540; +Cache_Set_IDROM_MMU_Info = 0x4fc00544; +Cache_Get_IROM_MMU_End = 0x4fc00548; +Cache_Get_DROM_MMU_End = 0x4fc0054c; +/* Data (.data, .bss, .rodata) */ +rom_cache_op_cb = 0x4ffbffdc; +rom_cache_internal_table_ptr = 0x4ffbffd8; + + +/*************************************** + Group clock + ***************************************/ + +/* Functions */ +ets_clk_get_xtal_freq = 0x4fc00550; +ets_clk_get_cpu_freq = 0x4fc00554; + + +/*************************************** + Group gpio + ***************************************/ + +/* Functions */ +gpio_set_output_level = 0x4fc00558; +gpio_get_input_level = 0x4fc0055c; +gpio_matrix_in = 0x4fc00560; +gpio_matrix_out = 0x4fc00564; +gpio_bypass_matrix_in = 0x4fc00568; +/* gpio_output_disable = 0x4fc0056c; */ +/* gpio_output_enable = 0x4fc00570; */ +gpio_pad_input_disable = 0x4fc00574; +gpio_pad_input_enable = 0x4fc00578; +gpio_pad_pulldown = 0x4fc0057c; +gpio_pad_pullup = 0x4fc00580; +gpio_pad_select_gpio = 0x4fc00584; +gpio_pad_set_drv = 0x4fc00588; +gpio_pad_unhold = 0x4fc0058c; +gpio_pad_hold = 0x4fc00590; +gpio_lppad_select_mux = 0x4fc00594; +gpio_ded_pad_set_drv = 0x4fc00598; +gpio_ded_pad_pullup = 0x4fc0059c; +gpio_ded_pad_pulldown = 0x4fc005a0; +gpio_ded_pad_hold = 0x4fc005a4; +gpio_ded_pad_unhold = 0x4fc005a8; + + +/*************************************** + Group interrupts + ***************************************/ + +/* Functions */ +esprv_intc_int_set_priority = 0x4fc005ac; +esprv_intc_int_set_threshold = 0x4fc005b0; +esprv_intc_int_enable = 0x4fc005b4; +esprv_intc_int_disable = 0x4fc005b8; +esprv_intc_int_set_type = 0x4fc005bc; +PROVIDE( intr_handler_set = 0x4fc005c0 ); +intr_matrix_set = 0x4fc005c4; +ets_intr_lock = 0x4fc005c8; +ets_intr_unlock = 0x4fc005cc; +ets_isr_attach = 0x4fc005d0; +ets_isr_mask = 0x4fc005d4; +ets_isr_unmask = 0x4fc005d8; + + +/*************************************** + Group crypto + ***************************************/ + +/* Functions */ +md5_vector = 0x4fc005dc; +MD5Init = 0x4fc005e0; +MD5Update = 0x4fc005e4; +MD5Final = 0x4fc005e8; +crc32_le = 0x4fc005ec; +crc16_le = 0x4fc005f0; +crc8_le = 0x4fc005f4; +crc32_be = 0x4fc005f8; +crc16_be = 0x4fc005fc; +crc8_be = 0x4fc00600; +esp_crc8 = 0x4fc00604; +ets_sha_enable = 0x4fc00608; +ets_sha_disable = 0x4fc0060c; +ets_sha_get_state = 0x4fc00610; +ets_sha_init = 0x4fc00614; +ets_sha_process = 0x4fc00618; +ets_sha_starts = 0x4fc0061c; +ets_sha_update = 0x4fc00620; +ets_sha_finish = 0x4fc00624; +ets_sha_clone = 0x4fc00628; +ets_hmac_enable = 0x4fc0062c; +ets_hmac_disable = 0x4fc00630; +ets_hmac_calculate_message = 0x4fc00634; +ets_hmac_calculate_downstream = 0x4fc00638; +ets_hmac_invalidate_downstream = 0x4fc0063c; +ets_jtag_enable_temporarily = 0x4fc00640; +ets_aes_enable = 0x4fc00644; +ets_aes_disable = 0x4fc00648; +ets_aes_setkey = 0x4fc0064c; +ets_aes_block = 0x4fc00650; +ets_aes_setkey_dec = 0x4fc00654; +ets_aes_setkey_enc = 0x4fc00658; +ets_bigint_enable = 0x4fc0065c; +ets_bigint_disable = 0x4fc00660; +ets_bigint_multiply = 0x4fc00664; +ets_bigint_modmult = 0x4fc00668; +ets_bigint_modexp = 0x4fc0066c; +ets_bigint_wait_finish = 0x4fc00670; +ets_bigint_getz = 0x4fc00674; +ets_ds_enable = 0x4fc00678; +ets_ds_disable = 0x4fc0067c; +ets_ds_start_sign = 0x4fc00680; +ets_ds_is_busy = 0x4fc00684; +ets_ds_finish_sign = 0x4fc00688; +ets_ds_encrypt_params = 0x4fc0068c; +ets_mgf1_sha256 = 0x4fc00690; +/* Data (.data, .bss, .rodata) */ +crc32_le_table_ptr = 0x4fc1fff8; +crc16_le_table_ptr = 0x4fc1fff4; +crc8_le_table_ptr = 0x4fc1fff0; +crc32_be_table_ptr = 0x4fc1ffec; +crc16_be_table_ptr = 0x4fc1ffe8; +crc8_be_table_ptr = 0x4fc1ffe4; + + +/*************************************** + Group efuse + ***************************************/ + +/* Functions */ +ets_efuse_read = 0x4fc00694; +ets_efuse_program = 0x4fc00698; +ets_efuse_clear_program_registers = 0x4fc0069c; +ets_efuse_write_key = 0x4fc006a0; +ets_efuse_get_read_register_address = 0x4fc006a4; +ets_efuse_get_key_purpose = 0x4fc006a8; +ets_efuse_key_block_unused = 0x4fc006ac; +ets_efuse_find_unused_key_block = 0x4fc006b0; +ets_efuse_rs_calculate = 0x4fc006b4; +ets_efuse_count_unused_key_blocks = 0x4fc006b8; +ets_efuse_secure_boot_enabled = 0x4fc006bc; +ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4fc006c0; +ets_efuse_cache_encryption_enabled = 0x4fc006c4; +ets_efuse_download_modes_disabled = 0x4fc006c8; +ets_efuse_find_purpose = 0x4fc006cc; +ets_efuse_force_send_resume = 0x4fc006d0; +ets_efuse_get_flash_delay_us = 0x4fc006d4; +ets_efuse_get_uart_print_control = 0x4fc006d8; +ets_efuse_direct_boot_mode_disabled = 0x4fc006dc; +ets_efuse_security_download_modes_enabled = 0x4fc006e0; +ets_efuse_jtag_disabled = 0x4fc006e4; +ets_efuse_usb_print_is_disabled = 0x4fc006e8; +ets_efuse_usb_download_mode_disabled = 0x4fc006ec; +ets_efuse_usb_device_disabled = 0x4fc006f0; +ets_efuse_get_km_huk_gen_state = 0x4fc006f4; +ets_efuse_get_km_deploy_only_once = 0x4fc006f8; +ets_efuse_get_force_use_km_key = 0x4fc006fc; +ets_efuse_xts_key_length_256 = 0x4fc00700; +ets_efuse_get_km_key_lock = 0x4fc00704; + + +/*************************************** + Group key_mgr + ***************************************/ + +/* Functions */ +esp_rom_check_recover_key = 0x4fc00708; +esp_rom_km_huk_conf = 0x4fc0070c; +esp_rom_km_huk_risk = 0x4fc00710; + + +/*************************************** + Group secureboot + ***************************************/ + +/* Functions */ +ets_emsa_pss_verify = 0x4fc00714; +ets_rsa_pss_verify = 0x4fc00718; +ets_ecdsa_verify = 0x4fc0071c; +ets_secure_boot_verify_bootloader_with_keys = 0x4fc00720; +ets_secure_boot_verify_signature = 0x4fc00724; +ets_secure_boot_read_key_digests = 0x4fc00728; +ets_secure_boot_revoke_public_key_digest = 0x4fc0072c; + + +/*************************************** + Group usb_device_uart + ***************************************/ + +/* Functions */ +usb_serial_device_rx_one_char = 0x4fc008a4; +usb_serial_device_rx_one_char_block = 0x4fc008a8; +usb_serial_device_tx_flush = 0x4fc008ac; +usb_serial_device_tx_one_char = 0x4fc008b0; + + +/*************************************** + Group usb_dwcotg_uart + ***************************************/ + +/* Functions */ +Uart_Init_USB = 0x4fc008b4; +usb_serial_otg_rx_one_char = 0x4fc008b8; +usb_serial_otg_rx_one_char_block = 0x4fc008bc; +usb_serial_otg_tx_flush = 0x4fc008c0; +usb_serial_otg_tx_one_char = 0x4fc008c4; +/* Data (.data, .bss, .rodata) */ +uart_acm_dev = 0x4ffbffd4; + + +/*************************************** + Group usb_dwcotg_module + ***************************************/ + +/* Functions */ +cdc_acm_class_handle_req = 0x4fc008c8; +cdc_acm_init = 0x4fc008cc; +cdc_acm_fifo_fill = 0x4fc008d0; +cdc_acm_rx_fifo_cnt = 0x4fc008d4; +cdc_acm_fifo_read = 0x4fc008d8; +cdc_acm_irq_tx_enable = 0x4fc008dc; +cdc_acm_irq_tx_disable = 0x4fc008e0; +cdc_acm_irq_state_enable = 0x4fc008e4; +cdc_acm_irq_state_disable = 0x4fc008e8; +cdc_acm_irq_tx_ready = 0x4fc008ec; +cdc_acm_irq_rx_enable = 0x4fc008f0; +cdc_acm_irq_rx_disable = 0x4fc008f4; +cdc_acm_irq_rx_ready = 0x4fc008f8; +cdc_acm_irq_is_pending = 0x4fc008fc; +cdc_acm_irq_callback_set = 0x4fc00900; +cdc_acm_line_ctrl_set = 0x4fc00904; +cdc_acm_line_ctrl_get = 0x4fc00908; +cdc_acm_poll_out = 0x4fc0090c; +chip_usb_dw_did_persist = 0x4fc00910; +chip_usb_dw_init = 0x4fc00914; +chip_usb_detach = 0x4fc00918; +chip_usb_dw_prepare_persist = 0x4fc0091c; +chip_usb_get_persist_flags = 0x4fc00920; +chip_usb_set_persist_flags = 0x4fc00924; +cpio_start = 0x4fc00928; +cpio_feed = 0x4fc0092c; +cpio_done = 0x4fc00930; +cpio_destroy = 0x4fc00934; +dfu_flash_init = 0x4fc00938; +dfu_flash_erase = 0x4fc0093c; +dfu_flash_program = 0x4fc00940; +dfu_flash_read = 0x4fc00944; +dfu_flash_attach = 0x4fc00948; +dfu_cpio_callback = 0x4fc0094c; +dfu_updater_get_err = 0x4fc00950; +dfu_updater_clear_err = 0x4fc00954; +dfu_updater_enable = 0x4fc00958; +dfu_updater_begin = 0x4fc0095c; +dfu_updater_feed = 0x4fc00960; +dfu_updater_end = 0x4fc00964; +dfu_updater_set_raw_addr = 0x4fc00968; +dfu_updater_flash_read = 0x4fc0096c; +usb_dc_prepare_persist = 0x4fc00970; +usb_dw_isr_handler = 0x4fc00974; +usb_dc_attach = 0x4fc00978; +usb_dc_detach = 0x4fc0097c; +usb_dc_reset = 0x4fc00980; +usb_dc_set_address = 0x4fc00984; +usb_dc_ep_check_cap = 0x4fc00988; +usb_dc_ep_configure = 0x4fc0098c; +usb_dc_ep_set_stall = 0x4fc00990; +usb_dc_ep_clear_stall = 0x4fc00994; +usb_dc_ep_halt = 0x4fc00998; +usb_dc_ep_is_stalled = 0x4fc0099c; +usb_dc_ep_enable = 0x4fc009a0; +usb_dc_ep_disable = 0x4fc009a4; +usb_dc_ep_flush = 0x4fc009a8; +usb_dc_ep_write_would_block = 0x4fc009ac; +usb_dc_ep_write = 0x4fc009b0; +usb_dc_ep_read_wait = 0x4fc009b4; +usb_dc_ep_read_continue = 0x4fc009b8; +usb_dc_ep_read = 0x4fc009bc; +usb_dc_ep_set_callback = 0x4fc009c0; +usb_dc_set_status_callback = 0x4fc009c4; +usb_dc_ep_mps = 0x4fc009c8; +usb_dc_check_poll_for_interrupts = 0x4fc009cc; +mac_addr_to_serial_str_desc = 0x4fc009d0; +usb_set_current_descriptor = 0x4fc009d4; +usb_get_descriptor = 0x4fc009d8; +usb_dev_resume = 0x4fc009dc; +usb_dev_get_configuration = 0x4fc009e0; +usb_set_config = 0x4fc009e4; +usb_deconfig = 0x4fc009e8; +usb_enable = 0x4fc009ec; +usb_disable = 0x4fc009f0; +usb_write_would_block = 0x4fc009f4; +usb_write = 0x4fc009f8; +usb_read = 0x4fc009fc; +usb_ep_set_stall = 0x4fc00a00; +usb_ep_clear_stall = 0x4fc00a04; +usb_ep_read_wait = 0x4fc00a08; +usb_ep_read_continue = 0x4fc00a0c; +usb_transfer_ep_callback = 0x4fc00a10; +usb_transfer = 0x4fc00a14; +usb_cancel_transfer = 0x4fc00a18; +usb_transfer_sync = 0x4fc00a1c; +usb_dfu_set_detach_cb = 0x4fc00a20; +dfu_class_handle_req = 0x4fc00a24; +dfu_status_cb = 0x4fc00a28; +dfu_custom_handle_req = 0x4fc00a2c; +usb_dfu_init = 0x4fc00a30; +usb_dfu_force_detach = 0x4fc00a34; +usb_dev_deinit = 0x4fc00a38; +usb_dw_ctrl_deinit = 0x4fc00a3c; +/* Data (.data, .bss, .rodata) */ +s_usb_osglue = 0x4ffbffc8; + + +/*************************************** + Group recovery_bootloader + ***************************************/ + +/* Functions */ +ets_get_bootloader_offset = 0x4fc00a40; +ets_set_bootloader_offset = 0x4fc00a44; diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.libc.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.libc.ld new file mode 100644 index 000000000000..62230dc8ebbe --- /dev/null +++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.libc.ld @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +esp_rom_newlib_init_common_mutexes = 0x4fc00264; +memset = 0x4fc00268; +strlen = 0x4fc00288; +strstr = 0x4fc0028c; +bzero = 0x4fc00290; +sbrk = 0x4fc00298; +isalnum = 0x4fc0029c; +isalpha = 0x4fc002a0; +isascii = 0x4fc002a4; +isblank = 0x4fc002a8; +iscntrl = 0x4fc002ac; +isdigit = 0x4fc002b0; +islower = 0x4fc002b4; +isgraph = 0x4fc002b8; +isprint = 0x4fc002bc; +ispunct = 0x4fc002c0; +isspace = 0x4fc002c4; +isupper = 0x4fc002c8; +toupper = 0x4fc002cc; +tolower = 0x4fc002d0; +toascii = 0x4fc002d4; +memccpy = 0x4fc002d8; +memchr = 0x4fc002dc; +memrchr = 0x4fc002e0; +strcasecmp = 0x4fc002e4; +strcasestr = 0x4fc002e8; +strcat = 0x4fc002ec; +strchr = 0x4fc002f4; +strcspn = 0x4fc002f8; +strcoll = 0x4fc002fc; +strlcat = 0x4fc00300; +strlcpy = 0x4fc00304; +strlwr = 0x4fc00308; +strncasecmp = 0x4fc0030c; +strncat = 0x4fc00310; +strnlen = 0x4fc00318; +strrchr = 0x4fc0031c; +strsep = 0x4fc00320; +strspn = 0x4fc00324; +strtok_r = 0x4fc00328; +strupr = 0x4fc0032c; +longjmp = 0x4fc00330; +setjmp = 0x4fc00334; +abs = 0x4fc00338; +div = 0x4fc0033c; +labs = 0x4fc00340; +ldiv = 0x4fc00344; +qsort = 0x4fc00348; +utoa = 0x4fc00358; +itoa = 0x4fc0035c; +/* Data (.data, .bss, .rodata) */ +syscall_table_ptr = 0x4ffbffe4; +_global_impure_ptr = 0x4ffbffe0; diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.libgcc.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.libgcc.ld new file mode 100644 index 000000000000..7dcac301e9eb --- /dev/null +++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.libgcc.ld @@ -0,0 +1,95 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32p4.rom.libgcc.ld for esp32p4 + * + * + * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum 56d78222be1daa0502090a078288f4d5 + * + * Compatible with ROM where ECO version equal or greater to 5. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group libgccdf + ***************************************/ + +/* Functions */ +__absvdi2 = 0x4fc00730; +__absvsi2 = 0x4fc00734; +__adddf3 = 0x4fc00738; +__addvdi3 = 0x4fc0073c; +__addvsi3 = 0x4fc00740; +__ashldi3 = 0x4fc00744; +__ashrdi3 = 0x4fc00748; +__bswapdi2 = 0x4fc0074c; +__bswapsi2 = 0x4fc00750; +__clear_cache = 0x4fc00754; +__clrsbdi2 = 0x4fc00758; +__clrsbsi2 = 0x4fc0075c; +__clzdi2 = 0x4fc00760; +__clzsi2 = 0x4fc00764; +__cmpdi2 = 0x4fc00768; +__ctzdi2 = 0x4fc0076c; +__ctzsi2 = 0x4fc00770; +__divdc3 = 0x4fc00774; +__divdf3 = 0x4fc00778; +__divdi3 = 0x4fc0077c; +__divsc3 = 0x4fc00780; +__divsi3 = 0x4fc00784; +__eqdf2 = 0x4fc00788; +__extendsfdf2 = 0x4fc0078c; +__ffsdi2 = 0x4fc00790; +__ffssi2 = 0x4fc00794; +__fixdfdi = 0x4fc00798; +__fixdfsi = 0x4fc0079c; +__fixsfdi = 0x4fc007a0; +__fixunsdfsi = 0x4fc007a4; +__fixunssfdi = 0x4fc007a8; +__fixunssfsi = 0x4fc007ac; +__floatdidf = 0x4fc007b0; +__floatdisf = 0x4fc007b4; +__floatsidf = 0x4fc007b8; +__floatundidf = 0x4fc007bc; +__floatundisf = 0x4fc007c0; +__floatunsidf = 0x4fc007c4; +__gcc_bcmp = 0x4fc007c8; +__gedf2 = 0x4fc007cc; +__gtdf2 = 0x4fc007d0; +__ledf2 = 0x4fc007d4; +__lshrdi3 = 0x4fc007d8; +__ltdf2 = 0x4fc007dc; +__moddi3 = 0x4fc007e0; +__modsi3 = 0x4fc007e4; +__muldc3 = 0x4fc007e8; +__muldf3 = 0x4fc007ec; +__muldi3 = 0x4fc007f0; +__mulsc3 = 0x4fc007f4; +__mulsi3 = 0x4fc007f8; +__mulvdi3 = 0x4fc007fc; +__mulvsi3 = 0x4fc00800; +__nedf2 = 0x4fc00804; +__negdf2 = 0x4fc00808; +__negdi2 = 0x4fc0080c; +__negvdi2 = 0x4fc00810; +__negvsi2 = 0x4fc00814; +__paritysi2 = 0x4fc00818; +__popcountdi2 = 0x4fc0081c; +__popcountsi2 = 0x4fc00820; +__powidf2 = 0x4fc00824; +__subdf3 = 0x4fc00828; +__subvdi3 = 0x4fc0082c; +__subvsi3 = 0x4fc00830; +__ucmpdi2 = 0x4fc00834; +__udivdi3 = 0x4fc00838; +__udivmoddi4 = 0x4fc0083c; +__udivsi3 = 0x4fc00840; +__udiv_w_sdiv = 0x4fc00844; +__umoddi3 = 0x4fc00848; +__umodsi3 = 0x4fc0084c; +__unorddf2 = 0x4fc00850; +__extenddftf2 = 0x4fc00854; +__trunctfdf2 = 0x4fc00858; diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.newlib.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.newlib.ld new file mode 100644 index 000000000000..0498c23bf16d --- /dev/null +++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.newlib.ld @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32p4.rom.newlib.ld for esp32p4 + * + * + * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum 56d78222be1daa0502090a078288f4d5 + * + * Compatible with ROM where ECO version equal or greater to 5. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group newlib + ***************************************/ + +/* Functions */ +esp_rom_newlib_init_common_mutexes = 0x4fc00264; +memset = 0x4fc00268; +memcpy = 0x4fc0026c; +memmove = 0x4fc00270; +memcmp = 0x4fc00274; +strcpy = 0x4fc00278; +strncpy = 0x4fc0027c; +strcmp = 0x4fc00280; +strncmp = 0x4fc00284; +strlen = 0x4fc00288; +strstr = 0x4fc0028c; +bzero = 0x4fc00290; +_isatty_r = 0x4fc00294; +sbrk = 0x4fc00298; +isalnum = 0x4fc0029c; +isalpha = 0x4fc002a0; +isascii = 0x4fc002a4; +isblank = 0x4fc002a8; +iscntrl = 0x4fc002ac; +isdigit = 0x4fc002b0; +islower = 0x4fc002b4; +isgraph = 0x4fc002b8; +isprint = 0x4fc002bc; +ispunct = 0x4fc002c0; +isspace = 0x4fc002c4; +isupper = 0x4fc002c8; +toupper = 0x4fc002cc; +tolower = 0x4fc002d0; +toascii = 0x4fc002d4; +memccpy = 0x4fc002d8; +memchr = 0x4fc002dc; +memrchr = 0x4fc002e0; +strcasecmp = 0x4fc002e4; +strcasestr = 0x4fc002e8; +strcat = 0x4fc002ec; +strdup = 0x4fc002f0; +strchr = 0x4fc002f4; +strcspn = 0x4fc002f8; +strcoll = 0x4fc002fc; +strlcat = 0x4fc00300; +strlcpy = 0x4fc00304; +strlwr = 0x4fc00308; +strncasecmp = 0x4fc0030c; +strncat = 0x4fc00310; +strndup = 0x4fc00314; +strnlen = 0x4fc00318; +strrchr = 0x4fc0031c; +strsep = 0x4fc00320; +strspn = 0x4fc00324; +strtok_r = 0x4fc00328; +strupr = 0x4fc0032c; +longjmp = 0x4fc00330; +setjmp = 0x4fc00334; +abs = 0x4fc00338; +div = 0x4fc0033c; +labs = 0x4fc00340; +ldiv = 0x4fc00344; +qsort = 0x4fc00348; +rand_r = 0x4fc0034c; +rand = 0x4fc00350; +srand = 0x4fc00354; +utoa = 0x4fc00358; +itoa = 0x4fc0035c; +atoi = 0x4fc00360; +atol = 0x4fc00364; +strtol = 0x4fc00368; +strtoul = 0x4fc0036c; +fflush = 0x4fc00370; +_fflush_r = 0x4fc00374; +_fwalk = 0x4fc00378; +_fwalk_reent = 0x4fc0037c; +__smakebuf_r = 0x4fc00380; +__swhatbuf_r = 0x4fc00384; +__swbuf_r = 0x4fc00388; +__swbuf = 0x4fc0038c; +__swsetup_r = 0x4fc00390; +/* Data (.data, .bss, .rodata) */ +syscall_table_ptr = 0x4ffbffe4; +_global_impure_ptr = 0x4ffbffe0; diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.rvfp.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.rvfp.ld new file mode 100644 index 000000000000..05749d8a4d55 --- /dev/null +++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.rvfp.ld @@ -0,0 +1,101 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32p4.rom.rvfp.ld for esp32p4 + * + * + * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum 56d78222be1daa0502090a078288f4d5 + * + * Compatible with ROM where ECO version equal or greater to 5. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group rvfplibdf + ***************************************/ + +/* Functions */ +__adddf3 = 0x4fc0085c; +__eqdf2 = 0x4fc00860; +__fixdfdi = 0x4fc00864; +__fixdfsi = 0x4fc00868; +__fixunsdfsi = 0x4fc00870; +__floatdidf = 0x4fc00878; +__floatsidf = 0x4fc0087c; +__floatundidf = 0x4fc00880; +__floatunsidf = 0x4fc00884; +__gedf2 = 0x4fc00888; +__gtdf2 = 0x4fc0088c; +__ledf2 = 0x4fc00890; +__ltdf2 = 0x4fc00894; +__muldf3 = 0x4fc00898; +__nedf2 = 0x4fc0089c; +__subdf3 = 0x4fc008a0; + +/*************************************** + Group libgcc +***************************************/ + +/* Functions */ +__absvdi2 = 0x4fc00730; +__absvsi2 = 0x4fc00734; +__addvdi3 = 0x4fc0073c; +__addvsi3 = 0x4fc00740; +__ashldi3 = 0x4fc00744; +__ashrdi3 = 0x4fc00748; +__bswapdi2 = 0x4fc0074c; +__bswapsi2 = 0x4fc00750; +__clear_cache = 0x4fc00754; +__clrsbdi2 = 0x4fc00758; +__clrsbsi2 = 0x4fc0075c; +__clzdi2 = 0x4fc00760; +__clzsi2 = 0x4fc00764; +__cmpdi2 = 0x4fc00768; +__ctzdi2 = 0x4fc0076c; +__ctzsi2 = 0x4fc00770; +__divdc3 = 0x4fc00774; +__divdf3 = 0x4fc00778; +__divdi3 = 0x4fc0077c; +__divsc3 = 0x4fc00780; +__divsi3 = 0x4fc00784; +__extendsfdf2 = 0x4fc0078c; +__ffsdi2 = 0x4fc00790; +__ffssi2 = 0x4fc00794; +__fixsfdi = 0x4fc007a0; +__fixunssfdi = 0x4fc007a8; +__fixunssfsi = 0x4fc007ac; +__floatdisf = 0x4fc007b4; +__floatundisf = 0x4fc007c0; +__gcc_bcmp = 0x4fc007c8; +__lshrdi3 = 0x4fc007d8; +__moddi3 = 0x4fc007e0; +__modsi3 = 0x4fc007e4; +__muldc3 = 0x4fc007e8; +__muldi3 = 0x4fc007f0; +__mulsc3 = 0x4fc007f4; +__mulsi3 = 0x4fc007f8; +__mulvdi3 = 0x4fc007fc; +__mulvsi3 = 0x4fc00800; +__negdf2 = 0x4fc00808; +__negdi2 = 0x4fc0080c; +__negvdi2 = 0x4fc00810; +__negvsi2 = 0x4fc00814; +__paritysi2 = 0x4fc00818; +__popcountdi2 = 0x4fc0081c; +__popcountsi2 = 0x4fc00820; +__powidf2 = 0x4fc00824; +__subvdi3 = 0x4fc0082c; +__subvsi3 = 0x4fc00830; +__ucmpdi2 = 0x4fc00834; +__udivdi3 = 0x4fc00838; +__udivmoddi4 = 0x4fc0083c; +__udivsi3 = 0x4fc00840; +__udiv_w_sdiv = 0x4fc00844; +__umoddi3 = 0x4fc00848; +__umodsi3 = 0x4fc0084c; +__unorddf2 = 0x4fc00850; +__extenddftf2 = 0x4fc00854; +__trunctfdf2 = 0x4fc00858; diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.ld index 1ddf2b794516..b9950412e064 100644 --- a/components/esp_rom/esp32p4/ld/esp32p4.rom.ld +++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.ld @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.libgcc.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.libgcc.ld index 3f3bcd3f2263..3b969ade5a94 100644 --- a/components/esp_rom/esp32p4/ld/esp32p4.rom.libgcc.ld +++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.libgcc.ld @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.newlib-nano.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.newlib-nano.ld index 0155ac4f4b60..c0a7c5b16886 100644 --- a/components/esp_rom/esp32p4/ld/esp32p4.rom.newlib-nano.ld +++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.newlib-nano.ld @@ -1,12 +1,12 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ /* ROM function interface esp32p4.rom.newlib-nano.ld for esp32p4 * * - * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum f6516bd9708d890f63db87f8aed53ca7 + * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum 56d78222be1daa0502090a078288f4d5 * * Compatible with ROM where ECO version equal or greater to 0. * diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.newlib.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.newlib.ld index c5db4832c20c..88dd2a62f18b 100644 --- a/components/esp_rom/esp32p4/ld/esp32p4.rom.newlib.ld +++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.newlib.ld @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.rvfp.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.rvfp.ld index 9b13c98b696e..bb28d141915a 100644 --- a/components/esp_rom/esp32p4/ld/esp32p4.rom.rvfp.ld +++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.rvfp.ld @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -47,7 +47,7 @@ __subdf3 = 0x4fc008ac; Group libgcc ***************************************/ -/* Not part of the orginal ROM interface, but RVFP versions cannot work with float-abi */ +/* Not part of the original ROM interface, but RVFP versions cannot work with float-abi */ __fixsfdi = 0x4fc007ac; __fixunssfdi = 0x4fc007b4; diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.version.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.version.ld index 9a5970bc41be..6a0c65c27028 100644 --- a/components/esp_rom/esp32p4/ld/esp32p4.rom.version.ld +++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.version.ld @@ -1,8 +1,9 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ + /* ROM version variables for esp32p4 * * These addresses should be compatible with any ROM version for this chip. diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.wdt.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.wdt.ld index d38dc05e73d2..6b872fa581ec 100644 --- a/components/esp_rom/esp32p4/ld/esp32p4.rom.wdt.ld +++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.wdt.ld @@ -1,12 +1,12 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ /* ROM function interface esp32p4.rom.wdt.ld for esp32p4 * * - * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum f6516bd9708d890f63db87f8aed53ca7 + * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum 56d78222be1daa0502090a078288f4d5 * * Compatible with ROM where ECO version equal or greater to 0. * diff --git a/components/esp_system/CMakeLists.txt b/components/esp_system/CMakeLists.txt index 6dc94c5c99c9..4ba3b1b39a1c 100644 --- a/components/esp_system/CMakeLists.txt +++ b/components/esp_system/CMakeLists.txt @@ -145,7 +145,8 @@ if(NOT BOOTLOADER_BUILD) endif() endif() -if(CONFIG_SOC_MEM_NON_CONTIGUOUS_SRAM) +# For P4, since P4 REV2, the SRAM is contiguous +if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3) target_link_options(${COMPONENT_LIB} INTERFACE "-Wl,--enable-non-contiguous-regions") endif() diff --git a/components/esp_system/fpga_overrides_clk.c b/components/esp_system/fpga_overrides_clk.c index 1b1f9efad2f1..a6688a18674c 100644 --- a/components/esp_system/fpga_overrides_clk.c +++ b/components/esp_system/fpga_overrides_clk.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -65,8 +65,13 @@ void bootloader_clock_configure(void) void esp_rtc_init(void) { #if SOC_PMU_SUPPORTED +#if CONFIG_ESP32P4_REV_MIN_300 + //TODO: IDF-13453 + ESP_EARLY_LOGW(TAG, "pmu_init not supported\n"); +#else pmu_init(); #endif +#endif } void esp_clk_init(void) diff --git a/components/esp_system/ld/esp32p4/memory.ld.in b/components/esp_system/ld/esp32p4/memory.ld.in index bad851213670..107b00d98b70 100644 --- a/components/esp_system/ld/esp32p4/memory.ld.in +++ b/components/esp_system/ld/esp32p4/memory.ld.in @@ -15,6 +15,11 @@ #include "sdkconfig.h" #include "ld.common" +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 +#define SRAM_START 0x4FF00000 + CONFIG_CACHE_L2_CACHE_SIZE +#define SRAM_END 0x4FFAEFC0 /* 2nd stage bootloader iram_loader_seg start address */ +#define SRAM_SIZE SRAM_END - SRAM_START +#else #define SRAM_LOW_START 0x4FF00000 #define SRAM_LOW_END 0x4FF2CBD0 /* 2nd stage bootloader iram_loader_seg start address */ #define SRAM_LOW_SIZE SRAM_LOW_END - SRAM_LOW_START @@ -25,6 +30,13 @@ #define SRAM_HIGH_START 0x4FF40000 #define SRAM_HIGH_SIZE 0x80000 - CONFIG_CACHE_L2_CACHE_SIZE #define SRAM_HIGH_END SRAM_HIGH_START + SRAM_HIGH_SIZE +#endif + +#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND +#define MSPI_WORKAROUND_SIZE CONFIG_P4_REV3_MSPI_WORKAROUND_SIZE +#else +#define MSPI_WORKAROUND_SIZE 0x0 +#endif #define IDROM_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 10) @@ -65,9 +77,12 @@ MEMORY * Shared data RAM, excluding memory reserved for ROM bss/data/stack. * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available. */ +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 sram_low (RWX) : org = SRAM_LOW_START, len = SRAM_LOW_SIZE - sram_high (RW) : org = SRAM_HIGH_START, len = SRAM_HIGH_SIZE +#else + sram_seg (RWX) : org = SRAM_START, len = SRAM_SIZE +#endif #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS #if CONFIG_SPIRAM_RODATA @@ -81,14 +96,17 @@ MEMORY /* (See irom_seg for meaning of 0x20 offset in the above.) */ #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS + /* Used to store the deep sleep workaround code of P4 rev3.0. The reset vector will be set here before the chip enters sleep. */ + rev3_mspi_workaround_seg(RWX) : org = 0x50108000, len = MSPI_WORKAROUND_SIZE + /** * lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667 */ #if CONFIG_ULP_COPROC_ENABLED - lp_ram_seg(RW) : org = 0x50108000 + RESERVE_RTC_MEM + CONFIG_ULP_COPROC_RESERVE_MEM, + lp_ram_seg(RW) : org = 0x50108000 + MSPI_WORKAROUND_SIZE + RESERVE_RTC_MEM + CONFIG_ULP_COPROC_RESERVE_MEM, len = 0x8000 - CONFIG_ULP_COPROC_RESERVE_MEM - RESERVE_RTC_MEM - LP_ROM_DRAM_SIZE #else - lp_ram_seg(RW) : org = 0x50108000 + RESERVE_RTC_MEM, len = 0x8000 - RESERVE_RTC_MEM + lp_ram_seg(RW) : org = 0x50108000 + MSPI_WORKAROUND_SIZE + RESERVE_RTC_MEM, len = 0x8000 - RESERVE_RTC_MEM - MSPI_WORKAROUND_SIZE #endif // CONFIG_ULP_COPROC_ENABLED /* We reduced the size of lp_ram_seg by RESERVE_RTC_MEM value. @@ -99,7 +117,7 @@ MEMORY The aim of this is to keep data that will not be moved around and have a fixed address. This segment is placed at the beginning of LP RAM, as the end of LP RAM is occupied by LP ROM stack/data */ - lp_reserved_seg(RW) : org = 0x50108000, len = RESERVE_RTC_MEM + lp_reserved_seg(RW) : org = 0x50108000 + MSPI_WORKAROUND_SIZE, len = RESERVE_RTC_MEM /* PSRAM seg */ extern_ram_seg(RWX) : org = 0x48000000, len = IDROM_SEG_SIZE diff --git a/components/esp_system/ld/esp32p4/sections.rev3.ld.in b/components/esp_system/ld/esp32p4/sections.rev3.ld.in new file mode 100644 index 000000000000..8c3a6cfdae42 --- /dev/null +++ b/components/esp_system/ld/esp32p4/sections.rev3.ld.in @@ -0,0 +1,556 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include "ld.common" + +/* Default entry point */ +ENTRY(call_start_cpu0); + +SECTIONS +{ + /** + * RTC fast memory holds RTC wake stub code, + * including from any source file named rtc_wake_stub*.c + */ + .rtc.text : + { + /* Align the start of RTC code region as per PMP granularity + * this ensures we do not overwrite the permissions for the previous + * region (ULP mem/RTC reserved) regardless of their end alignment + */ + ALIGNED_SYMBOL(_esp_pmp_align_size, _rtc_fast_start) + ALIGNED_SYMBOL(_esp_pmp_align_size, _rtc_text_start) + + arrays[rtc_text] + mapping[rtc_text] + + *rtc_wake_stub*.*(.text .text.*) + *(.rtc_text_end_test) + + /* Align the end of RTC code region as per PMP granularity */ + . = ALIGN(_esp_pmp_align_size); + + ALIGNED_SYMBOL(4, _rtc_text_end) + } > lp_ram_seg + + /** + * This section located in RTC FAST Memory area. + * It holds data marked with RTC_FAST_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_fast : + { + ALIGNED_SYMBOL(4, _rtc_force_fast_start) + + arrays[rtc_force_fast] + mapping[rtc_force_fast] + + *(.rtc.force_fast .rtc.force_fast.*) + + ALIGNED_SYMBOL(4, _rtc_force_fast_end) + } > lp_ram_seg + + /** + * RTC data section holds RTC wake stub + * data/rodata, including from any source file + * named rtc_wake_stub*.c and the data marked with + * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. + */ + .rtc.data : + { + _rtc_data_start = ABSOLUTE(.); + + arrays[rtc_data] + mapping[rtc_data] + + *rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .srodata.*) + + _rtc_data_end = ABSOLUTE(.); + } > lp_ram_seg + + /* RTC bss, from any source file named rtc_wake_stub*.c */ + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + + *rtc_wake_stub*.*(.bss .bss.* .sbss .sbss.*) + *rtc_wake_stub*.*(COMMON) + + arrays[rtc_bss] + mapping[rtc_bss] + + _rtc_bss_end = ABSOLUTE(.); + } > lp_ram_seg + + /** + * This section holds data that should not be initialized at power up + * and will be retained during deep sleep. + * User data marked with RTC_NOINIT_ATTR will be placed + * into this section. See the file "esp_attr.h" for more information. + */ + .rtc_noinit (NOLOAD): + { + ALIGNED_SYMBOL(4, _rtc_noinit_start) + + *(.rtc_noinit .rtc_noinit.*) + + ALIGNED_SYMBOL(4, _rtc_noinit_end) + } > lp_ram_seg + + /** + * This section located in RTC SLOW Memory area. + * It holds data marked with RTC_SLOW_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : + { + ALIGNED_SYMBOL(4, _rtc_force_slow_start) + + *(.rtc.force_slow .rtc.force_slow.*) + + ALIGNED_SYMBOL(4, _rtc_force_slow_end) + } > lp_ram_seg + +#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND + .rtc.p4_rev3_mspi_workaround : + { + ALIGNED_SYMBOL(4, _rtc_p4_rev3_mspi_workaround_start) + KEEP (*(.p4_rev3_mspi_workaround.rtc_text .p4_rev3_mspi_workaround.rtc_text.*)) + ALIGNED_SYMBOL(4, _rtc_p4_rev3_mspi_workaround_end) + } > rev3_mspi_workaround_seg +#endif + + /** + * This section holds RTC data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep + * sleep. + */ + .rtc_reserved (NOLOAD): + { + ALIGNED_SYMBOL(4, _rtc_reserved_start) + + KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) + *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) + + /** + * New data can only be added here to ensure existing data are not moved. + * Because data have adhered to the beginning of the segment and code is relied + * on it. + * >> put new data here << + */ + + _rtc_reserved_end = ABSOLUTE(.); + } > rtc_reserved_seg + + _rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start; + _rtc_ulp_memory_start = _rtc_reserved_start + LENGTH(rtc_reserved_seg); + ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)), + "RTC reserved segment data does not fit.") + + /* Get size of rtc slow data based on rtc_data_location alias */ + _rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) + ? (_rtc_force_slow_end - _rtc_data_start) + : (_rtc_force_slow_end - _rtc_force_slow_start); + + _rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) + ? (_rtc_force_fast_end - _rtc_fast_start) + : (_rtc_noinit_end - _rtc_fast_start); + + ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), + "RTC_SLOW segment data does not fit.") + + ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), + "RTC_FAST segment data does not fit.") + + .tcm.text : + { + /* Code marked as running out of TCM */ + _tcm_text_start = ABSOLUTE(.); + + arrays[tcm_text] + mapping[tcm_text] + + _tcm_text_end = ABSOLUTE(.); + } > tcm_idram_seg + + .tcm.data : + { + _tcm_data_start = ABSOLUTE(.); + + arrays[tcm_data] + mapping[tcm_data] + + _tcm_data_end = ABSOLUTE(.); + } > tcm_idram_seg + + .iram0.text : + { + _iram_start = ABSOLUTE(.); + /* Vectors go to start of IRAM */ + ASSERT(ABSOLUTE(.) % 0x40 == 0, "vector address must be 64 byte aligned"); + KEEP(*(.exception_vectors_table.text)); + KEEP(*(.exception_vectors.text)); + + /* Code marked as running out of IRAM */ + _iram_text_start = ABSOLUTE(.); + + mapping[iram0_text] + + } > sram_seg + + /* Marks the end of IRAM code segment */ + .iram0.text_end (NOLOAD) : + { + /* Align the end of code region as per PMP region granularity */ + . = ALIGN(_esp_pmp_align_size); + + ALIGNED_SYMBOL(4, _iram_text_end) + } > sram_seg + + .iram0.data : + { + ALIGNED_SYMBOL(16, _iram_data_start) + + mapping[iram0_data] + + _iram_data_end = ABSOLUTE(.); + } > sram_seg + + .iram0.bss (NOLOAD) : + { + ALIGNED_SYMBOL(16, _iram_bss_start) + + mapping[iram0_bss] + + _iram_bss_end = ABSOLUTE(.); + + ALIGNED_SYMBOL(16, _iram_end) + } > sram_seg + + /** + * This section is required to skip .iram0.text area because sram_seg and + * sram_seg reflect the same address space on different buses. + */ + .dram0.dummy (NOLOAD): + { + . = ORIGIN(sram_seg) + _iram_end - _iram_start; + } > sram_seg + + .dram0.data : + { + _data_start = ABSOLUTE(.); + *(.gnu.linkonce.d.*) + *(.data1) + __global_pointer$ = . + 0x800; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + + mapping[dram0_data] + + _data_end = ABSOLUTE(.); + } > sram_seg + + /** + * This section holds data that should not be initialized at power up. + * The section located in Internal SRAM memory region. The macro _NOINIT + * can be used as attribute to place data into this section. + * See the "esp_attr.h" file for more information. + */ + .noinit (NOLOAD): + { + ALIGNED_SYMBOL(4, _noinit_start) + + *(.noinit .noinit.*) + + ALIGNED_SYMBOL(4, _noinit_end) + } > sram_seg + + .dram0.bss (NOLOAD) : + { + ALIGNED_SYMBOL(4, _bss_start) + + /** + * ldgen places all bss-related data to mapping[dram0_bss] + * (See components/esp_system/app.lf). + */ + mapping[dram0_bss] + + ALIGNED_SYMBOL(4, _bss_end) + } > sram_seg + + /* Marks the end of data, bss and possibly rodata */ + .dram0.heap_start (NOLOAD) : + { + ALIGNED_SYMBOL(16, _heap_start) + } > sram_seg + + ASSERT(((_heap_start - ORIGIN(sram_seg)) <= LENGTH(sram_seg)), "DRAM segment data does not fit.") + + .flash.text : + { + _stext = .; + /** + * Mark the start of flash.text. + * This can be used by the MMU driver to maintain the virtual address. + */ + _instruction_reserved_start = ABSOLUTE(.); + _text_start = ABSOLUTE(.); + + arrays[flash_text] + mapping[flash_text] + + *(.stub) + *(.gnu.linkonce.t.*) + *(.gnu.warning) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + + /** + * CPU will try to prefetch up to 16 bytes of of instructions. + * This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += _esp_flash_mmap_prefetch_pad_size; + +#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION + /* Align the end of flash text region as per PMP granularity to allow using the + * page alignment gap created while mapping the flash region into the PSRAM memory. + */ + . = ALIGN(_esp_pmp_align_size); +#endif // CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION + + _text_end = ABSOLUTE(.); + /** + * Mark the flash.text end. + * This can be used for MMU driver to maintain virtual address. + */ + _instruction_reserved_end = ABSOLUTE(.); + _etext = .; + + /** + * Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } > text_seg_low + + /** + * Dummy section represents the .flash.text section but in default_rodata_seg. + * Thus, it must have its alignment and (at least) its size. + */ + .flash_rodata_dummy (NOLOAD): + { + _flash_rodata_dummy_start = .; + + . = ALIGN(ALIGNOF(.flash.text)) + SIZEOF(.flash.text); + + /* Add alignment of MMU page size + 0x20 bytes for the mapping header. */ + . = ALIGN(_esp_mmu_page_size) + 0x20; + } > rodata_seg_low + + .flash.appdesc : ALIGN(0x10) + { + /** + * Mark flash.rodata start. + * This can be used for mmu driver to maintain virtual address + */ + _rodata_reserved_start = ABSOLUTE(.); + _rodata_start = ABSOLUTE(.); + + /* !DO NOT PUT ANYTHING BEFORE THIS! */ + + /* Should be the first. App version info. */ + *(.rodata_desc .rodata_desc.*) + /* Should be the second. Custom app version info. */ + *(.rodata_custom_desc .rodata_custom_desc.*) + + /** + * Create an empty gap within this section. Thanks to this, the end of this + * section will match .flash.rodata's begin address. Thus, both sections + * will be merged when creating the final bin image. + */ + . = ALIGN(ALIGNOF(.flash.rodata)); + } > rodata_seg_low + ASSERT_SECTIONS_GAP(.flash.appdesc, .flash.rodata) + + .flash.rodata : ALIGN(0x10) + { + _flash_rodata_start = ABSOLUTE(.); + + arrays[flash_rodata] + mapping[flash_rodata] + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + . = ALIGN(ALIGNOF(.flash.init_array)); + } > rodata_seg_low + ASSERT_SECTIONS_GAP(.flash.rodata, .flash.init_array) + + .flash.init_array : + { + /** + * C++ constructor tables. + * + * Excluding crtbegin.o/crtend.o since IDF doesn't use the toolchain crt. + * + * RISC-V gcc is configured with --enable-initfini-array so it emits + * .init_array section instead. But the init_priority sections will be + * sorted for iteration in ascending order during startup. + * The rest of the init_array sections is sorted for iteration in descending + * order during startup, however. Hence a different section is generated for + * the init_priority functions which is iterated in ascending order during + * startup. The corresponding code can be found in startup.c. + */ + ALIGNED_SYMBOL(4, __init_priority_array_start) + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) + __init_priority_array_end = ABSOLUTE(.); + + ALIGNED_SYMBOL(4, __init_array_start) + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) + __init_array_end = ABSOLUTE(.); + + /* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */ + ALIGNED_SYMBOL(4, soc_reserved_memory_region_start) + KEEP (*(.reserved_memory_address)) + soc_reserved_memory_region_end = ABSOLUTE(.); + + /* System init functions registered via ESP_SYSTEM_INIT_FN */ + ALIGNED_SYMBOL(4, _esp_system_init_fn_array_start) + KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*))) + _esp_system_init_fn_array_end = ABSOLUTE(.); + + _rodata_end = ABSOLUTE(.); + . = ALIGN(ALIGNOF(.eh_frame_hdr)); + } > rodata_seg_low + ASSERT_SECTIONS_GAP(.flash.init_array, .eh_frame_hdr) + + .eh_frame_hdr : + { +#if CONFIG_COMPILER_CXX_EXCEPTIONS || CONFIG_ESP_SYSTEM_USE_EH_FRAME + ALIGNED_SYMBOL(4, __eh_frame_hdr) + + KEEP (*(.eh_frame_hdr)) + + __eh_frame_hdr_end = ABSOLUTE(.); +#endif // CONFIG_COMPILER_CXX_EXCEPTIONS || CONFIG_ESP_SYSTEM_USE_EH_FRAME + + . = ALIGN(ALIGNOF(.eh_frame)); + } > rodata_seg_low + ASSERT_SECTIONS_GAP(.eh_frame_hdr, .eh_frame) + + .eh_frame : + { +#if CONFIG_COMPILER_CXX_EXCEPTIONS || CONFIG_ESP_SYSTEM_USE_EH_FRAME + ALIGNED_SYMBOL(4, __eh_frame) + + KEEP (*(.eh_frame)) + /** + * As we are not linking with crtend.o, which includes the CIE terminator + * (see __FRAME_END__ in libgcc sources), it is manually provided here. + */ + LONG(0); + + __eh_frame_end = ABSOLUTE(.); +#endif // CONFIG_COMPILER_CXX_EXCEPTIONS || CONFIG_ESP_SYSTEM_USE_EH_FRAME + + . = ALIGN(ALIGNOF(.flash.tdata)); + } > rodata_seg_low + ASSERT_SECTIONS_GAP(.eh_frame, .flash.tdata) + + .flash.tdata : + { + _thread_local_data_start = ABSOLUTE(.); + + *(.tdata .tdata.* .gnu.linkonce.td.*) + + . = ALIGN(ALIGNOF(.flash.tbss)); + +#if CONFIG_SPIRAM_RODATA && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION + /* Align the end of flash rodata region as per PMP granularity to allow using the + * page alignment gap created while mapping the flash region into the PSRAM memory. + */ + . = ALIGN(_esp_pmp_align_size); +#endif // CONFIG_SPIRAM_RODATA && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION + + _thread_local_data_end = ABSOLUTE(.); + } > rodata_seg_low + ASSERT_SECTIONS_GAP(.flash.tdata, .flash.tbss) + + .flash.tbss (NOLOAD) : + { + _thread_local_bss_start = ABSOLUTE(.); + + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon .tcommon.*) + + _thread_local_bss_end = ABSOLUTE(.); + } > rodata_seg_low + + /** + * This section contains all the rodata that is not used + * at runtime, helping to avoid an increase in binary size. + */ + .flash.rodata_noload (NOLOAD) : + { + /** + * This symbol marks the end of flash.rodata. It can be utilized by the MMU + * driver to maintain the virtual address. + * NOLOAD rodata may not be included in this section. + */ + _rodata_reserved_end = ADDR(.flash.tbss); + + arrays[rodata_noload] + mapping[rodata_noload] + } > rodata_seg_low + +#if CONFIG_SPIRAM_XIP_FROM_PSRAM + /** + * This section is required to skip flash sections, because `extern_ram_seg` + * and `drom_seg` / `irom_seg` are on the same bus when xip on psram + */ + .ext_ram.dummy (NOLOAD): + { + . = ORIGIN(ext_ram_seg) + (_rodata_reserved_end - _flash_rodata_dummy_start); + . = ALIGN (_esp_mmu_page_size); + } > ext_ram_seg +#endif //CONFIG_SPIRAM_XIP_FROM_PSRAM + +#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY + /* This section holds .ext_ram.bss data, and will be put in PSRAM */ + .ext_ram.bss (NOLOAD) : + { + _ext_ram_bss_start = ABSOLUTE(.); + arrays[extern_ram] + mapping[extern_ram] + ALIGNED_SYMBOL(4, _ext_ram_bss_end) + } > ext_ram_seg +#endif //CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY + +#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY + /** + * This section holds data that won't be initialised when startup. + * This section locates in External RAM region. + */ + .ext_ram_noinit (NOLOAD) : + { + _ext_ram_noinit_start = ABSOLUTE(.); + + *(.ext_ram_noinit*) + + ALIGNED_SYMBOL(4, _ext_ram_noinit_end) + } > ext_ram_seg +#endif //CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY + +#include "elf_misc.ld.in" +} diff --git a/components/esp_system/ld/ld.cmake b/components/esp_system/ld/ld.cmake index 5fbb90f6c576..7ddc776c9a7e 100644 --- a/components/esp_system/ld/ld.cmake +++ b/components/esp_system/ld/ld.cmake @@ -48,6 +48,10 @@ preprocess_linker_file("memory.ld.in" "memory.ld" ld_out_path) target_linker_script(${COMPONENT_LIB} INTERFACE "${ld_out_path}") # Generate sections.ld.in and pass it through linker script generator -preprocess_linker_file("sections.ld.in" "sections.ld.in" ld_out_path) +if(CONFIG_ESP32P4_REV_MIN_300) + preprocess_linker_file("sections.rev3.ld.in" "sections.ld.in" ld_out_path) +else() + preprocess_linker_file("sections.ld.in" "sections.ld.in" ld_out_path) +endif() target_linker_script(${COMPONENT_LIB} INTERFACE "${ld_out_path}" PROCESS "${CMAKE_CURRENT_BINARY_DIR}/ld/sections.ld") diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 74c20e315a54..f769faefe7c1 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -121,13 +121,13 @@ #include "esp_private/startup_internal.h" #include "esp_private/system_internal.h" -#if SOC_MEM_NON_CONTIGUOUS_SRAM +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 extern int _bss_start_low, _bss_start_high; extern int _bss_end_low, _bss_end_high; #else extern int _bss_start; extern int _bss_end; -#endif // SOC_MEM_NON_CONTIGUOUS_SRAM +#endif // CONFIG_ESP32P4_SELECTS_REV_LESS_V3 extern int _rtc_bss_start; extern int _rtc_bss_end; #if CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED @@ -431,12 +431,12 @@ void IRAM_ATTR call_start_cpu0(void) #endif //Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this. -#if SOC_MEM_NON_CONTIGUOUS_SRAM +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 memset(&_bss_start_low, 0, (&_bss_end_low - &_bss_start_low) * sizeof(_bss_start_low)); memset(&_bss_start_high, 0, (&_bss_end_high - &_bss_start_high) * sizeof(_bss_start_high)); #else memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start)); -#endif // SOC_MEM_NON_CONTIGUOUS_SRAM +#endif // CONFIG_ESP32P4_SELECTS_REV_LESS_V3 #if CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED // Clear Bluetooth bss @@ -523,12 +523,6 @@ void IRAM_ATTR call_start_cpu0(void) Cache_Resume_DCache(0); #endif // CONFIG_IDF_TARGET_ESP32S3 -#if CONFIG_IDF_TARGET_ESP32P4 - //TODO: IDF-5670, add cache init API - extern void esp_config_l2_cache_mode(void); - esp_config_l2_cache_mode(); -#endif - #if ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE #if CONFIG_APP_BUILD_TYPE_ELF_RAM // For RAM loadable ELF case, we don't need to reserve IROM/DROM as instructions and data diff --git a/components/esp_system/port/soc/esp32/system_internal.c b/components/esp_system/port/soc/esp32/system_internal.c index fa91ea850bf5..bd6a26de7c57 100644 --- a/components/esp_system/port/soc/esp32/system_internal.c +++ b/components/esp_system/port/soc/esp32/system_internal.c @@ -48,8 +48,13 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, //UART TX FIFO cannot be reset correctly on ESP32, so reset the UART memory by DPORT here. DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | - DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | - DPORT_UART_MEM_RST | DPORT_PWM0_RST | DPORT_PWM1_RST); + // The DMA inside SPI needs to be reset to avoid memory corruption after restart. + DPORT_SPI_DMA_RST | + DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST | + DPORT_PWM0_RST | DPORT_PWM1_RST | + // The DMA inside I2S needs to be reset to avoid memory corruption after restart. + DPORT_I2S0_RST | DPORT_I2S1_RST | + DPORT_UHCI0_RST | DPORT_UHCI1_RST); DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); // Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart and hence diff --git a/components/esp_system/port/soc/esp32c5/system_internal.c b/components/esp_system/port/soc/esp32c5/system_internal.c index 4afbaf9c4947..c406b57e386f 100644 --- a/components/esp_system/port/soc/esp32c5/system_internal.c +++ b/components/esp_system/port/soc/esp32c5/system_internal.c @@ -52,6 +52,8 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN); SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN); SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN); + //ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control. + SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN); // Clear Peripheral clk rst CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN); @@ -59,9 +61,9 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN); CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN); CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN); - // CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN); CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN); CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN); + CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN); // Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart // and hence avoiding any possibility with crypto failure in ROM security workflows. diff --git a/components/esp_system/port/soc/esp32c6/system_internal.c b/components/esp_system/port/soc/esp32c6/system_internal.c index 5d4bf93131c7..1ad1068d1c30 100644 --- a/components/esp_system/port/soc/esp32c6/system_internal.c +++ b/components/esp_system/port/soc/esp32c6/system_internal.c @@ -51,6 +51,8 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) SET_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN); SET_PERI_REG_MASK(PCR_MODEM_APB_CONF_REG, PCR_MODEM_RST_EN); SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN); + //ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control. + SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN); // Clear Peripheral clk rst CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN); @@ -61,6 +63,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN); CLEAR_PERI_REG_MASK(PCR_MODEM_APB_CONF_REG, PCR_MODEM_RST_EN); CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN); + CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN); // Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart // and hence avoiding any possibility with crypto failure in ROM security workflows. diff --git a/components/esp_system/port/soc/esp32c61/system_internal.c b/components/esp_system/port/soc/esp32c61/system_internal.c index bfe80c1055c7..83d6204f70cb 100644 --- a/components/esp_system/port/soc/esp32c61/system_internal.c +++ b/components/esp_system/port/soc/esp32c61/system_internal.c @@ -54,6 +54,10 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) SET_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN); SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN); SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN); + // The DMA inside SDIO slave needs to be reset to avoid memory corruption after restart. + SET_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN); + //ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control. + SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN); // Clear Peripheral clk rst CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN); @@ -62,6 +66,8 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN); CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN); CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN); + CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN); + CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN); // Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart // and hence avoiding any possibility with crypto failure in ROM security workflows. diff --git a/components/esp_system/port/soc/esp32h2/system_internal.c b/components/esp_system/port/soc/esp32h2/system_internal.c index e08beb85eae3..26975864a8d3 100644 --- a/components/esp_system/port/soc/esp32h2/system_internal.c +++ b/components/esp_system/port/soc/esp32h2/system_internal.c @@ -48,6 +48,8 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN); SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN); SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN); + //ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control. + SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN); // Clear Peripheral clk rst CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN); @@ -57,6 +59,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN); CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN); CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN); + CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN); // Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart // and hence avoiding any possibility with crypto failure in ROM security workflows. diff --git a/components/esp_system/port/soc/esp32p4/Kconfig.cpu b/components/esp_system/port/soc/esp32p4/Kconfig.cpu index 18ad8025983f..d88464cc994d 100644 --- a/components/esp_system/port/soc/esp32p4/Kconfig.cpu +++ b/components/esp_system/port/soc/esp32p4/Kconfig.cpu @@ -1,7 +1,8 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ prompt "CPU frequency" default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA || ESP_BRINGUP_BYPASS_CPU_CLK_SETTING - default ESP_DEFAULT_CPU_FREQ_MHZ_360 + default ESP_DEFAULT_CPU_FREQ_MHZ_360 if ESP32P4_SELECTS_REV_LESS_V3 + default ESP_DEFAULT_CPU_FREQ_MHZ_400 help CPU frequency to be set on application startup. @@ -10,9 +11,13 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ depends on IDF_ENV_FPGA || ESP_BRINGUP_BYPASS_CPU_CLK_SETTING config ESP_DEFAULT_CPU_FREQ_MHZ_360 bool "360 MHz" + depends on ESP32P4_SELECTS_REV_LESS_V3 + config ESP_DEFAULT_CPU_FREQ_MHZ_400 + bool "400 MHz" endchoice config ESP_DEFAULT_CPU_FREQ_MHZ int default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40 default 360 if ESP_DEFAULT_CPU_FREQ_MHZ_360 + default 400 if ESP_DEFAULT_CPU_FREQ_MHZ_400 diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c index 7ecf0801db3a..bf88f0dd6d23 100644 --- a/components/esp_system/port/soc/esp32p4/clk.c +++ b/components/esp_system/port/soc/esp32p4/clk.c @@ -260,17 +260,8 @@ __attribute__((weak)) void esp_perip_clk_init(void) REG_CLR_BIT(HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG, HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON | HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON | HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON - | HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON - | HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON - | HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON - | HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON | HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON - | HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON - | HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON - | HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON - | HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON - | HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON - | HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON); + | HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON); _adc_ll_sar1_clock_force_en(false); _adc_ll_sar2_clock_force_en(false); _emac_ll_clock_force_en(false); diff --git a/components/esp_system/port/soc/esp32p4/system_internal.c b/components/esp_system/port/soc/esp32p4/system_internal.c index bde5b6fdd9f9..d046c54848b7 100644 --- a/components/esp_system/port/soc/esp32p4/system_internal.c +++ b/components/esp_system/port/soc/esp32p4/system_internal.c @@ -69,28 +69,38 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) } // Set Peripheral clk rst + SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI); + SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI); + // DMA needs to be reset to avoid memory corruption after restart. Now only AHB supports this. + // For other AXI DMAs, we have already stop them above. + SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA); SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1); SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_STIMER); - SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI); - SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI); SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART0_CORE); SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART1_CORE); SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART2_CORE); SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART3_CORE); SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART4_CORE); SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_ADC); + SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_H264); // Clear Peripheral clk rst + CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI); + CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI); + CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA); CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1); CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_STIMER); - CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI); - CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI); CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART0_CORE); CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART1_CORE); CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART2_CORE); CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART3_CORE); CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_UART4_CORE); CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_ADC); + CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_H264); + + // The DMA inside SDMMC Host needs to be reset to avoid memory corruption after restart. + SET_PERI_REG_MASK(LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG, LP_CLKRST_RST_EN_SDMMC); + CLEAR_PERI_REG_MASK(LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG, LP_CLKRST_RST_EN_SDMMC); // Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart // and hence avoiding any possibility with crypto failure in ROM security workflows. diff --git a/components/esp_system/port/soc/esp32s3/system_internal.c b/components/esp_system/port/soc/esp32s3/system_internal.c index 35201287e9de..06284724e7a8 100644 --- a/components/esp_system/port/soc/esp32s3/system_internal.c +++ b/components/esp_system/port/soc/esp32s3/system_internal.c @@ -56,7 +56,9 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) // Reset dma and crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart // and hence avoiding any possibility with crypto failure in ROM security workflows. SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST | SYSTEM_CRYPTO_AES_RST | SYSTEM_CRYPTO_DS_RST | - SYSTEM_CRYPTO_HMAC_RST | SYSTEM_CRYPTO_RSA_RST | SYSTEM_CRYPTO_SHA_RST); + SYSTEM_CRYPTO_HMAC_RST | SYSTEM_CRYPTO_RSA_RST | SYSTEM_CRYPTO_SHA_RST | + // The DMA inside SDMMC Host needs to be reset to avoid memory corruption after restart. + SYSTEM_SDIO_HOST_RST); REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); diff --git a/components/esp_wifi/Kconfig b/components/esp_wifi/Kconfig index 10fbc5c53bdb..6fec8447b404 100644 --- a/components/esp_wifi/Kconfig +++ b/components/esp_wifi/Kconfig @@ -723,6 +723,14 @@ menu "Wi-Fi" be shared to other devices, making it in readable format increases that risk, also passphrase requires pbkdf2 to convert in psk. + config ESP_WIFI_WPS_RECONNECT_ON_FAIL + bool "Reconnect to previous SSID if WPS failed" + default n + help + Select this option to enable reconnection to previous SSID if WPS fails. + This option will only work if station was connected to a network + when WPS was started. + endmenu # "WPS Configuration Options" @@ -737,12 +745,6 @@ menu "Wi-Fi" Enabling this could increase the build size ~60kb depending on the project logging level. - config ESP_WIFI_TESTING_OPTIONS - bool "Add DPP testing code" - default n - help - Select this to enable unity test for DPP. - config ESP_WIFI_ENTERPRISE_SUPPORT bool "Enable enterprise option" default y diff --git a/components/esp_wifi/include/esp_now.h b/components/esp_wifi/include/esp_now.h index ddc1f9efae48..29116fa92d11 100644 --- a/components/esp_wifi/include/esp_now.h +++ b/components/esp_wifi/include/esp_now.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,23 +15,6 @@ extern "C" { #endif -/** \defgroup WiFi_APIs WiFi Related APIs - * @brief WiFi APIs - */ - -/** @addtogroup WiFi_APIs - * @{ - */ - -/** \defgroup ESPNOW_APIs ESPNOW APIs - * @brief ESP32 ESPNOW APIs - * - */ - -/** @addtogroup ESPNOW_APIs - * @{ - */ - #define ESP_ERR_ESPNOW_BASE (ESP_ERR_WIFI_BASE + 100) /*!< ESPNOW error number base. */ #define ESP_ERR_ESPNOW_NOT_INIT (ESP_ERR_ESPNOW_BASE + 1) /*!< ESPNOW is not initialized. */ #define ESP_ERR_ESPNOW_ARG (ESP_ERR_ESPNOW_BASE + 2) /*!< Invalid argument */ @@ -368,14 +351,6 @@ esp_err_t esp_now_set_pmk(const uint8_t *pmk); */ esp_err_t esp_now_set_wake_window(uint16_t window); -/** - * @} - */ - -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index eda58fb15f0c..e87a28e2ded5 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit eda58fb15f0cdd4cb8bac2b46ea97b31f0ef0316 +Subproject commit e87a28e2ded519804ebbe1605ba9eee988262ecd diff --git a/components/esp_wifi/sdkconfig.rename b/components/esp_wifi/sdkconfig.rename index 3d43daf19822..273b291fb560 100644 --- a/components/esp_wifi/sdkconfig.rename +++ b/components/esp_wifi/sdkconfig.rename @@ -35,7 +35,6 @@ CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT CONFIG_WPA_WAPI_PSK CONFIG_ESP_WIFI_WAPI_PSK CONFIG_WPA_SUITE_B_192 CONFIG_ESP_WIFI_SUITE_B_192 CONFIG_WPA_DEBUG_PRINT CONFIG_ESP_WIFI_DEBUG_PRINT -CONFIG_WPA_TESTING_OPTIONS CONFIG_ESP_WIFI_TESTING_OPTIONS CONFIG_WPA_WPS_STRICT CONFIG_ESP_WIFI_WPS_STRICT CONFIG_WPA_11KV_SUPPORT CONFIG_ESP_WIFI_11KV_SUPPORT CONFIG_WPA_SCAN_CACHE CONFIG_ESP_WIFI_SCAN_CACHE diff --git a/components/freertos/FreeRTOS-Kernel/include/freertos/task.h b/components/freertos/FreeRTOS-Kernel/include/freertos/task.h index a2bf05e2489f..2feb86276ade 100644 --- a/components/freertos/FreeRTOS-Kernel/include/freertos/task.h +++ b/components/freertos/FreeRTOS-Kernel/include/freertos/task.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: MIT * - * SPDX-FileContributor: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2023-2025 Espressif Systems (Shanghai) CO LTD * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -1493,9 +1493,9 @@ TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; / * this function to be available. * * Returns the high water mark of the stack associated with xTask. That is, - * the minimum free stack space there has been (in words, so on a 32 bit machine - * a value of 1 means 4 bytes) since the task started. The smaller the returned - * number the closer the task has come to overflowing its stack. + * the minimum free stack space there has been in bytes (as opposed to words + * in the standard FreeRTOS documentation) since the task started. The smaller + * the returned number the closer the task has come to overflowing its stack. * * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the * same except for their return type. Using configSTACK_DEPTH_TYPE allows the @@ -1506,9 +1506,9 @@ TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; / * @param xTask Handle of the task associated with the stack to be checked. * Set xTask to NULL to check the stack of the calling task. * - * @return The smallest amount of free stack space there has been (in words, so - * actual spaces on the stack rather than bytes) since the task referenced by - * xTask was created. + * @return The smallest amount of free stack space there has been in bytes + * (as opposed to words in the standard FreeRTOS documentation) since the task + * referenced by xTask was created. */ UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; @@ -1518,9 +1518,9 @@ UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTIO * this function to be available. * * Returns the high water mark of the stack associated with xTask. That is, - * the minimum free stack space there has been (in words, so on a 32 bit machine - * a value of 1 means 4 bytes) since the task started. The smaller the returned - * number the closer the task has come to overflowing its stack. + * the minimum free stack space there has been in bytes (as opposed to words in + * the standard FreeRTOS documentation) since the task started. The smaller the + * returned number the closer the task has come to overflowing its stack. * * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the * same except for their return type. Using configSTACK_DEPTH_TYPE allows the @@ -1531,9 +1531,9 @@ UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTIO * @param xTask Handle of the task associated with the stack to be checked. * Set xTask to NULL to check the stack of the calling task. * - * @return The smallest amount of free stack space there has been (in words, so - * actual spaces on the stack rather than bytes) since the task referenced by - * xTask was created. + * @return The smallest amount of free stack space there has been in bytes + * (as opposed to words in the standard FreeRTOS documentation) since the task + * referenced by xTask was created. */ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; diff --git a/components/hal/cache_hal.c b/components/hal/cache_hal.c index 1c518b46f5e4..00d2a81fd139 100644 --- a/components/hal/cache_hal.c +++ b/components/hal/cache_hal.c @@ -55,6 +55,31 @@ void s_cache_hal_init_ctx(void) ctx.l2.i_autoload_en = cache_ll_is_cache_autoload_enabled(2, CACHE_TYPE_INSTRUCTION, CACHE_LL_ID_ALL); } +#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE +//TODO: IDF-5670, add cache init API, then don't need sdkconfig +void cache_hal_init_l2_cache(void) +{ + cache_size_t cache_size; + cache_line_size_t cache_line_size; +#if CONFIG_CACHE_L2_CACHE_128KB + cache_size = CACHE_SIZE_128K; +#elif CONFIG_CACHE_L2_CACHE_256KB + cache_size = CACHE_SIZE_256K; +#else + cache_size = CACHE_SIZE_512K; +#endif + +#if CONFIG_CACHE_L2_CACHE_LINE_64B + cache_line_size = CACHE_LINE_SIZE_64B; +#else + cache_line_size = CACHE_LINE_SIZE_128B; +#endif + + Cache_Set_L2_Cache_Mode(cache_size, 8, cache_line_size); + Cache_Invalidate_All(CACHE_MAP_L2_CACHE); +} +#endif + void cache_hal_init(void) { s_cache_hal_init_ctx(); @@ -78,6 +103,10 @@ void cache_hal_init(void) ctx.l2.i_cache_enabled = 1; ctx.l2.d_cache_enabled = 1; #endif + +#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE + cache_hal_init_l2_cache(); +#endif } #if CACHE_LL_ENABLE_DISABLE_STATE_SW diff --git a/components/hal/color_hal.c b/components/hal/color_hal.c index 664d97490db0..c26b3db6a659 100644 --- a/components/hal/color_hal.c +++ b/components/hal/color_hal.c @@ -29,6 +29,8 @@ uint32_t color_hal_pixel_format_get_bit_depth(color_space_pixel_format_t format) case COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565): case COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422): return 16; + case COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB666): + return 18; case COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB888): case COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV444): return 24; diff --git a/components/hal/esp32p4/include/hal/ahb_dma_ll.h b/components/hal/esp32p4/include/hal/ahb_dma_ll.h index 383062c995cb..2b0890214674 100644 --- a/components/hal/esp32p4/include/hal/ahb_dma_ll.h +++ b/components/hal/esp32p4/include/hal/ahb_dma_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -69,6 +69,31 @@ static inline void ahb_dma_ll_set_default_memory_range(ahb_dma_dev_t *dev) dev->intr_mem_end_addr.val = 0x4FFC0000; } +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +/** + * @brief Enable the weighted arbitration for AHB-DMA + * + * @param dev DMA register base address + * @param enable True to enable, false to disable + */ +static inline void ahb_dma_ll_enable_weighted_arb(ahb_dma_dev_t *dev, bool enable) +{ + dev->weight_en.weight_en = enable; +} + +/** + * @brief Set the weighted arbitration timeout for AHB-DMA + * + * @param dev DMA register base address + * @param timeout AHB bus clock cycle + */ +static inline void ahb_dma_ll_set_weighted_arb_timeout(ahb_dma_dev_t *dev, uint32_t timeout) +{ + HAL_ASSERT(timeout != 0 && timeout <= 65535); + dev->arb_timeout.arb_timeout_num = timeout; +} +#endif + ///////////////////////////////////// RX ///////////////////////////////////////// /** * @brief Get DMA RX channel interrupt status word @@ -136,6 +161,34 @@ static inline void ahb_dma_ll_rx_enable_descriptor_burst(ahb_dma_dev_t *dev, uin dev->channel[channel].in.in_conf0.indscr_burst_en_chn = enable; } +#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE +/** + * @brief Set RX channel burst size + */ +static inline void ahb_dma_ll_rx_set_burst_size(ahb_dma_dev_t *dev, uint32_t channel, uint32_t sz) +{ + uint8_t burst_mode = 0; + switch (sz) { + case 4: + burst_mode = 0; // single + break; + case 16: + burst_mode = 1; // incr4 + break; + case 32: + burst_mode = 2; // incr8 + break; + case 64: + burst_mode = 3; // incr16 + break; + default: + HAL_ASSERT(false); + break; + } + dev->channel[channel].in.in_conf0.in_data_burst_mode_sel_chn = burst_mode; +} +#endif + /** * @brief Reset DMA RX channel FSM and FIFO pointer */ @@ -297,6 +350,32 @@ static inline void ahb_dma_ll_rx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t ch dev->channel[channel].in.in_conf0.in_etm_en_chn = enable; } +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +/** + * @brief Enable the weighted arbitration optimize for DMA RX channel + * + * @param dev DMA register base address + * @param channel Channel ID + * @param enable True to enable, false to disable + */ +static inline void ahb_dma_ll_rx_enable_weighted_arb_opt(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->in_crc_arb[channel].arb_weight_opt.rx_arb_weight_opt_dis_chn = !enable; +} + +/** + * @brief Set the weight for DMA RX channel + * + * @param dev DMA register base address + * @param channel Channel ID + * @param weight Weight value + */ +static inline void ahb_dma_ll_rx_set_weight(ahb_dma_dev_t *dev, uint32_t channel, uint32_t weight) +{ + dev->in_crc_arb[channel].ch_arb_weight.rx_arb_weight_value_chn = weight; +} +#endif + ///////////////////////////////////// TX ///////////////////////////////////////// /** * @brief Get DMA TX channel interrupt status word @@ -364,6 +443,34 @@ static inline void ahb_dma_ll_tx_enable_descriptor_burst(ahb_dma_dev_t *dev, uin dev->channel[channel].out.out_conf0.outdscr_burst_en_chn = enable; } +#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE +/** + * @brief Set TX channel burst size + */ +static inline void ahb_dma_ll_tx_set_burst_size(ahb_dma_dev_t *dev, uint32_t channel, uint32_t sz) +{ + uint8_t burst_mode = 0; + switch (sz) { + case 4: + burst_mode = 0; // single + break; + case 16: + burst_mode = 1; // incr4 + break; + case 32: + burst_mode = 2; // incr8 + break; + case 64: + burst_mode = 3; // incr16 + break; + default: + HAL_ASSERT(false); + break; + } + dev->channel[channel].out.out_conf0.out_data_burst_mode_sel_chn = burst_mode; +} +#endif + /** * @brief Set TX channel EOF mode */ @@ -523,6 +630,32 @@ static inline void ahb_dma_ll_tx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t ch dev->channel[channel].out.out_conf0.out_etm_en_chn = enable; } +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +/** + * @brief Enable the weighted arbitration optimize for DMA TX channel + * + * @param dev DMA register base address + * @param channel Channel ID + * @param enable True to enable, false to disable + */ +static inline void ahb_dma_ll_tx_enable_weighted_arb_opt(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->out_crc_arb[channel].arb_weight_opt.tx_arb_weight_opt_dis_chn = !enable; +} + +/** + * @brief Set the weight for DMA TX channel + * + * @param dev DMA register base address + * @param channel Channel ID + * @param weight Weight value + */ +static inline void ahb_dma_ll_tx_set_weight(ahb_dma_dev_t *dev, uint32_t channel, uint32_t weight) +{ + dev->out_crc_arb[channel].ch_arb_weight.tx_arb_weight_value_chn = weight; +} +#endif + ///////////////////////////////////// CRC-TX ///////////////////////////////////////// /** diff --git a/components/hal/esp32p4/include/hal/dw_gdma_ll.h b/components/hal/esp32p4/include/hal/dw_gdma_ll.h index e20692884456..30f0c35e5b3c 100644 --- a/components/hal/esp32p4/include/hal/dw_gdma_ll.h +++ b/components/hal/esp32p4/include/hal/dw_gdma_ll.h @@ -294,6 +294,7 @@ static inline void dw_gdma_ll_channel_clear_intr(dw_gdma_dev_t *dev, uint8_t cha * @param channel Channel number * @param en True to enable, false to disable */ +__attribute__((always_inline)) static inline void dw_gdma_ll_channel_enable(dw_gdma_dev_t *dev, uint8_t channel, bool en) { if (en) { @@ -812,6 +813,7 @@ static inline void dw_gdma_ll_channel_set_dst_outstanding_limit(dw_gdma_dev_t *d * @param channel Channel number * @param addr Address of the first link list item, it must be aligned 64 bytes */ +__attribute__((always_inline)) static inline void dw_gdma_ll_channel_set_link_list_head_addr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t addr) { dev->ch[channel].llp0.loc0 = addr >> 6; @@ -840,6 +842,7 @@ static inline intptr_t dw_gdma_ll_channel_get_current_link_list_item_addr(dw_gdm * @param channel Channel number * @param port Master port */ +__attribute__((always_inline)) static inline void dw_gdma_ll_channel_set_link_list_master_port(dw_gdma_dev_t *dev, uint8_t channel, uint32_t port) { dev->ch[channel].llp0.lms = port; diff --git a/components/hal/esp32p4/include/hal/gdma_ll.h b/components/hal/esp32p4/include/hal/gdma_ll.h index 17f1b5a15e34..6e463aa781e4 100644 --- a/components/hal/esp32p4/include/hal/gdma_ll.h +++ b/components/hal/esp32p4/include/hal/gdma_ll.h @@ -14,6 +14,7 @@ #include #include "soc/hp_sys_clkrst_struct.h" #include "soc/soc_etm_source.h" +#include "hal/config.h" #define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5] @@ -48,6 +49,10 @@ #define GDMA_LL_AHB_DESC_ALIGNMENT 4 #define GDMA_LL_AXI_DESC_ALIGNMENT 8 +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size +#endif + #define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event) \ (uint32_t[2][GDMA_ETM_EVENT_MAX]){ \ { \ diff --git a/components/hal/esp32p4/include/hal/jpeg_ll.h b/components/hal/esp32p4/include/hal/jpeg_ll.h index 9285576f2ee6..9dea4adfda20 100644 --- a/components/hal/esp32p4/include/hal/jpeg_ll.h +++ b/components/hal/esp32p4/include/hal/jpeg_ll.h @@ -14,6 +14,7 @@ #include "soc/jpeg_struct.h" #include "hal/jpeg_types.h" #include "soc/hp_sys_clkrst_struct.h" +#include "hal/config.h" #ifdef __cplusplus extern "C" { @@ -635,6 +636,11 @@ static inline uint32_t jpeg_ll_get_intr_status(jpeg_dev_t *hw) static inline void jpeg_ll_config_picture_pixel_format(jpeg_dev_t *hw, jpeg_enc_src_type_t pixel_format) { uint8_t cs = 0; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + uint8_t ecs = 0; + // Default, we disable extend color space + hw->extd_config.extd_color_space_en = 0; +#endif switch (pixel_format) { case JPEG_ENC_SRC_RGB888: cs = 0; @@ -648,10 +654,23 @@ static inline void jpeg_ll_config_picture_pixel_format(jpeg_dev_t *hw, jpeg_enc_ case JPEG_ENC_SRC_GRAY: cs = 3; break; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case JPEG_ENC_SRC_YUV444: + hw->extd_config.extd_color_space_en = 1; + ecs = 0; + break; + case JPEG_ENC_SRC_YUV420: + hw->extd_config.extd_color_space_en = 1; + ecs = 1; + break; +#endif default: abort(); } hw->config.color_space = cs; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + hw->extd_config.extd_color_space = ecs; +#endif } #ifdef __cplusplus diff --git a/components/hal/esp32p4/include/hal/lp_clkrst_ll.h b/components/hal/esp32p4/include/hal/lp_clkrst_ll.h new file mode 100644 index 000000000000..68f4b424f2c7 --- /dev/null +++ b/components/hal/esp32p4/include/hal/lp_clkrst_ll.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-P4 LP_CLKRST register operations + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "soc/lp_clkrst_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * Select CPU reset vector + * @param boot_from_lp_ram + * true: boot from LP TCM RAM: 0x50108000 + * false: boot from HP TCM ROM: 0x4FC00000 + */ +__attribute__((always_inline)) +static inline void lp_clkrst_ll_boot_from_lp_ram(bool boot_from_lp_ram) +{ + LP_AON_CLKRST.hpcpu_reset_ctrl0.hpcore0_stat_vector_sel = !boot_from_lp_ram; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/lp_sys_ll.h b/components/hal/esp32p4/include/hal/lp_sys_ll.h index e28a69a67831..4c84b779c27d 100644 --- a/components/hal/esp32p4/include/hal/lp_sys_ll.h +++ b/components/hal/esp32p4/include/hal/lp_sys_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,6 +13,7 @@ #include "soc/soc.h" #include "soc/lp_system_struct.h" #include "hal/misc.h" +#include "hal/config.h" #include "esp32p4/rom/rtc.h" @@ -40,6 +41,11 @@ FORCE_INLINE_ATTR void lp_sys_ll_set_pau_aon_bypass(bool bypass) LP_SYS.backup_dma_cfg1.aon_bypass = bypass ? 1 : 0; } +FORCE_INLINE_ATTR bool lp_sys_ll_get_pau_aon_bypass(void) +{ + return LP_SYS.backup_dma_cfg1.aon_bypass; +} + FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_tout_thres(uint32_t tout) { LP_SYS.backup_dma_cfg0.link_tout_thres_aon = tout; diff --git a/components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h b/components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h index 78979e8453a3..fdeeea34111e 100644 --- a/components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h +++ b/components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,9 +12,16 @@ #include "soc/mipi_dsi_bridge_struct.h" #include "hal/mipi_dsi_types.h" #include "hal/lcd_types.h" +#include "hal/config.h" #define MIPI_DSI_LL_GET_BRG(bus_id) (bus_id == 0 ? &MIPI_DSI_BRIDGE : NULL) -#define MIPI_DSI_LL_EVENT_UNDERRUN (1 << 0) + +#define MIPI_DSI_BRG_LL_EVENT_UNDERRUN (1 << 0) +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +#define MIPI_DSI_BRG_LL_EVENT_VSYNC (1 << 1) +#else +#define MIPI_DSI_BRG_LL_EVENT_VSYNC 0 // not supported +#endif #ifdef __cplusplus extern "C" { @@ -166,53 +173,6 @@ static inline void mipi_dsi_brg_ll_credit_reset(dsi_brg_dev_t *dev) dev->raw_buf_credit_ctl.credit_reset = 1; } -/** - * @brief Set the color coding for the bridge controller - * - * @param dev Pointer to the DSI bridge controller register base address - * @param color_coding Color coding value - * @param sub_config Sub configuration - */ -static inline void mipi_dsi_brg_ll_set_pixel_format(dsi_brg_dev_t *dev, lcd_color_format_t color_coding, uint32_t sub_config) -{ - switch (color_coding) { - case LCD_COLOR_FMT_RGB565: - dev->pixel_type.raw_type = 2; - break; - case LCD_COLOR_FMT_RGB666: - dev->pixel_type.raw_type = 1; - break; - case LCD_COLOR_FMT_RGB888: - dev->pixel_type.raw_type = 0; - break; - default: - // MIPI DSI host can only accept RGB data, no YUV data - HAL_ASSERT(false); - break; - } - dev->pixel_type.dpi_config = sub_config; -} - -/** - * @brief Set the color space for input color data - * - * @param dev Pointer to the DSI bridge controller register base address - * @param color_space Color space type - */ -static inline void mipi_dsi_brg_ll_set_input_color_space(dsi_brg_dev_t *dev, lcd_color_space_t color_space) -{ - switch (color_space) { - case LCD_COLOR_SPACE_RGB: - dev->pixel_type.data_in_type = 0; - break; - case LCD_COLOR_SPACE_YUV: - dev->pixel_type.data_in_type = 1; - break; - default: - abort(); - } -} - /** * @brief Set the vertical timing parameters for the bridge controller * @@ -376,6 +336,161 @@ static inline void mipi_dsi_brg_ll_set_yuv422_pack_order(dsi_brg_dev_t *dev, lcd } } +/**********************************************************************************************************************/ +/************************ The following functions behave differently based on the chip revision ***********************/ +/**********************************************************************************************************************/ + +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +/** + * @brief Set the color format for the input color data + * + * @param dev Pointer to the DSI bridge controller register base address + * @param color_format Color format + */ +static inline void mipi_dsi_brg_ll_set_input_color_format(dsi_brg_dev_t *dev, lcd_color_format_t color_format) +{ + switch (color_format) { + case LCD_COLOR_FMT_RGB888: + dev->pixel_type.raw_type = 0; + dev->pixel_type.data_in_type = 0; + break; + case LCD_COLOR_FMT_RGB666: + dev->pixel_type.raw_type = 1; + dev->pixel_type.data_in_type = 0; + break; + case LCD_COLOR_FMT_RGB565: + dev->pixel_type.raw_type = 2; + dev->pixel_type.data_in_type = 0; + break; + case LCD_COLOR_FMT_YUV422: + dev->pixel_type.raw_type = 9; + dev->pixel_type.data_in_type = 1; + break; + case LCD_COLOR_FMT_GRAY8: + dev->pixel_type.raw_type = 12; + dev->pixel_type.data_in_type = 0; + break; + default: + abort(); + } +} + +/** + * @brief Set the color space for output color data + * + * @param dev Pointer to the DSI bridge controller register base address + * @param color_format Color format + */ +static inline void mipi_dsi_brg_ll_set_output_color_format(dsi_brg_dev_t *dev, lcd_color_format_t color_format, uint32_t sub_config) +{ + switch (color_format) { + case LCD_COLOR_FMT_RGB888: + dev->pixel_type.dpi_type = 0; + break; + case LCD_COLOR_FMT_RGB666: + dev->pixel_type.dpi_type = 1; + break; + case LCD_COLOR_FMT_RGB565: + dev->pixel_type.dpi_type = 2; + break; + default: + abort(); + } + dev->pixel_type.dpi_config = sub_config; +} + +/** + * @brief Reset the DSI bridge module + * + * @param dev Pointer to the DSI bridge controller register base address + */ +static inline void mipi_dsi_brg_ll_reset(dsi_brg_dev_t *dev) +{ + dev->en.dsi_brig_rst = 1; + dev->en.dsi_brig_rst = 0; +} + +/** + * @brief Set the color range of input data + * + * @param dev LCD register base address + * @param range Color range + */ +static inline void mipi_dsi_brg_ll_set_input_color_range(dsi_brg_dev_t *dev, lcd_color_range_t range) +{ + if (range == LCD_COLOR_RANGE_LIMIT) { + dev->yuv_cfg.yuv_range = 0; + } else if (range == LCD_COLOR_RANGE_FULL) { + dev->yuv_cfg.yuv_range = 1; + } +} + +#else + +/** + * @brief Set the color format for the input color data + * + * @param dev Pointer to the DSI bridge controller register base address + * @param color_format Color format + */ +static inline void mipi_dsi_brg_ll_set_input_color_format(dsi_brg_dev_t *dev, lcd_color_format_t color_format) +{ + switch (color_format) { + case LCD_COLOR_FMT_RGB888: + dev->pixel_type.raw_type = 0; + dev->pixel_type.data_in_type = 0; + break; + case LCD_COLOR_FMT_RGB666: + dev->pixel_type.raw_type = 1; + dev->pixel_type.data_in_type = 0; + break; + case LCD_COLOR_FMT_RGB565: + dev->pixel_type.raw_type = 2; + dev->pixel_type.data_in_type = 0; + break; + case LCD_COLOR_FMT_YUV422: + dev->pixel_type.data_in_type = 1; + break; + default: + abort(); + } +} + +/** + * @brief Set the color space for output color data + * + * @param dev Pointer to the DSI bridge controller register base address + * @param color_format Color format + */ +static inline void mipi_dsi_brg_ll_set_output_color_format(dsi_brg_dev_t *dev, lcd_color_format_t color_format, uint32_t sub_config) +{ + switch (color_format) { + case LCD_COLOR_FMT_RGB565: + dev->pixel_type.raw_type = 2; + break; + case LCD_COLOR_FMT_RGB666: + dev->pixel_type.raw_type = 1; + break; + case LCD_COLOR_FMT_RGB888: + dev->pixel_type.raw_type = 0; + break; + default: + abort(); + } + dev->pixel_type.dpi_config = sub_config; +} + +static inline void mipi_dsi_brg_ll_reset(dsi_brg_dev_t *dev) +{ + // Not supported +} + +static inline void mipi_dsi_brg_ll_set_input_color_range(dsi_brg_dev_t *dev, lcd_color_range_t range) +{ + // Not supported +} +#endif + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32p4/include/hal/mipi_dsi_ll.h b/components/hal/esp32p4/include/hal/mipi_dsi_ll.h index 3ea1767a7ce7..ac5fe7cc1e9b 100644 --- a/components/hal/esp32p4/include/hal/mipi_dsi_ll.h +++ b/components/hal/esp32p4/include/hal/mipi_dsi_ll.h @@ -10,6 +10,7 @@ #include #include "soc/hp_sys_clkrst_struct.h" #include "hal/misc.h" +#include "hal/config.h" #include "hal/mipi_dsi_host_ll.h" #include "hal/mipi_dsi_brg_ll.h" #include "hal/mipi_dsi_phy_ll.h" @@ -82,11 +83,14 @@ static inline void mipi_dsi_ll_set_dpi_clock_source(int group_id, mipi_dsi_dpi_c case MIPI_DSI_DPI_CLK_SRC_XTAL: HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 0; break; + case MIPI_DSI_DPI_CLK_SRC_PLL_F240M: + HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 1; + break; case MIPI_DSI_DPI_CLK_SRC_PLL_F160M: HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 2; break; - case MIPI_DSI_DPI_CLK_SRC_PLL_F240M: - HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 1; + case MIPI_DSI_DPI_CLK_SRC_APLL: + HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 3; break; default: abort(); @@ -129,13 +133,44 @@ static inline void mipi_dsi_ll_enable_phy_config_clock(int group_id, bool enable /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance #define mipi_dsi_ll_enable_phy_config_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_enable_phy_config_clock(__VA_ARGS__) +/** + * @brief Set the clock source for the DSI PHY configuration interface + * + * @param group_id Group ID + * @param source Clock source + */ +static inline void _mipi_dsi_ll_set_phy_config_clock_source(int group_id, soc_periph_mipi_dsi_phy_cfg_clk_src_t source) +{ + (void)group_id; + switch (source) { + case MIPI_DSI_PHY_CFG_CLK_SRC_PLL_F20M: + HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 0; + break; + case MIPI_DSI_PHY_CFG_CLK_SRC_RC_FAST: + HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 1; + break; + case MIPI_DSI_PHY_CFG_CLK_SRC_PLL_F25M: + HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 2; + break; + default: + abort(); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define mipi_dsi_ll_set_phy_config_clock_source(...) do { \ + (void)__DECLARE_RCC_ATOMIC_ENV; \ + _mipi_dsi_ll_set_phy_config_clock_source(__VA_ARGS__); \ + } while(0) + /** * @brief Enable MIPI DSI PHY PLL reference clock * * @param group_id Group ID * @param enable true to enable, false to disable */ -static inline void mipi_dsi_ll_enable_phy_reference_clock(int group_id, bool enable) +static inline void mipi_dsi_ll_enable_phy_pllref_clock(int group_id, bool enable) { (void)group_id; HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dphy_pll_refclk_en = enable; @@ -143,25 +178,94 @@ static inline void mipi_dsi_ll_enable_phy_reference_clock(int group_id, bool ena /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define mipi_dsi_ll_enable_phy_reference_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_enable_phy_reference_clock(__VA_ARGS__) +#define mipi_dsi_ll_enable_phy_pllref_clock(...) do { \ + (void)__DECLARE_RCC_ATOMIC_ENV; \ + mipi_dsi_ll_enable_phy_pllref_clock(__VA_ARGS__); \ + } while(0) + +/**********************************************************************************************************************/ +/************************ The following functions behave differently based on the chip revision ***********************/ +/**********************************************************************************************************************/ + +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 /** - * @brief Set the clock source for the DSI PHY interface + * @brief Set the clock source for the DSI PHY PLL reference clock * * @param group_id Group ID * @param source Clock source */ -static inline void mipi_dsi_ll_set_phy_clock_source(int group_id, mipi_dsi_phy_clock_source_t source) +static inline void _mipi_dsi_ll_set_phy_pllref_clock_source(int group_id, mipi_dsi_phy_pllref_clock_source_t source) { (void)group_id; switch (source) { - case MIPI_DSI_PHY_CLK_SRC_PLL_F20M: + case MIPI_DSI_PHY_PLLREF_CLK_SRC_XTAL: + HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dphy_pll_refclk_src_sel = 0; + break; + case MIPI_DSI_PHY_PLLREF_CLK_SRC_APLL: + HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dphy_pll_refclk_src_sel = 1; + break; + case MIPI_DSI_PHY_PLLREF_CLK_SRC_CPLL: + HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dphy_pll_refclk_src_sel = 2; + break; + case MIPI_DSI_PHY_PLLREF_CLK_SRC_SPLL: + HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dphy_pll_refclk_src_sel = 3; + break; + case MIPI_DSI_PHY_PLLREF_CLK_SRC_MPLL: + HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dphy_pll_refclk_src_sel = 4; + break; + default: + abort(); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define mipi_dsi_ll_set_phy_pllref_clock_source(...) do { \ + (void)__DECLARE_RCC_ATOMIC_ENV; \ + _mipi_dsi_ll_set_phy_pllref_clock_source(__VA_ARGS__); \ + } while(0) + +/** + * @brief Set the clock division factor for the DSI PHY clock source + * + * @param group_id Group ID + * @param div Division factor + */ +static inline void _mipi_dsi_ll_set_phy_pll_ref_clock_div(int group_id, uint32_t div) +{ + (void) group_id; + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl03, reg_mipi_dsi_dphy_pll_refclk_div_num, div - 1); +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define mipi_dsi_ll_set_phy_pll_ref_clock_div(...) do { \ + (void)__DECLARE_RCC_ATOMIC_ENV; \ + _mipi_dsi_ll_set_phy_pll_ref_clock_div(__VA_ARGS__);\ + } while (0) + +#else + +/** + * @brief Set the clock source for the DSI PHY PLL reference clock + * + * @note The PHY PLL reference clock source is same as PHY configuration clock source + * + * @param group_id Group ID + * @param source Clock source + */ +static inline void _mipi_dsi_ll_set_phy_pllref_clock_source(int group_id, mipi_dsi_phy_pllref_clock_source_t source) +{ + (void)group_id; + switch (source) { + case MIPI_DSI_PHY_PLLREF_CLK_SRC_PLL_F20M: HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 0; break; - case MIPI_DSI_PHY_CLK_SRC_RC_FAST: + case MIPI_DSI_PHY_PLLREF_CLK_SRC_RC_FAST: HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 1; break; - case MIPI_DSI_PHY_CLK_SRC_PLL_F25M: + case MIPI_DSI_PHY_PLLREF_CLK_SRC_PLL_F25M: HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 2; break; default: @@ -171,7 +275,19 @@ static inline void mipi_dsi_ll_set_phy_clock_source(int group_id, mipi_dsi_phy_c /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define mipi_dsi_ll_set_phy_clock_source(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_set_phy_clock_source(__VA_ARGS__) +#define mipi_dsi_ll_set_phy_pllref_clock_source(...) do { \ + (void)__DECLARE_RCC_ATOMIC_ENV; \ + _mipi_dsi_ll_set_phy_pllref_clock_source(__VA_ARGS__); \ + } while(0) + +static inline void mipi_dsi_ll_set_phy_pll_ref_clock_div(int group_id, uint32_t div) +{ + // not supported + (void)group_id; + (void)div; +} + +#endif #ifdef __cplusplus } diff --git a/components/hal/esp32p4/include/hal/mspi_timing_tuning_ll.h b/components/hal/esp32p4/include/hal/mspi_timing_tuning_ll.h index 6b84ef3c263b..848bc5ea86fa 100644 --- a/components/hal/esp32p4/include/hal/mspi_timing_tuning_ll.h +++ b/components/hal/esp32p4/include/hal/mspi_timing_tuning_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -86,6 +86,17 @@ static inline void _mspi_timing_ll_reset_mspi(void) /// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance #define mspi_timing_ll_reset_mspi(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _mspi_timing_ll_reset_mspi(__VA_ARGS__) +__attribute__((always_inline)) +static inline void _mspi_timing_ll_reset_mspi_apb(void) +{ + REG_SET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_APB); + REG_CLR_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_APB); +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define mspi_timing_ll_reset_mspi_apb(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _mspi_timing_ll_reset_mspi_apb(__VA_ARGS__) + /** * Set all MSPI DQS phase * diff --git a/components/hal/esp32p4/include/hal/pmu_ll.h b/components/hal/esp32p4/include/hal/pmu_ll.h index 599dcbb79a83..49d4aba9bc2e 100644 --- a/components/hal/esp32p4/include/hal/pmu_ll.h +++ b/components/hal/esp32p4/include/hal/pmu_ll.h @@ -379,32 +379,68 @@ FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_pad_hold_all(pmu_dev_t *hw, bool hold_a FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool rst) { - hw->power.hp_pd[domain].force_reset = rst; + if (domain == PMU_HP_PD_CPU) { +#if SOC_PMU_STRUCT_HW_VER >= 3 + hw->power_pd_hp_cpu_cntl.force_hp_cpu_reset = rst; +#endif + } else { + hw->power.hp_pd[domain].force_reset = rst; + } } FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool iso) { - hw->power.hp_pd[domain].force_iso = iso; + if (domain == PMU_HP_PD_CPU) { +#if SOC_PMU_STRUCT_HW_VER >= 3 + hw->power_pd_hp_cpu_cntl.force_hp_cpu_iso = iso; +#endif + } else { + hw->power.hp_pd[domain].force_iso = iso; + } } FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_up(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpu) { - hw->power.hp_pd[domain].force_pu = fpu; + if (domain == PMU_HP_PD_CPU) { +#if SOC_PMU_STRUCT_HW_VER >= 3 + hw->power_pd_hp_cpu_cntl.force_hp_cpu_pu = fpu; +#endif + } else { + hw->power.hp_pd[domain].force_pu = fpu; + } } FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_rst) { - hw->power.hp_pd[domain].force_no_reset = no_rst; + if (domain == PMU_HP_PD_CPU) { +#if SOC_PMU_STRUCT_HW_VER >= 3 + hw->power_pd_hp_cpu_cntl.force_hp_cpu_no_reset = no_rst; +#endif + } else { + hw->power.hp_pd[domain].force_no_reset = no_rst; + } } FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_iso) { - hw->power.hp_pd[domain].force_no_iso = no_iso; + if (domain == PMU_HP_PD_CPU) { +#if SOC_PMU_STRUCT_HW_VER >= 3 + hw->power_pd_hp_cpu_cntl.force_hp_cpu_no_iso = no_iso; +#endif + } else { + hw->power.hp_pd[domain].force_no_iso = no_iso; + } } FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_down(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpd) { - hw->power.hp_pd[domain].force_pd = fpd; + if (domain == PMU_HP_PD_CPU) { +#if SOC_PMU_STRUCT_HW_VER >= 3 + hw->power_pd_hp_cpu_cntl.force_hp_cpu_pd = fpd; +#endif + } else { + hw->power.hp_pd[domain].force_pd = fpd; + } } FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_reset(pmu_dev_t *hw, bool rst) @@ -638,9 +674,9 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_analog_wait_target_cycle(pmu_dev_t *hw) return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target); } -FORCE_INLINE_ATTR uint32_t pmu_ll_hp_set_lite_wakeup_enable(pmu_dev_t *hw, bool wakeup_en) +FORCE_INLINE_ATTR void pmu_ll_hp_set_lite_wakeup_enable(pmu_dev_t *hw, bool wakeup_en) { - return hw->wakeup.cntl8.lp_lite_wakeup_ena = wakeup_en; + hw->wakeup.cntl8.lp_lite_wakeup_ena = wakeup_en; } FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle) diff --git a/components/hal/esp32p4/include/hal/touch_sensor_ll.h b/components/hal/esp32p4/include/hal/touch_sensor_ll.h index 5d47aa137ec3..cc0339d5c8d2 100644 --- a/components/hal/esp32p4/include/hal/touch_sensor_ll.h +++ b/components/hal/esp32p4/include/hal/touch_sensor_ll.h @@ -482,11 +482,7 @@ static inline void touch_ll_set_idle_channel_connect(touch_pad_conn_type_t type) __attribute__((always_inline)) static inline uint32_t touch_ll_get_current_meas_channel(void) { - uint32_t curr_chan = LP_TOUCH.chn_status.scan_curr; - HAL_ASSERT(curr_chan < 14); - // Workaround: the curr channel read 0 when the actual channel is 14 - curr_chan = curr_chan == 0 ? 14 : curr_chan; - return curr_chan; + return LP_TOUCH.chn_status.scan_curr; } /** diff --git a/components/hal/esp32p4/include/hal/usb_dwc_ll.h b/components/hal/esp32p4/include/hal/usb_dwc_ll.h index 6760db563731..1ee7334a749a 100644 --- a/components/hal/esp32p4/include/hal/usb_dwc_ll.h +++ b/components/hal/esp32p4/include/hal/usb_dwc_ll.h @@ -28,7 +28,8 @@ extern "C" { ----------------------------------------------------------------------------- */ #define USB_DWC_QTD_LIST_MEM_ALIGN 512 -#define USB_DWC_FRAME_LIST_MEM_ALIGN 512 // The frame list needs to be 512 bytes aligned (contrary to the databook) +#define USB_DWC_FRAME_LIST_MEM_ALIGN 512 // The frame list needs to be 512 bytes aligned (contrary to the databook) +#define USB_DWC_CORE_REG_GSNPSID_4_20a 0x4F54420A // From 4.20a upward, the reset sequence is changed /* ----------------------------------------------------------------------------- ------------------------------- Global Registers ------------------------------- @@ -279,12 +280,28 @@ static inline void usb_dwc_ll_grstctl_reset_frame_counter(usb_dwc_dev_t *hw) static inline void usb_dwc_ll_grstctl_core_soft_reset(usb_dwc_dev_t *hw) { + const uint32_t gnspsid = hw->gsnpsid_reg.val; + + // Start core soft reset hw->grstctl_reg.csftrst = 1; -} -static inline bool usb_dwc_ll_grstctl_is_core_soft_reset_in_progress(usb_dwc_dev_t *hw) -{ - return hw->grstctl_reg.csftrst; + // Wait for the reset to complete + if (gnspsid < USB_DWC_CORE_REG_GSNPSID_4_20a) { + // Version < 4.20a + while (hw->grstctl_reg.csftrst) { + ; + } + } else { + // Version >= 4.20a + while (!(hw->grstctl_reg.csftrstdone)) { + ; + } + usb_dwc_grstctl_reg_t grstctl; + grstctl.val = hw->grstctl_reg.val; + grstctl.csftrst = 0; // Clear RESET bit once reset is done + grstctl.csftrstdone = 1; // Write 1 to clear RESET_DONE bit + hw->grstctl_reg.val = grstctl.val; + } } // --------------------------- GINTSTS Register -------------------------------- @@ -1011,6 +1028,28 @@ static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem qtd->buffer_status_val = 0; } +/** + * @brief Get the current BVALID override configuration. + * + * @param[out] Get the current BVALID override configuration. + */ +FORCE_INLINE_ATTR bool usb_dwc_ll_get_bvalid_override(usb_dwc_dev_t *hw) +{ + return hw->gotgctl_reg.bvalidoven; +} + +/** + * @brief Enable BVALID override in USB OTG controller. + * + * When enabled, the controller ignores the hardware-detected VBUS BVALID signal + * and uses the software-defined override value instead. This is typically used + * to reduce USB leakage current during sleep by forcing BVALID low. + */ +FORCE_INLINE_ATTR void usb_dwc_ll_enable_bvalid_override(usb_dwc_dev_t *hw, bool override) +{ + hw->gotgctl_reg.bvalidoven = override; +} + // ---------------------------- Power and Clock Gating Register -------------------------------- FORCE_INLINE_ATTR void usb_dwc_ll_set_stoppclk(usb_dwc_dev_t *hw, bool stop) { diff --git a/components/hal/esp32s2/include/hal/usb_dwc_ll.h b/components/hal/esp32s2/include/hal/usb_dwc_ll.h index 27859e5ef7ce..d3eef71367be 100644 --- a/components/hal/esp32s2/include/hal/usb_dwc_ll.h +++ b/components/hal/esp32s2/include/hal/usb_dwc_ll.h @@ -274,11 +274,9 @@ static inline void usb_dwc_ll_grstctl_reset_frame_counter(usb_dwc_dev_t *hw) static inline void usb_dwc_ll_grstctl_core_soft_reset(usb_dwc_dev_t *hw) { hw->grstctl_reg.csftrst = 1; -} - -static inline bool usb_dwc_ll_grstctl_is_core_soft_reset_in_progress(usb_dwc_dev_t *hw) -{ - return hw->grstctl_reg.csftrst; + while (hw->grstctl_reg.csftrst) { + ; + } } // --------------------------- GINTSTS Register -------------------------------- diff --git a/components/hal/esp32s3/include/hal/usb_dwc_ll.h b/components/hal/esp32s3/include/hal/usb_dwc_ll.h index fc5edff0bdbd..32f7469a3e35 100644 --- a/components/hal/esp32s3/include/hal/usb_dwc_ll.h +++ b/components/hal/esp32s3/include/hal/usb_dwc_ll.h @@ -274,11 +274,9 @@ static inline void usb_dwc_ll_grstctl_reset_frame_counter(usb_dwc_dev_t *hw) static inline void usb_dwc_ll_grstctl_core_soft_reset(usb_dwc_dev_t *hw) { hw->grstctl_reg.csftrst = 1; -} - -static inline bool usb_dwc_ll_grstctl_is_core_soft_reset_in_progress(usb_dwc_dev_t *hw) -{ - return hw->grstctl_reg.csftrst; + while (hw->grstctl_reg.csftrst) { + ; + } } // --------------------------- GINTSTS Register -------------------------------- diff --git a/components/hal/include/hal/jpeg_types.h b/components/hal/include/hal/jpeg_types.h index a8a833cdf94a..d34c69d8da95 100644 --- a/components/hal/include/hal/jpeg_types.h +++ b/components/hal/include/hal/jpeg_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -78,6 +78,8 @@ typedef enum { JPEG_ENC_SRC_RGB888 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB888), /*!< JPEG encoder source RGB888 */ JPEG_ENC_SRC_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< JPEG encoder source YUV422 */ JPEG_ENC_SRC_RGB565 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565), /*!< JPEG encoder source RGB565 */ + JPEG_ENC_SRC_YUV444 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV444), /*!< JPEG encoder source YUV444 */ + JPEG_ENC_SRC_YUV420 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV420), /*!< JPEG encoder source YUV420 */ JPEG_ENC_SRC_GRAY = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< JPEG encoder source GRAY */ } jpeg_enc_src_type_t; diff --git a/components/hal/include/hal/lcd_types.h b/components/hal/include/hal/lcd_types.h index 5fbdb1aea27f..7428f2da8b67 100644 --- a/components/hal/include/hal/lcd_types.h +++ b/components/hal/include/hal/lcd_types.h @@ -56,6 +56,7 @@ typedef enum { LCD_COLOR_FMT_RGB666 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB666), ///< RGB666 LCD_COLOR_FMT_RGB888 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB888), ///< RGB888 LCD_COLOR_FMT_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), ///< YUV422 + LCD_COLOR_FMT_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), ///< 8-bit gray scale } lcd_color_format_t; /** diff --git a/components/hal/include/hal/mipi_dsi_hal.h b/components/hal/include/hal/mipi_dsi_hal.h index e3e43b2b3bbb..d7f3737f523c 100644 --- a/components/hal/include/hal/mipi_dsi_hal.h +++ b/components/hal/include/hal/mipi_dsi_hal.h @@ -143,15 +143,6 @@ void mipi_dsi_hal_host_gen_write_short_packet(mipi_dsi_hal_context_t *hal, uint8 void mipi_dsi_hal_host_gen_read_short_packet(mipi_dsi_hal_context_t *hal, uint8_t vc, mipi_dsi_data_type_t dt, uint16_t header_data, void *ret_buffer, uint16_t buffer_size); -/** - * @brief Set DPI color coding - * - * @param hal Pointer to the HAL driver context - * @param color_coding Color coding - * @param sub_config Sub configuration - */ -void mipi_dsi_hal_host_dpi_set_color_coding(mipi_dsi_hal_context_t *hal, lcd_color_format_t color_coding, uint32_t sub_config); - /** * @brief Set horizontal timing parameters for DPI * diff --git a/components/hal/include/hal/mipi_dsi_types.h b/components/hal/include/hal/mipi_dsi_types.h index 8c2a880a7ea4..3d5078bd4b87 100644 --- a/components/hal/include/hal/mipi_dsi_types.h +++ b/components/hal/include/hal/mipi_dsi_types.h @@ -9,6 +9,7 @@ #include #include "soc/clk_tree_defs.h" #include "esp_assert.h" +#include "soc/soc_caps.h" #ifdef __cplusplus extern "C" { @@ -58,17 +59,25 @@ typedef enum { } mipi_dsi_pattern_type_t; #if SOC_MIPI_DSI_SUPPORTED + /** - * @brief MIPI DSI PHY clock source + * @brief MIPI DSI PHY PLL reference clock source */ -typedef soc_periph_mipi_dsi_phy_clk_src_t mipi_dsi_phy_clock_source_t; +typedef soc_periph_mipi_dsi_phy_pllref_clk_src_t mipi_dsi_phy_pllref_clock_source_t; /** * @brief MIPI DSI DPI clock source */ typedef soc_periph_mipi_dsi_dpi_clk_src_t mipi_dsi_dpi_clock_source_t; + +/** + * @brief For backward compatibility + */ +typedef mipi_dsi_phy_pllref_clock_source_t mipi_dsi_phy_clock_source_t; + #else -typedef int mipi_dsi_phy_clock_source_t; + +typedef int mipi_dsi_phy_pllref_clock_source_t; typedef int mipi_dsi_dpi_clock_source_t; #endif // SOC_MIPI_DSI_SUPPORTED diff --git a/components/hal/include/hal/pmu_types.h b/components/hal/include/hal/pmu_types.h index cb1fab415e99..a0f2aa12c176 100644 --- a/components/hal/include/hal/pmu_types.h +++ b/components/hal/include/hal/pmu_types.h @@ -41,6 +41,7 @@ typedef enum { PMU_HP_PD_TOP = 0, /*!< Power domain of digital top */ PMU_HP_PD_CNNT = 1, /*!< Power domain of high-speed IO peripherals such as USB/SDIO/Ethernet etc.*/ PMU_HP_PD_HPMEM = 2, + PMU_HP_PD_CPU = 3, } pmu_hp_power_domain_t; #else typedef enum { diff --git a/components/hal/mipi_dsi_hal.c b/components/hal/mipi_dsi_hal.c index 9ca4b6f71e47..8e57fab19100 100644 --- a/components/hal/mipi_dsi_hal.c +++ b/components/hal/mipi_dsi_hal.c @@ -25,6 +25,8 @@ void mipi_dsi_hal_init(mipi_dsi_hal_context_t *hal, const mipi_dsi_hal_config_t mipi_dsi_phy_ll_reset(hal->host); mipi_dsi_phy_ll_enable_clock_lane(hal->host, true); mipi_dsi_phy_ll_force_pll(hal->host, true); + // reset the dsi bridge + mipi_dsi_brg_ll_reset(hal->bridge); } void mipi_dsi_hal_deinit(mipi_dsi_hal_context_t *hal) @@ -227,12 +229,6 @@ void mipi_dsi_hal_host_gen_read_dcs_command(mipi_dsi_hal_context_t *hal, uint8_t mipi_dsi_hal_host_gen_read_short_packet(hal, vc, MIPI_DSI_DT_DCS_READ_0, header_data, ret_param, param_buf_size); } -void mipi_dsi_hal_host_dpi_set_color_coding(mipi_dsi_hal_context_t *hal, lcd_color_format_t color_coding, uint32_t sub_config) -{ - mipi_dsi_host_ll_dpi_set_color_coding(hal->host, color_coding, sub_config); - mipi_dsi_brg_ll_set_pixel_format(hal->bridge, color_coding, sub_config); -} - void mipi_dsi_hal_host_dpi_set_horizontal_timing(mipi_dsi_hal_context_t *hal, uint32_t hsw, uint32_t hbp, uint32_t active_width, uint32_t hfp) { float dpi2lane_clk_ratio = (float)hal->lane_bit_rate_mbps / hal->dpi_clock_freq_mhz / 8; diff --git a/components/hal/platform_port/include/hal/config.h b/components/hal/platform_port/include/hal/config.h new file mode 100644 index 000000000000..aa0ae895f9a5 --- /dev/null +++ b/components/hal/platform_port/include/hal/config.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Macro to access HAL configuration options. + * + * This macro is used to access various HAL configuration options defined in config.h + * It should be used instead of directly accessing the HAL_CONFIG_ prefixed options. + * + * @param x The configuration option to access, without the HAL_CONFIG_ prefix. + */ +#define HAL_CONFIG(x) HAL_CONFIG_##x + +/** + * @brief The minimum supported chip revision. + */ +#define HAL_CONFIG_CHIP_SUPPORT_MIN_REV CONFIG_ESP_REV_MIN_FULL + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/usb_dwc_hal.c b/components/hal/usb_dwc_hal.c index 96b26d33b92e..ed646682b315 100644 --- a/components/hal/usb_dwc_hal.c +++ b/components/hal/usb_dwc_hal.c @@ -23,7 +23,9 @@ #define BENDPOINTADDRESS_NUM_MSK 0x0F //Endpoint number mask of the bEndpointAddress field of an endpoint descriptor #define BENDPOINTADDRESS_DIR_MSK 0x80 //Endpoint direction mask of the bEndpointAddress field of an endpoint descriptor -#define CORE_REG_GSNPSID 0x4F54400A //Release number of USB_DWC used in Espressif's SoCs +// Core register IDs supported by this driver: v4.00a and v4.30a +#define CORE_REG_GSNPSID_4_00a 0x4F54400A +#define CORE_REG_GSNPSID_4_30a 0x4F54430A // -------------------- Configurable ----------------------- @@ -131,7 +133,7 @@ void usb_dwc_hal_init(usb_dwc_hal_context_t *hal, int port_id) HAL_ASSERT(port_id < SOC_USB_OTG_PERIPH_NUM); usb_dwc_dev_t *dev = USB_DWC_LL_GET_HW(port_id); uint32_t core_id = usb_dwc_ll_gsnpsid_get_id(dev); - HAL_ASSERT(core_id == CORE_REG_GSNPSID); + HAL_ASSERT(core_id == CORE_REG_GSNPSID_4_00a || core_id == CORE_REG_GSNPSID_4_30a); (void) core_id; //Suppress unused variable warning if asserts are disabled // Initialize HAL context @@ -163,9 +165,6 @@ void usb_dwc_hal_deinit(usb_dwc_hal_context_t *hal) void usb_dwc_hal_core_soft_reset(usb_dwc_hal_context_t *hal) { usb_dwc_ll_grstctl_core_soft_reset(hal->dev); - while (usb_dwc_ll_grstctl_is_core_soft_reset_in_progress(hal->dev)) { - ; // Wait until core reset is done - } while (!usb_dwc_ll_grstctl_is_ahb_idle(hal->dev)) { ; // Wait until AHB Master bus is idle before doing any other operations } diff --git a/components/heap/port/esp32p4/memory_layout.c b/components/heap/port/esp32p4/memory_layout.c index dadd34a75560..31df537b4e4e 100644 --- a/components/heap/port/esp32p4/memory_layout.c +++ b/components/heap/port/esp32p4/memory_layout.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -26,10 +26,18 @@ /* Index of memory in `soc_memory_types[]` */ enum { - SOC_MEMORY_TYPE_L2MEM = 0, - SOC_MEMORY_TYPE_SPIRAM = 1, - SOC_MEMORY_TYPE_TCM = 2, - SOC_MEMORY_TYPE_RTCRAM = 3, + SOC_MEMORY_TYPE_L2MEM = 0, + /** + * The L2 memory that regdma can access regardless of the l2 cache size. After PD_TOP sleep, the cache + * occupancy MEM configuration is reset, regdma allocates linked list memory from here to avoid being + * unable to access the linked list memory occupied by cache after reset. + * For esp32p4 chips with version < V3.0, the hardware default size of the L2 Cache is 256KB. + * For esp32p4 chips with version >= V3.0, the hardware default size of the L2 Cache is 128KB. + */ + SOC_MEMORY_TYPE_RETENT_MEM = 1, + SOC_MEMORY_TYPE_SPIRAM = 2, + SOC_MEMORY_TYPE_TCM = 3, + SOC_MEMORY_TYPE_RTCRAM = 4, SOC_MEMORY_TYPE_NUM, }; @@ -54,11 +62,12 @@ enum { * in turn to continue matching. */ const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { - /* Mem Type Name | High Priority Matching | Medium Priority Matching | Low Priority Matching */ - [SOC_MEMORY_TYPE_L2MEM] = { "RAM", { MALLOC_L2MEM_BASE_CAPS | MALLOC_CAP_SIMD, 0, 0 }}, - [SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM, 0, ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_SIMD }}, - [SOC_MEMORY_TYPE_TCM] = { "TCM", { MALLOC_CAP_TCM, ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL, 0 }}, - [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, 0, MALLOC_RTCRAM_BASE_CAPS}}, + /* Mem Type Name | High Priority Matching | Medium Priority Matching | Low Priority Matching */ + [SOC_MEMORY_TYPE_RETENT_MEM] = { "RETENT_RAM", { MALLOC_L2MEM_BASE_CAPS | MALLOC_CAP_RETENTION | MALLOC_CAP_SIMD, 0, 0 }}, + [SOC_MEMORY_TYPE_L2MEM] = { "RAM", { MALLOC_L2MEM_BASE_CAPS | MALLOC_CAP_SIMD, 0, 0 }}, + [SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM, 0, ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_SIMD }}, + [SOC_MEMORY_TYPE_TCM] = { "TCM", { MALLOC_CAP_TCM, ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL, 0 }}, + [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, 0, MALLOC_RTCRAM_BASE_CAPS}}, }; const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); @@ -74,8 +83,19 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor /** * Register the shared buffer area of the last memory block into the heap during heap initialization */ -#define APP_USABLE_DIRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) // 0x4ff3cfc0 - 0x2000 = 0x4ff3afc0 -#define STARTUP_DATA_SIZE (SOC_DRAM_HIGH - CONFIG_CACHE_L2_CACHE_SIZE - APP_USABLE_DIRAM_END) // 0x4ffc0000 - 0x20000/0x40000/0x80000 - 0x4ff3afc0 = 0x65040 / 0x45040 / 0x5040 +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 +#define ROM_STACK_START (SOC_ROM_STACK_START) +#define APP_USABLE_DIRAM_END (ROM_STACK_START - SOC_ROM_STACK_SIZE) // 0x4ff3cfc0 - 0x2000 = 0x4ff3afc0 +#define STARTUP_DATA_SIZE (SOC_DRAM_HIGH - CONFIG_CACHE_L2_CACHE_SIZE - APP_USABLE_DIRAM_END) // 0x4ffc0000 - 0x20000/0x40000/0x80000 - 0x4ff3afc0 = 0x65040 / 0x45040 / 0x5040 +#define SOC_DRAM_USABLE_LOW (SOC_DRAM_LOW) +#define SOC_IRAM_USABLE_LOW (SOC_IRAM_LOW) +#else +#define ROM_STACK_START (SOC_ROM_STACK_START_REV2) +#define APP_USABLE_DIRAM_END (ROM_STACK_START - SOC_ROM_STACK_SIZE) // 0x4ffbcfc0 - 0x2000 = 0x4ffbafc0 +#define STARTUP_DATA_SIZE (SOC_DRAM_HIGH - APP_USABLE_DIRAM_END) // 0x4ffc0000 - 0x4ffbafc0 = 0x65040 / 0x45040 / 0x5040 +#define SOC_DRAM_USABLE_LOW (SOC_DRAM_LOW + CONFIG_CACHE_L2_CACHE_SIZE) +#define SOC_IRAM_USABLE_LOW (SOC_IRAM_LOW + CONFIG_CACHE_L2_CACHE_SIZE) +#endif #if CONFIG_ULP_COPROC_ENABLED #define APP_USABLE_LP_RAM_SIZE 0x8000 - LP_ROM_DRAM_SIZE @@ -85,20 +105,26 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor const soc_memory_region_t soc_memory_regions[] = { #ifdef CONFIG_SPIRAM - { SOC_EXTRAM_LOW, SOC_EXTRAM_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0, false}, //PSRAM, if available + { SOC_EXTRAM_LOW, SOC_EXTRAM_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0, false}, //PSRAM, if available #endif - { SOC_DRAM_LOW, APP_USABLE_DIRAM_END - SOC_DRAM_LOW, SOC_MEMORY_TYPE_L2MEM, SOC_IRAM_LOW, false}, - { APP_USABLE_DIRAM_END, STARTUP_DATA_SIZE, SOC_MEMORY_TYPE_L2MEM, APP_USABLE_DIRAM_END, true}, + { SOC_DRAM_USABLE_LOW, APP_USABLE_DIRAM_END - SOC_DRAM_USABLE_LOW, SOC_MEMORY_TYPE_RETENT_MEM, SOC_IRAM_USABLE_LOW, false}, + { APP_USABLE_DIRAM_END, STARTUP_DATA_SIZE, SOC_MEMORY_TYPE_L2MEM, APP_USABLE_DIRAM_END, true}, #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP - { 0x50108000, APP_USABLE_LP_RAM_SIZE, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM + { 0x50108000, APP_USABLE_LP_RAM_SIZE, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM #endif - { 0x30100000, 0x2000, SOC_MEMORY_TYPE_TCM, 0, false}, + { 0x30100000, 0x2000, SOC_MEMORY_TYPE_TCM, 0, false}, }; const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); - +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 extern int _data_start_low, _data_start_high, _heap_start_low, _heap_start_high, _iram_start, _iram_end, _rtc_force_slow_end; +#else +extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end; +#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND +extern int _rtc_p4_rev3_mspi_workaround_start, _rtc_p4_rev3_mspi_workaround_end; +#endif +#endif extern int _tcm_text_start, _tcm_data_end; extern int _rtc_reserved_start, _rtc_reserved_end; extern int _rtc_ulp_memory_start; @@ -110,8 +136,12 @@ extern int _rtc_ulp_memory_start; */ // Static data region. DRAM used by data+bss and possibly rodata +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start_low, (intptr_t)&_heap_start_low, dram_data_low); SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start_high, (intptr_t)&_heap_start_high, dram_data_high); +#else +SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data_high) +#endif // Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code); @@ -127,5 +157,7 @@ SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_LOW, SOC_EXTRAM_HIGH, extram_region); SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data); /* This includes any memory reserved for ULP RAM */ SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_end, (intptr_t)&_rtc_force_slow_end, rtcram_data); - +#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND +SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_p4_rev3_mspi_workaround_start, (intptr_t)&_rtc_p4_rev3_mspi_workaround_end, p4_rev3_mspi_workaround); +#endif #endif diff --git a/components/heap/port/memory_layout_utils.c b/components/heap/port/memory_layout_utils.c index 3de9f6db22a5..0c5af3bb13de 100644 --- a/components/heap/port/memory_layout_utils.c +++ b/components/heap/port/memory_layout_utils.c @@ -75,7 +75,7 @@ static void s_prepare_reserved_regions(soc_reserved_region_t *reserved, size_t c /* Get the ROM layout to find which part of DRAM is reserved */ const ets_rom_layout_t *layout = ets_rom_layout_p; reserved[0].start = (intptr_t)layout->dram0_rtos_reserved_start; -#ifdef SOC_DIRAM_ROM_RESERVE_HIGH +#if SOC_DIRAM_ROM_RESERVE_HIGH && CONFIG_ESP32P4_SELECTS_REV_LESS_V3 reserved[0].end = SOC_DIRAM_ROM_RESERVE_HIGH; #else reserved[0].end = SOC_DIRAM_DRAM_HIGH; diff --git a/components/ieee802154/Kconfig b/components/ieee802154/Kconfig index 5d0b46666d2a..54e7229affe9 100644 --- a/components/ieee802154/Kconfig +++ b/components/ieee802154/Kconfig @@ -53,9 +53,9 @@ menu "IEEE 802.15.4" int "CCA detection threshold" depends on IEEE802154_ENABLED range -120 0 - default -60 + default -75 help - set the CCA threshold, in dB + set the CCA threshold, in dBm config IEEE802154_PENDING_TABLE_SIZE int "Pending table size" diff --git a/components/openthread/CMakeLists.txt b/components/openthread/CMakeLists.txt index dc3938e76f19..54e8f99d8a68 100644 --- a/components/openthread/CMakeLists.txt +++ b/components/openthread/CMakeLists.txt @@ -113,6 +113,7 @@ if(CONFIG_OPENTHREAD_ENABLED) "openthread/src/core/thread/mesh_forwarder.cpp" "openthread/src/core/thread/mesh_forwarder_ftd.cpp" "openthread/src/core/thread/mesh_forwarder_mtd.cpp" + "openthread/src/core/thread/message_framer.cpp" "openthread/src/core/thread/mle.cpp" "openthread/src/core/thread/mle_router.cpp" "openthread/src/core/thread/mle_types.cpp" diff --git a/components/openthread/Kconfig b/components/openthread/Kconfig index 7d7c0ff0ab12..b113cfd1f4c0 100644 --- a/components/openthread/Kconfig +++ b/components/openthread/Kconfig @@ -6,6 +6,28 @@ menu "OpenThread" help Select this option to enable OpenThread and show the submenu with OpenThread configuration choices. + menu "Thread Task Parameters" + depends on OPENTHREAD_ENABLED + + config OPENTHREAD_TASK_NAME + string "OpenThread task name" + default "ot_main" + help + The OpenThread task name. + + config OPENTHREAD_TASK_SIZE + int "Size of OpenThread task" + default 8192 + help + The size in bytes of OpenThread task. + + config OPENTHREAD_TASK_PRIORITY + int "Priority of OpenThread task" + default 5 + help + The priority of OpenThread task. + endmenu + menu "Thread Version Message" depends on OPENTHREAD_ENABLED @@ -23,10 +45,18 @@ menu "OpenThread" endmenu menu "Thread Console" - depends on OPENTHREAD_ENABLED + config OPENTHREAD_CONSOLE_ENABLE + bool "Enable OpenThread console" + depends on OPENTHREAD_ENABLED + default y + help + Enable the OpenThread-specific console provided by the SDK. This only controls whether + the SDK sets up a dedicated console for OpenThread. Even if disabled, the default + ESP-IDF console (if initialized elsewhere) can still be used independently. choice OPENTHREAD_CONSOLE_TYPE prompt "OpenThread console type" + depends on OPENTHREAD_CONSOLE_ENABLE default OPENTHREAD_CONSOLE_TYPE_UART help Select OpenThread console type @@ -277,10 +307,17 @@ menu "OpenThread" Set the DNS server IPv4 address. endmenu + config OPENTHREAD_TIMING_OPTIMIZATION + bool "Enable timing optimization" + default n + help + Select this option to enable timing optimization for link metrics / CSL features. + config OPENTHREAD_LINK_METRICS bool "Enable link metrics feature" default n select IEEE802154_TIMING_OPTIMIZATION if IEEE802154_ENABLED + select OPENTHREAD_TIMING_OPTIMIZATION help Select this option to enable link metrics feature @@ -301,6 +338,7 @@ menu "OpenThread" bool "Enable CSL feature" default n select IEEE802154_TIMING_OPTIMIZATION if IEEE802154_ENABLED + select OPENTHREAD_TIMING_OPTIMIZATION help Select this option to enable CSL feature menu "CSL Configurations" diff --git a/components/openthread/include/esp_openthread.h b/components/openthread/include/esp_openthread.h index a3f0528f935d..7ce38a58844e 100644 --- a/components/openthread/include/esp_openthread.h +++ b/components/openthread/include/esp_openthread.h @@ -7,6 +7,7 @@ #pragma once #include "esp_err.h" +#include "esp_netif.h" #include "esp_openthread_types.h" #include "openthread/dataset.h" #include "openthread/error.h" @@ -89,6 +90,29 @@ otInstance *esp_openthread_get_instance(void); */ esp_err_t esp_openthread_mainloop_exit(void); +/** + * @brief Starts the full OpenThread stack and create a handle task. + * + * @note The OpenThread instance will also be initialized in this function. + * + * @param[in] config The OpenThread platform configuration. + * + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_STATE if already initialized + * + */ +esp_err_t esp_openthread_start(const esp_openthread_config_t *config); + +/** + * @brief This function performs OpenThread stack and platform driver deinitialization and delete the handle task. + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_STATE if Thread is already active + * + */ +esp_err_t esp_openthread_stop(void); + #ifdef __cplusplus } // end of extern "C" #endif diff --git a/components/openthread/include/esp_openthread_types.h b/components/openthread/include/esp_openthread_types.h index c5f4f4cba672..e384603b7366 100644 --- a/components/openthread/include/esp_openthread_types.h +++ b/components/openthread/include/esp_openthread_types.h @@ -11,6 +11,7 @@ #include #include "esp_event_base.h" +#include "esp_netif_types.h" #include "driver/gpio.h" #include "driver/spi_master.h" #include "driver/spi_slave.h" @@ -199,6 +200,15 @@ typedef struct { esp_openthread_port_config_t port_config; /*!< The port configuration */ } esp_openthread_platform_config_t; +/** + * @brief The OpenThread configuration + * + */ +typedef struct { + esp_netif_config_t netif_config; /*!< The netif configuration */ + esp_openthread_platform_config_t platform_config; /*!< The platform configuration */ +} esp_openthread_config_t; + /** * @brief The OpenThread rcp failure handler * diff --git a/components/openthread/include/esp_radio_spinel.h b/components/openthread/include/esp_radio_spinel.h index 3f21e9e198ef..504eda1f4f82 100644 --- a/components/openthread/include/esp_radio_spinel.h +++ b/components/openthread/include/esp_radio_spinel.h @@ -57,12 +57,6 @@ typedef struct void (*energy_scan_done)(int8_t max_rssi); /* Callback for Energy Scan Done.*/ void (*transmit_started)(const uint8_t *frame); /* Callback for Transmit Started.*/ void (*switchover_done)(bool success); /* Callback for Switchover Done.*/ - -#if CONFIG_OPENTHREAD_DIAG - void (*diag_receive_done)(const uint8_t *frame, esp_ieee802154_frame_info_t *frame_info); /* Callback for Receive Done (diag).*/ - void (*diag_transmit_done)(const uint8_t *frame, esp_ieee802154_frame_info_t *frame_info); /* Callback for Transmit Done (diag).*/ - void (*diag_transmit_failed)(esp_ieee802154_tx_error_t error); /* Callback for Transmit Failed (diag).*/ -#endif // CONFIG_OPENTHREAD_DIAG } esp_radio_spinel_callbacks_t; /* ESP Radio Spinel Callbacks.*/ /** diff --git a/components/openthread/lib b/components/openthread/lib index d42fd889dd9a..52f5e03e6c53 160000 --- a/components/openthread/lib +++ b/components/openthread/lib @@ -1 +1 @@ -Subproject commit d42fd889dd9a0a5c0e016ee1bd24750df54cb0c2 +Subproject commit 52f5e03e6c535a67750a710c4c4066b9c9a5b7d3 diff --git a/components/openthread/linker.lf b/components/openthread/linker.lf index ffadcdff9129..58c830c8e7a4 100644 --- a/components/openthread/linker.lf +++ b/components/openthread/linker.lf @@ -1,15 +1,17 @@ [mapping:openthread] archive: libopenthread.a entries: - if OPENTHREAD_CSL_ENABLE = y || OPENTHREAD_LINK_METRICS = y: - csl_tx_scheduler (noflash) + if OPENTHREAD_TIMING_OPTIMIZATION = y: link_metrics (noflash) link_quality (noflash) - mac (noflash) mac_frame (noflash) - mesh_forwarder (noflash) radio (noflash) sub_mac (noflash) + if OPENTHREAD_TIMING_OPTIMIZATION = y && OPENTHREAD_RADIO = n: + mesh_forwarder (noflash) + csl_tx_scheduler (noflash) + mac (noflash) + if OPENTHREAD_RCP_SPI = y: ncp_spi (noflash) diff --git a/components/openthread/openthread b/components/openthread/openthread index b945928d7221..36b14d3ef74f 160000 --- a/components/openthread/openthread +++ b/components/openthread/openthread @@ -1 +1 @@ -Subproject commit b945928d722177cd9caeab2e1025499628c101ef +Subproject commit 36b14d3ef74f5e37e5be8902e1c1955a642fdfbf diff --git a/components/openthread/private_include/esp_openthread_ncp.h b/components/openthread/private_include/esp_openthread_ncp.h index 507d305daa19..65053bb56a8a 100644 --- a/components/openthread/private_include/esp_openthread_ncp.h +++ b/components/openthread/private_include/esp_openthread_ncp.h @@ -1,10 +1,11 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include +#include #if CONFIG_OPENTHREAD_NCP_VENDOR_HOOK @@ -15,3 +16,13 @@ #define SPINEL_PROP_VENDOR_ESP_COEX_EVENT (SPINEL_PROP_VENDOR_ESP__BEGIN + 3) #endif + +#ifdef __cplusplus +extern "C" { +#endif + +void otAppNcpInit(otInstance *aInstance); + +#ifdef __cplusplus +} +#endif diff --git a/components/openthread/private_include/esp_openthread_platform.h b/components/openthread/private_include/esp_openthread_platform.h index 3999322a8d1b..582599f5d7fa 100644 --- a/components/openthread/private_include/esp_openthread_platform.h +++ b/components/openthread/private_include/esp_openthread_platform.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/openthread/private_include/openthread-core-esp32x-ftd-config.h b/components/openthread/private_include/openthread-core-esp32x-ftd-config.h index 6e62ee5f390f..284c5493fe19 100644 --- a/components/openthread/private_include/openthread-core-esp32x-ftd-config.h +++ b/components/openthread/private_include/openthread-core-esp32x-ftd-config.h @@ -457,6 +457,36 @@ #define OPENTHREAD_CONFIG_BORDER_AGENT_ID_ENABLE 1 #endif +/** + * @def OPENTHREAD_CONFIG_BORDER_ROUTING_DHCP6_PD_ENABLE + * + * Define to 1 to enable Border Routing DHCPv6 PD. + * + */ +#ifndef OPENTHREAD_CONFIG_BORDER_ROUTING_DHCP6_PD_ENABLE +#define OPENTHREAD_CONFIG_BORDER_ROUTING_DHCP6_PD_ENABLE 1 +#endif + +/** + * @def OPENTHREAD_CONFIG_BORDER_ROUTING_DHCP6_PD_CLIENT_ENABLE + * + * Define to 1 to enable Border Routing DHCPv6 client. + * + */ +#ifndef OPENTHREAD_CONFIG_BORDER_ROUTING_DHCP6_PD_CLIENT_ENABLE +#define OPENTHREAD_CONFIG_BORDER_ROUTING_DHCP6_PD_CLIENT_ENABLE 1 +#endif + +/** + * @def OPENTHREAD_CONFIG_BORDER_ROUTING_DHCP6_PD_CLIENT_MIN_LIFETIME + * + * This parameter sets the minimum preferred lifetime (in seconds) for the Border Router's built-in OpenThread + * DHCPv6 Prefix Delegation (PD) client feature. The default value is set to 30 to pass the certification case. + */ +#ifndef OPENTHREAD_CONFIG_BORDER_ROUTING_DHCP6_PD_CLIENT_MIN_LIFETIME +#define OPENTHREAD_CONFIG_BORDER_ROUTING_DHCP6_PD_CLIENT_MIN_LIFETIME 30 +#endif + /** * @def OPENTHREAD_CONFIG_BORDER_ROUTING_ENABLE * diff --git a/components/openthread/sbom_openthread.yml b/components/openthread/sbom_openthread.yml index 51447eac6103..74398658c691 100644 --- a/components/openthread/sbom_openthread.yml +++ b/components/openthread/sbom_openthread.yml @@ -5,4 +5,4 @@ supplier: 'Organization: Espressif Systems (Shanghai) CO LTD' originator: 'Organization: Google LLC' description: OpenThread released by Google is an open-source implementation of the Thread networking url: https://github.com/espressif/openthread -hash: b945928d722177cd9caeab2e1025499628c101ef +hash: 36b14d3ef74f5e37e5be8902e1c1955a642fdfbf diff --git a/components/openthread/src/esp_openthread.cpp b/components/openthread/src/esp_openthread.cpp index d816cd121d54..3379b318d4af 100644 --- a/components/openthread/src/esp_openthread.cpp +++ b/components/openthread/src/esp_openthread.cpp @@ -4,12 +4,17 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include "sdkconfig.h" #include "esp_openthread.h" #include "esp_check.h" +#include "esp_heap_caps.h" #include "esp_openthread_border_router.h" #include "esp_openthread_common_macro.h" +#include "esp_openthread_cli.h" #include "esp_openthread_dns64.h" #include "esp_openthread_lock.h" +#include "esp_openthread_ncp.h" +#include "esp_openthread_netif_glue.h" #include "esp_openthread_platform.h" #include "esp_openthread_sleep.h" #include "esp_openthread_state.h" @@ -18,15 +23,19 @@ #include "freertos/FreeRTOS.h" #include "lwip/dns.h" #include "openthread/instance.h" +#include "openthread/logging.h" #include "openthread/netdata.h" #include "openthread/tasklet.h" #include "openthread/thread.h" +#include #if CONFIG_OPENTHREAD_FTD #include "openthread/dataset_ftd.h" #endif static bool s_ot_mainloop_running = false; +static SemaphoreHandle_t s_ot_syn_semaphore = NULL; +static TaskHandle_t s_ot_task_handle = NULL; static int hex_digit_to_int(char hex) { @@ -223,3 +232,81 @@ esp_err_t esp_openthread_deinit(void) otInstanceFinalize(esp_openthread_get_instance()); return esp_openthread_platform_deinit(); } + +static void ot_task_worker(void *aContext) +{ + const esp_openthread_config_t* config = *(esp_openthread_config_t **)aContext; + // Initialize the OpenThread stack + ESP_ERROR_CHECK(esp_openthread_init(&(config->platform_config))); + +#if CONFIG_OPENTHREAD_FTD || CONFIG_OPENTHREAD_MTD + esp_netif_t *openthread_netif = esp_netif_new(&(config->netif_config)); + assert(openthread_netif != NULL); + ESP_ERROR_CHECK(esp_netif_attach(openthread_netif, esp_openthread_netif_glue_init(&(config->platform_config)))); +#endif + +#if CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC + // The OpenThread log level directly matches ESP log level + (void)otLoggingSetLevel(CONFIG_LOG_DEFAULT_LEVEL); +#endif // CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC + +#if CONFIG_OPENTHREAD_CLI + esp_openthread_cli_init(); + esp_openthread_cli_console_command_register(); +#endif // CONFIG_OPENTHREAD_CLI + +#if CONFIG_OPENTHREAD_RADIO + otAppNcpInit(esp_openthread_get_instance()); +#endif + xSemaphoreGive(s_ot_syn_semaphore); + + // Run the main loop + esp_openthread_launch_mainloop(); + +#if CONFIG_OPENTHREAD_RADIO + ESP_LOGE(OT_PLAT_LOG_TAG, "RCP deinitialization is not supported for now"); + assert(false); +#endif +#if CONFIG_OPENTHREAD_CLI + esp_openthread_cli_console_command_unregister(); +#endif // CONFIG_OPENTHREAD_CLI + +#if CONFIG_OPENTHREAD_FTD || CONFIG_OPENTHREAD_MTD + // Clean up + esp_openthread_netif_glue_deinit(); + esp_netif_destroy(openthread_netif); +#endif + + ESP_ERROR_CHECK(esp_openthread_deinit()); + + xSemaphoreGive(s_ot_syn_semaphore); + vTaskDelay(portMAX_DELAY); +} + +esp_err_t esp_openthread_start(const esp_openthread_config_t *config) +{ + assert(config); + ESP_RETURN_ON_FALSE(s_ot_syn_semaphore == NULL, ESP_ERR_INVALID_STATE, OT_PLAT_LOG_TAG, "OpenThread has been initialized"); + s_ot_syn_semaphore = xSemaphoreCreateBinary(); + ESP_RETURN_ON_FALSE(s_ot_syn_semaphore != NULL, ESP_ERR_INVALID_STATE, OT_PLAT_LOG_TAG, "Failed to create s_ot_syn_semaphore"); + assert(xTaskCreate(ot_task_worker, CONFIG_OPENTHREAD_TASK_NAME, CONFIG_OPENTHREAD_TASK_SIZE, &config, CONFIG_OPENTHREAD_TASK_PRIORITY, &s_ot_task_handle) == pdPASS); + xSemaphoreTake(s_ot_syn_semaphore, portMAX_DELAY); + return ESP_OK; +} + +esp_err_t esp_openthread_stop(void) +{ + ESP_RETURN_ON_FALSE(s_ot_syn_semaphore != NULL, ESP_ERR_INVALID_STATE, OT_PLAT_LOG_TAG, "OpenThread is not initialized"); + esp_openthread_lock_acquire(portMAX_DELAY); + otInstance *instance = esp_openthread_get_instance(); + bool is_thread_not_active = (otThreadGetDeviceRole(instance) == OT_DEVICE_ROLE_DISABLED && otIp6IsEnabled(instance) == false); + esp_openthread_lock_release(); + ESP_RETURN_ON_FALSE(is_thread_not_active, ESP_ERR_INVALID_STATE, OT_PLAT_LOG_TAG, "Thread interface is still active"); + esp_openthread_mainloop_exit(); + xSemaphoreTake(s_ot_syn_semaphore, portMAX_DELAY); + vTaskDelete(s_ot_task_handle); + vSemaphoreDelete(s_ot_syn_semaphore); + s_ot_task_handle = NULL; + s_ot_syn_semaphore = NULL; + return ESP_OK; +} diff --git a/components/openthread/src/esp_openthread_cli.c b/components/openthread/src/esp_openthread_cli.c index b7e1b933f907..f87e39f017ba 100644 --- a/components/openthread/src/esp_openthread_cli.c +++ b/components/openthread/src/esp_openthread_cli.c @@ -65,6 +65,7 @@ esp_err_t esp_openthread_cli_input(const char *line) static int ot_cli_console_callback(int argc, char **argv) { + ESP_RETURN_ON_FALSE(argv[1] != NULL && strlen(argv[1]) > 0, ESP_FAIL, OT_PLAT_LOG_TAG, "Invalid OpenThread command"); char cli_cmd[OT_CLI_MAX_LINE_LENGTH] = {0}; strncpy(cli_cmd, argv[1], sizeof(cli_cmd) - strlen(cli_cmd) - 1); for (int i = 2; i < argc; i++) { diff --git a/components/openthread/src/port/esp_openthread_radio.c b/components/openthread/src/port/esp_openthread_radio.c index cc9a4a280b81..e83acb58ae07 100644 --- a/components/openthread/src/port/esp_openthread_radio.c +++ b/components/openthread/src/port/esp_openthread_radio.c @@ -165,51 +165,39 @@ esp_err_t esp_openthread_radio_process(otInstance *aInstance, const esp_openthre if (get_event(EVENT_TX_DONE)) { clr_event(EVENT_TX_DONE); -#if CONFIG_OPENTHREAD_DIAG - if (otPlatDiagModeGet()) { - otPlatDiagRadioTransmitDone(aInstance, &s_transmit_frame, OT_ERROR_NONE); - } else -#endif - { - if (s_ack_frame.mPsdu == NULL) { - otPlatRadioTxDone(aInstance, &s_transmit_frame, NULL, OT_ERROR_NONE); - } else { - otPlatRadioTxDone(aInstance, &s_transmit_frame, &s_ack_frame, OT_ERROR_NONE); - esp_ieee802154_receive_handle_done(s_ack_frame.mPsdu - 1); - s_ack_frame.mPsdu = NULL; - } + + if (s_ack_frame.mPsdu == NULL) { + otPlatRadioTxDone(aInstance, &s_transmit_frame, NULL, OT_ERROR_NONE); + } else { + otPlatRadioTxDone(aInstance, &s_transmit_frame, &s_ack_frame, OT_ERROR_NONE); + esp_ieee802154_receive_handle_done(s_ack_frame.mPsdu - 1); + s_ack_frame.mPsdu = NULL; } } if (get_event(EVENT_TX_FAILED)) { clr_event(EVENT_TX_FAILED); -#if CONFIG_OPENTHREAD_DIAG - if (otPlatDiagModeGet()) { - otPlatDiagRadioTransmitDone(aInstance, &s_transmit_frame, OT_ERROR_CHANNEL_ACCESS_FAILURE); - } else -#endif - { - otError err = OT_ERROR_NONE; - - switch (s_tx_error) { - case ESP_IEEE802154_TX_ERR_CCA_BUSY: - case ESP_IEEE802154_TX_ERR_ABORT: - case ESP_IEEE802154_TX_ERR_COEXIST: - err = OT_ERROR_CHANNEL_ACCESS_FAILURE; - break; - - case ESP_IEEE802154_TX_ERR_NO_ACK: - case ESP_IEEE802154_TX_ERR_INVALID_ACK: - err = OT_ERROR_NO_ACK; - break; - - default: - ETS_ASSERT(false); - break; - } - otPlatRadioTxDone(aInstance, &s_transmit_frame, NULL, err); + otError err = OT_ERROR_NONE; + + switch (s_tx_error) { + case ESP_IEEE802154_TX_ERR_CCA_BUSY: + case ESP_IEEE802154_TX_ERR_ABORT: + case ESP_IEEE802154_TX_ERR_COEXIST: + err = OT_ERROR_CHANNEL_ACCESS_FAILURE; + break; + + case ESP_IEEE802154_TX_ERR_NO_ACK: + case ESP_IEEE802154_TX_ERR_INVALID_ACK: + err = OT_ERROR_NO_ACK; + break; + + default: + ETS_ASSERT(false); + break; } + + otPlatRadioTxDone(aInstance, &s_transmit_frame, NULL, err); } if (get_event(EVENT_ENERGY_DETECT_DONE)) { @@ -219,14 +207,7 @@ esp_err_t esp_openthread_radio_process(otInstance *aInstance, const esp_openthre while (atomic_load(&s_recv_queue.used)) { if (s_receive_frame[s_recv_queue.head].mPsdu != NULL) { -#if CONFIG_OPENTHREAD_DIAG - if (otPlatDiagModeGet()) { - otPlatDiagRadioReceiveDone(aInstance, &s_receive_frame[s_recv_queue.head], OT_ERROR_NONE); - } else -#endif - { - otPlatRadioReceiveDone(aInstance, &s_receive_frame[s_recv_queue.head], OT_ERROR_NONE); - } + otPlatRadioReceiveDone(aInstance, &s_receive_frame[s_recv_queue.head], OT_ERROR_NONE); esp_ieee802154_receive_handle_done(s_receive_frame[s_recv_queue.head].mPsdu - 1); s_receive_frame[s_recv_queue.head].mPsdu = NULL; s_recv_queue.head = (s_recv_queue.head + 1) % CONFIG_IEEE802154_RX_BUFFER_SIZE; diff --git a/components/openthread/src/port/esp_openthread_radio_spinel.cpp b/components/openthread/src/port/esp_openthread_radio_spinel.cpp index 531d7503b4ed..846544b98a2b 100644 --- a/components/openthread/src/port/esp_openthread_radio_spinel.cpp +++ b/components/openthread/src/port/esp_openthread_radio_spinel.cpp @@ -100,10 +100,6 @@ esp_err_t esp_openthread_radio_init(const esp_openthread_platform_config_t *conf ot::Spinel::RadioSpinelCallbacks callbacks; memset(&callbacks, 0, sizeof(callbacks)); -#if CONFIG_OPENTHREAD_DIAG - callbacks.mDiagReceiveDone = otPlatDiagRadioReceiveDone; - callbacks.mDiagTransmitDone = otPlatDiagRadioTransmitDone; -#endif // CONFIG_OPENTHREAD_DIAG callbacks.mEnergyScanDone = otPlatRadioEnergyScanDone; callbacks.mReceiveDone = otPlatRadioReceiveDone; callbacks.mTransmitDone = otPlatRadioTxDone; diff --git a/components/openthread/src/port/esp_openthread_uart.c b/components/openthread/src/port/esp_openthread_uart.c index 6893d0400e3f..1e19af66e5b5 100644 --- a/components/openthread/src/port/esp_openthread_uart.c +++ b/components/openthread/src/port/esp_openthread_uart.c @@ -25,6 +25,9 @@ #include "utils/uart.h" #include "driver/usb_serial_jtag_vfs.h" #include "driver/usb_serial_jtag.h" +#if CONFIG_OPENTHREAD_RCP_USB_SERIAL_JTAG +#include "hal/usb_serial_jtag_ll.h" +#endif static int s_uart_port; static int s_uart_fd; @@ -51,6 +54,11 @@ otError otPlatUartSend(const uint8_t *buf, uint16_t buf_length) { int rval = write(s_uart_fd, buf, buf_length); + // DIG-727 +#if CONFIG_OPENTHREAD_RCP_USB_SERIAL_JTAG + usb_serial_jtag_ll_txfifo_flush(); +#endif + if (rval != (int)buf_length) { return OT_ERROR_FAILED; } diff --git a/components/openthread/src/spinel/esp_radio_spinel.cpp b/components/openthread/src/spinel/esp_radio_spinel.cpp index bef9cbe0110e..bbcc8d2bea18 100644 --- a/components/openthread/src/spinel/esp_radio_spinel.cpp +++ b/components/openthread/src/spinel/esp_radio_spinel.cpp @@ -185,58 +185,6 @@ void SwitchoverDone(otInstance *aInstance, bool aSuccess) s_esp_radio_spinel_callbacks[idx].switchover_done(aSuccess); } -#if CONFIG_OPENTHREAD_DIAG -void DiagReceiveDone(otInstance *aInstance, otRadioFrame *aFrame, otError aError) -{ - esp_radio_spinel_idx_t idx = get_index_from_instance(aInstance); - assert(s_esp_radio_spinel_callbacks[idx].diag_receive_done); - uint8_t *frame = (uint8_t *)malloc(aFrame->mLength + 1); - esp_ieee802154_frame_info_t frame_info; - if (frame) { - frame[0] = aFrame->mLength; - memcpy((void *)(frame + 1), aFrame->mPsdu, frame[0]); - frame_info.rssi = aFrame->mInfo.mRxInfo.mRssi; - frame_info.timestamp = aFrame->mInfo.mRxInfo.mTimestamp; - frame_info.pending = aFrame->mInfo.mRxInfo.mAckedWithFramePending; - s_esp_radio_spinel_callbacks[idx].diag_receive_done(frame, &frame_info); - free(frame); - } else { - ESP_LOGE(ESP_SPINEL_LOG_TAG, "Fail to alloc memory for frame"); - } -} - -void DiagTransmitDone(otInstance *aInstance, otRadioFrame *aFrame, otError aError) -{ - esp_radio_spinel_idx_t idx = get_index_from_instance(aInstance); - assert(s_esp_radio_spinel_callbacks[idx].diag_transmit_done && s_esp_radio_spinel_callbacks[idx].diag_transmit_failed); - if (aError == OT_ERROR_NONE) { - uint8_t *frame = (uint8_t *)malloc(aFrame->mLength + 1); - if (frame) { - esp_ieee802154_frame_info_t ack_info; - frame[0] = aFrame->mLength; - memcpy((void *)(frame + 1), aFrame->mPsdu, frame[0]); - s_esp_radio_spinel_callbacks[idx].diag_transmit_done(frame, &ack_info); - free(frame); - } else { - ESP_LOGE(ESP_SPINEL_LOG_TAG, "Fail to alloc memory for frame"); - } - } else { - switch (aError) { - case OT_ERROR_CHANNEL_ACCESS_FAILURE: - s_esp_radio_spinel_callbacks[idx].diag_transmit_failed(ESP_IEEE802154_TX_ERR_CCA_BUSY); - break; - case OT_ERROR_NO_ACK: - s_esp_radio_spinel_callbacks[idx].diag_transmit_failed(ESP_IEEE802154_TX_ERR_NO_ACK); - break; - default: - s_esp_radio_spinel_callbacks[idx].diag_transmit_failed(ESP_IEEE802154_TX_ERR_CCA_BUSY); - break; - } - } -} -#endif // CONFIG_OPENTHREAD_DIAG - - void esp_radio_spinel_set_callbacks(const esp_radio_spinel_callbacks_t aCallbacks, esp_radio_spinel_idx_t idx) { s_esp_radio_spinel_callbacks[idx] = aCallbacks; @@ -247,10 +195,6 @@ void esp_radio_spinel_set_callbacks(const esp_radio_spinel_callbacks_t aCallback Callbacks.mEnergyScanDone = EnergyScanDone; Callbacks.mTxStarted = TxStarted; Callbacks.mSwitchoverDone = SwitchoverDone; -#if CONFIG_OPENTHREAD_DIAG - Callbacks.mDiagReceiveDone = DiagReceiveDone; - Callbacks.mDiagTransmitDone = DiagTransmitDone; -#endif // CONFIG_OPENTHREAD_DIAG s_radio[idx].SetCallbacks(Callbacks); } diff --git a/components/protocomm/src/transports/protocomm_nimble.c b/components/protocomm/src/transports/protocomm_nimble.c index 51f5c6332735..fea2516a5aca 100644 --- a/components/protocomm/src/transports/protocomm_nimble.c +++ b/components/protocomm/src/transports/protocomm_nimble.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -547,6 +547,7 @@ static int simple_ble_start(const simple_ble_cfg_t *cfg) ble_hs_cfg.sm_our_key_dist = BLE_SM_PAIR_KEY_DIST_ENC | BLE_SM_PAIR_KEY_DIST_ID; ble_hs_cfg.sm_their_key_dist = BLE_SM_PAIR_KEY_DIST_ENC | BLE_SM_PAIR_KEY_DIST_ID; +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(cfg); if (rc != 0) { ESP_LOGE(TAG, "Error initializing GATT server"); @@ -565,6 +566,7 @@ static int simple_ble_start(const simple_ble_cfg_t *cfg) resp_data.name_len = strlen(ble_svc_gap_device_name()); resp_data.name_is_complete = 1; } +#endif /* Set manufacturer data if protocomm_ble_mfg_data points to valid data */ if (protocomm_ble_mfg_data != NULL) { diff --git a/components/pthread/test_apps/pthread_unity_tests/main/test_pthread_semaphore.c b/components/pthread/test_apps/pthread_unity_tests/main/test_pthread_semaphore.c index a4bb84b09e2c..119520398b74 100644 --- a/components/pthread/test_apps/pthread_unity_tests/main/test_pthread_semaphore.c +++ b/components/pthread/test_apps/pthread_unity_tests/main/test_pthread_semaphore.c @@ -311,7 +311,7 @@ TEST_CASE("sem_timedwait wait on locked semaphore (timeout)", "[semaphore]") abstime.tv_nsec = abstime.tv_nsec + 20000000; if (abstime.tv_nsec >= 1000000000) { abstime.tv_sec = abstime.tv_sec + 1; - abstime.tv_sec = abstime.tv_nsec % 1000000000; + abstime.tv_nsec = abstime.tv_nsec % 1000000000; } TEST_ASSERT_EQUAL_INT(-1, sem_timedwait(&semaphore, &abstime)); diff --git a/components/riscv/include/esp_private/interrupt_clic.h b/components/riscv/include/esp_private/interrupt_clic.h index 8f0981b7815b..25dc84c482ee 100644 --- a/components/riscv/include/esp_private/interrupt_clic.h +++ b/components/riscv/include/esp_private/interrupt_clic.h @@ -46,7 +46,7 @@ extern "C" { #define MTVT_CSR 0x307 -#if CONFIG_IDF_TARGET_ESP32P4 +#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3 /** * The ESP32-P4 and the beta version of the ESP32-C5 implement a non-standard version of the CLIC: @@ -56,9 +56,9 @@ extern "C" { #define INTTHRESH_STANDARD 0 #define MINTSTATUS_CSR 0x346 -#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 +#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 -/* The ESP32-C5 (MP) and C61 use the standard CLIC specification, for example, it defines the mintthresh CSR */ +/* The ESP32-C5 (MP), C61 and P4 (since REV2) use the standard CLIC specification, for example, it defines the mintthresh CSR */ #define INTTHRESH_STANDARD 1 #define MINTSTATUS_CSR 0xFB1 #define MINTTHRESH_CSR 0x347 diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index 0d2c467863a6..f530f70bebe9 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -20,7 +20,11 @@ endif() # register headers that generated by script from CSV if(CONFIG_IDF_TARGET_ESP32P4) - list(APPEND includes "${target_folder}/register/hw_ver1") + if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3) + list(APPEND includes "${target_folder}/register/hw_ver1") + else() + list(APPEND includes "${target_folder}/register/hw_ver3") + endif() else() if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/register") list(APPEND includes "${target_folder}/register") diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 161e1fd7055c..4bac8668ec14 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -595,6 +595,10 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX int default 3 +config SOC_AHB_GDMA_SUPPORT_PSRAM + bool + default y + config SOC_AXI_GDMA_SUPPORT_PSRAM bool default y @@ -1931,6 +1935,10 @@ config SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP bool default y +config SOC_PM_SUPPORT_CPU_PD + bool + default y + config SOC_PM_SUPPORT_XTAL32K_PD bool default y @@ -1983,10 +1991,6 @@ config SOC_PAU_IN_TOP_DOMAIN bool default y -config SOC_CPU_IN_TOP_DOMAIN - bool - default y - config SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE bool default y @@ -2071,10 +2075,6 @@ config SOC_MEM_TCM_SUPPORTED bool default y -config SOC_MEM_NON_CONTIGUOUS_SRAM - bool - default y - config SOC_ASYNCHRONOUS_BUS_ERROR_MODE bool default y diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h index 3d684b62dcf0..bd4c7a51b2a6 100644 --- a/components/soc/esp32p4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h @@ -375,7 +375,7 @@ typedef enum { LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */ } soc_periph_lcd_clk_src_t; -//////////////////////////////////////////////////LCD/////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////CAM/////////////////////////////////////////////////////////////////// /** * @brief Array initializer for all supported clock sources of CAM @@ -392,7 +392,7 @@ typedef enum { CAM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */ } soc_periph_cam_clk_src_t; -/////////////////////////////////////////////////MIPI/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////MIPI CSI/////////////////////////////////////////////////////////////// /** * @brief Array initializer for all supported clock sources of MIPI CSI PHY interface @@ -409,10 +409,12 @@ typedef enum { MIPI_CSI_PHY_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F20M, /*!< Select PLL_F20M as default clock */ } soc_periph_mipi_csi_phy_clk_src_t; +/////////////////////////////////////////////////MIPI DSI/////////////////////////////////////////////////////////////// + /** * @brief Array initializer for all supported clock sources of MIPI DSI DPI interface */ -#define SOC_MIPI_DSI_DPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_PLL_F240M} +#define SOC_MIPI_DSI_DPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_PLL_F240M, SOC_MOD_CLK_APLL} /** * @brief Type of MIPI DSI DPI clock source @@ -421,23 +423,46 @@ typedef enum { MIPI_DSI_DPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as MIPI DSI DPI source clock */ MIPI_DSI_DPI_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as MIPI DSI DPI source clock */ MIPI_DSI_DPI_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as MIPI DSI DPI source clock */ + MIPI_DSI_DPI_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as MIPI DSI DPI source clock */ MIPI_DSI_DPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as default clock */ } soc_periph_mipi_dsi_dpi_clk_src_t; /** - * @brief Array initializer for all supported clock sources of MIPI DSI PHY interface + * @brief Type of MIPI DSI PHY configuration clock source */ -#define SOC_MIPI_DSI_PHY_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F25M, SOC_MOD_CLK_PLL_F20M} +typedef enum { + MIPI_DSI_PHY_CFG_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as MIPI DSI PHY configuration source clock */ + MIPI_DSI_PHY_CFG_CLK_SRC_PLL_F25M = SOC_MOD_CLK_PLL_F25M, /*!< Select PLL_F25M as MIPI DSI PHY configuration source clock */ + MIPI_DSI_PHY_CFG_CLK_SRC_PLL_F20M = SOC_MOD_CLK_PLL_F20M, /*!< Select PLL_F20M as MIPI DSI PHY configuration source clock */ + MIPI_DSI_PHY_CFG_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F20M, /*!< Select PLL_F20M as default clock */ +} soc_periph_mipi_dsi_phy_cfg_clk_src_t; /** - * @brief Type of MIPI DSI PHY clock source + * @brief Type of MIPI DSI PHY PLL reference clock source */ typedef enum { - MIPI_DSI_PHY_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as MIPI DSI PHY source clock */ - MIPI_DSI_PHY_CLK_SRC_PLL_F25M = SOC_MOD_CLK_PLL_F25M, /*!< Select PLL_F25M as MIPI DSI PHY source clock */ - MIPI_DSI_PHY_CLK_SRC_PLL_F20M = SOC_MOD_CLK_PLL_F20M, /*!< Select PLL_F20M as MIPI DSI PHY source clock */ - MIPI_DSI_PHY_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F20M, /*!< Select PLL_F20M as default clock */ -} soc_periph_mipi_dsi_phy_clk_src_t; + // only available on esp32p4 version < 3.0 + MIPI_DSI_PHY_PLLREF_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as MIPI DSI PHY PLL reference clock */ + MIPI_DSI_PHY_PLLREF_CLK_SRC_PLL_F25M = SOC_MOD_CLK_PLL_F25M, /*!< Select PLL_F25M as MIPI DSI PHY PLL reference clock */ + MIPI_DSI_PHY_PLLREF_CLK_SRC_PLL_F20M = SOC_MOD_CLK_PLL_F20M, /*!< Select PLL_F20M as MIPI DSI PHY PLL reference clock */ + MIPI_DSI_PHY_PLLREF_CLK_SRC_DEFAULT_LEGACY = SOC_MOD_CLK_PLL_F20M, /*!< Select PLL_F20M as default clock */ + + // only available on esp32p4 version >= 3.0 + MIPI_DSI_PHY_PLLREF_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as MIPI DSI PHY PLL reference clock */ + MIPI_DSI_PHY_PLLREF_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as MIPI DSI PHY PLL reference clock */ + MIPI_DSI_PHY_PLLREF_CLK_SRC_CPLL = SOC_MOD_CLK_CPLL, /*!< Select CPLL as MIPI DSI PHY PLL reference clock */ + MIPI_DSI_PHY_PLLREF_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as MIPI DSI PHY PLL reference clock */ + MIPI_DSI_PHY_PLLREF_CLK_SRC_MPLL = SOC_MOD_CLK_MPLL, /*!< Select MPLL as MIPI DSI PHY PLL reference clock */ + MIPI_DSI_PHY_PLLREF_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as default clock */ +} soc_periph_mipi_dsi_phy_pllref_clk_src_t; + +/** + * @brief For backward compatibility, old macro definitions are kept. Remove it in the next major release (esp-idf v7.0) + */ +#define MIPI_DSI_PHY_CLK_SRC_RC_FAST SOC_MOD_CLK_RC_FAST +#define MIPI_DSI_PHY_CLK_SRC_PLL_F25M SOC_MOD_CLK_PLL_F25M +#define MIPI_DSI_PHY_CLK_SRC_PLL_F20M SOC_MOD_CLK_PLL_F20M +#define MIPI_DSI_PHY_CLK_SRC_DEFAULT SOC_MOD_CLK_PLL_F20M /////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h index d36ecc9e2969..7948a3ac9f8f 100644 --- a/components/soc/esp32p4/include/soc/soc.h +++ b/components/soc/esp32p4/include/soc/soc.h @@ -20,7 +20,6 @@ #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1 #define UART_FIFO_AHB_REG(i) (REG_UART_BASE(i) + 0x0) #define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000) -#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_FLASH_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 #define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 #define REG_I2C_BASE(i) (DR_REG_I2C0_BASE + (i) * 0x1000) diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index f19b78f7dbf9..8042f0bf3faf 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -215,6 +215,7 @@ #define SOC_GDMA_SUPPORT_CRC 1 #define SOC_GDMA_NUM_GROUPS_MAX 2 #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 +#define SOC_AHB_GDMA_SUPPORT_PSRAM 1 #define SOC_AXI_GDMA_SUPPORT_PSRAM 1 #define SOC_GDMA_SUPPORT_ETM 1 #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 @@ -720,6 +721,7 @@ #define SOC_PM_EXT1_WAKEUP_BY_PMU (1) #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) #define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP (1) /*! v4.30a +- GRSTCTL register now contains the CSftRstDone bit which indicates the completion of a soft reset. */ /* ---------------------------- Register Types ------------------------------ */ @@ -129,7 +132,8 @@ typedef union { uint32_t rxfflsh: 1; uint32_t txfflsh: 1; uint32_t txfnum: 5; - uint32_t reserved_11: 19; + uint32_t reserved_11: 18; + uint32_t csftrstdone: 1; uint32_t dmareq: 1; uint32_t ahbidle: 1; }; diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld index fd880fc50aef..d4d9188c180f 100644 --- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld +++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld @@ -24,6 +24,7 @@ PROVIDE ( AXI_ICM_QOS = 0x500A4400 ); PROVIDE ( HP_PERI_PMS = 0x500A5000 ); PROVIDE ( LP2HP_PERI_PMS = 0x500A5800 ); PROVIDE ( DMA_PMS = 0x500A6000 ); +PROVIDE ( AXI_PERF_MON = 0x500A8000 ); PROVIDE ( LEDC = 0x500D3000 ); PROVIDE ( LEDC_GAMMA_RAM = 0x500D3400 ); PROVIDE ( TIMERG0 = 0x500C2000 ); diff --git a/components/soc/esp32p4/mipi_dsi_periph.c b/components/soc/esp32p4/mipi_dsi_periph.c index ca2eb57f0078..b8ae4de768f9 100644 --- a/components/soc/esp32p4/mipi_dsi_periph.c +++ b/components/soc/esp32p4/mipi_dsi_periph.c @@ -1,10 +1,11 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "soc/mipi_dsi_periph.h" +#include "soc/interrupts.h" const soc_mipi_dsi_phy_pll_freq_range_t soc_mipi_dsi_phy_pll_ranges[] = { {80, 89, 0x00}, // [80,90) Mbps @@ -49,3 +50,9 @@ const soc_mipi_dsi_phy_pll_freq_range_t soc_mipi_dsi_phy_pll_ranges[] = { }; const size_t num_of_soc_mipi_dsi_phy_pll_ranges = sizeof(soc_mipi_dsi_phy_pll_ranges) / sizeof(soc_mipi_dsi_phy_pll_freq_range_t); + +const soc_mipi_dsi_signal_desc_t soc_mipi_dsi_signals[1] = { + [0] = { + .brg_irq_id = ETS_DSI_BRIDGE_INTR_SOURCE, + } +}; diff --git a/components/soc/esp32p4/register/hw_ver1/soc/pmu_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/pmu_struct.h index d8936af001e0..dd7aa57b00ad 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/pmu_struct.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/pmu_struct.h @@ -6,11 +6,13 @@ #pragma once #include -#include "soc/pmu_reg.h" +#include "pmu_reg.h" #ifdef __cplusplus extern "C" { #endif +#define SOC_PMU_STRUCT_HW_VER 1 + typedef union { struct { uint32_t reserved0 : 21; diff --git a/components/soc/esp32p4/register/hw_ver1/soc/timer_group_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/timer_group_reg.h index 53679d5b048d..7dc0d8eb3b87 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/timer_group_reg.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/timer_group_reg.h @@ -11,6 +11,8 @@ extern "C" { #endif +#define REG_TIMG_BASE(i) (DR_REG_TIMG0_BASE + (i) * 0x1000) + /** TIMG_T0CONFIG_REG register * Timer 0 configuration register */ diff --git a/components/soc/esp32p4/include/soc/usb_dwc_cfg.h b/components/soc/esp32p4/register/hw_ver1/soc/usb_dwc_cfg.h similarity index 100% rename from components/soc/esp32p4/include/soc/usb_dwc_cfg.h rename to components/soc/esp32p4/register/hw_ver1/soc/usb_dwc_cfg.h diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ahb_dma_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ahb_dma_eco5_struct.h deleted file mode 100644 index 43769ae0ee1d..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/ahb_dma_eco5_struct.h +++ /dev/null @@ -1,3866 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Interrupt Registers */ -/** Type of in_int_raw_ch0 register - * Raw interrupt status of RX channel 0 - */ -typedef union { - struct { - /** in_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT - */ - uint32_t in_done_ch0_int_raw:1; - /** in_suc_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT - */ - uint32_t in_suc_eof_ch0_int_raw:1; - /** in_err_eof_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT - */ - uint32_t in_err_eof_ch0_int_raw:1; - /** in_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT - */ - uint32_t in_dscr_err_ch0_int_raw:1; - /** in_dscr_empty_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT - */ - uint32_t in_dscr_empty_ch0_int_raw:1; - /** infifo_ovf_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT - */ - uint32_t infifo_ovf_ch0_int_raw:1; - /** infifo_udf_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT - */ - uint32_t infifo_udf_ch0_int_raw:1; - /** in_ahbinf_resp_err_ch0_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT - */ - uint32_t in_ahbinf_resp_err_ch0_int_raw:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_raw_ch0_reg_t; - - -/** Group: Status Registers */ -/** Type of in_int_st_ch0 register - * Masked interrupt status of RX channel 0 - */ -typedef union { - struct { - /** in_done_ch0_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT - */ - uint32_t in_done_ch0_int_st:1; - /** in_suc_eof_ch0_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT - */ - uint32_t in_suc_eof_ch0_int_st:1; - /** in_err_eof_ch0_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT - */ - uint32_t in_err_eof_ch0_int_st:1; - /** in_dscr_err_ch0_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT - */ - uint32_t in_dscr_err_ch0_int_st:1; - /** in_dscr_empty_ch0_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT - */ - uint32_t in_dscr_empty_ch0_int_st:1; - /** infifo_ovf_ch0_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT - */ - uint32_t infifo_ovf_ch0_int_st:1; - /** infifo_udf_ch0_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT - */ - uint32_t infifo_udf_ch0_int_st:1; - /** in_ahbinf_resp_err_ch0_int_st : RO; bitpos: [7]; default: 0; - * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT - */ - uint32_t in_ahbinf_resp_err_ch0_int_st:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_st_ch0_reg_t; - -/** Type of in_int_ena_ch0 register - * Interrupt enable bits of RX channel 0 - */ -typedef union { - struct { - /** in_done_ch0_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH0_INT - */ - uint32_t in_done_ch0_int_ena:1; - /** in_suc_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT - */ - uint32_t in_suc_eof_ch0_int_ena:1; - /** in_err_eof_ch0_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH0_INT - */ - uint32_t in_err_eof_ch0_int_ena:1; - /** in_dscr_err_ch0_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT - */ - uint32_t in_dscr_err_ch0_int_ena:1; - /** in_dscr_empty_ch0_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT - */ - uint32_t in_dscr_empty_ch0_int_ena:1; - /** infifo_ovf_ch0_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT - */ - uint32_t infifo_ovf_ch0_int_ena:1; - /** infifo_udf_ch0_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT - */ - uint32_t infifo_udf_ch0_int_ena:1; - /** in_ahbinf_resp_err_ch0_int_ena : R/W; bitpos: [7]; default: 0; - * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH0_INT - */ - uint32_t in_ahbinf_resp_err_ch0_int_ena:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_ena_ch0_reg_t; - -/** Type of in_int_clr_ch0 register - * Interrupt clear bits of RX channel 0 - */ -typedef union { - struct { - /** in_done_ch0_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH0_INT - */ - uint32_t in_done_ch0_int_clr:1; - /** in_suc_eof_ch0_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT - */ - uint32_t in_suc_eof_ch0_int_clr:1; - /** in_err_eof_ch0_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH0_INT - */ - uint32_t in_err_eof_ch0_int_clr:1; - /** in_dscr_err_ch0_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT - */ - uint32_t in_dscr_err_ch0_int_clr:1; - /** in_dscr_empty_ch0_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT - */ - uint32_t in_dscr_empty_ch0_int_clr:1; - /** infifo_ovf_ch0_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT - */ - uint32_t infifo_ovf_ch0_int_clr:1; - /** infifo_udf_ch0_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT - */ - uint32_t infifo_udf_ch0_int_clr:1; - /** in_ahbinf_resp_err_ch0_int_clr : WT; bitpos: [7]; default: 0; - * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH0_INT - */ - uint32_t in_ahbinf_resp_err_ch0_int_clr:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_clr_ch0_reg_t; - -/** Type of in_int_raw_ch1 register - * Raw interrupt status of RX channel 1 - */ -typedef union { - struct { - /** in_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT - */ - uint32_t in_done_ch1_int_raw:1; - /** in_suc_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT - */ - uint32_t in_suc_eof_ch1_int_raw:1; - /** in_err_eof_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT - */ - uint32_t in_err_eof_ch1_int_raw:1; - /** in_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT - */ - uint32_t in_dscr_err_ch1_int_raw:1; - /** in_dscr_empty_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT - */ - uint32_t in_dscr_empty_ch1_int_raw:1; - /** infifo_ovf_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT - */ - uint32_t infifo_ovf_ch1_int_raw:1; - /** infifo_udf_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT - */ - uint32_t infifo_udf_ch1_int_raw:1; - /** in_ahbinf_resp_err_ch1_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT - */ - uint32_t in_ahbinf_resp_err_ch1_int_raw:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_raw_ch1_reg_t; - -/** Type of in_int_st_ch1 register - * Masked interrupt status of RX channel 1 - */ -typedef union { - struct { - /** in_done_ch1_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT - */ - uint32_t in_done_ch1_int_st:1; - /** in_suc_eof_ch1_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT - */ - uint32_t in_suc_eof_ch1_int_st:1; - /** in_err_eof_ch1_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT - */ - uint32_t in_err_eof_ch1_int_st:1; - /** in_dscr_err_ch1_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT - */ - uint32_t in_dscr_err_ch1_int_st:1; - /** in_dscr_empty_ch1_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT - */ - uint32_t in_dscr_empty_ch1_int_st:1; - /** infifo_ovf_ch1_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT - */ - uint32_t infifo_ovf_ch1_int_st:1; - /** infifo_udf_ch1_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT - */ - uint32_t infifo_udf_ch1_int_st:1; - /** in_ahbinf_resp_err_ch1_int_st : RO; bitpos: [7]; default: 0; - * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT - */ - uint32_t in_ahbinf_resp_err_ch1_int_st:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_st_ch1_reg_t; - -/** Type of in_int_ena_ch1 register - * Interrupt enable bits of RX channel 1 - */ -typedef union { - struct { - /** in_done_ch1_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH1_INT - */ - uint32_t in_done_ch1_int_ena:1; - /** in_suc_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT - */ - uint32_t in_suc_eof_ch1_int_ena:1; - /** in_err_eof_ch1_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH1_INT - */ - uint32_t in_err_eof_ch1_int_ena:1; - /** in_dscr_err_ch1_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT - */ - uint32_t in_dscr_err_ch1_int_ena:1; - /** in_dscr_empty_ch1_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT - */ - uint32_t in_dscr_empty_ch1_int_ena:1; - /** infifo_ovf_ch1_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT - */ - uint32_t infifo_ovf_ch1_int_ena:1; - /** infifo_udf_ch1_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT - */ - uint32_t infifo_udf_ch1_int_ena:1; - /** in_ahbinf_resp_err_ch1_int_ena : R/W; bitpos: [7]; default: 0; - * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH1_INT - */ - uint32_t in_ahbinf_resp_err_ch1_int_ena:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_ena_ch1_reg_t; - -/** Type of in_int_clr_ch1 register - * Interrupt clear bits of RX channel 1 - */ -typedef union { - struct { - /** in_done_ch1_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH1_INT - */ - uint32_t in_done_ch1_int_clr:1; - /** in_suc_eof_ch1_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT - */ - uint32_t in_suc_eof_ch1_int_clr:1; - /** in_err_eof_ch1_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH1_INT - */ - uint32_t in_err_eof_ch1_int_clr:1; - /** in_dscr_err_ch1_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT - */ - uint32_t in_dscr_err_ch1_int_clr:1; - /** in_dscr_empty_ch1_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT - */ - uint32_t in_dscr_empty_ch1_int_clr:1; - /** infifo_ovf_ch1_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT - */ - uint32_t infifo_ovf_ch1_int_clr:1; - /** infifo_udf_ch1_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT - */ - uint32_t infifo_udf_ch1_int_clr:1; - /** in_ahbinf_resp_err_ch1_int_clr : WT; bitpos: [7]; default: 0; - * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH1_INT - */ - uint32_t in_ahbinf_resp_err_ch1_int_clr:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_clr_ch1_reg_t; - -/** Type of in_int_raw_ch2 register - * Raw interrupt status of RX channel 2 - */ -typedef union { - struct { - /** in_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH2_INT - */ - uint32_t in_done_ch2_int_raw:1; - /** in_suc_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT - */ - uint32_t in_suc_eof_ch2_int_raw:1; - /** in_err_eof_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT - */ - uint32_t in_err_eof_ch2_int_raw:1; - /** in_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT - */ - uint32_t in_dscr_err_ch2_int_raw:1; - /** in_dscr_empty_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT - */ - uint32_t in_dscr_empty_ch2_int_raw:1; - /** infifo_ovf_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT - */ - uint32_t infifo_ovf_ch2_int_raw:1; - /** infifo_udf_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT - */ - uint32_t infifo_udf_ch2_int_raw:1; - /** in_ahbinf_resp_err_ch2_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT - */ - uint32_t in_ahbinf_resp_err_ch2_int_raw:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_raw_ch2_reg_t; - -/** Type of in_int_st_ch2 register - * Masked interrupt status of RX channel 2 - */ -typedef union { - struct { - /** in_done_ch2_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH2_INT - */ - uint32_t in_done_ch2_int_st:1; - /** in_suc_eof_ch2_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT - */ - uint32_t in_suc_eof_ch2_int_st:1; - /** in_err_eof_ch2_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT - */ - uint32_t in_err_eof_ch2_int_st:1; - /** in_dscr_err_ch2_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT - */ - uint32_t in_dscr_err_ch2_int_st:1; - /** in_dscr_empty_ch2_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT - */ - uint32_t in_dscr_empty_ch2_int_st:1; - /** infifo_ovf_ch2_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT - */ - uint32_t infifo_ovf_ch2_int_st:1; - /** infifo_udf_ch2_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT - */ - uint32_t infifo_udf_ch2_int_st:1; - /** in_ahbinf_resp_err_ch2_int_st : RO; bitpos: [7]; default: 0; - * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT - */ - uint32_t in_ahbinf_resp_err_ch2_int_st:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_st_ch2_reg_t; - -/** Type of in_int_ena_ch2 register - * Interrupt enable bits of RX channel 2 - */ -typedef union { - struct { - /** in_done_ch2_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH2_INT - */ - uint32_t in_done_ch2_int_ena:1; - /** in_suc_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH2_INT - */ - uint32_t in_suc_eof_ch2_int_ena:1; - /** in_err_eof_ch2_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH2_INT - */ - uint32_t in_err_eof_ch2_int_ena:1; - /** in_dscr_err_ch2_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH2_INT - */ - uint32_t in_dscr_err_ch2_int_ena:1; - /** in_dscr_empty_ch2_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH2_INT - */ - uint32_t in_dscr_empty_ch2_int_ena:1; - /** infifo_ovf_ch2_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH2_INT - */ - uint32_t infifo_ovf_ch2_int_ena:1; - /** infifo_udf_ch2_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH2_INT - */ - uint32_t infifo_udf_ch2_int_ena:1; - /** in_ahbinf_resp_err_ch2_int_ena : R/W; bitpos: [7]; default: 0; - * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH2_INT - */ - uint32_t in_ahbinf_resp_err_ch2_int_ena:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_ena_ch2_reg_t; - -/** Type of in_int_clr_ch2 register - * Interrupt clear bits of RX channel 2 - */ -typedef union { - struct { - /** in_done_ch2_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH2_INT - */ - uint32_t in_done_ch2_int_clr:1; - /** in_suc_eof_ch2_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH2_INT - */ - uint32_t in_suc_eof_ch2_int_clr:1; - /** in_err_eof_ch2_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH2_INT - */ - uint32_t in_err_eof_ch2_int_clr:1; - /** in_dscr_err_ch2_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH2_INT - */ - uint32_t in_dscr_err_ch2_int_clr:1; - /** in_dscr_empty_ch2_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH2_INT - */ - uint32_t in_dscr_empty_ch2_int_clr:1; - /** infifo_ovf_ch2_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH2_INT - */ - uint32_t infifo_ovf_ch2_int_clr:1; - /** infifo_udf_ch2_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH2_INT - */ - uint32_t infifo_udf_ch2_int_clr:1; - /** in_ahbinf_resp_err_ch2_int_clr : WT; bitpos: [7]; default: 0; - * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH2_INT - */ - uint32_t in_ahbinf_resp_err_ch2_int_clr:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_int_clr_ch2_reg_t; - -/** Type of out_int_raw_ch0 register - * //Raw interrupt status of TX channel 0 - */ -typedef union { - struct { - /** out_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT - */ - uint32_t out_done_ch0_int_raw:1; - /** out_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT - */ - uint32_t out_eof_ch0_int_raw:1; - /** out_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT - */ - uint32_t out_dscr_err_ch0_int_raw:1; - /** out_total_eof_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT - */ - uint32_t out_total_eof_ch0_int_raw:1; - /** outfifo_ovf_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT - */ - uint32_t outfifo_ovf_ch0_int_raw:1; - /** outfifo_udf_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT - */ - uint32_t outfifo_udf_ch0_int_raw:1; - /** out_ahbinf_resp_err_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT - */ - uint32_t out_ahbinf_resp_err_ch0_int_raw:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_raw_ch0_reg_t; - -/** Type of out_int_st_ch0 register - * Masked interrupt status of TX channel 0 - */ -typedef union { - struct { - /** out_done_ch0_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT - */ - uint32_t out_done_ch0_int_st:1; - /** out_eof_ch0_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT - */ - uint32_t out_eof_ch0_int_st:1; - /** out_dscr_err_ch0_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT - */ - uint32_t out_dscr_err_ch0_int_st:1; - /** out_total_eof_ch0_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT - */ - uint32_t out_total_eof_ch0_int_st:1; - /** outfifo_ovf_ch0_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT - */ - uint32_t outfifo_ovf_ch0_int_st:1; - /** outfifo_udf_ch0_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT - */ - uint32_t outfifo_udf_ch0_int_st:1; - /** out_ahbinf_resp_err_ch0_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT - */ - uint32_t out_ahbinf_resp_err_ch0_int_st:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_st_ch0_reg_t; - -/** Type of out_int_ena_ch0 register - * Interrupt enable bits of TX channel 0 - */ -typedef union { - struct { - /** out_done_ch0_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT - */ - uint32_t out_done_ch0_int_ena:1; - /** out_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT - */ - uint32_t out_eof_ch0_int_ena:1; - /** out_dscr_err_ch0_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT - */ - uint32_t out_dscr_err_ch0_int_ena:1; - /** out_total_eof_ch0_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT - */ - uint32_t out_total_eof_ch0_int_ena:1; - /** outfifo_ovf_ch0_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT - */ - uint32_t outfifo_ovf_ch0_int_ena:1; - /** outfifo_udf_ch0_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT - */ - uint32_t outfifo_udf_ch0_int_ena:1; - /** out_ahbinf_resp_err_ch0_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH0_INT - */ - uint32_t out_ahbinf_resp_err_ch0_int_ena:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_ena_ch0_reg_t; - -/** Type of out_int_clr_ch0 register - * Interrupt clear bits of TX channel 0 - */ -typedef union { - struct { - /** out_done_ch0_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT - */ - uint32_t out_done_ch0_int_clr:1; - /** out_eof_ch0_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT - */ - uint32_t out_eof_ch0_int_clr:1; - /** out_dscr_err_ch0_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT - */ - uint32_t out_dscr_err_ch0_int_clr:1; - /** out_total_eof_ch0_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT - */ - uint32_t out_total_eof_ch0_int_clr:1; - /** outfifo_ovf_ch0_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT - */ - uint32_t outfifo_ovf_ch0_int_clr:1; - /** outfifo_udf_ch0_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT - */ - uint32_t outfifo_udf_ch0_int_clr:1; - /** out_ahbinf_resp_err_ch0_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH0_INT - */ - uint32_t out_ahbinf_resp_err_ch0_int_clr:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_clr_ch0_reg_t; - -/** Type of out_int_raw_ch1 register - * //Raw interrupt status of TX channel 1 - */ -typedef union { - struct { - /** out_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT - */ - uint32_t out_done_ch1_int_raw:1; - /** out_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT - */ - uint32_t out_eof_ch1_int_raw:1; - /** out_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT - */ - uint32_t out_dscr_err_ch1_int_raw:1; - /** out_total_eof_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT - */ - uint32_t out_total_eof_ch1_int_raw:1; - /** outfifo_ovf_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT - */ - uint32_t outfifo_ovf_ch1_int_raw:1; - /** outfifo_udf_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT - */ - uint32_t outfifo_udf_ch1_int_raw:1; - /** out_ahbinf_resp_err_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT - */ - uint32_t out_ahbinf_resp_err_ch1_int_raw:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_raw_ch1_reg_t; - -/** Type of out_int_st_ch1 register - * Masked interrupt status of TX channel 1 - */ -typedef union { - struct { - /** out_done_ch1_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT - */ - uint32_t out_done_ch1_int_st:1; - /** out_eof_ch1_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT - */ - uint32_t out_eof_ch1_int_st:1; - /** out_dscr_err_ch1_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT - */ - uint32_t out_dscr_err_ch1_int_st:1; - /** out_total_eof_ch1_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT - */ - uint32_t out_total_eof_ch1_int_st:1; - /** outfifo_ovf_ch1_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT - */ - uint32_t outfifo_ovf_ch1_int_st:1; - /** outfifo_udf_ch1_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT - */ - uint32_t outfifo_udf_ch1_int_st:1; - /** out_ahbinf_resp_err_ch1_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT - */ - uint32_t out_ahbinf_resp_err_ch1_int_st:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_st_ch1_reg_t; - -/** Type of out_int_ena_ch1 register - * Interrupt enable bits of TX channel 1 - */ -typedef union { - struct { - /** out_done_ch1_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT - */ - uint32_t out_done_ch1_int_ena:1; - /** out_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT - */ - uint32_t out_eof_ch1_int_ena:1; - /** out_dscr_err_ch1_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT - */ - uint32_t out_dscr_err_ch1_int_ena:1; - /** out_total_eof_ch1_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT - */ - uint32_t out_total_eof_ch1_int_ena:1; - /** outfifo_ovf_ch1_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT - */ - uint32_t outfifo_ovf_ch1_int_ena:1; - /** outfifo_udf_ch1_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT - */ - uint32_t outfifo_udf_ch1_int_ena:1; - /** out_ahbinf_resp_err_ch1_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH1_INT - */ - uint32_t out_ahbinf_resp_err_ch1_int_ena:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_ena_ch1_reg_t; - -/** Type of out_int_clr_ch1 register - * Interrupt clear bits of TX channel 1 - */ -typedef union { - struct { - /** out_done_ch1_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT - */ - uint32_t out_done_ch1_int_clr:1; - /** out_eof_ch1_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT - */ - uint32_t out_eof_ch1_int_clr:1; - /** out_dscr_err_ch1_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT - */ - uint32_t out_dscr_err_ch1_int_clr:1; - /** out_total_eof_ch1_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT - */ - uint32_t out_total_eof_ch1_int_clr:1; - /** outfifo_ovf_ch1_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT - */ - uint32_t outfifo_ovf_ch1_int_clr:1; - /** outfifo_udf_ch1_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT - */ - uint32_t outfifo_udf_ch1_int_clr:1; - /** out_ahbinf_resp_err_ch1_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH1_INT - */ - uint32_t out_ahbinf_resp_err_ch1_int_clr:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_clr_ch1_reg_t; - -/** Type of out_int_raw_ch2 register - * //Raw interrupt status of TX channel 2 - */ -typedef union { - struct { - /** out_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH2_INT - */ - uint32_t out_done_ch2_int_raw:1; - /** out_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH2_INT - */ - uint32_t out_eof_ch2_int_raw:1; - /** out_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT - */ - uint32_t out_dscr_err_ch2_int_raw:1; - /** out_total_eof_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT - */ - uint32_t out_total_eof_ch2_int_raw:1; - /** outfifo_ovf_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT - */ - uint32_t outfifo_ovf_ch2_int_raw:1; - /** outfifo_udf_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT - */ - uint32_t outfifo_udf_ch2_int_raw:1; - /** out_ahbinf_resp_err_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT - */ - uint32_t out_ahbinf_resp_err_ch2_int_raw:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_raw_ch2_reg_t; - -/** Type of out_int_st_ch2 register - * Masked interrupt status of TX channel 2 - */ -typedef union { - struct { - /** out_done_ch2_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH2_INT - */ - uint32_t out_done_ch2_int_st:1; - /** out_eof_ch2_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH2_INT - */ - uint32_t out_eof_ch2_int_st:1; - /** out_dscr_err_ch2_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT - */ - uint32_t out_dscr_err_ch2_int_st:1; - /** out_total_eof_ch2_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT - */ - uint32_t out_total_eof_ch2_int_st:1; - /** outfifo_ovf_ch2_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT - */ - uint32_t outfifo_ovf_ch2_int_st:1; - /** outfifo_udf_ch2_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT - */ - uint32_t outfifo_udf_ch2_int_st:1; - /** out_ahbinf_resp_err_ch2_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT - */ - uint32_t out_ahbinf_resp_err_ch2_int_st:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_st_ch2_reg_t; - -/** Type of out_int_ena_ch2 register - * Interrupt enable bits of TX channel 2 - */ -typedef union { - struct { - /** out_done_ch2_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH2_INT - */ - uint32_t out_done_ch2_int_ena:1; - /** out_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH2_INT - */ - uint32_t out_eof_ch2_int_ena:1; - /** out_dscr_err_ch2_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH2_INT - */ - uint32_t out_dscr_err_ch2_int_ena:1; - /** out_total_eof_ch2_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH2_INT - */ - uint32_t out_total_eof_ch2_int_ena:1; - /** outfifo_ovf_ch2_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH2_INT - */ - uint32_t outfifo_ovf_ch2_int_ena:1; - /** outfifo_udf_ch2_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH2_INT - */ - uint32_t outfifo_udf_ch2_int_ena:1; - /** out_ahbinf_resp_err_ch2_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH2_INT - */ - uint32_t out_ahbinf_resp_err_ch2_int_ena:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_ena_ch2_reg_t; - -/** Type of out_int_clr_ch2 register - * Interrupt clear bits of TX channel 2 - */ -typedef union { - struct { - /** out_done_ch2_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH2_INT - */ - uint32_t out_done_ch2_int_clr:1; - /** out_eof_ch2_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH2_INT - */ - uint32_t out_eof_ch2_int_clr:1; - /** out_dscr_err_ch2_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH2_INT - */ - uint32_t out_dscr_err_ch2_int_clr:1; - /** out_total_eof_ch2_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH2_INT - */ - uint32_t out_total_eof_ch2_int_clr:1; - /** outfifo_ovf_ch2_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH2_INT - */ - uint32_t outfifo_ovf_ch2_int_clr:1; - /** outfifo_udf_ch2_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH2_INT - */ - uint32_t outfifo_udf_ch2_int_clr:1; - /** out_ahbinf_resp_err_ch2_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH2_INT - */ - uint32_t out_ahbinf_resp_err_ch2_int_clr:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ahb_dma_out_int_clr_ch2_reg_t; - -/** Type of ahb_test register - * only for test - */ -typedef union { - struct { - /** ahb_testmode : R/W; bitpos: [2:0]; default: 0; - * reserved - */ - uint32_t ahb_testmode:3; - uint32_t reserved_3:1; - /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0; - * reserved - */ - uint32_t ahb_testaddr:2; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_ahb_test_reg_t; - -/** Type of misc_conf register - * reserved - */ -typedef union { - struct { - /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset the internal AHB FSM - */ - uint32_t ahbm_rst_inter:1; - uint32_t reserved_1:1; - /** arb_pri_dis : R/W; bitpos: [2]; default: 0; - * Configures whether to disable the fixed-priority channel arbitration. - * 0: Enable - * 1: Disable - */ - uint32_t arb_pri_dis:1; - /** clk_en : R/W; bitpos: [3]; default: 0; - * Configures clock gating. - * 0: Support clock only when the application writes registers. - * 1: Always force the clock on for registers. - */ - uint32_t clk_en:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_misc_conf_reg_t; - -/** Type of date register - * Version control register - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 2425376; - * Version control register - */ - uint32_t date:32; - }; - uint32_t val; -} ahb_dma_date_reg_t; - -/** Type of in_conf0_ch0 register - * Configuration register 0 of RX channel 0 - */ -typedef union { - struct { - /** in_rst_ch0 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. - */ - uint32_t in_rst_ch0:1; - /** in_loop_test_ch0 : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t in_loop_test_ch0:1; - /** indscr_burst_en_ch0 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable INCR burst transfer for RX channel 0 to read - * descriptors. - * 0: Disable - * 1: Enable - */ - uint32_t indscr_burst_en_ch0:1; - /** in_data_burst_en_ch0 : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 to enable INCR4 burst transfer for Rx channel 0 receiving data - * when accessing internal SRAM. - */ - uint32_t in_data_burst_en_ch0:1; - /** mem_trans_en_ch0 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable memory-to-memory data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t mem_trans_en_ch0:1; - /** in_etm_en_ch0 : R/W; bitpos: [5]; default: 0; - * Configures whether to enable ETM control for RX channel0. - * 0: Disable - * 1: Enable - */ - uint32_t in_etm_en_ch0:1; - /** in_data_burst_mode_sel_ch0 : R/W; bitpos: [7:6]; default: 1; - * Configures max burst size for Rx channel0. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ - uint32_t in_data_burst_mode_sel_ch0:2; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_conf0_ch0_reg_t; - -/** Type of in_conf1_ch0 register - * Configuration register 1 of RX channel 0 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** in_check_owner_ch0 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for RX channel 0. - * 0: Disable - * 1: Enable - */ - uint32_t in_check_owner_ch0:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_in_conf1_ch0_reg_t; - -/** Type of infifo_status_ch0 register - * Receive FIFO status of RX channel 0 - */ -typedef union { - struct { - /** infifo_full_ch0 : RO; bitpos: [0]; default: 1; - * Represents whether L1 RX FIFO is full. - * 0: Not Full - * 1: Full - */ - uint32_t infifo_full_ch0:1; - /** infifo_empty_ch0 : RO; bitpos: [1]; default: 1; - * Represents whether L1 RX FIFO is empty. - * 0: Not empty - * 1: Empty - */ - uint32_t infifo_empty_ch0:1; - uint32_t reserved_2:6; - /** infifo_cnt_ch0 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 0 - */ - uint32_t infifo_cnt_ch0:7; - uint32_t reserved_15:8; - /** in_remain_under_1b_ch0 : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t in_remain_under_1b_ch0:1; - /** in_remain_under_2b_ch0 : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t in_remain_under_2b_ch0:1; - /** in_remain_under_3b_ch0 : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t in_remain_under_3b_ch0:1; - /** in_remain_under_4b_ch0 : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t in_remain_under_4b_ch0:1; - /** in_buf_hungry_ch0 : RO; bitpos: [27]; default: 0; - * reserved - */ - uint32_t in_buf_hungry_ch0:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} ahb_dma_infifo_status_ch0_reg_t; - -/** Type of in_pop_ch0 register - * Receive FIFO status of RX channel 0 - */ -typedef union { - struct { - /** infifo_rdata_ch0 : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB_DMA FIFO. - */ - uint32_t infifo_rdata_ch0:12; - /** infifo_pop_ch0 : WT; bitpos: [12]; default: 0; - * Configures whether to pop data from AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Pop - */ - uint32_t infifo_pop_ch0:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_in_pop_ch0_reg_t; - -/** Type of in_link_ch0 register - * Receive FIFO status of RX channel 0 - */ -typedef union { - struct { - /** inlink_auto_ret_ch0 : R/W; bitpos: [0]; default: 1; - * Configures whether to return to current receive descriptor's address when there are - * some errors in current receiving data. - * 0: Not return - * 1: Return - * . - */ - uint32_t inlink_auto_ret_ch0:1; - /** inlink_stop_ch0 : WT; bitpos: [1]; default: 0; - * Configures whether to stop AHB_DMA's RX channel 0 from receiving data. - * 0: Invalid. No effect - * 1: Stop - */ - uint32_t inlink_stop_ch0:1; - /** inlink_start_ch0 : WT; bitpos: [2]; default: 0; - * Configures whether to enable AHB_DMA's RX channel 0 for data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t inlink_start_ch0:1; - /** inlink_restart_ch0 : WT; bitpos: [3]; default: 0; - * Configures whether to restart RX channel 0 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ - uint32_t inlink_restart_ch0:1; - /** inlink_park_ch0 : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM. - * 0: Running - * 1: Idle - */ - uint32_t inlink_park_ch0:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} ahb_dma_in_link_ch0_reg_t; - -/** Type of in_state_ch0 register - * Receive status of RX channel 0 - */ -typedef union { - struct { - /** inlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0; - * reserved - */ - uint32_t inlink_dscr_addr_ch0:18; - /** in_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t in_dscr_state_ch0:2; - /** in_state_ch0 : RO; bitpos: [22:20]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. - */ - uint32_t in_state_ch0:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} ahb_dma_in_state_ch0_reg_t; - -/** Type of in_suc_eof_des_addr_ch0 register - * Receive descriptor address when EOF occurs on RX channel 0 - */ -typedef union { - struct { - /** in_suc_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_in_suc_eof_des_addr_ch0_reg_t; - -/** Type of in_err_eof_des_addr_ch0 register - * Receive descriptor address when errors occur of RX channel 0 - */ -typedef union { - struct { - /** in_err_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when there are some errors in the - * currently received data. - */ - uint32_t in_err_eof_des_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_in_err_eof_des_addr_ch0_reg_t; - -/** Type of in_dscr_ch0 register - * Current receive descriptor address of RX channel 0 - */ -typedef union { - struct { - /** inlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that has already been fetched. - */ - uint32_t inlink_dscr_ch0:32; - }; - uint32_t val; -} ahb_dma_in_dscr_ch0_reg_t; - -/** Type of in_dscr_bf0_ch0 register - * The last receive descriptor address of RX channel 0 - */ -typedef union { - struct { - /** inlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that has already been - * fetched. - */ - uint32_t inlink_dscr_bf0_ch0:32; - }; - uint32_t val; -} ahb_dma_in_dscr_bf0_ch0_reg_t; - -/** Type of in_dscr_bf1_ch0 register - * The second-to-last receive descriptor address of RX channel 0 - */ -typedef union { - struct { - /** inlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that has already been - * fetched. - */ - uint32_t inlink_dscr_bf1_ch0:32; - }; - uint32_t val; -} ahb_dma_in_dscr_bf1_ch0_reg_t; - -/** Type of in_peri_ch0 register - * Priority register of RX channel 0 - */ -typedef union { - struct { - /** rx_pri_ch0 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel 0.The larger of the value, the higher of the - * priority.. - */ - uint32_t rx_pri_ch0:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_in_peri_ch0_reg_t; - -/** Type of in_peri_sel_ch0 register - * Peripheral selection register of RX channel 0 - */ -typedef union { - struct { - /** peri_in_sel_ch0 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel 0. - * 0: I3C - * 1: Dummy - * 2: UHCI0 - * 3: I2S0 - * 4: I2S1 - * 5: I2S2 - * 6: Dummy - * 7: Dummy - * 8: ADC_DAC - * 9: Dummy - * 10: RMT - * 11~15: Dummy - */ - uint32_t peri_in_sel_ch0:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_in_peri_sel_ch0_reg_t; - -/** Type of out_conf0_ch0 register - * Configuration register 0 of TX channel 0 - */ -typedef union { - struct { - /** out_rst_ch0 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer. - * 0: Release reset - * 1: Reset - */ - uint32_t out_rst_ch0:1; - /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t out_loop_test_ch0:1; - /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable automatic outlink write-back when all the data in TX - * FIFO has been transmitted. - * 0: Disable - * 1: Enable - */ - uint32_t out_auto_wrback_ch0:1; - /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag. - * 0: EOF flag for TX channel 0 is generated when data to be transmitted has been - * pushed into FIFO in AHB_DMA. - * 1: EOF flag for TX channel 0 is generated when data to be transmitted has been - * popped from FIFO in AHB_DMA. - */ - uint32_t out_eof_mode_ch0:1; - /** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable INCR burst transfer for TX channel 0 reading - * descriptors. - * 0: Disable - * 1: Enable - */ - uint32_t outdscr_burst_en_ch0:1; - /** out_data_burst_en_ch0 : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable INCR4 burst transfer for Tx channel 0 transmitting data - * when accessing internal SRAM. - */ - uint32_t out_data_burst_en_ch0:1; - /** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0; - * Configures whether to enable ETM control for TX channel 0. - * 0: Disable - * 1: Enable - */ - uint32_t out_etm_en_ch0:1; - uint32_t reserved_7:1; - /** out_data_burst_mode_sel_ch0 : R/W; bitpos: [9:8]; default: 1; - * Configures max burst size for TX channel0. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ - uint32_t out_data_burst_mode_sel_ch0:2; - uint32_t reserved_10:22; - }; - uint32_t val; -} ahb_dma_out_conf0_ch0_reg_t; - -/** Type of out_conf1_ch0 register - * Configuration register 1 of TX channel 0 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** out_check_owner_ch0 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for TX channel 0. - * 0: Disable - * 1: Enable - */ - uint32_t out_check_owner_ch0:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_out_conf1_ch0_reg_t; - -/** Type of outfifo_status_ch0 register - * Receive FIFO status of RX channel 0 - */ -typedef union { - struct { - /** outfifo_full_ch0 : RO; bitpos: [0]; default: 0; - * Represents whether L1 TX FIFO is full. - * 0: Not Full - * 1: Full - */ - uint32_t outfifo_full_ch0:1; - /** outfifo_empty_ch0 : RO; bitpos: [1]; default: 1; - * Represents whether L1 TX FIFO is empty. - * 0: Not empty - * 1: Empty - */ - uint32_t outfifo_empty_ch0:1; - uint32_t reserved_2:6; - /** outfifo_cnt_ch0 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 0 - */ - uint32_t outfifo_cnt_ch0:7; - uint32_t reserved_15:8; - /** out_remain_under_1b_ch0 : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t out_remain_under_1b_ch0:1; - /** out_remain_under_2b_ch0 : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t out_remain_under_2b_ch0:1; - /** out_remain_under_3b_ch0 : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t out_remain_under_3b_ch0:1; - /** out_remain_under_4b_ch0 : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t out_remain_under_4b_ch0:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} ahb_dma_outfifo_status_ch0_reg_t; - -/** Type of out_push_ch0 register - * Push control register of TX channel 0 - */ -typedef union { - struct { - /** outfifo_wdata_ch0 : R/W; bitpos: [8:0]; default: 0; - * Configures whether to push data into AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Push - */ - uint32_t outfifo_wdata_ch0:9; - /** outfifo_push_ch0 : WT; bitpos: [9]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. - */ - uint32_t outfifo_push_ch0:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} ahb_dma_out_push_ch0_reg_t; - -/** Type of out_link_ch0 register - * Push control register of TX channel 0 - */ -typedef union { - struct { - /** outlink_stop_ch0 : WT; bitpos: [0]; default: 0; - * Configures whether to stop AHB_DMA's TX channel 0 from transmitting data. - * 0: Invalid. No effect - * 1: Stop - */ - uint32_t outlink_stop_ch0:1; - /** outlink_start_ch0 : WT; bitpos: [1]; default: 0; - * Configures whether to enable AHB_DMA's TX channel 0 for data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t outlink_start_ch0:1; - /** outlink_restart_ch0 : WT; bitpos: [2]; default: 0; - * Configures whether to restart TX channel 0 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ - uint32_t outlink_restart_ch0:1; - /** outlink_park_ch0 : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM. - * 0: Running - * 1: Idle - */ - uint32_t outlink_park_ch0:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_out_link_ch0_reg_t; - -/** Type of out_state_ch0 register - * Transmit status of TX channel 0 - */ -typedef union { - struct { - /** outlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the address of the next transmit descriptor to be - * processed. - */ - uint32_t outlink_dscr_addr_ch0:18; - /** out_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t out_dscr_state_ch0:2; - /** out_state_ch0 : RO; bitpos: [22:20]; default: 0; - * reserved - */ - uint32_t out_state_ch0:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} ahb_dma_out_state_ch0_reg_t; - -/** Type of out_eof_des_addr_ch0 register - * Transmit descriptor address when EOF occurs on TX channel 0 - */ -typedef union { - struct { - /** out_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_out_eof_des_addr_ch0_reg_t; - -/** Type of out_eof_bfr_des_addr_ch0 register - * The last transmit descriptor address when EOF occurs on TX channel 0 - */ -typedef union { - struct { - /** out_eof_bfr_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor before the last transmit - * descriptor. - */ - uint32_t out_eof_bfr_des_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_out_eof_bfr_des_addr_ch0_reg_t; - -/** Type of out_dscr_ch0 register - * Current transmit descriptor address of TX channel 0 - */ -typedef union { - struct { - /** outlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that has already been fetched. - */ - uint32_t outlink_dscr_ch0:32; - }; - uint32_t val; -} ahb_dma_out_dscr_ch0_reg_t; - -/** Type of out_dscr_bf0_ch0 register - * The last transmit descriptor address of TX channel 0 - */ -typedef union { - struct { - /** outlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that has already been - * fetched. - */ - uint32_t outlink_dscr_bf0_ch0:32; - }; - uint32_t val; -} ahb_dma_out_dscr_bf0_ch0_reg_t; - -/** Type of out_dscr_bf1_ch0 register - * The second-to-last transmit descriptor address of TX channel 0 - */ -typedef union { - struct { - /** outlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that has already - * been fetched. - */ - uint32_t outlink_dscr_bf1_ch0:32; - }; - uint32_t val; -} ahb_dma_out_dscr_bf1_ch0_reg_t; - -/** Type of out_peri_ch0 register - * Priority register of TX channel 0 - */ -typedef union { - struct { - /** tx_pri_ch0 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel 0.The larger of the value, the higher of the - * priority.. - */ - uint32_t tx_pri_ch0:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_out_peri_ch0_reg_t; - -/** Type of out_peri_sel_ch0 register - * Peripheral selection register of TX channel 0 - */ -typedef union { - struct { - /** peri_out_sel_ch0 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel 0. - * 0: I3C - * 1: Dummy - * 2: UHCI0 - * 3: I2S0 - * 4: I2S1 - * 5: I2S2 - * 6: Dummy - * 7: Dummy - * 8: ADC_DAC - * 9: Dummy - * 10: RMT - * 11~15: Dummy - */ - uint32_t peri_out_sel_ch0:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_out_peri_sel_ch0_reg_t; - -/** Type of in_conf0_ch1 register - * Configuration register 0 of RX channel 1 - */ -typedef union { - struct { - /** in_rst_ch1 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 1 RX FSM and RX FIFO pointer. - */ - uint32_t in_rst_ch1:1; - /** in_loop_test_ch1 : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t in_loop_test_ch1:1; - /** indscr_burst_en_ch1 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable INCR burst transfer for RX channel 1 to read - * descriptors. - * 0: Disable - * 1: Enable - */ - uint32_t indscr_burst_en_ch1:1; - /** in_data_burst_en_ch1 : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 to enable INCR4 burst transfer for Rx channel 1 receiving data - * when accessing internal SRAM. - */ - uint32_t in_data_burst_en_ch1:1; - /** mem_trans_en_ch1 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable memory-to-memory data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t mem_trans_en_ch1:1; - /** in_etm_en_ch1 : R/W; bitpos: [5]; default: 0; - * Configures whether to enable ETM control for RX channel1. - * 0: Disable - * 1: Enable - */ - uint32_t in_etm_en_ch1:1; - /** in_data_burst_mode_sel_ch1 : R/W; bitpos: [7:6]; default: 1; - * Configures max burst size for Rx channel1. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ - uint32_t in_data_burst_mode_sel_ch1:2; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_conf0_ch1_reg_t; - -/** Type of in_conf1_ch1 register - * Configuration register 1 of RX channel 1 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** in_check_owner_ch1 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for RX channel 1. - * 0: Disable - * 1: Enable - */ - uint32_t in_check_owner_ch1:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_in_conf1_ch1_reg_t; - -/** Type of infifo_status_ch1 register - * Receive FIFO status of RX channel 1 - */ -typedef union { - struct { - /** infifo_full_ch1 : RO; bitpos: [0]; default: 1; - * Represents whether L1 RX FIFO is full. - * 0: Not Full - * 1: Full - */ - uint32_t infifo_full_ch1:1; - /** infifo_empty_ch1 : RO; bitpos: [1]; default: 1; - * Represents whether L1 RX FIFO is empty. - * 0: Not empty - * 1: Empty - */ - uint32_t infifo_empty_ch1:1; - uint32_t reserved_2:6; - /** infifo_cnt_ch1 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 1 - */ - uint32_t infifo_cnt_ch1:7; - uint32_t reserved_15:8; - /** in_remain_under_1b_ch1 : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t in_remain_under_1b_ch1:1; - /** in_remain_under_2b_ch1 : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t in_remain_under_2b_ch1:1; - /** in_remain_under_3b_ch1 : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t in_remain_under_3b_ch1:1; - /** in_remain_under_4b_ch1 : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t in_remain_under_4b_ch1:1; - /** in_buf_hungry_ch1 : RO; bitpos: [27]; default: 0; - * reserved - */ - uint32_t in_buf_hungry_ch1:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} ahb_dma_infifo_status_ch1_reg_t; - -/** Type of in_pop_ch1 register - * Receive FIFO status of RX channel 1 - */ -typedef union { - struct { - /** infifo_rdata_ch1 : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB_DMA FIFO. - */ - uint32_t infifo_rdata_ch1:12; - /** infifo_pop_ch1 : WT; bitpos: [12]; default: 0; - * Configures whether to pop data from AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Pop - */ - uint32_t infifo_pop_ch1:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_in_pop_ch1_reg_t; - -/** Type of in_link_ch1 register - * Receive FIFO status of RX channel 1 - */ -typedef union { - struct { - /** inlink_auto_ret_ch1 : R/W; bitpos: [0]; default: 1; - * Configures whether to return to current receive descriptor's address when there are - * some errors in current receiving data. - * 0: Not return - * 1: Return - * . - */ - uint32_t inlink_auto_ret_ch1:1; - /** inlink_stop_ch1 : WT; bitpos: [1]; default: 0; - * Configures whether to stop AHB_DMA's RX channel 1 from receiving data. - * 0: Invalid. No effect - * 1: Stop - */ - uint32_t inlink_stop_ch1:1; - /** inlink_start_ch1 : WT; bitpos: [2]; default: 0; - * Configures whether to enable AHB_DMA's RX channel 1 for data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t inlink_start_ch1:1; - /** inlink_restart_ch1 : WT; bitpos: [3]; default: 0; - * Configures whether to restart RX channel 1 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ - uint32_t inlink_restart_ch1:1; - /** inlink_park_ch1 : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM. - * 0: Running - * 1: Idle - */ - uint32_t inlink_park_ch1:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} ahb_dma_in_link_ch1_reg_t; - -/** Type of in_state_ch1 register - * Receive status of RX channel 1 - */ -typedef union { - struct { - /** inlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0; - * reserved - */ - uint32_t inlink_dscr_addr_ch1:18; - /** in_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t in_dscr_state_ch1:2; - /** in_state_ch1 : RO; bitpos: [22:20]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. - */ - uint32_t in_state_ch1:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} ahb_dma_in_state_ch1_reg_t; - -/** Type of in_suc_eof_des_addr_ch1 register - * Receive descriptor address when EOF occurs on RX channel 1 - */ -typedef union { - struct { - /** in_suc_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_in_suc_eof_des_addr_ch1_reg_t; - -/** Type of in_err_eof_des_addr_ch1 register - * Receive descriptor address when errors occur of RX channel 1 - */ -typedef union { - struct { - /** in_err_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when there are some errors in the - * currently received data. - */ - uint32_t in_err_eof_des_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_in_err_eof_des_addr_ch1_reg_t; - -/** Type of in_dscr_ch1 register - * Current receive descriptor address of RX channel 1 - */ -typedef union { - struct { - /** inlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that has already been fetched. - */ - uint32_t inlink_dscr_ch1:32; - }; - uint32_t val; -} ahb_dma_in_dscr_ch1_reg_t; - -/** Type of in_dscr_bf0_ch1 register - * The last receive descriptor address of RX channel 1 - */ -typedef union { - struct { - /** inlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that has already been - * fetched. - */ - uint32_t inlink_dscr_bf0_ch1:32; - }; - uint32_t val; -} ahb_dma_in_dscr_bf0_ch1_reg_t; - -/** Type of in_dscr_bf1_ch1 register - * The second-to-last receive descriptor address of RX channel 1 - */ -typedef union { - struct { - /** inlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that has already been - * fetched. - */ - uint32_t inlink_dscr_bf1_ch1:32; - }; - uint32_t val; -} ahb_dma_in_dscr_bf1_ch1_reg_t; - -/** Type of in_peri_ch1 register - * Priority register of RX channel 1 - */ -typedef union { - struct { - /** rx_pri_ch1 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel 1.The larger of the value, the higher of the - * priority.. - */ - uint32_t rx_pri_ch1:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_in_peri_ch1_reg_t; - -/** Type of in_peri_sel_ch1 register - * Peripheral selection register of RX channel 1 - */ -typedef union { - struct { - /** peri_in_sel_ch1 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel 1. - * 0: I3C - * 1: Dummy - * 2: UHCI0 - * 3: I2S0 - * 4: I2S1 - * 5: I2S2 - * 6: Dummy - * 7: Dummy - * 8: ADC_DAC - * 9: Dummy - * 10: RMT - * 11~15: Dummy - */ - uint32_t peri_in_sel_ch1:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_in_peri_sel_ch1_reg_t; - -/** Type of out_conf0_ch1 register - * Configuration register 0 of TX channel 1 - */ -typedef union { - struct { - /** out_rst_ch1 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer. - * 0: Release reset - * 1: Reset - */ - uint32_t out_rst_ch1:1; - /** out_loop_test_ch1 : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t out_loop_test_ch1:1; - /** out_auto_wrback_ch1 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable automatic outlink write-back when all the data in TX - * FIFO has been transmitted. - * 0: Disable - * 1: Enable - */ - uint32_t out_auto_wrback_ch1:1; - /** out_eof_mode_ch1 : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag. - * 0: EOF flag for TX channel 1 is generated when data to be transmitted has been - * pushed into FIFO in AHB_DMA. - * 1: EOF flag for TX channel 1 is generated when data to be transmitted has been - * popped from FIFO in AHB_DMA. - */ - uint32_t out_eof_mode_ch1:1; - /** outdscr_burst_en_ch1 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable INCR burst transfer for TX channel 1 reading - * descriptors. - * 0: Disable - * 1: Enable - */ - uint32_t outdscr_burst_en_ch1:1; - /** out_data_burst_en_ch1 : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data - * when accessing internal SRAM. - */ - uint32_t out_data_burst_en_ch1:1; - /** out_etm_en_ch1 : R/W; bitpos: [6]; default: 0; - * Configures whether to enable ETM control for TX channel 1. - * 0: Disable - * 1: Enable - */ - uint32_t out_etm_en_ch1:1; - uint32_t reserved_7:1; - /** out_data_burst_mode_sel_ch1 : R/W; bitpos: [9:8]; default: 1; - * Configures max burst size for TX channel1. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ - uint32_t out_data_burst_mode_sel_ch1:2; - uint32_t reserved_10:22; - }; - uint32_t val; -} ahb_dma_out_conf0_ch1_reg_t; - -/** Type of out_conf1_ch1 register - * Configuration register 1 of TX channel 1 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** out_check_owner_ch1 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for TX channel 1. - * 0: Disable - * 1: Enable - */ - uint32_t out_check_owner_ch1:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_out_conf1_ch1_reg_t; - -/** Type of outfifo_status_ch1 register - * Receive FIFO status of RX channel 1 - */ -typedef union { - struct { - /** outfifo_full_ch1 : RO; bitpos: [0]; default: 0; - * Represents whether L1 TX FIFO is full. - * 0: Not Full - * 1: Full - */ - uint32_t outfifo_full_ch1:1; - /** outfifo_empty_ch1 : RO; bitpos: [1]; default: 1; - * Represents whether L1 TX FIFO is empty. - * 0: Not empty - * 1: Empty - */ - uint32_t outfifo_empty_ch1:1; - uint32_t reserved_2:6; - /** outfifo_cnt_ch1 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 1 - */ - uint32_t outfifo_cnt_ch1:7; - uint32_t reserved_15:8; - /** out_remain_under_1b_ch1 : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t out_remain_under_1b_ch1:1; - /** out_remain_under_2b_ch1 : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t out_remain_under_2b_ch1:1; - /** out_remain_under_3b_ch1 : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t out_remain_under_3b_ch1:1; - /** out_remain_under_4b_ch1 : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t out_remain_under_4b_ch1:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} ahb_dma_outfifo_status_ch1_reg_t; - -/** Type of out_push_ch1 register - * Push control register of TX channel 1 - */ -typedef union { - struct { - /** outfifo_wdata_ch1 : R/W; bitpos: [8:0]; default: 0; - * Configures whether to push data into AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Push - */ - uint32_t outfifo_wdata_ch1:9; - /** outfifo_push_ch1 : WT; bitpos: [9]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. - */ - uint32_t outfifo_push_ch1:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} ahb_dma_out_push_ch1_reg_t; - -/** Type of out_link_ch1 register - * Push control register of TX channel 1 - */ -typedef union { - struct { - /** outlink_stop_ch1 : WT; bitpos: [0]; default: 0; - * Configures whether to stop AHB_DMA's TX channel 1 from transmitting data. - * 0: Invalid. No effect - * 1: Stop - */ - uint32_t outlink_stop_ch1:1; - /** outlink_start_ch1 : WT; bitpos: [1]; default: 0; - * Configures whether to enable AHB_DMA's TX channel 1 for data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t outlink_start_ch1:1; - /** outlink_restart_ch1 : WT; bitpos: [2]; default: 0; - * Configures whether to restart TX channel 1 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ - uint32_t outlink_restart_ch1:1; - /** outlink_park_ch1 : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM. - * 0: Running - * 1: Idle - */ - uint32_t outlink_park_ch1:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_out_link_ch1_reg_t; - -/** Type of out_state_ch1 register - * Transmit status of TX channel 1 - */ -typedef union { - struct { - /** outlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the address of the next transmit descriptor to be - * processed. - */ - uint32_t outlink_dscr_addr_ch1:18; - /** out_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t out_dscr_state_ch1:2; - /** out_state_ch1 : RO; bitpos: [22:20]; default: 0; - * reserved - */ - uint32_t out_state_ch1:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} ahb_dma_out_state_ch1_reg_t; - -/** Type of out_eof_des_addr_ch1 register - * Transmit descriptor address when EOF occurs on TX channel 1 - */ -typedef union { - struct { - /** out_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_out_eof_des_addr_ch1_reg_t; - -/** Type of out_eof_bfr_des_addr_ch1 register - * The last transmit descriptor address when EOF occurs on TX channel 1 - */ -typedef union { - struct { - /** out_eof_bfr_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor before the last transmit - * descriptor. - */ - uint32_t out_eof_bfr_des_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_out_eof_bfr_des_addr_ch1_reg_t; - -/** Type of out_dscr_ch1 register - * Current transmit descriptor address of TX channel 1 - */ -typedef union { - struct { - /** outlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that has already been fetched. - */ - uint32_t outlink_dscr_ch1:32; - }; - uint32_t val; -} ahb_dma_out_dscr_ch1_reg_t; - -/** Type of out_dscr_bf0_ch1 register - * The last transmit descriptor address of TX channel 1 - */ -typedef union { - struct { - /** outlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that has already been - * fetched. - */ - uint32_t outlink_dscr_bf0_ch1:32; - }; - uint32_t val; -} ahb_dma_out_dscr_bf0_ch1_reg_t; - -/** Type of out_dscr_bf1_ch1 register - * The second-to-last transmit descriptor address of TX channel 1 - */ -typedef union { - struct { - /** outlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that has already - * been fetched. - */ - uint32_t outlink_dscr_bf1_ch1:32; - }; - uint32_t val; -} ahb_dma_out_dscr_bf1_ch1_reg_t; - -/** Type of out_peri_ch1 register - * Priority register of TX channel 1 - */ -typedef union { - struct { - /** tx_pri_ch1 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel 1.The larger of the value, the higher of the - * priority.. - */ - uint32_t tx_pri_ch1:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_out_peri_ch1_reg_t; - -/** Type of out_peri_sel_ch1 register - * Peripheral selection register of TX channel 1 - */ -typedef union { - struct { - /** peri_out_sel_ch1 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel 1. - * 0: I3C - * 1: Dummy - * 2: UHCI0 - * 3: I2S0 - * 4: I2S1 - * 5: I2S2 - * 6: Dummy - * 7: Dummy - * 8: ADC_DAC - * 9: Dummy - * 10: RMT - * 11~15: Dummy - */ - uint32_t peri_out_sel_ch1:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_out_peri_sel_ch1_reg_t; - -/** Type of in_conf0_ch2 register - * Configuration register 0 of RX channel 2 - */ -typedef union { - struct { - /** in_rst_ch2 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 2 RX FSM and RX FIFO pointer. - */ - uint32_t in_rst_ch2:1; - /** in_loop_test_ch2 : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t in_loop_test_ch2:1; - /** indscr_burst_en_ch2 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable INCR burst transfer for RX channel 2 to read - * descriptors. - * 0: Disable - * 1: Enable - */ - uint32_t indscr_burst_en_ch2:1; - /** in_data_burst_en_ch2 : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 to enable INCR4 burst transfer for Rx channel 2 receiving data - * when accessing internal SRAM. - */ - uint32_t in_data_burst_en_ch2:1; - /** mem_trans_en_ch2 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable memory-to-memory data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t mem_trans_en_ch2:1; - /** in_etm_en_ch2 : R/W; bitpos: [5]; default: 0; - * Configures whether to enable ETM control for RX channel2. - * 0: Disable - * 1: Enable - */ - uint32_t in_etm_en_ch2:1; - /** in_data_burst_mode_sel_ch2 : R/W; bitpos: [7:6]; default: 1; - * Configures max burst size for Rx channel2. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ - uint32_t in_data_burst_mode_sel_ch2:2; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_in_conf0_ch2_reg_t; - -/** Type of in_conf1_ch2 register - * Configuration register 1 of RX channel 2 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** in_check_owner_ch2 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for RX channel 2. - * 0: Disable - * 1: Enable - */ - uint32_t in_check_owner_ch2:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_in_conf1_ch2_reg_t; - -/** Type of infifo_status_ch2 register - * Receive FIFO status of RX channel 2 - */ -typedef union { - struct { - /** infifo_full_ch2 : RO; bitpos: [0]; default: 1; - * Represents whether L1 RX FIFO is full. - * 0: Not Full - * 1: Full - */ - uint32_t infifo_full_ch2:1; - /** infifo_empty_ch2 : RO; bitpos: [1]; default: 1; - * Represents whether L1 RX FIFO is empty. - * 0: Not empty - * 1: Empty - */ - uint32_t infifo_empty_ch2:1; - uint32_t reserved_2:6; - /** infifo_cnt_ch2 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 2 - */ - uint32_t infifo_cnt_ch2:7; - uint32_t reserved_15:8; - /** in_remain_under_1b_ch2 : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t in_remain_under_1b_ch2:1; - /** in_remain_under_2b_ch2 : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t in_remain_under_2b_ch2:1; - /** in_remain_under_3b_ch2 : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t in_remain_under_3b_ch2:1; - /** in_remain_under_4b_ch2 : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t in_remain_under_4b_ch2:1; - /** in_buf_hungry_ch2 : RO; bitpos: [27]; default: 0; - * reserved - */ - uint32_t in_buf_hungry_ch2:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} ahb_dma_infifo_status_ch2_reg_t; - -/** Type of in_pop_ch2 register - * Receive FIFO status of RX channel 2 - */ -typedef union { - struct { - /** infifo_rdata_ch2 : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB_DMA FIFO. - */ - uint32_t infifo_rdata_ch2:12; - /** infifo_pop_ch2 : WT; bitpos: [12]; default: 0; - * Configures whether to pop data from AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Pop - */ - uint32_t infifo_pop_ch2:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_in_pop_ch2_reg_t; - -/** Type of in_link_ch2 register - * Receive FIFO status of RX channel 2 - */ -typedef union { - struct { - /** inlink_auto_ret_ch2 : R/W; bitpos: [0]; default: 1; - * Configures whether to return to current receive descriptor's address when there are - * some errors in current receiving data. - * 0: Not return - * 1: Return - * . - */ - uint32_t inlink_auto_ret_ch2:1; - /** inlink_stop_ch2 : WT; bitpos: [1]; default: 0; - * Configures whether to stop AHB_DMA's RX channel 2 from receiving data. - * 0: Invalid. No effect - * 1: Stop - */ - uint32_t inlink_stop_ch2:1; - /** inlink_start_ch2 : WT; bitpos: [2]; default: 0; - * Configures whether to enable AHB_DMA's RX channel 2 for data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t inlink_start_ch2:1; - /** inlink_restart_ch2 : WT; bitpos: [3]; default: 0; - * Configures whether to restart RX channel 2 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ - uint32_t inlink_restart_ch2:1; - /** inlink_park_ch2 : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM. - * 0: Running - * 1: Idle - */ - uint32_t inlink_park_ch2:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} ahb_dma_in_link_ch2_reg_t; - -/** Type of in_state_ch2 register - * Receive status of RX channel 2 - */ -typedef union { - struct { - /** inlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0; - * reserved - */ - uint32_t inlink_dscr_addr_ch2:18; - /** in_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t in_dscr_state_ch2:2; - /** in_state_ch2 : RO; bitpos: [22:20]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. - */ - uint32_t in_state_ch2:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} ahb_dma_in_state_ch2_reg_t; - -/** Type of in_suc_eof_des_addr_ch2 register - * Receive descriptor address when EOF occurs on RX channel 2 - */ -typedef union { - struct { - /** in_suc_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_in_suc_eof_des_addr_ch2_reg_t; - -/** Type of in_err_eof_des_addr_ch2 register - * Receive descriptor address when errors occur of RX channel 2 - */ -typedef union { - struct { - /** in_err_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when there are some errors in the - * currently received data. - */ - uint32_t in_err_eof_des_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_in_err_eof_des_addr_ch2_reg_t; - -/** Type of in_dscr_ch2 register - * Current receive descriptor address of RX channel 2 - */ -typedef union { - struct { - /** inlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that has already been fetched. - */ - uint32_t inlink_dscr_ch2:32; - }; - uint32_t val; -} ahb_dma_in_dscr_ch2_reg_t; - -/** Type of in_dscr_bf0_ch2 register - * The last receive descriptor address of RX channel 2 - */ -typedef union { - struct { - /** inlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that has already been - * fetched. - */ - uint32_t inlink_dscr_bf0_ch2:32; - }; - uint32_t val; -} ahb_dma_in_dscr_bf0_ch2_reg_t; - -/** Type of in_dscr_bf1_ch2 register - * The second-to-last receive descriptor address of RX channel 2 - */ -typedef union { - struct { - /** inlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that has already been - * fetched. - */ - uint32_t inlink_dscr_bf1_ch2:32; - }; - uint32_t val; -} ahb_dma_in_dscr_bf1_ch2_reg_t; - -/** Type of in_peri_ch2 register - * Priority register of RX channel 2 - */ -typedef union { - struct { - /** rx_pri_ch2 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel 2.The larger of the value, the higher of the - * priority.. - */ - uint32_t rx_pri_ch2:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_in_peri_ch2_reg_t; - -/** Type of in_peri_sel_ch2 register - * Peripheral selection register of RX channel 2 - */ -typedef union { - struct { - /** peri_in_sel_ch2 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel 2. - * 0: I3C - * 1: Dummy - * 2: UHCI0 - * 3: I2S0 - * 4: I2S1 - * 5: I2S2 - * 6: Dummy - * 7: Dummy - * 8: ADC_DAC - * 9: Dummy - * 10: RMT - * 11~15: Dummy - */ - uint32_t peri_in_sel_ch2:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_in_peri_sel_ch2_reg_t; - -/** Type of out_conf0_ch2 register - * Configuration register 0 of TX channel 2 - */ -typedef union { - struct { - /** out_rst_ch2 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 2 TX FSM and TX FIFO pointer. - * 0: Release reset - * 1: Reset - */ - uint32_t out_rst_ch2:1; - /** out_loop_test_ch2 : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t out_loop_test_ch2:1; - /** out_auto_wrback_ch2 : R/W; bitpos: [2]; default: 0; - * Configures whether to enable automatic outlink write-back when all the data in TX - * FIFO has been transmitted. - * 0: Disable - * 1: Enable - */ - uint32_t out_auto_wrback_ch2:1; - /** out_eof_mode_ch2 : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag. - * 0: EOF flag for TX channel 2 is generated when data to be transmitted has been - * pushed into FIFO in AHB_DMA. - * 1: EOF flag for TX channel 2 is generated when data to be transmitted has been - * popped from FIFO in AHB_DMA. - */ - uint32_t out_eof_mode_ch2:1; - /** outdscr_burst_en_ch2 : R/W; bitpos: [4]; default: 0; - * Configures whether to enable INCR burst transfer for TX channel 2 reading - * descriptors. - * 0: Disable - * 1: Enable - */ - uint32_t outdscr_burst_en_ch2:1; - /** out_data_burst_en_ch2 : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data - * when accessing internal SRAM. - */ - uint32_t out_data_burst_en_ch2:1; - /** out_etm_en_ch2 : R/W; bitpos: [6]; default: 0; - * Configures whether to enable ETM control for TX channel 2. - * 0: Disable - * 1: Enable - */ - uint32_t out_etm_en_ch2:1; - uint32_t reserved_7:1; - /** out_data_burst_mode_sel_ch2 : R/W; bitpos: [9:8]; default: 1; - * Configures max burst size for TX channel2. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 - */ - uint32_t out_data_burst_mode_sel_ch2:2; - uint32_t reserved_10:22; - }; - uint32_t val; -} ahb_dma_out_conf0_ch2_reg_t; - -/** Type of out_conf1_ch2 register - * Configuration register 1 of TX channel 2 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** out_check_owner_ch2 : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for TX channel 2. - * 0: Disable - * 1: Enable - */ - uint32_t out_check_owner_ch2:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} ahb_dma_out_conf1_ch2_reg_t; - -/** Type of outfifo_status_ch2 register - * Receive FIFO status of RX channel 2 - */ -typedef union { - struct { - /** outfifo_full_ch2 : RO; bitpos: [0]; default: 0; - * Represents whether L1 TX FIFO is full. - * 0: Not Full - * 1: Full - */ - uint32_t outfifo_full_ch2:1; - /** outfifo_empty_ch2 : RO; bitpos: [1]; default: 1; - * Represents whether L1 TX FIFO is empty. - * 0: Not empty - * 1: Empty - */ - uint32_t outfifo_empty_ch2:1; - uint32_t reserved_2:6; - /** outfifo_cnt_ch2 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 2 - */ - uint32_t outfifo_cnt_ch2:7; - uint32_t reserved_15:8; - /** out_remain_under_1b_ch2 : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t out_remain_under_1b_ch2:1; - /** out_remain_under_2b_ch2 : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t out_remain_under_2b_ch2:1; - /** out_remain_under_3b_ch2 : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t out_remain_under_3b_ch2:1; - /** out_remain_under_4b_ch2 : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t out_remain_under_4b_ch2:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} ahb_dma_outfifo_status_ch2_reg_t; - -/** Type of out_push_ch2 register - * Push control register of TX channel 2 - */ -typedef union { - struct { - /** outfifo_wdata_ch2 : R/W; bitpos: [8:0]; default: 0; - * Configures whether to push data into AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Push - */ - uint32_t outfifo_wdata_ch2:9; - /** outfifo_push_ch2 : WT; bitpos: [9]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. - */ - uint32_t outfifo_push_ch2:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} ahb_dma_out_push_ch2_reg_t; - -/** Type of out_link_ch2 register - * Push control register of TX channel 2 - */ -typedef union { - struct { - /** outlink_stop_ch2 : WT; bitpos: [0]; default: 0; - * Configures whether to stop AHB_DMA's TX channel 2 from transmitting data. - * 0: Invalid. No effect - * 1: Stop - */ - uint32_t outlink_stop_ch2:1; - /** outlink_start_ch2 : WT; bitpos: [1]; default: 0; - * Configures whether to enable AHB_DMA's TX channel 2 for data transfer. - * 0: Disable - * 1: Enable - */ - uint32_t outlink_start_ch2:1; - /** outlink_restart_ch2 : WT; bitpos: [2]; default: 0; - * Configures whether to restart TX channel 2 for AHB_DMA transfer. - * 0: Invalid. No effect - * 1: Restart - */ - uint32_t outlink_restart_ch2:1; - /** outlink_park_ch2 : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM. - * 0: Running - * 1: Idle - */ - uint32_t outlink_park_ch2:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_out_link_ch2_reg_t; - -/** Type of out_state_ch2 register - * Transmit status of TX channel 2 - */ -typedef union { - struct { - /** outlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the address of the next transmit descriptor to be - * processed. - */ - uint32_t outlink_dscr_addr_ch2:18; - /** out_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t out_dscr_state_ch2:2; - /** out_state_ch2 : RO; bitpos: [22:20]; default: 0; - * reserved - */ - uint32_t out_state_ch2:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} ahb_dma_out_state_ch2_reg_t; - -/** Type of out_eof_des_addr_ch2 register - * Transmit descriptor address when EOF occurs on TX channel 2 - */ -typedef union { - struct { - /** out_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_out_eof_des_addr_ch2_reg_t; - -/** Type of out_eof_bfr_des_addr_ch2 register - * The last transmit descriptor address when EOF occurs on TX channel 2 - */ -typedef union { - struct { - /** out_eof_bfr_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor before the last transmit - * descriptor. - */ - uint32_t out_eof_bfr_des_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_out_eof_bfr_des_addr_ch2_reg_t; - -/** Type of out_dscr_ch2 register - * Current transmit descriptor address of TX channel 2 - */ -typedef union { - struct { - /** outlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that has already been fetched. - */ - uint32_t outlink_dscr_ch2:32; - }; - uint32_t val; -} ahb_dma_out_dscr_ch2_reg_t; - -/** Type of out_dscr_bf0_ch2 register - * The last transmit descriptor address of TX channel 2 - */ -typedef union { - struct { - /** outlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that has already been - * fetched. - */ - uint32_t outlink_dscr_bf0_ch2:32; - }; - uint32_t val; -} ahb_dma_out_dscr_bf0_ch2_reg_t; - -/** Type of out_dscr_bf1_ch2 register - * The second-to-last transmit descriptor address of TX channel 2 - */ -typedef union { - struct { - /** outlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that has already - * been fetched. - */ - uint32_t outlink_dscr_bf1_ch2:32; - }; - uint32_t val; -} ahb_dma_out_dscr_bf1_ch2_reg_t; - -/** Type of out_peri_ch2 register - * Priority register of TX channel 2 - */ -typedef union { - struct { - /** tx_pri_ch2 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel 2.The larger of the value, the higher of the - * priority.. - */ - uint32_t tx_pri_ch2:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_out_peri_ch2_reg_t; - -/** Type of out_peri_sel_ch2 register - * Peripheral selection register of TX channel 2 - */ -typedef union { - struct { - /** peri_out_sel_ch2 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel 2. - * 0: I3C - * 1: Dummy - * 2: UHCI0 - * 3: I2S0 - * 4: I2S1 - * 5: I2S2 - * 6: Dummy - * 7: Dummy - * 8: ADC_DAC - * 9: Dummy - * 10: RMT - * 11~15: Dummy - */ - uint32_t peri_out_sel_ch2:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_out_peri_sel_ch2_reg_t; - -/** Type of tx_ch_arb_weight_ch0 register - * TX channel 0 arbitration weight configuration register - */ -typedef union { - struct { - /** tx_arb_weight_value_ch0 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of TX channel0 - */ - uint32_t tx_arb_weight_value_ch0:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_tx_ch_arb_weight_ch0_reg_t; - -/** Type of tx_arb_weight_opt_dir_ch0 register - * TX channel 0 weight arbitration optimization enable register - */ -typedef union { - struct { - /** tx_arb_weight_opt_dis_ch0 : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t tx_arb_weight_opt_dis_ch0:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_tx_arb_weight_opt_dir_ch0_reg_t; - -/** Type of tx_ch_arb_weight_ch1 register - * TX channel 1 arbitration weight configuration register - */ -typedef union { - struct { - /** tx_arb_weight_value_ch1 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of TX channel1 - */ - uint32_t tx_arb_weight_value_ch1:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_tx_ch_arb_weight_ch1_reg_t; - -/** Type of tx_arb_weight_opt_dir_ch1 register - * TX channel 1 weight arbitration optimization enable register - */ -typedef union { - struct { - /** tx_arb_weight_opt_dis_ch1 : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t tx_arb_weight_opt_dis_ch1:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_tx_arb_weight_opt_dir_ch1_reg_t; - -/** Type of tx_ch_arb_weight_ch2 register - * TX channel 2 arbitration weight configuration register - */ -typedef union { - struct { - /** tx_arb_weight_value_ch2 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of TX channel2 - */ - uint32_t tx_arb_weight_value_ch2:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_tx_ch_arb_weight_ch2_reg_t; - -/** Type of tx_arb_weight_opt_dir_ch2 register - * TX channel 2 weight arbitration optimization enable register - */ -typedef union { - struct { - /** tx_arb_weight_opt_dis_ch2 : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t tx_arb_weight_opt_dis_ch2:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_tx_arb_weight_opt_dir_ch2_reg_t; - -/** Type of rx_ch_arb_weight_ch0 register - * RX channel 0 arbitration weight configuration register - */ -typedef union { - struct { - /** rx_arb_weight_value_ch0 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of RX channel0 - */ - uint32_t rx_arb_weight_value_ch0:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_rx_ch_arb_weight_ch0_reg_t; - -/** Type of rx_arb_weight_opt_dir_ch0 register - * RX channel 0 weight arbitration optimization enable register - */ -typedef union { - struct { - /** rx_arb_weight_opt_dis_ch0 : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t rx_arb_weight_opt_dis_ch0:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_rx_arb_weight_opt_dir_ch0_reg_t; - -/** Type of rx_ch_arb_weight_ch1 register - * RX channel 1 arbitration weight configuration register - */ -typedef union { - struct { - /** rx_arb_weight_value_ch1 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of RX channel1 - */ - uint32_t rx_arb_weight_value_ch1:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_rx_ch_arb_weight_ch1_reg_t; - -/** Type of rx_arb_weight_opt_dir_ch1 register - * RX channel 1 weight arbitration optimization enable register - */ -typedef union { - struct { - /** rx_arb_weight_opt_dis_ch1 : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t rx_arb_weight_opt_dis_ch1:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_rx_arb_weight_opt_dir_ch1_reg_t; - -/** Type of in_link_addr_ch0 register - * Link list descriptor address configuration of RX channel 0 - */ -typedef union { - struct { - /** inlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address - */ - uint32_t inlink_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_in_link_addr_ch0_reg_t; - -/** Type of in_link_addr_ch1 register - * Link list descriptor address configuration of RX channel 1 - */ -typedef union { - struct { - /** inlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address - */ - uint32_t inlink_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_in_link_addr_ch1_reg_t; - -/** Type of in_link_addr_ch2 register - * Link list descriptor address configuration of RX channel 2 - */ -typedef union { - struct { - /** inlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address - */ - uint32_t inlink_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_in_link_addr_ch2_reg_t; - -/** Type of out_link_addr_ch0 register - * Link list descriptor address configuration of TX channel 0 - */ -typedef union { - struct { - /** outlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. - */ - uint32_t outlink_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_out_link_addr_ch0_reg_t; - -/** Type of out_link_addr_ch1 register - * Link list descriptor address configuration of TX channel 1 - */ -typedef union { - struct { - /** outlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. - */ - uint32_t outlink_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_out_link_addr_ch1_reg_t; - -/** Type of out_link_addr_ch2 register - * Link list descriptor address configuration of TX channel 2 - */ -typedef union { - struct { - /** outlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. - */ - uint32_t outlink_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_out_link_addr_ch2_reg_t; - -/** Type of intr_mem_start_addr register - * Accessible address space start address configuration register - */ -typedef union { - struct { - /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 0; - * Accessible address space start address configuration register - */ - uint32_t access_intr_mem_start_addr:32; - }; - uint32_t val; -} ahb_dma_intr_mem_start_addr_reg_t; - -/** Type of intr_mem_end_addr register - * Accessible address space end address configuration register - */ -typedef union { - struct { - /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; - * Configures the end address of accessible address space. - */ - uint32_t access_intr_mem_end_addr:32; - }; - uint32_t val; -} ahb_dma_intr_mem_end_addr_reg_t; - -/** Type of arb_timeout register - * TX arbitration timeout configuration register - */ -typedef union { - struct { - /** arb_timeout_num : R/W; bitpos: [15:0]; default: 0; - * Configures the time slot. Measurement unit: AHB bus clock cycle. - */ - uint32_t arb_timeout_num:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} ahb_dma_arb_timeout_reg_t; - -/** Type of weight_en register - * TX weight arbitration enable register - */ -typedef union { - struct { - /** weight_en : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration. - * 0: Disable - * 1: Enable - */ - uint32_t weight_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ahb_dma_weight_en_reg_t; - -/** Type of module_clk_en register - * Module clock force on register - */ -typedef union { - struct { - /** ahb_apb_sync_clk_en : R/W; bitpos: [2:0]; default: 7; - * Configures whether to force on ahb_apb_sync 2~0 module clock. For bit n: - * 0 : Not force on ahb_apb_sync n clock - * 1 : Force on ahb_apb_sync n clock - */ - uint32_t ahb_apb_sync_clk_en:3; - /** out_dscr_clk_en : R/W; bitpos: [5:3]; default: 7; - * Configures whether to force on out_dscr 2~0 module clock. For bit n: - * 0 : Not force on out_dscr n clock - * 1 : Force on out_dscr n clock - */ - uint32_t out_dscr_clk_en:3; - /** out_ctrl_clk_en : R/W; bitpos: [8:6]; default: 7; - * Configures whether to force on out_ctrl 2~0 module clock. For bit n: - * 0 : Not force on out_ctrl n clock - * 1 : Force on out_ctrl n clock - */ - uint32_t out_ctrl_clk_en:3; - /** in_dscr_clk_en : R/W; bitpos: [11:9]; default: 7; - * Configures whether to force on in_dscr 2~0 module clock. For bit n: - * 0 : Not force on in_dscr n clock - * 1 : Force on in_dscr n clock - */ - uint32_t in_dscr_clk_en:3; - /** in_ctrl_clk_en : R/W; bitpos: [14:12]; default: 7; - * Configures whether to force on in_ctrl 2~0 module clock. For bit n: - * 0 : Not force on in_ctrl n clock - * 1 : Force on in_ctrl n clock - */ - uint32_t in_ctrl_clk_en:3; - uint32_t reserved_15:12; - /** cmd_arb_clk_en : R/W; bitpos: [27]; default: 0; - * Configures whether to force on cmd_arb module clock. - * 0 : Not force on cmd_arb clock - * 1 : Force on cmd_arb clock - */ - uint32_t cmd_arb_clk_en:1; - /** ahbinf_clk_en : R/W; bitpos: [28]; default: 0; - * Configures whether to force on ahbinf module clock. - * 0 : Not force on ahbinf clock - * 1 : Force on ahbinf clock - */ - uint32_t ahbinf_clk_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} ahb_dma_module_clk_en_reg_t; - -/** Type of ahbinf_resp_err_status0 register - * AHB response error status 0 register - */ -typedef union { - struct { - /** ahbinf_resp_err_addr : RO; bitpos: [31:0]; default: 0; - * Represents the address of the AHB response error. - */ - uint32_t ahbinf_resp_err_addr:32; - }; - uint32_t val; -} ahb_dma_ahbinf_resp_err_status0_reg_t; - -/** Type of ahbinf_resp_err_status1 register - * AHB response error status 1 register - */ -typedef union { - struct { - /** ahbinf_resp_err_wr : RO; bitpos: [0]; default: 0; - * Represents the AHB response error is write request. - */ - uint32_t ahbinf_resp_err_wr:1; - /** ahbinf_resp_err_id : RO; bitpos: [4:1]; default: 15; - * Represents the AHB response error request id. - */ - uint32_t ahbinf_resp_err_id:4; - /** ahbinf_resp_err_ch_id : RO; bitpos: [7:5]; default: 0; - * Represents the AHB response error request channel id.bit[2]=1:TX channel. - * bit[2]=0:RX channel. - */ - uint32_t ahbinf_resp_err_ch_id:3; - uint32_t reserved_8:24; - }; - uint32_t val; -} ahb_dma_ahbinf_resp_err_status1_reg_t; - -/** Type of in_done_des_addr_ch0 register - * RX_done Inlink descriptor address of RX channel 0 - */ -typedef union { - struct { - /** in_done_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed . - */ - uint32_t in_done_des_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_in_done_des_addr_ch0_reg_t; - -/** Type of out_done_des_addr_ch0 register - * TX done outlink descriptor address of TX channel 0 - */ -typedef union { - struct { - /** out_done_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the outlink descriptor when this descriptor is completed. - */ - uint32_t out_done_des_addr_ch0:32; - }; - uint32_t val; -} ahb_dma_out_done_des_addr_ch0_reg_t; - -/** Type of in_done_des_addr_ch1 register - * RX_done Inlink descriptor address of RX channel 1 - */ -typedef union { - struct { - /** in_done_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed . - */ - uint32_t in_done_des_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_in_done_des_addr_ch1_reg_t; - -/** Type of out_done_des_addr_ch1 register - * TX done outlink descriptor address of TX channel 1 - */ -typedef union { - struct { - /** out_done_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the outlink descriptor when this descriptor is completed. - */ - uint32_t out_done_des_addr_ch1:32; - }; - uint32_t val; -} ahb_dma_out_done_des_addr_ch1_reg_t; - -/** Type of in_done_des_addr_ch2 register - * RX_done Inlink descriptor address of RX channel 2 - */ -typedef union { - struct { - /** in_done_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed . - */ - uint32_t in_done_des_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_in_done_des_addr_ch2_reg_t; - -/** Type of out_done_des_addr_ch2 register - * TX done outlink descriptor address of TX channel 2 - */ -typedef union { - struct { - /** out_done_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the outlink descriptor when this descriptor is completed. - */ - uint32_t out_done_des_addr_ch2:32; - }; - uint32_t val; -} ahb_dma_out_done_des_addr_ch2_reg_t; - - -/** Group: Configuration Registers */ -/** Type of out_crc_init_data_chn register - * This register is used to config chn crc initial data(max 32 bit) - */ -typedef union { - struct { - /** out_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295; - * This register is used to config ch0 of tx crc initial value - */ - uint32_t out_crc_init_data_chn:32; - }; - uint32_t val; -} ahb_dma_out_crc_init_data_chn_reg_t; - -/** Type of tx_crc_width_chn register - * This register is used to confiig tx chn crc result width,2'b00 mean crc_width - * <=8bit,2'b01 8 -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Interrupt Registers */ -/** Type of in_int_raw_chn register - * Raw status interrupt of channel n - */ -typedef union { - struct { - /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received for Rx channel 0. - */ - uint32_t in_done_chn_int_raw:1; - /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit - * turns to high level when the last data pointed by one inlink descriptor has been - * received and no data error is detected for Rx channel 0. - */ - uint32_t in_suc_eof_chn_int_raw:1; - /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when data error is detected only in the - * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw - * interrupt is reserved. - */ - uint32_t in_err_eof_chn_int_raw:1; - /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error - * including owner error and the second and third word error of inlink descriptor for - * Rx channel 0. - */ - uint32_t in_dscr_err_chn_int_raw:1; - /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full - * and receiving data is not completed but there is no more inlink for Rx channel 0. - */ - uint32_t in_dscr_empty_chn_int_raw:1; - /** infifo_l1_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is - * overflow. - */ - uint32_t infifo_l1_ovf_chn_int_raw:1; - /** infifo_l1_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is - * underflow. - */ - uint32_t infifo_l1_udf_chn_int_raw:1; - /** infifo_l2_ovf_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is - * overflow. - */ - uint32_t infifo_l2_ovf_chn_int_raw:1; - /** infifo_l2_udf_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is - * underflow. - */ - uint32_t infifo_l2_udf_chn_int_raw:1; - /** infifo_l3_ovf_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is - * overflow. - */ - uint32_t infifo_l3_ovf_chn_int_raw:1; - /** infifo_l3_udf_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is - * underflow. - */ - uint32_t infifo_l3_udf_chn_int_raw:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} axi_dma_in_int_raw_chn_reg_t; - -/** Type of in_int_st_chn register - * Masked interrupt of channel n - */ -typedef union { - struct { - /** in_done_chn_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_chn_int_st:1; - /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_chn_int_st:1; - /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_chn_int_st:1; - /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_chn_int_st:1; - /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_chn_int_st:1; - /** infifo_ovf_chn_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_chn_int_st:1; - /** infifo_udf_chn_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_chn_int_st:1; - /** infifo_l1_ovf_chn_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_l1_ovf_chn_int_st:1; - /** infifo_l1_udf_chn_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_l1_udf_chn_int_st:1; - /** infifo_l3_ovf_chn_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t infifo_l3_ovf_chn_int_st:1; - /** infifo_l3_udf_chn_int_st : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t infifo_l3_udf_chn_int_st:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} axi_dma_in_int_st_chn_reg_t; - -/** Type of in_int_ena_chn register - * Interrupt enable bits of channel n - */ -typedef union { - struct { - /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_chn_int_ena:1; - /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_chn_int_ena:1; - /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_chn_int_ena:1; - /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_chn_int_ena:1; - /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_chn_int_ena:1; - /** infifo_l1_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_l1_ovf_chn_int_ena:1; - /** infifo_l1_udf_chn_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_l1_udf_chn_int_ena:1; - /** infifo_l2_ovf_chn_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_l2_ovf_chn_int_ena:1; - /** infifo_l2_udf_chn_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_l2_udf_chn_int_ena:1; - /** infifo_l3_ovf_chn_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t infifo_l3_ovf_chn_int_ena:1; - /** infifo_l3_udf_chn_int_ena : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t infifo_l3_udf_chn_int_ena:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} axi_dma_in_int_ena_chn_reg_t; - -/** Type of in_int_clr_chn register - * Interrupt clear bits of channel n - */ -typedef union { - struct { - /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_chn_int_clr:1; - /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_chn_int_clr:1; - /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_chn_int_clr:1; - /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_chn_int_clr:1; - /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_chn_int_clr:1; - /** infifo_l1_ovf_chn_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_l1_ovf_chn_int_clr:1; - /** infifo_l1_udf_chn_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_l1_udf_chn_int_clr:1; - /** infifo_l2_ovf_chn_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_l2_ovf_chn_int_clr:1; - /** infifo_l2_udf_chn_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_l2_udf_chn_int_clr:1; - /** infifo_l3_ovf_chn_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t infifo_l3_ovf_chn_int_clr:1; - /** infifo_l3_udf_chn_int_clr : WT; bitpos: [10]; default: 0; - * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t infifo_l3_udf_chn_int_clr:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} axi_dma_in_int_clr_chn_reg_t; - -/** Type of out_int_raw_chn register - * Raw status interrupt of channeln - */ -typedef union { - struct { - /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel0. - */ - uint32_t out_done_chn_int_raw:1; - /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel0. - */ - uint32_t out_eof_chn_int_raw:1; - /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error - * including owner error and the second and third word error of outlink descriptor for - * Tx channel0. - */ - uint32_t out_dscr_err_chn_int_raw:1; - /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel0. - */ - uint32_t out_total_eof_chn_int_raw:1; - /** outfifo_l1_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is - * overflow. - */ - uint32_t outfifo_l1_ovf_chn_int_raw:1; - /** outfifo_l1_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is - * underflow. - */ - uint32_t outfifo_l1_udf_chn_int_raw:1; - /** outfifo_l2_ovf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is - * overflow. - */ - uint32_t outfifo_l2_ovf_chn_int_raw:1; - /** outfifo_l2_udf_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is - * underflow. - */ - uint32_t outfifo_l2_udf_chn_int_raw:1; - /** outfifo_l3_ovf_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is - * overflow. - */ - uint32_t outfifo_l3_ovf_chn_int_raw:1; - /** outfifo_l3_udf_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is - * underflow. - */ - uint32_t outfifo_l3_udf_chn_int_raw:1; - /** out_link_switch_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when the dma switch to new link for Tx - * channel0. - */ - uint32_t out_link_switch_chn_int_raw:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} axi_dma_out_int_raw_chn_reg_t; - -/** Type of out_int_st_chn register - * Masked interrupt of channeln - */ -typedef union { - struct { - /** out_done_chn_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_chn_int_st:1; - /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_chn_int_st:1; - /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_chn_int_st:1; - /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_chn_int_st:1; - /** outfifo_ovf_chn_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_chn_int_st:1; - /** outfifo_udf_chn_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_chn_int_st:1; - /** outfifo_l1_ovf_chn_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_l1_ovf_chn_int_st:1; - /** outfifo_l1_udf_chn_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_l1_udf_chn_int_st:1; - /** outfifo_l3_ovf_chn_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t outfifo_l3_ovf_chn_int_st:1; - /** outfifo_l3_udf_chn_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t outfifo_l3_udf_chn_int_st:1; - /** out_link_switch_chn_int_st : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUT_LINK_SWITCH_CH_INT interrupt. - */ - uint32_t out_link_switch_chn_int_st:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} axi_dma_out_int_st_chn_reg_t; - -/** Type of out_int_ena_chn register - * Interrupt enable bits of channeln - */ -typedef union { - struct { - /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_chn_int_ena:1; - /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_chn_int_ena:1; - /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_chn_int_ena:1; - /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_chn_int_ena:1; - /** outfifo_l1_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_l1_ovf_chn_int_ena:1; - /** outfifo_l1_udf_chn_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_l1_udf_chn_int_ena:1; - /** outfifo_l2_ovf_chn_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_l2_ovf_chn_int_ena:1; - /** outfifo_l2_udf_chn_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_l2_udf_chn_int_ena:1; - /** outfifo_l3_ovf_chn_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t outfifo_l3_ovf_chn_int_ena:1; - /** outfifo_l3_udf_chn_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t outfifo_l3_udf_chn_int_ena:1; - /** out_link_switch_chn_int_ena : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUT_LINK_SWITCH_CH_INT interrupt. - */ - uint32_t out_link_switch_chn_int_ena:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} axi_dma_out_int_ena_chn_reg_t; - -/** Type of out_int_clr_chn register - * Interrupt clear bits of channeln - */ -typedef union { - struct { - /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_chn_int_clr:1; - /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_chn_int_clr:1; - /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_chn_int_clr:1; - /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_chn_int_clr:1; - /** outfifo_l1_ovf_chn_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_l1_ovf_chn_int_clr:1; - /** outfifo_l1_udf_chn_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_l1_udf_chn_int_clr:1; - /** outfifo_l2_ovf_chn_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_l2_ovf_chn_int_clr:1; - /** outfifo_l2_udf_chn_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_l2_udf_chn_int_clr:1; - /** outfifo_l3_ovf_chn_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t outfifo_l3_ovf_chn_int_clr:1; - /** outfifo_l3_udf_chn_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t outfifo_l3_udf_chn_int_clr:1; - /** out_link_switch_chn_int_clr : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUT_LINK_SWITCH_CH_INT interrupt. - */ - uint32_t out_link_switch_chn_int_clr:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} axi_dma_out_int_clr_chn_reg_t; - - -/** Group: Configuration Registers */ -/** Type of in_conf0_chn register - * Configure 0 register of Rx channel n - */ -typedef union { - struct { - /** in_rst_chn : R/W; bitpos: [0]; default: 0; - * This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer. - */ - uint32_t in_rst_chn:1; - /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t in_loop_test_chn:1; - /** mem_trans_en_chn : R/W; bitpos: [2]; default: 0; - * Set this bit 1 to enable automatic transmitting data from memory to memory via - * AXI_DMA. - */ - uint32_t mem_trans_en_chn:1; - /** in_etm_en_chn : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm - * task. - */ - uint32_t in_etm_en_chn:1; - /** in_burst_size_sel_chn : R/W; bitpos: [6:4]; default: 0; - * 3'b000-3'b100:burst length 8byte~128byte - */ - uint32_t in_burst_size_sel_chn:3; - /** in_cmd_disable_chn : R/W; bitpos: [7]; default: 0; - * 1:mean disable cmd of this ch0 - */ - uint32_t in_cmd_disable_chn:1; - /** in_ecc_aec_en_chn : R/W; bitpos: [8]; default: 0; - * 1: mean access ecc or aes domain,0: mean not - */ - uint32_t in_ecc_aec_en_chn:1; - /** indscr_burst_en_chn : R/W; bitpos: [9]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t indscr_burst_en_chn:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} axi_dma_in_conf0_chn_reg_t; - -/** Type of in_conf1_chn register - * Configure 1 register of Rx channel n - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t in_check_owner_chn:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} axi_dma_in_conf1_chn_reg_t; - -/** Type of in_pop_chn register - * Pop control register of Rx channel n - */ -typedef union { - struct { - /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; - * This register stores the data popping from AXI_DMA FIFO. - */ - uint32_t infifo_rdata_chn:12; - /** infifo_pop_chn : WT; bitpos: [12]; default: 0; - * Set this bit to pop data from AXI_DMA FIFO. - */ - uint32_t infifo_pop_chn:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} axi_dma_in_pop_chn_reg_t; - -/** Type of in_link1_chn register - * Link descriptor configure and control register of Rx channel n - */ -typedef union { - struct { - /** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1; - * Set this bit to return to current inlink descriptor's address when there are some - * errors in current receiving data. - */ - uint32_t inlink_auto_ret_chn:1; - /** inlink_stop_chn : WT; bitpos: [1]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ - uint32_t inlink_stop_chn:1; - /** inlink_start_chn : WT; bitpos: [2]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ - uint32_t inlink_start_chn:1; - /** inlink_restart_chn : WT; bitpos: [3]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ - uint32_t inlink_restart_chn:1; - /** inlink_park_chn : RO; bitpos: [4]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ - uint32_t inlink_park_chn:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} axi_dma_in_link1_chn_reg_t; - -/** Type of in_link2_chn register - * Link descriptor configure and control register of Rx channel n - */ -typedef union { - struct { - /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0; - * This register stores the 20 least significant bits of the first inlink descriptor's - * address. - */ - uint32_t inlink_addr_chn:32; - }; - uint32_t val; -} axi_dma_in_link2_chn_reg_t; - -/** Type of in_crc_init_data_chn register - * This register is used to config chn crc initial data(max 32 bit) - */ -typedef union { - struct { - /** in_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295; - * This register is used to config ch0 of rx crc initial value - */ - uint32_t in_crc_init_data_chn:32; - }; - uint32_t val; -} axi_dma_in_crc_init_data_chn_reg_t; - -/** Type of rx_crc_width_chn register - * This register is used to confiig rx chn crc result width,2'b00 mean crc_width - * <=8bit,2'b01 8 -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Control and configuration registers */ -/** Type of tx_inst_cfg0 register - * Control and configuration registers - */ -typedef union { - struct { - /** tx_inst_idx : R/W; bitpos: [2:0]; default: 0; - * write this bits to specify the one of 8 instruction - */ - uint32_t tx_inst_idx:3; - /** tx_inst_pos : R/W; bitpos: [6:3]; default: 0; - * write this bits to specify the bit position of 257 bit instruction which in units - * of 32 bits - */ - uint32_t tx_inst_pos:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} bitscrambler_tx_inst_cfg0_reg_t; - -/** Type of tx_inst_cfg1 register - * Control and configuration registers - */ -typedef union { - struct { - /** tx_inst : R/W; bitpos: [31:0]; default: 4; - * write this bits to update instruction which specified by - * BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by - * BITSCRAMBLER_TX_INST_CFG0_REG - */ - uint32_t tx_inst:32; - }; - uint32_t val; -} bitscrambler_tx_inst_cfg1_reg_t; - -/** Type of rx_inst_cfg0 register - * Control and configuration registers - */ -typedef union { - struct { - /** rx_inst_idx : R/W; bitpos: [2:0]; default: 0; - * write this bits to specify the one of 8 instruction - */ - uint32_t rx_inst_idx:3; - /** rx_inst_pos : R/W; bitpos: [6:3]; default: 0; - * write this bits to specify the bit position of 257 bit instruction which in units - * of 32 bits - */ - uint32_t rx_inst_pos:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} bitscrambler_rx_inst_cfg0_reg_t; - -/** Type of rx_inst_cfg1 register - * Control and configuration registers - */ -typedef union { - struct { - /** rx_inst : R/W; bitpos: [31:0]; default: 12; - * write this bits to update instruction which specified by - * BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by - * BITSCRAMBLER_RX_INST_CFG0_REG - */ - uint32_t rx_inst:32; - }; - uint32_t val; -} bitscrambler_rx_inst_cfg1_reg_t; - -/** Type of tx_lut_cfg0 register - * Control and configuration registers - */ -typedef union { - struct { - /** tx_lut_idx : R/W; bitpos: [10:0]; default: 0; - * write this bits to specify the bytes position of LUT RAM based on - * reg_bitscrambler_tx_lut_mode - */ - uint32_t tx_lut_idx:11; - /** tx_lut_mode : R/W; bitpos: [12:11]; default: 0; - * write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 - * bytes - */ - uint32_t tx_lut_mode:2; - uint32_t reserved_13:19; - }; - uint32_t val; -} bitscrambler_tx_lut_cfg0_reg_t; - -/** Type of tx_lut_cfg1 register - * Control and configuration registers - */ -typedef union { - struct { - /** tx_lut : R/W; bitpos: [31:0]; default: 20; - * write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read - * this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG - */ - uint32_t tx_lut:32; - }; - uint32_t val; -} bitscrambler_tx_lut_cfg1_reg_t; - -/** Type of rx_lut_cfg0 register - * Control and configuration registers - */ -typedef union { - struct { - /** rx_lut_idx : R/W; bitpos: [10:0]; default: 0; - * write this bits to specify the bytes position of LUT RAM based on - * reg_bitscrambler_rx_lut_mode - */ - uint32_t rx_lut_idx:11; - /** rx_lut_mode : R/W; bitpos: [12:11]; default: 0; - * write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 - * bytes - */ - uint32_t rx_lut_mode:2; - uint32_t reserved_13:19; - }; - uint32_t val; -} bitscrambler_rx_lut_cfg0_reg_t; - -/** Type of rx_lut_cfg1 register - * Control and configuration registers - */ -typedef union { - struct { - /** rx_lut : R/W; bitpos: [31:0]; default: 28; - * write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read - * this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG - */ - uint32_t rx_lut:32; - }; - uint32_t val; -} bitscrambler_rx_lut_cfg1_reg_t; - - -/** Group: Configuration registers */ -/** Type of tx_tailing_bits register - * Control and configuration registers - */ -typedef union { - struct { - /** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0; - * write this bits to specify the extra data bit length after getting EOF - */ - uint32_t tx_tailing_bits:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} bitscrambler_tx_tailing_bits_reg_t; - -/** Type of rx_tailing_bits register - * Control and configuration registers - */ -typedef union { - struct { - /** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0; - * write this bits to specify the extra data bit length after getting EOF - */ - uint32_t rx_tailing_bits:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} bitscrambler_rx_tailing_bits_reg_t; - -/** Type of tx_ctrl register - * Control and configuration registers - */ -typedef union { - struct { - /** tx_ena : R/W; bitpos: [0]; default: 0; - * write this bit to enable the bitscrambler tx - */ - uint32_t tx_ena:1; - /** tx_pause : R/W; bitpos: [1]; default: 0; - * write this bit to pause the bitscrambler tx core - */ - uint32_t tx_pause:1; - /** tx_halt : R/W; bitpos: [2]; default: 1; - * write this bit to halt the bitscrambler tx core - */ - uint32_t tx_halt:1; - /** tx_eof_mode : R/W; bitpos: [3]; default: 0; - * write this bit to ser the bitscrambler tx core EOF signal generating mode which is - * combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 - * counter by write peripheral buffer - */ - uint32_t tx_eof_mode:1; - /** tx_cond_mode : R/W; bitpos: [4]; default: 0; - * write this bit to specify the LOOP instruction condition mode of bitscrambler tx - * core, 0: use the little than operator to get the condition, 1: use not equal - * operator to get the condition - */ - uint32_t tx_cond_mode:1; - /** tx_fetch_mode : R/W; bitpos: [5]; default: 0; - * write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch - * by reset, 1: fetch by instructions - */ - uint32_t tx_fetch_mode:1; - /** tx_halt_mode : R/W; bitpos: [6]; default: 0; - * write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: - * wait write data back done, , 1: ignore write data back - */ - uint32_t tx_halt_mode:1; - /** tx_rd_dummy : R/W; bitpos: [7]; default: 0; - * write this bit to set the bitscrambler tx core read data mode when EOF received.0: - * wait read data, 1: ignore read data - */ - uint32_t tx_rd_dummy:1; - /** tx_fifo_rst : WT; bitpos: [8]; default: 0; - * write this bit to reset the bitscrambler tx fifo - */ - uint32_t tx_fifo_rst:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} bitscrambler_tx_ctrl_reg_t; - -/** Type of rx_ctrl register - * Control and configuration registers - */ -typedef union { - struct { - /** rx_ena : R/W; bitpos: [0]; default: 0; - * write this bit to enable the bitscrambler rx - */ - uint32_t rx_ena:1; - /** rx_pause : R/W; bitpos: [1]; default: 0; - * write this bit to pause the bitscrambler rx core - */ - uint32_t rx_pause:1; - /** rx_halt : R/W; bitpos: [2]; default: 1; - * write this bit to halt the bitscrambler rx core - */ - uint32_t rx_halt:1; - /** rx_eof_mode : R/W; bitpos: [3]; default: 0; - * write this bit to ser the bitscrambler rx core EOF signal generating mode which is - * combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral - * buffer, 0 counter by write dma fifo - */ - uint32_t rx_eof_mode:1; - /** rx_cond_mode : R/W; bitpos: [4]; default: 0; - * write this bit to specify the LOOP instruction condition mode of bitscrambler rx - * core, 0: use the little than operator to get the condition, 1: use not equal - * operator to get the condition - */ - uint32_t rx_cond_mode:1; - /** rx_fetch_mode : R/W; bitpos: [5]; default: 0; - * write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch - * by reset, 1: fetch by instructions - */ - uint32_t rx_fetch_mode:1; - /** rx_halt_mode : R/W; bitpos: [6]; default: 0; - * write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0: - * wait write data back done, , 1: ignore write data back - */ - uint32_t rx_halt_mode:1; - /** rx_rd_dummy : R/W; bitpos: [7]; default: 0; - * write this bit to set the bitscrambler rx core read data mode when EOF received.0: - * wait read data, 1: ignore read data - */ - uint32_t rx_rd_dummy:1; - /** rx_fifo_rst : WT; bitpos: [8]; default: 0; - * write this bit to reset the bitscrambler rx fifo - */ - uint32_t rx_fifo_rst:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} bitscrambler_rx_ctrl_reg_t; - -/** Type of sys register - * Control and configuration registers - */ -typedef union { - struct { - /** loop_mode : R/W; bitpos: [0]; default: 0; - * write this bit to set the bitscrambler tx loop back to DMA rx - */ - uint32_t loop_mode:1; - uint32_t reserved_1:30; - /** clk_en : R/W; bitpos: [31]; default: 0; - * Reserved - */ - uint32_t clk_en:1; - }; - uint32_t val; -} bitscrambler_sys_reg_t; - - -/** Group: Status registers */ -/** Type of tx_state register - * Status registers - */ -typedef union { - struct { - /** tx_in_idle : RO; bitpos: [0]; default: 1; - * represents the bitscrambler tx core in halt mode - */ - uint32_t tx_in_idle:1; - /** tx_in_run : RO; bitpos: [1]; default: 0; - * represents the bitscrambler tx core in run mode - */ - uint32_t tx_in_run:1; - /** tx_in_wait : RO; bitpos: [2]; default: 0; - * represents the bitscrambler tx core in wait mode to wait write back done - */ - uint32_t tx_in_wait:1; - /** tx_in_pause : RO; bitpos: [3]; default: 0; - * represents the bitscrambler tx core in pause mode - */ - uint32_t tx_in_pause:1; - /** tx_fifo_empty : RO; bitpos: [4]; default: 0; - * represents the bitscrambler tx fifo in empty state - */ - uint32_t tx_fifo_empty:1; - uint32_t reserved_5:11; - /** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0; - * represents the bytes numbers of bitscrambler tx core when get EOF - */ - uint32_t tx_eof_get_cnt:14; - /** tx_eof_overload : RO; bitpos: [30]; default: 0; - * represents the some EOFs will be lost for bitscrambler tx core - */ - uint32_t tx_eof_overload:1; - /** tx_eof_trace_clr : WT; bitpos: [31]; default: 0; - * write this bit to clear reg_bitscrambler_tx_eof_overload and - * reg_bitscrambler_tx_eof_get_cnt registers - */ - uint32_t tx_eof_trace_clr:1; - }; - uint32_t val; -} bitscrambler_tx_state_reg_t; - -/** Type of rx_state register - * Status registers - */ -typedef union { - struct { - /** rx_in_idle : RO; bitpos: [0]; default: 1; - * represents the bitscrambler rx core in halt mode - */ - uint32_t rx_in_idle:1; - /** rx_in_run : RO; bitpos: [1]; default: 0; - * represents the bitscrambler rx core in run mode - */ - uint32_t rx_in_run:1; - /** rx_in_wait : RO; bitpos: [2]; default: 0; - * represents the bitscrambler rx core in wait mode to wait write back done - */ - uint32_t rx_in_wait:1; - /** rx_in_pause : RO; bitpos: [3]; default: 0; - * represents the bitscrambler rx core in pause mode - */ - uint32_t rx_in_pause:1; - /** rx_fifo_full : RO; bitpos: [4]; default: 0; - * represents the bitscrambler rx fifo in full state - */ - uint32_t rx_fifo_full:1; - uint32_t reserved_5:11; - /** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0; - * represents the bytes numbers of bitscrambler rx core when get EOF - */ - uint32_t rx_eof_get_cnt:14; - /** rx_eof_overload : RO; bitpos: [30]; default: 0; - * represents the some EOFs will be lost for bitscrambler rx core - */ - uint32_t rx_eof_overload:1; - /** rx_eof_trace_clr : WT; bitpos: [31]; default: 0; - * write this bit to clear reg_bitscrambler_rx_eof_overload and - * reg_bitscrambler_rx_eof_get_cnt registers - */ - uint32_t rx_eof_trace_clr:1; - }; - uint32_t val; -} bitscrambler_rx_state_reg_t; - - -/** Group: Version register */ -/** Type of version register - * Control and configuration registers - */ -typedef union { - struct { - /** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36713024; - * Reserved - */ - uint32_t bitscrambler_ver:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} bitscrambler_version_reg_t; - - -typedef struct { - volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0; - volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1; - volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0; - volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1; - volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0; - volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1; - volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0; - volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1; - volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits; - volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits; - volatile bitscrambler_tx_ctrl_reg_t tx_ctrl; - volatile bitscrambler_rx_ctrl_reg_t rx_ctrl; - volatile bitscrambler_tx_state_reg_t tx_state; - volatile bitscrambler_rx_state_reg_t rx_state; - uint32_t reserved_038[48]; - volatile bitscrambler_sys_reg_t sys; - volatile bitscrambler_version_reg_t version; -} bitscrambler_dev_t; - -extern bitscrambler_dev_t BITSCRAMBLER; - -#ifndef __cplusplus -_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/cache_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/cache_reg.h index a99a74bbcbf1..ee63baf3a111 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/cache_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/cache_reg.h @@ -5,7 +5,6 @@ */ #pragma once -#include #include "soc/soc.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dw_gdma_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/dw_gdma_eco5_struct.h deleted file mode 100644 index c030f0e037f9..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/dw_gdma_eco5_struct.h +++ /dev/null @@ -1,5184 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Version Register */ -/** Type of id0 register - * NA - */ -typedef union { - struct { - /** dmac_id : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t dmac_id:32; - }; - uint32_t val; -} dmac_id0_reg_t; - -/** Type of compver0 register - * NA - */ -typedef union { - struct { - /** dmac_compver : RO; bitpos: [31:0]; default: 842018858; - * NA - */ - uint32_t dmac_compver:32; - }; - uint32_t val; -} dmac_compver0_reg_t; - - -/** Group: Configuration Registers */ -/** Type of cfg0 register - * NA - */ -typedef union { - struct { - /** dmac_en : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t dmac_en:1; - /** int_en : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t int_en:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} dmac_cfg0_reg_t; - -/** Type of chen0 register - * NA - */ -typedef union { - struct { - /** ch1_en : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch1_en:1; - /** ch2_en : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch2_en:1; - /** ch3_en : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch3_en:1; - /** ch4_en : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch4_en:1; - uint32_t reserved_4:4; - /** ch1_en_we : WO; bitpos: [8]; default: 0; - * NA - */ - uint32_t ch1_en_we:1; - /** ch2_en_we : WO; bitpos: [9]; default: 0; - * NA - */ - uint32_t ch2_en_we:1; - /** ch3_en_we : WO; bitpos: [10]; default: 0; - * NA - */ - uint32_t ch3_en_we:1; - /** ch4_en_we : WO; bitpos: [11]; default: 0; - * NA - */ - uint32_t ch4_en_we:1; - uint32_t reserved_12:4; - /** ch1_susp : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t ch1_susp:1; - /** ch2_susp : R/W; bitpos: [17]; default: 0; - * NA - */ - uint32_t ch2_susp:1; - /** ch3_susp : R/W; bitpos: [18]; default: 0; - * NA - */ - uint32_t ch3_susp:1; - /** ch4_susp : R/W; bitpos: [19]; default: 0; - * NA - */ - uint32_t ch4_susp:1; - uint32_t reserved_20:4; - /** ch1_susp_we : WO; bitpos: [24]; default: 0; - * NA - */ - uint32_t ch1_susp_we:1; - /** ch2_susp_we : WO; bitpos: [25]; default: 0; - * NA - */ - uint32_t ch2_susp_we:1; - /** ch3_susp_we : WO; bitpos: [26]; default: 0; - * NA - */ - uint32_t ch3_susp_we:1; - /** ch4_susp_we : WO; bitpos: [27]; default: 0; - * NA - */ - uint32_t ch4_susp_we:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} dmac_chen0_reg_t; - -/** Type of chen1 register - * NA - */ -typedef union { - struct { - /** ch1_abort : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch1_abort:1; - /** ch2_abort : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch2_abort:1; - /** ch3_abort : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch3_abort:1; - /** ch4_abort : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch4_abort:1; - uint32_t reserved_4:4; - /** ch1_abort_we : WO; bitpos: [8]; default: 0; - * NA - */ - uint32_t ch1_abort_we:1; - /** ch2_abort_we : WO; bitpos: [9]; default: 0; - * NA - */ - uint32_t ch2_abort_we:1; - /** ch3_abort_we : WO; bitpos: [10]; default: 0; - * NA - */ - uint32_t ch3_abort_we:1; - /** ch4_abort_we : WO; bitpos: [11]; default: 0; - * NA - */ - uint32_t ch4_abort_we:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} dmac_chen1_reg_t; - -/** Type of reset0 register - * NA - */ -typedef union { - struct { - /** dmac_rst : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t dmac_rst:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} dmac_reset0_reg_t; - -/** Type of lowpower_cfg0 register - * NA - */ -typedef union { - struct { - /** gbl_cslp_en : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t gbl_cslp_en:1; - /** chnl_cslp_en : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t chnl_cslp_en:1; - /** sbiu_cslp_en : R/W; bitpos: [2]; default: 1; - * NA - */ - uint32_t sbiu_cslp_en:1; - /** mxif_cslp_en : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t mxif_cslp_en:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_lowpower_cfg0_reg_t; - -/** Type of lowpower_cfg1 register - * NA - */ -typedef union { - struct { - /** glch_lpdly : R/W; bitpos: [7:0]; default: 64; - * NA - */ - uint32_t glch_lpdly:8; - /** sbiu_lpdly : R/W; bitpos: [15:8]; default: 64; - * NA - */ - uint32_t sbiu_lpdly:8; - /** mxif_lpdly : R/W; bitpos: [23:16]; default: 64; - * NA - */ - uint32_t mxif_lpdly:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} dmac_lowpower_cfg1_reg_t; - -/** Type of ch1_sar0 register - * NA - */ -typedef union { - struct { - /** ch1_sar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch1_sar0:32; - }; - uint32_t val; -} dmac_ch1_sar0_reg_t; - -/** Type of ch1_sar1 register - * NA - */ -typedef union { - struct { - /** ch1_sar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch1_sar1:32; - }; - uint32_t val; -} dmac_ch1_sar1_reg_t; - -/** Type of ch1_dar0 register - * NA - */ -typedef union { - struct { - /** ch1_dar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch1_dar0:32; - }; - uint32_t val; -} dmac_ch1_dar0_reg_t; - -/** Type of ch1_dar1 register - * NA - */ -typedef union { - struct { - /** ch1_dar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch1_dar1:32; - }; - uint32_t val; -} dmac_ch1_dar1_reg_t; - -/** Type of ch1_block_ts0 register - * NA - */ -typedef union { - struct { - /** ch1_block_ts : R/W; bitpos: [21:0]; default: 0; - * NA - */ - uint32_t ch1_block_ts:22; - uint32_t reserved_22:10; - }; - uint32_t val; -} dmac_ch1_block_ts0_reg_t; - -/** Type of ch1_ctl0 register - * NA - */ -typedef union { - struct { - /** ch1_sms : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch1_sms:1; - uint32_t reserved_1:1; - /** ch1_dms : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch1_dms:1; - uint32_t reserved_3:1; - /** ch1_sinc : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch1_sinc:1; - uint32_t reserved_5:1; - /** ch1_dinc : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch1_dinc:1; - uint32_t reserved_7:1; - /** ch1_src_tr_width : R/W; bitpos: [10:8]; default: 2; - * NA - */ - uint32_t ch1_src_tr_width:3; - /** ch1_dst_tr_width : R/W; bitpos: [13:11]; default: 2; - * NA - */ - uint32_t ch1_dst_tr_width:3; - /** ch1_src_msize : R/W; bitpos: [17:14]; default: 0; - * NA - */ - uint32_t ch1_src_msize:4; - /** ch1_dst_msize : R/W; bitpos: [21:18]; default: 0; - * NA - */ - uint32_t ch1_dst_msize:4; - /** ch1_ar_cache : R/W; bitpos: [25:22]; default: 0; - * NA - */ - uint32_t ch1_ar_cache:4; - /** ch1_aw_cache : R/W; bitpos: [29:26]; default: 0; - * NA - */ - uint32_t ch1_aw_cache:4; - /** ch1_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch1_nonposted_lastwrite_en:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} dmac_ch1_ctl0_reg_t; - -/** Type of ch1_ctl1 register - * NA - */ -typedef union { - struct { - /** ch1_ar_prot : R/W; bitpos: [2:0]; default: 0; - * NA - */ - uint32_t ch1_ar_prot:3; - /** ch1_aw_prot : R/W; bitpos: [5:3]; default: 0; - * NA - */ - uint32_t ch1_aw_prot:3; - /** ch1_arlen_en : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch1_arlen_en:1; - /** ch1_arlen : R/W; bitpos: [14:7]; default: 0; - * NA - */ - uint32_t ch1_arlen:8; - /** ch1_awlen_en : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t ch1_awlen_en:1; - /** ch1_awlen : R/W; bitpos: [23:16]; default: 0; - * NA - */ - uint32_t ch1_awlen:8; - /** ch1_src_stat_en : R/W; bitpos: [24]; default: 0; - * NA - */ - uint32_t ch1_src_stat_en:1; - /** ch1_dst_stat_en : R/W; bitpos: [25]; default: 0; - * NA - */ - uint32_t ch1_dst_stat_en:1; - /** ch1_ioc_blktfr : R/W; bitpos: [26]; default: 0; - * NA - */ - uint32_t ch1_ioc_blktfr:1; - uint32_t reserved_27:3; - /** ch1_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch1_shadowreg_or_lli_last:1; - /** ch1_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0; - * NA - */ - uint32_t ch1_shadowreg_or_lli_valid:1; - }; - uint32_t val; -} dmac_ch1_ctl1_reg_t; - -/** Type of ch1_cfg0 register - * NA - */ -typedef union { - struct { - /** ch1_src_multblk_type : R/W; bitpos: [1:0]; default: 0; - * NA - */ - uint32_t ch1_src_multblk_type:2; - /** ch1_dst_multblk_type : R/W; bitpos: [3:2]; default: 0; - * NA - */ - uint32_t ch1_dst_multblk_type:2; - uint32_t reserved_4:14; - /** ch1_rd_uid : RO; bitpos: [21:18]; default: 0; - * NA - */ - uint32_t ch1_rd_uid:4; - uint32_t reserved_22:3; - /** ch1_wr_uid : RO; bitpos: [28:25]; default: 0; - * NA - */ - uint32_t ch1_wr_uid:4; - uint32_t reserved_29:3; - }; - uint32_t val; -} dmac_ch1_cfg0_reg_t; - -/** Type of ch1_cfg1 register - * NA - */ -typedef union { - struct { - /** ch1_tt_fc : R/W; bitpos: [2:0]; default: 3; - * NA - */ - uint32_t ch1_tt_fc:3; - /** ch1_hs_sel_src : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch1_hs_sel_src:1; - /** ch1_hs_sel_dst : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t ch1_hs_sel_dst:1; - /** ch1_src_hwhs_pol : RO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch1_src_hwhs_pol:1; - /** ch1_dst_hwhs_pol : RO; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch1_dst_hwhs_pol:1; - /** ch1_src_per : R/W; bitpos: [8:7]; default: 0; - * NA - */ - uint32_t ch1_src_per:2; - uint32_t reserved_9:3; - /** ch1_dst_per : R/W; bitpos: [13:12]; default: 0; - * NA - */ - uint32_t ch1_dst_per:2; - uint32_t reserved_14:3; - /** ch1_ch_prior : R/W; bitpos: [19:17]; default: 3; - * NA - */ - uint32_t ch1_ch_prior:3; - /** ch1_lock_ch : RO; bitpos: [20]; default: 0; - * NA - */ - uint32_t ch1_lock_ch:1; - /** ch1_lock_ch_l : RO; bitpos: [22:21]; default: 0; - * NA - */ - uint32_t ch1_lock_ch_l:2; - /** ch1_src_osr_lmt : R/W; bitpos: [26:23]; default: 0; - * NA - */ - uint32_t ch1_src_osr_lmt:4; - /** ch1_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0; - * NA - */ - uint32_t ch1_dst_osr_lmt:4; - uint32_t reserved_31:1; - }; - uint32_t val; -} dmac_ch1_cfg1_reg_t; - -/** Type of ch1_llp0 register - * NA - */ -typedef union { - struct { - /** ch1_lms : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch1_lms:1; - uint32_t reserved_1:5; - /** ch1_loc0 : R/W; bitpos: [31:6]; default: 0; - * NA - */ - uint32_t ch1_loc0:26; - }; - uint32_t val; -} dmac_ch1_llp0_reg_t; - -/** Type of ch1_llp1 register - * NA - */ -typedef union { - struct { - /** ch1_loc1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch1_loc1:32; - }; - uint32_t val; -} dmac_ch1_llp1_reg_t; - -/** Type of ch1_swhssrc0 register - * NA - */ -typedef union { - struct { - /** ch1_swhs_req_src : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch1_swhs_req_src:1; - /** ch1_swhs_req_src_we : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch1_swhs_req_src_we:1; - /** ch1_swhs_sglreq_src : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch1_swhs_sglreq_src:1; - /** ch1_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch1_swhs_sglreq_src_we:1; - /** ch1_swhs_lst_src : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch1_swhs_lst_src:1; - /** ch1_swhs_lst_src_we : WO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch1_swhs_lst_src_we:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} dmac_ch1_swhssrc0_reg_t; - -/** Type of ch1_swhsdst0 register - * NA - */ -typedef union { - struct { - /** ch1_swhs_req_dst : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch1_swhs_req_dst:1; - /** ch1_swhs_req_dst_we : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch1_swhs_req_dst_we:1; - /** ch1_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch1_swhs_sglreq_dst:1; - /** ch1_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch1_swhs_sglreq_dst_we:1; - /** ch1_swhs_lst_dst : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch1_swhs_lst_dst:1; - /** ch1_swhs_lst_dst_we : WO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch1_swhs_lst_dst_we:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} dmac_ch1_swhsdst0_reg_t; - -/** Type of ch1_blk_tfr_resumereq0 register - * NA - */ -typedef union { - struct { - /** ch1_blk_tfr_resumereq : WO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch1_blk_tfr_resumereq:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} dmac_ch1_blk_tfr_resumereq0_reg_t; - -/** Type of ch1_axi_id0 register - * NA - */ -typedef union { - struct { - /** ch1_axi_read_id_suffix : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch1_axi_read_id_suffix:1; - uint32_t reserved_1:15; - /** ch1_axi_write_id_suffix : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t ch1_axi_write_id_suffix:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} dmac_ch1_axi_id0_reg_t; - -/** Type of ch1_axi_qos0 register - * NA - */ -typedef union { - struct { - /** ch1_axi_awqos : R/W; bitpos: [3:0]; default: 0; - * NA - */ - uint32_t ch1_axi_awqos:4; - /** ch1_axi_arqos : R/W; bitpos: [7:4]; default: 0; - * NA - */ - uint32_t ch1_axi_arqos:4; - uint32_t reserved_8:24; - }; - uint32_t val; -} dmac_ch1_axi_qos0_reg_t; - -/** Type of ch2_sar0 register - * NA - */ -typedef union { - struct { - /** ch2_sar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch2_sar0:32; - }; - uint32_t val; -} dmac_ch2_sar0_reg_t; - -/** Type of ch2_sar1 register - * NA - */ -typedef union { - struct { - /** ch2_sar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch2_sar1:32; - }; - uint32_t val; -} dmac_ch2_sar1_reg_t; - -/** Type of ch2_dar0 register - * NA - */ -typedef union { - struct { - /** ch2_dar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch2_dar0:32; - }; - uint32_t val; -} dmac_ch2_dar0_reg_t; - -/** Type of ch2_dar1 register - * NA - */ -typedef union { - struct { - /** ch2_dar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch2_dar1:32; - }; - uint32_t val; -} dmac_ch2_dar1_reg_t; - -/** Type of ch2_block_ts0 register - * NA - */ -typedef union { - struct { - /** ch2_block_ts : R/W; bitpos: [21:0]; default: 0; - * NA - */ - uint32_t ch2_block_ts:22; - uint32_t reserved_22:10; - }; - uint32_t val; -} dmac_ch2_block_ts0_reg_t; - -/** Type of ch2_ctl0 register - * NA - */ -typedef union { - struct { - /** ch2_sms : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch2_sms:1; - uint32_t reserved_1:1; - /** ch2_dms : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch2_dms:1; - uint32_t reserved_3:1; - /** ch2_sinc : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch2_sinc:1; - uint32_t reserved_5:1; - /** ch2_dinc : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch2_dinc:1; - uint32_t reserved_7:1; - /** ch2_src_tr_width : R/W; bitpos: [10:8]; default: 2; - * NA - */ - uint32_t ch2_src_tr_width:3; - /** ch2_dst_tr_width : R/W; bitpos: [13:11]; default: 2; - * NA - */ - uint32_t ch2_dst_tr_width:3; - /** ch2_src_msize : R/W; bitpos: [17:14]; default: 0; - * NA - */ - uint32_t ch2_src_msize:4; - /** ch2_dst_msize : R/W; bitpos: [21:18]; default: 0; - * NA - */ - uint32_t ch2_dst_msize:4; - /** ch2_ar_cache : R/W; bitpos: [25:22]; default: 0; - * NA - */ - uint32_t ch2_ar_cache:4; - /** ch2_aw_cache : R/W; bitpos: [29:26]; default: 0; - * NA - */ - uint32_t ch2_aw_cache:4; - /** ch2_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch2_nonposted_lastwrite_en:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} dmac_ch2_ctl0_reg_t; - -/** Type of ch2_ctl1 register - * NA - */ -typedef union { - struct { - /** ch2_ar_prot : R/W; bitpos: [2:0]; default: 0; - * NA - */ - uint32_t ch2_ar_prot:3; - /** ch2_aw_prot : R/W; bitpos: [5:3]; default: 0; - * NA - */ - uint32_t ch2_aw_prot:3; - /** ch2_arlen_en : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch2_arlen_en:1; - /** ch2_arlen : R/W; bitpos: [14:7]; default: 0; - * NA - */ - uint32_t ch2_arlen:8; - /** ch2_awlen_en : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t ch2_awlen_en:1; - /** ch2_awlen : R/W; bitpos: [23:16]; default: 0; - * NA - */ - uint32_t ch2_awlen:8; - /** ch2_src_stat_en : R/W; bitpos: [24]; default: 0; - * NA - */ - uint32_t ch2_src_stat_en:1; - /** ch2_dst_stat_en : R/W; bitpos: [25]; default: 0; - * NA - */ - uint32_t ch2_dst_stat_en:1; - /** ch2_ioc_blktfr : R/W; bitpos: [26]; default: 0; - * NA - */ - uint32_t ch2_ioc_blktfr:1; - uint32_t reserved_27:3; - /** ch2_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch2_shadowreg_or_lli_last:1; - /** ch2_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0; - * NA - */ - uint32_t ch2_shadowreg_or_lli_valid:1; - }; - uint32_t val; -} dmac_ch2_ctl1_reg_t; - -/** Type of ch2_cfg0 register - * NA - */ -typedef union { - struct { - /** ch2_src_multblk_type : R/W; bitpos: [1:0]; default: 0; - * NA - */ - uint32_t ch2_src_multblk_type:2; - /** ch2_dst_multblk_type : R/W; bitpos: [3:2]; default: 0; - * NA - */ - uint32_t ch2_dst_multblk_type:2; - uint32_t reserved_4:14; - /** ch2_rd_uid : RO; bitpos: [21:18]; default: 0; - * NA - */ - uint32_t ch2_rd_uid:4; - uint32_t reserved_22:3; - /** ch2_wr_uid : RO; bitpos: [28:25]; default: 0; - * NA - */ - uint32_t ch2_wr_uid:4; - uint32_t reserved_29:3; - }; - uint32_t val; -} dmac_ch2_cfg0_reg_t; - -/** Type of ch2_cfg1 register - * NA - */ -typedef union { - struct { - /** ch2_tt_fc : R/W; bitpos: [2:0]; default: 3; - * NA - */ - uint32_t ch2_tt_fc:3; - /** ch2_hs_sel_src : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch2_hs_sel_src:1; - /** ch2_hs_sel_dst : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t ch2_hs_sel_dst:1; - /** ch2_src_hwhs_pol : RO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch2_src_hwhs_pol:1; - /** ch2_dst_hwhs_pol : RO; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch2_dst_hwhs_pol:1; - /** ch2_src_per : R/W; bitpos: [8:7]; default: 0; - * NA - */ - uint32_t ch2_src_per:2; - uint32_t reserved_9:3; - /** ch2_dst_per : R/W; bitpos: [13:12]; default: 0; - * NA - */ - uint32_t ch2_dst_per:2; - uint32_t reserved_14:3; - /** ch2_ch_prior : R/W; bitpos: [19:17]; default: 2; - * NA - */ - uint32_t ch2_ch_prior:3; - /** ch2_lock_ch : RO; bitpos: [20]; default: 0; - * NA - */ - uint32_t ch2_lock_ch:1; - /** ch2_lock_ch_l : RO; bitpos: [22:21]; default: 0; - * NA - */ - uint32_t ch2_lock_ch_l:2; - /** ch2_src_osr_lmt : R/W; bitpos: [26:23]; default: 0; - * NA - */ - uint32_t ch2_src_osr_lmt:4; - /** ch2_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0; - * NA - */ - uint32_t ch2_dst_osr_lmt:4; - uint32_t reserved_31:1; - }; - uint32_t val; -} dmac_ch2_cfg1_reg_t; - -/** Type of ch2_llp0 register - * NA - */ -typedef union { - struct { - /** ch2_lms : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch2_lms:1; - uint32_t reserved_1:5; - /** ch2_loc0 : R/W; bitpos: [31:6]; default: 0; - * NA - */ - uint32_t ch2_loc0:26; - }; - uint32_t val; -} dmac_ch2_llp0_reg_t; - -/** Type of ch2_llp1 register - * NA - */ -typedef union { - struct { - /** ch2_loc1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch2_loc1:32; - }; - uint32_t val; -} dmac_ch2_llp1_reg_t; - -/** Type of ch2_swhssrc0 register - * NA - */ -typedef union { - struct { - /** ch2_swhs_req_src : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch2_swhs_req_src:1; - /** ch2_swhs_req_src_we : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch2_swhs_req_src_we:1; - /** ch2_swhs_sglreq_src : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch2_swhs_sglreq_src:1; - /** ch2_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch2_swhs_sglreq_src_we:1; - /** ch2_swhs_lst_src : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch2_swhs_lst_src:1; - /** ch2_swhs_lst_src_we : WO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch2_swhs_lst_src_we:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} dmac_ch2_swhssrc0_reg_t; - -/** Type of ch2_swhsdst0 register - * NA - */ -typedef union { - struct { - /** ch2_swhs_req_dst : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch2_swhs_req_dst:1; - /** ch2_swhs_req_dst_we : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch2_swhs_req_dst_we:1; - /** ch2_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch2_swhs_sglreq_dst:1; - /** ch2_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch2_swhs_sglreq_dst_we:1; - /** ch2_swhs_lst_dst : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch2_swhs_lst_dst:1; - /** ch2_swhs_lst_dst_we : WO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch2_swhs_lst_dst_we:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} dmac_ch2_swhsdst0_reg_t; - -/** Type of ch2_blk_tfr_resumereq0 register - * NA - */ -typedef union { - struct { - /** ch2_blk_tfr_resumereq : WO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch2_blk_tfr_resumereq:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} dmac_ch2_blk_tfr_resumereq0_reg_t; - -/** Type of ch2_axi_id0 register - * NA - */ -typedef union { - struct { - /** ch2_axi_read_id_suffix : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch2_axi_read_id_suffix:1; - uint32_t reserved_1:15; - /** ch2_axi_write_id_suffix : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t ch2_axi_write_id_suffix:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} dmac_ch2_axi_id0_reg_t; - -/** Type of ch2_axi_qos0 register - * NA - */ -typedef union { - struct { - /** ch2_axi_awqos : R/W; bitpos: [3:0]; default: 0; - * NA - */ - uint32_t ch2_axi_awqos:4; - /** ch2_axi_arqos : R/W; bitpos: [7:4]; default: 0; - * NA - */ - uint32_t ch2_axi_arqos:4; - uint32_t reserved_8:24; - }; - uint32_t val; -} dmac_ch2_axi_qos0_reg_t; - -/** Type of ch3_sar0 register - * NA - */ -typedef union { - struct { - /** ch3_sar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch3_sar0:32; - }; - uint32_t val; -} dmac_ch3_sar0_reg_t; - -/** Type of ch3_sar1 register - * NA - */ -typedef union { - struct { - /** ch3_sar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch3_sar1:32; - }; - uint32_t val; -} dmac_ch3_sar1_reg_t; - -/** Type of ch3_dar0 register - * NA - */ -typedef union { - struct { - /** ch3_dar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch3_dar0:32; - }; - uint32_t val; -} dmac_ch3_dar0_reg_t; - -/** Type of ch3_dar1 register - * NA - */ -typedef union { - struct { - /** ch3_dar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch3_dar1:32; - }; - uint32_t val; -} dmac_ch3_dar1_reg_t; - -/** Type of ch3_block_ts0 register - * NA - */ -typedef union { - struct { - /** ch3_block_ts : R/W; bitpos: [21:0]; default: 0; - * NA - */ - uint32_t ch3_block_ts:22; - uint32_t reserved_22:10; - }; - uint32_t val; -} dmac_ch3_block_ts0_reg_t; - -/** Type of ch3_ctl0 register - * NA - */ -typedef union { - struct { - /** ch3_sms : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch3_sms:1; - uint32_t reserved_1:1; - /** ch3_dms : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch3_dms:1; - uint32_t reserved_3:1; - /** ch3_sinc : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch3_sinc:1; - uint32_t reserved_5:1; - /** ch3_dinc : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch3_dinc:1; - uint32_t reserved_7:1; - /** ch3_src_tr_width : R/W; bitpos: [10:8]; default: 2; - * NA - */ - uint32_t ch3_src_tr_width:3; - /** ch3_dst_tr_width : R/W; bitpos: [13:11]; default: 2; - * NA - */ - uint32_t ch3_dst_tr_width:3; - /** ch3_src_msize : R/W; bitpos: [17:14]; default: 0; - * NA - */ - uint32_t ch3_src_msize:4; - /** ch3_dst_msize : R/W; bitpos: [21:18]; default: 0; - * NA - */ - uint32_t ch3_dst_msize:4; - /** ch3_ar_cache : R/W; bitpos: [25:22]; default: 0; - * NA - */ - uint32_t ch3_ar_cache:4; - /** ch3_aw_cache : R/W; bitpos: [29:26]; default: 0; - * NA - */ - uint32_t ch3_aw_cache:4; - /** ch3_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch3_nonposted_lastwrite_en:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} dmac_ch3_ctl0_reg_t; - -/** Type of ch3_ctl1 register - * NA - */ -typedef union { - struct { - /** ch3_ar_prot : R/W; bitpos: [2:0]; default: 0; - * NA - */ - uint32_t ch3_ar_prot:3; - /** ch3_aw_prot : R/W; bitpos: [5:3]; default: 0; - * NA - */ - uint32_t ch3_aw_prot:3; - /** ch3_arlen_en : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch3_arlen_en:1; - /** ch3_arlen : R/W; bitpos: [14:7]; default: 0; - * NA - */ - uint32_t ch3_arlen:8; - /** ch3_awlen_en : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t ch3_awlen_en:1; - /** ch3_awlen : R/W; bitpos: [23:16]; default: 0; - * NA - */ - uint32_t ch3_awlen:8; - /** ch3_src_stat_en : R/W; bitpos: [24]; default: 0; - * NA - */ - uint32_t ch3_src_stat_en:1; - /** ch3_dst_stat_en : R/W; bitpos: [25]; default: 0; - * NA - */ - uint32_t ch3_dst_stat_en:1; - /** ch3_ioc_blktfr : R/W; bitpos: [26]; default: 0; - * NA - */ - uint32_t ch3_ioc_blktfr:1; - uint32_t reserved_27:3; - /** ch3_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch3_shadowreg_or_lli_last:1; - /** ch3_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0; - * NA - */ - uint32_t ch3_shadowreg_or_lli_valid:1; - }; - uint32_t val; -} dmac_ch3_ctl1_reg_t; - -/** Type of ch3_cfg0 register - * NA - */ -typedef union { - struct { - /** ch3_src_multblk_type : R/W; bitpos: [1:0]; default: 0; - * NA - */ - uint32_t ch3_src_multblk_type:2; - /** ch3_dst_multblk_type : R/W; bitpos: [3:2]; default: 0; - * NA - */ - uint32_t ch3_dst_multblk_type:2; - uint32_t reserved_4:14; - /** ch3_rd_uid : RO; bitpos: [21:18]; default: 0; - * NA - */ - uint32_t ch3_rd_uid:4; - uint32_t reserved_22:3; - /** ch3_wr_uid : RO; bitpos: [28:25]; default: 0; - * NA - */ - uint32_t ch3_wr_uid:4; - uint32_t reserved_29:3; - }; - uint32_t val; -} dmac_ch3_cfg0_reg_t; - -/** Type of ch3_cfg1 register - * NA - */ -typedef union { - struct { - /** ch3_tt_fc : R/W; bitpos: [2:0]; default: 3; - * NA - */ - uint32_t ch3_tt_fc:3; - /** ch3_hs_sel_src : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch3_hs_sel_src:1; - /** ch3_hs_sel_dst : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t ch3_hs_sel_dst:1; - /** ch3_src_hwhs_pol : RO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch3_src_hwhs_pol:1; - /** ch3_dst_hwhs_pol : RO; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch3_dst_hwhs_pol:1; - /** ch3_src_per : R/W; bitpos: [8:7]; default: 0; - * NA - */ - uint32_t ch3_src_per:2; - uint32_t reserved_9:3; - /** ch3_dst_per : R/W; bitpos: [13:12]; default: 0; - * NA - */ - uint32_t ch3_dst_per:2; - uint32_t reserved_14:3; - /** ch3_ch_prior : R/W; bitpos: [19:17]; default: 1; - * NA - */ - uint32_t ch3_ch_prior:3; - /** ch3_lock_ch : RO; bitpos: [20]; default: 0; - * NA - */ - uint32_t ch3_lock_ch:1; - /** ch3_lock_ch_l : RO; bitpos: [22:21]; default: 0; - * NA - */ - uint32_t ch3_lock_ch_l:2; - /** ch3_src_osr_lmt : R/W; bitpos: [26:23]; default: 0; - * NA - */ - uint32_t ch3_src_osr_lmt:4; - /** ch3_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0; - * NA - */ - uint32_t ch3_dst_osr_lmt:4; - uint32_t reserved_31:1; - }; - uint32_t val; -} dmac_ch3_cfg1_reg_t; - -/** Type of ch3_llp0 register - * NA - */ -typedef union { - struct { - /** ch3_lms : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch3_lms:1; - uint32_t reserved_1:5; - /** ch3_loc0 : R/W; bitpos: [31:6]; default: 0; - * NA - */ - uint32_t ch3_loc0:26; - }; - uint32_t val; -} dmac_ch3_llp0_reg_t; - -/** Type of ch3_llp1 register - * NA - */ -typedef union { - struct { - /** ch3_loc1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch3_loc1:32; - }; - uint32_t val; -} dmac_ch3_llp1_reg_t; - -/** Type of ch3_swhssrc0 register - * NA - */ -typedef union { - struct { - /** ch3_swhs_req_src : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch3_swhs_req_src:1; - /** ch3_swhs_req_src_we : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch3_swhs_req_src_we:1; - /** ch3_swhs_sglreq_src : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch3_swhs_sglreq_src:1; - /** ch3_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch3_swhs_sglreq_src_we:1; - /** ch3_swhs_lst_src : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch3_swhs_lst_src:1; - /** ch3_swhs_lst_src_we : WO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch3_swhs_lst_src_we:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} dmac_ch3_swhssrc0_reg_t; - -/** Type of ch3_swhsdst0 register - * NA - */ -typedef union { - struct { - /** ch3_swhs_req_dst : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch3_swhs_req_dst:1; - /** ch3_swhs_req_dst_we : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch3_swhs_req_dst_we:1; - /** ch3_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch3_swhs_sglreq_dst:1; - /** ch3_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch3_swhs_sglreq_dst_we:1; - /** ch3_swhs_lst_dst : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch3_swhs_lst_dst:1; - /** ch3_swhs_lst_dst_we : WO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch3_swhs_lst_dst_we:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} dmac_ch3_swhsdst0_reg_t; - -/** Type of ch3_blk_tfr_resumereq0 register - * NA - */ -typedef union { - struct { - /** ch3_blk_tfr_resumereq : WO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch3_blk_tfr_resumereq:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} dmac_ch3_blk_tfr_resumereq0_reg_t; - -/** Type of ch3_axi_id0 register - * NA - */ -typedef union { - struct { - /** ch3_axi_read_id_suffix : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch3_axi_read_id_suffix:1; - uint32_t reserved_1:15; - /** ch3_axi_write_id_suffix : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t ch3_axi_write_id_suffix:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} dmac_ch3_axi_id0_reg_t; - -/** Type of ch3_axi_qos0 register - * NA - */ -typedef union { - struct { - /** ch3_axi_awqos : R/W; bitpos: [3:0]; default: 0; - * NA - */ - uint32_t ch3_axi_awqos:4; - /** ch3_axi_arqos : R/W; bitpos: [7:4]; default: 0; - * NA - */ - uint32_t ch3_axi_arqos:4; - uint32_t reserved_8:24; - }; - uint32_t val; -} dmac_ch3_axi_qos0_reg_t; - -/** Type of ch4_sar0 register - * NA - */ -typedef union { - struct { - /** ch4_sar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch4_sar0:32; - }; - uint32_t val; -} dmac_ch4_sar0_reg_t; - -/** Type of ch4_sar1 register - * NA - */ -typedef union { - struct { - /** ch4_sar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch4_sar1:32; - }; - uint32_t val; -} dmac_ch4_sar1_reg_t; - -/** Type of ch4_dar0 register - * NA - */ -typedef union { - struct { - /** ch4_dar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch4_dar0:32; - }; - uint32_t val; -} dmac_ch4_dar0_reg_t; - -/** Type of ch4_dar1 register - * NA - */ -typedef union { - struct { - /** ch4_dar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch4_dar1:32; - }; - uint32_t val; -} dmac_ch4_dar1_reg_t; - -/** Type of ch4_block_ts0 register - * NA - */ -typedef union { - struct { - /** ch4_block_ts : R/W; bitpos: [21:0]; default: 0; - * NA - */ - uint32_t ch4_block_ts:22; - uint32_t reserved_22:10; - }; - uint32_t val; -} dmac_ch4_block_ts0_reg_t; - -/** Type of ch4_ctl0 register - * NA - */ -typedef union { - struct { - /** ch4_sms : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch4_sms:1; - uint32_t reserved_1:1; - /** ch4_dms : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch4_dms:1; - uint32_t reserved_3:1; - /** ch4_sinc : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch4_sinc:1; - uint32_t reserved_5:1; - /** ch4_dinc : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch4_dinc:1; - uint32_t reserved_7:1; - /** ch4_src_tr_width : R/W; bitpos: [10:8]; default: 2; - * NA - */ - uint32_t ch4_src_tr_width:3; - /** ch4_dst_tr_width : R/W; bitpos: [13:11]; default: 2; - * NA - */ - uint32_t ch4_dst_tr_width:3; - /** ch4_src_msize : R/W; bitpos: [17:14]; default: 0; - * NA - */ - uint32_t ch4_src_msize:4; - /** ch4_dst_msize : R/W; bitpos: [21:18]; default: 0; - * NA - */ - uint32_t ch4_dst_msize:4; - /** ch4_ar_cache : R/W; bitpos: [25:22]; default: 0; - * NA - */ - uint32_t ch4_ar_cache:4; - /** ch4_aw_cache : R/W; bitpos: [29:26]; default: 0; - * NA - */ - uint32_t ch4_aw_cache:4; - /** ch4_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch4_nonposted_lastwrite_en:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} dmac_ch4_ctl0_reg_t; - -/** Type of ch4_ctl1 register - * NA - */ -typedef union { - struct { - /** ch4_ar_prot : R/W; bitpos: [2:0]; default: 0; - * NA - */ - uint32_t ch4_ar_prot:3; - /** ch4_aw_prot : R/W; bitpos: [5:3]; default: 0; - * NA - */ - uint32_t ch4_aw_prot:3; - /** ch4_arlen_en : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch4_arlen_en:1; - /** ch4_arlen : R/W; bitpos: [14:7]; default: 0; - * NA - */ - uint32_t ch4_arlen:8; - /** ch4_awlen_en : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t ch4_awlen_en:1; - /** ch4_awlen : R/W; bitpos: [23:16]; default: 0; - * NA - */ - uint32_t ch4_awlen:8; - /** ch4_src_stat_en : R/W; bitpos: [24]; default: 0; - * NA - */ - uint32_t ch4_src_stat_en:1; - /** ch4_dst_stat_en : R/W; bitpos: [25]; default: 0; - * NA - */ - uint32_t ch4_dst_stat_en:1; - /** ch4_ioc_blktfr : R/W; bitpos: [26]; default: 0; - * NA - */ - uint32_t ch4_ioc_blktfr:1; - uint32_t reserved_27:3; - /** ch4_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch4_shadowreg_or_lli_last:1; - /** ch4_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0; - * NA - */ - uint32_t ch4_shadowreg_or_lli_valid:1; - }; - uint32_t val; -} dmac_ch4_ctl1_reg_t; - -/** Type of ch4_cfg0 register - * NA - */ -typedef union { - struct { - /** ch4_src_multblk_type : R/W; bitpos: [1:0]; default: 0; - * NA - */ - uint32_t ch4_src_multblk_type:2; - /** ch4_dst_multblk_type : R/W; bitpos: [3:2]; default: 0; - * NA - */ - uint32_t ch4_dst_multblk_type:2; - uint32_t reserved_4:14; - /** ch4_rd_uid : RO; bitpos: [21:18]; default: 0; - * NA - */ - uint32_t ch4_rd_uid:4; - uint32_t reserved_22:3; - /** ch4_wr_uid : RO; bitpos: [28:25]; default: 0; - * NA - */ - uint32_t ch4_wr_uid:4; - uint32_t reserved_29:3; - }; - uint32_t val; -} dmac_ch4_cfg0_reg_t; - -/** Type of ch4_cfg1 register - * NA - */ -typedef union { - struct { - /** ch4_tt_fc : R/W; bitpos: [2:0]; default: 3; - * NA - */ - uint32_t ch4_tt_fc:3; - /** ch4_hs_sel_src : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch4_hs_sel_src:1; - /** ch4_hs_sel_dst : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t ch4_hs_sel_dst:1; - /** ch4_src_hwhs_pol : RO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch4_src_hwhs_pol:1; - /** ch4_dst_hwhs_pol : RO; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch4_dst_hwhs_pol:1; - /** ch4_src_per : R/W; bitpos: [8:7]; default: 0; - * NA - */ - uint32_t ch4_src_per:2; - uint32_t reserved_9:3; - /** ch4_dst_per : R/W; bitpos: [13:12]; default: 0; - * NA - */ - uint32_t ch4_dst_per:2; - uint32_t reserved_14:3; - /** ch4_ch_prior : R/W; bitpos: [19:17]; default: 0; - * NA - */ - uint32_t ch4_ch_prior:3; - /** ch4_lock_ch : RO; bitpos: [20]; default: 0; - * NA - */ - uint32_t ch4_lock_ch:1; - /** ch4_lock_ch_l : RO; bitpos: [22:21]; default: 0; - * NA - */ - uint32_t ch4_lock_ch_l:2; - /** ch4_src_osr_lmt : R/W; bitpos: [26:23]; default: 0; - * NA - */ - uint32_t ch4_src_osr_lmt:4; - /** ch4_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0; - * NA - */ - uint32_t ch4_dst_osr_lmt:4; - uint32_t reserved_31:1; - }; - uint32_t val; -} dmac_ch4_cfg1_reg_t; - -/** Type of ch4_llp0 register - * NA - */ -typedef union { - struct { - /** ch4_lms : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch4_lms:1; - uint32_t reserved_1:5; - /** ch4_loc0 : R/W; bitpos: [31:6]; default: 0; - * NA - */ - uint32_t ch4_loc0:26; - }; - uint32_t val; -} dmac_ch4_llp0_reg_t; - -/** Type of ch4_llp1 register - * NA - */ -typedef union { - struct { - /** ch4_loc1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch4_loc1:32; - }; - uint32_t val; -} dmac_ch4_llp1_reg_t; - -/** Type of ch4_swhssrc0 register - * NA - */ -typedef union { - struct { - /** ch4_swhs_req_src : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch4_swhs_req_src:1; - /** ch4_swhs_req_src_we : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch4_swhs_req_src_we:1; - /** ch4_swhs_sglreq_src : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch4_swhs_sglreq_src:1; - /** ch4_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch4_swhs_sglreq_src_we:1; - /** ch4_swhs_lst_src : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch4_swhs_lst_src:1; - /** ch4_swhs_lst_src_we : WO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch4_swhs_lst_src_we:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} dmac_ch4_swhssrc0_reg_t; - -/** Type of ch4_swhsdst0 register - * NA - */ -typedef union { - struct { - /** ch4_swhs_req_dst : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch4_swhs_req_dst:1; - /** ch4_swhs_req_dst_we : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch4_swhs_req_dst_we:1; - /** ch4_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch4_swhs_sglreq_dst:1; - /** ch4_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch4_swhs_sglreq_dst_we:1; - /** ch4_swhs_lst_dst : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch4_swhs_lst_dst:1; - /** ch4_swhs_lst_dst_we : WO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch4_swhs_lst_dst_we:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} dmac_ch4_swhsdst0_reg_t; - -/** Type of ch4_blk_tfr_resumereq0 register - * NA - */ -typedef union { - struct { - /** ch4_blk_tfr_resumereq : WO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch4_blk_tfr_resumereq:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} dmac_ch4_blk_tfr_resumereq0_reg_t; - -/** Type of ch4_axi_id0 register - * NA - */ -typedef union { - struct { - /** ch4_axi_read_id_suffix : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch4_axi_read_id_suffix:1; - uint32_t reserved_1:15; - /** ch4_axi_write_id_suffix : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t ch4_axi_write_id_suffix:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} dmac_ch4_axi_id0_reg_t; - -/** Type of ch4_axi_qos0 register - * NA - */ -typedef union { - struct { - /** ch4_axi_awqos : R/W; bitpos: [3:0]; default: 0; - * NA - */ - uint32_t ch4_axi_awqos:4; - /** ch4_axi_arqos : R/W; bitpos: [7:4]; default: 0; - * NA - */ - uint32_t ch4_axi_arqos:4; - uint32_t reserved_8:24; - }; - uint32_t val; -} dmac_ch4_axi_qos0_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of intstatus0 register - * NA - */ -typedef union { - struct { - /** ch1_intstat : RO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch1_intstat:1; - /** ch2_intstat : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch2_intstat:1; - /** ch3_intstat : RO; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch3_intstat:1; - /** ch4_intstat : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch4_intstat:1; - uint32_t reserved_4:12; - /** commonreg_intstat : RO; bitpos: [16]; default: 0; - * NA - */ - uint32_t commonreg_intstat:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} dmac_intstatus0_reg_t; - -/** Type of commonreg_intclear0 register - * NA - */ -typedef union { - struct { - /** clear_slvif_commonreg_dec_err_intstat : WO; bitpos: [0]; default: 0; - * NA - */ - uint32_t clear_slvif_commonreg_dec_err_intstat:1; - /** clear_slvif_commonreg_wr2ro_err_intstat : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t clear_slvif_commonreg_wr2ro_err_intstat:1; - /** clear_slvif_commonreg_rd2wo_err_intstat : WO; bitpos: [2]; default: 0; - * NA - */ - uint32_t clear_slvif_commonreg_rd2wo_err_intstat:1; - /** clear_slvif_commonreg_wronhold_err_intstat : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t clear_slvif_commonreg_wronhold_err_intstat:1; - uint32_t reserved_4:3; - /** clear_slvif_commonreg_wrparity_err_intstat : WO; bitpos: [7]; default: 0; - * NA - */ - uint32_t clear_slvif_commonreg_wrparity_err_intstat:1; - /** clear_slvif_undefinedreg_dec_err_intstat : WO; bitpos: [8]; default: 0; - * NA - */ - uint32_t clear_slvif_undefinedreg_dec_err_intstat:1; - /** clear_mxif1_rch0_eccprot_correrr_intstat : WO; bitpos: [9]; default: 0; - * NA - */ - uint32_t clear_mxif1_rch0_eccprot_correrr_intstat:1; - /** clear_mxif1_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [10]; default: 0; - * NA - */ - uint32_t clear_mxif1_rch0_eccprot_uncorrerr_intstat:1; - /** clear_mxif1_rch1_eccprot_correrr_intstat : WO; bitpos: [11]; default: 0; - * NA - */ - uint32_t clear_mxif1_rch1_eccprot_correrr_intstat:1; - /** clear_mxif1_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [12]; default: 0; - * NA - */ - uint32_t clear_mxif1_rch1_eccprot_uncorrerr_intstat:1; - /** clear_mxif1_bch_eccprot_correrr_intstat : WO; bitpos: [13]; default: 0; - * NA - */ - uint32_t clear_mxif1_bch_eccprot_correrr_intstat:1; - /** clear_mxif1_bch_eccprot_uncorrerr_intstat : WO; bitpos: [14]; default: 0; - * NA - */ - uint32_t clear_mxif1_bch_eccprot_uncorrerr_intstat:1; - /** clear_mxif2_rch0_eccprot_correrr_intstat : WO; bitpos: [15]; default: 0; - * NA - */ - uint32_t clear_mxif2_rch0_eccprot_correrr_intstat:1; - /** clear_mxif2_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [16]; default: 0; - * NA - */ - uint32_t clear_mxif2_rch0_eccprot_uncorrerr_intstat:1; - /** clear_mxif2_rch1_eccprot_correrr_intstat : WO; bitpos: [17]; default: 0; - * NA - */ - uint32_t clear_mxif2_rch1_eccprot_correrr_intstat:1; - /** clear_mxif2_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [18]; default: 0; - * NA - */ - uint32_t clear_mxif2_rch1_eccprot_uncorrerr_intstat:1; - /** clear_mxif2_bch_eccprot_correrr_intstat : WO; bitpos: [19]; default: 0; - * NA - */ - uint32_t clear_mxif2_bch_eccprot_correrr_intstat:1; - /** clear_mxif2_bch_eccprot_uncorrerr_intstat : WO; bitpos: [20]; default: 0; - * NA - */ - uint32_t clear_mxif2_bch_eccprot_uncorrerr_intstat:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} dmac_commonreg_intclear0_reg_t; - -/** Type of commonreg_intstatus_enable0 register - * NA - */ -typedef union { - struct { - /** enable_slvif_commonreg_dec_err_intstat : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t enable_slvif_commonreg_dec_err_intstat:1; - /** enable_slvif_commonreg_wr2ro_err_intstat : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t enable_slvif_commonreg_wr2ro_err_intstat:1; - /** enable_slvif_commonreg_rd2wo_err_intstat : R/W; bitpos: [2]; default: 1; - * NA - */ - uint32_t enable_slvif_commonreg_rd2wo_err_intstat:1; - /** enable_slvif_commonreg_wronhold_err_intstat : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t enable_slvif_commonreg_wronhold_err_intstat:1; - uint32_t reserved_4:3; - /** enable_slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 1; - * NA - */ - uint32_t enable_slvif_commonreg_wrparity_err_intstat:1; - /** enable_slvif_undefinedreg_dec_err_intstat : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t enable_slvif_undefinedreg_dec_err_intstat:1; - /** enable_mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 1; - * NA - */ - uint32_t enable_mxif1_rch0_eccprot_correrr_intstat:1; - /** enable_mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 1; - * NA - */ - uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intstat:1; - /** enable_mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 1; - * NA - */ - uint32_t enable_mxif1_rch1_eccprot_correrr_intstat:1; - /** enable_mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 1; - * NA - */ - uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intstat:1; - /** enable_mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 1; - * NA - */ - uint32_t enable_mxif1_bch_eccprot_correrr_intstat:1; - /** enable_mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 1; - * NA - */ - uint32_t enable_mxif1_bch_eccprot_uncorrerr_intstat:1; - /** enable_mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 1; - * NA - */ - uint32_t enable_mxif2_rch0_eccprot_correrr_intstat:1; - /** enable_mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 1; - * NA - */ - uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intstat:1; - /** enable_mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 1; - * NA - */ - uint32_t enable_mxif2_rch1_eccprot_correrr_intstat:1; - /** enable_mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 1; - * NA - */ - uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intstat:1; - /** enable_mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 1; - * NA - */ - uint32_t enable_mxif2_bch_eccprot_correrr_intstat:1; - /** enable_mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 1; - * NA - */ - uint32_t enable_mxif2_bch_eccprot_uncorrerr_intstat:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} dmac_commonreg_intstatus_enable0_reg_t; - -/** Type of commonreg_intsignal_enable0 register - * NA - */ -typedef union { - struct { - /** enable_slvif_commonreg_dec_err_intsignal : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t enable_slvif_commonreg_dec_err_intsignal:1; - /** enable_slvif_commonreg_wr2ro_err_intsignal : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t enable_slvif_commonreg_wr2ro_err_intsignal:1; - /** enable_slvif_commonreg_rd2wo_err_intsignal : R/W; bitpos: [2]; default: 1; - * NA - */ - uint32_t enable_slvif_commonreg_rd2wo_err_intsignal:1; - /** enable_slvif_commonreg_wronhold_err_intsignal : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t enable_slvif_commonreg_wronhold_err_intsignal:1; - uint32_t reserved_4:3; - /** enable_slvif_commonreg_wrparity_err_intsignal : RO; bitpos: [7]; default: 1; - * NA - */ - uint32_t enable_slvif_commonreg_wrparity_err_intsignal:1; - /** enable_slvif_undefinedreg_dec_err_intsignal : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t enable_slvif_undefinedreg_dec_err_intsignal:1; - /** enable_mxif1_rch0_eccprot_correrr_intsignal : RO; bitpos: [9]; default: 1; - * NA - */ - uint32_t enable_mxif1_rch0_eccprot_correrr_intsignal:1; - /** enable_mxif1_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [10]; default: 1; - * NA - */ - uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intsignal:1; - /** enable_mxif1_rch1_eccprot_correrr_intsignal : RO; bitpos: [11]; default: 1; - * NA - */ - uint32_t enable_mxif1_rch1_eccprot_correrr_intsignal:1; - /** enable_mxif1_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [12]; default: 1; - * NA - */ - uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intsignal:1; - /** enable_mxif1_bch_eccprot_correrr_intsignal : RO; bitpos: [13]; default: 1; - * NA - */ - uint32_t enable_mxif1_bch_eccprot_correrr_intsignal:1; - /** enable_mxif1_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [14]; default: 1; - * NA - */ - uint32_t enable_mxif1_bch_eccprot_uncorrerr_intsignal:1; - /** enable_mxif2_rch0_eccprot_correrr_intsignal : RO; bitpos: [15]; default: 1; - * NA - */ - uint32_t enable_mxif2_rch0_eccprot_correrr_intsignal:1; - /** enable_mxif2_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [16]; default: 1; - * NA - */ - uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intsignal:1; - /** enable_mxif2_rch1_eccprot_correrr_intsignal : RO; bitpos: [17]; default: 1; - * NA - */ - uint32_t enable_mxif2_rch1_eccprot_correrr_intsignal:1; - /** enable_mxif2_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [18]; default: 1; - * NA - */ - uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intsignal:1; - /** enable_mxif2_bch_eccprot_correrr_intsignal : RO; bitpos: [19]; default: 1; - * NA - */ - uint32_t enable_mxif2_bch_eccprot_correrr_intsignal:1; - /** enable_mxif2_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [20]; default: 1; - * NA - */ - uint32_t enable_mxif2_bch_eccprot_uncorrerr_intsignal:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} dmac_commonreg_intsignal_enable0_reg_t; - -/** Type of commonreg_intstatus0 register - * NA - */ -typedef union { - struct { - /** slvif_commonreg_dec_err_intstat : RO; bitpos: [0]; default: 0; - * NA - */ - uint32_t slvif_commonreg_dec_err_intstat:1; - /** slvif_commonreg_wr2ro_err_intstat : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t slvif_commonreg_wr2ro_err_intstat:1; - /** slvif_commonreg_rd2wo_err_intstat : RO; bitpos: [2]; default: 0; - * NA - */ - uint32_t slvif_commonreg_rd2wo_err_intstat:1; - /** slvif_commonreg_wronhold_err_intstat : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t slvif_commonreg_wronhold_err_intstat:1; - uint32_t reserved_4:3; - /** slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 0; - * NA - */ - uint32_t slvif_commonreg_wrparity_err_intstat:1; - /** slvif_undefinedreg_dec_err_intstat : RO; bitpos: [8]; default: 0; - * NA - */ - uint32_t slvif_undefinedreg_dec_err_intstat:1; - /** mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 0; - * NA - */ - uint32_t mxif1_rch0_eccprot_correrr_intstat:1; - /** mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 0; - * NA - */ - uint32_t mxif1_rch0_eccprot_uncorrerr_intstat:1; - /** mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 0; - * NA - */ - uint32_t mxif1_rch1_eccprot_correrr_intstat:1; - /** mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 0; - * NA - */ - uint32_t mxif1_rch1_eccprot_uncorrerr_intstat:1; - /** mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 0; - * NA - */ - uint32_t mxif1_bch_eccprot_correrr_intstat:1; - /** mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 0; - * NA - */ - uint32_t mxif1_bch_eccprot_uncorrerr_intstat:1; - /** mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 0; - * NA - */ - uint32_t mxif2_rch0_eccprot_correrr_intstat:1; - /** mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 0; - * NA - */ - uint32_t mxif2_rch0_eccprot_uncorrerr_intstat:1; - /** mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 0; - * NA - */ - uint32_t mxif2_rch1_eccprot_correrr_intstat:1; - /** mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 0; - * NA - */ - uint32_t mxif2_rch1_eccprot_uncorrerr_intstat:1; - /** mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 0; - * NA - */ - uint32_t mxif2_bch_eccprot_correrr_intstat:1; - /** mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 0; - * NA - */ - uint32_t mxif2_bch_eccprot_uncorrerr_intstat:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} dmac_commonreg_intstatus0_reg_t; - -/** Type of ch1_intstatus_enable0 register - * NA - */ -typedef union { - struct { - /** ch1_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch1_enable_block_tfr_done_intstat:1; - /** ch1_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch1_enable_dma_tfr_done_intstat:1; - uint32_t reserved_2:1; - /** ch1_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch1_enable_src_transcomp_intstat:1; - /** ch1_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t ch1_enable_dst_transcomp_intstat:1; - /** ch1_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1; - * NA - */ - uint32_t ch1_enable_src_dec_err_intstat:1; - /** ch1_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t ch1_enable_dst_dec_err_intstat:1; - /** ch1_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t ch1_enable_src_slv_err_intstat:1; - /** ch1_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t ch1_enable_dst_slv_err_intstat:1; - /** ch1_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t ch1_enable_lli_rd_dec_err_intstat:1; - /** ch1_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t ch1_enable_lli_wr_dec_err_intstat:1; - /** ch1_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t ch1_enable_lli_rd_slv_err_intstat:1; - /** ch1_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1; - * NA - */ - uint32_t ch1_enable_lli_wr_slv_err_intstat:1; - /** ch1_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1; - * NA - */ - uint32_t ch1_enable_shadowreg_or_lli_invalid_err_intstat:1; - /** ch1_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_multiblktype_err_intstat:1; - uint32_t reserved_15:1; - /** ch1_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_dec_err_intstat:1; - /** ch1_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_wr2ro_err_intstat:1; - /** ch1_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_rd2rwo_err_intstat:1; - /** ch1_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_wronchen_err_intstat:1; - /** ch1_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_shadowreg_wron_valid_err_intstat:1; - /** ch1_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_wronhold_err_intstat:1; - uint32_t reserved_22:3; - /** ch1_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_wrparity_err_intstat:1; - uint32_t reserved_26:1; - /** ch1_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1; - * NA - */ - uint32_t ch1_enable_ch_lock_cleared_intstat:1; - /** ch1_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1; - * NA - */ - uint32_t ch1_enable_ch_src_suspended_intstat:1; - /** ch1_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1; - * NA - */ - uint32_t ch1_enable_ch_suspended_intstat:1; - /** ch1_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1; - * NA - */ - uint32_t ch1_enable_ch_disabled_intstat:1; - /** ch1_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1; - * NA - */ - uint32_t ch1_enable_ch_aborted_intstat:1; - }; - uint32_t val; -} dmac_ch1_intstatus_enable0_reg_t; - -/** Type of ch1_intstatus_enable1 register - * NA - */ -typedef union { - struct { - /** ch1_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch1_enable_ecc_prot_chmem_correrr_intstat:1; - /** ch1_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch1_enable_ecc_prot_chmem_uncorrerr_intstat:1; - /** ch1_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1; - * NA - */ - uint32_t ch1_enable_ecc_prot_uidmem_correrr_intstat:1; - /** ch1_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch1_enable_ecc_prot_uidmem_uncorrerr_intstat:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch1_intstatus_enable1_reg_t; - -/** Type of ch1_intstatus0 register - * NA - */ -typedef union { - struct { - /** ch1_block_tfr_done_intstat : RO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch1_block_tfr_done_intstat:1; - /** ch1_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch1_dma_tfr_done_intstat:1; - uint32_t reserved_2:1; - /** ch1_src_transcomp_intstat : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch1_src_transcomp_intstat:1; - /** ch1_dst_transcomp_intstat : RO; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch1_dst_transcomp_intstat:1; - /** ch1_src_dec_err_intstat : RO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch1_src_dec_err_intstat:1; - /** ch1_dst_dec_err_intstat : RO; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch1_dst_dec_err_intstat:1; - /** ch1_src_slv_err_intstat : RO; bitpos: [7]; default: 0; - * NA - */ - uint32_t ch1_src_slv_err_intstat:1; - /** ch1_dst_slv_err_intstat : RO; bitpos: [8]; default: 0; - * NA - */ - uint32_t ch1_dst_slv_err_intstat:1; - /** ch1_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0; - * NA - */ - uint32_t ch1_lli_rd_dec_err_intstat:1; - /** ch1_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0; - * NA - */ - uint32_t ch1_lli_wr_dec_err_intstat:1; - /** ch1_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0; - * NA - */ - uint32_t ch1_lli_rd_slv_err_intstat:1; - /** ch1_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0; - * NA - */ - uint32_t ch1_lli_wr_slv_err_intstat:1; - /** ch1_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0; - * NA - */ - uint32_t ch1_shadowreg_or_lli_invalid_err_intstat:1; - /** ch1_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0; - * NA - */ - uint32_t ch1_slvif_multiblktype_err_intstat:1; - uint32_t reserved_15:1; - /** ch1_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0; - * NA - */ - uint32_t ch1_slvif_dec_err_intstat:1; - /** ch1_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0; - * NA - */ - uint32_t ch1_slvif_wr2ro_err_intstat:1; - /** ch1_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0; - * NA - */ - uint32_t ch1_slvif_rd2rwo_err_intstat:1; - /** ch1_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0; - * NA - */ - uint32_t ch1_slvif_wronchen_err_intstat:1; - /** ch1_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0; - * NA - */ - uint32_t ch1_slvif_shadowreg_wron_valid_err_intstat:1; - /** ch1_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0; - * NA - */ - uint32_t ch1_slvif_wronhold_err_intstat:1; - uint32_t reserved_22:3; - /** ch1_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0; - * NA - */ - uint32_t ch1_slvif_wrparity_err_intstat:1; - uint32_t reserved_26:1; - /** ch1_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0; - * NA - */ - uint32_t ch1_ch_lock_cleared_intstat:1; - /** ch1_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0; - * NA - */ - uint32_t ch1_ch_src_suspended_intstat:1; - /** ch1_ch_suspended_intstat : RO; bitpos: [29]; default: 0; - * NA - */ - uint32_t ch1_ch_suspended_intstat:1; - /** ch1_ch_disabled_intstat : RO; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch1_ch_disabled_intstat:1; - /** ch1_ch_aborted_intstat : RO; bitpos: [31]; default: 0; - * NA - */ - uint32_t ch1_ch_aborted_intstat:1; - }; - uint32_t val; -} dmac_ch1_intstatus0_reg_t; - -/** Type of ch1_intstatus1 register - * NA - */ -typedef union { - struct { - /** ch1_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch1_ecc_prot_chmem_correrr_intstat:1; - /** ch1_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch1_ecc_prot_chmem_uncorrerr_intstat:1; - /** ch1_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch1_ecc_prot_uidmem_correrr_intstat:1; - /** ch1_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch1_ecc_prot_uidmem_uncorrerr_intstat:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch1_intstatus1_reg_t; - -/** Type of ch1_intsignal_enable0 register - * NA - */ -typedef union { - struct { - /** ch1_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch1_enable_block_tfr_done_intsignal:1; - /** ch1_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch1_enable_dma_tfr_done_intsignal:1; - uint32_t reserved_2:1; - /** ch1_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch1_enable_src_transcomp_intsignal:1; - /** ch1_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t ch1_enable_dst_transcomp_intsignal:1; - /** ch1_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1; - * NA - */ - uint32_t ch1_enable_src_dec_err_intsignal:1; - /** ch1_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t ch1_enable_dst_dec_err_intsignal:1; - /** ch1_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t ch1_enable_src_slv_err_intsignal:1; - /** ch1_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t ch1_enable_dst_slv_err_intsignal:1; - /** ch1_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t ch1_enable_lli_rd_dec_err_intsignal:1; - /** ch1_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t ch1_enable_lli_wr_dec_err_intsignal:1; - /** ch1_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t ch1_enable_lli_rd_slv_err_intsignal:1; - /** ch1_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1; - * NA - */ - uint32_t ch1_enable_lli_wr_slv_err_intsignal:1; - /** ch1_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1; - * NA - */ - uint32_t ch1_enable_shadowreg_or_lli_invalid_err_intsignal:1; - /** ch1_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_multiblktype_err_intsignal:1; - uint32_t reserved_15:1; - /** ch1_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_dec_err_intsignal:1; - /** ch1_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_wr2ro_err_intsignal:1; - /** ch1_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_rd2rwo_err_intsignal:1; - /** ch1_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_wronchen_err_intsignal:1; - /** ch1_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_shadowreg_wron_valid_err_intsignal:1; - /** ch1_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_wronhold_err_intsignal:1; - uint32_t reserved_22:3; - /** ch1_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1; - * NA - */ - uint32_t ch1_enable_slvif_wrparity_err_intsignal:1; - uint32_t reserved_26:1; - /** ch1_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1; - * NA - */ - uint32_t ch1_enable_ch_lock_cleared_intsignal:1; - /** ch1_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1; - * NA - */ - uint32_t ch1_enable_ch_src_suspended_intsignal:1; - /** ch1_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1; - * NA - */ - uint32_t ch1_enable_ch_suspended_intsignal:1; - /** ch1_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1; - * NA - */ - uint32_t ch1_enable_ch_disabled_intsignal:1; - /** ch1_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1; - * NA - */ - uint32_t ch1_enable_ch_aborted_intsignal:1; - }; - uint32_t val; -} dmac_ch1_intsignal_enable0_reg_t; - -/** Type of ch1_intsignal_enable1 register - * NA - */ -typedef union { - struct { - /** ch1_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch1_enable_ecc_prot_chmem_correrr_intsignal:1; - /** ch1_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch1_enable_ecc_prot_chmem_uncorrerr_intsignal:1; - /** ch1_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1; - * NA - */ - uint32_t ch1_enable_ecc_prot_uidmem_correrr_intsignal:1; - /** ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch1_intsignal_enable1_reg_t; - -/** Type of ch1_intclear0 register - * NA - */ -typedef union { - struct { - /** ch1_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch1_clear_block_tfr_done_intstat:1; - /** ch1_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch1_clear_dma_tfr_done_intstat:1; - uint32_t reserved_2:1; - /** ch1_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch1_clear_src_transcomp_intstat:1; - /** ch1_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch1_clear_dst_transcomp_intstat:1; - /** ch1_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch1_clear_src_dec_err_intstat:1; - /** ch1_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch1_clear_dst_dec_err_intstat:1; - /** ch1_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0; - * NA - */ - uint32_t ch1_clear_src_slv_err_intstat:1; - /** ch1_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0; - * NA - */ - uint32_t ch1_clear_dst_slv_err_intstat:1; - /** ch1_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0; - * NA - */ - uint32_t ch1_clear_lli_rd_dec_err_intstat:1; - /** ch1_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0; - * NA - */ - uint32_t ch1_clear_lli_wr_dec_err_intstat:1; - /** ch1_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0; - * NA - */ - uint32_t ch1_clear_lli_rd_slv_err_intstat:1; - /** ch1_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0; - * NA - */ - uint32_t ch1_clear_lli_wr_slv_err_intstat:1; - /** ch1_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0; - * NA - */ - uint32_t ch1_clear_shadowreg_or_lli_invalid_err_intstat:1; - /** ch1_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0; - * NA - */ - uint32_t ch1_clear_slvif_multiblktype_err_intstat:1; - uint32_t reserved_15:1; - /** ch1_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0; - * NA - */ - uint32_t ch1_clear_slvif_dec_err_intstat:1; - /** ch1_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0; - * NA - */ - uint32_t ch1_clear_slvif_wr2ro_err_intstat:1; - /** ch1_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0; - * NA - */ - uint32_t ch1_clear_slvif_rd2rwo_err_intstat:1; - /** ch1_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0; - * NA - */ - uint32_t ch1_clear_slvif_wronchen_err_intstat:1; - /** ch1_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0; - * NA - */ - uint32_t ch1_clear_slvif_shadowreg_wron_valid_err_intstat:1; - /** ch1_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0; - * NA - */ - uint32_t ch1_clear_slvif_wronhold_err_intstat:1; - uint32_t reserved_22:3; - /** ch1_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0; - * NA - */ - uint32_t ch1_clear_slvif_wrparity_err_intstat:1; - uint32_t reserved_26:1; - /** ch1_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0; - * NA - */ - uint32_t ch1_clear_ch_lock_cleared_intstat:1; - /** ch1_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0; - * NA - */ - uint32_t ch1_clear_ch_src_suspended_intstat:1; - /** ch1_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0; - * NA - */ - uint32_t ch1_clear_ch_suspended_intstat:1; - /** ch1_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch1_clear_ch_disabled_intstat:1; - /** ch1_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0; - * NA - */ - uint32_t ch1_clear_ch_aborted_intstat:1; - }; - uint32_t val; -} dmac_ch1_intclear0_reg_t; - -/** Type of ch1_intclear1 register - * NA - */ -typedef union { - struct { - /** ch1_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch1_clear_ecc_prot_chmem_correrr_intstat:1; - /** ch1_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch1_clear_ecc_prot_chmem_uncorrerr_intstat:1; - /** ch1_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch1_clear_ecc_prot_uidmem_correrr_intstat:1; - /** ch1_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch1_clear_ecc_prot_uidmem_uncorrerr_intstat:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch1_intclear1_reg_t; - -/** Type of ch2_intstatus_enable0 register - * NA - */ -typedef union { - struct { - /** ch2_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch2_enable_block_tfr_done_intstat:1; - /** ch2_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch2_enable_dma_tfr_done_intstat:1; - uint32_t reserved_2:1; - /** ch2_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch2_enable_src_transcomp_intstat:1; - /** ch2_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t ch2_enable_dst_transcomp_intstat:1; - /** ch2_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1; - * NA - */ - uint32_t ch2_enable_src_dec_err_intstat:1; - /** ch2_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t ch2_enable_dst_dec_err_intstat:1; - /** ch2_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t ch2_enable_src_slv_err_intstat:1; - /** ch2_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t ch2_enable_dst_slv_err_intstat:1; - /** ch2_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t ch2_enable_lli_rd_dec_err_intstat:1; - /** ch2_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t ch2_enable_lli_wr_dec_err_intstat:1; - /** ch2_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t ch2_enable_lli_rd_slv_err_intstat:1; - /** ch2_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1; - * NA - */ - uint32_t ch2_enable_lli_wr_slv_err_intstat:1; - /** ch2_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1; - * NA - */ - uint32_t ch2_enable_shadowreg_or_lli_invalid_err_intstat:1; - /** ch2_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_multiblktype_err_intstat:1; - uint32_t reserved_15:1; - /** ch2_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_dec_err_intstat:1; - /** ch2_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_wr2ro_err_intstat:1; - /** ch2_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_rd2rwo_err_intstat:1; - /** ch2_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_wronchen_err_intstat:1; - /** ch2_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_shadowreg_wron_valid_err_intstat:1; - /** ch2_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_wronhold_err_intstat:1; - uint32_t reserved_22:3; - /** ch2_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_wrparity_err_intstat:1; - uint32_t reserved_26:1; - /** ch2_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1; - * NA - */ - uint32_t ch2_enable_ch_lock_cleared_intstat:1; - /** ch2_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1; - * NA - */ - uint32_t ch2_enable_ch_src_suspended_intstat:1; - /** ch2_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1; - * NA - */ - uint32_t ch2_enable_ch_suspended_intstat:1; - /** ch2_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1; - * NA - */ - uint32_t ch2_enable_ch_disabled_intstat:1; - /** ch2_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1; - * NA - */ - uint32_t ch2_enable_ch_aborted_intstat:1; - }; - uint32_t val; -} dmac_ch2_intstatus_enable0_reg_t; - -/** Type of ch2_intstatus_enable1 register - * NA - */ -typedef union { - struct { - /** ch2_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch2_enable_ecc_prot_chmem_correrr_intstat:1; - /** ch2_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch2_enable_ecc_prot_chmem_uncorrerr_intstat:1; - /** ch2_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1; - * NA - */ - uint32_t ch2_enable_ecc_prot_uidmem_correrr_intstat:1; - /** ch2_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch2_enable_ecc_prot_uidmem_uncorrerr_intstat:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch2_intstatus_enable1_reg_t; - -/** Type of ch2_intstatus0 register - * NA - */ -typedef union { - struct { - /** ch2_block_tfr_done_intstat : RO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch2_block_tfr_done_intstat:1; - /** ch2_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch2_dma_tfr_done_intstat:1; - uint32_t reserved_2:1; - /** ch2_src_transcomp_intstat : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch2_src_transcomp_intstat:1; - /** ch2_dst_transcomp_intstat : RO; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch2_dst_transcomp_intstat:1; - /** ch2_src_dec_err_intstat : RO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch2_src_dec_err_intstat:1; - /** ch2_dst_dec_err_intstat : RO; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch2_dst_dec_err_intstat:1; - /** ch2_src_slv_err_intstat : RO; bitpos: [7]; default: 0; - * NA - */ - uint32_t ch2_src_slv_err_intstat:1; - /** ch2_dst_slv_err_intstat : RO; bitpos: [8]; default: 0; - * NA - */ - uint32_t ch2_dst_slv_err_intstat:1; - /** ch2_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0; - * NA - */ - uint32_t ch2_lli_rd_dec_err_intstat:1; - /** ch2_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0; - * NA - */ - uint32_t ch2_lli_wr_dec_err_intstat:1; - /** ch2_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0; - * NA - */ - uint32_t ch2_lli_rd_slv_err_intstat:1; - /** ch2_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0; - * NA - */ - uint32_t ch2_lli_wr_slv_err_intstat:1; - /** ch2_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0; - * NA - */ - uint32_t ch2_shadowreg_or_lli_invalid_err_intstat:1; - /** ch2_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0; - * NA - */ - uint32_t ch2_slvif_multiblktype_err_intstat:1; - uint32_t reserved_15:1; - /** ch2_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0; - * NA - */ - uint32_t ch2_slvif_dec_err_intstat:1; - /** ch2_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0; - * NA - */ - uint32_t ch2_slvif_wr2ro_err_intstat:1; - /** ch2_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0; - * NA - */ - uint32_t ch2_slvif_rd2rwo_err_intstat:1; - /** ch2_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0; - * NA - */ - uint32_t ch2_slvif_wronchen_err_intstat:1; - /** ch2_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0; - * NA - */ - uint32_t ch2_slvif_shadowreg_wron_valid_err_intstat:1; - /** ch2_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0; - * NA - */ - uint32_t ch2_slvif_wronhold_err_intstat:1; - uint32_t reserved_22:3; - /** ch2_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0; - * NA - */ - uint32_t ch2_slvif_wrparity_err_intstat:1; - uint32_t reserved_26:1; - /** ch2_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0; - * NA - */ - uint32_t ch2_ch_lock_cleared_intstat:1; - /** ch2_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0; - * NA - */ - uint32_t ch2_ch_src_suspended_intstat:1; - /** ch2_ch_suspended_intstat : RO; bitpos: [29]; default: 0; - * NA - */ - uint32_t ch2_ch_suspended_intstat:1; - /** ch2_ch_disabled_intstat : RO; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch2_ch_disabled_intstat:1; - /** ch2_ch_aborted_intstat : RO; bitpos: [31]; default: 0; - * NA - */ - uint32_t ch2_ch_aborted_intstat:1; - }; - uint32_t val; -} dmac_ch2_intstatus0_reg_t; - -/** Type of ch2_intstatus1 register - * NA - */ -typedef union { - struct { - /** ch2_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch2_ecc_prot_chmem_correrr_intstat:1; - /** ch2_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch2_ecc_prot_chmem_uncorrerr_intstat:1; - /** ch2_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch2_ecc_prot_uidmem_correrr_intstat:1; - /** ch2_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch2_ecc_prot_uidmem_uncorrerr_intstat:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch2_intstatus1_reg_t; - -/** Type of ch2_intsignal_enable0 register - * NA - */ -typedef union { - struct { - /** ch2_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch2_enable_block_tfr_done_intsignal:1; - /** ch2_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch2_enable_dma_tfr_done_intsignal:1; - uint32_t reserved_2:1; - /** ch2_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch2_enable_src_transcomp_intsignal:1; - /** ch2_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t ch2_enable_dst_transcomp_intsignal:1; - /** ch2_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1; - * NA - */ - uint32_t ch2_enable_src_dec_err_intsignal:1; - /** ch2_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t ch2_enable_dst_dec_err_intsignal:1; - /** ch2_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t ch2_enable_src_slv_err_intsignal:1; - /** ch2_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t ch2_enable_dst_slv_err_intsignal:1; - /** ch2_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t ch2_enable_lli_rd_dec_err_intsignal:1; - /** ch2_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t ch2_enable_lli_wr_dec_err_intsignal:1; - /** ch2_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t ch2_enable_lli_rd_slv_err_intsignal:1; - /** ch2_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1; - * NA - */ - uint32_t ch2_enable_lli_wr_slv_err_intsignal:1; - /** ch2_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1; - * NA - */ - uint32_t ch2_enable_shadowreg_or_lli_invalid_err_intsignal:1; - /** ch2_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_multiblktype_err_intsignal:1; - uint32_t reserved_15:1; - /** ch2_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_dec_err_intsignal:1; - /** ch2_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_wr2ro_err_intsignal:1; - /** ch2_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_rd2rwo_err_intsignal:1; - /** ch2_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_wronchen_err_intsignal:1; - /** ch2_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_shadowreg_wron_valid_err_intsignal:1; - /** ch2_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_wronhold_err_intsignal:1; - uint32_t reserved_22:3; - /** ch2_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1; - * NA - */ - uint32_t ch2_enable_slvif_wrparity_err_intsignal:1; - uint32_t reserved_26:1; - /** ch2_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1; - * NA - */ - uint32_t ch2_enable_ch_lock_cleared_intsignal:1; - /** ch2_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1; - * NA - */ - uint32_t ch2_enable_ch_src_suspended_intsignal:1; - /** ch2_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1; - * NA - */ - uint32_t ch2_enable_ch_suspended_intsignal:1; - /** ch2_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1; - * NA - */ - uint32_t ch2_enable_ch_disabled_intsignal:1; - /** ch2_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1; - * NA - */ - uint32_t ch2_enable_ch_aborted_intsignal:1; - }; - uint32_t val; -} dmac_ch2_intsignal_enable0_reg_t; - -/** Type of ch2_intsignal_enable1 register - * NA - */ -typedef union { - struct { - /** ch2_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch2_enable_ecc_prot_chmem_correrr_intsignal:1; - /** ch2_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch2_enable_ecc_prot_chmem_uncorrerr_intsignal:1; - /** ch2_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1; - * NA - */ - uint32_t ch2_enable_ecc_prot_uidmem_correrr_intsignal:1; - /** ch2_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch2_enable_ecc_prot_uidmem_uncorrerr_intsignal:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch2_intsignal_enable1_reg_t; - -/** Type of ch2_intclear0 register - * NA - */ -typedef union { - struct { - /** ch2_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch2_clear_block_tfr_done_intstat:1; - /** ch2_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch2_clear_dma_tfr_done_intstat:1; - uint32_t reserved_2:1; - /** ch2_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch2_clear_src_transcomp_intstat:1; - /** ch2_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch2_clear_dst_transcomp_intstat:1; - /** ch2_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch2_clear_src_dec_err_intstat:1; - /** ch2_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch2_clear_dst_dec_err_intstat:1; - /** ch2_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0; - * NA - */ - uint32_t ch2_clear_src_slv_err_intstat:1; - /** ch2_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0; - * NA - */ - uint32_t ch2_clear_dst_slv_err_intstat:1; - /** ch2_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0; - * NA - */ - uint32_t ch2_clear_lli_rd_dec_err_intstat:1; - /** ch2_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0; - * NA - */ - uint32_t ch2_clear_lli_wr_dec_err_intstat:1; - /** ch2_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0; - * NA - */ - uint32_t ch2_clear_lli_rd_slv_err_intstat:1; - /** ch2_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0; - * NA - */ - uint32_t ch2_clear_lli_wr_slv_err_intstat:1; - /** ch2_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0; - * NA - */ - uint32_t ch2_clear_shadowreg_or_lli_invalid_err_intstat:1; - /** ch2_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0; - * NA - */ - uint32_t ch2_clear_slvif_multiblktype_err_intstat:1; - uint32_t reserved_15:1; - /** ch2_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0; - * NA - */ - uint32_t ch2_clear_slvif_dec_err_intstat:1; - /** ch2_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0; - * NA - */ - uint32_t ch2_clear_slvif_wr2ro_err_intstat:1; - /** ch2_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0; - * NA - */ - uint32_t ch2_clear_slvif_rd2rwo_err_intstat:1; - /** ch2_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0; - * NA - */ - uint32_t ch2_clear_slvif_wronchen_err_intstat:1; - /** ch2_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0; - * NA - */ - uint32_t ch2_clear_slvif_shadowreg_wron_valid_err_intstat:1; - /** ch2_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0; - * NA - */ - uint32_t ch2_clear_slvif_wronhold_err_intstat:1; - uint32_t reserved_22:3; - /** ch2_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0; - * NA - */ - uint32_t ch2_clear_slvif_wrparity_err_intstat:1; - uint32_t reserved_26:1; - /** ch2_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0; - * NA - */ - uint32_t ch2_clear_ch_lock_cleared_intstat:1; - /** ch2_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0; - * NA - */ - uint32_t ch2_clear_ch_src_suspended_intstat:1; - /** ch2_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0; - * NA - */ - uint32_t ch2_clear_ch_suspended_intstat:1; - /** ch2_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch2_clear_ch_disabled_intstat:1; - /** ch2_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0; - * NA - */ - uint32_t ch2_clear_ch_aborted_intstat:1; - }; - uint32_t val; -} dmac_ch2_intclear0_reg_t; - -/** Type of ch2_intclear1 register - * NA - */ -typedef union { - struct { - /** ch2_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch2_clear_ecc_prot_chmem_correrr_intstat:1; - /** ch2_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch2_clear_ecc_prot_chmem_uncorrerr_intstat:1; - /** ch2_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch2_clear_ecc_prot_uidmem_correrr_intstat:1; - /** ch2_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch2_clear_ecc_prot_uidmem_uncorrerr_intstat:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch2_intclear1_reg_t; - -/** Type of ch3_intstatus_enable0 register - * NA - */ -typedef union { - struct { - /** ch3_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch3_enable_block_tfr_done_intstat:1; - /** ch3_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch3_enable_dma_tfr_done_intstat:1; - uint32_t reserved_2:1; - /** ch3_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch3_enable_src_transcomp_intstat:1; - /** ch3_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t ch3_enable_dst_transcomp_intstat:1; - /** ch3_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1; - * NA - */ - uint32_t ch3_enable_src_dec_err_intstat:1; - /** ch3_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t ch3_enable_dst_dec_err_intstat:1; - /** ch3_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t ch3_enable_src_slv_err_intstat:1; - /** ch3_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t ch3_enable_dst_slv_err_intstat:1; - /** ch3_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t ch3_enable_lli_rd_dec_err_intstat:1; - /** ch3_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t ch3_enable_lli_wr_dec_err_intstat:1; - /** ch3_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t ch3_enable_lli_rd_slv_err_intstat:1; - /** ch3_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1; - * NA - */ - uint32_t ch3_enable_lli_wr_slv_err_intstat:1; - /** ch3_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1; - * NA - */ - uint32_t ch3_enable_shadowreg_or_lli_invalid_err_intstat:1; - /** ch3_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_multiblktype_err_intstat:1; - uint32_t reserved_15:1; - /** ch3_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_dec_err_intstat:1; - /** ch3_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_wr2ro_err_intstat:1; - /** ch3_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_rd2rwo_err_intstat:1; - /** ch3_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_wronchen_err_intstat:1; - /** ch3_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_shadowreg_wron_valid_err_intstat:1; - /** ch3_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_wronhold_err_intstat:1; - uint32_t reserved_22:3; - /** ch3_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_wrparity_err_intstat:1; - uint32_t reserved_26:1; - /** ch3_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1; - * NA - */ - uint32_t ch3_enable_ch_lock_cleared_intstat:1; - /** ch3_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1; - * NA - */ - uint32_t ch3_enable_ch_src_suspended_intstat:1; - /** ch3_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1; - * NA - */ - uint32_t ch3_enable_ch_suspended_intstat:1; - /** ch3_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1; - * NA - */ - uint32_t ch3_enable_ch_disabled_intstat:1; - /** ch3_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1; - * NA - */ - uint32_t ch3_enable_ch_aborted_intstat:1; - }; - uint32_t val; -} dmac_ch3_intstatus_enable0_reg_t; - -/** Type of ch3_intstatus_enable1 register - * NA - */ -typedef union { - struct { - /** ch3_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch3_enable_ecc_prot_chmem_correrr_intstat:1; - /** ch3_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch3_enable_ecc_prot_chmem_uncorrerr_intstat:1; - /** ch3_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1; - * NA - */ - uint32_t ch3_enable_ecc_prot_uidmem_correrr_intstat:1; - /** ch3_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch3_enable_ecc_prot_uidmem_uncorrerr_intstat:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch3_intstatus_enable1_reg_t; - -/** Type of ch3_intstatus0 register - * NA - */ -typedef union { - struct { - /** ch3_block_tfr_done_intstat : RO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch3_block_tfr_done_intstat:1; - /** ch3_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch3_dma_tfr_done_intstat:1; - uint32_t reserved_2:1; - /** ch3_src_transcomp_intstat : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch3_src_transcomp_intstat:1; - /** ch3_dst_transcomp_intstat : RO; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch3_dst_transcomp_intstat:1; - /** ch3_src_dec_err_intstat : RO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch3_src_dec_err_intstat:1; - /** ch3_dst_dec_err_intstat : RO; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch3_dst_dec_err_intstat:1; - /** ch3_src_slv_err_intstat : RO; bitpos: [7]; default: 0; - * NA - */ - uint32_t ch3_src_slv_err_intstat:1; - /** ch3_dst_slv_err_intstat : RO; bitpos: [8]; default: 0; - * NA - */ - uint32_t ch3_dst_slv_err_intstat:1; - /** ch3_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0; - * NA - */ - uint32_t ch3_lli_rd_dec_err_intstat:1; - /** ch3_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0; - * NA - */ - uint32_t ch3_lli_wr_dec_err_intstat:1; - /** ch3_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0; - * NA - */ - uint32_t ch3_lli_rd_slv_err_intstat:1; - /** ch3_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0; - * NA - */ - uint32_t ch3_lli_wr_slv_err_intstat:1; - /** ch3_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0; - * NA - */ - uint32_t ch3_shadowreg_or_lli_invalid_err_intstat:1; - /** ch3_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0; - * NA - */ - uint32_t ch3_slvif_multiblktype_err_intstat:1; - uint32_t reserved_15:1; - /** ch3_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0; - * NA - */ - uint32_t ch3_slvif_dec_err_intstat:1; - /** ch3_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0; - * NA - */ - uint32_t ch3_slvif_wr2ro_err_intstat:1; - /** ch3_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0; - * NA - */ - uint32_t ch3_slvif_rd2rwo_err_intstat:1; - /** ch3_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0; - * NA - */ - uint32_t ch3_slvif_wronchen_err_intstat:1; - /** ch3_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0; - * NA - */ - uint32_t ch3_slvif_shadowreg_wron_valid_err_intstat:1; - /** ch3_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0; - * NA - */ - uint32_t ch3_slvif_wronhold_err_intstat:1; - uint32_t reserved_22:3; - /** ch3_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0; - * NA - */ - uint32_t ch3_slvif_wrparity_err_intstat:1; - uint32_t reserved_26:1; - /** ch3_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0; - * NA - */ - uint32_t ch3_ch_lock_cleared_intstat:1; - /** ch3_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0; - * NA - */ - uint32_t ch3_ch_src_suspended_intstat:1; - /** ch3_ch_suspended_intstat : RO; bitpos: [29]; default: 0; - * NA - */ - uint32_t ch3_ch_suspended_intstat:1; - /** ch3_ch_disabled_intstat : RO; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch3_ch_disabled_intstat:1; - /** ch3_ch_aborted_intstat : RO; bitpos: [31]; default: 0; - * NA - */ - uint32_t ch3_ch_aborted_intstat:1; - }; - uint32_t val; -} dmac_ch3_intstatus0_reg_t; - -/** Type of ch3_intstatus1 register - * NA - */ -typedef union { - struct { - /** ch3_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch3_ecc_prot_chmem_correrr_intstat:1; - /** ch3_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch3_ecc_prot_chmem_uncorrerr_intstat:1; - /** ch3_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch3_ecc_prot_uidmem_correrr_intstat:1; - /** ch3_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch3_ecc_prot_uidmem_uncorrerr_intstat:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch3_intstatus1_reg_t; - -/** Type of ch3_intsignal_enable0 register - * NA - */ -typedef union { - struct { - /** ch3_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch3_enable_block_tfr_done_intsignal:1; - /** ch3_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch3_enable_dma_tfr_done_intsignal:1; - uint32_t reserved_2:1; - /** ch3_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch3_enable_src_transcomp_intsignal:1; - /** ch3_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t ch3_enable_dst_transcomp_intsignal:1; - /** ch3_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1; - * NA - */ - uint32_t ch3_enable_src_dec_err_intsignal:1; - /** ch3_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t ch3_enable_dst_dec_err_intsignal:1; - /** ch3_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t ch3_enable_src_slv_err_intsignal:1; - /** ch3_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t ch3_enable_dst_slv_err_intsignal:1; - /** ch3_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t ch3_enable_lli_rd_dec_err_intsignal:1; - /** ch3_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t ch3_enable_lli_wr_dec_err_intsignal:1; - /** ch3_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t ch3_enable_lli_rd_slv_err_intsignal:1; - /** ch3_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1; - * NA - */ - uint32_t ch3_enable_lli_wr_slv_err_intsignal:1; - /** ch3_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1; - * NA - */ - uint32_t ch3_enable_shadowreg_or_lli_invalid_err_intsignal:1; - /** ch3_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_multiblktype_err_intsignal:1; - uint32_t reserved_15:1; - /** ch3_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_dec_err_intsignal:1; - /** ch3_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_wr2ro_err_intsignal:1; - /** ch3_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_rd2rwo_err_intsignal:1; - /** ch3_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_wronchen_err_intsignal:1; - /** ch3_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_shadowreg_wron_valid_err_intsignal:1; - /** ch3_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_wronhold_err_intsignal:1; - uint32_t reserved_22:3; - /** ch3_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1; - * NA - */ - uint32_t ch3_enable_slvif_wrparity_err_intsignal:1; - uint32_t reserved_26:1; - /** ch3_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1; - * NA - */ - uint32_t ch3_enable_ch_lock_cleared_intsignal:1; - /** ch3_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1; - * NA - */ - uint32_t ch3_enable_ch_src_suspended_intsignal:1; - /** ch3_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1; - * NA - */ - uint32_t ch3_enable_ch_suspended_intsignal:1; - /** ch3_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1; - * NA - */ - uint32_t ch3_enable_ch_disabled_intsignal:1; - /** ch3_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1; - * NA - */ - uint32_t ch3_enable_ch_aborted_intsignal:1; - }; - uint32_t val; -} dmac_ch3_intsignal_enable0_reg_t; - -/** Type of ch3_intsignal_enable1 register - * NA - */ -typedef union { - struct { - /** ch3_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch3_enable_ecc_prot_chmem_correrr_intsignal:1; - /** ch3_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch3_enable_ecc_prot_chmem_uncorrerr_intsignal:1; - /** ch3_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1; - * NA - */ - uint32_t ch3_enable_ecc_prot_uidmem_correrr_intsignal:1; - /** ch3_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch3_enable_ecc_prot_uidmem_uncorrerr_intsignal:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch3_intsignal_enable1_reg_t; - -/** Type of ch3_intclear0 register - * NA - */ -typedef union { - struct { - /** ch3_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch3_clear_block_tfr_done_intstat:1; - /** ch3_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch3_clear_dma_tfr_done_intstat:1; - uint32_t reserved_2:1; - /** ch3_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch3_clear_src_transcomp_intstat:1; - /** ch3_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch3_clear_dst_transcomp_intstat:1; - /** ch3_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch3_clear_src_dec_err_intstat:1; - /** ch3_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch3_clear_dst_dec_err_intstat:1; - /** ch3_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0; - * NA - */ - uint32_t ch3_clear_src_slv_err_intstat:1; - /** ch3_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0; - * NA - */ - uint32_t ch3_clear_dst_slv_err_intstat:1; - /** ch3_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0; - * NA - */ - uint32_t ch3_clear_lli_rd_dec_err_intstat:1; - /** ch3_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0; - * NA - */ - uint32_t ch3_clear_lli_wr_dec_err_intstat:1; - /** ch3_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0; - * NA - */ - uint32_t ch3_clear_lli_rd_slv_err_intstat:1; - /** ch3_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0; - * NA - */ - uint32_t ch3_clear_lli_wr_slv_err_intstat:1; - /** ch3_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0; - * NA - */ - uint32_t ch3_clear_shadowreg_or_lli_invalid_err_intstat:1; - /** ch3_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0; - * NA - */ - uint32_t ch3_clear_slvif_multiblktype_err_intstat:1; - uint32_t reserved_15:1; - /** ch3_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0; - * NA - */ - uint32_t ch3_clear_slvif_dec_err_intstat:1; - /** ch3_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0; - * NA - */ - uint32_t ch3_clear_slvif_wr2ro_err_intstat:1; - /** ch3_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0; - * NA - */ - uint32_t ch3_clear_slvif_rd2rwo_err_intstat:1; - /** ch3_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0; - * NA - */ - uint32_t ch3_clear_slvif_wronchen_err_intstat:1; - /** ch3_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0; - * NA - */ - uint32_t ch3_clear_slvif_shadowreg_wron_valid_err_intstat:1; - /** ch3_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0; - * NA - */ - uint32_t ch3_clear_slvif_wronhold_err_intstat:1; - uint32_t reserved_22:3; - /** ch3_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0; - * NA - */ - uint32_t ch3_clear_slvif_wrparity_err_intstat:1; - uint32_t reserved_26:1; - /** ch3_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0; - * NA - */ - uint32_t ch3_clear_ch_lock_cleared_intstat:1; - /** ch3_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0; - * NA - */ - uint32_t ch3_clear_ch_src_suspended_intstat:1; - /** ch3_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0; - * NA - */ - uint32_t ch3_clear_ch_suspended_intstat:1; - /** ch3_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch3_clear_ch_disabled_intstat:1; - /** ch3_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0; - * NA - */ - uint32_t ch3_clear_ch_aborted_intstat:1; - }; - uint32_t val; -} dmac_ch3_intclear0_reg_t; - -/** Type of ch3_intclear1 register - * NA - */ -typedef union { - struct { - /** ch3_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch3_clear_ecc_prot_chmem_correrr_intstat:1; - /** ch3_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch3_clear_ecc_prot_chmem_uncorrerr_intstat:1; - /** ch3_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch3_clear_ecc_prot_uidmem_correrr_intstat:1; - /** ch3_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch3_clear_ecc_prot_uidmem_uncorrerr_intstat:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch3_intclear1_reg_t; - -/** Type of ch4_intstatus_enable0 register - * NA - */ -typedef union { - struct { - /** ch4_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch4_enable_block_tfr_done_intstat:1; - /** ch4_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch4_enable_dma_tfr_done_intstat:1; - uint32_t reserved_2:1; - /** ch4_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch4_enable_src_transcomp_intstat:1; - /** ch4_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t ch4_enable_dst_transcomp_intstat:1; - /** ch4_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1; - * NA - */ - uint32_t ch4_enable_src_dec_err_intstat:1; - /** ch4_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t ch4_enable_dst_dec_err_intstat:1; - /** ch4_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t ch4_enable_src_slv_err_intstat:1; - /** ch4_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t ch4_enable_dst_slv_err_intstat:1; - /** ch4_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t ch4_enable_lli_rd_dec_err_intstat:1; - /** ch4_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t ch4_enable_lli_wr_dec_err_intstat:1; - /** ch4_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t ch4_enable_lli_rd_slv_err_intstat:1; - /** ch4_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1; - * NA - */ - uint32_t ch4_enable_lli_wr_slv_err_intstat:1; - /** ch4_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1; - * NA - */ - uint32_t ch4_enable_shadowreg_or_lli_invalid_err_intstat:1; - /** ch4_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_multiblktype_err_intstat:1; - uint32_t reserved_15:1; - /** ch4_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_dec_err_intstat:1; - /** ch4_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_wr2ro_err_intstat:1; - /** ch4_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_rd2rwo_err_intstat:1; - /** ch4_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_wronchen_err_intstat:1; - /** ch4_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_shadowreg_wron_valid_err_intstat:1; - /** ch4_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_wronhold_err_intstat:1; - uint32_t reserved_22:3; - /** ch4_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_wrparity_err_intstat:1; - uint32_t reserved_26:1; - /** ch4_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1; - * NA - */ - uint32_t ch4_enable_ch_lock_cleared_intstat:1; - /** ch4_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1; - * NA - */ - uint32_t ch4_enable_ch_src_suspended_intstat:1; - /** ch4_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1; - * NA - */ - uint32_t ch4_enable_ch_suspended_intstat:1; - /** ch4_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1; - * NA - */ - uint32_t ch4_enable_ch_disabled_intstat:1; - /** ch4_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1; - * NA - */ - uint32_t ch4_enable_ch_aborted_intstat:1; - }; - uint32_t val; -} dmac_ch4_intstatus_enable0_reg_t; - -/** Type of ch4_intstatus_enable1 register - * NA - */ -typedef union { - struct { - /** ch4_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch4_enable_ecc_prot_chmem_correrr_intstat:1; - /** ch4_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch4_enable_ecc_prot_chmem_uncorrerr_intstat:1; - /** ch4_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1; - * NA - */ - uint32_t ch4_enable_ecc_prot_uidmem_correrr_intstat:1; - /** ch4_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch4_enable_ecc_prot_uidmem_uncorrerr_intstat:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch4_intstatus_enable1_reg_t; - -/** Type of ch4_intstatus0 register - * NA - */ -typedef union { - struct { - /** ch4_block_tfr_done_intstat : RO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch4_block_tfr_done_intstat:1; - /** ch4_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch4_dma_tfr_done_intstat:1; - uint32_t reserved_2:1; - /** ch4_src_transcomp_intstat : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch4_src_transcomp_intstat:1; - /** ch4_dst_transcomp_intstat : RO; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch4_dst_transcomp_intstat:1; - /** ch4_src_dec_err_intstat : RO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch4_src_dec_err_intstat:1; - /** ch4_dst_dec_err_intstat : RO; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch4_dst_dec_err_intstat:1; - /** ch4_src_slv_err_intstat : RO; bitpos: [7]; default: 0; - * NA - */ - uint32_t ch4_src_slv_err_intstat:1; - /** ch4_dst_slv_err_intstat : RO; bitpos: [8]; default: 0; - * NA - */ - uint32_t ch4_dst_slv_err_intstat:1; - /** ch4_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0; - * NA - */ - uint32_t ch4_lli_rd_dec_err_intstat:1; - /** ch4_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0; - * NA - */ - uint32_t ch4_lli_wr_dec_err_intstat:1; - /** ch4_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0; - * NA - */ - uint32_t ch4_lli_rd_slv_err_intstat:1; - /** ch4_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0; - * NA - */ - uint32_t ch4_lli_wr_slv_err_intstat:1; - /** ch4_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0; - * NA - */ - uint32_t ch4_shadowreg_or_lli_invalid_err_intstat:1; - /** ch4_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0; - * NA - */ - uint32_t ch4_slvif_multiblktype_err_intstat:1; - uint32_t reserved_15:1; - /** ch4_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0; - * NA - */ - uint32_t ch4_slvif_dec_err_intstat:1; - /** ch4_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0; - * NA - */ - uint32_t ch4_slvif_wr2ro_err_intstat:1; - /** ch4_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0; - * NA - */ - uint32_t ch4_slvif_rd2rwo_err_intstat:1; - /** ch4_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0; - * NA - */ - uint32_t ch4_slvif_wronchen_err_intstat:1; - /** ch4_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0; - * NA - */ - uint32_t ch4_slvif_shadowreg_wron_valid_err_intstat:1; - /** ch4_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0; - * NA - */ - uint32_t ch4_slvif_wronhold_err_intstat:1; - uint32_t reserved_22:3; - /** ch4_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0; - * NA - */ - uint32_t ch4_slvif_wrparity_err_intstat:1; - uint32_t reserved_26:1; - /** ch4_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0; - * NA - */ - uint32_t ch4_ch_lock_cleared_intstat:1; - /** ch4_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0; - * NA - */ - uint32_t ch4_ch_src_suspended_intstat:1; - /** ch4_ch_suspended_intstat : RO; bitpos: [29]; default: 0; - * NA - */ - uint32_t ch4_ch_suspended_intstat:1; - /** ch4_ch_disabled_intstat : RO; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch4_ch_disabled_intstat:1; - /** ch4_ch_aborted_intstat : RO; bitpos: [31]; default: 0; - * NA - */ - uint32_t ch4_ch_aborted_intstat:1; - }; - uint32_t val; -} dmac_ch4_intstatus0_reg_t; - -/** Type of ch4_intstatus1 register - * NA - */ -typedef union { - struct { - /** ch4_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch4_ecc_prot_chmem_correrr_intstat:1; - /** ch4_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch4_ecc_prot_chmem_uncorrerr_intstat:1; - /** ch4_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch4_ecc_prot_uidmem_correrr_intstat:1; - /** ch4_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch4_ecc_prot_uidmem_uncorrerr_intstat:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch4_intstatus1_reg_t; - -/** Type of ch4_intsignal_enable0 register - * NA - */ -typedef union { - struct { - /** ch4_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch4_enable_block_tfr_done_intsignal:1; - /** ch4_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch4_enable_dma_tfr_done_intsignal:1; - uint32_t reserved_2:1; - /** ch4_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch4_enable_src_transcomp_intsignal:1; - /** ch4_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1; - * NA - */ - uint32_t ch4_enable_dst_transcomp_intsignal:1; - /** ch4_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1; - * NA - */ - uint32_t ch4_enable_src_dec_err_intsignal:1; - /** ch4_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1; - * NA - */ - uint32_t ch4_enable_dst_dec_err_intsignal:1; - /** ch4_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1; - * NA - */ - uint32_t ch4_enable_src_slv_err_intsignal:1; - /** ch4_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1; - * NA - */ - uint32_t ch4_enable_dst_slv_err_intsignal:1; - /** ch4_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1; - * NA - */ - uint32_t ch4_enable_lli_rd_dec_err_intsignal:1; - /** ch4_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1; - * NA - */ - uint32_t ch4_enable_lli_wr_dec_err_intsignal:1; - /** ch4_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1; - * NA - */ - uint32_t ch4_enable_lli_rd_slv_err_intsignal:1; - /** ch4_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1; - * NA - */ - uint32_t ch4_enable_lli_wr_slv_err_intsignal:1; - /** ch4_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1; - * NA - */ - uint32_t ch4_enable_shadowreg_or_lli_invalid_err_intsignal:1; - /** ch4_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_multiblktype_err_intsignal:1; - uint32_t reserved_15:1; - /** ch4_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_dec_err_intsignal:1; - /** ch4_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_wr2ro_err_intsignal:1; - /** ch4_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_rd2rwo_err_intsignal:1; - /** ch4_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_wronchen_err_intsignal:1; - /** ch4_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_shadowreg_wron_valid_err_intsignal:1; - /** ch4_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_wronhold_err_intsignal:1; - uint32_t reserved_22:3; - /** ch4_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1; - * NA - */ - uint32_t ch4_enable_slvif_wrparity_err_intsignal:1; - uint32_t reserved_26:1; - /** ch4_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1; - * NA - */ - uint32_t ch4_enable_ch_lock_cleared_intsignal:1; - /** ch4_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1; - * NA - */ - uint32_t ch4_enable_ch_src_suspended_intsignal:1; - /** ch4_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1; - * NA - */ - uint32_t ch4_enable_ch_suspended_intsignal:1; - /** ch4_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1; - * NA - */ - uint32_t ch4_enable_ch_disabled_intsignal:1; - /** ch4_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1; - * NA - */ - uint32_t ch4_enable_ch_aborted_intsignal:1; - }; - uint32_t val; -} dmac_ch4_intsignal_enable0_reg_t; - -/** Type of ch4_intsignal_enable1 register - * NA - */ -typedef union { - struct { - /** ch4_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1; - * NA - */ - uint32_t ch4_enable_ecc_prot_chmem_correrr_intsignal:1; - /** ch4_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1; - * NA - */ - uint32_t ch4_enable_ecc_prot_chmem_uncorrerr_intsignal:1; - /** ch4_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1; - * NA - */ - uint32_t ch4_enable_ecc_prot_uidmem_correrr_intsignal:1; - /** ch4_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1; - * NA - */ - uint32_t ch4_enable_ecc_prot_uidmem_uncorrerr_intsignal:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch4_intsignal_enable1_reg_t; - -/** Type of ch4_intclear0 register - * NA - */ -typedef union { - struct { - /** ch4_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch4_clear_block_tfr_done_intstat:1; - /** ch4_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch4_clear_dma_tfr_done_intstat:1; - uint32_t reserved_2:1; - /** ch4_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch4_clear_src_transcomp_intstat:1; - /** ch4_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0; - * NA - */ - uint32_t ch4_clear_dst_transcomp_intstat:1; - /** ch4_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ch4_clear_src_dec_err_intstat:1; - /** ch4_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0; - * NA - */ - uint32_t ch4_clear_dst_dec_err_intstat:1; - /** ch4_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0; - * NA - */ - uint32_t ch4_clear_src_slv_err_intstat:1; - /** ch4_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0; - * NA - */ - uint32_t ch4_clear_dst_slv_err_intstat:1; - /** ch4_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0; - * NA - */ - uint32_t ch4_clear_lli_rd_dec_err_intstat:1; - /** ch4_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0; - * NA - */ - uint32_t ch4_clear_lli_wr_dec_err_intstat:1; - /** ch4_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0; - * NA - */ - uint32_t ch4_clear_lli_rd_slv_err_intstat:1; - /** ch4_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0; - * NA - */ - uint32_t ch4_clear_lli_wr_slv_err_intstat:1; - /** ch4_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0; - * NA - */ - uint32_t ch4_clear_shadowreg_or_lli_invalid_err_intstat:1; - /** ch4_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0; - * NA - */ - uint32_t ch4_clear_slvif_multiblktype_err_intstat:1; - uint32_t reserved_15:1; - /** ch4_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0; - * NA - */ - uint32_t ch4_clear_slvif_dec_err_intstat:1; - /** ch4_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0; - * NA - */ - uint32_t ch4_clear_slvif_wr2ro_err_intstat:1; - /** ch4_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0; - * NA - */ - uint32_t ch4_clear_slvif_rd2rwo_err_intstat:1; - /** ch4_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0; - * NA - */ - uint32_t ch4_clear_slvif_wronchen_err_intstat:1; - /** ch4_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0; - * NA - */ - uint32_t ch4_clear_slvif_shadowreg_wron_valid_err_intstat:1; - /** ch4_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0; - * NA - */ - uint32_t ch4_clear_slvif_wronhold_err_intstat:1; - uint32_t reserved_22:3; - /** ch4_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0; - * NA - */ - uint32_t ch4_clear_slvif_wrparity_err_intstat:1; - uint32_t reserved_26:1; - /** ch4_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0; - * NA - */ - uint32_t ch4_clear_ch_lock_cleared_intstat:1; - /** ch4_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0; - * NA - */ - uint32_t ch4_clear_ch_src_suspended_intstat:1; - /** ch4_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0; - * NA - */ - uint32_t ch4_clear_ch_suspended_intstat:1; - /** ch4_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0; - * NA - */ - uint32_t ch4_clear_ch_disabled_intstat:1; - /** ch4_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0; - * NA - */ - uint32_t ch4_clear_ch_aborted_intstat:1; - }; - uint32_t val; -} dmac_ch4_intclear0_reg_t; - -/** Type of ch4_intclear1 register - * NA - */ -typedef union { - struct { - /** ch4_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ch4_clear_ecc_prot_chmem_correrr_intstat:1; - /** ch4_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ch4_clear_ecc_prot_chmem_uncorrerr_intstat:1; - /** ch4_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0; - * NA - */ - uint32_t ch4_clear_ecc_prot_uidmem_correrr_intstat:1; - /** ch4_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ch4_clear_ecc_prot_uidmem_uncorrerr_intstat:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dmac_ch4_intclear1_reg_t; - - -/** Group: Status Registers */ -/** Type of ch1_status0 register - * NA - */ -typedef union { - struct { - /** ch1_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0; - * NA - */ - uint32_t ch1_cmpltd_blk_tfr_size:22; - uint32_t reserved_22:10; - }; - uint32_t val; -} dmac_ch1_status0_reg_t; - -/** Type of ch1_status1 register - * NA - */ -typedef union { - struct { - /** ch1_data_left_in_fifo : RO; bitpos: [14:0]; default: 0; - * NA - */ - uint32_t ch1_data_left_in_fifo:15; - uint32_t reserved_15:17; - }; - uint32_t val; -} dmac_ch1_status1_reg_t; - -/** Type of ch1_sstat0 register - * NA - */ -typedef union { - struct { - /** ch1_sstat : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch1_sstat:32; - }; - uint32_t val; -} dmac_ch1_sstat0_reg_t; - -/** Type of ch1_dstat0 register - * NA - */ -typedef union { - struct { - /** ch1_dstat : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch1_dstat:32; - }; - uint32_t val; -} dmac_ch1_dstat0_reg_t; - -/** Type of ch1_sstatar0 register - * NA - */ -typedef union { - struct { - /** ch1_sstatar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch1_sstatar0:32; - }; - uint32_t val; -} dmac_ch1_sstatar0_reg_t; - -/** Type of ch1_sstatar1 register - * NA - */ -typedef union { - struct { - /** ch1_sstatar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch1_sstatar1:32; - }; - uint32_t val; -} dmac_ch1_sstatar1_reg_t; - -/** Type of ch1_dstatar0 register - * NA - */ -typedef union { - struct { - /** ch1_dstatar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch1_dstatar0:32; - }; - uint32_t val; -} dmac_ch1_dstatar0_reg_t; - -/** Type of ch1_dstatar1 register - * NA - */ -typedef union { - struct { - /** ch1_dstatar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch1_dstatar1:32; - }; - uint32_t val; -} dmac_ch1_dstatar1_reg_t; - -/** Type of ch2_status0 register - * NA - */ -typedef union { - struct { - /** ch2_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0; - * NA - */ - uint32_t ch2_cmpltd_blk_tfr_size:22; - uint32_t reserved_22:10; - }; - uint32_t val; -} dmac_ch2_status0_reg_t; - -/** Type of ch2_status1 register - * NA - */ -typedef union { - struct { - /** ch2_data_left_in_fifo : RO; bitpos: [14:0]; default: 0; - * NA - */ - uint32_t ch2_data_left_in_fifo:15; - uint32_t reserved_15:17; - }; - uint32_t val; -} dmac_ch2_status1_reg_t; - -/** Type of ch2_sstat0 register - * NA - */ -typedef union { - struct { - /** ch2_sstat : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch2_sstat:32; - }; - uint32_t val; -} dmac_ch2_sstat0_reg_t; - -/** Type of ch2_dstat0 register - * NA - */ -typedef union { - struct { - /** ch2_dstat : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch2_dstat:32; - }; - uint32_t val; -} dmac_ch2_dstat0_reg_t; - -/** Type of ch2_sstatar0 register - * NA - */ -typedef union { - struct { - /** ch2_sstatar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch2_sstatar0:32; - }; - uint32_t val; -} dmac_ch2_sstatar0_reg_t; - -/** Type of ch2_sstatar1 register - * NA - */ -typedef union { - struct { - /** ch2_sstatar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch2_sstatar1:32; - }; - uint32_t val; -} dmac_ch2_sstatar1_reg_t; - -/** Type of ch2_dstatar0 register - * NA - */ -typedef union { - struct { - /** ch2_dstatar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch2_dstatar0:32; - }; - uint32_t val; -} dmac_ch2_dstatar0_reg_t; - -/** Type of ch2_dstatar1 register - * NA - */ -typedef union { - struct { - /** ch2_dstatar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch2_dstatar1:32; - }; - uint32_t val; -} dmac_ch2_dstatar1_reg_t; - -/** Type of ch3_status0 register - * NA - */ -typedef union { - struct { - /** ch3_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0; - * NA - */ - uint32_t ch3_cmpltd_blk_tfr_size:22; - uint32_t reserved_22:10; - }; - uint32_t val; -} dmac_ch3_status0_reg_t; - -/** Type of ch3_status1 register - * NA - */ -typedef union { - struct { - /** ch3_data_left_in_fifo : RO; bitpos: [14:0]; default: 0; - * NA - */ - uint32_t ch3_data_left_in_fifo:15; - uint32_t reserved_15:17; - }; - uint32_t val; -} dmac_ch3_status1_reg_t; - -/** Type of ch3_sstat0 register - * NA - */ -typedef union { - struct { - /** ch3_sstat : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch3_sstat:32; - }; - uint32_t val; -} dmac_ch3_sstat0_reg_t; - -/** Type of ch3_dstat0 register - * NA - */ -typedef union { - struct { - /** ch3_dstat : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch3_dstat:32; - }; - uint32_t val; -} dmac_ch3_dstat0_reg_t; - -/** Type of ch3_sstatar0 register - * NA - */ -typedef union { - struct { - /** ch3_sstatar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch3_sstatar0:32; - }; - uint32_t val; -} dmac_ch3_sstatar0_reg_t; - -/** Type of ch3_sstatar1 register - * NA - */ -typedef union { - struct { - /** ch3_sstatar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch3_sstatar1:32; - }; - uint32_t val; -} dmac_ch3_sstatar1_reg_t; - -/** Type of ch3_dstatar0 register - * NA - */ -typedef union { - struct { - /** ch3_dstatar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch3_dstatar0:32; - }; - uint32_t val; -} dmac_ch3_dstatar0_reg_t; - -/** Type of ch3_dstatar1 register - * NA - */ -typedef union { - struct { - /** ch3_dstatar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch3_dstatar1:32; - }; - uint32_t val; -} dmac_ch3_dstatar1_reg_t; - -/** Type of ch4_status0 register - * NA - */ -typedef union { - struct { - /** ch4_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0; - * NA - */ - uint32_t ch4_cmpltd_blk_tfr_size:22; - uint32_t reserved_22:10; - }; - uint32_t val; -} dmac_ch4_status0_reg_t; - -/** Type of ch4_status1 register - * NA - */ -typedef union { - struct { - /** ch4_data_left_in_fifo : RO; bitpos: [14:0]; default: 0; - * NA - */ - uint32_t ch4_data_left_in_fifo:15; - uint32_t reserved_15:17; - }; - uint32_t val; -} dmac_ch4_status1_reg_t; - -/** Type of ch4_sstat0 register - * NA - */ -typedef union { - struct { - /** ch4_sstat : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch4_sstat:32; - }; - uint32_t val; -} dmac_ch4_sstat0_reg_t; - -/** Type of ch4_dstat0 register - * NA - */ -typedef union { - struct { - /** ch4_dstat : RO; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch4_dstat:32; - }; - uint32_t val; -} dmac_ch4_dstat0_reg_t; - -/** Type of ch4_sstatar0 register - * NA - */ -typedef union { - struct { - /** ch4_sstatar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch4_sstatar0:32; - }; - uint32_t val; -} dmac_ch4_sstatar0_reg_t; - -/** Type of ch4_sstatar1 register - * NA - */ -typedef union { - struct { - /** ch4_sstatar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch4_sstatar1:32; - }; - uint32_t val; -} dmac_ch4_sstatar1_reg_t; - -/** Type of ch4_dstatar0 register - * NA - */ -typedef union { - struct { - /** ch4_dstatar0 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch4_dstatar0:32; - }; - uint32_t val; -} dmac_ch4_dstatar0_reg_t; - -/** Type of ch4_dstatar1 register - * NA - */ -typedef union { - struct { - /** ch4_dstatar1 : R/W; bitpos: [31:0]; default: 0; - * NA - */ - uint32_t ch4_dstatar1:32; - }; - uint32_t val; -} dmac_ch4_dstatar1_reg_t; - - -typedef struct { - volatile dmac_id0_reg_t id0; - uint32_t reserved_004; - volatile dmac_compver0_reg_t compver0; - uint32_t reserved_00c; - volatile dmac_cfg0_reg_t cfg0; - uint32_t reserved_014; - volatile dmac_chen0_reg_t chen0; - volatile dmac_chen1_reg_t chen1; - uint32_t reserved_020[4]; - volatile dmac_intstatus0_reg_t intstatus0; - uint32_t reserved_034; - volatile dmac_commonreg_intclear0_reg_t commonreg_intclear0; - uint32_t reserved_03c; - volatile dmac_commonreg_intstatus_enable0_reg_t commonreg_intstatus_enable0; - uint32_t reserved_044; - volatile dmac_commonreg_intsignal_enable0_reg_t commonreg_intsignal_enable0; - uint32_t reserved_04c; - volatile dmac_commonreg_intstatus0_reg_t commonreg_intstatus0; - uint32_t reserved_054; - volatile dmac_reset0_reg_t reset0; - uint32_t reserved_05c; - volatile dmac_lowpower_cfg0_reg_t lowpower_cfg0; - volatile dmac_lowpower_cfg1_reg_t lowpower_cfg1; - uint32_t reserved_068[38]; - volatile dmac_ch1_sar0_reg_t ch1_sar0; - volatile dmac_ch1_sar1_reg_t ch1_sar1; - volatile dmac_ch1_dar0_reg_t ch1_dar0; - volatile dmac_ch1_dar1_reg_t ch1_dar1; - volatile dmac_ch1_block_ts0_reg_t ch1_block_ts0; - uint32_t reserved_114; - volatile dmac_ch1_ctl0_reg_t ch1_ctl0; - volatile dmac_ch1_ctl1_reg_t ch1_ctl1; - volatile dmac_ch1_cfg0_reg_t ch1_cfg0; - volatile dmac_ch1_cfg1_reg_t ch1_cfg1; - volatile dmac_ch1_llp0_reg_t ch1_llp0; - volatile dmac_ch1_llp1_reg_t ch1_llp1; - volatile dmac_ch1_status0_reg_t ch1_status0; - volatile dmac_ch1_status1_reg_t ch1_status1; - volatile dmac_ch1_swhssrc0_reg_t ch1_swhssrc0; - uint32_t reserved_13c; - volatile dmac_ch1_swhsdst0_reg_t ch1_swhsdst0; - uint32_t reserved_144; - volatile dmac_ch1_blk_tfr_resumereq0_reg_t ch1_blk_tfr_resumereq0; - uint32_t reserved_14c; - volatile dmac_ch1_axi_id0_reg_t ch1_axi_id0; - uint32_t reserved_154; - volatile dmac_ch1_axi_qos0_reg_t ch1_axi_qos0; - uint32_t reserved_15c; - volatile dmac_ch1_sstat0_reg_t ch1_sstat0; - uint32_t reserved_164; - volatile dmac_ch1_dstat0_reg_t ch1_dstat0; - uint32_t reserved_16c; - volatile dmac_ch1_sstatar0_reg_t ch1_sstatar0; - volatile dmac_ch1_sstatar1_reg_t ch1_sstatar1; - volatile dmac_ch1_dstatar0_reg_t ch1_dstatar0; - volatile dmac_ch1_dstatar1_reg_t ch1_dstatar1; - volatile dmac_ch1_intstatus_enable0_reg_t ch1_intstatus_enable0; - volatile dmac_ch1_intstatus_enable1_reg_t ch1_intstatus_enable1; - volatile dmac_ch1_intstatus0_reg_t ch1_intstatus0; - volatile dmac_ch1_intstatus1_reg_t ch1_intstatus1; - volatile dmac_ch1_intsignal_enable0_reg_t ch1_intsignal_enable0; - volatile dmac_ch1_intsignal_enable1_reg_t ch1_intsignal_enable1; - volatile dmac_ch1_intclear0_reg_t ch1_intclear0; - volatile dmac_ch1_intclear1_reg_t ch1_intclear1; - uint32_t reserved_1a0[24]; - volatile dmac_ch2_sar0_reg_t ch2_sar0; - volatile dmac_ch2_sar1_reg_t ch2_sar1; - volatile dmac_ch2_dar0_reg_t ch2_dar0; - volatile dmac_ch2_dar1_reg_t ch2_dar1; - volatile dmac_ch2_block_ts0_reg_t ch2_block_ts0; - uint32_t reserved_214; - volatile dmac_ch2_ctl0_reg_t ch2_ctl0; - volatile dmac_ch2_ctl1_reg_t ch2_ctl1; - volatile dmac_ch2_cfg0_reg_t ch2_cfg0; - volatile dmac_ch2_cfg1_reg_t ch2_cfg1; - volatile dmac_ch2_llp0_reg_t ch2_llp0; - volatile dmac_ch2_llp1_reg_t ch2_llp1; - volatile dmac_ch2_status0_reg_t ch2_status0; - volatile dmac_ch2_status1_reg_t ch2_status1; - volatile dmac_ch2_swhssrc0_reg_t ch2_swhssrc0; - uint32_t reserved_23c; - volatile dmac_ch2_swhsdst0_reg_t ch2_swhsdst0; - uint32_t reserved_244; - volatile dmac_ch2_blk_tfr_resumereq0_reg_t ch2_blk_tfr_resumereq0; - uint32_t reserved_24c; - volatile dmac_ch2_axi_id0_reg_t ch2_axi_id0; - uint32_t reserved_254; - volatile dmac_ch2_axi_qos0_reg_t ch2_axi_qos0; - uint32_t reserved_25c; - volatile dmac_ch2_sstat0_reg_t ch2_sstat0; - uint32_t reserved_264; - volatile dmac_ch2_dstat0_reg_t ch2_dstat0; - uint32_t reserved_26c; - volatile dmac_ch2_sstatar0_reg_t ch2_sstatar0; - volatile dmac_ch2_sstatar1_reg_t ch2_sstatar1; - volatile dmac_ch2_dstatar0_reg_t ch2_dstatar0; - volatile dmac_ch2_dstatar1_reg_t ch2_dstatar1; - volatile dmac_ch2_intstatus_enable0_reg_t ch2_intstatus_enable0; - volatile dmac_ch2_intstatus_enable1_reg_t ch2_intstatus_enable1; - volatile dmac_ch2_intstatus0_reg_t ch2_intstatus0; - volatile dmac_ch2_intstatus1_reg_t ch2_intstatus1; - volatile dmac_ch2_intsignal_enable0_reg_t ch2_intsignal_enable0; - volatile dmac_ch2_intsignal_enable1_reg_t ch2_intsignal_enable1; - volatile dmac_ch2_intclear0_reg_t ch2_intclear0; - volatile dmac_ch2_intclear1_reg_t ch2_intclear1; - uint32_t reserved_2a0[24]; - volatile dmac_ch3_sar0_reg_t ch3_sar0; - volatile dmac_ch3_sar1_reg_t ch3_sar1; - volatile dmac_ch3_dar0_reg_t ch3_dar0; - volatile dmac_ch3_dar1_reg_t ch3_dar1; - volatile dmac_ch3_block_ts0_reg_t ch3_block_ts0; - uint32_t reserved_314; - volatile dmac_ch3_ctl0_reg_t ch3_ctl0; - volatile dmac_ch3_ctl1_reg_t ch3_ctl1; - volatile dmac_ch3_cfg0_reg_t ch3_cfg0; - volatile dmac_ch3_cfg1_reg_t ch3_cfg1; - volatile dmac_ch3_llp0_reg_t ch3_llp0; - volatile dmac_ch3_llp1_reg_t ch3_llp1; - volatile dmac_ch3_status0_reg_t ch3_status0; - volatile dmac_ch3_status1_reg_t ch3_status1; - volatile dmac_ch3_swhssrc0_reg_t ch3_swhssrc0; - uint32_t reserved_33c; - volatile dmac_ch3_swhsdst0_reg_t ch3_swhsdst0; - uint32_t reserved_344; - volatile dmac_ch3_blk_tfr_resumereq0_reg_t ch3_blk_tfr_resumereq0; - uint32_t reserved_34c; - volatile dmac_ch3_axi_id0_reg_t ch3_axi_id0; - uint32_t reserved_354; - volatile dmac_ch3_axi_qos0_reg_t ch3_axi_qos0; - uint32_t reserved_35c; - volatile dmac_ch3_sstat0_reg_t ch3_sstat0; - uint32_t reserved_364; - volatile dmac_ch3_dstat0_reg_t ch3_dstat0; - uint32_t reserved_36c; - volatile dmac_ch3_sstatar0_reg_t ch3_sstatar0; - volatile dmac_ch3_sstatar1_reg_t ch3_sstatar1; - volatile dmac_ch3_dstatar0_reg_t ch3_dstatar0; - volatile dmac_ch3_dstatar1_reg_t ch3_dstatar1; - volatile dmac_ch3_intstatus_enable0_reg_t ch3_intstatus_enable0; - volatile dmac_ch3_intstatus_enable1_reg_t ch3_intstatus_enable1; - volatile dmac_ch3_intstatus0_reg_t ch3_intstatus0; - volatile dmac_ch3_intstatus1_reg_t ch3_intstatus1; - volatile dmac_ch3_intsignal_enable0_reg_t ch3_intsignal_enable0; - volatile dmac_ch3_intsignal_enable1_reg_t ch3_intsignal_enable1; - volatile dmac_ch3_intclear0_reg_t ch3_intclear0; - volatile dmac_ch3_intclear1_reg_t ch3_intclear1; - uint32_t reserved_3a0[24]; - volatile dmac_ch4_sar0_reg_t ch4_sar0; - volatile dmac_ch4_sar1_reg_t ch4_sar1; - volatile dmac_ch4_dar0_reg_t ch4_dar0; - volatile dmac_ch4_dar1_reg_t ch4_dar1; - volatile dmac_ch4_block_ts0_reg_t ch4_block_ts0; - uint32_t reserved_414; - volatile dmac_ch4_ctl0_reg_t ch4_ctl0; - volatile dmac_ch4_ctl1_reg_t ch4_ctl1; - volatile dmac_ch4_cfg0_reg_t ch4_cfg0; - volatile dmac_ch4_cfg1_reg_t ch4_cfg1; - volatile dmac_ch4_llp0_reg_t ch4_llp0; - volatile dmac_ch4_llp1_reg_t ch4_llp1; - volatile dmac_ch4_status0_reg_t ch4_status0; - volatile dmac_ch4_status1_reg_t ch4_status1; - volatile dmac_ch4_swhssrc0_reg_t ch4_swhssrc0; - uint32_t reserved_43c; - volatile dmac_ch4_swhsdst0_reg_t ch4_swhsdst0; - uint32_t reserved_444; - volatile dmac_ch4_blk_tfr_resumereq0_reg_t ch4_blk_tfr_resumereq0; - uint32_t reserved_44c; - volatile dmac_ch4_axi_id0_reg_t ch4_axi_id0; - uint32_t reserved_454; - volatile dmac_ch4_axi_qos0_reg_t ch4_axi_qos0; - uint32_t reserved_45c; - volatile dmac_ch4_sstat0_reg_t ch4_sstat0; - uint32_t reserved_464; - volatile dmac_ch4_dstat0_reg_t ch4_dstat0; - uint32_t reserved_46c; - volatile dmac_ch4_sstatar0_reg_t ch4_sstatar0; - volatile dmac_ch4_sstatar1_reg_t ch4_sstatar1; - volatile dmac_ch4_dstatar0_reg_t ch4_dstatar0; - volatile dmac_ch4_dstatar1_reg_t ch4_dstatar1; - volatile dmac_ch4_intstatus_enable0_reg_t ch4_intstatus_enable0; - volatile dmac_ch4_intstatus_enable1_reg_t ch4_intstatus_enable1; - volatile dmac_ch4_intstatus0_reg_t ch4_intstatus0; - volatile dmac_ch4_intstatus1_reg_t ch4_intstatus1; - volatile dmac_ch4_intsignal_enable0_reg_t ch4_intsignal_enable0; - volatile dmac_ch4_intsignal_enable1_reg_t ch4_intsignal_enable1; - volatile dmac_ch4_intclear0_reg_t ch4_intclear0; - volatile dmac_ch4_intclear1_reg_t ch4_intclear1; -} dmac_dev_t; - -extern dmac_dev_t GDMA; - -#ifndef __cplusplus -_Static_assert(sizeof(dmac_dev_t) == 0x4a0, "Invalid size of dmac_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/h264_dma_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/h264_dma_struct.h index 66197170e970..0738d5375096 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/h264_dma_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/h264_dma_struct.h @@ -10,5915 +10,1403 @@ extern "C" { #endif -/** Group: Configuration Registers */ -/** Type of out_conf0_ch0 register - * TX CH0 config0 register - */ -typedef union { - struct { - /** out_auto_wrback_ch0 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ - uint32_t out_auto_wrback_ch0:1; - /** out_eof_mode_ch0 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ - uint32_t out_eof_mode_ch0:1; - /** outdscr_burst_en_ch0 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t outdscr_burst_en_ch0:1; - /** out_ecc_aes_en_ch0 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t out_ecc_aes_en_ch0:1; - /** out_check_owner_ch0 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t out_check_owner_ch0:1; - uint32_t reserved_5:1; - /** out_mem_burst_length_ch0 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t out_mem_burst_length_ch0:3; - uint32_t reserved_9:3; - /** out_page_bound_en_ch0 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ - uint32_t out_page_bound_en_ch0:1; - uint32_t reserved_13:3; - /** out_reorder_en_ch0 : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ - uint32_t out_reorder_en_ch0:1; - uint32_t reserved_17:7; - /** out_rst_ch0 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ - uint32_t out_rst_ch0:1; - /** out_cmd_disable_ch0 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t out_cmd_disable_ch0:1; - /** out_arb_weight_opt_dis_ch0 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t out_arb_weight_opt_dis_ch0:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} h264_dma_out_conf0_ch0_reg_t; - -/** Type of out_push_ch0 register - * TX CH0 outfifo push register - */ -typedef union { - struct { - /** outfifo_wdata_ch0 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ - uint32_t outfifo_wdata_ch0:10; - /** outfifo_push_ch0 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ - uint32_t outfifo_push_ch0:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} h264_dma_out_push_ch0_reg_t; - -/** Type of out_link_conf_ch0 register - * TX CH0 out_link dscr ctrl register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** outlink_stop_ch0 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - uint32_t outlink_stop_ch0:1; - /** outlink_start_ch0 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - uint32_t outlink_start_ch0:1; - /** outlink_restart_ch0 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - uint32_t outlink_restart_ch0:1; - /** outlink_park_ch0 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ - uint32_t outlink_park_ch0:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_out_link_conf_ch0_reg_t; - -/** Type of out_ro_pd_conf_ch0 register - * TX CH0 reorder power config register - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** out_ro_ram_force_pd_ch0 : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ - uint32_t out_ro_ram_force_pd_ch0:1; - /** out_ro_ram_force_pu_ch0 : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ - uint32_t out_ro_ram_force_pu_ch0:1; - /** out_ro_ram_clk_fo_ch0 : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ - uint32_t out_ro_ram_clk_fo_ch0:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} h264_dma_out_ro_pd_conf_ch0_reg_t; - -/** Type of out_push_ch1 register - * TX CH1 outfifo push register - */ -typedef union { - struct { - /** outfifo_wdata_ch1 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ - uint32_t outfifo_wdata_ch1:10; - /** outfifo_push_ch1 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ - uint32_t outfifo_push_ch1:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} h264_dma_out_push_ch1_reg_t; - -/** Type of out_link_conf_ch1 register - * TX CH1 out_link dscr ctrl register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** outlink_stop_ch1 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - uint32_t outlink_stop_ch1:1; - /** outlink_start_ch1 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - uint32_t outlink_start_ch1:1; - /** outlink_restart_ch1 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - uint32_t outlink_restart_ch1:1; - /** outlink_park_ch1 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ - uint32_t outlink_park_ch1:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_out_link_conf_ch1_reg_t; - -/** Type of out_push_ch2 register - * TX CH2 outfifo push register - */ -typedef union { - struct { - /** outfifo_wdata_ch2 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ - uint32_t outfifo_wdata_ch2:10; - /** outfifo_push_ch2 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ - uint32_t outfifo_push_ch2:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} h264_dma_out_push_ch2_reg_t; - -/** Type of out_link_conf_ch2 register - * TX CH2 out_link dscr ctrl register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** outlink_stop_ch2 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - uint32_t outlink_stop_ch2:1; - /** outlink_start_ch2 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - uint32_t outlink_start_ch2:1; - /** outlink_restart_ch2 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - uint32_t outlink_restart_ch2:1; - /** outlink_park_ch2 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ - uint32_t outlink_park_ch2:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_out_link_conf_ch2_reg_t; - -/** Type of out_push_ch3 register - * TX CH3 outfifo push register - */ -typedef union { - struct { - /** outfifo_wdata_ch3 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ - uint32_t outfifo_wdata_ch3:10; - /** outfifo_push_ch3 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ - uint32_t outfifo_push_ch3:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} h264_dma_out_push_ch3_reg_t; - -/** Type of out_link_conf_ch3 register - * TX CH3 out_link dscr ctrl register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** outlink_stop_ch3 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - uint32_t outlink_stop_ch3:1; - /** outlink_start_ch3 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - uint32_t outlink_start_ch3:1; - /** outlink_restart_ch3 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - uint32_t outlink_restart_ch3:1; - /** outlink_park_ch3 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ - uint32_t outlink_park_ch3:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_out_link_conf_ch3_reg_t; -/** Type of out_push_ch4 register - * TX CH4 outfifo push register +/** Type of out_push register + * TX CHn outfifo push register */ typedef union { struct { - /** outfifo_wdata_ch4 : R/W; bitpos: [9:0]; default: 0; + /** outfifo_wdata : R/W; bitpos: [9:0]; default: 0; * This register stores the data that need to be pushed into DMA Tx FIFO. */ - uint32_t outfifo_wdata_ch4:10; - /** outfifo_push_ch4 : R/W/SC; bitpos: [10]; default: 0; + uint32_t outfifo_wdata: 10; + /** outfifo_push : R/W/SC; bitpos: [10]; default: 0; * Set this bit to push data into DMA Tx FIFO. */ - uint32_t outfifo_push_ch4:1; - uint32_t reserved_11:21; + uint32_t outfifo_push: 1; + uint32_t reserved_11: 21; }; uint32_t val; -} h264_dma_out_push_ch4_reg_t; +} h264_dma_out_push_chn_reg_t; -/** Type of out_link_conf_ch4 register - * TX CH4 out_link dscr ctrl register +/** Type of out_link_conf register + * TX CHn out_link dscr ctrl register */ typedef union { struct { - uint32_t reserved_0:20; - /** outlink_stop_ch4 : R/W/SC; bitpos: [20]; default: 0; + uint32_t reserved_0: 20; + /** outlink_stop : R/W/SC; bitpos: [20]; default: 0; * Set this bit to stop dealing with the outlink descriptors. */ - uint32_t outlink_stop_ch4:1; - /** outlink_start_ch4 : R/W/SC; bitpos: [21]; default: 0; + uint32_t outlink_stop: 1; + /** outlink_start : R/W/SC; bitpos: [21]; default: 0; * Set this bit to start dealing with the outlink descriptors. */ - uint32_t outlink_start_ch4:1; - /** outlink_restart_ch4 : R/W/SC; bitpos: [22]; default: 0; + uint32_t outlink_start: 1; + /** outlink_restart : R/W/SC; bitpos: [22]; default: 0; * Set this bit to restart a new outlink from the last address. */ - uint32_t outlink_restart_ch4:1; - /** outlink_park_ch4 : RO; bitpos: [23]; default: 1; + uint32_t outlink_restart: 1; + /** outlink_park : RO; bitpos: [23]; default: 1; * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM * is working. */ - uint32_t outlink_park_ch4:1; - uint32_t reserved_24:8; + uint32_t outlink_park: 1; + uint32_t reserved_24: 8; }; uint32_t val; -} h264_dma_out_link_conf_ch4_reg_t; +} h264_dma_out_link_conf_chn_reg_t; -/** Type of in_conf0_ch0 register - * RX CH0 config0 register +/** Type of in_conf0 register + * RX CHn config0 register */ typedef union { struct { - uint32_t reserved_0:2; - /** indscr_burst_en_ch0 : R/W; bitpos: [2]; default: 0; + uint32_t reserved_0: 2; + /** indscr_burst_en : R/W; bitpos: [2]; default: 0; * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor * when accessing SRAM. */ - uint32_t indscr_burst_en_ch0:1; - /** in_ecc_aes_en_ch0 : R/W; bitpos: [3]; default: 0; + uint32_t indscr_burst_en: 1; + /** in_ecc_aes_en : R/W; bitpos: [3]; default: 0; * When access address space is ecc/aes area, this bit should be set to 1. In this * case, the start address of square should be 16-bit aligned. The width of square * multiply byte number of one pixel should be 16-bit aligned. */ - uint32_t in_ecc_aes_en_ch0:1; - /** in_check_owner_ch0 : R/W; bitpos: [4]; default: 0; + uint32_t in_ecc_aes_en: 1; + /** in_check_owner : R/W; bitpos: [4]; default: 0; * Set this bit to enable checking the owner attribute of the link descriptor. */ - uint32_t in_check_owner_ch0:1; - uint32_t reserved_5:1; - /** in_mem_burst_length_ch0 : R/W; bitpos: [8:6]; default: 0; + uint32_t in_check_owner: 1; + uint32_t reserved_5: 1; + /** in_mem_burst_length : R/W; bitpos: [8:6]; default: 0; * Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 * bytes 4: 128 bytes */ - uint32_t in_mem_burst_length_ch0:3; - uint32_t reserved_9:3; - /** in_page_bound_en_ch0 : R/W; bitpos: [12]; default: 0; + uint32_t in_mem_burst_length: 3; + uint32_t reserved_9: 3; + /** in_page_bound_en : R/W; bitpos: [12]; default: 0; * Set this bit to 1 to make sure AXI write data don't cross the address boundary * which define by mem_burst_length */ - uint32_t in_page_bound_en_ch0:1; - uint32_t reserved_13:11; - /** in_rst_ch0 : R/W; bitpos: [24]; default: 0; + uint32_t in_page_bound_en: 1; + uint32_t reserved_13: 11; + /** in_rst : R/W; bitpos: [24]; default: 0; * Write 1 then write 0 to this bit to reset Rx channel */ - uint32_t in_rst_ch0:1; - /** in_cmd_disable_ch0 : R/W; bitpos: [25]; default: 0; + uint32_t in_rst: 1; + /** in_cmd_disable : R/W; bitpos: [25]; default: 0; * Write 1 before reset and write 0 after reset */ - uint32_t in_cmd_disable_ch0:1; - /** in_arb_weight_opt_dis_ch0 : R/W; bitpos: [26]; default: 0; + uint32_t in_cmd_disable: 1; + /** in_arb_weight_opt_dis : R/W; bitpos: [26]; default: 0; * Set this bit to 1 to disable arbiter optimum weight function. */ - uint32_t in_arb_weight_opt_dis_ch0:1; - uint32_t reserved_27:5; + uint32_t in_arb_weight_opt_dis: 1; + uint32_t reserved_27: 5; }; uint32_t val; -} h264_dma_in_conf0_ch0_reg_t; +} h264_dma_in_conf0_chn_reg_t; -/** Type of in_pop_ch0 register - * RX CH0 INFIFO pop register +/** Type of in_pop register + * RX CHn INFIFO pop register */ typedef union { struct { - /** infifo_rdata_ch0 : RO; bitpos: [10:0]; default: 1024; + /** infifo_rdata : RO; bitpos: [10:0]; default: 1024; * This register stores the data popping from DMA Rx FIFO. */ - uint32_t infifo_rdata_ch0:11; - /** infifo_pop_ch0 : R/W/SC; bitpos: [11]; default: 0; + uint32_t infifo_rdata: 11; + /** infifo_pop : R/W/SC; bitpos: [11]; default: 0; * Set this bit to pop data from DMA Rx FIFO. */ - uint32_t infifo_pop_ch0:1; - uint32_t reserved_12:20; + uint32_t infifo_pop: 1; + uint32_t reserved_12: 20; }; uint32_t val; -} h264_dma_in_pop_ch0_reg_t; +} h264_dma_in_pop_chn_reg_t; -/** Type of in_link_conf_ch0 register - * RX CH0 in_link dscr ctrl register +/** Type of in_link_conf register + * RX CHn in_link dscr ctrl register */ typedef union { struct { - uint32_t reserved_0:20; - /** inlink_auto_ret_ch0 : R/W; bitpos: [20]; default: 1; + uint32_t reserved_0: 20; + /** inlink_auto_ret : R/W; bitpos: [20]; default: 1; * Set this bit to return to current inlink descriptor's address, when there are some * errors in current receiving data. */ - uint32_t inlink_auto_ret_ch0:1; - /** inlink_stop_ch0 : R/W/SC; bitpos: [21]; default: 0; + uint32_t inlink_auto_ret: 1; + /** inlink_stop : R/W/SC; bitpos: [21]; default: 0; * Set this bit to stop dealing with the inlink descriptors. */ - uint32_t inlink_stop_ch0:1; - /** inlink_start_ch0 : R/W/SC; bitpos: [22]; default: 0; + uint32_t inlink_stop: 1; + /** inlink_start : R/W/SC; bitpos: [22]; default: 0; * Set this bit to start dealing with the inlink descriptors. */ - uint32_t inlink_start_ch0:1; - /** inlink_restart_ch0 : R/W/SC; bitpos: [23]; default: 0; + uint32_t inlink_start: 1; + /** inlink_restart : R/W/SC; bitpos: [23]; default: 0; * Set this bit to mount a new inlink descriptor. */ - uint32_t inlink_restart_ch0:1; - /** inlink_park_ch0 : RO; bitpos: [24]; default: 1; + uint32_t inlink_restart: 1; + /** inlink_park : RO; bitpos: [24]; default: 1; * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is * working. */ - uint32_t inlink_park_ch0:1; - uint32_t reserved_25:7; + uint32_t inlink_park: 1; + uint32_t reserved_25: 7; }; uint32_t val; -} h264_dma_in_link_conf_ch0_reg_t; +} h264_dma_in_link_conf_chn_reg_t; -/** Type of in_ro_pd_conf_ch0 register - * RX CH0 reorder power config register +/** Type of in_ro_pd_conf register + * RX CHn reorder power config register */ typedef union { struct { - uint32_t reserved_0:6; - /** in_ro_ram_clk_fo_ch0 : R/W; bitpos: [6]; default: 0; + uint32_t reserved_0: 6; + /** in_ro_ram_clk_fo : R/W; bitpos: [6]; default: 0; * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. * 0: A gate-clock will be used when accessing the RAM in DMA. */ - uint32_t in_ro_ram_clk_fo_ch0:1; - uint32_t reserved_7:25; + uint32_t in_ro_ram_clk_fo: 1; + uint32_t reserved_7: 25; }; uint32_t val; -} h264_dma_in_ro_pd_conf_ch0_reg_t; +} h264_dma_in_ro_pd_conf_chn_reg_t; -/** Type of in_conf0_ch1 register - * RX CH1 config0 register +/** Type of in_conf0_ch5 register + * RX CH5 config0 register */ typedef union { struct { - uint32_t reserved_0:2; - /** indscr_burst_en_ch1 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ - uint32_t indscr_burst_en_ch1:1; - /** in_ecc_aes_en_ch1 : R/W; bitpos: [3]; default: 0; + uint32_t reserved_0: 3; + /** in_ecc_aes_en : R/W; bitpos: [3]; default: 0; * When access address space is ecc/aes area, this bit should be set to 1. In this * case, the start address of square should be 16-bit aligned. The width of square * multiply byte number of one pixel should be 16-bit aligned. */ - uint32_t in_ecc_aes_en_ch1:1; - /** in_check_owner_ch1 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t in_check_owner_ch1:1; - uint32_t reserved_5:1; - /** in_mem_burst_length_ch1 : R/W; bitpos: [8:6]; default: 0; + uint32_t in_ecc_aes_en: 1; + uint32_t reserved_4: 2; + /** in_mem_burst_length : R/W; bitpos: [8:6]; default: 0; * Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 * bytes 4: 128 bytes */ - uint32_t in_mem_burst_length_ch1:3; - uint32_t reserved_9:3; - /** in_page_bound_en_ch1 : R/W; bitpos: [12]; default: 0; + uint32_t in_mem_burst_length: 3; + uint32_t reserved_9: 3; + /** in_page_bound_en : R/W; bitpos: [12]; default: 0; * Set this bit to 1 to make sure AXI write data don't cross the address boundary * which define by mem_burst_length */ - uint32_t in_page_bound_en_ch1:1; - uint32_t reserved_13:11; - /** in_rst_ch1 : R/W; bitpos: [24]; default: 0; + uint32_t in_page_bound_en: 1; + uint32_t reserved_13: 11; + /** in_rst : R/W; bitpos: [24]; default: 0; * Write 1 then write 0 to this bit to reset Rx channel */ - uint32_t in_rst_ch1:1; - /** in_cmd_disable_ch1 : R/W; bitpos: [25]; default: 0; + uint32_t in_rst: 1; + /** in_cmd_disable : R/W; bitpos: [25]; default: 0; * Write 1 before reset and write 0 after reset */ - uint32_t in_cmd_disable_ch1:1; - /** in_arb_weight_opt_dis_ch1 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t in_arb_weight_opt_dis_ch1:1; - uint32_t reserved_27:5; + uint32_t in_cmd_disable: 1; + uint32_t reserved_26: 6; }; uint32_t val; -} h264_dma_in_conf0_ch1_reg_t; +} h264_dma_in_conf0_ch5_reg_t; -/** Type of in_pop_ch1 register - * RX CH1 INFIFO pop register +/** Type of in_pop_ch5 register + * RX CH5 INFIFO pop register */ typedef union { struct { - /** infifo_rdata_ch1 : RO; bitpos: [10:0]; default: 1024; + /** infifo_rdata : RO; bitpos: [10:0]; default: 1024; * This register stores the data popping from DMA Rx FIFO. */ - uint32_t infifo_rdata_ch1:11; - /** infifo_pop_ch1 : R/W/SC; bitpos: [11]; default: 0; + uint32_t infifo_rdata: 11; + /** infifo_pop : R/W/SC; bitpos: [11]; default: 0; * Set this bit to pop data from DMA Rx FIFO. */ - uint32_t infifo_pop_ch1:1; - uint32_t reserved_12:20; + uint32_t infifo_pop: 1; + uint32_t reserved_12: 20; }; uint32_t val; -} h264_dma_in_pop_ch1_reg_t; +} h264_dma_in_pop_ch5_reg_t; -/** Type of in_link_conf_ch1 register - * RX CH1 in_link dscr ctrl register +/** Type of rst_conf register + * axi reset config register */ typedef union { struct { - uint32_t reserved_0:20; - /** inlink_auto_ret_ch1 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. + /** inter_axim_rd_rst : R/W; bitpos: [0]; default: 0; + * Write 1 then write 0 to this bit to reset axi master read data FIFO. */ - uint32_t inlink_auto_ret_ch1:1; - /** inlink_stop_ch1 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. + uint32_t inter_axim_rd_rst: 1; + /** inter_axim_wr_rst : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset axi master write data FIFO. */ - uint32_t inlink_stop_ch1:1; - /** inlink_start_ch1 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. + uint32_t inter_axim_wr_rst: 1; + /** exter_axim_rd_rst : R/W; bitpos: [2]; default: 0; + * Write 1 then write 0 to this bit to reset axi master read data FIFO. */ - uint32_t inlink_start_ch1:1; - /** inlink_restart_ch1 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. + uint32_t exter_axim_rd_rst: 1; + /** exter_axim_wr_rst : R/W; bitpos: [3]; default: 0; + * Write 1 then write 0 to this bit to reset axi master write data FIFO. */ - uint32_t inlink_restart_ch1:1; - /** inlink_park_ch1 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. + uint32_t exter_axim_wr_rst: 1; + /** clk_en : R/W; bitpos: [4]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. */ - uint32_t inlink_park_ch1:1; - uint32_t reserved_25:7; + uint32_t clk_en: 1; + uint32_t reserved_5: 27; }; uint32_t val; -} h264_dma_in_link_conf_ch1_reg_t; +} h264_dma_rst_conf_reg_t; + -/** Type of in_conf0_ch2 register - * RX CH2 config0 register +/** Type of out_int_raw register + * TX CHn interrupt raw register */ typedef union { struct { - uint32_t reserved_0:2; - /** indscr_burst_en_ch2 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. + /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. */ - uint32_t indscr_burst_en_ch2:1; - /** in_ecc_aes_en_ch2 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. + uint32_t done_int_raw: 1; + /** eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. */ - uint32_t in_ecc_aes_en_ch2:1; - /** in_check_owner_ch2 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. + uint32_t eof_int_raw: 1; + /** dscr_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error, + * including owner error, the second and third word error of outlink descriptor for Tx + * channel 0. */ - uint32_t in_check_owner_ch2:1; - uint32_t reserved_5:1; - /** in_mem_burst_length_ch2 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes + uint32_t dscr_err_int_raw: 1; + /** total_eof_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. */ - uint32_t in_mem_burst_length_ch2:3; - uint32_t reserved_9:3; - /** in_page_bound_en_ch2 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length + uint32_t total_eof_int_raw: 1; + /** outfifo_ovf_l1_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when fifo is overflow. */ - uint32_t in_page_bound_en_ch2:1; - uint32_t reserved_13:11; - /** in_rst_ch2 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel + uint32_t outfifo_ovf_l1_int_raw: 1; + /** outfifo_udf_l1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when fifo is underflow. */ - uint32_t in_rst_ch2:1; - /** in_cmd_disable_ch2 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset + uint32_t outfifo_udf_l1_int_raw: 1; + /** outfifo_ovf_l2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when fifo is overflow. */ - uint32_t in_cmd_disable_ch2:1; - /** in_arb_weight_opt_dis_ch2 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. + uint32_t outfifo_ovf_l2_int_raw: 1; + /** outfifo_udf_l2_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when fifo is underflow. + */ + uint32_t outfifo_udf_l2_int_raw: 1; + /** dscr_task_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. */ - uint32_t in_arb_weight_opt_dis_ch2:1; - uint32_t reserved_27:5; + uint32_t dscr_task_ovf_int_raw: 1; + uint32_t reserved_9: 23; }; uint32_t val; -} h264_dma_in_conf0_ch2_reg_t; +} h264_dma_out_int_raw_chn_reg_t; -/** Type of in_pop_ch2 register - * RX CH2 INFIFO pop register +/** Type of out_int_ena register + * TX CHn interrupt ena register */ typedef union { struct { - /** infifo_rdata_ch2 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. + /** done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ - uint32_t infifo_rdata_ch2:11; - /** infifo_pop_ch2 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. + uint32_t done_int_ena: 1; + /** eof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ + uint32_t eof_int_ena: 1; + /** dscr_err_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t dscr_err_int_ena: 1; + /** total_eof_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t total_eof_int_ena: 1; + /** outfifo_ovf_l1_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_l1_int_ena: 1; + /** outfifo_udf_l1_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_l1_int_ena: 1; + /** outfifo_ovf_l2_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + */ + uint32_t outfifo_ovf_l2_int_ena: 1; + /** outfifo_udf_l2_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ - uint32_t infifo_pop_ch2:1; - uint32_t reserved_12:20; + uint32_t outfifo_udf_l2_int_ena: 1; + /** dscr_task_ovf_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + */ + uint32_t dscr_task_ovf_int_ena: 1; + uint32_t reserved_9: 23; }; uint32_t val; -} h264_dma_in_pop_ch2_reg_t; +} h264_dma_out_int_ena_chn_reg_t; -/** Type of in_link_conf_ch2 register - * RX CH2 in_link dscr ctrl register +/** Type of out_int_st register + * TX CHn interrupt st register */ typedef union { struct { - uint32_t reserved_0:20; - /** inlink_auto_ret_ch2 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. + /** done_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ - uint32_t inlink_auto_ret_ch2:1; - /** inlink_stop_ch2 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. + uint32_t done_int_st: 1; + /** eof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ - uint32_t inlink_stop_ch2:1; - /** inlink_start_ch2 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. + uint32_t eof_int_st: 1; + /** dscr_err_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - uint32_t inlink_start_ch2:1; - /** inlink_restart_ch2 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. + uint32_t dscr_err_int_st: 1; + /** total_eof_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - uint32_t inlink_restart_ch2:1; - /** inlink_park_ch2 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. + uint32_t total_eof_int_st: 1; + /** outfifo_ovf_l1_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_l1_int_st: 1; + /** outfifo_udf_l1_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t inlink_park_ch2:1; - uint32_t reserved_25:7; + uint32_t outfifo_udf_l1_int_st: 1; + /** outfifo_ovf_l2_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + */ + uint32_t outfifo_ovf_l2_int_st: 1; + /** outfifo_udf_l2_int_st : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + */ + uint32_t outfifo_udf_l2_int_st: 1; + /** dscr_task_ovf_int_st : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + */ + uint32_t dscr_task_ovf_int_st: 1; + uint32_t reserved_9: 23; }; uint32_t val; -} h264_dma_in_link_conf_ch2_reg_t; +} h264_dma_out_int_st_chn_reg_t; -/** Type of in_conf0_ch3 register - * RX CH3 config0 register +/** Type of out_int_clr register + * TX CHn interrupt clr register */ typedef union { struct { - uint32_t reserved_0:2; - /** indscr_burst_en_ch3 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. + /** done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. */ - uint32_t indscr_burst_en_ch3:1; - /** in_ecc_aes_en_ch3 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. + uint32_t done_int_clr: 1; + /** eof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. */ - uint32_t in_ecc_aes_en_ch3:1; - /** in_check_owner_ch3 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. + uint32_t eof_int_clr: 1; + /** dscr_err_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ - uint32_t in_check_owner_ch3:1; - uint32_t reserved_5:1; - /** in_mem_burst_length_ch3 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t in_mem_burst_length_ch3:3; - uint32_t reserved_9:3; - /** in_page_bound_en_ch3 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ - uint32_t in_page_bound_en_ch3:1; - uint32_t reserved_13:11; - /** in_rst_ch3 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ - uint32_t in_rst_ch3:1; - /** in_cmd_disable_ch3 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t in_cmd_disable_ch3:1; - /** in_arb_weight_opt_dis_ch3 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t in_arb_weight_opt_dis_ch3:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} h264_dma_in_conf0_ch3_reg_t; - -/** Type of in_pop_ch3 register - * RX CH3 INFIFO pop register - */ -typedef union { - struct { - /** infifo_rdata_ch3 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ - uint32_t infifo_rdata_ch3:11; - /** infifo_pop_ch3 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ - uint32_t infifo_pop_ch3:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} h264_dma_in_pop_ch3_reg_t; - -/** Type of in_link_conf_ch3 register - * RX CH3 in_link dscr ctrl register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** inlink_auto_ret_ch3 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ - uint32_t inlink_auto_ret_ch3:1; - /** inlink_stop_ch3 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ - uint32_t inlink_stop_ch3:1; - /** inlink_start_ch3 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ - uint32_t inlink_start_ch3:1; - /** inlink_restart_ch3 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ - uint32_t inlink_restart_ch3:1; - /** inlink_park_ch3 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ - uint32_t inlink_park_ch3:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} h264_dma_in_link_conf_ch3_reg_t; - -/** Type of in_conf0_ch4 register - * RX CH4 config0 register - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** indscr_burst_en_ch4 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ - uint32_t indscr_burst_en_ch4:1; - /** in_ecc_aes_en_ch4 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t in_ecc_aes_en_ch4:1; - /** in_check_owner_ch4 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t in_check_owner_ch4:1; - uint32_t reserved_5:1; - /** in_mem_burst_length_ch4 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t in_mem_burst_length_ch4:3; - uint32_t reserved_9:3; - /** in_page_bound_en_ch4 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ - uint32_t in_page_bound_en_ch4:1; - uint32_t reserved_13:11; - /** in_rst_ch4 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ - uint32_t in_rst_ch4:1; - /** in_cmd_disable_ch4 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t in_cmd_disable_ch4:1; - /** in_arb_weight_opt_dis_ch4 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t in_arb_weight_opt_dis_ch4:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} h264_dma_in_conf0_ch4_reg_t; - -/** Type of in_pop_ch4 register - * RX CH4 INFIFO pop register - */ -typedef union { - struct { - /** infifo_rdata_ch4 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ - uint32_t infifo_rdata_ch4:11; - /** infifo_pop_ch4 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ - uint32_t infifo_pop_ch4:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} h264_dma_in_pop_ch4_reg_t; - -/** Type of in_link_conf_ch4 register - * RX CH4 in_link dscr ctrl register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** inlink_auto_ret_ch4 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ - uint32_t inlink_auto_ret_ch4:1; - /** inlink_stop_ch4 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ - uint32_t inlink_stop_ch4:1; - /** inlink_start_ch4 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ - uint32_t inlink_start_ch4:1; - /** inlink_restart_ch4 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ - uint32_t inlink_restart_ch4:1; - /** inlink_park_ch4 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. + uint32_t dscr_err_int_clr: 1; + /** total_eof_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ - uint32_t inlink_park_ch4:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} h264_dma_in_link_conf_ch4_reg_t; - -/** Type of in_conf0_ch5 register - * RX CH5 config0 register - */ -typedef union { - struct { - uint32_t reserved_0:3; - /** in_ecc_aes_en_ch5 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. + uint32_t total_eof_int_clr: 1; + /** outfifo_ovf_l1_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t in_ecc_aes_en_ch5:1; - uint32_t reserved_4:2; - /** in_mem_burst_length_ch5 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes + uint32_t outfifo_ovf_l1_int_clr: 1; + /** outfifo_udf_l1_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t in_mem_burst_length_ch5:3; - uint32_t reserved_9:3; - /** in_page_bound_en_ch5 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length + uint32_t outfifo_udf_l1_int_clr: 1; + /** outfifo_ovf_l2_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. */ - uint32_t in_page_bound_en_ch5:1; - uint32_t reserved_13:11; - /** in_rst_ch5 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel + uint32_t outfifo_ovf_l2_int_clr: 1; + /** outfifo_udf_l2_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. */ - uint32_t in_rst_ch5:1; - /** in_cmd_disable_ch5 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset + uint32_t outfifo_udf_l2_int_clr: 1; + /** dscr_task_ovf_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t in_cmd_disable_ch5:1; - uint32_t reserved_26:6; + uint32_t dscr_task_ovf_int_clr: 1; + uint32_t reserved_9: 23; }; uint32_t val; -} h264_dma_in_conf0_ch5_reg_t; +} h264_dma_out_int_clr_chn_reg_t; -/** Type of in_pop_ch5 register - * RX CH5 INFIFO pop register - */ -typedef union { - struct { - /** infifo_rdata_ch5 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ - uint32_t infifo_rdata_ch5:11; - /** infifo_pop_ch5 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ - uint32_t infifo_pop_ch5:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} h264_dma_in_pop_ch5_reg_t; -/** Type of rst_conf register - * axi reset config register +/** Type of in_int_raw register + * RX CH0 interrupt raw register */ typedef union { struct { - /** inter_axim_rd_rst : R/W; bitpos: [0]; default: 0; - * Write 1 then write 0 to this bit to reset axi master read data FIFO. - */ - uint32_t inter_axim_rd_rst:1; - /** inter_axim_wr_rst : R/W; bitpos: [1]; default: 0; - * Write 1 then write 0 to this bit to reset axi master write data FIFO. - */ - uint32_t inter_axim_wr_rst:1; - /** exter_axim_rd_rst : R/W; bitpos: [2]; default: 0; - * Write 1 then write 0 to this bit to reset axi master read data FIFO. - */ - uint32_t exter_axim_rd_rst:1; - /** exter_axim_wr_rst : R/W; bitpos: [3]; default: 0; - * Write 1 then write 0 to this bit to reset axi master write data FIFO. - */ - uint32_t exter_axim_wr_rst:1; - /** clk_en : R/W; bitpos: [4]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes - * registers. + /** in_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been transmitted to peripherals for Rx channel 0. */ - uint32_t clk_en:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} h264_dma_rst_conf_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of out_int_raw_ch0 register - * TX CH0 interrupt raw register - */ -typedef union { - struct { - /** out_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. + uint32_t in_done_int_raw: 1; + /** in_suc_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received and no data error is detected for Rx channel 0. */ - uint32_t out_done_ch0_int_raw:1; - /** out_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. + uint32_t in_suc_eof_int_raw: 1; + /** in_err_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received and data error is detected */ - uint32_t out_eof_ch0_int_raw:1; - /** out_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx + uint32_t in_err_eof_int_raw: 1; + /** in_dscr_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error, + * including owner error, the second and third word error of inlink descriptor for Rx * channel 0. */ - uint32_t out_dscr_err_ch0_int_raw:1; - /** out_total_eof_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. + uint32_t in_dscr_err_int_raw: 1; + /** infifo_ovf_l1_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. */ - uint32_t out_total_eof_ch0_int_raw:1; - /** outfifo_ovf_l1_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. + uint32_t infifo_ovf_l1_int_raw: 1; + /** infifo_udf_l1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. */ - uint32_t outfifo_ovf_l1_ch0_int_raw:1; - /** outfifo_udf_l1_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. + uint32_t infifo_udf_l1_int_raw: 1; + /** infifo_ovf_l2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. */ - uint32_t outfifo_udf_l1_ch0_int_raw:1; - /** outfifo_ovf_l2_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. + uint32_t infifo_ovf_l2_int_raw: 1; + /** infifo_udf_l2_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. */ - uint32_t outfifo_ovf_l2_ch0_int_raw:1; - /** outfifo_udf_l2_ch0_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. + uint32_t infifo_udf_l2_int_raw: 1; + /** in_dscr_empty_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when the last descriptor is done but fifo + * also remain data. */ - uint32_t outfifo_udf_l2_ch0_int_raw:1; - /** out_dscr_task_ovf_ch0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + uint32_t in_dscr_empty_int_raw: 1; + /** in_dscr_task_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0; * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. */ - uint32_t out_dscr_task_ovf_ch0_int_raw:1; - uint32_t reserved_9:23; + uint32_t in_dscr_task_ovf_int_raw: 1; + uint32_t reserved_10: 22; }; uint32_t val; -} h264_dma_out_int_raw_ch0_reg_t; +} h264_dma_in_int_raw_chn_reg_t; -/** Type of out_int_ena_ch0 register - * TX CH0 interrupt ena register +/** Type of in_int_ena register + * RX CH0 interrupt ena register */ typedef union { struct { - /** out_done_ch0_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + /** in_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ - uint32_t out_done_ch0_int_ena:1; - /** out_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + uint32_t in_done_int_ena: 1; + /** in_suc_eof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ - uint32_t out_eof_ch0_int_ena:1; - /** out_dscr_err_ch0_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + uint32_t in_suc_eof_int_ena: 1; + /** in_err_eof_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ - uint32_t out_dscr_err_ch0_int_ena:1; - /** out_total_eof_ch0_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + uint32_t in_err_eof_int_ena: 1; + /** in_dscr_err_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ - uint32_t out_total_eof_ch0_int_ena:1; - /** outfifo_ovf_l1_ch0_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + uint32_t in_dscr_err_int_ena: 1; + /** infifo_ovf_l1_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t outfifo_ovf_l1_ch0_int_ena:1; - /** outfifo_udf_l1_ch0_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + uint32_t infifo_ovf_l1_int_ena: 1; + /** infifo_udf_l1_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t outfifo_udf_l1_ch0_int_ena:1; - /** outfifo_ovf_l2_ch0_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + uint32_t infifo_udf_l1_int_ena: 1; + /** infifo_ovf_l2_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. */ - uint32_t outfifo_ovf_l2_ch0_int_ena:1; - /** outfifo_udf_l2_ch0_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + uint32_t infifo_ovf_l2_int_ena: 1; + /** infifo_udf_l2_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. */ - uint32_t outfifo_udf_l2_ch0_int_ena:1; - /** out_dscr_task_ovf_ch0_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + uint32_t infifo_udf_l2_int_ena: 1; + /** in_dscr_empty_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_int_ena: 1; + /** in_dscr_task_ovf_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t out_dscr_task_ovf_ch0_int_ena:1; - uint32_t reserved_9:23; + uint32_t in_dscr_task_ovf_int_ena: 1; + uint32_t reserved_10: 22; }; uint32_t val; -} h264_dma_out_int_ena_ch0_reg_t; +} h264_dma_in_int_ena_chn_reg_t; -/** Type of out_int_st_ch0 register - * TX CH0 interrupt st register +/** Type of in_int_st register + * RX CH0 interrupt st register */ typedef union { struct { - /** out_done_ch0_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + /** in_done_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ - uint32_t out_done_ch0_int_st:1; - /** out_eof_ch0_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + uint32_t in_done_int_st: 1; + /** in_suc_eof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ - uint32_t out_eof_ch0_int_st:1; - /** out_dscr_err_ch0_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + uint32_t in_suc_eof_int_st: 1; + /** in_err_eof_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ - uint32_t out_dscr_err_ch0_int_st:1; - /** out_total_eof_ch0_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + uint32_t in_err_eof_int_st: 1; + /** in_dscr_err_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ - uint32_t out_total_eof_ch0_int_st:1; - /** outfifo_ovf_l1_ch0_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + uint32_t in_dscr_err_int_st: 1; + /** infifo_ovf_l1_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t outfifo_ovf_l1_ch0_int_st:1; - /** outfifo_udf_l1_ch0_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + uint32_t infifo_ovf_l1_int_st: 1; + /** infifo_udf_l1_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t outfifo_udf_l1_ch0_int_st:1; - /** outfifo_ovf_l2_ch0_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + uint32_t infifo_udf_l1_int_st: 1; + /** infifo_ovf_l2_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. */ - uint32_t outfifo_ovf_l2_ch0_int_st:1; - /** outfifo_udf_l2_ch0_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + uint32_t infifo_ovf_l2_int_st: 1; + /** infifo_udf_l2_int_st : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. */ - uint32_t outfifo_udf_l2_ch0_int_st:1; - /** out_dscr_task_ovf_ch0_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + uint32_t infifo_udf_l2_int_st: 1; + /** in_dscr_empty_int_st : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_int_st: 1; + /** in_dscr_task_ovf_int_st : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t out_dscr_task_ovf_ch0_int_st:1; - uint32_t reserved_9:23; + uint32_t in_dscr_task_ovf_int_st: 1; + uint32_t reserved_10: 22; }; uint32_t val; -} h264_dma_out_int_st_ch0_reg_t; +} h264_dma_in_int_st_chn_reg_t; -/** Type of out_int_clr_ch0 register - * TX CH0 interrupt clr register +/** Type of in_int_clr register + * RX CH0 interrupt clr register */ typedef union { struct { - /** out_done_ch0_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch0_int_clr:1; - /** out_eof_ch0_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch0_int_clr:1; - /** out_dscr_err_ch0_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch0_int_clr:1; - /** out_total_eof_ch0_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + /** in_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. */ - uint32_t out_total_eof_ch0_int_clr:1; - /** outfifo_ovf_l1_ch0_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + uint32_t in_done_int_clr: 1; + /** in_suc_eof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ - uint32_t outfifo_ovf_l1_ch0_int_clr:1; - /** outfifo_udf_l1_ch0_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + uint32_t in_suc_eof_int_clr: 1; + /** in_err_eof_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ - uint32_t outfifo_udf_l1_ch0_int_clr:1; - /** outfifo_ovf_l2_ch0_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + uint32_t in_err_eof_int_clr: 1; + /** in_dscr_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. */ - uint32_t outfifo_ovf_l2_ch0_int_clr:1; - /** outfifo_udf_l2_ch0_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + uint32_t in_dscr_err_int_clr: 1; + /** infifo_ovf_l1_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ - uint32_t outfifo_udf_l2_ch0_int_clr:1; - /** out_dscr_task_ovf_ch0_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + uint32_t infifo_ovf_l1_int_clr: 1; + /** infifo_udf_l1_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t out_dscr_task_ovf_ch0_int_clr:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_clr_ch0_reg_t; - -/** Type of out_int_raw_ch1 register - * TX CH1 interrupt raw register - */ -typedef union { - struct { - /** out_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. + uint32_t infifo_udf_l1_int_clr: 1; + /** infifo_ovf_l2_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. */ - uint32_t out_done_ch1_int_raw:1; - /** out_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. + uint32_t infifo_ovf_l2_int_clr: 1; + /** infifo_udf_l2_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. */ - uint32_t out_eof_ch1_int_raw:1; - /** out_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ - uint32_t out_dscr_err_ch1_int_raw:1; - /** out_total_eof_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ - uint32_t out_total_eof_ch1_int_raw:1; - /** outfifo_ovf_l1_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l1_ch1_int_raw:1; - /** outfifo_udf_l1_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l1_ch1_int_raw:1; - /** outfifo_ovf_l2_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l2_ch1_int_raw:1; - /** outfifo_udf_l2_ch1_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l2_ch1_int_raw:1; - /** out_dscr_task_ovf_ch1_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t out_dscr_task_ovf_ch1_int_raw:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_raw_ch1_reg_t; - -/** Type of out_int_ena_ch1 register - * TX CH1 interrupt ena register - */ -typedef union { - struct { - /** out_done_ch1_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch1_int_ena:1; - /** out_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch1_int_ena:1; - /** out_dscr_err_ch1_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch1_int_ena:1; - /** out_total_eof_ch1_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch1_int_ena:1; - /** outfifo_ovf_l1_ch1_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch1_int_ena:1; - /** outfifo_udf_l1_ch1_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch1_int_ena:1; - /** outfifo_ovf_l2_ch1_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch1_int_ena:1; - /** outfifo_udf_l2_ch1_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch1_int_ena:1; - /** out_dscr_task_ovf_ch1_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch1_int_ena:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_ena_ch1_reg_t; - -/** Type of out_int_st_ch1 register - * TX CH1 interrupt st register - */ -typedef union { - struct { - /** out_done_ch1_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch1_int_st:1; - /** out_eof_ch1_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch1_int_st:1; - /** out_dscr_err_ch1_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch1_int_st:1; - /** out_total_eof_ch1_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch1_int_st:1; - /** outfifo_ovf_l1_ch1_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch1_int_st:1; - /** outfifo_udf_l1_ch1_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch1_int_st:1; - /** outfifo_ovf_l2_ch1_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch1_int_st:1; - /** outfifo_udf_l2_ch1_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch1_int_st:1; - /** out_dscr_task_ovf_ch1_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch1_int_st:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_st_ch1_reg_t; - -/** Type of out_int_clr_ch1 register - * TX CH1 interrupt clr register - */ -typedef union { - struct { - /** out_done_ch1_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch1_int_clr:1; - /** out_eof_ch1_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch1_int_clr:1; - /** out_dscr_err_ch1_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch1_int_clr:1; - /** out_total_eof_ch1_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch1_int_clr:1; - /** outfifo_ovf_l1_ch1_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch1_int_clr:1; - /** outfifo_udf_l1_ch1_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch1_int_clr:1; - /** outfifo_ovf_l2_ch1_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch1_int_clr:1; - /** outfifo_udf_l2_ch1_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch1_int_clr:1; - /** out_dscr_task_ovf_ch1_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch1_int_clr:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_clr_ch1_reg_t; - -/** Type of out_int_raw_ch2 register - * TX CH2 interrupt raw register - */ -typedef union { - struct { - /** out_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ - uint32_t out_done_ch2_int_raw:1; - /** out_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ - uint32_t out_eof_ch2_int_raw:1; - /** out_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ - uint32_t out_dscr_err_ch2_int_raw:1; - /** out_total_eof_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ - uint32_t out_total_eof_ch2_int_raw:1; - /** outfifo_ovf_l1_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l1_ch2_int_raw:1; - /** outfifo_udf_l1_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l1_ch2_int_raw:1; - /** outfifo_ovf_l2_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l2_ch2_int_raw:1; - /** outfifo_udf_l2_ch2_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l2_ch2_int_raw:1; - /** out_dscr_task_ovf_ch2_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t out_dscr_task_ovf_ch2_int_raw:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_raw_ch2_reg_t; - -/** Type of out_int_ena_ch2 register - * TX CH2 interrupt ena register - */ -typedef union { - struct { - /** out_done_ch2_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch2_int_ena:1; - /** out_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch2_int_ena:1; - /** out_dscr_err_ch2_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch2_int_ena:1; - /** out_total_eof_ch2_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch2_int_ena:1; - /** outfifo_ovf_l1_ch2_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch2_int_ena:1; - /** outfifo_udf_l1_ch2_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch2_int_ena:1; - /** outfifo_ovf_l2_ch2_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch2_int_ena:1; - /** outfifo_udf_l2_ch2_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch2_int_ena:1; - /** out_dscr_task_ovf_ch2_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch2_int_ena:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_ena_ch2_reg_t; - -/** Type of out_int_st_ch2 register - * TX CH2 interrupt st register - */ -typedef union { - struct { - /** out_done_ch2_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch2_int_st:1; - /** out_eof_ch2_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch2_int_st:1; - /** out_dscr_err_ch2_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch2_int_st:1; - /** out_total_eof_ch2_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch2_int_st:1; - /** outfifo_ovf_l1_ch2_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch2_int_st:1; - /** outfifo_udf_l1_ch2_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch2_int_st:1; - /** outfifo_ovf_l2_ch2_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch2_int_st:1; - /** outfifo_udf_l2_ch2_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch2_int_st:1; - /** out_dscr_task_ovf_ch2_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch2_int_st:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_st_ch2_reg_t; - -/** Type of out_int_clr_ch2 register - * TX CH2 interrupt clr register - */ -typedef union { - struct { - /** out_done_ch2_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch2_int_clr:1; - /** out_eof_ch2_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch2_int_clr:1; - /** out_dscr_err_ch2_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch2_int_clr:1; - /** out_total_eof_ch2_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch2_int_clr:1; - /** outfifo_ovf_l1_ch2_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch2_int_clr:1; - /** outfifo_udf_l1_ch2_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch2_int_clr:1; - /** outfifo_ovf_l2_ch2_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch2_int_clr:1; - /** outfifo_udf_l2_ch2_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch2_int_clr:1; - /** out_dscr_task_ovf_ch2_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch2_int_clr:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_clr_ch2_reg_t; - -/** Type of out_int_raw_ch3 register - * TX CH3 interrupt raw register - */ -typedef union { - struct { - /** out_done_ch3_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ - uint32_t out_done_ch3_int_raw:1; - /** out_eof_ch3_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ - uint32_t out_eof_ch3_int_raw:1; - /** out_dscr_err_ch3_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ - uint32_t out_dscr_err_ch3_int_raw:1; - /** out_total_eof_ch3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ - uint32_t out_total_eof_ch3_int_raw:1; - /** outfifo_ovf_l1_ch3_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l1_ch3_int_raw:1; - /** outfifo_udf_l1_ch3_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l1_ch3_int_raw:1; - /** outfifo_ovf_l2_ch3_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l2_ch3_int_raw:1; - /** outfifo_udf_l2_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l2_ch3_int_raw:1; - /** out_dscr_task_ovf_ch3_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t out_dscr_task_ovf_ch3_int_raw:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_raw_ch3_reg_t; - -/** Type of out_int_ena_ch3 register - * TX CH3 interrupt ena register - */ -typedef union { - struct { - /** out_done_ch3_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch3_int_ena:1; - /** out_eof_ch3_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch3_int_ena:1; - /** out_dscr_err_ch3_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch3_int_ena:1; - /** out_total_eof_ch3_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch3_int_ena:1; - /** outfifo_ovf_l1_ch3_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch3_int_ena:1; - /** outfifo_udf_l1_ch3_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch3_int_ena:1; - /** outfifo_ovf_l2_ch3_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch3_int_ena:1; - /** outfifo_udf_l2_ch3_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch3_int_ena:1; - /** out_dscr_task_ovf_ch3_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch3_int_ena:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_ena_ch3_reg_t; - -/** Type of out_int_st_ch3 register - * TX CH3 interrupt st register - */ -typedef union { - struct { - /** out_done_ch3_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch3_int_st:1; - /** out_eof_ch3_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch3_int_st:1; - /** out_dscr_err_ch3_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch3_int_st:1; - /** out_total_eof_ch3_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch3_int_st:1; - /** outfifo_ovf_l1_ch3_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch3_int_st:1; - /** outfifo_udf_l1_ch3_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch3_int_st:1; - /** outfifo_ovf_l2_ch3_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch3_int_st:1; - /** outfifo_udf_l2_ch3_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch3_int_st:1; - /** out_dscr_task_ovf_ch3_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch3_int_st:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_st_ch3_reg_t; - -/** Type of out_int_clr_ch3 register - * TX CH3 interrupt clr register - */ -typedef union { - struct { - /** out_done_ch3_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch3_int_clr:1; - /** out_eof_ch3_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch3_int_clr:1; - /** out_dscr_err_ch3_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch3_int_clr:1; - /** out_total_eof_ch3_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch3_int_clr:1; - /** outfifo_ovf_l1_ch3_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch3_int_clr:1; - /** outfifo_udf_l1_ch3_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch3_int_clr:1; - /** outfifo_ovf_l2_ch3_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch3_int_clr:1; - /** outfifo_udf_l2_ch3_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch3_int_clr:1; - /** out_dscr_task_ovf_ch3_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch3_int_clr:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_clr_ch3_reg_t; - -/** Type of out_int_raw_ch4 register - * TX CH4 interrupt raw register - */ -typedef union { - struct { - /** out_done_ch4_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ - uint32_t out_done_ch4_int_raw:1; - /** out_eof_ch4_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ - uint32_t out_eof_ch4_int_raw:1; - /** out_dscr_err_ch4_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ - uint32_t out_dscr_err_ch4_int_raw:1; - /** out_total_eof_ch4_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ - uint32_t out_total_eof_ch4_int_raw:1; - /** outfifo_ovf_l1_ch4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l1_ch4_int_raw:1; - /** outfifo_udf_l1_ch4_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l1_ch4_int_raw:1; - /** outfifo_ovf_l2_ch4_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l2_ch4_int_raw:1; - /** outfifo_udf_l2_ch4_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l2_ch4_int_raw:1; - /** out_dscr_task_ovf_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t out_dscr_task_ovf_ch4_int_raw:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_raw_ch4_reg_t; - -/** Type of out_int_ena_ch4 register - * TX CH4 interrupt ena register - */ -typedef union { - struct { - /** out_done_ch4_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch4_int_ena:1; - /** out_eof_ch4_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch4_int_ena:1; - /** out_dscr_err_ch4_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch4_int_ena:1; - /** out_total_eof_ch4_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch4_int_ena:1; - /** outfifo_ovf_l1_ch4_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch4_int_ena:1; - /** outfifo_udf_l1_ch4_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch4_int_ena:1; - /** outfifo_ovf_l2_ch4_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch4_int_ena:1; - /** outfifo_udf_l2_ch4_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch4_int_ena:1; - /** out_dscr_task_ovf_ch4_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch4_int_ena:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_ena_ch4_reg_t; - -/** Type of out_int_st_ch4 register - * TX CH4 interrupt st register - */ -typedef union { - struct { - /** out_done_ch4_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch4_int_st:1; - /** out_eof_ch4_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch4_int_st:1; - /** out_dscr_err_ch4_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch4_int_st:1; - /** out_total_eof_ch4_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch4_int_st:1; - /** outfifo_ovf_l1_ch4_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch4_int_st:1; - /** outfifo_udf_l1_ch4_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch4_int_st:1; - /** outfifo_ovf_l2_ch4_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch4_int_st:1; - /** outfifo_udf_l2_ch4_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch4_int_st:1; - /** out_dscr_task_ovf_ch4_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch4_int_st:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_st_ch4_reg_t; - -/** Type of out_int_clr_ch4 register - * TX CH4 interrupt clr register - */ -typedef union { - struct { - /** out_done_ch4_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_ch4_int_clr:1; - /** out_eof_ch4_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_ch4_int_clr:1; - /** out_dscr_err_ch4_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_ch4_int_clr:1; - /** out_total_eof_ch4_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_ch4_int_clr:1; - /** outfifo_ovf_l1_ch4_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_ch4_int_clr:1; - /** outfifo_udf_l1_ch4_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_ch4_int_clr:1; - /** outfifo_ovf_l2_ch4_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_ch4_int_clr:1; - /** outfifo_udf_l2_ch4_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_ch4_int_clr:1; - /** out_dscr_task_ovf_ch4_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_ch4_int_clr:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_out_int_clr_ch4_reg_t; - -/** Type of in_int_raw_ch0 register - * RX CH0 interrupt raw register - */ -typedef union { - struct { - /** in_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 0. - */ - uint32_t in_done_ch0_int_raw:1; - /** in_suc_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 0. - */ - uint32_t in_suc_eof_ch0_int_raw:1; - /** in_err_eof_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ - uint32_t in_err_eof_ch0_int_raw:1; - /** in_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 0. - */ - uint32_t in_dscr_err_ch0_int_raw:1; - /** infifo_ovf_l1_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l1_ch0_int_raw:1; - /** infifo_udf_l1_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l1_ch0_int_raw:1; - /** infifo_ovf_l2_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l2_ch0_int_raw:1; - /** infifo_udf_l2_ch0_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l2_ch0_int_raw:1; - /** in_dscr_empty_ch0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ - uint32_t in_dscr_empty_ch0_int_raw:1; - /** in_dscr_task_ovf_ch0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t in_dscr_task_ovf_ch0_int_raw:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_raw_ch0_reg_t; - -/** Type of in_int_ena_ch0 register - * RX CH0 interrupt ena register - */ -typedef union { - struct { - /** in_done_ch0_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch0_int_ena:1; - /** in_suc_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch0_int_ena:1; - /** in_err_eof_ch0_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch0_int_ena:1; - /** in_dscr_err_ch0_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch0_int_ena:1; - /** infifo_ovf_l1_ch0_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch0_int_ena:1; - /** infifo_udf_l1_ch0_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch0_int_ena:1; - /** infifo_ovf_l2_ch0_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch0_int_ena:1; - /** infifo_udf_l2_ch0_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch0_int_ena:1; - /** in_dscr_empty_ch0_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch0_int_ena:1; - /** in_dscr_task_ovf_ch0_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch0_int_ena:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_ena_ch0_reg_t; - -/** Type of in_int_st_ch0 register - * RX CH0 interrupt st register - */ -typedef union { - struct { - /** in_done_ch0_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch0_int_st:1; - /** in_suc_eof_ch0_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch0_int_st:1; - /** in_err_eof_ch0_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch0_int_st:1; - /** in_dscr_err_ch0_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch0_int_st:1; - /** infifo_ovf_l1_ch0_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch0_int_st:1; - /** infifo_udf_l1_ch0_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch0_int_st:1; - /** infifo_ovf_l2_ch0_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch0_int_st:1; - /** infifo_udf_l2_ch0_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch0_int_st:1; - /** in_dscr_empty_ch0_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch0_int_st:1; - /** in_dscr_task_ovf_ch0_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch0_int_st:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_st_ch0_reg_t; - -/** Type of in_int_clr_ch0 register - * RX CH0 interrupt clr register - */ -typedef union { - struct { - /** in_done_ch0_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch0_int_clr:1; - /** in_suc_eof_ch0_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch0_int_clr:1; - /** in_err_eof_ch0_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch0_int_clr:1; - /** in_dscr_err_ch0_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch0_int_clr:1; - /** infifo_ovf_l1_ch0_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch0_int_clr:1; - /** infifo_udf_l1_ch0_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch0_int_clr:1; - /** infifo_ovf_l2_ch0_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch0_int_clr:1; - /** infifo_udf_l2_ch0_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch0_int_clr:1; - /** in_dscr_empty_ch0_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch0_int_clr:1; - /** in_dscr_task_ovf_ch0_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch0_int_clr:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_clr_ch0_reg_t; - -/** Type of in_int_raw_ch1 register - * RX CH1 interrupt raw register - */ -typedef union { - struct { - /** in_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 1. - */ - uint32_t in_done_ch1_int_raw:1; - /** in_suc_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 1. - */ - uint32_t in_suc_eof_ch1_int_raw:1; - /** in_err_eof_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ - uint32_t in_err_eof_ch1_int_raw:1; - /** in_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 1. - */ - uint32_t in_dscr_err_ch1_int_raw:1; - /** infifo_ovf_l1_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l1_ch1_int_raw:1; - /** infifo_udf_l1_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l1_ch1_int_raw:1; - /** infifo_ovf_l2_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l2_ch1_int_raw:1; - /** infifo_udf_l2_ch1_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l2_ch1_int_raw:1; - /** in_dscr_empty_ch1_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ - uint32_t in_dscr_empty_ch1_int_raw:1; - /** in_dscr_task_ovf_ch1_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t in_dscr_task_ovf_ch1_int_raw:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_raw_ch1_reg_t; - -/** Type of in_int_ena_ch1 register - * RX CH1 interrupt ena register - */ -typedef union { - struct { - /** in_done_ch1_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch1_int_ena:1; - /** in_suc_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch1_int_ena:1; - /** in_err_eof_ch1_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch1_int_ena:1; - /** in_dscr_err_ch1_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch1_int_ena:1; - /** infifo_ovf_l1_ch1_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch1_int_ena:1; - /** infifo_udf_l1_ch1_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch1_int_ena:1; - /** infifo_ovf_l2_ch1_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch1_int_ena:1; - /** infifo_udf_l2_ch1_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch1_int_ena:1; - /** in_dscr_empty_ch1_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch1_int_ena:1; - /** in_dscr_task_ovf_ch1_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch1_int_ena:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_ena_ch1_reg_t; - -/** Type of in_int_st_ch1 register - * RX CH1 interrupt st register - */ -typedef union { - struct { - /** in_done_ch1_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch1_int_st:1; - /** in_suc_eof_ch1_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch1_int_st:1; - /** in_err_eof_ch1_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch1_int_st:1; - /** in_dscr_err_ch1_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch1_int_st:1; - /** infifo_ovf_l1_ch1_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch1_int_st:1; - /** infifo_udf_l1_ch1_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch1_int_st:1; - /** infifo_ovf_l2_ch1_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch1_int_st:1; - /** infifo_udf_l2_ch1_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch1_int_st:1; - /** in_dscr_empty_ch1_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch1_int_st:1; - /** in_dscr_task_ovf_ch1_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch1_int_st:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_st_ch1_reg_t; - -/** Type of in_int_clr_ch1 register - * RX CH1 interrupt clr register - */ -typedef union { - struct { - /** in_done_ch1_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch1_int_clr:1; - /** in_suc_eof_ch1_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch1_int_clr:1; - /** in_err_eof_ch1_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch1_int_clr:1; - /** in_dscr_err_ch1_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch1_int_clr:1; - /** infifo_ovf_l1_ch1_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch1_int_clr:1; - /** infifo_udf_l1_ch1_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch1_int_clr:1; - /** infifo_ovf_l2_ch1_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch1_int_clr:1; - /** infifo_udf_l2_ch1_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch1_int_clr:1; - /** in_dscr_empty_ch1_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch1_int_clr:1; - /** in_dscr_task_ovf_ch1_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch1_int_clr:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_clr_ch1_reg_t; - -/** Type of in_int_raw_ch2 register - * RX CH2 interrupt raw register - */ -typedef union { - struct { - /** in_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 1. - */ - uint32_t in_done_ch2_int_raw:1; - /** in_suc_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 1. - */ - uint32_t in_suc_eof_ch2_int_raw:1; - /** in_err_eof_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ - uint32_t in_err_eof_ch2_int_raw:1; - /** in_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 1. - */ - uint32_t in_dscr_err_ch2_int_raw:1; - /** infifo_ovf_l1_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l1_ch2_int_raw:1; - /** infifo_udf_l1_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l1_ch2_int_raw:1; - /** infifo_ovf_l2_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l2_ch2_int_raw:1; - /** infifo_udf_l2_ch2_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l2_ch2_int_raw:1; - /** in_dscr_empty_ch2_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ - uint32_t in_dscr_empty_ch2_int_raw:1; - /** in_dscr_task_ovf_ch2_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t in_dscr_task_ovf_ch2_int_raw:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_raw_ch2_reg_t; - -/** Type of in_int_ena_ch2 register - * RX CH2 interrupt ena register - */ -typedef union { - struct { - /** in_done_ch2_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch2_int_ena:1; - /** in_suc_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch2_int_ena:1; - /** in_err_eof_ch2_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch2_int_ena:1; - /** in_dscr_err_ch2_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch2_int_ena:1; - /** infifo_ovf_l1_ch2_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch2_int_ena:1; - /** infifo_udf_l1_ch2_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch2_int_ena:1; - /** infifo_ovf_l2_ch2_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch2_int_ena:1; - /** infifo_udf_l2_ch2_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch2_int_ena:1; - /** in_dscr_empty_ch2_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch2_int_ena:1; - /** in_dscr_task_ovf_ch2_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch2_int_ena:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_ena_ch2_reg_t; - -/** Type of in_int_st_ch2 register - * RX CH2 interrupt st register - */ -typedef union { - struct { - /** in_done_ch2_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch2_int_st:1; - /** in_suc_eof_ch2_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch2_int_st:1; - /** in_err_eof_ch2_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch2_int_st:1; - /** in_dscr_err_ch2_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch2_int_st:1; - /** infifo_ovf_l1_ch2_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch2_int_st:1; - /** infifo_udf_l1_ch2_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch2_int_st:1; - /** infifo_ovf_l2_ch2_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch2_int_st:1; - /** infifo_udf_l2_ch2_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch2_int_st:1; - /** in_dscr_empty_ch2_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch2_int_st:1; - /** in_dscr_task_ovf_ch2_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch2_int_st:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_st_ch2_reg_t; - -/** Type of in_int_clr_ch2 register - * RX CH2 interrupt clr register - */ -typedef union { - struct { - /** in_done_ch2_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch2_int_clr:1; - /** in_suc_eof_ch2_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch2_int_clr:1; - /** in_err_eof_ch2_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch2_int_clr:1; - /** in_dscr_err_ch2_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch2_int_clr:1; - /** infifo_ovf_l1_ch2_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch2_int_clr:1; - /** infifo_udf_l1_ch2_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch2_int_clr:1; - /** infifo_ovf_l2_ch2_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch2_int_clr:1; - /** infifo_udf_l2_ch2_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch2_int_clr:1; - /** in_dscr_empty_ch2_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch2_int_clr:1; - /** in_dscr_task_ovf_ch2_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch2_int_clr:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_clr_ch2_reg_t; - -/** Type of in_int_raw_ch3 register - * RX CH3 interrupt raw register - */ -typedef union { - struct { - /** in_done_ch3_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 1. - */ - uint32_t in_done_ch3_int_raw:1; - /** in_suc_eof_ch3_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 1. - */ - uint32_t in_suc_eof_ch3_int_raw:1; - /** in_err_eof_ch3_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ - uint32_t in_err_eof_ch3_int_raw:1; - /** in_dscr_err_ch3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 1. - */ - uint32_t in_dscr_err_ch3_int_raw:1; - /** infifo_ovf_l1_ch3_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l1_ch3_int_raw:1; - /** infifo_udf_l1_ch3_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l1_ch3_int_raw:1; - /** infifo_ovf_l2_ch3_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l2_ch3_int_raw:1; - /** infifo_udf_l2_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l2_ch3_int_raw:1; - /** in_dscr_empty_ch3_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ - uint32_t in_dscr_empty_ch3_int_raw:1; - /** in_dscr_task_ovf_ch3_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t in_dscr_task_ovf_ch3_int_raw:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_raw_ch3_reg_t; - -/** Type of in_int_ena_ch3 register - * RX CH3 interrupt ena register - */ -typedef union { - struct { - /** in_done_ch3_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch3_int_ena:1; - /** in_suc_eof_ch3_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch3_int_ena:1; - /** in_err_eof_ch3_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch3_int_ena:1; - /** in_dscr_err_ch3_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch3_int_ena:1; - /** infifo_ovf_l1_ch3_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch3_int_ena:1; - /** infifo_udf_l1_ch3_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch3_int_ena:1; - /** infifo_ovf_l2_ch3_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch3_int_ena:1; - /** infifo_udf_l2_ch3_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch3_int_ena:1; - /** in_dscr_empty_ch3_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch3_int_ena:1; - /** in_dscr_task_ovf_ch3_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch3_int_ena:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_ena_ch3_reg_t; - -/** Type of in_int_st_ch3 register - * RX CH3 interrupt st register - */ -typedef union { - struct { - /** in_done_ch3_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch3_int_st:1; - /** in_suc_eof_ch3_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch3_int_st:1; - /** in_err_eof_ch3_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch3_int_st:1; - /** in_dscr_err_ch3_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch3_int_st:1; - /** infifo_ovf_l1_ch3_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch3_int_st:1; - /** infifo_udf_l1_ch3_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch3_int_st:1; - /** infifo_ovf_l2_ch3_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch3_int_st:1; - /** infifo_udf_l2_ch3_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch3_int_st:1; - /** in_dscr_empty_ch3_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch3_int_st:1; - /** in_dscr_task_ovf_ch3_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch3_int_st:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_st_ch3_reg_t; - -/** Type of in_int_clr_ch3 register - * RX CH3 interrupt clr register - */ -typedef union { - struct { - /** in_done_ch3_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch3_int_clr:1; - /** in_suc_eof_ch3_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch3_int_clr:1; - /** in_err_eof_ch3_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch3_int_clr:1; - /** in_dscr_err_ch3_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch3_int_clr:1; - /** infifo_ovf_l1_ch3_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch3_int_clr:1; - /** infifo_udf_l1_ch3_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch3_int_clr:1; - /** infifo_ovf_l2_ch3_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch3_int_clr:1; - /** infifo_udf_l2_ch3_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch3_int_clr:1; - /** in_dscr_empty_ch3_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch3_int_clr:1; - /** in_dscr_task_ovf_ch3_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch3_int_clr:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_clr_ch3_reg_t; - -/** Type of in_int_raw_ch4 register - * RX CH4 interrupt raw register - */ -typedef union { - struct { - /** in_done_ch4_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 1. - */ - uint32_t in_done_ch4_int_raw:1; - /** in_suc_eof_ch4_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 1. - */ - uint32_t in_suc_eof_ch4_int_raw:1; - /** in_err_eof_ch4_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ - uint32_t in_err_eof_ch4_int_raw:1; - /** in_dscr_err_ch4_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 1. - */ - uint32_t in_dscr_err_ch4_int_raw:1; - /** infifo_ovf_l1_ch4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l1_ch4_int_raw:1; - /** infifo_udf_l1_ch4_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l1_ch4_int_raw:1; - /** infifo_ovf_l2_ch4_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l2_ch4_int_raw:1; - /** infifo_udf_l2_ch4_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l2_ch4_int_raw:1; - /** in_dscr_empty_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ - uint32_t in_dscr_empty_ch4_int_raw:1; - /** in_dscr_task_ovf_ch4_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t in_dscr_task_ovf_ch4_int_raw:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_raw_ch4_reg_t; - -/** Type of in_int_ena_ch4 register - * RX CH4 interrupt ena register - */ -typedef union { - struct { - /** in_done_ch4_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch4_int_ena:1; - /** in_suc_eof_ch4_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch4_int_ena:1; - /** in_err_eof_ch4_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch4_int_ena:1; - /** in_dscr_err_ch4_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch4_int_ena:1; - /** infifo_ovf_l1_ch4_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch4_int_ena:1; - /** infifo_udf_l1_ch4_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch4_int_ena:1; - /** infifo_ovf_l2_ch4_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch4_int_ena:1; - /** infifo_udf_l2_ch4_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch4_int_ena:1; - /** in_dscr_empty_ch4_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch4_int_ena:1; - /** in_dscr_task_ovf_ch4_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch4_int_ena:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_ena_ch4_reg_t; - -/** Type of in_int_st_ch4 register - * RX CH4 interrupt st register - */ -typedef union { - struct { - /** in_done_ch4_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch4_int_st:1; - /** in_suc_eof_ch4_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch4_int_st:1; - /** in_err_eof_ch4_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch4_int_st:1; - /** in_dscr_err_ch4_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch4_int_st:1; - /** infifo_ovf_l1_ch4_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch4_int_st:1; - /** infifo_udf_l1_ch4_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch4_int_st:1; - /** infifo_ovf_l2_ch4_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch4_int_st:1; - /** infifo_udf_l2_ch4_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch4_int_st:1; - /** in_dscr_empty_ch4_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch4_int_st:1; - /** in_dscr_task_ovf_ch4_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch4_int_st:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_st_ch4_reg_t; - -/** Type of in_int_clr_ch4 register - * RX CH4 interrupt clr register - */ -typedef union { - struct { - /** in_done_ch4_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch4_int_clr:1; - /** in_suc_eof_ch4_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch4_int_clr:1; - /** in_err_eof_ch4_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_ch4_int_clr:1; - /** in_dscr_err_ch4_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_ch4_int_clr:1; - /** infifo_ovf_l1_ch4_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch4_int_clr:1; - /** infifo_udf_l1_ch4_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch4_int_clr:1; - /** infifo_ovf_l2_ch4_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_ch4_int_clr:1; - /** infifo_udf_l2_ch4_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_ch4_int_clr:1; - /** in_dscr_empty_ch4_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_ch4_int_clr:1; - /** in_dscr_task_ovf_ch4_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_ch4_int_clr:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_int_clr_ch4_reg_t; - -/** Type of in_int_raw_ch5 register - * RX CH5 interrupt raw register - */ -typedef union { - struct { - /** in_done_ch5_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 1. - */ - uint32_t in_done_ch5_int_raw:1; - /** in_suc_eof_ch5_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 1. - */ - uint32_t in_suc_eof_ch5_int_raw:1; - /** infifo_ovf_l1_ch5_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l1_ch5_int_raw:1; - /** infifo_udf_l1_ch5_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l1_ch5_int_raw:1; - /** fetch_mb_col_cnt_ovf_ch5_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t fetch_mb_col_cnt_ovf_ch5_int_raw:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} h264_dma_in_int_raw_ch5_reg_t; - -/** Type of in_int_ena_ch5 register - * RX CH5 interrupt ena register - */ -typedef union { - struct { - /** in_done_ch5_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch5_int_ena:1; - /** in_suc_eof_ch5_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch5_int_ena:1; - /** infifo_ovf_l1_ch5_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch5_int_ena:1; - /** infifo_udf_l1_ch5_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch5_int_ena:1; - /** fetch_mb_col_cnt_ovf_ch5_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t fetch_mb_col_cnt_ovf_ch5_int_ena:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} h264_dma_in_int_ena_ch5_reg_t; - -/** Type of in_int_st_ch5 register - * RX CH5 interrupt st register - */ -typedef union { - struct { - /** in_done_ch5_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch5_int_st:1; - /** in_suc_eof_ch5_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch5_int_st:1; - /** infifo_ovf_l1_ch5_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch5_int_st:1; - /** infifo_udf_l1_ch5_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch5_int_st:1; - /** fetch_mb_col_cnt_ovf_ch5_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t fetch_mb_col_cnt_ovf_ch5_int_st:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} h264_dma_in_int_st_ch5_reg_t; - -/** Type of in_int_clr_ch5 register - * RX CH5 interrupt clr register - */ -typedef union { - struct { - /** in_done_ch5_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_ch5_int_clr:1; - /** in_suc_eof_ch5_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_ch5_int_clr:1; - /** infifo_ovf_l1_ch5_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_ch5_int_clr:1; - /** infifo_udf_l1_ch5_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_ch5_int_clr:1; - /** fetch_mb_col_cnt_ovf_ch5_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t fetch_mb_col_cnt_ovf_ch5_int_clr:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} h264_dma_in_int_clr_ch5_reg_t; - - -/** Group: Status Registers */ -/** Type of outfifo_status_ch0 register - * TX CH0 outfifo status register - */ -typedef union { - struct { - /** outfifo_full_l2_ch0 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ - uint32_t outfifo_full_l2_ch0:1; - /** outfifo_empty_l2_ch0 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ - uint32_t outfifo_empty_l2_ch0:1; - /** outfifo_cnt_l2_ch0 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ - uint32_t outfifo_cnt_l2_ch0:4; - /** outfifo_full_l1_ch0 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ - uint32_t outfifo_full_l1_ch0:1; - /** outfifo_empty_l1_ch0 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ - uint32_t outfifo_empty_l1_ch0:1; - /** outfifo_cnt_l1_ch0 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ - uint32_t outfifo_cnt_l1_ch0:5; - uint32_t reserved_13:3; - /** outfifo_full_l3_ch0 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ - uint32_t outfifo_full_l3_ch0:1; - /** outfifo_empty_l3_ch0 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ - uint32_t outfifo_empty_l3_ch0:1; - /** outfifo_cnt_l3_ch0 : RO; bitpos: [19:18]; default: 0; - * The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. - */ - uint32_t outfifo_cnt_l3_ch0:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_outfifo_status_ch0_reg_t; - -/** Type of out_state_ch0 register - * TX CH0 state register - */ -typedef union { - struct { - /** outlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - uint32_t outlink_dscr_addr_ch0:18; - /** out_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t out_dscr_state_ch0:2; - /** out_state_ch0 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t out_state_ch0:4; - /** out_reset_avail_ch0 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t out_reset_avail_ch0:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} h264_dma_out_state_ch0_reg_t; - -/** Type of out_eof_des_addr_ch0 register - * TX CH0 eof des addr register - */ -typedef union { - struct { - /** out_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_ch0:32; - }; - uint32_t val; -} h264_dma_out_eof_des_addr_ch0_reg_t; - -/** Type of out_dscr_ch0 register - * TX CH0 next dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ - uint32_t outlink_dscr_ch0:32; - }; - uint32_t val; -} h264_dma_out_dscr_ch0_reg_t; - -/** Type of out_dscr_bf0_ch0 register - * TX CH0 last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ - uint32_t outlink_dscr_bf0_ch0:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf0_ch0_reg_t; - -/** Type of out_dscr_bf1_ch0 register - * TX CH0 second-to-last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ - uint32_t outlink_dscr_bf1_ch0:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf1_ch0_reg_t; - -/** Type of out_ro_status_ch0 register - * TX CH0 reorder status register - */ -typedef union { - struct { - /** outfifo_ro_cnt_ch0 : RO; bitpos: [1:0]; default: 0; - * The register stores the 8byte number of the data in reorder Tx FIFO for channel 0. - */ - uint32_t outfifo_ro_cnt_ch0:2; - uint32_t reserved_2:4; - /** out_ro_wr_state_ch0 : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ - uint32_t out_ro_wr_state_ch0:2; - /** out_ro_rd_state_ch0 : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ - uint32_t out_ro_rd_state_ch0:2; - /** out_pixel_byte_ch0 : RO; bitpos: [13:10]; default: 2; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ - uint32_t out_pixel_byte_ch0:4; - /** out_burst_block_num_ch0 : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ - uint32_t out_burst_block_num_ch0:4; - uint32_t reserved_18:14; - }; - uint32_t val; -} h264_dma_out_ro_status_ch0_reg_t; - -/** Type of outfifo_status_ch1 register - * TX CH1 outfifo status register - */ -typedef union { - struct { - /** outfifo_full_l2_ch1 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t outfifo_full_l2_ch1:1; - /** outfifo_empty_l2_ch1 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t outfifo_empty_l2_ch1:1; - /** outfifo_cnt_l2_ch1 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t outfifo_cnt_l2_ch1:4; - /** outfifo_full_l1_ch1 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t outfifo_full_l1_ch1:1; - /** outfifo_empty_l1_ch1 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t outfifo_empty_l1_ch1:1; - /** outfifo_cnt_l1_ch1 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t outfifo_cnt_l1_ch1:5; - uint32_t reserved_13:3; - /** outfifo_full_l3_ch1 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t outfifo_full_l3_ch1:1; - /** outfifo_empty_l3_ch1 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t outfifo_empty_l3_ch1:1; - /** outfifo_cnt_l3_ch1 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t outfifo_cnt_l3_ch1:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_outfifo_status_ch1_reg_t; - -/** Type of out_state_ch1 register - * TX CH1 state register - */ -typedef union { - struct { - /** outlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - uint32_t outlink_dscr_addr_ch1:18; - /** out_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t out_dscr_state_ch1:2; - /** out_state_ch1 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t out_state_ch1:4; - /** out_reset_avail_ch1 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t out_reset_avail_ch1:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} h264_dma_out_state_ch1_reg_t; - -/** Type of out_eof_des_addr_ch1 register - * TX CH1 eof des addr register - */ -typedef union { - struct { - /** out_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_ch1:32; - }; - uint32_t val; -} h264_dma_out_eof_des_addr_ch1_reg_t; - -/** Type of out_dscr_ch1 register - * TX CH1 next dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ - uint32_t outlink_dscr_ch1:32; - }; - uint32_t val; -} h264_dma_out_dscr_ch1_reg_t; - -/** Type of out_dscr_bf0_ch1 register - * TX CH1 last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ - uint32_t outlink_dscr_bf0_ch1:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf0_ch1_reg_t; - -/** Type of out_dscr_bf1_ch1 register - * TX CH1 second-to-last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ - uint32_t outlink_dscr_bf1_ch1:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf1_ch1_reg_t; - -/** Type of outfifo_status_ch2 register - * TX CH2 outfifo status register - */ -typedef union { - struct { - /** outfifo_full_l2_ch2 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l2_ch2:1; - /** outfifo_empty_l2_ch2 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l2_ch2:1; - /** outfifo_cnt_l2_ch2 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l2_ch2:4; - /** outfifo_full_l1_ch2 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l1_ch2:1; - /** outfifo_empty_l1_ch2 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l1_ch2:1; - /** outfifo_cnt_l1_ch2 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l1_ch2:5; - uint32_t reserved_13:3; - /** outfifo_full_l3_ch2 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l3_ch2:1; - /** outfifo_empty_l3_ch2 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l3_ch2:1; - /** outfifo_cnt_l3_ch2 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l3_ch2:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_outfifo_status_ch2_reg_t; - -/** Type of out_state_ch2 register - * TX CH2 state register - */ -typedef union { - struct { - /** outlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - uint32_t outlink_dscr_addr_ch2:18; - /** out_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t out_dscr_state_ch2:2; - /** out_state_ch2 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t out_state_ch2:4; - /** out_reset_avail_ch2 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t out_reset_avail_ch2:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} h264_dma_out_state_ch2_reg_t; - -/** Type of out_eof_des_addr_ch2 register - * TX CH2 eof des addr register - */ -typedef union { - struct { - /** out_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_ch2:32; - }; - uint32_t val; -} h264_dma_out_eof_des_addr_ch2_reg_t; - -/** Type of out_dscr_ch2 register - * TX CH2 next dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ - uint32_t outlink_dscr_ch2:32; - }; - uint32_t val; -} h264_dma_out_dscr_ch2_reg_t; - -/** Type of out_dscr_bf0_ch2 register - * TX CH2 last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ - uint32_t outlink_dscr_bf0_ch2:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf0_ch2_reg_t; - -/** Type of out_dscr_bf1_ch2 register - * TX CH2 second-to-last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ - uint32_t outlink_dscr_bf1_ch2:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf1_ch2_reg_t; - -/** Type of outfifo_status_ch3 register - * TX CH3 outfifo status register - */ -typedef union { - struct { - /** outfifo_full_l2_ch3 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l2_ch3:1; - /** outfifo_empty_l2_ch3 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l2_ch3:1; - /** outfifo_cnt_l2_ch3 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l2_ch3:4; - /** outfifo_full_l1_ch3 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l1_ch3:1; - /** outfifo_empty_l1_ch3 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l1_ch3:1; - /** outfifo_cnt_l1_ch3 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l1_ch3:5; - uint32_t reserved_13:3; - /** outfifo_full_l3_ch3 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l3_ch3:1; - /** outfifo_empty_l3_ch3 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l3_ch3:1; - /** outfifo_cnt_l3_ch3 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l3_ch3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_outfifo_status_ch3_reg_t; - -/** Type of out_state_ch3 register - * TX CH3 state register - */ -typedef union { - struct { - /** outlink_dscr_addr_ch3 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - uint32_t outlink_dscr_addr_ch3:18; - /** out_dscr_state_ch3 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t out_dscr_state_ch3:2; - /** out_state_ch3 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t out_state_ch3:4; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_out_state_ch3_reg_t; - -/** Type of out_eof_des_addr_ch3 register - * TX CH3 eof des addr register - */ -typedef union { - struct { - /** out_eof_des_addr_ch3 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_ch3:32; - }; - uint32_t val; -} h264_dma_out_eof_des_addr_ch3_reg_t; - -/** Type of out_dscr_ch3 register - * TX CH3 next dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_ch3 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ - uint32_t outlink_dscr_ch3:32; - }; - uint32_t val; -} h264_dma_out_dscr_ch3_reg_t; - -/** Type of out_dscr_bf0_ch3 register - * TX CH3 last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf0_ch3 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ - uint32_t outlink_dscr_bf0_ch3:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf0_ch3_reg_t; - -/** Type of out_dscr_bf1_ch3 register - * TX CH3 second-to-last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf1_ch3 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ - uint32_t outlink_dscr_bf1_ch3:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf1_ch3_reg_t; - -/** Type of outfifo_status_ch4 register - * TX CH4 outfifo status register - */ -typedef union { - struct { - /** outfifo_full_l2_ch4 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l2_ch4:1; - /** outfifo_empty_l2_ch4 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l2_ch4:1; - /** outfifo_cnt_l2_ch4 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l2_ch4:4; - /** outfifo_full_l1_ch4 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l1_ch4:1; - /** outfifo_empty_l1_ch4 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l1_ch4:1; - /** outfifo_cnt_l1_ch4 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l1_ch4:5; - uint32_t reserved_13:3; - /** outfifo_full_l3_ch4 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_l3_ch4:1; - /** outfifo_empty_l3_ch4 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_l3_ch4:1; - /** outfifo_cnt_l3_ch4 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_l3_ch4:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_outfifo_status_ch4_reg_t; - -/** Type of out_state_ch4 register - * TX CH4 state register - */ -typedef union { - struct { - /** outlink_dscr_addr_ch4 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - uint32_t outlink_dscr_addr_ch4:18; - /** out_dscr_state_ch4 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t out_dscr_state_ch4:2; - /** out_state_ch4 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t out_state_ch4:4; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_out_state_ch4_reg_t; - -/** Type of out_eof_des_addr_ch4 register - * TX CH4 eof des addr register - */ -typedef union { - struct { - /** out_eof_des_addr_ch4 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_ch4:32; - }; - uint32_t val; -} h264_dma_out_eof_des_addr_ch4_reg_t; - -/** Type of out_dscr_ch4 register - * TX CH4 next dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_ch4 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ - uint32_t outlink_dscr_ch4:32; - }; - uint32_t val; -} h264_dma_out_dscr_ch4_reg_t; - -/** Type of out_dscr_bf0_ch4 register - * TX CH4 last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf0_ch4 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ - uint32_t outlink_dscr_bf0_ch4:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf0_ch4_reg_t; - -/** Type of out_dscr_bf1_ch4 register - * TX CH4 second-to-last dscr addr register - */ -typedef union { - struct { - /** outlink_dscr_bf1_ch4 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ - uint32_t outlink_dscr_bf1_ch4:32; - }; - uint32_t val; -} h264_dma_out_dscr_bf1_ch4_reg_t; - -/** Type of infifo_status_ch0 register - * RX CH0 INFIFO status register - */ -typedef union { - struct { - /** infifo_full_l2_ch0 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ - uint32_t infifo_full_l2_ch0:1; - /** infifo_empty_l2_ch0 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ - uint32_t infifo_empty_l2_ch0:1; - /** infifo_cnt_l2_ch0 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ - uint32_t infifo_cnt_l2_ch0:4; - /** infifo_full_l1_ch0 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ - uint32_t infifo_full_l1_ch0:1; - /** infifo_empty_l1_ch0 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ - uint32_t infifo_empty_l1_ch0:1; - /** infifo_cnt_l1_ch0 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ - uint32_t infifo_cnt_l1_ch0:5; - uint32_t reserved_13:3; - /** infifo_full_l3_ch0 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ - uint32_t infifo_full_l3_ch0:1; - /** infifo_empty_l3_ch0 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ - uint32_t infifo_empty_l3_ch0:1; - /** infifo_cnt_l3_ch0 : RO; bitpos: [19:18]; default: 0; - * The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. - */ - uint32_t infifo_cnt_l3_ch0:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_infifo_status_ch0_reg_t; - -/** Type of in_state_ch0 register - * RX CH0 state register - */ -typedef union { - struct { - /** inlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - uint32_t inlink_dscr_addr_ch0:18; - /** in_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t in_dscr_state_ch0:2; - /** in_state_ch0 : RO; bitpos: [22:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t in_state_ch0:3; - /** in_reset_avail_ch0 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t in_reset_avail_ch0:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_in_state_ch0_reg_t; - -/** Type of in_suc_eof_des_addr_ch0 register - * RX CH0 eof des addr register - */ -typedef union { - struct { - /** in_suc_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_ch0:32; - }; - uint32_t val; -} h264_dma_in_suc_eof_des_addr_ch0_reg_t; - -/** Type of in_err_eof_des_addr_ch0 register - * RX CH0 err eof des addr register - */ -typedef union { - struct { - /** in_err_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ - uint32_t in_err_eof_des_addr_ch0:32; - }; - uint32_t val; -} h264_dma_in_err_eof_des_addr_ch0_reg_t; - -/** Type of in_dscr_ch0 register - * RX CH0 next dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ - uint32_t inlink_dscr_ch0:32; - }; - uint32_t val; -} h264_dma_in_dscr_ch0_reg_t; - -/** Type of in_dscr_bf0_ch0 register - * RX CH0 last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ - uint32_t inlink_dscr_bf0_ch0:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf0_ch0_reg_t; - -/** Type of in_dscr_bf1_ch0 register - * RX CH0 second-to-last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ - uint32_t inlink_dscr_bf1_ch0:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf1_ch0_reg_t; - -/** Type of infifo_status_ch1 register - * RX CH1 INFIFO status register - */ -typedef union { - struct { - /** infifo_full_l2_ch1 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ - uint32_t infifo_full_l2_ch1:1; - /** infifo_empty_l2_ch1 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ - uint32_t infifo_empty_l2_ch1:1; - /** infifo_cnt_l2_ch1 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ - uint32_t infifo_cnt_l2_ch1:4; - /** infifo_full_l1_ch1 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l1_ch1:1; - /** infifo_empty_l1_ch1 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l1_ch1:1; - /** infifo_cnt_l1_ch1 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l1_ch1:5; - uint32_t reserved_13:3; - /** infifo_full_l3_ch1 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l3_ch1:1; - /** infifo_empty_l3_ch1 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l3_ch1:1; - /** infifo_cnt_l3_ch1 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l3_ch1:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_infifo_status_ch1_reg_t; - -/** Type of in_state_ch1 register - * RX CH1 state register - */ -typedef union { - struct { - /** inlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - uint32_t inlink_dscr_addr_ch1:18; - /** in_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t in_dscr_state_ch1:2; - /** in_state_ch1 : RO; bitpos: [22:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t in_state_ch1:3; - /** in_reset_avail_ch1 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t in_reset_avail_ch1:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_in_state_ch1_reg_t; - -/** Type of in_suc_eof_des_addr_ch1 register - * RX CH1 eof des addr register - */ -typedef union { - struct { - /** in_suc_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_ch1:32; - }; - uint32_t val; -} h264_dma_in_suc_eof_des_addr_ch1_reg_t; - -/** Type of in_err_eof_des_addr_ch1 register - * RX CH1 err eof des addr register - */ -typedef union { - struct { - /** in_err_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ - uint32_t in_err_eof_des_addr_ch1:32; - }; - uint32_t val; -} h264_dma_in_err_eof_des_addr_ch1_reg_t; - -/** Type of in_dscr_ch1 register - * RX CH1 next dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ - uint32_t inlink_dscr_ch1:32; - }; - uint32_t val; -} h264_dma_in_dscr_ch1_reg_t; - -/** Type of in_dscr_bf0_ch1 register - * RX CH1 last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ - uint32_t inlink_dscr_bf0_ch1:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf0_ch1_reg_t; - -/** Type of in_dscr_bf1_ch1 register - * RX CH1 second-to-last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ - uint32_t inlink_dscr_bf1_ch1:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf1_ch1_reg_t; - -/** Type of infifo_status_ch2 register - * RX CH2 INFIFO status register - */ -typedef union { - struct { - /** infifo_full_l2_ch2 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ - uint32_t infifo_full_l2_ch2:1; - /** infifo_empty_l2_ch2 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ - uint32_t infifo_empty_l2_ch2:1; - /** infifo_cnt_l2_ch2 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ - uint32_t infifo_cnt_l2_ch2:4; - /** infifo_full_l1_ch2 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l1_ch2:1; - /** infifo_empty_l1_ch2 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l1_ch2:1; - /** infifo_cnt_l1_ch2 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l1_ch2:5; - uint32_t reserved_13:3; - /** infifo_full_l3_ch2 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l3_ch2:1; - /** infifo_empty_l3_ch2 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l3_ch2:1; - /** infifo_cnt_l3_ch2 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l3_ch2:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_infifo_status_ch2_reg_t; - -/** Type of in_state_ch2 register - * RX CH2 state register - */ -typedef union { - struct { - /** inlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - uint32_t inlink_dscr_addr_ch2:18; - /** in_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t in_dscr_state_ch2:2; - /** in_state_ch2 : RO; bitpos: [22:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t in_state_ch2:3; - /** in_reset_avail_ch2 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t in_reset_avail_ch2:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_in_state_ch2_reg_t; - -/** Type of in_suc_eof_des_addr_ch2 register - * RX CH2 eof des addr register - */ -typedef union { - struct { - /** in_suc_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_ch2:32; - }; - uint32_t val; -} h264_dma_in_suc_eof_des_addr_ch2_reg_t; - -/** Type of in_err_eof_des_addr_ch2 register - * RX CH2 err eof des addr register - */ -typedef union { - struct { - /** in_err_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ - uint32_t in_err_eof_des_addr_ch2:32; - }; - uint32_t val; -} h264_dma_in_err_eof_des_addr_ch2_reg_t; - -/** Type of in_dscr_ch2 register - * RX CH2 next dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ - uint32_t inlink_dscr_ch2:32; - }; - uint32_t val; -} h264_dma_in_dscr_ch2_reg_t; - -/** Type of in_dscr_bf0_ch2 register - * RX CH2 last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ - uint32_t inlink_dscr_bf0_ch2:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf0_ch2_reg_t; - -/** Type of in_dscr_bf1_ch2 register - * RX CH2 second-to-last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ - uint32_t inlink_dscr_bf1_ch2:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf1_ch2_reg_t; - -/** Type of infifo_status_ch3 register - * RX CH3 INFIFO status register - */ -typedef union { - struct { - /** infifo_full_l2_ch3 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ - uint32_t infifo_full_l2_ch3:1; - /** infifo_empty_l2_ch3 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ - uint32_t infifo_empty_l2_ch3:1; - /** infifo_cnt_l2_ch3 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ - uint32_t infifo_cnt_l2_ch3:4; - /** infifo_full_l1_ch3 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l1_ch3:1; - /** infifo_empty_l1_ch3 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l1_ch3:1; - /** infifo_cnt_l1_ch3 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l1_ch3:5; - uint32_t reserved_13:3; - /** infifo_full_l3_ch3 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l3_ch3:1; - /** infifo_empty_l3_ch3 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l3_ch3:1; - /** infifo_cnt_l3_ch3 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l3_ch3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_infifo_status_ch3_reg_t; - -/** Type of in_state_ch3 register - * RX CH3 state register - */ -typedef union { - struct { - /** inlink_dscr_addr_ch3 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - uint32_t inlink_dscr_addr_ch3:18; - /** in_dscr_state_ch3 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t in_dscr_state_ch3:2; - /** in_state_ch3 : RO; bitpos: [22:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t in_state_ch3:3; - /** in_reset_avail_ch3 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t in_reset_avail_ch3:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_in_state_ch3_reg_t; - -/** Type of in_suc_eof_des_addr_ch3 register - * RX CH3 eof des addr register - */ -typedef union { - struct { - /** in_suc_eof_des_addr_ch3 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_ch3:32; - }; - uint32_t val; -} h264_dma_in_suc_eof_des_addr_ch3_reg_t; - -/** Type of in_err_eof_des_addr_ch3 register - * RX CH3 err eof des addr register - */ -typedef union { - struct { - /** in_err_eof_des_addr_ch3 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ - uint32_t in_err_eof_des_addr_ch3:32; - }; - uint32_t val; -} h264_dma_in_err_eof_des_addr_ch3_reg_t; - -/** Type of in_dscr_ch3 register - * RX CH3 next dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_ch3 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ - uint32_t inlink_dscr_ch3:32; - }; - uint32_t val; -} h264_dma_in_dscr_ch3_reg_t; - -/** Type of in_dscr_bf0_ch3 register - * RX CH3 last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf0_ch3 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ - uint32_t inlink_dscr_bf0_ch3:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf0_ch3_reg_t; - -/** Type of in_dscr_bf1_ch3 register - * RX CH3 second-to-last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf1_ch3 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ - uint32_t inlink_dscr_bf1_ch3:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf1_ch3_reg_t; - -/** Type of infifo_status_ch4 register - * RX CH4 INFIFO status register - */ -typedef union { - struct { - /** infifo_full_l2_ch4 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ - uint32_t infifo_full_l2_ch4:1; - /** infifo_empty_l2_ch4 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ - uint32_t infifo_empty_l2_ch4:1; - /** infifo_cnt_l2_ch4 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ - uint32_t infifo_cnt_l2_ch4:4; - /** infifo_full_l1_ch4 : RO; bitpos: [6]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l1_ch4:1; - /** infifo_empty_l1_ch4 : RO; bitpos: [7]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l1_ch4:1; - /** infifo_cnt_l1_ch4 : RO; bitpos: [12:8]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l1_ch4:5; - uint32_t reserved_13:3; - /** infifo_full_l3_ch4 : RO; bitpos: [16]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l3_ch4:1; - /** infifo_empty_l3_ch4 : RO; bitpos: [17]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l3_ch4:1; - /** infifo_cnt_l3_ch4 : RO; bitpos: [19:18]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l3_ch4:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_dma_infifo_status_ch4_reg_t; - -/** Type of in_state_ch4 register - * RX CH4 state register - */ -typedef union { - struct { - /** inlink_dscr_addr_ch4 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - uint32_t inlink_dscr_addr_ch4:18; - /** in_dscr_state_ch4 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t in_dscr_state_ch4:2; - /** in_state_ch4 : RO; bitpos: [22:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t in_state_ch4:3; - /** in_reset_avail_ch4 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t in_reset_avail_ch4:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_in_state_ch4_reg_t; - -/** Type of in_suc_eof_des_addr_ch4 register - * RX CH4 eof des addr register - */ -typedef union { - struct { - /** in_suc_eof_des_addr_ch4 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_ch4:32; - }; - uint32_t val; -} h264_dma_in_suc_eof_des_addr_ch4_reg_t; - -/** Type of in_err_eof_des_addr_ch4 register - * RX CH4 err eof des addr register - */ -typedef union { - struct { - /** in_err_eof_des_addr_ch4 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ - uint32_t in_err_eof_des_addr_ch4:32; - }; - uint32_t val; -} h264_dma_in_err_eof_des_addr_ch4_reg_t; - -/** Type of in_dscr_ch4 register - * RX CH4 next dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_ch4 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ - uint32_t inlink_dscr_ch4:32; - }; - uint32_t val; -} h264_dma_in_dscr_ch4_reg_t; - -/** Type of in_dscr_bf0_ch4 register - * RX CH4 last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf0_ch4 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ - uint32_t inlink_dscr_bf0_ch4:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf0_ch4_reg_t; - -/** Type of in_dscr_bf1_ch4 register - * RX CH4 second-to-last dscr addr register - */ -typedef union { - struct { - /** inlink_dscr_bf1_ch4 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ - uint32_t inlink_dscr_bf1_ch4:32; - }; - uint32_t val; -} h264_dma_in_dscr_bf1_ch4_reg_t; - -/** Type of infifo_status_ch5 register - * RX CH5 INFIFO status register - */ -typedef union { - struct { - /** infifo_full_l1_ch5 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 1. - */ - uint32_t infifo_full_l1_ch5:1; - /** infifo_empty_l1_ch5 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 1. - */ - uint32_t infifo_empty_l1_ch5:1; - /** infifo_cnt_l1_ch5 : RO; bitpos: [6:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 1. - */ - uint32_t infifo_cnt_l1_ch5:5; - uint32_t reserved_7:25; - }; - uint32_t val; -} h264_dma_infifo_status_ch5_reg_t; - -/** Type of in_state_ch5 register - * RX CH5 state register - */ -typedef union { - struct { - /** in_state_ch5 : RO; bitpos: [2:0]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t in_state_ch5:3; - /** in_reset_avail_ch5 : RO; bitpos: [3]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t in_reset_avail_ch5:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} h264_dma_in_state_ch5_reg_t; - - -/** Group: out_link addr register */ -/** Type of out_link_addr_ch0 register - * TX CH0 out_link dscr addr register - */ -typedef union { - struct { - /** outlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ - uint32_t outlink_addr_ch0:32; - }; - uint32_t val; -} h264_dma_out_link_addr_ch0_reg_t; - - -/** Group: tx ch0 arb register */ -/** Type of out_arb_ch0 register - * TX CH0 arb register - */ -typedef union { - struct { - /** out_arb_token_num_ch0 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t out_arb_token_num_ch0:4; - /** exter_out_arb_priority_ch0 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ - uint32_t exter_out_arb_priority_ch0:2; - uint32_t reserved_6:26; - }; - uint32_t val; -} h264_dma_out_arb_ch0_reg_t; - - -/** Group: TX CH0 test mode register */ -/** Type of out_mode_enable_ch0 register - * tx CH0 mode enable register - */ -typedef union { - struct { - /** out_test_mode_enable_ch0 : R/W; bitpos: [0]; default: 0; - * tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test - * mode - */ - uint32_t out_test_mode_enable_ch0:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} h264_dma_out_mode_enable_ch0_reg_t; - -/** Type of out_mode_yuv_ch0 register - * tx CH0 test mode yuv value register - */ -typedef union { - struct { - /** out_test_y_value_ch0 : R/W; bitpos: [7:0]; default: 0; - * tx CH0 test mode y value - */ - uint32_t out_test_y_value_ch0:8; - /** out_test_u_value_ch0 : R/W; bitpos: [15:8]; default: 0; - * tx CH0 test mode u value - */ - uint32_t out_test_u_value_ch0:8; - /** out_test_v_value_ch0 : R/W; bitpos: [23:16]; default: 0; - * tx CH0 test mode v value - */ - uint32_t out_test_v_value_ch0:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_dma_out_mode_yuv_ch0_reg_t; - - -/** Group: ETM config register */ -/** Type of out_etm_conf_ch0 register - * TX CH0 ETM config register - */ -typedef union { - struct { - /** out_etm_en_ch0 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function - */ - uint32_t out_etm_en_ch0:1; - /** out_etm_loop_en_ch0 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task - */ - uint32_t out_etm_loop_en_ch0:1; - /** out_dscr_task_mak_ch0 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers - */ - uint32_t out_dscr_task_mak_ch0:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} h264_dma_out_etm_conf_ch0_reg_t; - - -/** Group: TX CH0 debug info */ -/** Type of out_buf_len_ch0 register - * tx CH0 buf len register - */ -typedef union { - struct { - /** out_cmdfifo_buf_len_hb_ch0 : RO; bitpos: [27:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_buf_len_hb_ch0:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} h264_dma_out_buf_len_ch0_reg_t; - -/** Type of out_fifo_bcnt_ch0 register - * tx CH0 fifo byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_outfifo_bcnt_ch0 : RO; bitpos: [9:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_outfifo_bcnt_ch0:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_out_fifo_bcnt_ch0_reg_t; - -/** Type of out_push_bytecnt_ch0 register - * tx CH0 push byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_push_bytecnt_ch0 : RO; bitpos: [7:0]; default: 255; - * only for debug - */ - uint32_t out_cmdfifo_push_bytecnt_ch0:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} h264_dma_out_push_bytecnt_ch0_reg_t; - -/** Type of out_xaddr_ch0 register - * tx CH0 xaddr register - */ -typedef union { - struct { - /** out_cmdfifo_xaddr_ch0 : RO; bitpos: [31:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_xaddr_ch0:32; - }; - uint32_t val; -} h264_dma_out_xaddr_ch0_reg_t; - - -/** Group: TX CH1 config0 register */ -/** Type of out_conf0_ch1 register - * TX CH1 config0 register - */ -typedef union { - struct { - /** out_auto_wrback_ch1 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ - uint32_t out_auto_wrback_ch1:1; - /** out_eof_mode_ch1 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ - uint32_t out_eof_mode_ch1:1; - /** outdscr_burst_en_ch1 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t outdscr_burst_en_ch1:1; - /** out_ecc_aes_en_ch1 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t out_ecc_aes_en_ch1:1; - /** out_check_owner_ch1 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t out_check_owner_ch1:1; - uint32_t reserved_5:1; - /** out_mem_burst_length_ch1 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 64 bytes - */ - uint32_t out_mem_burst_length_ch1:3; - uint32_t reserved_9:3; - /** out_page_bound_en_ch1 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ - uint32_t out_page_bound_en_ch1:1; - uint32_t reserved_13:11; - /** out_rst_ch1 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ - uint32_t out_rst_ch1:1; - /** out_cmd_disable_ch1 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t out_cmd_disable_ch1:1; - /** out_arb_weight_opt_dis_ch1 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t out_arb_weight_opt_dis_ch1:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} h264_dma_out_conf0_ch1_reg_t; - - -/** Group: TX CH1 out_link dscr addr register */ -/** Type of out_link_addr_ch1 register - * TX CH1 out_link dscr addr register - */ -typedef union { - struct { - /** outlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ - uint32_t outlink_addr_ch1:32; - }; - uint32_t val; -} h264_dma_out_link_addr_ch1_reg_t; - - -/** Group: TX CH1 arb register */ -/** Type of out_arb_ch1 register - * TX CH1 arb register - */ -typedef union { - struct { - /** out_arb_token_num_ch1 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t out_arb_token_num_ch1:4; - uint32_t reserved_4:2; - /** inter_out_arb_priority_ch1 : R/W; bitpos: [6]; default: 1; - * Set the priority of channel - */ - uint32_t inter_out_arb_priority_ch1:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} h264_dma_out_arb_ch1_reg_t; - - -/** Group: TX CH1 ETM config register */ -/** Type of out_etm_conf_ch1 register - * TX CH1 ETM config register - */ -typedef union { - struct { - /** out_etm_en_ch1 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function - */ - uint32_t out_etm_en_ch1:1; - /** out_etm_loop_en_ch1 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task - */ - uint32_t out_etm_loop_en_ch1:1; - /** out_dscr_task_mak_ch1 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers - */ - uint32_t out_dscr_task_mak_ch1:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} h264_dma_out_etm_conf_ch1_reg_t; - - -/** Group: TX CH1 debug info */ -/** Type of out_buf_len_ch1 register - * tx CH1 buf len register - */ -typedef union { - struct { - /** out_cmdfifo_buf_len_hb_ch1 : RO; bitpos: [27:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_buf_len_hb_ch1:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} h264_dma_out_buf_len_ch1_reg_t; - -/** Type of out_fifo_bcnt_ch1 register - * tx CH1 fifo byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_outfifo_bcnt_ch1 : RO; bitpos: [9:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_outfifo_bcnt_ch1:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_out_fifo_bcnt_ch1_reg_t; - -/** Type of out_push_bytecnt_ch1 register - * tx CH1 push byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_push_bytecnt_ch1 : RO; bitpos: [7:0]; default: 255; - * only for debug - */ - uint32_t out_cmdfifo_push_bytecnt_ch1:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} h264_dma_out_push_bytecnt_ch1_reg_t; - -/** Type of out_xaddr_ch1 register - * tx CH1 xaddr register - */ -typedef union { - struct { - /** out_cmdfifo_xaddr_ch1 : RO; bitpos: [31:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_xaddr_ch1:32; - }; - uint32_t val; -} h264_dma_out_xaddr_ch1_reg_t; - - -/** Group: TX CH2 config0 register */ -/** Type of out_conf0_ch2 register - * TX CH2 config0 register - */ -typedef union { - struct { - /** out_auto_wrback_ch2 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ - uint32_t out_auto_wrback_ch2:1; - /** out_eof_mode_ch2 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ - uint32_t out_eof_mode_ch2:1; - /** outdscr_burst_en_ch2 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t outdscr_burst_en_ch2:1; - /** out_ecc_aes_en_ch2 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t out_ecc_aes_en_ch2:1; - /** out_check_owner_ch2 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t out_check_owner_ch2:1; - uint32_t reserved_5:1; - /** out_mem_burst_length_ch2 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t out_mem_burst_length_ch2:3; - uint32_t reserved_9:3; - /** out_page_bound_en_ch2 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ - uint32_t out_page_bound_en_ch2:1; - uint32_t reserved_13:11; - /** out_rst_ch2 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ - uint32_t out_rst_ch2:1; - /** out_cmd_disable_ch2 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t out_cmd_disable_ch2:1; - /** out_arb_weight_opt_dis_ch2 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t out_arb_weight_opt_dis_ch2:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} h264_dma_out_conf0_ch2_reg_t; - - -/** Group: TX CH2 out_link dscr addr register */ -/** Type of out_link_addr_ch2 register - * TX CH2 out_link dscr addr register - */ -typedef union { - struct { - /** outlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ - uint32_t outlink_addr_ch2:32; - }; - uint32_t val; -} h264_dma_out_link_addr_ch2_reg_t; - - -/** Group: TX CH2 arb register */ -/** Type of out_arb_ch2 register - * TX CH2 arb register - */ -typedef union { - struct { - /** out_arb_token_num_ch2 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t out_arb_token_num_ch2:4; - uint32_t reserved_4:2; - /** inter_out_arb_priority_ch2 : R/W; bitpos: [6]; default: 1; - * Set the priority of channel - */ - uint32_t inter_out_arb_priority_ch2:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} h264_dma_out_arb_ch2_reg_t; - - -/** Group: TX CH2 ETM config register */ -/** Type of out_etm_conf_ch2 register - * TX CH2 ETM config register - */ -typedef union { - struct { - /** out_etm_en_ch2 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function - */ - uint32_t out_etm_en_ch2:1; - /** out_etm_loop_en_ch2 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task - */ - uint32_t out_etm_loop_en_ch2:1; - /** out_dscr_task_mak_ch2 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers - */ - uint32_t out_dscr_task_mak_ch2:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} h264_dma_out_etm_conf_ch2_reg_t; - - -/** Group: TX CH2 debug info */ -/** Type of out_buf_len_ch2 register - * tx CH2 buf len register - */ -typedef union { - struct { - /** out_cmdfifo_buf_len_hb_ch2 : RO; bitpos: [27:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_buf_len_hb_ch2:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} h264_dma_out_buf_len_ch2_reg_t; - -/** Type of out_fifo_bcnt_ch2 register - * tx CH2 fifo byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_outfifo_bcnt_ch2 : RO; bitpos: [9:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_outfifo_bcnt_ch2:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_out_fifo_bcnt_ch2_reg_t; - -/** Type of out_push_bytecnt_ch2 register - * tx CH2 push byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_push_bytecnt_ch2 : RO; bitpos: [7:0]; default: 255; - * only for debug - */ - uint32_t out_cmdfifo_push_bytecnt_ch2:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} h264_dma_out_push_bytecnt_ch2_reg_t; - -/** Type of out_xaddr_ch2 register - * tx CH2 xaddr register - */ -typedef union { - struct { - /** out_cmdfifo_xaddr_ch2 : RO; bitpos: [31:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_xaddr_ch2:32; - }; - uint32_t val; -} h264_dma_out_xaddr_ch2_reg_t; - - -/** Group: TX CH3 config0 register */ -/** Type of out_conf0_ch3 register - * TX CH3 config0 register - */ -typedef union { - struct { - /** out_auto_wrback_ch3 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ - uint32_t out_auto_wrback_ch3:1; - /** out_eof_mode_ch3 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ - uint32_t out_eof_mode_ch3:1; - /** outdscr_burst_en_ch3 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t outdscr_burst_en_ch3:1; - /** out_ecc_aes_en_ch3 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t out_ecc_aes_en_ch3:1; - /** out_check_owner_ch3 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t out_check_owner_ch3:1; - uint32_t reserved_5:1; - /** out_mem_burst_length_ch3 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t out_mem_burst_length_ch3:3; - uint32_t reserved_9:3; - /** out_page_bound_en_ch3 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ - uint32_t out_page_bound_en_ch3:1; - uint32_t reserved_13:13; - /** out_arb_weight_opt_dis_ch3 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t out_arb_weight_opt_dis_ch3:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} h264_dma_out_conf0_ch3_reg_t; - - -/** Group: TX CH3 out_link dscr addr register */ -/** Type of out_link_addr_ch3 register - * TX CH3 out_link dscr addr register - */ -typedef union { - struct { - /** outlink_addr_ch3 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ - uint32_t outlink_addr_ch3:32; - }; - uint32_t val; -} h264_dma_out_link_addr_ch3_reg_t; - - -/** Group: TX CH3 arb register */ -/** Type of out_arb_ch3 register - * TX CH3 arb register - */ -typedef union { - struct { - /** out_arb_token_num_ch3 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t out_arb_token_num_ch3:4; - /** exter_out_arb_priority_ch3 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ - uint32_t exter_out_arb_priority_ch3:2; - uint32_t reserved_6:26; - }; - uint32_t val; -} h264_dma_out_arb_ch3_reg_t; - - -/** Group: TX CH3 ETM config register */ -/** Type of out_etm_conf_ch3 register - * TX CH3 ETM config register - */ -typedef union { - struct { - /** out_etm_en_ch3 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function - */ - uint32_t out_etm_en_ch3:1; - /** out_etm_loop_en_ch3 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task - */ - uint32_t out_etm_loop_en_ch3:1; - /** out_dscr_task_mak_ch3 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers - */ - uint32_t out_dscr_task_mak_ch3:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} h264_dma_out_etm_conf_ch3_reg_t; - - -/** Group: TX CH3 debug info */ -/** Type of out_buf_len_ch3 register - * tx CH3 buf len register - */ -typedef union { - struct { - /** out_cmdfifo_buf_len_hb_ch3 : RO; bitpos: [27:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_buf_len_hb_ch3:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} h264_dma_out_buf_len_ch3_reg_t; - -/** Type of out_fifo_bcnt_ch3 register - * tx CH3 fifo byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_outfifo_bcnt_ch3 : RO; bitpos: [9:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_outfifo_bcnt_ch3:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_out_fifo_bcnt_ch3_reg_t; - -/** Type of out_push_bytecnt_ch3 register - * tx CH3 push byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_push_bytecnt_ch3 : RO; bitpos: [7:0]; default: 63; - * only for debug - */ - uint32_t out_cmdfifo_push_bytecnt_ch3:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} h264_dma_out_push_bytecnt_ch3_reg_t; - -/** Type of out_xaddr_ch3 register - * tx CH3 xaddr register - */ -typedef union { - struct { - /** out_cmdfifo_xaddr_ch3 : RO; bitpos: [31:0]; default: 0; - * only for debug - */ - uint32_t out_cmdfifo_xaddr_ch3:32; - }; - uint32_t val; -} h264_dma_out_xaddr_ch3_reg_t; - -/** Type of out_block_buf_len_ch3 register - * tx CH3 block buf len register - */ -typedef union { - struct { - /** out_block_buf_len_ch3 : RO; bitpos: [27:0]; default: 0; - * only for debug - */ - uint32_t out_block_buf_len_ch3:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} h264_dma_out_block_buf_len_ch3_reg_t; - - -/** Group: TX CH4 config0 register */ -/** Type of out_conf0_ch4 register - * TX CH4 config0 register - */ -typedef union { - struct { - /** out_auto_wrback_ch4 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ - uint32_t out_auto_wrback_ch4:1; - /** out_eof_mode_ch4 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ - uint32_t out_eof_mode_ch4:1; - /** outdscr_burst_en_ch4 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t outdscr_burst_en_ch4:1; - /** out_ecc_aes_en_ch4 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t out_ecc_aes_en_ch4:1; - /** out_check_owner_ch4 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t out_check_owner_ch4:1; - uint32_t reserved_5:1; - /** out_mem_burst_length_ch4 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 4. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t out_mem_burst_length_ch4:3; - uint32_t reserved_9:3; - /** out_page_bound_en_ch4 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ - uint32_t out_page_bound_en_ch4:1; - uint32_t reserved_13:13; - /** out_arb_weight_opt_dis_ch4 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t out_arb_weight_opt_dis_ch4:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} h264_dma_out_conf0_ch4_reg_t; - - -/** Group: TX CH4 out_link dscr addr register */ -/** Type of out_link_addr_ch4 register - * TX CH4 out_link dscr addr register - */ -typedef union { - struct { - /** outlink_addr_ch4 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ - uint32_t outlink_addr_ch4:32; - }; - uint32_t val; -} h264_dma_out_link_addr_ch4_reg_t; - - -/** Group: TX CH4 arb register */ -/** Type of out_arb_ch4 register - * TX CH4 arb register - */ -typedef union { - struct { - /** out_arb_token_num_ch4 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t out_arb_token_num_ch4:4; - /** exter_out_arb_priority_ch4 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ - uint32_t exter_out_arb_priority_ch4:2; - uint32_t reserved_6:26; - }; - uint32_t val; -} h264_dma_out_arb_ch4_reg_t; - - -/** Group: TX CH4 ETM config register */ -/** Type of out_etm_conf_ch4 register - * TX CH4 ETM config register - */ -typedef union { - struct { - /** out_etm_en_ch4 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function - */ - uint32_t out_etm_en_ch4:1; - /** out_etm_loop_en_ch4 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task + uint32_t infifo_udf_l2_int_clr: 1; + /** in_dscr_empty_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ - uint32_t out_etm_loop_en_ch4:1; - /** out_dscr_task_mak_ch4 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers + uint32_t in_dscr_empty_int_clr: 1; + /** in_dscr_task_ovf_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t out_dscr_task_mak_ch4:2; - uint32_t reserved_4:28; + uint32_t in_dscr_task_ovf_int_clr: 1; + uint32_t reserved_10: 22; }; uint32_t val; -} h264_dma_out_etm_conf_ch4_reg_t; +} h264_dma_in_int_clr_chn_reg_t; -/** Group: TX CH4 debug info */ -/** Type of out_buf_len_ch4 register - * tx CH4 buf len register +/** Type of in_int_raw_ch5 register + * RX CH5 interrupt raw register */ typedef union { struct { - /** out_cmdfifo_buf_len_hb_ch4 : RO; bitpos: [27:0]; default: 0; - * only for debug + /** in_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been transmitted to peripherals for Rx channel 1. */ - uint32_t out_cmdfifo_buf_len_hb_ch4:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} h264_dma_out_buf_len_ch4_reg_t; - -/** Type of out_fifo_bcnt_ch4 register - * tx CH4 fifo byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_outfifo_bcnt_ch4 : RO; bitpos: [9:0]; default: 0; - * only for debug + uint32_t in_done_int_raw: 1; + /** in_suc_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received and no data error is detected for Rx channel 1. */ - uint32_t out_cmdfifo_outfifo_bcnt_ch4:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_out_fifo_bcnt_ch4_reg_t; - -/** Type of out_push_bytecnt_ch4 register - * tx CH4 push byte cnt register - */ -typedef union { - struct { - /** out_cmdfifo_push_bytecnt_ch4 : RO; bitpos: [7:0]; default: 63; - * only for debug + uint32_t in_suc_eof_int_raw: 1; + /** infifo_ovf_l1_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * This raw interrupt bit turns to high level when fifo of Rx channel is overflow. */ - uint32_t out_cmdfifo_push_bytecnt_ch4:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} h264_dma_out_push_bytecnt_ch4_reg_t; - -/** Type of out_xaddr_ch4 register - * tx CH4 xaddr register - */ -typedef union { - struct { - /** out_cmdfifo_xaddr_ch4 : RO; bitpos: [31:0]; default: 0; - * only for debug + uint32_t infifo_ovf_l1_int_raw: 1; + /** infifo_udf_l1_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + */ + uint32_t infifo_udf_l1_int_raw: 1; + /** fetch_mb_col_cnt_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when fifo of Rx channel is underflow. */ - uint32_t out_cmdfifo_xaddr_ch4:32; + uint32_t fetch_mb_col_cnt_ovf_int_raw: 1; + uint32_t reserved_5: 27; }; uint32_t val; -} h264_dma_out_xaddr_ch4_reg_t; +} h264_dma_in_int_raw_ch5_reg_t; -/** Type of out_block_buf_len_ch4 register - * tx CH4 block buf len register +/** Type of in_int_ena_ch5 register + * RX CH5 interrupt ena register */ typedef union { struct { - /** out_block_buf_len_ch4 : RO; bitpos: [27:0]; default: 0; - * only for debug + /** in_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_int_ena: 1; + /** in_suc_eof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_int_ena: 1; + /** infifo_ovf_l1_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_l1_int_ena: 1; + /** infifo_udf_l1_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_l1_int_ena: 1; + /** fetch_mb_col_cnt_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t out_block_buf_len_ch4:28; - uint32_t reserved_28:4; + uint32_t fetch_mb_col_cnt_ovf_int_ena: 1; + uint32_t reserved_5: 27; }; uint32_t val; -} h264_dma_out_block_buf_len_ch4_reg_t; - +} h264_dma_in_int_ena_ch5_reg_t; -/** Group: RX CH0 in_link dscr addr register */ -/** Type of in_link_addr_ch0 register - * RX CH0 in_link dscr addr register +/** Type of in_int_st_ch5 register + * RX CH5 interrupt st register */ typedef union { struct { - /** inlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. + /** in_done_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_int_st: 1; + /** in_suc_eof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_int_st: 1; + /** infifo_ovf_l1_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_l1_int_st: 1; + /** infifo_udf_l1_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_l1_int_st: 1; + /** fetch_mb_col_cnt_ovf_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t inlink_addr_ch0:32; + uint32_t fetch_mb_col_cnt_ovf_int_st: 1; + uint32_t reserved_5: 27; }; uint32_t val; -} h264_dma_in_link_addr_ch0_reg_t; - +} h264_dma_in_int_st_ch5_reg_t; -/** Group: RX CH0 arb register */ -/** Type of in_arb_ch0 register - * RX CH0 arb register +/** Type of in_int_clr_ch5 register + * RX CH5 interrupt clr register */ typedef union { struct { - /** in_arb_token_num_ch0 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter + /** in_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. */ - uint32_t in_arb_token_num_ch0:4; - /** exter_in_arb_priority_ch0 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel + uint32_t in_done_int_clr: 1; + /** in_suc_eof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ - uint32_t exter_in_arb_priority_ch0:2; - /** inter_in_arb_priority_ch0 : R/W; bitpos: [8:6]; default: 1; - * Set the priority of channel + uint32_t in_suc_eof_int_clr: 1; + /** infifo_ovf_l1_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_l1_int_clr: 1; + /** infifo_udf_l1_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_l1_int_clr: 1; + /** fetch_mb_col_cnt_ovf_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t inter_in_arb_priority_ch0:3; - uint32_t reserved_9:23; + uint32_t fetch_mb_col_cnt_ovf_int_clr: 1; + uint32_t reserved_5: 27; }; uint32_t val; -} h264_dma_in_arb_ch0_reg_t; +} h264_dma_in_int_clr_ch5_reg_t; -/** Group: RX CH0 ETM config register */ -/** Type of in_etm_conf_ch0 register - * RX CH0 ETM config register +/** Type of outfifo_status register + * TX CHn outfifo status register */ typedef union { struct { - /** in_etm_en_ch0 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function + /** outfifo_full_l2 : RO; bitpos: [0]; default: 0; + * Tx FIFO full signal for Tx channel 2. */ - uint32_t in_etm_en_ch0:1; - /** in_etm_loop_en_ch0 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task + uint32_t outfifo_full_l2: 1; + /** outfifo_empty_l2 : RO; bitpos: [1]; default: 1; + * Tx FIFO empty signal for Tx channel 2. */ - uint32_t in_etm_loop_en_ch0:1; - /** in_dscr_task_mak_ch0 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers + uint32_t outfifo_empty_l2: 1; + /** outfifo_cnt_l2 : RO; bitpos: [5:2]; default: 0; + * The register stores the byte number of the data in Tx FIFO for Tx channel 2. + */ + uint32_t outfifo_cnt_l2: 4; + /** outfifo_full_l1 : RO; bitpos: [6]; default: 0; + * Tx FIFO full signal for Tx channel 2. + */ + uint32_t outfifo_full_l1: 1; + /** outfifo_empty_l1 : RO; bitpos: [7]; default: 1; + * Tx FIFO empty signal for Tx channel 2. + */ + uint32_t outfifo_empty_l1: 1; + /** outfifo_cnt_l1 : RO; bitpos: [12:8]; default: 0; + * The register stores the byte number of the data in Tx FIFO for Tx channel 2. + */ + uint32_t outfifo_cnt_l1: 5; + uint32_t reserved_13: 3; + /** outfifo_full_l3 : RO; bitpos: [16]; default: 0; + * Tx FIFO full signal for Tx channel 2. + */ + uint32_t outfifo_full_l3: 1; + /** outfifo_empty_l3 : RO; bitpos: [17]; default: 1; + * Tx FIFO empty signal for Tx channel 2. + */ + uint32_t outfifo_empty_l3: 1; + /** outfifo_cnt_l3 : RO; bitpos: [19:18]; default: 0; + * The register stores the byte number of the data in Tx FIFO for Tx channel 2. */ - uint32_t in_dscr_task_mak_ch0:2; - uint32_t reserved_4:28; + uint32_t outfifo_cnt_l3: 2; + uint32_t reserved_20: 12; }; uint32_t val; -} h264_dma_in_etm_conf_ch0_reg_t; - +} h264_dma_outfifo_status_reg_t; -/** Group: RX CH0 debug info */ -/** Type of in_fifo_cnt_ch0 register - * rx CH0 fifo cnt register +/** Type of out_state register + * TX CHn state register */ typedef union { struct { - /** in_cmdfifo_infifo_cnt_ch0 : RO; bitpos: [9:0]; default: 0; - * only for debug + /** outlink_dscr_addr : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + uint32_t outlink_dscr_addr: 18; + /** out_dscr_state : RO; bitpos: [19:18]; default: 0; + * This register stores the current descriptor state machine state. + */ + uint32_t out_dscr_state: 2; + /** out_state : RO; bitpos: [23:20]; default: 0; + * This register stores the current control module state machine state. + */ + uint32_t out_state: 4; + /** out_reset_avail : RO; bitpos: [24]; default: 1; + * This register indicate that if the channel reset is safety. */ - uint32_t in_cmdfifo_infifo_cnt_ch0:10; - uint32_t reserved_10:22; + uint32_t out_reset_avail: 1; + uint32_t reserved_25: 7; }; uint32_t val; -} h264_dma_in_fifo_cnt_ch0_reg_t; +} h264_dma_out_state_chn_reg_t; -/** Type of in_pop_data_cnt_ch0 register - * rx CH0 pop data cnt register +/** Type of out_eof_des_addr register + * TX CHn eof des addr register */ typedef union { struct { - /** in_cmdfifo_pop_data_cnt_ch0 : RO; bitpos: [7:0]; default: 7; - * only for debug + /** out_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. */ - uint32_t in_cmdfifo_pop_data_cnt_ch0:8; - uint32_t reserved_8:24; + uint32_t out_eof_des_addr: 32; }; uint32_t val; -} h264_dma_in_pop_data_cnt_ch0_reg_t; +} h264_dma_out_eof_des_addr_chn_reg_t; -/** Type of in_xaddr_ch0 register - * rx CH0 xaddr register +/** Type of out_dscr register + * TX CHn next dscr addr register */ typedef union { struct { - /** in_cmdfifo_xaddr_ch0 : RO; bitpos: [31:0]; default: 0; - * only for debug + /** outlink_dscr : RO; bitpos: [31:0]; default: 0; + * The address of the next outlink descriptor address y. */ - uint32_t in_cmdfifo_xaddr_ch0:32; + uint32_t outlink_dscr: 32; }; uint32_t val; -} h264_dma_in_xaddr_ch0_reg_t; +} h264_dma_out_dscr_chn_reg_t; -/** Type of in_buf_hb_rcv_ch0 register - * rx CH0 buf len hb rcv register +/** Type of out_dscr_bf0 register + * TX CHn last dscr addr register */ typedef union { struct { - /** in_cmdfifo_buf_hb_rcv_ch0 : RO; bitpos: [28:0]; default: 0; - * only for debug + /** outlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor's next address y-1. */ - uint32_t in_cmdfifo_buf_hb_rcv_ch0:29; - uint32_t reserved_29:3; + uint32_t outlink_dscr_bf0: 32; }; uint32_t val; -} h264_dma_in_buf_hb_rcv_ch0_reg_t; +} h264_dma_out_dscr_bf0_chn_reg_t; - -/** Group: RX CH1 in_link dscr addr register */ -/** Type of in_link_addr_ch1 register - * RX CH1 in_link dscr addr register +/** Type of out_dscr_bf1 register + * TX CHn second-to-last dscr addr register */ typedef union { struct { - /** inlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. + /** outlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last outlink descriptor's next address y-2. */ - uint32_t inlink_addr_ch1:32; + uint32_t outlink_dscr_bf1: 32; }; uint32_t val; -} h264_dma_in_link_addr_ch1_reg_t; - +} h264_dma_out_dscr_bf1_chn_reg_t; -/** Group: RX CH1 arb register */ -/** Type of in_arb_ch1 register - * RX CH1 arb register +/** Type of infifo_status register + * RX CH0 INFIFO status register */ typedef union { struct { - /** in_arb_token_num_ch1 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter + /** infifo_full_l2 : RO; bitpos: [0]; default: 0; + * Rx FIFO full signal for Rx channel. */ - uint32_t in_arb_token_num_ch1:4; - /** exter_in_arb_priority_ch1 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel + uint32_t infifo_full_l2: 1; + /** infifo_empty_l2 : RO; bitpos: [1]; default: 1; + * Rx FIFO empty signal for Rx channel. */ - uint32_t exter_in_arb_priority_ch1:2; - /** inter_in_arb_priority_ch1 : R/W; bitpos: [8:6]; default: 1; - * Set the priority of channel + uint32_t infifo_empty_l2: 1; + /** infifo_cnt_l2 : RO; bitpos: [5:2]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel. */ - uint32_t inter_in_arb_priority_ch1:3; - uint32_t reserved_9:23; - }; - uint32_t val; -} h264_dma_in_arb_ch1_reg_t; - - -/** Group: RX CH1 ETM config register */ -/** Type of in_etm_conf_ch1 register - * RX CH1 ETM config register - */ -typedef union { - struct { - /** in_etm_en_ch1 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function + uint32_t infifo_cnt_l2: 4; + /** infifo_full_l1 : RO; bitpos: [6]; default: 0; + * Tx FIFO full signal for Tx channel 0. */ - uint32_t in_etm_en_ch1:1; - /** in_etm_loop_en_ch1 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task + uint32_t infifo_full_l1: 1; + /** infifo_empty_l1 : RO; bitpos: [7]; default: 1; + * Tx FIFO empty signal for Tx channel 0. */ - uint32_t in_etm_loop_en_ch1:1; - /** in_dscr_task_mak_ch1 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers + uint32_t infifo_empty_l1: 1; + /** infifo_cnt_l1 : RO; bitpos: [12:8]; default: 0; + * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + */ + uint32_t infifo_cnt_l1: 5; + uint32_t reserved_13: 3; + /** infifo_full_l3 : RO; bitpos: [16]; default: 0; + * Tx FIFO full signal for Tx channel 0. + */ + uint32_t infifo_full_l3: 1; + /** infifo_empty_l3 : RO; bitpos: [17]; default: 1; + * Tx FIFO empty signal for Tx channel 0. + */ + uint32_t infifo_empty_l3: 1; + /** infifo_cnt_l3 : RO; bitpos: [19:18]; default: 0; + * The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. */ - uint32_t in_dscr_task_mak_ch1:2; - uint32_t reserved_4:28; + uint32_t infifo_cnt_l3: 2; + uint32_t reserved_20: 12; }; uint32_t val; -} h264_dma_in_etm_conf_ch1_reg_t; +} h264_dma_infifo_status_chn_reg_t; - -/** Group: RX CH1 debug info */ -/** Type of in_fifo_cnt_ch1 register - * rx CH1 fifo cnt register +/** Type of in_state register + * RX CH0 state register */ typedef union { struct { - /** in_cmdfifo_infifo_cnt_ch1 : RO; bitpos: [9:0]; default: 0; - * only for debug + /** inlink_dscr_addr : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + uint32_t inlink_dscr_addr: 18; + /** in_dscr_state : RO; bitpos: [19:18]; default: 0; + * This register stores the current descriptor state machine state. + */ + uint32_t in_dscr_state: 2; + /** in_state : RO; bitpos: [22:20]; default: 0; + * This register stores the current control module state machine state. */ - uint32_t in_cmdfifo_infifo_cnt_ch1:10; - uint32_t reserved_10:22; + uint32_t in_state: 3; + /** in_reset_avail : RO; bitpos: [23]; default: 1; + * This register indicate that if the channel reset is safety. + */ + uint32_t in_reset_avail: 1; + uint32_t reserved_24: 8; }; uint32_t val; -} h264_dma_in_fifo_cnt_ch1_reg_t; +} h264_dma_in_state_chn_reg_t; -/** Type of in_pop_data_cnt_ch1 register - * rx CH1 pop data cnt register +/** Type of in_suc_eof_des_addr register + * RX CH0 eof des addr register */ typedef union { struct { - /** in_cmdfifo_pop_data_cnt_ch1 : RO; bitpos: [7:0]; default: 7; - * only for debug + /** in_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. */ - uint32_t in_cmdfifo_pop_data_cnt_ch1:8; - uint32_t reserved_8:24; + uint32_t in_suc_eof_des_addr: 32; }; uint32_t val; -} h264_dma_in_pop_data_cnt_ch1_reg_t; +} h264_dma_in_suc_eof_des_addr_chn_reg_t; -/** Type of in_xaddr_ch1 register - * rx CH1 xaddr register +/** Type of in_err_eof_des_addr register + * RX CH0 err eof des addr register */ typedef union { struct { - /** in_cmdfifo_xaddr_ch1 : RO; bitpos: [31:0]; default: 0; - * only for debug + /** in_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. */ - uint32_t in_cmdfifo_xaddr_ch1:32; + uint32_t in_err_eof_des_addr: 32; }; uint32_t val; -} h264_dma_in_xaddr_ch1_reg_t; +} h264_dma_in_err_eof_des_addr_chn_reg_t; -/** Type of in_buf_hb_rcv_ch1 register - * rx CH1 buf len hb rcv register +/** Type of in_dscr register + * RX CH0 next dscr addr register */ typedef union { struct { - /** in_cmdfifo_buf_hb_rcv_ch1 : RO; bitpos: [28:0]; default: 0; - * only for debug + /** inlink_dscr : RO; bitpos: [31:0]; default: 0; + * The address of the next inlink descriptor address x. */ - uint32_t in_cmdfifo_buf_hb_rcv_ch1:29; - uint32_t reserved_29:3; + uint32_t inlink_dscr: 32; }; uint32_t val; -} h264_dma_in_buf_hb_rcv_ch1_reg_t; - +} h264_dma_in_dscr_chn_reg_t; -/** Group: RX CH2 in_link dscr addr register */ -/** Type of in_link_addr_ch2 register - * RX CH2 in_link dscr addr register +/** Type of in_dscr_bf0 register + * RX CH0 last dscr addr register */ typedef union { struct { - /** inlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. + /** inlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor's next address x-1. */ - uint32_t inlink_addr_ch2:32; + uint32_t inlink_dscr_bf0: 32; }; uint32_t val; -} h264_dma_in_link_addr_ch2_reg_t; - +} h264_dma_in_dscr_bf0_chn_reg_t; -/** Group: RX CH2 arb register */ -/** Type of in_arb_ch2 register - * RX CH2 arb register +/** Type of in_dscr_bf1 register + * RX CH0 second-to-last dscr addr register */ typedef union { struct { - /** in_arb_token_num_ch2 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t in_arb_token_num_ch2:4; - uint32_t reserved_4:2; - /** inter_in_arb_priority_ch2 : R/W; bitpos: [8:6]; default: 1; - * Set the priority of channel + /** inlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor's next address x-2. */ - uint32_t inter_in_arb_priority_ch2:3; - uint32_t reserved_9:23; + uint32_t inlink_dscr_bf1: 32; }; uint32_t val; -} h264_dma_in_arb_ch2_reg_t; +} h264_dma_in_dscr_bf1_chn_reg_t; -/** Group: RX CH2 ETM config register */ -/** Type of in_etm_conf_ch2 register - * RX CH2 ETM config register +/** Type of infifo_status_ch5 register + * RX CH5 INFIFO status register */ typedef union { struct { - /** in_etm_en_ch2 : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable ETM task function + /** infifo_full_l1 : RO; bitpos: [0]; default: 0; + * Tx FIFO full signal for Tx channel 1. */ - uint32_t in_etm_en_ch2:1; - /** in_etm_loop_en_ch2 : R/W; bitpos: [1]; default: 0; - * when this bit is 1, dscr can be processed after receiving a task + uint32_t infifo_full_l1: 1; + /** infifo_empty_l1 : RO; bitpos: [1]; default: 1; + * Tx FIFO empty signal for Tx channel 1. */ - uint32_t in_etm_loop_en_ch2:1; - /** in_dscr_task_mak_ch2 : R/W; bitpos: [3:2]; default: 1; - * ETM dscr_ready maximum cache numbers + uint32_t infifo_empty_l1: 1; + /** infifo_cnt_l1 : RO; bitpos: [6:2]; default: 0; + * The register stores the byte number of the data in Tx FIFO for Tx channel 1. */ - uint32_t in_dscr_task_mak_ch2:2; - uint32_t reserved_4:28; + uint32_t infifo_cnt_l1: 5; + uint32_t reserved_7: 25; }; uint32_t val; -} h264_dma_in_etm_conf_ch2_reg_t; - +} h264_dma_infifo_status_ch5_reg_t; -/** Group: RX CH2 debug info */ -/** Type of in_fifo_cnt_ch2 register - * rx CH2 fifo cnt register +/** Type of in_state_ch5 register + * RX CH5 state register */ typedef union { struct { - /** in_cmdfifo_infifo_cnt_ch2 : RO; bitpos: [9:0]; default: 0; - * only for debug + /** in_state : RO; bitpos: [2:0]; default: 0; + * This register stores the current control module state machine state. */ - uint32_t in_cmdfifo_infifo_cnt_ch2:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} h264_dma_in_fifo_cnt_ch2_reg_t; - -/** Type of in_pop_data_cnt_ch2 register - * rx CH2 pop data cnt register - */ -typedef union { - struct { - /** in_cmdfifo_pop_data_cnt_ch2 : RO; bitpos: [7:0]; default: 7; - * only for debug + uint32_t in_state: 3; + /** in_reset_avail : RO; bitpos: [3]; default: 1; + * This register indicate that if the channel reset is safety. */ - uint32_t in_cmdfifo_pop_data_cnt_ch2:8; - uint32_t reserved_8:24; + uint32_t in_reset_avail: 1; + uint32_t reserved_4: 28; }; uint32_t val; -} h264_dma_in_pop_data_cnt_ch2_reg_t; +} h264_dma_in_state_ch5_reg_t; -/** Type of in_xaddr_ch2 register - * rx CH2 xaddr register +/** Group: TX CHn config0 register */ +/** Type of out_conf0 register + * TX CHn config0 register */ typedef union { struct { - /** in_cmdfifo_xaddr_ch2 : RO; bitpos: [31:0]; default: 0; - * only for debug + /** out_auto_wrback : R/W; bitpos: [0]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data pointed by + * outlink descriptor has been received. */ - uint32_t in_cmdfifo_xaddr_ch2:32; - }; - uint32_t val; -} h264_dma_in_xaddr_ch2_reg_t; - -/** Type of in_buf_hb_rcv_ch2 register - * rx CH2 buf len hb rcv register - */ -typedef union { - struct { - /** in_cmdfifo_buf_hb_rcv_ch2 : RO; bitpos: [28:0]; default: 0; - * only for debug + uint32_t out_auto_wrback: 1; + /** out_eof_mode : R/W; bitpos: [1]; default: 1; + * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is + * generated when data need to read has been popped from FIFO in DMA + */ + uint32_t out_eof_mode: 1; + /** outdscr_burst_en_ch3 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t outdscr_burst_en_ch3: 1; + /** out_ecc_aes_en : R/W; bitpos: [3]; default: 0; + * When access address space is ecc/aes area, this bit should be set to 1. In this + * case, the start address of square should be 16-bit aligned. The width of square + * multiply byte number of one pixel should be 16-bit aligned. + */ + uint32_t out_ecc_aes_en: 1; + /** out_check_owner : R/W; bitpos: [4]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t out_check_owner: 1; + uint32_t reserved_5: 1; + /** out_mem_burst_length : R/W; bitpos: [8:6]; default: 0; + * Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes 3: 64 + * bytes 4: 128 bytes + */ + uint32_t out_mem_burst_length: 3; + uint32_t reserved_9: 3; + /** out_page_bound_en : R/W; bitpos: [12]; default: 0; + * Set this bit to 1 to make sure AXI read data don't cross the address boundary which + * define by mem_burst_length + */ + uint32_t out_page_bound_en: 1; + uint32_t reserved_13: 3; + /** out_reorder_en : R/W; bitpos: [16]; default: 0; + * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this + * selection + */ + uint32_t out_reorder_en: 1; + uint32_t reserved_17: 7; + /** out_rst : R/W; bitpos: [24]; default: 0; + * Write 1 then write 0 to this bit to reset TX channel + */ + uint32_t out_rst: 1; + /** out_cmd_disable : R/W; bitpos: [25]; default: 0; + * Write 1 before reset and write 0 after reset + */ + uint32_t out_cmd_disable: 1; + /** out_arb_weight_opt_dis : R/W; bitpos: [26]; default: 0; + * Set this bit to 1 to disable arbiter optimum weight function. */ - uint32_t in_cmdfifo_buf_hb_rcv_ch2:29; - uint32_t reserved_29:3; + uint32_t out_arb_weight_opt_dis: 1; + uint32_t reserved_27: 5; }; uint32_t val; -} h264_dma_in_buf_hb_rcv_ch2_reg_t; +} h264_dma_out_conf0_chn_reg_t; -/** Group: RX CH3 in_link dscr addr register */ -/** Type of in_link_addr_ch3 register - * RX CH3 in_link dscr addr register +/** Group: TX CHn out_link dscr addr register */ +/** Type of out_link_addr register + * TX CHn out_link dscr addr register */ typedef union { struct { - /** inlink_addr_ch3 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. + /** outlink_addr : R/W; bitpos: [31:0]; default: 0; + * This register stores the first outlink descriptor's address. */ - uint32_t inlink_addr_ch3:32; + uint32_t outlink_addr: 32; }; uint32_t val; -} h264_dma_in_link_addr_ch3_reg_t; +} h264_dma_out_link_addr_chn_reg_t; -/** Group: RX CH3 arb register */ -/** Type of in_arb_ch3 register - * RX CH3 arb register +/** Group: TX CHn arb register */ +/** Type of out_arb register + * TX CHn arb register */ typedef union { struct { - /** in_arb_token_num_ch3 : R/W; bitpos: [3:0]; default: 1; + /** out_arb_token_num : R/W; bitpos: [3:0]; default: 1; * Set the max number of token count of arbiter */ - uint32_t in_arb_token_num_ch3:4; - uint32_t reserved_4:2; - /** inter_in_arb_priority_ch3 : R/W; bitpos: [8:6]; default: 1; + uint32_t out_arb_token_num: 4; + /** exter_out_arb_priority : R/W; bitpos: [5:4]; default: 1; * Set the priority of channel */ - uint32_t inter_in_arb_priority_ch3:3; - uint32_t reserved_9:23; + uint32_t exter_out_arb_priority: 2; + uint32_t reserved_6: 26; }; uint32_t val; -} h264_dma_in_arb_ch3_reg_t; +} h264_dma_out_arb_chn_reg_t; -/** Group: RX CH3 ETM config register */ -/** Type of in_etm_conf_ch3 register - * RX CH3 ETM config register +/** Group: TX CHn ETM config register */ +/** Type of out_etm_conf register + * TX CHn ETM config register */ typedef union { struct { - /** in_etm_en_ch3 : R/W; bitpos: [0]; default: 0; + /** out_etm_en : R/W; bitpos: [0]; default: 0; * Set this bit to 1 to enable ETM task function */ - uint32_t in_etm_en_ch3:1; - /** in_etm_loop_en_ch3 : R/W; bitpos: [1]; default: 0; + uint32_t out_etm_en: 1; + /** out_etm_loop_en : R/W; bitpos: [1]; default: 0; * when this bit is 1, dscr can be processed after receiving a task */ - uint32_t in_etm_loop_en_ch3:1; - /** in_dscr_task_mak_ch3 : R/W; bitpos: [3:2]; default: 1; + uint32_t out_etm_loop_en: 1; + /** out_dscr_task_mak : R/W; bitpos: [3:2]; default: 1; * ETM dscr_ready maximum cache numbers */ - uint32_t in_dscr_task_mak_ch3:2; - uint32_t reserved_4:28; + uint32_t out_dscr_task_mak: 2; + uint32_t reserved_4: 28; }; uint32_t val; -} h264_dma_in_etm_conf_ch3_reg_t; +} h264_dma_out_etm_conf_chn_reg_t; + +/** Group: TX CHn debug info */ +/** Type of out_buf_len register + * tx CHn buf len register + */ +typedef union { + struct { + /** out_cmdfifo_buf_len_hb : RO; bitpos: [12:0]; default: 0; + * only for debug + */ + uint32_t out_cmdfifo_buf_len_hb: 28; + uint32_t reserved_13: 4; + }; + uint32_t val; +} h264_dma_out_buf_len_chn_reg_t; -/** Group: RX CH3 debug info */ -/** Type of in_fifo_cnt_ch3 register - * rx CH3 fifo cnt register +/** Type of out_fifo_bcnt register + * tx CHn fifo byte cnt register */ typedef union { struct { - /** in_cmdfifo_infifo_cnt_ch3 : RO; bitpos: [9:0]; default: 0; + /** out_cmdfifo_outfifo_bcnt : RO; bitpos: [9:0]; default: 0; * only for debug */ - uint32_t in_cmdfifo_infifo_cnt_ch3:10; - uint32_t reserved_10:22; + uint32_t out_cmdfifo_outfifo_bcnt: 10; + uint32_t reserved_10: 22; }; uint32_t val; -} h264_dma_in_fifo_cnt_ch3_reg_t; +} h264_dma_out_fifo_bcnt_chn_reg_t; -/** Type of in_pop_data_cnt_ch3 register - * rx CH3 pop data cnt register +/** Type of out_push_bytecnt register + * tx CHn push byte cnt register */ typedef union { struct { - /** in_cmdfifo_pop_data_cnt_ch3 : RO; bitpos: [7:0]; default: 7; + /** out_cmdfifo_push_bytecnt : RO; bitpos: [7:0]; default: 63; * only for debug */ - uint32_t in_cmdfifo_pop_data_cnt_ch3:8; - uint32_t reserved_8:24; + uint32_t out_cmdfifo_push_bytecnt: 8; + uint32_t reserved_8: 24; }; uint32_t val; -} h264_dma_in_pop_data_cnt_ch3_reg_t; +} h264_dma_out_push_bytecnt_chn_reg_t; -/** Type of in_xaddr_ch3 register - * rx CH3 xaddr register +/** Type of out_xaddr register + * tx CHn xaddr register */ typedef union { struct { - /** in_cmdfifo_xaddr_ch3 : RO; bitpos: [31:0]; default: 0; + /** out_cmdfifo_xaddr : RO; bitpos: [31:0]; default: 0; * only for debug */ - uint32_t in_cmdfifo_xaddr_ch3:32; + uint32_t out_cmdfifo_xaddr: 32; }; uint32_t val; -} h264_dma_in_xaddr_ch3_reg_t; +} h264_dma_out_xaddr_chn_reg_t; -/** Type of in_buf_hb_rcv_ch3 register - * rx CH3 buf len hb rcv register +/** Type of out_block_buf_len register + * tx CHn block buf len register */ typedef union { struct { - /** in_cmdfifo_buf_hb_rcv_ch3 : RO; bitpos: [28:0]; default: 0; + /** out_block_buf_len : RO; bitpos: [27:0]; default: 0; * only for debug */ - uint32_t in_cmdfifo_buf_hb_rcv_ch3:29; - uint32_t reserved_29:3; + uint32_t out_block_buf_len: 28; + uint32_t reserved_28: 4; }; uint32_t val; -} h264_dma_in_buf_hb_rcv_ch3_reg_t; +} h264_dma_out_block_buf_len_chn_reg_t; -/** Group: RX CH4 in_link dscr addr register */ -/** Type of in_link_addr_ch4 register - * RX CH4 in_link dscr addr register +/** Group: RX CH0 in_link dscr addr register */ +/** Type of in_link_addr register + * RX CH0 in_link dscr addr register */ typedef union { struct { - /** inlink_addr_ch4 : R/W; bitpos: [31:0]; default: 0; + /** inlink_addr : R/W; bitpos: [31:0]; default: 0; * This register stores the first inlink descriptor's address. */ - uint32_t inlink_addr_ch4:32; + uint32_t inlink_addr: 32; }; uint32_t val; -} h264_dma_in_link_addr_ch4_reg_t; +} h264_dma_in_link_addr_chn_reg_t; -/** Group: RX CH4 arb register */ -/** Type of in_arb_ch4 register - * RX CH4 arb register +/** Group: RX CH0 arb register */ +/** Type of in_arb register + * RX CH0 arb register */ typedef union { struct { - /** in_arb_token_num_ch4 : R/W; bitpos: [3:0]; default: 1; + /** in_arb_token_num : R/W; bitpos: [3:0]; default: 1; * Set the max number of token count of arbiter */ - uint32_t in_arb_token_num_ch4:4; - /** exter_in_arb_priority_ch4 : R/W; bitpos: [5:4]; default: 1; + uint32_t in_arb_token_num: 4; + /** exter_in_arb_priority : R/W; bitpos: [5:4]; default: 1; * Set the priority of channel */ - uint32_t exter_in_arb_priority_ch4:2; - /** inter_in_arb_priority_ch4 : R/W; bitpos: [8:6]; default: 1; + uint32_t exter_in_arb_priority: 2; + /** inter_in_arb_priority : R/W; bitpos: [8:6]; default: 1; * Set the priority of channel */ - uint32_t inter_in_arb_priority_ch4:3; - uint32_t reserved_9:23; + uint32_t inter_in_arb_priority: 3; + uint32_t reserved_9: 23; }; uint32_t val; -} h264_dma_in_arb_ch4_reg_t; +} h264_dma_in_arb_chn_reg_t; -/** Group: RX CH4 ETM config register */ -/** Type of in_etm_conf_ch4 register - * RX CH4 ETM config register +/** Group: RX CH0 ETM config register */ +/** Type of in_etm_conf register + * RX CH0 ETM config register */ typedef union { struct { - /** in_etm_en_ch4 : R/W; bitpos: [0]; default: 0; + /** in_etm_en : R/W; bitpos: [0]; default: 0; * Set this bit to 1 to enable ETM task function */ - uint32_t in_etm_en_ch4:1; - /** in_etm_loop_en_ch4 : R/W; bitpos: [1]; default: 0; + uint32_t in_etm_en: 1; + /** in_etm_loop_en : R/W; bitpos: [1]; default: 0; * when this bit is 1, dscr can be processed after receiving a task */ - uint32_t in_etm_loop_en_ch4:1; - /** in_dscr_task_mak_ch4 : R/W; bitpos: [3:2]; default: 1; + uint32_t in_etm_loop_en: 1; + /** in_dscr_task_mak : R/W; bitpos: [3:2]; default: 1; * ETM dscr_ready maximum cache numbers */ - uint32_t in_dscr_task_mak_ch4:2; - uint32_t reserved_4:28; + uint32_t in_dscr_task_mak: 2; + uint32_t reserved_4: 28; }; uint32_t val; -} h264_dma_in_etm_conf_ch4_reg_t; +} h264_dma_in_etm_conf_chn_reg_t; -/** Group: RX CH4 debug info */ -/** Type of in_fifo_cnt_ch4 register - * rx CH4 fifo cnt register +/** Group: RX CH0 debug info */ +/** Type of in_fifo_cnt register + * rx CH0 fifo cnt register */ typedef union { struct { - /** in_cmdfifo_infifo_cnt_ch4 : RO; bitpos: [9:0]; default: 0; + /** in_cmdfifo_infifo_cnt : RO; bitpos: [9:0]; default: 0; * only for debug */ - uint32_t in_cmdfifo_infifo_cnt_ch4:10; - uint32_t reserved_10:22; + uint32_t in_cmdfifo_infifo_cnt: 10; + uint32_t reserved_10: 22; }; uint32_t val; -} h264_dma_in_fifo_cnt_ch4_reg_t; +} h264_dma_in_fifo_cnt_chn_reg_t; -/** Type of in_pop_data_cnt_ch4 register - * rx CH4 pop data cnt register +/** Type of in_pop_data_cnt register + * rx CH0 pop data cnt register */ typedef union { struct { - /** in_cmdfifo_pop_data_cnt_ch4 : RO; bitpos: [7:0]; default: 7; + /** in_cmdfifo_pop_data_cnt : RO; bitpos: [7:0]; default: 7; * only for debug */ - uint32_t in_cmdfifo_pop_data_cnt_ch4:8; - uint32_t reserved_8:24; + uint32_t in_cmdfifo_pop_data_cnt: 8; + uint32_t reserved_8: 24; }; uint32_t val; -} h264_dma_in_pop_data_cnt_ch4_reg_t; +} h264_dma_in_pop_data_cnt_chn_reg_t; -/** Type of in_xaddr_ch4 register - * rx CH4 xaddr register +/** Type of in_xaddr register + * rx CH0 xaddr register */ typedef union { struct { - /** in_cmdfifo_xaddr_ch4 : RO; bitpos: [31:0]; default: 0; + /** in_cmdfifo_xaddr : RO; bitpos: [31:0]; default: 0; * only for debug */ - uint32_t in_cmdfifo_xaddr_ch4:32; + uint32_t in_cmdfifo_xaddr: 32; }; uint32_t val; -} h264_dma_in_xaddr_ch4_reg_t; +} h264_dma_in_xaddr_chn_reg_t; -/** Type of in_buf_hb_rcv_ch4 register - * rx CH4 buf len hb rcv register +/** Type of in_buf_hb_rcv register + * rx CH0 buf len hb rcv register */ typedef union { struct { - /** in_cmdfifo_buf_hb_rcv_ch4 : RO; bitpos: [28:0]; default: 0; + /** in_cmdfifo_buf_hb_rcv : RO; bitpos: [28:0]; default: 0; * only for debug */ - uint32_t in_cmdfifo_buf_hb_rcv_ch4:29; - uint32_t reserved_29:3; + uint32_t in_cmdfifo_buf_hb_rcv: 29; + uint32_t reserved_29: 3; }; uint32_t val; -} h264_dma_in_buf_hb_rcv_ch4_reg_t; - +} h264_dma_in_buf_hb_rcv_chn_reg_t; /** Group: RX CH5 config1 register */ /** Type of in_conf1_ch5 register @@ -5926,10 +1414,10 @@ typedef union { */ typedef union { struct { - /** block_start_addr_ch5 : R/W; bitpos: [31:0]; default: 0; + /** block_start_addr : R/W; bitpos: [31:0]; default: 0; * RX Channel 5 destination start address */ - uint32_t block_start_addr_ch5:32; + uint32_t block_start_addr: 32; }; uint32_t val; } h264_dma_in_conf1_ch5_reg_t; @@ -5941,14 +1429,14 @@ typedef union { */ typedef union { struct { - /** block_row_length_12line_ch5 : R/W; bitpos: [15:0]; default: 30720; + /** block_row_length_12line : R/W; bitpos: [15:0]; default: 30720; * The number of bytes contained in a row block 12line in RX channel 5 */ - uint32_t block_row_length_12line_ch5:16; - /** block_row_length_4line_ch5 : R/W; bitpos: [31:16]; default: 15360; + uint32_t block_row_length_12line: 16; + /** block_row_length_4line : R/W; bitpos: [31:16]; default: 15360; * The number of bytes contained in a row block 4line in RX channel 5 */ - uint32_t block_row_length_4line_ch5:16; + uint32_t block_row_length_4line: 16; }; uint32_t val; } h264_dma_in_conf2_ch5_reg_t; @@ -5960,15 +1448,15 @@ typedef union { */ typedef union { struct { - /** block_length_12line_ch5 : R/W; bitpos: [13:0]; default: 256; + /** block_length_12line : R/W; bitpos: [13:0]; default: 256; * The number of bytes contained in a block 12line */ - uint32_t block_length_12line_ch5:14; - /** block_length_4line_ch5 : R/W; bitpos: [27:14]; default: 128; + uint32_t block_length_12line: 14; + /** block_length_4line : R/W; bitpos: [27:14]; default: 128; * The number of bytes contained in a block 4line */ - uint32_t block_length_4line_ch5:14; - uint32_t reserved_28:4; + uint32_t block_length_4line: 14; + uint32_t reserved_28: 4; }; uint32_t val; } h264_dma_in_conf3_ch5_reg_t; @@ -5980,16 +1468,16 @@ typedef union { */ typedef union { struct { - /** in_arb_token_num_ch5 : R/W; bitpos: [3:0]; default: 1; + /** in_arb_token_num : R/W; bitpos: [3:0]; default: 1; * Set the max number of token count of arbiter */ - uint32_t in_arb_token_num_ch5:4; - uint32_t reserved_4:2; - /** inter_in_arb_priority_ch5 : R/W; bitpos: [8:6]; default: 1; + uint32_t in_arb_token_num: 4; + uint32_t reserved_4: 2; + /** inter_in_arb_priority : R/W; bitpos: [8:6]; default: 1; * Set the priority of channel */ - uint32_t inter_in_arb_priority_ch5:3; - uint32_t reserved_9:23; + uint32_t inter_in_arb_priority: 3; + uint32_t reserved_9: 23; }; uint32_t val; } h264_dma_in_arb_ch5_reg_t; @@ -6001,11 +1489,11 @@ typedef union { */ typedef union { struct { - /** in_cmdfifo_infifo_cnt_ch5 : RO; bitpos: [9:0]; default: 0; + /** in_cmdfifo_infifo_cnt : RO; bitpos: [9:0]; default: 0; * only for debug */ - uint32_t in_cmdfifo_infifo_cnt_ch5:10; - uint32_t reserved_10:22; + uint32_t in_cmdfifo_infifo_cnt: 10; + uint32_t reserved_10: 22; }; uint32_t val; } h264_dma_in_fifo_cnt_ch5_reg_t; @@ -6015,11 +1503,11 @@ typedef union { */ typedef union { struct { - /** in_cmdfifo_pop_data_cnt_ch5 : RO; bitpos: [7:0]; default: 255; + /** in_cmdfifo_pop_data_cnt : RO; bitpos: [7:0]; default: 255; * only for debug */ - uint32_t in_cmdfifo_pop_data_cnt_ch5:8; - uint32_t reserved_8:24; + uint32_t in_cmdfifo_pop_data_cnt: 8; + uint32_t reserved_8: 24; }; uint32_t val; } h264_dma_in_pop_data_cnt_ch5_reg_t; @@ -6029,10 +1517,10 @@ typedef union { */ typedef union { struct { - /** in_cmdfifo_xaddr_ch5 : RO; bitpos: [31:0]; default: 0; + /** in_cmdfifo_xaddr : RO; bitpos: [31:0]; default: 0; * only for debug */ - uint32_t in_cmdfifo_xaddr_ch5:32; + uint32_t in_cmdfifo_xaddr: 32; }; uint32_t val; } h264_dma_in_xaddr_ch5_reg_t; @@ -6042,11 +1530,11 @@ typedef union { */ typedef union { struct { - /** in_cmdfifo_buf_hb_rcv_ch5 : RO; bitpos: [28:0]; default: 0; + /** in_cmdfifo_buf_hb_rcv : RO; bitpos: [28:0]; default: 0; * only for debug */ - uint32_t in_cmdfifo_buf_hb_rcv_ch5:29; - uint32_t reserved_29:3; + uint32_t in_cmdfifo_buf_hb_rcv: 29; + uint32_t reserved_29: 3; }; uint32_t val; } h264_dma_in_buf_hb_rcv_ch5_reg_t; @@ -6061,32 +1549,32 @@ typedef union { /** inter_rid_err_cnt : RO; bitpos: [3:0]; default: 0; * AXI read id err cnt */ - uint32_t inter_rid_err_cnt:4; + uint32_t inter_rid_err_cnt: 4; /** inter_rresp_err_cnt : RO; bitpos: [7:4]; default: 0; * AXI read resp err cnt */ - uint32_t inter_rresp_err_cnt:4; + uint32_t inter_rresp_err_cnt: 4; /** inter_wresp_err_cnt : RO; bitpos: [11:8]; default: 0; * AXI write resp err cnt */ - uint32_t inter_wresp_err_cnt:4; + uint32_t inter_wresp_err_cnt: 4; /** inter_rd_fifo_cnt : RO; bitpos: [14:12]; default: 0; * AXI read cmd fifo remain cmd count */ - uint32_t inter_rd_fifo_cnt:3; + uint32_t inter_rd_fifo_cnt: 3; /** inter_rd_bak_fifo_cnt : RO; bitpos: [18:15]; default: 0; * AXI read backup cmd fifo remain cmd count */ - uint32_t inter_rd_bak_fifo_cnt:4; + uint32_t inter_rd_bak_fifo_cnt: 4; /** inter_wr_fifo_cnt : RO; bitpos: [21:19]; default: 0; * AXI write cmd fifo remain cmd count */ - uint32_t inter_wr_fifo_cnt:3; + uint32_t inter_wr_fifo_cnt: 3; /** inter_wr_bak_fifo_cnt : RO; bitpos: [25:22]; default: 0; * AXI write backup cmd fifo remain cmd count */ - uint32_t inter_wr_bak_fifo_cnt:4; - uint32_t reserved_26:6; + uint32_t inter_wr_bak_fifo_cnt: 4; + uint32_t reserved_26: 6; }; uint32_t val; } h264_dma_inter_axi_err_reg_t; @@ -6101,185 +1589,83 @@ typedef union { /** exter_rid_err_cnt : RO; bitpos: [3:0]; default: 0; * AXI read id err cnt */ - uint32_t exter_rid_err_cnt:4; + uint32_t exter_rid_err_cnt: 4; /** exter_rresp_err_cnt : RO; bitpos: [7:4]; default: 0; * AXI read resp err cnt */ - uint32_t exter_rresp_err_cnt:4; + uint32_t exter_rresp_err_cnt: 4; /** exter_wresp_err_cnt : RO; bitpos: [11:8]; default: 0; * AXI write resp err cnt */ - uint32_t exter_wresp_err_cnt:4; + uint32_t exter_wresp_err_cnt: 4; /** exter_rd_fifo_cnt : RO; bitpos: [14:12]; default: 0; * AXI read cmd fifo remain cmd count */ - uint32_t exter_rd_fifo_cnt:3; + uint32_t exter_rd_fifo_cnt: 3; /** exter_rd_bak_fifo_cnt : RO; bitpos: [18:15]; default: 0; * AXI read backup cmd fifo remain cmd count */ - uint32_t exter_rd_bak_fifo_cnt:4; + uint32_t exter_rd_bak_fifo_cnt: 4; /** exter_wr_fifo_cnt : RO; bitpos: [21:19]; default: 0; * AXI write cmd fifo remain cmd count */ - uint32_t exter_wr_fifo_cnt:3; + uint32_t exter_wr_fifo_cnt: 3; /** exter_wr_bak_fifo_cnt : RO; bitpos: [25:22]; default: 0; * AXI write backup cmd fifo remain cmd count */ - uint32_t exter_wr_bak_fifo_cnt:4; - uint32_t reserved_26:6; + uint32_t exter_wr_bak_fifo_cnt: 4; + uint32_t reserved_26: 6; }; uint32_t val; } h264_dma_exter_axi_err_reg_t; /** Group: dscr addr range register */ -/** Type of inter_mem_start_addr0 register - * Start address of inter memory range0 register - */ -typedef union { - struct { - /** access_inter_mem_start_addr0 : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ - uint32_t access_inter_mem_start_addr0:32; - }; - uint32_t val; -} h264_dma_inter_mem_start_addr0_reg_t; - -/** Type of inter_mem_end_addr0 register - * end address of inter memory range0 register - */ -typedef union { - struct { - /** access_inter_mem_end_addr0 : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ - uint32_t access_inter_mem_end_addr0:32; - }; - uint32_t val; -} h264_dma_inter_mem_end_addr0_reg_t; - -/** Type of inter_mem_start_addr1 register - * Start address of inter memory range1 register - */ -typedef union { - struct { - /** access_inter_mem_start_addr1 : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ - uint32_t access_inter_mem_start_addr1:32; - }; - uint32_t val; -} h264_dma_inter_mem_start_addr1_reg_t; - -/** Type of inter_mem_end_addr1 register - * end address of inter memory range1 register - */ -typedef union { - struct { - /** access_inter_mem_end_addr1 : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ - uint32_t access_inter_mem_end_addr1:32; - }; - uint32_t val; -} h264_dma_inter_mem_end_addr1_reg_t; - -/** Type of exter_mem_start_addr0 register - * Start address of exter memory range0 register - */ -typedef union { - struct { - /** access_exter_mem_start_addr0 : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ - uint32_t access_exter_mem_start_addr0:32; - }; - uint32_t val; -} h264_dma_exter_mem_start_addr0_reg_t; - -/** Type of exter_mem_end_addr0 register - * end address of exter memory range0 register - */ -typedef union { - struct { - /** access_exter_mem_end_addr0 : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ - uint32_t access_exter_mem_end_addr0:32; - }; - uint32_t val; -} h264_dma_exter_mem_end_addr0_reg_t; - -/** Type of exter_mem_start_addr1 register - * Start address of exter memory range1 register +/** Type of mem_start_addr register + * Start address of inter memory range register */ typedef union { struct { - /** access_exter_mem_start_addr1 : R/W; bitpos: [31:0]; default: 806354944; + /** access_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944; * The start address of accessible address space. */ - uint32_t access_exter_mem_start_addr1:32; + uint32_t access_mem_start_addr: 32; }; uint32_t val; -} h264_dma_exter_mem_start_addr1_reg_t; +} h264_dma_mem_start_addr_reg_t; -/** Type of exter_mem_end_addr1 register - * end address of exter memory range1 register +/** Type of mem_end_addr register + * end address of inter memory range register */ typedef union { struct { - /** access_exter_mem_end_addr1 : R/W; bitpos: [31:0]; default: 2415919103; + /** access_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103; * The end address of accessible address space. The access address beyond this range * would lead to descriptor error. */ - uint32_t access_exter_mem_end_addr1:32; - }; - uint32_t val; -} h264_dma_exter_mem_end_addr1_reg_t; - - -/** Group: out arb config register */ -/** Type of out_arb_config register - * reserved - */ -typedef union { - struct { - /** out_arb_timeout_num : R/W; bitpos: [15:0]; default: 0; - * Set the max number of timeout count of arbiter - */ - uint32_t out_arb_timeout_num:16; - /** out_weight_en : R/W; bitpos: [16]; default: 0; - * reserved - */ - uint32_t out_weight_en:1; - uint32_t reserved_17:15; + uint32_t access_mem_end_addr: 32; }; uint32_t val; -} h264_dma_out_arb_config_reg_t; +} h264_dma_mem_end_addr_reg_t; - -/** Group: in arb config register */ -/** Type of in_arb_config register +/** Group: arb config register */ +/** Type of arb_config register * reserved */ typedef union { struct { - /** in_arb_timeout_num : R/W; bitpos: [15:0]; default: 0; + /** arb_timeout_num : R/W; bitpos: [15:0]; default: 0; * Set the max number of timeout count of arbiter */ - uint32_t in_arb_timeout_num:16; - /** in_weight_en : R/W; bitpos: [16]; default: 0; + uint32_t arb_timeout_num: 16; + /** weight_en : R/W; bitpos: [16]; default: 0; * reserved */ - uint32_t in_weight_en:1; - uint32_t reserved_17:15; + uint32_t weight_en: 1; + uint32_t reserved_17: 15; }; uint32_t val; -} h264_dma_in_arb_config_reg_t; +} h264_dma_arb_config_reg_t; /** Group: date register */ @@ -6291,7 +1677,7 @@ typedef union { /** date : R/W; bitpos: [31:0]; default: 539165699; * register version. */ - uint32_t date:32; + uint32_t date: 32; }; uint32_t val; } h264_dma_date_reg_t; @@ -6306,20 +1692,20 @@ typedef union { /** rx_ch0_exter_counter_rst : R/W; bitpos: [0]; default: 0; * Write 1 then write 0 to this bit to reset rx ch0 counter. */ - uint32_t rx_ch0_exter_counter_rst:1; + uint32_t rx_ch0_exter_counter_rst: 1; /** rx_ch1_exter_counter_rst : R/W; bitpos: [1]; default: 0; * Write 1 then write 0 to this bit to reset rx ch1 counter. */ - uint32_t rx_ch1_exter_counter_rst:1; + uint32_t rx_ch1_exter_counter_rst: 1; /** rx_ch2_inter_counter_rst : R/W; bitpos: [2]; default: 0; * Write 1 then write 0 to this bit to reset rx ch2 counter. */ - uint32_t rx_ch2_inter_counter_rst:1; + uint32_t rx_ch2_inter_counter_rst: 1; /** rx_ch5_inter_counter_rst : R/W; bitpos: [3]; default: 0; * Write 1 then write 0 to this bit to reset rx ch5 counter. */ - uint32_t rx_ch5_inter_counter_rst:1; - uint32_t reserved_4:28; + uint32_t rx_ch5_inter_counter_rst: 1; + uint32_t reserved_4: 28; }; uint32_t val; } h264_dma_counter_rst_reg_t; @@ -6334,8 +1720,8 @@ typedef union { /** rx_ch0_cnt : RO; bitpos: [22:0]; default: 0; * rx ch0 counter register */ - uint32_t rx_ch0_cnt:23; - uint32_t reserved_23:9; + uint32_t rx_ch0_cnt: 23; + uint32_t reserved_23: 9; }; uint32_t val; } h264_dma_rx_ch0_counter_reg_t; @@ -6348,8 +1734,8 @@ typedef union { /** rx_ch1_cnt : RO; bitpos: [20:0]; default: 0; * rx ch1 counter register */ - uint32_t rx_ch1_cnt:21; - uint32_t reserved_21:11; + uint32_t rx_ch1_cnt: 21; + uint32_t reserved_21: 11; }; uint32_t val; } h264_dma_rx_ch1_counter_reg_t; @@ -6362,8 +1748,8 @@ typedef union { /** rx_ch2_cnt : RO; bitpos: [10:0]; default: 0; * rx ch2 counter register */ - uint32_t rx_ch2_cnt:11; - uint32_t reserved_11:21; + uint32_t rx_ch2_cnt: 11; + uint32_t reserved_11: 21; }; uint32_t val; } h264_dma_rx_ch2_counter_reg_t; @@ -6376,13 +1762,12 @@ typedef union { /** rx_ch5_cnt : RO; bitpos: [16:0]; default: 0; * rx ch5 counter register */ - uint32_t rx_ch5_cnt:17; - uint32_t reserved_17:15; + uint32_t rx_ch5_cnt: 17; + uint32_t reserved_17: 15; }; uint32_t val; } h264_dma_rx_ch5_counter_reg_t; - /** Group: pbyte register */ /** Type of pbyte register * image pbyte register @@ -6393,644 +1778,109 @@ typedef union { * configures bytes per pixel for ori img. 0: 0.5byte/pix, 1: 1byte/pix, 2: * 1.5byte/pix, 3: 2byte/pix, 4: 3byte/pix */ - uint32_t ori_pbyte:4; - uint32_t reserved_4:28; + uint32_t ori_pbyte: 4; + uint32_t reserved_4: 28; }; uint32_t val; } h264_dma_pbyte_reg_t; - -/** Group: debug register */ -/** Type of ch_dbg_en register - * channel debug enable register - */ -typedef union { - struct { - /** out_ch0_dbg_en : R/W; bitpos: [0]; default: 0; - * configures whether to enable out channel 0 debug. 0: disable, 1: enable - */ - uint32_t out_ch0_dbg_en:1; - /** out_ch1_dbg_en : R/W; bitpos: [1]; default: 0; - * configures whether to enable out channel 1 debug. 0: disable, 1: enable - */ - uint32_t out_ch1_dbg_en:1; - /** out_ch2_dbg_en : R/W; bitpos: [2]; default: 0; - * configures whether to enable out channel 2 debug. 0: disable, 1: enable - */ - uint32_t out_ch2_dbg_en:1; - /** out_ch3_dbg_en : R/W; bitpos: [3]; default: 0; - * configures whether to enable out channel 3 debug. 0: disable, 1: enable - */ - uint32_t out_ch3_dbg_en:1; - /** out_ch4_dbg_en : R/W; bitpos: [4]; default: 0; - * configures whether to enable out channel 4 debug. 0: disable, 1: enable - */ - uint32_t out_ch4_dbg_en:1; - uint32_t reserved_5:11; - /** in_ch0_dbg_en : R/W; bitpos: [16]; default: 0; - * configures whether to enable in channel 0 debug. 0: disable, 1: enable - */ - uint32_t in_ch0_dbg_en:1; - /** in_ch1_dbg_en : R/W; bitpos: [17]; default: 0; - * configures whether to enable in channel 1 debug. 0: disable, 1: enable - */ - uint32_t in_ch1_dbg_en:1; - /** in_ch2_dbg_en : R/W; bitpos: [18]; default: 0; - * configures whether to enable in channel 2 debug. 0: disable, 1: enable - */ - uint32_t in_ch2_dbg_en:1; - /** in_ch3_dbg_en : R/W; bitpos: [19]; default: 0; - * configures whether to enable in channel 3 debug. 0: disable, 1: enable - */ - uint32_t in_ch3_dbg_en:1; - /** in_ch4_dbg_en : R/W; bitpos: [20]; default: 0; - * configures whether to enable in channel 4 debug. 0: disable, 1: enable - */ - uint32_t in_ch4_dbg_en:1; - /** in_ch5_dbg_en : R/W; bitpos: [21]; default: 0; - * configures whether to enable in channel 5 debug. 0: disable, 1: enable - */ - uint32_t in_ch5_dbg_en:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} h264_dma_ch_dbg_en_reg_t; - -/** Type of out_ch0_dbg_data_l register - * out channel 0 debug data register - */ -typedef union { - struct { - /** out_ch0_dbg_data_l : R/W; bitpos: [31:0]; default: 0; - * configures out channel 0 debug data bit 31-0 - */ - uint32_t out_ch0_dbg_data_l:32; - }; - uint32_t val; -} h264_dma_out_ch0_dbg_data_l_reg_t; - -/** Type of out_ch0_dbg_data_h register - * out channel 0 debug data register - */ -typedef union { - struct { - /** out_ch0_dbg_data_h : R/W; bitpos: [31:0]; default: 0; - * configures out channel 0 debug data bit 63-32 - */ - uint32_t out_ch0_dbg_data_h:32; - }; - uint32_t val; -} h264_dma_out_ch0_dbg_data_h_reg_t; - -/** Type of out_ch1_dbg_data_l register - * out channel 1 debug data register - */ -typedef union { - struct { - /** out_ch1_dbg_data_l : R/W; bitpos: [31:0]; default: 0; - * configures out channel 1 debug data bit 31-0 - */ - uint32_t out_ch1_dbg_data_l:32; - }; - uint32_t val; -} h264_dma_out_ch1_dbg_data_l_reg_t; - -/** Type of out_ch1_dbg_data_h register - * out channel 1 debug data register - */ -typedef union { - struct { - /** out_ch1_dbg_data_h : R/W; bitpos: [31:0]; default: 0; - * configures out channel 1 debug data bit 63-32 - */ - uint32_t out_ch1_dbg_data_h:32; - }; - uint32_t val; -} h264_dma_out_ch1_dbg_data_h_reg_t; - -/** Type of out_ch2_dbg_data_l register - * out channel 2 debug data register - */ -typedef union { - struct { - /** out_ch2_dbg_data_l : R/W; bitpos: [31:0]; default: 0; - * configures out channel 2 debug data bit 31-0 - */ - uint32_t out_ch2_dbg_data_l:32; - }; - uint32_t val; -} h264_dma_out_ch2_dbg_data_l_reg_t; - -/** Type of out_ch2_dbg_data_h register - * out channel 2 debug data register - */ -typedef union { - struct { - /** out_ch2_dbg_data_h : R/W; bitpos: [31:0]; default: 0; - * configures out channel 2 debug data bit 63-32 - */ - uint32_t out_ch2_dbg_data_h:32; - }; - uint32_t val; -} h264_dma_out_ch2_dbg_data_h_reg_t; - -/** Type of out_ch3_dbg_data_l register - * out channel 3 debug data register - */ -typedef union { - struct { - /** out_ch3_dbg_data_l : R/W; bitpos: [31:0]; default: 0; - * configures out channel 3 debug data bit 31-0 - */ - uint32_t out_ch3_dbg_data_l:32; - }; - uint32_t val; -} h264_dma_out_ch3_dbg_data_l_reg_t; - -/** Type of out_ch3_dbg_data_h register - * out channel 3 debug data register - */ -typedef union { - struct { - /** out_ch3_dbg_data_h : R/W; bitpos: [31:0]; default: 0; - * configures out channel 3 debug data bit 63-32 - */ - uint32_t out_ch3_dbg_data_h:32; - }; - uint32_t val; -} h264_dma_out_ch3_dbg_data_h_reg_t; - -/** Type of out_ch4_dbg_data_l register - * out channel 4 debug data register - */ -typedef union { - struct { - /** out_ch4_dbg_data_l : R/W; bitpos: [31:0]; default: 0; - * configures out channel 4 debug data bit 31-0 - */ - uint32_t out_ch4_dbg_data_l:32; - }; - uint32_t val; -} h264_dma_out_ch4_dbg_data_l_reg_t; - -/** Type of out_ch4_dbg_data_h register - * out channel 4 debug data register - */ -typedef union { - struct { - /** out_ch4_dbg_data_h : R/W; bitpos: [31:0]; default: 0; - * configures out channel 4 debug data bit 63-32 - */ - uint32_t out_ch4_dbg_data_h:32; - }; - uint32_t val; -} h264_dma_out_ch4_dbg_data_h_reg_t; - -/** Type of in_ch0_dbg_data_l register - * in channel 0 debug data register - */ -typedef union { - struct { - /** in_ch0_dbg_data_l : R/W; bitpos: [31:0]; default: 0; - * configures in channel 0 debug data bit 31-0 - */ - uint32_t in_ch0_dbg_data_l:32; - }; - uint32_t val; -} h264_dma_in_ch0_dbg_data_l_reg_t; - -/** Type of in_ch0_dbg_data_h register - * in channel 0 debug data register - */ -typedef union { - struct { - /** in_ch0_dbg_data_h : R/W; bitpos: [31:0]; default: 0; - * configures in channel 0 debug data bit 63-32 - */ - uint32_t in_ch0_dbg_data_h:32; - }; - uint32_t val; -} h264_dma_in_ch0_dbg_data_h_reg_t; - -/** Type of in_ch1_dbg_data_l register - * in channel 1 debug data register - */ -typedef union { - struct { - /** in_ch1_dbg_data_l : R/W; bitpos: [31:0]; default: 0; - * configures in channel 1 debug data bit 31-0 - */ - uint32_t in_ch1_dbg_data_l:32; - }; - uint32_t val; -} h264_dma_in_ch1_dbg_data_l_reg_t; - -/** Type of in_ch1_dbg_data_h register - * in channel 1 debug data register - */ -typedef union { - struct { - /** in_ch1_dbg_data_h : R/W; bitpos: [31:0]; default: 0; - * configures in channel 1 debug data bit 63-32 - */ - uint32_t in_ch1_dbg_data_h:32; - }; - uint32_t val; -} h264_dma_in_ch1_dbg_data_h_reg_t; - -/** Type of in_ch2_dbg_data_l register - * in channel 2 debug data register - */ -typedef union { - struct { - /** in_ch2_dbg_data_l : R/W; bitpos: [31:0]; default: 0; - * configures in channel 2 debug data bit 31-0 - */ - uint32_t in_ch2_dbg_data_l:32; - }; - uint32_t val; -} h264_dma_in_ch2_dbg_data_l_reg_t; - -/** Type of in_ch2_dbg_data_h register - * in channel 2 debug data register - */ -typedef union { - struct { - /** in_ch2_dbg_data_h : R/W; bitpos: [31:0]; default: 0; - * configures in channel 2 debug data bit 63-32 - */ - uint32_t in_ch2_dbg_data_h:32; - }; - uint32_t val; -} h264_dma_in_ch2_dbg_data_h_reg_t; - -/** Type of in_ch3_dbg_data_l register - * in channel 3 debug data register - */ -typedef union { - struct { - /** in_ch3_dbg_data_l : R/W; bitpos: [31:0]; default: 0; - * configures in channel 3 debug data bit 31-0 - */ - uint32_t in_ch3_dbg_data_l:32; - }; - uint32_t val; -} h264_dma_in_ch3_dbg_data_l_reg_t; - -/** Type of in_ch3_dbg_data_h register - * in channel 3 debug data register - */ -typedef union { - struct { - /** in_ch3_dbg_data_h : R/W; bitpos: [31:0]; default: 0; - * configures in channel 3 debug data bit 63-32 - */ - uint32_t in_ch3_dbg_data_h:32; - }; - uint32_t val; -} h264_dma_in_ch3_dbg_data_h_reg_t; - -/** Type of in_ch4_dbg_data_l register - * in channel 4 debug data register - */ -typedef union { - struct { - /** in_ch4_dbg_data_l : R/W; bitpos: [31:0]; default: 0; - * configures in channel 4 debug data bit 31-0 - */ - uint32_t in_ch4_dbg_data_l:32; - }; - uint32_t val; -} h264_dma_in_ch4_dbg_data_l_reg_t; - -/** Type of in_ch4_dbg_data_h register - * in channel 4 debug data register - */ -typedef union { - struct { - /** in_ch4_dbg_data_h : R/W; bitpos: [31:0]; default: 0; - * configures in channel 4 debug data bit 63-32 - */ - uint32_t in_ch4_dbg_data_h:32; - }; - uint32_t val; -} h264_dma_in_ch4_dbg_data_h_reg_t; - -/** Type of in_ch5_dbg_data_l register - * in channel 5 debug data register - */ -typedef union { - struct { - /** in_ch5_dbg_data_l : R/W; bitpos: [31:0]; default: 0; - * configures in channel 5 debug data bit 31-0 - */ - uint32_t in_ch5_dbg_data_l:32; - }; - uint32_t val; -} h264_dma_in_ch5_dbg_data_l_reg_t; - -/** Type of in_ch5_dbg_data_h register - * in channel 5 debug data register - */ -typedef union { - struct { - /** in_ch5_dbg_data_h : R/W; bitpos: [31:0]; default: 0; - * configures in channel 5 debug data bit 63-32 - */ - uint32_t in_ch5_dbg_data_h:32; - }; - uint32_t val; -} h264_dma_in_ch5_dbg_data_h_reg_t; - - typedef struct { - volatile h264_dma_out_conf0_ch0_reg_t out_conf0_ch0; - volatile h264_dma_out_int_raw_ch0_reg_t out_int_raw_ch0; - volatile h264_dma_out_int_ena_ch0_reg_t out_int_ena_ch0; - volatile h264_dma_out_int_st_ch0_reg_t out_int_st_ch0; - volatile h264_dma_out_int_clr_ch0_reg_t out_int_clr_ch0; - volatile h264_dma_outfifo_status_ch0_reg_t outfifo_status_ch0; - volatile h264_dma_out_push_ch0_reg_t out_push_ch0; - volatile h264_dma_out_link_conf_ch0_reg_t out_link_conf_ch0; - volatile h264_dma_out_link_addr_ch0_reg_t out_link_addr_ch0; - volatile h264_dma_out_state_ch0_reg_t out_state_ch0; - volatile h264_dma_out_eof_des_addr_ch0_reg_t out_eof_des_addr_ch0; - volatile h264_dma_out_dscr_ch0_reg_t out_dscr_ch0; - volatile h264_dma_out_dscr_bf0_ch0_reg_t out_dscr_bf0_ch0; - volatile h264_dma_out_dscr_bf1_ch0_reg_t out_dscr_bf1_ch0; - uint32_t reserved_038; - volatile h264_dma_out_arb_ch0_reg_t out_arb_ch0; - volatile h264_dma_out_ro_status_ch0_reg_t out_ro_status_ch0; - volatile h264_dma_out_ro_pd_conf_ch0_reg_t out_ro_pd_conf_ch0; - uint32_t reserved_048[2]; - volatile h264_dma_out_mode_enable_ch0_reg_t out_mode_enable_ch0; - volatile h264_dma_out_mode_yuv_ch0_reg_t out_mode_yuv_ch0; - uint32_t reserved_058[4]; - volatile h264_dma_out_etm_conf_ch0_reg_t out_etm_conf_ch0; - uint32_t reserved_06c; - volatile h264_dma_out_buf_len_ch0_reg_t out_buf_len_ch0; - volatile h264_dma_out_fifo_bcnt_ch0_reg_t out_fifo_bcnt_ch0; - volatile h264_dma_out_push_bytecnt_ch0_reg_t out_push_bytecnt_ch0; - volatile h264_dma_out_xaddr_ch0_reg_t out_xaddr_ch0; - uint32_t reserved_080[32]; - volatile h264_dma_out_conf0_ch1_reg_t out_conf0_ch1; - volatile h264_dma_out_int_raw_ch1_reg_t out_int_raw_ch1; - volatile h264_dma_out_int_ena_ch1_reg_t out_int_ena_ch1; - volatile h264_dma_out_int_st_ch1_reg_t out_int_st_ch1; - volatile h264_dma_out_int_clr_ch1_reg_t out_int_clr_ch1; - volatile h264_dma_outfifo_status_ch1_reg_t outfifo_status_ch1; - volatile h264_dma_out_push_ch1_reg_t out_push_ch1; - volatile h264_dma_out_link_conf_ch1_reg_t out_link_conf_ch1; - volatile h264_dma_out_link_addr_ch1_reg_t out_link_addr_ch1; - volatile h264_dma_out_state_ch1_reg_t out_state_ch1; - volatile h264_dma_out_eof_des_addr_ch1_reg_t out_eof_des_addr_ch1; - volatile h264_dma_out_dscr_ch1_reg_t out_dscr_ch1; - volatile h264_dma_out_dscr_bf0_ch1_reg_t out_dscr_bf0_ch1; - volatile h264_dma_out_dscr_bf1_ch1_reg_t out_dscr_bf1_ch1; - uint32_t reserved_138; - volatile h264_dma_out_arb_ch1_reg_t out_arb_ch1; - uint32_t reserved_140[10]; - volatile h264_dma_out_etm_conf_ch1_reg_t out_etm_conf_ch1; - uint32_t reserved_16c; - volatile h264_dma_out_buf_len_ch1_reg_t out_buf_len_ch1; - volatile h264_dma_out_fifo_bcnt_ch1_reg_t out_fifo_bcnt_ch1; - volatile h264_dma_out_push_bytecnt_ch1_reg_t out_push_bytecnt_ch1; - volatile h264_dma_out_xaddr_ch1_reg_t out_xaddr_ch1; - uint32_t reserved_180[32]; - volatile h264_dma_out_conf0_ch2_reg_t out_conf0_ch2; - volatile h264_dma_out_int_raw_ch2_reg_t out_int_raw_ch2; - volatile h264_dma_out_int_ena_ch2_reg_t out_int_ena_ch2; - volatile h264_dma_out_int_st_ch2_reg_t out_int_st_ch2; - volatile h264_dma_out_int_clr_ch2_reg_t out_int_clr_ch2; - volatile h264_dma_outfifo_status_ch2_reg_t outfifo_status_ch2; - volatile h264_dma_out_push_ch2_reg_t out_push_ch2; - volatile h264_dma_out_link_conf_ch2_reg_t out_link_conf_ch2; - volatile h264_dma_out_link_addr_ch2_reg_t out_link_addr_ch2; - volatile h264_dma_out_state_ch2_reg_t out_state_ch2; - volatile h264_dma_out_eof_des_addr_ch2_reg_t out_eof_des_addr_ch2; - volatile h264_dma_out_dscr_ch2_reg_t out_dscr_ch2; - volatile h264_dma_out_dscr_bf0_ch2_reg_t out_dscr_bf0_ch2; - volatile h264_dma_out_dscr_bf1_ch2_reg_t out_dscr_bf1_ch2; - uint32_t reserved_238; - volatile h264_dma_out_arb_ch2_reg_t out_arb_ch2; - uint32_t reserved_240[10]; - volatile h264_dma_out_etm_conf_ch2_reg_t out_etm_conf_ch2; - uint32_t reserved_26c; - volatile h264_dma_out_buf_len_ch2_reg_t out_buf_len_ch2; - volatile h264_dma_out_fifo_bcnt_ch2_reg_t out_fifo_bcnt_ch2; - volatile h264_dma_out_push_bytecnt_ch2_reg_t out_push_bytecnt_ch2; - volatile h264_dma_out_xaddr_ch2_reg_t out_xaddr_ch2; - uint32_t reserved_280[32]; - volatile h264_dma_out_conf0_ch3_reg_t out_conf0_ch3; - volatile h264_dma_out_int_raw_ch3_reg_t out_int_raw_ch3; - volatile h264_dma_out_int_ena_ch3_reg_t out_int_ena_ch3; - volatile h264_dma_out_int_st_ch3_reg_t out_int_st_ch3; - volatile h264_dma_out_int_clr_ch3_reg_t out_int_clr_ch3; - volatile h264_dma_outfifo_status_ch3_reg_t outfifo_status_ch3; - volatile h264_dma_out_push_ch3_reg_t out_push_ch3; - volatile h264_dma_out_link_conf_ch3_reg_t out_link_conf_ch3; - volatile h264_dma_out_link_addr_ch3_reg_t out_link_addr_ch3; - volatile h264_dma_out_state_ch3_reg_t out_state_ch3; - volatile h264_dma_out_eof_des_addr_ch3_reg_t out_eof_des_addr_ch3; - volatile h264_dma_out_dscr_ch3_reg_t out_dscr_ch3; - volatile h264_dma_out_dscr_bf0_ch3_reg_t out_dscr_bf0_ch3; - volatile h264_dma_out_dscr_bf1_ch3_reg_t out_dscr_bf1_ch3; + volatile h264_dma_out_conf0_chn_reg_t conf0; + volatile h264_dma_out_int_raw_chn_reg_t int_raw; + volatile h264_dma_out_int_ena_chn_reg_t int_ena; + volatile h264_dma_out_int_st_chn_reg_t int_st; + volatile h264_dma_out_int_clr_chn_reg_t int_clr; + volatile h264_dma_outfifo_status_reg_t outfifo_status; + volatile h264_dma_out_push_chn_reg_t push; + volatile h264_dma_out_link_conf_chn_reg_t link_conf; + volatile h264_dma_out_link_addr_chn_reg_t link_addr; + volatile h264_dma_out_state_chn_reg_t state; + volatile h264_dma_out_eof_des_addr_chn_reg_t eof_des_addr; + volatile h264_dma_out_dscr_chn_reg_t dscr; + volatile h264_dma_out_dscr_bf0_chn_reg_t dscr_bf0; + volatile h264_dma_out_dscr_bf1_chn_reg_t dscr_bf1; uint32_t reserved_338; - volatile h264_dma_out_arb_ch3_reg_t out_arb_ch3; + volatile h264_dma_out_arb_chn_reg_t arb; uint32_t reserved_340[10]; - volatile h264_dma_out_etm_conf_ch3_reg_t out_etm_conf_ch3; + volatile h264_dma_out_etm_conf_chn_reg_t etm_conf; uint32_t reserved_36c; - volatile h264_dma_out_buf_len_ch3_reg_t out_buf_len_ch3; - volatile h264_dma_out_fifo_bcnt_ch3_reg_t out_fifo_bcnt_ch3; - volatile h264_dma_out_push_bytecnt_ch3_reg_t out_push_bytecnt_ch3; - volatile h264_dma_out_xaddr_ch3_reg_t out_xaddr_ch3; - volatile h264_dma_out_block_buf_len_ch3_reg_t out_block_buf_len_ch3; + volatile h264_dma_out_buf_len_chn_reg_t buf_len; + volatile h264_dma_out_fifo_bcnt_chn_reg_t fifo_bcnt; + volatile h264_dma_out_push_bytecnt_chn_reg_t push_bytecnt; + volatile h264_dma_out_xaddr_chn_reg_t xaddr; + volatile h264_dma_out_block_buf_len_chn_reg_t block_buf_len; // Please note that this reg only exists on out[3] and out[4] uint32_t reserved_384[31]; - volatile h264_dma_out_conf0_ch4_reg_t out_conf0_ch4; - volatile h264_dma_out_int_raw_ch4_reg_t out_int_raw_ch4; - volatile h264_dma_out_int_ena_ch4_reg_t out_int_ena_ch4; - volatile h264_dma_out_int_st_ch4_reg_t out_int_st_ch4; - volatile h264_dma_out_int_clr_ch4_reg_t out_int_clr_ch4; - volatile h264_dma_outfifo_status_ch4_reg_t outfifo_status_ch4; - volatile h264_dma_out_push_ch4_reg_t out_push_ch4; - volatile h264_dma_out_link_conf_ch4_reg_t out_link_conf_ch4; - volatile h264_dma_out_link_addr_ch4_reg_t out_link_addr_ch4; - volatile h264_dma_out_state_ch4_reg_t out_state_ch4; - volatile h264_dma_out_eof_des_addr_ch4_reg_t out_eof_des_addr_ch4; - volatile h264_dma_out_dscr_ch4_reg_t out_dscr_ch4; - volatile h264_dma_out_dscr_bf0_ch4_reg_t out_dscr_bf0_ch4; - volatile h264_dma_out_dscr_bf1_ch4_reg_t out_dscr_bf1_ch4; - uint32_t reserved_438; - volatile h264_dma_out_arb_ch4_reg_t out_arb_ch4; - uint32_t reserved_440[10]; - volatile h264_dma_out_etm_conf_ch4_reg_t out_etm_conf_ch4; - uint32_t reserved_46c; - volatile h264_dma_out_buf_len_ch4_reg_t out_buf_len_ch4; - volatile h264_dma_out_fifo_bcnt_ch4_reg_t out_fifo_bcnt_ch4; - volatile h264_dma_out_push_bytecnt_ch4_reg_t out_push_bytecnt_ch4; - volatile h264_dma_out_xaddr_ch4_reg_t out_xaddr_ch4; - volatile h264_dma_out_block_buf_len_ch4_reg_t out_block_buf_len_ch4; - uint32_t reserved_484[31]; - volatile h264_dma_in_conf0_ch0_reg_t in_conf0_ch0; - volatile h264_dma_in_int_raw_ch0_reg_t in_int_raw_ch0; - volatile h264_dma_in_int_ena_ch0_reg_t in_int_ena_ch0; - volatile h264_dma_in_int_st_ch0_reg_t in_int_st_ch0; - volatile h264_dma_in_int_clr_ch0_reg_t in_int_clr_ch0; - volatile h264_dma_infifo_status_ch0_reg_t infifo_status_ch0; - volatile h264_dma_in_pop_ch0_reg_t in_pop_ch0; - volatile h264_dma_in_link_conf_ch0_reg_t in_link_conf_ch0; - volatile h264_dma_in_link_addr_ch0_reg_t in_link_addr_ch0; - volatile h264_dma_in_state_ch0_reg_t in_state_ch0; - volatile h264_dma_in_suc_eof_des_addr_ch0_reg_t in_suc_eof_des_addr_ch0; - volatile h264_dma_in_err_eof_des_addr_ch0_reg_t in_err_eof_des_addr_ch0; - volatile h264_dma_in_dscr_ch0_reg_t in_dscr_ch0; - volatile h264_dma_in_dscr_bf0_ch0_reg_t in_dscr_bf0_ch0; - volatile h264_dma_in_dscr_bf1_ch0_reg_t in_dscr_bf1_ch0; +} h264_dma_out_chn_regs_t; + +typedef struct { + volatile h264_dma_in_conf0_chn_reg_t conf0; + volatile h264_dma_in_int_raw_chn_reg_t int_raw; + volatile h264_dma_in_int_ena_chn_reg_t int_ena; + volatile h264_dma_in_int_st_chn_reg_t int_st; + volatile h264_dma_in_int_clr_chn_reg_t int_clr; + volatile h264_dma_infifo_status_chn_reg_t infifo_status; + volatile h264_dma_in_pop_chn_reg_t pop; + volatile h264_dma_in_link_conf_chn_reg_t link_conf; + volatile h264_dma_in_link_addr_chn_reg_t link_addr; + volatile h264_dma_in_state_chn_reg_t state; + volatile h264_dma_in_suc_eof_des_addr_chn_reg_t suc_eof_des_addr; + volatile h264_dma_in_err_eof_des_addr_chn_reg_t err_eof_des_addr; + volatile h264_dma_in_dscr_chn_reg_t dscr; + volatile h264_dma_in_dscr_bf0_chn_reg_t dscr_bf0; + volatile h264_dma_in_dscr_bf1_chn_reg_t dscr_bf1; uint32_t reserved_53c; - volatile h264_dma_in_arb_ch0_reg_t in_arb_ch0; + volatile h264_dma_in_arb_chn_reg_t arb; uint32_t reserved_544; - volatile h264_dma_in_ro_pd_conf_ch0_reg_t in_ro_pd_conf_ch0; + volatile h264_dma_in_ro_pd_conf_chn_reg_t ro_pd_conf; uint32_t reserved_54c[8]; - volatile h264_dma_in_etm_conf_ch0_reg_t in_etm_conf_ch0; + volatile h264_dma_in_etm_conf_chn_reg_t etm_conf; uint32_t reserved_570[4]; - volatile h264_dma_in_fifo_cnt_ch0_reg_t in_fifo_cnt_ch0; - volatile h264_dma_in_pop_data_cnt_ch0_reg_t in_pop_data_cnt_ch0; - volatile h264_dma_in_xaddr_ch0_reg_t in_xaddr_ch0; - volatile h264_dma_in_buf_hb_rcv_ch0_reg_t in_buf_hb_rcv_ch0; + volatile h264_dma_in_fifo_cnt_chn_reg_t fifo_cnt; + volatile h264_dma_in_pop_data_cnt_chn_reg_t pop_data_cnt; + volatile h264_dma_in_xaddr_chn_reg_t xaddr; + volatile h264_dma_in_buf_hb_rcv_chn_reg_t buf_hb_rcv; uint32_t reserved_590[28]; - volatile h264_dma_in_conf0_ch1_reg_t in_conf0_ch1; - volatile h264_dma_in_int_raw_ch1_reg_t in_int_raw_ch1; - volatile h264_dma_in_int_ena_ch1_reg_t in_int_ena_ch1; - volatile h264_dma_in_int_st_ch1_reg_t in_int_st_ch1; - volatile h264_dma_in_int_clr_ch1_reg_t in_int_clr_ch1; - volatile h264_dma_infifo_status_ch1_reg_t infifo_status_ch1; - volatile h264_dma_in_pop_ch1_reg_t in_pop_ch1; - volatile h264_dma_in_link_conf_ch1_reg_t in_link_conf_ch1; - volatile h264_dma_in_link_addr_ch1_reg_t in_link_addr_ch1; - volatile h264_dma_in_state_ch1_reg_t in_state_ch1; - volatile h264_dma_in_suc_eof_des_addr_ch1_reg_t in_suc_eof_des_addr_ch1; - volatile h264_dma_in_err_eof_des_addr_ch1_reg_t in_err_eof_des_addr_ch1; - volatile h264_dma_in_dscr_ch1_reg_t in_dscr_ch1; - volatile h264_dma_in_dscr_bf0_ch1_reg_t in_dscr_bf0_ch1; - volatile h264_dma_in_dscr_bf1_ch1_reg_t in_dscr_bf1_ch1; - uint32_t reserved_63c; - volatile h264_dma_in_arb_ch1_reg_t in_arb_ch1; - uint32_t reserved_644; - volatile h264_dma_in_etm_conf_ch1_reg_t in_etm_conf_ch1; - uint32_t reserved_64c[13]; - volatile h264_dma_in_fifo_cnt_ch1_reg_t in_fifo_cnt_ch1; - volatile h264_dma_in_pop_data_cnt_ch1_reg_t in_pop_data_cnt_ch1; - volatile h264_dma_in_xaddr_ch1_reg_t in_xaddr_ch1; - volatile h264_dma_in_buf_hb_rcv_ch1_reg_t in_buf_hb_rcv_ch1; - uint32_t reserved_690[28]; - volatile h264_dma_in_conf0_ch2_reg_t in_conf0_ch2; - volatile h264_dma_in_int_raw_ch2_reg_t in_int_raw_ch2; - volatile h264_dma_in_int_ena_ch2_reg_t in_int_ena_ch2; - volatile h264_dma_in_int_st_ch2_reg_t in_int_st_ch2; - volatile h264_dma_in_int_clr_ch2_reg_t in_int_clr_ch2; - volatile h264_dma_infifo_status_ch2_reg_t infifo_status_ch2; - volatile h264_dma_in_pop_ch2_reg_t in_pop_ch2; - volatile h264_dma_in_link_conf_ch2_reg_t in_link_conf_ch2; - volatile h264_dma_in_link_addr_ch2_reg_t in_link_addr_ch2; - volatile h264_dma_in_state_ch2_reg_t in_state_ch2; - volatile h264_dma_in_suc_eof_des_addr_ch2_reg_t in_suc_eof_des_addr_ch2; - volatile h264_dma_in_err_eof_des_addr_ch2_reg_t in_err_eof_des_addr_ch2; - volatile h264_dma_in_dscr_ch2_reg_t in_dscr_ch2; - volatile h264_dma_in_dscr_bf0_ch2_reg_t in_dscr_bf0_ch2; - volatile h264_dma_in_dscr_bf1_ch2_reg_t in_dscr_bf1_ch2; - uint32_t reserved_73c; - volatile h264_dma_in_arb_ch2_reg_t in_arb_ch2; - uint32_t reserved_744; - volatile h264_dma_in_etm_conf_ch2_reg_t in_etm_conf_ch2; - uint32_t reserved_74c[13]; - volatile h264_dma_in_fifo_cnt_ch2_reg_t in_fifo_cnt_ch2; - volatile h264_dma_in_pop_data_cnt_ch2_reg_t in_pop_data_cnt_ch2; - volatile h264_dma_in_xaddr_ch2_reg_t in_xaddr_ch2; - volatile h264_dma_in_buf_hb_rcv_ch2_reg_t in_buf_hb_rcv_ch2; - uint32_t reserved_790[28]; - volatile h264_dma_in_conf0_ch3_reg_t in_conf0_ch3; - volatile h264_dma_in_int_raw_ch3_reg_t in_int_raw_ch3; - volatile h264_dma_in_int_ena_ch3_reg_t in_int_ena_ch3; - volatile h264_dma_in_int_st_ch3_reg_t in_int_st_ch3; - volatile h264_dma_in_int_clr_ch3_reg_t in_int_clr_ch3; - volatile h264_dma_infifo_status_ch3_reg_t infifo_status_ch3; - volatile h264_dma_in_pop_ch3_reg_t in_pop_ch3; - volatile h264_dma_in_link_conf_ch3_reg_t in_link_conf_ch3; - volatile h264_dma_in_link_addr_ch3_reg_t in_link_addr_ch3; - volatile h264_dma_in_state_ch3_reg_t in_state_ch3; - volatile h264_dma_in_suc_eof_des_addr_ch3_reg_t in_suc_eof_des_addr_ch3; - volatile h264_dma_in_err_eof_des_addr_ch3_reg_t in_err_eof_des_addr_ch3; - volatile h264_dma_in_dscr_ch3_reg_t in_dscr_ch3; - volatile h264_dma_in_dscr_bf0_ch3_reg_t in_dscr_bf0_ch3; - volatile h264_dma_in_dscr_bf1_ch3_reg_t in_dscr_bf1_ch3; - uint32_t reserved_83c; - volatile h264_dma_in_arb_ch3_reg_t in_arb_ch3; - uint32_t reserved_844; - volatile h264_dma_in_etm_conf_ch3_reg_t in_etm_conf_ch3; - uint32_t reserved_84c[13]; - volatile h264_dma_in_fifo_cnt_ch3_reg_t in_fifo_cnt_ch3; - volatile h264_dma_in_pop_data_cnt_ch3_reg_t in_pop_data_cnt_ch3; - volatile h264_dma_in_xaddr_ch3_reg_t in_xaddr_ch3; - volatile h264_dma_in_buf_hb_rcv_ch3_reg_t in_buf_hb_rcv_ch3; - uint32_t reserved_890[28]; - volatile h264_dma_in_conf0_ch4_reg_t in_conf0_ch4; - volatile h264_dma_in_int_raw_ch4_reg_t in_int_raw_ch4; - volatile h264_dma_in_int_ena_ch4_reg_t in_int_ena_ch4; - volatile h264_dma_in_int_st_ch4_reg_t in_int_st_ch4; - volatile h264_dma_in_int_clr_ch4_reg_t in_int_clr_ch4; - volatile h264_dma_infifo_status_ch4_reg_t infifo_status_ch4; - volatile h264_dma_in_pop_ch4_reg_t in_pop_ch4; - volatile h264_dma_in_link_conf_ch4_reg_t in_link_conf_ch4; - volatile h264_dma_in_link_addr_ch4_reg_t in_link_addr_ch4; - volatile h264_dma_in_state_ch4_reg_t in_state_ch4; - volatile h264_dma_in_suc_eof_des_addr_ch4_reg_t in_suc_eof_des_addr_ch4; - volatile h264_dma_in_err_eof_des_addr_ch4_reg_t in_err_eof_des_addr_ch4; - volatile h264_dma_in_dscr_ch4_reg_t in_dscr_ch4; - volatile h264_dma_in_dscr_bf0_ch4_reg_t in_dscr_bf0_ch4; - volatile h264_dma_in_dscr_bf1_ch4_reg_t in_dscr_bf1_ch4; - uint32_t reserved_93c; - volatile h264_dma_in_arb_ch4_reg_t in_arb_ch4; - uint32_t reserved_944; - volatile h264_dma_in_etm_conf_ch4_reg_t in_etm_conf_ch4; - uint32_t reserved_94c[13]; - volatile h264_dma_in_fifo_cnt_ch4_reg_t in_fifo_cnt_ch4; - volatile h264_dma_in_pop_data_cnt_ch4_reg_t in_pop_data_cnt_ch4; - volatile h264_dma_in_xaddr_ch4_reg_t in_xaddr_ch4; - volatile h264_dma_in_buf_hb_rcv_ch4_reg_t in_buf_hb_rcv_ch4; - uint32_t reserved_990[28]; - volatile h264_dma_in_conf0_ch5_reg_t in_conf0_ch5; - volatile h264_dma_in_conf1_ch5_reg_t in_conf1_ch5; - volatile h264_dma_in_conf2_ch5_reg_t in_conf2_ch5; - volatile h264_dma_in_conf3_ch5_reg_t in_conf3_ch5; - volatile h264_dma_in_int_raw_ch5_reg_t in_int_raw_ch5; - volatile h264_dma_in_int_ena_ch5_reg_t in_int_ena_ch5; - volatile h264_dma_in_int_st_ch5_reg_t in_int_st_ch5; - volatile h264_dma_in_int_clr_ch5_reg_t in_int_clr_ch5; - volatile h264_dma_infifo_status_ch5_reg_t infifo_status_ch5; - volatile h264_dma_in_pop_ch5_reg_t in_pop_ch5; - volatile h264_dma_in_state_ch5_reg_t in_state_ch5; +} h264_dma_in_chn_regs_t; + +typedef struct { + volatile h264_dma_in_conf0_ch5_reg_t conf0; + volatile h264_dma_in_conf1_ch5_reg_t conf1; + volatile h264_dma_in_conf2_ch5_reg_t conf2; + volatile h264_dma_in_conf3_ch5_reg_t conf3; + volatile h264_dma_in_int_raw_ch5_reg_t int_raw; + volatile h264_dma_in_int_ena_ch5_reg_t int_ena; + volatile h264_dma_in_int_st_ch5_reg_t int_st; + volatile h264_dma_in_int_clr_ch5_reg_t int_clr; + volatile h264_dma_infifo_status_ch5_reg_t infifo_status; + volatile h264_dma_in_pop_ch5_reg_t pop; + volatile h264_dma_in_state_ch5_reg_t state; uint32_t reserved_a2c[5]; - volatile h264_dma_in_arb_ch5_reg_t in_arb_ch5; + volatile h264_dma_in_arb_ch5_reg_t arb; uint32_t reserved_a44[15]; - volatile h264_dma_in_fifo_cnt_ch5_reg_t in_fifo_cnt_ch5; - volatile h264_dma_in_pop_data_cnt_ch5_reg_t in_pop_data_cnt_ch5; - volatile h264_dma_in_xaddr_ch5_reg_t in_xaddr_ch5; - volatile h264_dma_in_buf_hb_rcv_ch5_reg_t in_buf_hb_rcv_ch5; + volatile h264_dma_in_fifo_cnt_ch5_reg_t fifo_cnt; + volatile h264_dma_in_pop_data_cnt_ch5_reg_t pop_data_cnt; + volatile h264_dma_in_xaddr_ch5_reg_t xaddr; + volatile h264_dma_in_buf_hb_rcv_ch5_reg_t buf_hb_rcv; uint32_t reserved_a90[28]; +} h264_dma_in_ch5_regs_t; + +typedef struct { + volatile h264_dma_mem_start_addr_reg_t start; + volatile h264_dma_mem_end_addr_reg_t end; +} h264_dma_mem_addr_reg_t; + +typedef struct { + volatile h264_dma_out_chn_regs_t dma_out_ch[5]; + volatile h264_dma_in_chn_regs_t dma_in_ch[5]; + volatile h264_dma_in_ch5_regs_t dma_in_ch5; volatile h264_dma_inter_axi_err_reg_t inter_axi_err; volatile h264_dma_exter_axi_err_reg_t exter_axi_err; volatile h264_dma_rst_conf_reg_t rst_conf; - volatile h264_dma_inter_mem_start_addr0_reg_t inter_mem_start_addr0; - volatile h264_dma_inter_mem_end_addr0_reg_t inter_mem_end_addr0; - volatile h264_dma_inter_mem_start_addr1_reg_t inter_mem_start_addr1; - volatile h264_dma_inter_mem_end_addr1_reg_t inter_mem_end_addr1; + volatile h264_dma_mem_addr_reg_t inter_mem_addr[2]; uint32_t reserved_b1c; - volatile h264_dma_exter_mem_start_addr0_reg_t exter_mem_start_addr0; - volatile h264_dma_exter_mem_end_addr0_reg_t exter_mem_end_addr0; - volatile h264_dma_exter_mem_start_addr1_reg_t exter_mem_start_addr1; - volatile h264_dma_exter_mem_end_addr1_reg_t exter_mem_end_addr1; - volatile h264_dma_out_arb_config_reg_t out_arb_config; - volatile h264_dma_in_arb_config_reg_t in_arb_config; + volatile h264_dma_mem_addr_reg_t exter_mem_addr[2]; + volatile h264_dma_arb_config_reg_t out_arb_config; + volatile h264_dma_arb_config_reg_t in_arb_config; uint32_t reserved_b38; volatile h264_dma_date_reg_t date; uint32_t reserved_b40[4]; @@ -7040,33 +1890,9 @@ typedef struct { volatile h264_dma_rx_ch2_counter_reg_t rx_ch2_counter; volatile h264_dma_rx_ch5_counter_reg_t rx_ch5_counter; volatile h264_dma_pbyte_reg_t pbyte; - volatile h264_dma_ch_dbg_en_reg_t ch_dbg_en; - volatile h264_dma_out_ch0_dbg_data_l_reg_t out_ch0_dbg_data_l; - volatile h264_dma_out_ch0_dbg_data_h_reg_t out_ch0_dbg_data_h; - volatile h264_dma_out_ch1_dbg_data_l_reg_t out_ch1_dbg_data_l; - volatile h264_dma_out_ch1_dbg_data_h_reg_t out_ch1_dbg_data_h; - volatile h264_dma_out_ch2_dbg_data_l_reg_t out_ch2_dbg_data_l; - volatile h264_dma_out_ch2_dbg_data_h_reg_t out_ch2_dbg_data_h; - volatile h264_dma_out_ch3_dbg_data_l_reg_t out_ch3_dbg_data_l; - volatile h264_dma_out_ch3_dbg_data_h_reg_t out_ch3_dbg_data_h; - volatile h264_dma_out_ch4_dbg_data_l_reg_t out_ch4_dbg_data_l; - volatile h264_dma_out_ch4_dbg_data_h_reg_t out_ch4_dbg_data_h; - volatile h264_dma_in_ch0_dbg_data_l_reg_t in_ch0_dbg_data_l; - volatile h264_dma_in_ch0_dbg_data_h_reg_t in_ch0_dbg_data_h; - volatile h264_dma_in_ch1_dbg_data_l_reg_t in_ch1_dbg_data_l; - volatile h264_dma_in_ch1_dbg_data_h_reg_t in_ch1_dbg_data_h; - volatile h264_dma_in_ch2_dbg_data_l_reg_t in_ch2_dbg_data_l; - volatile h264_dma_in_ch2_dbg_data_h_reg_t in_ch2_dbg_data_h; - volatile h264_dma_in_ch3_dbg_data_l_reg_t in_ch3_dbg_data_l; - volatile h264_dma_in_ch3_dbg_data_h_reg_t in_ch3_dbg_data_h; - volatile h264_dma_in_ch4_dbg_data_l_reg_t in_ch4_dbg_data_l; - volatile h264_dma_in_ch4_dbg_data_h_reg_t in_ch4_dbg_data_h; - volatile h264_dma_in_ch5_dbg_data_l_reg_t in_ch5_dbg_data_l; - volatile h264_dma_in_ch5_dbg_data_h_reg_t in_ch5_dbg_data_h; + uint32_t debug_regs[23]; } h264_dma_dev_t; -extern h264_dma_dev_t H264_DMA; - #ifndef __cplusplus _Static_assert(sizeof(h264_dma_dev_t) == 0xbc4, "Invalid size of h264_dma_dev_t structure"); #endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/h264_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/h264_struct.h index 81d4832dec59..29915034fe56 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/h264_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/h264_struct.h @@ -17,32 +17,28 @@ extern "C" { typedef union { struct { /** frame_start : WT; bitpos: [0]; default: 0; - * Configures whether or not to start encoding one frame. - * 0: Invalid. No effect - * 1: Start encoding one frame + * Configures whether or not to start encoding one frame.\\0: Invalid. No effect\\1: + * Start encoding one frame */ - uint32_t frame_start:1; + uint32_t frame_start: 1; /** dma_move_start : WT; bitpos: [1]; default: 0; - * Configures whether or not to start moving reference data from external mem. - * 0: Invalid. No effect - * 1: H264 start moving two MB lines of reference frame from external mem to internal - * mem + * Configures whether or not to start moving reference data from external mem.\\0: + * Invalid. No effect\\1: H264 start moving two MB lines of reference frame from + * external mem to internal mem */ - uint32_t dma_move_start:1; + uint32_t dma_move_start: 1; /** frame_mode : R/W; bitpos: [2]; default: 0; * Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this - * field must be set to 1 too. - * 0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA - * 1: Frame mode. Before every frame start, need reconfig reference frame DMA + * field must be set to 1 too.\\0: GOP mode. Before every GOP first frame start, need + * reconfig reference frame DMA\\1: Frame mode. Before every frame start, need + * reconfig reference frame DMA */ - uint32_t frame_mode:1; + uint32_t frame_mode: 1; /** sys_rst_pulse : WT; bitpos: [3]; default: 0; - * Configures whether or not to reset H264 ip. - * 0: Invalid. No effect - * 1: Reset H264 ip + * Configures whether or not to reset H264 ip.\\0: Invalid. No effect\\1: Reset H264 ip */ - uint32_t sys_rst_pulse:1; - uint32_t reserved_4:28; + uint32_t sys_rst_pulse: 1; + uint32_t reserved_4: 28; }; uint32_t val; } h264_sys_ctrl_reg_t; @@ -54,1073 +50,299 @@ typedef union { struct { /** dual_stream_mode : R/W; bitpos: [0]; default: 0; * Configures whether or not to enable dual stream mode. When this field is set to 1, - * H264_FRAME_MODE field must be set to 1 too. - * 0: Normal mode - * 1: Dual stream mode + * H264_FRAME_MODE field must be set to 1 too.\\0: Normal mode\\1: Dual stream mode */ - uint32_t dual_stream_mode:1; + uint32_t dual_stream_mode: 1; /** gop_num : R/W; bitpos: [8:1]; default: 0; - * Configures the frame number of one GOP. - * 0: The frame number of one GOP is infinite - * Others: Actual frame number of one GOP + * Configures the frame number of one GOP.\\0: The frame number of one GOP is + * infinite\\Others: Actual frame number of one GOP */ - uint32_t gop_num:8; - uint32_t reserved_9:23; + uint32_t gop_num: 8; + uint32_t reserved_9: 23; }; uint32_t val; } h264_gop_conf_reg_t; -/** Type of a_sys_mb_res register +/** Type of sys_mb_res register * Video A horizontal and vertical MB resolution register. */ typedef union { struct { - /** a_sys_total_mb_y : R/W; bitpos: [6:0]; default: 0; + /** sys_total_mb_y : R/W; bitpos: [6:0]; default: 0; * Configures video A vertical MB resolution. */ - uint32_t a_sys_total_mb_y:7; - /** a_sys_total_mb_x : R/W; bitpos: [13:7]; default: 0; + uint32_t sys_total_mb_y: 7; + /** sys_total_mb_x : R/W; bitpos: [13:7]; default: 0; * Configures video A horizontal MB resolution. */ - uint32_t a_sys_total_mb_x:7; - uint32_t reserved_14:18; + uint32_t sys_total_mb_x: 7; + uint32_t reserved_14: 18; }; uint32_t val; -} h264_a_sys_mb_res_reg_t; +} h264_sys_mb_res_reg_t; -/** Type of a_sys_conf register +/** Type of sys_conf register * Video A system level configuration register. */ typedef union { struct { - /** a_db_tmp_ready_trigger_mb_num : R/W; bitpos: [6:0]; default: 3; + /** db_tmp_ready_trigger_mb_num : R/W; bitpos: [6:0]; default: 3; * Configures when to trigger video A H264_DB_TMP_READY_INT. When the (MB number of * written db temp+1) is greater than this filed in first MB line, trigger * H264_DB_TMP_READY_INT. Min is 3. */ - uint32_t a_db_tmp_ready_trigger_mb_num:7; - /** a_rec_ready_trigger_mb_lines : R/W; bitpos: [13:7]; default: 4; + uint32_t db_tmp_ready_trigger_mb_num: 7; + /** rec_ready_trigger_mb_lines : R/W; bitpos: [13:7]; default: 4; * Configures when to trigger video A H264_REC_READY_INT. When the MB line number of * generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. * Min is 4. */ - uint32_t a_rec_ready_trigger_mb_lines:7; - /** a_intra_cost_cmp_offset : R/W; bitpos: [29:14]; default: 0; + uint32_t rec_ready_trigger_mb_lines: 7; + /** intra_cost_cmp_offset : R/W; bitpos: [29:14]; default: 0; * Configures video A intra cost offset when I MB compared with P MB. */ - uint32_t a_intra_cost_cmp_offset:16; - uint32_t reserved_30:2; + uint32_t intra_cost_cmp_offset: 16; + uint32_t reserved_30: 2; }; uint32_t val; -} h264_a_sys_conf_reg_t; +} h264_sys_conf_reg_t; -/** Type of a_deci_score register +/** Type of deci_score register * Video A luma and chroma MB decimate score Register. */ typedef union { struct { - /** a_c_deci_score : R/W; bitpos: [9:0]; default: 0; + /** c_deci_score : R/W; bitpos: [9:0]; default: 0; * Configures video A chroma MB decimate score. When chroma score is smaller than it, * chroma decimate will be enable. */ - uint32_t a_c_deci_score:10; - /** a_l_deci_score : R/W; bitpos: [19:10]; default: 0; + uint32_t c_deci_score: 10; + /** l_deci_score : R/W; bitpos: [19:10]; default: 0; * Configures video A luma MB decimate score. When luma score is smaller than it, luma * decimate will be enable. */ - uint32_t a_l_deci_score:10; - uint32_t reserved_20:12; + uint32_t l_deci_score: 10; + uint32_t reserved_20: 12; }; uint32_t val; -} h264_a_deci_score_reg_t; +} h264_deci_score_reg_t; -/** Type of a_deci_score_offset register +/** Type of deci_score_offset register * Video A luma and chroma MB decimate score offset Register. */ typedef union { struct { - /** a_i16x16_deci_score_offset : R/W; bitpos: [5:0]; default: 0; + /** i16x16_deci_score_offset : R/W; bitpos: [5:0]; default: 0; * Configures video A i16x16 MB decimate score offset. This offset will be added to * i16x16 MB score. */ - uint32_t a_i16x16_deci_score_offset:6; - /** a_i_chroma_deci_score_offset : R/W; bitpos: [11:6]; default: 0; + uint32_t i16x16_deci_score_offset: 6; + /** i_chroma_deci_score_offset : R/W; bitpos: [11:6]; default: 0; * Configures video A I chroma MB decimate score offset. This offset will be added to * I chroma MB score. */ - uint32_t a_i_chroma_deci_score_offset:6; - /** a_p16x16_deci_score_offset : R/W; bitpos: [17:12]; default: 0; + uint32_t i_chroma_deci_score_offset: 6; + /** p16x16_deci_score_offset : R/W; bitpos: [17:12]; default: 0; * Configures video A p16x16 MB decimate score offset. This offset will be added to * p16x16 MB score. */ - uint32_t a_p16x16_deci_score_offset:6; - /** a_p_chroma_deci_score_offset : R/W; bitpos: [23:18]; default: 0; + uint32_t p16x16_deci_score_offset: 6; + /** p_chroma_deci_score_offset : R/W; bitpos: [23:18]; default: 0; * Configures video A p chroma MB decimate score offset. This offset will be added to * p chroma MB score. */ - uint32_t a_p_chroma_deci_score_offset:6; - uint32_t reserved_24:8; + uint32_t p_chroma_deci_score_offset: 6; + uint32_t reserved_24: 8; }; uint32_t val; -} h264_a_deci_score_offset_reg_t; +} h264_deci_score_offset_reg_t; -/** Type of a_rc_conf0 register +/** Type of rc_conf0 register * Video A rate control configuration register0. */ typedef union { struct { - /** a_qp : R/W; bitpos: [5:0]; default: 0; + /** qp : R/W; bitpos: [5:0]; default: 0; * Configures video A frame level initial luma QP value. */ - uint32_t a_qp:6; - /** a_rate_ctrl_u : R/W; bitpos: [21:6]; default: 0; + uint32_t qp: 6; + /** rate_ctrl_u : R/W; bitpos: [21:6]; default: 0; * Configures video A parameter U value. U = int((float) u << 8). */ - uint32_t a_rate_ctrl_u:16; - /** a_mb_rate_ctrl_en : R/W; bitpos: [22]; default: 0; - * Configures video A whether or not to open macro block rate ctrl. - * 1:Open the macro block rate ctrl - * 1:Close the macro block rate ctrl. + uint32_t rate_ctrl_u: 16; + /** mb_rate_ctrl_en : R/W; bitpos: [22]; default: 0; + * Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro + * block rate ctrl\\1:Close the macro block rate ctrl. */ - uint32_t a_mb_rate_ctrl_en:1; - uint32_t reserved_23:9; + uint32_t mb_rate_ctrl_en: 1; + uint32_t reserved_23: 9; }; uint32_t val; -} h264_a_rc_conf0_reg_t; +} h264_rc_conf0_reg_t; -/** Type of a_rc_conf1 register +/** Type of rc_conf1 register * Video A rate control configuration register1. */ typedef union { struct { - /** a_chroma_dc_qp_delta : R/W; bitpos: [2:0]; default: 0; + /** chroma_dc_qp_delta : R/W; bitpos: [2:0]; default: 0; * Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma * QP(after map) + reg_chroma_dc_qp_delta. */ - uint32_t a_chroma_dc_qp_delta:3; - /** a_chroma_qp_delta : R/W; bitpos: [6:3]; default: 0; + uint32_t chroma_dc_qp_delta: 3; + /** chroma_qp_delta : R/W; bitpos: [6:3]; default: 0; * Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma * QP + reg_chroma_qp_delta. */ - uint32_t a_chroma_qp_delta:4; - /** a_qp_min : R/W; bitpos: [12:7]; default: 0; + uint32_t chroma_qp_delta: 4; + /** qp_min : R/W; bitpos: [12:7]; default: 0; * Configures video A allowed luma QP min value. */ - uint32_t a_qp_min:6; - /** a_qp_max : R/W; bitpos: [18:13]; default: 0; + uint32_t qp_min: 6; + /** qp_max : R/W; bitpos: [18:13]; default: 0; * Configures video A allowed luma QP max value. */ - uint32_t a_qp_max:6; - /** a_mad_frame_pred : R/W; bitpos: [30:19]; default: 0; + uint32_t qp_max: 6; + /** mad_frame_pred : R/W; bitpos: [30:19]; default: 0; * Configures vdieo A frame level predicted MB MAD value. */ - uint32_t a_mad_frame_pred:12; - uint32_t reserved_31:1; + uint32_t mad_frame_pred: 12; + uint32_t reserved_31: 1; }; uint32_t val; -} h264_a_rc_conf1_reg_t; +} h264_rc_conf1_reg_t; -/** Type of a_db_bypass register +/** Type of db_bypass register * Video A Deblocking bypass register */ typedef union { struct { - /** a_bypass_db_filter : R/W; bitpos: [0]; default: 0; - * Configures whether or not to bypass video A deblcoking filter. - * 0: Open the deblock filter - * 1: Close the deblock filter + /** bypass_db_filter : R/W; bitpos: [0]; default: 0; + * Configures whether or not to bypass video A deblcoking filter. \\0: Open the + * deblock filter\\1: Close the deblock filter */ - uint32_t a_bypass_db_filter:1; - uint32_t reserved_1:31; + uint32_t bypass_db_filter: 1; + uint32_t reserved_1: 31; }; uint32_t val; -} h264_a_db_bypass_reg_t; +} h264_db_bypass_reg_t; -/** Type of a_roi_region0 register - * Video A H264 ROI region0 range configure register. +/** Type of roi_region register + * Video A H264 ROI region range configure register. */ typedef union { struct { - /** a_roi_region0_x : R/W; bitpos: [6:0]; default: 0; + /** roi_region_x : R/W; bitpos: [6:0]; default: 0; * Configures the horizontal start macroblocks of region 0 in Video A. */ - uint32_t a_roi_region0_x:7; - /** a_roi_region0_y : R/W; bitpos: [13:7]; default: 0; + uint32_t roi_region_x: 7; + /** roi_region_y : R/W; bitpos: [13:7]; default: 0; * Configures the vertical start macroblocks of region 0 in Video A. */ - uint32_t a_roi_region0_y:7; - /** a_roi_region0_x_len : R/W; bitpos: [20:14]; default: 0; + uint32_t roi_region_y: 7; + /** roi_region_x_len : R/W; bitpos: [20:14]; default: 0; * Configures the number of macroblocks in horizontal direction of the region 0 in * Video A. */ - uint32_t a_roi_region0_x_len:7; - /** a_roi_region0_y_len : R/W; bitpos: [27:21]; default: 0; + uint32_t roi_region_x_len: 7; + /** roi_region_y_len : R/W; bitpos: [27:21]; default: 0; * Configures the number of macroblocks in vertical direction of the region 0 in * Video A. */ - uint32_t a_roi_region0_y_len:7; - /** a_roi_region0_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video A ROI of region 0 . - * 0:Close ROI - * 1:Open ROI. + uint32_t roi_region_y_len: 7; + /** roi_region_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to open Video A ROI of region 0 .\\0:Close ROI\\1:Open + * ROI. */ - uint32_t a_roi_region0_en:1; - uint32_t reserved_29:3; + uint32_t roi_region_en: 1; + uint32_t reserved_29: 3; }; uint32_t val; -} h264_a_roi_region0_reg_t; +} h264_roi_region_reg_t; -/** Type of a_roi_region1 register - * Video A H264 ROI region1 range configure register. - */ -typedef union { - struct { - /** a_roi_region1_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 1 in Video A. - */ - uint32_t a_roi_region1_x:7; - /** a_roi_region1_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 1 in Video A. - */ - uint32_t a_roi_region1_y:7; - /** a_roi_region1_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 1 in - * Video A. - */ - uint32_t a_roi_region1_x_len:7; - /** a_roi_region1_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 1 in - * Video A. - */ - uint32_t a_roi_region1_y_len:7; - /** a_roi_region1_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video A ROI of region 1 . - * 0:Close ROI - * 1:Open ROI. - */ - uint32_t a_roi_region1_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_a_roi_region1_reg_t; - -/** Type of a_roi_region2 register - * Video A H264 ROI region2 range configure register. - */ -typedef union { - struct { - /** a_roi_region2_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 2 in Video A. - */ - uint32_t a_roi_region2_x:7; - /** a_roi_region2_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 2 in Video A. - */ - uint32_t a_roi_region2_y:7; - /** a_roi_region2_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 2 in - * Video A. - */ - uint32_t a_roi_region2_x_len:7; - /** a_roi_region2_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 2 in - * Video A. - */ - uint32_t a_roi_region2_y_len:7; - /** a_roi_region2_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video A ROI of region 2 . - * 0:Close ROI - * 1:Open ROI. - */ - uint32_t a_roi_region2_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_a_roi_region2_reg_t; - -/** Type of a_roi_region3 register - * Video A H264 ROI region3 range configure register. - */ -typedef union { - struct { - /** a_roi_region3_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 3 in Video A. - */ - uint32_t a_roi_region3_x:7; - /** a_roi_region3_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 3 in Video A. - */ - uint32_t a_roi_region3_y:7; - /** a_roi_region3_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 3 in - * video A. - */ - uint32_t a_roi_region3_x_len:7; - /** a_roi_region3_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 3 in - * video A. - */ - uint32_t a_roi_region3_y_len:7; - /** a_roi_region3_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video A ROI of region 3 . - * 0:Close ROI - * 1:Open ROI. - */ - uint32_t a_roi_region3_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_a_roi_region3_reg_t; - -/** Type of a_roi_region4 register - * Video A H264 ROI region4 range configure register. - */ -typedef union { - struct { - /** a_roi_region4_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 4 in Video A. - */ - uint32_t a_roi_region4_x:7; - /** a_roi_region4_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 4 in Video A. - */ - uint32_t a_roi_region4_y:7; - /** a_roi_region4_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 4 in - * video A. - */ - uint32_t a_roi_region4_x_len:7; - /** a_roi_region4_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 4 in - * video A. - */ - uint32_t a_roi_region4_y_len:7; - /** a_roi_region4_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video A ROI of region 4 . - * 0:Close ROI - * 1:Open ROI. - */ - uint32_t a_roi_region4_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_a_roi_region4_reg_t; - -/** Type of a_roi_region5 register - * Video A H264 ROI region5 range configure register. - */ -typedef union { - struct { - /** a_roi_region5_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontial start macroblocks of region 5 video A. - */ - uint32_t a_roi_region5_x:7; - /** a_roi_region5_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 5 video A. - */ - uint32_t a_roi_region5_y:7; - /** a_roi_region5_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 5 - * video A. - */ - uint32_t a_roi_region5_x_len:7; - /** a_roi_region5_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 5 in - * video A. - */ - uint32_t a_roi_region5_y_len:7; - /** a_roi_region5_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video A ROI of region 5 . - * 0:Close ROI - * 1:Open ROI. - */ - uint32_t a_roi_region5_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_a_roi_region5_reg_t; - -/** Type of a_roi_region6 register - * Video A H264 ROI region6 range configure register. - */ -typedef union { - struct { - /** a_roi_region6_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontial start macroblocks of region 6 video A. - */ - uint32_t a_roi_region6_x:7; - /** a_roi_region6_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 6 in video A. - */ - uint32_t a_roi_region6_y:7; - /** a_roi_region6_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 6 in - * video A. - */ - uint32_t a_roi_region6_x_len:7; - /** a_roi_region6_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 6 in - * video A. - */ - uint32_t a_roi_region6_y_len:7; - /** a_roi_region6_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video A ROI of region 6 . - * 0:Close ROI - * 1:Open ROI. - */ - uint32_t a_roi_region6_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_a_roi_region6_reg_t; - -/** Type of a_roi_region7 register - * Video A H264 ROI region7 range configure register. - */ -typedef union { - struct { - /** a_roi_region7_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 7 in video A. - */ - uint32_t a_roi_region7_x:7; - /** a_roi_region7_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 7 in video A. - */ - uint32_t a_roi_region7_y:7; - /** a_roi_region7_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 7 in - * video A. - */ - uint32_t a_roi_region7_x_len:7; - /** a_roi_region7_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 7 in - * video A. - */ - uint32_t a_roi_region7_y_len:7; - /** a_roi_region7_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video A ROI of region 7 . - * 0:Close ROI - * 1:Open ROI. - */ - uint32_t a_roi_region7_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_a_roi_region7_reg_t; - -/** Type of a_roi_region0_3_qp register +/** Type of roi_region0_3_qp register * Video A H264 ROI region0, region1,region2,region3 QP register. */ typedef union { struct { - /** a_roi_region0_qp : R/W; bitpos: [6:0]; default: 0; + /** roi_region0_qp : R/W; bitpos: [6:0]; default: 0; * Configure H264 ROI region0 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region0_qp:7; - /** a_roi_region1_qp : R/W; bitpos: [13:7]; default: 0; + uint32_t roi_region0_qp: 7; + /** roi_region1_qp : R/W; bitpos: [13:7]; default: 0; * Configure H264 ROI region1 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region1_qp:7; - /** a_roi_region2_qp : R/W; bitpos: [20:14]; default: 0; + uint32_t roi_region1_qp: 7; + /** roi_region2_qp : R/W; bitpos: [20:14]; default: 0; * Configure H264 ROI region2 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region2_qp:7; - /** a_roi_region3_qp : R/W; bitpos: [27:21]; default: 0; + uint32_t roi_region2_qp: 7; + /** roi_region3_qp : R/W; bitpos: [27:21]; default: 0; * Configure H264 ROI region3 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region3_qp:7; - uint32_t reserved_28:4; + uint32_t roi_region3_qp: 7; + uint32_t reserved_28: 4; }; uint32_t val; -} h264_a_roi_region0_3_qp_reg_t; +} h264_roi_region0_3_qp_reg_t; -/** Type of a_roi_region4_7_qp register +/** Type of roi_region4_7_qp register * Video A H264 ROI region4, region5,region6,region7 QP register. */ typedef union { struct { - /** a_roi_region4_qp : R/W; bitpos: [6:0]; default: 0; + /** roi_region4_qp : R/W; bitpos: [6:0]; default: 0; * Configure H264 ROI region4 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region4_qp:7; - /** a_roi_region5_qp : R/W; bitpos: [13:7]; default: 0; + uint32_t roi_region4_qp: 7; + /** roi_region5_qp : R/W; bitpos: [13:7]; default: 0; * Configure H264 ROI region5 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region5_qp:7; - /** a_roi_region6_qp : R/W; bitpos: [20:14]; default: 0; + uint32_t roi_region5_qp: 7; + /** roi_region6_qp : R/W; bitpos: [20:14]; default: 0; * Configure H264 ROI region6 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region6_qp:7; - /** a_roi_region7_qp : R/W; bitpos: [27:21]; default: 0; + uint32_t roi_region6_qp: 7; + /** roi_region7_qp : R/W; bitpos: [27:21]; default: 0; * Configure H264 ROI region7 qp in video A,fixed qp or delta qp. */ - uint32_t a_roi_region7_qp:7; - uint32_t reserved_28:4; + uint32_t roi_region7_qp: 7; + uint32_t reserved_28: 4; }; uint32_t val; -} h264_a_roi_region4_7_qp_reg_t; +} h264_roi_region4_7_qp_reg_t; -/** Type of a_no_roi_region_qp_offset register +/** Type of no_roi_region_qp_offset register * Video A H264 no roi region QP register. */ typedef union { struct { - /** a_no_roi_region_qp : R/W; bitpos: [6:0]; default: 0; + /** no_roi_region_qp : R/W; bitpos: [6:0]; default: 0; * Configure H264 no region qp in video A, delta qp. */ - uint32_t a_no_roi_region_qp:7; - uint32_t reserved_7:25; + uint32_t no_roi_region_qp: 7; + uint32_t reserved_7: 25; }; uint32_t val; -} h264_a_no_roi_region_qp_offset_reg_t; +} h264_no_roi_region_qp_offset_reg_t; -/** Type of a_roi_config register +/** Type of roi_config register * Video A H264 ROI configure register. */ typedef union { struct { - /** a_roi_en : R/W; bitpos: [0]; default: 0; - * Configure whether or not to enable ROI in video A. - * 0:not enable ROI - * 1:enable ROI. - */ - uint32_t a_roi_en:1; - /** a_roi_mode : R/W; bitpos: [1]; default: 0; - * Configure the mode of ROI in video A. - * 0:fixed qp - * 1:delta qp. - */ - uint32_t a_roi_mode:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} h264_a_roi_config_reg_t; - -/** Type of b_sys_mb_res register - * Video B horizontal and vertical MB resolution register. - */ -typedef union { - struct { - /** b_sys_total_mb_y : R/W; bitpos: [6:0]; default: 0; - * Configures video B vertical MB resolution. - */ - uint32_t b_sys_total_mb_y:7; - /** b_sys_total_mb_x : R/W; bitpos: [13:7]; default: 0; - * Configures video B horizontal MB resolution. - */ - uint32_t b_sys_total_mb_x:7; - uint32_t reserved_14:18; - }; - uint32_t val; -} h264_b_sys_mb_res_reg_t; - -/** Type of b_sys_conf register - * Video B system level configuration register. - */ -typedef union { - struct { - /** b_db_tmp_ready_trigger_mb_num : R/W; bitpos: [6:0]; default: 3; - * Configures when to trigger video B H264_DB_TMP_READY_INT. When the (MB number of - * written db temp+1) is greater than this filed in first MB line, trigger - * H264_DB_TMP_READY_INT. Min is 3. - */ - uint32_t b_db_tmp_ready_trigger_mb_num:7; - /** b_rec_ready_trigger_mb_lines : R/W; bitpos: [13:7]; default: 4; - * Configures when to trigger video B H264_REC_READY_INT. When the MB line number of - * generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. - * Min is 4. + /** roi_en : R/W; bitpos: [0]; default: 0; + * Configure whether or not to enable ROI in video A.\\0:not enable ROI\\1:enable ROI. */ - uint32_t b_rec_ready_trigger_mb_lines:7; - /** b_intra_cost_cmp_offset : R/W; bitpos: [29:14]; default: 0; - * Configures video B intra cost offset when I MB compared with P MB. + uint32_t roi_en: 1; + /** roi_mode : R/W; bitpos: [1]; default: 0; + * Configure the mode of ROI in video A.\\0:fixed qp\\1:delta qp. */ - uint32_t b_intra_cost_cmp_offset:16; - uint32_t reserved_30:2; + uint32_t roi_mode: 1; + uint32_t reserved_2: 30; }; uint32_t val; -} h264_b_sys_conf_reg_t; - -/** Type of b_deci_score register - * Video B luma and chroma MB decimate score Register. - */ -typedef union { - struct { - /** b_c_deci_score : R/W; bitpos: [9:0]; default: 0; - * Configures video B chroma MB decimate score. When chroma score is smaller than it, - * chroma decimate will be enable. - */ - uint32_t b_c_deci_score:10; - /** b_l_deci_score : R/W; bitpos: [19:10]; default: 0; - * Configures video B luma MB decimate score. When luma score is smaller than it, luma - * decimate will be enable. - */ - uint32_t b_l_deci_score:10; - uint32_t reserved_20:12; - }; - uint32_t val; -} h264_b_deci_score_reg_t; - -/** Type of b_deci_score_offset register - * Video B luma and chroma MB decimate score offset Register. - */ -typedef union { - struct { - /** b_i16x16_deci_score_offset : R/W; bitpos: [5:0]; default: 0; - * Configures video B i16x16 MB decimate score offset. This offset will be added to - * i16x16 MB score. - */ - uint32_t b_i16x16_deci_score_offset:6; - /** b_i_chroma_deci_score_offset : R/W; bitpos: [11:6]; default: 0; - * Configures video B I chroma MB decimate score offset. This offset will be added to - * I chroma MB score. - */ - uint32_t b_i_chroma_deci_score_offset:6; - /** b_p16x16_deci_score_offset : R/W; bitpos: [17:12]; default: 0; - * Configures video B p16x16 MB decimate score offset. This offset will be added to - * p16x16 MB score. - */ - uint32_t b_p16x16_deci_score_offset:6; - /** b_p_chroma_deci_score_offset : R/W; bitpos: [23:18]; default: 0; - * Configures video B p chroma MB decimate score offset. This offset will be added to - * p chroma MB score. - */ - uint32_t b_p_chroma_deci_score_offset:6; - uint32_t reserved_24:8; - }; - uint32_t val; -} h264_b_deci_score_offset_reg_t; - -/** Type of b_rc_conf0 register - * Video B rate control configuration register0. - */ -typedef union { - struct { - /** b_qp : R/W; bitpos: [5:0]; default: 0; - * Configures video B frame level initial luma QP value. - */ - uint32_t b_qp:6; - /** b_rate_ctrl_u : R/W; bitpos: [21:6]; default: 0; - * Configures video B parameter U value. U = int((float) u << 8). - */ - uint32_t b_rate_ctrl_u:16; - /** b_mb_rate_ctrl_en : R/W; bitpos: [22]; default: 0; - * Configures video A whether or not to open macro block rate ctrl. - * 1:Open the macro block rate ctrl - * 1:Close the macro block rate ctrl. - */ - uint32_t b_mb_rate_ctrl_en:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} h264_b_rc_conf0_reg_t; - -/** Type of b_rc_conf1 register - * Video B rate control configuration register1. - */ -typedef union { - struct { - /** b_chroma_dc_qp_delta : R/W; bitpos: [2:0]; default: 0; - * Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma - * QP(after map) + reg_chroma_dc_qp_delta. - */ - uint32_t b_chroma_dc_qp_delta:3; - /** b_chroma_qp_delta : R/W; bitpos: [6:3]; default: 0; - * Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma - * QP + reg_chroma_qp_delta. - */ - uint32_t b_chroma_qp_delta:4; - /** b_qp_min : R/W; bitpos: [12:7]; default: 0; - * Configures video B allowed luma QP min value. - */ - uint32_t b_qp_min:6; - /** b_qp_max : R/W; bitpos: [18:13]; default: 0; - * Configures video B allowed luma QP max value. - */ - uint32_t b_qp_max:6; - /** b_mad_frame_pred : R/W; bitpos: [30:19]; default: 0; - * Configures vdieo B frame level predicted MB MAD value. - */ - uint32_t b_mad_frame_pred:12; - uint32_t reserved_31:1; - }; - uint32_t val; -} h264_b_rc_conf1_reg_t; - -/** Type of b_db_bypass register - * Video B Deblocking bypass register - */ -typedef union { - struct { - /** b_bypass_db_filter : R/W; bitpos: [0]; default: 0; - * Configures whether or not to bypass video B deblcoking filter. - * 0: Open the deblock filter - * 1: Close the deblock filter - */ - uint32_t b_bypass_db_filter:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} h264_b_db_bypass_reg_t; - -/** Type of b_roi_region0 register - * Video B H264 ROI region0 range configure register. - */ -typedef union { - struct { - /** b_roi_region0_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 0 in Video B. - */ - uint32_t b_roi_region0_x:7; - /** b_roi_region0_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 0 in Video B. - */ - uint32_t b_roi_region0_y:7; - /** b_roi_region0_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 0 in - * Video B. - */ - uint32_t b_roi_region0_x_len:7; - /** b_roi_region0_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 0 in - * Video B. - */ - uint32_t b_roi_region0_y_len:7; - /** b_roi_region0_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 0 . - * 0:Close ROI - * 1:Open ROI. - */ - uint32_t b_roi_region0_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region0_reg_t; - -/** Type of b_roi_region1 register - * Video B H264 ROI region1 range configure register. - */ -typedef union { - struct { - /** b_roi_region1_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 1 in Video B. - */ - uint32_t b_roi_region1_x:7; - /** b_roi_region1_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 1 in Video B. - */ - uint32_t b_roi_region1_y:7; - /** b_roi_region1_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 1 in - * Video B. - */ - uint32_t b_roi_region1_x_len:7; - /** b_roi_region1_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 1 in - * Video B. - */ - uint32_t b_roi_region1_y_len:7; - /** b_roi_region1_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 1 . - * 0:Close ROI - * 1:Open ROI. - */ - uint32_t b_roi_region1_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region1_reg_t; - -/** Type of b_roi_region2 register - * Video B H264 ROI region2 range configure register. - */ -typedef union { - struct { - /** b_roi_region2_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 2 in Video B. - */ - uint32_t b_roi_region2_x:7; - /** b_roi_region2_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 2 in Video B. - */ - uint32_t b_roi_region2_y:7; - /** b_roi_region2_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 2 in - * Video B. - */ - uint32_t b_roi_region2_x_len:7; - /** b_roi_region2_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 2 in - * Video B. - */ - uint32_t b_roi_region2_y_len:7; - /** b_roi_region2_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 2 . - * 0:Close ROI - * 1:Open ROI. - */ - uint32_t b_roi_region2_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region2_reg_t; - -/** Type of b_roi_region3 register - * Video B H264 ROI region3 range configure register. - */ -typedef union { - struct { - /** b_roi_region3_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 3 in Video B. - */ - uint32_t b_roi_region3_x:7; - /** b_roi_region3_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 3 in Video B. - */ - uint32_t b_roi_region3_y:7; - /** b_roi_region3_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 3 in - * video B. - */ - uint32_t b_roi_region3_x_len:7; - /** b_roi_region3_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 3 in - * video B. - */ - uint32_t b_roi_region3_y_len:7; - /** b_roi_region3_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 3 . - * 0:Close ROI - * 1:Open ROI. - */ - uint32_t b_roi_region3_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region3_reg_t; - -/** Type of b_roi_region4 register - * Video B H264 ROI region4 range configure register. - */ -typedef union { - struct { - /** b_roi_region4_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 4 in Video B. - */ - uint32_t b_roi_region4_x:7; - /** b_roi_region4_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 4 in Video B. - */ - uint32_t b_roi_region4_y:7; - /** b_roi_region4_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 4 in - * video B. - */ - uint32_t b_roi_region4_x_len:7; - /** b_roi_region4_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 4 in - * video B. - */ - uint32_t b_roi_region4_y_len:7; - /** b_roi_region4_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 4 . - * 0:Close ROI - * 1:Open ROI. - */ - uint32_t b_roi_region4_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region4_reg_t; - -/** Type of b_roi_region5 register - * Video B H264 ROI region5 range configure register. - */ -typedef union { - struct { - /** b_roi_region5_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontial start macroblocks of region 5 video B. - */ - uint32_t b_roi_region5_x:7; - /** b_roi_region5_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 5 video B. - */ - uint32_t b_roi_region5_y:7; - /** b_roi_region5_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 5 - * video B. - */ - uint32_t b_roi_region5_x_len:7; - /** b_roi_region5_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 5 in - * video B. - */ - uint32_t b_roi_region5_y_len:7; - /** b_roi_region5_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 5 . - * 0:Close ROI - * 1:Open ROI. - */ - uint32_t b_roi_region5_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region5_reg_t; - -/** Type of b_roi_region6 register - * Video B H264 ROI region6 range configure register. - */ -typedef union { - struct { - /** b_roi_region6_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontial start macroblocks of region 6 video B. - */ - uint32_t b_roi_region6_x:7; - /** b_roi_region6_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 6 in video B. - */ - uint32_t b_roi_region6_y:7; - /** b_roi_region6_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 6 in - * video B. - */ - uint32_t b_roi_region6_x_len:7; - /** b_roi_region6_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 6 in - * video B. - */ - uint32_t b_roi_region6_y_len:7; - /** b_roi_region6_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 6 . - * 0:Close ROI - * 1:Open ROI. - */ - uint32_t b_roi_region6_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region6_reg_t; - -/** Type of b_roi_region7 register - * Video B H264 ROI region7 range configure register. - */ -typedef union { - struct { - /** b_roi_region7_x : R/W; bitpos: [6:0]; default: 0; - * Configures the horizontal start macroblocks of region 7 in video B. - */ - uint32_t b_roi_region7_x:7; - /** b_roi_region7_y : R/W; bitpos: [13:7]; default: 0; - * Configures the vertical start macroblocks of region 7 in video B. - */ - uint32_t b_roi_region7_y:7; - /** b_roi_region7_x_len : R/W; bitpos: [20:14]; default: 0; - * Configures the number of macroblocks in horizontal direction of the region 7 in - * video B. - */ - uint32_t b_roi_region7_x_len:7; - /** b_roi_region7_y_len : R/W; bitpos: [27:21]; default: 0; - * Configures the number of macroblocks in vertical direction of the region 7 in - * video B. - */ - uint32_t b_roi_region7_y_len:7; - /** b_roi_region7_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to open Video B ROI of region 7 . - * 0:Close ROI - * 1:Open ROI. - */ - uint32_t b_roi_region7_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} h264_b_roi_region7_reg_t; - -/** Type of b_roi_region0_3_qp register - * Video B H264 ROI region0, region1,region2,region3 QP register. - */ -typedef union { - struct { - /** b_roi_region0_qp : R/W; bitpos: [6:0]; default: 0; - * Configure H264 ROI region0 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region0_qp:7; - /** b_roi_region1_qp : R/W; bitpos: [13:7]; default: 0; - * Configure H264 ROI region1 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region1_qp:7; - /** b_roi_region2_qp : R/W; bitpos: [20:14]; default: 0; - * Configure H264 ROI region2 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region2_qp:7; - /** b_roi_region3_qp : R/W; bitpos: [27:21]; default: 0; - * Configure H264 ROI region3 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region3_qp:7; - uint32_t reserved_28:4; - }; - uint32_t val; -} h264_b_roi_region0_3_qp_reg_t; - -/** Type of b_roi_region4_7_qp register - * Video B H264 ROI region4, region5,region6,region7 QP register. - */ -typedef union { - struct { - /** b_roi_region4_qp : R/W; bitpos: [6:0]; default: 0; - * Configure H264 ROI region4 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region4_qp:7; - /** b_roi_region5_qp : R/W; bitpos: [13:7]; default: 0; - * Configure H264 ROI region5 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region5_qp:7; - /** b_roi_region6_qp : R/W; bitpos: [20:14]; default: 0; - * Configure H264 ROI region6 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region6_qp:7; - /** b_roi_region7_qp : R/W; bitpos: [27:21]; default: 0; - * Configure H264 ROI region7 qp in video B,fixed qp or delta qp. - */ - uint32_t b_roi_region7_qp:7; - uint32_t reserved_28:4; - }; - uint32_t val; -} h264_b_roi_region4_7_qp_reg_t; - -/** Type of b_no_roi_region_qp_offset register - * Video B H264 no roi region QP register. - */ -typedef union { - struct { - /** b_no_roi_region_qp : R/W; bitpos: [6:0]; default: 0; - * Configure H264 no region qp in video B, delta qp. - */ - uint32_t b_no_roi_region_qp:7; - uint32_t reserved_7:25; - }; - uint32_t val; -} h264_b_no_roi_region_qp_offset_reg_t; - -/** Type of b_roi_config register - * Video B H264 ROI configure register. - */ -typedef union { - struct { - /** b_roi_en : R/W; bitpos: [0]; default: 0; - * Configure whether or not to enable ROI in video B. - * 0:not enable ROI - * 1:enable ROI. - */ - uint32_t b_roi_en:1; - /** b_roi_mode : R/W; bitpos: [1]; default: 0; - * Configure the mode of ROI in video B. - * 0:fixed qp - * 1:delta qp. - */ - uint32_t b_roi_mode:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} h264_b_roi_config_reg_t; +} h264_roi_config_reg_t; /** Type of slice_header_remain register * Frame Slice Header remain bit register. @@ -1130,12 +352,12 @@ typedef union { /** slice_remain_bitlength : R/W; bitpos: [2:0]; default: 0; * Configures Slice Header remain bit number */ - uint32_t slice_remain_bitlength:3; + uint32_t slice_remain_bitlength: 3; /** slice_remain_bit : R/W; bitpos: [10:3]; default: 0; * Configures Slice Header remain bit */ - uint32_t slice_remain_bit:8; - uint32_t reserved_11:21; + uint32_t slice_remain_bit: 8; + uint32_t reserved_11: 21; }; uint32_t val; } h264_slice_header_remain_reg_t; @@ -1148,8 +370,8 @@ typedef union { /** slice_byte_length : R/W; bitpos: [3:0]; default: 0; * Configures Slice Header byte number */ - uint32_t slice_byte_length:4; - uint32_t reserved_4:28; + uint32_t slice_byte_length: 4; + uint32_t reserved_4: 28; }; uint32_t val; } h264_slice_header_byte_length_reg_t; @@ -1163,37 +385,24 @@ typedef union { * Configures bitstream buffer overflow threshold. This value should be bigger than * the encode bytes of one 4x4 submb. */ - uint32_t bs_buffer_threshold:7; - uint32_t reserved_7:25; + uint32_t bs_buffer_threshold: 7; + uint32_t reserved_7: 25; }; uint32_t val; } h264_bs_threshold_reg_t; -/** Type of slice_header_byte0 register - * Frame Slice Header byte low 32 bit register. +/** Type of slice_header_byte register + * Frame Slice Header byte 32 bit register. */ typedef union { struct { - /** slice_byte_lsb : R/W; bitpos: [31:0]; default: 0; - * Configures Slice Header low 32 bit + /** byte : R/W; bitpos: [31:0]; default: 0; + * Configures Slice Header 32 bit */ - uint32_t slice_byte_lsb:32; + uint32_t byte: 32; }; uint32_t val; -} h264_slice_header_byte0_reg_t; - -/** Type of slice_header_byte1 register - * Frame Slice Header byte high 32 bit register. - */ -typedef union { - struct { - /** slice_byte_msb : R/W; bitpos: [31:0]; default: 0; - * Configures Slice Header high 32 bit - */ - uint32_t slice_byte_msb:32; - }; - uint32_t val; -} h264_slice_header_byte1_reg_t; +} h264_slice_header_reg_t; /** Type of conf register * General configuration register. @@ -1201,174 +410,166 @@ typedef union { typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to open register clock gate. - * 0: Open the clock gate only when application writes registers - * 1: Force open the clock gate for register + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register */ - uint32_t clk_en:1; + uint32_t clk_en: 1; /** rec_ram_clk_en2 : R/W; bitpos: [1]; default: 0; - * Configures whether or not to open the clock gate for rec ram2. - * 0: Open the clock gate only when application writes or reads rec ram2 - * 1: Force open the clock gate for rec ram2 + * Configures whether or not to open the clock gate for rec ram2.\\0: Open the clock + * gate only when application writes or reads rec ram2\\1: Force open the clock gate + * for rec ram2 */ - uint32_t rec_ram_clk_en2:1; + uint32_t rec_ram_clk_en2: 1; /** rec_ram_clk_en1 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to open the clock gate for rec ram1. - * 0: Open the clock gate only when application writes or reads rec ram1 - * 1: Force open the clock gate for rec ram1 + * Configures whether or not to open the clock gate for rec ram1.\\0: Open the clock + * gate only when application writes or reads rec ram1\\1: Force open the clock gate + * for rec ram1 */ - uint32_t rec_ram_clk_en1:1; + uint32_t rec_ram_clk_en1: 1; /** quant_ram_clk_en2 : R/W; bitpos: [3]; default: 0; - * Configures whether or not to open the clock gate for quant ram2. - * 0: Open the clock gate only when application writes or reads quant ram2 - * 1: Force open the clock gate for quant ram2 + * Configures whether or not to open the clock gate for quant ram2.\\0: Open the clock + * gate only when application writes or reads quant ram2\\1: Force open the clock gate + * for quant ram2 */ - uint32_t quant_ram_clk_en2:1; + uint32_t quant_ram_clk_en2: 1; /** quant_ram_clk_en1 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to open the clock gate for quant ram1. - * 0: Open the clock gate only when application writes or reads quant ram1 - * 1: Force open the clock gate for quant ram1 + * Configures whether or not to open the clock gate for quant ram1.\\0: Open the clock + * gate only when application writes or reads quant ram1\\1: Force open the clock gate + * for quant ram1 */ - uint32_t quant_ram_clk_en1:1; + uint32_t quant_ram_clk_en1: 1; /** pre_ram_clk_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to open the clock gate for pre ram. - * 0: Open the clock gate only when application writes or reads pre ram - * 1: Force open the clock gate for pre ram + * Configures whether or not to open the clock gate for pre ram.\\0: Open the clock + * gate only when application writes or reads pre ram\\1: Force open the clock gate + * for pre ram */ - uint32_t pre_ram_clk_en:1; + uint32_t pre_ram_clk_en: 1; /** mvd_ram_clk_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to open the clock gate for mvd ram. - * 0: Open the clock gate only when application writes or reads mvd ram - * 1: Force open the clock gate for mvd ram + * Configures whether or not to open the clock gate for mvd ram.\\0: Open the clock + * gate only when application writes or reads mvd ram\\1: Force open the clock gate + * for mvd ram */ - uint32_t mvd_ram_clk_en:1; + uint32_t mvd_ram_clk_en: 1; /** mc_ram_clk_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to open the clock gate for mc ram. - * 0: Open the clock gate only when application writes or reads mc ram - * 1: Force open the clock gate for mc ram + * Configures whether or not to open the clock gate for mc ram.\\0: Open the clock + * gate only when application writes or reads mc ram\\1: Force open the clock gate for + * mc ram */ - uint32_t mc_ram_clk_en:1; + uint32_t mc_ram_clk_en: 1; /** ref_ram_clk_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to open the clock gate for ref ram. - * 0: Open the clock gate only when application writes or reads ref ram - * 1: Force open the clock gate for ref ram + * Configures whether or not to open the clock gate for ref ram.\\0: Open the clock + * gate only when application writes or reads ref ram\\1: Force open the clock gate + * for ref ram */ - uint32_t ref_ram_clk_en:1; + uint32_t ref_ram_clk_en: 1; /** i4x4_ref_ram_clk_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to open the clock gate for i4x4_mode ram. - * 0: Open the clock gate only when application writes or reads i4x4_mode ram - * 1: Force open the clock gate for i4x4_mode ram + * Configures whether or not to open the clock gate for i4x4_mode ram.\\0: Open the + * clock gate only when application writes or reads i4x4_mode ram\\1: Force open the + * clock gate for i4x4_mode ram */ - uint32_t i4x4_ref_ram_clk_en:1; + uint32_t i4x4_ref_ram_clk_en: 1; /** ime_ram_clk_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to open the clock gate for ime ram. - * 0: Open the clock gate only when application writes or reads ime ram - * 1: Force open the clock gate for ime ram + * Configures whether or not to open the clock gate for ime ram.\\0: Open the clock + * gate only when application writes or reads ime ram\\1: Force open the clock gate + * for ime ram */ - uint32_t ime_ram_clk_en:1; + uint32_t ime_ram_clk_en: 1; /** fme_ram_clk_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to open the clock gate for fme ram. - * 0: Open the clock gate only when application writes or readsfme ram - * 1: Force open the clock gate for fme ram + * Configures whether or not to open the clock gate for fme ram.\\0: Open the clock + * gate only when application writes or readsfme ram\\1: Force open the clock gate for + * fme ram */ - uint32_t fme_ram_clk_en:1; + uint32_t fme_ram_clk_en: 1; /** fetch_ram_clk_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to open the clock gate for fetch ram. - * 0: Open the clock gate only when application writes or reads fetch ram - * 1: Force open the clock gate for fetch ram + * Configures whether or not to open the clock gate for fetch ram.\\0: Open the clock + * gate only when application writes or reads fetch ram\\1: Force open the clock gate + * for fetch ram */ - uint32_t fetch_ram_clk_en:1; + uint32_t fetch_ram_clk_en: 1; /** db_ram_clk_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to open the clock gate for db ram. - * 0: Open the clock gate only when application writes or reads db ram - * 1: Force open the clock gate for db ram + * Configures whether or not to open the clock gate for db ram.\\0: Open the clock + * gate only when application writes or reads db ram\\1: Force open the clock gate for + * db ram */ - uint32_t db_ram_clk_en:1; + uint32_t db_ram_clk_en: 1; /** cur_mb_ram_clk_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to open the clock gate for cur_mb ram. - * 0: Open the clock gate only when application writes or reads cur_mb ram - * 1: Force open the clock gate for cur_mb ram + * Configures whether or not to open the clock gate for cur_mb ram.\\0: Open the clock + * gate only when application writes or reads cur_mb ram\\1: Force open the clock gate + * for cur_mb ram */ - uint32_t cur_mb_ram_clk_en:1; + uint32_t cur_mb_ram_clk_en: 1; /** cavlc_ram_clk_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to open the clock gate for cavlc ram. - * 0: Open the clock gate only when application writes or reads cavlc ram - * 1: Force open the clock gate for cavlc ram + * Configures whether or not to open the clock gate for cavlc ram.\\0: Open the clock + * gate only when application writes or reads cavlc ram\\1: Force open the clock gate + * for cavlc ram */ - uint32_t cavlc_ram_clk_en:1; + uint32_t cavlc_ram_clk_en: 1; /** ime_clk_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to open the clock gate for ime. - * 0: Open the clock gate only when ime work - * 1: Force open the clock gate for ime + * Configures whether or not to open the clock gate for ime.\\0: Open the clock gate + * only when ime work\\1: Force open the clock gate for ime */ - uint32_t ime_clk_en:1; + uint32_t ime_clk_en: 1; /** fme_clk_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to open the clock gate for fme. - * 0: Open the clock gate only when fme work - * 1: Force open the clock gate for fme + * Configures whether or not to open the clock gate for fme.\\0: Open the clock gate + * only when fme work\\1: Force open the clock gate for fme */ - uint32_t fme_clk_en:1; + uint32_t fme_clk_en: 1; /** mc_clk_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to open the clock gate for mc. - * 0: Open the clock gate only when mc work - * 1: Force open the clock gate for mc + * Configures whether or not to open the clock gate for mc.\\0: Open the clock gate + * only when mc work\\1: Force open the clock gate for mc */ - uint32_t mc_clk_en:1; + uint32_t mc_clk_en: 1; /** interpolator_clk_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to open the clock gate for interpolator. - * 0: Open the clock gate only when interpolator work - * 1: Force open the clock gate for interpolator + * Configures whether or not to open the clock gate for interpolator.\\0: Open the + * clock gate only when interpolator work\\1: Force open the clock gate for + * interpolator */ - uint32_t interpolator_clk_en:1; + uint32_t interpolator_clk_en: 1; /** db_clk_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to open the clock gate for deblocking filter. - * 0: Open the clock gate only when deblocking filter work - * 1: Force open the clock gate for deblocking filter + * Configures whether or not to open the clock gate for deblocking filter.\\0: Open + * the clock gate only when deblocking filter work\\1: Force open the clock gate for + * deblocking filter */ - uint32_t db_clk_en:1; + uint32_t db_clk_en: 1; /** clavlc_clk_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to open the clock gate for cavlc. - * 0: Open the clock gate only when cavlc work - * 1: Force open the clock gate for cavlc + * Configures whether or not to open the clock gate for cavlc.\\0: Open the clock gate + * only when cavlc work\\1: Force open the clock gate for cavlc */ - uint32_t clavlc_clk_en:1; + uint32_t clavlc_clk_en: 1; /** intra_clk_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to open the clock gate for intra. - * 0: Open the clock gate only when intra work - * 1: Force open the clock gate for intra + * Configures whether or not to open the clock gate for intra.\\0: Open the clock gate + * only when intra work\\1: Force open the clock gate for intra */ - uint32_t intra_clk_en:1; + uint32_t intra_clk_en: 1; /** deci_clk_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to open the clock gate for decimate. - * 0: Open the clock gate only when decimate work - * 1: Force open the clock gate for decimate + * Configures whether or not to open the clock gate for decimate.\\0: Open the clock + * gate only when decimate work\\1: Force open the clock gate for decimate */ - uint32_t deci_clk_en:1; + uint32_t deci_clk_en: 1; /** bs_clk_en : R/W; bitpos: [24]; default: 0; - * Configures whether or not to open the clock gate for bs buffer. - * 0: Open the clock gate only when bs buffer work - * 1: Force open the clock gate for bs buffer + * Configures whether or not to open the clock gate for bs buffer.\\0: Open the clock + * gate only when bs buffer work\\1: Force open the clock gate for bs buffer */ - uint32_t bs_clk_en:1; + uint32_t bs_clk_en: 1; /** mv_merge_clk_en : R/W; bitpos: [25]; default: 0; - * Configures whether or not to open the clock gate for mv merge. - * 0: Open the clock gate only when mv merge work - * 1: Force open the clock gate for mv merge + * Configures whether or not to open the clock gate for mv merge.\\0: Open the clock + * gate only when mv merge work\\1: Force open the clock gate for mv merge */ - uint32_t mv_merge_clk_en:1; + uint32_t mv_merge_clk_en: 1; + /** cur_mb_rdcmb_clk_en : R/W; bitpos: [26]; default: 0; * Configures whether or not to open the clock gate for cur_mb read macroblock. * 0: Open the clock gate only when cur_mb read macroblock work * 1: Force open the clock gate for cur_mb read macroblock */ - uint32_t cur_mb_rdcmb_clk_en:1; + uint32_t cur_mb_rdcmb_clk_en: 1; /** cur_mb_refresh_reggroup_clk_en : R/W; bitpos: [27]; default: 0; * Configures whether or not to open the clock gate for cur_mb refresh register group. * 0: Open the clock gate only when cur_mb refresh register group work * 1: Force open the clock gate for cur_mb refresh register group */ - uint32_t cur_mb_refresh_reggroup_clk_en:1; - uint32_t reserved_28:4; + uint32_t cur_mb_refresh_reggroup_clk_en: 1; + uint32_t reserved_28: 4; }; uint32_t val; } h264_conf_reg_t; @@ -1379,36 +580,28 @@ typedef union { typedef union { struct { /** mv_merge_type : R/W; bitpos: [1:0]; default: 0; - * Configure mv merge type. - * 0: merge p16x16 mv - * 1: merge min mv - * 2: merge max mv - * 3: not valid. + * Configure mv merge type.\\0: merge p16x16 mv\\1: merge min mv\\2: merge max mv\\3: + * not valid. */ - uint32_t mv_merge_type:2; + uint32_t mv_merge_type: 2; /** int_mv_out_en : R/W; bitpos: [2]; default: 0; - * Configure mv merge output integer part not zero mv or all part not zero mv. - * 0: output all part not zero mv - * 1: output integer part not zero mv. + * Configure mv merge output integer part not zero mv or all part not zero mv.\\0: + * output all part not zero mv\\1: output integer part not zero mv. */ - uint32_t int_mv_out_en:1; + uint32_t int_mv_out_en: 1; /** a_mv_merge_en : R/W; bitpos: [3]; default: 0; - * Configure whether or not to enable video A mv merge. - * 0: disable - * 1: enable. + * Configure whether or not to enable video A mv merge.\\0: disable\\1: enable. */ - uint32_t a_mv_merge_en:1; + uint32_t a_mv_merge_en: 1; /** b_mv_merge_en : R/W; bitpos: [4]; default: 0; - * Configure whether or not to enable video B mv merge. - * 0: disable - * 1: enable. + * Configure whether or not to enable video B mv merge.\\0: disable\\1: enable. */ - uint32_t b_mv_merge_en:1; + uint32_t b_mv_merge_en: 1; /** mb_valid_num : RO; bitpos: [17:5]; default: 0; * Represents the valid mb number of mv merge output. */ - uint32_t mb_valid_num:13; - uint32_t reserved_18:14; + uint32_t mb_valid_num: 13; + uint32_t reserved_18: 14; }; uint32_t val; } h264_mv_merge_config_reg_t; @@ -1421,8 +614,8 @@ typedef union { /** dbg_dma_sel : R/W; bitpos: [7:0]; default: 0; * Every bit represents a dma in h264 */ - uint32_t dbg_dma_sel:8; - uint32_t reserved_8:24; + uint32_t dbg_dma_sel: 8; + uint32_t reserved_8: 24; }; uint32_t val; } h264_debug_dma_sel_reg_t; @@ -1432,7 +625,7 @@ typedef union { */ typedef union { struct { - /** a_ori_color_space : R/W; bitpos: [2:0]; default: 4; + /** ori_color_space : R/W; bitpos: [2:0]; default: 4; * Configures video A original picture color space. * 0: RGB888 * 1: RGB565 @@ -1442,32 +635,11 @@ typedef union { * 5: GRAY * Others: Invalid */ - uint32_t a_ori_color_space:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} h264_a_ori_conf_reg_t; - -/** Type of b_ori_conf register - * Video B original picture configuration register. - */ -typedef union { - struct { - /** b_ori_color_space : R/W; bitpos: [2:0]; default: 4; - * Configures video B original picture color space. - * 0: RGB888 - * 1: RGB565 - * 2: YUV444 - * 3: YUV422 - * 4: YUV420 - * 5: GRAY - * Others: Invalid - */ - uint32_t b_ori_color_space:3; - uint32_t reserved_3:29; + uint32_t ori_color_space: 3; + uint32_t reserved_3: 29; }; uint32_t val; -} h264_b_ori_conf_reg_t; +} h264_ori_conf_reg_t; /** Type of ori_debug_conf register * Original picture debug configuration register. @@ -1479,14 +651,14 @@ typedef union { * 0: not replace * 1: replace */ - uint32_t dbg_replace_ori_data_en:1; + uint32_t dbg_replace_ori_data_en: 1; /** dbg_replace_ori_data : R/W; bitpos: [24:1]; default: 0; * Configures original picture pixels to be replaced. When the original picture color * space is RGB, byte0~2 is BGR. When the original picture color space is YUV, byte0~2 * is VUY. When the original picture color space is GRAY, byte0 is GRAY. */ - uint32_t dbg_replace_ori_data:24; - uint32_t reserved_25:7; + uint32_t dbg_replace_ori_data: 24; + uint32_t reserved_25: 7; }; uint32_t val; } h264_ori_debug_conf_reg_t; @@ -1501,12 +673,12 @@ typedef union { * 0: not replace * 1: replace */ - uint32_t dbg_replace_mv_merge_data_en:1; + uint32_t dbg_replace_mv_merge_data_en: 1; /** dbg_replace_mv_merge_data : R/W; bitpos: [8:1]; default: 0; * Configures mv merge data to be replaced. */ - uint32_t dbg_replace_mv_merge_data:8; - uint32_t reserved_9:23; + uint32_t dbg_replace_mv_merge_data: 8; + uint32_t reserved_9: 23; }; uint32_t val; } h264_mv_merge_debug_conf_reg_t; @@ -1521,12 +693,12 @@ typedef union { * 0: not replace * 1: replace */ - uint32_t dbg_replace_wr_bs_data_en:1; + uint32_t dbg_replace_wr_bs_data_en: 1; /** dbg_replace_wr_bs_data : R/W; bitpos: [8:1]; default: 0; * Configures bs data to be replaced */ - uint32_t dbg_replace_wr_bs_data:8; - uint32_t reserved_9:23; + uint32_t dbg_replace_wr_bs_data: 8; + uint32_t reserved_9: 23; }; uint32_t val; } h264_bs_debug_cong_reg_t; @@ -1541,12 +713,12 @@ typedef union { * 0: not replace * 1: replace */ - uint32_t dbg_replace_wr_db_temp_data_en:1; + uint32_t dbg_replace_wr_db_temp_data_en: 1; /** dbg_replace_wr_db_temp_data : R/W; bitpos: [24:1]; default: 0; * Configure deblocking filter write temp data to be replaced.byte0~2 is VUY */ - uint32_t dbg_replace_wr_db_temp_data:24; - uint32_t reserved_25:7; + uint32_t dbg_replace_wr_db_temp_data: 24; + uint32_t reserved_25: 7; }; uint32_t val; } h264_db_wr_temp_debug_cong_reg_t; @@ -1561,12 +733,12 @@ typedef union { * 0: not replace * 1: replace */ - uint32_t dbg_replace_rd_db_temp_data_en:1; + uint32_t dbg_replace_rd_db_temp_data_en: 1; /** dbg_replace_rd_db_temp_data : R/W; bitpos: [24:1]; default: 0; * Configure deblocking filter read temp data to be replaced.byte0~2 is VUY */ - uint32_t dbg_replace_rd_db_temp_data:24; - uint32_t reserved_25:7; + uint32_t dbg_replace_rd_db_temp_data: 24; + uint32_t reserved_25: 7; }; uint32_t val; } h264_db_rd_temp_debug_cong_reg_t; @@ -1581,12 +753,12 @@ typedef union { * 0: not replace * 1: replace */ - uint32_t dbg_replace_wr_db_data_en:1; + uint32_t dbg_replace_wr_db_data_en: 1; /** dbg_replace_wr_db_data : R/W; bitpos: [24:1]; default: 0; * Configure deblocking filter write data to be replaced.byte0~2 is VUY */ - uint32_t dbg_replace_wr_db_data:24; - uint32_t reserved_25:7; + uint32_t dbg_replace_wr_db_data: 24; + uint32_t reserved_25: 7; }; uint32_t val; } h264_db_wr_debug_cong_reg_t; @@ -1601,17 +773,16 @@ typedef union { * 0: not replace * 1: replace */ - uint32_t dbg_replace_ref_data_en:1; + uint32_t dbg_replace_ref_data_en: 1; /** dbg_replace_ref_data : R/W; bitpos: [24:1]; default: 0; * Configure reference picture pixels to be replaced.byte0~2 is VUY */ - uint32_t dbg_replace_ref_data:24; - uint32_t reserved_25:7; + uint32_t dbg_replace_ref_data: 24; + uint32_t reserved_25: 7; }; uint32_t val; } h264_ref_debug_cong_reg_t; - /** Group: Status Register */ /** Type of rc_status0 register * Rate control status register0. @@ -1621,8 +792,8 @@ typedef union { /** frame_mad_sum : RO; bitpos: [20:0]; default: 0; * Represents all MB actual MAD sum value of one frame. */ - uint32_t frame_mad_sum:21; - uint32_t reserved_21:11; + uint32_t frame_mad_sum: 21; + uint32_t reserved_21: 11; }; uint32_t val; } h264_rc_status0_reg_t; @@ -1635,8 +806,8 @@ typedef union { /** frame_enc_bits : RO; bitpos: [26:0]; default: 0; * Represents all MB actual encoding bits sum value of one frame. */ - uint32_t frame_enc_bits:27; - uint32_t reserved_27:5; + uint32_t frame_enc_bits: 27; + uint32_t reserved_27: 5; }; uint32_t val; } h264_rc_status1_reg_t; @@ -1649,8 +820,8 @@ typedef union { /** frame_qp_sum : RO; bitpos: [18:0]; default: 0; * Represents all MB actual luma QP sum value of one frame. */ - uint32_t frame_qp_sum:19; - uint32_t reserved_19:13; + uint32_t frame_qp_sum: 19; + uint32_t reserved_19: 13; }; uint32_t val; } h264_rc_status2_reg_t; @@ -1663,20 +834,17 @@ typedef union { /** frame_num : RO; bitpos: [8:0]; default: 0; * Represents current frame number. */ - uint32_t frame_num:9; + uint32_t frame_num: 9; /** dual_stream_sel : RO; bitpos: [9]; default: 0; - * Represents which register group is used for cur frame. - * 0: Register group A is used - * 1: Register group B is used. + * Represents which register group is used for cur frame.\\0: Register group A is + * used\\1: Register group B is used. */ - uint32_t dual_stream_sel:1; + uint32_t dual_stream_sel: 1; /** intra_flag : RO; bitpos: [10]; default: 0; - * Represents the type of current encoding frame. - * 0: P frame - * 1: I frame. + * Represents the type of current encoding frame.\\0: P frame\\1: I frame. */ - uint32_t intra_flag:1; - uint32_t reserved_11:21; + uint32_t intra_flag: 1; + uint32_t reserved_11: 21; }; uint32_t val; } h264_sys_status_reg_t; @@ -1689,8 +857,8 @@ typedef union { /** frame_code_length : RO; bitpos: [23:0]; default: 0; * Represents current frame code byte length. */ - uint32_t frame_code_length:24; - uint32_t reserved_24:8; + uint32_t frame_code_length: 24; + uint32_t reserved_24: 8; }; uint32_t val; } h264_frame_code_length_reg_t; @@ -1703,40 +871,40 @@ typedef union { /** top_ctrl_inter_debug_state : RO; bitpos: [3:0]; default: 0; * Represents top_ctrl_inter module FSM info. */ - uint32_t top_ctrl_inter_debug_state:4; + uint32_t top_ctrl_inter_debug_state: 4; /** top_ctrl_intra_debug_state : RO; bitpos: [6:4]; default: 0; * Represents top_ctrl_intra module FSM info. */ - uint32_t top_ctrl_intra_debug_state:3; + uint32_t top_ctrl_intra_debug_state: 3; /** p_i_cmp_debug_state : RO; bitpos: [9:7]; default: 0; * Represents p_i_cmp module FSM info. */ - uint32_t p_i_cmp_debug_state:3; + uint32_t p_i_cmp_debug_state: 3; /** mvd_debug_state : RO; bitpos: [12:10]; default: 0; * Represents mvd module FSM info. */ - uint32_t mvd_debug_state:3; + uint32_t mvd_debug_state: 3; /** mc_chroma_ip_debug_state : RO; bitpos: [13]; default: 0; * Represents mc_chroma_ip module FSM info. */ - uint32_t mc_chroma_ip_debug_state:1; + uint32_t mc_chroma_ip_debug_state: 1; /** intra_16x16_chroma_ctrl_debug_state : RO; bitpos: [17:14]; default: 0; * Represents intra_16x16_chroma_ctrl module FSM info. */ - uint32_t intra_16x16_chroma_ctrl_debug_state:4; + uint32_t intra_16x16_chroma_ctrl_debug_state: 4; /** intra_4x4_ctrl_debug_state : RO; bitpos: [21:18]; default: 0; * Represents intra_4x4_ctrl module FSM info. */ - uint32_t intra_4x4_ctrl_debug_state:4; + uint32_t intra_4x4_ctrl_debug_state: 4; /** intra_top_ctrl_debug_state : RO; bitpos: [24:22]; default: 0; * Represents intra_top_ctrl module FSM info. */ - uint32_t intra_top_ctrl_debug_state:3; + uint32_t intra_top_ctrl_debug_state: 3; /** ime_ctrl_debug_state : RO; bitpos: [27:25]; default: 0; * Represents ime_ctrl module FSM info. */ - uint32_t ime_ctrl_debug_state:3; - uint32_t reserved_28:4; + uint32_t ime_ctrl_debug_state: 3; + uint32_t reserved_28: 4; }; uint32_t val; } h264_debug_info0_reg_t; @@ -1749,28 +917,29 @@ typedef union { /** fme_ctrl_debug_state : RO; bitpos: [2:0]; default: 0; * Represents fme_ctrl module FSM info. */ - uint32_t fme_ctrl_debug_state:3; + uint32_t fme_ctrl_debug_state: 3; /** deci_calc_debug_state : RO; bitpos: [4:3]; default: 0; * Represents deci_calc module's FSM info. DEV use only. */ - uint32_t deci_calc_debug_state:2; + uint32_t deci_calc_debug_state: 2; /** db_debug_state : RO; bitpos: [7:5]; default: 0; * Represents db module FSM info. */ - uint32_t db_debug_state:3; + uint32_t db_debug_state: 3; /** cavlc_enc_debug_state : RO; bitpos: [11:8]; default: 0; * Represents cavlc module enc FSM info. */ - uint32_t cavlc_enc_debug_state:4; + uint32_t cavlc_enc_debug_state: 4; /** cavlc_scan_debug_state : RO; bitpos: [15:12]; default: 0; * Represents cavlc module scan FSM info. */ - uint32_t cavlc_scan_debug_state:4; + uint32_t cavlc_scan_debug_state: 4; /** cavlc_ctrl_debug_state : RO; bitpos: [17:16]; default: 0; * Represents cavlc module ctrl FSM info. */ - uint32_t cavlc_ctrl_debug_state:2; - uint32_t reserved_18:14; + uint32_t cavlc_ctrl_debug_state: 2; + + uint32_t reserved_19: 14; }; uint32_t val; } h264_debug_info1_reg_t; @@ -1781,114 +950,78 @@ typedef union { typedef union { struct { /** p_rc_done_debug_flag : RO; bitpos: [0]; default: 0; - * Represents p rate ctrl done status. - * 0: not done - * 1: done. + * Represents p rate ctrl done status.\\0: not done\\1: done. */ - uint32_t p_rc_done_debug_flag:1; + uint32_t p_rc_done_debug_flag: 1; /** p_p_i_cmp_done_debug_flag : RO; bitpos: [1]; default: 0; - * Represents p p_i_cmp done status. - * 0: not done - * 1: done. + * Represents p p_i_cmp done status.\\0: not done\\1: done. */ - uint32_t p_p_i_cmp_done_debug_flag:1; + uint32_t p_p_i_cmp_done_debug_flag: 1; /** p_mv_merge_done_debug_flag : RO; bitpos: [2]; default: 0; - * Represents p mv merge done status. - * 0: not done - * 1: done. + * Represents p mv merge done status.\\0: not done\\1: done. */ - uint32_t p_mv_merge_done_debug_flag:1; + uint32_t p_mv_merge_done_debug_flag: 1; /** p_move_ori_done_debug_flag : RO; bitpos: [3]; default: 0; - * Represents p move origin done status. - * 0: not done - * 1: done. + * Represents p move origin done status.\\0: not done\\1: done. */ - uint32_t p_move_ori_done_debug_flag:1; + uint32_t p_move_ori_done_debug_flag: 1; /** p_mc_done_debug_flag : RO; bitpos: [4]; default: 0; - * Represents p mc done status. - * 0: not done - * 1: done. + * Represents p mc done status.\\0: not done\\1: done. */ - uint32_t p_mc_done_debug_flag:1; + uint32_t p_mc_done_debug_flag: 1; /** p_ime_done_debug_flag : RO; bitpos: [5]; default: 0; - * Represents p ime done status. - * 0: not done - * 1: done. + * Represents p ime done status.\\0: not done\\1: done. */ - uint32_t p_ime_done_debug_flag:1; + uint32_t p_ime_done_debug_flag: 1; /** p_get_ori_done_debug_flag : RO; bitpos: [6]; default: 0; - * Represents p get origin done status. - * 0: not done - * 1: done. + * Represents p get origin done status.\\0: not done\\1: done. */ - uint32_t p_get_ori_done_debug_flag:1; + uint32_t p_get_ori_done_debug_flag: 1; /** p_fme_done_debug_flag : RO; bitpos: [7]; default: 0; - * Represents p fme done status. - * 0: not done - * 1: done. + * Represents p fme done status.\\0: not done\\1: done. */ - uint32_t p_fme_done_debug_flag:1; + uint32_t p_fme_done_debug_flag: 1; /** p_fetch_done_debug_flag : RO; bitpos: [8]; default: 0; - * Represents p fetch done status. - * 0: not done - * 1: done. + * Represents p fetch done status.\\0: not done\\1: done. */ - uint32_t p_fetch_done_debug_flag:1; + uint32_t p_fetch_done_debug_flag: 1; /** p_db_done_debug_flag : RO; bitpos: [9]; default: 0; - * Represents p deblocking done status. - * 0: not done - * 1: done. + * Represents p deblocking done status.\\0: not done\\1: done. */ - uint32_t p_db_done_debug_flag:1; + uint32_t p_db_done_debug_flag: 1; /** p_bs_buf_done_debug_flag : RO; bitpos: [10]; default: 0; - * Represents p bitstream buffer done status. - * 0: not done - * 1: done. + * Represents p bitstream buffer done status.\\0: not done\\1: done. */ - uint32_t p_bs_buf_done_debug_flag:1; + uint32_t p_bs_buf_done_debug_flag: 1; /** ref_move_2mb_line_done_debug_flag : RO; bitpos: [11]; default: 0; - * Represents dma move 2 ref mb line done status. - * 0: not done - * 1: done. + * Represents dma move 2 ref mb line done status.\\0: not done\\1: done. */ - uint32_t ref_move_2mb_line_done_debug_flag:1; + uint32_t ref_move_2mb_line_done_debug_flag: 1; /** i_p_i_cmp_done_debug_flag : RO; bitpos: [12]; default: 0; - * Represents I p_i_cmp done status. - * 0: not done - * 1: done. + * Represents I p_i_cmp done status.\\0: not done\\1: done. */ - uint32_t i_p_i_cmp_done_debug_flag:1; + uint32_t i_p_i_cmp_done_debug_flag: 1; /** i_move_ori_done_debug_flag : RO; bitpos: [13]; default: 0; - * Represents I move origin done status. - * 0: not done - * 1: done. + * Represents I move origin done status.\\0: not done\\1: done. */ - uint32_t i_move_ori_done_debug_flag:1; + uint32_t i_move_ori_done_debug_flag: 1; /** i_get_ori_done_debug_flag : RO; bitpos: [14]; default: 0; - * Represents I get origin done status. - * 0: not done - * 1: done. + * Represents I get origin done status.\\0: not done\\1: done. */ - uint32_t i_get_ori_done_debug_flag:1; + uint32_t i_get_ori_done_debug_flag: 1; /** i_ec_done_debug_flag : RO; bitpos: [15]; default: 0; - * Represents I encoder done status. - * 0: not done - * 1: done. + * Represents I encoder done status.\\0: not done\\1: done. */ - uint32_t i_ec_done_debug_flag:1; + uint32_t i_ec_done_debug_flag: 1; /** i_db_done_debug_flag : RO; bitpos: [16]; default: 0; - * Represents I deblocking done status. - * 0: not done - * 1: done. + * Represents I deblocking done status.\\0: not done\\1: done. */ - uint32_t i_db_done_debug_flag:1; + uint32_t i_db_done_debug_flag: 1; /** i_bs_buf_done_debug_flag : RO; bitpos: [17]; default: 0; - * Represents I bitstream buffer done status. - * 0: not done - * 1: done. + * Represents I bitstream buffer done status.\\0: not done\\1: done. */ - uint32_t i_bs_buf_done_debug_flag:1; - uint32_t reserved_18:14; + uint32_t i_bs_buf_done_debug_flag: 1; + uint32_t reserved_18: 14; }; uint32_t val; } h264_debug_info2_reg_t; @@ -1904,29 +1037,29 @@ typedef union { * Raw status bit: The raw interrupt status of H264_DB_TMP_READY_INT. Triggered when * H264 written enough db tmp pixel. */ - uint32_t db_tmp_ready_int_raw:1; + uint32_t db_tmp_ready_int_raw: 1; /** rec_ready_int_raw : R/WTC/SS; bitpos: [1]; default: 0; * Raw status bit: The raw interrupt status of H264_REC_READY_INT. Triggered when * H264 encoding enough reconstruct pixel. */ - uint32_t rec_ready_int_raw:1; + uint32_t rec_ready_int_raw: 1; /** frame_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0; * Raw status bit: The raw interrupt status of H264_FRAME_DONE_INT. Triggered when * H264 encoding one frame done. */ - uint32_t frame_done_int_raw:1; + uint32_t frame_done_int_raw: 1; /** dma_move_2mb_line_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0; * Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. * Triggered when H264 move two MB lines of reference frame from external mem to * internal mem done. */ - uint32_t dma_move_2mb_line_done_int_raw:1; + uint32_t dma_move_2mb_line_done_int_raw: 1; /** bs_buffer_overflow_int_raw : R/WTC/SS; bitpos: [4]; default: 0; * Raw status bit: The raw interrupt status of H264_BS_BUFFER_OVERFLOW_INT. Triggered * when H264 bit stream buffer overflow. */ - uint32_t bs_buffer_overflow_int_raw:1; - uint32_t reserved_5:27; + uint32_t bs_buffer_overflow_int_raw: 1; + uint32_t reserved_5: 27; }; uint32_t val; } h264_int_raw_reg_t; @@ -1937,31 +1070,31 @@ typedef union { typedef union { struct { /** db_tmp_ready_int_st : RO; bitpos: [0]; default: 0; - * Masked status bit: The masked interrupt status of H264_DB_TMP_READY_INT. Valid only - * when the H264_DB_TMP_READY_INT_ENA is set to 1. + * The masked interrupt status of H264_DB_TMP_READY_INT. Valid only when the + * H264_DB_TMP_READY_INT_ENA is set to 1. */ - uint32_t db_tmp_ready_int_st:1; + uint32_t db_tmp_ready_int_st: 1; /** rec_ready_int_st : RO; bitpos: [1]; default: 0; - * Masked status bit: The masked interrupt status of H264_REC_READY_INT. Valid only - * when the H264_REC_READY_INT_ENA is set to 1. + * The masked interrupt status of H264_REC_READY_INT. Valid only when the + * H264_REC_READY_INT_ENA is set to 1. */ - uint32_t rec_ready_int_st:1; + uint32_t rec_ready_int_st: 1; /** frame_done_int_st : RO; bitpos: [2]; default: 0; - * Masked status bit: The masked interrupt status of H264_FRAME_DONE_INT. Valid only - * when the H264_FRAME_DONE_INT_ENA is set to 1. + * The masked interrupt status of H264_FRAME_DONE_INT. Valid only when the + * H264_FRAME_DONE_INT_ENA is set to 1. */ - uint32_t frame_done_int_st:1; + uint32_t frame_done_int_st: 1; /** dma_move_2mb_line_done_int_st : RO; bitpos: [3]; default: 0; * Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. * Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA is set to 1. */ - uint32_t dma_move_2mb_line_done_int_st:1; + uint32_t dma_move_2mb_line_done_int_st: 1; /** bs_buffer_overflow_int_st : RO; bitpos: [4]; default: 0; * Masked status bit: The masked interrupt status of H264_BS_BUFFER_OVERFLOW_INT. * Valid only when the H264_BS_BUFFER_OVERFLOW_INT_ENA is set to 1. */ - uint32_t bs_buffer_overflow_int_st:1; - uint32_t reserved_5:27; + uint32_t bs_buffer_overflow_int_st: 1; + uint32_t reserved_5: 27; }; uint32_t val; } h264_int_st_reg_t; @@ -1972,26 +1105,26 @@ typedef union { typedef union { struct { /** db_tmp_ready_int_ena : R/W; bitpos: [0]; default: 0; - * Enable bit: Write 1 to enable H264_DB_TMP_READY_INT. + * Write 1 to enable H264_DB_TMP_READY_INT. */ - uint32_t db_tmp_ready_int_ena:1; + uint32_t db_tmp_ready_int_ena: 1; /** rec_ready_int_ena : R/W; bitpos: [1]; default: 0; - * Enable bit: Write 1 to enable H264_REC_READY_INT. + * Write 1 to enable H264_REC_READY_INT. */ - uint32_t rec_ready_int_ena:1; + uint32_t rec_ready_int_ena: 1; /** frame_done_int_ena : R/W; bitpos: [2]; default: 0; - * Enable bit: Write 1 to enable H264_FRAME_DONE_INT. + * Write 1 to enable H264_FRAME_DONE_INT. */ - uint32_t frame_done_int_ena:1; + uint32_t frame_done_int_ena: 1; /** dma_move_2mb_line_done_int_ena : R/W; bitpos: [3]; default: 0; * Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT. */ - uint32_t dma_move_2mb_line_done_int_ena:1; + uint32_t dma_move_2mb_line_done_int_ena: 1; /** bs_buffer_overflow_int_ena : R/W; bitpos: [4]; default: 0; * Enable bit: Write 1 to enable H264_BS_BUFFER_OVERFLOW_INT. */ - uint32_t bs_buffer_overflow_int_ena:1; - uint32_t reserved_5:27; + uint32_t bs_buffer_overflow_int_ena: 1; + uint32_t reserved_5: 27; }; uint32_t val; } h264_int_ena_reg_t; @@ -2002,26 +1135,26 @@ typedef union { typedef union { struct { /** db_tmp_ready_int_clr : WT; bitpos: [0]; default: 0; - * Clear bit: Write 1 to clear H264_DB_TMP_READY_INT. + * Write 1 to clear H264_DB_TMP_READY_INT. */ - uint32_t db_tmp_ready_int_clr:1; + uint32_t db_tmp_ready_int_clr: 1; /** rec_ready_int_clr : WT; bitpos: [1]; default: 0; - * Clear bit: Write 1 to clear H264_REC_READY_INT. + * Write 1 to clear H264_REC_READY_INT. */ - uint32_t rec_ready_int_clr:1; + uint32_t rec_ready_int_clr: 1; /** frame_done_int_clr : WT; bitpos: [2]; default: 0; - * Clear bit: Write 1 to clear H264_FRAME_DONE_INT. + * Write 1 to clear H264_FRAME_DONE_INT. */ - uint32_t frame_done_int_clr:1; + uint32_t frame_done_int_clr: 1; /** dma_move_2mb_line_done_int_clr : WT; bitpos: [3]; default: 0; * Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT. */ - uint32_t dma_move_2mb_line_done_int_clr:1; + uint32_t dma_move_2mb_line_done_int_clr: 1; /** bs_buffer_overflow_int_clr : WT; bitpos: [4]; default: 0; * Clear bit: Write 1 to clear H264_BS_BUFFER_OVERFLOW_INT. */ - uint32_t bs_buffer_overflow_int_clr:1; - uint32_t reserved_5:27; + uint32_t bs_buffer_overflow_int_clr: 1; + uint32_t reserved_5: 27; }; uint32_t val; } h264_int_clr_reg_t; @@ -2033,65 +1166,42 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 37823232; + /** ledc_date : R/W; bitpos: [27:0]; default: 37823232; * Configures the version. */ - uint32_t date:28; - uint32_t reserved_28:4; + uint32_t ledc_date: 28; + uint32_t reserved_28: 4; }; uint32_t val; } h264_date_reg_t; +typedef struct { + volatile h264_sys_mb_res_reg_t sys_mb_res; + volatile h264_sys_conf_reg_t sys_conf; + volatile h264_deci_score_reg_t deci_score; + volatile h264_deci_score_offset_reg_t deci_score_offset; + volatile h264_rc_conf0_reg_t rc_conf0; + volatile h264_rc_conf1_reg_t rc_conf1; + volatile h264_db_bypass_reg_t db_bypass; + volatile h264_roi_region_reg_t roi_region[8]; + volatile h264_roi_region0_3_qp_reg_t roi_region0_3_qp; + volatile h264_roi_region4_7_qp_reg_t roi_region4_7_qp; + volatile h264_no_roi_region_qp_offset_reg_t no_roi_region_qp_offset; + volatile h264_roi_config_reg_t roi_config; +} h264_ctrl_regs_t; + typedef struct { volatile h264_sys_ctrl_reg_t sys_ctrl; volatile h264_gop_conf_reg_t gop_conf; - volatile h264_a_sys_mb_res_reg_t a_sys_mb_res; - volatile h264_a_sys_conf_reg_t a_sys_conf; - volatile h264_a_deci_score_reg_t a_deci_score; - volatile h264_a_deci_score_offset_reg_t a_deci_score_offset; - volatile h264_a_rc_conf0_reg_t a_rc_conf0; - volatile h264_a_rc_conf1_reg_t a_rc_conf1; - volatile h264_a_db_bypass_reg_t a_db_bypass; - volatile h264_a_roi_region0_reg_t a_roi_region0; - volatile h264_a_roi_region1_reg_t a_roi_region1; - volatile h264_a_roi_region2_reg_t a_roi_region2; - volatile h264_a_roi_region3_reg_t a_roi_region3; - volatile h264_a_roi_region4_reg_t a_roi_region4; - volatile h264_a_roi_region5_reg_t a_roi_region5; - volatile h264_a_roi_region6_reg_t a_roi_region6; - volatile h264_a_roi_region7_reg_t a_roi_region7; - volatile h264_a_roi_region0_3_qp_reg_t a_roi_region0_3_qp; - volatile h264_a_roi_region4_7_qp_reg_t a_roi_region4_7_qp; - volatile h264_a_no_roi_region_qp_offset_reg_t a_no_roi_region_qp_offset; - volatile h264_a_roi_config_reg_t a_roi_config; - volatile h264_b_sys_mb_res_reg_t b_sys_mb_res; - volatile h264_b_sys_conf_reg_t b_sys_conf; - volatile h264_b_deci_score_reg_t b_deci_score; - volatile h264_b_deci_score_offset_reg_t b_deci_score_offset; - volatile h264_b_rc_conf0_reg_t b_rc_conf0; - volatile h264_b_rc_conf1_reg_t b_rc_conf1; - volatile h264_b_db_bypass_reg_t b_db_bypass; - volatile h264_b_roi_region0_reg_t b_roi_region0; - volatile h264_b_roi_region1_reg_t b_roi_region1; - volatile h264_b_roi_region2_reg_t b_roi_region2; - volatile h264_b_roi_region3_reg_t b_roi_region3; - volatile h264_b_roi_region4_reg_t b_roi_region4; - volatile h264_b_roi_region5_reg_t b_roi_region5; - volatile h264_b_roi_region6_reg_t b_roi_region6; - volatile h264_b_roi_region7_reg_t b_roi_region7; - volatile h264_b_roi_region0_3_qp_reg_t b_roi_region0_3_qp; - volatile h264_b_roi_region4_7_qp_reg_t b_roi_region4_7_qp; - volatile h264_b_no_roi_region_qp_offset_reg_t b_no_roi_region_qp_offset; - volatile h264_b_roi_config_reg_t b_roi_config; + volatile h264_ctrl_regs_t ctrl[2]; volatile h264_rc_status0_reg_t rc_status0; volatile h264_rc_status1_reg_t rc_status1; volatile h264_rc_status2_reg_t rc_status2; volatile h264_slice_header_remain_reg_t slice_header_remain; volatile h264_slice_header_byte_length_reg_t slice_header_byte_length; volatile h264_bs_threshold_reg_t bs_threshold; - volatile h264_slice_header_byte0_reg_t slice_header_byte0; - volatile h264_slice_header_byte1_reg_t slice_header_byte1; + volatile h264_slice_header_reg_t slice_header[2]; volatile h264_int_raw_reg_t int_raw; volatile h264_int_st_reg_t int_st; volatile h264_int_ena_reg_t int_ena; @@ -2105,8 +1215,7 @@ typedef struct { volatile h264_debug_info1_reg_t debug_info1; volatile h264_debug_info2_reg_t debug_info2; volatile h264_date_reg_t date; - volatile h264_a_ori_conf_reg_t a_ori_conf; - volatile h264_b_ori_conf_reg_t b_ori_conf; + volatile h264_ori_conf_reg_t ori_conf[2]; volatile h264_ori_debug_conf_reg_t ori_debug_conf; volatile h264_mv_merge_debug_conf_reg_t mv_merge_debug_conf; volatile h264_bs_debug_cong_reg_t bs_debug_cong; @@ -2116,8 +1225,6 @@ typedef struct { volatile h264_ref_debug_cong_reg_t ref_debug_cong; } h264_dev_t; -extern h264_dev_t H264; - #ifndef __cplusplus _Static_assert(sizeof(h264_dev_t) == 0x118, "Invalid size of h264_dev_t structure"); #endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i2c_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/i2c_eco5_struct.h deleted file mode 100644 index 4f3e3789ebc1..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/i2c_eco5_struct.h +++ /dev/null @@ -1,1235 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Timing registers */ -/** Type of scl_low_period register - * Configures the low level width of the SCL - * Clock - */ -typedef union { - struct { - /** scl_low_period : R/W; bitpos: [8:0]; default: 0; - * Configures the low level width of the SCL Clock in master mode. - * Measurement unit: i2c_sclk - */ - uint32_t scl_low_period:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} i2c_scl_low_period_reg_t; - -/** Type of sda_hold register - * Configures the hold time after a negative SCL edge - */ -typedef union { - struct { - /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; - * Configures the time to hold the data after the falling edge of SCL. - * Measurement unit: i2c_sclk - */ - uint32_t sda_hold_time:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} i2c_sda_hold_reg_t; - -/** Type of sda_sample register - * Configures the sample time after a positive SCL edge - */ -typedef union { - struct { - /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; - * Configures the time for sampling SDA. - * Measurement unit: i2c_sclk - */ - uint32_t sda_sample_time:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} i2c_sda_sample_reg_t; - -/** Type of scl_high_period register - * Configures the high level width of SCL - */ -typedef union { - struct { - /** scl_high_period : R/W; bitpos: [8:0]; default: 0; - * Configures for how long SCL remains high in master mode. - * Measurement unit: i2c_sclk - */ - uint32_t scl_high_period:9; - /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; - * Configures the SCL_FSM's waiting period for SCL high level in master mode. - * Measurement unit: i2c_sclk - */ - uint32_t scl_wait_high_period:7; - uint32_t reserved_16:16; - }; - uint32_t val; -} i2c_scl_high_period_reg_t; - -/** Type of scl_start_hold register - * Configures the delay between the SDA and SCL negative edge for a start condition - */ -typedef union { - struct { - /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; - * Configures the time between the falling edge of SDA and the falling edge of SCL for - * a START condition. - * Measurement unit: i2c_sclk - */ - uint32_t scl_start_hold_time:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} i2c_scl_start_hold_reg_t; - -/** Type of scl_rstart_setup register - * Configures the delay between the positive - * edge of SCL and the negative edge of SDA - */ -typedef union { - struct { - /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; - * Configures the time between the positive edge of SCL and the negative edge of SDA - * for a RESTART condition. - * Measurement unit: i2c_sclk - */ - uint32_t scl_rstart_setup_time:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} i2c_scl_rstart_setup_reg_t; - -/** Type of scl_stop_hold register - * Configures the delay after the SCL clock - * edge for a stop condition - */ -typedef union { - struct { - /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; - * Configures the delay after the STOP condition. - * Measurement unit: i2c_sclk - */ - uint32_t scl_stop_hold_time:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} i2c_scl_stop_hold_reg_t; - -/** Type of scl_stop_setup register - * Configures the delay between the SDA and - * SCL positive edge for a stop condition - */ -typedef union { - struct { - /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8; - * This register is used to configure the time between the positive edgeof SCL and the - * positive edge of SDA, in I2C module clock cycles. - */ - uint32_t scl_stop_setup_time:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} i2c_scl_stop_setup_reg_t; - -/** Type of scl_st_time_out register - * SCL status time out register - */ -typedef union { - struct { - /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; - * Configures the threshold value of SCL_FSM state unchanged period. It should be no - * more than 23. - * Measurement unit: i2c_sclk - */ - uint32_t scl_st_to_i2c:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} i2c_scl_st_time_out_reg_t; - -/** Type of scl_main_st_time_out register - * SCL main status time out register - */ -typedef union { - struct { - /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; - * Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be - * no more than 23. - * Measurement unit: i2c_sclk - */ - uint32_t scl_main_st_to_i2c:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} i2c_scl_main_st_time_out_reg_t; - - -/** Group: Configuration registers */ -/** Type of ctr register - * Transmission setting - */ -typedef union { - struct { - /** sda_force_out : R/W; bitpos: [0]; default: 0; - * Configures the SDA output mode. - * 0: Open drain output - * 1: Direct output - */ - uint32_t sda_force_out:1; - /** scl_force_out : R/W; bitpos: [1]; default: 0; - * Configures the SCL output mode. - * 0: Open drain output - * 1: Direct output - */ - uint32_t scl_force_out:1; - /** sample_scl_level : R/W; bitpos: [2]; default: 0; - * Configures the sample mode for SDA. - * 0: Sample SDA data on the SCL high level - * 1: Sample SDA data on the SCL low level - */ - uint32_t sample_scl_level:1; - /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; - * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has - * reached the threshold. - */ - uint32_t rx_full_ack_level:1; - /** ms_mode : R/W; bitpos: [4]; default: 0; - * Configures the module as an I2C Master or Slave. - * 0: Slave - * 1: Master - */ - uint32_t ms_mode:1; - /** trans_start : WT; bitpos: [5]; default: 0; - * Configures whether the slave starts sending the data in txfifo. - * 0: No effect - * 1: Start - */ - uint32_t trans_start:1; - /** tx_lsb_first : R/W; bitpos: [6]; default: 0; - * Configures to control the sending order for data needing to be sent. - * 0: send data from the most significant bit - * 1: send data from the least significant bit - */ - uint32_t tx_lsb_first:1; - /** rx_lsb_first : R/W; bitpos: [7]; default: 0; - * Configures to control the storage order for received data. - * 0: receive data from the most significant bit - * 1: receive data from the least significant bit - */ - uint32_t rx_lsb_first:1; - /** clk_en : R/W; bitpos: [8]; default: 0; - * Configures whether to gate clock signal for registers. - * 0: Support clock only when registers are read or written to by software - * 1: Force clock on for registers - */ - uint32_t clk_en:1; - /** arbitration_en : R/W; bitpos: [9]; default: 1; - * Configures to enable I2C bus arbitration detection. - * 0: No effect - * 1: Enable - */ - uint32_t arbitration_en:1; - /** fsm_rst : WT; bitpos: [10]; default: 0; - * Configures to reset the SCL_FSM. - * 0: No effect - * 1: Reset - */ - uint32_t fsm_rst:1; - /** conf_upgate : WT; bitpos: [11]; default: 0; - * Configures this bit for synchronization. - * 0: No effect - * 1: Synchronize - */ - uint32_t conf_upgate:1; - /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0; - * Configures to enable slave to send data automatically - * 0: Disable - * 1: Enable - */ - uint32_t slv_tx_auto_start_en:1; - /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0; - * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. - * 0: Not check - * 1: Check - */ - uint32_t addr_10bit_rw_check_en:1; - /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0; - * Configures to support the 7 bit general call function. - * 0: Not support - * 1: Support - */ - uint32_t addr_broadcasting_en:1; - uint32_t reserved_15:17; - }; - uint32_t val; -} i2c_ctr_reg_t; - -/** Type of to register - * Setting time out control for receiving data - */ -typedef union { - struct { - /** time_out_value : R/W; bitpos: [4:0]; default: 16; - * Configures the timeout threshold period for SCL stucking at high or low level. The - * actual period is 2\^{}(reg_time_out_value). - * Measurement unit: i2c_sclk - */ - uint32_t time_out_value:5; - /** time_out_en : R/W; bitpos: [5]; default: 0; - * Configures to enable time out control. - * 0: No effect - * 1: Enable - */ - uint32_t time_out_en:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} i2c_to_reg_t; - -/** Type of slave_addr register - * Local slave address setting - */ -typedef union { - struct { - /** slave_addr : R/W; bitpos: [14:0]; default: 0; - * Configure the slave address of I2C Slave. - */ - uint32_t slave_addr:15; - uint32_t reserved_15:16; - /** addr_10bit_en : R/W; bitpos: [31]; default: 0; - * Configures to enable the slave 10-bit addressing mode in master mode. - * 0: No effect - * 1: Enable - */ - uint32_t addr_10bit_en:1; - }; - uint32_t val; -} i2c_slave_addr_reg_t; - -/** Type of fifo_conf register - * FIFO configuration register - */ -typedef union { - struct { - /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11; - * Configures the water mark threshold of RXFIFO in nonfifo access mode. When - * I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0], - * I2C_RXFIFO_WM_INT_RAW bit will be valid. - * \tododone{For CJ, please check this description. I habe doubt about - * reg_reg_fifo_prt_en.CJ: modified} - */ - uint32_t rxfifo_wm_thrhd:5; - /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4; - * Configures the water mark threshold of TXFIFO in nonfifo access mode. When - * I2C_FIFO_PRT_EN is 1 and TC FIFO counter is bigger than I2C_TXFIFO_WM_THRHD[4:0], - * I2C_TXFIFO_WM_INT_RAW bit will be valid. - */ - uint32_t txfifo_wm_thrhd:5; - /** nonfifo_en : R/W; bitpos: [10]; default: 0; - * Configures to enable APB nonfifo access. - */ - uint32_t nonfifo_en:1; - /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0; - * Configures the slave to enable dual address mode. When this mode is enabled, the - * byte received after the I2C address byte represents the offset address in the I2C - * Slave RAM. - * 0: Disable - * 1: Enable - */ - uint32_t fifo_addr_cfg_en:1; - /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; - * Configures to reset RXFIFO. - * 0: No effect - * 1: Reset - */ - uint32_t rx_fifo_rst:1; - /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; - * Configures to reset TXFIFO. - * 0: No effect - * 1: Reset - */ - uint32_t tx_fifo_rst:1; - /** fifo_prt_en : R/W; bitpos: [14]; default: 1; - * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the - * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. - * 0: No effect - * 1: Enable - */ - uint32_t fifo_prt_en:1; - uint32_t reserved_15:17; - }; - uint32_t val; -} i2c_fifo_conf_reg_t; - -/** Type of filter_cfg register - * SCL and SDA filter configuration register - */ -typedef union { - struct { - /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0; - * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL - * input has smaller width than this register value, the I2C controller will ignore - * that pulse. - * Measurement unit: i2c_sclk - */ - uint32_t scl_filter_thres:4; - /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; - * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA - * input has smaller width than this register value, the I2C controller will ignore - * that pulse. - * Measurement unit: i2c_sclk - */ - uint32_t sda_filter_thres:4; - /** scl_filter_en : R/W; bitpos: [8]; default: 1; - * Configures to enable the filter function for SCL. - * 0: No effect - * 1: Enable - */ - uint32_t scl_filter_en:1; - /** sda_filter_en : R/W; bitpos: [9]; default: 1; - * Configures to enable the filter function for SDA. - * 0: No effect - * 1: Enable - */ - uint32_t sda_filter_en:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} i2c_filter_cfg_reg_t; - -/** Type of scl_sp_conf register - * Power configuration register - */ -typedef union { - struct { - /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0; - * Configures to send out SCL pulses when I2C master is IDLE. The number of pulses - * equals to I2C_SCL_RST_SLV_NUM[4:0]. - */ - uint32_t scl_rst_slv_en:1; - /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; - * Configure the pulses of SCL generated in I2C master mode. - * Valid when I2C_SCL_RST_SLV_EN is 1. - * Measurement unit: i2c_sclk - */ - uint32_t scl_rst_slv_num:5; - /** scl_pd_en : R/W; bitpos: [6]; default: 0; - * Configures to power down the I2C output SCL line. - * 0: Not power down. - * 1: Not work and power down. - * Valid only when I2C_SCL_FORCE_OUT is 1. - */ - uint32_t scl_pd_en:1; - /** sda_pd_en : R/W; bitpos: [7]; default: 0; - * Configures to power down the I2C output SDA line. - * 0: Not power down. - * 1: Not work and power down. - * Valid only when I2C_SDA_FORCE_OUT is 1. - */ - uint32_t sda_pd_en:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} i2c_scl_sp_conf_reg_t; - -/** Type of scl_stretch_conf register - * Set SCL stretch of I2C slave - */ -typedef union { - struct { - /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0; - * Configures the time period to release the SCL line from stretching to avoid timing - * violation. Usually it should be larger than the SDA setup time. - * Measurement unit: i2c_sclk - */ - uint32_t stretch_protect_num:10; - /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0; - * Configures to enable slave SCL stretch function. The SCL output line will be - * stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The - * stretch cause can be seen in I2C_STRETCH_CAUSE. - * 0: Disable - * 1: Enable - */ - uint32_t slave_scl_stretch_en:1; - /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0; - * Configures to clear the I2C slave SCL stretch function. - * 0: No effect - * 1: Clear - */ - uint32_t slave_scl_stretch_clr:1; - /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0; - * Configures to enable the function for slave to control ACK level. - * 0: Disable - * 1: Enable - */ - uint32_t slave_byte_ack_ctl_en:1; - /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0; - * Set the ACK level when slave controlling ACK level function enables. - * 0: Low level - * 1: High level - */ - uint32_t slave_byte_ack_lvl:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} i2c_scl_stretch_conf_reg_t; - - -/** Group: Status registers */ -/** Type of sr register - * Describe I2C work status - */ -typedef union { - struct { - /** resp_rec : RO; bitpos: [0]; default: 0; - * Represents the received ACK value in master mode or slave mode. - * 0: ACK - * 1: NACK. - */ - uint32_t resp_rec:1; - /** slave_rw : RO; bitpos: [1]; default: 0; - * Represents the transfer direction in slave mode. - * 1: Master reads from slave - * 0: Master writes to slave. - */ - uint32_t slave_rw:1; - uint32_t reserved_2:1; - /** arb_lost : RO; bitpos: [3]; default: 0; - * Represents whether the I2C controller loses control of SCL line. - * 0: No arbitration lost - * 1: Arbitration lost - */ - uint32_t arb_lost:1; - /** bus_busy : RO; bitpos: [4]; default: 0; - * Represents the I2C bus state. - * 1: The I2C bus is busy transferring data - * 0: The I2C bus is in idle state. - */ - uint32_t bus_busy:1; - /** slave_addressed : RO; bitpos: [5]; default: 0; - * Represents whether the address sent by the master is equal to the address of the - * slave. - * Valid only when the module is configured as an I2C Slave. - * 0: Not equal - * 1: Equal - */ - uint32_t slave_addressed:1; - uint32_t reserved_6:2; - /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0; - * Represents the number of data bytes received in RAM. - */ - uint32_t rxfifo_cnt:6; - /** stretch_cause : RO; bitpos: [15:14]; default: 3; - * Represents the cause of SCL clocking stretching in slave mode. - * 0: Stretching SCL low when the master starts to read data. - * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode. - * 2: Stretching SCL low when I2C RX FIFO is full in slave mode. - */ - uint32_t stretch_cause:2; - uint32_t reserved_16:2; - /** txfifo_cnt : RO; bitpos: [23:18]; default: 0; - * Represents the number of data bytes to be sent. - */ - uint32_t txfifo_cnt:6; - /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; - * Represents the states of the I2C module state machine. - * 0: Idle - * 1: Address shift - * 2: ACK address - * 3: Rx data - * 4: Tx data - * 5: Send ACK - * 6: Wait ACK - */ - uint32_t scl_main_state_last:3; - uint32_t reserved_27:1; - /** scl_state_last : RO; bitpos: [30:28]; default: 0; - * Represents the states of the state machine used to produce SCL. - * 0: Idle - * 1: Start - * 2: Negative edge - * 3: Low - * 4: Positive edge - * 5: High - * 6: Stop - */ - uint32_t scl_state_last:3; - uint32_t reserved_31:1; - }; - uint32_t val; -} i2c_sr_reg_t; - -/** Type of fifo_st register - * FIFO status register - */ -typedef union { - struct { - /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0; - * Represents the offset address of the APB reading from RXFIFO. - */ - uint32_t rxfifo_raddr:5; - /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0; - * Represents the offset address of i2c module receiving data and writing to RXFIFO. - */ - uint32_t rxfifo_waddr:5; - /** txfifo_raddr : RO; bitpos: [14:10]; default: 0; - * Represents the offset address of i2c module reading from TXFIFO. - */ - uint32_t txfifo_raddr:5; - /** txfifo_waddr : RO; bitpos: [19:15]; default: 0; - * Represents the offset address of APB bus writing to TXFIFO. - */ - uint32_t txfifo_waddr:5; - uint32_t reserved_20:2; - /** slave_rw_point : RO; bitpos: [29:22]; default: 0; - * Represents the offset address in the I2C Slave RAM addressed by I2C Master when in - * I2C slave mode. - */ - uint32_t slave_rw_point:8; - uint32_t reserved_30:2; - }; - uint32_t val; -} i2c_fifo_st_reg_t; - -/** Type of data register - * Rx FIFO read data - */ -typedef union { - struct { - /** fifo_rdata : HRO; bitpos: [7:0]; default: 0; - * Represents the value of RXFIFO read data. - */ - uint32_t fifo_rdata:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} i2c_data_reg_t; - - -/** Group: Interrupt registers */ -/** Type of int_raw register - * Raw interrupt status - */ -typedef union { - struct { - /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. - */ - uint32_t rxfifo_wm_int_raw:1; - /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1; - * The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. - */ - uint32_t txfifo_wm_int_raw:1; - /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0; - * The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. - */ - uint32_t rxfifo_ovf_int_raw:1; - /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0; - * The raw interrupt status of the I2C_END_DETECT_INT interrupt. - */ - uint32_t end_detect_int_raw:1; - /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0; - * The raw interrupt status of the I2C_END_DETECT_INT interrupt. - */ - uint32_t byte_trans_done_int_raw:1; - /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0; - * The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. - */ - uint32_t arbitration_lost_int_raw:1; - /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0; - * The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t mst_txfifo_udf_int_raw:1; - /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0; - * The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t trans_complete_int_raw:1; - /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0; - * The raw interrupt status of the I2C_TIME_OUT_INT interrupt. - */ - uint32_t time_out_int_raw:1; - /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0; - * The raw interrupt status of the I2C_TRANS_START_INT interrupt. - */ - uint32_t trans_start_int_raw:1; - /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0; - * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t nack_int_raw:1; - /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0; - * The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. - */ - uint32_t txfifo_ovf_int_raw:1; - /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0; - * The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. - */ - uint32_t rxfifo_udf_int_raw:1; - /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0; - * The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. - */ - uint32_t scl_st_to_int_raw:1; - /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0; - * The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. - */ - uint32_t scl_main_st_to_int_raw:1; - /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0; - * The raw interrupt status of I2C_DET_START_INT interrupt. - */ - uint32_t det_start_int_raw:1; - /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0; - * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t slave_stretch_int_raw:1; - /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0; - * The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. - */ - uint32_t general_call_int_raw:1; - /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0; - * The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. - */ - uint32_t slave_addr_unmatch_int_raw:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} i2c_int_raw_reg_t; - -/** Type of int_clr register - * Interrupt clear bits - */ -typedef union { - struct { - /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear I2C_RXFIFO_WM_INT interrupt. - */ - uint32_t rxfifo_wm_int_clr:1; - /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear I2C_TXFIFO_WM_INT interrupt. - */ - uint32_t txfifo_wm_int_clr:1; - /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. - */ - uint32_t rxfifo_ovf_int_clr:1; - /** end_detect_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear the I2C_END_DETECT_INT interrupt. - */ - uint32_t end_detect_int_clr:1; - /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear the I2C_END_DETECT_INT interrupt. - */ - uint32_t byte_trans_done_int_clr:1; - /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. - */ - uint32_t arbitration_lost_int_clr:1; - /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t mst_txfifo_udf_int_clr:1; - /** trans_complete_int_clr : WT; bitpos: [7]; default: 0; - * Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t trans_complete_int_clr:1; - /** time_out_int_clr : WT; bitpos: [8]; default: 0; - * Write 1 to clear the I2C_TIME_OUT_INT interrupt. - */ - uint32_t time_out_int_clr:1; - /** trans_start_int_clr : WT; bitpos: [9]; default: 0; - * Write 1 to clear the I2C_TRANS_START_INT interrupt. - */ - uint32_t trans_start_int_clr:1; - /** nack_int_clr : WT; bitpos: [10]; default: 0; - * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t nack_int_clr:1; - /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0; - * Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. - */ - uint32_t txfifo_ovf_int_clr:1; - /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0; - * Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. - */ - uint32_t rxfifo_udf_int_clr:1; - /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0; - * Write 1 to clear I2C_SCL_ST_TO_INT interrupt. - */ - uint32_t scl_st_to_int_clr:1; - /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0; - * Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. - */ - uint32_t scl_main_st_to_int_clr:1; - /** det_start_int_clr : WT; bitpos: [15]; default: 0; - * Write 1 to clear I2C_DET_START_INT interrupt. - */ - uint32_t det_start_int_clr:1; - /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0; - * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t slave_stretch_int_clr:1; - /** general_call_int_clr : WT; bitpos: [17]; default: 0; - * Write 1 to clear I2C_GENARAL_CALL_INT interrupt. - */ - uint32_t general_call_int_clr:1; - /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0; - * Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. - */ - uint32_t slave_addr_unmatch_int_clr:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} i2c_int_clr_reg_t; - -/** Type of int_ena register - * Interrupt enable bits - */ -typedef union { - struct { - /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable I2C_RXFIFO_WM_INT interrupt. - */ - uint32_t rxfifo_wm_int_ena:1; - /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable I2C_TXFIFO_WM_INT interrupt. - */ - uint32_t txfifo_wm_int_ena:1; - /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. - */ - uint32_t rxfifo_ovf_int_ena:1; - /** end_detect_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable the I2C_END_DETECT_INT interrupt. - */ - uint32_t end_detect_int_ena:1; - /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable the I2C_END_DETECT_INT interrupt. - */ - uint32_t byte_trans_done_int_ena:1; - /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. - */ - uint32_t arbitration_lost_int_ena:1; - /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t mst_txfifo_udf_int_ena:1; - /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0; - * Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t trans_complete_int_ena:1; - /** time_out_int_ena : R/W; bitpos: [8]; default: 0; - * Write 1 to enable the I2C_TIME_OUT_INT interrupt. - */ - uint32_t time_out_int_ena:1; - /** trans_start_int_ena : R/W; bitpos: [9]; default: 0; - * Write 1 to enable the I2C_TRANS_START_INT interrupt. - */ - uint32_t trans_start_int_ena:1; - /** nack_int_ena : R/W; bitpos: [10]; default: 0; - * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t nack_int_ena:1; - /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0; - * Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. - */ - uint32_t txfifo_ovf_int_ena:1; - /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0; - * Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. - */ - uint32_t rxfifo_udf_int_ena:1; - /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0; - * Write 1 to enable I2C_SCL_ST_TO_INT interrupt. - */ - uint32_t scl_st_to_int_ena:1; - /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0; - * Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. - */ - uint32_t scl_main_st_to_int_ena:1; - /** det_start_int_ena : R/W; bitpos: [15]; default: 0; - * Write 1 to enable I2C_DET_START_INT interrupt. - */ - uint32_t det_start_int_ena:1; - /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0; - * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t slave_stretch_int_ena:1; - /** general_call_int_ena : R/W; bitpos: [17]; default: 0; - * Write 1 to enable I2C_GENARAL_CALL_INT interrupt. - */ - uint32_t general_call_int_ena:1; - /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0; - * Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. - */ - uint32_t slave_addr_unmatch_int_ena:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} i2c_int_ena_reg_t; - -/** Type of int_status register - * Status of captured I2C communication events - */ -typedef union { - struct { - /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. - */ - uint32_t rxfifo_wm_int_st:1; - /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. - */ - uint32_t txfifo_wm_int_st:1; - /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. - */ - uint32_t rxfifo_ovf_int_st:1; - /** end_detect_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. - */ - uint32_t end_detect_int_st:1; - /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. - */ - uint32_t byte_trans_done_int_st:1; - /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. - */ - uint32_t arbitration_lost_int_st:1; - /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t mst_txfifo_udf_int_st:1; - /** trans_complete_int_st : RO; bitpos: [7]; default: 0; - * The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. - */ - uint32_t trans_complete_int_st:1; - /** time_out_int_st : RO; bitpos: [8]; default: 0; - * The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. - */ - uint32_t time_out_int_st:1; - /** trans_start_int_st : RO; bitpos: [9]; default: 0; - * The masked interrupt status status of the I2C_TRANS_START_INT interrupt. - */ - uint32_t trans_start_int_st:1; - /** nack_int_st : RO; bitpos: [10]; default: 0; - * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t nack_int_st:1; - /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0; - * The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. - */ - uint32_t txfifo_ovf_int_st:1; - /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0; - * The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. - */ - uint32_t rxfifo_udf_int_st:1; - /** scl_st_to_int_st : RO; bitpos: [13]; default: 0; - * The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. - */ - uint32_t scl_st_to_int_st:1; - /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0; - * The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. - */ - uint32_t scl_main_st_to_int_st:1; - /** det_start_int_st : RO; bitpos: [15]; default: 0; - * The masked interrupt status status of I2C_DET_START_INT interrupt. - */ - uint32_t det_start_int_st:1; - /** slave_stretch_int_st : RO; bitpos: [16]; default: 0; - * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. - */ - uint32_t slave_stretch_int_st:1; - /** general_call_int_st : RO; bitpos: [17]; default: 0; - * The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. - */ - uint32_t general_call_int_st:1; - /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0; - * The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. - */ - uint32_t slave_addr_unmatch_int_st:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} i2c_int_status_reg_t; - - -/** Group: Command registers */ -/** Type of comd0 register - * I2C command register 0 - */ -typedef union { - struct { - /** command0 : R/W; bitpos: [13:0]; default: 0; - * Configures command 0. - * It consists of three parts: - * op_code is the command - * 1: WRITE - * 2: STOP - * 3: READ - * 4: END - * 6: RSTART - * Byte_num represents the number of bytes that need to be sent or received. - * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure for more information. - * \tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}" - */ - uint32_t command0:14; - uint32_t reserved_14:17; - /** command0_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 0 is done in I2C Master mode. - * 0: Not done - * 1: Done - */ - uint32_t command0_done:1; - }; - uint32_t val; -} i2c_comd0_reg_t; - -/** Type of comd1 register - * I2C command register 1 - */ -typedef union { - struct { - /** command1 : R/W; bitpos: [13:0]; default: 0; - * Configures command 1. - * See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command1:14; - uint32_t reserved_14:17; - /** command1_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 1 is done in I2C Master mode. - * 0: Not done - * 1: Done - */ - uint32_t command1_done:1; - }; - uint32_t val; -} i2c_comd1_reg_t; - -/** Type of comd2 register - * I2C command register 2 - */ -typedef union { - struct { - /** command2 : R/W; bitpos: [13:0]; default: 0; - * Configures command 2. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command2:14; - uint32_t reserved_14:17; - /** command2_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 2 is done in I2C Master mode. - * 0: Not done - * 1: Done - */ - uint32_t command2_done:1; - }; - uint32_t val; -} i2c_comd2_reg_t; - -/** Type of comd3 register - * I2C command register 3 - */ -typedef union { - struct { - /** command3 : R/W; bitpos: [13:0]; default: 0; - * Configures command 3. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command3:14; - uint32_t reserved_14:17; - /** command3_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 3 is done in I2C Master mode. - * 0: Not done - * 1: Done - */ - uint32_t command3_done:1; - }; - uint32_t val; -} i2c_comd3_reg_t; - -/** Type of comd4 register - * I2C command register 4 - */ -typedef union { - struct { - /** command4 : R/W; bitpos: [13:0]; default: 0; - * Configures command 4. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command4:14; - uint32_t reserved_14:17; - /** command4_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 4 is done in I2C Master mode. - * 0: Not done - * 1: Done - */ - uint32_t command4_done:1; - }; - uint32_t val; -} i2c_comd4_reg_t; - -/** Type of comd5 register - * I2C command register 5 - */ -typedef union { - struct { - /** command5 : R/W; bitpos: [13:0]; default: 0; - * Configures command 5. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command5:14; - uint32_t reserved_14:17; - /** command5_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 5 is done in I2C Master mode. - * 0: Not done - * 1: Done - */ - uint32_t command5_done:1; - }; - uint32_t val; -} i2c_comd5_reg_t; - -/** Type of comd6 register - * I2C command register 6 - */ -typedef union { - struct { - /** command6 : R/W; bitpos: [13:0]; default: 0; - * Configures command 6. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command6:14; - uint32_t reserved_14:17; - /** command6_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 6 is done in I2C Master mode. - * 0: Not done - * 1: Done - */ - uint32_t command6_done:1; - }; - uint32_t val; -} i2c_comd6_reg_t; - -/** Type of comd7 register - * I2C command register 7 - */ -typedef union { - struct { - /** command7 : R/W; bitpos: [13:0]; default: 0; - * Configures command 7. See details in I2C_CMD0_REG[13:0]. - */ - uint32_t command7:14; - uint32_t reserved_14:17; - /** command7_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 7 is done in I2C Master mode. - * 0: Not done - * 1: Done - */ - uint32_t command7_done:1; - }; - uint32_t val; -} i2c_comd7_reg_t; - - -/** Group: Version register */ -/** Type of date register - * Version register - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 37765248; - * Version control register. - */ - uint32_t date:32; - }; - uint32_t val; -} i2c_date_reg_t; - - -/** Group: Address register */ -/** Type of txfifo_start_addr register - * I2C TXFIFO base address register - */ -typedef union { - struct { - /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; - * Represents the I2C txfifo first address. - */ - uint32_t txfifo_start_addr:32; - }; - uint32_t val; -} i2c_txfifo_start_addr_reg_t; - -/** Type of rxfifo_start_addr register - * I2C RXFIFO base address register - */ -typedef union { - struct { - /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; - * Represents the I2C rxfifo first address. - */ - uint32_t rxfifo_start_addr:32; - }; - uint32_t val; -} i2c_rxfifo_start_addr_reg_t; - - -typedef struct { - volatile i2c_scl_low_period_reg_t scl_low_period; - volatile i2c_ctr_reg_t ctr; - volatile i2c_sr_reg_t sr; - volatile i2c_to_reg_t to; - volatile i2c_slave_addr_reg_t slave_addr; - volatile i2c_fifo_st_reg_t fifo_st; - volatile i2c_fifo_conf_reg_t fifo_conf; - volatile i2c_data_reg_t data; - volatile i2c_int_raw_reg_t int_raw; - volatile i2c_int_clr_reg_t int_clr; - volatile i2c_int_ena_reg_t int_ena; - volatile i2c_int_status_reg_t int_status; - volatile i2c_sda_hold_reg_t sda_hold; - volatile i2c_sda_sample_reg_t sda_sample; - volatile i2c_scl_high_period_reg_t scl_high_period; - uint32_t reserved_03c; - volatile i2c_scl_start_hold_reg_t scl_start_hold; - volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup; - volatile i2c_scl_stop_hold_reg_t scl_stop_hold; - volatile i2c_scl_stop_setup_reg_t scl_stop_setup; - volatile i2c_filter_cfg_reg_t filter_cfg; - uint32_t reserved_054; - volatile i2c_comd0_reg_t comd0; - volatile i2c_comd1_reg_t comd1; - volatile i2c_comd2_reg_t comd2; - volatile i2c_comd3_reg_t comd3; - volatile i2c_comd4_reg_t comd4; - volatile i2c_comd5_reg_t comd5; - volatile i2c_comd6_reg_t comd6; - volatile i2c_comd7_reg_t comd7; - volatile i2c_scl_st_time_out_reg_t scl_st_time_out; - volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; - volatile i2c_scl_sp_conf_reg_t scl_sp_conf; - volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf; - uint32_t reserved_088[28]; - volatile i2c_date_reg_t date; - uint32_t reserved_0fc; - volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; - uint32_t reserved_104[31]; - volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; -} i2c_dev_t; - -extern i2c_dev_t I2C0; -extern i2c_dev_t I2C1; - -#ifndef __cplusplus -_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i2c_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/i2c_struct.h index b8c06265a140..f1a5729968bf 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/i2c_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/i2c_struct.h @@ -235,9 +235,9 @@ typedef union { /** clk_en : R/W; bitpos: [8]; default: 0; * Configures whether to gate clock signal for registers. * - * 0: Force clock on for registers + * 0: Support clock only when registers are read or written to by software * - * 1: Support clock only when registers are read or written to by software. + * 1: Force clock on for registers */ uint32_t clk_en:1; /** arbitration_en : R/W; bitpos: [9]; default: 1; @@ -550,7 +550,7 @@ typedef union { uint32_t slave_addressed:1; uint32_t reserved_6:2; /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0; - * Represents the number of data bytes to be sent. + * Represents the number of data bytes received in RAM. */ uint32_t rxfifo_cnt:6; /** stretch_cause : RO; bitpos: [15:14]; default: 3; @@ -564,7 +564,7 @@ typedef union { uint32_t stretch_cause:2; uint32_t reserved_16:2; /** txfifo_cnt : RO; bitpos: [23:18]; default: 0; - * Represents the number of data bytes received in RAM. + * Represents the number of data bytes to be sent. */ uint32_t txfifo_cnt:6; /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; @@ -1009,11 +1009,11 @@ typedef union { /** command : R/W; bitpos: [13:0]; default: 0; * Configures command. It consists of three parts: * op_code is the command, - * 0: RSTART, - * 1: WRITE, - * 2: READ, - * 3: STOP, - * 4: END. + * 1: WRITE + * 2: STOP + * 3: READ + * 4: END + * 6: RSTART * * Byte_num represents the number of bytes that need to be sent or received. * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd diff --git a/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_qos_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_qos_struct.h index 8e66405ca97b..4fbe7cbe1e32 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_qos_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_qos_struct.h @@ -144,12 +144,12 @@ typedef struct { volatile icm_axi_hw_cfg_reg_reg_t hw_cfg_reg; volatile icm_axi_cmd_reg_t cmd; volatile icm_axi_data_reg_t data; -} icm_axi_dev_t; +} axi_icm_qos_dev_t; -extern icm_axi_dev_t ICM_SYS; +extern axi_icm_qos_dev_t AXI_ICM_QOS; #ifndef __cplusplus -_Static_assert(sizeof(icm_axi_dev_t) == 0x10, "Invalid size of icm_axi_dev_t structure"); +_Static_assert(sizeof(axi_icm_qos_dev_t) == 0x10, "Invalid size of axi_icm_qos_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_struct.h index 92fe8de9fd6a..097455faa84a 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/icm_sys_struct.h @@ -508,12 +508,12 @@ typedef struct { volatile icm_rdn_eco_cs_reg_t rdn_eco_cs; volatile icm_rdn_eco_low_reg_t rdn_eco_low; volatile icm_rdn_eco_high_reg_t rdn_eco_high; -} icm_dev_t; +} axi_icm_dev_t; -extern icm_dev_t ICM_SYS; +extern axi_icm_dev_t AXI_ICM; #ifndef __cplusplus -_Static_assert(sizeof(icm_dev_t) == 0x5c, "Invalid size of icm_dev_t structure"); +_Static_assert(sizeof(axi_icm_dev_t) == 0x5c, "Invalid size of axi_icm_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/jpeg_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/jpeg_eco5_struct.h deleted file mode 100644 index c2c73c5bb57d..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/jpeg_eco5_struct.h +++ /dev/null @@ -1,1483 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Control and configuration registers */ -/** Type of config register - * Control and configuration registers - */ -typedef union { - struct { - /** fsm_rst : WT; bitpos: [0]; default: 0; - * fsm reset - */ - uint32_t fsm_rst:1; - /** jpeg_start : WT; bitpos: [1]; default: 0; - * start to compress a new pic(in dma reg mode) - */ - uint32_t jpeg_start:1; - /** qnr_precision : R/W; bitpos: [2]; default: 0; - * 0:8bit qnr,1:12bit qnr(TBD) - */ - uint32_t qnr_precision:1; - /** ff_check_en : R/W; bitpos: [3]; default: 1; - * enable whether to add '00' after 'ff' - */ - uint32_t ff_check_en:1; - /** sample_sel : R/W; bitpos: [5:4]; default: 1; - * 0:yuv444,1:yuv422, 2:yuv420 - */ - uint32_t sample_sel:2; - /** dma_linklist_mode : RO; bitpos: [6]; default: 1; - * 1:use linklist to configure dma - */ - uint32_t dma_linklist_mode:1; - /** debug_direct_out_en : R/W; bitpos: [7]; default: 0; - * 0:normal mode,1:debug mode for direct output from input - */ - uint32_t debug_direct_out_en:1; - /** qnr_fifo_en : R/W; bitpos: [8]; default: 1; - * 0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram - */ - uint32_t qnr_fifo_en:1; - /** lqnr_tbl_sel : R/W; bitpos: [10:9]; default: 0; - * choose luminance quntization table id(TBD) - */ - uint32_t lqnr_tbl_sel:2; - /** cqnr_tbl_sel : R/W; bitpos: [12:11]; default: 1; - * choose chrominance quntization table id (TBD) - */ - uint32_t cqnr_tbl_sel:2; - /** color_space : R/W; bitpos: [14:13]; default: 0; - * configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray - */ - uint32_t color_space:2; - /** dht_fifo_en : R/W; bitpos: [15]; default: 1; - * 0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to - * write dht len_total/codemin/value table. Reading dht len_total/codemin/value table - * only has nonfifo way - */ - uint32_t dht_fifo_en:1; - /** mem_clk_force_on : R/W; bitpos: [16]; default: 0; - * force memory's clock enabled - */ - uint32_t mem_clk_force_on:1; - /** decode_timeout_thres : R/W; bitpos: [22:17]; default: 32; - * decode pause period to trigger decode_timeout int, the timeout periods =2 power - * (reg_decode_timeout_thres) -1 - */ - uint32_t decode_timeout_thres:6; - /** decode_timeout_task_sel : R/W; bitpos: [23]; default: 0; - * 0: software use reset to abort decode process ,1: decoder abort decode process by - * itself - */ - uint32_t decode_timeout_task_sel:1; - /** soft_rst : R/W; bitpos: [24]; default: 0; - * when set to 1, soft reset JPEG module except jpeg_reg module - */ - uint32_t soft_rst:1; - /** fifo_rst : R/W; bitpos: [25]; default: 0; - * fifo reset - */ - uint32_t fifo_rst:1; - /** pixel_rev : R/W; bitpos: [26]; default: 0; - * reverse the source color pixel - */ - uint32_t pixel_rev:1; - /** tailer_en : R/W; bitpos: [27]; default: 0; - * set this bit to add EOI of '0xffd9' at the end of bitstream - */ - uint32_t tailer_en:1; - /** pause_en : R/W; bitpos: [28]; default: 0; - * set this bit to pause jpeg encoding - */ - uint32_t pause_en:1; - /** mem_force_pd : R/W; bitpos: [29]; default: 0; - * 0: no operation,1:force jpeg memory to power down - */ - uint32_t mem_force_pd:1; - /** mem_force_pu : R/W; bitpos: [30]; default: 0; - * 0: no operation,1:force jpeg memory to power up - */ - uint32_t mem_force_pu:1; - /** mode : R/W; bitpos: [31]; default: 0; - * 0:encoder mode, 1: decoder mode - */ - uint32_t mode:1; - }; - uint32_t val; -} jpeg_config_reg_t; - -/** Type of dqt_info register - * Control and configuration registers - */ -typedef union { - struct { - /** t0_dqt_info : R/W; bitpos: [7:0]; default: 0; - * Configure dqt table0's quantization coefficient precision in bit[7:4], configure - * dqt table0's table id in bit[3:0] - */ - uint32_t t0_dqt_info:8; - /** t1_dqt_info : R/W; bitpos: [15:8]; default: 1; - * Configure dqt table1's quantization coefficient precision in bit[7:4], configure - * dqt table1's table id in bit[3:0] - */ - uint32_t t1_dqt_info:8; - /** t2_dqt_info : R/W; bitpos: [23:16]; default: 2; - * Configure dqt table2's quantization coefficient precision in bit[7:4], configure - * dqt table2's table id in bit[3:0] - */ - uint32_t t2_dqt_info:8; - /** t3_dqt_info : R/W; bitpos: [31:24]; default: 3; - * Configure dqt table3's quantization coefficient precision in bit[7:4], configure - * dqt table3's table id in bit[3:0] - */ - uint32_t t3_dqt_info:8; - }; - uint32_t val; -} jpeg_dqt_info_reg_t; - -/** Type of pic_size register - * Control and configuration registers - */ -typedef union { - struct { - /** va : R/W; bitpos: [15:0]; default: 480; - * configure picture's height. when encode, the max configurable bits is 14, when - * decode, the max configurable bits is 16 - */ - uint32_t va:16; - /** ha : R/W; bitpos: [31:16]; default: 640; - * configure picture's width. when encode, the max configurable bits is 14, when - * decode, the max configurable bits is 16 - */ - uint32_t ha:16; - }; - uint32_t val; -} jpeg_pic_size_reg_t; - -/** Type of extd_config register - * Control and configuration registers - */ -typedef union { - struct { - /** extd_color_space_en : R/W; bitpos: [0]; default: 0; - * Configure whether to extend picture's color space - * 0:disable - * 1:enable - */ - uint32_t extd_color_space_en:1; - /** extd_color_space : R/W; bitpos: [1]; default: 0; - * Configure extended picture's color space. Valid when JPEG_EXTD_COLOR_SPACE_EN - * configured to 1 - * 0:yuv444 - * 1:yuv420 - */ - uint32_t extd_color_space:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} jpeg_extd_config_reg_t; - -/** Type of t0qnr register - * Control and configuration registers - */ -typedef union { - struct { - /** t0_qnr_val : HRO; bitpos: [31:0]; default: 0; - * write this reg to configure 64 quantization coefficient in t0 table - */ - uint32_t t0_qnr_val:32; - }; - uint32_t val; -} jpeg_t0qnr_reg_t; - -/** Type of t1qnr register - * Control and configuration registers - */ -typedef union { - struct { - /** t1_qnr_val : HRO; bitpos: [31:0]; default: 0; - * write this reg to configure 64 quantization coefficient in t1 table - */ - uint32_t t1_qnr_val:32; - }; - uint32_t val; -} jpeg_t1qnr_reg_t; - -/** Type of t2qnr register - * Control and configuration registers - */ -typedef union { - struct { - /** t2_qnr_val : HRO; bitpos: [31:0]; default: 0; - * write this reg to configure 64 quantization coefficient in t2 table - */ - uint32_t t2_qnr_val:32; - }; - uint32_t val; -} jpeg_t2qnr_reg_t; - -/** Type of t3qnr register - * Control and configuration registers - */ -typedef union { - struct { - /** t3_qnr_val : HRO; bitpos: [31:0]; default: 0; - * write this reg to configure 64 quantization coefficient in t3 table - */ - uint32_t t3_qnr_val:32; - }; - uint32_t val; -} jpeg_t3qnr_reg_t; - -/** Type of decode_conf register - * Control and configuration registers - */ -typedef union { - struct { - /** restart_interval : R/W; bitpos: [15:0]; default: 0; - * configure restart interval in DRI marker when decode - */ - uint32_t restart_interval:16; - /** component_num : R/W; bitpos: [23:16]; default: 3; - * configure number of components in frame when decode - */ - uint32_t component_num:8; - /** sw_dht_en : RO; bitpos: [24]; default: 1; - * software decode dht table enable - */ - uint32_t sw_dht_en:1; - /** sos_check_byte_num : R/W; bitpos: [26:25]; default: 3; - * Configure the byte number to check next sos marker in the multi-scan picture after - * one scan is decoded down. The real check number is reg_sos_check_byte_num+1 - */ - uint32_t sos_check_byte_num:2; - /** rst_check_byte_num : R/W; bitpos: [28:27]; default: 3; - * Configure the byte number to check next rst marker after one rst interval is - * decoded down. The real check number is reg_rst_check_byte_num+1 - */ - uint32_t rst_check_byte_num:2; - /** multi_scan_err_check : R/W; bitpos: [29]; default: 0; - * reserved for decoder - */ - uint32_t multi_scan_err_check:1; - /** dezigzag_ready_ctl : R/W; bitpos: [30]; default: 1; - * reserved for decoder - */ - uint32_t dezigzag_ready_ctl:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} jpeg_decode_conf_reg_t; - -/** Type of c0 register - * Control and configuration registers - */ -typedef union { - struct { - /** c0_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0; - * choose c0 quntization table id (TBD) - */ - uint32_t c0_dqt_tbl_sel:8; - /** c0_y_factor : R/W; bitpos: [11:8]; default: 1; - * vertical sampling factor of c0 - */ - uint32_t c0_y_factor:4; - /** c0_x_factor : R/W; bitpos: [15:12]; default: 1; - * horizontal sampling factor of c0 - */ - uint32_t c0_x_factor:4; - /** c0_id : R/W; bitpos: [23:16]; default: 0; - * the identifier of c0 - */ - uint32_t c0_id:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} jpeg_c0_reg_t; - -/** Type of c1 register - * Control and configuration registers - */ -typedef union { - struct { - /** c1_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0; - * choose c1 quntization table id (TBD) - */ - uint32_t c1_dqt_tbl_sel:8; - /** c1_y_factor : R/W; bitpos: [11:8]; default: 1; - * vertical sampling factor of c1 - */ - uint32_t c1_y_factor:4; - /** c1_x_factor : R/W; bitpos: [15:12]; default: 1; - * horizontal sampling factor of c1 - */ - uint32_t c1_x_factor:4; - /** c1_id : R/W; bitpos: [23:16]; default: 0; - * the identifier of c1 - */ - uint32_t c1_id:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} jpeg_c1_reg_t; - -/** Type of c2 register - * Control and configuration registers - */ -typedef union { - struct { - /** c2_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0; - * choose c2 quntization table id (TBD) - */ - uint32_t c2_dqt_tbl_sel:8; - /** c2_y_factor : R/W; bitpos: [11:8]; default: 1; - * vertical sampling factor of c2 - */ - uint32_t c2_y_factor:4; - /** c2_x_factor : R/W; bitpos: [15:12]; default: 1; - * horizontal sampling factor of c2 - */ - uint32_t c2_x_factor:4; - /** c2_id : R/W; bitpos: [23:16]; default: 0; - * the identifier of c2 - */ - uint32_t c2_id:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} jpeg_c2_reg_t; - -/** Type of c3 register - * Control and configuration registers - */ -typedef union { - struct { - /** c3_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0; - * choose c3 quntization table id (TBD) - */ - uint32_t c3_dqt_tbl_sel:8; - /** c3_y_factor : R/W; bitpos: [11:8]; default: 1; - * vertical sampling factor of c3 - */ - uint32_t c3_y_factor:4; - /** c3_x_factor : R/W; bitpos: [15:12]; default: 1; - * horizontal sampling factor of c3 - */ - uint32_t c3_x_factor:4; - /** c3_id : R/W; bitpos: [23:16]; default: 0; - * the identifier of c3 - */ - uint32_t c3_id:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} jpeg_c3_reg_t; - -/** Type of dht_info register - * Control and configuration registers - */ -typedef union { - struct { - /** dc0_dht_id : R/W; bitpos: [3:0]; default: 0; - * configure dht dc table 0 id - */ - uint32_t dc0_dht_id:4; - /** dc1_dht_id : R/W; bitpos: [7:4]; default: 1; - * configure dht dc table 1 id - */ - uint32_t dc1_dht_id:4; - /** ac0_dht_id : R/W; bitpos: [11:8]; default: 0; - * configure dht ac table 0 id - */ - uint32_t ac0_dht_id:4; - /** ac1_dht_id : R/W; bitpos: [15:12]; default: 1; - * configure dht ac table 1 id - */ - uint32_t ac1_dht_id:4; - uint32_t reserved_16:16; - }; - uint32_t val; -} jpeg_dht_info_reg_t; - - -/** Group: Interrupt registers */ -/** Type of int_raw register - * Interrupt raw registers - */ -typedef union { - struct { - /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * This raw interrupt bit turns to high level when JPEG finishes encoding a picture.. - */ - uint32_t done_int_raw:1; - /** rle_parallel_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit to sign that rle parallel error when decoding. - */ - uint32_t rle_parallel_err_int_raw:1; - /** cid_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit to sign that scan id check with component fails when decoding. - */ - uint32_t cid_err_int_raw:1; - /** c_dht_dc_id_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit to sign that scan component's dc dht id check with dc dht - * table's id fails when decoding. - */ - uint32_t c_dht_dc_id_err_int_raw:1; - /** c_dht_ac_id_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit to sign that scan component's ac dht id check with ac dht - * table's id fails when decoding. - */ - uint32_t c_dht_ac_id_err_int_raw:1; - /** c_dqt_id_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit to sign that scan component's dqt id check with dqt table's - * id fails when decoding. - */ - uint32_t c_dqt_id_err_int_raw:1; - /** rst_uxp_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit to sign that RST header marker is detected but restart - * interval is 0 when decoding. - */ - uint32_t rst_uxp_err_int_raw:1; - /** rst_check_none_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit to sign that RST header marker is not detected but restart - * interval is not 0 when decoding. - */ - uint32_t rst_check_none_err_int_raw:1; - /** rst_check_pos_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit to sign that RST header marker position mismatches with - * restart interval when decoding. - */ - uint32_t rst_check_pos_err_int_raw:1; - /** out_eof_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when the last pixel of one square has - * been transmitted for Tx channel. - */ - uint32_t out_eof_int_raw:1; - /** sr_color_mode_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit to sign that the selected source color mode is not supported. - */ - uint32_t sr_color_mode_err_int_raw:1; - /** dct_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit to sign that one dct calculation is finished. - */ - uint32_t dct_done_int_raw:1; - /** bs_last_block_eof_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit to sign that the coding process for last block is finished. - */ - uint32_t bs_last_block_eof_int_raw:1; - /** scan_check_none_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * The raw interrupt bit to sign that SOS header marker is not detected but there are - * still components left to be decoded. - */ - uint32_t scan_check_none_err_int_raw:1; - /** scan_check_pos_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * The raw interrupt bit to sign that SOS header marker position wrong when decoding. - */ - uint32_t scan_check_pos_err_int_raw:1; - /** uxp_det_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * The raw interrupt bit to sign that unsupported header marker is detected when - * decoding. - */ - uint32_t uxp_det_int_raw:1; - /** en_frame_eof_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * The raw interrupt bit to sign that received pixel blocks are smaller than expected - * when encoding. - */ - uint32_t en_frame_eof_err_int_raw:1; - /** en_frame_eof_lack_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * The raw interrupt bit to sign that the frame eof sign bit from dma input is missing - * when encoding. But the number of pixel blocks is enough. - */ - uint32_t en_frame_eof_lack_int_raw:1; - /** de_frame_eof_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * The raw interrupt bit to sign that decoded blocks are smaller than expected when - * decoding. - */ - uint32_t de_frame_eof_err_int_raw:1; - /** de_frame_eof_lack_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * The raw interrupt bit to sign that the either frame eof from dma input or eoi - * marker is missing when encoding. But the number of decoded blocks is enough. - */ - uint32_t de_frame_eof_lack_int_raw:1; - /** sos_unmatch_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * The raw interrupt bit to sign that the component number of a scan is 0 or does not - * match the sos marker's length when decoding. - */ - uint32_t sos_unmatch_err_int_raw:1; - /** marker_err_fst_scan_int_raw : R/WTC/SS; bitpos: [21]; default: 0; - * The raw interrupt bit to sign that the first scan has header marker error when - * decoding. - */ - uint32_t marker_err_fst_scan_int_raw:1; - /** marker_err_other_scan_int_raw : R/WTC/SS; bitpos: [22]; default: 0; - * The raw interrupt bit to sign that the following scans but not the first scan have - * header marker error when decoding. - */ - uint32_t marker_err_other_scan_int_raw:1; - /** undet_int_raw : R/WTC/SS; bitpos: [23]; default: 0; - * The raw interrupt bit to sign that JPEG format is not detected at the eof data of a - * packet when decoding. - */ - uint32_t undet_int_raw:1; - /** decode_timeout_int_raw : R/WTC/SS; bitpos: [24]; default: 0; - * The raw interrupt bit to sign that decode pause time is longer than the setting - * decode timeout time when decoding. - */ - uint32_t decode_timeout_int_raw:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} jpeg_int_raw_reg_t; - -/** Type of int_ena register - * Interrupt enable registers - */ -typedef union { - struct { - /** done_int_ena : R/W; bitpos: [0]; default: 0; - * This enable interrupt bit turns to high level when JPEG finishes encoding a - * picture.. - */ - uint32_t done_int_ena:1; - /** rle_parallel_err_int_ena : R/W; bitpos: [1]; default: 0; - * The enable interrupt bit to sign that rle parallel error when decoding. - */ - uint32_t rle_parallel_err_int_ena:1; - /** cid_err_int_ena : R/W; bitpos: [2]; default: 0; - * The enable interrupt bit to sign that scan id check with component fails when - * decoding. - */ - uint32_t cid_err_int_ena:1; - /** c_dht_dc_id_err_int_ena : R/W; bitpos: [3]; default: 0; - * The enable interrupt bit to sign that scan component's dc dht id check with dc dht - * table's id fails when decoding. - */ - uint32_t c_dht_dc_id_err_int_ena:1; - /** c_dht_ac_id_err_int_ena : R/W; bitpos: [4]; default: 0; - * The enable interrupt bit to sign that scan component's ac dht id check with ac dht - * table's id fails when decoding. - */ - uint32_t c_dht_ac_id_err_int_ena:1; - /** c_dqt_id_err_int_ena : R/W; bitpos: [5]; default: 0; - * The enable interrupt bit to sign that scan component's dqt id check with dqt - * table's id fails when decoding. - */ - uint32_t c_dqt_id_err_int_ena:1; - /** rst_uxp_err_int_ena : R/W; bitpos: [6]; default: 0; - * The enable interrupt bit to sign that RST header marker is detected but restart - * interval is 0 when decoding. - */ - uint32_t rst_uxp_err_int_ena:1; - /** rst_check_none_err_int_ena : R/W; bitpos: [7]; default: 0; - * The enable interrupt bit to sign that RST header marker is not detected but restart - * interval is not 0 when decoding. - */ - uint32_t rst_check_none_err_int_ena:1; - /** rst_check_pos_err_int_ena : R/W; bitpos: [8]; default: 0; - * The enable interrupt bit to sign that RST header marker position mismatches with - * restart interval when decoding. - */ - uint32_t rst_check_pos_err_int_ena:1; - /** out_eof_int_ena : R/W; bitpos: [9]; default: 0; - * The enable interrupt bit turns to high level when the last pixel of one square has - * been transmitted for Tx channel. - */ - uint32_t out_eof_int_ena:1; - /** sr_color_mode_err_int_ena : R/W; bitpos: [10]; default: 0; - * The enable interrupt bit to sign that the selected source color mode is not - * supported. - */ - uint32_t sr_color_mode_err_int_ena:1; - /** dct_done_int_ena : R/W; bitpos: [11]; default: 0; - * The enable interrupt bit to sign that one dct calculation is finished. - */ - uint32_t dct_done_int_ena:1; - /** bs_last_block_eof_int_ena : R/W; bitpos: [12]; default: 0; - * The enable interrupt bit to sign that the coding process for last block is finished. - */ - uint32_t bs_last_block_eof_int_ena:1; - /** scan_check_none_err_int_ena : R/W; bitpos: [13]; default: 0; - * The enable interrupt bit to sign that SOS header marker is not detected but there - * are still components left to be decoded. - */ - uint32_t scan_check_none_err_int_ena:1; - /** scan_check_pos_err_int_ena : R/W; bitpos: [14]; default: 0; - * The enable interrupt bit to sign that SOS header marker position wrong when - * decoding. - */ - uint32_t scan_check_pos_err_int_ena:1; - /** uxp_det_int_ena : R/W; bitpos: [15]; default: 0; - * The enable interrupt bit to sign that unsupported header marker is detected when - * decoding. - */ - uint32_t uxp_det_int_ena:1; - /** en_frame_eof_err_int_ena : R/W; bitpos: [16]; default: 0; - * The enable interrupt bit to sign that received pixel blocks are smaller than - * expected when encoding. - */ - uint32_t en_frame_eof_err_int_ena:1; - /** en_frame_eof_lack_int_ena : R/W; bitpos: [17]; default: 0; - * The enable interrupt bit to sign that the frame eof sign bit from dma input is - * missing when encoding. But the number of pixel blocks is enough. - */ - uint32_t en_frame_eof_lack_int_ena:1; - /** de_frame_eof_err_int_ena : R/W; bitpos: [18]; default: 0; - * The enable interrupt bit to sign that decoded blocks are smaller than expected when - * decoding. - */ - uint32_t de_frame_eof_err_int_ena:1; - /** de_frame_eof_lack_int_ena : R/W; bitpos: [19]; default: 0; - * The enable interrupt bit to sign that the either frame eof from dma input or eoi - * marker is missing when encoding. But the number of decoded blocks is enough. - */ - uint32_t de_frame_eof_lack_int_ena:1; - /** sos_unmatch_err_int_ena : R/W; bitpos: [20]; default: 0; - * The enable interrupt bit to sign that the component number of a scan is 0 or does - * not match the sos marker's length when decoding. - */ - uint32_t sos_unmatch_err_int_ena:1; - /** marker_err_fst_scan_int_ena : R/W; bitpos: [21]; default: 0; - * The enable interrupt bit to sign that the first scan has header marker error when - * decoding. - */ - uint32_t marker_err_fst_scan_int_ena:1; - /** marker_err_other_scan_int_ena : R/W; bitpos: [22]; default: 0; - * The enable interrupt bit to sign that the following scans but not the first scan - * have header marker error when decoding. - */ - uint32_t marker_err_other_scan_int_ena:1; - /** undet_int_ena : R/W; bitpos: [23]; default: 0; - * The enable interrupt bit to sign that JPEG format is not detected at the eof data - * of a packet when decoding. - */ - uint32_t undet_int_ena:1; - /** decode_timeout_int_ena : R/W; bitpos: [24]; default: 0; - * The enable interrupt bit to sign that decode pause time is longer than the setting - * decode timeout time when decoding. - */ - uint32_t decode_timeout_int_ena:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} jpeg_int_ena_reg_t; - -/** Type of int_st register - * Interrupt status registers - */ -typedef union { - struct { - /** done_int_st : RO; bitpos: [0]; default: 0; - * This status interrupt bit turns to high level when JPEG finishes encoding a - * picture.. - */ - uint32_t done_int_st:1; - /** rle_parallel_err_int_st : RO; bitpos: [1]; default: 0; - * The status interrupt bit to sign that rle parallel error when decoding. - */ - uint32_t rle_parallel_err_int_st:1; - /** cid_err_int_st : RO; bitpos: [2]; default: 0; - * The status interrupt bit to sign that scan id check with component fails when - * decoding. - */ - uint32_t cid_err_int_st:1; - /** c_dht_dc_id_err_int_st : RO; bitpos: [3]; default: 0; - * The status interrupt bit to sign that scan component's dc dht id check with dc dht - * table's id fails when decoding. - */ - uint32_t c_dht_dc_id_err_int_st:1; - /** c_dht_ac_id_err_int_st : RO; bitpos: [4]; default: 0; - * The status interrupt bit to sign that scan component's ac dht id check with ac dht - * table's id fails when decoding. - */ - uint32_t c_dht_ac_id_err_int_st:1; - /** c_dqt_id_err_int_st : RO; bitpos: [5]; default: 0; - * The status interrupt bit to sign that scan component's dqt id check with dqt - * table's id fails when decoding. - */ - uint32_t c_dqt_id_err_int_st:1; - /** rst_uxp_err_int_st : RO; bitpos: [6]; default: 0; - * The status interrupt bit to sign that RST header marker is detected but restart - * interval is 0 when decoding. - */ - uint32_t rst_uxp_err_int_st:1; - /** rst_check_none_err_int_st : RO; bitpos: [7]; default: 0; - * The status interrupt bit to sign that RST header marker is not detected but restart - * interval is not 0 when decoding. - */ - uint32_t rst_check_none_err_int_st:1; - /** rst_check_pos_err_int_st : RO; bitpos: [8]; default: 0; - * The status interrupt bit to sign that RST header marker position mismatches with - * restart interval when decoding. - */ - uint32_t rst_check_pos_err_int_st:1; - /** out_eof_int_st : RO; bitpos: [9]; default: 0; - * The status interrupt bit turns to high level when the last pixel of one square has - * been transmitted for Tx channel. - */ - uint32_t out_eof_int_st:1; - /** sr_color_mode_err_int_st : RO; bitpos: [10]; default: 0; - * The status interrupt bit to sign that the selected source color mode is not - * supported. - */ - uint32_t sr_color_mode_err_int_st:1; - /** dct_done_int_st : RO; bitpos: [11]; default: 0; - * The status interrupt bit to sign that one dct calculation is finished. - */ - uint32_t dct_done_int_st:1; - /** bs_last_block_eof_int_st : RO; bitpos: [12]; default: 0; - * The status interrupt bit to sign that the coding process for last block is finished. - */ - uint32_t bs_last_block_eof_int_st:1; - /** scan_check_none_err_int_st : RO; bitpos: [13]; default: 0; - * The status interrupt bit to sign that SOS header marker is not detected but there - * are still components left to be decoded. - */ - uint32_t scan_check_none_err_int_st:1; - /** scan_check_pos_err_int_st : RO; bitpos: [14]; default: 0; - * The status interrupt bit to sign that SOS header marker position wrong when - * decoding. - */ - uint32_t scan_check_pos_err_int_st:1; - /** uxp_det_int_st : RO; bitpos: [15]; default: 0; - * The status interrupt bit to sign that unsupported header marker is detected when - * decoding. - */ - uint32_t uxp_det_int_st:1; - /** en_frame_eof_err_int_st : RO; bitpos: [16]; default: 0; - * The status interrupt bit to sign that received pixel blocks are smaller than - * expected when encoding. - */ - uint32_t en_frame_eof_err_int_st:1; - /** en_frame_eof_lack_int_st : RO; bitpos: [17]; default: 0; - * The status interrupt bit to sign that the frame eof sign bit from dma input is - * missing when encoding. But the number of pixel blocks is enough. - */ - uint32_t en_frame_eof_lack_int_st:1; - /** de_frame_eof_err_int_st : RO; bitpos: [18]; default: 0; - * The status interrupt bit to sign that decoded blocks are smaller than expected when - * decoding. - */ - uint32_t de_frame_eof_err_int_st:1; - /** de_frame_eof_lack_int_st : RO; bitpos: [19]; default: 0; - * The status interrupt bit to sign that the either frame eof from dma input or eoi - * marker is missing when encoding. But the number of decoded blocks is enough. - */ - uint32_t de_frame_eof_lack_int_st:1; - /** sos_unmatch_err_int_st : RO; bitpos: [20]; default: 0; - * The status interrupt bit to sign that the component number of a scan is 0 or does - * not match the sos marker's length when decoding. - */ - uint32_t sos_unmatch_err_int_st:1; - /** marker_err_fst_scan_int_st : RO; bitpos: [21]; default: 0; - * The status interrupt bit to sign that the first scan has header marker error when - * decoding. - */ - uint32_t marker_err_fst_scan_int_st:1; - /** marker_err_other_scan_int_st : RO; bitpos: [22]; default: 0; - * The status interrupt bit to sign that the following scans but not the first scan - * have header marker error when decoding. - */ - uint32_t marker_err_other_scan_int_st:1; - /** undet_int_st : RO; bitpos: [23]; default: 0; - * The status interrupt bit to sign that JPEG format is not detected at the eof data - * of a packet when decoding. - */ - uint32_t undet_int_st:1; - /** decode_timeout_int_st : RO; bitpos: [24]; default: 0; - * The status interrupt bit to sign that decode pause time is longer than the setting - * decode timeout time when decoding. - */ - uint32_t decode_timeout_int_st:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} jpeg_int_st_reg_t; - -/** Type of int_clr register - * Interrupt clear registers - */ -typedef union { - struct { - /** done_int_clr : WT; bitpos: [0]; default: 0; - * This clear interrupt bit turns to high level when JPEG finishes encoding a picture.. - */ - uint32_t done_int_clr:1; - /** rle_parallel_err_int_clr : WT; bitpos: [1]; default: 0; - * The clear interrupt bit to sign that rle parallel error when decoding. - */ - uint32_t rle_parallel_err_int_clr:1; - /** cid_err_int_clr : WT; bitpos: [2]; default: 0; - * The clear interrupt bit to sign that scan id check with component fails when - * decoding. - */ - uint32_t cid_err_int_clr:1; - /** c_dht_dc_id_err_int_clr : WT; bitpos: [3]; default: 0; - * The clear interrupt bit to sign that scan component's dc dht id check with dc dht - * table's id fails when decoding. - */ - uint32_t c_dht_dc_id_err_int_clr:1; - /** c_dht_ac_id_err_int_clr : WT; bitpos: [4]; default: 0; - * The clear interrupt bit to sign that scan component's ac dht id check with ac dht - * table's id fails when decoding. - */ - uint32_t c_dht_ac_id_err_int_clr:1; - /** c_dqt_id_err_int_clr : WT; bitpos: [5]; default: 0; - * The clear interrupt bit to sign that scan component's dqt id check with dqt table's - * id fails when decoding. - */ - uint32_t c_dqt_id_err_int_clr:1; - /** rst_uxp_err_int_clr : WT; bitpos: [6]; default: 0; - * The clear interrupt bit to sign that RST header marker is detected but restart - * interval is 0 when decoding. - */ - uint32_t rst_uxp_err_int_clr:1; - /** rst_check_none_err_int_clr : WT; bitpos: [7]; default: 0; - * The clear interrupt bit to sign that RST header marker is not detected but restart - * interval is not 0 when decoding. - */ - uint32_t rst_check_none_err_int_clr:1; - /** rst_check_pos_err_int_clr : WT; bitpos: [8]; default: 0; - * The clear interrupt bit to sign that RST header marker position mismatches with - * restart interval when decoding. - */ - uint32_t rst_check_pos_err_int_clr:1; - /** out_eof_int_clr : WT; bitpos: [9]; default: 0; - * The clear interrupt bit turns to high level when the last pixel of one square has - * been transmitted for Tx channel. - */ - uint32_t out_eof_int_clr:1; - /** sr_color_mode_err_int_clr : WT; bitpos: [10]; default: 0; - * The clear interrupt bit to sign that the selected source color mode is not - * supported. - */ - uint32_t sr_color_mode_err_int_clr:1; - /** dct_done_int_clr : WT; bitpos: [11]; default: 0; - * The clear interrupt bit to sign that one dct calculation is finished. - */ - uint32_t dct_done_int_clr:1; - /** bs_last_block_eof_int_clr : WT; bitpos: [12]; default: 0; - * The clear interrupt bit to sign that the coding process for last block is finished. - */ - uint32_t bs_last_block_eof_int_clr:1; - /** scan_check_none_err_int_clr : WT; bitpos: [13]; default: 0; - * The clear interrupt bit to sign that SOS header marker is not detected but there - * are still components left to be decoded. - */ - uint32_t scan_check_none_err_int_clr:1; - /** scan_check_pos_err_int_clr : WT; bitpos: [14]; default: 0; - * The clear interrupt bit to sign that SOS header marker position wrong when decoding. - */ - uint32_t scan_check_pos_err_int_clr:1; - /** uxp_det_int_clr : WT; bitpos: [15]; default: 0; - * The clear interrupt bit to sign that unsupported header marker is detected when - * decoding. - */ - uint32_t uxp_det_int_clr:1; - /** en_frame_eof_err_int_clr : WT; bitpos: [16]; default: 0; - * The clear interrupt bit to sign that received pixel blocks are smaller than - * expected when encoding. - */ - uint32_t en_frame_eof_err_int_clr:1; - /** en_frame_eof_lack_int_clr : WT; bitpos: [17]; default: 0; - * The clear interrupt bit to sign that the frame eof sign bit from dma input is - * missing when encoding. But the number of pixel blocks is enough. - */ - uint32_t en_frame_eof_lack_int_clr:1; - /** de_frame_eof_err_int_clr : WT; bitpos: [18]; default: 0; - * The clear interrupt bit to sign that decoded blocks are smaller than expected when - * decoding. - */ - uint32_t de_frame_eof_err_int_clr:1; - /** de_frame_eof_lack_int_clr : WT; bitpos: [19]; default: 0; - * The clear interrupt bit to sign that the either frame eof from dma input or eoi - * marker is missing when encoding. But the number of decoded blocks is enough. - */ - uint32_t de_frame_eof_lack_int_clr:1; - /** sos_unmatch_err_int_clr : WT; bitpos: [20]; default: 0; - * The clear interrupt bit to sign that the component number of a scan is 0 or does - * not match the sos marker's length when decoding. - */ - uint32_t sos_unmatch_err_int_clr:1; - /** marker_err_fst_scan_int_clr : WT; bitpos: [21]; default: 0; - * The clear interrupt bit to sign that the first scan has header marker error when - * decoding. - */ - uint32_t marker_err_fst_scan_int_clr:1; - /** marker_err_other_scan_int_clr : WT; bitpos: [22]; default: 0; - * The clear interrupt bit to sign that the following scans but not the first scan - * have header marker error when decoding. - */ - uint32_t marker_err_other_scan_int_clr:1; - /** undet_int_clr : WT; bitpos: [23]; default: 0; - * The clear interrupt bit to sign that JPEG format is not detected at the eof data of - * a packet when decoding. - */ - uint32_t undet_int_clr:1; - /** decode_timeout_int_clr : WT; bitpos: [24]; default: 0; - * The clear interrupt bit to sign that decode pause time is longer than the setting - * decode timeout time when decoding. - */ - uint32_t decode_timeout_int_clr:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} jpeg_int_clr_reg_t; - - -/** Group: Trace and Debug registers */ -/** Type of status0 register - * Trace and Debug registers - */ -typedef union { - struct { - uint32_t reserved_0:11; - /** bitstream_eof_vld_cnt : RO; bitpos: [16:11]; default: 0; - * the valid bit count for last bitstream - */ - uint32_t bitstream_eof_vld_cnt:6; - /** dctout_zzscan_addr : RO; bitpos: [22:17]; default: 0; - * the zig-zag read addr from dctout_ram - */ - uint32_t dctout_zzscan_addr:6; - /** qnrval_zzscan_addr : RO; bitpos: [28:23]; default: 0; - * the zig-zag read addr from qnrval_ram - */ - uint32_t qnrval_zzscan_addr:6; - /** reg_state_yuv : RO; bitpos: [31:29]; default: 0; - * the state of jpeg fsm - */ - uint32_t reg_state_yuv:3; - }; - uint32_t val; -} jpeg_status0_reg_t; - -/** Type of status2 register - * Trace and Debug registers - */ -typedef union { - struct { - /** source_pixel : RO; bitpos: [23:0]; default: 0; - * source pixels fetched from dma - */ - uint32_t source_pixel:24; - /** last_block : RO; bitpos: [24]; default: 0; - * indicate the encoding process for the last mcu of the picture - */ - uint32_t last_block:1; - /** last_mcu : RO; bitpos: [25]; default: 0; - * indicate the encoding process for the last block of the picture - */ - uint32_t last_mcu:1; - /** last_dc : RO; bitpos: [26]; default: 0; - * indicate the encoding process is at the header of the last block of the picture - */ - uint32_t last_dc:1; - /** packfifo_ready : RO; bitpos: [27]; default: 1; - * the jpeg pack_fifo ready signal, high active - */ - uint32_t packfifo_ready:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} jpeg_status2_reg_t; - -/** Type of status3 register - * Trace and Debug registers - */ -typedef union { - struct { - /** yo : RO; bitpos: [8:0]; default: 0; - * component y transferred from rgb input - */ - uint32_t yo:9; - /** y_ready : RO; bitpos: [9]; default: 0; - * component y valid signal, high active - */ - uint32_t y_ready:1; - /** cbo : RO; bitpos: [18:10]; default: 0; - * component cb transferred from rgb input - */ - uint32_t cbo:9; - /** cb_ready : RO; bitpos: [19]; default: 0; - * component cb valid signal, high active - */ - uint32_t cb_ready:1; - /** cro : RO; bitpos: [28:20]; default: 0; - * component cr transferred from rgb input - */ - uint32_t cro:9; - /** cr_ready : RO; bitpos: [29]; default: 0; - * component cr valid signal, high active - */ - uint32_t cr_ready:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} jpeg_status3_reg_t; - -/** Type of status4 register - * Trace and Debug registers - */ -typedef union { - struct { - /** hfm_bitstream : RO; bitpos: [31:0]; default: 0; - * the hufman bitstream during encoding process - */ - uint32_t hfm_bitstream:32; - }; - uint32_t val; -} jpeg_status4_reg_t; - -/** Type of dht_totlen_dc0 register - * Trace and Debug registers - */ -typedef union { - struct { - /** dht_totlen_dc0 : HRO; bitpos: [31:0]; default: 0; - * write the numbers of 1~n codeword length sum from 1~16 of dc0 table - */ - uint32_t dht_totlen_dc0:32; - }; - uint32_t val; -} jpeg_dht_totlen_dc0_reg_t; - -/** Type of dht_val_dc0 register - * Trace and Debug registers - */ -typedef union { - struct { - /** dht_val_dc0 : HRO; bitpos: [31:0]; default: 0; - * write codeword corresponding huffman values of dc0 table - */ - uint32_t dht_val_dc0:32; - }; - uint32_t val; -} jpeg_dht_val_dc0_reg_t; - -/** Type of dht_totlen_ac0 register - * Trace and Debug registers - */ -typedef union { - struct { - /** dht_totlen_ac0 : HRO; bitpos: [31:0]; default: 0; - * write the numbers of 1~n codeword length sum from 1~16 of ac0 table - */ - uint32_t dht_totlen_ac0:32; - }; - uint32_t val; -} jpeg_dht_totlen_ac0_reg_t; - -/** Type of dht_val_ac0 register - * Trace and Debug registers - */ -typedef union { - struct { - /** dht_val_ac0 : HRO; bitpos: [31:0]; default: 0; - * write codeword corresponding huffman values of ac0 table - */ - uint32_t dht_val_ac0:32; - }; - uint32_t val; -} jpeg_dht_val_ac0_reg_t; - -/** Type of dht_totlen_dc1 register - * Trace and Debug registers - */ -typedef union { - struct { - /** dht_totlen_dc1 : HRO; bitpos: [31:0]; default: 0; - * write the numbers of 1~n codeword length sum from 1~16 of dc1 table - */ - uint32_t dht_totlen_dc1:32; - }; - uint32_t val; -} jpeg_dht_totlen_dc1_reg_t; - -/** Type of dht_val_dc1 register - * Trace and Debug registers - */ -typedef union { - struct { - /** dht_val_dc1 : HRO; bitpos: [31:0]; default: 0; - * write codeword corresponding huffman values of dc1 table - */ - uint32_t dht_val_dc1:32; - }; - uint32_t val; -} jpeg_dht_val_dc1_reg_t; - -/** Type of dht_totlen_ac1 register - * Trace and Debug registers - */ -typedef union { - struct { - /** dht_totlen_ac1 : HRO; bitpos: [31:0]; default: 0; - * write the numbers of 1~n codeword length sum from 1~16 of ac1 table - */ - uint32_t dht_totlen_ac1:32; - }; - uint32_t val; -} jpeg_dht_totlen_ac1_reg_t; - -/** Type of dht_val_ac1 register - * Trace and Debug registers - */ -typedef union { - struct { - /** dht_val_ac1 : HRO; bitpos: [31:0]; default: 0; - * write codeword corresponding huffman values of ac1 table - */ - uint32_t dht_val_ac1:32; - }; - uint32_t val; -} jpeg_dht_val_ac1_reg_t; - -/** Type of dht_codemin_dc0 register - * Trace and Debug registers - */ -typedef union { - struct { - /** dht_codemin_dc0 : HRO; bitpos: [31:0]; default: 0; - * write the minimum codeword of code length from 1~16 of dc0 table. The codeword is - * left shifted to the MSB position of a 16bit word - */ - uint32_t dht_codemin_dc0:32; - }; - uint32_t val; -} jpeg_dht_codemin_dc0_reg_t; - -/** Type of dht_codemin_ac0 register - * Trace and Debug registers - */ -typedef union { - struct { - /** dht_codemin_ac0 : HRO; bitpos: [31:0]; default: 0; - * write the minimum codeword of code length from 1~16 of ac0 table. The codeword is - * left shifted to the MSB position of a 16bit word - */ - uint32_t dht_codemin_ac0:32; - }; - uint32_t val; -} jpeg_dht_codemin_ac0_reg_t; - -/** Type of dht_codemin_dc1 register - * Trace and Debug registers - */ -typedef union { - struct { - /** dht_codemin_dc1 : HRO; bitpos: [31:0]; default: 0; - * write the minimum codeword of code length from 1~16 of dc1 table. The codeword is - * left shifted to the MSB position of a 16bit word - */ - uint32_t dht_codemin_dc1:32; - }; - uint32_t val; -} jpeg_dht_codemin_dc1_reg_t; - -/** Type of dht_codemin_ac1 register - * Trace and Debug registers - */ -typedef union { - struct { - /** dht_codemin_ac1 : HRO; bitpos: [31:0]; default: 0; - * write the minimum codeword of code length from 1~16 of ac1 table. The codeword is - * left shifted to the MSB position of a 16bit word - */ - uint32_t dht_codemin_ac1:32; - }; - uint32_t val; -} jpeg_dht_codemin_ac1_reg_t; - -/** Type of decoder_status0 register - * Trace and Debug registers - */ -typedef union { - struct { - /** decode_byte_cnt : RO; bitpos: [25:0]; default: 0; - * Reserved - */ - uint32_t decode_byte_cnt:26; - /** header_dec_st : RO; bitpos: [29:26]; default: 0; - * Reserved - */ - uint32_t header_dec_st:4; - /** decode_sample_sel : RO; bitpos: [31:30]; default: 0; - * Reserved - */ - uint32_t decode_sample_sel:2; - }; - uint32_t val; -} jpeg_decoder_status0_reg_t; - -/** Type of decoder_status1 register - * Trace and Debug registers - */ -typedef union { - struct { - /** encode_data : RO; bitpos: [15:0]; default: 0; - * Reserved - */ - uint32_t encode_data:16; - /** count_q : RO; bitpos: [22:16]; default: 0; - * Reserved - */ - uint32_t count_q:7; - /** mcu_fsm_ready : RO; bitpos: [23]; default: 0; - * Reserved - */ - uint32_t mcu_fsm_ready:1; - /** decode_data : RO; bitpos: [31:24]; default: 0; - * Reserved - */ - uint32_t decode_data:8; - }; - uint32_t val; -} jpeg_decoder_status1_reg_t; - -/** Type of decoder_status2 register - * Trace and Debug registers - */ -typedef union { - struct { - /** comp_block_num : RO; bitpos: [25:0]; default: 0; - * Reserved - */ - uint32_t comp_block_num:26; - /** scan_num : RO; bitpos: [28:26]; default: 0; - * Reserved - */ - uint32_t scan_num:3; - /** rst_check_wait : RO; bitpos: [29]; default: 0; - * Reserved - */ - uint32_t rst_check_wait:1; - /** scan_check_wait : RO; bitpos: [30]; default: 0; - * Reserved - */ - uint32_t scan_check_wait:1; - /** mcu_in_proc : RO; bitpos: [31]; default: 0; - * Reserved - */ - uint32_t mcu_in_proc:1; - }; - uint32_t val; -} jpeg_decoder_status2_reg_t; - -/** Type of decoder_status3 register - * Trace and Debug registers - */ -typedef union { - struct { - /** lookup_data : RO; bitpos: [31:0]; default: 0; - * Reserved - */ - uint32_t lookup_data:32; - }; - uint32_t val; -} jpeg_decoder_status3_reg_t; - -/** Type of decoder_status4 register - * Trace and Debug registers - */ -typedef union { - struct { - /** block_eof_cnt : RO; bitpos: [25:0]; default: 0; - * Reserved - */ - uint32_t block_eof_cnt:26; - /** dezigzag_ready : RO; bitpos: [26]; default: 0; - * Reserved - */ - uint32_t dezigzag_ready:1; - /** de_frame_eof_check : RO; bitpos: [27]; default: 0; - * Reserved - */ - uint32_t de_frame_eof_check:1; - /** de_dma2d_in_push : RO; bitpos: [28]; default: 0; - * Reserved - */ - uint32_t de_dma2d_in_push:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} jpeg_decoder_status4_reg_t; - -/** Type of decoder_status5 register - * Trace and Debug registers - */ -typedef union { - struct { - /** idct_hfm_data : RO; bitpos: [15:0]; default: 0; - * Reserved - */ - uint32_t idct_hfm_data:16; - /** ns0 : RO; bitpos: [18:16]; default: 0; - * Reserved - */ - uint32_t ns0:3; - /** ns1 : RO; bitpos: [21:19]; default: 0; - * Reserved - */ - uint32_t ns1:3; - /** ns2 : RO; bitpos: [24:22]; default: 0; - * Reserved - */ - uint32_t ns2:3; - /** ns3 : RO; bitpos: [27:25]; default: 0; - * Reserved - */ - uint32_t ns3:3; - /** data_last_o : RO; bitpos: [28]; default: 0; - * Reserved - */ - uint32_t data_last_o:1; - /** rdn_result : RO; bitpos: [29]; default: 0; - * redundant registers for jpeg - */ - uint32_t rdn_result:1; - /** rdn_ena : R/W; bitpos: [30]; default: 0; - * redundant control registers for jpeg - */ - uint32_t rdn_ena:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} jpeg_decoder_status5_reg_t; - -/** Type of status5 register - * Trace and Debug registers - */ -typedef union { - struct { - /** pic_block_num : RO; bitpos: [23:0]; default: 0; - * Reserved - */ - uint32_t pic_block_num:24; - uint32_t reserved_24:8; - }; - uint32_t val; -} jpeg_status5_reg_t; - -/** Type of eco_low register - * Trace and Debug registers - */ -typedef union { - struct { - /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0; - * redundant registers for jpeg - */ - uint32_t rdn_eco_low:32; - }; - uint32_t val; -} jpeg_eco_low_reg_t; - -/** Type of eco_high register - * Trace and Debug registers - */ -typedef union { - struct { - /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; - * redundant registers for jpeg - */ - uint32_t rdn_eco_high:32; - }; - uint32_t val; -} jpeg_eco_high_reg_t; - -/** Type of sys register - * Trace and Debug registers - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** clk_en : R/W; bitpos: [31]; default: 0; - * Reserved - */ - uint32_t clk_en:1; - }; - uint32_t val; -} jpeg_sys_reg_t; - -/** Type of version register - * Trace and Debug registers - */ -typedef union { - struct { - /** jpeg_ver : R/W; bitpos: [27:0]; default: 37823072; - * Reserved - */ - uint32_t jpeg_ver:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} jpeg_version_reg_t; - - -typedef struct { - volatile jpeg_config_reg_t config; - volatile jpeg_dqt_info_reg_t dqt_info; - volatile jpeg_pic_size_reg_t pic_size; - volatile jpeg_extd_config_reg_t extd_config; - volatile jpeg_t0qnr_reg_t t0qnr; - volatile jpeg_t1qnr_reg_t t1qnr; - volatile jpeg_t2qnr_reg_t t2qnr; - volatile jpeg_t3qnr_reg_t t3qnr; - volatile jpeg_decode_conf_reg_t decode_conf; - volatile jpeg_c0_reg_t c0; - volatile jpeg_c1_reg_t c1; - volatile jpeg_c2_reg_t c2; - volatile jpeg_c3_reg_t c3; - volatile jpeg_dht_info_reg_t dht_info; - volatile jpeg_int_raw_reg_t int_raw; - volatile jpeg_int_ena_reg_t int_ena; - volatile jpeg_int_st_reg_t int_st; - volatile jpeg_int_clr_reg_t int_clr; - volatile jpeg_status0_reg_t status0; - volatile jpeg_status2_reg_t status2; - volatile jpeg_status3_reg_t status3; - volatile jpeg_status4_reg_t status4; - volatile jpeg_dht_totlen_dc0_reg_t dht_totlen_dc0; - volatile jpeg_dht_val_dc0_reg_t dht_val_dc0; - volatile jpeg_dht_totlen_ac0_reg_t dht_totlen_ac0; - volatile jpeg_dht_val_ac0_reg_t dht_val_ac0; - volatile jpeg_dht_totlen_dc1_reg_t dht_totlen_dc1; - volatile jpeg_dht_val_dc1_reg_t dht_val_dc1; - volatile jpeg_dht_totlen_ac1_reg_t dht_totlen_ac1; - volatile jpeg_dht_val_ac1_reg_t dht_val_ac1; - volatile jpeg_dht_codemin_dc0_reg_t dht_codemin_dc0; - volatile jpeg_dht_codemin_ac0_reg_t dht_codemin_ac0; - volatile jpeg_dht_codemin_dc1_reg_t dht_codemin_dc1; - volatile jpeg_dht_codemin_ac1_reg_t dht_codemin_ac1; - volatile jpeg_decoder_status0_reg_t decoder_status0; - volatile jpeg_decoder_status1_reg_t decoder_status1; - volatile jpeg_decoder_status2_reg_t decoder_status2; - volatile jpeg_decoder_status3_reg_t decoder_status3; - volatile jpeg_decoder_status4_reg_t decoder_status4; - volatile jpeg_decoder_status5_reg_t decoder_status5; - volatile jpeg_status5_reg_t status5; - volatile jpeg_eco_low_reg_t eco_low; - volatile jpeg_eco_high_reg_t eco_high; - uint32_t reserved_0ac[19]; - volatile jpeg_sys_reg_t sys; - volatile jpeg_version_reg_t version; -} jpeg_dev_t; - -extern jpeg_dev_t JPEG; - -#ifndef __cplusplus -_Static_assert(sizeof(jpeg_dev_t) == 0x100, "Invalid size of jpeg_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/jpeg_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/jpeg_struct.h index 854c04e63bbb..0e49abab525c 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/jpeg_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/jpeg_struct.h @@ -164,6 +164,29 @@ typedef union { uint32_t val; } jpeg_pic_size_reg_t; +/** Type of extd_config register + * Control and configuration registers + */ +typedef union { + struct { + /** extd_color_space_en : R/W; bitpos: [0]; default: 0; + * Configure whether to extend picture's color space + * 0:disable + * 1:enable + */ + uint32_t extd_color_space_en:1; + /** extd_color_space : R/W; bitpos: [1]; default: 0; + * Configure extended picture's color space. Valid when JPEG_EXTD_COLOR_SPACE_EN + * configured to 1 + * 0:yuv444 + * 1:yuv420 + */ + uint32_t extd_color_space:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} jpeg_extd_config_reg_t; + /** Type of t0qnr register * Control and configuration registers */ @@ -1390,7 +1413,7 @@ typedef union { */ typedef union { struct { - /** jpeg_ver : R/W; bitpos: [27:0]; default: 34673040; + /** jpeg_ver : R/W; bitpos: [27:0]; default: 37823072; * Reserved */ uint32_t jpeg_ver:28; @@ -1404,7 +1427,7 @@ typedef struct jpeg_dev_t { volatile jpeg_config_reg_t config; volatile jpeg_dqt_info_reg_t dqt_info; volatile jpeg_pic_size_reg_t pic_size; - uint32_t reserved_00c; + volatile jpeg_extd_config_reg_t extd_config; volatile jpeg_t0qnr_reg_t t0qnr; volatile jpeg_t1qnr_reg_t t1qnr; volatile jpeg_t2qnr_reg_t t2qnr; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_eco5_struct.h deleted file mode 100644 index 6864fab43336..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_eco5_struct.h +++ /dev/null @@ -1,875 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: lcd configuration registers */ -/** Type of lcd_clock register - * LCD clock config register. - */ -typedef union { - struct { - /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3; - * f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. - */ - uint32_t lcd_clkcnt_n:6; - /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1; - * 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). - */ - uint32_t lcd_clk_equ_sysclk:1; - /** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0; - * 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. - */ - uint32_t lcd_ck_idle_edge:1; - /** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0; - * 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low - * in the second half data cycle. - */ - uint32_t lcd_ck_out_edge:1; - /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4; - * Integral LCD clock divider value - */ - uint32_t lcd_clkm_div_num:8; - /** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0; - * Fractional clock divider numerator value - */ - uint32_t lcd_clkm_div_b:6; - /** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0; - * Fractional clock divider denominator value - */ - uint32_t lcd_clkm_div_a:6; - /** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0; - * Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. - */ - uint32_t lcd_clk_sel:2; - /** clk_en : R/W; bitpos: [31]; default: 0; - * Set this bit to enable clk gate - */ - uint32_t clk_en:1; - }; - uint32_t val; -} lcdcam_lcd_clock_reg_t; - -/** Type of lcd_rgb_yuv register - * LCD YUV/RGB converter configuration register. - */ -typedef union { - struct { - uint32_t reserved_0:18; - /** lcd_conv_rgb2rgb_mode : R/W; bitpos: [19:18]; default: 3; - * 0:rgb888 trans to rgb565. 1:rgb565 trans to rgb888.2,3:disabled - */ - uint32_t lcd_conv_rgb2rgb_mode:2; - /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0; - * 1:invert every two 8bits input data. 2. disabled. - */ - uint32_t lcd_conv_8bits_data_inv:1; - /** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0; - * 0: txtorx mode off. 1: txtorx mode on. - */ - uint32_t lcd_conv_txtorx:1; - /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3; - * 0: to yuv422. 2: to yuv411. 1,3: disabled. To enable yuv2yuv mode, trans_mode - * must be set to 1. - */ - uint32_t lcd_conv_yuv2yuv_mode:2; - /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0; - * 0: yuv422. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in - */ - uint32_t lcd_conv_yuv_mode:2; - /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0; - * 0:BT601. 1:BT709. - */ - uint32_t lcd_conv_protocol_mode:1; - /** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0; - * LIMIT or FULL mode of Data out. 0: limit. 1: full - */ - uint32_t lcd_conv_data_out_mode:1; - /** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0; - * LIMIT or FULL mode of Data in. 0: limit. 1: full - */ - uint32_t lcd_conv_data_in_mode:1; - /** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0; - * 0: 16bits mode. 1: 8bits mode. - */ - uint32_t lcd_conv_mode_8bits_on:1; - /** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0; - * 0: YUV to RGB. 1: RGB to YUV. - */ - uint32_t lcd_conv_trans_mode:1; - /** lcd_conv_enable : R/W; bitpos: [31]; default: 0; - * 0: Bypass converter. 1: Enable converter. - */ - uint32_t lcd_conv_enable:1; - }; - uint32_t val; -} lcdcam_lcd_rgb_yuv_reg_t; - -/** Type of lcd_user register - * LCD config register. - */ -typedef union { - struct { - /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1; - * The output data cycles minus 1 of LCD module. - */ - uint32_t lcd_dout_cyclelen:13; - /** lcd_always_out_en : R/W; bitpos: [13]; default: 0; - * LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or - * reg_lcd_reset is set. - */ - uint32_t lcd_always_out_en:1; - /** lcd_dout_byte_swizzle_mode : R/W; bitpos: [16:14]; default: 0; - * 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA - */ - uint32_t lcd_dout_byte_swizzle_mode:3; - /** lcd_dout_byte_swizzle_enable : R/W; bitpos: [17]; default: 0; - * 1: enable byte swizzle 0: disable - */ - uint32_t lcd_dout_byte_swizzle_enable:1; - /** lcd_dout_bit_order : R/W; bitpos: [18]; default: 0; - * 1: change bit order in every byte. 0: Not change. - */ - uint32_t lcd_dout_bit_order:1; - /** lcd_byte_mode : R/W; bitpos: [20:19]; default: 0; - * 2: 24bit mode. 1: 16bit mode. 0: 8bit mode - */ - uint32_t lcd_byte_mode:2; - /** lcd_update_reg : R/W/SC; bitpos: [21]; default: 0; - * 1: Update LCD registers, will be cleared by hardware. 0 : Not care. - */ - uint32_t lcd_update_reg:1; - /** lcd_bit_order : R/W; bitpos: [22]; default: 0; - * 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte - * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. - */ - uint32_t lcd_bit_order:1; - /** lcd_byte_order : R/W; bitpos: [23]; default: 0; - * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. - */ - uint32_t lcd_byte_order:1; - /** lcd_dout : R/W; bitpos: [24]; default: 0; - * 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. - */ - uint32_t lcd_dout:1; - /** lcd_dummy : R/W; bitpos: [25]; default: 0; - * 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. - */ - uint32_t lcd_dummy:1; - /** lcd_cmd : R/W; bitpos: [26]; default: 0; - * 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. - */ - uint32_t lcd_cmd:1; - /** lcd_start : R/W/SC; bitpos: [27]; default: 0; - * LCD start sending data enable signal, valid in high level. - */ - uint32_t lcd_start:1; - /** lcd_reset : WT; bitpos: [28]; default: 0; - * The value of command. - */ - uint32_t lcd_reset:1; - /** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0; - * The dummy cycle length minus 1. - */ - uint32_t lcd_dummy_cyclelen:2; - /** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0; - * The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. - */ - uint32_t lcd_cmd_2_cycle_en:1; - }; - uint32_t val; -} lcdcam_lcd_user_reg_t; - -/** Type of lcd_misc register - * LCD config register. - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** lcd_wire_mode : R/W; bitpos: [5:4]; default: 0; - * The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit - */ - uint32_t lcd_wire_mode:2; - /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3; - * The setup cycle length minus 1 in LCD non-RGB mode. - */ - uint32_t lcd_vfk_cyclelen:6; - /** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0; - * The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold - * time cycle length in LCD non-RGB mode. - */ - uint32_t lcd_vbk_cyclelen:13; - /** lcd_next_frame_en : R/W; bitpos: [25]; default: 0; - * 1: Send the next frame data when the current frame is sent out. 0: LCD stops when - * the current frame is sent out. - */ - uint32_t lcd_next_frame_en:1; - /** lcd_bk_en : R/W; bitpos: [26]; default: 0; - * 1: Enable blank region when LCD sends data out. 0: No blank region. - */ - uint32_t lcd_bk_en:1; - /** lcd_afifo_reset : WT; bitpos: [27]; default: 0; - * LCD AFIFO reset signal. - */ - uint32_t lcd_afifo_reset:1; - /** lcd_cd_data_set : R/W; bitpos: [28]; default: 0; - * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = - * reg_cd_idle_edge. - */ - uint32_t lcd_cd_data_set:1; - /** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0; - * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = - * reg_cd_idle_edge. - */ - uint32_t lcd_cd_dummy_set:1; - /** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0; - * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = - * reg_cd_idle_edge. - */ - uint32_t lcd_cd_cmd_set:1; - /** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0; - * The default value of LCD_CD. - */ - uint32_t lcd_cd_idle_edge:1; - }; - uint32_t val; -} lcdcam_lcd_misc_reg_t; - -/** Type of lcd_ctrl register - * LCD config register. - */ -typedef union { - struct { - /** lcd_hb_front : R/W; bitpos: [10:0]; default: 0; - * It is the horizontal blank front porch of a frame. - */ - uint32_t lcd_hb_front:11; - /** lcd_va_height : R/W; bitpos: [20:11]; default: 0; - * It is the vertical active height of a frame. - */ - uint32_t lcd_va_height:10; - /** lcd_vt_height : R/W; bitpos: [30:21]; default: 0; - * It is the vertical total height of a frame. - */ - uint32_t lcd_vt_height:10; - /** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0; - * 1: Enable LCD RGB mode. 0: Disable LCD RGB mode. - */ - uint32_t lcd_rgb_mode_en:1; - }; - uint32_t val; -} lcdcam_lcd_ctrl_reg_t; - -/** Type of lcd_ctrl1 register - * LCD config register. - */ -typedef union { - struct { - /** lcd_vb_front : R/W; bitpos: [7:0]; default: 0; - * It is the vertical blank front porch of a frame. - */ - uint32_t lcd_vb_front:8; - /** lcd_ha_width : R/W; bitpos: [19:8]; default: 0; - * It is the horizontal active width of a frame. - */ - uint32_t lcd_ha_width:12; - /** lcd_ht_width : R/W; bitpos: [31:20]; default: 0; - * It is the horizontal total width of a frame. - */ - uint32_t lcd_ht_width:12; - }; - uint32_t val; -} lcdcam_lcd_ctrl1_reg_t; - -/** Type of lcd_ctrl2 register - * LCD config register. - */ -typedef union { - struct { - /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1; - * It is the position of LCD_VSYNC active pulse in a line. - */ - uint32_t lcd_vsync_width:7; - /** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0; - * It is the idle value of LCD_VSYNC. - */ - uint32_t lcd_vsync_idle_pol:1; - /** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0; - * It is the idle value of LCD_DE. - */ - uint32_t lcd_de_idle_pol:1; - /** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0; - * 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC - * pulse is valid only in active region lines in RGB mode. - */ - uint32_t lcd_hs_blank_en:1; - uint32_t reserved_10:6; - /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1; - * It is the position of LCD_HSYNC active pulse in a line. - */ - uint32_t lcd_hsync_width:7; - /** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0; - * It is the idle value of LCD_HSYNC. - */ - uint32_t lcd_hsync_idle_pol:1; - /** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0; - * It is the position of LCD_HSYNC active pulse in a line. - */ - uint32_t lcd_hsync_position:8; - }; - uint32_t val; -} lcdcam_lcd_ctrl2_reg_t; - -/** Type of lcd_first_cmd_val register - * LCD config register. - */ -typedef union { - struct { - /** lcd_first_cmd_value : R/W; bitpos: [31:0]; default: 0; - * The LCD write command value of first cmd cycle. - */ - uint32_t lcd_first_cmd_value:32; - }; - uint32_t val; -} lcdcam_lcd_first_cmd_val_reg_t; - -/** Type of lcd_latter_cmd_val register - * LCD config register. - */ -typedef union { - struct { - /** lcd_latter_cmd_value : R/W; bitpos: [31:0]; default: 0; - * The LCD write command value of latter cmd cycle. - */ - uint32_t lcd_latter_cmd_value:32; - }; - uint32_t val; -} lcdcam_lcd_latter_cmd_val_reg_t; - -/** Type of lcd_dly_mode_cfg1 register - * LCD config register. - */ -typedef union { - struct { - /** dout16_mode : R/W; bitpos: [1:0]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout16_mode:2; - /** dout17_mode : R/W; bitpos: [3:2]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout17_mode:2; - /** dout18_mode : R/W; bitpos: [5:4]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout18_mode:2; - /** dout19_mode : R/W; bitpos: [7:6]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout19_mode:2; - /** dout20_mode : R/W; bitpos: [9:8]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout20_mode:2; - /** dout21_mode : R/W; bitpos: [11:10]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout21_mode:2; - /** dout22_mode : R/W; bitpos: [13:12]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout22_mode:2; - /** dout23_mode : R/W; bitpos: [15:14]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout23_mode:2; - /** lcd_cd_mode : R/W; bitpos: [17:16]; default: 0; - * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: - * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - */ - uint32_t lcd_cd_mode:2; - /** lcd_de_mode : R/W; bitpos: [19:18]; default: 0; - * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: - * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - */ - uint32_t lcd_de_mode:2; - /** lcd_hsync_mode : R/W; bitpos: [21:20]; default: 0; - * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. - * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - */ - uint32_t lcd_hsync_mode:2; - /** lcd_vsync_mode : R/W; bitpos: [23:22]; default: 0; - * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. - * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - */ - uint32_t lcd_vsync_mode:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} lcdcam_lcd_dly_mode_cfg1_reg_t; - -/** Type of lcd_dly_mode_cfg2 register - * LCD config register. - */ -typedef union { - struct { - /** dout0_mode : R/W; bitpos: [1:0]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout0_mode:2; - /** dout1_mode : R/W; bitpos: [3:2]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout1_mode:2; - /** dout2_mode : R/W; bitpos: [5:4]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout2_mode:2; - /** dout3_mode : R/W; bitpos: [7:6]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout3_mode:2; - /** dout4_mode : R/W; bitpos: [9:8]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout4_mode:2; - /** dout5_mode : R/W; bitpos: [11:10]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout5_mode:2; - /** dout6_mode : R/W; bitpos: [13:12]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout6_mode:2; - /** dout7_mode : R/W; bitpos: [15:14]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout7_mode:2; - /** dout8_mode : R/W; bitpos: [17:16]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout8_mode:2; - /** dout9_mode : R/W; bitpos: [19:18]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout9_mode:2; - /** dout10_mode : R/W; bitpos: [21:20]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout10_mode:2; - /** dout11_mode : R/W; bitpos: [23:22]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout11_mode:2; - /** dout12_mode : R/W; bitpos: [25:24]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout12_mode:2; - /** dout13_mode : R/W; bitpos: [27:26]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout13_mode:2; - /** dout14_mode : R/W; bitpos: [29:28]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout14_mode:2; - /** dout15_mode : R/W; bitpos: [31:30]; default: 0; - * The output data bit $n is delayed by module clock LCD_CLK. 0: output without - * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of - * LCD_CLK. - */ - uint32_t dout15_mode:2; - }; - uint32_t val; -} lcdcam_lcd_dly_mode_cfg2_reg_t; - - -/** Group: cam configuration registers */ -/** Type of cam_ctrl register - * CAM config register. - */ -typedef union { - struct { - /** cam_stop_en : R/W; bitpos: [0]; default: 0; - * Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. - */ - uint32_t cam_stop_en:1; - /** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0; - * Filter threshold value for CAM_VSYNC signal. - */ - uint32_t cam_vsync_filter_thres:3; - /** cam_update_reg : R/W/SC; bitpos: [4]; default: 0; - * 1: Update Camera registers, will be cleared by hardware. 0 : Not care. - */ - uint32_t cam_update_reg:1; - /** cam_byte_order : R/W; bitpos: [5]; default: 0; - * 1: invert data byte order. 0: Not change. - */ - uint32_t cam_byte_order:1; - /** cam_bit_order : R/W; bitpos: [6]; default: 0; - * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte - * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. - */ - uint32_t cam_bit_order:1; - /** cam_line_int_en : R/W; bitpos: [7]; default: 0; - * 1: Enable to generate CAM_HS_INT. 0: Disable. - */ - uint32_t cam_line_int_en:1; - /** cam_vs_eof_en : R/W; bitpos: [8]; default: 0; - * 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by - * reg_cam_rec_data_cyclelen. - */ - uint32_t cam_vs_eof_en:1; - /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4; - * Integral Camera clock divider value - */ - uint32_t cam_clkm_div_num:8; - /** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0; - * Fractional clock divider numerator value - */ - uint32_t cam_clkm_div_b:6; - /** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0; - * Fractional clock divider denominator value - */ - uint32_t cam_clkm_div_a:6; - /** cam_clk_sel : R/W; bitpos: [30:29]; default: 0; - * Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. - */ - uint32_t cam_clk_sel:2; - uint32_t reserved_31:1; - }; - uint32_t val; -} lcdcam_cam_ctrl_reg_t; - -/** Type of cam_ctrl1 register - * CAM config register. - */ -typedef union { - struct { - /** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0; - * Camera receive data byte length minus 1 to set DMA in_suc_eof_int. - */ - uint32_t cam_rec_data_bytelen:16; - /** cam_line_int_num : R/W; bitpos: [21:16]; default: 0; - * The line number minus 1 to generate cam_hs_int. - */ - uint32_t cam_line_int_num:6; - /** cam_clk_inv : R/W; bitpos: [22]; default: 0; - * 1: Invert the input signal CAM_PCLK. 0: Not invert. - */ - uint32_t cam_clk_inv:1; - /** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0; - * 1: Enable CAM_VSYNC filter function. 0: bypass. - */ - uint32_t cam_vsync_filter_en:1; - /** cam_2byte_en : R/W; bitpos: [24]; default: 0; - * 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. - */ - uint32_t cam_2byte_en:1; - /** cam_de_inv : R/W; bitpos: [25]; default: 0; - * CAM_DE invert enable signal, valid in high level. - */ - uint32_t cam_de_inv:1; - /** cam_hsync_inv : R/W; bitpos: [26]; default: 0; - * CAM_HSYNC invert enable signal, valid in high level. - */ - uint32_t cam_hsync_inv:1; - /** cam_vsync_inv : R/W; bitpos: [27]; default: 0; - * CAM_VSYNC invert enable signal, valid in high level. - */ - uint32_t cam_vsync_inv:1; - /** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0; - * 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control - * signals are CAM_DE and CAM_VSYNC. - */ - uint32_t cam_vh_de_mode_en:1; - /** cam_start : R/W/SC; bitpos: [29]; default: 0; - * Camera module start signal. - */ - uint32_t cam_start:1; - /** cam_reset : WT; bitpos: [30]; default: 0; - * Camera module reset signal. - */ - uint32_t cam_reset:1; - /** cam_afifo_reset : WT; bitpos: [31]; default: 0; - * Camera AFIFO reset signal. - */ - uint32_t cam_afifo_reset:1; - }; - uint32_t val; -} lcdcam_cam_ctrl1_reg_t; - -/** Type of cam_rgb_yuv register - * CAM YUV/RGB converter configuration register. - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0; - * 1:invert every two 8bits input data. 2. disabled. - */ - uint32_t cam_conv_8bits_data_inv:1; - /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3; - * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, - * trans_mode must be set to 1. - */ - uint32_t cam_conv_yuv2yuv_mode:2; - /** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0; - * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv - * mode of Data_in - */ - uint32_t cam_conv_yuv_mode:2; - /** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0; - * 0:BT601. 1:BT709. - */ - uint32_t cam_conv_protocol_mode:1; - /** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0; - * LIMIT or FULL mode of Data out. 0: limit. 1: full - */ - uint32_t cam_conv_data_out_mode:1; - /** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0; - * LIMIT or FULL mode of Data in. 0: limit. 1: full - */ - uint32_t cam_conv_data_in_mode:1; - /** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0; - * 0: 16bits mode. 1: 8bits mode. - */ - uint32_t cam_conv_mode_8bits_on:1; - /** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0; - * 0: YUV to RGB. 1: RGB to YUV. - */ - uint32_t cam_conv_trans_mode:1; - /** cam_conv_enable : R/W; bitpos: [31]; default: 0; - * 0: Bypass converter. 1: Enable converter. - */ - uint32_t cam_conv_enable:1; - }; - uint32_t val; -} lcdcam_cam_rgb_yuv_reg_t; - - -/** Group: Interrupt registers */ -/** Type of lc_dma_int_ena register - * LCDCAM interrupt enable register. - */ -typedef union { - struct { - /** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0; - * The enable bit for LCD frame end interrupt. - */ - uint32_t lcd_vsync_int_ena:1; - /** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0; - * The enable bit for lcd transfer end interrupt. - */ - uint32_t lcd_trans_done_int_ena:1; - /** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0; - * The enable bit for Camera frame end interrupt. - */ - uint32_t cam_vsync_int_ena:1; - /** cam_hs_int_ena : R/W; bitpos: [3]; default: 0; - * The enable bit for Camera line interrupt. - */ - uint32_t cam_hs_int_ena:1; - /** lcd_underrun_int_ena : R/W; bitpos: [4]; default: 0; - * The enable bit for LCD underrun interrupt - */ - uint32_t lcd_underrun_int_ena:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} lcdcam_lc_dma_int_ena_reg_t; - -/** Type of lc_dma_int_raw register - * LCDCAM interrupt raw register, valid in level. - */ -typedef union { - struct { - /** lcd_vsync_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; - * The raw bit for LCD frame end interrupt. - */ - uint32_t lcd_vsync_int_raw:1; - /** lcd_trans_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; - * The raw bit for lcd transfer end interrupt. - */ - uint32_t lcd_trans_done_int_raw:1; - /** cam_vsync_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; - * The raw bit for Camera frame end interrupt. - */ - uint32_t cam_vsync_int_raw:1; - /** cam_hs_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for Camera line interrupt. - */ - uint32_t cam_hs_int_raw:1; - /** lcd_underrun_int_raw : RO/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for LCD underrun interrupt - */ - uint32_t lcd_underrun_int_raw:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} lcdcam_lc_dma_int_raw_reg_t; - -/** Type of lc_dma_int_st register - * LCDCAM interrupt status register. - */ -typedef union { - struct { - /** lcd_vsync_int_st : RO; bitpos: [0]; default: 0; - * The status bit for LCD frame end interrupt. - */ - uint32_t lcd_vsync_int_st:1; - /** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0; - * The status bit for lcd transfer end interrupt. - */ - uint32_t lcd_trans_done_int_st:1; - /** cam_vsync_int_st : RO; bitpos: [2]; default: 0; - * The status bit for Camera frame end interrupt. - */ - uint32_t cam_vsync_int_st:1; - /** cam_hs_int_st : RO; bitpos: [3]; default: 0; - * The status bit for Camera transfer end interrupt. - */ - uint32_t cam_hs_int_st:1; - /** lcd_underrun_int_st : RO; bitpos: [4]; default: 0; - * The status bit for LCD underrun interrupt - */ - uint32_t lcd_underrun_int_st:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} lcdcam_lc_dma_int_st_reg_t; - -/** Type of lc_dma_int_clr register - * LCDCAM interrupt clear register. - */ -typedef union { - struct { - /** lcd_vsync_int_clr : WT; bitpos: [0]; default: 0; - * The clear bit for LCD frame end interrupt. - */ - uint32_t lcd_vsync_int_clr:1; - /** lcd_trans_done_int_clr : WT; bitpos: [1]; default: 0; - * The clear bit for lcd transfer end interrupt. - */ - uint32_t lcd_trans_done_int_clr:1; - /** cam_vsync_int_clr : WT; bitpos: [2]; default: 0; - * The clear bit for Camera frame end interrupt. - */ - uint32_t cam_vsync_int_clr:1; - /** cam_hs_int_clr : WT; bitpos: [3]; default: 0; - * The clear bit for Camera line interrupt. - */ - uint32_t cam_hs_int_clr:1; - /** lcd_underrun_int_clr : WT; bitpos: [4]; default: 0; - * The clear bit for LCD underrun interrupt - */ - uint32_t lcd_underrun_int_clr:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} lcdcam_lc_dma_int_clr_reg_t; - - -/** Group: Version register */ -/** Type of lc_reg_date register - * Version register - */ -typedef union { - struct { - /** lc_date : R/W; bitpos: [27:0]; default: 38806054; - * LCD_CAM version control register - */ - uint32_t lc_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} lcdcam_lc_reg_date_reg_t; - - -typedef struct { - volatile lcdcam_lcd_clock_reg_t lcd_clock; - volatile lcdcam_cam_ctrl_reg_t cam_ctrl; - volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1; - volatile lcdcam_cam_rgb_yuv_reg_t cam_rgb_yuv; - volatile lcdcam_lcd_rgb_yuv_reg_t lcd_rgb_yuv; - volatile lcdcam_lcd_user_reg_t lcd_user; - volatile lcdcam_lcd_misc_reg_t lcd_misc; - volatile lcdcam_lcd_ctrl_reg_t lcd_ctrl; - volatile lcdcam_lcd_ctrl1_reg_t lcd_ctrl1; - volatile lcdcam_lcd_ctrl2_reg_t lcd_ctrl2; - volatile lcdcam_lcd_first_cmd_val_reg_t lcd_first_cmd_val; - volatile lcdcam_lcd_latter_cmd_val_reg_t lcd_latter_cmd_val; - volatile lcdcam_lcd_dly_mode_cfg1_reg_t lcd_dly_mode_cfg1; - uint32_t reserved_034; - volatile lcdcam_lcd_dly_mode_cfg2_reg_t lcd_dly_mode_cfg2; - uint32_t reserved_03c[10]; - volatile lcdcam_lc_dma_int_ena_reg_t lc_dma_int_ena; - volatile lcdcam_lc_dma_int_raw_reg_t lc_dma_int_raw; - volatile lcdcam_lc_dma_int_st_reg_t lc_dma_int_st; - volatile lcdcam_lc_dma_int_clr_reg_t lc_dma_int_clr; - uint32_t reserved_074[34]; - volatile lcdcam_lc_reg_date_reg_t lc_reg_date; -} lcdcam_dev_t; - -extern lcdcam_dev_t LCD_CAM; - -#ifndef __cplusplus -_Static_assert(sizeof(lcdcam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_struct.h index 470ef9961ab8..08d5844e0e54 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_struct.h @@ -62,7 +62,11 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:20; + uint32_t reserved_0:18; + /** lcd_conv_rgb2rgb_mode : R/W; bitpos: [19:18]; default: 3; + * 0:rgb888 trans to rgb565. 1:rgb565 trans to rgb888.2,3:disabled + */ + uint32_t lcd_conv_rgb2rgb_mode:2; /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0; * 1:invert every two 8bits input data. 2. disabled. */ @@ -72,13 +76,12 @@ typedef union { */ uint32_t lcd_conv_txtorx:1; /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3; - * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, - * trans_mode must be set to 1. + * 0: to yuv422. 2: to yuv411. 1,3: disabled. To enable yuv2yuv mode, trans_mode + * must be set to 1. */ uint32_t lcd_conv_yuv2yuv_mode:2; /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0; - * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv - * mode of Data_in + * 0: yuv422. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in */ uint32_t lcd_conv_yuv_mode:2; /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0; @@ -553,12 +556,12 @@ typedef union { */ uint32_t cam_update_reg:1; /** cam_byte_order : R/W; bitpos: [5]; default: 0; - * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte - * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + * 1: invert data byte order. 0: Not change. */ uint32_t cam_byte_order:1; /** cam_bit_order : R/W; bitpos: [6]; default: 0; - * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte + * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. */ uint32_t cam_bit_order:1; /** cam_line_int_en : R/W; bitpos: [7]; default: 0; @@ -720,7 +723,11 @@ typedef union { * The enable bit for Camera line interrupt. */ uint32_t cam_hs_int_ena:1; - uint32_t reserved_4:28; + /** lcd_underrun_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for LCD underrun interrupt + */ + uint32_t lcd_underrun_int_ena:1; + uint32_t reserved_5:27; }; uint32_t val; } lcdcam_lc_dma_int_ena_reg_t; @@ -746,7 +753,11 @@ typedef union { * The raw bit for Camera line interrupt. */ uint32_t cam_hs_int_raw:1; - uint32_t reserved_4:28; + /** lcd_underrun_int_raw : RO/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for LCD underrun interrupt + */ + uint32_t lcd_underrun_int_raw:1; + uint32_t reserved_5:27; }; uint32_t val; } lcdcam_lc_dma_int_raw_reg_t; @@ -772,7 +783,11 @@ typedef union { * The status bit for Camera transfer end interrupt. */ uint32_t cam_hs_int_st:1; - uint32_t reserved_4:28; + /** lcd_underrun_int_st : RO; bitpos: [4]; default: 0; + * The status bit for LCD underrun interrupt + */ + uint32_t lcd_underrun_int_st:1; + uint32_t reserved_5:27; }; uint32_t val; } lcdcam_lc_dma_int_st_reg_t; @@ -798,7 +813,11 @@ typedef union { * The clear bit for Camera line interrupt. */ uint32_t cam_hs_int_clr:1; - uint32_t reserved_4:28; + /** lcd_underrun_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for LCD underrun interrupt + */ + uint32_t lcd_underrun_int_clr:1; + uint32_t reserved_5:27; }; uint32_t val; } lcdcam_lc_dma_int_clr_reg_t; @@ -810,7 +829,7 @@ typedef union { */ typedef union { struct { - /** lc_date : R/W; bitpos: [27:0]; default: 36712592; + /** lc_date : R/W; bitpos: [27:0]; default: 38806054; * LCD_CAM version control register */ uint32_t lc_date:28; @@ -845,13 +864,12 @@ typedef struct lcd_cam_dev_t { volatile lcdcam_lc_reg_date_reg_t lc_reg_date; } lcd_cam_dev_t; +extern lcd_cam_dev_t LCD_CAM; #ifndef __cplusplus -_Static_assert(sizeof(lcd_cam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure"); +_Static_assert(sizeof(lcd_cam_dev_t) == 0x100, "Invalid size of lcd_cam_dev_t structure"); #endif -extern lcd_cam_dev_t LCD_CAM; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h index 0735efd6bed2..6afcf7b482d7 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h @@ -813,244 +813,19 @@ typedef union { } lp_spi_sleep_conf1_reg_t; -/** Group: LP SPI W0 REG */ -/** Type of spi_w0 register - * SPI CPU-controlled buffer0 +/** Group: LP SPI Wn REG */ +/** Type of spi_wn register + * SPI CPU-controlled buffer */ typedef union { struct { - /** reg_buf0 : R/W/SS; bitpos: [31:0]; default: 0; + /** reg_buf : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ - uint32_t reg_buf0:32; + uint32_t reg_buf:32; }; uint32_t val; -} lp_spi_w0_reg_t; - - -/** Group: LP SPI W1 REG */ -/** Type of spi_w1 register - * SPI CPU-controlled buffer1 - */ -typedef union { - struct { - /** reg_buf1 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf1:32; - }; - uint32_t val; -} lp_spi_w1_reg_t; - - -/** Group: LP SPI W2 REG */ -/** Type of spi_w2 register - * SPI CPU-controlled buffer2 - */ -typedef union { - struct { - /** reg_buf2 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf2:32; - }; - uint32_t val; -} lp_spi_w2_reg_t; - - -/** Group: LP SPI W3 REG */ -/** Type of spi_w3 register - * SPI CPU-controlled buffer3 - */ -typedef union { - struct { - /** reg_buf3 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf3:32; - }; - uint32_t val; -} lp_spi_w3_reg_t; - - -/** Group: LP SPI W4 REG */ -/** Type of spi_w4 register - * SPI CPU-controlled buffer4 - */ -typedef union { - struct { - /** reg_buf4 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf4:32; - }; - uint32_t val; -} lp_spi_w4_reg_t; - - -/** Group: LP SPI W5 REG */ -/** Type of spi_w5 register - * SPI CPU-controlled buffer5 - */ -typedef union { - struct { - /** reg_buf5 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf5:32; - }; - uint32_t val; -} lp_spi_w5_reg_t; - - -/** Group: LP SPI W6 REG */ -/** Type of spi_w6 register - * SPI CPU-controlled buffer6 - */ -typedef union { - struct { - /** reg_buf6 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf6:32; - }; - uint32_t val; -} lp_spi_w6_reg_t; - - -/** Group: LP SPI W7 REG */ -/** Type of spi_w7 register - * SPI CPU-controlled buffer7 - */ -typedef union { - struct { - /** reg_buf7 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf7:32; - }; - uint32_t val; -} lp_spi_w7_reg_t; - - -/** Group: LP SPI W8 REG */ -/** Type of spi_w8 register - * SPI CPU-controlled buffer8 - */ -typedef union { - struct { - /** reg_buf8 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf8:32; - }; - uint32_t val; -} lp_spi_w8_reg_t; - - -/** Group: LP SPI W9 REG */ -/** Type of spi_w9 register - * SPI CPU-controlled buffer9 - */ -typedef union { - struct { - /** reg_buf9 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf9:32; - }; - uint32_t val; -} lp_spi_w9_reg_t; - - -/** Group: LP SPI W10 REG */ -/** Type of spi_w10 register - * SPI CPU-controlled buffer10 - */ -typedef union { - struct { - /** reg_buf10 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf10:32; - }; - uint32_t val; -} lp_spi_w10_reg_t; - - -/** Group: LP SPI W11 REG */ -/** Type of spi_w11 register - * SPI CPU-controlled buffer11 - */ -typedef union { - struct { - /** reg_buf11 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf11:32; - }; - uint32_t val; -} lp_spi_w11_reg_t; - - -/** Group: LP SPI W12 REG */ -/** Type of spi_w12 register - * SPI CPU-controlled buffer12 - */ -typedef union { - struct { - /** reg_buf12 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf12:32; - }; - uint32_t val; -} lp_spi_w12_reg_t; - - -/** Group: LP SPI W13 REG */ -/** Type of spi_w13 register - * SPI CPU-controlled buffer13 - */ -typedef union { - struct { - /** reg_buf13 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf13:32; - }; - uint32_t val; -} lp_spi_w13_reg_t; - - -/** Group: LP SPI W14 REG */ -/** Type of spi_w14 register - * SPI CPU-controlled buffer14 - */ -typedef union { - struct { - /** reg_buf14 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf14:32; - }; - uint32_t val; -} lp_spi_w14_reg_t; - - -/** Group: LP SPI W15 REG */ -/** Type of spi_w15 register - * SPI CPU-controlled buffer15 - */ -typedef union { - struct { - /** reg_buf15 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf15:32; - }; - uint32_t val; -} lp_spi_w15_reg_t; +} lp_spi_wn_reg_t; /** Group: LP SPI SLAVE REG */ @@ -1238,22 +1013,7 @@ typedef struct { volatile lp_spi_sleep_conf1_reg_t spi_sleep_conf1; volatile lp_spi_dma_int_set_reg_t spi_dma_int_set; uint32_t reserved_050[18]; - volatile lp_spi_w0_reg_t spi_w0; - volatile lp_spi_w1_reg_t spi_w1; - volatile lp_spi_w2_reg_t spi_w2; - volatile lp_spi_w3_reg_t spi_w3; - volatile lp_spi_w4_reg_t spi_w4; - volatile lp_spi_w5_reg_t spi_w5; - volatile lp_spi_w6_reg_t spi_w6; - volatile lp_spi_w7_reg_t spi_w7; - volatile lp_spi_w8_reg_t spi_w8; - volatile lp_spi_w9_reg_t spi_w9; - volatile lp_spi_w10_reg_t spi_w10; - volatile lp_spi_w11_reg_t spi_w11; - volatile lp_spi_w12_reg_t spi_w12; - volatile lp_spi_w13_reg_t spi_w13; - volatile lp_spi_w14_reg_t spi_w14; - volatile lp_spi_w15_reg_t spi_w15; + volatile lp_spi_wn_reg_t data_buf[16]; uint32_t reserved_0d8[2]; volatile lp_spi_slave_reg_t spi_slave; volatile lp_spi_slave1_reg_t spi_slave1; @@ -1263,12 +1023,12 @@ typedef struct { volatile lp_rnd_eco_cs_reg_t rnd_eco_cs; volatile lp_rnd_eco_low_reg_t rnd_eco_low; volatile lp_rnd_eco_high_reg_t rnd_eco_high; -} lp_dev_t; +} lp_spi_dev_t; -extern lp_dev_t LP_SPI; +extern lp_spi_dev_t LP_SPI; #ifndef __cplusplus -_Static_assert(sizeof(lp_dev_t) == 0x100, "Invalid size of lp_dev_t structure"); +_Static_assert(sizeof(lp_spi_dev_t) == 0x100, "Invalid size of lp_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_eco5_struct.h deleted file mode 100644 index f2f78f4ec96b..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_eco5_struct.h +++ /dev/null @@ -1,868 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of clk_en register - * dsi bridge clk control register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * this bit configures force_on of dsi_bridge register clock gate - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} dsi_brg_clk_en_reg_t; - -/** Type of en register - * dsi bridge en register - */ -typedef union { - struct { - /** dsi_en : R/W; bitpos: [0]; default: 0; - * this bit configures module enable of dsi_bridge. 0: disable, 1: enable - */ - uint32_t dsi_en:1; - /** dsi_brig_rst : R/W; bitpos: [1]; default: 0; - * Configures software reset of dsi_bridge. 0: release reset, 1: reset - */ - uint32_t dsi_brig_rst:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} dsi_brg_en_reg_t; - -/** Type of dma_req_cfg register - * dsi bridge dma burst len register - */ -typedef union { - struct { - /** dma_burst_len : R/W; bitpos: [11:0]; default: 128; - * this field configures the num of 64-bit in one dma burst transfer, valid only when - * dsi_bridge as flow controller - */ - uint32_t dma_burst_len:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} dsi_brg_dma_req_cfg_reg_t; - -/** Type of raw_num_cfg register - * dsi bridge raw number control register - */ -typedef union { - struct { - /** raw_num_total : R/W; bitpos: [21:0]; default: 230400; - * this field configures number of total pix bits/64 - */ - uint32_t raw_num_total:22; - /** unalign_64bit_en : R/W; bitpos: [22]; default: 0; - * this field configures whether the total pix bits is a multiple of 64bits. 0: align - * to 64-bit, 1: unalign to 64-bit - */ - uint32_t unalign_64bit_en:1; - uint32_t reserved_23:8; - /** raw_num_total_set : WT; bitpos: [31]; default: 0; - * this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable, - * 1: enable. valid only when dsi_bridge as flow controller - */ - uint32_t raw_num_total_set:1; - }; - uint32_t val; -} dsi_brg_raw_num_cfg_reg_t; - -/** Type of raw_buf_credit_ctl register - * dsi bridge credit register - */ -typedef union { - struct { - /** credit_thrd : R/W; bitpos: [14:0]; default: 1024; - * this field configures the threshold whether dsi_bridge fifo can receive one more - * 64-bit, valid only when dsi_bridge as flow controller - */ - uint32_t credit_thrd:15; - uint32_t reserved_15:1; - /** credit_burst_thrd : R/W; bitpos: [30:16]; default: 800; - * this field configures the threshold whether dsi_bridge fifo can receive one more - * dma burst, valid only when dsi_bridge as flow controller - */ - uint32_t credit_burst_thrd:15; - /** credit_reset : R/W; bitpos: [31]; default: 0; - * this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when - * dsi_bridge as flow controller - */ - uint32_t credit_reset:1; - }; - uint32_t val; -} dsi_brg_raw_buf_credit_ctl_reg_t; - -/** Type of pixel_type register - * dsi bridge dpi type control register - */ -typedef union { - struct { - /** raw_type : R/W; bitpos: [3:0]; default: 0; - * this field configures the raw pixel type. 0: rgb888, 1:rgb666, 2:rgb565, 8:yuv444, - * 9:yuv422, 10:yuv420, 12:gray - */ - uint32_t raw_type:4; - /** dpi_config : R/W; bitpos: [5:4]; default: 0; - * this field configures the pixel arrange type of dpi interface - */ - uint32_t dpi_config:2; - /** data_in_type : R/W; bitpos: [6]; default: 0; - * input data type, 0: not yuv, 1: yuv - */ - uint32_t data_in_type:1; - /** dpi_type : R/W; bitpos: [10:7]; default: 0; - * this field configures the dpi pixel type. 0: rgb888, 1:rgb666, 2:rgb565 - */ - uint32_t dpi_type:4; - uint32_t reserved_11:21; - }; - uint32_t val; -} dsi_brg_pixel_type_reg_t; - -/** Type of dma_block_interval register - * dsi bridge dma block interval control register - */ -typedef union { - struct { - /** dma_block_slot : R/W; bitpos: [9:0]; default: 9; - * this field configures the max block_slot_cnt - */ - uint32_t dma_block_slot:10; - /** dma_block_interval : R/W; bitpos: [27:10]; default: 9; - * this field configures the max block_interval_cnt, block_interval_cnt increased by 1 - * when block_slot_cnt if full - */ - uint32_t dma_block_interval:18; - /** raw_num_total_auto_reload : R/W; bitpos: [28]; default: 1; - * this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable - */ - uint32_t raw_num_total_auto_reload:1; - /** dma_block_interval_en : R/W; bitpos: [29]; default: 1; - * this bit configures enable of interval between dma block transfer, 0: disable, 1: - * enable - */ - uint32_t dma_block_interval_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} dsi_brg_dma_block_interval_reg_t; - -/** Type of dma_req_interval register - * dsi bridge dma req interval control register - */ -typedef union { - struct { - /** dma_req_interval : R/W; bitpos: [15:0]; default: 1; - * this field configures the interval between dma req events - */ - uint32_t dma_req_interval:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} dsi_brg_dma_req_interval_reg_t; - -/** Type of dpi_lcd_ctl register - * dsi bridge dpi signal control register - */ -typedef union { - struct { - /** dpishutdn : R/W; bitpos: [0]; default: 0; - * this bit configures dpishutdn signal in dpi interface - */ - uint32_t dpishutdn:1; - /** dpicolorm : R/W; bitpos: [1]; default: 0; - * this bit configures dpicolorm signal in dpi interface - */ - uint32_t dpicolorm:1; - /** dpiupdatecfg : R/W; bitpos: [2]; default: 0; - * this bit configures dpiupdatecfg signal in dpi interface - */ - uint32_t dpiupdatecfg:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} dsi_brg_dpi_lcd_ctl_reg_t; - -/** Type of dpi_rsv_dpi_data register - * dsi bridge dpi reserved data register - */ -typedef union { - struct { - /** dpi_rsv_data : R/W; bitpos: [29:0]; default: 16383; - * this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow - */ - uint32_t dpi_rsv_data:30; - /** dpi_dbg_en : R/W; bitpos: [30]; default: 0; - * Configures data debug feature enable. 0: disable, 1: enable - */ - uint32_t dpi_dbg_en:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} dsi_brg_dpi_rsv_dpi_data_reg_t; - -/** Type of dpi_v_cfg0 register - * dsi bridge dpi v config register 0 - */ -typedef union { - struct { - /** vtotal : R/W; bitpos: [11:0]; default: 525; - * this field configures the total length of one frame (by line) for dpi output, must - * meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank - */ - uint32_t vtotal:12; - uint32_t reserved_12:4; - /** vdisp : R/W; bitpos: [27:16]; default: 480; - * this field configures the length of valid line (by line) for dpi output - */ - uint32_t vdisp:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} dsi_brg_dpi_v_cfg0_reg_t; - -/** Type of dpi_v_cfg1 register - * dsi bridge dpi v config register 1 - */ -typedef union { - struct { - /** vbank : R/W; bitpos: [11:0]; default: 33; - * this field configures the length between vsync and valid line (by line) for dpi - * output - */ - uint32_t vbank:12; - uint32_t reserved_12:4; - /** vsync : R/W; bitpos: [27:16]; default: 2; - * this field configures the length of vsync (by line) for dpi output - */ - uint32_t vsync:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} dsi_brg_dpi_v_cfg1_reg_t; - -/** Type of dpi_h_cfg0 register - * dsi bridge dpi h config register 0 - */ -typedef union { - struct { - /** htotal : R/W; bitpos: [11:0]; default: 800; - * this field configures the total length of one line (by pixel num) for dpi output, - * must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank - */ - uint32_t htotal:12; - uint32_t reserved_12:4; - /** hdisp : R/W; bitpos: [27:16]; default: 640; - * this field configures the length of valid pixel data (by pixel num) for dpi output - */ - uint32_t hdisp:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} dsi_brg_dpi_h_cfg0_reg_t; - -/** Type of dpi_h_cfg1 register - * dsi bridge dpi h config register 1 - */ -typedef union { - struct { - /** hbank : R/W; bitpos: [11:0]; default: 48; - * this field configures the length between hsync and pixel data valid (by pixel num) - * for dpi output - */ - uint32_t hbank:12; - uint32_t reserved_12:4; - /** hsync : R/W; bitpos: [27:16]; default: 96; - * this field configures the length of hsync (by pixel num) for dpi output - */ - uint32_t hsync:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} dsi_brg_dpi_h_cfg1_reg_t; - -/** Type of dpi_misc_config register - * dsi_bridge dpi misc config register - */ -typedef union { - struct { - /** dpi_en : R/W; bitpos: [0]; default: 0; - * this bit configures enable of dpi output, 0: disable, 1: enable - */ - uint32_t dpi_en:1; - uint32_t reserved_1:3; - /** fifo_underrun_discard_vcnt : R/W; bitpos: [15:4]; default: 413; - * this field configures the underrun interrupt musk, when underrun occurs and line - * cnt is less then this field - */ - uint32_t fifo_underrun_discard_vcnt:12; - uint32_t reserved_16:16; - }; - uint32_t val; -} dsi_brg_dpi_misc_config_reg_t; - -/** Type of dpi_config_update register - * dsi_bridge dpi config update register - */ -typedef union { - struct { - /** dpi_config_update : WT; bitpos: [0]; default: 0; - * write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_* - */ - uint32_t dpi_config_update:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} dsi_brg_dpi_config_update_reg_t; - -/** Type of host_trigger_rev register - * dsi_bridge host trigger reverse control register - */ -typedef union { - struct { - /** tx_trigger_rev_en : R/W; bitpos: [0]; default: 0; - * tx_trigger reverse. 0: disable, 1: enable - */ - uint32_t tx_trigger_rev_en:1; - /** rx_trigger_rev_en : R/W; bitpos: [1]; default: 0; - * rx_trigger reverse. 0: disable, 1: enable - */ - uint32_t rx_trigger_rev_en:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} dsi_brg_host_trigger_rev_reg_t; - -/** Type of blk_raw_num_cfg register - * dsi_bridge block raw number control register - */ -typedef union { - struct { - /** blk_raw_num_total : R/W; bitpos: [21:0]; default: 230400; - * this field configures number of total block pix bits/64 - */ - uint32_t blk_raw_num_total:22; - uint32_t reserved_22:9; - /** blk_raw_num_total_set : WT; bitpos: [31]; default: 0; - * write 1 to reload reg_blk_raw_num_total to internal cnt - */ - uint32_t blk_raw_num_total_set:1; - }; - uint32_t val; -} dsi_brg_blk_raw_num_cfg_reg_t; - -/** Type of dma_frame_interval register - * dsi_bridge dam frame interval control register - */ -typedef union { - struct { - /** dma_frame_slot : R/W; bitpos: [9:0]; default: 9; - * this field configures the max frame_slot_cnt - */ - uint32_t dma_frame_slot:10; - /** dma_frame_interval : R/W; bitpos: [27:10]; default: 9; - * this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 - * when frame_slot_cnt if full - */ - uint32_t dma_frame_interval:18; - /** dma_multiblk_en : R/W; bitpos: [28]; default: 0; - * this bit configures enable multi-blk transfer, 0: disable, 1: enable - */ - uint32_t dma_multiblk_en:1; - /** dma_frame_interval_en : R/W; bitpos: [29]; default: 1; - * this bit configures enable interval between frame transfer, 0: disable, 1: enable - */ - uint32_t dma_frame_interval_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} dsi_brg_dma_frame_interval_reg_t; - -/** Type of mem_aux_ctrl register - * dsi_bridge mem aux control register - */ -typedef union { - struct { - /** dsi_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; - * this field configures dsi_bridge fifo memory aux ctrl - */ - uint32_t dsi_mem_aux_ctrl:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} dsi_brg_mem_aux_ctrl_reg_t; - -/** Type of rdn_eco_low register - * dsi_bridge rdn eco all low register - */ -typedef union { - struct { - /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0; - * rdn_eco_low - */ - uint32_t rdn_eco_low:32; - }; - uint32_t val; -} dsi_brg_rdn_eco_low_reg_t; - -/** Type of rdn_eco_high register - * dsi_bridge rdn eco all high register - */ -typedef union { - struct { - /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; - * rdn_eco_high - */ - uint32_t rdn_eco_high:32; - }; - uint32_t val; -} dsi_brg_rdn_eco_high_reg_t; - -/** Type of host_ctrl register - * dsi_bridge host control register - */ -typedef union { - struct { - /** dsi_cfg_ref_clk_en : R/W; bitpos: [0]; default: 1; - * this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: - * enable - */ - uint32_t dsi_cfg_ref_clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} dsi_brg_host_ctrl_reg_t; - -/** Type of mem_clk_ctrl register - * dsi_bridge mem force on control register - */ -typedef union { - struct { - /** dsi_bridge_mem_clk_force_on : R/W; bitpos: [0]; default: 0; - * this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: - * force on - */ - uint32_t dsi_bridge_mem_clk_force_on:1; - /** dsi_mem_clk_force_on : R/W; bitpos: [1]; default: 0; - * this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on - */ - uint32_t dsi_mem_clk_force_on:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} dsi_brg_mem_clk_ctrl_reg_t; - -/** Type of dma_flow_ctrl register - * dsi_bridge dma flow controller register - */ -typedef union { - struct { - /** dsi_dma_flow_controller : R/W; bitpos: [0]; default: 1; - * this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge - * as flow controller - */ - uint32_t dsi_dma_flow_controller:1; - uint32_t reserved_1:3; - /** dma_flow_multiblk_num : R/W; bitpos: [7:4]; default: 1; - * this field configures the num of blocks when multi-blk is enable and dmac as flow - * controller - */ - uint32_t dma_flow_multiblk_num:4; - uint32_t reserved_8:24; - }; - uint32_t val; -} dsi_brg_dma_flow_ctrl_reg_t; - -/** Type of raw_buf_almost_empty_thrd register - * dsi_bridge buffer empty threshold register - */ -typedef union { - struct { - /** dsi_raw_buf_almost_empty_thrd : R/W; bitpos: [10:0]; default: 512; - * this field configures the fifo almost empty threshold, is valid only when dmac as - * flow controller - */ - uint32_t dsi_raw_buf_almost_empty_thrd:11; - uint32_t reserved_11:21; - }; - uint32_t val; -} dsi_brg_raw_buf_almost_empty_thrd_reg_t; - -/** Type of yuv_cfg register - * dsi_bridge yuv format config register - */ -typedef union { - struct { - /** protocol : R/W; bitpos: [0]; default: 0; - * this bit configures yuv protoocl, 0: bt.601, 1: bt.709 - */ - uint32_t protocol:1; - /** yuv_pix_endian : R/W; bitpos: [1]; default: 0; - * this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0 - */ - uint32_t yuv_pix_endian:1; - /** yuv422_format : R/W; bitpos: [3:2]; default: 0; - * this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy - */ - uint32_t yuv422_format:2; - /** yuv_range : R/W; bitpos: [4]; default: 0; - * Configures yuv pixel range, 0: limit range, 1: full range - */ - uint32_t yuv_range:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} dsi_brg_yuv_cfg_reg_t; - -/** Type of phy_lp_loopback_ctrl register - * dsi phy lp_loopback test ctrl - */ -typedef union { - struct { - /** phy_lp_txdataesc_1 : R/W; bitpos: [7:0]; default: 0; - * txdataesc_1 ctrl when enable dsi phy lp_loopback_test - */ - uint32_t phy_lp_txdataesc_1:8; - /** phy_lp_txrequestesc_1 : R/W; bitpos: [8]; default: 0; - * txrequestesc_1 ctrl when enable dsi phy lp_loopback_test - */ - uint32_t phy_lp_txrequestesc_1:1; - /** phy_lp_txvalidesc_1 : R/W; bitpos: [9]; default: 0; - * txvalidesc_1 ctrl when enable dsi phy lp_loopback_test - */ - uint32_t phy_lp_txvalidesc_1:1; - /** phy_lp_txlpdtesc_1 : R/W; bitpos: [10]; default: 0; - * txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test - */ - uint32_t phy_lp_txlpdtesc_1:1; - /** phy_lp_basedir_1 : R/W; bitpos: [11]; default: 0; - * basedir_1 ctrl when enable dsi phy lp_loopback_test - */ - uint32_t phy_lp_basedir_1:1; - uint32_t reserved_12:4; - /** phy_lp_txdataesc_0 : R/W; bitpos: [23:16]; default: 0; - * txdataesc_0 ctrl when enable dsi phy lp_loopback_test - */ - uint32_t phy_lp_txdataesc_0:8; - /** phy_lp_txrequestesc_0 : R/W; bitpos: [24]; default: 0; - * txrequestesc_0 ctrl when enable dsi phy lp_loopback_test - */ - uint32_t phy_lp_txrequestesc_0:1; - /** phy_lp_txvalidesc_0 : R/W; bitpos: [25]; default: 0; - * txvalidesc_0 ctrl when enable dsi phy lp_loopback_test - */ - uint32_t phy_lp_txvalidesc_0:1; - /** phy_lp_txlpdtesc_0 : R/W; bitpos: [26]; default: 0; - * txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test - */ - uint32_t phy_lp_txlpdtesc_0:1; - /** phy_lp_basedir_0 : R/W; bitpos: [27]; default: 0; - * basedir_0 ctrl when enable dsi phy lp_loopback_test - */ - uint32_t phy_lp_basedir_0:1; - /** phy_lp_loopback_check : WT; bitpos: [28]; default: 0; - * dsi phy lp_loopback test start check - */ - uint32_t phy_lp_loopback_check:1; - /** phy_lp_loopback_check_done : RO; bitpos: [29]; default: 0; - * dsi phy lp_loopback test check done - */ - uint32_t phy_lp_loopback_check_done:1; - /** phy_lp_loopback_en : R/W; bitpos: [30]; default: 0; - * dsi phy lp_loopback ctrl en - */ - uint32_t phy_lp_loopback_en:1; - /** phy_lp_loopback_ok : RO; bitpos: [31]; default: 0; - * result of dsi phy lp_loopback test - */ - uint32_t phy_lp_loopback_ok:1; - }; - uint32_t val; -} dsi_brg_phy_lp_loopback_ctrl_reg_t; - -/** Type of phy_hs_loopback_ctrl register - * dsi phy hp_loopback test ctrl - */ -typedef union { - struct { - /** phy_hs_txdatahs_1 : R/W; bitpos: [7:0]; default: 0; - * txdatahs_1 ctrl when enable dsi phy hs_loopback_test - */ - uint32_t phy_hs_txdatahs_1:8; - /** phy_hs_txrequestdatahs_1 : R/W; bitpos: [8]; default: 0; - * txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test - */ - uint32_t phy_hs_txrequestdatahs_1:1; - /** phy_hs_basedir_1 : R/W; bitpos: [9]; default: 1; - * basedir_1 ctrl when enable dsi phy hs_loopback_test - */ - uint32_t phy_hs_basedir_1:1; - uint32_t reserved_10:6; - /** phy_hs_txdatahs_0 : R/W; bitpos: [23:16]; default: 0; - * txdatahs_0 ctrl when enable dsi phy hs_loopback_test - */ - uint32_t phy_hs_txdatahs_0:8; - /** phy_hs_txrequestdatahs_0 : R/W; bitpos: [24]; default: 0; - * txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test - */ - uint32_t phy_hs_txrequestdatahs_0:1; - /** phy_hs_basedir_0 : R/W; bitpos: [25]; default: 0; - * basedir_0 ctrl when enable dsi phy hs_loopback_test - */ - uint32_t phy_hs_basedir_0:1; - uint32_t reserved_26:1; - /** phy_hs_txrequesthsclk : R/W; bitpos: [27]; default: 0; - * txrequesthsclk when enable dsi phy hs_loopback_test - */ - uint32_t phy_hs_txrequesthsclk:1; - /** phy_hs_loopback_check : WT; bitpos: [28]; default: 0; - * dsi phy hs_loopback test start check - */ - uint32_t phy_hs_loopback_check:1; - /** phy_hs_loopback_check_done : RO; bitpos: [29]; default: 0; - * dsi phy hs_loopback test check done - */ - uint32_t phy_hs_loopback_check_done:1; - /** phy_hs_loopback_en : R/W; bitpos: [30]; default: 0; - * dsi phy hs_loopback ctrl en - */ - uint32_t phy_hs_loopback_en:1; - /** phy_hs_loopback_ok : RO; bitpos: [31]; default: 0; - * result of dsi phy hs_loopback test - */ - uint32_t phy_hs_loopback_ok:1; - }; - uint32_t val; -} dsi_brg_phy_hs_loopback_ctrl_reg_t; - -/** Type of phy_loopback_cnt register - * loopback test cnt - */ -typedef union { - struct { - /** phy_hs_check_cnt_th : R/W; bitpos: [7:0]; default: 64; - * hs_loopback test check cnt - */ - uint32_t phy_hs_check_cnt_th:8; - uint32_t reserved_8:8; - /** phy_lp_check_cnt_th : R/W; bitpos: [23:16]; default: 64; - * lp_loopback test check cnt - */ - uint32_t phy_lp_check_cnt_th:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} dsi_brg_phy_loopback_cnt_reg_t; - - -/** Group: Status Registers */ -/** Type of fifo_flow_status register - * dsi bridge raw buffer depth register - */ -typedef union { - struct { - /** raw_buf_depth : RO; bitpos: [13:0]; default: 0; - * this field configures the depth of dsi_bridge fifo depth - */ - uint32_t raw_buf_depth:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} dsi_brg_fifo_flow_status_reg_t; - -/** Type of host_bist_ctl register - * dsi_bridge host bist control register - */ -typedef union { - struct { - /** bistok : RO; bitpos: [0]; default: 0; - * bistok - */ - uint32_t bistok:1; - /** biston : R/W; bitpos: [1]; default: 0; - * biston - */ - uint32_t biston:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} dsi_brg_host_bist_ctl_reg_t; - -/** Type of rdn_eco_cs register - * dsi_bridge rdn eco cs register - */ -typedef union { - struct { - /** rdn_eco_en : R/W; bitpos: [0]; default: 0; - * rdn_eco_en - */ - uint32_t rdn_eco_en:1; - /** rdn_eco_result : RO; bitpos: [1]; default: 0; - * rdn_eco_result - */ - uint32_t rdn_eco_result:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} dsi_brg_rdn_eco_cs_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of int_ena register - * dsi_bridge interrupt enable register - */ -typedef union { - struct { - /** underrun_int_ena : R/W; bitpos: [0]; default: 0; - * write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled - * by dpi_underrun interrupt signal - */ - uint32_t underrun_int_ena:1; - /** vsync_int_ena : R/W; bitpos: [1]; default: 0; - * write 1 to enables dpi_vsync_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by - * dpi_vsync interrupt signal - */ - uint32_t vsync_int_ena:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} dsi_brg_int_ena_reg_t; - -/** Type of int_clr register - * dsi_bridge interrupt clear register - */ -typedef union { - struct { - /** underrun_int_clr : WT; bitpos: [0]; default: 0; - * write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG - */ - uint32_t underrun_int_clr:1; - /** vsync_int_clr : WT; bitpos: [1]; default: 0; - * write 1 to this bit to clear dpi_vsync_int_raw field of MIPI_DSI_BRG_INT_RAW_REG - */ - uint32_t vsync_int_clr:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} dsi_brg_int_clr_reg_t; - -/** Type of int_raw register - * dsi_bridge raw interrupt register - */ -typedef union { - struct { - /** underrun_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * the raw interrupt status of dpi_underrun - */ - uint32_t underrun_int_raw:1; - /** vsync_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * the raw interrupt status of dpi_vsync - */ - uint32_t vsync_int_raw:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} dsi_brg_int_raw_reg_t; - -/** Type of int_st register - * dsi_bridge masked interrupt register - */ -typedef union { - struct { - /** underrun_int_st : RO; bitpos: [0]; default: 0; - * the masked interrupt status of dpi_underrun - */ - uint32_t underrun_int_st:1; - /** vsync_int_st : RO; bitpos: [1]; default: 0; - * the masked interrupt status of dpi_vsync - */ - uint32_t vsync_int_st:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} dsi_brg_int_st_reg_t; - - -/** Group: Version Register */ -/** Type of ver_date register - * version control register - */ -typedef union { - struct { - /** ver_data : R/W; bitpos: [31:0]; default: 539296009; - * Represents csv version - */ - uint32_t ver_data:32; - }; - uint32_t val; -} dsi_brg_ver_date_reg_t; - - -typedef struct { - volatile dsi_brg_clk_en_reg_t clk_en; - volatile dsi_brg_en_reg_t en; - volatile dsi_brg_dma_req_cfg_reg_t dma_req_cfg; - volatile dsi_brg_raw_num_cfg_reg_t raw_num_cfg; - volatile dsi_brg_raw_buf_credit_ctl_reg_t raw_buf_credit_ctl; - volatile dsi_brg_fifo_flow_status_reg_t fifo_flow_status; - volatile dsi_brg_pixel_type_reg_t pixel_type; - volatile dsi_brg_dma_block_interval_reg_t dma_block_interval; - volatile dsi_brg_dma_req_interval_reg_t dma_req_interval; - volatile dsi_brg_dpi_lcd_ctl_reg_t dpi_lcd_ctl; - volatile dsi_brg_dpi_rsv_dpi_data_reg_t dpi_rsv_dpi_data; - uint32_t reserved_02c; - volatile dsi_brg_dpi_v_cfg0_reg_t dpi_v_cfg0; - volatile dsi_brg_dpi_v_cfg1_reg_t dpi_v_cfg1; - volatile dsi_brg_dpi_h_cfg0_reg_t dpi_h_cfg0; - volatile dsi_brg_dpi_h_cfg1_reg_t dpi_h_cfg1; - volatile dsi_brg_dpi_misc_config_reg_t dpi_misc_config; - volatile dsi_brg_dpi_config_update_reg_t dpi_config_update; - uint32_t reserved_048[2]; - volatile dsi_brg_int_ena_reg_t int_ena; - volatile dsi_brg_int_clr_reg_t int_clr; - volatile dsi_brg_int_raw_reg_t int_raw; - volatile dsi_brg_int_st_reg_t int_st; - volatile dsi_brg_host_bist_ctl_reg_t host_bist_ctl; - volatile dsi_brg_host_trigger_rev_reg_t host_trigger_rev; - volatile dsi_brg_blk_raw_num_cfg_reg_t blk_raw_num_cfg; - volatile dsi_brg_dma_frame_interval_reg_t dma_frame_interval; - volatile dsi_brg_mem_aux_ctrl_reg_t mem_aux_ctrl; - volatile dsi_brg_rdn_eco_cs_reg_t rdn_eco_cs; - volatile dsi_brg_rdn_eco_low_reg_t rdn_eco_low; - volatile dsi_brg_rdn_eco_high_reg_t rdn_eco_high; - volatile dsi_brg_host_ctrl_reg_t host_ctrl; - volatile dsi_brg_mem_clk_ctrl_reg_t mem_clk_ctrl; - volatile dsi_brg_dma_flow_ctrl_reg_t dma_flow_ctrl; - volatile dsi_brg_raw_buf_almost_empty_thrd_reg_t raw_buf_almost_empty_thrd; - volatile dsi_brg_yuv_cfg_reg_t yuv_cfg; - volatile dsi_brg_phy_lp_loopback_ctrl_reg_t phy_lp_loopback_ctrl; - volatile dsi_brg_phy_hs_loopback_ctrl_reg_t phy_hs_loopback_ctrl; - volatile dsi_brg_phy_loopback_cnt_reg_t phy_loopback_cnt; - uint32_t reserved_0a0[24]; - volatile dsi_brg_ver_date_reg_t ver_date; -} dsi_brg_dev_t; - -extern dsi_brg_dev_t MIPI_DSI_BRIDGE; - -#ifndef __cplusplus -_Static_assert(sizeof(dsi_brg_dev_t) == 0x104, "Invalid size of dsi_brg_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_struct.h index 3da6f91b242b..266f441ec65d 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_bridge_struct.h @@ -34,7 +34,11 @@ typedef union { * this bit configures module enable of dsi_bridge. 0: disable, 1: enable */ uint32_t dsi_en:1; - uint32_t reserved_1:31; + /** dsi_brig_rst : R/W; bitpos: [1]; default: 0; + * Configures software reset of dsi_bridge. 0: release reset, 1: reset + */ + uint32_t dsi_brig_rst:1; + uint32_t reserved_2:30; }; uint32_t val; } dsi_brg_en_reg_t; @@ -109,7 +113,8 @@ typedef union { typedef union { struct { /** raw_type : R/W; bitpos: [3:0]; default: 0; - * this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565 + * this field configures the raw pixel type. 0: rgb888, 1:rgb666, 2:rgb565, 8:yuv444, + * 9:yuv422, 10:yuv420, 12:gray */ uint32_t raw_type:4; /** dpi_config : R/W; bitpos: [5:4]; default: 0; @@ -117,10 +122,14 @@ typedef union { */ uint32_t dpi_config:2; /** data_in_type : R/W; bitpos: [6]; default: 0; - * input data type, 0: rgb, 1: yuv + * input data type, 0: not yuv, 1: yuv */ uint32_t data_in_type:1; - uint32_t reserved_7:25; + /** dpi_type : R/W; bitpos: [10:7]; default: 0; + * this field configures the dpi pixel type. 0: rgb888, 1:rgb666, 2:rgb565 + */ + uint32_t dpi_type:4; + uint32_t reserved_11:21; }; uint32_t val; } dsi_brg_pixel_type_reg_t; @@ -198,7 +207,11 @@ typedef union { * this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow */ uint32_t dpi_rsv_data:30; - uint32_t reserved_30:2; + /** dpi_dbg_en : R/W; bitpos: [30]; default: 0; + * Configures data debug feature enable. 0: disable, 1: enable + */ + uint32_t dpi_dbg_en:1; + uint32_t reserved_31:1; }; uint32_t val; } dsi_brg_dpi_rsv_dpi_data_reg_t; @@ -507,7 +520,11 @@ typedef union { * this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy */ uint32_t yuv422_format:2; - uint32_t reserved_4:28; + /** yuv_range : R/W; bitpos: [4]; default: 0; + * Configures yuv pixel range, 0: limit range, 1: full range + */ + uint32_t yuv_range:1; + uint32_t reserved_5:27; }; uint32_t val; } dsi_brg_yuv_cfg_reg_t; @@ -716,7 +733,12 @@ typedef union { * by dpi_underrun interrupt signal */ uint32_t underrun_int_ena:1; - uint32_t reserved_1:31; + /** vsync_int_ena : R/W; bitpos: [1]; default: 0; + * write 1 to enables dpi_vsync_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by + * dpi_vsync interrupt signal + */ + uint32_t vsync_int_ena:1; + uint32_t reserved_2:30; }; uint32_t val; } dsi_brg_int_ena_reg_t; @@ -730,7 +752,11 @@ typedef union { * write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG */ uint32_t underrun_int_clr:1; - uint32_t reserved_1:31; + /** vsync_int_clr : WT; bitpos: [1]; default: 0; + * write 1 to this bit to clear dpi_vsync_int_raw field of MIPI_DSI_BRG_INT_RAW_REG + */ + uint32_t vsync_int_clr:1; + uint32_t reserved_2:30; }; uint32_t val; } dsi_brg_int_clr_reg_t; @@ -744,7 +770,11 @@ typedef union { * the raw interrupt status of dpi_underrun */ uint32_t underrun_int_raw:1; - uint32_t reserved_1:31; + /** vsync_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * the raw interrupt status of dpi_vsync + */ + uint32_t vsync_int_raw:1; + uint32_t reserved_2:30; }; uint32_t val; } dsi_brg_int_raw_reg_t; @@ -758,11 +788,28 @@ typedef union { * the masked interrupt status of dpi_underrun */ uint32_t underrun_int_st:1; - uint32_t reserved_1:31; + /** vsync_int_st : RO; bitpos: [1]; default: 0; + * the masked interrupt status of dpi_vsync + */ + uint32_t vsync_int_st:1; + uint32_t reserved_2:30; }; uint32_t val; } dsi_brg_int_st_reg_t; +/** Group: Version Register */ +/** Type of ver_date register + * version control register + */ +typedef union { + struct { + /** ver_data : R/W; bitpos: [31:0]; default: 539296009; + * Represents csv version + */ + uint32_t ver_data:32; + }; + uint32_t val; +} dsi_brg_ver_date_reg_t; typedef struct dsi_brg_dev_t { volatile dsi_brg_clk_en_reg_t clk_en; @@ -804,15 +851,16 @@ typedef struct dsi_brg_dev_t { volatile dsi_brg_phy_lp_loopback_ctrl_reg_t phy_lp_loopback_ctrl; volatile dsi_brg_phy_hs_loopback_ctrl_reg_t phy_hs_loopback_ctrl; volatile dsi_brg_phy_loopback_cnt_reg_t phy_loopback_cnt; + uint32_t reserved_0a0[24]; + volatile dsi_brg_ver_date_reg_t ver_date; } dsi_brg_dev_t; +extern dsi_brg_dev_t MIPI_DSI_BRIDGE; #ifndef __cplusplus -_Static_assert(sizeof(dsi_brg_dev_t) == 0xa0, "Invalid size of dsi_brg_dev_t structure"); +_Static_assert(sizeof(dsi_brg_dev_t) == 0x104, "Invalid size of dsi_brg_dev_t structure"); #endif -extern dsi_brg_dev_t MIPI_DSI_BRIDGE; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_host_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_host_eco5_struct.h deleted file mode 100644 index 496ea0095f99..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/mipi_dsi_host_eco5_struct.h +++ /dev/null @@ -1,2007 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Version Register */ -/** Type of version register - * NA - */ -typedef union { - struct { - /** version : RO; bitpos: [31:0]; default: 825504042; - * NA - */ - uint32_t version:32; - }; - uint32_t val; -} dsi_host_version_reg_t; - - -/** Group: Configuration Registers */ -/** Type of pwr_up register - * NA - */ -typedef union { - struct { - /** shutdownz : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t shutdownz:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} dsi_host_pwr_up_reg_t; - -/** Type of clkmgr_cfg register - * NA - */ -typedef union { - struct { - /** tx_esc_clk_division : R/W; bitpos: [7:0]; default: 0; - * NA - */ - uint32_t tx_esc_clk_division:8; - /** to_clk_division : R/W; bitpos: [15:8]; default: 0; - * NA - */ - uint32_t to_clk_division:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} dsi_host_clkmgr_cfg_reg_t; - -/** Type of dpi_vcid register - * NA - */ -typedef union { - struct { - /** dpi_vcid : R/W; bitpos: [1:0]; default: 0; - * NA - */ - uint32_t dpi_vcid:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} dsi_host_dpi_vcid_reg_t; - -/** Type of dpi_color_coding register - * NA - */ -typedef union { - struct { - /** dpi_color_coding : R/W; bitpos: [3:0]; default: 0; - * NA - */ - uint32_t dpi_color_coding:4; - uint32_t reserved_4:4; - /** loosely18_en : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t loosely18_en:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} dsi_host_dpi_color_coding_reg_t; - -/** Type of dpi_cfg_pol register - * NA - */ -typedef union { - struct { - /** dataen_active_low : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t dataen_active_low:1; - /** vsync_active_low : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t vsync_active_low:1; - /** hsync_active_low : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t hsync_active_low:1; - /** shutd_active_low : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t shutd_active_low:1; - /** colorm_active_low : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t colorm_active_low:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} dsi_host_dpi_cfg_pol_reg_t; - -/** Type of dpi_lp_cmd_tim register - * NA - */ -typedef union { - struct { - /** invact_lpcmd_time : R/W; bitpos: [7:0]; default: 0; - * NA - */ - uint32_t invact_lpcmd_time:8; - uint32_t reserved_8:8; - /** outvact_lpcmd_time : R/W; bitpos: [23:16]; default: 0; - * NA - */ - uint32_t outvact_lpcmd_time:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} dsi_host_dpi_lp_cmd_tim_reg_t; - -/** Type of dbi_vcid register - * NA - */ -typedef union { - struct { - /** dbi_vcid : R/W; bitpos: [1:0]; default: 0; - * NA - */ - uint32_t dbi_vcid:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} dsi_host_dbi_vcid_reg_t; - -/** Type of dbi_cfg register - * NA - */ -typedef union { - struct { - /** in_dbi_conf : R/W; bitpos: [3:0]; default: 0; - * NA - */ - uint32_t in_dbi_conf:4; - uint32_t reserved_4:4; - /** out_dbi_conf : R/W; bitpos: [11:8]; default: 0; - * NA - */ - uint32_t out_dbi_conf:4; - uint32_t reserved_12:4; - /** lut_size_conf : R/W; bitpos: [17:16]; default: 0; - * NA - */ - uint32_t lut_size_conf:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} dsi_host_dbi_cfg_reg_t; - -/** Type of dbi_partitioning_en register - * NA - */ -typedef union { - struct { - /** partitioning_en : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t partitioning_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} dsi_host_dbi_partitioning_en_reg_t; - -/** Type of dbi_cmdsize register - * NA - */ -typedef union { - struct { - /** wr_cmd_size : R/W; bitpos: [15:0]; default: 0; - * NA - */ - uint32_t wr_cmd_size:16; - /** allowed_cmd_size : R/W; bitpos: [31:16]; default: 0; - * NA - */ - uint32_t allowed_cmd_size:16; - }; - uint32_t val; -} dsi_host_dbi_cmdsize_reg_t; - -/** Type of pckhdl_cfg register - * NA - */ -typedef union { - struct { - /** eotp_tx_en : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t eotp_tx_en:1; - /** eotp_rx_en : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t eotp_rx_en:1; - /** bta_en : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t bta_en:1; - /** ecc_rx_en : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t ecc_rx_en:1; - /** crc_rx_en : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t crc_rx_en:1; - /** eotp_tx_lp_en : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t eotp_tx_lp_en:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} dsi_host_pckhdl_cfg_reg_t; - -/** Type of gen_vcid register - * NA - */ -typedef union { - struct { - /** gen_vcid_rx : R/W; bitpos: [1:0]; default: 0; - * NA - */ - uint32_t gen_vcid_rx:2; - uint32_t reserved_2:6; - /** gen_vcid_tear_auto : R/W; bitpos: [9:8]; default: 0; - * NA - */ - uint32_t gen_vcid_tear_auto:2; - uint32_t reserved_10:6; - /** gen_vcid_tx_auto : R/W; bitpos: [17:16]; default: 0; - * NA - */ - uint32_t gen_vcid_tx_auto:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} dsi_host_gen_vcid_reg_t; - -/** Type of mode_cfg register - * NA - */ -typedef union { - struct { - /** cmd_video_mode : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t cmd_video_mode:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} dsi_host_mode_cfg_reg_t; - -/** Type of vid_mode_cfg register - * NA - */ -typedef union { - struct { - /** vid_mode_type : R/W; bitpos: [1:0]; default: 0; - * NA - */ - uint32_t vid_mode_type:2; - uint32_t reserved_2:6; - /** lp_vsa_en : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t lp_vsa_en:1; - /** lp_vbp_en : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t lp_vbp_en:1; - /** lp_vfp_en : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t lp_vfp_en:1; - /** lp_vact_en : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t lp_vact_en:1; - /** lp_hbp_en : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t lp_hbp_en:1; - /** lp_hfp_en : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t lp_hfp_en:1; - /** frame_bta_ack_en : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t frame_bta_ack_en:1; - /** lp_cmd_en : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t lp_cmd_en:1; - /** vpg_en : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t vpg_en:1; - uint32_t reserved_17:3; - /** vpg_mode : R/W; bitpos: [20]; default: 0; - * NA - */ - uint32_t vpg_mode:1; - uint32_t reserved_21:3; - /** vpg_orientation : R/W; bitpos: [24]; default: 0; - * NA - */ - uint32_t vpg_orientation:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} dsi_host_vid_mode_cfg_reg_t; - -/** Type of vid_pkt_size register - * NA - */ -typedef union { - struct { - /** vid_pkt_size : R/W; bitpos: [13:0]; default: 0; - * NA - */ - uint32_t vid_pkt_size:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} dsi_host_vid_pkt_size_reg_t; - -/** Type of vid_num_chunks register - * NA - */ -typedef union { - struct { - /** vid_num_chunks : R/W; bitpos: [12:0]; default: 0; - * NA - */ - uint32_t vid_num_chunks:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} dsi_host_vid_num_chunks_reg_t; - -/** Type of vid_null_size register - * NA - */ -typedef union { - struct { - /** vid_null_size : R/W; bitpos: [12:0]; default: 0; - * NA - */ - uint32_t vid_null_size:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} dsi_host_vid_null_size_reg_t; - -/** Type of vid_hsa_time register - * NA - */ -typedef union { - struct { - /** vid_hsa_time : R/W; bitpos: [11:0]; default: 0; - * NA - */ - uint32_t vid_hsa_time:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} dsi_host_vid_hsa_time_reg_t; - -/** Type of vid_hbp_time register - * NA - */ -typedef union { - struct { - /** vid_hbp_time : R/W; bitpos: [11:0]; default: 0; - * NA - */ - uint32_t vid_hbp_time:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} dsi_host_vid_hbp_time_reg_t; - -/** Type of vid_hline_time register - * NA - */ -typedef union { - struct { - /** vid_hline_time : R/W; bitpos: [14:0]; default: 0; - * NA - */ - uint32_t vid_hline_time:15; - uint32_t reserved_15:17; - }; - uint32_t val; -} dsi_host_vid_hline_time_reg_t; - -/** Type of vid_vsa_lines register - * NA - */ -typedef union { - struct { - /** vsa_lines : R/W; bitpos: [9:0]; default: 0; - * NA - */ - uint32_t vsa_lines:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} dsi_host_vid_vsa_lines_reg_t; - -/** Type of vid_vbp_lines register - * NA - */ -typedef union { - struct { - /** vbp_lines : R/W; bitpos: [9:0]; default: 0; - * NA - */ - uint32_t vbp_lines:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} dsi_host_vid_vbp_lines_reg_t; - -/** Type of vid_vfp_lines register - * NA - */ -typedef union { - struct { - /** vfp_lines : R/W; bitpos: [9:0]; default: 0; - * NA - */ - uint32_t vfp_lines:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} dsi_host_vid_vfp_lines_reg_t; - -/** Type of vid_vactive_lines register - * NA - */ -typedef union { - struct { - /** v_active_lines : R/W; bitpos: [13:0]; default: 0; - * NA - */ - uint32_t v_active_lines:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} dsi_host_vid_vactive_lines_reg_t; - -/** Type of edpi_cmd_size register - * NA - */ -typedef union { - struct { - /** edpi_allowed_cmd_size : R/W; bitpos: [15:0]; default: 0; - * NA - */ - uint32_t edpi_allowed_cmd_size:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} dsi_host_edpi_cmd_size_reg_t; - -/** Type of cmd_mode_cfg register - * NA - */ -typedef union { - struct { - /** tear_fx_en : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t tear_fx_en:1; - /** ack_rqst_en : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t ack_rqst_en:1; - uint32_t reserved_2:6; - /** gen_sw_0p_tx : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t gen_sw_0p_tx:1; - /** gen_sw_1p_tx : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t gen_sw_1p_tx:1; - /** gen_sw_2p_tx : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t gen_sw_2p_tx:1; - /** gen_sr_0p_tx : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t gen_sr_0p_tx:1; - /** gen_sr_1p_tx : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t gen_sr_1p_tx:1; - /** gen_sr_2p_tx : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t gen_sr_2p_tx:1; - /** gen_lw_tx : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t gen_lw_tx:1; - uint32_t reserved_15:1; - /** dcs_sw_0p_tx : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t dcs_sw_0p_tx:1; - /** dcs_sw_1p_tx : R/W; bitpos: [17]; default: 0; - * NA - */ - uint32_t dcs_sw_1p_tx:1; - /** dcs_sr_0p_tx : R/W; bitpos: [18]; default: 0; - * NA - */ - uint32_t dcs_sr_0p_tx:1; - /** dcs_lw_tx : R/W; bitpos: [19]; default: 0; - * NA - */ - uint32_t dcs_lw_tx:1; - uint32_t reserved_20:4; - /** max_rd_pkt_size : R/W; bitpos: [24]; default: 0; - * NA - */ - uint32_t max_rd_pkt_size:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} dsi_host_cmd_mode_cfg_reg_t; - -/** Type of gen_hdr register - * NA - */ -typedef union { - struct { - /** gen_dt : R/W; bitpos: [5:0]; default: 0; - * NA - */ - uint32_t gen_dt:6; - /** gen_vc : R/W; bitpos: [7:6]; default: 0; - * NA - */ - uint32_t gen_vc:2; - /** gen_wc_lsbyte : R/W; bitpos: [15:8]; default: 0; - * NA - */ - uint32_t gen_wc_lsbyte:8; - /** gen_wc_msbyte : R/W; bitpos: [23:16]; default: 0; - * NA - */ - uint32_t gen_wc_msbyte:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} dsi_host_gen_hdr_reg_t; - -/** Type of gen_pld_data register - * NA - */ -typedef union { - struct { - /** gen_pld_b1 : R/W; bitpos: [7:0]; default: 0; - * NA - */ - uint32_t gen_pld_b1:8; - /** gen_pld_b2 : R/W; bitpos: [15:8]; default: 0; - * NA - */ - uint32_t gen_pld_b2:8; - /** gen_pld_b3 : R/W; bitpos: [23:16]; default: 0; - * NA - */ - uint32_t gen_pld_b3:8; - /** gen_pld_b4 : R/W; bitpos: [31:24]; default: 0; - * NA - */ - uint32_t gen_pld_b4:8; - }; - uint32_t val; -} dsi_host_gen_pld_data_reg_t; - -/** Type of to_cnt_cfg register - * NA - */ -typedef union { - struct { - /** lprx_to_cnt : R/W; bitpos: [15:0]; default: 0; - * NA - */ - uint32_t lprx_to_cnt:16; - /** hstx_to_cnt : R/W; bitpos: [31:16]; default: 0; - * NA - */ - uint32_t hstx_to_cnt:16; - }; - uint32_t val; -} dsi_host_to_cnt_cfg_reg_t; - -/** Type of hs_rd_to_cnt register - * NA - */ -typedef union { - struct { - /** hs_rd_to_cnt : R/W; bitpos: [15:0]; default: 0; - * NA - */ - uint32_t hs_rd_to_cnt:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} dsi_host_hs_rd_to_cnt_reg_t; - -/** Type of lp_rd_to_cnt register - * NA - */ -typedef union { - struct { - /** lp_rd_to_cnt : R/W; bitpos: [15:0]; default: 0; - * NA - */ - uint32_t lp_rd_to_cnt:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} dsi_host_lp_rd_to_cnt_reg_t; - -/** Type of hs_wr_to_cnt register - * NA - */ -typedef union { - struct { - /** hs_wr_to_cnt : R/W; bitpos: [15:0]; default: 0; - * NA - */ - uint32_t hs_wr_to_cnt:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} dsi_host_hs_wr_to_cnt_reg_t; - -/** Type of lp_wr_to_cnt register - * NA - */ -typedef union { - struct { - /** lp_wr_to_cnt : R/W; bitpos: [15:0]; default: 0; - * NA - */ - uint32_t lp_wr_to_cnt:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} dsi_host_lp_wr_to_cnt_reg_t; - -/** Type of bta_to_cnt register - * NA - */ -typedef union { - struct { - /** bta_to_cnt : R/W; bitpos: [15:0]; default: 0; - * NA - */ - uint32_t bta_to_cnt:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} dsi_host_bta_to_cnt_reg_t; - -/** Type of sdf_3d register - * NA - */ -typedef union { - struct { - /** mode_3d : R/W; bitpos: [1:0]; default: 0; - * NA - */ - uint32_t mode_3d:2; - /** format_3d : R/W; bitpos: [3:2]; default: 0; - * NA - */ - uint32_t format_3d:2; - /** second_vsync : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t second_vsync:1; - /** right_first : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t right_first:1; - uint32_t reserved_6:10; - /** send_3d_cfg : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t send_3d_cfg:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} dsi_host_sdf_3d_reg_t; - -/** Type of lpclk_ctrl register - * NA - */ -typedef union { - struct { - /** phy_txrequestclkhs : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t phy_txrequestclkhs:1; - /** auto_clklane_ctrl : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t auto_clklane_ctrl:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} dsi_host_lpclk_ctrl_reg_t; - -/** Type of phy_tmr_lpclk_cfg register - * NA - */ -typedef union { - struct { - /** phy_clklp2hs_time : R/W; bitpos: [9:0]; default: 0; - * NA - */ - uint32_t phy_clklp2hs_time:10; - uint32_t reserved_10:6; - /** phy_clkhs2lp_time : R/W; bitpos: [25:16]; default: 0; - * NA - */ - uint32_t phy_clkhs2lp_time:10; - uint32_t reserved_26:6; - }; - uint32_t val; -} dsi_host_phy_tmr_lpclk_cfg_reg_t; - -/** Type of phy_tmr_cfg register - * NA - */ -typedef union { - struct { - /** phy_lp2hs_time : R/W; bitpos: [9:0]; default: 0; - * NA - */ - uint32_t phy_lp2hs_time:10; - uint32_t reserved_10:6; - /** phy_hs2lp_time : R/W; bitpos: [25:16]; default: 0; - * NA - */ - uint32_t phy_hs2lp_time:10; - uint32_t reserved_26:6; - }; - uint32_t val; -} dsi_host_phy_tmr_cfg_reg_t; - -/** Type of phy_rstz register - * NA - */ -typedef union { - struct { - /** phy_shutdownz : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t phy_shutdownz:1; - /** phy_rstz : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t phy_rstz:1; - /** phy_enableclk : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t phy_enableclk:1; - /** phy_forcepll : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t phy_forcepll:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dsi_host_phy_rstz_reg_t; - -/** Type of phy_if_cfg register - * NA - */ -typedef union { - struct { - /** n_lanes : R/W; bitpos: [1:0]; default: 1; - * NA - */ - uint32_t n_lanes:2; - uint32_t reserved_2:6; - /** phy_stop_wait_time : R/W; bitpos: [15:8]; default: 0; - * NA - */ - uint32_t phy_stop_wait_time:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} dsi_host_phy_if_cfg_reg_t; - -/** Type of phy_ulps_ctrl register - * NA - */ -typedef union { - struct { - /** phy_txrequlpsclk : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t phy_txrequlpsclk:1; - /** phy_txexitulpsclk : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t phy_txexitulpsclk:1; - /** phy_txrequlpslan : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t phy_txrequlpslan:1; - /** phy_txexitulpslan : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t phy_txexitulpslan:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} dsi_host_phy_ulps_ctrl_reg_t; - -/** Type of phy_tx_triggers register - * NA - */ -typedef union { - struct { - /** phy_tx_triggers : R/W; bitpos: [3:0]; default: 0; - * NA - */ - uint32_t phy_tx_triggers:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} dsi_host_phy_tx_triggers_reg_t; - -/** Type of phy_tst_ctrl0 register - * NA - */ -typedef union { - struct { - /** phy_testclr : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t phy_testclr:1; - /** phy_testclk : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t phy_testclk:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} dsi_host_phy_tst_ctrl0_reg_t; - -/** Type of phy_tst_ctrl1 register - * NA - */ -typedef union { - struct { - /** phy_testdin : R/W; bitpos: [7:0]; default: 0; - * NA - */ - uint32_t phy_testdin:8; - /** pht_testdout : RO; bitpos: [15:8]; default: 0; - * NA - */ - uint32_t pht_testdout:8; - /** phy_testen : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t phy_testen:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} dsi_host_phy_tst_ctrl1_reg_t; - -/** Type of phy_cal register - * NA - */ -typedef union { - struct { - /** txskewcalhs : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t txskewcalhs:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} dsi_host_phy_cal_reg_t; - -/** Type of dsc_parameter register - * NA - */ -typedef union { - struct { - /** compression_mode : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t compression_mode:1; - uint32_t reserved_1:7; - /** compress_algo : R/W; bitpos: [9:8]; default: 0; - * NA - */ - uint32_t compress_algo:2; - uint32_t reserved_10:6; - /** pps_sel : R/W; bitpos: [17:16]; default: 0; - * NA - */ - uint32_t pps_sel:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} dsi_host_dsc_parameter_reg_t; - -/** Type of phy_tmr_rd_cfg register - * NA - */ -typedef union { - struct { - /** max_rd_time : R/W; bitpos: [14:0]; default: 0; - * NA - */ - uint32_t max_rd_time:15; - uint32_t reserved_15:17; - }; - uint32_t val; -} dsi_host_phy_tmr_rd_cfg_reg_t; - -/** Type of vid_shadow_ctrl register - * NA - */ -typedef union { - struct { - /** vid_shadow_en : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t vid_shadow_en:1; - uint32_t reserved_1:7; - /** vid_shadow_req : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t vid_shadow_req:1; - uint32_t reserved_9:7; - /** vid_shadow_pin_req : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t vid_shadow_pin_req:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} dsi_host_vid_shadow_ctrl_reg_t; - -/** Type of edpi_te_hw_cfg register - * NA - */ -typedef union { - struct { - /** hw_tear_effect_on : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t hw_tear_effect_on:1; - /** hw_tear_effect_gen : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t hw_tear_effect_gen:1; - uint32_t reserved_2:2; - /** hw_set_scan_line : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t hw_set_scan_line:1; - uint32_t reserved_5:11; - /** scan_line_parameter : R/W; bitpos: [31:16]; default: 0; - * NA - */ - uint32_t scan_line_parameter:16; - }; - uint32_t val; -} dsi_host_edpi_te_hw_cfg_reg_t; - - -/** Group: Status Registers */ -/** Type of cmd_pkt_status register - * NA - */ -typedef union { - struct { - /** gen_cmd_empty : RO; bitpos: [0]; default: 1; - * NA - */ - uint32_t gen_cmd_empty:1; - /** gen_cmd_full : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t gen_cmd_full:1; - /** gen_pld_w_empty : RO; bitpos: [2]; default: 1; - * NA - */ - uint32_t gen_pld_w_empty:1; - /** gen_pld_w_full : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t gen_pld_w_full:1; - /** gen_pld_r_empty : RO; bitpos: [4]; default: 1; - * NA - */ - uint32_t gen_pld_r_empty:1; - /** gen_pld_r_full : RO; bitpos: [5]; default: 0; - * NA - */ - uint32_t gen_pld_r_full:1; - /** gen_rd_cmd_busy : RO; bitpos: [6]; default: 0; - * NA - */ - uint32_t gen_rd_cmd_busy:1; - uint32_t reserved_7:9; - /** gen_buff_cmd_empty : RO; bitpos: [16]; default: 1; - * NA - */ - uint32_t gen_buff_cmd_empty:1; - /** gen_buff_cmd_full : RO; bitpos: [17]; default: 0; - * NA - */ - uint32_t gen_buff_cmd_full:1; - /** gen_buff_pld_empty : RO; bitpos: [18]; default: 1; - * NA - */ - uint32_t gen_buff_pld_empty:1; - /** gen_buff_pld_full : RO; bitpos: [19]; default: 0; - * NA - */ - uint32_t gen_buff_pld_full:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} dsi_host_cmd_pkt_status_reg_t; - -/** Type of phy_status register - * NA - */ -typedef union { - struct { - /** phy_lock : RO; bitpos: [0]; default: 0; - * NA - */ - uint32_t phy_lock:1; - /** phy_direction : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t phy_direction:1; - /** phy_stopstateclklane : RO; bitpos: [2]; default: 0; - * NA - */ - uint32_t phy_stopstateclklane:1; - /** phy_ulpsactivenotclk : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t phy_ulpsactivenotclk:1; - /** phy_stopstate0lane : RO; bitpos: [4]; default: 0; - * NA - */ - uint32_t phy_stopstate0lane:1; - /** phy_ulpsactivenot0lane : RO; bitpos: [5]; default: 0; - * NA - */ - uint32_t phy_ulpsactivenot0lane:1; - /** phy_rxulpsesc0lane : RO; bitpos: [6]; default: 1; - * NA - */ - uint32_t phy_rxulpsesc0lane:1; - /** phy_stopstate1lane : RO; bitpos: [7]; default: 0; - * NA - */ - uint32_t phy_stopstate1lane:1; - /** phy_ulpsactivenot1lane : RO; bitpos: [8]; default: 1; - * NA - */ - uint32_t phy_ulpsactivenot1lane:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} dsi_host_phy_status_reg_t; - -/** Type of dpi_vcid_act register - * NA - */ -typedef union { - struct { - /** dpi_vcid_act : RO; bitpos: [1:0]; default: 0; - * NA - */ - uint32_t dpi_vcid_act:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} dsi_host_dpi_vcid_act_reg_t; - -/** Type of dpi_color_coding_act register - * NA - */ -typedef union { - struct { - /** dpi_color_coding_act : RO; bitpos: [3:0]; default: 0; - * NA - */ - uint32_t dpi_color_coding_act:4; - uint32_t reserved_4:4; - /** loosely18_en_act : RO; bitpos: [8]; default: 0; - * NA - */ - uint32_t loosely18_en_act:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} dsi_host_dpi_color_coding_act_reg_t; - -/** Type of dpi_lp_cmd_tim_act register - * NA - */ -typedef union { - struct { - /** invact_lpcmd_time_act : RO; bitpos: [7:0]; default: 0; - * NA - */ - uint32_t invact_lpcmd_time_act:8; - uint32_t reserved_8:8; - /** outvact_lpcmd_time_act : RO; bitpos: [23:16]; default: 0; - * NA - */ - uint32_t outvact_lpcmd_time_act:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} dsi_host_dpi_lp_cmd_tim_act_reg_t; - -/** Type of vid_mode_cfg_act register - * NA - */ -typedef union { - struct { - /** vid_mode_type_act : RO; bitpos: [1:0]; default: 0; - * NA - */ - uint32_t vid_mode_type_act:2; - /** lp_vsa_en_act : RO; bitpos: [2]; default: 0; - * NA - */ - uint32_t lp_vsa_en_act:1; - /** lp_vbp_en_act : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t lp_vbp_en_act:1; - /** lp_vfp_en_act : RO; bitpos: [4]; default: 0; - * NA - */ - uint32_t lp_vfp_en_act:1; - /** lp_vact_en_act : RO; bitpos: [5]; default: 0; - * NA - */ - uint32_t lp_vact_en_act:1; - /** lp_hbp_en_act : RO; bitpos: [6]; default: 0; - * NA - */ - uint32_t lp_hbp_en_act:1; - /** lp_hfp_en_act : RO; bitpos: [7]; default: 0; - * NA - */ - uint32_t lp_hfp_en_act:1; - /** frame_bta_ack_en_act : RO; bitpos: [8]; default: 0; - * NA - */ - uint32_t frame_bta_ack_en_act:1; - /** lp_cmd_en_act : RO; bitpos: [9]; default: 0; - * NA - */ - uint32_t lp_cmd_en_act:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} dsi_host_vid_mode_cfg_act_reg_t; - -/** Type of vid_pkt_size_act register - * NA - */ -typedef union { - struct { - /** vid_pkt_size_act : RO; bitpos: [13:0]; default: 0; - * NA - */ - uint32_t vid_pkt_size_act:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} dsi_host_vid_pkt_size_act_reg_t; - -/** Type of vid_num_chunks_act register - * NA - */ -typedef union { - struct { - /** vid_num_chunks_act : RO; bitpos: [12:0]; default: 0; - * NA - */ - uint32_t vid_num_chunks_act:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} dsi_host_vid_num_chunks_act_reg_t; - -/** Type of vid_null_size_act register - * NA - */ -typedef union { - struct { - /** vid_null_size_act : RO; bitpos: [12:0]; default: 0; - * NA - */ - uint32_t vid_null_size_act:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} dsi_host_vid_null_size_act_reg_t; - -/** Type of vid_hsa_time_act register - * NA - */ -typedef union { - struct { - /** vid_hsa_time_act : RO; bitpos: [11:0]; default: 0; - * NA - */ - uint32_t vid_hsa_time_act:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} dsi_host_vid_hsa_time_act_reg_t; - -/** Type of vid_hbp_time_act register - * NA - */ -typedef union { - struct { - /** vid_hbp_time_act : RO; bitpos: [11:0]; default: 0; - * NA - */ - uint32_t vid_hbp_time_act:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} dsi_host_vid_hbp_time_act_reg_t; - -/** Type of vid_hline_time_act register - * NA - */ -typedef union { - struct { - /** vid_hline_time_act : RO; bitpos: [14:0]; default: 0; - * NA - */ - uint32_t vid_hline_time_act:15; - uint32_t reserved_15:17; - }; - uint32_t val; -} dsi_host_vid_hline_time_act_reg_t; - -/** Type of vid_vsa_lines_act register - * NA - */ -typedef union { - struct { - /** vsa_lines_act : RO; bitpos: [9:0]; default: 0; - * NA - */ - uint32_t vsa_lines_act:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} dsi_host_vid_vsa_lines_act_reg_t; - -/** Type of vid_vbp_lines_act register - * NA - */ -typedef union { - struct { - /** vbp_lines_act : RO; bitpos: [9:0]; default: 0; - * NA - */ - uint32_t vbp_lines_act:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} dsi_host_vid_vbp_lines_act_reg_t; - -/** Type of vid_vfp_lines_act register - * NA - */ -typedef union { - struct { - /** vfp_lines_act : RO; bitpos: [9:0]; default: 0; - * NA - */ - uint32_t vfp_lines_act:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} dsi_host_vid_vfp_lines_act_reg_t; - -/** Type of vid_vactive_lines_act register - * NA - */ -typedef union { - struct { - /** v_active_lines_act : RO; bitpos: [13:0]; default: 0; - * NA - */ - uint32_t v_active_lines_act:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} dsi_host_vid_vactive_lines_act_reg_t; - -/** Type of vid_pkt_status register - * NA - */ -typedef union { - struct { - /** dpi_cmd_w_empty : RO; bitpos: [0]; default: 1; - * NA - */ - uint32_t dpi_cmd_w_empty:1; - /** dpi_cmd_w_full : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t dpi_cmd_w_full:1; - /** dpi_pld_w_empty : RO; bitpos: [2]; default: 1; - * NA - */ - uint32_t dpi_pld_w_empty:1; - /** dpi_pld_w_full : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t dpi_pld_w_full:1; - uint32_t reserved_4:12; - /** dpi_buff_pld_empty : RO; bitpos: [16]; default: 1; - * NA - */ - uint32_t dpi_buff_pld_empty:1; - /** dpi_buff_pld_full : RO; bitpos: [17]; default: 0; - * NA - */ - uint32_t dpi_buff_pld_full:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} dsi_host_vid_pkt_status_reg_t; - -/** Type of sdf_3d_act register - * NA - */ -typedef union { - struct { - /** mode_3d_act : RO; bitpos: [1:0]; default: 0; - * NA - */ - uint32_t mode_3d_act:2; - /** format_3d_act : RO; bitpos: [3:2]; default: 0; - * NA - */ - uint32_t format_3d_act:2; - /** second_vsync_act : RO; bitpos: [4]; default: 0; - * NA - */ - uint32_t second_vsync_act:1; - /** right_first_act : RO; bitpos: [5]; default: 0; - * NA - */ - uint32_t right_first_act:1; - uint32_t reserved_6:10; - /** send_3d_cfg_act : RO; bitpos: [16]; default: 0; - * NA - */ - uint32_t send_3d_cfg_act:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} dsi_host_sdf_3d_act_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of int_st0 register - * NA - */ -typedef union { - struct { - /** ack_with_err_0 : RO; bitpos: [0]; default: 0; - * NA - */ - uint32_t ack_with_err_0:1; - /** ack_with_err_1 : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t ack_with_err_1:1; - /** ack_with_err_2 : RO; bitpos: [2]; default: 0; - * NA - */ - uint32_t ack_with_err_2:1; - /** ack_with_err_3 : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ack_with_err_3:1; - /** ack_with_err_4 : RO; bitpos: [4]; default: 0; - * NA - */ - uint32_t ack_with_err_4:1; - /** ack_with_err_5 : RO; bitpos: [5]; default: 0; - * NA - */ - uint32_t ack_with_err_5:1; - /** ack_with_err_6 : RO; bitpos: [6]; default: 0; - * NA - */ - uint32_t ack_with_err_6:1; - /** ack_with_err_7 : RO; bitpos: [7]; default: 0; - * NA - */ - uint32_t ack_with_err_7:1; - /** ack_with_err_8 : RO; bitpos: [8]; default: 0; - * NA - */ - uint32_t ack_with_err_8:1; - /** ack_with_err_9 : RO; bitpos: [9]; default: 0; - * NA - */ - uint32_t ack_with_err_9:1; - /** ack_with_err_10 : RO; bitpos: [10]; default: 0; - * NA - */ - uint32_t ack_with_err_10:1; - /** ack_with_err_11 : RO; bitpos: [11]; default: 0; - * NA - */ - uint32_t ack_with_err_11:1; - /** ack_with_err_12 : RO; bitpos: [12]; default: 0; - * NA - */ - uint32_t ack_with_err_12:1; - /** ack_with_err_13 : RO; bitpos: [13]; default: 0; - * NA - */ - uint32_t ack_with_err_13:1; - /** ack_with_err_14 : RO; bitpos: [14]; default: 0; - * NA - */ - uint32_t ack_with_err_14:1; - /** ack_with_err_15 : RO; bitpos: [15]; default: 0; - * NA - */ - uint32_t ack_with_err_15:1; - /** dphy_errors_0 : RO; bitpos: [16]; default: 0; - * NA - */ - uint32_t dphy_errors_0:1; - /** dphy_errors_1 : RO; bitpos: [17]; default: 0; - * NA - */ - uint32_t dphy_errors_1:1; - /** dphy_errors_2 : RO; bitpos: [18]; default: 0; - * NA - */ - uint32_t dphy_errors_2:1; - /** dphy_errors_3 : RO; bitpos: [19]; default: 0; - * NA - */ - uint32_t dphy_errors_3:1; - /** dphy_errors_4 : RO; bitpos: [20]; default: 0; - * NA - */ - uint32_t dphy_errors_4:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} dsi_host_int_st0_reg_t; - -/** Type of int_st1 register - * NA - */ -typedef union { - struct { - /** to_hs_tx : RO; bitpos: [0]; default: 0; - * NA - */ - uint32_t to_hs_tx:1; - /** to_lp_rx : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t to_lp_rx:1; - /** ecc_single_err : RO; bitpos: [2]; default: 0; - * NA - */ - uint32_t ecc_single_err:1; - /** ecc_milti_err : RO; bitpos: [3]; default: 0; - * NA - */ - uint32_t ecc_milti_err:1; - /** crc_err : RO; bitpos: [4]; default: 0; - * NA - */ - uint32_t crc_err:1; - /** pkt_size_err : RO; bitpos: [5]; default: 0; - * NA - */ - uint32_t pkt_size_err:1; - /** eopt_err : RO; bitpos: [6]; default: 0; - * NA - */ - uint32_t eopt_err:1; - /** dpi_pld_wr_err : RO; bitpos: [7]; default: 0; - * NA - */ - uint32_t dpi_pld_wr_err:1; - /** gen_cmd_wr_err : RO; bitpos: [8]; default: 0; - * NA - */ - uint32_t gen_cmd_wr_err:1; - /** gen_pld_wr_err : RO; bitpos: [9]; default: 0; - * NA - */ - uint32_t gen_pld_wr_err:1; - /** gen_pld_send_err : RO; bitpos: [10]; default: 0; - * NA - */ - uint32_t gen_pld_send_err:1; - /** gen_pld_rd_err : RO; bitpos: [11]; default: 0; - * NA - */ - uint32_t gen_pld_rd_err:1; - /** gen_pld_recev_err : RO; bitpos: [12]; default: 0; - * NA - */ - uint32_t gen_pld_recev_err:1; - uint32_t reserved_13:6; - /** dpi_buff_pld_under : RO; bitpos: [19]; default: 0; - * NA - */ - uint32_t dpi_buff_pld_under:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} dsi_host_int_st1_reg_t; - -/** Type of int_msk0 register - * NA - */ -typedef union { - struct { - /** mask_ack_with_err_0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_0:1; - /** mask_ack_with_err_1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_1:1; - /** mask_ack_with_err_2 : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_2:1; - /** mask_ack_with_err_3 : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_3:1; - /** mask_ack_with_err_4 : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_4:1; - /** mask_ack_with_err_5 : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_5:1; - /** mask_ack_with_err_6 : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_6:1; - /** mask_ack_with_err_7 : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_7:1; - /** mask_ack_with_err_8 : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_8:1; - /** mask_ack_with_err_9 : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_9:1; - /** mask_ack_with_err_10 : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_10:1; - /** mask_ack_with_err_11 : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_11:1; - /** mask_ack_with_err_12 : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_12:1; - /** mask_ack_with_err_13 : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_13:1; - /** mask_ack_with_err_14 : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_14:1; - /** mask_ack_with_err_15 : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t mask_ack_with_err_15:1; - /** mask_dphy_errors_0 : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t mask_dphy_errors_0:1; - /** mask_dphy_errors_1 : R/W; bitpos: [17]; default: 0; - * NA - */ - uint32_t mask_dphy_errors_1:1; - /** mask_dphy_errors_2 : R/W; bitpos: [18]; default: 0; - * NA - */ - uint32_t mask_dphy_errors_2:1; - /** mask_dphy_errors_3 : R/W; bitpos: [19]; default: 0; - * NA - */ - uint32_t mask_dphy_errors_3:1; - /** mask_dphy_errors_4 : R/W; bitpos: [20]; default: 0; - * NA - */ - uint32_t mask_dphy_errors_4:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} dsi_host_int_msk0_reg_t; - -/** Type of int_msk1 register - * NA - */ -typedef union { - struct { - /** mask_to_hs_tx : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t mask_to_hs_tx:1; - /** mask_to_lp_rx : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t mask_to_lp_rx:1; - /** mask_ecc_single_err : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t mask_ecc_single_err:1; - /** mask_ecc_milti_err : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t mask_ecc_milti_err:1; - /** mask_crc_err : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t mask_crc_err:1; - /** mask_pkt_size_err : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t mask_pkt_size_err:1; - /** mask_eopt_err : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t mask_eopt_err:1; - /** mask_dpi_pld_wr_err : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t mask_dpi_pld_wr_err:1; - /** mask_gen_cmd_wr_err : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t mask_gen_cmd_wr_err:1; - /** mask_gen_pld_wr_err : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t mask_gen_pld_wr_err:1; - /** mask_gen_pld_send_err : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t mask_gen_pld_send_err:1; - /** mask_gen_pld_rd_err : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t mask_gen_pld_rd_err:1; - /** mask_gen_pld_recev_err : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t mask_gen_pld_recev_err:1; - uint32_t reserved_13:6; - /** mask_dpi_buff_pld_under : R/W; bitpos: [19]; default: 0; - * NA - */ - uint32_t mask_dpi_buff_pld_under:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} dsi_host_int_msk1_reg_t; - -/** Type of int_force0 register - * NA - */ -typedef union { - struct { - /** force_ack_with_err_0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t force_ack_with_err_0:1; - /** force_ack_with_err_1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t force_ack_with_err_1:1; - /** force_ack_with_err_2 : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t force_ack_with_err_2:1; - /** force_ack_with_err_3 : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t force_ack_with_err_3:1; - /** force_ack_with_err_4 : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t force_ack_with_err_4:1; - /** force_ack_with_err_5 : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t force_ack_with_err_5:1; - /** force_ack_with_err_6 : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t force_ack_with_err_6:1; - /** force_ack_with_err_7 : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t force_ack_with_err_7:1; - /** force_ack_with_err_8 : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t force_ack_with_err_8:1; - /** force_ack_with_err_9 : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t force_ack_with_err_9:1; - /** force_ack_with_err_10 : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t force_ack_with_err_10:1; - /** force_ack_with_err_11 : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t force_ack_with_err_11:1; - /** force_ack_with_err_12 : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t force_ack_with_err_12:1; - /** force_ack_with_err_13 : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t force_ack_with_err_13:1; - /** force_ack_with_err_14 : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t force_ack_with_err_14:1; - /** force_ack_with_err_15 : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t force_ack_with_err_15:1; - /** force_dphy_errors_0 : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t force_dphy_errors_0:1; - /** force_dphy_errors_1 : R/W; bitpos: [17]; default: 0; - * NA - */ - uint32_t force_dphy_errors_1:1; - /** force_dphy_errors_2 : R/W; bitpos: [18]; default: 0; - * NA - */ - uint32_t force_dphy_errors_2:1; - /** force_dphy_errors_3 : R/W; bitpos: [19]; default: 0; - * NA - */ - uint32_t force_dphy_errors_3:1; - /** force_dphy_errors_4 : R/W; bitpos: [20]; default: 0; - * NA - */ - uint32_t force_dphy_errors_4:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} dsi_host_int_force0_reg_t; - -/** Type of int_force1 register - * NA - */ -typedef union { - struct { - /** force_to_hs_tx : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t force_to_hs_tx:1; - /** force_to_lp_rx : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t force_to_lp_rx:1; - /** force_ecc_single_err : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t force_ecc_single_err:1; - /** force_ecc_milti_err : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t force_ecc_milti_err:1; - /** force_crc_err : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t force_crc_err:1; - /** force_pkt_size_err : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t force_pkt_size_err:1; - /** force_eopt_err : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t force_eopt_err:1; - /** force_dpi_pld_wr_err : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t force_dpi_pld_wr_err:1; - /** force_gen_cmd_wr_err : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t force_gen_cmd_wr_err:1; - /** force_gen_pld_wr_err : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t force_gen_pld_wr_err:1; - /** force_gen_pld_send_err : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t force_gen_pld_send_err:1; - /** force_gen_pld_rd_err : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t force_gen_pld_rd_err:1; - /** force_gen_pld_recev_err : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t force_gen_pld_recev_err:1; - uint32_t reserved_13:6; - /** force_dpi_buff_pld_under : R/W; bitpos: [19]; default: 0; - * NA - */ - uint32_t force_dpi_buff_pld_under:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} dsi_host_int_force1_reg_t; - - -typedef struct { - volatile dsi_host_version_reg_t version; - volatile dsi_host_pwr_up_reg_t pwr_up; - volatile dsi_host_clkmgr_cfg_reg_t clkmgr_cfg; - volatile dsi_host_dpi_vcid_reg_t dpi_vcid; - volatile dsi_host_dpi_color_coding_reg_t dpi_color_coding; - volatile dsi_host_dpi_cfg_pol_reg_t dpi_cfg_pol; - volatile dsi_host_dpi_lp_cmd_tim_reg_t dpi_lp_cmd_tim; - volatile dsi_host_dbi_vcid_reg_t dbi_vcid; - volatile dsi_host_dbi_cfg_reg_t dbi_cfg; - volatile dsi_host_dbi_partitioning_en_reg_t dbi_partitioning_en; - volatile dsi_host_dbi_cmdsize_reg_t dbi_cmdsize; - volatile dsi_host_pckhdl_cfg_reg_t pckhdl_cfg; - volatile dsi_host_gen_vcid_reg_t gen_vcid; - volatile dsi_host_mode_cfg_reg_t mode_cfg; - volatile dsi_host_vid_mode_cfg_reg_t vid_mode_cfg; - volatile dsi_host_vid_pkt_size_reg_t vid_pkt_size; - volatile dsi_host_vid_num_chunks_reg_t vid_num_chunks; - volatile dsi_host_vid_null_size_reg_t vid_null_size; - volatile dsi_host_vid_hsa_time_reg_t vid_hsa_time; - volatile dsi_host_vid_hbp_time_reg_t vid_hbp_time; - volatile dsi_host_vid_hline_time_reg_t vid_hline_time; - volatile dsi_host_vid_vsa_lines_reg_t vid_vsa_lines; - volatile dsi_host_vid_vbp_lines_reg_t vid_vbp_lines; - volatile dsi_host_vid_vfp_lines_reg_t vid_vfp_lines; - volatile dsi_host_vid_vactive_lines_reg_t vid_vactive_lines; - volatile dsi_host_edpi_cmd_size_reg_t edpi_cmd_size; - volatile dsi_host_cmd_mode_cfg_reg_t cmd_mode_cfg; - volatile dsi_host_gen_hdr_reg_t gen_hdr; - volatile dsi_host_gen_pld_data_reg_t gen_pld_data; - volatile dsi_host_cmd_pkt_status_reg_t cmd_pkt_status; - volatile dsi_host_to_cnt_cfg_reg_t to_cnt_cfg; - volatile dsi_host_hs_rd_to_cnt_reg_t hs_rd_to_cnt; - volatile dsi_host_lp_rd_to_cnt_reg_t lp_rd_to_cnt; - volatile dsi_host_hs_wr_to_cnt_reg_t hs_wr_to_cnt; - volatile dsi_host_lp_wr_to_cnt_reg_t lp_wr_to_cnt; - volatile dsi_host_bta_to_cnt_reg_t bta_to_cnt; - volatile dsi_host_sdf_3d_reg_t sdf_3d; - volatile dsi_host_lpclk_ctrl_reg_t lpclk_ctrl; - volatile dsi_host_phy_tmr_lpclk_cfg_reg_t phy_tmr_lpclk_cfg; - volatile dsi_host_phy_tmr_cfg_reg_t phy_tmr_cfg; - volatile dsi_host_phy_rstz_reg_t phy_rstz; - volatile dsi_host_phy_if_cfg_reg_t phy_if_cfg; - volatile dsi_host_phy_ulps_ctrl_reg_t phy_ulps_ctrl; - volatile dsi_host_phy_tx_triggers_reg_t phy_tx_triggers; - volatile dsi_host_phy_status_reg_t phy_status; - volatile dsi_host_phy_tst_ctrl0_reg_t phy_tst_ctrl0; - volatile dsi_host_phy_tst_ctrl1_reg_t phy_tst_ctrl1; - volatile dsi_host_int_st0_reg_t int_st0; - volatile dsi_host_int_st1_reg_t int_st1; - volatile dsi_host_int_msk0_reg_t int_msk0; - volatile dsi_host_int_msk1_reg_t int_msk1; - volatile dsi_host_phy_cal_reg_t phy_cal; - uint32_t reserved_0d0[2]; - volatile dsi_host_int_force0_reg_t int_force0; - volatile dsi_host_int_force1_reg_t int_force1; - uint32_t reserved_0e0[4]; - volatile dsi_host_dsc_parameter_reg_t dsc_parameter; - volatile dsi_host_phy_tmr_rd_cfg_reg_t phy_tmr_rd_cfg; - uint32_t reserved_0f8[2]; - volatile dsi_host_vid_shadow_ctrl_reg_t vid_shadow_ctrl; - uint32_t reserved_104[2]; - volatile dsi_host_dpi_vcid_act_reg_t dpi_vcid_act; - volatile dsi_host_dpi_color_coding_act_reg_t dpi_color_coding_act; - uint32_t reserved_114; - volatile dsi_host_dpi_lp_cmd_tim_act_reg_t dpi_lp_cmd_tim_act; - volatile dsi_host_edpi_te_hw_cfg_reg_t edpi_te_hw_cfg; - uint32_t reserved_120[6]; - volatile dsi_host_vid_mode_cfg_act_reg_t vid_mode_cfg_act; - volatile dsi_host_vid_pkt_size_act_reg_t vid_pkt_size_act; - volatile dsi_host_vid_num_chunks_act_reg_t vid_num_chunks_act; - volatile dsi_host_vid_null_size_act_reg_t vid_null_size_act; - volatile dsi_host_vid_hsa_time_act_reg_t vid_hsa_time_act; - volatile dsi_host_vid_hbp_time_act_reg_t vid_hbp_time_act; - volatile dsi_host_vid_hline_time_act_reg_t vid_hline_time_act; - volatile dsi_host_vid_vsa_lines_act_reg_t vid_vsa_lines_act; - volatile dsi_host_vid_vbp_lines_act_reg_t vid_vbp_lines_act; - volatile dsi_host_vid_vfp_lines_act_reg_t vid_vfp_lines_act; - volatile dsi_host_vid_vactive_lines_act_reg_t vid_vactive_lines_act; - uint32_t reserved_164; - volatile dsi_host_vid_pkt_status_reg_t vid_pkt_status; - uint32_t reserved_16c[9]; - volatile dsi_host_sdf_3d_act_reg_t sdf_3d_act; -} dsi_host_dev_t; - -extern dsi_host_dev_t MIPI_DSI_HOST; - -#ifndef __cplusplus -_Static_assert(sizeof(dsi_host_dev_t) == 0x194, "Invalid size of dsi_host_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pmu_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/pmu_eco5_struct.h deleted file mode 100644 index b800521b0da9..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/pmu_eco5_struct.h +++ /dev/null @@ -1,3973 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: configure_register */ -/** Type of hp_active_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** hp_active_dcdc_switch_pd_en : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t hp_active_dcdc_switch_pd_en:1; - /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_active_hp_mem_dslp:1; - /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_mem_pd_en:1; - uint32_t reserved_24:5; - /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_cpu_pd_en:1; - /** hp_active_pd_cnnt_pd_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_pd_cnnt_pd_en:1; - /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active_pd_top_pd_en:1; - }; - uint32_t val; -} pmu_hp_active_dig_power_reg_t; - -/** Type of hp_active_icg_hp_func register - * need_des - */ -typedef union { - struct { - /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_active_dig_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_active_icg_hp_func_reg_t; - -/** Type of hp_active_icg_hp_apb register - * need_des - */ -typedef union { - struct { - /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_active_dig_icg_apb_en:32; - }; - uint32_t val; -} pmu_hp_active_icg_hp_apb_reg_t; - -/** Type of hp_active_icg_modem register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_active_dig_icg_modem_code:2; - }; - uint32_t val; -} pmu_hp_active_icg_modem_reg_t; - -/** Type of hp_active_hp_sys_cntl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** hp_active_hp_power_det_bypass : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t hp_active_hp_power_det_bypass:1; - /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t hp_active_uart_wakeup_en:1; - /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_active_lp_pad_hold_all:1; - /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_hp_pad_hold_all:1; - /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_dig_pad_slp_sel:1; - /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_dig_pause_wdt:1; - /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_dig_cpu_stall:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} pmu_hp_active_hp_sys_cntl_reg_t; - -/** Type of hp_active_hp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** hp_active_i2c_iso_en : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t hp_active_i2c_iso_en:1; - /** hp_active_i2c_retention : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_active_i2c_retention:1; - /** hp_active_xpd_pll_i2c : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_pll_i2c:4; - /** hp_active_xpd_pll : R/W; bitpos: [30:27]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_pll:4; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_hp_active_hp_ck_power_reg_t; - -/** Type of hp_active_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:18; - /** hp_active_dcm_vset : R/W; bitpos: [22:18]; default: 20; - * need_des - */ - uint32_t hp_active_dcm_vset:5; - /** hp_active_dcm_mode : R/W; bitpos: [24:23]; default: 0; - * need_des - */ - uint32_t hp_active_dcm_mode:2; - /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bias:1; - /** hp_active_dbg_atten : R/W; bitpos: [29:26]; default: 0; - * need_des - */ - uint32_t hp_active_dbg_atten:4; - /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_pd_cur:1; - /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active_bias_sleep:1; - }; - uint32_t val; -} pmu_hp_active_bias_reg_t; - -/** Type of hp_active_backup register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_modem_clk_code:2; - /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_modem_clk_code:2; - uint32_t reserved_8:2; - /** hp_active_retention_mode : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t hp_active_retention_mode:1; - /** hp_sleep2active_retention_en : R/W; bitpos: [11]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_retention_en:1; - /** hp_modem2active_retention_en : R/W; bitpos: [12]; default: 0; - * need_des - */ - uint32_t hp_modem2active_retention_en:1; - uint32_t reserved_13:1; - /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_clk_sel:2; - /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_clk_sel:2; - uint32_t reserved_18:2; - /** hp_sleep2active_backup_mode : R/W; bitpos: [22:20]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_mode:3; - /** hp_modem2active_backup_mode : R/W; bitpos: [25:23]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_mode:3; - uint32_t reserved_26:3; - /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_en:1; - /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_en:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_hp_active_backup_reg_t; - -/** Type of hp_active_backup_clk register - * need_des - */ -typedef union { - struct { - /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_active_backup_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_active_backup_clk_reg_t; - -/** Type of hp_active_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_dig_sys_clk_no_div:1; - /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_icg_sys_clock_en:1; - /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_sys_clk_slp_sel:1; - /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_icg_slp_sel:1; - /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_active_dig_sys_clk_sel:2; - }; - uint32_t val; -} pmu_hp_active_sysclk_reg_t; - -/** Type of hp_active_hp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** lp_dbias_vol : RO; bitpos: [8:4]; default: 24; - * need_des - */ - uint32_t lp_dbias_vol:5; - /** hp_dbias_vol : RO; bitpos: [13:9]; default: 24; - * need_des - */ - uint32_t hp_dbias_vol:5; - /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1; - * need_des - */ - uint32_t dig_regulator0_dbias_sel:1; - /** dig_dbias_init : WT; bitpos: [15]; default: 0; - * need_des - */ - uint32_t dig_dbias_init:1; - /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_mem_xpd:1; - /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_logic_xpd:1; - /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_xpd:1; - /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_mem_dbias:4; - /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_logic_dbias:4; - /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; - * need_des - */ - uint32_t hp_active_hp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_active_hp_regulator0_reg_t; - -/** Type of hp_active_hp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:26]; default: 0; - * need_des - */ - uint32_t hp_active_hp_regulator_drv_b:6; - }; - uint32_t val; -} pmu_hp_active_hp_regulator1_reg_t; - -/** Type of hp_active_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t hp_active_xpd_xtal:1; - }; - uint32_t val; -} pmu_hp_active_xtal_reg_t; - -/** Type of hp_modem_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** hp_modem_dcdc_switch_pd_en : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t hp_modem_dcdc_switch_pd_en:1; - /** hp_modem_hp_mem_dslp : WT; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_mem_dslp:1; - /** hp_modem_pd_hp_mem_pd_en : WT; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_hp_mem_pd_en:4; - /** hp_modem_pd_hp_wifi_pd_en : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_hp_wifi_pd_en:1; - uint32_t reserved_28:1; - /** hp_modem_pd_hp_cpu_pd_en : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_hp_cpu_pd_en:1; - /** hp_modem_pd_cnnt_pd_en : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_cnnt_pd_en:1; - /** hp_modem_pd_top_pd_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_top_pd_en:1; - }; - uint32_t val; -} pmu_hp_modem_dig_power_reg_t; - -/** Type of hp_modem_icg_hp_func register - * need_des - */ -typedef union { - struct { - /** hp_modem_dig_icg_func_en : WT; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_modem_icg_hp_func_reg_t; - -/** Type of hp_modem_icg_hp_apb register - * need_des - */ -typedef union { - struct { - /** hp_modem_dig_icg_apb_en : WT; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_icg_apb_en:32; - }; - uint32_t val; -} pmu_hp_modem_icg_hp_apb_reg_t; - -/** Type of hp_modem_icg_modem register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** hp_modem_dig_icg_modem_code : WT; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_icg_modem_code:2; - }; - uint32_t val; -} pmu_hp_modem_icg_modem_reg_t; - -/** Type of hp_modem_hp_sys_cntl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** hp_modem_hp_power_det_bypass : WT; bitpos: [23]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_power_det_bypass:1; - /** hp_modem_uart_wakeup_en : WT; bitpos: [24]; default: 0; - * need_des - */ - uint32_t hp_modem_uart_wakeup_en:1; - /** hp_modem_lp_pad_hold_all : WT; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_modem_lp_pad_hold_all:1; - /** hp_modem_hp_pad_hold_all : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_pad_hold_all:1; - /** hp_modem_dig_pad_slp_sel : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_pad_slp_sel:1; - /** hp_modem_dig_pause_wdt : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_pause_wdt:1; - /** hp_modem_dig_cpu_stall : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_cpu_stall:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} pmu_hp_modem_hp_sys_cntl_reg_t; - -/** Type of hp_modem_hp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** hp_modem_i2c_iso_en : WT; bitpos: [21]; default: 0; - * need_des - */ - uint32_t hp_modem_i2c_iso_en:1; - /** hp_modem_i2c_retention : WT; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_modem_i2c_retention:1; - /** hp_modem_xpd_pll_i2c : WT; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_modem_xpd_pll_i2c:4; - /** hp_modem_xpd_pll : WT; bitpos: [30:27]; default: 0; - * need_des - */ - uint32_t hp_modem_xpd_pll:4; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_hp_modem_hp_ck_power_reg_t; - -/** Type of hp_modem_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:18; - /** hp_modem_dcm_vset : WT; bitpos: [22:18]; default: 0; - * need_des - */ - uint32_t hp_modem_dcm_vset:5; - /** hp_modem_dcm_mode : WT; bitpos: [24:23]; default: 0; - * need_des - */ - uint32_t hp_modem_dcm_mode:2; - /** hp_modem_xpd_bias : WT; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_modem_xpd_bias:1; - /** hp_modem_dbg_atten : WT; bitpos: [29:26]; default: 0; - * need_des - */ - uint32_t hp_modem_dbg_atten:4; - /** hp_modem_pd_cur : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_cur:1; - /** hp_modem_bias_sleep : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_modem_bias_sleep:1; - }; - uint32_t val; -} pmu_hp_modem_bias_reg_t; - -/** Type of hp_modem_backup register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** hp_sleep2modem_backup_modem_clk_code : WT; bitpos: [5:4]; default: 0; - * need_des - */ - uint32_t hp_sleep2modem_backup_modem_clk_code:2; - uint32_t reserved_6:4; - /** hp_modem_retention_mode : WT; bitpos: [10]; default: 0; - * need_des - */ - uint32_t hp_modem_retention_mode:1; - /** hp_sleep2modem_retention_en : WT; bitpos: [11]; default: 0; - * need_des - */ - uint32_t hp_sleep2modem_retention_en:1; - uint32_t reserved_12:2; - /** hp_sleep2modem_backup_clk_sel : WT; bitpos: [15:14]; default: 0; - * need_des - */ - uint32_t hp_sleep2modem_backup_clk_sel:2; - uint32_t reserved_16:4; - /** hp_sleep2modem_backup_mode : WT; bitpos: [22:20]; default: 0; - * need_des - */ - uint32_t hp_sleep2modem_backup_mode:3; - uint32_t reserved_23:6; - /** hp_sleep2modem_backup_en : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep2modem_backup_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} pmu_hp_modem_backup_reg_t; - -/** Type of hp_modem_backup_clk register - * need_des - */ -typedef union { - struct { - /** hp_modem_backup_icg_func_en : WT; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_modem_backup_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_modem_backup_clk_reg_t; - -/** Type of hp_modem_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_modem_dig_sys_clk_no_div : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_sys_clk_no_div:1; - /** hp_modem_icg_sys_clock_en : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_modem_icg_sys_clock_en:1; - /** hp_modem_sys_clk_slp_sel : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_modem_sys_clk_slp_sel:1; - /** hp_modem_icg_slp_sel : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_modem_icg_slp_sel:1; - /** hp_modem_dig_sys_clk_sel : WT; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_sys_clk_sel:2; - }; - uint32_t val; -} pmu_hp_modem_sysclk_reg_t; - -/** Type of hp_modem_hp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** hp_modem_hp_regulator_slp_mem_xpd : WT; bitpos: [16]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_regulator_slp_mem_xpd:1; - /** hp_modem_hp_regulator_slp_logic_xpd : WT; bitpos: [17]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_regulator_slp_logic_xpd:1; - /** hp_modem_hp_regulator_xpd : WT; bitpos: [18]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_regulator_xpd:1; - /** hp_modem_hp_regulator_slp_mem_dbias : WT; bitpos: [22:19]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_regulator_slp_mem_dbias:4; - /** hp_modem_hp_regulator_slp_logic_dbias : WT; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_regulator_slp_logic_dbias:4; - /** hp_modem_hp_regulator_dbias : WT; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_modem_hp_regulator0_reg_t; - -/** Type of hp_modem_hp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** hp_modem_hp_regulator_drv_b : WT; bitpos: [31:8]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_regulator_drv_b:24; - }; - uint32_t val; -} pmu_hp_modem_hp_regulator1_reg_t; - -/** Type of hp_modem_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** hp_modem_xpd_xtal : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_modem_xpd_xtal:1; - }; - uint32_t val; -} pmu_hp_modem_xtal_reg_t; - -/** Type of hp_sleep_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** hp_sleep_dcdc_switch_pd_en : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t hp_sleep_dcdc_switch_pd_en:1; - /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_mem_dslp:1; - /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_mem_pd_en:1; - uint32_t reserved_24:5; - /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_cpu_pd_en:1; - /** hp_sleep_pd_cnnt_pd_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_cnnt_pd_en:1; - /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_top_pd_en:1; - }; - uint32_t val; -} pmu_hp_sleep_dig_power_reg_t; - -/** Type of hp_sleep_icg_hp_func register - * need_des - */ -typedef union { - struct { - /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_sleep_dig_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_sleep_icg_hp_func_reg_t; - -/** Type of hp_sleep_icg_hp_apb register - * need_des - */ -typedef union { - struct { - /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_sleep_dig_icg_apb_en:32; - }; - uint32_t val; -} pmu_hp_sleep_icg_hp_apb_reg_t; - -/** Type of hp_sleep_icg_modem register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_icg_modem_code:2; - }; - uint32_t val; -} pmu_hp_sleep_icg_modem_reg_t; - -/** Type of hp_sleep_hp_sys_cntl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** hp_sleep_hp_power_det_bypass : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_power_det_bypass:1; - /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t hp_sleep_uart_wakeup_en:1; - /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_pad_hold_all:1; - /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_pad_hold_all:1; - /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_pad_slp_sel:1; - /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_pause_wdt:1; - /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_cpu_stall:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} pmu_hp_sleep_hp_sys_cntl_reg_t; - -/** Type of hp_sleep_hp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** hp_sleep_i2c_iso_en : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t hp_sleep_i2c_iso_en:1; - /** hp_sleep_i2c_retention : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_sleep_i2c_retention:1; - /** hp_sleep_xpd_pll_i2c : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_pll_i2c:4; - /** hp_sleep_xpd_pll : R/W; bitpos: [30:27]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_pll:4; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_hp_sleep_hp_ck_power_reg_t; - -/** Type of hp_sleep_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:18; - /** hp_sleep_dcm_vset : R/W; bitpos: [22:18]; default: 20; - * need_des - */ - uint32_t hp_sleep_dcm_vset:5; - /** hp_sleep_dcm_mode : R/W; bitpos: [24:23]; default: 0; - * need_des - */ - uint32_t hp_sleep_dcm_mode:2; - /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bias:1; - /** hp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; - * need_des - */ - uint32_t hp_sleep_dbg_atten:4; - /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_cur:1; - /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_bias_sleep:1; - }; - uint32_t val; -} pmu_hp_sleep_bias_reg_t; - -/** Type of hp_sleep_backup register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_modem_clk_code:2; - /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_modem_clk_code:2; - /** hp_sleep_retention_mode : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t hp_sleep_retention_mode:1; - uint32_t reserved_11:1; - /** hp_modem2sleep_retention_en : R/W; bitpos: [12]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_retention_en:1; - /** hp_active2sleep_retention_en : R/W; bitpos: [13]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_retention_en:1; - uint32_t reserved_14:2; - /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_clk_sel:2; - /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_clk_sel:2; - uint32_t reserved_20:3; - /** hp_modem2sleep_backup_mode : R/W; bitpos: [25:23]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_mode:3; - /** hp_active2sleep_backup_mode : R/W; bitpos: [28:26]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_mode:3; - uint32_t reserved_29:1; - /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_en:1; - /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_en:1; - }; - uint32_t val; -} pmu_hp_sleep_backup_reg_t; - -/** Type of hp_sleep_backup_clk register - * need_des - */ -typedef union { - struct { - /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_sleep_backup_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_sleep_backup_clk_reg_t; - -/** Type of hp_sleep_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_sys_clk_no_div:1; - /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_icg_sys_clock_en:1; - /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_sys_clk_slp_sel:1; - /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_icg_slp_sel:1; - /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_sys_clk_sel:2; - }; - uint32_t val; -} pmu_hp_sleep_sysclk_reg_t; - -/** Type of hp_sleep_hp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1; - /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1; - /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_xpd:1; - /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4; - /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4; - /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; - * need_des - */ - uint32_t hp_sleep_hp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_sleep_hp_regulator0_reg_t; - -/** Type of hp_sleep_hp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:26]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_regulator_drv_b:6; - }; - uint32_t val; -} pmu_hp_sleep_hp_regulator1_reg_t; - -/** Type of hp_sleep_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_xtal:1; - }; - uint32_t val; -} pmu_hp_sleep_xtal_reg_t; - -/** Type of hp_sleep_lp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; - * need_des - */ - uint32_t hp_sleep_lp_regulator_slp_xpd:1; - /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; - * need_des - */ - uint32_t hp_sleep_lp_regulator_xpd:1; - /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; - * need_des - */ - uint32_t hp_sleep_lp_regulator_slp_dbias:4; - /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; - * need_des - */ - uint32_t hp_sleep_lp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_sleep_lp_regulator0_reg_t; - -/** Type of hp_sleep_lp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:26]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_regulator_drv_b:6; - }; - uint32_t val; -} pmu_hp_sleep_lp_regulator1_reg_t; - -/** Type of hp_sleep_lp_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_sleep_lp_pad_slp_sel : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_pad_slp_sel:1; - /** hp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_bod_source_sel:1; - /** hp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; - * need_des - */ - uint32_t hp_sleep_vddbat_mode:2; - /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_mem_dslp:1; - /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_lp_peri_pd_en:1; - }; - uint32_t val; -} pmu_hp_sleep_lp_dig_power_reg_t; - -/** Type of hp_sleep_lp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** hp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_lppll:1; - /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_xtal32k:1; - /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_rc32k:1; - /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_fosc_clk:1; - /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_osc_clk:1; - }; - uint32_t val; -} pmu_hp_sleep_lp_ck_power_reg_t; - -/** Type of lp_sleep_lp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; - * need_des - */ - uint32_t lp_sleep_lp_regulator_slp_xpd:1; - /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; - * need_des - */ - uint32_t lp_sleep_lp_regulator_xpd:1; - /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; - * need_des - */ - uint32_t lp_sleep_lp_regulator_slp_dbias:4; - /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; - * need_des - */ - uint32_t lp_sleep_lp_regulator_dbias:5; - }; - uint32_t val; -} pmu_lp_sleep_lp_regulator0_reg_t; - -/** Type of lp_sleep_lp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:26]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_regulator_drv_b:6; - }; - uint32_t val; -} pmu_lp_sleep_lp_regulator1_reg_t; - -/** Type of lp_sleep_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t lp_sleep_xpd_xtal:1; - }; - uint32_t val; -} pmu_lp_sleep_xtal_reg_t; - -/** Type of lp_sleep_lp_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** lp_sleep_lp_pad_slp_sel : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_pad_slp_sel:1; - /** lp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_sleep_bod_source_sel:1; - /** lp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; - * need_des - */ - uint32_t lp_sleep_vddbat_mode:2; - /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_mem_dslp:1; - /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_lp_peri_pd_en:1; - }; - uint32_t val; -} pmu_lp_sleep_lp_dig_power_reg_t; - -/** Type of lp_sleep_lp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** lp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_lppll:1; - /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_xtal32k:1; - /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_rc32k:1; - /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t lp_sleep_xpd_fosc_clk:1; - /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_osc_clk:1; - }; - uint32_t val; -} pmu_lp_sleep_lp_ck_power_reg_t; - -/** Type of lp_sleep_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:25; - /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_bias:1; - /** lp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; - * need_des - */ - uint32_t lp_sleep_dbg_atten:4; - /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_cur:1; - /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_bias_sleep:1; - }; - uint32_t val; -} pmu_lp_sleep_bias_reg_t; - -/** Type of imm_hp_ck_power register - * need_des - */ -typedef union { - struct { - /** tie_low_cali_xtal_icg : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t tie_low_cali_xtal_icg:1; - /** tie_low_global_pll_icg : WT; bitpos: [4:1]; default: 0; - * need_des - */ - uint32_t tie_low_global_pll_icg:4; - /** tie_low_global_xtal_icg : WT; bitpos: [5]; default: 0; - * need_des - */ - uint32_t tie_low_global_xtal_icg:1; - /** tie_low_i2c_retention : WT; bitpos: [6]; default: 0; - * need_des - */ - uint32_t tie_low_i2c_retention:1; - /** tie_low_xpd_pll_i2c : WT; bitpos: [10:7]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_pll_i2c:4; - /** tie_low_xpd_pll : WT; bitpos: [14:11]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_pll:4; - /** tie_low_xpd_xtal : WT; bitpos: [15]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_xtal:1; - /** tie_high_cali_xtal_icg : R/W; bitpos: [16]; default: 0; - * need_des - */ - uint32_t tie_high_cali_xtal_icg:1; - /** tie_high_global_pll_icg : WT; bitpos: [20:17]; default: 0; - * need_des - */ - uint32_t tie_high_global_pll_icg:4; - /** tie_high_global_xtal_icg : WT; bitpos: [21]; default: 0; - * need_des - */ - uint32_t tie_high_global_xtal_icg:1; - /** tie_high_i2c_retention : WT; bitpos: [22]; default: 0; - * need_des - */ - uint32_t tie_high_i2c_retention:1; - /** tie_high_xpd_pll_i2c : WT; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_pll_i2c:4; - /** tie_high_xpd_pll : WT; bitpos: [30:27]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_pll:4; - /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_xtal:1; - }; - uint32_t val; -} pmu_imm_hp_ck_power_reg_t; - -/** Type of imm_sleep_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** update_dig_icg_switch : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t update_dig_icg_switch:1; - /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_low_icg_slp_sel:1; - /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_icg_slp_sel:1; - /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_sys_clk_sel:1; - }; - uint32_t val; -} pmu_imm_sleep_sysclk_reg_t; - -/** Type of imm_hp_func_icg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_func_en:1; - }; - uint32_t val; -} pmu_imm_hp_func_icg_reg_t; - -/** Type of imm_hp_apb_icg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_apb_en:1; - }; - uint32_t val; -} pmu_imm_hp_apb_icg_reg_t; - -/** Type of imm_modem_icg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_modem_en:1; - }; - uint32_t val; -} pmu_imm_modem_icg_reg_t; - -/** Type of imm_lp_icg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_low_lp_rootclk_sel:1; - /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_high_lp_rootclk_sel:1; - }; - uint32_t val; -} pmu_imm_lp_icg_reg_t; - -/** Type of imm_pad_hold_all register - * need_des - */ -typedef union { - struct { - /** pad_slp_sel : RO; bitpos: [0]; default: 0; - * need_des - */ - uint32_t pad_slp_sel:1; - /** lp_pad_hold_all : RO; bitpos: [1]; default: 0; - * need_des - */ - uint32_t lp_pad_hold_all:1; - /** hp_pad_hold_all : RO; bitpos: [2]; default: 0; - * need_des - */ - uint32_t hp_pad_hold_all:1; - uint32_t reserved_3:23; - /** tie_high_pad_slp_sel : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t tie_high_pad_slp_sel:1; - /** tie_low_pad_slp_sel : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t tie_low_pad_slp_sel:1; - /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t tie_high_lp_pad_hold_all:1; - /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_low_lp_pad_hold_all:1; - /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_hp_pad_hold_all:1; - /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_low_hp_pad_hold_all:1; - }; - uint32_t val; -} pmu_imm_pad_hold_all_reg_t; - -/** Type of imm_i2c_iso register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_i2c_iso_en:1; - /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_low_i2c_iso_en:1; - }; - uint32_t val; -} pmu_imm_i2c_iso_reg_t; - -/** Type of power_wait_timer0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; - * need_des - */ - uint32_t dg_hp_powerdown_timer:9; - /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255; - * need_des - */ - uint32_t dg_hp_powerup_timer:9; - /** dg_hp_wait_timer : R/W; bitpos: [31:23]; default: 255; - * need_des - */ - uint32_t dg_hp_wait_timer:9; - }; - uint32_t val; -} pmu_power_wait_timer0_reg_t; - -/** Type of power_wait_timer1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** dg_lp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; - * need_des - */ - uint32_t dg_lp_powerdown_timer:9; - /** dg_lp_powerup_timer : R/W; bitpos: [22:14]; default: 255; - * need_des - */ - uint32_t dg_lp_powerup_timer:9; - /** dg_lp_wait_timer : R/W; bitpos: [31:23]; default: 255; - * need_des - */ - uint32_t dg_lp_wait_timer:9; - }; - uint32_t val; -} pmu_power_wait_timer1_reg_t; - -/** Type of power_pd_top_cntl register - * need_des - */ -typedef union { - struct { - /** force_top_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_top_reset:1; - /** force_top_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_top_iso:1; - /** force_top_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_top_pu:1; - /** force_top_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_top_no_reset:1; - /** force_top_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_top_no_iso:1; - /** force_top_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_top_pd:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} pmu_power_pd_top_cntl_reg_t; - -/** Type of power_pd_cnnt_cntl register - * need_des - */ -typedef union { - struct { - /** force_cnnt_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_cnnt_reset:1; - /** force_cnnt_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_cnnt_iso:1; - /** force_cnnt_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_cnnt_pu:1; - /** force_cnnt_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_cnnt_no_reset:1; - /** force_cnnt_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_cnnt_no_iso:1; - /** force_cnnt_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_cnnt_pd:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} pmu_power_pd_cnnt_cntl_reg_t; - -/** Type of power_pd_hpmem_cntl register - * need_des - */ -typedef union { - struct { - /** force_hp_mem_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_mem_reset:1; - /** force_hp_mem_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_mem_iso:1; - /** force_hp_mem_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_mem_pu:1; - /** force_hp_mem_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_mem_no_reset:1; - /** force_hp_mem_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_mem_no_iso:1; - /** force_hp_mem_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_mem_pd:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} pmu_power_pd_hpmem_cntl_reg_t; - -/** Type of power_pd_top_mask register - * need_des - */ -typedef union { - struct { - /** xpd_top_mask : R/W; bitpos: [4:0]; default: 0; - * need_des - */ - uint32_t xpd_top_mask:5; - uint32_t reserved_5:22; - /** pd_top_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_top_mask:5; - }; - uint32_t val; -} pmu_power_pd_top_mask_reg_t; - -/** Type of power_pd_cnnt_mask register - * need_des - */ -typedef union { - struct { - /** xpd_cnnt_mask : R/W; bitpos: [4:0]; default: 0; - * need_des - */ - uint32_t xpd_cnnt_mask:5; - uint32_t reserved_5:22; - /** pd_cnnt_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_cnnt_mask:5; - }; - uint32_t val; -} pmu_power_pd_cnnt_mask_reg_t; - -/** Type of power_pd_hpmem_mask register - * need_des - */ -typedef union { - struct { - /** xpd_hp_mem_mask : R/W; bitpos: [5:0]; default: 0; - * need_des - */ - uint32_t xpd_hp_mem_mask:6; - uint32_t reserved_6:20; - /** pd_hp_mem_mask : R/W; bitpos: [31:26]; default: 0; - * need_des - */ - uint32_t pd_hp_mem_mask:6; - }; - uint32_t val; -} pmu_power_pd_hpmem_mask_reg_t; - -/** Type of power_dcdc_switch register - * need_des - */ -typedef union { - struct { - /** force_dcdc_switch_pu : R/W; bitpos: [0]; default: 1; - * need_des - */ - uint32_t force_dcdc_switch_pu:1; - /** force_dcdc_switch_pd : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_dcdc_switch_pd:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} pmu_power_dcdc_switch_reg_t; - -/** Type of power_pd_lpperi_cntl register - * need_des - */ -typedef union { - struct { - /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_lp_peri_reset:1; - /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_lp_peri_iso:1; - /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_lp_peri_pu:1; - /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_lp_peri_no_reset:1; - /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_lp_peri_no_iso:1; - /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_lp_peri_pd:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} pmu_power_pd_lpperi_cntl_reg_t; - -/** Type of power_pd_lpperi_mask register - * need_des - */ -typedef union { - struct { - /** xpd_lp_peri_mask : R/W; bitpos: [4:0]; default: 0; - * need_des - */ - uint32_t xpd_lp_peri_mask:5; - uint32_t reserved_5:22; - /** pd_lp_peri_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_lp_peri_mask:5; - }; - uint32_t val; -} pmu_power_pd_lpperi_mask_reg_t; - -/** Type of power_hp_pad register - * need_des - */ -typedef union { - struct { - /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_pad_no_iso_all:1; - /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_pad_iso_all:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} pmu_power_hp_pad_reg_t; - -/** Type of power_ck_wait_cntl register - * need_des - */ -typedef union { - struct { - /** pmu_wait_xtl_stable : R/W; bitpos: [15:0]; default: 256; - * need_des - */ - uint32_t pmu_wait_xtl_stable:16; - /** pmu_wait_pll_stable : R/W; bitpos: [31:16]; default: 256; - * need_des - */ - uint32_t pmu_wait_pll_stable:16; - }; - uint32_t val; -} pmu_power_ck_wait_cntl_reg_t; - -/** Type of slp_wakeup_cntl0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** sleep_req : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t sleep_req:1; - }; - uint32_t val; -} pmu_slp_wakeup_cntl0_reg_t; - -/** Type of slp_wakeup_cntl1 register - * need_des - */ -typedef union { - struct { - /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0; - * need_des - */ - uint32_t sleep_reject_ena:31; - /** slp_reject_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t slp_reject_en:1; - }; - uint32_t val; -} pmu_slp_wakeup_cntl1_reg_t; - -/** Type of slp_wakeup_cntl2 register - * need_des - */ -typedef union { - struct { - /** wakeup_ena : R/W; bitpos: [30:0]; default: 0; - * need_des - */ - uint32_t wakeup_ena:31; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_slp_wakeup_cntl2_reg_t; - -/** Type of slp_wakeup_cntl3 register - * need_des - */ -typedef union { - struct { - /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0; - * need_des - */ - uint32_t lp_min_slp_val:8; - /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0; - * need_des - */ - uint32_t hp_min_slp_val:8; - /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t sleep_prt_sel:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} pmu_slp_wakeup_cntl3_reg_t; - -/** Type of slp_wakeup_cntl4 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t slp_reject_cause_clr:1; - }; - uint32_t val; -} pmu_slp_wakeup_cntl4_reg_t; - -/** Type of slp_wakeup_cntl5 register - * need_des - */ -typedef union { - struct { - /** modem_wait_target : R/W; bitpos: [19:0]; default: 128; - * need_des - */ - uint32_t modem_wait_target:20; - uint32_t reserved_20:2; - /** lp_ana_wait_target_expand : R/W; bitpos: [23:22]; default: 0; - * need_des - */ - uint32_t lp_ana_wait_target_expand:2; - /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1; - * need_des - */ - uint32_t lp_ana_wait_target:8; - }; - uint32_t val; -} pmu_slp_wakeup_cntl5_reg_t; - -/** Type of slp_wakeup_cntl6 register - * need_des - */ -typedef union { - struct { - /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128; - * need_des - */ - uint32_t soc_wakeup_wait:20; - uint32_t reserved_20:10; - /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t soc_wakeup_wait_cfg:2; - }; - uint32_t val; -} pmu_slp_wakeup_cntl6_reg_t; - -/** Type of slp_wakeup_cntl7 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** ana_wait_target : R/W; bitpos: [31:16]; default: 1; - * need_des - */ - uint32_t ana_wait_target:16; - }; - uint32_t val; -} pmu_slp_wakeup_cntl7_reg_t; - -/** Type of slp_wakeup_cntl8 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** lp_lite_wakeup_ena : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_lite_wakeup_ena:1; - }; - uint32_t val; -} pmu_slp_wakeup_cntl8_reg_t; - -/** Type of slp_wakeup_status0 register - * need_des - */ -typedef union { - struct { - /** wakeup_cause : RO; bitpos: [30:0]; default: 0; - * need_des - */ - uint32_t wakeup_cause:31; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_slp_wakeup_status0_reg_t; - -/** Type of slp_wakeup_status1 register - * need_des - */ -typedef union { - struct { - /** reject_cause : RO; bitpos: [30:0]; default: 0; - * need_des - */ - uint32_t reject_cause:31; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_slp_wakeup_status1_reg_t; - -/** Type of slp_wakeup_status2 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** lp_lite_wakeup_cause : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_lite_wakeup_cause:1; - }; - uint32_t val; -} pmu_slp_wakeup_status2_reg_t; - -/** Type of hp_ck_poweron register - * need_des - */ -typedef union { - struct { - /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50; - * need_des - */ - uint32_t i2c_por_wait_target:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} pmu_hp_ck_poweron_reg_t; - -/** Type of hp_ck_cntl register - * need_des - */ -typedef union { - struct { - /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10; - * need_des - */ - uint32_t modify_icg_cntl_wait:8; - /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10; - * need_des - */ - uint32_t switch_icg_cntl_wait:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} pmu_hp_ck_cntl_reg_t; - -/** Type of por_status register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** por_done : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t por_done:1; - }; - uint32_t val; -} pmu_por_status_reg_t; - -/** Type of rf_pwc register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** mspi_phy_xpd : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t mspi_phy_xpd:1; - /** sdio_pll_xpd : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t sdio_pll_xpd:1; - /** perif_i2c_rstb : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t perif_i2c_rstb:1; - /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1; - * need_des - */ - uint32_t xpd_perif_i2c:1; - /** xpd_txrf_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t xpd_txrf_i2c:1; - /** xpd_rfrx_pbus : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t xpd_rfrx_pbus:1; - /** xpd_ckgen_i2c : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t xpd_ckgen_i2c:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_rf_pwc_reg_t; - -/** Type of backup_cfg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t backup_sys_clk_no_div:1; - }; - uint32_t val; -} pmu_backup_cfg_reg_t; - -/** Type of int_raw register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:14; - /** pmu_0p1a_cnt_target0_reach_0_hp_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * reg_0p1a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_0_hp_int_raw:1; - /** pmu_0p1a_cnt_target1_reach_0_hp_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_0_hp_int_raw:1; - /** pmu_0p1a_cnt_target0_reach_1_hp_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * reg_0p1a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_1_hp_int_raw:1; - /** pmu_0p1a_cnt_target1_reach_1_hp_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_1_hp_int_raw:1; - /** pmu_0p2a_cnt_target0_reach_0_hp_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_0_hp_int_raw:1; - /** pmu_0p2a_cnt_target1_reach_0_hp_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_0_hp_int_raw:1; - /** pmu_0p2a_cnt_target0_reach_1_hp_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_1_hp_int_raw:1; - /** pmu_0p2a_cnt_target1_reach_1_hp_int_raw : R/WTC/SS; bitpos: [21]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_1_hp_int_raw:1; - /** pmu_0p3a_cnt_target0_reach_0_hp_int_raw : R/WTC/SS; bitpos: [22]; default: 0; - * reg_0p3a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_0_hp_int_raw:1; - /** pmu_0p3a_cnt_target1_reach_0_hp_int_raw : R/WTC/SS; bitpos: [23]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_0_hp_int_raw:1; - /** pmu_0p3a_cnt_target0_reach_1_hp_int_raw : R/WTC/SS; bitpos: [24]; default: 0; - * reg_0p3a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_1_hp_int_raw:1; - /** pmu_0p3a_cnt_target1_reach_1_hp_int_raw : R/WTC/SS; bitpos: [25]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_1_hp_int_raw:1; - uint32_t reserved_26:1; - /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_raw:1; - /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_raw:1; - /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_raw:1; - /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_raw:1; - /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_raw:1; - }; - uint32_t val; -} pmu_int_raw_reg_t; - -/** Type of hp_int_st register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:14; - /** pmu_0p1a_cnt_target0_reach_0_hp_int_st : RO; bitpos: [14]; default: 0; - * reg_0p1a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_0_hp_int_st:1; - /** pmu_0p1a_cnt_target1_reach_0_hp_int_st : RO; bitpos: [15]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_0_hp_int_st:1; - /** pmu_0p1a_cnt_target0_reach_1_hp_int_st : RO; bitpos: [16]; default: 0; - * reg_0p1a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_1_hp_int_st:1; - /** pmu_0p1a_cnt_target1_reach_1_hp_int_st : RO; bitpos: [17]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_1_hp_int_st:1; - /** pmu_0p2a_cnt_target0_reach_0_hp_int_st : RO; bitpos: [18]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_0_hp_int_st:1; - /** pmu_0p2a_cnt_target1_reach_0_hp_int_st : RO; bitpos: [19]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_0_hp_int_st:1; - /** pmu_0p2a_cnt_target0_reach_1_hp_int_st : RO; bitpos: [20]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_1_hp_int_st:1; - /** pmu_0p2a_cnt_target1_reach_1_hp_int_st : RO; bitpos: [21]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_1_hp_int_st:1; - /** pmu_0p3a_cnt_target0_reach_0_hp_int_st : RO; bitpos: [22]; default: 0; - * reg_0p3a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_0_hp_int_st:1; - /** pmu_0p3a_cnt_target1_reach_0_hp_int_st : RO; bitpos: [23]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_0_hp_int_st:1; - /** pmu_0p3a_cnt_target0_reach_1_hp_int_st : RO; bitpos: [24]; default: 0; - * reg_0p3a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_1_hp_int_st:1; - /** pmu_0p3a_cnt_target1_reach_1_hp_int_st : RO; bitpos: [25]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_1_hp_int_st:1; - uint32_t reserved_26:1; - /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_st:1; - /** sdio_idle_int_st : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_st:1; - /** sw_int_st : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_st:1; - /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_st:1; - /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_st:1; - }; - uint32_t val; -} pmu_hp_int_st_reg_t; - -/** Type of hp_int_ena register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:14; - /** pmu_0p1a_cnt_target0_reach_0_hp_int_ena : R/W; bitpos: [14]; default: 0; - * reg_0p1a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_0_hp_int_ena:1; - /** pmu_0p1a_cnt_target1_reach_0_hp_int_ena : R/W; bitpos: [15]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_0_hp_int_ena:1; - /** pmu_0p1a_cnt_target0_reach_1_hp_int_ena : R/W; bitpos: [16]; default: 0; - * reg_0p1a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_1_hp_int_ena:1; - /** pmu_0p1a_cnt_target1_reach_1_hp_int_ena : R/W; bitpos: [17]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_1_hp_int_ena:1; - /** pmu_0p2a_cnt_target0_reach_0_hp_int_ena : R/W; bitpos: [18]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_0_hp_int_ena:1; - /** pmu_0p2a_cnt_target1_reach_0_hp_int_ena : R/W; bitpos: [19]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_0_hp_int_ena:1; - /** pmu_0p2a_cnt_target0_reach_1_hp_int_ena : R/W; bitpos: [20]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_1_hp_int_ena:1; - /** pmu_0p2a_cnt_target1_reach_1_hp_int_ena : R/W; bitpos: [21]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_1_hp_int_ena:1; - /** pmu_0p3a_cnt_target0_reach_0_hp_int_ena : R/W; bitpos: [22]; default: 0; - * reg_0p3a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_0_hp_int_ena:1; - /** pmu_0p3a_cnt_target1_reach_0_hp_int_ena : R/W; bitpos: [23]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_0_hp_int_ena:1; - /** pmu_0p3a_cnt_target0_reach_1_hp_int_ena : R/W; bitpos: [24]; default: 0; - * reg_0p3a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_1_hp_int_ena:1; - /** pmu_0p3a_cnt_target1_reach_1_hp_int_ena : R/W; bitpos: [25]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_1_hp_int_ena:1; - uint32_t reserved_26:1; - /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_ena:1; - /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_ena:1; - /** sw_int_ena : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_ena:1; - /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_ena:1; - /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_ena:1; - }; - uint32_t val; -} pmu_hp_int_ena_reg_t; - -/** Type of hp_int_clr register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:14; - /** pmu_0p1a_cnt_target0_reach_0_hp_int_clr : WT; bitpos: [14]; default: 0; - * reg_0p1a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_0_hp_int_clr:1; - /** pmu_0p1a_cnt_target1_reach_0_hp_int_clr : WT; bitpos: [15]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_0_hp_int_clr:1; - /** pmu_0p1a_cnt_target0_reach_1_hp_int_clr : WT; bitpos: [16]; default: 0; - * reg_0p1a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_1_hp_int_clr:1; - /** pmu_0p1a_cnt_target1_reach_1_hp_int_clr : WT; bitpos: [17]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_1_hp_int_clr:1; - /** pmu_0p2a_cnt_target0_reach_0_hp_int_clr : WT; bitpos: [18]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_0_hp_int_clr:1; - /** pmu_0p2a_cnt_target1_reach_0_hp_int_clr : WT; bitpos: [19]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_0_hp_int_clr:1; - /** pmu_0p2a_cnt_target0_reach_1_hp_int_clr : WT; bitpos: [20]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_1_hp_int_clr:1; - /** pmu_0p2a_cnt_target1_reach_1_hp_int_clr : WT; bitpos: [21]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_1_hp_int_clr:1; - /** pmu_0p3a_cnt_target0_reach_0_hp_int_clr : WT; bitpos: [22]; default: 0; - * reg_0p3a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_0_hp_int_clr:1; - /** pmu_0p3a_cnt_target1_reach_0_hp_int_clr : WT; bitpos: [23]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_0_hp_int_clr:1; - /** pmu_0p3a_cnt_target0_reach_1_hp_int_clr : WT; bitpos: [24]; default: 0; - * reg_0p3a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_1_hp_int_clr:1; - /** pmu_0p3a_cnt_target1_reach_1_hp_int_clr : WT; bitpos: [25]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_1_hp_int_clr:1; - uint32_t reserved_26:1; - /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_clr:1; - /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_clr:1; - /** sw_int_clr : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_clr:1; - /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_clr:1; - /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_clr:1; - }; - uint32_t val; -} pmu_hp_int_clr_reg_t; - -/** Type of lp_int_raw register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:13; - /** lp_cpu_sleep_reject_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * need_des - */ - uint32_t lp_cpu_sleep_reject_int_raw:1; - /** pmu_0p1a_cnt_target0_reach_0_lp_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * reg_0p1a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_0_lp_int_raw:1; - /** pmu_0p1a_cnt_target1_reach_0_lp_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_0_lp_int_raw:1; - /** pmu_0p1a_cnt_target0_reach_1_lp_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * reg_0p1a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_1_lp_int_raw:1; - /** pmu_0p1a_cnt_target1_reach_1_lp_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_1_lp_int_raw:1; - /** pmu_0p2a_cnt_target0_reach_0_lp_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_0_lp_int_raw:1; - /** pmu_0p2a_cnt_target1_reach_0_lp_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_0_lp_int_raw:1; - /** pmu_0p2a_cnt_target0_reach_1_lp_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_1_lp_int_raw:1; - /** pmu_0p2a_cnt_target1_reach_1_lp_int_raw : R/WTC/SS; bitpos: [21]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_1_lp_int_raw:1; - /** pmu_0p3a_cnt_target0_reach_0_lp_int_raw : R/WTC/SS; bitpos: [22]; default: 0; - * reg_0p3a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_0_lp_int_raw:1; - /** pmu_0p3a_cnt_target1_reach_0_lp_int_raw : R/WTC/SS; bitpos: [23]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_0_lp_int_raw:1; - /** pmu_0p3a_cnt_target0_reach_1_lp_int_raw : R/WTC/SS; bitpos: [24]; default: 0; - * reg_0p3a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_1_lp_int_raw:1; - /** pmu_0p3a_cnt_target1_reach_1_lp_int_raw : R/WTC/SS; bitpos: [25]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_1_lp_int_raw:1; - /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [26]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_raw:1; - /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_raw:1; - /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_raw:1; - /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_raw:1; - /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_raw:1; - /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_raw:1; - }; - uint32_t val; -} pmu_lp_int_raw_reg_t; - -/** Type of lp_int_st register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:13; - /** lp_cpu_sleep_reject_int_st : RO; bitpos: [13]; default: 0; - * need_des - */ - uint32_t lp_cpu_sleep_reject_int_st:1; - /** pmu_0p1a_cnt_target0_reach_0_lp_int_st : RO; bitpos: [14]; default: 0; - * reg_0p1a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_0_lp_int_st:1; - /** pmu_0p1a_cnt_target1_reach_0_lp_int_st : RO; bitpos: [15]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_0_lp_int_st:1; - /** pmu_0p1a_cnt_target0_reach_1_lp_int_st : RO; bitpos: [16]; default: 0; - * reg_0p1a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_1_lp_int_st:1; - /** pmu_0p1a_cnt_target1_reach_1_lp_int_st : RO; bitpos: [17]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_1_lp_int_st:1; - /** pmu_0p2a_cnt_target0_reach_0_lp_int_st : RO; bitpos: [18]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_0_lp_int_st:1; - /** pmu_0p2a_cnt_target1_reach_0_lp_int_st : RO; bitpos: [19]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_0_lp_int_st:1; - /** pmu_0p2a_cnt_target0_reach_1_lp_int_st : RO; bitpos: [20]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_1_lp_int_st:1; - /** pmu_0p2a_cnt_target1_reach_1_lp_int_st : RO; bitpos: [21]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_1_lp_int_st:1; - /** pmu_0p3a_cnt_target0_reach_0_lp_int_st : RO; bitpos: [22]; default: 0; - * reg_0p3a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_0_lp_int_st:1; - /** pmu_0p3a_cnt_target1_reach_0_lp_int_st : RO; bitpos: [23]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_0_lp_int_st:1; - /** pmu_0p3a_cnt_target0_reach_1_lp_int_st : RO; bitpos: [24]; default: 0; - * reg_0p3a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_1_lp_int_st:1; - /** pmu_0p3a_cnt_target1_reach_1_lp_int_st : RO; bitpos: [25]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_1_lp_int_st:1; - /** lp_cpu_wakeup_int_st : RO; bitpos: [26]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_st:1; - /** sleep_switch_active_end_int_st : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_st:1; - /** active_switch_sleep_end_int_st : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_st:1; - /** sleep_switch_active_start_int_st : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_st:1; - /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_st:1; - /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_st:1; - }; - uint32_t val; -} pmu_lp_int_st_reg_t; - -/** Type of lp_int_ena register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:13; - /** lp_cpu_sleep_reject_int_ena : R/W; bitpos: [13]; default: 0; - * need_des - */ - uint32_t lp_cpu_sleep_reject_int_ena:1; - /** pmu_0p1a_cnt_target0_reach_0_lp_int_ena : R/W; bitpos: [14]; default: 0; - * reg_0p1a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_0_lp_int_ena:1; - /** pmu_0p1a_cnt_target1_reach_0_lp_int_ena : R/W; bitpos: [15]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_0_lp_int_ena:1; - /** pmu_0p1a_cnt_target0_reach_1_lp_int_ena : R/W; bitpos: [16]; default: 0; - * reg_0p1a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_1_lp_int_ena:1; - /** pmu_0p1a_cnt_target1_reach_1_lp_int_ena : R/W; bitpos: [17]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_1_lp_int_ena:1; - /** pmu_0p2a_cnt_target0_reach_0_lp_int_ena : R/W; bitpos: [18]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_0_lp_int_ena:1; - /** pmu_0p2a_cnt_target1_reach_0_lp_int_ena : R/W; bitpos: [19]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_0_lp_int_ena:1; - /** pmu_0p2a_cnt_target0_reach_1_lp_int_ena : R/W; bitpos: [20]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_1_lp_int_ena:1; - /** pmu_0p2a_cnt_target1_reach_1_lp_int_ena : R/W; bitpos: [21]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_1_lp_int_ena:1; - /** pmu_0p3a_cnt_target0_reach_0_lp_int_ena : R/W; bitpos: [22]; default: 0; - * reg_0p3a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_0_lp_int_ena:1; - /** pmu_0p3a_cnt_target1_reach_0_lp_int_ena : R/W; bitpos: [23]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_0_lp_int_ena:1; - /** pmu_0p3a_cnt_target0_reach_1_lp_int_ena : R/W; bitpos: [24]; default: 0; - * reg_0p3a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_1_lp_int_ena:1; - /** pmu_0p3a_cnt_target1_reach_1_lp_int_ena : R/W; bitpos: [25]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_1_lp_int_ena:1; - /** lp_cpu_wakeup_int_ena : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_ena:1; - /** sleep_switch_active_end_int_ena : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_ena:1; - /** active_switch_sleep_end_int_ena : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_ena:1; - /** sleep_switch_active_start_int_ena : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_ena:1; - /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_ena:1; - /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_ena:1; - }; - uint32_t val; -} pmu_lp_int_ena_reg_t; - -/** Type of lp_int_clr register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:13; - /** lp_cpu_sleep_reject_lp_int_clr : WT; bitpos: [13]; default: 0; - * need_des - */ - uint32_t lp_cpu_sleep_reject_lp_int_clr:1; - /** pmu_0p1a_cnt_target0_reach_0_lp_int_clr : WT; bitpos: [14]; default: 0; - * reg_0p1a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_0_lp_int_clr:1; - /** pmu_0p1a_cnt_target1_reach_0_lp_int_clr : WT; bitpos: [15]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_0_lp_int_clr:1; - /** pmu_0p1a_cnt_target0_reach_1_lp_int_clr : WT; bitpos: [16]; default: 0; - * reg_0p1a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p1a_cnt_target0_reach_1_lp_int_clr:1; - /** pmu_0p1a_cnt_target1_reach_1_lp_int_clr : WT; bitpos: [17]; default: 0; - * reg_0p1a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p1a_cnt_target1_reach_1_lp_int_clr:1; - /** pmu_0p2a_cnt_target0_reach_0_lp_int_clr : WT; bitpos: [18]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_0_lp_int_clr:1; - /** pmu_0p2a_cnt_target1_reach_0_lp_int_clr : WT; bitpos: [19]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_0_lp_int_clr:1; - /** pmu_0p2a_cnt_target0_reach_1_lp_int_clr : WT; bitpos: [20]; default: 0; - * reg_0p2a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p2a_cnt_target0_reach_1_lp_int_clr:1; - /** pmu_0p2a_cnt_target1_reach_1_lp_int_clr : WT; bitpos: [21]; default: 0; - * reg_0p2a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p2a_cnt_target1_reach_1_lp_int_clr:1; - /** pmu_0p3a_cnt_target0_reach_0_lp_int_clr : WT; bitpos: [22]; default: 0; - * reg_0p3a_0 counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_0_lp_int_clr:1; - /** pmu_0p3a_cnt_target1_reach_0_lp_int_clr : WT; bitpos: [23]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_0_lp_int_clr:1; - /** pmu_0p3a_cnt_target0_reach_1_lp_int_clr : WT; bitpos: [24]; default: 0; - * reg_0p3a_0_counter after xpd reach target0 - */ - uint32_t pmu_0p3a_cnt_target0_reach_1_lp_int_clr:1; - /** pmu_0p3a_cnt_target1_reach_1_lp_int_clr : WT; bitpos: [25]; default: 0; - * reg_0p3a_1_counter after xpd reach target1 - */ - uint32_t pmu_0p3a_cnt_target1_reach_1_lp_int_clr:1; - /** lp_cpu_wakeup_int_clr : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_clr:1; - /** sleep_switch_active_end_int_clr : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_clr:1; - /** active_switch_sleep_end_int_clr : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_clr:1; - /** sleep_switch_active_start_int_clr : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_clr:1; - /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_clr:1; - /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_clr:1; - }; - uint32_t val; -} pmu_lp_int_clr_reg_t; - -/** Type of lp_cpu_pwr0 register - * need_des - */ -typedef union { - struct { - /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0; - * need_des - */ - uint32_t lp_cpu_waiti_rdy:1; - /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0; - * need_des - */ - uint32_t lp_cpu_stall_rdy:1; - uint32_t reserved_2:16; - /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0; - * need_des - */ - uint32_t lp_cpu_force_stall:1; - /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_waiti_flag_en:1; - /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1; - * need_des - */ - uint32_t lp_cpu_slp_stall_flag_en:1; - /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255; - * need_des - */ - uint32_t lp_cpu_slp_stall_wait:8; - /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_stall_en:1; - /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_reset_en:1; - /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_bypass_intr_en:1; - }; - uint32_t val; -} pmu_lp_cpu_pwr0_reg_t; - -/** Type of lp_cpu_pwr1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_sleep_req:1; - }; - uint32_t val; -} pmu_lp_cpu_pwr1_reg_t; - -/** Type of lp_cpu_pwr2 register - * need_des - */ -typedef union { - struct { - /** lp_cpu_wakeup_en : R/W; bitpos: [30:0]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_en:31; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_lp_cpu_pwr2_reg_t; - -/** Type of lp_cpu_pwr3 register - * need_des - */ -typedef union { - struct { - /** lp_cpu_wakeup_cause : RO; bitpos: [30:0]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_cause:31; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_lp_cpu_pwr3_reg_t; - -/** Type of lp_cpu_pwr4 register - * need_des - */ -typedef union { - struct { - /** lp_cpu_reject_en : R/W; bitpos: [30:0]; default: 0; - * need_des - */ - uint32_t lp_cpu_reject_en:31; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_lp_cpu_pwr4_reg_t; - -/** Type of lp_cpu_pwr5 register - * need_des - */ -typedef union { - struct { - /** lp_cpu_reject_cause : RO; bitpos: [30:0]; default: 0; - * need_des - */ - uint32_t lp_cpu_reject_cause:31; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_lp_cpu_pwr5_reg_t; - -/** Type of hp_lp_cpu_comm register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** lp_trigger_hp : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_trigger_hp:1; - /** hp_trigger_lp : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_trigger_lp:1; - }; - uint32_t val; -} pmu_hp_lp_cpu_comm_reg_t; - -/** Type of hp_regulator_cfg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t dig_regulator_en_cal:1; - }; - uint32_t val; -} pmu_hp_regulator_cfg_reg_t; - -/** Type of main_state register - * need_des - */ -typedef union { - struct { - /** enable_cali_pmu_cntl : R/W; bitpos: [0]; default: 1; - * need_des - */ - uint32_t enable_cali_pmu_cntl:1; - uint32_t reserved_1:10; - /** pmu_main_last_st_state : RO; bitpos: [17:11]; default: 1; - * need_des - */ - uint32_t pmu_main_last_st_state:7; - /** pmu_main_tar_st_state : RO; bitpos: [24:18]; default: 4; - * need_des - */ - uint32_t pmu_main_tar_st_state:7; - /** pmu_main_cur_st_state : RO; bitpos: [31:25]; default: 1; - * need_des - */ - uint32_t pmu_main_cur_st_state:7; - }; - uint32_t val; -} pmu_main_state_reg_t; - -/** Type of pwr_state register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:13; - /** pmu_backup_st_state : RO; bitpos: [17:13]; default: 1; - * need_des - */ - uint32_t pmu_backup_st_state:5; - /** pmu_lp_pwr_st_state : RO; bitpos: [22:18]; default: 0; - * need_des - */ - uint32_t pmu_lp_pwr_st_state:5; - /** pmu_hp_pwr_st_state : RO; bitpos: [31:23]; default: 1; - * need_des - */ - uint32_t pmu_hp_pwr_st_state:9; - }; - uint32_t val; -} pmu_pwr_state_reg_t; - -/** Type of ext_ldo_p0_0p1a register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** pmu_0p1a_cnt_clr_0 : WT; bitpos: [6]; default: 0; - * need_des - */ - uint32_t pmu_0p1a_cnt_clr_0:1; - /** pmu_0p1a_force_tieh_sel_0 : R/W; bitpos: [7]; default: 0; - * need_des - */ - uint32_t pmu_0p1a_force_tieh_sel_0:1; - /** pmu_0p1a_xpd_0 : R/W; bitpos: [8]; default: 1; - * need_des - */ - uint32_t pmu_0p1a_xpd_0:1; - /** pmu_0p1a_tieh_sel_0 : R/W; bitpos: [11:9]; default: 0; - * need_des - */ - uint32_t pmu_0p1a_tieh_sel_0:3; - /** pmu_0p1a_tieh_pos_en_0 : R/W; bitpos: [12]; default: 0; - * need_des - */ - uint32_t pmu_0p1a_tieh_pos_en_0:1; - /** pmu_0p1a_tieh_neg_en_0 : R/W; bitpos: [13]; default: 0; - * need_des - */ - uint32_t pmu_0p1a_tieh_neg_en_0:1; - /** pmu_0p1a_tieh_0 : R/W; bitpos: [14]; default: 0; - * need_des - */ - uint32_t pmu_0p1a_tieh_0:1; - /** pmu_0p1a_target1_0 : R/W; bitpos: [22:15]; default: 64; - * need_des - */ - uint32_t pmu_0p1a_target1_0:8; - /** pmu_0p1a_target0_0 : R/W; bitpos: [30:23]; default: 128; - * need_des - */ - uint32_t pmu_0p1a_target0_0:8; - /** pmu_0p1a_ldo_cnt_prescaler_sel_0 : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t pmu_0p1a_ldo_cnt_prescaler_sel_0:1; - }; - uint32_t val; -} pmu_ext_ldo_p0_0p1a_reg_t; - -/** Type of ext_ldo_p0_0p1a_ana register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** ana_0p1a_mul_0 : R/W; bitpos: [25:23]; default: 2; - * need_des - */ - uint32_t ana_0p1a_mul_0:3; - /** ana_0p1a_en_vdet_0 : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t ana_0p1a_en_vdet_0:1; - /** ana_0p1a_en_cur_lim_0 : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t ana_0p1a_en_cur_lim_0:1; - /** ana_0p1a_dref_0 : R/W; bitpos: [31:28]; default: 11; - * need_des - */ - uint32_t ana_0p1a_dref_0:4; - }; - uint32_t val; -} pmu_ext_ldo_p0_0p1a_ana_reg_t; - -/** Type of ext_ldo_p0_0p2a register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** pmu_0p2a_cnt_clr_0 : WT; bitpos: [6]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_cnt_clr_0:1; - /** 0p2a_force_tieh_sel_0 : R/W; bitpos: [7]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_force_tieh_sel_0:1; - /** pmu_0p2a_xpd_0 : R/W; bitpos: [8]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_xpd_0:1; - /** pmu_0p2a_tieh_sel_0 : R/W; bitpos: [11:9]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_tieh_sel_0:3; - /** pmu_0p2a_tieh_pos_en_0 : R/W; bitpos: [12]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_tieh_pos_en_0:1; - /** pmu_0p2a_tieh_neg_en_0 : R/W; bitpos: [13]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_tieh_neg_en_0:1; - /** pmu_0p2a_tieh_0 : R/W; bitpos: [14]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_tieh_0:1; - /** pmu_0p2a_target1_0 : R/W; bitpos: [22:15]; default: 64; - * need_des - */ - uint32_t pmu_0p2a_target1_0:8; - /** pmu_0p2a_target0_0 : R/W; bitpos: [30:23]; default: 128; - * need_des - */ - uint32_t pmu_0p2a_target0_0:8; - /** pmu_0p2a_ldo_cnt_prescaler_sel_0 : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_ldo_cnt_prescaler_sel_0:1; - }; - uint32_t val; -} pmu_ext_ldo_p0_0p2a_reg_t; - -/** Type of ext_ldo_p0_0p2a_ana register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** ana_0p2a_mul_0 : R/W; bitpos: [25:23]; default: 0; - * need_des - */ - uint32_t ana_0p2a_mul_0:3; - /** ana_0p2a_en_vdet_0 : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t ana_0p2a_en_vdet_0:1; - /** ana_0p2a_en_cur_lim_0 : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t ana_0p2a_en_cur_lim_0:1; - /** ana_0p2a_dref_0 : R/W; bitpos: [31:28]; default: 10; - * need_des - */ - uint32_t ana_0p2a_dref_0:4; - }; - uint32_t val; -} pmu_ext_ldo_p0_0p2a_ana_reg_t; - -/** Type of ext_ldo_p0_0p3a register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** pmu_0p3a_cnt_clr_0 : WT; bitpos: [6]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_cnt_clr_0:1; - /** pmu_0p3a_force_tieh_sel_0 : R/W; bitpos: [7]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_force_tieh_sel_0:1; - /** pmu_0p3a_xpd_0 : R/W; bitpos: [8]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_xpd_0:1; - /** pmu_0p3a_tieh_sel_0 : R/W; bitpos: [11:9]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_tieh_sel_0:3; - /** pmu_0p3a_tieh_pos_en_0 : R/W; bitpos: [12]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_tieh_pos_en_0:1; - /** pmu_0p3a_tieh_neg_en_0 : R/W; bitpos: [13]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_tieh_neg_en_0:1; - /** pmu_0p3a_tieh_0 : R/W; bitpos: [14]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_tieh_0:1; - /** pmu_0p3a_target1_0 : R/W; bitpos: [22:15]; default: 64; - * need_des - */ - uint32_t pmu_0p3a_target1_0:8; - /** pmu_0p3a_target0_0 : R/W; bitpos: [30:23]; default: 128; - * need_des - */ - uint32_t pmu_0p3a_target0_0:8; - /** pmu_0p3a_ldo_cnt_prescaler_sel_0 : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_ldo_cnt_prescaler_sel_0:1; - }; - uint32_t val; -} pmu_ext_ldo_p0_0p3a_reg_t; - -/** Type of ext_ldo_p0_0p3a_ana register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** ana_0p3a_mul_0 : R/W; bitpos: [25:23]; default: 0; - * need_des - */ - uint32_t ana_0p3a_mul_0:3; - /** ana_0p3a_en_vdet_0 : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t ana_0p3a_en_vdet_0:1; - /** ana_0p3a_en_cur_lim_0 : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t ana_0p3a_en_cur_lim_0:1; - /** ana_0p3a_dref_0 : R/W; bitpos: [31:28]; default: 10; - * need_des - */ - uint32_t ana_0p3a_dref_0:4; - }; - uint32_t val; -} pmu_ext_ldo_p0_0p3a_ana_reg_t; - -/** Type of ext_ldo_p1_0p1a register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** pmu_0p1a_cnt_clr_1 : WT; bitpos: [6]; default: 0; - * need_des - */ - uint32_t pmu_0p1a_cnt_clr_1:1; - /** pmu_0p1a_force_tieh_sel_1 : R/W; bitpos: [7]; default: 0; - * need_des - */ - uint32_t pmu_0p1a_force_tieh_sel_1:1; - /** pmu_0p1a_xpd_1 : R/W; bitpos: [8]; default: 0; - * need_des - */ - uint32_t pmu_0p1a_xpd_1:1; - /** pmu_0p1a_tieh_sel_1 : R/W; bitpos: [11:9]; default: 0; - * need_des - */ - uint32_t pmu_0p1a_tieh_sel_1:3; - /** pmu_0p1a_tieh_pos_en_1 : R/W; bitpos: [12]; default: 0; - * need_des - */ - uint32_t pmu_0p1a_tieh_pos_en_1:1; - /** pmu_0p1a_tieh_neg_en_1 : R/W; bitpos: [13]; default: 0; - * need_des - */ - uint32_t pmu_0p1a_tieh_neg_en_1:1; - /** pmu_0p1a_tieh_1 : R/W; bitpos: [14]; default: 0; - * need_des - */ - uint32_t pmu_0p1a_tieh_1:1; - /** pmu_0p1a_target1_1 : R/W; bitpos: [22:15]; default: 64; - * need_des - */ - uint32_t pmu_0p1a_target1_1:8; - /** pmu_0p1a_target0_1 : R/W; bitpos: [30:23]; default: 128; - * need_des - */ - uint32_t pmu_0p1a_target0_1:8; - /** pmu_0p1a_ldo_cnt_prescaler_sel_1 : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t pmu_0p1a_ldo_cnt_prescaler_sel_1:1; - }; - uint32_t val; -} pmu_ext_ldo_p1_0p1a_reg_t; - -/** Type of ext_ldo_p1_0p1a_ana register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** ana_0p1a_mul_1 : R/W; bitpos: [25:23]; default: 0; - * need_des - */ - uint32_t ana_0p1a_mul_1:3; - /** ana_0p1a_en_vdet_1 : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t ana_0p1a_en_vdet_1:1; - /** ana_0p1a_en_cur_lim_1 : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t ana_0p1a_en_cur_lim_1:1; - /** ana_0p1a_dref_1 : R/W; bitpos: [31:28]; default: 10; - * need_des - */ - uint32_t ana_0p1a_dref_1:4; - }; - uint32_t val; -} pmu_ext_ldo_p1_0p1a_ana_reg_t; - -/** Type of ext_ldo_p1_0p2a register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** pmu_0p2a_cnt_clr_1 : WT; bitpos: [6]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_cnt_clr_1:1; - /** pmu_0p2a_force_tieh_sel_1 : R/W; bitpos: [7]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_force_tieh_sel_1:1; - /** pmu_0p2a_xpd_1 : R/W; bitpos: [8]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_xpd_1:1; - /** pmu_0p2a_tieh_sel_1 : R/W; bitpos: [11:9]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_tieh_sel_1:3; - /** pmu_0p2a_tieh_pos_en_1 : R/W; bitpos: [12]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_tieh_pos_en_1:1; - /** pmu_0p2a_tieh_neg_en_1 : R/W; bitpos: [13]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_tieh_neg_en_1:1; - /** pmu_0p2a_tieh_1 : R/W; bitpos: [14]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_tieh_1:1; - /** pmu_0p2a_target1_1 : R/W; bitpos: [22:15]; default: 64; - * need_des - */ - uint32_t pmu_0p2a_target1_1:8; - /** pmu_0p2a_target0_1 : R/W; bitpos: [30:23]; default: 128; - * need_des - */ - uint32_t pmu_0p2a_target0_1:8; - /** pmu_0p2a_ldo_cnt_prescaler_sel_1 : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t pmu_0p2a_ldo_cnt_prescaler_sel_1:1; - }; - uint32_t val; -} pmu_ext_ldo_p1_0p2a_reg_t; - -/** Type of ext_ldo_p1_0p2a_ana register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** ana_0p2a_mul_1 : R/W; bitpos: [25:23]; default: 0; - * need_des - */ - uint32_t ana_0p2a_mul_1:3; - /** ana_0p2a_en_vdet_1 : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t ana_0p2a_en_vdet_1:1; - /** ana_0p2a_en_cur_lim_1 : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t ana_0p2a_en_cur_lim_1:1; - /** ana_0p2a_dref_1 : R/W; bitpos: [31:28]; default: 10; - * need_des - */ - uint32_t ana_0p2a_dref_1:4; - }; - uint32_t val; -} pmu_ext_ldo_p1_0p2a_ana_reg_t; - -/** Type of ext_ldo_p1_0p3a register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** pmu_0p3a_cnt_clr_1 : WT; bitpos: [6]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_cnt_clr_1:1; - /** pmu_0p3a_force_tieh_sel_1 : R/W; bitpos: [7]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_force_tieh_sel_1:1; - /** pmu_0p3a_xpd_1 : R/W; bitpos: [8]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_xpd_1:1; - /** pmu_0p3a_tieh_sel_1 : R/W; bitpos: [11:9]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_tieh_sel_1:3; - /** pmu_0p3a_tieh_pos_en_1 : R/W; bitpos: [12]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_tieh_pos_en_1:1; - /** pmu_0p3a_tieh_neg_en_1 : R/W; bitpos: [13]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_tieh_neg_en_1:1; - /** pmu_0p3a_tieh_1 : R/W; bitpos: [14]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_tieh_1:1; - /** pmu_0p3a_target1_1 : R/W; bitpos: [22:15]; default: 64; - * need_des - */ - uint32_t pmu_0p3a_target1_1:8; - /** pmu_0p3a_target0_1 : R/W; bitpos: [30:23]; default: 128; - * need_des - */ - uint32_t pmu_0p3a_target0_1:8; - /** pmu_0p3a_ldo_cnt_prescaler_sel_1 : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t pmu_0p3a_ldo_cnt_prescaler_sel_1:1; - }; - uint32_t val; -} pmu_ext_ldo_p1_0p3a_reg_t; - -/** Type of ext_ldo_p1_0p3a_ana register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** ana_0p3a_mul_1 : R/W; bitpos: [25:23]; default: 0; - * need_des - */ - uint32_t ana_0p3a_mul_1:3; - /** ana_0p3a_en_vdet_1 : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t ana_0p3a_en_vdet_1:1; - /** ana_0p3a_en_cur_lim_1 : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t ana_0p3a_en_cur_lim_1:1; - /** ana_0p3a_dref_1 : R/W; bitpos: [31:28]; default: 10; - * need_des - */ - uint32_t ana_0p3a_dref_1:4; - }; - uint32_t val; -} pmu_ext_ldo_p1_0p3a_ana_reg_t; - -/** Type of ext_wakeup_lv register - * need_des - */ -typedef union { - struct { - /** ext_wakeup_lv : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t ext_wakeup_lv:32; - }; - uint32_t val; -} pmu_ext_wakeup_lv_reg_t; - -/** Type of ext_wakeup_sel register - * need_des - */ -typedef union { - struct { - /** ext_wakeup_sel : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t ext_wakeup_sel:32; - }; - uint32_t val; -} pmu_ext_wakeup_sel_reg_t; - -/** Type of ext_wakeup_st register - * need_des - */ -typedef union { - struct { - /** ext_wakeup_status : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t ext_wakeup_status:32; - }; - uint32_t val; -} pmu_ext_wakeup_st_reg_t; - -/** Type of ext_wakeup_cntl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** ext_wakeup_status_clr : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t ext_wakeup_status_clr:1; - /** ext_wakeup_filter : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t ext_wakeup_filter:1; - }; - uint32_t val; -} pmu_ext_wakeup_cntl_reg_t; - -/** Type of sdio_wakeup_cntl register - * need_des - */ -typedef union { - struct { - /** sdio_act_dnum : R/W; bitpos: [9:0]; default: 1023; - * need_des - */ - uint32_t sdio_act_dnum:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} pmu_sdio_wakeup_cntl_reg_t; - -/** Type of cpu_sw_stall register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** hpcore1_sw_stall_code : R/W; bitpos: [23:16]; default: 0; - * need_des - */ - uint32_t hpcore1_sw_stall_code:8; - /** hpcore0_sw_stall_code : R/W; bitpos: [31:24]; default: 0; - * need_des - */ - uint32_t hpcore0_sw_stall_code:8; - }; - uint32_t val; -} pmu_cpu_sw_stall_reg_t; - -/** Type of dcm_ctrl register - * need_des - */ -typedef union { - struct { - /** dcdc_on_req : WT; bitpos: [0]; default: 0; - * SW trigger dcdc on - */ - uint32_t dcdc_on_req:1; - /** dcdc_off_req : WT; bitpos: [1]; default: 0; - * SW trigger dcdc off - */ - uint32_t dcdc_off_req:1; - /** dcdc_lightslp_req : WT; bitpos: [2]; default: 0; - * SW trigger dcdc enter lightsleep - */ - uint32_t dcdc_lightslp_req:1; - /** dcdc_deepslp_req : WT; bitpos: [3]; default: 0; - * SW trigger dcdc enter deepsleep - */ - uint32_t dcdc_deepslp_req:1; - uint32_t reserved_4:3; - /** dcdc_done_force : R/W; bitpos: [7]; default: 0; - * need_des - */ - uint32_t dcdc_done_force:1; - /** dcdc_on_force_pu : R/W; bitpos: [8]; default: 0; - * need_des - */ - uint32_t dcdc_on_force_pu:1; - /** dcdc_on_force_pd : R/W; bitpos: [9]; default: 0; - * need_des - */ - uint32_t dcdc_on_force_pd:1; - /** dcdc_fb_res_force_pu : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t dcdc_fb_res_force_pu:1; - /** dcdc_fb_res_force_pd : R/W; bitpos: [11]; default: 0; - * need_des - */ - uint32_t dcdc_fb_res_force_pd:1; - /** dcdc_ls_force_pu : R/W; bitpos: [12]; default: 0; - * need_des - */ - uint32_t dcdc_ls_force_pu:1; - /** dcdc_ls_force_pd : R/W; bitpos: [13]; default: 0; - * need_des - */ - uint32_t dcdc_ls_force_pd:1; - /** dcdc_ds_force_pu : R/W; bitpos: [14]; default: 0; - * need_des - */ - uint32_t dcdc_ds_force_pu:1; - /** dcdc_ds_force_pd : R/W; bitpos: [15]; default: 0; - * need_des - */ - uint32_t dcdc_ds_force_pd:1; - /** dcm_cur_st : RO; bitpos: [23:16]; default: 1; - * need_des - */ - uint32_t dcm_cur_st:8; - uint32_t reserved_24:5; - /** dcdc_en_amux_test : R/W; bitpos: [29]; default: 0; - * Enable analog mux to pull PAD TEST_DCDC voltage signal - */ - uint32_t dcdc_en_amux_test:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} pmu_dcm_ctrl_reg_t; - -/** Type of dcm_wait_delay register - * need_des - */ -typedef union { - struct { - /** dcdc_pre_delay : R/W; bitpos: [7:0]; default: 5; - * DCDC pre-on/post off delay - */ - uint32_t dcdc_pre_delay:8; - /** dcdc_res_off_delay : R/W; bitpos: [15:8]; default: 2; - * DCDC fb res off delay - */ - uint32_t dcdc_res_off_delay:8; - /** dcdc_stable_delay : R/W; bitpos: [25:16]; default: 75; - * DCDC stable delay - */ - uint32_t dcdc_stable_delay:10; - uint32_t reserved_26:6; - }; - uint32_t val; -} pmu_dcm_wait_delay_reg_t; - -/** Type of vddbat_cfg register - * need_des - */ -typedef union { - struct { - /** ana_vddbat_mode : RO; bitpos: [1:0]; default: 0; - * need_des - */ - uint32_t ana_vddbat_mode:2; - uint32_t reserved_2:29; - /** vddbat_sw_update : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t vddbat_sw_update:1; - }; - uint32_t val; -} pmu_vddbat_cfg_reg_t; - -/** Type of touch_pwr_cntl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** touch_wait_cycles : R/W; bitpos: [13:5]; default: 10; - * need_des - */ - uint32_t touch_wait_cycles:9; - /** touch_sleep_cycles : R/W; bitpos: [29:14]; default: 100; - * need_des - */ - uint32_t touch_sleep_cycles:16; - /** touch_force_done : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t touch_force_done:1; - /** touch_sleep_timer_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t touch_sleep_timer_en:1; - }; - uint32_t val; -} pmu_touch_pwr_cntl_reg_t; - -/** Type of rdn_eco register - * need_des - */ -typedef union { - struct { - /** pmu_rdn_eco_result : RO; bitpos: [0]; default: 0; - * need_des - */ - uint32_t pmu_rdn_eco_result:1; - uint32_t reserved_1:30; - /** pmu_rdn_eco_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t pmu_rdn_eco_en:1; - }; - uint32_t val; -} pmu_rdn_eco_reg_t; - -/** Type of power_pd_hp_cpu_cntl register - * need_des - */ -typedef union { - struct { - /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_reset:1; - /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_iso:1; - /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_pu:1; - /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_no_reset:1; - /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_no_iso:1; - /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_pd:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} pmu_power_pd_hp_cpu_cntl_reg_t; - -/** Type of power_pd_hp_cpu_mask register - * need_des - */ -typedef union { - struct { - /** xpd_hp_cpu_mask : R/W; bitpos: [4:0]; default: 0; - * need_des - */ - uint32_t xpd_hp_cpu_mask:5; - uint32_t reserved_5:22; - /** pd_hp_cpu_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_cpu_mask:5; - }; - uint32_t val; -} pmu_power_pd_hp_cpu_mask_reg_t; - -/** Type of date register - * need_des - */ -typedef union { - struct { - /** pmu_date : R/W; bitpos: [30:0]; default: 38801456; - * need_des - */ - uint32_t pmu_date:31; - /** clk_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t clk_en:1; - }; - uint32_t val; -} pmu_date_reg_t; - - -/** Group: status_register */ -/** Type of clk_state0 register - * need_des - */ -typedef union { - struct { - /** stable_xpd_pll_state : RO; bitpos: [2:0]; default: 0; - * need_des - */ - uint32_t stable_xpd_pll_state:3; - /** stable_xpd_xtal_state : RO; bitpos: [3]; default: 0; - * need_des - */ - uint32_t stable_xpd_xtal_state:1; - /** pmu_ana_xpd_pll_i2c_state : RO; bitpos: [6:4]; default: 0; - * need_des - */ - uint32_t pmu_ana_xpd_pll_i2c_state:3; - uint32_t reserved_7:3; - /** pmu_sys_clk_slp_sel_state : RO; bitpos: [10]; default: 0; - * need_des - */ - uint32_t pmu_sys_clk_slp_sel_state:1; - /** pmu_sys_clk_sel_state : RO; bitpos: [12:11]; default: 0; - * need_des - */ - uint32_t pmu_sys_clk_sel_state:2; - /** pmu_sys_clk_no_div_state : RO; bitpos: [13]; default: 0; - * need_des - */ - uint32_t pmu_sys_clk_no_div_state:1; - /** pmu_icg_sys_clk_en_state : RO; bitpos: [14]; default: 1; - * need_des - */ - uint32_t pmu_icg_sys_clk_en_state:1; - /** pmu_icg_modem_switch_state : RO; bitpos: [15]; default: 0; - * need_des - */ - uint32_t pmu_icg_modem_switch_state:1; - /** pmu_icg_modem_code_state : RO; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t pmu_icg_modem_code_state:2; - /** pmu_icg_slp_sel_state : RO; bitpos: [18]; default: 0; - * need_des - */ - uint32_t pmu_icg_slp_sel_state:1; - /** pmu_icg_global_xtal_state : RO; bitpos: [19]; default: 0; - * need_des - */ - uint32_t pmu_icg_global_xtal_state:1; - /** pmu_icg_global_pll_state : RO; bitpos: [23:20]; default: 0; - * need_des - */ - uint32_t pmu_icg_global_pll_state:4; - /** pmu_ana_i2c_iso_en_state : RO; bitpos: [24]; default: 0; - * need_des - */ - uint32_t pmu_ana_i2c_iso_en_state:1; - /** pmu_ana_i2c_retention_state : RO; bitpos: [25]; default: 0; - * need_des - */ - uint32_t pmu_ana_i2c_retention_state:1; - uint32_t reserved_26:1; - /** pmu_ana_xpd_pll_state : RO; bitpos: [30:27]; default: 0; - * need_des - */ - uint32_t pmu_ana_xpd_pll_state:4; - /** pmu_ana_xpd_xtal_state : RO; bitpos: [31]; default: 1; - * need_des - */ - uint32_t pmu_ana_xpd_xtal_state:1; - }; - uint32_t val; -} pmu_clk_state0_reg_t; - -/** Type of clk_state1 register - * need_des - */ -typedef union { - struct { - /** pmu_icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t pmu_icg_func_en_state:32; - }; - uint32_t val; -} pmu_clk_state1_reg_t; - -/** Type of clk_state2 register - * need_des - */ -typedef union { - struct { - /** pmu_icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t pmu_icg_apb_en_state:32; - }; - uint32_t val; -} pmu_clk_state2_reg_t; - -/** Type of xtal_slp register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** xtal_slp_cnt_target : R/W; bitpos: [31:16]; default: 15; - * need_des - */ - uint32_t xtal_slp_cnt_target:16; - }; - uint32_t val; -} pmu_xtal_slp_reg_t; - - -typedef struct { - volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power; - volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func; - volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb; - volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem; - volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl; - volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power; - volatile pmu_hp_active_bias_reg_t hp_active_bias; - volatile pmu_hp_active_backup_reg_t hp_active_backup; - volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk; - volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk; - volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0; - volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1; - volatile pmu_hp_active_xtal_reg_t hp_active_xtal; - volatile pmu_hp_modem_dig_power_reg_t hp_modem_dig_power; - volatile pmu_hp_modem_icg_hp_func_reg_t hp_modem_icg_hp_func; - volatile pmu_hp_modem_icg_hp_apb_reg_t hp_modem_icg_hp_apb; - volatile pmu_hp_modem_icg_modem_reg_t hp_modem_icg_modem; - volatile pmu_hp_modem_hp_sys_cntl_reg_t hp_modem_hp_sys_cntl; - volatile pmu_hp_modem_hp_ck_power_reg_t hp_modem_hp_ck_power; - volatile pmu_hp_modem_bias_reg_t hp_modem_bias; - volatile pmu_hp_modem_backup_reg_t hp_modem_backup; - volatile pmu_hp_modem_backup_clk_reg_t hp_modem_backup_clk; - volatile pmu_hp_modem_sysclk_reg_t hp_modem_sysclk; - volatile pmu_hp_modem_hp_regulator0_reg_t hp_modem_hp_regulator0; - volatile pmu_hp_modem_hp_regulator1_reg_t hp_modem_hp_regulator1; - volatile pmu_hp_modem_xtal_reg_t hp_modem_xtal; - volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power; - volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func; - volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb; - volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem; - volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl; - volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power; - volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias; - volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup; - volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk; - volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk; - volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0; - volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1; - volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal; - volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0; - volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1; - uint32_t reserved_0a4; - volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power; - volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power; - uint32_t reserved_0b0; - volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0; - volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1; - volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal; - volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power; - volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power; - volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias; - volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power; - volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk; - volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg; - volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg; - volatile pmu_imm_modem_icg_reg_t imm_modem_icg; - volatile pmu_imm_lp_icg_reg_t imm_lp_icg; - volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all; - volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso; - volatile pmu_power_wait_timer0_reg_t power_wait_timer0; - volatile pmu_power_wait_timer1_reg_t power_wait_timer1; - volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl; - volatile pmu_power_pd_cnnt_cntl_reg_t power_pd_cnnt_cntl; - volatile pmu_power_pd_hpmem_cntl_reg_t power_pd_hpmem_cntl; - volatile pmu_power_pd_top_mask_reg_t power_pd_top_mask; - volatile pmu_power_pd_cnnt_mask_reg_t power_pd_cnnt_mask; - volatile pmu_power_pd_hpmem_mask_reg_t power_pd_hpmem_mask; - volatile pmu_power_dcdc_switch_reg_t power_dcdc_switch; - volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl; - volatile pmu_power_pd_lpperi_mask_reg_t power_pd_lpperi_mask; - volatile pmu_power_hp_pad_reg_t power_hp_pad; - volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl; - volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0; - volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1; - volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2; - volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3; - volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4; - volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5; - volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6; - volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7; - volatile pmu_slp_wakeup_cntl8_reg_t slp_wakeup_cntl8; - volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0; - volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1; - volatile pmu_slp_wakeup_status2_reg_t slp_wakeup_status2; - volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron; - volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl; - volatile pmu_por_status_reg_t por_status; - volatile pmu_rf_pwc_reg_t rf_pwc; - volatile pmu_backup_cfg_reg_t backup_cfg; - volatile pmu_int_raw_reg_t int_raw; - volatile pmu_hp_int_st_reg_t hp_int_st; - volatile pmu_hp_int_ena_reg_t hp_int_ena; - volatile pmu_hp_int_clr_reg_t hp_int_clr; - volatile pmu_lp_int_raw_reg_t lp_int_raw; - volatile pmu_lp_int_st_reg_t lp_int_st; - volatile pmu_lp_int_ena_reg_t lp_int_ena; - volatile pmu_lp_int_clr_reg_t lp_int_clr; - volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0; - volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1; - volatile pmu_lp_cpu_pwr2_reg_t lp_cpu_pwr2; - volatile pmu_lp_cpu_pwr3_reg_t lp_cpu_pwr3; - volatile pmu_lp_cpu_pwr4_reg_t lp_cpu_pwr4; - volatile pmu_lp_cpu_pwr5_reg_t lp_cpu_pwr5; - volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; - volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; - volatile pmu_main_state_reg_t main_state; - volatile pmu_pwr_state_reg_t pwr_state; - volatile pmu_clk_state0_reg_t clk_state0; - volatile pmu_clk_state1_reg_t clk_state1; - volatile pmu_clk_state2_reg_t clk_state2; - volatile pmu_ext_ldo_p0_0p1a_reg_t ext_ldo_p0_0p1a; - volatile pmu_ext_ldo_p0_0p1a_ana_reg_t ext_ldo_p0_0p1a_ana; - volatile pmu_ext_ldo_p0_0p2a_reg_t ext_ldo_p0_0p2a; - volatile pmu_ext_ldo_p0_0p2a_ana_reg_t ext_ldo_p0_0p2a_ana; - volatile pmu_ext_ldo_p0_0p3a_reg_t ext_ldo_p0_0p3a; - volatile pmu_ext_ldo_p0_0p3a_ana_reg_t ext_ldo_p0_0p3a_ana; - volatile pmu_ext_ldo_p1_0p1a_reg_t ext_ldo_p1_0p1a; - volatile pmu_ext_ldo_p1_0p1a_ana_reg_t ext_ldo_p1_0p1a_ana; - volatile pmu_ext_ldo_p1_0p2a_reg_t ext_ldo_p1_0p2a; - volatile pmu_ext_ldo_p1_0p2a_ana_reg_t ext_ldo_p1_0p2a_ana; - volatile pmu_ext_ldo_p1_0p3a_reg_t ext_ldo_p1_0p3a; - volatile pmu_ext_ldo_p1_0p3a_ana_reg_t ext_ldo_p1_0p3a_ana; - volatile pmu_ext_wakeup_lv_reg_t ext_wakeup_lv; - volatile pmu_ext_wakeup_sel_reg_t ext_wakeup_sel; - volatile pmu_ext_wakeup_st_reg_t ext_wakeup_st; - volatile pmu_ext_wakeup_cntl_reg_t ext_wakeup_cntl; - volatile pmu_sdio_wakeup_cntl_reg_t sdio_wakeup_cntl; - volatile pmu_xtal_slp_reg_t xtal_slp; - volatile pmu_cpu_sw_stall_reg_t cpu_sw_stall; - volatile pmu_dcm_ctrl_reg_t dcm_ctrl; - volatile pmu_dcm_wait_delay_reg_t dcm_wait_delay; - volatile pmu_vddbat_cfg_reg_t vddbat_cfg; - volatile pmu_touch_pwr_cntl_reg_t touch_pwr_cntl; - volatile pmu_rdn_eco_reg_t rdn_eco; - volatile pmu_power_pd_hp_cpu_cntl_reg_t power_pd_hp_cpu_cntl; - volatile pmu_power_pd_hp_cpu_mask_reg_t power_pd_hp_cpu_mask; - uint32_t reserved_220[119]; - volatile pmu_date_reg_t date; -} pmu_dev_t; - -extern pmu_dev_t PMU; - -#ifndef __cplusplus -_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pmu_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/pmu_reg.h index bb17970949df..6c120a7046b2 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/pmu_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/pmu_reg.h @@ -11,8 +11,6 @@ extern "C" { #endif -//TODO: IDF-13420 - /** PMU_HP_ACTIVE_DIG_POWER_REG register * need_des */ @@ -38,6 +36,13 @@ extern "C" { #define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_M (PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V << PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S) #define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V 0x00000001U #define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_M (PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V << PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S 29 /** PMU_HP_ACTIVE_PD_CNNT_PD_EN : R/W; bitpos: [30]; default: 0; * need_des */ @@ -514,7 +519,7 @@ extern "C" { * need_des */ #define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38) -/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : WT; bitpos: [31:0]; default: 4294967295; +/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : WT; bitpos: [31:0]; default: 0; * need_des */ #define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU @@ -526,7 +531,7 @@ extern "C" { * need_des */ #define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c) -/** PMU_HP_MODEM_DIG_ICG_APB_EN : WT; bitpos: [31:0]; default: 4294967295; +/** PMU_HP_MODEM_DIG_ICG_APB_EN : WT; bitpos: [31:0]; default: 0; * need_des */ #define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU @@ -637,7 +642,7 @@ extern "C" { * need_des */ #define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) -/** PMU_HP_MODEM_DCM_VSET : WT; bitpos: [22:18]; default: 20; +/** PMU_HP_MODEM_DCM_VSET : WT; bitpos: [22:18]; default: 0; * need_des */ #define PMU_HP_MODEM_DCM_VSET 0x0000001FU @@ -783,42 +788,42 @@ extern "C" { * need_des */ #define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c) -/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : WT; bitpos: [16]; default: 1; +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : WT; bitpos: [16]; default: 0; * need_des */ #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S) #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16 -/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : WT; bitpos: [17]; default: 1; +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : WT; bitpos: [17]; default: 0; * need_des */ #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S) #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17 -/** PMU_HP_MODEM_HP_REGULATOR_XPD : WT; bitpos: [18]; default: 1; +/** PMU_HP_MODEM_HP_REGULATOR_XPD : WT; bitpos: [18]; default: 0; * need_des */ #define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18)) #define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S) #define PMU_HP_MODEM_HP_REGULATOR_XPD_V 0x00000001U #define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18 -/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : WT; bitpos: [22:19]; default: 12; +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : WT; bitpos: [22:19]; default: 0; * need_des */ #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S) #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19 -/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : WT; bitpos: [26:23]; default: 12; +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : WT; bitpos: [26:23]; default: 0; * need_des */ #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S) #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 -/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : WT; bitpos: [31:27]; default: 24; +/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : WT; bitpos: [31:27]; default: 0; * need_des */ #define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU @@ -842,7 +847,7 @@ extern "C" { * need_des */ #define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) -/** PMU_HP_MODEM_XPD_XTAL : WT; bitpos: [31]; default: 1; +/** PMU_HP_MODEM_XPD_XTAL : WT; bitpos: [31]; default: 0; * need_des */ #define PMU_HP_MODEM_XPD_XTAL (BIT(31)) @@ -875,6 +880,13 @@ extern "C" { #define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_M (PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V << PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S) #define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V 0x00000001U #define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_M (PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V << PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S 29 /** PMU_HP_SLEEP_PD_CNNT_PD_EN : R/W; bitpos: [30]; default: 0; * need_des */ @@ -1310,6 +1322,18 @@ extern "C" { #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000003FU #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 26 +/** PMU_HP_SLEEP_LP_DCDC_RESERVE_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_REG (DR_REG_PMU_BASE + 0xa4) +/** PMU_PMU_HP_SLEEP_LP_DCDC_RESERVE : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_PMU_HP_SLEEP_LP_DCDC_RESERVE 0xFFFFFFFFU +#define PMU_PMU_HP_SLEEP_LP_DCDC_RESERVE_M (PMU_PMU_HP_SLEEP_LP_DCDC_RESERVE_V << PMU_PMU_HP_SLEEP_LP_DCDC_RESERVE_S) +#define PMU_PMU_HP_SLEEP_LP_DCDC_RESERVE_V 0xFFFFFFFFU +#define PMU_PMU_HP_SLEEP_LP_DCDC_RESERVE_S 0 + /** PMU_HP_SLEEP_LP_DIG_POWER_REG register * need_des */ @@ -1390,6 +1414,18 @@ extern "C" { #define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U #define PMU_HP_SLEEP_PD_OSC_CLK_S 31 +/** PMU_LP_SLEEP_LP_BIAS_RESERVE_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_REG (DR_REG_PMU_BASE + 0xb0) +/** PMU_PMU_LP_SLEEP_LP_BIAS_RESERVE : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_PMU_LP_SLEEP_LP_BIAS_RESERVE 0xFFFFFFFFU +#define PMU_PMU_LP_SLEEP_LP_BIAS_RESERVE_M (PMU_PMU_LP_SLEEP_LP_BIAS_RESERVE_V << PMU_PMU_LP_SLEEP_LP_BIAS_RESERVE_S) +#define PMU_PMU_LP_SLEEP_LP_BIAS_RESERVE_V 0xFFFFFFFFU +#define PMU_PMU_LP_SLEEP_LP_BIAS_RESERVE_S 0 + /** PMU_LP_SLEEP_LP_REGULATOR0_REG register * need_des */ @@ -1571,7 +1607,7 @@ extern "C" { #define PMU_TIE_LOW_CALI_XTAL_ICG_M (PMU_TIE_LOW_CALI_XTAL_ICG_V << PMU_TIE_LOW_CALI_XTAL_ICG_S) #define PMU_TIE_LOW_CALI_XTAL_ICG_V 0x00000001U #define PMU_TIE_LOW_CALI_XTAL_ICG_S 0 -/** PMU_TIE_LOW_GLOBAL_CPLL_ICG : WT; bitpos: [1]; default: 0; +/** PMU_TIE_LOW_GLOBAL_PLL_ICG : WT; bitpos: [4:1]; default: 0; * need_des */ #define PMU_TIE_LOW_GLOBAL_CPLL_ICG (BIT(1)) @@ -2429,6 +2465,13 @@ extern "C" { #define PMU_MODEM_WAIT_TARGET_M (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S) #define PMU_MODEM_WAIT_TARGET_V 0x000FFFFFU #define PMU_MODEM_WAIT_TARGET_S 0 +/** PMU_LP_ANA_WAIT_TARGET_EXPAND : R/W; bitpos: [23:22]; default: 0; + * need_des + */ +#define PMU_LP_ANA_WAIT_TARGET_EXPAND 0x00000003U +#define PMU_LP_ANA_WAIT_TARGET_EXPAND_M (PMU_LP_ANA_WAIT_TARGET_EXPAND_V << PMU_LP_ANA_WAIT_TARGET_EXPAND_S) +#define PMU_LP_ANA_WAIT_TARGET_EXPAND_V 0x00000003U +#define PMU_LP_ANA_WAIT_TARGET_EXPAND_S 22 /** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1; * need_des */ @@ -2551,7 +2594,7 @@ extern "C" { * need_des */ #define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x158) -/** PMU_POR_DONE : RO; bitpos: [31]; default: 1; +/** PMU_POR_DONE : RO; bitpos: [31]; default: 0; * need_des */ #define PMU_POR_DONE (BIT(31)) @@ -3857,7 +3900,7 @@ extern "C" { #define PMU_PMU_MAIN_TAR_ST_STATE_M (PMU_PMU_MAIN_TAR_ST_STATE_V << PMU_PMU_MAIN_TAR_ST_STATE_S) #define PMU_PMU_MAIN_TAR_ST_STATE_V 0x0000007FU #define PMU_PMU_MAIN_TAR_ST_STATE_S 18 -/** PMU_PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 4; +/** PMU_PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 1; * need_des */ #define PMU_PMU_MAIN_CUR_ST_STATE 0x0000007FU @@ -3895,14 +3938,14 @@ extern "C" { * need_des */ #define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x1ac) -/** PMU_STABLE_XPD_PLL_STATE : RO; bitpos: [2:0]; default: 7; +/** PMU_STABLE_XPD_PLL_STATE : RO; bitpos: [2:0]; default: 0; * need_des */ #define PMU_STABLE_XPD_PLL_STATE 0x00000007U #define PMU_STABLE_XPD_PLL_STATE_M (PMU_STABLE_XPD_PLL_STATE_V << PMU_STABLE_XPD_PLL_STATE_S) #define PMU_STABLE_XPD_PLL_STATE_V 0x00000007U #define PMU_STABLE_XPD_PLL_STATE_S 0 -/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [3]; default: 1; +/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [3]; default: 0; * need_des */ #define PMU_STABLE_XPD_XTAL_STATE (BIT(3)) @@ -3937,7 +3980,7 @@ extern "C" { #define PMU_PMU_SYS_CLK_NO_DIV_STATE_M (PMU_PMU_SYS_CLK_NO_DIV_STATE_V << PMU_PMU_SYS_CLK_NO_DIV_STATE_S) #define PMU_PMU_SYS_CLK_NO_DIV_STATE_V 0x00000001U #define PMU_PMU_SYS_CLK_NO_DIV_STATE_S 13 -/** PMU_PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [14]; default: 0; +/** PMU_PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [14]; default: 1; * need_des */ #define PMU_PMU_ICG_SYS_CLK_EN_STATE (BIT(14)) @@ -4000,7 +4043,7 @@ extern "C" { #define PMU_PMU_ANA_XPD_PLL_STATE_M (PMU_PMU_ANA_XPD_PLL_STATE_V << PMU_PMU_ANA_XPD_PLL_STATE_S) #define PMU_PMU_ANA_XPD_PLL_STATE_V 0x0000000FU #define PMU_PMU_ANA_XPD_PLL_STATE_S 27 -/** PMU_PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 0; +/** PMU_PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 1; * need_des */ #define PMU_PMU_ANA_XPD_XTAL_STATE (BIT(31)) @@ -4036,6 +4079,13 @@ extern "C" { * need_des */ #define PMU_EXT_LDO_P0_0P1A_REG (DR_REG_PMU_BASE + 0x1b8) +/** PMU_0P1A_CNT_CLR_0 : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_0P1A_CNT_CLR_0 (BIT(6)) +#define PMU_0P1A_CNT_CLR_0_M (PMU_0P1A_CNT_CLR_0_V << PMU_0P1A_CNT_CLR_0_S) +#define PMU_0P1A_CNT_CLR_0_V 0x00000001U +#define PMU_0P1A_CNT_CLR_0_S 6 /** PMU_0P1A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0; * need_des */ @@ -4137,6 +4187,13 @@ extern "C" { * need_des */ #define PMU_EXT_LDO_P0_0P2A_REG (DR_REG_PMU_BASE + 0x1c0) +/** PMU_0P2A_CNT_CLR_0 : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_0P2A_CNT_CLR_0 (BIT(6)) +#define PMU_0P2A_CNT_CLR_0_M (PMU_0P2A_CNT_CLR_0_V << PMU_0P2A_CNT_CLR_0_S) +#define PMU_0P2A_CNT_CLR_0_V 0x00000001U +#define PMU_0P2A_CNT_CLR_0_S 6 /** PMU_0P2A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0; * need_des */ @@ -4238,6 +4295,13 @@ extern "C" { * need_des */ #define PMU_EXT_LDO_P0_0P3A_REG (DR_REG_PMU_BASE + 0x1c8) +/** PMU_0P3A_CNT_CLR_0 : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_0P3A_CNT_CLR_0 (BIT(6)) +#define PMU_0P3A_CNT_CLR_0_M (PMU_0P3A_CNT_CLR_0_V << PMU_0P3A_CNT_CLR_0_S) +#define PMU_0P3A_CNT_CLR_0_V 0x00000001U +#define PMU_0P3A_CNT_CLR_0_S 6 /** PMU_0P3A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0; * need_des */ @@ -4339,6 +4403,13 @@ extern "C" { * need_des */ #define PMU_EXT_LDO_P1_0P1A_REG (DR_REG_PMU_BASE + 0x1d0) +/** PMU_0P1A_CNT_CLR_1 : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_0P1A_CNT_CLR_1 (BIT(6)) +#define PMU_0P1A_CNT_CLR_1_M (PMU_0P1A_CNT_CLR_1_V << PMU_0P1A_CNT_CLR_1_S) +#define PMU_0P1A_CNT_CLR_1_V 0x00000001U +#define PMU_0P1A_CNT_CLR_1_S 6 /** PMU_0P1A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0; * need_des */ @@ -4440,6 +4511,13 @@ extern "C" { * need_des */ #define PMU_EXT_LDO_P1_0P2A_REG (DR_REG_PMU_BASE + 0x1d8) +/** PMU_0P2A_CNT_CLR_1 : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_0P2A_CNT_CLR_1 (BIT(6)) +#define PMU_0P2A_CNT_CLR_1_M (PMU_0P2A_CNT_CLR_1_V << PMU_0P2A_CNT_CLR_1_S) +#define PMU_0P2A_CNT_CLR_1_V 0x00000001U +#define PMU_0P2A_CNT_CLR_1_S 6 /** PMU_0P2A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0; * need_des */ @@ -4541,6 +4619,13 @@ extern "C" { * need_des */ #define PMU_EXT_LDO_P1_0P3A_REG (DR_REG_PMU_BASE + 0x1e0) +/** PMU_0P3A_CNT_CLR_1 : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_0P3A_CNT_CLR_1 (BIT(6)) +#define PMU_0P3A_CNT_CLR_1_M (PMU_0P3A_CNT_CLR_1_V << PMU_0P3A_CNT_CLR_1_S) +#define PMU_0P3A_CNT_CLR_1_V 0x00000001U +#define PMU_0P3A_CNT_CLR_1_S 6 /** PMU_0P3A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0; * need_des */ @@ -4943,11 +5028,77 @@ extern "C" { #define PMU_PMU_RDN_ECO_EN_V 0x00000001U #define PMU_PMU_RDN_ECO_EN_S 31 +/** PMU_POWER_PD_HP_CPU_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HP_CPU_CNTL_REG (DR_REG_PMU_BASE + 0x218) +/** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_RESET (BIT(0)) +#define PMU_FORCE_HP_CPU_RESET_M (PMU_FORCE_HP_CPU_RESET_V << PMU_FORCE_HP_CPU_RESET_S) +#define PMU_FORCE_HP_CPU_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_RESET_S 0 +/** PMU_FORCE_HP_CPU_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_ISO (BIT(1)) +#define PMU_FORCE_HP_CPU_ISO_M (PMU_FORCE_HP_CPU_ISO_V << PMU_FORCE_HP_CPU_ISO_S) +#define PMU_FORCE_HP_CPU_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_ISO_S 1 +/** PMU_FORCE_HP_CPU_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_PU (BIT(2)) +#define PMU_FORCE_HP_CPU_PU_M (PMU_FORCE_HP_CPU_PU_V << PMU_FORCE_HP_CPU_PU_S) +#define PMU_FORCE_HP_CPU_PU_V 0x00000001U +#define PMU_FORCE_HP_CPU_PU_S 2 +/** PMU_FORCE_HP_CPU_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_CPU_NO_RESET_M (PMU_FORCE_HP_CPU_NO_RESET_V << PMU_FORCE_HP_CPU_NO_RESET_S) +#define PMU_FORCE_HP_CPU_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_RESET_S 3 +/** PMU_FORCE_HP_CPU_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_CPU_NO_ISO_M (PMU_FORCE_HP_CPU_NO_ISO_V << PMU_FORCE_HP_CPU_NO_ISO_S) +#define PMU_FORCE_HP_CPU_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_ISO_S 4 +/** PMU_FORCE_HP_CPU_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_PD (BIT(5)) +#define PMU_FORCE_HP_CPU_PD_M (PMU_FORCE_HP_CPU_PD_V << PMU_FORCE_HP_CPU_PD_S) +#define PMU_FORCE_HP_CPU_PD_V 0x00000001U +#define PMU_FORCE_HP_CPU_PD_S 5 + +/** PMU_POWER_PD_HP_CPU_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_HP_CPU_MASK_REG (DR_REG_PMU_BASE + 0x21c) +/** PMU_XPD_HP_CPU_MASK : R/W; bitpos: [4:0]; default: 0; + * need_des + */ +#define PMU_XPD_HP_CPU_MASK 0x0000001FU +#define PMU_XPD_HP_CPU_MASK_M (PMU_XPD_HP_CPU_MASK_V << PMU_XPD_HP_CPU_MASK_S) +#define PMU_XPD_HP_CPU_MASK_V 0x0000001FU +#define PMU_XPD_HP_CPU_MASK_S 0 +/** PMU_PD_HP_CPU_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_CPU_MASK 0x0000001FU +#define PMU_PD_HP_CPU_MASK_M (PMU_PD_HP_CPU_MASK_V << PMU_PD_HP_CPU_MASK_S) +#define PMU_PD_HP_CPU_MASK_V 0x0000001FU +#define PMU_PD_HP_CPU_MASK_S 27 + /** PMU_DATE_REG register * need_des */ #define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc) -/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 36712768; +/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 38801456; * need_des */ #define PMU_PMU_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h index 8d9e91538ab7..32b477ef1085 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h @@ -1,17 +1,17 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once #include -#include "soc/pmu_reg.h" +#include "pmu_reg.h" #ifdef __cplusplus extern "C" { #endif -//TODO: IDF-13420 +#define SOC_PMU_STRUCT_HW_VER 3 typedef union { struct { @@ -19,7 +19,8 @@ typedef union { uint32_t dcdc_switch_pd_en :1; uint32_t mem_dslp : 1; uint32_t mem_pd_en : 1; - uint32_t reserved1 : 6; + uint32_t reserved1 : 5; + uint32_t hp_cpu_pd_en : 1; uint32_t cnnt_pd_en : 1; uint32_t top_pd_en : 1; }; @@ -243,10 +244,10 @@ typedef union { typedef struct pmu_lp_hw_regmap_t { pmu_lp_regulator0_reg_t regulator0; pmu_lp_regulator1_reg_t regulator1; - pmu_lp_xtal_reg_t xtal; /* Only LP_SLEEP mode under lp system is valid */ + pmu_lp_xtal_reg_t xtal; /* HP_SLEEP: PMU_HP_SLEEP_LP_DCDC_RESERVE_REG LP_SLEEP: PMU_LP_SLEEP_XTAL_REG */ pmu_lp_dig_power_reg_t dig_power; pmu_lp_clk_power_reg_t clk_power; - pmu_lp_bias_reg_t bias; /* Only LP_SLEEP mode under lp system is valid */ + pmu_lp_bias_reg_t bias; /* HP_SLEEP: PMU_LP_SLEEP_LP_BIAS_RESERVE_REG LP_SLEEP: PMU_LP_SLEEP_BIAS_REG */ } pmu_lp_hw_regmap_t; @@ -474,9 +475,10 @@ typedef union { typedef union { struct { - uint32_t modem_wait_target : 20; - uint32_t reserved0 : 4; - uint32_t lp_ana_wait_target: 8; + uint32_t modem_wait_target : 20; + uint32_t reserved0 : 2; + uint32_t lp_ana_wait_target_expand : 2; + uint32_t lp_ana_wait_target : 8; }; uint32_t val; } pmu_slp_wakeup_cntl5_reg_t; @@ -703,7 +705,8 @@ typedef struct pmu_lp_ext_hw_regmap_t { typedef union { struct { - uint32_t reserved_0:7; + uint32_t reserved_0:6; + uint32_t cnt_clr:1; uint32_t force_tieh_sel:1; uint32_t xpd:1; uint32_t tieh_sel:3; @@ -771,9 +774,9 @@ typedef union { typedef union { struct { - uint32_t ana_vddbat_mode : 2; - uint32_t reserved1 : 29; - uint32_t sw_update : 1; + uint32_t module : 2; + uint32_t reserved1 : 29; + uint32_t sw_update : 1; }; uint32_t val; } pmu_vddbat_cfg_t; @@ -917,8 +920,28 @@ typedef struct pmu_dev_t { volatile uint32_t val; } pmu_rdn_eco; + union { + struct { + volatile uint32_t force_hp_cpu_reset : 1; + volatile uint32_t force_hp_cpu_iso : 1; + volatile uint32_t force_hp_cpu_pu : 1; + volatile uint32_t force_hp_cpu_no_reset : 1; + volatile uint32_t force_hp_cpu_no_iso : 1; + volatile uint32_t force_hp_cpu_pd : 1; + volatile uint32_t reserved0 : 26; + }; + volatile uint32_t val; + } power_pd_hp_cpu_cntl; + + union { + struct { + volatile uint32_t xpd_hp_cpu_mask : 5; + volatile uint32_t pd_hp_cpu_mask : 27; + }; + volatile uint32_t val; + } power_pd_hp_cpu_mask; - uint32_t reserved[121]; + uint32_t reserved[119]; union { struct { @@ -934,7 +957,7 @@ extern pmu_dev_t PMU; #ifndef __cplusplus _Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); -_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_RDN_ECO_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); +_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_POWER_PD_HP_CPU_MASK_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/soc_etm_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/soc_etm_struct.h index 63d820d1c52d..9d8b56cdc9d0 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/soc_etm_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/soc_etm_struct.h @@ -10,8 +10,6 @@ extern "C" { #endif -// TODO: IDF-13428 - /** Group: Status register */ /** Type of ch_ena_ad0 register * Channel enable status register diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_reg.h index e1f54ec7bbac..9be06b72dc61 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_reg.h @@ -33,8 +33,9 @@ extern "C" { #define SPI1_MEM_C_SLV_ST_S 4 /** SPI1_MEM_C_FLASH_PE : R/W/SC; bitpos: [17]; default: 0; * In user mode, it is set to indicate that program/erase operation will be triggered. - * The bit is combined with spi1_mem_c_usr bit. The bit will be cleared once the + * The bit is combined with spi_mem_usr bit. The bit will be cleared once the * operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_PE (BIT(17)) #define SPI1_MEM_C_FLASH_PE_M (SPI1_MEM_C_FLASH_PE_V << SPI1_MEM_C_FLASH_PE_S) @@ -51,6 +52,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0; * Drive Flash into high performance mode. The bit will be cleared once the operation * done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_HPM (BIT(19)) #define SPI1_MEM_C_FLASH_HPM_M (SPI1_MEM_C_FLASH_HPM_V << SPI1_MEM_C_FLASH_HPM_S) @@ -60,6 +62,7 @@ extern "C" { * This bit combined with reg_resandres bit releases Flash from the power-down state * or high performance mode and obtains the devices ID. The bit will be cleared once * the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_RES (BIT(20)) #define SPI1_MEM_C_FLASH_RES_M (SPI1_MEM_C_FLASH_RES_V << SPI1_MEM_C_FLASH_RES_S) @@ -68,6 +71,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_DP : R/W/SC; bitpos: [21]; default: 0; * Drive Flash into power down. An operation will be triggered when the bit is set. * The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_DP (BIT(21)) #define SPI1_MEM_C_FLASH_DP_M (SPI1_MEM_C_FLASH_DP_V << SPI1_MEM_C_FLASH_DP_S) @@ -76,6 +80,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_CE : R/W/SC; bitpos: [22]; default: 0; * Chip erase enable. Chip erase operation will be triggered when the bit is set. The * bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_CE (BIT(22)) #define SPI1_MEM_C_FLASH_CE_M (SPI1_MEM_C_FLASH_CE_V << SPI1_MEM_C_FLASH_CE_S) @@ -84,6 +89,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_BE : R/W/SC; bitpos: [23]; default: 0; * Block erase enable(32KB) . Block erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_BE (BIT(23)) #define SPI1_MEM_C_FLASH_BE_M (SPI1_MEM_C_FLASH_BE_V << SPI1_MEM_C_FLASH_BE_S) @@ -92,6 +98,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_SE : R/W/SC; bitpos: [24]; default: 0; * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_SE (BIT(24)) #define SPI1_MEM_C_FLASH_SE_M (SPI1_MEM_C_FLASH_SE_V << SPI1_MEM_C_FLASH_SE_S) @@ -101,6 +108,7 @@ extern "C" { * Page program enable(1 byte ~256 bytes data to be programmed). Page program * operation will be triggered when the bit is set. The bit will be cleared once the * operation done .1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_PP (BIT(25)) #define SPI1_MEM_C_FLASH_PP_M (SPI1_MEM_C_FLASH_PP_V << SPI1_MEM_C_FLASH_PP_S) @@ -109,6 +117,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0; * Write status register enable. Write status operation will be triggered when the * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_WRSR (BIT(26)) #define SPI1_MEM_C_FLASH_WRSR_M (SPI1_MEM_C_FLASH_WRSR_V << SPI1_MEM_C_FLASH_WRSR_S) @@ -117,6 +126,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0; * Read status register-1. Read status operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_RDSR (BIT(27)) #define SPI1_MEM_C_FLASH_RDSR_M (SPI1_MEM_C_FLASH_RDSR_V << SPI1_MEM_C_FLASH_RDSR_S) @@ -125,6 +135,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0; * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_RDID (BIT(28)) #define SPI1_MEM_C_FLASH_RDID_M (SPI1_MEM_C_FLASH_RDID_V << SPI1_MEM_C_FLASH_RDID_S) @@ -133,6 +144,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0; * Write flash disable. Write disable command will be sent when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_WRDI (BIT(29)) #define SPI1_MEM_C_FLASH_WRDI_M (SPI1_MEM_C_FLASH_WRDI_V << SPI1_MEM_C_FLASH_WRDI_S) @@ -141,6 +153,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0; * Write flash enable. Write enable command will be sent when the bit is set. The bit * will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_WREN (BIT(30)) #define SPI1_MEM_C_FLASH_WREN_M (SPI1_MEM_C_FLASH_WREN_V << SPI1_MEM_C_FLASH_WREN_S) @@ -149,6 +162,7 @@ extern "C" { /** SPI1_MEM_C_FLASH_READ : R/W/SC; bitpos: [31]; default: 0; * Read flash enable. Read flash operation will be triggered when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FLASH_READ (BIT(31)) #define SPI1_MEM_C_FLASH_READ_M (SPI1_MEM_C_FLASH_READ_V << SPI1_MEM_C_FLASH_READ_S) @@ -226,6 +240,7 @@ extern "C" { /** SPI1_MEM_C_FCS_CRC_EN : HRO; bitpos: [10]; default: 0; * For SPI1, initialize crc32 module before writing encrypted data to flash. Active * low. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FCS_CRC_EN (BIT(10)) #define SPI1_MEM_C_FCS_CRC_EN_M (SPI1_MEM_C_FCS_CRC_EN_V << SPI1_MEM_C_FCS_CRC_EN_S) @@ -233,14 +248,15 @@ extern "C" { #define SPI1_MEM_C_FCS_CRC_EN_S 10 /** SPI1_MEM_C_TX_CRC_EN : HRO; bitpos: [11]; default: 0; * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_TX_CRC_EN (BIT(11)) #define SPI1_MEM_C_TX_CRC_EN_M (SPI1_MEM_C_TX_CRC_EN_V << SPI1_MEM_C_TX_CRC_EN_S) #define SPI1_MEM_C_TX_CRC_EN_V 0x00000001U #define SPI1_MEM_C_TX_CRC_EN_S 11 /** SPI1_MEM_C_FASTRD_MODE : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: spi1_mem_c_fread_qio, spi1_mem_c_fread_dio, spi1_mem_c_fread_qout - * and spi1_mem_c_fread_dout. 1: enable 0: disable. + * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout + * and spi_mem_fread_dout. 1: enable 0: disable. */ #define SPI1_MEM_C_FASTRD_MODE (BIT(13)) #define SPI1_MEM_C_FASTRD_MODE_M (SPI1_MEM_C_FASTRD_MODE_V << SPI1_MEM_C_FASTRD_MODE_S) @@ -255,7 +271,8 @@ extern "C" { #define SPI1_MEM_C_FREAD_DUAL_S 14 /** SPI1_MEM_C_RESANDRES : R/W; bitpos: [15]; default: 1; * The Device ID is read out to SPI1_MEM_C_RD_STATUS register, this bit combine with - * spi1_mem_c_flash_res bit. 1: enable 0: disable. + * spi_mem_flash_res bit. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_RESANDRES (BIT(15)) #define SPI1_MEM_C_RESANDRES_M (SPI1_MEM_C_RESANDRES_V << SPI1_MEM_C_RESANDRES_S) @@ -292,6 +309,7 @@ extern "C" { /** SPI1_MEM_C_WRSR_2B : R/W; bitpos: [22]; default: 0; * two bytes data will be written to status register when it is set. 1: enable 0: * disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_WRSR_2B (BIT(22)) #define SPI1_MEM_C_WRSR_2B_M (SPI1_MEM_C_WRSR_2B_V << SPI1_MEM_C_WRSR_2B_S) @@ -328,13 +346,30 @@ extern "C" { #define SPI1_MEM_C_CLK_MODE_V 0x00000003U #define SPI1_MEM_C_CLK_MODE_S 0 /** SPI1_MEM_C_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * + * 512) SPI_CLK cycles. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_CS_HOLD_DLY_RES 0x000003FFU #define SPI1_MEM_C_CS_HOLD_DLY_RES_M (SPI1_MEM_C_CS_HOLD_DLY_RES_V << SPI1_MEM_C_CS_HOLD_DLY_RES_S) #define SPI1_MEM_C_CS_HOLD_DLY_RES_V 0x000003FFU #define SPI1_MEM_C_CS_HOLD_DLY_RES_S 2 +/** SPI1_MEM_C_CS_HOLD_DLY_PER : R/W; bitpos: [20:12]; default: 511; + * After PER command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DLY_PER[8:0] * 128) + * SPI_CLK cycles. + */ +#define SPI1_MEM_C_CS_HOLD_DLY_PER 0x000001FFU +#define SPI1_MEM_C_CS_HOLD_DLY_PER_M (SPI1_MEM_C_CS_HOLD_DLY_PER_V << SPI1_MEM_C_CS_HOLD_DLY_PER_S) +#define SPI1_MEM_C_CS_HOLD_DLY_PER_V 0x000001FFU +#define SPI1_MEM_C_CS_HOLD_DLY_PER_S 12 +/** SPI1_MEM_C_CS_HOLD_DLY_PER_EN : R/W; bitpos: [23]; default: 0; + * 1: use SPI1_MEM_C_CS_HOLD_DLY_PER for per, use SPI1_MEM_C_CS_HOLD_DELAY_RES for + * pes/dp/hpm . 0: use SPI1_MEM_C_CS_HOLD_DELAY_RES for pes/dp/hpm/per . + */ +#define SPI1_MEM_C_CS_HOLD_DLY_PER_EN (BIT(23)) +#define SPI1_MEM_C_CS_HOLD_DLY_PER_EN_M (SPI1_MEM_C_CS_HOLD_DLY_PER_EN_V << SPI1_MEM_C_CS_HOLD_DLY_PER_EN_S) +#define SPI1_MEM_C_CS_HOLD_DLY_PER_EN_V 0x00000001U +#define SPI1_MEM_C_CS_HOLD_DLY_PER_EN_S 23 /** SPI1_MEM_C_CTRL2_REG register * SPI1 control2 register. @@ -353,22 +388,22 @@ extern "C" { */ #define SPI1_MEM_C_CLOCK_REG (DR_REG_FLASH_SPI1_BASE + 0x14) /** SPI1_MEM_C_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi1_mem_c_clkcnt_N. + * In the master mode it must be equal to SPI1_MEM_C_CLKCNT_N. */ #define SPI1_MEM_C_CLKCNT_L 0x000000FFU #define SPI1_MEM_C_CLKCNT_L_M (SPI1_MEM_C_CLKCNT_L_V << SPI1_MEM_C_CLKCNT_L_S) #define SPI1_MEM_C_CLKCNT_L_V 0x000000FFU #define SPI1_MEM_C_CLKCNT_L_S 0 /** SPI1_MEM_C_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi1_mem_c_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI1_MEM_C_CLKCNT_N+1)/2-1). */ #define SPI1_MEM_C_CLKCNT_H 0x000000FFU #define SPI1_MEM_C_CLKCNT_H_M (SPI1_MEM_C_CLKCNT_H_V << SPI1_MEM_C_CLKCNT_H_S) #define SPI1_MEM_C_CLKCNT_H_V 0x000000FFU #define SPI1_MEM_C_CLKCNT_H_S 8 /** SPI1_MEM_C_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi1_mem_c_clk. So spi1_mem_c_clk frequency is - * system/(spi1_mem_c_clkcnt_N+1) + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(SPI1_MEM_C_CLKCNT_N+1) */ #define SPI1_MEM_C_CLKCNT_N 0x000000FFU #define SPI1_MEM_C_CLKCNT_N_M (SPI1_MEM_C_CLKCNT_N_V << SPI1_MEM_C_CLKCNT_N_S) @@ -387,7 +422,7 @@ extern "C" { */ #define SPI1_MEM_C_USER_REG (DR_REG_FLASH_SPI1_BASE + 0x18) /** SPI1_MEM_C_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; - * the bit combined with spi1_mem_c_mosi_delay_mode bits to set mosi signal delay mode. + * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. */ #define SPI1_MEM_C_CK_OUT_EDGE (BIT(9)) #define SPI1_MEM_C_CK_OUT_EDGE_M (SPI1_MEM_C_CK_OUT_EDGE_V << SPI1_MEM_C_CK_OUT_EDGE_S) @@ -422,16 +457,18 @@ extern "C" { #define SPI1_MEM_C_FWRITE_QIO_V 0x00000001U #define SPI1_MEM_C_FWRITE_QIO_S 15 /** SPI1_MEM_C_USR_MISO_HIGHPART : HRO; bitpos: [24]; default: 0; - * read-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: + * read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_USR_MISO_HIGHPART (BIT(24)) #define SPI1_MEM_C_USR_MISO_HIGHPART_M (SPI1_MEM_C_USR_MISO_HIGHPART_V << SPI1_MEM_C_USR_MISO_HIGHPART_S) #define SPI1_MEM_C_USR_MISO_HIGHPART_V 0x00000001U #define SPI1_MEM_C_USR_MISO_HIGHPART_S 24 /** SPI1_MEM_C_USR_MOSI_HIGHPART : HRO; bitpos: [25]; default: 0; - * write-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: + * write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_USR_MOSI_HIGHPART (BIT(25)) #define SPI1_MEM_C_USR_MOSI_HIGHPART_M (SPI1_MEM_C_USR_MOSI_HIGHPART_V << SPI1_MEM_C_USR_MOSI_HIGHPART_S) @@ -485,7 +522,7 @@ extern "C" { */ #define SPI1_MEM_C_USER1_REG (DR_REG_FLASH_SPI1_BASE + 0x1c) /** SPI1_MEM_C_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; - * The length in spi1_mem_c_clk cycles of dummy phase. The register value shall be + * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). */ #define SPI1_MEM_C_USR_DUMMY_CYCLELEN 0x0000003FU @@ -548,14 +585,15 @@ extern "C" { */ #define SPI1_MEM_C_RD_STATUS_REG (DR_REG_FLASH_SPI1_BASE + 0x2c) /** SPI1_MEM_C_STATUS : R/W/SS; bitpos: [15:0]; default: 0; - * The value is stored when set spi1_mem_c_flash_rdsr bit and spi1_mem_c_flash_res bit. + * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. */ #define SPI1_MEM_C_STATUS 0x0000FFFFU #define SPI1_MEM_C_STATUS_M (SPI1_MEM_C_STATUS_V << SPI1_MEM_C_STATUS_S) #define SPI1_MEM_C_STATUS_V 0x0000FFFFU #define SPI1_MEM_C_STATUS_S 0 /** SPI1_MEM_C_WB_MODE : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi1_mem_c_fastrd_mode bit. + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_WB_MODE 0x000000FFU #define SPI1_MEM_C_WB_MODE_M (SPI1_MEM_C_WB_MODE_V << SPI1_MEM_C_WB_MODE_S) @@ -599,10 +637,13 @@ extern "C" { /** SPI1_MEM_C_TX_CRC_REG register * SPI1 TX CRC data register. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI1_MEM_C_TX_CRC_REG (DR_REG_FLASH_SPI1_BASE + 0x38) /** SPI1_MEM_C_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295; * For SPI1, the value of crc32. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_TX_CRC_DATA 0xFFFFFFFFU #define SPI1_MEM_C_TX_CRC_DATA_M (SPI1_MEM_C_TX_CRC_DATA_V << SPI1_MEM_C_TX_CRC_DATA_S) @@ -611,10 +652,13 @@ extern "C" { /** SPI1_MEM_C_CACHE_FCTRL_REG register * SPI1 bit mode control register. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI1_MEM_C_CACHE_FCTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x3c) /** SPI1_MEM_C_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE (BIT(1)) #define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_M (SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S) @@ -622,7 +666,8 @@ extern "C" { #define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S 1 /** SPI1_MEM_C_FDIN_DUAL : R/W; bitpos: [3]; default: 0; * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with - * spi1_mem_c_fread_dio. + * spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FDIN_DUAL (BIT(3)) #define SPI1_MEM_C_FDIN_DUAL_M (SPI1_MEM_C_FDIN_DUAL_V << SPI1_MEM_C_FDIN_DUAL_S) @@ -630,7 +675,8 @@ extern "C" { #define SPI1_MEM_C_FDIN_DUAL_S 3 /** SPI1_MEM_C_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FDOUT_DUAL (BIT(4)) #define SPI1_MEM_C_FDOUT_DUAL_M (SPI1_MEM_C_FDOUT_DUAL_V << SPI1_MEM_C_FDOUT_DUAL_S) @@ -638,7 +684,8 @@ extern "C" { #define SPI1_MEM_C_FDOUT_DUAL_S 4 /** SPI1_MEM_C_FADDR_DUAL : R/W; bitpos: [5]; default: 0; * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FADDR_DUAL (BIT(5)) #define SPI1_MEM_C_FADDR_DUAL_M (SPI1_MEM_C_FADDR_DUAL_V << SPI1_MEM_C_FADDR_DUAL_S) @@ -646,7 +693,8 @@ extern "C" { #define SPI1_MEM_C_FADDR_DUAL_S 5 /** SPI1_MEM_C_FDIN_QUAD : R/W; bitpos: [6]; default: 0; * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FDIN_QUAD (BIT(6)) #define SPI1_MEM_C_FDIN_QUAD_M (SPI1_MEM_C_FDIN_QUAD_V << SPI1_MEM_C_FDIN_QUAD_S) @@ -654,7 +702,8 @@ extern "C" { #define SPI1_MEM_C_FDIN_QUAD_S 6 /** SPI1_MEM_C_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FDOUT_QUAD (BIT(7)) #define SPI1_MEM_C_FDOUT_QUAD_M (SPI1_MEM_C_FDOUT_QUAD_V << SPI1_MEM_C_FDOUT_QUAD_S) @@ -662,7 +711,8 @@ extern "C" { #define SPI1_MEM_C_FDOUT_QUAD_S 7 /** SPI1_MEM_C_FADDR_QUAD : R/W; bitpos: [8]; default: 0; * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_C_FADDR_QUAD (BIT(8)) #define SPI1_MEM_C_FADDR_QUAD_M (SPI1_MEM_C_FADDR_QUAD_V << SPI1_MEM_C_FADDR_QUAD_S) @@ -891,8 +941,8 @@ extern "C" { #define SPI1_MEM_C_WAITI_ADDR_EN_S 2 /** SPI1_MEM_C_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0; * When SPI1_MEM_C_WAITI_ADDR_EN is set, the cycle length of sent out address is - * (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when - * SPI1_MEM_C_WAITI_ADDR_EN is cleared. + * (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active + * when SPI1_MEM_C_WAITI_ADDR_EN is cleared. */ #define SPI1_MEM_C_WAITI_ADDR_CYCLELEN 0x00000003U #define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_M (SPI1_MEM_C_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_C_WAITI_ADDR_CYCLELEN_S) @@ -1010,8 +1060,8 @@ extern "C" { #define SPI1_MEM_C_PES_END_EN_V 0x00000001U #define SPI1_MEM_C_PES_END_EN_S 24 /** SPI1_MEM_C_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4; - * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, it - * will be treated as check pass. + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, + * it will be treated as check pass. */ #define SPI1_MEM_C_SUS_TIMEOUT_CNT 0x0000007FU #define SPI1_MEM_C_SUS_TIMEOUT_CNT_M (SPI1_MEM_C_SUS_TIMEOUT_CNT_V << SPI1_MEM_C_SUS_TIMEOUT_CNT_S) @@ -1059,8 +1109,8 @@ extern "C" { #define SPI1_MEM_C_WAIT_PESR_CMD_2B_S 1 /** SPI1_MEM_C_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0; * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM - * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after HPM command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after HPM command is sent. */ #define SPI1_MEM_C_FLASH_HPM_DLY_128 (BIT(2)) #define SPI1_MEM_C_FLASH_HPM_DLY_128_M (SPI1_MEM_C_FLASH_HPM_DLY_128_V << SPI1_MEM_C_FLASH_HPM_DLY_128_S) @@ -1068,8 +1118,8 @@ extern "C" { #define SPI1_MEM_C_FLASH_HPM_DLY_128_S 2 /** SPI1_MEM_C_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0; * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES - * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after RES command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after RES command is sent. */ #define SPI1_MEM_C_FLASH_RES_DLY_128 (BIT(3)) #define SPI1_MEM_C_FLASH_RES_DLY_128_M (SPI1_MEM_C_FLASH_RES_DLY_128_V << SPI1_MEM_C_FLASH_RES_DLY_128_S) @@ -1077,8 +1127,8 @@ extern "C" { #define SPI1_MEM_C_FLASH_RES_DLY_128_S 3 /** SPI1_MEM_C_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0; * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP - * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after DP command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after DP command is sent. */ #define SPI1_MEM_C_FLASH_DP_DLY_128 (BIT(4)) #define SPI1_MEM_C_FLASH_DP_DLY_128_M (SPI1_MEM_C_FLASH_DP_DLY_128_V << SPI1_MEM_C_FLASH_DP_DLY_128_S) @@ -1086,9 +1136,9 @@ extern "C" { #define SPI1_MEM_C_FLASH_DP_DLY_128_S 4 /** SPI1_MEM_C_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0; * Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: - * SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is - * sent. + * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. + * 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER + * command is sent. */ #define SPI1_MEM_C_FLASH_PER_DLY_128 (BIT(5)) #define SPI1_MEM_C_FLASH_PER_DLY_128_M (SPI1_MEM_C_FLASH_PER_DLY_128_V << SPI1_MEM_C_FLASH_PER_DLY_128_S) @@ -1096,9 +1146,9 @@ extern "C" { #define SPI1_MEM_C_FLASH_PER_DLY_128_S 5 /** SPI1_MEM_C_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0; * Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: - * SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is - * sent. + * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. + * 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES + * command is sent. */ #define SPI1_MEM_C_FLASH_PES_DLY_128 (BIT(6)) #define SPI1_MEM_C_FLASH_PES_DLY_128_M (SPI1_MEM_C_FLASH_PES_DLY_128_V << SPI1_MEM_C_FLASH_PES_DLY_128_S) @@ -1242,16 +1292,16 @@ extern "C" { #define SPI1_MEM_C_PES_END_INT_RAW_V 0x00000001U #define SPI1_MEM_C_PES_END_INT_RAW_S 1 /** SPI1_MEM_C_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE - * is sent and flash is already idle. 0: Others. + * The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when + * WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. */ #define SPI1_MEM_C_WPE_END_INT_RAW (BIT(2)) #define SPI1_MEM_C_WPE_END_INT_RAW_M (SPI1_MEM_C_WPE_END_INT_RAW_V << SPI1_MEM_C_WPE_END_INT_RAW_S) #define SPI1_MEM_C_WPE_END_INT_RAW_V 0x00000001U #define SPI1_MEM_C_WPE_END_INT_RAW_S 2 /** SPI1_MEM_C_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st + * is changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ #define SPI1_MEM_C_SLV_ST_END_INT_RAW (BIT(3)) @@ -1259,8 +1309,8 @@ extern "C" { #define SPI1_MEM_C_SLV_ST_END_INT_RAW_V 0x00000001U #define SPI1_MEM_C_SLV_ST_END_INT_RAW_S 3 /** SPI1_MEM_C_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is - * changed from non idle state to idle state. 0: Others. + * The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st + * is changed from non idle state to idle state. 0: Others. */ #define SPI1_MEM_C_MST_ST_END_INT_RAW (BIT(4)) #define SPI1_MEM_C_MST_ST_END_INT_RAW_M (SPI1_MEM_C_MST_ST_END_INT_RAW_V << SPI1_MEM_C_MST_ST_END_INT_RAW_S) @@ -1379,8 +1429,8 @@ extern "C" { #define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_S 14 /** SPI1_MEM_C_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ #define SPI1_MEM_C_FMEM_DDR_DQS_LOOP (BIT(21)) @@ -1468,7 +1518,7 @@ extern "C" { * Version control register */ #define SPI1_MEM_C_DATE_REG (DR_REG_FLASH_SPI1_BASE + 0x3fc) -/** SPI1_MEM_C_DATE : R/W; bitpos: [27:0]; default: 35660128; +/** SPI1_MEM_C_DATE : R/W; bitpos: [27:0]; default: 38801712; * Version control register */ #define SPI1_MEM_C_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_struct.h index 52941e2d361a..84903e357753 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_c_struct.h @@ -29,8 +29,9 @@ typedef union { uint32_t reserved_8:9; /** flash_pe : R/W/SC; bitpos: [17]; default: 0; * In user mode, it is set to indicate that program/erase operation will be triggered. - * The bit is combined with spi1_mem_c_usr bit. The bit will be cleared once the + * The bit is combined with spi_mem_usr bit. The bit will be cleared once the * operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_pe:1; /** usr : R/W/SC; bitpos: [18]; default: 0; @@ -41,68 +42,81 @@ typedef union { /** flash_hpm : R/W/SC; bitpos: [19]; default: 0; * Drive Flash into high performance mode. The bit will be cleared once the operation * done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_hpm:1; /** flash_res : R/W/SC; bitpos: [20]; default: 0; * This bit combined with reg_resandres bit releases Flash from the power-down state * or high performance mode and obtains the devices ID. The bit will be cleared once * the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_res:1; /** flash_dp : R/W/SC; bitpos: [21]; default: 0; * Drive Flash into power down. An operation will be triggered when the bit is set. * The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_dp:1; /** flash_ce : R/W/SC; bitpos: [22]; default: 0; * Chip erase enable. Chip erase operation will be triggered when the bit is set. The * bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_ce:1; /** flash_be : R/W/SC; bitpos: [23]; default: 0; * Block erase enable(32KB) . Block erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_be:1; /** flash_se : R/W/SC; bitpos: [24]; default: 0; * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_se:1; /** flash_pp : R/W/SC; bitpos: [25]; default: 0; * Page program enable(1 byte ~256 bytes data to be programmed). Page program * operation will be triggered when the bit is set. The bit will be cleared once the * operation done .1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_pp:1; /** flash_wrsr : R/W/SC; bitpos: [26]; default: 0; * Write status register enable. Write status operation will be triggered when the * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wrsr:1; /** flash_rdsr : R/W/SC; bitpos: [27]; default: 0; * Read status register-1. Read status operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_rdsr:1; /** flash_rdid : R/W/SC; bitpos: [28]; default: 0; * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_rdid:1; /** flash_wrdi : R/W/SC; bitpos: [29]; default: 0; * Write flash disable. Write disable command will be sent when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wrdi:1; /** flash_wren : R/W/SC; bitpos: [30]; default: 0; * Write flash enable. Write enable command will be sent when the bit is set. The bit * will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wren:1; /** flash_read : R/W/SC; bitpos: [31]; default: 0; * Read flash enable. Read flash operation will be triggered when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_read:1; }; @@ -130,7 +144,7 @@ typedef union { struct { uint32_t reserved_0:9; /** ck_out_edge : R/W; bitpos: [9]; default: 0; - * the bit combined with spi1_mem_c_mosi_delay_mode bits to set mosi signal delay mode. + * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. */ uint32_t ck_out_edge:1; uint32_t reserved_10:2; @@ -152,13 +166,15 @@ typedef union { uint32_t fwrite_qio:1; uint32_t reserved_16:8; /** usr_miso_highpart : HRO; bitpos: [24]; default: 0; - * read-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: + * read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t usr_miso_highpart:1; /** usr_mosi_highpart : HRO; bitpos: [25]; default: 0; - * write-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1: + * write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t usr_mosi_highpart:1; /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; @@ -195,7 +211,7 @@ typedef union { typedef union { struct { /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; - * The length in spi1_mem_c_clk cycles of dummy phase. The register value shall be + * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). */ uint32_t usr_dummy_cyclelen:6; @@ -268,16 +284,18 @@ typedef union { /** fcs_crc_en : HRO; bitpos: [10]; default: 0; * For SPI1, initialize crc32 module before writing encrypted data to flash. Active * low. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fcs_crc_en:1; /** tx_crc_en : HRO; bitpos: [11]; default: 0; * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t tx_crc_en:1; uint32_t reserved_12:1; /** fastrd_mode : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: spi1_mem_c_fread_qio, spi1_mem_c_fread_dio, spi1_mem_c_fread_qout - * and spi1_mem_c_fread_dout. 1: enable 0: disable. + * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout + * and spi_mem_fread_dout. 1: enable 0: disable. */ uint32_t fastrd_mode:1; /** fread_dual : R/W; bitpos: [14]; default: 0; @@ -286,7 +304,8 @@ typedef union { uint32_t fread_dual:1; /** resandres : R/W; bitpos: [15]; default: 1; * The Device ID is read out to SPI1_MEM_C_RD_STATUS register, this bit combine with - * spi1_mem_c_flash_res bit. 1: enable 0: disable. + * spi_mem_flash_res bit. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t resandres:1; uint32_t reserved_16:2; @@ -309,6 +328,7 @@ typedef union { /** wrsr_2b : R/W; bitpos: [22]; default: 0; * two bytes data will be written to status register when it is set. 1: enable 0: * disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wrsr_2b:1; /** fread_dio : R/W; bitpos: [23]; default: 0; @@ -338,11 +358,23 @@ typedef union { */ uint32_t clk_mode:2; /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * + * 512) SPI_CLK cycles. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t cs_hold_dly_res:10; - uint32_t reserved_12:20; + /** cs_hold_dly_per : R/W; bitpos: [20:12]; default: 511; + * After PER command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DLY_PER[8:0] * 128) + * SPI_CLK cycles. + */ + uint32_t cs_hold_dly_per:9; + uint32_t reserved_21:2; + /** cs_hold_dly_per_en : R/W; bitpos: [23]; default: 0; + * 1: use SPI1_MEM_C_CS_HOLD_DLY_PER for per, use SPI1_MEM_C_CS_HOLD_DELAY_RES for + * pes/dp/hpm . 0: use SPI1_MEM_C_CS_HOLD_DELAY_RES for pes/dp/hpm/per . + */ + uint32_t cs_hold_dly_per_en:1; + uint32_t reserved_24:8; }; uint32_t val; } spi1_mem_c_ctrl1_reg_t; @@ -367,16 +399,16 @@ typedef union { typedef union { struct { /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi1_mem_c_clkcnt_N. + * In the master mode it must be equal to SPI1_MEM_C_CLKCNT_N. */ uint32_t clkcnt_l:8; /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi1_mem_c_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI1_MEM_C_CLKCNT_N+1)/2-1). */ uint32_t clkcnt_h:8; /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi1_mem_c_clk. So spi1_mem_c_clk frequency is - * system/(spi1_mem_c_clkcnt_N+1) + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(SPI1_MEM_C_CLKCNT_N+1) */ uint32_t clkcnt_n:8; uint32_t reserved_24:7; @@ -422,11 +454,12 @@ typedef union { typedef union { struct { /** status : R/W/SS; bitpos: [15:0]; default: 0; - * The value is stored when set spi1_mem_c_flash_rdsr bit and spi1_mem_c_flash_res bit. + * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. */ uint32_t status:16; /** wb_mode : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi1_mem_c_fastrd_mode bit. + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wb_mode:8; uint32_t reserved_24:8; @@ -471,37 +504,44 @@ typedef union { uint32_t reserved_0:1; /** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t cache_usr_addr_4byte:1; uint32_t reserved_2:1; /** fdin_dual : R/W; bitpos: [3]; default: 0; * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with - * spi1_mem_c_fread_dio. + * spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdin_dual:1; /** fdout_dual : R/W; bitpos: [4]; default: 0; * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdout_dual:1; /** faddr_dual : R/W; bitpos: [5]; default: 0; * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t faddr_dual:1; /** fdin_quad : R/W; bitpos: [6]; default: 0; * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdin_quad:1; /** fdout_quad : R/W; bitpos: [7]; default: 0; * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdout_quad:1; /** faddr_quad : R/W; bitpos: [8]; default: 0; * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_c_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t faddr_quad:1; uint32_t reserved_9:23; @@ -531,8 +571,8 @@ typedef union { uint32_t waiti_addr_en:1; /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0; * When SPI1_MEM_C_WAITI_ADDR_EN is set, the cycle length of sent out address is - * (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when - * SPI1_MEM_C_WAITI_ADDR_EN is cleared. + * (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active + * when SPI1_MEM_C_WAITI_ADDR_EN is cleared. */ uint32_t waiti_addr_cyclelen:2; uint32_t reserved_5:4; @@ -613,8 +653,8 @@ typedef union { */ uint32_t pes_end_en:1; /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4; - * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, it - * will be treated as check pass. + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, + * it will be treated as check pass. */ uint32_t sus_timeout_cnt:7; }; @@ -655,34 +695,34 @@ typedef union { uint32_t wait_pesr_cmd_2b:1; /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0; * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM - * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after HPM command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after HPM command is sent. */ uint32_t flash_hpm_dly_128:1; /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0; * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES - * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after RES command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after RES command is sent. */ uint32_t flash_res_dly_128:1; /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0; * 1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP - * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after DP command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after DP command is sent. */ uint32_t flash_dp_dly_128:1; /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0; * Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: - * SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is - * sent. + * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. + * 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER + * command is sent. */ uint32_t flash_per_dly_128:1; /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0; * Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: - * SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is - * sent. + * (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. + * 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES + * command is sent. */ uint32_t flash_pes_dly_128:1; /** spi0_lock_en : R/W; bitpos: [7]; default: 0; @@ -739,8 +779,8 @@ typedef union { uint32_t fmem_usr_ddr_dqs_thd:7; /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ uint32_t fmem_ddr_dqs_loop:1; @@ -801,12 +841,14 @@ typedef union { struct { /** tx_crc_data : RO; bitpos: [31:0]; default: 4294967295; * For SPI1, the value of crc32. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t tx_crc_data:32; }; uint32_t val; } spi1_mem_c_tx_crc_reg_t; + /** Group: Interrupt registers */ /** Type of int_ena register * SPI1 interrupt enable register @@ -894,19 +936,19 @@ typedef union { */ uint32_t pes_end_int_raw:1; /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE - * is sent and flash is already idle. 0: Others. + * The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when + * WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. */ uint32_t wpe_end_int_raw:1; /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st + * is changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ uint32_t slv_st_end_int_raw:1; /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is - * changed from non idle state to idle state. 0: Others. + * The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st + * is changed from non idle state to idle state. 0: Others. */ uint32_t mst_st_end_int_raw:1; uint32_t reserved_5:5; @@ -985,7 +1027,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 35660128; + /** date : R/W; bitpos: [27:0]; default: 38801712; * Version control register */ uint32_t date:28; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_reg.h index 22df90ee72ae..f8219e708e14 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_reg.h @@ -33,8 +33,9 @@ extern "C" { #define SPI1_MEM_S_SLV_ST_S 4 /** SPI1_MEM_S_FLASH_PE : R/W/SC; bitpos: [17]; default: 0; * In user mode, it is set to indicate that program/erase operation will be triggered. - * The bit is combined with spi1_mem_s_usr bit. The bit will be cleared once the + * The bit is combined with spi_mem_usr bit. The bit will be cleared once the * operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_PE (BIT(17)) #define SPI1_MEM_S_FLASH_PE_M (SPI1_MEM_S_FLASH_PE_V << SPI1_MEM_S_FLASH_PE_S) @@ -51,6 +52,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0; * Drive Flash into high performance mode. The bit will be cleared once the operation * done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_HPM (BIT(19)) #define SPI1_MEM_S_FLASH_HPM_M (SPI1_MEM_S_FLASH_HPM_V << SPI1_MEM_S_FLASH_HPM_S) @@ -60,6 +62,7 @@ extern "C" { * This bit combined with reg_resandres bit releases Flash from the power-down state * or high performance mode and obtains the devices ID. The bit will be cleared once * the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_RES (BIT(20)) #define SPI1_MEM_S_FLASH_RES_M (SPI1_MEM_S_FLASH_RES_V << SPI1_MEM_S_FLASH_RES_S) @@ -68,6 +71,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_DP : R/W/SC; bitpos: [21]; default: 0; * Drive Flash into power down. An operation will be triggered when the bit is set. * The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_DP (BIT(21)) #define SPI1_MEM_S_FLASH_DP_M (SPI1_MEM_S_FLASH_DP_V << SPI1_MEM_S_FLASH_DP_S) @@ -76,6 +80,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_CE : R/W/SC; bitpos: [22]; default: 0; * Chip erase enable. Chip erase operation will be triggered when the bit is set. The * bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_CE (BIT(22)) #define SPI1_MEM_S_FLASH_CE_M (SPI1_MEM_S_FLASH_CE_V << SPI1_MEM_S_FLASH_CE_S) @@ -84,6 +89,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_BE : R/W/SC; bitpos: [23]; default: 0; * Block erase enable(32KB) . Block erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_BE (BIT(23)) #define SPI1_MEM_S_FLASH_BE_M (SPI1_MEM_S_FLASH_BE_V << SPI1_MEM_S_FLASH_BE_S) @@ -92,6 +98,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_SE : R/W/SC; bitpos: [24]; default: 0; * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_SE (BIT(24)) #define SPI1_MEM_S_FLASH_SE_M (SPI1_MEM_S_FLASH_SE_V << SPI1_MEM_S_FLASH_SE_S) @@ -101,6 +108,7 @@ extern "C" { * Page program enable(1 byte ~256 bytes data to be programmed). Page program * operation will be triggered when the bit is set. The bit will be cleared once the * operation done .1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_PP (BIT(25)) #define SPI1_MEM_S_FLASH_PP_M (SPI1_MEM_S_FLASH_PP_V << SPI1_MEM_S_FLASH_PP_S) @@ -109,6 +117,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0; * Write status register enable. Write status operation will be triggered when the * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_WRSR (BIT(26)) #define SPI1_MEM_S_FLASH_WRSR_M (SPI1_MEM_S_FLASH_WRSR_V << SPI1_MEM_S_FLASH_WRSR_S) @@ -117,6 +126,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0; * Read status register-1. Read status operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_RDSR (BIT(27)) #define SPI1_MEM_S_FLASH_RDSR_M (SPI1_MEM_S_FLASH_RDSR_V << SPI1_MEM_S_FLASH_RDSR_S) @@ -125,6 +135,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0; * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_RDID (BIT(28)) #define SPI1_MEM_S_FLASH_RDID_M (SPI1_MEM_S_FLASH_RDID_V << SPI1_MEM_S_FLASH_RDID_S) @@ -133,6 +144,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0; * Write flash disable. Write disable command will be sent when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_WRDI (BIT(29)) #define SPI1_MEM_S_FLASH_WRDI_M (SPI1_MEM_S_FLASH_WRDI_V << SPI1_MEM_S_FLASH_WRDI_S) @@ -141,6 +153,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0; * Write flash enable. Write enable command will be sent when the bit is set. The bit * will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_WREN (BIT(30)) #define SPI1_MEM_S_FLASH_WREN_M (SPI1_MEM_S_FLASH_WREN_V << SPI1_MEM_S_FLASH_WREN_S) @@ -149,6 +162,7 @@ extern "C" { /** SPI1_MEM_S_FLASH_READ : R/W/SC; bitpos: [31]; default: 0; * Read flash enable. Read flash operation will be triggered when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FLASH_READ (BIT(31)) #define SPI1_MEM_S_FLASH_READ_M (SPI1_MEM_S_FLASH_READ_V << SPI1_MEM_S_FLASH_READ_S) @@ -226,6 +240,7 @@ extern "C" { /** SPI1_MEM_S_FCS_CRC_EN : R/W; bitpos: [10]; default: 0; * For SPI1, initialize crc32 module before writing encrypted data to flash. Active * low. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FCS_CRC_EN (BIT(10)) #define SPI1_MEM_S_FCS_CRC_EN_M (SPI1_MEM_S_FCS_CRC_EN_V << SPI1_MEM_S_FCS_CRC_EN_S) @@ -233,14 +248,15 @@ extern "C" { #define SPI1_MEM_S_FCS_CRC_EN_S 10 /** SPI1_MEM_S_TX_CRC_EN : R/W; bitpos: [11]; default: 0; * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_TX_CRC_EN (BIT(11)) #define SPI1_MEM_S_TX_CRC_EN_M (SPI1_MEM_S_TX_CRC_EN_V << SPI1_MEM_S_TX_CRC_EN_S) #define SPI1_MEM_S_TX_CRC_EN_V 0x00000001U #define SPI1_MEM_S_TX_CRC_EN_S 11 /** SPI1_MEM_S_FASTRD_MODE : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: spi1_mem_s_fread_qio, spi1_mem_s_fread_dio, spi1_mem_s_fread_qout - * and spi1_mem_s_fread_dout. 1: enable 0: disable. + * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout + * and spi_mem_fread_dout. 1: enable 0: disable. */ #define SPI1_MEM_S_FASTRD_MODE (BIT(13)) #define SPI1_MEM_S_FASTRD_MODE_M (SPI1_MEM_S_FASTRD_MODE_V << SPI1_MEM_S_FASTRD_MODE_S) @@ -255,7 +271,8 @@ extern "C" { #define SPI1_MEM_S_FREAD_DUAL_S 14 /** SPI1_MEM_S_RESANDRES : R/W; bitpos: [15]; default: 1; * The Device ID is read out to SPI1_MEM_S_RD_STATUS register, this bit combine with - * spi1_mem_s_flash_res bit. 1: enable 0: disable. + * spi_mem_flash_res bit. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_RESANDRES (BIT(15)) #define SPI1_MEM_S_RESANDRES_M (SPI1_MEM_S_RESANDRES_V << SPI1_MEM_S_RESANDRES_S) @@ -292,6 +309,7 @@ extern "C" { /** SPI1_MEM_S_WRSR_2B : R/W; bitpos: [22]; default: 0; * two bytes data will be written to status register when it is set. 1: enable 0: * disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_WRSR_2B (BIT(22)) #define SPI1_MEM_S_WRSR_2B_M (SPI1_MEM_S_WRSR_2B_V << SPI1_MEM_S_WRSR_2B_S) @@ -328,13 +346,30 @@ extern "C" { #define SPI1_MEM_S_CLK_MODE_V 0x00000003U #define SPI1_MEM_S_CLK_MODE_S 0 /** SPI1_MEM_S_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * + * 512) SPI_CLK cycles. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_CS_HOLD_DLY_RES 0x000003FFU #define SPI1_MEM_S_CS_HOLD_DLY_RES_M (SPI1_MEM_S_CS_HOLD_DLY_RES_V << SPI1_MEM_S_CS_HOLD_DLY_RES_S) #define SPI1_MEM_S_CS_HOLD_DLY_RES_V 0x000003FFU #define SPI1_MEM_S_CS_HOLD_DLY_RES_S 2 +/** SPI1_MEM_S_CS_HOLD_DLY_PER : R/W; bitpos: [20:12]; default: 511; + * After PER command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DLY_PER[8:0] * 128) + * SPI_CLK cycles. + */ +#define SPI1_MEM_S_CS_HOLD_DLY_PER 0x000001FFU +#define SPI1_MEM_S_CS_HOLD_DLY_PER_M (SPI1_MEM_S_CS_HOLD_DLY_PER_V << SPI1_MEM_S_CS_HOLD_DLY_PER_S) +#define SPI1_MEM_S_CS_HOLD_DLY_PER_V 0x000001FFU +#define SPI1_MEM_S_CS_HOLD_DLY_PER_S 12 +/** SPI1_MEM_S_CS_HOLD_DLY_PER_EN : R/W; bitpos: [23]; default: 0; + * 1: use SPI1_MEM_S_CS_HOLD_DLY_PER for per, use SPI1_MEM_S_CS_HOLD_DELAY_RES for + * pes/dp/hpm . 0: use SPI1_MEM_S_CS_HOLD_DELAY_RES for pes/dp/hpm/per . + */ +#define SPI1_MEM_S_CS_HOLD_DLY_PER_EN (BIT(23)) +#define SPI1_MEM_S_CS_HOLD_DLY_PER_EN_M (SPI1_MEM_S_CS_HOLD_DLY_PER_EN_V << SPI1_MEM_S_CS_HOLD_DLY_PER_EN_S) +#define SPI1_MEM_S_CS_HOLD_DLY_PER_EN_V 0x00000001U +#define SPI1_MEM_S_CS_HOLD_DLY_PER_EN_S 23 /** SPI1_MEM_S_CTRL2_REG register * SPI1 control2 register. @@ -353,22 +388,22 @@ extern "C" { */ #define SPI1_MEM_S_CLOCK_REG (DR_REG_PSRAM_MSPI1_BASE + 0x14) /** SPI1_MEM_S_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi1_mem_s_clkcnt_N. + * In the master mode it must be equal to SPI1_MEM_S_CLKCNT_N. */ #define SPI1_MEM_S_CLKCNT_L 0x000000FFU #define SPI1_MEM_S_CLKCNT_L_M (SPI1_MEM_S_CLKCNT_L_V << SPI1_MEM_S_CLKCNT_L_S) #define SPI1_MEM_S_CLKCNT_L_V 0x000000FFU #define SPI1_MEM_S_CLKCNT_L_S 0 /** SPI1_MEM_S_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi1_mem_s_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI1_MEM_S_CLKCNT_N+1)/2-1). */ #define SPI1_MEM_S_CLKCNT_H 0x000000FFU #define SPI1_MEM_S_CLKCNT_H_M (SPI1_MEM_S_CLKCNT_H_V << SPI1_MEM_S_CLKCNT_H_S) #define SPI1_MEM_S_CLKCNT_H_V 0x000000FFU #define SPI1_MEM_S_CLKCNT_H_S 8 /** SPI1_MEM_S_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi1_mem_s_clk. So spi1_mem_s_clk frequency is - * system/(spi1_mem_s_clkcnt_N+1) + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(SPI1_MEM_S_CLKCNT_N+1) */ #define SPI1_MEM_S_CLKCNT_N 0x000000FFU #define SPI1_MEM_S_CLKCNT_N_M (SPI1_MEM_S_CLKCNT_N_V << SPI1_MEM_S_CLKCNT_N_S) @@ -387,7 +422,7 @@ extern "C" { */ #define SPI1_MEM_S_USER_REG (DR_REG_PSRAM_MSPI1_BASE + 0x18) /** SPI1_MEM_S_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; - * the bit combined with spi1_mem_s_mosi_delay_mode bits to set mosi signal delay mode. + * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. */ #define SPI1_MEM_S_CK_OUT_EDGE (BIT(9)) #define SPI1_MEM_S_CK_OUT_EDGE_M (SPI1_MEM_S_CK_OUT_EDGE_V << SPI1_MEM_S_CK_OUT_EDGE_S) @@ -422,7 +457,7 @@ extern "C" { #define SPI1_MEM_S_FWRITE_QIO_V 0x00000001U #define SPI1_MEM_S_FWRITE_QIO_S 15 /** SPI1_MEM_S_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; - * read-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: + * read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. */ #define SPI1_MEM_S_USR_MISO_HIGHPART (BIT(24)) @@ -430,7 +465,7 @@ extern "C" { #define SPI1_MEM_S_USR_MISO_HIGHPART_V 0x00000001U #define SPI1_MEM_S_USR_MISO_HIGHPART_S 24 /** SPI1_MEM_S_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; - * write-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: + * write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. */ #define SPI1_MEM_S_USR_MOSI_HIGHPART (BIT(25)) @@ -485,7 +520,7 @@ extern "C" { */ #define SPI1_MEM_S_USER1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x1c) /** SPI1_MEM_S_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; - * The length in spi1_mem_s_clk cycles of dummy phase. The register value shall be + * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). */ #define SPI1_MEM_S_USR_DUMMY_CYCLELEN 0x0000003FU @@ -548,14 +583,15 @@ extern "C" { */ #define SPI1_MEM_S_RD_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0x2c) /** SPI1_MEM_S_STATUS : R/W/SS; bitpos: [15:0]; default: 0; - * The value is stored when set spi1_mem_s_flash_rdsr bit and spi1_mem_s_flash_res bit. + * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. */ #define SPI1_MEM_S_STATUS 0x0000FFFFU #define SPI1_MEM_S_STATUS_M (SPI1_MEM_S_STATUS_V << SPI1_MEM_S_STATUS_S) #define SPI1_MEM_S_STATUS_V 0x0000FFFFU #define SPI1_MEM_S_STATUS_S 0 /** SPI1_MEM_S_WB_MODE : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi1_mem_s_fastrd_mode bit. + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_WB_MODE 0x000000FFU #define SPI1_MEM_S_WB_MODE_M (SPI1_MEM_S_WB_MODE_V << SPI1_MEM_S_WB_MODE_S) @@ -611,10 +647,13 @@ extern "C" { /** SPI1_MEM_S_CACHE_FCTRL_REG register * SPI1 bit mode control register. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI1_MEM_S_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3c) /** SPI1_MEM_S_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE (BIT(1)) #define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_M (SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S) @@ -622,7 +661,8 @@ extern "C" { #define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S 1 /** SPI1_MEM_S_FDIN_DUAL : R/W; bitpos: [3]; default: 0; * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with - * spi1_mem_s_fread_dio. + * spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FDIN_DUAL (BIT(3)) #define SPI1_MEM_S_FDIN_DUAL_M (SPI1_MEM_S_FDIN_DUAL_V << SPI1_MEM_S_FDIN_DUAL_S) @@ -630,7 +670,8 @@ extern "C" { #define SPI1_MEM_S_FDIN_DUAL_S 3 /** SPI1_MEM_S_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FDOUT_DUAL (BIT(4)) #define SPI1_MEM_S_FDOUT_DUAL_M (SPI1_MEM_S_FDOUT_DUAL_V << SPI1_MEM_S_FDOUT_DUAL_S) @@ -638,7 +679,8 @@ extern "C" { #define SPI1_MEM_S_FDOUT_DUAL_S 4 /** SPI1_MEM_S_FADDR_DUAL : R/W; bitpos: [5]; default: 0; * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FADDR_DUAL (BIT(5)) #define SPI1_MEM_S_FADDR_DUAL_M (SPI1_MEM_S_FADDR_DUAL_V << SPI1_MEM_S_FADDR_DUAL_S) @@ -646,7 +688,8 @@ extern "C" { #define SPI1_MEM_S_FADDR_DUAL_S 5 /** SPI1_MEM_S_FDIN_QUAD : R/W; bitpos: [6]; default: 0; * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FDIN_QUAD (BIT(6)) #define SPI1_MEM_S_FDIN_QUAD_M (SPI1_MEM_S_FDIN_QUAD_V << SPI1_MEM_S_FDIN_QUAD_S) @@ -654,7 +697,8 @@ extern "C" { #define SPI1_MEM_S_FDIN_QUAD_S 6 /** SPI1_MEM_S_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FDOUT_QUAD (BIT(7)) #define SPI1_MEM_S_FDOUT_QUAD_M (SPI1_MEM_S_FDOUT_QUAD_V << SPI1_MEM_S_FDOUT_QUAD_S) @@ -662,7 +706,8 @@ extern "C" { #define SPI1_MEM_S_FDOUT_QUAD_S 7 /** SPI1_MEM_S_FADDR_QUAD : R/W; bitpos: [8]; default: 0; * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI1_MEM_S_FADDR_QUAD (BIT(8)) #define SPI1_MEM_S_FADDR_QUAD_M (SPI1_MEM_S_FADDR_QUAD_V << SPI1_MEM_S_FADDR_QUAD_S) @@ -891,8 +936,8 @@ extern "C" { #define SPI1_MEM_S_WAITI_ADDR_EN_S 2 /** SPI1_MEM_S_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0; * When SPI1_MEM_S_WAITI_ADDR_EN is set, the cycle length of sent out address is - * (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when - * SPI1_MEM_S_WAITI_ADDR_EN is cleared. + * (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active + * when SPI1_MEM_S_WAITI_ADDR_EN is cleared. */ #define SPI1_MEM_S_WAITI_ADDR_CYCLELEN 0x00000003U #define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_M (SPI1_MEM_S_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_S_WAITI_ADDR_CYCLELEN_S) @@ -1010,8 +1055,8 @@ extern "C" { #define SPI1_MEM_S_PES_END_EN_V 0x00000001U #define SPI1_MEM_S_PES_END_EN_S 24 /** SPI1_MEM_S_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4; - * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, it - * will be treated as check pass. + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, + * it will be treated as check pass. */ #define SPI1_MEM_S_SUS_TIMEOUT_CNT 0x0000007FU #define SPI1_MEM_S_SUS_TIMEOUT_CNT_M (SPI1_MEM_S_SUS_TIMEOUT_CNT_V << SPI1_MEM_S_SUS_TIMEOUT_CNT_S) @@ -1059,8 +1104,8 @@ extern "C" { #define SPI1_MEM_S_WAIT_PESR_CMD_2B_S 1 /** SPI1_MEM_S_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0; * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM - * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after HPM command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after HPM command is sent. */ #define SPI1_MEM_S_FLASH_HPM_DLY_128 (BIT(2)) #define SPI1_MEM_S_FLASH_HPM_DLY_128_M (SPI1_MEM_S_FLASH_HPM_DLY_128_V << SPI1_MEM_S_FLASH_HPM_DLY_128_S) @@ -1068,8 +1113,8 @@ extern "C" { #define SPI1_MEM_S_FLASH_HPM_DLY_128_S 2 /** SPI1_MEM_S_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0; * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES - * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after RES command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after RES command is sent. */ #define SPI1_MEM_S_FLASH_RES_DLY_128 (BIT(3)) #define SPI1_MEM_S_FLASH_RES_DLY_128_M (SPI1_MEM_S_FLASH_RES_DLY_128_V << SPI1_MEM_S_FLASH_RES_DLY_128_S) @@ -1077,8 +1122,8 @@ extern "C" { #define SPI1_MEM_S_FLASH_RES_DLY_128_S 3 /** SPI1_MEM_S_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0; * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP - * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after DP command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after DP command is sent. */ #define SPI1_MEM_S_FLASH_DP_DLY_128 (BIT(4)) #define SPI1_MEM_S_FLASH_DP_DLY_128_M (SPI1_MEM_S_FLASH_DP_DLY_128_V << SPI1_MEM_S_FLASH_DP_DLY_128_S) @@ -1086,9 +1131,9 @@ extern "C" { #define SPI1_MEM_S_FLASH_DP_DLY_128_S 4 /** SPI1_MEM_S_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0; * Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: - * SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is - * sent. + * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. + * 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER + * command is sent. */ #define SPI1_MEM_S_FLASH_PER_DLY_128 (BIT(5)) #define SPI1_MEM_S_FLASH_PER_DLY_128_M (SPI1_MEM_S_FLASH_PER_DLY_128_V << SPI1_MEM_S_FLASH_PER_DLY_128_S) @@ -1096,9 +1141,9 @@ extern "C" { #define SPI1_MEM_S_FLASH_PER_DLY_128_S 5 /** SPI1_MEM_S_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0; * Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: - * SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is - * sent. + * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. + * 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES + * command is sent. */ #define SPI1_MEM_S_FLASH_PES_DLY_128 (BIT(6)) #define SPI1_MEM_S_FLASH_PES_DLY_128_M (SPI1_MEM_S_FLASH_PES_DLY_128_V << SPI1_MEM_S_FLASH_PES_DLY_128_S) @@ -1242,16 +1287,16 @@ extern "C" { #define SPI1_MEM_S_PES_END_INT_RAW_V 0x00000001U #define SPI1_MEM_S_PES_END_INT_RAW_S 1 /** SPI1_MEM_S_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE - * is sent and flash is already idle. 0: Others. + * The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when + * WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. */ #define SPI1_MEM_S_WPE_END_INT_RAW (BIT(2)) #define SPI1_MEM_S_WPE_END_INT_RAW_M (SPI1_MEM_S_WPE_END_INT_RAW_V << SPI1_MEM_S_WPE_END_INT_RAW_S) #define SPI1_MEM_S_WPE_END_INT_RAW_V 0x00000001U #define SPI1_MEM_S_WPE_END_INT_RAW_S 2 /** SPI1_MEM_S_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st + * is changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ #define SPI1_MEM_S_SLV_ST_END_INT_RAW (BIT(3)) @@ -1259,8 +1304,8 @@ extern "C" { #define SPI1_MEM_S_SLV_ST_END_INT_RAW_V 0x00000001U #define SPI1_MEM_S_SLV_ST_END_INT_RAW_S 3 /** SPI1_MEM_S_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is - * changed from non idle state to idle state. 0: Others. + * The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st + * is changed from non idle state to idle state. 0: Others. */ #define SPI1_MEM_S_MST_ST_END_INT_RAW (BIT(4)) #define SPI1_MEM_S_MST_ST_END_INT_RAW_M (SPI1_MEM_S_MST_ST_END_INT_RAW_V << SPI1_MEM_S_MST_ST_END_INT_RAW_S) @@ -1379,8 +1424,8 @@ extern "C" { #define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_S 14 /** SPI1_MEM_S_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ #define SPI1_MEM_S_FMEM_DDR_DQS_LOOP (BIT(21)) @@ -1468,7 +1513,7 @@ extern "C" { * Version control register */ #define SPI1_MEM_S_DATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3fc) -/** SPI1_MEM_S_DATE : R/W; bitpos: [27:0]; default: 34673216; +/** SPI1_MEM_S_DATE : R/W; bitpos: [27:0]; default: 38801712; * Version control register */ #define SPI1_MEM_S_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_struct.h index 756985a0470c..e36743cc8a03 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi1_mem_s_struct.h @@ -29,8 +29,9 @@ typedef union { uint32_t reserved_8:9; /** flash_pe : R/W/SC; bitpos: [17]; default: 0; * In user mode, it is set to indicate that program/erase operation will be triggered. - * The bit is combined with spi1_mem_s_usr bit. The bit will be cleared once the + * The bit is combined with spi_mem_usr bit. The bit will be cleared once the * operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_pe:1; /** usr : R/W/SC; bitpos: [18]; default: 0; @@ -41,68 +42,81 @@ typedef union { /** flash_hpm : R/W/SC; bitpos: [19]; default: 0; * Drive Flash into high performance mode. The bit will be cleared once the operation * done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_hpm:1; /** flash_res : R/W/SC; bitpos: [20]; default: 0; * This bit combined with reg_resandres bit releases Flash from the power-down state * or high performance mode and obtains the devices ID. The bit will be cleared once * the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_res:1; /** flash_dp : R/W/SC; bitpos: [21]; default: 0; * Drive Flash into power down. An operation will be triggered when the bit is set. * The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_dp:1; /** flash_ce : R/W/SC; bitpos: [22]; default: 0; * Chip erase enable. Chip erase operation will be triggered when the bit is set. The * bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_ce:1; /** flash_be : R/W/SC; bitpos: [23]; default: 0; * Block erase enable(32KB) . Block erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_be:1; /** flash_se : R/W/SC; bitpos: [24]; default: 0; * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_se:1; /** flash_pp : R/W/SC; bitpos: [25]; default: 0; * Page program enable(1 byte ~256 bytes data to be programmed). Page program * operation will be triggered when the bit is set. The bit will be cleared once the * operation done .1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_pp:1; /** flash_wrsr : R/W/SC; bitpos: [26]; default: 0; * Write status register enable. Write status operation will be triggered when the * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wrsr:1; /** flash_rdsr : R/W/SC; bitpos: [27]; default: 0; * Read status register-1. Read status operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_rdsr:1; /** flash_rdid : R/W/SC; bitpos: [28]; default: 0; * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_rdid:1; /** flash_wrdi : R/W/SC; bitpos: [29]; default: 0; * Write flash disable. Write disable command will be sent when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wrdi:1; /** flash_wren : R/W/SC; bitpos: [30]; default: 0; * Write flash enable. Write enable command will be sent when the bit is set. The bit * will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wren:1; /** flash_read : R/W/SC; bitpos: [31]; default: 0; * Read flash enable. Read flash operation will be triggered when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_read:1; }; @@ -130,7 +144,7 @@ typedef union { struct { uint32_t reserved_0:9; /** ck_out_edge : R/W; bitpos: [9]; default: 0; - * the bit combined with spi1_mem_s_mosi_delay_mode bits to set mosi signal delay mode. + * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. */ uint32_t ck_out_edge:1; uint32_t reserved_10:2; @@ -152,12 +166,12 @@ typedef union { uint32_t fwrite_qio:1; uint32_t reserved_16:8; /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; - * read-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: + * read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. */ uint32_t usr_miso_highpart:1; /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; - * write-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1: + * write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: * enable 0: disable. */ uint32_t usr_mosi_highpart:1; @@ -195,7 +209,7 @@ typedef union { typedef union { struct { /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; - * The length in spi1_mem_s_clk cycles of dummy phase. The register value shall be + * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). */ uint32_t usr_dummy_cyclelen:6; @@ -268,16 +282,18 @@ typedef union { /** fcs_crc_en : R/W; bitpos: [10]; default: 0; * For SPI1, initialize crc32 module before writing encrypted data to flash. Active * low. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fcs_crc_en:1; /** tx_crc_en : R/W; bitpos: [11]; default: 0; * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t tx_crc_en:1; uint32_t reserved_12:1; /** fastrd_mode : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: spi1_mem_s_fread_qio, spi1_mem_s_fread_dio, spi1_mem_s_fread_qout - * and spi1_mem_s_fread_dout. 1: enable 0: disable. + * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout + * and spi_mem_fread_dout. 1: enable 0: disable. */ uint32_t fastrd_mode:1; /** fread_dual : R/W; bitpos: [14]; default: 0; @@ -286,7 +302,8 @@ typedef union { uint32_t fread_dual:1; /** resandres : R/W; bitpos: [15]; default: 1; * The Device ID is read out to SPI1_MEM_S_RD_STATUS register, this bit combine with - * spi1_mem_s_flash_res bit. 1: enable 0: disable. + * spi_mem_flash_res bit. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t resandres:1; uint32_t reserved_16:2; @@ -309,6 +326,7 @@ typedef union { /** wrsr_2b : R/W; bitpos: [22]; default: 0; * two bytes data will be written to status register when it is set. 1: enable 0: * disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wrsr_2b:1; /** fread_dio : R/W; bitpos: [23]; default: 0; @@ -338,11 +356,23 @@ typedef union { */ uint32_t clk_mode:2; /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * + * 512) SPI_CLK cycles. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t cs_hold_dly_res:10; - uint32_t reserved_12:20; + /** cs_hold_dly_per : R/W; bitpos: [20:12]; default: 511; + * After PER command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DLY_PER[8:0] * 128) + * SPI_CLK cycles. + */ + uint32_t cs_hold_dly_per:9; + uint32_t reserved_21:2; + /** cs_hold_dly_per_en : R/W; bitpos: [23]; default: 0; + * 1: use SPI1_MEM_S_CS_HOLD_DLY_PER for per, use SPI1_MEM_S_CS_HOLD_DELAY_RES for + * pes/dp/hpm . 0: use SPI1_MEM_S_CS_HOLD_DELAY_RES for pes/dp/hpm/per . + */ + uint32_t cs_hold_dly_per_en:1; + uint32_t reserved_24:8; }; uint32_t val; } spi1_mem_s_ctrl1_reg_t; @@ -367,16 +397,16 @@ typedef union { typedef union { struct { /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi1_mem_s_clkcnt_N. + * In the master mode it must be equal to SPI1_MEM_S_CLKCNT_N. */ uint32_t clkcnt_l:8; /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi1_mem_s_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI1_MEM_S_CLKCNT_N+1)/2-1). */ uint32_t clkcnt_h:8; /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi1_mem_s_clk. So spi1_mem_s_clk frequency is - * system/(spi1_mem_s_clkcnt_N+1) + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(SPI1_MEM_S_CLKCNT_N+1) */ uint32_t clkcnt_n:8; uint32_t reserved_24:7; @@ -422,11 +452,12 @@ typedef union { typedef union { struct { /** status : R/W/SS; bitpos: [15:0]; default: 0; - * The value is stored when set spi1_mem_s_flash_rdsr bit and spi1_mem_s_flash_res bit. + * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. */ uint32_t status:16; /** wb_mode : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi1_mem_s_fastrd_mode bit. + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wb_mode:8; uint32_t reserved_24:8; @@ -471,37 +502,44 @@ typedef union { uint32_t reserved_0:1; /** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t cache_usr_addr_4byte:1; uint32_t reserved_2:1; /** fdin_dual : R/W; bitpos: [3]; default: 0; * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with - * spi1_mem_s_fread_dio. + * spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdin_dual:1; /** fdout_dual : R/W; bitpos: [4]; default: 0; * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdout_dual:1; /** faddr_dual : R/W; bitpos: [5]; default: 0; * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_dio. + * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t faddr_dual:1; /** fdin_quad : R/W; bitpos: [6]; default: 0; * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdin_quad:1; /** fdout_quad : R/W; bitpos: [7]; default: 0; * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdout_quad:1; /** faddr_quad : R/W; bitpos: [8]; default: 0; * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same - * with spi1_mem_s_fread_qio. + * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t faddr_quad:1; uint32_t reserved_9:23; @@ -531,8 +569,8 @@ typedef union { uint32_t waiti_addr_en:1; /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0; * When SPI1_MEM_S_WAITI_ADDR_EN is set, the cycle length of sent out address is - * (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when - * SPI1_MEM_S_WAITI_ADDR_EN is cleared. + * (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active + * when SPI1_MEM_S_WAITI_ADDR_EN is cleared. */ uint32_t waiti_addr_cyclelen:2; uint32_t reserved_5:4; @@ -613,8 +651,8 @@ typedef union { */ uint32_t pes_end_en:1; /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4; - * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, it - * will be treated as check pass. + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, + * it will be treated as check pass. */ uint32_t sus_timeout_cnt:7; }; @@ -655,34 +693,34 @@ typedef union { uint32_t wait_pesr_cmd_2b:1; /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0; * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM - * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after HPM command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after HPM command is sent. */ uint32_t flash_hpm_dly_128:1; /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0; * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES - * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after RES command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after RES command is sent. */ uint32_t flash_res_dly_128:1; /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0; * 1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP - * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - * after DP command is sent. + * command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + * cycles after DP command is sent. */ uint32_t flash_dp_dly_128:1; /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0; * Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: - * SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is - * sent. + * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. + * 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER + * command is sent. */ uint32_t flash_per_dly_128:1; /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0; * Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits - * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: - * SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is - * sent. + * (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. + * 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES + * command is sent. */ uint32_t flash_pes_dly_128:1; /** spi0_lock_en : R/W; bitpos: [7]; default: 0; @@ -739,8 +777,8 @@ typedef union { uint32_t fmem_usr_ddr_dqs_thd:7; /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ uint32_t fmem_ddr_dqs_loop:1; @@ -1105,19 +1143,19 @@ typedef union { */ uint32_t pes_end_int_raw:1; /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE - * is sent and flash is already idle. 0: Others. + * The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when + * WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. */ uint32_t wpe_end_int_raw:1; /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st + * is changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ uint32_t slv_st_end_int_raw:1; /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is - * changed from non idle state to idle state. 0: Others. + * The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st + * is changed from non idle state to idle state. 0: Others. */ uint32_t mst_st_end_int_raw:1; uint32_t reserved_5:5; @@ -1196,7 +1234,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 34673216; + /** date : R/W; bitpos: [27:0]; default: 38801712; * Version control register */ uint32_t date:28; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_reg.h index d105863da381..14dcc8ec5015 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_reg.h @@ -34,9 +34,9 @@ extern "C" { #define SPI_MEM_C_SLV_ST_V 0x0000000FU #define SPI_MEM_C_SLV_ST_S 4 /** SPI_MEM_C_USR : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when SPI_MEM_C_AXI_REQ_EN is cleared. An operation - * will be triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. + * SPI0 USR_CMD start bit, only used when SPI_MEM_C_AXI_REQ_EN is cleared. An + * operation will be triggered when the bit is set. The bit will be cleared once the + * operation done.1: enable 0: disable. */ #define SPI_MEM_C_USR (BIT(18)) #define SPI_MEM_C_USR_M (SPI_MEM_C_USR_V << SPI_MEM_C_USR_S) @@ -117,8 +117,8 @@ extern "C" { #define SPI_MEM_C_FCMD_OCT_V 0x00000001U #define SPI_MEM_C_FCMD_OCT_S 9 /** SPI_MEM_C_FASTRD_MODE : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: SPI_MEM_C_FREAD_QIO, SPI_MEM_C_FREAD_DIO, SPI_MEM_C_FREAD_QOUT - * and SPI_MEM_C_FREAD_DOUT. 1: enable 0: disable. + * This bit enable the bits: SPI_MEM_C_FREAD_QIO, SPI_MEM_C_FREAD_DIO, + * SPI_MEM_C_FREAD_QOUT and SPI_MEM_C_FREAD_DOUT. 1: enable 0: disable. */ #define SPI_MEM_C_FASTRD_MODE (BIT(13)) #define SPI_MEM_C_FASTRD_MODE_M (SPI_MEM_C_FASTRD_MODE_V << SPI_MEM_C_FASTRD_MODE_S) @@ -220,14 +220,6 @@ extern "C" { #define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_M (SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_V << SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_S) #define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U #define SPI_MEM_C_AW_SIZE0_1_SUPPORT_EN_S 22 -/** SPI_MEM_C_AXI_RDATA_BACK_FAST : HRO; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ -#define SPI_MEM_C_AXI_RDATA_BACK_FAST (BIT(23)) -#define SPI_MEM_C_AXI_RDATA_BACK_FAST_M (SPI_MEM_C_AXI_RDATA_BACK_FAST_V << SPI_MEM_C_AXI_RDATA_BACK_FAST_S) -#define SPI_MEM_C_AXI_RDATA_BACK_FAST_V 0x00000001U -#define SPI_MEM_C_AXI_RDATA_BACK_FAST_S 23 /** SPI_MEM_C_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded @@ -316,8 +308,8 @@ extern "C" { #define SPI_MEM_C_CS_HOLD_TIME_V 0x0000001FU #define SPI_MEM_C_CS_HOLD_TIME_S 5 /** SPI_MEM_C_ECC_CS_HOLD_TIME : HRO; bitpos: [12:10]; default: 3; - * SPI_MEM_C_CS_HOLD_TIME + SPI_MEM_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC - * mode when accessed flash. + * SPI_MEM_C_CS_HOLD_TIME + SPI_MEM_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in + * ECC mode when accessed flash. */ #define SPI_MEM_C_ECC_CS_HOLD_TIME 0x00000007U #define SPI_MEM_C_ECC_CS_HOLD_TIME_M (SPI_MEM_C_ECC_CS_HOLD_TIME_V << SPI_MEM_C_ECC_CS_HOLD_TIME_S) @@ -370,14 +362,14 @@ extern "C" { */ #define SPI_MEM_C_CLOCK_REG (DR_REG_FLASH_SPI0_BASE + 0x14) /** SPI_MEM_C_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_C_CLKCNT_N. */ #define SPI_MEM_C_CLKCNT_L 0x000000FFU #define SPI_MEM_C_CLKCNT_L_M (SPI_MEM_C_CLKCNT_L_V << SPI_MEM_C_CLKCNT_L_S) #define SPI_MEM_C_CLKCNT_L_V 0x000000FFU #define SPI_MEM_C_CLKCNT_L_S 0 /** SPI_MEM_C_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_C_CLKCNT_N+1)/2-1). */ #define SPI_MEM_C_CLKCNT_H 0x000000FFU #define SPI_MEM_C_CLKCNT_H_M (SPI_MEM_C_CLKCNT_H_V << SPI_MEM_C_CLKCNT_H_S) @@ -385,7 +377,7 @@ extern "C" { #define SPI_MEM_C_CLKCNT_H_S 8 /** SPI_MEM_C_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) + * system/(SPI_MEM_C_CLKCNT_N+1) */ #define SPI_MEM_C_CLKCNT_N 0x000000FFU #define SPI_MEM_C_CLKCNT_N_M (SPI_MEM_C_CLKCNT_N_V << SPI_MEM_C_CLKCNT_N_S) @@ -486,10 +478,46 @@ extern "C" { #define SPI_MEM_C_USR_COMMAND_BITLEN_V 0x0000000FU #define SPI_MEM_C_USR_COMMAND_BITLEN_S 28 +/** SPI_MEM_C_RD_STATUS_REG register + * SPI0 read control register. + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_C_RD_STATUS_REG (DR_REG_FLASH_SPI0_BASE + 0x2c) +/** SPI_MEM_C_WB_MODE : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_WB_MODE 0x000000FFU +#define SPI_MEM_C_WB_MODE_M (SPI_MEM_C_WB_MODE_V << SPI_MEM_C_WB_MODE_S) +#define SPI_MEM_C_WB_MODE_V 0x000000FFU +#define SPI_MEM_C_WB_MODE_S 16 + /** SPI_MEM_C_MISC_REG register * SPI0 misc register */ #define SPI_MEM_C_MISC_REG (DR_REG_FLASH_SPI0_BASE + 0x34) +/** SPI_MEM_C_DQ_OE_CTRL : R/W; bitpos: [4]; default: 1; + * For SPI BUS IO, APB ctrl IO DQ OE func.1: enable 0: disable. + */ +#define SPI_MEM_C_DQ_OE_CTRL (BIT(4)) +#define SPI_MEM_C_DQ_OE_CTRL_M (SPI_MEM_C_DQ_OE_CTRL_V << SPI_MEM_C_DQ_OE_CTRL_S) +#define SPI_MEM_C_DQ_OE_CTRL_V 0x00000001U +#define SPI_MEM_C_DQ_OE_CTRL_S 4 +/** SPI_MEM_C_CK_OE_CTRL : R/W; bitpos: [5]; default: 1; + * For SPI BUS IO, APB ctrl IO CK OE func.1: enable 0: disable. + */ +#define SPI_MEM_C_CK_OE_CTRL (BIT(5)) +#define SPI_MEM_C_CK_OE_CTRL_M (SPI_MEM_C_CK_OE_CTRL_V << SPI_MEM_C_CK_OE_CTRL_S) +#define SPI_MEM_C_CK_OE_CTRL_V 0x00000001U +#define SPI_MEM_C_CK_OE_CTRL_S 5 +/** SPI_MEM_C_CS_OE_CTRL : R/W; bitpos: [6]; default: 1; + * For SPI BUS IO, APB ctrl IO CS OE func.1: enable 0: disable. + */ +#define SPI_MEM_C_CS_OE_CTRL (BIT(6)) +#define SPI_MEM_C_CS_OE_CTRL_M (SPI_MEM_C_CS_OE_CTRL_V << SPI_MEM_C_CS_OE_CTRL_S) +#define SPI_MEM_C_CS_OE_CTRL_V 0x00000001U +#define SPI_MEM_C_CS_OE_CTRL_S 6 /** SPI_MEM_C_FSUB_PIN : HRO; bitpos: [7]; default: 0; * For SPI0, flash is connected to SUBPINs. */ @@ -523,11 +551,129 @@ extern "C" { * SPI0 bit mode control register. */ #define SPI_MEM_C_CACHE_FCTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x3c) +/** SPI_MEM_C_AXI_REQ_EN : R/W; bitpos: [0]; default: 0; + * For SPI0, AXI master access enable, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_AXI_REQ_EN (BIT(0)) +#define SPI_MEM_C_AXI_REQ_EN_M (SPI_MEM_C_AXI_REQ_EN_V << SPI_MEM_C_AXI_REQ_EN_S) +#define SPI_MEM_C_AXI_REQ_EN_V 0x00000001U +#define SPI_MEM_C_AXI_REQ_EN_S 0 +/** SPI_MEM_C_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; + * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_USR_ADDR_4BYTE (BIT(1)) +#define SPI_MEM_C_CACHE_USR_ADDR_4BYTE_M (SPI_MEM_C_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_C_CACHE_USR_ADDR_4BYTE_S) +#define SPI_MEM_C_CACHE_USR_ADDR_4BYTE_V 0x00000001U +#define SPI_MEM_C_CACHE_USR_ADDR_4BYTE_S 1 +/** SPI_MEM_C_CACHE_FLASH_USR_CMD : R/W; bitpos: [2]; default: 0; + * For SPI0, cache read flash for user define command, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_MEM_C_CACHE_FLASH_USR_CMD_M (SPI_MEM_C_CACHE_FLASH_USR_CMD_V << SPI_MEM_C_CACHE_FLASH_USR_CMD_S) +#define SPI_MEM_C_CACHE_FLASH_USR_CMD_V 0x00000001U +#define SPI_MEM_C_CACHE_FLASH_USR_CMD_S 2 +/** SPI_MEM_C_FDIN_DUAL : R/W; bitpos: [3]; default: 0; + * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_FDIN_DUAL (BIT(3)) +#define SPI_MEM_C_FDIN_DUAL_M (SPI_MEM_C_FDIN_DUAL_V << SPI_MEM_C_FDIN_DUAL_S) +#define SPI_MEM_C_FDIN_DUAL_V 0x00000001U +#define SPI_MEM_C_FDIN_DUAL_S 3 +/** SPI_MEM_C_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; + * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_FDOUT_DUAL (BIT(4)) +#define SPI_MEM_C_FDOUT_DUAL_M (SPI_MEM_C_FDOUT_DUAL_V << SPI_MEM_C_FDOUT_DUAL_S) +#define SPI_MEM_C_FDOUT_DUAL_V 0x00000001U +#define SPI_MEM_C_FDOUT_DUAL_S 4 +/** SPI_MEM_C_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_FADDR_DUAL (BIT(5)) +#define SPI_MEM_C_FADDR_DUAL_M (SPI_MEM_C_FADDR_DUAL_V << SPI_MEM_C_FADDR_DUAL_S) +#define SPI_MEM_C_FADDR_DUAL_V 0x00000001U +#define SPI_MEM_C_FADDR_DUAL_S 5 +/** SPI_MEM_C_FDIN_QUAD : R/W; bitpos: [6]; default: 0; + * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_FDIN_QUAD (BIT(6)) +#define SPI_MEM_C_FDIN_QUAD_M (SPI_MEM_C_FDIN_QUAD_V << SPI_MEM_C_FDIN_QUAD_S) +#define SPI_MEM_C_FDIN_QUAD_V 0x00000001U +#define SPI_MEM_C_FDIN_QUAD_S 6 +/** SPI_MEM_C_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; + * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_FDOUT_QUAD (BIT(7)) +#define SPI_MEM_C_FDOUT_QUAD_M (SPI_MEM_C_FDOUT_QUAD_V << SPI_MEM_C_FDOUT_QUAD_S) +#define SPI_MEM_C_FDOUT_QUAD_V 0x00000001U +#define SPI_MEM_C_FDOUT_QUAD_S 7 +/** SPI_MEM_C_FADDR_QUAD : R/W; bitpos: [8]; default: 0; + * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_FADDR_QUAD (BIT(8)) +#define SPI_MEM_C_FADDR_QUAD_M (SPI_MEM_C_FADDR_QUAD_V << SPI_MEM_C_FADDR_QUAD_S) +#define SPI_MEM_C_FADDR_QUAD_V 0x00000001U +#define SPI_MEM_C_FADDR_QUAD_S 8 +/** SPI_MEM_C_ARB_WEI_EN : HRO; bitpos: [9]; default: 0; + * To enable SPI0 arbiter weight func while AXI read/write access SPI0 1: enable 0: + * disable. + */ +#define SPI_MEM_C_ARB_WEI_EN (BIT(9)) +#define SPI_MEM_C_ARB_WEI_EN_M (SPI_MEM_C_ARB_WEI_EN_V << SPI_MEM_C_ARB_WEI_EN_S) +#define SPI_MEM_C_ARB_WEI_EN_V 0x00000001U +#define SPI_MEM_C_ARB_WEI_EN_S 9 +/** SPI_MEM_C_ARB_REQ0_PRI : HRO; bitpos: [10]; default: 0; + * To set AXI read priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ +#define SPI_MEM_C_ARB_REQ0_PRI (BIT(10)) +#define SPI_MEM_C_ARB_REQ0_PRI_M (SPI_MEM_C_ARB_REQ0_PRI_V << SPI_MEM_C_ARB_REQ0_PRI_S) +#define SPI_MEM_C_ARB_REQ0_PRI_V 0x00000001U +#define SPI_MEM_C_ARB_REQ0_PRI_S 10 +/** SPI_MEM_C_ARB_REQ1_PRI : HRO; bitpos: [11]; default: 0; + * To set AXI write priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ +#define SPI_MEM_C_ARB_REQ1_PRI (BIT(11)) +#define SPI_MEM_C_ARB_REQ1_PRI_M (SPI_MEM_C_ARB_REQ1_PRI_V << SPI_MEM_C_ARB_REQ1_PRI_S) +#define SPI_MEM_C_ARB_REQ1_PRI_V 0x00000001U +#define SPI_MEM_C_ARB_REQ1_PRI_S 11 +/** SPI_MEM_C_ARB_REQ0_WEI : HRO; bitpos: [15:12]; default: 0; + * To set AXI read priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ +#define SPI_MEM_C_ARB_REQ0_WEI 0x0000000FU +#define SPI_MEM_C_ARB_REQ0_WEI_M (SPI_MEM_C_ARB_REQ0_WEI_V << SPI_MEM_C_ARB_REQ0_WEI_S) +#define SPI_MEM_C_ARB_REQ0_WEI_V 0x0000000FU +#define SPI_MEM_C_ARB_REQ0_WEI_S 12 +/** SPI_MEM_C_ARB_REQ1_WEI : HRO; bitpos: [19:16]; default: 0; + * To set AXI write priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ +#define SPI_MEM_C_ARB_REQ1_WEI 0x0000000FU +#define SPI_MEM_C_ARB_REQ1_WEI_M (SPI_MEM_C_ARB_REQ1_WEI_V << SPI_MEM_C_ARB_REQ1_WEI_S) +#define SPI_MEM_C_ARB_REQ1_WEI_V 0x0000000FU +#define SPI_MEM_C_ARB_REQ1_WEI_S 16 /** SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN : HRO; bitpos: [30]; default: 1; * Set this bit to check AXI read/write the same address region. */ #define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) -#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_M (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S) +#define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_M (SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_V << SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_S) #define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_V 0x00000001U #define SPI_MEM_C_SAME_AW_AR_ADDR_CHK_EN_S 30 /** SPI_MEM_C_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1; @@ -535,14 +681,247 @@ extern "C" { * SLV_ERR will be replied to BRESP/RRESP. */ #define SPI_MEM_C_CLOSE_AXI_INF_EN (BIT(31)) -#define SPI_MEM_C_CLOSE_AXI_INF_EN_M (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S) +#define SPI_MEM_C_CLOSE_AXI_INF_EN_M (SPI_MEM_C_CLOSE_AXI_INF_EN_V << SPI_MEM_C_CLOSE_AXI_INF_EN_S) #define SPI_MEM_C_CLOSE_AXI_INF_EN_V 0x00000001U #define SPI_MEM_C_CLOSE_AXI_INF_EN_S 31 +/** SPI_MEM_C_CACHE_SCTRL_REG register + * SPI0 external RAM control register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_C_CACHE_SCTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x40) +/** SPI_MEM_C_CACHE_USR_SADDR_4BYTE : HRO; bitpos: [0]; default: 0; + * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: + * enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_USR_SADDR_4BYTE (BIT(0)) +#define SPI_MEM_C_CACHE_USR_SADDR_4BYTE_M (SPI_MEM_C_CACHE_USR_SADDR_4BYTE_V << SPI_MEM_C_CACHE_USR_SADDR_4BYTE_S) +#define SPI_MEM_C_CACHE_USR_SADDR_4BYTE_V 0x00000001U +#define SPI_MEM_C_CACHE_USR_SADDR_4BYTE_S 0 +/** SPI_MEM_C_USR_SRAM_DIO : HRO; bitpos: [1]; default: 0; + * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_USR_SRAM_DIO (BIT(1)) +#define SPI_MEM_C_USR_SRAM_DIO_M (SPI_MEM_C_USR_SRAM_DIO_V << SPI_MEM_C_USR_SRAM_DIO_S) +#define SPI_MEM_C_USR_SRAM_DIO_V 0x00000001U +#define SPI_MEM_C_USR_SRAM_DIO_S 1 +/** SPI_MEM_C_USR_SRAM_QIO : HRO; bitpos: [2]; default: 0; + * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_USR_SRAM_QIO (BIT(2)) +#define SPI_MEM_C_USR_SRAM_QIO_M (SPI_MEM_C_USR_SRAM_QIO_V << SPI_MEM_C_USR_SRAM_QIO_S) +#define SPI_MEM_C_USR_SRAM_QIO_V 0x00000001U +#define SPI_MEM_C_USR_SRAM_QIO_S 2 +/** SPI_MEM_C_USR_WR_SRAM_DUMMY : HRO; bitpos: [3]; default: 0; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write + * operations. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_MEM_C_USR_WR_SRAM_DUMMY_M (SPI_MEM_C_USR_WR_SRAM_DUMMY_V << SPI_MEM_C_USR_WR_SRAM_DUMMY_S) +#define SPI_MEM_C_USR_WR_SRAM_DUMMY_V 0x00000001U +#define SPI_MEM_C_USR_WR_SRAM_DUMMY_S 3 +/** SPI_MEM_C_USR_RD_SRAM_DUMMY : HRO; bitpos: [4]; default: 1; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read + * operations. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_MEM_C_USR_RD_SRAM_DUMMY_M (SPI_MEM_C_USR_RD_SRAM_DUMMY_V << SPI_MEM_C_USR_RD_SRAM_DUMMY_S) +#define SPI_MEM_C_USR_RD_SRAM_DUMMY_V 0x00000001U +#define SPI_MEM_C_USR_RD_SRAM_DUMMY_S 4 +/** SPI_MEM_C_CACHE_SRAM_USR_RCMD : HRO; bitpos: [5]; default: 1; + * For SPI0, In the external RAM mode cache read external RAM for user define command. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_MEM_C_CACHE_SRAM_USR_RCMD_M (SPI_MEM_C_CACHE_SRAM_USR_RCMD_V << SPI_MEM_C_CACHE_SRAM_USR_RCMD_S) +#define SPI_MEM_C_CACHE_SRAM_USR_RCMD_V 0x00000001U +#define SPI_MEM_C_CACHE_SRAM_USR_RCMD_S 5 +/** SPI_MEM_C_SRAM_RDUMMY_CYCLELEN : HRO; bitpos: [11:6]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SRAM_RDUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_C_SRAM_RDUMMY_CYCLELEN_M (SPI_MEM_C_SRAM_RDUMMY_CYCLELEN_V << SPI_MEM_C_SRAM_RDUMMY_CYCLELEN_S) +#define SPI_MEM_C_SRAM_RDUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_C_SRAM_RDUMMY_CYCLELEN_S 6 +/** SPI_MEM_C_SRAM_ADDR_BITLEN : HRO; bitpos: [19:14]; default: 23; + * For SPI0, In the external RAM mode, it is the length in bits of address phase. The + * register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SRAM_ADDR_BITLEN 0x0000003FU +#define SPI_MEM_C_SRAM_ADDR_BITLEN_M (SPI_MEM_C_SRAM_ADDR_BITLEN_V << SPI_MEM_C_SRAM_ADDR_BITLEN_S) +#define SPI_MEM_C_SRAM_ADDR_BITLEN_V 0x0000003FU +#define SPI_MEM_C_SRAM_ADDR_BITLEN_S 14 +/** SPI_MEM_C_CACHE_SRAM_USR_WCMD : HRO; bitpos: [20]; default: 1; + * For SPI0, In the external RAM mode cache write sram for user define command + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_SRAM_USR_WCMD (BIT(20)) +#define SPI_MEM_C_CACHE_SRAM_USR_WCMD_M (SPI_MEM_C_CACHE_SRAM_USR_WCMD_V << SPI_MEM_C_CACHE_SRAM_USR_WCMD_S) +#define SPI_MEM_C_CACHE_SRAM_USR_WCMD_V 0x00000001U +#define SPI_MEM_C_CACHE_SRAM_USR_WCMD_S 20 +/** SPI_MEM_C_SRAM_OCT : HRO; bitpos: [21]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SRAM_OCT (BIT(21)) +#define SPI_MEM_C_SRAM_OCT_M (SPI_MEM_C_SRAM_OCT_V << SPI_MEM_C_SRAM_OCT_S) +#define SPI_MEM_C_SRAM_OCT_V 0x00000001U +#define SPI_MEM_C_SRAM_OCT_S 21 +/** SPI_MEM_C_SRAM_WDUMMY_CYCLELEN : HRO; bitpos: [27:22]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SRAM_WDUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_C_SRAM_WDUMMY_CYCLELEN_M (SPI_MEM_C_SRAM_WDUMMY_CYCLELEN_V << SPI_MEM_C_SRAM_WDUMMY_CYCLELEN_S) +#define SPI_MEM_C_SRAM_WDUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_C_SRAM_WDUMMY_CYCLELEN_S 22 + /** SPI_MEM_C_SRAM_CMD_REG register * SPI0 external RAM mode control register */ #define SPI_MEM_C_SRAM_CMD_REG (DR_REG_FLASH_SPI0_BASE + 0x44) +/** SPI_MEM_C_SCLK_MODE : HRO; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SCLK_MODE 0x00000003U +#define SPI_MEM_C_SCLK_MODE_M (SPI_MEM_C_SCLK_MODE_V << SPI_MEM_C_SCLK_MODE_S) +#define SPI_MEM_C_SCLK_MODE_V 0x00000003U +#define SPI_MEM_C_SCLK_MODE_S 0 +/** SPI_MEM_C_SWB_MODE : HRO; bitpos: [9:2]; default: 0; + * Mode bits in the external RAM fast read mode it is combined with + * spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SWB_MODE 0x000000FFU +#define SPI_MEM_C_SWB_MODE_M (SPI_MEM_C_SWB_MODE_V << SPI_MEM_C_SWB_MODE_S) +#define SPI_MEM_C_SWB_MODE_V 0x000000FFU +#define SPI_MEM_C_SWB_MODE_S 2 +/** SPI_MEM_C_SDIN_DUAL : HRO; bitpos: [10]; default: 0; + * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDIN_DUAL (BIT(10)) +#define SPI_MEM_C_SDIN_DUAL_M (SPI_MEM_C_SDIN_DUAL_V << SPI_MEM_C_SDIN_DUAL_S) +#define SPI_MEM_C_SDIN_DUAL_V 0x00000001U +#define SPI_MEM_C_SDIN_DUAL_S 10 +/** SPI_MEM_C_SDOUT_DUAL : HRO; bitpos: [11]; default: 0; + * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDOUT_DUAL (BIT(11)) +#define SPI_MEM_C_SDOUT_DUAL_M (SPI_MEM_C_SDOUT_DUAL_V << SPI_MEM_C_SDOUT_DUAL_S) +#define SPI_MEM_C_SDOUT_DUAL_V 0x00000001U +#define SPI_MEM_C_SDOUT_DUAL_S 11 +/** SPI_MEM_C_SADDR_DUAL : HRO; bitpos: [12]; default: 0; + * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SADDR_DUAL (BIT(12)) +#define SPI_MEM_C_SADDR_DUAL_M (SPI_MEM_C_SADDR_DUAL_V << SPI_MEM_C_SADDR_DUAL_S) +#define SPI_MEM_C_SADDR_DUAL_V 0x00000001U +#define SPI_MEM_C_SADDR_DUAL_S 12 +/** SPI_MEM_C_SDIN_QUAD : HRO; bitpos: [14]; default: 0; + * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDIN_QUAD (BIT(14)) +#define SPI_MEM_C_SDIN_QUAD_M (SPI_MEM_C_SDIN_QUAD_V << SPI_MEM_C_SDIN_QUAD_S) +#define SPI_MEM_C_SDIN_QUAD_V 0x00000001U +#define SPI_MEM_C_SDIN_QUAD_S 14 +/** SPI_MEM_C_SDOUT_QUAD : HRO; bitpos: [15]; default: 0; + * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDOUT_QUAD (BIT(15)) +#define SPI_MEM_C_SDOUT_QUAD_M (SPI_MEM_C_SDOUT_QUAD_V << SPI_MEM_C_SDOUT_QUAD_S) +#define SPI_MEM_C_SDOUT_QUAD_V 0x00000001U +#define SPI_MEM_C_SDOUT_QUAD_S 15 +/** SPI_MEM_C_SADDR_QUAD : HRO; bitpos: [16]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SADDR_QUAD (BIT(16)) +#define SPI_MEM_C_SADDR_QUAD_M (SPI_MEM_C_SADDR_QUAD_V << SPI_MEM_C_SADDR_QUAD_S) +#define SPI_MEM_C_SADDR_QUAD_V 0x00000001U +#define SPI_MEM_C_SADDR_QUAD_S 16 +/** SPI_MEM_C_SCMD_QUAD : HRO; bitpos: [17]; default: 0; + * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SCMD_QUAD (BIT(17)) +#define SPI_MEM_C_SCMD_QUAD_M (SPI_MEM_C_SCMD_QUAD_V << SPI_MEM_C_SCMD_QUAD_S) +#define SPI_MEM_C_SCMD_QUAD_V 0x00000001U +#define SPI_MEM_C_SCMD_QUAD_S 17 +/** SPI_MEM_C_SDIN_OCT : HRO; bitpos: [18]; default: 0; + * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDIN_OCT (BIT(18)) +#define SPI_MEM_C_SDIN_OCT_M (SPI_MEM_C_SDIN_OCT_V << SPI_MEM_C_SDIN_OCT_S) +#define SPI_MEM_C_SDIN_OCT_V 0x00000001U +#define SPI_MEM_C_SDIN_OCT_S 18 +/** SPI_MEM_C_SDOUT_OCT : HRO; bitpos: [19]; default: 0; + * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDOUT_OCT (BIT(19)) +#define SPI_MEM_C_SDOUT_OCT_M (SPI_MEM_C_SDOUT_OCT_V << SPI_MEM_C_SDOUT_OCT_S) +#define SPI_MEM_C_SDOUT_OCT_V 0x00000001U +#define SPI_MEM_C_SDOUT_OCT_S 19 +/** SPI_MEM_C_SADDR_OCT : HRO; bitpos: [20]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SADDR_OCT (BIT(20)) +#define SPI_MEM_C_SADDR_OCT_M (SPI_MEM_C_SADDR_OCT_V << SPI_MEM_C_SADDR_OCT_S) +#define SPI_MEM_C_SADDR_OCT_V 0x00000001U +#define SPI_MEM_C_SADDR_OCT_S 20 +/** SPI_MEM_C_SCMD_OCT : HRO; bitpos: [21]; default: 0; + * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SCMD_OCT (BIT(21)) +#define SPI_MEM_C_SCMD_OCT_M (SPI_MEM_C_SCMD_OCT_V << SPI_MEM_C_SCMD_OCT_S) +#define SPI_MEM_C_SCMD_OCT_V 0x00000001U +#define SPI_MEM_C_SCMD_OCT_S 21 +/** SPI_MEM_C_SDUMMY_RIN : R/W; bitpos: [22]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDUMMY_RIN (BIT(22)) +#define SPI_MEM_C_SDUMMY_RIN_M (SPI_MEM_C_SDUMMY_RIN_V << SPI_MEM_C_SDUMMY_RIN_S) +#define SPI_MEM_C_SDUMMY_RIN_V 0x00000001U +#define SPI_MEM_C_SDUMMY_RIN_S 22 +/** SPI_MEM_C_SDUMMY_WOUT : HRO; bitpos: [23]; default: 0; + * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SDUMMY_WOUT (BIT(23)) +#define SPI_MEM_C_SDUMMY_WOUT_M (SPI_MEM_C_SDUMMY_WOUT_V << SPI_MEM_C_SDUMMY_WOUT_S) +#define SPI_MEM_C_SDUMMY_WOUT_V 0x00000001U +#define SPI_MEM_C_SDUMMY_WOUT_S 23 /** SPI_MEM_C_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [24]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_DQS is output by the MSPI controller. @@ -576,16 +955,107 @@ extern "C" { #define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_V 0x00000001U #define SPI_MEM_C_SMEM_DATA_IE_ALWAYS_ON_S 31 +/** SPI_MEM_C_SRAM_DRD_CMD_REG register + * SPI0 external RAM DDR read command control register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_C_SRAM_DRD_CMD_REG (DR_REG_FLASH_SPI0_BASE + 0x48) +/** SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_VALUE : HRO; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the read command value of command phase + * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFFU +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_VALUE_M (SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_VALUE_V << SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_VALUE_S) +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_VALUE_V 0x0000FFFFU +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 +/** SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_BITLEN : HRO; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the length in bits of command phase for + * sram. The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000FU +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_BITLEN_M (SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_BITLEN_V << SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_BITLEN_S) +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0x0000000FU +#define SPI_MEM_C_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 + +/** SPI_MEM_C_SRAM_DWR_CMD_REG register + * SPI0 external RAM DDR write command control register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_C_SRAM_DWR_CMD_REG (DR_REG_FLASH_SPI0_BASE + 0x4c) +/** SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_VALUE : HRO; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the write command value of command phase + * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFFU +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_VALUE_M (SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_VALUE_V << SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_VALUE_S) +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_VALUE_V 0x0000FFFFU +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 +/** SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_BITLEN : HRO; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the in bits of command phase for sram. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000FU +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_BITLEN_M (SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_BITLEN_V << SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_BITLEN_S) +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0x0000000FU +#define SPI_MEM_C_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 + +/** SPI_MEM_C_SRAM_CLK_REG register + * SPI0 external RAM clock control register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_C_SRAM_CLK_REG (DR_REG_FLASH_SPI0_BASE + 0x50) +/** SPI_MEM_C_SCLKCNT_L : HRO; bitpos: [7:0]; default: 3; + * For SPI0 external RAM interface, it must be equal to SPI_MEM_C_SCLKCNT_N. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SCLKCNT_L 0x000000FFU +#define SPI_MEM_C_SCLKCNT_L_M (SPI_MEM_C_SCLKCNT_L_V << SPI_MEM_C_SCLKCNT_L_S) +#define SPI_MEM_C_SCLKCNT_L_V 0x000000FFU +#define SPI_MEM_C_SCLKCNT_L_S 0 +/** SPI_MEM_C_SCLKCNT_H : HRO; bitpos: [15:8]; default: 1; + * For SPI0 external RAM interface, it must be floor((SPI_MEM_C_SCLKCNT_N+1)/2-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SCLKCNT_H 0x000000FFU +#define SPI_MEM_C_SCLKCNT_H_M (SPI_MEM_C_SCLKCNT_H_V << SPI_MEM_C_SCLKCNT_H_S) +#define SPI_MEM_C_SCLKCNT_H_V 0x000000FFU +#define SPI_MEM_C_SCLKCNT_H_S 8 +/** SPI_MEM_C_SCLKCNT_N : HRO; bitpos: [23:16]; default: 3; + * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk + * frequency is system/(SPI_MEM_C_SCLKCNT_N+1) + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SCLKCNT_N 0x000000FFU +#define SPI_MEM_C_SCLKCNT_N_M (SPI_MEM_C_SCLKCNT_N_V << SPI_MEM_C_SCLKCNT_N_S) +#define SPI_MEM_C_SCLKCNT_N_V 0x000000FFU +#define SPI_MEM_C_SCLKCNT_N_S 16 +/** SPI_MEM_C_SCLK_EQU_SYSCLK : HRO; bitpos: [31]; default: 0; + * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk + * is divided from system clock. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_SCLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_C_SCLK_EQU_SYSCLK_M (SPI_MEM_C_SCLK_EQU_SYSCLK_V << SPI_MEM_C_SCLK_EQU_SYSCLK_S) +#define SPI_MEM_C_SCLK_EQU_SYSCLK_V 0x00000001U +#define SPI_MEM_C_SCLK_EQU_SYSCLK_S 31 + /** SPI_MEM_C_FSM_REG register * SPI0 FSM status register */ #define SPI_MEM_C_FSM_REG (DR_REG_FLASH_SPI0_BASE + 0x54) -/** SPI_MEM_C_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; +/** SPI_MEM_C_LOCK_DELAY_TIME : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ -#define SPI_MEM_C_LOCK_DELAY_TIME 0x0000001FU +#define SPI_MEM_C_LOCK_DELAY_TIME 0x00000FFFU #define SPI_MEM_C_LOCK_DELAY_TIME_M (SPI_MEM_C_LOCK_DELAY_TIME_V << SPI_MEM_C_LOCK_DELAY_TIME_S) -#define SPI_MEM_C_LOCK_DELAY_TIME_V 0x0000001FU +#define SPI_MEM_C_LOCK_DELAY_TIME_V 0x00000FFFU #define SPI_MEM_C_LOCK_DELAY_TIME_S 7 /** SPI_MEM_C_INT_ENA_REG register @@ -641,6 +1111,20 @@ extern "C" { #define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_S) #define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_V 0x00000001U #define SPI_MEM_C_AXI_WADDR_ERR_INT__ENA_S 9 +/** SPI_MEM_C_RX_TRANS_OVF_INT_ENA : HRO; bitpos: [26]; default: 0; + * The enable bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. + */ +#define SPI_MEM_C_RX_TRANS_OVF_INT_ENA (BIT(26)) +#define SPI_MEM_C_RX_TRANS_OVF_INT_ENA_M (SPI_MEM_C_RX_TRANS_OVF_INT_ENA_V << SPI_MEM_C_RX_TRANS_OVF_INT_ENA_S) +#define SPI_MEM_C_RX_TRANS_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_C_RX_TRANS_OVF_INT_ENA_S 26 +/** SPI_MEM_C_TX_TRANS_UDF_INT_ENA : HRO; bitpos: [27]; default: 0; + * The enable bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. + */ +#define SPI_MEM_C_TX_TRANS_UDF_INT_ENA (BIT(27)) +#define SPI_MEM_C_TX_TRANS_UDF_INT_ENA_M (SPI_MEM_C_TX_TRANS_UDF_INT_ENA_V << SPI_MEM_C_TX_TRANS_UDF_INT_ENA_S) +#define SPI_MEM_C_TX_TRANS_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_C_TX_TRANS_UDF_INT_ENA_S 27 /** SPI_MEM_C_INT_CLR_REG register * SPI0 interrupt clear register @@ -695,14 +1179,28 @@ extern "C" { #define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_S) #define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_V 0x00000001U #define SPI_MEM_C_AXI_WADDR_ERR_INT_CLR_S 9 +/** SPI_MEM_C_RX_TRANS_OVF_INT_CLR : HRO; bitpos: [26]; default: 0; + * The clear bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. + */ +#define SPI_MEM_C_RX_TRANS_OVF_INT_CLR (BIT(26)) +#define SPI_MEM_C_RX_TRANS_OVF_INT_CLR_M (SPI_MEM_C_RX_TRANS_OVF_INT_CLR_V << SPI_MEM_C_RX_TRANS_OVF_INT_CLR_S) +#define SPI_MEM_C_RX_TRANS_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_C_RX_TRANS_OVF_INT_CLR_S 26 +/** SPI_MEM_C_TX_TRANS_UDF_INT_CLR : HRO; bitpos: [27]; default: 0; + * The clear bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. + */ +#define SPI_MEM_C_TX_TRANS_UDF_INT_CLR (BIT(27)) +#define SPI_MEM_C_TX_TRANS_UDF_INT_CLR_M (SPI_MEM_C_TX_TRANS_UDF_INT_CLR_V << SPI_MEM_C_TX_TRANS_UDF_INT_CLR_S) +#define SPI_MEM_C_TX_TRANS_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_C_TX_TRANS_UDF_INT_CLR_S 27 /** SPI_MEM_C_INT_RAW_REG register * SPI0 interrupt raw register */ #define SPI_MEM_C_INT_RAW_REG (DR_REG_FLASH_SPI0_BASE + 0xc8) /** SPI_MEM_C_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * The raw bit for SPI_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st + * is changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ #define SPI_MEM_C_SLV_ST_END_INT_RAW (BIT(3)) @@ -710,32 +1208,33 @@ extern "C" { #define SPI_MEM_C_SLV_ST_END_INT_RAW_V 0x00000001U #define SPI_MEM_C_SLV_ST_END_INT_RAW_S 3 /** SPI_MEM_C_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is - * changed from non idle state to idle state. 0: Others. + * The raw bit for SPI_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st + * is changed from non idle state to idle state. 0: Others. */ #define SPI_MEM_C_MST_ST_END_INT_RAW (BIT(4)) #define SPI_MEM_C_MST_ST_END_INT_RAW_M (SPI_MEM_C_MST_ST_END_INT_RAW_V << SPI_MEM_C_MST_ST_END_INT_RAW_S) #define SPI_MEM_C_MST_ST_END_INT_RAW_V 0x00000001U #define SPI_MEM_C_MST_ST_END_INT_RAW_S 4 /** SPI_MEM_C_ECC_ERR_INT_RAW : HRO; bitpos: [5]; default: 0; - * The raw bit for SPI_MEM_C_ECC_ERR_INT interrupt. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN is set - * and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_C_ECC_ERR_INT_NUM. When - * SPI_MEM_C_FMEM__ECC_ERR_INT_EN is cleared and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is set, this bit is - * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and - * SPI_MEM_C_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times - * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and SPI_MEM_C_SMEM_ECC_ERR_INT_EN - * are cleared, this bit will not be triggered. + * The raw bit for SPI_MEM_C_ECC_ERR_INT interrupt. When + * SPI_MEM_C_FMEM__ECC_ERR_INT_EN is set and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is + * cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are + * equal or bigger than SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN + * is cleared and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when + * the error times of SPI0/1 ECC read external RAM are equal or bigger than + * SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and + * SPI_MEM_C_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error + * times of SPI0/1 ECC read external RAM and flash are equal or bigger than + * SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and + * SPI_MEM_C_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered. */ #define SPI_MEM_C_ECC_ERR_INT_RAW (BIT(5)) #define SPI_MEM_C_ECC_ERR_INT_RAW_M (SPI_MEM_C_ECC_ERR_INT_RAW_V << SPI_MEM_C_ECC_ERR_INT_RAW_S) #define SPI_MEM_C_ECC_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_C_ECC_ERR_INT_RAW_S 5 /** SPI_MEM_C_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for SPI_MEM_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is - * rejected. 0: Others. + * The raw bit for SPI_MEM_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access + * is rejected. 0: Others. */ #define SPI_MEM_C_PMS_REJECT_INT_RAW (BIT(6)) #define SPI_MEM_C_PMS_REJECT_INT_RAW_M (SPI_MEM_C_PMS_REJECT_INT_RAW_V << SPI_MEM_C_PMS_REJECT_INT_RAW_S) @@ -750,8 +1249,8 @@ extern "C" { #define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_C_AXI_RADDR_ERR_INT_RAW_S 7 /** SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW : HRO; bitpos: [8]; default: 0; - * The raw bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write - * flash request is received. 0: Others. + * The raw bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI + * write flash request is received. 0: Others. */ #define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) #define SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_C_AXI_WR_FLASH_ERR_INT_RAW_S) @@ -765,6 +1264,22 @@ extern "C" { #define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_S) #define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_C_AXI_WADDR_ERR_INT_RAW_S 9 +/** SPI_MEM_C_RX_TRANS_OVF_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * The raw bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. 1: Triggered when the rx + * fifo to spi bus is overrflow. + */ +#define SPI_MEM_C_RX_TRANS_OVF_INT_RAW (BIT(26)) +#define SPI_MEM_C_RX_TRANS_OVF_INT_RAW_M (SPI_MEM_C_RX_TRANS_OVF_INT_RAW_V << SPI_MEM_C_RX_TRANS_OVF_INT_RAW_S) +#define SPI_MEM_C_RX_TRANS_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_C_RX_TRANS_OVF_INT_RAW_S 26 +/** SPI_MEM_C_TX_TRANS_UDF_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * The raw bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. 1: Triggered when the tx fifo + * to spi bus is underflow. + */ +#define SPI_MEM_C_TX_TRANS_UDF_INT_RAW (BIT(27)) +#define SPI_MEM_C_TX_TRANS_UDF_INT_RAW_M (SPI_MEM_C_TX_TRANS_UDF_INT_RAW_V << SPI_MEM_C_TX_TRANS_UDF_INT_RAW_S) +#define SPI_MEM_C_TX_TRANS_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_C_TX_TRANS_UDF_INT_RAW_S 27 /** SPI_MEM_C_INT_ST_REG register * SPI0 interrupt status register @@ -819,6 +1334,20 @@ extern "C" { #define SPI_MEM_C_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_C_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_C_AXI_WADDR_ERR_INT_ST_S) #define SPI_MEM_C_AXI_WADDR_ERR_INT_ST_V 0x00000001U #define SPI_MEM_C_AXI_WADDR_ERR_INT_ST_S 9 +/** SPI_MEM_C_RX_TRANS_OVF_INT_ST : HRO; bitpos: [26]; default: 0; + * The status bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. + */ +#define SPI_MEM_C_RX_TRANS_OVF_INT_ST (BIT(26)) +#define SPI_MEM_C_RX_TRANS_OVF_INT_ST_M (SPI_MEM_C_RX_TRANS_OVF_INT_ST_V << SPI_MEM_C_RX_TRANS_OVF_INT_ST_S) +#define SPI_MEM_C_RX_TRANS_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_C_RX_TRANS_OVF_INT_ST_S 26 +/** SPI_MEM_C_TX_TRANS_UDF_INT_ST : HRO; bitpos: [27]; default: 0; + * The status bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. + */ +#define SPI_MEM_C_TX_TRANS_UDF_INT_ST (BIT(27)) +#define SPI_MEM_C_TX_TRANS_UDF_INT_ST_M (SPI_MEM_C_TX_TRANS_UDF_INT_ST_V << SPI_MEM_C_TX_TRANS_UDF_INT_ST_S) +#define SPI_MEM_C_TX_TRANS_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_C_TX_TRANS_UDF_INT_ST_S 27 /** SPI_MEM_C_DDR_REG register * SPI0 flash DDR mode control register @@ -891,8 +1420,8 @@ extern "C" { #define SPI_MEM_C_FMEM__USR_DDR_DQS_THD_S 14 /** SPI_MEM_C_FMEM__DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ #define SPI_MEM_C_FMEM__DDR_DQS_LOOP (BIT(21)) @@ -1016,8 +1545,8 @@ extern "C" { #define SPI_MEM_C_SMEM_USR_DDR_DQS_THD_S 14 /** SPI_MEM_C_SMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ #define SPI_MEM_C_SMEM_DDR_DQS_LOOP (BIT(21)) @@ -1071,8 +1600,70 @@ extern "C" { #define SPI_MEM_C_SMEM_HYPERBUS_CA_V 0x00000001U #define SPI_MEM_C_SMEM_HYPERBUS_CA_S 30 +/** SPI_MEM_C_DLL_DLY_DB_REG register + * MSPI DLL function and debug configuration register + */ +#define SPI_MEM_C_DLL_DLY_DB_REG (DR_REG_FLASH_SPI0_BASE + 0xdc) +/** SPI_MEM_C_DLL_DB_CFG_VLD_CNT : HRO; bitpos: [7:0]; default: 0; + * Configures the end time of the debug window. + */ +#define SPI_MEM_C_DLL_DB_CFG_VLD_CNT 0x000000FFU +#define SPI_MEM_C_DLL_DB_CFG_VLD_CNT_M (SPI_MEM_C_DLL_DB_CFG_VLD_CNT_V << SPI_MEM_C_DLL_DB_CFG_VLD_CNT_S) +#define SPI_MEM_C_DLL_DB_CFG_VLD_CNT_V 0x000000FFU +#define SPI_MEM_C_DLL_DB_CFG_VLD_CNT_S 0 +/** SPI_MEM_C_DLL_DB_CNT_MODE_SEL : HRO; bitpos: [11:8]; default: 0; + * [3]:1-spi_din[15:8]. 0-spi_din[7:0]. [2]:1-only shift wptr or rptr. 0-both shift + * wptr and rptr. [1]:1-wprt[3:0] and rptr[3:0]. 0-rptr[3:0] and wprt[3:0]. + * [0]:1-neg_ptr[3:0]. 0-pos_prt[3:0]. + */ +#define SPI_MEM_C_DLL_DB_CNT_MODE_SEL 0x0000000FU +#define SPI_MEM_C_DLL_DB_CNT_MODE_SEL_M (SPI_MEM_C_DLL_DB_CNT_MODE_SEL_V << SPI_MEM_C_DLL_DB_CNT_MODE_SEL_S) +#define SPI_MEM_C_DLL_DB_CNT_MODE_SEL_V 0x0000000FU +#define SPI_MEM_C_DLL_DB_CNT_MODE_SEL_S 8 +/** SPI_MEM_C_DLL_DB_CNT_CLR : HRO; bitpos: [12]; default: 0; + * Configures the start time of the debug window. 1: Clear db_vld_cnt to 0 and Get + * ready for debug. 0: No debug. + */ +#define SPI_MEM_C_DLL_DB_CNT_CLR (BIT(12)) +#define SPI_MEM_C_DLL_DB_CNT_CLR_M (SPI_MEM_C_DLL_DB_CNT_CLR_V << SPI_MEM_C_DLL_DB_CNT_CLR_S) +#define SPI_MEM_C_DLL_DB_CNT_CLR_V 0x00000001U +#define SPI_MEM_C_DLL_DB_CNT_CLR_S 12 +/** SPI_MEM_C_DLL_DIN_DLY_SEL : HRO; bitpos: [13]; default: 0; + * Configures the din channel. 1: Use delayed data. 0: Do not use delayed data. + */ +#define SPI_MEM_C_DLL_DIN_DLY_SEL (BIT(13)) +#define SPI_MEM_C_DLL_DIN_DLY_SEL_M (SPI_MEM_C_DLL_DIN_DLY_SEL_V << SPI_MEM_C_DLL_DIN_DLY_SEL_S) +#define SPI_MEM_C_DLL_DIN_DLY_SEL_V 0x00000001U +#define SPI_MEM_C_DLL_DIN_DLY_SEL_S 13 + +/** SPI_MEM_C_DLL_DB_ST0_REG register + * MSPI DLL debug status0 register + */ +#define SPI_MEM_C_DLL_DB_ST0_REG (DR_REG_FLASH_SPI0_BASE + 0xe0) +/** SPI_MEM_C_DB_FIFO_CNT_H : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[63:32] + */ +#define SPI_MEM_C_DB_FIFO_CNT_H 0xFFFFFFFFU +#define SPI_MEM_C_DB_FIFO_CNT_H_M (SPI_MEM_C_DB_FIFO_CNT_H_V << SPI_MEM_C_DB_FIFO_CNT_H_S) +#define SPI_MEM_C_DB_FIFO_CNT_H_V 0xFFFFFFFFU +#define SPI_MEM_C_DB_FIFO_CNT_H_S 0 + +/** SPI_MEM_C_DLL_DB_ST1_REG register + * MSPI DLL debug status1 register + */ +#define SPI_MEM_C_DLL_DB_ST1_REG (DR_REG_FLASH_SPI0_BASE + 0xe4) +/** SPI_MEM_C_DB_FIFO_CNT_L : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[31:0] + */ +#define SPI_MEM_C_DB_FIFO_CNT_L 0xFFFFFFFFU +#define SPI_MEM_C_DB_FIFO_CNT_L_M (SPI_MEM_C_DB_FIFO_CNT_L_V << SPI_MEM_C_DB_FIFO_CNT_L_S) +#define SPI_MEM_C_DB_FIFO_CNT_L_V 0xFFFFFFFFU +#define SPI_MEM_C_DB_FIFO_CNT_L_S 0 + /** SPI_MEM_C_FMEM__PMS0_ATTR_REG register - * MSPI flash PMS section 0 attribute register + * SPI1 flash PMS section 0 attribute register */ #define SPI_MEM_C_FMEM__PMS0_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x100) /** SPI_MEM_C_FMEM__PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1098,9 +1689,32 @@ extern "C" { #define SPI_MEM_C_FMEM__PMS0_ECC_M (SPI_MEM_C_FMEM__PMS0_ECC_V << SPI_MEM_C_FMEM__PMS0_ECC_S) #define SPI_MEM_C_FMEM__PMS0_ECC_V 0x00000001U #define SPI_MEM_C_FMEM__PMS0_ECC_S 2 +/** SPI_MEM_C_FMEM__PMS0_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_RD_ATTR_M (SPI_MEM_C_FMEM__PMS0_NONSECURE_RD_ATTR_V << SPI_MEM_C_FMEM__PMS0_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_FMEM__PMS0_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_WR_ATTR_M (SPI_MEM_C_FMEM__PMS0_NONSECURE_WR_ATTR_V << SPI_MEM_C_FMEM__PMS0_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_FMEM__PMS0_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 0 is configured by registers SPI_MEM_C_FMEM__PMS0_ADDR_REG + * and SPI_MEM_C_FMEM__PMS0_SIZE_REG. + */ +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_ECC_M (SPI_MEM_C_FMEM__PMS0_NONSECURE_ECC_V << SPI_MEM_C_FMEM__PMS0_NONSECURE_ECC_S) +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS0_NONSECURE_ECC_S 5 /** SPI_MEM_C_FMEM__PMS1_ATTR_REG register - * MSPI flash PMS section 1 attribute register + * SPI1 flash PMS section 1 attribute register */ #define SPI_MEM_C_FMEM__PMS1_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x104) /** SPI_MEM_C_FMEM__PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1126,9 +1740,32 @@ extern "C" { #define SPI_MEM_C_FMEM__PMS1_ECC_M (SPI_MEM_C_FMEM__PMS1_ECC_V << SPI_MEM_C_FMEM__PMS1_ECC_S) #define SPI_MEM_C_FMEM__PMS1_ECC_V 0x00000001U #define SPI_MEM_C_FMEM__PMS1_ECC_S 2 +/** SPI_MEM_C_FMEM__PMS1_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_RD_ATTR_M (SPI_MEM_C_FMEM__PMS1_NONSECURE_RD_ATTR_V << SPI_MEM_C_FMEM__PMS1_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_FMEM__PMS1_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_WR_ATTR_M (SPI_MEM_C_FMEM__PMS1_NONSECURE_WR_ATTR_V << SPI_MEM_C_FMEM__PMS1_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_FMEM__PMS1_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 1 is configured by registers SPI_MEM_C_FMEM__PMS1_ADDR_REG + * and SPI_MEM_C_FMEM__PMS1_SIZE_REG. + */ +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_ECC_M (SPI_MEM_C_FMEM__PMS1_NONSECURE_ECC_V << SPI_MEM_C_FMEM__PMS1_NONSECURE_ECC_S) +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS1_NONSECURE_ECC_S 5 /** SPI_MEM_C_FMEM__PMS2_ATTR_REG register - * MSPI flash PMS section 2 attribute register + * SPI1 flash PMS section 2 attribute register */ #define SPI_MEM_C_FMEM__PMS2_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x108) /** SPI_MEM_C_FMEM__PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1154,9 +1791,32 @@ extern "C" { #define SPI_MEM_C_FMEM__PMS2_ECC_M (SPI_MEM_C_FMEM__PMS2_ECC_V << SPI_MEM_C_FMEM__PMS2_ECC_S) #define SPI_MEM_C_FMEM__PMS2_ECC_V 0x00000001U #define SPI_MEM_C_FMEM__PMS2_ECC_S 2 +/** SPI_MEM_C_FMEM__PMS2_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_RD_ATTR_M (SPI_MEM_C_FMEM__PMS2_NONSECURE_RD_ATTR_V << SPI_MEM_C_FMEM__PMS2_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_FMEM__PMS2_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_WR_ATTR_M (SPI_MEM_C_FMEM__PMS2_NONSECURE_WR_ATTR_V << SPI_MEM_C_FMEM__PMS2_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_FMEM__PMS2_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 2 is configured by registers SPI_MEM_C_FMEM__PMS2_ADDR_REG + * and SPI_MEM_C_FMEM__PMS2_SIZE_REG. + */ +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_ECC_M (SPI_MEM_C_FMEM__PMS2_NONSECURE_ECC_V << SPI_MEM_C_FMEM__PMS2_NONSECURE_ECC_S) +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS2_NONSECURE_ECC_S 5 /** SPI_MEM_C_FMEM__PMS3_ATTR_REG register - * MSPI flash PMS section 3 attribute register + * SPI1 flash PMS section 3 attribute register */ #define SPI_MEM_C_FMEM__PMS3_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x10c) /** SPI_MEM_C_FMEM__PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1182,6 +1842,29 @@ extern "C" { #define SPI_MEM_C_FMEM__PMS3_ECC_M (SPI_MEM_C_FMEM__PMS3_ECC_V << SPI_MEM_C_FMEM__PMS3_ECC_S) #define SPI_MEM_C_FMEM__PMS3_ECC_V 0x00000001U #define SPI_MEM_C_FMEM__PMS3_ECC_S 2 +/** SPI_MEM_C_FMEM__PMS3_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_RD_ATTR_M (SPI_MEM_C_FMEM__PMS3_NONSECURE_RD_ATTR_V << SPI_MEM_C_FMEM__PMS3_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_FMEM__PMS3_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_WR_ATTR_M (SPI_MEM_C_FMEM__PMS3_NONSECURE_WR_ATTR_V << SPI_MEM_C_FMEM__PMS3_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_FMEM__PMS3_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 3 is configured by registers SPI_MEM_C_FMEM__PMS3_ADDR_REG + * and SPI_MEM_C_FMEM__PMS3_SIZE_REG. + */ +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_ECC_M (SPI_MEM_C_FMEM__PMS3_NONSECURE_ECC_V << SPI_MEM_C_FMEM__PMS3_NONSECURE_ECC_S) +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_FMEM__PMS3_NONSECURE_ECC_S 5 /** SPI_MEM_C_FMEM__PMS0_ADDR_REG register * SPI1 flash PMS section 0 start address register @@ -1284,7 +1967,7 @@ extern "C" { #define SPI_MEM_C_FMEM__PMS3_SIZE_S 0 /** SPI_MEM_C_SMEM_PMS0_ATTR_REG register - * SPI1 flash PMS section 0 start address register + * SPI1 external RAM PMS section 0 attribute register */ #define SPI_MEM_C_SMEM_PMS0_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x130) /** SPI_MEM_C_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1303,16 +1986,39 @@ extern "C" { #define SPI_MEM_C_SMEM_PMS0_WR_ATTR_S 1 /** SPI_MEM_C_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 0 is configured by registers SPI_MEM_C_SMEM_PMS0_ADDR_REG and - * SPI_MEM_C_SMEM_PMS0_SIZE_REG. + * external RAM PMS section 0 is configured by registers SPI_MEM_C_SMEM_PMS0_ADDR_REG + * and SPI_MEM_C_SMEM_PMS0_SIZE_REG. */ #define SPI_MEM_C_SMEM_PMS0_ECC (BIT(2)) #define SPI_MEM_C_SMEM_PMS0_ECC_M (SPI_MEM_C_SMEM_PMS0_ECC_V << SPI_MEM_C_SMEM_PMS0_ECC_S) #define SPI_MEM_C_SMEM_PMS0_ECC_V 0x00000001U #define SPI_MEM_C_SMEM_PMS0_ECC_S 2 +/** SPI_MEM_C_SMEM_PMS0_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_RD_ATTR_M (SPI_MEM_C_SMEM_PMS0_NONSECURE_RD_ATTR_V << SPI_MEM_C_SMEM_PMS0_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_SMEM_PMS0_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_WR_ATTR_M (SPI_MEM_C_SMEM_PMS0_NONSECURE_WR_ATTR_V << SPI_MEM_C_SMEM_PMS0_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_SMEM_PMS0_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 0 is configured by registers + * SPI_MEM_C_SMEM_PMS0_ADDR_REG and SPI_MEM_C_SMEM_PMS0_SIZE_REG. + */ +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_ECC_M (SPI_MEM_C_SMEM_PMS0_NONSECURE_ECC_V << SPI_MEM_C_SMEM_PMS0_NONSECURE_ECC_S) +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS0_NONSECURE_ECC_S 5 /** SPI_MEM_C_SMEM_PMS1_ATTR_REG register - * SPI1 flash PMS section 1 start address register + * SPI1 external RAM PMS section 1 attribute register */ #define SPI_MEM_C_SMEM_PMS1_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x134) /** SPI_MEM_C_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1331,16 +2037,39 @@ extern "C" { #define SPI_MEM_C_SMEM_PMS1_WR_ATTR_S 1 /** SPI_MEM_C_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 1 is configured by registers SPI_MEM_C_SMEM_PMS1_ADDR_REG and - * SPI_MEM_C_SMEM_PMS1_SIZE_REG. + * external RAM PMS section 1 is configured by registers SPI_MEM_C_SMEM_PMS1_ADDR_REG + * and SPI_MEM_C_SMEM_PMS1_SIZE_REG. */ #define SPI_MEM_C_SMEM_PMS1_ECC (BIT(2)) #define SPI_MEM_C_SMEM_PMS1_ECC_M (SPI_MEM_C_SMEM_PMS1_ECC_V << SPI_MEM_C_SMEM_PMS1_ECC_S) #define SPI_MEM_C_SMEM_PMS1_ECC_V 0x00000001U #define SPI_MEM_C_SMEM_PMS1_ECC_S 2 +/** SPI_MEM_C_SMEM_PMS1_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_RD_ATTR_M (SPI_MEM_C_SMEM_PMS1_NONSECURE_RD_ATTR_V << SPI_MEM_C_SMEM_PMS1_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_SMEM_PMS1_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_WR_ATTR_M (SPI_MEM_C_SMEM_PMS1_NONSECURE_WR_ATTR_V << SPI_MEM_C_SMEM_PMS1_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_SMEM_PMS1_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 1 is configured by registers + * SPI_MEM_C_SMEM_PMS1_ADDR_REG and SPI_MEM_C_SMEM_PMS1_SIZE_REG. + */ +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_ECC_M (SPI_MEM_C_SMEM_PMS1_NONSECURE_ECC_V << SPI_MEM_C_SMEM_PMS1_NONSECURE_ECC_S) +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS1_NONSECURE_ECC_S 5 /** SPI_MEM_C_SMEM_PMS2_ATTR_REG register - * SPI1 flash PMS section 2 start address register + * SPI1 external RAM PMS section 2 attribute register */ #define SPI_MEM_C_SMEM_PMS2_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x138) /** SPI_MEM_C_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1359,16 +2088,39 @@ extern "C" { #define SPI_MEM_C_SMEM_PMS2_WR_ATTR_S 1 /** SPI_MEM_C_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 2 is configured by registers SPI_MEM_C_SMEM_PMS2_ADDR_REG and - * SPI_MEM_C_SMEM_PMS2_SIZE_REG. + * external RAM PMS section 2 is configured by registers SPI_MEM_C_SMEM_PMS2_ADDR_REG + * and SPI_MEM_C_SMEM_PMS2_SIZE_REG. */ #define SPI_MEM_C_SMEM_PMS2_ECC (BIT(2)) #define SPI_MEM_C_SMEM_PMS2_ECC_M (SPI_MEM_C_SMEM_PMS2_ECC_V << SPI_MEM_C_SMEM_PMS2_ECC_S) #define SPI_MEM_C_SMEM_PMS2_ECC_V 0x00000001U #define SPI_MEM_C_SMEM_PMS2_ECC_S 2 +/** SPI_MEM_C_SMEM_PMS2_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_RD_ATTR_M (SPI_MEM_C_SMEM_PMS2_NONSECURE_RD_ATTR_V << SPI_MEM_C_SMEM_PMS2_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_SMEM_PMS2_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_WR_ATTR_M (SPI_MEM_C_SMEM_PMS2_NONSECURE_WR_ATTR_V << SPI_MEM_C_SMEM_PMS2_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_SMEM_PMS2_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 2 is configured by registers + * SPI_MEM_C_SMEM_PMS2_ADDR_REG and SPI_MEM_C_SMEM_PMS2_SIZE_REG. + */ +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_ECC_M (SPI_MEM_C_SMEM_PMS2_NONSECURE_ECC_V << SPI_MEM_C_SMEM_PMS2_NONSECURE_ECC_S) +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS2_NONSECURE_ECC_S 5 /** SPI_MEM_C_SMEM_PMS3_ATTR_REG register - * SPI1 flash PMS section 3 start address register + * SPI1 external RAM PMS section 3 attribute register */ #define SPI_MEM_C_SMEM_PMS3_ATTR_REG (DR_REG_FLASH_SPI0_BASE + 0x13c) /** SPI_MEM_C_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1387,13 +2139,36 @@ extern "C" { #define SPI_MEM_C_SMEM_PMS3_WR_ATTR_S 1 /** SPI_MEM_C_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 3 is configured by registers SPI_MEM_C_SMEM_PMS3_ADDR_REG and - * SPI_MEM_C_SMEM_PMS3_SIZE_REG. + * external RAM PMS section 3 is configured by registers SPI_MEM_C_SMEM_PMS3_ADDR_REG + * and SPI_MEM_C_SMEM_PMS3_SIZE_REG. */ #define SPI_MEM_C_SMEM_PMS3_ECC (BIT(2)) #define SPI_MEM_C_SMEM_PMS3_ECC_M (SPI_MEM_C_SMEM_PMS3_ECC_V << SPI_MEM_C_SMEM_PMS3_ECC_S) #define SPI_MEM_C_SMEM_PMS3_ECC_V 0x00000001U #define SPI_MEM_C_SMEM_PMS3_ECC_S 2 +/** SPI_MEM_C_SMEM_PMS3_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_RD_ATTR_M (SPI_MEM_C_SMEM_PMS3_NONSECURE_RD_ATTR_V << SPI_MEM_C_SMEM_PMS3_NONSECURE_RD_ATTR_S) +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_C_SMEM_PMS3_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_WR_ATTR_M (SPI_MEM_C_SMEM_PMS3_NONSECURE_WR_ATTR_V << SPI_MEM_C_SMEM_PMS3_NONSECURE_WR_ATTR_S) +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_C_SMEM_PMS3_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 3 is configured by registers + * SPI_MEM_C_SMEM_PMS3_ADDR_REG and SPI_MEM_C_SMEM_PMS3_SIZE_REG. + */ +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_ECC_M (SPI_MEM_C_SMEM_PMS3_NONSECURE_ECC_V << SPI_MEM_C_SMEM_PMS3_NONSECURE_ECC_S) +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_C_SMEM_PMS3_NONSECURE_ECC_S 5 /** SPI_MEM_C_SMEM_PMS0_ADDR_REG register * SPI1 external RAM PMS section 0 start address register @@ -1560,7 +2335,8 @@ extern "C" { #define SPI_MEM_C_ECC_ERR_CNT_V 0x0000003FU #define SPI_MEM_C_ECC_ERR_CNT_S 5 /** SPI_MEM_C_FMEM__ECC_ERR_INT_NUM : HRO; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_C_ECC_ERR_INT interrupt. + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_C_ECC_ERR_INT + * interrupt. */ #define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM 0x0000003FU #define SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_M (SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_V << SPI_MEM_C_FMEM__ECC_ERR_INT_NUM_S) @@ -2447,8 +3223,8 @@ extern "C" { #define SPI_MEM_C_SMEM_CS_HOLD_TIME_V 0x0000001FU #define SPI_MEM_C_SMEM_CS_HOLD_TIME_S 7 /** SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME : HRO; bitpos: [14:12]; default: 3; - * SPI_MEM_C_SMEM_CS_HOLD_TIME + SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold - * cycles in ECC mode when accessed external RAM. + * SPI_MEM_C_SMEM_CS_HOLD_TIME + SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 + * CS hold cycles in ECC mode when accessed external RAM. */ #define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME 0x00000007U #define SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_M (SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_V << SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME_S) @@ -2472,8 +3248,8 @@ extern "C" { #define SPI_MEM_C_SMEM_ECC_16TO18_BYTE_EN_S 16 /** SPI_MEM_C_SMEM_CS_HOLD_DELAY : HRO; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_MEM_C_SMEM_CS_HOLD_DELAY[5:0] + 1) - * MSPI core clock cycles. + * transfer when accesses to external RAM. tSHSL is (SPI_MEM_C_SMEM_CS_HOLD_DELAY[5:0] + * + 1) MSPI core clock cycles. */ #define SPI_MEM_C_SMEM_CS_HOLD_DELAY 0x0000003FU #define SPI_MEM_C_SMEM_CS_HOLD_DELAY_M (SPI_MEM_C_SMEM_CS_HOLD_DELAY_V << SPI_MEM_C_SMEM_CS_HOLD_DELAY_S) @@ -2493,13 +3269,13 @@ extern "C" { * SPI0 clock gate register */ #define SPI_MEM_C_CLOCK_GATE_REG (DR_REG_FLASH_SPI0_BASE + 0x200) -/** SPI_MEM_C_CLK_EN : R/W; bitpos: [0]; default: 1; +/** SPI_MEM_C_CLK : R/W; bitpos: [0]; default: 1; * Register clock gate enable signal. 1: Enable. 0: Disable. */ -#define SPI_MEM_C_CLK_EN (BIT(0)) -#define SPI_MEM_C_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) -#define SPI_MEM_C_CLK_EN_V 0x00000001U -#define SPI_MEM_C_CLK_EN_S 0 +#define SPI_MEM_C_CLK (BIT(0)) +#define SPI_MEM_C_CLK_M (SPI_MEM_C_CLK_V << SPI_MEM_C_CLK_S) +#define SPI_MEM_C_CLK_V 0x00000001U +#define SPI_MEM_C_CLK_S 0 /** SPI_MEM_C_XTS_PLAIN_BASE_REG register * The base address of the memory that stores plaintext in Manual Encryption @@ -2510,7 +3286,7 @@ extern "C" { * Please do not use this field. */ #define SPI_MEM_C_XTS_PLAIN 0xFFFFFFFFU -#define SPI_MEM_C_XTS_PLAIN_M (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S) +#define SPI_MEM_C_XTS_PLAIN_M (SPI_MEM_C_XTS_PLAIN_V << SPI_MEM_C_XTS_PLAIN_S) #define SPI_MEM_C_XTS_PLAIN_V 0xFFFFFFFFU #define SPI_MEM_C_XTS_PLAIN_S 0 @@ -2524,7 +3300,7 @@ extern "C" { * 32-bytes, 2: 64-bytes, 3:reserved. */ #define SPI_MEM_C_XTS_LINESIZE 0x00000003U -#define SPI_MEM_C_XTS_LINESIZE_M (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S) +#define SPI_MEM_C_XTS_LINESIZE_M (SPI_MEM_C_XTS_LINESIZE_V << SPI_MEM_C_XTS_LINESIZE_S) #define SPI_MEM_C_XTS_LINESIZE_V 0x00000003U #define SPI_MEM_C_XTS_LINESIZE_S 0 @@ -2537,7 +3313,7 @@ extern "C" { * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. */ #define SPI_MEM_C_XTS_DESTINATION (BIT(0)) -#define SPI_MEM_C_XTS_DESTINATION_M (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S) +#define SPI_MEM_C_XTS_DESTINATION_M (SPI_MEM_C_XTS_DESTINATION_V << SPI_MEM_C_XTS_DESTINATION_S) #define SPI_MEM_C_XTS_DESTINATION_V 0x00000001U #define SPI_MEM_C_XTS_DESTINATION_S 0 @@ -2545,21 +3321,21 @@ extern "C" { * Manual Encryption physical address register */ #define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_REG (DR_REG_FLASH_SPI0_BASE + 0x348) -/** SPI_MEM_C_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0; +/** SPI_MEM_C_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0; * This bits stores the physical-address parameter which will be used in manual * encryption calculation. This value should aligned with byte number decided by * line-size parameter. */ -#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS 0x03FFFFFFU -#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_M (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S) -#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_V 0x03FFFFFFU +#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS 0x3FFFFFFFU +#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_M (SPI_MEM_C_XTS_PHYSICAL_ADDRESS_V << SPI_MEM_C_XTS_PHYSICAL_ADDRESS_S) +#define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFFFU #define SPI_MEM_C_XTS_PHYSICAL_ADDRESS_S 0 /** SPI_MEM_C_XTS_TRIGGER_REG register * Manual Encryption physical address register */ #define SPI_MEM_C_XTS_TRIGGER_REG (DR_REG_FLASH_SPI0_BASE + 0x34c) -/** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0; +/** SPI_MEM_C_XTS_TRIGGER : WT; bitpos: [0]; default: 0; * Set this bit to trigger the process of manual encryption calculation. This action * should only be asserted when manual encryption status is 0. After this action, * manual encryption status becomes 1. After calculation is done, manual encryption @@ -2580,7 +3356,7 @@ extern "C" { * status will become 3. */ #define SPI_MEM_C_XTS_RELEASE (BIT(0)) -#define SPI_MEM_C_XTS_RELEASE_M (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S) +#define SPI_MEM_C_XTS_RELEASE_M (SPI_MEM_C_XTS_RELEASE_V << SPI_MEM_C_XTS_RELEASE_S) #define SPI_MEM_C_XTS_RELEASE_V 0x00000001U #define SPI_MEM_C_XTS_RELEASE_S 0 @@ -2594,7 +3370,7 @@ extern "C" { * become 0. */ #define SPI_MEM_C_XTS_DESTROY (BIT(0)) -#define SPI_MEM_C_XTS_DESTROY_M (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S) +#define SPI_MEM_C_XTS_DESTROY_M (SPI_MEM_C_XTS_DESTROY_V << SPI_MEM_C_XTS_DESTROY_S) #define SPI_MEM_C_XTS_DESTROY_V 0x00000001U #define SPI_MEM_C_XTS_DESTROY_S 0 @@ -2608,7 +3384,7 @@ extern "C" { * invisible to mspi, 3: the encrypted result is visible to mspi. */ #define SPI_MEM_C_XTS_STATE 0x00000003U -#define SPI_MEM_C_XTS_STATE_M (SPI_XTS_STATE_V << SPI_XTS_STATE_S) +#define SPI_MEM_C_XTS_STATE_M (SPI_MEM_C_XTS_STATE_V << SPI_MEM_C_XTS_STATE_S) #define SPI_MEM_C_XTS_STATE_V 0x00000003U #define SPI_MEM_C_XTS_STATE_S 0 @@ -2616,11 +3392,11 @@ extern "C" { * Manual Encryption version register */ #define SPI_MEM_C_XTS_DATE_REG (DR_REG_FLASH_SPI0_BASE + 0x35c) -/** SPI_MEM_C_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176; +/** SPI_MEM_C_XTS_DATE : R/W; bitpos: [29:0]; default: 539035911; * This bits stores the last modified-time of manual encryption feature. */ #define SPI_MEM_C_XTS_DATE 0x3FFFFFFFU -#define SPI_MEM_C_XTS_DATE_M (SPI_XTS_DATE_V << SPI_XTS_DATE_S) +#define SPI_MEM_C_XTS_DATE_M (SPI_MEM_C_XTS_DATE_V << SPI_MEM_C_XTS_DATE_S) #define SPI_MEM_C_XTS_DATE_V 0x3FFFFFFFU #define SPI_MEM_C_XTS_DATE_S 0 @@ -2632,7 +3408,7 @@ extern "C" { * MSPI-MMU item content */ #define SPI_MEM_C_MMU_ITEM_CONTENT 0xFFFFFFFFU -#define SPI_MEM_C_MMU_ITEM_CONTENT_M (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S) +#define SPI_MEM_C_MMU_ITEM_CONTENT_M (SPI_MEM_C_MMU_ITEM_CONTENT_V << SPI_MEM_C_MMU_ITEM_CONTENT_S) #define SPI_MEM_C_MMU_ITEM_CONTENT_V 0xFFFFFFFFU #define SPI_MEM_C_MMU_ITEM_CONTENT_S 0 @@ -2644,7 +3420,7 @@ extern "C" { * MSPI-MMU item index */ #define SPI_MEM_C_MMU_ITEM_INDEX 0xFFFFFFFFU -#define SPI_MEM_C_MMU_ITEM_INDEX_M (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S) +#define SPI_MEM_C_MMU_ITEM_INDEX_M (SPI_MEM_C_MMU_ITEM_INDEX_V << SPI_MEM_C_MMU_ITEM_INDEX_S) #define SPI_MEM_C_MMU_ITEM_INDEX_V 0xFFFFFFFFU #define SPI_MEM_C_MMU_ITEM_INDEX_S 0 @@ -2656,14 +3432,14 @@ extern "C" { * Set this bit to enable mmu-memory clock force on */ #define SPI_MEM_C_MMU_MEM_FORCE_ON (BIT(0)) -#define SPI_MEM_C_MMU_MEM_FORCE_ON_M (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S) +#define SPI_MEM_C_MMU_MEM_FORCE_ON_M (SPI_MEM_C_MMU_MEM_FORCE_ON_V << SPI_MEM_C_MMU_MEM_FORCE_ON_S) #define SPI_MEM_C_MMU_MEM_FORCE_ON_V 0x00000001U #define SPI_MEM_C_MMU_MEM_FORCE_ON_S 0 /** SPI_MEM_C_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; * Set this bit to force mmu-memory powerdown */ #define SPI_MEM_C_MMU_MEM_FORCE_PD (BIT(1)) -#define SPI_MEM_C_MMU_MEM_FORCE_PD_M (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S) +#define SPI_MEM_C_MMU_MEM_FORCE_PD_M (SPI_MEM_C_MMU_MEM_FORCE_PD_V << SPI_MEM_C_MMU_MEM_FORCE_PD_S) #define SPI_MEM_C_MMU_MEM_FORCE_PD_V 0x00000001U #define SPI_MEM_C_MMU_MEM_FORCE_PD_S 1 /** SPI_MEM_C_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; @@ -2671,14 +3447,14 @@ extern "C" { * controlled by rtc. */ #define SPI_MEM_C_MMU_MEM_FORCE_PU (BIT(2)) -#define SPI_MEM_C_MMU_MEM_FORCE_PU_M (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S) +#define SPI_MEM_C_MMU_MEM_FORCE_PU_M (SPI_MEM_C_MMU_MEM_FORCE_PU_V << SPI_MEM_C_MMU_MEM_FORCE_PU_S) #define SPI_MEM_C_MMU_MEM_FORCE_PU_V 0x00000001U #define SPI_MEM_C_MMU_MEM_FORCE_PU_S 2 /** SPI_MEM_C_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 */ #define SPI_MEM_C_MMU_PAGE_SIZE 0x00000003U -#define SPI_MEM_C_MMU_PAGE_SIZE_M (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S) +#define SPI_MEM_C_MMU_PAGE_SIZE_M (SPI_MEM_C_MMU_PAGE_SIZE_V << SPI_MEM_C_MMU_PAGE_SIZE_S) #define SPI_MEM_C_MMU_PAGE_SIZE_V 0x00000003U #define SPI_MEM_C_MMU_PAGE_SIZE_S 3 /** SPI_MEM_C_AUX_CTRL : HRO; bitpos: [29:16]; default: 4896; @@ -2688,6 +3464,22 @@ extern "C" { #define SPI_MEM_C_AUX_CTRL_M (SPI_MEM_C_AUX_CTRL_V << SPI_MEM_C_AUX_CTRL_S) #define SPI_MEM_C_AUX_CTRL_V 0x00003FFFU #define SPI_MEM_C_AUX_CTRL_S 16 +/** SPI_MEM_C_RDN_ENA : HRO; bitpos: [30]; default: 0; + * ECO register enable bit + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_RDN_ENA (BIT(30)) +#define SPI_MEM_C_RDN_ENA_M (SPI_MEM_C_RDN_ENA_V << SPI_MEM_C_RDN_ENA_S) +#define SPI_MEM_C_RDN_ENA_V 0x00000001U +#define SPI_MEM_C_RDN_ENA_S 30 +/** SPI_MEM_C_RDN_RESULT : RO; bitpos: [31]; default: 0; + * MSPI module clock domain and AXI clock domain ECO register result register + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_RDN_RESULT (BIT(31)) +#define SPI_MEM_C_RDN_RESULT_M (SPI_MEM_C_RDN_RESULT_V << SPI_MEM_C_RDN_RESULT_S) +#define SPI_MEM_C_RDN_RESULT_V 0x00000001U +#define SPI_MEM_C_RDN_RESULT_S 31 /** SPI_MEM_C_DPA_CTRL_REG register * SPI memory cryption DPA register @@ -2699,32 +3491,98 @@ extern "C" { * performance of cryption will decrease together with this number increasing) */ #define SPI_MEM_C_CRYPT_SECURITY_LEVEL 0x00000007U -#define SPI_MEM_C_CRYPT_SECURITY_LEVEL_M (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S) +#define SPI_MEM_C_CRYPT_SECURITY_LEVEL_M (SPI_MEM_C_CRYPT_SECURITY_LEVEL_V << SPI_MEM_C_CRYPT_SECURITY_LEVEL_S) #define SPI_MEM_C_CRYPT_SECURITY_LEVEL_V 0x00000007U #define SPI_MEM_C_CRYPT_SECURITY_LEVEL_S 0 /** SPI_MEM_C_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1; - * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * Only available when SPI_MEM_C_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that * using key 1. */ #define SPI_MEM_C_CRYPT_CALC_D_DPA_EN (BIT(3)) -#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_M (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S) +#define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_M (SPI_MEM_C_CRYPT_CALC_D_DPA_EN_V << SPI_MEM_C_CRYPT_CALC_D_DPA_EN_S) #define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_V 0x00000001U #define SPI_MEM_C_CRYPT_CALC_D_DPA_EN_S 3 /** SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0; - * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and - * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + * 1: MSPI XTS DPA clock gate is controlled by SPI_MEM_C_CRYPT_CALC_D_DPA_EN and + * SPI_MEM_C_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. */ #define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER (BIT(4)) -#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_M (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S) +#define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_M (SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_V << SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_S) #define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_V 0x00000001U #define SPI_MEM_C_CRYPT_DPA_SELECT_REGISTER_S 4 +/** SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG register + * SPI memory cryption PSEUDO register + */ +#define SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG (DR_REG_FLASH_SPI0_BASE + 0x38c) +/** SPI_MEM_C_MODE_PSEUDO : R/W; bitpos: [1:0]; default: 0; + * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo + * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. + * 2'b11: crypto with pseudo. + */ +#define SPI_MEM_C_MODE_PSEUDO 0x00000003U +#define SPI_MEM_C_MODE_PSEUDO_M (SPI_MEM_C_MODE_PSEUDO_V << SPI_MEM_C_MODE_PSEUDO_S) +#define SPI_MEM_C_MODE_PSEUDO_V 0x00000003U +#define SPI_MEM_C_MODE_PSEUDO_S 0 +/** SPI_MEM_C_PSEUDO_RNG_CNT : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be performed. + */ +#define SPI_MEM_C_PSEUDO_RNG_CNT 0x00000007U +#define SPI_MEM_C_PSEUDO_RNG_CNT_M (SPI_MEM_C_PSEUDO_RNG_CNT_V << SPI_MEM_C_PSEUDO_RNG_CNT_S) +#define SPI_MEM_C_PSEUDO_RNG_CNT_V 0x00000007U +#define SPI_MEM_C_PSEUDO_RNG_CNT_S 2 +/** SPI_MEM_C_PSEUDO_BASE : R/W; bitpos: [8:5]; default: 2; + * xts aes peseudo function base round that must be performed. + */ +#define SPI_MEM_C_PSEUDO_BASE 0x0000000FU +#define SPI_MEM_C_PSEUDO_BASE_M (SPI_MEM_C_PSEUDO_BASE_V << SPI_MEM_C_PSEUDO_BASE_S) +#define SPI_MEM_C_PSEUDO_BASE_V 0x0000000FU +#define SPI_MEM_C_PSEUDO_BASE_S 5 +/** SPI_MEM_C_PSEUDO_INC : R/W; bitpos: [10:9]; default: 2; + * xts aes peseudo function increment round that will be performed randomly between 0 & + * 2**(inc+1). + */ +#define SPI_MEM_C_PSEUDO_INC 0x00000003U +#define SPI_MEM_C_PSEUDO_INC_M (SPI_MEM_C_PSEUDO_INC_V << SPI_MEM_C_PSEUDO_INC_S) +#define SPI_MEM_C_PSEUDO_INC_V 0x00000003U +#define SPI_MEM_C_PSEUDO_INC_S 9 + +/** SPI_MEM_C_REGISTERRND_ECO_HIGH_REG register + * MSPI ECO high register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_C_REGISTERRND_ECO_HIGH_REG (DR_REG_FLASH_SPI0_BASE + 0x3f0) +/** SPI_MEM_C_REGISTERRND_ECO_HIGH : RO; bitpos: [31:0]; default: 892; + * ECO high register + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_REGISTERRND_ECO_HIGH 0xFFFFFFFFU +#define SPI_MEM_C_REGISTERRND_ECO_HIGH_M (SPI_MEM_C_REGISTERRND_ECO_HIGH_V << SPI_MEM_C_REGISTERRND_ECO_HIGH_S) +#define SPI_MEM_C_REGISTERRND_ECO_HIGH_V 0xFFFFFFFFU +#define SPI_MEM_C_REGISTERRND_ECO_HIGH_S 0 + +/** SPI_MEM_C_REGISTERRND_ECO_LOW_REG register + * MSPI ECO low register + * This register is only for internal debugging purposes. Do not use it in + * applications. + */ +#define SPI_MEM_C_REGISTERRND_ECO_LOW_REG (DR_REG_FLASH_SPI0_BASE + 0x3f4) +/** SPI_MEM_C_REGISTERRND_ECO_LOW : RO; bitpos: [31:0]; default: 892; + * ECO low register + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_C_REGISTERRND_ECO_LOW 0xFFFFFFFFU +#define SPI_MEM_C_REGISTERRND_ECO_LOW_M (SPI_MEM_C_REGISTERRND_ECO_LOW_V << SPI_MEM_C_REGISTERRND_ECO_LOW_S) +#define SPI_MEM_C_REGISTERRND_ECO_LOW_V 0xFFFFFFFFU +#define SPI_MEM_C_REGISTERRND_ECO_LOW_S 0 + /** SPI_MEM_C_DATE_REG register * SPI0 version control register */ #define SPI_MEM_C_DATE_REG (DR_REG_FLASH_SPI0_BASE + 0x3fc) -/** SPI_MEM_C_DATE : R/W; bitpos: [27:0]; default: 36712560; +/** SPI_MEM_C_DATE : R/W; bitpos: [27:0]; default: 38805888; * SPI0 register version. */ #define SPI_MEM_C_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_struct.h index 9ddcb3f6ce59..e4c093e73a7a 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_c_struct.h @@ -30,9 +30,9 @@ typedef union { uint32_t slv_st:4; uint32_t reserved_8:10; /** usr : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when spi_mem_c_C_AXI_REQ_EN is cleared. An operation - * will be triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. + * SPI0 USR_CMD start bit, only used when SPI_MEM_C_AXI_REQ_EN is cleared. An + * operation will be triggered when the bit is set. The bit will be cleared once the + * operation done.1: enable 0: disable. */ uint32_t usr:1; uint32_t reserved_19:13; @@ -47,8 +47,8 @@ typedef union { struct { /** axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first AXI write/read invalid error or AXI write flash error - * address. It is cleared by when spi_mem_c_C_AXI_WADDR_ERR_INT_CLR, - * spi_mem_c_C_AXI_WR_FLASH_ERR_IN_CLR or spi_mem_c_C_AXI_RADDR_ERR_IN_CLR bit is set. + * address. It is cleared by when SPI_MEM_C_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_C_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_C_AXI_RADDR_ERR_IN_CLR bit is set. */ uint32_t axi_err_addr:27; uint32_t reserved_27:5; @@ -108,8 +108,8 @@ typedef union { uint32_t fcmd_oct:1; uint32_t reserved_10:3; /** fastrd_mode : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: spi_mem_c_C_FREAD_QIO, spi_mem_c_C_FREAD_DIO, spi_mem_c_C_FREAD_QOUT - * and spi_mem_c_C_FREAD_DOUT. 1: enable 0: disable. + * This bit enable the bits: SPI_MEM_C_FREAD_QIO, SPI_MEM_C_FREAD_DIO, + * SPI_MEM_C_FREAD_QOUT and SPI_MEM_C_FREAD_DOUT. 1: enable 0: disable. */ uint32_t fastrd_mode:1; /** fread_dual : R/W; bitpos: [14]; default: 0; @@ -180,15 +180,11 @@ typedef union { * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. */ uint32_t aw_size0_1_support_en:1; - /** axi_rdata_back_fast : HRO; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ - uint32_t axi_rdata_back_fast:1; + uint32_t reserved_23:1; /** rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded - * in spi_mem_c_C_ECC_ERR_ADDR_REG. + * in SPI_MEM_C_ECC_ERR_ADDR_REG. */ uint32_t rresp_ecc_err_en:1; /** ar_splice_en : HRO; bitpos: [25]; default: 0; @@ -200,9 +196,9 @@ typedef union { */ uint32_t aw_splice_en:1; /** ram0_en : HRO; bitpos: [27]; default: 1; - * When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When spi_mem_c_C_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * When SPI_MEM_C_DUAL_RAM_EN is 0 and SPI_MEM_C_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_C_DUAL_RAM_EN is 0 and SPI_MEM_C_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_C_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be * accessed at the same time. */ uint32_t ram0_en:1; @@ -238,17 +234,17 @@ typedef union { struct { /** cs_setup_time : R/W; bitpos: [4:0]; default: 1; * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with - * spi_mem_c_C_CS_SETUP bit. + * SPI_MEM_C_CS_SETUP bit. */ uint32_t cs_setup_time:5; /** cs_hold_time : R/W; bitpos: [9:5]; default: 1; * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with - * spi_mem_c_C_CS_HOLD bit. + * SPI_MEM_C_CS_HOLD bit. */ uint32_t cs_hold_time:5; /** ecc_cs_hold_time : HRO; bitpos: [12:10]; default: 3; - * spi_mem_c_C_CS_HOLD_TIME + spi_mem_c_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC - * mode when accessed flash. + * SPI_MEM_C_CS_HOLD_TIME + SPI_MEM_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in + * ECC mode when accessed flash. */ uint32_t ecc_cs_hold_time:3; /** ecc_skip_page_corner : HRO; bitpos: [13]; default: 1; @@ -270,7 +266,7 @@ typedef union { uint32_t split_trans_en:1; /** cs_hold_delay : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to flash. tSHSL is (spi_mem_c_C_CS_HOLD_DELAY[5:0] + 1) MSPI + * transfer when accesses to flash. tSHSL is (SPI_MEM_C_CS_HOLD_DELAY[5:0] + 1) MSPI * core clock cycles. */ uint32_t cs_hold_delay:6; @@ -287,7 +283,19 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:7; + uint32_t reserved_0:4; + /** dq_oe_ctrl : R/W; bitpos: [4]; default: 1; + * For SPI BUS IO, APB ctrl IO DQ OE func.1: enable 0: disable. + */ + uint32_t dq_oe_ctrl:1; + /** ck_oe_ctrl : R/W; bitpos: [5]; default: 1; + * For SPI BUS IO, APB ctrl IO CK OE func.1: enable 0: disable. + */ + uint32_t ck_oe_ctrl:1; + /** cs_oe_ctrl : R/W; bitpos: [6]; default: 1; + * For SPI BUS IO, APB ctrl IO CS OE func.1: enable 0: disable. + */ + uint32_t cs_oe_ctrl:1; /** fsub_pin : HRO; bitpos: [7]; default: 0; * For SPI0, flash is connected to SUBPINs. */ @@ -314,7 +322,83 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:30; + /** axi_req_en : R/W; bitpos: [0]; default: 0; + * For SPI0, AXI master access enable, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t axi_req_en:1; + /** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; + * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_usr_addr_4byte:1; + /** cache_flash_usr_cmd : R/W; bitpos: [2]; default: 0; + * For SPI0, cache read flash for user define command, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_flash_usr_cmd:1; + /** fdin_dual : R/W; bitpos: [3]; default: 0; + * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t fdin_dual:1; + /** fdout_dual : R/W; bitpos: [4]; default: 0; + * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t fdout_dual:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t faddr_dual:1; + /** fdin_quad : R/W; bitpos: [6]; default: 0; + * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t fdin_quad:1; + /** fdout_quad : R/W; bitpos: [7]; default: 0; + * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the + * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t fdout_quad:1; + /** faddr_quad : R/W; bitpos: [8]; default: 0; + * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t faddr_quad:1; + /** arb_wei_en : HRO; bitpos: [9]; default: 0; + * To enable SPI0 arbiter weight func while AXI read/write access SPI0 1: enable 0: + * disable. + */ + uint32_t arb_wei_en:1; + /** arb_req0_pri : HRO; bitpos: [10]; default: 0; + * To set AXI read priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ + uint32_t arb_req0_pri:1; + /** arb_req1_pri : HRO; bitpos: [11]; default: 0; + * To set AXI write priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ + uint32_t arb_req1_pri:1; + /** arb_req0_wei : HRO; bitpos: [15:12]; default: 0; + * To set AXI read priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ + uint32_t arb_req0_wei:4; + /** arb_req1_wei : HRO; bitpos: [19:16]; default: 0; + * To set AXI write priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ + uint32_t arb_req1_wei:4; + uint32_t reserved_20:10; /** same_aw_ar_addr_chk_en : HRO; bitpos: [30]; default: 1; * Set this bit to check AXI read/write the same address region. */ @@ -373,8 +457,8 @@ typedef union { uint32_t fmem_usr_ddr_dqs_thd:7; /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in spi_mem_c_C_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ uint32_t fmem_ddr_dqs_loop:1; @@ -420,16 +504,16 @@ typedef union { typedef union { struct { /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_c_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_C_CLKCNT_N. */ uint32_t clkcnt_l:8; /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_c_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_C_CLKCNT_N+1)/2-1). */ uint32_t clkcnt_h:8; /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi_mem_c_clk. So spi_mem_c_clk frequency is - * system/(spi_mem_c_clkcnt_N+1) + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(SPI_MEM_C_CLKCNT_N+1) */ uint32_t clkcnt_n:8; uint32_t reserved_24:7; @@ -442,15 +526,47 @@ typedef union { uint32_t val; } spi_mem_c_clock_reg_t; +/** Type of sram_clk register + * SPI0 external RAM clock control register + */ +typedef union { + struct { + /** sclkcnt_l : HRO; bitpos: [7:0]; default: 3; + * For SPI0 external RAM interface, it must be equal to SPI_MEM_C_SCLKCNT_N. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sclkcnt_l:8; + /** sclkcnt_h : HRO; bitpos: [15:8]; default: 1; + * For SPI0 external RAM interface, it must be floor((SPI_MEM_C_SCLKCNT_N+1)/2-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sclkcnt_h:8; + /** sclkcnt_n : HRO; bitpos: [23:16]; default: 3; + * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk + * frequency is system/(SPI_MEM_C_SCLKCNT_N+1) + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sclkcnt_n:8; + uint32_t reserved_24:7; + /** sclk_equ_sysclk : HRO; bitpos: [31]; default: 0; + * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk + * is divided from system clock. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sclk_equ_sysclk:1; + }; + uint32_t val; +} spi_mem_c_sram_clk_reg_t; + /** Type of clock_gate register * SPI0 clock gate register */ typedef union { struct { - /** clk_en : R/W; bitpos: [0]; default: 1; + /** clk : R/W; bitpos: [0]; default: 1; * Register clock gate enable signal. 1: Enable. 0: Disable. */ - uint32_t clk_en:1; + uint32_t clk:1; uint32_t reserved_1:31; }; uint32_t val; @@ -474,7 +590,7 @@ typedef union { uint32_t cs_setup:1; uint32_t reserved_8:1; /** ck_out_edge : R/W; bitpos: [9]; default: 0; - * The bit combined with spi_mem_c_C_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + * The bit combined with SPI_MEM_C_CK_IDLE_EDGE bit to control SPI clock mode 0~3. */ uint32_t ck_out_edge:1; uint32_t reserved_10:16; @@ -498,7 +614,7 @@ typedef union { typedef union { struct { /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; - * The length in spi_mem_c_clk cycles of dummy phase. The register value shall be + * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). */ uint32_t usr_dummy_cyclelen:6; @@ -533,14 +649,189 @@ typedef union { uint32_t val; } spi_mem_c_user2_reg_t; +/** Type of rd_status register + * SPI0 read control register. + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** wb_mode : R/W; bitpos: [23:16]; default: 0; + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t wb_mode:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} spi_mem_c_rd_status_reg_t; + /** Group: External RAM Control and configuration registers */ +/** Type of cache_sctrl register + * SPI0 external RAM control register + */ +typedef union { + struct { + /** cache_usr_saddr_4byte : HRO; bitpos: [0]; default: 0; + * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: + * enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_usr_saddr_4byte:1; + /** usr_sram_dio : HRO; bitpos: [1]; default: 0; + * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usr_sram_dio:1; + /** usr_sram_qio : HRO; bitpos: [2]; default: 0; + * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usr_sram_qio:1; + /** usr_wr_sram_dummy : HRO; bitpos: [3]; default: 0; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write + * operations. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usr_wr_sram_dummy:1; + /** usr_rd_sram_dummy : HRO; bitpos: [4]; default: 1; + * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read + * operations. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usr_rd_sram_dummy:1; + /** cache_sram_usr_rcmd : HRO; bitpos: [5]; default: 1; + * For SPI0, In the external RAM mode cache read external RAM for user define command. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_sram_usr_rcmd:1; + /** sram_rdummy_cyclelen : HRO; bitpos: [11:6]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sram_rdummy_cyclelen:6; + uint32_t reserved_12:2; + /** sram_addr_bitlen : HRO; bitpos: [19:14]; default: 23; + * For SPI0, In the external RAM mode, it is the length in bits of address phase. The + * register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sram_addr_bitlen:6; + /** cache_sram_usr_wcmd : HRO; bitpos: [20]; default: 1; + * For SPI0, In the external RAM mode cache write sram for user define command + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_sram_usr_wcmd:1; + /** sram_oct : HRO; bitpos: [21]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sram_oct:1; + /** sram_wdummy_cyclelen : HRO; bitpos: [27:22]; default: 1; + * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sram_wdummy_cyclelen:6; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_mem_c_cache_sctrl_reg_t; + /** Type of sram_cmd register * SPI0 external RAM mode control register */ typedef union { struct { - uint32_t reserved_0:24; + /** sclk_mode : HRO; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sclk_mode:2; + /** swb_mode : HRO; bitpos: [9:2]; default: 0; + * Mode bits in the external RAM fast read mode it is combined with + * spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t swb_mode:8; + /** sdin_dual : HRO; bitpos: [10]; default: 0; + * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdin_dual:1; + /** sdout_dual : HRO; bitpos: [11]; default: 0; + * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdout_dual:1; + /** saddr_dual : HRO; bitpos: [12]; default: 0; + * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t saddr_dual:1; + uint32_t reserved_13:1; + /** sdin_quad : HRO; bitpos: [14]; default: 0; + * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdin_quad:1; + /** sdout_quad : HRO; bitpos: [15]; default: 0; + * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit + * is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdout_quad:1; + /** saddr_quad : HRO; bitpos: [16]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The + * bit is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t saddr_quad:1; + /** scmd_quad : HRO; bitpos: [17]; default: 0; + * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is + * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t scmd_quad:1; + /** sdin_oct : HRO; bitpos: [18]; default: 0; + * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdin_oct:1; + /** sdout_oct : HRO; bitpos: [19]; default: 0; + * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdout_oct:1; + /** saddr_oct : HRO; bitpos: [20]; default: 0; + * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t saddr_oct:1; + /** scmd_oct : HRO; bitpos: [21]; default: 0; + * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t scmd_oct:1; + /** sdummy_rin : R/W; bitpos: [22]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdummy_rin:1; + /** sdummy_wout : HRO; bitpos: [23]; default: 0; + * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the + * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t sdummy_wout:1; /** smem_wdummy_dqs_always_out : HRO; bitpos: [24]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_DQS is output by the MSPI controller. @@ -566,6 +857,50 @@ typedef union { uint32_t val; } spi_mem_c_sram_cmd_reg_t; +/** Type of sram_drd_cmd register + * SPI0 external RAM DDR read command control register + */ +typedef union { + struct { + /** cache_sram_usr_rd_cmd_value : HRO; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the read command value of command phase + * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_sram_usr_rd_cmd_value:16; + uint32_t reserved_16:12; + /** cache_sram_usr_rd_cmd_bitlen : HRO; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the length in bits of command phase for + * sram. The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_sram_usr_rd_cmd_bitlen:4; + }; + uint32_t val; +} spi_mem_c_sram_drd_cmd_reg_t; + +/** Type of sram_dwr_cmd register + * SPI0 external RAM DDR write command control register + */ +typedef union { + struct { + /** cache_sram_usr_wr_cmd_value : HRO; bitpos: [15:0]; default: 0; + * For SPI0,When cache mode is enable it is the write command value of command phase + * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_sram_usr_wr_cmd_value:16; + uint32_t reserved_16:12; + /** cache_sram_usr_wr_cmd_bitlen : HRO; bitpos: [31:28]; default: 0; + * For SPI0,When cache mode is enable it is the in bits of command phase for sram. + * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cache_sram_usr_wr_cmd_bitlen:4; + }; + uint32_t val; +} spi_mem_c_sram_dwr_cmd_reg_t; + /** Type of smem_ddr register * SPI0 external RAM DDR mode control register */ @@ -611,8 +946,8 @@ typedef union { uint32_t smem_usr_ddr_dqs_thd:7; /** smem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in spi_mem_c_C_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI_MEM_C_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ uint32_t smem_ddr_dqs_loop:1; @@ -667,17 +1002,17 @@ typedef union { uint32_t smem_cs_hold:1; /** smem_cs_setup_time : HRO; bitpos: [6:2]; default: 1; * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with - * spi_mem_c_cs_setup bit. + * spi_mem_cs_setup bit. */ uint32_t smem_cs_setup_time:5; /** smem_cs_hold_time : HRO; bitpos: [11:7]; default: 1; * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are - * combined with spi_mem_c_cs_hold bit. + * combined with spi_mem_cs_hold bit. */ uint32_t smem_cs_hold_time:5; /** smem_ecc_cs_hold_time : HRO; bitpos: [14:12]; default: 3; - * SPI_MEM_C_SMEM_CS_HOLD_TIME + SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold - * cycles in ECC mode when accessed external RAM. + * SPI_MEM_C_SMEM_CS_HOLD_TIME + SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 + * CS hold cycles in ECC mode when accessed external RAM. */ uint32_t smem_ecc_cs_hold_time:3; /** smem_ecc_skip_page_corner : HRO; bitpos: [15]; default: 1; @@ -693,8 +1028,8 @@ typedef union { uint32_t reserved_17:8; /** smem_cs_hold_delay : HRO; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_MEM_C_SMEM_CS_HOLD_DELAY[5:0] + 1) - * MSPI core clock cycles. + * transfer when accesses to external RAM. tSHSL is (SPI_MEM_C_SMEM_CS_HOLD_DELAY[5:0] + * + 1) MSPI core clock cycles. */ uint32_t smem_cs_hold_delay:6; /** smem_split_trans_en : HRO; bitpos: [31]; default: 1; @@ -715,11 +1050,11 @@ typedef union { typedef union { struct { uint32_t reserved_0:7; - /** lock_delay_time : R/W; bitpos: [11:7]; default: 4; + /** lock_delay_time : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ - uint32_t lock_delay_time:5; - uint32_t reserved_12:20; + uint32_t lock_delay_time:12; + uint32_t reserved_19:13; }; uint32_t val; } spi_mem_c_fsm_reg_t; @@ -733,34 +1068,43 @@ typedef union { struct { uint32_t reserved_0:3; /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; - * The enable bit for spi_mem_c_C_SLV_ST_END_INT interrupt. + * The enable bit for SPI_MEM_C_SLV_ST_END_INT interrupt. */ uint32_t slv_st_end_int_ena:1; /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; - * The enable bit for spi_mem_c_C_MST_ST_END_INT interrupt. + * The enable bit for SPI_MEM_C_MST_ST_END_INT interrupt. */ uint32_t mst_st_end_int_ena:1; /** ecc_err_int_ena : HRO; bitpos: [5]; default: 0; - * The enable bit for spi_mem_c_C_ECC_ERR_INT interrupt. + * The enable bit for SPI_MEM_C_ECC_ERR_INT interrupt. */ uint32_t ecc_err_int_ena:1; /** pms_reject_int_ena : R/W; bitpos: [6]; default: 0; - * The enable bit for spi_mem_c_C_PMS_REJECT_INT interrupt. + * The enable bit for SPI_MEM_C_PMS_REJECT_INT interrupt. */ uint32_t pms_reject_int_ena:1; /** axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; - * The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt. */ uint32_t axi_raddr_err_int_ena:1; /** axi_wr_flash_err_int_ena : HRO; bitpos: [8]; default: 0; - * The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. + * The enable bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t axi_wr_flash_err_int_ena:1; /** axi_waddr_err_int__ena : HRO; bitpos: [9]; default: 0; - * The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt. */ uint32_t axi_waddr_err_int__ena:1; - uint32_t reserved_10:22; + uint32_t reserved_10:16; + /** rx_trans_ovf_int_ena : HRO; bitpos: [26]; default: 0; + * The enable bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. + */ + uint32_t rx_trans_ovf_int_ena:1; + /** tx_trans_udf_int_ena : HRO; bitpos: [27]; default: 0; + * The enable bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. + */ + uint32_t tx_trans_udf_int_ena:1; + uint32_t reserved_28:4; }; uint32_t val; } spi_mem_c_int_ena_reg_t; @@ -772,34 +1116,43 @@ typedef union { struct { uint32_t reserved_0:3; /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0; - * The clear bit for spi_mem_c_C_SLV_ST_END_INT interrupt. + * The clear bit for SPI_MEM_C_SLV_ST_END_INT interrupt. */ uint32_t slv_st_end_int_clr:1; /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0; - * The clear bit for spi_mem_c_C_MST_ST_END_INT interrupt. + * The clear bit for SPI_MEM_C_MST_ST_END_INT interrupt. */ uint32_t mst_st_end_int_clr:1; /** ecc_err_int_clr : HRO; bitpos: [5]; default: 0; - * The clear bit for spi_mem_c_C_ECC_ERR_INT interrupt. + * The clear bit for SPI_MEM_C_ECC_ERR_INT interrupt. */ uint32_t ecc_err_int_clr:1; /** pms_reject_int_clr : WT; bitpos: [6]; default: 0; - * The clear bit for spi_mem_c_C_PMS_REJECT_INT interrupt. + * The clear bit for SPI_MEM_C_PMS_REJECT_INT interrupt. */ uint32_t pms_reject_int_clr:1; /** axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; - * The clear bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. + * The clear bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt. */ uint32_t axi_raddr_err_int_clr:1; /** axi_wr_flash_err_int_clr : HRO; bitpos: [8]; default: 0; - * The clear bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. + * The clear bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t axi_wr_flash_err_int_clr:1; /** axi_waddr_err_int_clr : HRO; bitpos: [9]; default: 0; - * The clear bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. + * The clear bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt. */ uint32_t axi_waddr_err_int_clr:1; - uint32_t reserved_10:22; + uint32_t reserved_10:16; + /** rx_trans_ovf_int_clr : HRO; bitpos: [26]; default: 0; + * The clear bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. + */ + uint32_t rx_trans_ovf_int_clr:1; + /** tx_trans_udf_int_clr : HRO; bitpos: [27]; default: 0; + * The clear bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. + */ + uint32_t tx_trans_udf_int_clr:1; + uint32_t reserved_28:4; }; uint32_t val; } spi_mem_c_int_clr_reg_t; @@ -811,50 +1164,62 @@ typedef union { struct { uint32_t reserved_0:3; /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for spi_mem_c_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * The raw bit for SPI_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st + * is changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ uint32_t slv_st_end_int_raw:1; /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for spi_mem_c_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is - * changed from non idle state to idle state. 0: Others. + * The raw bit for SPI_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st + * is changed from non idle state to idle state. 0: Others. */ uint32_t mst_st_end_int_raw:1; /** ecc_err_int_raw : HRO; bitpos: [5]; default: 0; - * The raw bit for spi_mem_c_C_ECC_ERR_INT interrupt. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN is set - * and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than spi_mem_c_C_ECC_ERR_INT_NUM. When - * SPI_MEM_C_FMEM__ECC_ERR_INT_EN is cleared and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is set, this bit is - * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than spi_mem_c_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and - * SPI_MEM_C_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times - * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * spi_mem_c_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and SPI_MEM_C_SMEM_ECC_ERR_INT_EN - * are cleared, this bit will not be triggered. + * The raw bit for SPI_MEM_C_ECC_ERR_INT interrupt. When + * SPI_MEM_C_fmem_ECC_ERR_INT_EN is set and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is + * cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are + * equal or bigger than SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_fmem_ECC_ERR_INT_EN + * is cleared and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when + * the error times of SPI0/1 ECC read external RAM are equal or bigger than + * SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_fmem_ECC_ERR_INT_EN and + * SPI_MEM_C_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error + * times of SPI0/1 ECC read external RAM and flash are equal or bigger than + * SPI_MEM_C_ECC_ERR_INT_NUM. When SPI_MEM_C_fmem_ECC_ERR_INT_EN and + * SPI_MEM_C_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered. */ uint32_t ecc_err_int_raw:1; /** pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for spi_mem_c_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is - * rejected. 0: Others. + * The raw bit for SPI_MEM_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access + * is rejected. 0: Others. */ uint32_t pms_reject_int_raw:1; /** axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * The raw bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t axi_raddr_err_int_raw:1; /** axi_wr_flash_err_int_raw : HRO; bitpos: [8]; default: 0; - * The raw bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write - * flash request is received. 0: Others. + * The raw bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI + * write flash request is received. 0: Others. */ uint32_t axi_wr_flash_err_int_raw:1; /** axi_waddr_err_int_raw : HRO; bitpos: [9]; default: 0; - * The raw bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * The raw bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t axi_waddr_err_int_raw:1; - uint32_t reserved_10:22; + uint32_t reserved_10:16; + /** rx_trans_ovf_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * The raw bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. 1: Triggered when the rx + * fifo to spi bus is overrflow. + */ + uint32_t rx_trans_ovf_int_raw:1; + /** tx_trans_udf_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * The raw bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. 1: Triggered when the tx fifo + * to spi bus is underflow. + */ + uint32_t tx_trans_udf_int_raw:1; + uint32_t reserved_28:4; }; uint32_t val; } spi_mem_c_int_raw_reg_t; @@ -866,42 +1231,112 @@ typedef union { struct { uint32_t reserved_0:3; /** slv_st_end_int_st : RO; bitpos: [3]; default: 0; - * The status bit for spi_mem_c_C_SLV_ST_END_INT interrupt. + * The status bit for SPI_MEM_C_SLV_ST_END_INT interrupt. */ uint32_t slv_st_end_int_st:1; /** mst_st_end_int_st : RO; bitpos: [4]; default: 0; - * The status bit for spi_mem_c_C_MST_ST_END_INT interrupt. + * The status bit for SPI_MEM_C_MST_ST_END_INT interrupt. */ uint32_t mst_st_end_int_st:1; /** ecc_err_int_st : HRO; bitpos: [5]; default: 0; - * The status bit for spi_mem_c_C_ECC_ERR_INT interrupt. + * The status bit for SPI_MEM_C_ECC_ERR_INT interrupt. */ uint32_t ecc_err_int_st:1; /** pms_reject_int_st : RO; bitpos: [6]; default: 0; - * The status bit for spi_mem_c_C_PMS_REJECT_INT interrupt. + * The status bit for SPI_MEM_C_PMS_REJECT_INT interrupt. */ uint32_t pms_reject_int_st:1; /** axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; - * The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_C_AXI_RADDR_ERR_INT interrupt. */ uint32_t axi_raddr_err_int_st:1; /** axi_wr_flash_err_int_st : HRO; bitpos: [8]; default: 0; - * The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. + * The enable bit for SPI_MEM_C_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t axi_wr_flash_err_int_st:1; /** axi_waddr_err_int_st : HRO; bitpos: [9]; default: 0; - * The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_C_AXI_WADDR_ERR_INT interrupt. */ uint32_t axi_waddr_err_int_st:1; - uint32_t reserved_10:22; + uint32_t reserved_10:16; + /** rx_trans_ovf_int_st : HRO; bitpos: [26]; default: 0; + * The status bit for SPI_MEM_C_RX_TRANS_OVF_INT interrupt. + */ + uint32_t rx_trans_ovf_int_st:1; + /** tx_trans_udf_int_st : HRO; bitpos: [27]; default: 0; + * The status bit for SPI_MEM_C_TX_TRANS_UDF_INT interrupt. + */ + uint32_t tx_trans_udf_int_st:1; + uint32_t reserved_28:4; }; uint32_t val; } spi_mem_c_int_st_reg_t; +/** Group: DLL debug and configuration registers */ +/** Type of dll_dly_db register + * MSPI DLL function and debug configuration register + */ +typedef union { + struct { + /** dll_db_cfg_vld_cnt : HRO; bitpos: [7:0]; default: 0; + * Configures the end time of the debug window. + */ + uint32_t dll_db_cfg_vld_cnt:8; + /** dll_db_cnt_mode_sel : HRO; bitpos: [11:8]; default: 0; + * [3]:1-spi_din[15:8]. 0-spi_din[7:0]. [2]:1-only shift wptr or rptr. 0-both shift + * wptr and rptr. [1]:1-wprt[3:0] and rptr[3:0]. 0-rptr[3:0] and wprt[3:0]. + * [0]:1-neg_ptr[3:0]. 0-pos_prt[3:0]. + */ + uint32_t dll_db_cnt_mode_sel:4; + /** dll_db_cnt_clr : HRO; bitpos: [12]; default: 0; + * Configures the start time of the debug window. 1: Clear db_vld_cnt to 0 and Get + * ready for debug. 0: No debug. + */ + uint32_t dll_db_cnt_clr:1; + /** dll_din_dly_sel : HRO; bitpos: [13]; default: 0; + * Configures the din channel. 1: Use delayed data. 0: Do not use delayed data. + */ + uint32_t dll_din_dly_sel:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} spi_mem_c_dll_dly_db_reg_t; + + +/** Group: DLL debug status registers */ +/** Type of dll_db_st0 register + * MSPI DLL debug status0 register + */ +typedef union { + struct { + /** db_fifo_cnt_h : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[63:32] + */ + uint32_t db_fifo_cnt_h:32; + }; + uint32_t val; +} spi_mem_c_dll_db_st0_reg_t; + +/** Type of dll_db_st1 register + * MSPI DLL debug status1 register + */ +typedef union { + struct { + /** db_fifo_cnt_l : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[31:0] + */ + uint32_t db_fifo_cnt_l:32; + }; + uint32_t val; +} spi_mem_c_dll_db_st1_reg_t; + + /** Group: PMS control and configuration registers */ /** Type of fmem_pmsn_attr register - * MSPI flash PMS section n attribute register + * SPI1 flash PMS section n attribute register */ typedef union { struct { @@ -915,11 +1350,25 @@ typedef union { uint32_t fmem_pmsn_wr_attr:1; /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0; * SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section n is configured by registers SPI_MEM_C_FMEM__PMSn_ADDR_REG and - * SPI_MEM_C_FMEM__PMSn_SIZE_REG. + * section n is configured by registers SPI_MEM_C_fmem_PMSn_ADDR_REG and + * SPI_MEM_C_fmem_PMSn_SIZE_REG. */ uint32_t fmem_pmsn_ecc:1; - uint32_t reserved_3:29; + /** fmem_pmsn_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section n read accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_nonsecure_rd_attr:1; + /** fmem_pmsn_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section n write accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_nonsecure_wr_attr:1; + /** fmem_pmsn_nonsecure_ecc : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section n is configured by registers SPI_MEM_C_fmem_PMSn_ADDR_REG + * and SPI_MEM_C_fmem_PMSn_SIZE_REG. + */ + uint32_t fmem_pmsn_nonsecure_ecc:1; + uint32_t reserved_6:26; }; uint32_t val; } spi_mem_c_fmem_pmsn_attr_reg_t; @@ -944,8 +1393,8 @@ typedef union { typedef union { struct { /** fmem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section n address region is (SPI_MEM_C_FMEM__PMSn_ADDR_S, - * SPI_MEM_C_FMEM__PMSn_ADDR_S + SPI_MEM_C_FMEM__PMSn_SIZE) + * SPI1 flash PMS section n address region is (SPI_MEM_C_fmem_PMSn_ADDR_S, + * SPI_MEM_C_fmem_PMSn_ADDR_S + SPI_MEM_C_fmem_PMSn_SIZE) */ uint32_t fmem_pmsn_size:15; uint32_t reserved_15:17; @@ -954,7 +1403,7 @@ typedef union { } spi_mem_c_fmem_pmsn_size_reg_t; /** Type of smem_pmsn_attr register - * SPI1 flash PMS section n start address register + * SPI1 external RAM PMS section n attribute register */ typedef union { struct { @@ -968,11 +1417,25 @@ typedef union { uint32_t smem_pmsn_wr_attr:1; /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section n is configured by registers SPI_MEM_C_SMEM_PMSn_ADDR_REG and - * SPI_MEM_C_SMEM_PMSn_SIZE_REG. + * external RAM PMS section n is configured by registers SPI_MEM_C_SMEM_PMSn_ADDR_REG + * and SPI_MEM_C_SMEM_PMSn_SIZE_REG. */ uint32_t smem_pmsn_ecc:1; - uint32_t reserved_3:29; + /** smem_pmsn_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section n read accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_nonsecure_rd_attr:1; + /** smem_pmsn_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section n write accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_nonsecure_wr_attr:1; + /** smem_pmsn_nonsecure_ecc : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section n ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section n is configured by registers + * SPI_MEM_C_SMEM_PMSn_ADDR_REG and SPI_MEM_C_SMEM_PMSn_SIZE_REG. + */ + uint32_t smem_pmsn_nonsecure_ecc:1; + uint32_t reserved_6:26; }; uint32_t val; } spi_mem_c_smem_pmsn_attr_reg_t; @@ -1013,7 +1476,7 @@ typedef union { struct { /** reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first SPI1 access error address. It is cleared by when - * spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_C_PMS_REJECT_INT_CLR bit is set. */ uint32_t reject_addr:27; /** pm_en : R/W; bitpos: [27]; default: 0; @@ -1022,22 +1485,22 @@ typedef union { uint32_t pm_en:1; /** pms_ld : R/SS/WTC; bitpos: [28]; default: 0; * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_C_PMS_REJECT_INT_CLR bit is set. */ uint32_t pms_ld:1; /** pms_st : R/SS/WTC; bitpos: [29]; default: 0; * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_C_PMS_REJECT_INT_CLR bit is set. */ uint32_t pms_st:1; /** pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. + * cleared by when SPI_MEM_C_PMS_REJECT_INT_CLR bit is set. */ uint32_t pms_multi_hit:1; /** pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. + * error. It is cleared by when SPI_MEM_C_PMS_REJECT_INT_CLR bit is set. */ uint32_t pms_ivd:1; }; @@ -1054,11 +1517,12 @@ typedef union { uint32_t reserved_0:5; /** ecc_err_cnt : HRO; bitpos: [10:5]; default: 0; * This bits show the error times of MSPI ECC read. It is cleared by when - * spi_mem_c_C_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_C_ECC_ERR_INT_CLR bit is set. */ uint32_t ecc_err_cnt:6; /** fmem_ecc_err_int_num : HRO; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI spi_mem_c_C_ECC_ERR_INT interrupt. + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_C_ECC_ERR_INT + * interrupt. */ uint32_t fmem_ecc_err_int_num:6; /** fmem_ecc_err_int_en : HRO; bitpos: [17]; default: 0; @@ -1082,9 +1546,9 @@ typedef union { uint32_t usr_ecc_addr_en:1; uint32_t reserved_22:2; /** ecc_continue_record_err_en : HRO; bitpos: [24]; default: 1; - * 1: The error information in spi_mem_c_C_ECC_ERR_BITS and spi_mem_c_C_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: spi_mem_c_C_ECC_ERR_BITS and - * spi_mem_c_C_ECC_ERR_ADDR record the first ECC error information. + * 1: The error information in SPI_MEM_C_ECC_ERR_BITS and SPI_MEM_C_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_C_ECC_ERR_BITS and + * SPI_MEM_C_ECC_ERR_ADDR record the first ECC error information. */ uint32_t ecc_continue_record_err_en:1; /** ecc_err_bits : HRO; bitpos: [31:25]; default: 0; @@ -1103,7 +1567,7 @@ typedef union { struct { /** ecc_err_addr : HRO; bitpos: [26:0]; default: 0; * This bits show the first MSPI ECC error address. It is cleared by when - * spi_mem_c_C_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_C_ECC_ERR_INT_CLR bit is set. */ uint32_t ecc_err_addr:27; uint32_t reserved_27:5; @@ -1744,13 +2208,13 @@ typedef union { */ typedef union { struct { - /** xts_physical_address : R/W; bitpos: [25:0]; default: 0; + /** xts_physical_address : R/W; bitpos: [29:0]; default: 0; * This bits stores the physical-address parameter which will be used in manual * encryption calculation. This value should aligned with byte number decided by * line-size parameter. */ - uint32_t xts_physical_address:26; - uint32_t reserved_26:6; + uint32_t xts_physical_address:30; + uint32_t reserved_30:2; }; uint32_t val; } spi_mem_c_xts_physical_address_reg_t; @@ -1829,7 +2293,7 @@ typedef union { */ typedef union { struct { - /** xts_date : R/W; bitpos: [29:0]; default: 538972176; + /** xts_date : R/W; bitpos: [29:0]; default: 539035911; * This bits stores the last modified-time of manual encryption feature. */ uint32_t xts_date:30; @@ -1895,7 +2359,16 @@ typedef union { * MMU PSRAM aux control register */ uint32_t aux_ctrl:14; - uint32_t reserved_30:2; + /** rdn_ena : HRO; bitpos: [30]; default: 0; + * ECO register enable bit + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t rdn_ena:1; + /** rdn_result : RO; bitpos: [31]; default: 0; + * MSPI module clock domain and AXI clock domain ECO register result register + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t rdn_result:1; }; uint32_t val; } spi_mem_c_mmu_power_ctrl_reg_t; @@ -1914,14 +2387,14 @@ typedef union { */ uint32_t crypt_security_level:3; /** crypt_calc_d_dpa_en : R/W; bitpos: [3]; default: 1; - * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * Only available when SPI_MEM_C_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that * using key 1. */ uint32_t crypt_calc_d_dpa_en:1; /** crypt_dpa_select_register : R/W; bitpos: [4]; default: 0; - * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and - * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + * 1: MSPI XTS DPA clock gate is controlled by SPI_MEM_C_CRYPT_CALC_D_DPA_EN and + * SPI_MEM_C_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. */ uint32_t crypt_dpa_select_register:1; uint32_t reserved_5:27; @@ -1930,13 +2403,74 @@ typedef union { } spi_mem_c_dpa_ctrl_reg_t; +/** Group: External mem cryption PSEUDO registers */ +/** Type of xts_pseudo_round_conf register + * SPI memory cryption PSEUDO register + */ +typedef union { + struct { + /** mode_pseudo : R/W; bitpos: [1:0]; default: 0; + * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo + * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. + * 2'b11: crypto with pseudo. + */ + uint32_t mode_pseudo:2; + /** pseudo_rng_cnt : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be performed. + */ + uint32_t pseudo_rng_cnt:3; + /** pseudo_base : R/W; bitpos: [8:5]; default: 2; + * xts aes peseudo function base round that must be performed. + */ + uint32_t pseudo_base:4; + /** pseudo_inc : R/W; bitpos: [10:9]; default: 2; + * xts aes peseudo function increment round that will be performed randomly between 0 & + * 2**(inc+1). + */ + uint32_t pseudo_inc:2; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_c_xts_pseudo_round_conf_reg_t; + + +/** Group: ECO registers */ +/** Type of registerrnd_eco_high register + * MSPI ECO high register + */ +typedef union { + struct { + /** registerrnd_eco_high : RO; bitpos: [31:0]; default: 892; + * ECO high register + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t registerrnd_eco_high:32; + }; + uint32_t val; +} spi_mem_c_registerrnd_eco_high_reg_t; + +/** Type of registerrnd_eco_low register + * MSPI ECO low register + */ +typedef union { + struct { + /** registerrnd_eco_low : RO; bitpos: [31:0]; default: 892; + * ECO low register + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t registerrnd_eco_low:32; + }; + uint32_t val; +} spi_mem_c_registerrnd_eco_low_reg_t; + + /** Group: Version control register */ /** Type of date register * SPI0 version control register */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36712560; + /** date : R/W; bitpos: [27:0]; default: 38805888; * SPI0 register version. */ uint32_t date:28; @@ -1946,7 +2480,7 @@ typedef union { } spi_mem_c_date_reg_t; -typedef struct spi_mem_c_dev_s { +typedef struct { volatile spi_mem_c_cmd_reg_t cmd; uint32_t reserved_004; volatile spi_mem_c_ctrl_reg_t ctrl; @@ -1956,13 +2490,17 @@ typedef struct spi_mem_c_dev_s { volatile spi_mem_c_user_reg_t user; volatile spi_mem_c_user1_reg_t user1; volatile spi_mem_c_user2_reg_t user2; - uint32_t reserved_024[4]; + uint32_t reserved_024[2]; + volatile spi_mem_c_rd_status_reg_t rd_status; + uint32_t reserved_030; volatile spi_mem_c_misc_reg_t misc; uint32_t reserved_038; volatile spi_mem_c_cache_fctrl_reg_t cache_fctrl; - uint32_t reserved_040; + volatile spi_mem_c_cache_sctrl_reg_t cache_sctrl; volatile spi_mem_c_sram_cmd_reg_t sram_cmd; - uint32_t reserved_048[3]; + volatile spi_mem_c_sram_drd_cmd_reg_t sram_drd_cmd; + volatile spi_mem_c_sram_dwr_cmd_reg_t sram_dwr_cmd; + volatile spi_mem_c_sram_clk_reg_t sram_clk; volatile spi_mem_c_fsm_reg_t fsm; uint32_t reserved_058[26]; volatile spi_mem_c_int_ena_reg_t int_ena; @@ -1972,7 +2510,10 @@ typedef struct spi_mem_c_dev_s { uint32_t reserved_0d0; volatile spi_mem_c_ddr_reg_t ddr; volatile spi_mem_c_smem_ddr_reg_t smem_ddr; - uint32_t reserved_0dc[9]; + volatile spi_mem_c_dll_dly_db_reg_t dll_dly_db; + volatile spi_mem_c_dll_db_st0_reg_t dll_db_st0; + volatile spi_mem_c_dll_db_st1_reg_t dll_db_st1; + uint32_t reserved_0e8[6]; volatile spi_mem_c_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; volatile spi_mem_c_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; volatile spi_mem_c_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; @@ -2014,7 +2555,11 @@ typedef struct spi_mem_c_dev_s { volatile spi_mem_c_mmu_item_index_reg_t mmu_item_index; volatile spi_mem_c_mmu_power_ctrl_reg_t mmu_power_ctrl; volatile spi_mem_c_dpa_ctrl_reg_t dpa_ctrl; - uint32_t reserved_38c[28]; + volatile spi_mem_c_xts_pseudo_round_conf_reg_t xts_pseudo_round_conf; + uint32_t reserved_390[24]; + volatile spi_mem_c_registerrnd_eco_high_reg_t registerrnd_eco_high; + volatile spi_mem_c_registerrnd_eco_low_reg_t registerrnd_eco_low; + uint32_t reserved_3f8; volatile spi_mem_c_date_reg_t date; } spi_mem_c_dev_t; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_reg.h index cb15d5b07d27..003f89681ecd 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_reg.h @@ -34,9 +34,9 @@ extern "C" { #define SPI_MEM_S_SLV_ST_V 0x0000000FU #define SPI_MEM_S_SLV_ST_S 4 /** SPI_MEM_S_USR : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when SPI_MEM_S_AXI_REQ_EN is cleared. An operation - * will be triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. + * SPI0 USR_CMD start bit, only used when SPI_MEM_S_AXI_REQ_EN is cleared. An + * operation will be triggered when the bit is set. The bit will be cleared once the + * operation done.1: enable 0: disable. */ #define SPI_MEM_S_USR (BIT(18)) #define SPI_MEM_S_USR_M (SPI_MEM_S_USR_V << SPI_MEM_S_USR_S) @@ -117,8 +117,8 @@ extern "C" { #define SPI_MEM_S_FCMD_OCT_V 0x00000001U #define SPI_MEM_S_FCMD_OCT_S 9 /** SPI_MEM_S_FASTRD_MODE : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: SPI_MEM_S_FREAD_QIO, SPI_MEM_S_FREAD_DIO, SPI_MEM_S_FREAD_QOUT - * and SPI_MEM_S_FREAD_DOUT. 1: enable 0: disable. + * This bit enable the bits: SPI_MEM_S_FREAD_QIO, SPI_MEM_S_FREAD_DIO, + * SPI_MEM_S_FREAD_QOUT and SPI_MEM_S_FREAD_DOUT. 1: enable 0: disable. */ #define SPI_MEM_S_FASTRD_MODE (BIT(13)) #define SPI_MEM_S_FASTRD_MODE_M (SPI_MEM_S_FASTRD_MODE_V << SPI_MEM_S_FASTRD_MODE_S) @@ -220,14 +220,6 @@ extern "C" { #define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_M (SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_V << SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_S) #define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U #define SPI_MEM_S_AW_SIZE0_1_SUPPORT_EN_S 22 -/** SPI_MEM_S_AXI_RDATA_BACK_FAST : R/W; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ -#define SPI_MEM_S_AXI_RDATA_BACK_FAST (BIT(23)) -#define SPI_MEM_S_AXI_RDATA_BACK_FAST_M (SPI_MEM_S_AXI_RDATA_BACK_FAST_V << SPI_MEM_S_AXI_RDATA_BACK_FAST_S) -#define SPI_MEM_S_AXI_RDATA_BACK_FAST_V 0x00000001U -#define SPI_MEM_S_AXI_RDATA_BACK_FAST_S 23 /** SPI_MEM_S_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded @@ -316,8 +308,8 @@ extern "C" { #define SPI_MEM_S_CS_HOLD_TIME_V 0x0000001FU #define SPI_MEM_S_CS_HOLD_TIME_S 5 /** SPI_MEM_S_ECC_CS_HOLD_TIME : R/W; bitpos: [12:10]; default: 3; - * SPI_MEM_S_CS_HOLD_TIME + SPI_MEM_S_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC - * mode when accessed flash. + * SPI_MEM_S_CS_HOLD_TIME + SPI_MEM_S_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in + * ECC mode when accessed flash. */ #define SPI_MEM_S_ECC_CS_HOLD_TIME 0x00000007U #define SPI_MEM_S_ECC_CS_HOLD_TIME_M (SPI_MEM_S_ECC_CS_HOLD_TIME_V << SPI_MEM_S_ECC_CS_HOLD_TIME_S) @@ -370,14 +362,14 @@ extern "C" { */ #define SPI_MEM_S_CLOCK_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14) /** SPI_MEM_S_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_S_CLKCNT_N. */ #define SPI_MEM_S_CLKCNT_L 0x000000FFU #define SPI_MEM_S_CLKCNT_L_M (SPI_MEM_S_CLKCNT_L_V << SPI_MEM_S_CLKCNT_L_S) #define SPI_MEM_S_CLKCNT_L_V 0x000000FFU #define SPI_MEM_S_CLKCNT_L_S 0 /** SPI_MEM_S_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_S_CLKCNT_N+1)/2-1). */ #define SPI_MEM_S_CLKCNT_H 0x000000FFU #define SPI_MEM_S_CLKCNT_H_M (SPI_MEM_S_CLKCNT_H_V << SPI_MEM_S_CLKCNT_H_S) @@ -385,7 +377,7 @@ extern "C" { #define SPI_MEM_S_CLKCNT_H_S 8 /** SPI_MEM_S_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) + * system/(SPI_MEM_S_CLKCNT_N+1) */ #define SPI_MEM_S_CLKCNT_N 0x000000FFU #define SPI_MEM_S_CLKCNT_N_M (SPI_MEM_S_CLKCNT_N_V << SPI_MEM_S_CLKCNT_N_S) @@ -488,10 +480,13 @@ extern "C" { /** SPI_MEM_S_RD_STATUS_REG register * SPI0 read control register. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_S_RD_STATUS_REG (DR_REG_PSRAM_MSPI0_BASE + 0x2c) /** SPI_MEM_S_WB_MODE : R/W; bitpos: [23:16]; default: 0; * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_WB_MODE 0x000000FFU #define SPI_MEM_S_WB_MODE_M (SPI_MEM_S_WB_MODE_V << SPI_MEM_S_WB_MODE_S) @@ -502,14 +497,35 @@ extern "C" { * SPI0 misc register */ #define SPI_MEM_S_MISC_REG (DR_REG_PSRAM_MSPI0_BASE + 0x34) -/** SPI_MEM_S_FSUB_PIN : R/W; bitpos: [7]; default: 0; +/** SPI_MEM_S_DQ_OE_CTRL : R/W; bitpos: [4]; default: 1; + * For SPI BUS IO, APB ctrl IO DQ OE func.1: enable 0: disable. + */ +#define SPI_MEM_S_DQ_OE_CTRL (BIT(4)) +#define SPI_MEM_S_DQ_OE_CTRL_M (SPI_MEM_S_DQ_OE_CTRL_V << SPI_MEM_S_DQ_OE_CTRL_S) +#define SPI_MEM_S_DQ_OE_CTRL_V 0x00000001U +#define SPI_MEM_S_DQ_OE_CTRL_S 4 +/** SPI_MEM_S_CK_OE_CTRL : R/W; bitpos: [5]; default: 1; + * For SPI BUS IO, APB ctrl IO CK OE func.1: enable 0: disable. + */ +#define SPI_MEM_S_CK_OE_CTRL (BIT(5)) +#define SPI_MEM_S_CK_OE_CTRL_M (SPI_MEM_S_CK_OE_CTRL_V << SPI_MEM_S_CK_OE_CTRL_S) +#define SPI_MEM_S_CK_OE_CTRL_V 0x00000001U +#define SPI_MEM_S_CK_OE_CTRL_S 5 +/** SPI_MEM_S_CS_OE_CTRL : R/W; bitpos: [6]; default: 1; + * For SPI BUS IO, APB ctrl IO CS OE func.1: enable 0: disable. + */ +#define SPI_MEM_S_CS_OE_CTRL (BIT(6)) +#define SPI_MEM_S_CS_OE_CTRL_M (SPI_MEM_S_CS_OE_CTRL_V << SPI_MEM_S_CS_OE_CTRL_S) +#define SPI_MEM_S_CS_OE_CTRL_V 0x00000001U +#define SPI_MEM_S_CS_OE_CTRL_S 6 +/** SPI_MEM_S_FSUB_PIN : HRO; bitpos: [7]; default: 0; * For SPI0, flash is connected to SUBPINs. */ #define SPI_MEM_S_FSUB_PIN (BIT(7)) #define SPI_MEM_S_FSUB_PIN_M (SPI_MEM_S_FSUB_PIN_V << SPI_MEM_S_FSUB_PIN_S) #define SPI_MEM_S_FSUB_PIN_V 0x00000001U #define SPI_MEM_S_FSUB_PIN_S 7 -/** SPI_MEM_S_SSUB_PIN : R/W; bitpos: [8]; default: 0; +/** SPI_MEM_S_SSUB_PIN : HRO; bitpos: [8]; default: 0; * For SPI0, sram is connected to SUBPINs. */ #define SPI_MEM_S_SSUB_PIN (BIT(8)) @@ -537,6 +553,7 @@ extern "C" { #define SPI_MEM_S_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3c) /** SPI_MEM_S_AXI_REQ_EN : R/W; bitpos: [0]; default: 0; * For SPI0, AXI master access enable, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_AXI_REQ_EN (BIT(0)) #define SPI_MEM_S_AXI_REQ_EN_M (SPI_MEM_S_AXI_REQ_EN_V << SPI_MEM_S_AXI_REQ_EN_S) @@ -544,6 +561,7 @@ extern "C" { #define SPI_MEM_S_AXI_REQ_EN_S 0 /** SPI_MEM_S_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_USR_ADDR_4BYTE (BIT(1)) #define SPI_MEM_S_CACHE_USR_ADDR_4BYTE_M (SPI_MEM_S_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_S_CACHE_USR_ADDR_4BYTE_S) @@ -551,6 +569,7 @@ extern "C" { #define SPI_MEM_S_CACHE_USR_ADDR_4BYTE_S 1 /** SPI_MEM_S_CACHE_FLASH_USR_CMD : R/W; bitpos: [2]; default: 0; * For SPI0, cache read flash for user define command, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_FLASH_USR_CMD (BIT(2)) #define SPI_MEM_S_CACHE_FLASH_USR_CMD_M (SPI_MEM_S_CACHE_FLASH_USR_CMD_V << SPI_MEM_S_CACHE_FLASH_USR_CMD_S) @@ -559,6 +578,7 @@ extern "C" { /** SPI_MEM_S_FDIN_DUAL : R/W; bitpos: [3]; default: 0; * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_FDIN_DUAL (BIT(3)) #define SPI_MEM_S_FDIN_DUAL_M (SPI_MEM_S_FDIN_DUAL_V << SPI_MEM_S_FDIN_DUAL_S) @@ -567,6 +587,7 @@ extern "C" { /** SPI_MEM_S_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the * same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_FDOUT_DUAL (BIT(4)) #define SPI_MEM_S_FDOUT_DUAL_M (SPI_MEM_S_FDOUT_DUAL_V << SPI_MEM_S_FDOUT_DUAL_S) @@ -575,6 +596,7 @@ extern "C" { /** SPI_MEM_S_FADDR_DUAL : R/W; bitpos: [5]; default: 0; * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is * the same with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_FADDR_DUAL (BIT(5)) #define SPI_MEM_S_FADDR_DUAL_M (SPI_MEM_S_FADDR_DUAL_V << SPI_MEM_S_FADDR_DUAL_S) @@ -583,6 +605,7 @@ extern "C" { /** SPI_MEM_S_FDIN_QUAD : R/W; bitpos: [6]; default: 0; * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_FDIN_QUAD (BIT(6)) #define SPI_MEM_S_FDIN_QUAD_M (SPI_MEM_S_FDIN_QUAD_V << SPI_MEM_S_FDIN_QUAD_S) @@ -591,6 +614,7 @@ extern "C" { /** SPI_MEM_S_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the * same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_FDOUT_QUAD (BIT(7)) #define SPI_MEM_S_FDOUT_QUAD_M (SPI_MEM_S_FDOUT_QUAD_V << SPI_MEM_S_FDOUT_QUAD_S) @@ -599,11 +623,52 @@ extern "C" { /** SPI_MEM_S_FADDR_QUAD : R/W; bitpos: [8]; default: 0; * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_FADDR_QUAD (BIT(8)) #define SPI_MEM_S_FADDR_QUAD_M (SPI_MEM_S_FADDR_QUAD_V << SPI_MEM_S_FADDR_QUAD_S) #define SPI_MEM_S_FADDR_QUAD_V 0x00000001U #define SPI_MEM_S_FADDR_QUAD_S 8 +/** SPI_MEM_S_ARB_WEI_EN : R/W; bitpos: [9]; default: 0; + * To enable SPI0 arbiter weight func while AXI read/write access SPI0 1: enable 0: + * disable. + */ +#define SPI_MEM_S_ARB_WEI_EN (BIT(9)) +#define SPI_MEM_S_ARB_WEI_EN_M (SPI_MEM_S_ARB_WEI_EN_V << SPI_MEM_S_ARB_WEI_EN_S) +#define SPI_MEM_S_ARB_WEI_EN_V 0x00000001U +#define SPI_MEM_S_ARB_WEI_EN_S 9 +/** SPI_MEM_S_ARB_REQ0_PRI : R/W; bitpos: [10]; default: 0; + * To set AXI read priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ +#define SPI_MEM_S_ARB_REQ0_PRI (BIT(10)) +#define SPI_MEM_S_ARB_REQ0_PRI_M (SPI_MEM_S_ARB_REQ0_PRI_V << SPI_MEM_S_ARB_REQ0_PRI_S) +#define SPI_MEM_S_ARB_REQ0_PRI_V 0x00000001U +#define SPI_MEM_S_ARB_REQ0_PRI_S 10 +/** SPI_MEM_S_ARB_REQ1_PRI : R/W; bitpos: [11]; default: 0; + * To set AXI write priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ +#define SPI_MEM_S_ARB_REQ1_PRI (BIT(11)) +#define SPI_MEM_S_ARB_REQ1_PRI_M (SPI_MEM_S_ARB_REQ1_PRI_V << SPI_MEM_S_ARB_REQ1_PRI_S) +#define SPI_MEM_S_ARB_REQ1_PRI_V 0x00000001U +#define SPI_MEM_S_ARB_REQ1_PRI_S 11 +/** SPI_MEM_S_ARB_REQ0_WEI : R/W; bitpos: [15:12]; default: 0; + * To set AXI read priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ +#define SPI_MEM_S_ARB_REQ0_WEI 0x0000000FU +#define SPI_MEM_S_ARB_REQ0_WEI_M (SPI_MEM_S_ARB_REQ0_WEI_V << SPI_MEM_S_ARB_REQ0_WEI_S) +#define SPI_MEM_S_ARB_REQ0_WEI_V 0x0000000FU +#define SPI_MEM_S_ARB_REQ0_WEI_S 12 +/** SPI_MEM_S_ARB_REQ1_WEI : R/W; bitpos: [19:16]; default: 0; + * To set AXI write priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ +#define SPI_MEM_S_ARB_REQ1_WEI 0x0000000FU +#define SPI_MEM_S_ARB_REQ1_WEI_M (SPI_MEM_S_ARB_REQ1_WEI_V << SPI_MEM_S_ARB_REQ1_WEI_S) +#define SPI_MEM_S_ARB_REQ1_WEI_V 0x0000000FU +#define SPI_MEM_S_ARB_REQ1_WEI_S 16 /** SPI_MEM_S_SAME_AW_AR_ADDR_CHK_EN : R/W; bitpos: [30]; default: 1; * Set this bit to check AXI read/write the same address region. */ @@ -622,11 +687,14 @@ extern "C" { /** SPI_MEM_S_CACHE_SCTRL_REG register * SPI0 external RAM control register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_S_CACHE_SCTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x40) /** SPI_MEM_S_CACHE_USR_SADDR_4BYTE : R/W; bitpos: [0]; default: 0; * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: * enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_USR_SADDR_4BYTE (BIT(0)) #define SPI_MEM_S_CACHE_USR_SADDR_4BYTE_M (SPI_MEM_S_CACHE_USR_SADDR_4BYTE_V << SPI_MEM_S_CACHE_USR_SADDR_4BYTE_S) @@ -634,6 +702,7 @@ extern "C" { #define SPI_MEM_S_CACHE_USR_SADDR_4BYTE_S 0 /** SPI_MEM_S_USR_SRAM_DIO : R/W; bitpos: [1]; default: 0; * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_USR_SRAM_DIO (BIT(1)) #define SPI_MEM_S_USR_SRAM_DIO_M (SPI_MEM_S_USR_SRAM_DIO_V << SPI_MEM_S_USR_SRAM_DIO_S) @@ -641,6 +710,7 @@ extern "C" { #define SPI_MEM_S_USR_SRAM_DIO_S 1 /** SPI_MEM_S_USR_SRAM_QIO : R/W; bitpos: [2]; default: 0; * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_USR_SRAM_QIO (BIT(2)) #define SPI_MEM_S_USR_SRAM_QIO_M (SPI_MEM_S_USR_SRAM_QIO_V << SPI_MEM_S_USR_SRAM_QIO_S) @@ -649,6 +719,7 @@ extern "C" { /** SPI_MEM_S_USR_WR_SRAM_DUMMY : R/W; bitpos: [3]; default: 0; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write * operations. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_USR_WR_SRAM_DUMMY (BIT(3)) #define SPI_MEM_S_USR_WR_SRAM_DUMMY_M (SPI_MEM_S_USR_WR_SRAM_DUMMY_V << SPI_MEM_S_USR_WR_SRAM_DUMMY_S) @@ -657,6 +728,7 @@ extern "C" { /** SPI_MEM_S_USR_RD_SRAM_DUMMY : R/W; bitpos: [4]; default: 1; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read * operations. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_USR_RD_SRAM_DUMMY (BIT(4)) #define SPI_MEM_S_USR_RD_SRAM_DUMMY_M (SPI_MEM_S_USR_RD_SRAM_DUMMY_V << SPI_MEM_S_USR_RD_SRAM_DUMMY_S) @@ -664,6 +736,7 @@ extern "C" { #define SPI_MEM_S_USR_RD_SRAM_DUMMY_S 4 /** SPI_MEM_S_CACHE_SRAM_USR_RCMD : R/W; bitpos: [5]; default: 1; * For SPI0, In the external RAM mode cache read external RAM for user define command. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_SRAM_USR_RCMD (BIT(5)) #define SPI_MEM_S_CACHE_SRAM_USR_RCMD_M (SPI_MEM_S_CACHE_SRAM_USR_RCMD_V << SPI_MEM_S_CACHE_SRAM_USR_RCMD_S) @@ -672,6 +745,7 @@ extern "C" { /** SPI_MEM_S_SRAM_RDUMMY_CYCLELEN : R/W; bitpos: [11:6]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SRAM_RDUMMY_CYCLELEN 0x0000003FU #define SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_M (SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_V << SPI_MEM_S_SRAM_RDUMMY_CYCLELEN_S) @@ -680,6 +754,7 @@ extern "C" { /** SPI_MEM_S_SRAM_ADDR_BITLEN : R/W; bitpos: [19:14]; default: 23; * For SPI0, In the external RAM mode, it is the length in bits of address phase. The * register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SRAM_ADDR_BITLEN 0x0000003FU #define SPI_MEM_S_SRAM_ADDR_BITLEN_M (SPI_MEM_S_SRAM_ADDR_BITLEN_V << SPI_MEM_S_SRAM_ADDR_BITLEN_S) @@ -687,6 +762,7 @@ extern "C" { #define SPI_MEM_S_SRAM_ADDR_BITLEN_S 14 /** SPI_MEM_S_CACHE_SRAM_USR_WCMD : R/W; bitpos: [20]; default: 1; * For SPI0, In the external RAM mode cache write sram for user define command + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_SRAM_USR_WCMD (BIT(20)) #define SPI_MEM_S_CACHE_SRAM_USR_WCMD_M (SPI_MEM_S_CACHE_SRAM_USR_WCMD_V << SPI_MEM_S_CACHE_SRAM_USR_WCMD_S) @@ -694,6 +770,7 @@ extern "C" { #define SPI_MEM_S_CACHE_SRAM_USR_WCMD_S 20 /** SPI_MEM_S_SRAM_OCT : R/W; bitpos: [21]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SRAM_OCT (BIT(21)) #define SPI_MEM_S_SRAM_OCT_M (SPI_MEM_S_SRAM_OCT_V << SPI_MEM_S_SRAM_OCT_S) @@ -702,6 +779,7 @@ extern "C" { /** SPI_MEM_S_SRAM_WDUMMY_CYCLELEN : R/W; bitpos: [27:22]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SRAM_WDUMMY_CYCLELEN 0x0000003FU #define SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_M (SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_V << SPI_MEM_S_SRAM_WDUMMY_CYCLELEN_S) @@ -716,6 +794,7 @@ extern "C" { * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: * SPI clock is always on. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SCLK_MODE 0x00000003U #define SPI_MEM_S_SCLK_MODE_M (SPI_MEM_S_SCLK_MODE_V << SPI_MEM_S_SCLK_MODE_S) @@ -724,6 +803,7 @@ extern "C" { /** SPI_MEM_S_SWB_MODE : R/W; bitpos: [9:2]; default: 0; * Mode bits in the external RAM fast read mode it is combined with * spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SWB_MODE 0x000000FFU #define SPI_MEM_S_SWB_MODE_M (SPI_MEM_S_SWB_MODE_V << SPI_MEM_S_SWB_MODE_S) @@ -732,6 +812,7 @@ extern "C" { /** SPI_MEM_S_SDIN_DUAL : R/W; bitpos: [10]; default: 0; * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is * the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDIN_DUAL (BIT(10)) #define SPI_MEM_S_SDIN_DUAL_M (SPI_MEM_S_SDIN_DUAL_V << SPI_MEM_S_SDIN_DUAL_S) @@ -740,6 +821,7 @@ extern "C" { /** SPI_MEM_S_SDOUT_DUAL : R/W; bitpos: [11]; default: 0; * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit * is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDOUT_DUAL (BIT(11)) #define SPI_MEM_S_SDOUT_DUAL_M (SPI_MEM_S_SDOUT_DUAL_V << SPI_MEM_S_SDOUT_DUAL_S) @@ -748,6 +830,7 @@ extern "C" { /** SPI_MEM_S_SADDR_DUAL : R/W; bitpos: [12]; default: 0; * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The * bit is the same with spi_mem_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SADDR_DUAL (BIT(12)) #define SPI_MEM_S_SADDR_DUAL_M (SPI_MEM_S_SADDR_DUAL_V << SPI_MEM_S_SADDR_DUAL_S) @@ -756,6 +839,7 @@ extern "C" { /** SPI_MEM_S_SDIN_QUAD : R/W; bitpos: [14]; default: 0; * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDIN_QUAD (BIT(14)) #define SPI_MEM_S_SDIN_QUAD_M (SPI_MEM_S_SDIN_QUAD_V << SPI_MEM_S_SDIN_QUAD_S) @@ -764,6 +848,7 @@ extern "C" { /** SPI_MEM_S_SDOUT_QUAD : R/W; bitpos: [15]; default: 0; * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit * is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDOUT_QUAD (BIT(15)) #define SPI_MEM_S_SDOUT_QUAD_M (SPI_MEM_S_SDOUT_QUAD_V << SPI_MEM_S_SDOUT_QUAD_S) @@ -772,6 +857,7 @@ extern "C" { /** SPI_MEM_S_SADDR_QUAD : R/W; bitpos: [16]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The * bit is the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SADDR_QUAD (BIT(16)) #define SPI_MEM_S_SADDR_QUAD_M (SPI_MEM_S_SADDR_QUAD_V << SPI_MEM_S_SADDR_QUAD_S) @@ -780,6 +866,7 @@ extern "C" { /** SPI_MEM_S_SCMD_QUAD : R/W; bitpos: [17]; default: 0; * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SCMD_QUAD (BIT(17)) #define SPI_MEM_S_SCMD_QUAD_M (SPI_MEM_S_SCMD_QUAD_V << SPI_MEM_S_SCMD_QUAD_S) @@ -787,6 +874,7 @@ extern "C" { #define SPI_MEM_S_SCMD_QUAD_S 17 /** SPI_MEM_S_SDIN_OCT : R/W; bitpos: [18]; default: 0; * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDIN_OCT (BIT(18)) #define SPI_MEM_S_SDIN_OCT_M (SPI_MEM_S_SDIN_OCT_V << SPI_MEM_S_SDIN_OCT_S) @@ -794,6 +882,7 @@ extern "C" { #define SPI_MEM_S_SDIN_OCT_S 18 /** SPI_MEM_S_SDOUT_OCT : R/W; bitpos: [19]; default: 0; * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDOUT_OCT (BIT(19)) #define SPI_MEM_S_SDOUT_OCT_M (SPI_MEM_S_SDOUT_OCT_V << SPI_MEM_S_SDOUT_OCT_S) @@ -801,6 +890,7 @@ extern "C" { #define SPI_MEM_S_SDOUT_OCT_S 19 /** SPI_MEM_S_SADDR_OCT : R/W; bitpos: [20]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SADDR_OCT (BIT(20)) #define SPI_MEM_S_SADDR_OCT_M (SPI_MEM_S_SADDR_OCT_V << SPI_MEM_S_SADDR_OCT_S) @@ -808,6 +898,7 @@ extern "C" { #define SPI_MEM_S_SADDR_OCT_S 20 /** SPI_MEM_S_SCMD_OCT : R/W; bitpos: [21]; default: 0; * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SCMD_OCT (BIT(21)) #define SPI_MEM_S_SCMD_OCT_M (SPI_MEM_S_SCMD_OCT_V << SPI_MEM_S_SCMD_OCT_S) @@ -816,6 +907,7 @@ extern "C" { /** SPI_MEM_S_SDUMMY_RIN : R/W; bitpos: [22]; default: 1; * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDUMMY_RIN (BIT(22)) #define SPI_MEM_S_SDUMMY_RIN_M (SPI_MEM_S_SDUMMY_RIN_V << SPI_MEM_S_SDUMMY_RIN_S) @@ -824,6 +916,7 @@ extern "C" { /** SPI_MEM_S_SDUMMY_WOUT : R/W; bitpos: [23]; default: 1; * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDUMMY_WOUT (BIT(23)) #define SPI_MEM_S_SDUMMY_WOUT_M (SPI_MEM_S_SDUMMY_WOUT_V << SPI_MEM_S_SDUMMY_WOUT_S) @@ -831,7 +924,7 @@ extern "C" { #define SPI_MEM_S_SDUMMY_WOUT_S 23 /** SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [24]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_MEM_S_DQS is output by the MSPI controller. + * the level of SPI_DQS is output by the MSPI controller. */ #define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) #define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_S) @@ -839,7 +932,7 @@ extern "C" { #define SPI_MEM_S_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 /** SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [25]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_MEM_S_IO[7:0] is output by the MSPI controller. + * the level of SPI_IO[7:0] is output by the MSPI controller. */ #define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) #define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_M (SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_S) @@ -847,6 +940,7 @@ extern "C" { #define SPI_MEM_S_SMEM_WDUMMY_ALWAYS_OUT_S 25 /** SPI_MEM_S_SDIN_HEX : R/W; bitpos: [26]; default: 0; * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDIN_HEX (BIT(26)) #define SPI_MEM_S_SDIN_HEX_M (SPI_MEM_S_SDIN_HEX_V << SPI_MEM_S_SDIN_HEX_S) @@ -854,13 +948,14 @@ extern "C" { #define SPI_MEM_S_SDIN_HEX_S 26 /** SPI_MEM_S_SDOUT_HEX : R/W; bitpos: [27]; default: 0; * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SDOUT_HEX (BIT(27)) #define SPI_MEM_S_SDOUT_HEX_M (SPI_MEM_S_SDOUT_HEX_V << SPI_MEM_S_SDOUT_HEX_S) #define SPI_MEM_S_SDOUT_HEX_V 0x00000001U #define SPI_MEM_S_SDOUT_HEX_S 27 /** SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_MEM_S_DQS are + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are * always 1. 0: Others. */ #define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) @@ -868,7 +963,7 @@ extern "C" { #define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_V 0x00000001U #define SPI_MEM_S_SMEM_DQS_IE_ALWAYS_ON_S 30 /** SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_MEM_S_IO[7:0] + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] * are always 1. 0: Others. */ #define SPI_MEM_S_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) @@ -878,11 +973,14 @@ extern "C" { /** SPI_MEM_S_SRAM_DRD_CMD_REG register * SPI0 external RAM DDR read command control register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_S_SRAM_DRD_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x48) /** SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the read command value of command phase * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFFU #define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_M (SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_V << SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_VALUE_S) @@ -891,6 +989,7 @@ extern "C" { /** SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the length in bits of command phase for * sram. The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000FU #define SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_M (SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_V << SPI_MEM_S_CACHE_SRAM_USR_RD_CMD_BITLEN_S) @@ -899,11 +998,14 @@ extern "C" { /** SPI_MEM_S_SRAM_DWR_CMD_REG register * SPI0 external RAM DDR write command control register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_S_SRAM_DWR_CMD_REG (DR_REG_PSRAM_MSPI0_BASE + 0x4c) /** SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the write command value of command phase * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFFU #define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_M (SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_V << SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_VALUE_S) @@ -912,6 +1014,7 @@ extern "C" { /** SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the in bits of command phase for sram. * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000FU #define SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_M (SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_V << SPI_MEM_S_CACHE_SRAM_USR_WR_CMD_BITLEN_S) @@ -920,17 +1023,21 @@ extern "C" { /** SPI_MEM_S_SRAM_CLK_REG register * SPI0 external RAM clock control register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_S_SRAM_CLK_REG (DR_REG_PSRAM_MSPI0_BASE + 0x50) /** SPI_MEM_S_SCLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. + * For SPI0 external RAM interface, it must be equal to SPI_MEM_S_SCLKCNT_N. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SCLKCNT_L 0x000000FFU #define SPI_MEM_S_SCLKCNT_L_M (SPI_MEM_S_SCLKCNT_L_V << SPI_MEM_S_SCLKCNT_L_S) #define SPI_MEM_S_SCLKCNT_L_V 0x000000FFU #define SPI_MEM_S_SCLKCNT_L_S 0 /** SPI_MEM_S_SCLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). + * For SPI0 external RAM interface, it must be floor((SPI_MEM_S_SCLKCNT_N+1)/2-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SCLKCNT_H 0x000000FFU #define SPI_MEM_S_SCLKCNT_H_M (SPI_MEM_S_SCLKCNT_H_V << SPI_MEM_S_SCLKCNT_H_S) @@ -938,7 +1045,8 @@ extern "C" { #define SPI_MEM_S_SCLKCNT_H_S 8 /** SPI_MEM_S_SCLKCNT_N : R/W; bitpos: [23:16]; default: 3; * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk - * frequency is system/(spi_mem_clkcnt_N+1) + * frequency is system/(SPI_MEM_S_SCLKCNT_N+1) + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SCLKCNT_N 0x000000FFU #define SPI_MEM_S_SCLKCNT_N_M (SPI_MEM_S_SCLKCNT_N_V << SPI_MEM_S_SCLKCNT_N_S) @@ -947,6 +1055,7 @@ extern "C" { /** SPI_MEM_S_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk * is divided from system clock. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_SCLK_EQU_SYSCLK (BIT(31)) #define SPI_MEM_S_SCLK_EQU_SYSCLK_M (SPI_MEM_S_SCLK_EQU_SYSCLK_V << SPI_MEM_S_SCLK_EQU_SYSCLK_S) @@ -957,12 +1066,12 @@ extern "C" { * SPI0 FSM status register */ #define SPI_MEM_S_FSM_REG (DR_REG_PSRAM_MSPI0_BASE + 0x54) -/** SPI_MEM_S_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; +/** SPI_MEM_S_LOCK_DELAY_TIME : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ -#define SPI_MEM_S_LOCK_DELAY_TIME 0x0000001FU +#define SPI_MEM_S_LOCK_DELAY_TIME 0x00000FFFU #define SPI_MEM_S_LOCK_DELAY_TIME_M (SPI_MEM_S_LOCK_DELAY_TIME_V << SPI_MEM_S_LOCK_DELAY_TIME_S) -#define SPI_MEM_S_LOCK_DELAY_TIME_V 0x0000001FU +#define SPI_MEM_S_LOCK_DELAY_TIME_V 0x00000FFFU #define SPI_MEM_S_LOCK_DELAY_TIME_S 7 /** SPI_MEM_S_INT_ENA_REG register @@ -1018,6 +1127,20 @@ extern "C" { #define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_S) #define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_V 0x00000001U #define SPI_MEM_S_AXI_WADDR_ERR_INT__ENA_S 9 +/** SPI_MEM_S_RX_TRANS_OVF_INT_ENA : R/W; bitpos: [26]; default: 0; + * The enable bit for SPI_MEM_S_RX_TRANS_OVF_INT interrupt. + */ +#define SPI_MEM_S_RX_TRANS_OVF_INT_ENA (BIT(26)) +#define SPI_MEM_S_RX_TRANS_OVF_INT_ENA_M (SPI_MEM_S_RX_TRANS_OVF_INT_ENA_V << SPI_MEM_S_RX_TRANS_OVF_INT_ENA_S) +#define SPI_MEM_S_RX_TRANS_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_S_RX_TRANS_OVF_INT_ENA_S 26 +/** SPI_MEM_S_TX_TRANS_UDF_INT_ENA : R/W; bitpos: [27]; default: 0; + * The enable bit for SPI_MEM_S_TX_TRANS_UDF_INT interrupt. + */ +#define SPI_MEM_S_TX_TRANS_UDF_INT_ENA (BIT(27)) +#define SPI_MEM_S_TX_TRANS_UDF_INT_ENA_M (SPI_MEM_S_TX_TRANS_UDF_INT_ENA_V << SPI_MEM_S_TX_TRANS_UDF_INT_ENA_S) +#define SPI_MEM_S_TX_TRANS_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_S_TX_TRANS_UDF_INT_ENA_S 27 /** SPI_MEM_S_DQS0_AFIFO_OVF_INT_ENA : R/W; bitpos: [28]; default: 0; * The enable bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ @@ -1100,6 +1223,20 @@ extern "C" { #define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_S) #define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_V 0x00000001U #define SPI_MEM_S_AXI_WADDR_ERR_INT_CLR_S 9 +/** SPI_MEM_S_RX_TRANS_OVF_INT_CLR : WT; bitpos: [26]; default: 0; + * The clear bit for SPI_MEM_S_RX_TRANS_OVF_INT interrupt. + */ +#define SPI_MEM_S_RX_TRANS_OVF_INT_CLR (BIT(26)) +#define SPI_MEM_S_RX_TRANS_OVF_INT_CLR_M (SPI_MEM_S_RX_TRANS_OVF_INT_CLR_V << SPI_MEM_S_RX_TRANS_OVF_INT_CLR_S) +#define SPI_MEM_S_RX_TRANS_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_S_RX_TRANS_OVF_INT_CLR_S 26 +/** SPI_MEM_S_TX_TRANS_UDF_INT_CLR : WT; bitpos: [27]; default: 0; + * The clear bit for SPI_MEM_S_TX_TRANS_UDF_INT interrupt. + */ +#define SPI_MEM_S_TX_TRANS_UDF_INT_CLR (BIT(27)) +#define SPI_MEM_S_TX_TRANS_UDF_INT_CLR_M (SPI_MEM_S_TX_TRANS_UDF_INT_CLR_V << SPI_MEM_S_TX_TRANS_UDF_INT_CLR_S) +#define SPI_MEM_S_TX_TRANS_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_S_TX_TRANS_UDF_INT_CLR_S 27 /** SPI_MEM_S_DQS0_AFIFO_OVF_INT_CLR : WT; bitpos: [28]; default: 0; * The clear bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ @@ -1134,8 +1271,8 @@ extern "C" { */ #define SPI_MEM_S_INT_RAW_REG (DR_REG_PSRAM_MSPI0_BASE + 0xc8) /** SPI_MEM_S_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * The raw bit for SPI_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st + * is changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ #define SPI_MEM_S_SLV_ST_END_INT_RAW (BIT(3)) @@ -1143,32 +1280,33 @@ extern "C" { #define SPI_MEM_S_SLV_ST_END_INT_RAW_V 0x00000001U #define SPI_MEM_S_SLV_ST_END_INT_RAW_S 3 /** SPI_MEM_S_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is - * changed from non idle state to idle state. 0: Others. + * The raw bit for SPI_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st + * is changed from non idle state to idle state. 0: Others. */ #define SPI_MEM_S_MST_ST_END_INT_RAW (BIT(4)) #define SPI_MEM_S_MST_ST_END_INT_RAW_M (SPI_MEM_S_MST_ST_END_INT_RAW_V << SPI_MEM_S_MST_ST_END_INT_RAW_S) #define SPI_MEM_S_MST_ST_END_INT_RAW_V 0x00000001U #define SPI_MEM_S_MST_ST_END_INT_RAW_S 4 /** SPI_MEM_S_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit for SPI_MEM_S_ECC_ERR_INT interrupt. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN is set - * and SPI_MEM_S_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_S_ECC_ERR_INT_NUM. When - * SPI_MEM_S_FMEM_ECC_ERR_INT_EN is cleared and SPI_MEM_S_SMEM_ECC_ERR_INT_EN is set, this bit is - * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and - * SPI_MEM_S_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times - * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and SPI_MEM_S_SMEM_ECC_ERR_INT_EN - * are cleared, this bit will not be triggered. + * The raw bit for SPI_MEM_S_ECC_ERR_INT interrupt. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN + * is set and SPI_MEM_S_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when + * the error times of SPI0/1 ECC read flash are equal or bigger than + * SPI_MEM_S_ECC_ERR_INT_NUM. When SPI_MEM_S_FMEM_ECC_ERR_INT_EN is cleared and + * SPI_MEM_S_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of + * SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_S_ECC_ERR_INT_NUM. + * When SPI_MEM_S_FMEM_ECC_ERR_INT_EN and SPI_MEM_S_SMEM_ECC_ERR_INT_EN are set, this + * bit is triggered when the total error times of SPI0/1 ECC read external RAM and + * flash are equal or bigger than SPI_MEM_S_ECC_ERR_INT_NUM. When + * SPI_MEM_S_FMEM_ECC_ERR_INT_EN and SPI_MEM_S_SMEM_ECC_ERR_INT_EN are cleared, this + * bit will not be triggered. */ #define SPI_MEM_S_ECC_ERR_INT_RAW (BIT(5)) #define SPI_MEM_S_ECC_ERR_INT_RAW_M (SPI_MEM_S_ECC_ERR_INT_RAW_V << SPI_MEM_S_ECC_ERR_INT_RAW_S) #define SPI_MEM_S_ECC_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_S_ECC_ERR_INT_RAW_S 5 /** SPI_MEM_S_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for SPI_MEM_S_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is - * rejected. 0: Others. + * The raw bit for SPI_MEM_S_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access + * is rejected. 0: Others. */ #define SPI_MEM_S_PMS_REJECT_INT_RAW (BIT(6)) #define SPI_MEM_S_PMS_REJECT_INT_RAW_M (SPI_MEM_S_PMS_REJECT_INT_RAW_V << SPI_MEM_S_PMS_REJECT_INT_RAW_S) @@ -1183,8 +1321,8 @@ extern "C" { #define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_S_AXI_RADDR_ERR_INT_RAW_S 7 /** SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write - * flash request is received. 0: Others. + * The raw bit for SPI_MEM_S_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI + * write flash request is received. 0: Others. */ #define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) #define SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_S_AXI_WR_FLASH_ERR_INT_RAW_S) @@ -1198,6 +1336,22 @@ extern "C" { #define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_S) #define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_S_AXI_WADDR_ERR_INT_RAW_S 9 +/** SPI_MEM_S_RX_TRANS_OVF_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * The raw bit for SPI_MEM_S_RX_TRANS_OVF_INT interrupt. 1: Triggered when the rx + * fifo to spi bus is overrflow. + */ +#define SPI_MEM_S_RX_TRANS_OVF_INT_RAW (BIT(26)) +#define SPI_MEM_S_RX_TRANS_OVF_INT_RAW_M (SPI_MEM_S_RX_TRANS_OVF_INT_RAW_V << SPI_MEM_S_RX_TRANS_OVF_INT_RAW_S) +#define SPI_MEM_S_RX_TRANS_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_S_RX_TRANS_OVF_INT_RAW_S 26 +/** SPI_MEM_S_TX_TRANS_UDF_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * The raw bit for SPI_MEM_S_TX_TRANS_UDF_INT interrupt. 1: Triggered when the tx fifo + * to spi bus is underflow. + */ +#define SPI_MEM_S_TX_TRANS_UDF_INT_RAW (BIT(27)) +#define SPI_MEM_S_TX_TRANS_UDF_INT_RAW_M (SPI_MEM_S_TX_TRANS_UDF_INT_RAW_V << SPI_MEM_S_TX_TRANS_UDF_INT_RAW_S) +#define SPI_MEM_S_TX_TRANS_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_S_TX_TRANS_UDF_INT_RAW_S 27 /** SPI_MEM_S_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; * The raw bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO * connected to SPI_DQS1 is overflow. @@ -1215,16 +1369,16 @@ extern "C" { #define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_V 0x00000001U #define SPI_MEM_S_DQS1_AFIFO_OVF_INT_RAW_S 29 /** SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; - * The raw bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is - * underflow. + * The raw bit for SPI_MEM_S_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO + * is underflow. */ #define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW (BIT(30)) #define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_M (SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_V << SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_S) #define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_V 0x00000001U #define SPI_MEM_S_BUS_FIFO1_UDF_INT_RAW_S 30 /** SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; - * The raw bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is - * underflow. + * The raw bit for SPI_MEM_S_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO + * is underflow. */ #define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW (BIT(31)) #define SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_M (SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_V << SPI_MEM_S_BUS_FIFO0_UDF_INT_RAW_S) @@ -1284,6 +1438,20 @@ extern "C" { #define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_S_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_S_AXI_WADDR_ERR_INT_ST_S) #define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_V 0x00000001U #define SPI_MEM_S_AXI_WADDR_ERR_INT_ST_S 9 +/** SPI_MEM_S_RX_TRANS_OVF_INT_ST : RO; bitpos: [26]; default: 0; + * The status bit for SPI_MEM_S_RX_TRANS_OVF_INT interrupt. + */ +#define SPI_MEM_S_RX_TRANS_OVF_INT_ST (BIT(26)) +#define SPI_MEM_S_RX_TRANS_OVF_INT_ST_M (SPI_MEM_S_RX_TRANS_OVF_INT_ST_V << SPI_MEM_S_RX_TRANS_OVF_INT_ST_S) +#define SPI_MEM_S_RX_TRANS_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_S_RX_TRANS_OVF_INT_ST_S 26 +/** SPI_MEM_S_TX_TRANS_UDF_INT_ST : RO; bitpos: [27]; default: 0; + * The status bit for SPI_MEM_S_TX_TRANS_UDF_INT interrupt. + */ +#define SPI_MEM_S_TX_TRANS_UDF_INT_ST (BIT(27)) +#define SPI_MEM_S_TX_TRANS_UDF_INT_ST_M (SPI_MEM_S_TX_TRANS_UDF_INT_ST_V << SPI_MEM_S_TX_TRANS_UDF_INT_ST_S) +#define SPI_MEM_S_TX_TRANS_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_S_TX_TRANS_UDF_INT_ST_S 27 /** SPI_MEM_S_DQS0_AFIFO_OVF_INT_ST : RO; bitpos: [28]; default: 0; * The status bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ @@ -1384,8 +1552,8 @@ extern "C" { #define SPI_MEM_S_FMEM_USR_DDR_DQS_THD_S 14 /** SPI_MEM_S_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ #define SPI_MEM_S_FMEM_DDR_DQS_LOOP (BIT(21)) @@ -1509,8 +1677,8 @@ extern "C" { #define SPI_MEM_S_SMEM_USR_DDR_DQS_THD_S 14 /** SPI_MEM_S_SMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal + * or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ #define SPI_MEM_S_SMEM_DDR_DQS_LOOP (BIT(21)) @@ -1564,124 +1732,278 @@ extern "C" { #define SPI_MEM_S_SMEM_HYPERBUS_CA_V 0x00000001U #define SPI_MEM_S_SMEM_HYPERBUS_CA_S 30 +/** SPI_MEM_S_DLL_DLY_DB_REG register + * MSPI DLL function and debug configuration register + */ +#define SPI_MEM_S_DLL_DLY_DB_REG (DR_REG_PSRAM_MSPI0_BASE + 0xdc) +/** SPI_MEM_S_DLL_DB_CFG_VLD_CNT : R/W; bitpos: [7:0]; default: 0; + * Configures the end time of the debug window. + */ +#define SPI_MEM_S_DLL_DB_CFG_VLD_CNT 0x000000FFU +#define SPI_MEM_S_DLL_DB_CFG_VLD_CNT_M (SPI_MEM_S_DLL_DB_CFG_VLD_CNT_V << SPI_MEM_S_DLL_DB_CFG_VLD_CNT_S) +#define SPI_MEM_S_DLL_DB_CFG_VLD_CNT_V 0x000000FFU +#define SPI_MEM_S_DLL_DB_CFG_VLD_CNT_S 0 +/** SPI_MEM_S_DLL_DB_CNT_MODE_SEL : R/W; bitpos: [11:8]; default: 0; + * [3]:1-spi_din[15:8]. 0-spi_din[7:0]. [2]:1-only shift wptr or rptr. 0-both shift + * wptr and rptr. [1]:1-wprt[3:0] and rptr[3:0]. 0-rptr[3:0] and wprt[3:0]. + * [0]:1-neg_ptr[3:0]. 0-pos_prt[3:0]. + */ +#define SPI_MEM_S_DLL_DB_CNT_MODE_SEL 0x0000000FU +#define SPI_MEM_S_DLL_DB_CNT_MODE_SEL_M (SPI_MEM_S_DLL_DB_CNT_MODE_SEL_V << SPI_MEM_S_DLL_DB_CNT_MODE_SEL_S) +#define SPI_MEM_S_DLL_DB_CNT_MODE_SEL_V 0x0000000FU +#define SPI_MEM_S_DLL_DB_CNT_MODE_SEL_S 8 +/** SPI_MEM_S_DLL_DB_CNT_CLR : R/W; bitpos: [12]; default: 0; + * Configures the start time of the debug window. 1: Clear db_vld_cnt to 0 and Get + * ready for debug. 0: No debug. + */ +#define SPI_MEM_S_DLL_DB_CNT_CLR (BIT(12)) +#define SPI_MEM_S_DLL_DB_CNT_CLR_M (SPI_MEM_S_DLL_DB_CNT_CLR_V << SPI_MEM_S_DLL_DB_CNT_CLR_S) +#define SPI_MEM_S_DLL_DB_CNT_CLR_V 0x00000001U +#define SPI_MEM_S_DLL_DB_CNT_CLR_S 12 +/** SPI_MEM_S_DLL_DIN_DLY_SEL : R/W; bitpos: [13]; default: 0; + * Configures the din channel. 1: Use delayed data. 0: Do not use delayed data. + */ +#define SPI_MEM_S_DLL_DIN_DLY_SEL (BIT(13)) +#define SPI_MEM_S_DLL_DIN_DLY_SEL_M (SPI_MEM_S_DLL_DIN_DLY_SEL_V << SPI_MEM_S_DLL_DIN_DLY_SEL_S) +#define SPI_MEM_S_DLL_DIN_DLY_SEL_V 0x00000001U +#define SPI_MEM_S_DLL_DIN_DLY_SEL_S 13 + +/** SPI_MEM_S_DLL_DB_ST0_REG register + * MSPI DLL debug status0 register + */ +#define SPI_MEM_S_DLL_DB_ST0_REG (DR_REG_PSRAM_MSPI0_BASE + 0xe0) +/** SPI_MEM_S_DB_FIFO_CNT_H : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[63:32] + */ +#define SPI_MEM_S_DB_FIFO_CNT_H 0xFFFFFFFFU +#define SPI_MEM_S_DB_FIFO_CNT_H_M (SPI_MEM_S_DB_FIFO_CNT_H_V << SPI_MEM_S_DB_FIFO_CNT_H_S) +#define SPI_MEM_S_DB_FIFO_CNT_H_V 0xFFFFFFFFU +#define SPI_MEM_S_DB_FIFO_CNT_H_S 0 + +/** SPI_MEM_S_DLL_DB_ST1_REG register + * MSPI DLL debug status1 register + */ +#define SPI_MEM_S_DLL_DB_ST1_REG (DR_REG_PSRAM_MSPI0_BASE + 0xe4) +/** SPI_MEM_S_DB_FIFO_CNT_L : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[31:0] + */ +#define SPI_MEM_S_DB_FIFO_CNT_L 0xFFFFFFFFU +#define SPI_MEM_S_DB_FIFO_CNT_L_M (SPI_MEM_S_DB_FIFO_CNT_L_V << SPI_MEM_S_DB_FIFO_CNT_L_S) +#define SPI_MEM_S_DB_FIFO_CNT_L_V 0xFFFFFFFFU +#define SPI_MEM_S_DB_FIFO_CNT_L_S 0 + /** SPI_MEM_S_FMEM_PMS0_ATTR_REG register * MSPI flash PMS section $n attribute register */ #define SPI_MEM_S_FMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x100) /** SPI_MEM_S_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS0_RD_ATTR (BIT(0)) #define SPI_MEM_S_FMEM_PMS0_RD_ATTR_M (SPI_MEM_S_FMEM_PMS0_RD_ATTR_V << SPI_MEM_S_FMEM_PMS0_RD_ATTR_S) #define SPI_MEM_S_FMEM_PMS0_RD_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS0_RD_ATTR_S 0 /** SPI_MEM_S_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 0 write accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS0_WR_ATTR (BIT(1)) #define SPI_MEM_S_FMEM_PMS0_WR_ATTR_M (SPI_MEM_S_FMEM_PMS0_WR_ATTR_V << SPI_MEM_S_FMEM_PMS0_WR_ATTR_S) #define SPI_MEM_S_FMEM_PMS0_WR_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS0_WR_ATTR_S 1 /** SPI_MEM_S_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash - * PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_FMEM_PMS$n_SIZE_REG. + * SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 0 is configured by registers SPI_MEM_S_FMEM_PMS0_ADDR_REG and + * SPI_MEM_S_FMEM_PMS0_SIZE_REG. */ #define SPI_MEM_S_FMEM_PMS0_ECC (BIT(2)) #define SPI_MEM_S_FMEM_PMS0_ECC_M (SPI_MEM_S_FMEM_PMS0_ECC_V << SPI_MEM_S_FMEM_PMS0_ECC_S) #define SPI_MEM_S_FMEM_PMS0_ECC_V 0x00000001U #define SPI_MEM_S_FMEM_PMS0_ECC_S 2 +/** SPI_MEM_S_FMEM_PMS0_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_RD_ATTR_M (SPI_MEM_S_FMEM_PMS0_NONSECURE_RD_ATTR_V << SPI_MEM_S_FMEM_PMS0_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_FMEM_PMS0_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_WR_ATTR_M (SPI_MEM_S_FMEM_PMS0_NONSECURE_WR_ATTR_V << SPI_MEM_S_FMEM_PMS0_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_FMEM_PMS0_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 0 is configured by registers SPI_MEM_S_FMEM_PMS0_ADDR_REG and + * SPI_MEM_S_FMEM_PMS0_SIZE_REG. + */ +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_ECC_M (SPI_MEM_S_FMEM_PMS0_NONSECURE_ECC_V << SPI_MEM_S_FMEM_PMS0_NONSECURE_ECC_S) +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS0_NONSECURE_ECC_S 5 /** SPI_MEM_S_FMEM_PMS1_ATTR_REG register - * SPI1 flash PMS section $n attribute register + * SPI1 flash PMS section 1 attribute register */ #define SPI_MEM_S_FMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x104) /** SPI_MEM_S_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 1 read accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS1_RD_ATTR (BIT(0)) #define SPI_MEM_S_FMEM_PMS1_RD_ATTR_M (SPI_MEM_S_FMEM_PMS1_RD_ATTR_V << SPI_MEM_S_FMEM_PMS1_RD_ATTR_S) #define SPI_MEM_S_FMEM_PMS1_RD_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS1_RD_ATTR_S 0 /** SPI_MEM_S_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 1 write accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS1_WR_ATTR (BIT(1)) #define SPI_MEM_S_FMEM_PMS1_WR_ATTR_M (SPI_MEM_S_FMEM_PMS1_WR_ATTR_V << SPI_MEM_S_FMEM_PMS1_WR_ATTR_S) #define SPI_MEM_S_FMEM_PMS1_WR_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS1_WR_ATTR_S 1 /** SPI_MEM_S_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash - * PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_FMEM_PMS$n_SIZE_REG. + * SPI1 flash PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 1 is configured by registers SPI_MEM_S_FMEM_PMS1_ADDR_REG and + * SPI_MEM_S_FMEM_PMS1_SIZE_REG. */ #define SPI_MEM_S_FMEM_PMS1_ECC (BIT(2)) #define SPI_MEM_S_FMEM_PMS1_ECC_M (SPI_MEM_S_FMEM_PMS1_ECC_V << SPI_MEM_S_FMEM_PMS1_ECC_S) #define SPI_MEM_S_FMEM_PMS1_ECC_V 0x00000001U #define SPI_MEM_S_FMEM_PMS1_ECC_S 2 +/** SPI_MEM_S_FMEM_PMS1_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_RD_ATTR_M (SPI_MEM_S_FMEM_PMS1_NONSECURE_RD_ATTR_V << SPI_MEM_S_FMEM_PMS1_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_FMEM_PMS1_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_WR_ATTR_M (SPI_MEM_S_FMEM_PMS1_NONSECURE_WR_ATTR_V << SPI_MEM_S_FMEM_PMS1_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_FMEM_PMS1_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 1 is configured by registers SPI_MEM_S_FMEM_PMS1_ADDR_REG and + * SPI_MEM_S_FMEM_PMS1_SIZE_REG. + */ +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_ECC_M (SPI_MEM_S_FMEM_PMS1_NONSECURE_ECC_V << SPI_MEM_S_FMEM_PMS1_NONSECURE_ECC_S) +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS1_NONSECURE_ECC_S 5 /** SPI_MEM_S_FMEM_PMS2_ATTR_REG register - * SPI1 flash PMS section $n attribute register + * SPI1 flash PMS section 2 attribute register */ #define SPI_MEM_S_FMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x108) /** SPI_MEM_S_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 2 read accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS2_RD_ATTR (BIT(0)) #define SPI_MEM_S_FMEM_PMS2_RD_ATTR_M (SPI_MEM_S_FMEM_PMS2_RD_ATTR_V << SPI_MEM_S_FMEM_PMS2_RD_ATTR_S) #define SPI_MEM_S_FMEM_PMS2_RD_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS2_RD_ATTR_S 0 /** SPI_MEM_S_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 2 write accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS2_WR_ATTR (BIT(1)) #define SPI_MEM_S_FMEM_PMS2_WR_ATTR_M (SPI_MEM_S_FMEM_PMS2_WR_ATTR_V << SPI_MEM_S_FMEM_PMS2_WR_ATTR_S) #define SPI_MEM_S_FMEM_PMS2_WR_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS2_WR_ATTR_S 1 /** SPI_MEM_S_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash - * PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_FMEM_PMS$n_SIZE_REG. + * SPI1 flash PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 2 is configured by registers SPI_MEM_S_FMEM_PMS2_ADDR_REG and + * SPI_MEM_S_FMEM_PMS2_SIZE_REG. */ #define SPI_MEM_S_FMEM_PMS2_ECC (BIT(2)) #define SPI_MEM_S_FMEM_PMS2_ECC_M (SPI_MEM_S_FMEM_PMS2_ECC_V << SPI_MEM_S_FMEM_PMS2_ECC_S) #define SPI_MEM_S_FMEM_PMS2_ECC_V 0x00000001U #define SPI_MEM_S_FMEM_PMS2_ECC_S 2 +/** SPI_MEM_S_FMEM_PMS2_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_RD_ATTR_M (SPI_MEM_S_FMEM_PMS2_NONSECURE_RD_ATTR_V << SPI_MEM_S_FMEM_PMS2_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_FMEM_PMS2_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_WR_ATTR_M (SPI_MEM_S_FMEM_PMS2_NONSECURE_WR_ATTR_V << SPI_MEM_S_FMEM_PMS2_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_FMEM_PMS2_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 2 is configured by registers SPI_MEM_S_FMEM_PMS2_ADDR_REG and + * SPI_MEM_S_FMEM_PMS2_SIZE_REG. + */ +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_ECC_M (SPI_MEM_S_FMEM_PMS2_NONSECURE_ECC_V << SPI_MEM_S_FMEM_PMS2_NONSECURE_ECC_S) +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS2_NONSECURE_ECC_S 5 /** SPI_MEM_S_FMEM_PMS3_ATTR_REG register - * SPI1 flash PMS section $n attribute register + * SPI1 flash PMS section 3 attribute register */ #define SPI_MEM_S_FMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x10c) /** SPI_MEM_S_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 3 read accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS3_RD_ATTR (BIT(0)) #define SPI_MEM_S_FMEM_PMS3_RD_ATTR_M (SPI_MEM_S_FMEM_PMS3_RD_ATTR_V << SPI_MEM_S_FMEM_PMS3_RD_ATTR_S) #define SPI_MEM_S_FMEM_PMS3_RD_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS3_RD_ATTR_S 0 /** SPI_MEM_S_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 flash PMS section 3 write accessible. 0: Not allowed. */ #define SPI_MEM_S_FMEM_PMS3_WR_ATTR (BIT(1)) #define SPI_MEM_S_FMEM_PMS3_WR_ATTR_M (SPI_MEM_S_FMEM_PMS3_WR_ATTR_V << SPI_MEM_S_FMEM_PMS3_WR_ATTR_S) #define SPI_MEM_S_FMEM_PMS3_WR_ATTR_V 0x00000001U #define SPI_MEM_S_FMEM_PMS3_WR_ATTR_S 1 /** SPI_MEM_S_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash - * PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_FMEM_PMS$n_SIZE_REG. + * SPI1 flash PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 3 is configured by registers SPI_MEM_S_FMEM_PMS3_ADDR_REG and + * SPI_MEM_S_FMEM_PMS3_SIZE_REG. */ #define SPI_MEM_S_FMEM_PMS3_ECC (BIT(2)) #define SPI_MEM_S_FMEM_PMS3_ECC_M (SPI_MEM_S_FMEM_PMS3_ECC_V << SPI_MEM_S_FMEM_PMS3_ECC_S) #define SPI_MEM_S_FMEM_PMS3_ECC_V 0x00000001U #define SPI_MEM_S_FMEM_PMS3_ECC_S 2 +/** SPI_MEM_S_FMEM_PMS3_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_RD_ATTR_M (SPI_MEM_S_FMEM_PMS3_NONSECURE_RD_ATTR_V << SPI_MEM_S_FMEM_PMS3_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_FMEM_PMS3_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_WR_ATTR_M (SPI_MEM_S_FMEM_PMS3_NONSECURE_WR_ATTR_V << SPI_MEM_S_FMEM_PMS3_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_FMEM_PMS3_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 3 is configured by registers SPI_MEM_S_FMEM_PMS3_ADDR_REG and + * SPI_MEM_S_FMEM_PMS3_SIZE_REG. + */ +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_ECC_M (SPI_MEM_S_FMEM_PMS3_NONSECURE_ECC_V << SPI_MEM_S_FMEM_PMS3_NONSECURE_ECC_S) +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_FMEM_PMS3_NONSECURE_ECC_S 5 /** SPI_MEM_S_FMEM_PMS0_ADDR_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 0 start address register */ #define SPI_MEM_S_FMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x110) /** SPI_MEM_S_FMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; - * SPI1 flash PMS section $n start address value + * SPI1 flash PMS section 0 start address value */ #define SPI_MEM_S_FMEM_PMS0_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_FMEM_PMS0_ADDR_S_M (SPI_MEM_S_FMEM_PMS0_ADDR_S_V << SPI_MEM_S_FMEM_PMS0_ADDR_S_S) @@ -1689,11 +2011,11 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS0_ADDR_S_S 0 /** SPI_MEM_S_FMEM_PMS1_ADDR_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 1 start address register */ #define SPI_MEM_S_FMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x114) -/** SPI_MEM_S_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 16777215; - * SPI1 flash PMS section $n start address value +/** SPI_MEM_S_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 1 start address value */ #define SPI_MEM_S_FMEM_PMS1_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_FMEM_PMS1_ADDR_S_M (SPI_MEM_S_FMEM_PMS1_ADDR_S_V << SPI_MEM_S_FMEM_PMS1_ADDR_S_S) @@ -1701,11 +2023,11 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS1_ADDR_S_S 0 /** SPI_MEM_S_FMEM_PMS2_ADDR_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 2 start address register */ #define SPI_MEM_S_FMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x118) -/** SPI_MEM_S_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 33554431; - * SPI1 flash PMS section $n start address value +/** SPI_MEM_S_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 2 start address value */ #define SPI_MEM_S_FMEM_PMS2_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_FMEM_PMS2_ADDR_S_M (SPI_MEM_S_FMEM_PMS2_ADDR_S_V << SPI_MEM_S_FMEM_PMS2_ADDR_S_S) @@ -1713,11 +2035,11 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS2_ADDR_S_S 0 /** SPI_MEM_S_FMEM_PMS3_ADDR_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 3 start address register */ #define SPI_MEM_S_FMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x11c) -/** SPI_MEM_S_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 50331647; - * SPI1 flash PMS section $n start address value +/** SPI_MEM_S_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 3 start address value */ #define SPI_MEM_S_FMEM_PMS3_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_FMEM_PMS3_ADDR_S_M (SPI_MEM_S_FMEM_PMS3_ADDR_S_V << SPI_MEM_S_FMEM_PMS3_ADDR_S_S) @@ -1725,12 +2047,12 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS3_ADDR_S_S 0 /** SPI_MEM_S_FMEM_PMS0_SIZE_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 0 start address register */ #define SPI_MEM_S_FMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x120) /** SPI_MEM_S_FMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, - * SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) + * SPI1 flash PMS section 0 address region is (SPI_MEM_S_FMEM_PMS0_ADDR_S, + * SPI_MEM_S_FMEM_PMS0_ADDR_S + SPI_MEM_S_FMEM_PMS0_SIZE) */ #define SPI_MEM_S_FMEM_PMS0_SIZE 0x00007FFFU #define SPI_MEM_S_FMEM_PMS0_SIZE_M (SPI_MEM_S_FMEM_PMS0_SIZE_V << SPI_MEM_S_FMEM_PMS0_SIZE_S) @@ -1738,12 +2060,12 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS0_SIZE_S 0 /** SPI_MEM_S_FMEM_PMS1_SIZE_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 1 start address register */ #define SPI_MEM_S_FMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x124) /** SPI_MEM_S_FMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, - * SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) + * SPI1 flash PMS section 1 address region is (SPI_MEM_S_FMEM_PMS1_ADDR_S, + * SPI_MEM_S_FMEM_PMS1_ADDR_S + SPI_MEM_S_FMEM_PMS1_SIZE) */ #define SPI_MEM_S_FMEM_PMS1_SIZE 0x00007FFFU #define SPI_MEM_S_FMEM_PMS1_SIZE_M (SPI_MEM_S_FMEM_PMS1_SIZE_V << SPI_MEM_S_FMEM_PMS1_SIZE_S) @@ -1751,12 +2073,12 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS1_SIZE_S 0 /** SPI_MEM_S_FMEM_PMS2_SIZE_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 2 start address register */ #define SPI_MEM_S_FMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x128) /** SPI_MEM_S_FMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, - * SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) + * SPI1 flash PMS section 2 address region is (SPI_MEM_S_FMEM_PMS2_ADDR_S, + * SPI_MEM_S_FMEM_PMS2_ADDR_S + SPI_MEM_S_FMEM_PMS2_SIZE) */ #define SPI_MEM_S_FMEM_PMS2_SIZE 0x00007FFFU #define SPI_MEM_S_FMEM_PMS2_SIZE_M (SPI_MEM_S_FMEM_PMS2_SIZE_V << SPI_MEM_S_FMEM_PMS2_SIZE_S) @@ -1764,12 +2086,12 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS2_SIZE_S 0 /** SPI_MEM_S_FMEM_PMS3_SIZE_REG register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section 3 start address register */ #define SPI_MEM_S_FMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x12c) /** SPI_MEM_S_FMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, - * SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) + * SPI1 flash PMS section 3 address region is (SPI_MEM_S_FMEM_PMS3_ADDR_S, + * SPI_MEM_S_FMEM_PMS3_ADDR_S + SPI_MEM_S_FMEM_PMS3_SIZE) */ #define SPI_MEM_S_FMEM_PMS3_SIZE 0x00007FFFU #define SPI_MEM_S_FMEM_PMS3_SIZE_M (SPI_MEM_S_FMEM_PMS3_SIZE_V << SPI_MEM_S_FMEM_PMS3_SIZE_S) @@ -1777,123 +2099,215 @@ extern "C" { #define SPI_MEM_S_FMEM_PMS3_SIZE_S 0 /** SPI_MEM_S_SMEM_PMS0_ATTR_REG register - * SPI1 flash PMS section $n start address register + * SPI1 external RAM PMS section 0 attribute register */ #define SPI_MEM_S_SMEM_PMS0_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x130) /** SPI_MEM_S_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS0_RD_ATTR (BIT(0)) #define SPI_MEM_S_SMEM_PMS0_RD_ATTR_M (SPI_MEM_S_SMEM_PMS0_RD_ATTR_V << SPI_MEM_S_SMEM_PMS0_RD_ATTR_S) #define SPI_MEM_S_SMEM_PMS0_RD_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS0_RD_ATTR_S 0 /** SPI_MEM_S_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 0 write accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS0_WR_ATTR (BIT(1)) #define SPI_MEM_S_SMEM_PMS0_WR_ATTR_M (SPI_MEM_S_SMEM_PMS0_WR_ATTR_V << SPI_MEM_S_SMEM_PMS0_WR_ATTR_S) #define SPI_MEM_S_SMEM_PMS0_WR_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS0_WR_ATTR_S 1 /** SPI_MEM_S_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_SMEM_PMS$n_SIZE_REG. + * SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 0 is configured by registers SPI_MEM_S_SMEM_PMS0_ADDR_REG + * and SPI_MEM_S_SMEM_PMS0_SIZE_REG. */ #define SPI_MEM_S_SMEM_PMS0_ECC (BIT(2)) #define SPI_MEM_S_SMEM_PMS0_ECC_M (SPI_MEM_S_SMEM_PMS0_ECC_V << SPI_MEM_S_SMEM_PMS0_ECC_S) #define SPI_MEM_S_SMEM_PMS0_ECC_V 0x00000001U #define SPI_MEM_S_SMEM_PMS0_ECC_S 2 +/** SPI_MEM_S_SMEM_PMS0_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_RD_ATTR_M (SPI_MEM_S_SMEM_PMS0_NONSECURE_RD_ATTR_V << SPI_MEM_S_SMEM_PMS0_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_SMEM_PMS0_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_WR_ATTR_M (SPI_MEM_S_SMEM_PMS0_NONSECURE_WR_ATTR_V << SPI_MEM_S_SMEM_PMS0_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_SMEM_PMS0_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 0 is configured by registers + * SPI_MEM_S_SMEM_PMS0_ADDR_REG and SPI_MEM_S_SMEM_PMS0_SIZE_REG. + */ +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_ECC_M (SPI_MEM_S_SMEM_PMS0_NONSECURE_ECC_V << SPI_MEM_S_SMEM_PMS0_NONSECURE_ECC_S) +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS0_NONSECURE_ECC_S 5 /** SPI_MEM_S_SMEM_PMS1_ATTR_REG register - * SPI1 external RAM PMS section $n attribute register + * SPI1 external RAM PMS section 1 attribute register */ #define SPI_MEM_S_SMEM_PMS1_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x134) /** SPI_MEM_S_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS1_RD_ATTR (BIT(0)) #define SPI_MEM_S_SMEM_PMS1_RD_ATTR_M (SPI_MEM_S_SMEM_PMS1_RD_ATTR_V << SPI_MEM_S_SMEM_PMS1_RD_ATTR_S) #define SPI_MEM_S_SMEM_PMS1_RD_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS1_RD_ATTR_S 0 /** SPI_MEM_S_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 1 write accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS1_WR_ATTR (BIT(1)) #define SPI_MEM_S_SMEM_PMS1_WR_ATTR_M (SPI_MEM_S_SMEM_PMS1_WR_ATTR_V << SPI_MEM_S_SMEM_PMS1_WR_ATTR_S) #define SPI_MEM_S_SMEM_PMS1_WR_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS1_WR_ATTR_S 1 /** SPI_MEM_S_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_SMEM_PMS$n_SIZE_REG. + * SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 1 is configured by registers SPI_MEM_S_SMEM_PMS1_ADDR_REG + * and SPI_MEM_S_SMEM_PMS1_SIZE_REG. */ #define SPI_MEM_S_SMEM_PMS1_ECC (BIT(2)) #define SPI_MEM_S_SMEM_PMS1_ECC_M (SPI_MEM_S_SMEM_PMS1_ECC_V << SPI_MEM_S_SMEM_PMS1_ECC_S) #define SPI_MEM_S_SMEM_PMS1_ECC_V 0x00000001U #define SPI_MEM_S_SMEM_PMS1_ECC_S 2 +/** SPI_MEM_S_SMEM_PMS1_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_RD_ATTR_M (SPI_MEM_S_SMEM_PMS1_NONSECURE_RD_ATTR_V << SPI_MEM_S_SMEM_PMS1_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_SMEM_PMS1_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_WR_ATTR_M (SPI_MEM_S_SMEM_PMS1_NONSECURE_WR_ATTR_V << SPI_MEM_S_SMEM_PMS1_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_SMEM_PMS1_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 1 is configured by registers + * SPI_MEM_S_SMEM_PMS1_ADDR_REG and SPI_MEM_S_SMEM_PMS1_SIZE_REG. + */ +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_ECC_M (SPI_MEM_S_SMEM_PMS1_NONSECURE_ECC_V << SPI_MEM_S_SMEM_PMS1_NONSECURE_ECC_S) +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS1_NONSECURE_ECC_S 5 /** SPI_MEM_S_SMEM_PMS2_ATTR_REG register - * SPI1 external RAM PMS section $n attribute register + * SPI1 external RAM PMS section 2 attribute register */ #define SPI_MEM_S_SMEM_PMS2_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x138) /** SPI_MEM_S_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS2_RD_ATTR (BIT(0)) #define SPI_MEM_S_SMEM_PMS2_RD_ATTR_M (SPI_MEM_S_SMEM_PMS2_RD_ATTR_V << SPI_MEM_S_SMEM_PMS2_RD_ATTR_S) #define SPI_MEM_S_SMEM_PMS2_RD_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS2_RD_ATTR_S 0 /** SPI_MEM_S_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 2 write accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS2_WR_ATTR (BIT(1)) #define SPI_MEM_S_SMEM_PMS2_WR_ATTR_M (SPI_MEM_S_SMEM_PMS2_WR_ATTR_V << SPI_MEM_S_SMEM_PMS2_WR_ATTR_S) #define SPI_MEM_S_SMEM_PMS2_WR_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS2_WR_ATTR_S 1 /** SPI_MEM_S_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_SMEM_PMS$n_SIZE_REG. + * SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 2 is configured by registers SPI_MEM_S_SMEM_PMS2_ADDR_REG + * and SPI_MEM_S_SMEM_PMS2_SIZE_REG. */ #define SPI_MEM_S_SMEM_PMS2_ECC (BIT(2)) #define SPI_MEM_S_SMEM_PMS2_ECC_M (SPI_MEM_S_SMEM_PMS2_ECC_V << SPI_MEM_S_SMEM_PMS2_ECC_S) #define SPI_MEM_S_SMEM_PMS2_ECC_V 0x00000001U #define SPI_MEM_S_SMEM_PMS2_ECC_S 2 +/** SPI_MEM_S_SMEM_PMS2_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_RD_ATTR_M (SPI_MEM_S_SMEM_PMS2_NONSECURE_RD_ATTR_V << SPI_MEM_S_SMEM_PMS2_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_SMEM_PMS2_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_WR_ATTR_M (SPI_MEM_S_SMEM_PMS2_NONSECURE_WR_ATTR_V << SPI_MEM_S_SMEM_PMS2_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_SMEM_PMS2_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 2 is configured by registers + * SPI_MEM_S_SMEM_PMS2_ADDR_REG and SPI_MEM_S_SMEM_PMS2_SIZE_REG. + */ +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_ECC_M (SPI_MEM_S_SMEM_PMS2_NONSECURE_ECC_V << SPI_MEM_S_SMEM_PMS2_NONSECURE_ECC_S) +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS2_NONSECURE_ECC_S 5 /** SPI_MEM_S_SMEM_PMS3_ATTR_REG register - * SPI1 external RAM PMS section $n attribute register + * SPI1 external RAM PMS section 3 attribute register */ #define SPI_MEM_S_SMEM_PMS3_ATTR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x13c) /** SPI_MEM_S_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS3_RD_ATTR (BIT(0)) #define SPI_MEM_S_SMEM_PMS3_RD_ATTR_M (SPI_MEM_S_SMEM_PMS3_RD_ATTR_V << SPI_MEM_S_SMEM_PMS3_RD_ATTR_S) #define SPI_MEM_S_SMEM_PMS3_RD_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS3_RD_ATTR_S 0 /** SPI_MEM_S_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed. + * 1: SPI1 external RAM PMS section 3 write accessible. 0: Not allowed. */ #define SPI_MEM_S_SMEM_PMS3_WR_ATTR (BIT(1)) #define SPI_MEM_S_SMEM_PMS3_WR_ATTR_M (SPI_MEM_S_SMEM_PMS3_WR_ATTR_V << SPI_MEM_S_SMEM_PMS3_WR_ATTR_S) #define SPI_MEM_S_SMEM_PMS3_WR_ATTR_V 0x00000001U #define SPI_MEM_S_SMEM_PMS3_WR_ATTR_S 1 /** SPI_MEM_S_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section $n is configured by registers SPI_MEM_S_SMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_SMEM_PMS$n_SIZE_REG. + * SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 3 is configured by registers SPI_MEM_S_SMEM_PMS3_ADDR_REG + * and SPI_MEM_S_SMEM_PMS3_SIZE_REG. */ #define SPI_MEM_S_SMEM_PMS3_ECC (BIT(2)) #define SPI_MEM_S_SMEM_PMS3_ECC_M (SPI_MEM_S_SMEM_PMS3_ECC_V << SPI_MEM_S_SMEM_PMS3_ECC_S) #define SPI_MEM_S_SMEM_PMS3_ECC_V 0x00000001U #define SPI_MEM_S_SMEM_PMS3_ECC_S 2 +/** SPI_MEM_S_SMEM_PMS3_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_RD_ATTR_M (SPI_MEM_S_SMEM_PMS3_NONSECURE_RD_ATTR_V << SPI_MEM_S_SMEM_PMS3_NONSECURE_RD_ATTR_S) +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_RD_ATTR_S 3 +/** SPI_MEM_S_SMEM_PMS3_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_WR_ATTR_M (SPI_MEM_S_SMEM_PMS3_NONSECURE_WR_ATTR_V << SPI_MEM_S_SMEM_PMS3_NONSECURE_WR_ATTR_S) +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_WR_ATTR_S 4 +/** SPI_MEM_S_SMEM_PMS3_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 3 is configured by registers + * SPI_MEM_S_SMEM_PMS3_ADDR_REG and SPI_MEM_S_SMEM_PMS3_SIZE_REG. + */ +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_ECC (BIT(5)) +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_ECC_M (SPI_MEM_S_SMEM_PMS3_NONSECURE_ECC_V << SPI_MEM_S_SMEM_PMS3_NONSECURE_ECC_S) +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_ECC_V 0x00000001U +#define SPI_MEM_S_SMEM_PMS3_NONSECURE_ECC_S 5 /** SPI_MEM_S_SMEM_PMS0_ADDR_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 0 start address register */ #define SPI_MEM_S_SMEM_PMS0_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x140) /** SPI_MEM_S_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; - * SPI1 external RAM PMS section $n start address value + * SPI1 external RAM PMS section 0 start address value */ #define SPI_MEM_S_SMEM_PMS0_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_SMEM_PMS0_ADDR_S_M (SPI_MEM_S_SMEM_PMS0_ADDR_S_V << SPI_MEM_S_SMEM_PMS0_ADDR_S_S) @@ -1901,11 +2315,11 @@ extern "C" { #define SPI_MEM_S_SMEM_PMS0_ADDR_S_S 0 /** SPI_MEM_S_SMEM_PMS1_ADDR_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 1 start address register */ #define SPI_MEM_S_SMEM_PMS1_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x144) -/** SPI_MEM_S_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 16777215; - * SPI1 external RAM PMS section $n start address value +/** SPI_MEM_S_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 1 start address value */ #define SPI_MEM_S_SMEM_PMS1_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_SMEM_PMS1_ADDR_S_M (SPI_MEM_S_SMEM_PMS1_ADDR_S_V << SPI_MEM_S_SMEM_PMS1_ADDR_S_S) @@ -1913,11 +2327,11 @@ extern "C" { #define SPI_MEM_S_SMEM_PMS1_ADDR_S_S 0 /** SPI_MEM_S_SMEM_PMS2_ADDR_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 2 start address register */ #define SPI_MEM_S_SMEM_PMS2_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x148) -/** SPI_MEM_S_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 33554431; - * SPI1 external RAM PMS section $n start address value +/** SPI_MEM_S_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 2 start address value */ #define SPI_MEM_S_SMEM_PMS2_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_SMEM_PMS2_ADDR_S_M (SPI_MEM_S_SMEM_PMS2_ADDR_S_V << SPI_MEM_S_SMEM_PMS2_ADDR_S_S) @@ -1925,11 +2339,11 @@ extern "C" { #define SPI_MEM_S_SMEM_PMS2_ADDR_S_S 0 /** SPI_MEM_S_SMEM_PMS3_ADDR_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 3 start address register */ #define SPI_MEM_S_SMEM_PMS3_ADDR_REG (DR_REG_PSRAM_MSPI0_BASE + 0x14c) -/** SPI_MEM_S_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 50331647; - * SPI1 external RAM PMS section $n start address value +/** SPI_MEM_S_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 3 start address value */ #define SPI_MEM_S_SMEM_PMS3_ADDR_S 0x07FFFFFFU #define SPI_MEM_S_SMEM_PMS3_ADDR_S_M (SPI_MEM_S_SMEM_PMS3_ADDR_S_V << SPI_MEM_S_SMEM_PMS3_ADDR_S_S) @@ -1937,12 +2351,12 @@ extern "C" { #define SPI_MEM_S_SMEM_PMS3_ADDR_S_S 0 /** SPI_MEM_S_SMEM_PMS0_SIZE_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 0 start address register */ #define SPI_MEM_S_SMEM_PMS0_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x150) /** SPI_MEM_S_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S, - * SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE) + * SPI1 external RAM PMS section 0 address region is (SPI_MEM_S_SMEM_PMS0_ADDR_S, + * SPI_MEM_S_SMEM_PMS0_ADDR_S + SPI_MEM_S_SMEM_PMS0_SIZE) */ #define SPI_MEM_S_SMEM_PMS0_SIZE 0x00007FFFU #define SPI_MEM_S_SMEM_PMS0_SIZE_M (SPI_MEM_S_SMEM_PMS0_SIZE_V << SPI_MEM_S_SMEM_PMS0_SIZE_S) @@ -1950,12 +2364,12 @@ extern "C" { #define SPI_MEM_S_SMEM_PMS0_SIZE_S 0 /** SPI_MEM_S_SMEM_PMS1_SIZE_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 1 start address register */ #define SPI_MEM_S_SMEM_PMS1_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x154) /** SPI_MEM_S_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S, - * SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE) + * SPI1 external RAM PMS section 1 address region is (SPI_MEM_S_SMEM_PMS1_ADDR_S, + * SPI_MEM_S_SMEM_PMS1_ADDR_S + SPI_MEM_S_SMEM_PMS1_SIZE) */ #define SPI_MEM_S_SMEM_PMS1_SIZE 0x00007FFFU #define SPI_MEM_S_SMEM_PMS1_SIZE_M (SPI_MEM_S_SMEM_PMS1_SIZE_V << SPI_MEM_S_SMEM_PMS1_SIZE_S) @@ -1963,12 +2377,12 @@ extern "C" { #define SPI_MEM_S_SMEM_PMS1_SIZE_S 0 /** SPI_MEM_S_SMEM_PMS2_SIZE_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 2 start address register */ #define SPI_MEM_S_SMEM_PMS2_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x158) /** SPI_MEM_S_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S, - * SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE) + * SPI1 external RAM PMS section 2 address region is (SPI_MEM_S_SMEM_PMS2_ADDR_S, + * SPI_MEM_S_SMEM_PMS2_ADDR_S + SPI_MEM_S_SMEM_PMS2_SIZE) */ #define SPI_MEM_S_SMEM_PMS2_SIZE 0x00007FFFU #define SPI_MEM_S_SMEM_PMS2_SIZE_M (SPI_MEM_S_SMEM_PMS2_SIZE_V << SPI_MEM_S_SMEM_PMS2_SIZE_S) @@ -1976,12 +2390,12 @@ extern "C" { #define SPI_MEM_S_SMEM_PMS2_SIZE_S 0 /** SPI_MEM_S_SMEM_PMS3_SIZE_REG register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section 3 start address register */ #define SPI_MEM_S_SMEM_PMS3_SIZE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x15c) /** SPI_MEM_S_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; - * SPI1 external RAM PMS section $n address region is (SPI_MEM_S_SMEM_PMS$n_ADDR_S, - * SPI_MEM_S_SMEM_PMS$n_ADDR_S + SPI_MEM_S_SMEM_PMS$n_SIZE) + * SPI1 external RAM PMS section 3 address region is (SPI_MEM_S_SMEM_PMS3_ADDR_S, + * SPI_MEM_S_SMEM_PMS3_ADDR_S + SPI_MEM_S_SMEM_PMS3_SIZE) */ #define SPI_MEM_S_SMEM_PMS3_SIZE 0x00007FFFU #define SPI_MEM_S_SMEM_PMS3_SIZE_M (SPI_MEM_S_SMEM_PMS3_SIZE_V << SPI_MEM_S_SMEM_PMS3_SIZE_S) @@ -2053,7 +2467,8 @@ extern "C" { #define SPI_MEM_S_ECC_ERR_CNT_V 0x0000003FU #define SPI_MEM_S_ECC_ERR_CNT_S 5 /** SPI_MEM_S_FMEM_ECC_ERR_INT_NUM : R/W; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_S_ECC_ERR_INT interrupt. + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_S_ECC_ERR_INT + * interrupt. */ #define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM 0x0000003FU #define SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_M (SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_V << SPI_MEM_S_FMEM_ECC_ERR_INT_NUM_S) @@ -2940,8 +3355,8 @@ extern "C" { #define SPI_MEM_S_SMEM_CS_HOLD_TIME_V 0x0000001FU #define SPI_MEM_S_SMEM_CS_HOLD_TIME_S 7 /** SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME : R/W; bitpos: [14:12]; default: 3; - * SPI_MEM_S_SMEM_CS_HOLD_TIME + SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold - * cycles in ECC mode when accessed external RAM. + * SPI_MEM_S_SMEM_CS_HOLD_TIME + SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 + * CS hold cycles in ECC mode when accessed external RAM. */ #define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME 0x00000007U #define SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_M (SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_V << SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME_S) @@ -2965,8 +3380,8 @@ extern "C" { #define SPI_MEM_S_SMEM_ECC_16TO18_BYTE_EN_S 16 /** SPI_MEM_S_SMEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_MEM_S_SMEM_CS_HOLD_DELAY[5:0] + 1) - * MSPI core clock cycles. + * transfer when accesses to external RAM. tSHSL is (SPI_MEM_S_SMEM_CS_HOLD_DELAY[5:0] + * + 1) MSPI core clock cycles. */ #define SPI_MEM_S_SMEM_CS_HOLD_DELAY 0x0000003FU #define SPI_MEM_S_SMEM_CS_HOLD_DELAY_M (SPI_MEM_S_SMEM_CS_HOLD_DELAY_V << SPI_MEM_S_SMEM_CS_HOLD_DELAY_S) @@ -3305,14 +3720,14 @@ extern "C" { * Manual Encryption physical address register */ #define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_REG (DR_REG_PSRAM_MSPI0_BASE + 0x348) -/** SPI_MEM_S_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0; +/** SPI_MEM_S_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0; * This bits stores the physical-address parameter which will be used in manual * encryption calculation. This value should aligned with byte number decided by * line-size parameter. */ -#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS 0x03FFFFFFU +#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS 0x3FFFFFFFU #define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_M (SPI_MEM_S_XTS_PHYSICAL_ADDRESS_V << SPI_MEM_S_XTS_PHYSICAL_ADDRESS_S) -#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_V 0x03FFFFFFU +#define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFFFU #define SPI_MEM_S_XTS_PHYSICAL_ADDRESS_S 0 /** SPI_MEM_S_XTS_TRIGGER_REG register @@ -3376,7 +3791,7 @@ extern "C" { * Manual Encryption version register */ #define SPI_MEM_S_XTS_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x35c) -/** SPI_MEM_S_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176; +/** SPI_MEM_S_XTS_DATE : R/W; bitpos: [29:0]; default: 539035911; * This bits stores the last modified-time of manual encryption feature. */ #define SPI_MEM_S_XTS_DATE 0x3FFFFFFFU @@ -3434,6 +3849,13 @@ extern "C" { #define SPI_MEM_S_MMU_MEM_FORCE_PU_M (SPI_MEM_S_MMU_MEM_FORCE_PU_V << SPI_MEM_S_MMU_MEM_FORCE_PU_S) #define SPI_MEM_S_MMU_MEM_FORCE_PU_V 0x00000001U #define SPI_MEM_S_MMU_MEM_FORCE_PU_S 2 +/** SPI_MEM_S_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; + * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + */ +#define SPI_MEM_S_MMU_PAGE_SIZE 0x00000003U +#define SPI_MEM_S_MMU_PAGE_SIZE_M (SPI_MEM_S_MMU_PAGE_SIZE_V << SPI_MEM_S_MMU_PAGE_SIZE_S) +#define SPI_MEM_S_MMU_PAGE_SIZE_V 0x00000003U +#define SPI_MEM_S_MMU_PAGE_SIZE_S 3 /** SPI_MEM_S_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; * MMU PSRAM aux control register */ @@ -3443,6 +3865,7 @@ extern "C" { #define SPI_MEM_S_AUX_CTRL_S 16 /** SPI_MEM_S_RDN_ENA : R/W; bitpos: [30]; default: 0; * ECO register enable bit + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_RDN_ENA (BIT(30)) #define SPI_MEM_S_RDN_ENA_M (SPI_MEM_S_RDN_ENA_V << SPI_MEM_S_RDN_ENA_S) @@ -3450,6 +3873,7 @@ extern "C" { #define SPI_MEM_S_RDN_ENA_S 30 /** SPI_MEM_S_RDN_RESULT : RO; bitpos: [31]; default: 0; * MSPI module clock domain and AXI clock domain ECO register result register + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_RDN_RESULT (BIT(31)) #define SPI_MEM_S_RDN_RESULT_M (SPI_MEM_S_RDN_RESULT_V << SPI_MEM_S_RDN_RESULT_S) @@ -3487,12 +3911,51 @@ extern "C" { #define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_V 0x00000001U #define SPI_MEM_S_CRYPT_DPA_SELECT_REGISTER_S 4 +/** SPI_MEM_S_XTS_PSEUDO_ROUND_CONF_REG register + * SPI memory cryption PSEUDO register + */ +#define SPI_MEM_S_XTS_PSEUDO_ROUND_CONF_REG (DR_REG_PSRAM_MSPI0_BASE + 0x38c) +/** SPI_MEM_S_MODE_PSEUDO : R/W; bitpos: [1:0]; default: 0; + * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo + * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. + * 2'b11: crypto with pseudo. + */ +#define SPI_MEM_S_MODE_PSEUDO 0x00000003U +#define SPI_MEM_S_MODE_PSEUDO_M (SPI_MEM_S_MODE_PSEUDO_V << SPI_MEM_S_MODE_PSEUDO_S) +#define SPI_MEM_S_MODE_PSEUDO_V 0x00000003U +#define SPI_MEM_S_MODE_PSEUDO_S 0 +/** SPI_MEM_S_PSEUDO_RNG_CNT : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be performed. + */ +#define SPI_MEM_S_PSEUDO_RNG_CNT 0x00000007U +#define SPI_MEM_S_PSEUDO_RNG_CNT_M (SPI_MEM_S_PSEUDO_RNG_CNT_V << SPI_MEM_S_PSEUDO_RNG_CNT_S) +#define SPI_MEM_S_PSEUDO_RNG_CNT_V 0x00000007U +#define SPI_MEM_S_PSEUDO_RNG_CNT_S 2 +/** SPI_MEM_S_PSEUDO_BASE : R/W; bitpos: [8:5]; default: 2; + * xts aes peseudo function base round that must be performed. + */ +#define SPI_MEM_S_PSEUDO_BASE 0x0000000FU +#define SPI_MEM_S_PSEUDO_BASE_M (SPI_MEM_S_PSEUDO_BASE_V << SPI_MEM_S_PSEUDO_BASE_S) +#define SPI_MEM_S_PSEUDO_BASE_V 0x0000000FU +#define SPI_MEM_S_PSEUDO_BASE_S 5 +/** SPI_MEM_S_PSEUDO_INC : R/W; bitpos: [10:9]; default: 2; + * xts aes peseudo function increment round that will be performed randomly between 0 & + * 2**(inc+1). + */ +#define SPI_MEM_S_PSEUDO_INC 0x00000003U +#define SPI_MEM_S_PSEUDO_INC_M (SPI_MEM_S_PSEUDO_INC_V << SPI_MEM_S_PSEUDO_INC_S) +#define SPI_MEM_S_PSEUDO_INC_V 0x00000003U +#define SPI_MEM_S_PSEUDO_INC_S 9 + /** SPI_MEM_S_REGISTERRND_ECO_HIGH_REG register * MSPI ECO high register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_S_REGISTERRND_ECO_HIGH_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3f0) /** SPI_MEM_S_REGISTERRND_ECO_HIGH : R/W; bitpos: [31:0]; default: 892; * ECO high register + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_REGISTERRND_ECO_HIGH 0xFFFFFFFFU #define SPI_MEM_S_REGISTERRND_ECO_HIGH_M (SPI_MEM_S_REGISTERRND_ECO_HIGH_V << SPI_MEM_S_REGISTERRND_ECO_HIGH_S) @@ -3501,10 +3964,13 @@ extern "C" { /** SPI_MEM_S_REGISTERRND_ECO_LOW_REG register * MSPI ECO low register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_S_REGISTERRND_ECO_LOW_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3f4) /** SPI_MEM_S_REGISTERRND_ECO_LOW : R/W; bitpos: [31:0]; default: 892; * ECO low register + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_S_REGISTERRND_ECO_LOW 0xFFFFFFFFU #define SPI_MEM_S_REGISTERRND_ECO_LOW_M (SPI_MEM_S_REGISTERRND_ECO_LOW_V << SPI_MEM_S_REGISTERRND_ECO_LOW_S) @@ -3515,7 +3981,7 @@ extern "C" { * SPI0 version control register */ #define SPI_MEM_S_DATE_REG (DR_REG_PSRAM_MSPI0_BASE + 0x3fc) -/** SPI_MEM_S_DATE : R/W; bitpos: [27:0]; default: 36712704; +/** SPI_MEM_S_DATE : R/W; bitpos: [27:0]; default: 38801984; * SPI0 register version. */ #define SPI_MEM_S_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_struct.h index 05386290ac7f..235cd5d7aa5c 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_mem_s_struct.h @@ -180,11 +180,7 @@ typedef union { * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. */ uint32_t aw_size0_1_support_en:1; - /** axi_rdata_back_fast : R/W; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ - uint32_t axi_rdata_back_fast:1; + uint32_t reserved_23:1; /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded @@ -200,9 +196,9 @@ typedef union { */ uint32_t mem_aw_splice_en:1; /** mem_ram0_en : HRO; bitpos: [27]; default: 1; - * When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When SPI_MEM_S_DUAL_RAM_EN is 0 and SPI_MEM_S_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When SPI_MEM_S_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * When spi_mem_s_DUAL_RAM_EN is 0 and spi_mem_s_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When spi_mem_s_DUAL_RAM_EN is 0 and spi_mem_s_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When spi_mem_s_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be * accessed at the same time. */ uint32_t mem_ram0_en:1; @@ -287,12 +283,24 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:7; - /** mem_fsub_pin : R/W; bitpos: [7]; default: 0; + uint32_t reserved_0:4; + /** mem_dq_oe_ctrl : R/W; bitpos: [4]; default: 1; + * For SPI BUS IO, APB ctrl IO DQ OE func.1: enable 0: disable. + */ + uint32_t mem_dq_oe_ctrl:1; + /** mem_ck_oe_ctrl : R/W; bitpos: [5]; default: 1; + * For SPI BUS IO, APB ctrl IO CK OE func.1: enable 0: disable. + */ + uint32_t mem_ck_oe_ctrl:1; + /** mem_cs_oe_ctrl : R/W; bitpos: [6]; default: 1; + * For SPI BUS IO, APB ctrl IO CS OE func.1: enable 0: disable. + */ + uint32_t mem_cs_oe_ctrl:1; + /** mem_fsub_pin : HRO; bitpos: [7]; default: 0; * For SPI0, flash is connected to SUBPINs. */ uint32_t mem_fsub_pin:1; - /** mem_ssub_pin : R/W; bitpos: [8]; default: 0; + /** mem_ssub_pin : HRO; bitpos: [8]; default: 0; * For SPI0, sram is connected to SUBPINs. */ uint32_t mem_ssub_pin:1; @@ -316,47 +324,81 @@ typedef union { struct { /** mem_axi_req_en : R/W; bitpos: [0]; default: 0; * For SPI0, AXI master access enable, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_axi_req_en:1; /** mem_cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_usr_addr_4byte:1; /** mem_cache_flash_usr_cmd : R/W; bitpos: [2]; default: 0; * For SPI0, cache read flash for user define command, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_flash_usr_cmd:1; /** mem_fdin_dual : R/W; bitpos: [3]; default: 0; * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the * same with spi_mem_s_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdin_dual:1; /** mem_fdout_dual : R/W; bitpos: [4]; default: 0; * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the * same with spi_mem_s_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdout_dual:1; /** mem_faddr_dual : R/W; bitpos: [5]; default: 0; * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is * the same with spi_mem_s_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_faddr_dual:1; /** mem_fdin_quad : R/W; bitpos: [6]; default: 0; * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the * same with spi_mem_s_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdin_quad:1; /** mem_fdout_quad : R/W; bitpos: [7]; default: 0; * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the * same with spi_mem_s_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdout_quad:1; /** mem_faddr_quad : R/W; bitpos: [8]; default: 0; * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_s_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_faddr_quad:1; - uint32_t reserved_9:21; + /** mem_arb_wei_en : R/W; bitpos: [9]; default: 0; + * To enable SPI0 arbiter weight func while AXI read/write access SPI0 1: enable 0: + * disable. + */ + uint32_t mem_arb_wei_en:1; + /** mem_arb_req0_pri : R/W; bitpos: [10]; default: 0; + * To set AXI read priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ + uint32_t mem_arb_req0_pri:1; + /** mem_arb_req1_pri : R/W; bitpos: [11]; default: 0; + * To set AXI write priority in SPI0 arbiter. The larger the value, the greater the + * priority. + */ + uint32_t mem_arb_req1_pri:1; + /** mem_arb_req0_wei : R/W; bitpos: [15:12]; default: 0; + * To set AXI read priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ + uint32_t mem_arb_req0_wei:4; + /** mem_arb_req1_wei : R/W; bitpos: [19:16]; default: 0; + * To set AXI write priority weight in SPI0 arbiter. While the priority are same, the + * larger the value, the greater the weight. + */ + uint32_t mem_arb_req1_wei:4; + uint32_t reserved_20:10; /** same_aw_ar_addr_chk_en : R/W; bitpos: [30]; default: 1; * Set this bit to check AXI read/write the same address region. */ @@ -462,16 +504,16 @@ typedef union { typedef union { struct { /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_s_clkcnt_N. + * In the master mode it must be equal to spi_mem_s_CLKCNT_N. */ uint32_t mem_clkcnt_l:8; /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_s_clkcnt_N+1)/2-1). + * In the master mode it must be floor((spi_mem_s_CLKCNT_N+1)/2-1). */ uint32_t mem_clkcnt_h:8; /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_s_clk. So spi_mem_s_clk frequency is - * system/(spi_mem_s_clkcnt_N+1) + * system/(spi_mem_s_CLKCNT_N+1) */ uint32_t mem_clkcnt_n:8; uint32_t reserved_24:7; @@ -490,22 +532,26 @@ typedef union { typedef union { struct { /** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to spi_mem_s_clkcnt_N. + * For SPI0 external RAM interface, it must be equal to spi_mem_s_SCLKCNT_N. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_l:8; /** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((spi_mem_s_clkcnt_N+1)/2-1). + * For SPI0 external RAM interface, it must be floor((spi_mem_s_SCLKCNT_N+1)/2-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_h:8; /** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3; * For SPI0 external RAM interface, it is the divider of spi_mem_s_clk. So spi_mem_s_clk - * frequency is system/(spi_mem_s_clkcnt_N+1) + * frequency is system/(spi_mem_s_SCLKCNT_N+1) + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_n:8; uint32_t reserved_24:7; /** mem_sclk_equ_sysclk : R/W; bitpos: [31]; default: 0; * For SPI0 external RAM interface, 1: spi_mem_s_clk is equal to system 0: spi_mem_s_clk * is divided from system clock. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclk_equ_sysclk:1; }; @@ -544,7 +590,7 @@ typedef union { uint32_t mem_cs_setup:1; uint32_t reserved_8:1; /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; - * The bit combined with SPI_MEM_S_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + * The bit combined with spi_mem_s_CK_IDLE_EDGE bit to control SPI clock mode 0~3. */ uint32_t mem_ck_out_edge:1; uint32_t reserved_10:16; @@ -611,6 +657,7 @@ typedef union { uint32_t reserved_0:16; /** mem_wb_mode : R/W; bitpos: [23:16]; default: 0; * Mode bits in the flash fast read mode it is combined with spi_mem_s_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_wb_mode:8; uint32_t reserved_24:8; @@ -628,52 +675,63 @@ typedef union { /** mem_cache_usr_saddr_4byte : R/W; bitpos: [0]; default: 0; * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: * enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_usr_saddr_4byte:1; /** mem_usr_sram_dio : R/W; bitpos: [1]; default: 0; * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_sram_dio:1; /** mem_usr_sram_qio : R/W; bitpos: [2]; default: 0; * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_sram_qio:1; /** mem_usr_wr_sram_dummy : R/W; bitpos: [3]; default: 0; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write * operations. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_wr_sram_dummy:1; /** mem_usr_rd_sram_dummy : R/W; bitpos: [4]; default: 1; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read * operations. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_rd_sram_dummy:1; /** mem_cache_sram_usr_rcmd : R/W; bitpos: [5]; default: 1; * For SPI0, In the external RAM mode cache read external RAM for user define command. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_rcmd:1; /** mem_sram_rdummy_cyclelen : R/W; bitpos: [11:6]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sram_rdummy_cyclelen:6; uint32_t reserved_12:2; /** mem_sram_addr_bitlen : R/W; bitpos: [19:14]; default: 23; * For SPI0, In the external RAM mode, it is the length in bits of address phase. The * register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sram_addr_bitlen:6; /** mem_cache_sram_usr_wcmd : R/W; bitpos: [20]; default: 1; * For SPI0, In the external RAM mode cache write sram for user define command + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_wcmd:1; /** mem_sram_oct : R/W; bitpos: [21]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sram_oct:1; /** mem_sram_wdummy_cyclelen : R/W; bitpos: [27:22]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sram_wdummy_cyclelen:6; uint32_t reserved_28:4; @@ -690,73 +748,88 @@ typedef union { * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: * SPI clock is always on. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclk_mode:2; /** mem_swb_mode : R/W; bitpos: [9:2]; default: 0; * Mode bits in the external RAM fast read mode it is combined with * spi_mem_s_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_swb_mode:8; /** mem_sdin_dual : R/W; bitpos: [10]; default: 0; * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is * the same with spi_mem_s_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdin_dual:1; /** mem_sdout_dual : R/W; bitpos: [11]; default: 0; * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit * is the same with spi_mem_s_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdout_dual:1; /** mem_saddr_dual : R/W; bitpos: [12]; default: 0; * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The * bit is the same with spi_mem_s_usr_sram_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_saddr_dual:1; uint32_t reserved_13:1; /** mem_sdin_quad : R/W; bitpos: [14]; default: 0; * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_s_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdin_quad:1; /** mem_sdout_quad : R/W; bitpos: [15]; default: 0; * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit * is the same with spi_mem_s_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdout_quad:1; /** mem_saddr_quad : R/W; bitpos: [16]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The * bit is the same with spi_mem_s_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_saddr_quad:1; /** mem_scmd_quad : R/W; bitpos: [17]; default: 0; * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_s_usr_sram_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_scmd_quad:1; /** mem_sdin_oct : R/W; bitpos: [18]; default: 0; * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdin_oct:1; /** mem_sdout_oct : R/W; bitpos: [19]; default: 0; * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdout_oct:1; /** mem_saddr_oct : R/W; bitpos: [20]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_saddr_oct:1; /** mem_scmd_oct : R/W; bitpos: [21]; default: 0; * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_scmd_oct:1; /** mem_sdummy_rin : R/W; bitpos: [22]; default: 1; * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdummy_rin:1; /** mem_sdummy_wout : R/W; bitpos: [23]; default: 1; * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the * signal level of SPI bus is output by the MSPI controller. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdummy_wout:1; /** smem_wdummy_dqs_always_out : R/W; bitpos: [24]; default: 0; @@ -771,10 +844,12 @@ typedef union { uint32_t smem_wdummy_always_out:1; /** mem_sdin_hex : R/W; bitpos: [26]; default: 0; * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdin_hex:1; /** mem_sdout_hex : R/W; bitpos: [27]; default: 0; * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdout_hex:1; uint32_t reserved_28:2; @@ -800,12 +875,14 @@ typedef union { /** mem_cache_sram_usr_rd_cmd_value : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the read command value of command phase * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_rd_cmd_value:16; uint32_t reserved_16:12; /** mem_cache_sram_usr_rd_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the length in bits of command phase for * sram. The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_rd_cmd_bitlen:4; }; @@ -820,12 +897,14 @@ typedef union { /** mem_cache_sram_usr_wr_cmd_value : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the write command value of command phase * for sram. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_wr_cmd_value:16; uint32_t reserved_16:12; /** mem_cache_sram_usr_wr_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the in bits of command phase for sram. * The register value shall be (bit_num-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_wr_cmd_bitlen:4; }; @@ -877,7 +956,7 @@ typedef union { uint32_t smem_usr_ddr_dqs_thd:7; /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_S_DIN state. It is used when there is no SPI_DQS signal or + * spi0_slv_st is in spi_mem_s_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ @@ -942,7 +1021,7 @@ typedef union { */ uint32_t smem_cs_hold_time:5; /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3; - * SPI_MEM_S_SMEM_CS_HOLD_TIME + SPI_MEM_S_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * spi_mem_s_smem_CS_HOLD_TIME + spi_mem_s_smem_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold * cycles in ECC mode when accessed external RAM. */ uint32_t smem_ecc_cs_hold_time:3; @@ -959,7 +1038,7 @@ typedef union { uint32_t reserved_17:8; /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_MEM_S_SMEM_CS_HOLD_DELAY[5:0] + 1) + * transfer when accesses to external RAM. tSHSL is (spi_mem_s_smem_CS_HOLD_DELAY[5:0] + 1) * MSPI core clock cycles. */ uint32_t smem_cs_hold_delay:6; @@ -981,11 +1060,11 @@ typedef union { typedef union { struct { uint32_t reserved_0:7; - /** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4; + /** mem_lock_delay_time : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ - uint32_t mem_lock_delay_time:5; - uint32_t reserved_12:20; + uint32_t mem_lock_delay_time:12; + uint32_t reserved_19:13; }; uint32_t val; } spi_mem_s_fsm_reg_t; @@ -1026,9 +1105,17 @@ typedef union { * The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int__ena:1; - uint32_t reserved_10:18; + uint32_t reserved_10:16; + /** mem_rx_trans_ovf_int_ena : R/W; bitpos: [26]; default: 0; + * The enable bit for spi_mem_s_RX_TRANS_OVF_INT interrupt. + */ + uint32_t mem_rx_trans_ovf_int_ena:1; + /** mem_tx_trans_udf_int_ena : R/W; bitpos: [27]; default: 0; + * The enable bit for spi_mem_s_TX_TRANS_UDF_INT interrupt. + */ + uint32_t mem_tx_trans_udf_int_ena:1; /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0; - * The enable bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. + * The enable bit for spi_mem_s_DQS0_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs0_afifo_ovf_int_ena:1; /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0; @@ -1081,7 +1168,15 @@ typedef union { * The clear bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int_clr:1; - uint32_t reserved_10:18; + uint32_t reserved_10:16; + /** mem_rx_trans_ovf_int_clr : WT; bitpos: [26]; default: 0; + * The clear bit for spi_mem_s_RX_TRANS_OVF_INT interrupt. + */ + uint32_t mem_rx_trans_ovf_int_clr:1; + /** mem_tx_trans_udf_int_clr : WT; bitpos: [27]; default: 0; + * The clear bit for spi_mem_s_TX_TRANS_UDF_INT interrupt. + */ + uint32_t mem_tx_trans_udf_int_clr:1; /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0; * The clear bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ @@ -1152,7 +1247,17 @@ typedef union { * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t mem_axi_waddr_err_int_raw:1; - uint32_t reserved_10:18; + uint32_t reserved_10:16; + /** mem_rx_trans_ovf_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * The raw bit for spi_mem_s_RX_TRANS_OVF_INT interrupt. 1: Triggered when the rx fifo + * to spi bus is overrflow. + */ + uint32_t mem_rx_trans_ovf_int_raw:1; + /** mem_tx_trans_udf_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * The raw bit for spi_mem_s_TX_TRANS_UDF_INT interrupt. 1: Triggered when the tx fifo + * to spi bus is underflow. + */ + uint32_t mem_tx_trans_udf_int_raw:1; /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0; * The raw bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO * connected to SPI_DQS1 is overflow. @@ -1211,7 +1316,15 @@ typedef union { * The enable bit for SPI_MEM_S_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int_st:1; - uint32_t reserved_10:18; + uint32_t reserved_10:16; + /** mem_rx_trans_ovf_int_st : RO; bitpos: [26]; default: 0; + * The status bit for spi_mem_s_RX_TRANS_OVF_INT interrupt. + */ + uint32_t mem_rx_trans_ovf_int_st:1; + /** mem_tx_trans_udf_int_st : RO; bitpos: [27]; default: 0; + * The status bit for spi_mem_s_TX_TRANS_UDF_INT interrupt. + */ + uint32_t mem_tx_trans_udf_int_st:1; /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0; * The status bit for SPI_MEM_S_DQS0_AFIFO_OVF_INT interrupt. */ @@ -1233,62 +1346,175 @@ typedef union { } spi_mem_s_int_st_reg_t; +/** Group: DLL debug and configuration registers */ +/** Type of mem_dll_dly_db register + * MSPI DLL function and debug configuration register + */ +typedef union { + struct { + /** mem_dll_db_cfg_vld_cnt : R/W; bitpos: [7:0]; default: 0; + * Configures the end time of the debug window. + */ + uint32_t mem_dll_db_cfg_vld_cnt:8; + /** mem_dll_db_cnt_mode_sel : R/W; bitpos: [11:8]; default: 0; + * [3]:1-spi_din[15:8]. 0-spi_din[7:0]. [2]:1-only shift wptr or rptr. 0-both shift + * wptr and rptr. [1]:1-wprt[3:0] and rptr[3:0]. 0-rptr[3:0] and wprt[3:0]. + * [0]:1-neg_ptr[3:0]. 0-pos_prt[3:0]. + */ + uint32_t mem_dll_db_cnt_mode_sel:4; + /** mem_dll_db_cnt_clr : R/W; bitpos: [12]; default: 0; + * Configures the start time of the debug window. 1: Clear db_vld_cnt to 0 and Get + * ready for debug. 0: No debug. + */ + uint32_t mem_dll_db_cnt_clr:1; + /** mem_dll_din_dly_sel : R/W; bitpos: [13]; default: 0; + * Configures the din channel. 1: Use delayed data. 0: Do not use delayed data. + */ + uint32_t mem_dll_din_dly_sel:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} spi_mem_s_dll_dly_db_reg_t; + + +/** Group: DLL debug status registers */ +/** Type of mem_dll_db_st0 register + * MSPI DLL debug status0 register + */ +typedef union { + struct { + /** mem_db_fifo_cnt_h : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[63:32] + */ + uint32_t mem_db_fifo_cnt_h:32; + }; + uint32_t val; +} spi_mem_s_dll_db_st0_reg_t; + +/** Type of mem_dll_db_st1 register + * MSPI DLL debug status1 register + */ +typedef union { + struct { + /** mem_db_fifo_cnt_l : RO; bitpos: [31:0]; default: 0; + * Debug for DLL FIFO pointer. Use a 64bits shift register to record pointer changes + * during the debug window. db_fifo_cnt[31:0] + */ + uint32_t mem_db_fifo_cnt_l:32; + }; + uint32_t val; +} spi_mem_s_dll_db_st1_reg_t; + + /** Group: PMS control and configuration registers */ -/** Type of fmem_pmsn_attr register +/** Type of fmem_pms0_attr register * MSPI flash PMS section $n attribute register */ typedef union { struct { - /** fmem_pms_rd_attr : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section $n read accessible. 0: Not allowed. + /** fmem_pms0_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed. + */ + uint32_t fmem_pms0_rd_attr:1; + /** fmem_pms0_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 0 write accessible. 0: Not allowed. + */ + uint32_t fmem_pms0_wr_attr:1; + /** fmem_pms0_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 0 is configured by registers spi_mem_s_fmem_PMS0_ADDR_REG and + * spi_mem_s_fmem_PMS0_SIZE_REG. + */ + uint32_t fmem_pms0_ecc:1; + /** fmem_pms0_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 0 read accessible. 0: Not allowed. + */ + uint32_t fmem_pms0_nonsecure_rd_attr:1; + /** fmem_pms0_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 0 write accessible. 0: Not allowed. + */ + uint32_t fmem_pms0_nonsecure_wr_attr:1; + /** fmem_pms0_nonsecure_ecc : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 0 is configured by registers spi_mem_s_fmem_PMS0_ADDR_REG and + * spi_mem_s_fmem_PMS0_SIZE_REG. + */ + uint32_t fmem_pms0_nonsecure_ecc:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} spi_mem_s_fmem_pms0_attr_reg_t; + +/** Type of fmem_pmsn_attr register + * SPI1 flash PMS section n attribute register + */ +typedef union { + struct { + /** fmem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section n read accessible. 0: Not allowed. */ - uint32_t fmem_pms_rd_attr:1; - /** fmem_pms_wr_attr : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section $n write accessible. 0: Not allowed. + uint32_t fmem_pmsn_rd_attr:1; + /** fmem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section n write accessible. 0: Not allowed. */ - uint32_t fmem_pms_wr_attr:1; - /** fmem_pms_ecc : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash - * PMS section $n is configured by registers SPI_MEM_S_FMEM_PMS$n_ADDR_REG and - * SPI_MEM_S_FMEM_PMS$n_SIZE_REG. + uint32_t fmem_pmsn_wr_attr:1; + /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section n is configured by registers spi_mem_s_fmem_PMSn_ADDR_REG and + * spi_mem_s_fmem_PMSn_SIZE_REG. */ - uint32_t fmem_pms_ecc:1; - uint32_t reserved_3:29; + uint32_t fmem_pmsn_ecc:1; + /** fmem_pmsn_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section n read accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_nonsecure_rd_attr:1; + /** fmem_pmsn_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section n write accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_nonsecure_wr_attr:1; + /** fmem_pmsn_nonsecure_ecc : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section n is configured by registers spi_mem_s_fmem_PMSn_ADDR_REG and + * spi_mem_s_fmem_PMSn_SIZE_REG. + */ + uint32_t fmem_pmsn_nonsecure_ecc:1; + uint32_t reserved_6:26; }; uint32_t val; } spi_mem_s_fmem_pmsn_attr_reg_t; /** Type of fmem_pmsn_addr register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section n start address register */ typedef union { struct { - /** fmem_pms_addr_s : R/W; bitpos: [26:0]; default: 0; - * SPI1 flash PMS section $n start address value + /** fmem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section n start address value */ - uint32_t fmem_pms_addr_s:27; + uint32_t fmem_pmsn_addr_s:27; uint32_t reserved_27:5; }; uint32_t val; } spi_mem_s_fmem_pmsn_addr_reg_t; /** Type of fmem_pmsn_size register - * SPI1 flash PMS section $n start address register + * SPI1 flash PMS section n start address register */ typedef union { struct { - /** fmem_pms_size : R/W; bitpos: [14:0]; default: 4096; - * SPI1 flash PMS section $n address region is (SPI_MEM_S_FMEM_PMS$n_ADDR_S, - * SPI_MEM_S_FMEM_PMS$n_ADDR_S + SPI_MEM_S_FMEM_PMS$n_SIZE) + /** fmem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section n address region is (spi_mem_s_fmem_PMSn_ADDR_S, + * spi_mem_s_fmem_PMSn_ADDR_S + spi_mem_s_fmem_PMSn_SIZE) */ - uint32_t fmem_pms_size:15; + uint32_t fmem_pmsn_size:15; uint32_t reserved_15:17; }; uint32_t val; } spi_mem_s_fmem_pmsn_size_reg_t; /** Type of smem_pmsn_attr register - * SPI1 flash PMS section $n start address register + * SPI1 external RAM PMS section n attribute register */ typedef union { struct { @@ -1306,18 +1532,32 @@ typedef union { * SPI_MEM_S_SMEM_PMS$n_SIZE_REG. */ uint32_t smem_pms_ecc:1; - uint32_t reserved_3:29; + /** smem_pmsn_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section n read accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_nonsecure_rd_attr:1; + /** smem_pmsn_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section n write accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_nonsecure_wr_attr:1; + /** smem_pmsn_nonsecure_ecc : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section n ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section n is configured by registers + * spi_mem_s_smem_PMSn_ADDR_REG and spi_mem_s_smem_PMSn_SIZE_REG. + */ + uint32_t smem_pmsn_nonsecure_ecc:1; + uint32_t reserved_6:26; }; uint32_t val; } spi_mem_s_smem_pmsn_attr_reg_t; /** Type of smem_pmsn_addr register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section n start address register */ typedef union { struct { - /** smem_pms_addr_s : R/W; bitpos: [26:0]; default: 0; - * SPI1 external RAM PMS section $n start address value + /** smem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section n start address value */ uint32_t smem_pms_addr_s:27; uint32_t reserved_27:5; @@ -1326,7 +1566,7 @@ typedef union { } spi_mem_s_smem_pmsn_addr_reg_t; /** Type of smem_pmsn_size register - * SPI1 external RAM PMS section $n start address register + * SPI1 external RAM PMS section n start address register */ typedef union { struct { @@ -1347,7 +1587,7 @@ typedef union { struct { /** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first SPI1 access error address. It is cleared by when - * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + * spi_mem_s_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_reject_addr:27; /** mem_pm_en : R/W; bitpos: [27]; default: 0; @@ -1356,22 +1596,22 @@ typedef union { uint32_t mem_pm_en:1; /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + * spi_mem_s_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_ld:1; /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + * spi_mem_s_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_st:1; /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + * cleared by when spi_mem_s_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_multi_hit:1; /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when SPI_MEM_S_PMS_REJECT_INT_CLR bit is set. + * error. It is cleared by when spi_mem_s_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_ivd:1; }; @@ -1388,11 +1628,11 @@ typedef union { uint32_t reserved_0:5; /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0; * This bits show the error times of MSPI ECC read. It is cleared by when - * SPI_MEM_S_ECC_ERR_INT_CLR bit is set. + * spi_mem_s_ECC_ERR_INT_CLR bit is set. */ uint32_t mem_ecc_err_cnt:6; /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_S_ECC_ERR_INT interrupt. + * Set the error times of MSPI ECC read to generate MSPI spi_mem_s_ECC_ERR_INT interrupt. */ uint32_t fmem_ecc_err_int_num:6; /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; @@ -1416,9 +1656,9 @@ typedef union { uint32_t mem_usr_ecc_addr_en:1; uint32_t reserved_22:2; /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1; - * 1: The error information in SPI_MEM_S_ECC_ERR_BITS and SPI_MEM_S_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: SPI_MEM_S_ECC_ERR_BITS and - * SPI_MEM_S_ECC_ERR_ADDR record the first ECC error information. + * 1: The error information in spi_mem_s_ECC_ERR_BITS and spi_mem_s_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: spi_mem_s_ECC_ERR_BITS and + * spi_mem_s_ECC_ERR_ADDR record the first ECC error information. */ uint32_t mem_ecc_continue_record_err_en:1; /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0; @@ -1437,7 +1677,7 @@ typedef union { struct { /** mem_ecc_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first MSPI ECC error address. It is cleared by when - * SPI_MEM_S_ECC_ERR_INT_CLR bit is set. + * spi_mem_s_ECC_ERR_INT_CLR bit is set. */ uint32_t mem_ecc_err_addr:27; uint32_t reserved_27:5; @@ -2279,13 +2519,13 @@ typedef union { */ typedef union { struct { - /** xts_physical_address : R/W; bitpos: [25:0]; default: 0; + /** xts_physical_address : R/W; bitpos: [29:0]; default: 0; * This bits stores the physical-address parameter which will be used in manual * encryption calculation. This value should aligned with byte number decided by * line-size parameter. */ - uint32_t xts_physical_address:26; - uint32_t reserved_26:6; + uint32_t xts_physical_address:30; + uint32_t reserved_30:2; }; uint32_t val; } spi_mem_s_xts_physical_address_reg_t; @@ -2364,7 +2604,7 @@ typedef union { */ typedef union { struct { - /** xts_date : R/W; bitpos: [29:0]; default: 538972176; + /** xts_date : R/W; bitpos: [29:0]; default: 539035911; * This bits stores the last modified-time of manual encryption feature. */ uint32_t xts_date:30; @@ -2421,17 +2661,23 @@ typedef union { * controlled by rtc. */ uint32_t mmu_mem_force_pu:1; - uint32_t reserved_3:13; + /** mmu_page_size : R/W; bitpos: [4:3]; default: 0; + * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + */ + uint32_t mmu_page_size:2; + uint32_t reserved_5:11; /** mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; * MMU PSRAM aux control register */ uint32_t mem_aux_ctrl:14; /** mem_rdn_ena : R/W; bitpos: [30]; default: 0; * ECO register enable bit + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_rdn_ena:1; /** mem_rdn_result : RO; bitpos: [31]; default: 0; * MSPI module clock domain and AXI clock domain ECO register result register + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_rdn_result:1; }; @@ -2468,6 +2714,37 @@ typedef union { } spi_mem_s_dpa_ctrl_reg_t; +/** Group: External mem cryption PSEUDO registers */ +/** Type of mem_xts_pseudo_round_conf register + * SPI memory cryption PSEUDO register + */ +typedef union { + struct { + /** mem_mode_pseudo : R/W; bitpos: [1:0]; default: 0; + * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo + * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. + * 2'b11: crypto with pseudo. + */ + uint32_t mem_mode_pseudo:2; + /** mem_pseudo_rng_cnt : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be performed. + */ + uint32_t mem_pseudo_rng_cnt:3; + /** mem_pseudo_base : R/W; bitpos: [8:5]; default: 2; + * xts aes peseudo function base round that must be performed. + */ + uint32_t mem_pseudo_base:4; + /** mem_pseudo_inc : R/W; bitpos: [10:9]; default: 2; + * xts aes peseudo function increment round that will be performed randomly between 0 & + * 2**(inc+1). + */ + uint32_t mem_pseudo_inc:2; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_s_xts_pseudo_round_conf_reg_t; + + /** Group: ECO registers */ /** Type of mem_registerrnd_eco_high register * MSPI ECO high register @@ -2476,6 +2753,7 @@ typedef union { struct { /** mem_registerrnd_eco_high : R/W; bitpos: [31:0]; default: 892; * ECO high register + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_registerrnd_eco_high:32; }; @@ -2489,6 +2767,7 @@ typedef union { struct { /** mem_registerrnd_eco_low : R/W; bitpos: [31:0]; default: 892; * ECO low register + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_registerrnd_eco_low:32; }; @@ -2502,7 +2781,7 @@ typedef union { */ typedef union { struct { - /** mem_date : R/W; bitpos: [27:0]; default: 36712704; + /** mem_date : R/W; bitpos: [27:0]; default: 38801984; * SPI0 register version. */ uint32_t mem_date:28; @@ -2542,8 +2821,12 @@ typedef struct spi_mem_s_dev_t { uint32_t reserved_0d0; volatile spi_mem_s_ddr_reg_t mem_ddr; volatile spi_mem_s_smem_ddr_reg_t smem_ddr; - uint32_t reserved_0dc[9]; - volatile spi_mem_s_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; + volatile spi_mem_s_dll_dly_db_reg_t mem_dll_dly_db; + volatile spi_mem_s_dll_db_st0_reg_t mem_dll_db_st0; + volatile spi_mem_s_dll_db_st1_reg_t mem_dll_db_st1; + uint32_t reserved_0e8[6]; + volatile spi_mem_s_fmem_pms0_attr_reg_t fmem_pms0_attr; + volatile spi_mem_s_fmem_pmsn_attr_reg_t fmem_pmsn_attr[3]; volatile spi_mem_s_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; volatile spi_mem_s_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; volatile spi_mem_s_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; @@ -2587,7 +2870,8 @@ typedef struct spi_mem_s_dev_t { volatile spi_mem_s_mmu_item_index_reg_t mem_mmu_item_index; volatile spi_mem_s_mmu_power_ctrl_reg_t mem_mmu_power_ctrl; volatile spi_mem_s_dpa_ctrl_reg_t mem_dpa_ctrl; - uint32_t reserved_38c[25]; + volatile spi_mem_s_xts_pseudo_round_conf_reg_t mem_xts_pseudo_round_conf; + uint32_t reserved_390[24]; volatile spi_mem_s_registerrnd_eco_high_reg_t mem_registerrnd_eco_high; volatile spi_mem_s_registerrnd_eco_low_reg_t mem_registerrnd_eco_low; uint32_t reserved_3f8; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/timer_group_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/timer_group_eco5_reg.h deleted file mode 100644 index cb893d23539d..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/timer_group_eco5_reg.h +++ /dev/null @@ -1,716 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** TIMG_T0CONFIG_REG register - * Timer 0 configuration register - */ -#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0) -/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; - * When set, the alarm is enabled. This bit is automatically cleared once an - * alarm occurs. - */ -#define TIMG_T0_ALARM_EN (BIT(10)) -#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S) -#define TIMG_T0_ALARM_EN_V 0x00000001U -#define TIMG_T0_ALARM_EN_S 10 -/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0; - * When set, Timer 0 's clock divider counter will be reset. - */ -#define TIMG_T0_DIVCNT_RST (BIT(12)) -#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S) -#define TIMG_T0_DIVCNT_RST_V 0x00000001U -#define TIMG_T0_DIVCNT_RST_S 12 -/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1; - * Timer 0 clock (T0_clk) prescaler value. - */ -#define TIMG_T0_DIVIDER 0x0000FFFFU -#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S) -#define TIMG_T0_DIVIDER_V 0x0000FFFFU -#define TIMG_T0_DIVIDER_S 13 -/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1; - * When set, timer 0 auto-reload at alarm is enabled. - */ -#define TIMG_T0_AUTORELOAD (BIT(29)) -#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S) -#define TIMG_T0_AUTORELOAD_V 0x00000001U -#define TIMG_T0_AUTORELOAD_S 29 -/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1; - * When set, the timer 0 time-base counter will increment every clock tick. When - * cleared, the timer 0 time-base counter will decrement. - */ -#define TIMG_T0_INCREASE (BIT(30)) -#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S) -#define TIMG_T0_INCREASE_V 0x00000001U -#define TIMG_T0_INCREASE_S 30 -/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0; - * When set, the timer 0 time-base counter is enabled. - */ -#define TIMG_T0_EN (BIT(31)) -#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S) -#define TIMG_T0_EN_V 0x00000001U -#define TIMG_T0_EN_S 31 - -/** TIMG_T0LO_REG register - * Timer 0 current value, low 32 bits - */ -#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4) -/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0; - * After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter - * of timer 0 can be read here. - */ -#define TIMG_T0_LO 0xFFFFFFFFU -#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S) -#define TIMG_T0_LO_V 0xFFFFFFFFU -#define TIMG_T0_LO_S 0 - -/** TIMG_T0HI_REG register - * Timer 0 current value, high 22 bits - */ -#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8) -/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0; - * After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter - * of timer 0 can be read here. - */ -#define TIMG_T0_HI 0x003FFFFFU -#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S) -#define TIMG_T0_HI_V 0x003FFFFFU -#define TIMG_T0_HI_S 0 - -/** TIMG_T0UPDATE_REG register - * Write to copy current timer value to TIMGn_T0_(LO/HI)_REG - */ -#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc) -/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0; - * After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched. - */ -#define TIMG_T0_UPDATE (BIT(31)) -#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S) -#define TIMG_T0_UPDATE_V 0x00000001U -#define TIMG_T0_UPDATE_S 31 - -/** TIMG_T0ALARMLO_REG register - * Timer 0 alarm value, low 32 bits - */ -#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10) -/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0; - * Timer 0 alarm trigger time-base counter value, low 32 bits. - */ -#define TIMG_T0_ALARM_LO 0xFFFFFFFFU -#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S) -#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU -#define TIMG_T0_ALARM_LO_S 0 - -/** TIMG_T0ALARMHI_REG register - * Timer 0 alarm value, high bits - */ -#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14) -/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0; - * Timer 0 alarm trigger time-base counter value, high 22 bits. - */ -#define TIMG_T0_ALARM_HI 0x003FFFFFU -#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S) -#define TIMG_T0_ALARM_HI_V 0x003FFFFFU -#define TIMG_T0_ALARM_HI_S 0 - -/** TIMG_T0LOADLO_REG register - * Timer 0 reload value, low 32 bits - */ -#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18) -/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; - * Low 32 bits of the value that a reload will load onto timer 0 time-base - * Counter. - */ -#define TIMG_T0_LOAD_LO 0xFFFFFFFFU -#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S) -#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU -#define TIMG_T0_LOAD_LO_S 0 - -/** TIMG_T0LOADHI_REG register - * Timer 0 reload value, high 22 bits - */ -#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c) -/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0; - * High 22 bits of the value that a reload will load onto timer 0 time-base - * counter. - */ -#define TIMG_T0_LOAD_HI 0x003FFFFFU -#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S) -#define TIMG_T0_LOAD_HI_V 0x003FFFFFU -#define TIMG_T0_LOAD_HI_S 0 - -/** TIMG_T0LOAD_REG register - * Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG - */ -#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20) -/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0; - * - * Write any value to trigger a timer 0 time-base counter reload. - */ -#define TIMG_T0_LOAD 0xFFFFFFFFU -#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S) -#define TIMG_T0_LOAD_V 0xFFFFFFFFU -#define TIMG_T0_LOAD_S 0 - -/** TIMG_T1CONFIG_REG register - * Timer 1 configuration register - */ -#define TIMG_T1CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x24) -/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; - * When set, the alarm is enabled. This bit is automatically cleared once an - * alarm occurs. - */ -#define TIMG_T1_ALARM_EN (BIT(10)) -#define TIMG_T1_ALARM_EN_M (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S) -#define TIMG_T1_ALARM_EN_V 0x00000001U -#define TIMG_T1_ALARM_EN_S 10 -/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0; - * When set, Timer 1 's clock divider counter will be reset. - */ -#define TIMG_T1_DIVCNT_RST (BIT(12)) -#define TIMG_T1_DIVCNT_RST_M (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S) -#define TIMG_T1_DIVCNT_RST_V 0x00000001U -#define TIMG_T1_DIVCNT_RST_S 12 -/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1; - * Timer 1 clock (T1_clk) prescaler value. - */ -#define TIMG_T1_DIVIDER 0x0000FFFFU -#define TIMG_T1_DIVIDER_M (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S) -#define TIMG_T1_DIVIDER_V 0x0000FFFFU -#define TIMG_T1_DIVIDER_S 13 -/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1; - * When set, timer 1 auto-reload at alarm is enabled. - */ -#define TIMG_T1_AUTORELOAD (BIT(29)) -#define TIMG_T1_AUTORELOAD_M (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S) -#define TIMG_T1_AUTORELOAD_V 0x00000001U -#define TIMG_T1_AUTORELOAD_S 29 -/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1; - * When set, the timer 1 time-base counter will increment every clock tick. When - * cleared, the timer 1 time-base counter will decrement. - */ -#define TIMG_T1_INCREASE (BIT(30)) -#define TIMG_T1_INCREASE_M (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S) -#define TIMG_T1_INCREASE_V 0x00000001U -#define TIMG_T1_INCREASE_S 30 -/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0; - * When set, the timer 1 time-base counter is enabled. - */ -#define TIMG_T1_EN (BIT(31)) -#define TIMG_T1_EN_M (TIMG_T1_EN_V << TIMG_T1_EN_S) -#define TIMG_T1_EN_V 0x00000001U -#define TIMG_T1_EN_S 31 - -/** TIMG_T1LO_REG register - * Timer 1 current value, low 32 bits - */ -#define TIMG_T1LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x28) -/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0; - * After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter - * of timer 1 can be read here. - */ -#define TIMG_T1_LO 0xFFFFFFFFU -#define TIMG_T1_LO_M (TIMG_T1_LO_V << TIMG_T1_LO_S) -#define TIMG_T1_LO_V 0xFFFFFFFFU -#define TIMG_T1_LO_S 0 - -/** TIMG_T1HI_REG register - * Timer 1 current value, high 22 bits - */ -#define TIMG_T1HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x2c) -/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0; - * After writing to TIMG_T1UPDATE_REG, the high 22 bits of the time-base counter - * of timer 1 can be read here. - */ -#define TIMG_T1_HI 0x003FFFFFU -#define TIMG_T1_HI_M (TIMG_T1_HI_V << TIMG_T1_HI_S) -#define TIMG_T1_HI_V 0x003FFFFFU -#define TIMG_T1_HI_S 0 - -/** TIMG_T1UPDATE_REG register - * Write to copy current timer value to TIMGn_T1_(LO/HI)_REG - */ -#define TIMG_T1UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0x30) -/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0; - * After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched. - */ -#define TIMG_T1_UPDATE (BIT(31)) -#define TIMG_T1_UPDATE_M (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S) -#define TIMG_T1_UPDATE_V 0x00000001U -#define TIMG_T1_UPDATE_S 31 - -/** TIMG_T1ALARMLO_REG register - * Timer 1 alarm value, low 32 bits - */ -#define TIMG_T1ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x34) -/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0; - * Timer 1 alarm trigger time-base counter value, low 32 bits. - */ -#define TIMG_T1_ALARM_LO 0xFFFFFFFFU -#define TIMG_T1_ALARM_LO_M (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S) -#define TIMG_T1_ALARM_LO_V 0xFFFFFFFFU -#define TIMG_T1_ALARM_LO_S 0 - -/** TIMG_T1ALARMHI_REG register - * Timer 1 alarm value, high bits - */ -#define TIMG_T1ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x38) -/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0; - * Timer 1 alarm trigger time-base counter value, high 22 bits. - */ -#define TIMG_T1_ALARM_HI 0x003FFFFFU -#define TIMG_T1_ALARM_HI_M (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S) -#define TIMG_T1_ALARM_HI_V 0x003FFFFFU -#define TIMG_T1_ALARM_HI_S 0 - -/** TIMG_T1LOADLO_REG register - * Timer 1 reload value, low 32 bits - */ -#define TIMG_T1LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x3c) -/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; - * Low 32 bits of the value that a reload will load onto timer 1 time-base - * Counter. - */ -#define TIMG_T1_LOAD_LO 0xFFFFFFFFU -#define TIMG_T1_LOAD_LO_M (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S) -#define TIMG_T1_LOAD_LO_V 0xFFFFFFFFU -#define TIMG_T1_LOAD_LO_S 0 - -/** TIMG_T1LOADHI_REG register - * Timer 1 reload value, high 22 bits - */ -#define TIMG_T1LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x40) -/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0; - * High 22 bits of the value that a reload will load onto timer 1 time-base - * counter. - */ -#define TIMG_T1_LOAD_HI 0x003FFFFFU -#define TIMG_T1_LOAD_HI_M (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S) -#define TIMG_T1_LOAD_HI_V 0x003FFFFFU -#define TIMG_T1_LOAD_HI_S 0 - -/** TIMG_T1LOAD_REG register - * Write to reload timer from TIMG_T1_(LOADLOLOADHI)_REG - */ -#define TIMG_T1LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x44) -/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0; - * - * Write any value to trigger a timer 1 time-base counter reload. - */ -#define TIMG_T1_LOAD 0xFFFFFFFFU -#define TIMG_T1_LOAD_M (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S) -#define TIMG_T1_LOAD_V 0xFFFFFFFFU -#define TIMG_T1_LOAD_S 0 - -/** TIMG_WDTCONFIG0_REG register - * Watchdog timer configuration register - */ -#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48) -/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0; - * WDT reset CPU enable. - */ -#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) -#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S) -#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U -#define TIMG_WDT_APPCPU_RESET_EN_S 12 -/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0; - * WDT reset CPU enable. - */ -#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) -#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S) -#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U -#define TIMG_WDT_PROCPU_RESET_EN_S 13 -/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1; - * When set, Flash boot protection is enabled. - */ -#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) -#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S) -#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U -#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 -/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1; - * System reset signal length selection. 0: 100 ns, 1: 200 ns, - * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. - */ -#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U -#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S) -#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U -#define TIMG_WDT_SYS_RESET_LENGTH_S 15 -/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1; - * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, - * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. - */ -#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U -#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S) -#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U -#define TIMG_WDT_CPU_RESET_LENGTH_S 18 -/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0; - * update the WDT configuration registers - */ -#define TIMG_WDT_CONF_UPDATE_EN (BIT(22)) -#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S) -#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U -#define TIMG_WDT_CONF_UPDATE_EN_S 22 -/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0; - * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ -#define TIMG_WDT_STG3 0x00000003U -#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S) -#define TIMG_WDT_STG3_V 0x00000003U -#define TIMG_WDT_STG3_S 23 -/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0; - * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ -#define TIMG_WDT_STG2 0x00000003U -#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S) -#define TIMG_WDT_STG2_V 0x00000003U -#define TIMG_WDT_STG2_S 25 -/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0; - * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ -#define TIMG_WDT_STG1 0x00000003U -#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S) -#define TIMG_WDT_STG1_V 0x00000003U -#define TIMG_WDT_STG1_S 27 -/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0; - * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ -#define TIMG_WDT_STG0 0x00000003U -#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S) -#define TIMG_WDT_STG0_V 0x00000003U -#define TIMG_WDT_STG0_S 29 -/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0; - * When set, MWDT is enabled. - */ -#define TIMG_WDT_EN (BIT(31)) -#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S) -#define TIMG_WDT_EN_V 0x00000001U -#define TIMG_WDT_EN_S 31 - -/** TIMG_WDTCONFIG1_REG register - * Watchdog timer prescaler register - */ -#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c) -/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0; - * When set, WDT 's clock divider counter will be reset. - */ -#define TIMG_WDT_DIVCNT_RST (BIT(0)) -#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S) -#define TIMG_WDT_DIVCNT_RST_V 0x00000001U -#define TIMG_WDT_DIVCNT_RST_S 0 -/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1; - * MWDT clock prescaler value. MWDT clock period = 12.5 ns * - * TIMG_WDT_CLK_PRESCALE. - */ -#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU -#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S) -#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU -#define TIMG_WDT_CLK_PRESCALE_S 16 - -/** TIMG_WDTCONFIG2_REG register - * Watchdog timer stage 0 timeout value - */ -#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50) -/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000; - * Stage 0 timeout value, in MWDT clock cycles. - */ -#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU -#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S) -#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU -#define TIMG_WDT_STG0_HOLD_S 0 - -/** TIMG_WDTCONFIG3_REG register - * Watchdog timer stage 1 timeout value - */ -#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54) -/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727; - * Stage 1 timeout value, in MWDT clock cycles. - */ -#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU -#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S) -#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU -#define TIMG_WDT_STG1_HOLD_S 0 - -/** TIMG_WDTCONFIG4_REG register - * Watchdog timer stage 2 timeout value - */ -#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58) -/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575; - * Stage 2 timeout value, in MWDT clock cycles. - */ -#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU -#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S) -#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU -#define TIMG_WDT_STG2_HOLD_S 0 - -/** TIMG_WDTCONFIG5_REG register - * Watchdog timer stage 3 timeout value - */ -#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c) -/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575; - * Stage 3 timeout value, in MWDT clock cycles. - */ -#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU -#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S) -#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU -#define TIMG_WDT_STG3_HOLD_S 0 - -/** TIMG_WDTFEED_REG register - * Write to feed the watchdog timer - */ -#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60) -/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0; - * Write any value to feed the MWDT. (WO) - */ -#define TIMG_WDT_FEED 0xFFFFFFFFU -#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S) -#define TIMG_WDT_FEED_V 0xFFFFFFFFU -#define TIMG_WDT_FEED_S 0 - -/** TIMG_WDTWPROTECT_REG register - * Watchdog write protect register - */ -#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64) -/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; - * If the register contains a different value than its reset value, write - * protection is enabled. - */ -#define TIMG_WDT_WKEY 0xFFFFFFFFU -#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S) -#define TIMG_WDT_WKEY_V 0xFFFFFFFFU -#define TIMG_WDT_WKEY_S 0 - -/** TIMG_RTCCALICFG_REG register - * RTC calibration configure register - */ -#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68) -/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1; - * 0: one-shot frequency calculation,1: periodic frequency calculation, - */ -#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) -#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S) -#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U -#define TIMG_RTC_CALI_START_CYCLING_S 12 -/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0; - * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. - */ -#define TIMG_RTC_CALI_CLK_SEL 0x00000003U -#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S) -#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U -#define TIMG_RTC_CALI_CLK_SEL_S 13 -/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0; - * indicate one-shot frequency calculation is done. - */ -#define TIMG_RTC_CALI_RDY (BIT(15)) -#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S) -#define TIMG_RTC_CALI_RDY_V 0x00000001U -#define TIMG_RTC_CALI_RDY_S 15 -/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1; - * Configure the time to calculate RTC slow clock's frequency. - */ -#define TIMG_RTC_CALI_MAX 0x00007FFFU -#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S) -#define TIMG_RTC_CALI_MAX_V 0x00007FFFU -#define TIMG_RTC_CALI_MAX_S 16 -/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0; - * Set this bit to start one-shot frequency calculation. - */ -#define TIMG_RTC_CALI_START (BIT(31)) -#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S) -#define TIMG_RTC_CALI_START_V 0x00000001U -#define TIMG_RTC_CALI_START_S 31 - -/** TIMG_RTCCALICFG1_REG register - * RTC calibration configure1 register - */ -#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c) -/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0; - * indicate periodic frequency calculation is done. - */ -#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) -#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S) -#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U -#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 -/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0; - * When one-shot or periodic frequency calculation is done, read this value to - * calculate RTC slow clock's frequency. - */ -#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU -#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S) -#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU -#define TIMG_RTC_CALI_VALUE_S 7 - -/** TIMG_INT_ENA_TIMERS_REG register - * Interrupt enable bits - */ -#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70) -/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the TIMG_T$x_INT interrupt. - */ -#define TIMG_T0_INT_ENA (BIT(0)) -#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S) -#define TIMG_T0_INT_ENA_V 0x00000001U -#define TIMG_T0_INT_ENA_S 0 -/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the TIMG_T$x_INT interrupt. - */ -#define TIMG_T1_INT_ENA (BIT(1)) -#define TIMG_T1_INT_ENA_M (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S) -#define TIMG_T1_INT_ENA_V 0x00000001U -#define TIMG_T1_INT_ENA_S 1 -/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the TIMG_WDT_INT interrupt. - */ -#define TIMG_WDT_INT_ENA (BIT(2)) -#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S) -#define TIMG_WDT_INT_ENA_V 0x00000001U -#define TIMG_WDT_INT_ENA_S 2 - -/** TIMG_INT_RAW_TIMERS_REG register - * Raw interrupt status - */ -#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74) -/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt status bit for the TIMG_T$x_INT interrupt. - */ -#define TIMG_T0_INT_RAW (BIT(0)) -#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S) -#define TIMG_T0_INT_RAW_V 0x00000001U -#define TIMG_T0_INT_RAW_S 0 -/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; - * The raw interrupt status bit for the TIMG_T$x_INT interrupt. - */ -#define TIMG_T1_INT_RAW (BIT(1)) -#define TIMG_T1_INT_RAW_M (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S) -#define TIMG_T1_INT_RAW_V 0x00000001U -#define TIMG_T1_INT_RAW_S 1 -/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; - * The raw interrupt status bit for the TIMG_WDT_INT interrupt. - */ -#define TIMG_WDT_INT_RAW (BIT(2)) -#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S) -#define TIMG_WDT_INT_RAW_V 0x00000001U -#define TIMG_WDT_INT_RAW_S 2 - -/** TIMG_INT_ST_TIMERS_REG register - * Masked interrupt status - */ -#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78) -/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for the TIMG_T$x_INT interrupt. - */ -#define TIMG_T0_INT_ST (BIT(0)) -#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S) -#define TIMG_T0_INT_ST_V 0x00000001U -#define TIMG_T0_INT_ST_S 0 -/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for the TIMG_T$x_INT interrupt. - */ -#define TIMG_T1_INT_ST (BIT(1)) -#define TIMG_T1_INT_ST_M (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S) -#define TIMG_T1_INT_ST_V 0x00000001U -#define TIMG_T1_INT_ST_S 1 -/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for the TIMG_WDT_INT interrupt. - */ -#define TIMG_WDT_INT_ST (BIT(2)) -#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S) -#define TIMG_WDT_INT_ST_V 0x00000001U -#define TIMG_WDT_INT_ST_S 2 - -/** TIMG_INT_CLR_TIMERS_REG register - * Interrupt clear bits - */ -#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c) -/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the TIMG_T$x_INT interrupt. - */ -#define TIMG_T0_INT_CLR (BIT(0)) -#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S) -#define TIMG_T0_INT_CLR_V 0x00000001U -#define TIMG_T0_INT_CLR_S 0 -/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the TIMG_T$x_INT interrupt. - */ -#define TIMG_T1_INT_CLR (BIT(1)) -#define TIMG_T1_INT_CLR_M (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S) -#define TIMG_T1_INT_CLR_V 0x00000001U -#define TIMG_T1_INT_CLR_S 1 -/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the TIMG_WDT_INT interrupt. - */ -#define TIMG_WDT_INT_CLR (BIT(2)) -#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S) -#define TIMG_WDT_INT_CLR_V 0x00000001U -#define TIMG_WDT_INT_CLR_S 2 - -/** TIMG_RTCCALICFG2_REG register - * Timer group calibration register - */ -#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80) -/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; - * RTC calibration timeout indicator - */ -#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) -#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S) -#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U -#define TIMG_RTC_CALI_TIMEOUT_S 0 -/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3; - * Cycles that release calibration timeout reset - */ -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S) -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 -/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431; - * Threshold value for the RTC calibration timer. If the calibration timer's value - * exceeds this threshold, a timeout is triggered. - */ -#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU -#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S) -#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU -#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 - -/** TIMG_NTIMERS_DATE_REG register - * Timer version control register - */ -#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8) -/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770; - * Timer version control register - */ -#define TIMG_NTIMGS_DATE 0x0FFFFFFFU -#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S) -#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU -#define TIMG_NTIMGS_DATE_S 0 - -/** TIMG_REGCLK_REG register - * Timer group clock gate register - */ -#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc) -/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1; - * enable timer's etm task and event - */ -#define TIMG_ETM_EN (BIT(28)) -#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S) -#define TIMG_ETM_EN_V 0x00000001U -#define TIMG_ETM_EN_S 28 -/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0; - * Register clock gate signal. 1: Registers can be read and written to by software. 0: - * Registers can not be read or written to by software. - */ -#define TIMG_CLK_EN (BIT(31)) -#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S) -#define TIMG_CLK_EN_V 0x00000001U -#define TIMG_CLK_EN_S 31 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/timer_group_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/timer_group_eco5_struct.h deleted file mode 100644 index 363dff92d1a7..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/timer_group_eco5_struct.h +++ /dev/null @@ -1,571 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: T0 Control and configuration registers */ -/** Type of txconfig register - * Timer x configuration register - */ -typedef union { - struct { - uint32_t reserved_0:10; - /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0; - * When set, the alarm is enabled. This bit is automatically cleared once an - * alarm occurs. - */ - uint32_t tx_alarm_en:1; - uint32_t reserved_11:1; - /** tx_divcnt_rst : WT; bitpos: [12]; default: 0; - * When set, Timer x 's clock divider counter will be reset. - */ - uint32_t tx_divcnt_rst:1; - /** tx_divider : R/W; bitpos: [28:13]; default: 1; - * Timer x clock (Tx_clk) prescaler value. - */ - uint32_t tx_divider:16; - /** tx_autoreload : R/W; bitpos: [29]; default: 1; - * When set, timer x auto-reload at alarm is enabled. - */ - uint32_t tx_autoreload:1; - /** tx_increase : R/W; bitpos: [30]; default: 1; - * When set, the timer x time-base counter will increment every clock tick. When - * cleared, the timer x time-base counter will decrement. - */ - uint32_t tx_increase:1; - /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0; - * When set, the timer x time-base counter is enabled. - */ - uint32_t tx_en:1; - }; - uint32_t val; -} timg_txconfig_reg_t; - -/** Type of txlo register - * Timer x current value, low 32 bits - */ -typedef union { - struct { - /** tx_lo : RO; bitpos: [31:0]; default: 0; - * After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter - * of timer x can be read here. - */ - uint32_t tx_lo:32; - }; - uint32_t val; -} timg_txlo_reg_t; - -/** Type of txhi register - * Timer x current value, high 22 bits - */ -typedef union { - struct { - /** tx_hi : RO; bitpos: [21:0]; default: 0; - * After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter - * of timer x can be read here. - */ - uint32_t tx_hi:22; - uint32_t reserved_22:10; - }; - uint32_t val; -} timg_txhi_reg_t; - -/** Type of txupdate register - * Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** tx_update : R/W/SC; bitpos: [31]; default: 0; - * After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched. - */ - uint32_t tx_update:1; - }; - uint32_t val; -} timg_txupdate_reg_t; - -/** Type of txalarmlo register - * Timer x alarm value, low 32 bits - */ -typedef union { - struct { - /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0; - * Timer x alarm trigger time-base counter value, low 32 bits. - */ - uint32_t tx_alarm_lo:32; - }; - uint32_t val; -} timg_txalarmlo_reg_t; - -/** Type of txalarmhi register - * Timer x alarm value, high bits - */ -typedef union { - struct { - /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0; - * Timer x alarm trigger time-base counter value, high 22 bits. - */ - uint32_t tx_alarm_hi:22; - uint32_t reserved_22:10; - }; - uint32_t val; -} timg_txalarmhi_reg_t; - -/** Type of txloadlo register - * Timer x reload value, low 32 bits - */ -typedef union { - struct { - /** tx_load_lo : R/W; bitpos: [31:0]; default: 0; - * Low 32 bits of the value that a reload will load onto timer x time-base - * Counter. - */ - uint32_t tx_load_lo:32; - }; - uint32_t val; -} timg_txloadlo_reg_t; - -/** Type of txloadhi register - * Timer x reload value, high 22 bits - */ -typedef union { - struct { - /** tx_load_hi : R/W; bitpos: [21:0]; default: 0; - * High 22 bits of the value that a reload will load onto timer x time-base - * counter. - */ - uint32_t tx_load_hi:22; - uint32_t reserved_22:10; - }; - uint32_t val; -} timg_txloadhi_reg_t; - -/** Type of txload register - * Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG - */ -typedef union { - struct { - /** tx_load : WT; bitpos: [31:0]; default: 0; - * - * Write any value to trigger a timer x time-base counter reload. - */ - uint32_t tx_load:32; - }; - uint32_t val; -} timg_txload_reg_t; - -/** Group: WDT Control and configuration registers */ -/** Type of wdtconfig0 register - * Watchdog timer configuration register - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0; - * WDT reset CPU enable. - */ - uint32_t wdt_appcpu_reset_en:1; - /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0; - * WDT reset CPU enable. - */ - uint32_t wdt_procpu_reset_en:1; - /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1; - * When set, Flash boot protection is enabled. - */ - uint32_t wdt_flashboot_mod_en:1; - /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1; - * System reset signal length selection. 0: 100 ns, 1: 200 ns, - * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. - */ - uint32_t wdt_sys_reset_length:3; - /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1; - * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, - * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. - */ - uint32_t wdt_cpu_reset_length:3; - uint32_t reserved_21:1; - /** wdt_conf_update_en : WT; bitpos: [22]; default: 0; - * update the WDT configuration registers - */ - uint32_t wdt_conf_update_en:1; - /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0; - * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ - uint32_t wdt_stg3:2; - /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0; - * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ - uint32_t wdt_stg2:2; - /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0; - * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ - uint32_t wdt_stg1:2; - /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0; - * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ - uint32_t wdt_stg0:2; - /** wdt_en : R/W; bitpos: [31]; default: 0; - * When set, MWDT is enabled. - */ - uint32_t wdt_en:1; - }; - uint32_t val; -} timg_wdtconfig0_reg_t; - -/** Type of wdtconfig1 register - * Watchdog timer prescaler register - */ -typedef union { - struct { - /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0; - * When set, WDT 's clock divider counter will be reset. - */ - uint32_t wdt_divcnt_rst:1; - uint32_t reserved_1:15; - /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1; - * MWDT clock prescaler value. MWDT clock period = 12.5 ns * - * TIMG_WDT_CLK_PRESCALE. - */ - uint32_t wdt_clk_prescale:16; - }; - uint32_t val; -} timg_wdtconfig1_reg_t; - -/** Type of wdtconfig2 register - * Watchdog timer stage 0 timeout value - */ -typedef union { - struct { - /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000; - * Stage 0 timeout value, in MWDT clock cycles. - */ - uint32_t wdt_stg0_hold:32; - }; - uint32_t val; -} timg_wdtconfig2_reg_t; - -/** Type of wdtconfig3 register - * Watchdog timer stage 1 timeout value - */ -typedef union { - struct { - /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727; - * Stage 1 timeout value, in MWDT clock cycles. - */ - uint32_t wdt_stg1_hold:32; - }; - uint32_t val; -} timg_wdtconfig3_reg_t; - -/** Type of wdtconfig4 register - * Watchdog timer stage 2 timeout value - */ -typedef union { - struct { - /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575; - * Stage 2 timeout value, in MWDT clock cycles. - */ - uint32_t wdt_stg2_hold:32; - }; - uint32_t val; -} timg_wdtconfig4_reg_t; - -/** Type of wdtconfig5 register - * Watchdog timer stage 3 timeout value - */ -typedef union { - struct { - /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575; - * Stage 3 timeout value, in MWDT clock cycles. - */ - uint32_t wdt_stg3_hold:32; - }; - uint32_t val; -} timg_wdtconfig5_reg_t; - -/** Type of wdtfeed register - * Write to feed the watchdog timer - */ -typedef union { - struct { - /** wdt_feed : WT; bitpos: [31:0]; default: 0; - * Write any value to feed the MWDT. (WO) - */ - uint32_t wdt_feed:32; - }; - uint32_t val; -} timg_wdtfeed_reg_t; - -/** Type of wdtwprotect register - * Watchdog write protect register - */ -typedef union { - struct { - /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065; - * If the register contains a different value than its reset value, write - * protection is enabled. - */ - uint32_t wdt_wkey:32; - }; - uint32_t val; -} timg_wdtwprotect_reg_t; - - -/** Group: RTC CALI Control and configuration registers */ -/** Type of rtccalicfg register - * RTC calibration configure register - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1; - * 0: one-shot frequency calculation,1: periodic frequency calculation, - */ - uint32_t rtc_cali_start_cycling:1; - /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0; - * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. - */ - uint32_t rtc_cali_clk_sel:2; - /** rtc_cali_rdy : RO; bitpos: [15]; default: 0; - * indicate one-shot frequency calculation is done. - */ - uint32_t rtc_cali_rdy:1; - /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1; - * Configure the time to calculate RTC slow clock's frequency. - */ - uint32_t rtc_cali_max:15; - /** rtc_cali_start : R/W; bitpos: [31]; default: 0; - * Set this bit to start one-shot frequency calculation. - */ - uint32_t rtc_cali_start:1; - }; - uint32_t val; -} timg_rtccalicfg_reg_t; - -/** Type of rtccalicfg1 register - * RTC calibration configure1 register - */ -typedef union { - struct { - /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0; - * indicate periodic frequency calculation is done. - */ - uint32_t rtc_cali_cycling_data_vld:1; - uint32_t reserved_1:6; - /** rtc_cali_value : RO; bitpos: [31:7]; default: 0; - * When one-shot or periodic frequency calculation is done, read this value to - * calculate RTC slow clock's frequency. - */ - uint32_t rtc_cali_value:25; - }; - uint32_t val; -} timg_rtccalicfg1_reg_t; - -/** Type of rtccalicfg2 register - * Timer group calibration register - */ -typedef union { - struct { - /** rtc_cali_timeout : RO; bitpos: [0]; default: 0; - * RTC calibration timeout indicator - */ - uint32_t rtc_cali_timeout:1; - uint32_t reserved_1:2; - /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3; - * Cycles that release calibration timeout reset - */ - uint32_t rtc_cali_timeout_rst_cnt:4; - /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431; - * Threshold value for the RTC calibration timer. If the calibration timer's value - * exceeds this threshold, a timeout is triggered. - */ - uint32_t rtc_cali_timeout_thres:25; - }; - uint32_t val; -} timg_rtccalicfg2_reg_t; - - -/** Group: Interrupt registers */ -/** Type of int_ena_timers register - * Interrupt enable bits - */ -typedef union { - struct { - /** t0_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the TIMG_T$x_INT interrupt. - */ - uint32_t t0_int_ena:1; - /** t1_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the TIMG_T$x_INT interrupt. - */ - uint32_t t1_int_ena:1; - /** wdt_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the TIMG_WDT_INT interrupt. - */ - uint32_t wdt_int_ena:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} timg_int_ena_timers_reg_t; - -/** Type of int_raw_timers register - * Raw interrupt status - */ -typedef union { - struct { - /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt status bit for the TIMG_T$x_INT interrupt. - */ - uint32_t t0_int_raw:1; - /** t1_int_raw : R/SS/WTC; bitpos: [1]; default: 0; - * The raw interrupt status bit for the TIMG_T$x_INT interrupt. - */ - uint32_t t1_int_raw:1; - /** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0; - * The raw interrupt status bit for the TIMG_WDT_INT interrupt. - */ - uint32_t wdt_int_raw:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} timg_int_raw_timers_reg_t; - -/** Type of int_st_timers register - * Masked interrupt status - */ -typedef union { - struct { - /** t0_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for the TIMG_T$x_INT interrupt. - */ - uint32_t t0_int_st:1; - /** t1_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for the TIMG_T$x_INT interrupt. - */ - uint32_t t1_int_st:1; - /** wdt_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for the TIMG_WDT_INT interrupt. - */ - uint32_t wdt_int_st:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} timg_int_st_timers_reg_t; - -/** Type of int_clr_timers register - * Interrupt clear bits - */ -typedef union { - struct { - /** t0_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the TIMG_T$x_INT interrupt. - */ - uint32_t t0_int_clr:1; - /** t1_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the TIMG_T$x_INT interrupt. - */ - uint32_t t1_int_clr:1; - /** wdt_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the TIMG_WDT_INT interrupt. - */ - uint32_t wdt_int_clr:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} timg_int_clr_timers_reg_t; - - -/** Group: Version register */ -/** Type of ntimers_date register - * Timer version control register - */ -typedef union { - struct { - /** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770; - * Timer version control register - */ - uint32_t ntimgs_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} timg_ntimers_date_reg_t; - - -/** Group: Clock configuration registers */ -/** Type of regclk register - * Timer group clock gate register - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** etm_en : R/W; bitpos: [28]; default: 1; - * enable timer's etm task and event - */ - uint32_t etm_en:1; - uint32_t reserved_29:2; - /** clk_en : R/W; bitpos: [31]; default: 0; - * Register clock gate signal. 1: Registers can be read and written to by software. 0: - * Registers can not be read or written to by software. - */ - uint32_t clk_en:1; - }; - uint32_t val; -} timg_regclk_reg_t; - - -typedef struct { - volatile timg_txconfig_reg_t t0config; - volatile timg_txlo_reg_t t0lo; - volatile timg_txhi_reg_t t0hi; - volatile timg_txupdate_reg_t t0update; - volatile timg_txalarmlo_reg_t t0alarmlo; - volatile timg_txalarmhi_reg_t t0alarmhi; - volatile timg_txloadlo_reg_t t0loadlo; - volatile timg_txloadhi_reg_t t0loadhi; - volatile timg_txload_reg_t t0load; - volatile timg_txconfig_reg_t t1config; - volatile timg_txlo_reg_t t1lo; - volatile timg_txhi_reg_t t1hi; - volatile timg_txupdate_reg_t t1update; - volatile timg_txalarmlo_reg_t t1alarmlo; - volatile timg_txalarmhi_reg_t t1alarmhi; - volatile timg_txloadlo_reg_t t1loadlo; - volatile timg_txloadhi_reg_t t1loadhi; - volatile timg_txload_reg_t t1load; - volatile timg_wdtconfig0_reg_t wdtconfig0; - volatile timg_wdtconfig1_reg_t wdtconfig1; - volatile timg_wdtconfig2_reg_t wdtconfig2; - volatile timg_wdtconfig3_reg_t wdtconfig3; - volatile timg_wdtconfig4_reg_t wdtconfig4; - volatile timg_wdtconfig5_reg_t wdtconfig5; - volatile timg_wdtfeed_reg_t wdtfeed; - volatile timg_wdtwprotect_reg_t wdtwprotect; - volatile timg_rtccalicfg_reg_t rtccalicfg; - volatile timg_rtccalicfg1_reg_t rtccalicfg1; - volatile timg_int_ena_timers_reg_t int_ena_timers; - volatile timg_int_raw_timers_reg_t int_raw_timers; - volatile timg_int_st_timers_reg_t int_st_timers; - volatile timg_int_clr_timers_reg_t int_clr_timers; - volatile timg_rtccalicfg2_reg_t rtccalicfg2; - uint32_t reserved_084[29]; - volatile timg_ntimers_date_reg_t ntimers_date; - volatile timg_regclk_reg_t regclk; -} timg_dev_t; - -extern timg_dev_t TIMERG0; -extern timg_dev_t TIMERG1; - -#ifndef __cplusplus -_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/timer_group_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/timer_group_reg.h index 7df8a1271f42..c260234634fe 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/timer_group_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/timer_group_reg.h @@ -11,7 +11,7 @@ extern "C" { #endif -// TODO: IDF-13422 +#define REG_TIMG_BASE(i) (DR_REG_TIMG0_BASE + (i) * 0x1000) /** TIMG_T0CONFIG_REG register * Timer 0 configuration register diff --git a/components/soc/esp32p4/register/hw_ver3/soc/timer_group_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/timer_group_struct.h index 1189b1d491c5..1f2b1535dd34 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/timer_group_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/timer_group_struct.h @@ -10,8 +10,6 @@ extern "C" { #endif -// TODO: IDF-13422 - /** Group: T0 Control and configuration registers */ /** Type of txconfig register * Timer x configuration register diff --git a/components/soc/esp32p4/register/hw_ver3/soc/usb_dwc_cfg.h b/components/soc/esp32p4/register/hw_ver3/soc/usb_dwc_cfg.h new file mode 100644 index 000000000000..788e5388239e --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver3/soc/usb_dwc_cfg.h @@ -0,0 +1,181 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/* +HS Instance: +Configuration Set ID: 11 +*/ + +/* 3.1 Basic Config Parameters */ +#define OTG20_MODE 0 +#define OTG20_ARCHITECTURE 2 +#define OTG20_SINGLE_POINT 1 +#define OTG20_ENABLE_LPM 0 +#define OTG20_EN_DED_TX_FIFO 1 +#define OTG20_EN_DESC_DMA 1 +#define OTG20_MULTI_PROC_INTRPT 1 + +/* 3.2 USB Physical Layer Interface Parameters */ +#define OTG20_HSPHY_INTERFACE 3 // Although we support both UTMI+ and ULPI, the ULPI is not wired out of the USB-DWC. Hence only UTMI+ can be used +#define OTG20_HSPHY_DWIDTH 2 +#define OTG20_FSPHY_INTERFACE 2 +#define OTG20_ENABLE_IC_USB 0 +#define OTG20_ENABLE_HSIC 0 +#define OTG20_I2C_INTERFACE 0 +#define OTG20_ULPI_CARKIT 1 +#define OTG20_ADP_SUPPORT 1 +#define OTG20_BC_SUPPORT 0 +#define OTG20_VENDOR_CTL_INTERFACE 1 + +/* 3.3 Device Endpoint Configuration Parameters */ +#define OTG20_NUM_EPS 15 +#define OTG20_NUM_IN_EPS 8 +#define OTG20_NUM_CRL_EPS 1 + +/* 3.4 Host Endpoint Configuration Parameters */ +#define OTG20_NUM_HOST_CHAN 16 +#define OTG20_EN_PERIO_HOST 1 + +/* 3.5 Endpoint Channel FIFO Configuration Parameters */ +#define OTG20_DFIFO_DEPTH 1024 +#define OTG20_DFIFO_DYNAMIC 1 +#define OTG20_RX_DFIFO_DEPTH 1024 +#define OTG20_TX_HNPERIO_DFIFO_DEPTH 1024 +#define OTG20_TX_HPERIO_DFIFO_DEPTH 1024 +#define OTG20_NPERIO_TX_QUEUE_DEPTH 8 +#define OTG20_PERIO_TX_QUEUE_DEPTH 16 + +/* 3.6 Additional Configuration Options Parameters */ +#define OTG20_TRANS_COUNT_WIDTH 17 +#define OTG20_PACKET_COUNT_WIDTH 8 +#define OTG20_RM_OPT_FEATURES 1 +#define OTG20_EN_PWROPT 1 +#define OTG20_SYNC_RESET_TYPE 0 +#define OTG20_EN_IDDIG_FILTER 1 +#define OTG20_EN_VBUSVALID_FILTER 1 +#define OTG20_EN_A_VALID_FILTER 1 +#define OTG20_EN_B_VALID_FILTER 1 +#define OTG20_EN_SESSIONEND_FILTER 1 +#define OTG20_EXCP_CNTL_XFER_FLOW 1 +#define OTG20_PWR_CLAMP 0 +#define OTG20_PWR_SWITCH_POLARITY 0 + +/* 3.7 Endpoint Direction Parameters */ +#define OTG20_EP_DIR_1 0 +#define OTG20_EP_DIR_2 0 +#define OTG20_EP_DIR_3 0 +#define OTG20_EP_DIR_4 0 +#define OTG20_EP_DIR_5 0 +#define OTG20_EP_DIR_6 0 +#define OTG20_EP_DIR_7 0 +#define OTG20_EP_DIR_8 0 +#define OTG20_EP_DIR_9 0 +#define OTG20_EP_DIR_10 0 +#define OTG20_EP_DIR_11 0 +#define OTG20_EP_DIR_12 0 +#define OTG20_EP_DIR_13 0 +#define OTG20_EP_DIR_14 0 +#define OTG20_EP_DIR_15 0 + +/* 3.8 Device Periodic FIFO Depth Parameters */ + +/* 3.9 Device IN Endpoint FIFO Depth Parameters */ +#define OTG20_TX_DINEP_DFIFO_DEPTH_0 512 +#define OTG20_TX_DINEP_DFIFO_DEPTH_1 512 +#define OTG20_TX_DINEP_DFIFO_DEPTH_2 512 +#define OTG20_TX_DINEP_DFIFO_DEPTH_3 512 +#define OTG20_TX_DINEP_DFIFO_DEPTH_4 512 +#define OTG20_TX_DINEP_DFIFO_DEPTH_5 512 +#define OTG20_TX_DINEP_DFIFO_DEPTH_6 512 +#define OTG20_TX_DINEP_DFIFO_DEPTH_7 512 + +/* 3.10 UTMI-To-UTMI Bridge Component Parameters */ +#define OTG20_U2UB_EN 0 + +/* +FS Instance: +Configuration Set ID: 1 +*/ + +/* 3.1 Basic Config Parameters */ +#define OTG11_MODE 0 +#define OTG11_ARCHITECTURE 2 +#define OTG11_SINGLE_POINT 1 +#define OTG11_ENABLE_LPM 0 +#define OTG11_EN_DED_TX_FIFO 1 +#define OTG11_EN_DESC_DMA 1 +#define OTG11_MULTI_PROC_INTRPT 0 + +/* 3.2 USB Physical Layer Interface Parameters */ +#define OTG11_HSPHY_INTERFACE 0 +#define OTG11_FSPHY_INTERFACE 1 +#define OTG11_ENABLE_IC_USB 0 +#define OTG11_I2C_INTERFACE 0 +#define OTG11_ADP_SUPPORT 0 +#define OTG11_BC_SUPPORT 0 + +/* 3.3 Device Endpoint Configuration Parameters */ +#define OTG11_NUM_EPS 6 +#define OTG11_NUM_IN_EPS 5 +#define OTG11_NUM_CRL_EPS 0 + +/* 3.4 Host Endpoint Configuration Parameters */ +#define OTG11_NUM_HOST_CHAN 8 +#define OTG11_EN_PERIO_HOST 1 + +/* 3.5 Endpoint Channel FIFO Configuration Parameters */ +#define OTG11_DFIFO_DEPTH 256 +#define OTG11_DFIFO_DYNAMIC 1 +#define OTG11_RX_DFIFO_DEPTH 256 +#define OTG11_TX_HNPERIO_DFIFO_DEPTH 256 +#define OTG11_TX_NPERIO_DFIFO_DEPTH 256 +#define OTG11_TX_HPERIO_DFIFO_DEPTH 256 +#define OTG11_NPERIO_TX_QUEUE_DEPTH 4 +#define OTG11_PERIO_TX_QUEUE_DEPTH 8 + +/* 3.6 Additional Configuration Options Parameters */ +#define OTG11_TRANS_COUNT_WIDTH 16 +#define OTG11_PACKET_COUNT_WIDTH 7 +#define OTG11_RM_OPT_FEATURES 1 +#define OTG11_EN_PWROPT 1 +#define OTG11_SYNC_RESET_TYPE 0 +#define OTG11_EN_IDDIG_FILTER 1 +#define OTG11_EN_VBUSVALID_FILTER 1 +#define OTG11_EN_A_VALID_FILTER 1 +#define OTG11_EN_B_VALID_FILTER 1 +#define OTG11_EN_SESSIONEND_FILTER 1 +#define OTG11_EXCP_CNTL_XFER_FLOW 1 +#define OTG11_PWR_CLAMP 0 +#define OTG11_PWR_SWITCH_POLARITY 0 + +/* 3.7 Endpoint Direction Parameters */ +#define OTG11_EP_DIR_1 0 +#define OTG11_EP_DIR_2 0 +#define OTG11_EP_DIR_3 0 +#define OTG11_EP_DIR_4 0 +#define OTG11_EP_DIR_5 0 +#define OTG11_EP_DIR_6 0 + +/* 3.8 Device Periodic FIFO Depth Parameters */ + +/* 3.9 Device IN Endpoint FIFO Depth Parameters */ +#define OTG11_TX_DINEP_DFIFO_DEPTH_1 256 +#define OTG11_TX_DINEP_DFIFO_DEPTH_2 256 +#define OTG11_TX_DINEP_DFIFO_DEPTH_3 256 +#define OTG11_TX_DINEP_DFIFO_DEPTH_4 256 + +/* 3.10 UTMI-To-UTMI Bridge Component Parameters */ +#define OTG11_U2UB_EN 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/usb_wrap_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/usb_wrap_eco5_struct.h deleted file mode 100644 index a90ba9b8d8bb..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/usb_wrap_eco5_struct.h +++ /dev/null @@ -1,139 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: USB wrapper registers. */ -/** Type of otg_conf register - * USB wrapper configuration registers. - */ -typedef union { - struct { - /** srp_sessend_override : R/W; bitpos: [0]; default: 0; - * This bit is used to enable the software over-ride of srp session end signal. 1'b0: - * the signal is controlled by the chip input, 1'b1: the signal is controlled by the - * software. - */ - uint32_t srp_sessend_override:1; - /** srp_sessend_value : R/W; bitpos: [1]; default: 0; - * Software over-ride value of srp session end signal. - */ - uint32_t srp_sessend_value:1; - /** phy_sel : R/W; bitpos: [2]; default: 0; - * Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY. - */ - uint32_t phy_sel:1; - /** dfifo_force_pd : R/W; bitpos: [3]; default: 0; - * Force the dfifo to go into low power mode. The data in dfifo will not lost. - */ - uint32_t dfifo_force_pd:1; - /** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0; - * Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals - */ - uint32_t dbnce_fltr_bypass:1; - /** exchg_pins_override : R/W; bitpos: [5]; default: 0; - * Enable software controlle USB D+ D- exchange - */ - uint32_t exchg_pins_override:1; - /** exchg_pins : R/W; bitpos: [6]; default: 0; - * USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-. - */ - uint32_t exchg_pins:1; - /** vrefh : R/W; bitpos: [8:7]; default: 0; - * Control single-end input high threshold,1.76V to 2V, step 80mV. - */ - uint32_t vrefh:2; - /** vrefl : R/W; bitpos: [10:9]; default: 0; - * Control single-end input low threshold,0.8V to 1.04V, step 80mV. - */ - uint32_t vrefl:2; - /** vref_override : R/W; bitpos: [11]; default: 0; - * Enable software controlle input threshold. - */ - uint32_t vref_override:1; - /** pad_pull_override : R/W; bitpos: [12]; default: 0; - * Enable software controlle USB D+ D- pullup pulldown. - */ - uint32_t pad_pull_override:1; - /** dp_pullup : R/W; bitpos: [13]; default: 0; - * Controlle USB D+ pullup. - */ - uint32_t dp_pullup:1; - /** dp_pulldown : R/W; bitpos: [14]; default: 0; - * Controlle USB D+ pulldown. - */ - uint32_t dp_pulldown:1; - /** dm_pullup : R/W; bitpos: [15]; default: 0; - * Controlle USB D+ pullup. - */ - uint32_t dm_pullup:1; - /** dm_pulldown : R/W; bitpos: [16]; default: 0; - * Controlle USB D+ pulldown. - */ - uint32_t dm_pulldown:1; - /** pullup_value : R/W; bitpos: [17]; default: 0; - * Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K. - */ - uint32_t pullup_value:1; - /** usb_pad_enable : R/W; bitpos: [18]; default: 0; - * Enable USB pad function. - */ - uint32_t usb_pad_enable:1; - /** ahb_clk_force_on : R/W; bitpos: [19]; default: 0; - * Force ahb clock always on. - */ - uint32_t ahb_clk_force_on:1; - /** phy_clk_force_on : R/W; bitpos: [20]; default: 1; - * Force phy clock always on. - */ - uint32_t phy_clk_force_on:1; - uint32_t reserved_21:1; - /** dfifo_force_pu : R/W; bitpos: [22]; default: 0; - * Disable the dfifo to go into low power mode. The data in dfifo will not lost. - */ - uint32_t dfifo_force_pu:1; - uint32_t reserved_23:8; - /** clk_en : R/W; bitpos: [31]; default: 0; - * Disable auto clock gating of CSR registers. - */ - uint32_t clk_en:1; - }; - uint32_t val; -} usb_wrap_otg_conf_reg_t; - -/** Type of date register - * Date register. - */ -typedef union { - struct { - /** usb_wrap_date : HRO; bitpos: [31:0]; default: 587400452; - * Date register. - */ - uint32_t usb_wrap_date:32; - }; - uint32_t val; -} usb_wrap_date_reg_t; - - -typedef struct { - volatile usb_wrap_otg_conf_reg_t otg_conf; - uint32_t reserved_004[254]; - volatile usb_wrap_date_reg_t date; -} usb_wrap_dev_t; - -extern usb_wrap_dev_t USB_WRAP; - -#ifndef __cplusplus -_Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/system_retention_periph.c b/components/soc/esp32p4/system_retention_periph.c index bdb57a92d413..c563717c12c6 100644 --- a/components/soc/esp32p4/system_retention_periph.c +++ b/components/soc/esp32p4/system_retention_periph.c @@ -46,17 +46,23 @@ static const uint32_t l1_cache_regs_map[4] = {0x7, 0x0, 0xc000000, 0x0}; CACHE_L2_CACHE_ACS_FAIL_CTRL_REG & CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG */ #define L2_CACHE_RETENTION_REGS_CNT (6) #define L2_CACHE_RETENTION_REGS_BASE (CACHE_L2_CACHE_CTRL_REG) +#define L1_CACHE_ACS_FAIL_INR_CLR (CACHE_L1_ICACHE0_FAIL_INT_CLR | CACHE_L1_ICACHE1_FAIL_INT_CLR | CACHE_L1_ICACHE2_FAIL_INT_CLR | CACHE_L1_ICACHE3_FAIL_INT_CLR |CACHE_L1_DCACHE_FAIL_INT_CLR) +#define L1_CACHE_ACS_FAIL_INR_CLR_M (CACHE_L1_ICACHE0_FAIL_INT_CLR_M | CACHE_L1_ICACHE1_FAIL_INT_CLR_M | CACHE_L1_ICACHE2_FAIL_INT_CLR_M | CACHE_L1_ICACHE3_FAIL_INT_CLR_M |CACHE_L1_DCACHE_FAIL_INT_CLR_M) + static const uint32_t l2_cache_regs_map[4] = {0xc000000f, 0x0, 0x0, 0x0}; const regdma_entries_config_t cache_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x00), L1_CACHE_RETENTION_REGS_BASE, L1_CACHE_RETENTION_REGS_BASE, \ + // Clear the cache error status, since the auto clock gating added to the cache after version v3, it may falsely report cache acs fail when the module is reset. + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x00), CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG, L1_CACHE_ACS_FAIL_INR_CLR, L1_CACHE_ACS_FAIL_INR_CLR_M, 1, 0), .owner = ENTRY(0) }, + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x01), CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG, CACHE_L2_CACHE_FAIL_INT_CLR, CACHE_L2_CACHE_FAIL_INT_CLR_M, 1, 0), .owner = ENTRY(0) }, + [2] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x02), L1_CACHE_RETENTION_REGS_BASE, L1_CACHE_RETENTION_REGS_BASE, \ L1_CACHE_RETENTION_REGS_CNT, 0, 0, \ l1_cache_regs_map[0], l1_cache_regs_map[1], \ l1_cache_regs_map[2], l1_cache_regs_map[3]), \ .owner = ENTRY(0) }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x01), \ + [3] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x03), \ L2_CACHE_RETENTION_REGS_BASE, L2_CACHE_RETENTION_REGS_BASE, \ L2_CACHE_RETENTION_REGS_CNT, 0, 0, \ l2_cache_regs_map[0], l2_cache_regs_map[1], \ @@ -64,12 +70,16 @@ const regdma_entries_config_t cache_regs_retention[] = { .owner = ENTRY(0) }, // Invalidate L1 Cache - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x02), CACHE_SYNC_ADDR_REG, 0, CACHE_SYNC_ADDR_M, 1, 0), .owner = ENTRY(0) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x03), CACHE_SYNC_SIZE_REG, 0, CACHE_SYNC_SIZE_M, 1, 0), .owner = ENTRY(0) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x04), CACHE_SYNC_MAP_REG, CACHE_MAP_L1_CACHE_MASK, CACHE_SYNC_MAP_M, 1, 0), .owner = ENTRY(0) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x05), CACHE_SYNC_CTRL_REG, 0, CACHE_SYNC_RGID_M, 1, 0), .owner = ENTRY(0) }, - [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x06), CACHE_SYNC_CTRL_REG, CACHE_INVALIDATE_ENA, CACHE_INVALIDATE_ENA_M, 1, 0), .owner = ENTRY(0) }, - [7] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_CACHE_LINK(0x07), CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE, CACHE_SYNC_DONE_M, 1, 0), .owner = ENTRY(0) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x04), CACHE_SYNC_ADDR_REG, 0, CACHE_SYNC_ADDR_M, 1, 0), .owner = ENTRY(0) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x05), CACHE_SYNC_SIZE_REG, 0, CACHE_SYNC_SIZE_M, 1, 0), .owner = ENTRY(0) }, + [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x06), CACHE_SYNC_MAP_REG, CACHE_MAP_L1_CACHE_MASK, CACHE_SYNC_MAP_M, 1, 0), .owner = ENTRY(0) }, + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x07), CACHE_SYNC_CTRL_REG, 0, CACHE_SYNC_RGID_M, 1, 0), .owner = ENTRY(0) }, + [8] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x08), CACHE_SYNC_CTRL_REG, CACHE_INVALIDATE_ENA, CACHE_INVALIDATE_ENA_M, 1, 0), .owner = ENTRY(0) }, + [9] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_CACHE_LINK(0x09), CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE, CACHE_SYNC_DONE_M, 1, 0), .owner = ENTRY(0) }, + // Reset L2 CACHE SYNC + [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x10), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, CACHE_L2_CACHE_SYNC_RST, CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) }, + [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x11), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, 0, CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) }, + }; _Static_assert(ARRAY_SIZE(cache_regs_retention) == CACHE_RETENTION_LINK_LEN, "Inconsistent L2 CACHE retention link length definitions"); @@ -124,19 +134,23 @@ _Static_assert(ARRAY_SIZE(iomux_regs_retention) == IOMUX_RETENTION_LINK_LEN, "In #define N_REGS_SPI0_C_MEM_1() (((SPI_MEM_C_SMEM_AC_REG - SPI_MEM_C_FMEM__PMS0_ATTR_REG) / 4) + 1) #define N_REGS_SPI0_C_MEM_2() (1) #define N_REGS_SPI0_C_MEM_3() (((SPI_MEM_C_DPA_CTRL_REG - SPI_MEM_C_MMU_POWER_CTRL_REG) / 4) + 1) - +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 +#define FLASH_SPIMEM_RETENTION_ENTRY (ENTRY(0) | REGDMA_SW_TRIGGER_ENTRY) +#else +#define FLASH_SPIMEM_RETENTION_ENTRY ENTRY(0) +#endif const regdma_entries_config_t flash_spimem_regs_retention[] = { /* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */ - [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), DR_REG_FLASH_SPI1_BASE, DR_REG_FLASH_SPI1_BASE, N_REGS_SPI1_C_MEM_0(), 0, 0), .owner = ENTRY(0) }, /* spi1_mem */ - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI1_MEM_C_INT_ENA_REG, SPI1_MEM_C_INT_ENA_REG, N_REGS_SPI1_C_MEM_1(), 0, 0), .owner = ENTRY(0) }, - [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), SPI1_MEM_C_TIMING_CALI_REG, SPI1_MEM_C_TIMING_CALI_REG, N_REGS_SPI1_C_MEM_2(), 0, 0), .owner = ENTRY(0) }, + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), DR_REG_FLASH_SPI1_BASE, DR_REG_FLASH_SPI1_BASE, N_REGS_SPI1_C_MEM_0(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY }, /* spi1_mem */ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI1_MEM_C_INT_ENA_REG, SPI1_MEM_C_INT_ENA_REG, N_REGS_SPI1_C_MEM_1(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY }, + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), SPI1_MEM_C_TIMING_CALI_REG, SPI1_MEM_C_TIMING_CALI_REG, N_REGS_SPI1_C_MEM_2(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY }, /* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */ - [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), DR_REG_FLASH_SPI0_BASE, DR_REG_FLASH_SPI0_BASE, N_REGS_SPI0_C_MEM_0(), 0, 0), .owner = ENTRY(0) }, /* spi0_mem */ - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_C_FMEM__PMS0_ATTR_REG, SPI_MEM_C_FMEM__PMS0_ATTR_REG, N_REGS_SPI0_C_MEM_1(), 0, 0), .owner = ENTRY(0) }, - [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_C_CLOCK_GATE_REG, SPI_MEM_C_CLOCK_GATE_REG, N_REGS_SPI0_C_MEM_2(), 0, 0), .owner = ENTRY(0) }, - [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x07), SPI_MEM_C_MMU_POWER_CTRL_REG, SPI_MEM_C_MMU_POWER_CTRL_REG, N_REGS_SPI0_C_MEM_3(), 0, 0), .owner = ENTRY(0) }, - [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SPIMEM_LINK(0x08), SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CALI_UPDATE, SPI_MEM_C_TIMING_CALI_UPDATE_M, 1, 0), .owner = ENTRY(0) }, + [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), DR_REG_FLASH_SPI0_BASE, DR_REG_FLASH_SPI0_BASE, N_REGS_SPI0_C_MEM_0(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY }, /* spi0_mem */ + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_C_FMEM__PMS0_ATTR_REG, SPI_MEM_C_FMEM__PMS0_ATTR_REG, N_REGS_SPI0_C_MEM_1(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY }, + [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_C_CLOCK_GATE_REG, SPI_MEM_C_CLOCK_GATE_REG, N_REGS_SPI0_C_MEM_2(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY }, + [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x07), SPI_MEM_C_MMU_POWER_CTRL_REG, SPI_MEM_C_MMU_POWER_CTRL_REG, N_REGS_SPI0_C_MEM_3(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY }, + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SPIMEM_LINK(0x08), SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CALI_UPDATE, SPI_MEM_C_TIMING_CALI_UPDATE_M, 1, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY }, }; _Static_assert(ARRAY_SIZE(flash_spimem_regs_retention) == SPIMEM_FLASH_RETENTION_LINK_LEN, "Inconsistent Flash SPI Mem retention link length definitions"); diff --git a/components/soc/include/soc/mipi_dsi_periph.h b/components/soc/include/soc/mipi_dsi_periph.h index 1264c517b67a..6c48dfa8262e 100644 --- a/components/soc/include/soc/mipi_dsi_periph.h +++ b/components/soc/include/soc/mipi_dsi_periph.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,11 +8,14 @@ #include #include +#include "soc/soc_caps.h" #ifdef __cplusplus extern "C" { #endif +#if SOC_MIPI_DSI_SUPPORTED + /** * @brief MIPI DSI PHY PLL frequency range */ @@ -25,6 +28,14 @@ typedef struct { extern const soc_mipi_dsi_phy_pll_freq_range_t soc_mipi_dsi_phy_pll_ranges[]; extern const size_t num_of_soc_mipi_dsi_phy_pll_ranges; +typedef struct { + const int brg_irq_id; // interrupt source ID for MIPI DSI Bridge +} soc_mipi_dsi_signal_desc_t; + +extern const soc_mipi_dsi_signal_desc_t soc_mipi_dsi_signals[1]; // only one MIPI DSI peripheral + +#endif // SOC_MIPI_DSI_SUPPORTED + #ifdef __cplusplus } #endif diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c index 69eefb0be9df..795336b28771 100644 --- a/components/spi_flash/cache_utils.c +++ b/components/spi_flash/cache_utils.c @@ -930,28 +930,3 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable) return ESP_OK; } #endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 - -#if CONFIG_IDF_TARGET_ESP32P4 -//TODO: IDF-5670 -void IRAM_ATTR esp_config_l2_cache_mode(void) -{ - cache_size_t cache_size; - cache_line_size_t cache_line_size; -#if CONFIG_CACHE_L2_CACHE_128KB - cache_size = CACHE_SIZE_128K; -#elif CONFIG_CACHE_L2_CACHE_256KB - cache_size = CACHE_SIZE_256K; -#else - cache_size = CACHE_SIZE_512K; -#endif - -#if CONFIG_CACHE_L2_CACHE_LINE_64B - cache_line_size = CACHE_LINE_SIZE_64B; -#else - cache_line_size = CACHE_LINE_SIZE_128B; -#endif - - Cache_Set_L2_Cache_Mode(cache_size, 8, cache_line_size); - Cache_Invalidate_All(CACHE_MAP_L2_CACHE); -} -#endif diff --git a/components/ulp/test_apps/ulp_fsm/pytest_ulp_fsm_app.py b/components/ulp/test_apps/ulp_fsm/pytest_ulp_fsm_app.py index 9db9abb6a9e9..67c57f2ade55 100644 --- a/components/ulp/test_apps/ulp_fsm/pytest_ulp_fsm_app.py +++ b/components/ulp/test_apps/ulp_fsm/pytest_ulp_fsm_app.py @@ -1,6 +1,5 @@ # SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 - import pytest from pytest_embedded import Dut @@ -10,4 +9,4 @@ @pytest.mark.esp32s3 @pytest.mark.generic def test_ulp_fsm(dut: Dut) -> None: - dut.run_all_single_board_cases() + dut.run_all_single_board_cases(reset=True) diff --git a/components/usb/usb_phy.c b/components/usb/usb_phy.c index 9432b446cb55..9904e6055d0b 100644 --- a/components/usb/usb_phy.c +++ b/components/usb/usb_phy.c @@ -145,7 +145,22 @@ esp_err_t usb_phy_otg_set_mode(usb_phy_handle_t handle, usb_otg_mode_t mode) // USB-DWC2.0 <-> UTMI PHY // USB-DWC1.1 <-> FSLS PHY if (handle->target == USB_PHY_TARGET_UTMI) { - return ESP_OK; // No need to configure anything for UTMI PHY + // ESP32-P4 v3 changed connection between USB-OTG peripheral and UTMI PHY. + // On v3 the 15k pulldown resistors on D+/D- are no longer controlled by USB-OTG, + // but must be controlled directly by this software driver. +#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 +#include "soc/lp_system_struct.h" + if (mode == USB_OTG_MODE_HOST) { + // Host must connect 15k pulldown resistors on D+ / D- + LP_SYS.hp_usb_otghs_phy_ctrl.hp_utmiotg_dppulldown = 1; + LP_SYS.hp_usb_otghs_phy_ctrl.hp_utmiotg_dmpulldown = 1; + } else { + // Device must not connect any pulldown resistors on D+ / D- + LP_SYS.hp_usb_otghs_phy_ctrl.hp_utmiotg_dppulldown = 0; + LP_SYS.hp_usb_otghs_phy_ctrl.hp_utmiotg_dmpulldown = 0; + } +#endif // !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 + return ESP_OK; } const usb_otg_signal_conn_t *otg_sig = usb_dwc_info.controllers[otg11_index].otg_signals; diff --git a/components/wpa_supplicant/CMakeLists.txt b/components/wpa_supplicant/CMakeLists.txt index 11421167d1a3..b066ee51c8bf 100644 --- a/components/wpa_supplicant/CMakeLists.txt +++ b/components/wpa_supplicant/CMakeLists.txt @@ -264,7 +264,6 @@ target_compile_definitions(${COMPONENT_LIB} PRIVATE EAP_PEAP USE_WPA2_TASK CONFIG_WPS - USE_WPS_TASK ESPRESSIF_USE CONFIG_ECC CONFIG_IEEE80211W @@ -288,6 +287,9 @@ endif() if(CONFIG_ESP_WIFI_WPS_STRICT) target_compile_definitions(${COMPONENT_LIB} PRIVATE CONFIG_WPS_STRICT) endif() +if(CONFIG_ESP_WIFI_WPS_RECONNECT_ON_FAIL) + target_compile_definitions(${COMPONENT_LIB} PRIVATE CONFIG_WPS_RECONNECT_ON_FAIL) +endif() if(CONFIG_ESP_WIFI_SUITE_B_192) target_compile_definitions(${COMPONENT_LIB} PRIVATE CONFIG_SUITEB192) endif() diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_wps.c b/components/wpa_supplicant/esp_supplicant/src/esp_wps.c index 933235270abb..186571237a7c 100644 --- a/components/wpa_supplicant/esp_supplicant/src/esp_wps.c +++ b/components/wpa_supplicant/esp_supplicant/src/esp_wps.c @@ -4,6 +4,18 @@ * SPDX-License-Identifier: Apache-2.0 */ +/* + This file implements the WPS Enrollee logic, which allows an ESP device to connect + to a WPS-enabled Access Point using either the Push-Button Configuration (PBC) or + PIN method. It handles the WPS state machine, EAPOL frame exchange, and credential + reception. + + The implementation relies on a global state machine (gWpsSm) and interacts with the + main Wi-Fi task via an event loop (eloop). Public API functions are provided to + enable, disable, and start the WPS process, with mutexes ensuring thread safety + at the API boundary. +*/ + #include #include @@ -31,221 +43,47 @@ #include "eap_common/eap_wsc_common.h" #include "esp_wpas_glue.h" +#ifdef CONFIG_WPS_RECONNECT_ON_FAIL +static wifi_config_t *s_previous_wifi_config = NULL; +#endif + +// WPS Timeout Constants (in seconds) +static const int WPS_TOTAL_TIMEOUT_SECS = 120; +static const int WPS_CONNECT_TIMEOUT_SECS = 20; +static const int EAPOL_START_HANDLE_TIMEOUT_SECS = 3; +static const int WPS_MSG_TIMEOUT_M2_SECS = 20; +static const int WPS_MSG_TIMEOUT_FINISH_SECS = 5; +static const int WPS_POST_M8_WORKAROUND_SECS = 2; +static const int WPS_SUCCESS_EVENT_TIMEOUT_SECS = 1; +static const int WPS_SCAN_RETRY_TIMEOUT_SECS = 2; + +// Callback structure for handling WPS events within the Wi-Fi task +static struct wps_sm_funcs *s_wps_sm_cb = NULL; + const char *wps_model_number = CONFIG_IDF_TARGET; +/* API lock to ensure thread safety for public WPS functions */ void *s_wps_api_lock = NULL; /* Used in WPS/WPS-REG public API only, never be freed */ void *s_wps_api_sem = NULL; /* Sync semaphore used between WPS/WPS-REG public API caller task and WPS task, never be freed */ +/* Synchronous flag to indicate if the WPS feature is enabled by the user. Protected by s_wps_api_lock. */ bool s_wps_enabled = false; -#ifdef USE_WPS_TASK -struct wps_rx_param { - u8 sa[ETH_ALEN]; - u8 *buf; - int len; - STAILQ_ENTRY(wps_rx_param) bqentry; -}; -static STAILQ_HEAD(, wps_rx_param) s_wps_rxq; - -static struct wps_sm_funcs *s_wps_sm_cb = NULL; -static void *s_wps_task_hdl = NULL; -static void *s_wps_queue = NULL; -static void *s_wps_data_lock = NULL; -static void *s_wps_task_create_sem = NULL; -static uint8_t s_wps_sig_cnt[SIG_WPS_NUM] = {0}; +static void wifi_wps_scan_done(void *arg, ETS_STATUS status); -#endif - -void wifi_wps_scan_done(void *arg, ETS_STATUS status); -void wifi_wps_scan(void *data, void *user_ctx); -int wifi_station_wps_start(void); -int wps_sm_rx_eapol_internal(u8 *src_addr, u8 *buf, u32 len); -void wifi_wps_start_internal(void); -int wifi_wps_enable_internal(const esp_wps_config_t *config); -int wifi_wps_disable_internal(void); -void wifi_station_wps_timeout_internal(void); -void wifi_station_wps_msg_timeout_internal(void); -void wifi_station_wps_success_internal(void); -void wifi_wps_scan_internal(void); -void wifi_station_wps_eapol_start_handle_internal(void); -void wps_add_discard_ap(u8 *bssid); - -void wifi_station_wps_msg_timeout(void *data, void *user_ctx); +static void wifi_wps_scan(void *data, void *user_ctx); +static int wifi_station_wps_start(void *data, void *user_ctx); +static int wifi_wps_enable_internal(void *ctx, void *data); +static int wifi_wps_disable_internal(void *ctx, void *data); +static void wifi_station_wps_msg_timeout(void *data, void *user_ctx); void wifi_station_wps_eapol_start_handle(void *data, void *user_ctx); -void wifi_station_wps_success(void *data, void *user_ctx); -void wifi_station_wps_timeout(void *data, void *user_ctx); -int wps_delete_timer(void); +static void wifi_station_wps_success(void *data, void *user_ctx); +static void wifi_station_wps_timeout(void *data, void *user_ctx); +static int wps_delete_timer(void); +static int wps_finish(void); struct wps_sm *gWpsSm = NULL; +static wifi_event_sta_wps_er_success_t s_wps_success_evt; static wps_factory_information_t *s_factory_info = NULL; -static void wps_rxq_init(void) -{ - DATA_MUTEX_TAKE(); - STAILQ_INIT(&s_wps_rxq); - DATA_MUTEX_GIVE(); -} - -static void wps_rxq_enqueue(struct wps_rx_param *param) -{ - DATA_MUTEX_TAKE(); - STAILQ_INSERT_TAIL(&s_wps_rxq, param, bqentry); - DATA_MUTEX_GIVE(); -} - -static struct wps_rx_param * wps_rxq_dequeue(void) -{ - struct wps_rx_param *param = NULL; - DATA_MUTEX_TAKE(); - if ((param = STAILQ_FIRST(&s_wps_rxq)) != NULL) { - STAILQ_REMOVE_HEAD(&s_wps_rxq, bqentry); - STAILQ_NEXT(param, bqentry) = NULL; - } - DATA_MUTEX_GIVE(); - return param; -} - -static void wps_rxq_deinit(void) -{ - struct wps_rx_param *param = NULL; - DATA_MUTEX_TAKE(); - while ((param = STAILQ_FIRST(&s_wps_rxq)) != NULL) { - STAILQ_REMOVE_HEAD(&s_wps_rxq, bqentry); - STAILQ_NEXT(param, bqentry) = NULL; - os_free(param->buf); - os_free(param); - } - DATA_MUTEX_GIVE(); -} - -#ifdef USE_WPS_TASK -void wps_task(void *pvParameters) -{ - ETSEvent e; - wps_ioctl_param_t *param; - bool del_task = false; - - os_semphr_give(s_wps_task_create_sem); - - wpa_printf(MSG_DEBUG, "wps_Task enter"); - for (;;) { - if (TRUE == os_queue_recv(s_wps_queue, &e, OS_BLOCK)) { - - if ((e.sig >= SIG_WPS_ENABLE) && (e.sig < SIG_WPS_NUM)) { - DATA_MUTEX_TAKE(); - if (s_wps_sig_cnt[e.sig]) { - s_wps_sig_cnt[e.sig]--; - } else { - wpa_printf(MSG_ERROR, "wpsT: invalid sig cnt, sig=%" PRId32 " cnt=%d", e.sig, s_wps_sig_cnt[e.sig]); - } - DATA_MUTEX_GIVE(); - } - - wpa_printf(MSG_DEBUG, "wpsT: rx sig=%" PRId32 "", e.sig); - - switch (e.sig) { - case SIG_WPS_ENABLE: - case SIG_WPS_DISABLE: - case SIG_WPS_START: - param = (wps_ioctl_param_t *)e.par; - if (!param) { - wpa_printf(MSG_ERROR, "wpsT: invalid param sig=%" PRId32 "", e.sig); - os_semphr_give(s_wps_api_sem); - break; - } - - if (e.sig == SIG_WPS_ENABLE) { - param->ret = wifi_wps_enable_internal((esp_wps_config_t *)(param->arg)); - } else if (e.sig == SIG_WPS_DISABLE) { - DATA_MUTEX_TAKE(); - param->ret = wifi_wps_disable_internal(); - del_task = true; - s_wps_task_hdl = NULL; - DATA_MUTEX_GIVE(); - } else { - param->ret = wifi_station_wps_start(); - } - - os_semphr_give(s_wps_api_sem); - break; - - case SIG_WPS_RX: { - struct wps_rx_param *param = NULL; - while ((param = wps_rxq_dequeue()) != NULL) { - wps_sm_rx_eapol_internal(param->sa, param->buf, param->len); - os_free(param->buf); - os_free(param); - } - break; - } - - case SIG_WPS_TIMER_TIMEOUT: - wifi_station_wps_timeout_internal(); - break; - - case SIG_WPS_TIMER_MSG_TIMEOUT: - wifi_station_wps_msg_timeout_internal(); - break; - - case SIG_WPS_TIMER_SUCCESS_CB: - wifi_station_wps_success_internal(); - break; - - case SIG_WPS_TIMER_SCAN: - wifi_wps_scan_internal(); - break; - - case SIG_WPS_TIMER_EAPOL_START: - wifi_station_wps_eapol_start_handle_internal(); - break; - - default: - wpa_printf(MSG_ERROR, "wpsT: invalid sig=%" PRId32 "", e.sig); - break; - } - - if (del_task) { - wpa_printf(MSG_DEBUG, "wpsT: delete task"); - break; - } - } - } - os_task_delete(NULL); -} - -/* wps_post() is thread-safe - * - */ -int wps_post(uint32_t sig, uint32_t par) -{ - wpa_printf(MSG_DEBUG, "wps post: sig=%" PRId32 " cnt=%d", sig, s_wps_sig_cnt[sig]); - ETSEvent evt; - - if (!s_wps_task_hdl) { - wpa_printf(MSG_DEBUG, "wps post: sig=%" PRId32 " failed as wps task has been deinited", sig); - return ESP_FAIL; - } - DATA_MUTEX_TAKE(); - if (s_wps_sig_cnt[sig]) { - wpa_printf(MSG_DEBUG, "wps post: sig=%" PRId32 " processing", sig); - DATA_MUTEX_GIVE(); - return ESP_OK; - } - - s_wps_sig_cnt[sig]++; - evt.sig = sig; - evt.par = par; - DATA_MUTEX_GIVE(); - - if (os_queue_send(s_wps_queue, &evt, os_task_ms_to_tick(10)) != TRUE) { - wpa_printf(MSG_ERROR, "WPS: Q S E"); - DATA_MUTEX_TAKE(); - s_wps_sig_cnt[sig]--; - DATA_MUTEX_GIVE(); - return ESP_FAIL; - } - return ESP_OK; -} -#endif - /* * wps_sm_ether_send - Send Ethernet frame * @wpa_s: Pointer to wpa_supplicant data @@ -261,34 +99,37 @@ static inline int wps_sm_ether_send(struct wps_sm *sm, u16 proto, int ret = esp_wifi_get_assoc_bssid_internal(bssid); if (ret != 0) { - wpa_printf(MSG_ERROR, "bssid is empty!"); + wpa_printf(MSG_ERROR, "WPS: BSSID is empty, cannot send EAPOL frame"); return -1; } return wpa_ether_send(sm, bssid, proto, data, data_len); } -u8 *wps_sm_alloc_eapol(struct wps_sm *sm, u8 type, - const void *data, u16 data_len, - size_t *msg_len, void **data_pos) +static inline u8 *wps_sm_alloc_eapol(struct wps_sm *sm, u8 type, + const void *data, u16 data_len, + size_t *msg_len, void **data_pos) { return wpa_alloc_eapol(sm, type, data, data_len, msg_len, data_pos); } -void wps_sm_free_eapol(u8 *buffer) +static inline void wps_sm_free_eapol(u8 *buffer) { return wpa_free_eapol(buffer); } -static void -wps_build_ic_appie_wps_pr(void) +static void wps_build_ic_appie_wps_pr(void) { + struct wps_sm *sm = wps_sm_get(); struct wpabuf *extra_ie = NULL; struct wpabuf *wps_ie; - struct wps_sm *sm = gWpsSm; u16 pw_id; - wpa_printf(MSG_DEBUG, "wps build: wps pr"); + if (!sm) { + return; + } + + wpa_printf(MSG_DEBUG, "WPS: Building Probe Request IE"); if (wps_get_type() == WPS_TYPE_PBC) { pw_id = DEV_PW_PUSHBUTTON; @@ -314,12 +155,11 @@ wps_build_ic_appie_wps_pr(void) wpabuf_free(extra_ie); } -static void -wps_build_ic_appie_wps_ar(void) +static void wps_build_ic_appie_wps_ar(void) { struct wpabuf *buf = wps_build_assoc_req_ie(WPS_REQ_ENROLLEE); - wpa_printf(MSG_DEBUG, "wps build: wps ar"); + wpa_printf(MSG_DEBUG, "WPS: Building Association Request IE"); if (buf) { esp_wifi_set_appie_internal(WIFI_APPIE_WPS_AR, (uint8_t *)wpabuf_head(buf), buf->used, 0); @@ -327,7 +167,34 @@ wps_build_ic_appie_wps_ar(void) } } -static bool ap_supports_sae(struct wps_scan_ie *scan) +static int wps_send_eapol_frame(u8 eapol_type, const void *payload, size_t payload_len) +{ + struct wps_sm *sm = gWpsSm; + u8 *buf; + int len; + int ret; + + if (!sm) { + return ESP_FAIL; + } + + buf = wps_sm_alloc_eapol(sm, eapol_type, payload, payload_len, (size_t *)&len, NULL); + if (!buf) { + wpa_printf(MSG_ERROR, "WPS: EAPOL buffer allocation failed"); + return ESP_ERR_NO_MEM; + } + + ret = wps_sm_ether_send(sm, ETH_P_EAPOL, buf, len); + wps_sm_free_eapol(buf); + + if (ret) { + wpa_printf(MSG_ERROR, "WPS: EAPOL send failed (ret=%d)", ret); + return ESP_FAIL; + } + return ESP_OK; +} + +static bool is_ap_supports_sae(struct wps_scan_ie *scan) { struct wpa_ie_data rsn_info; @@ -344,8 +211,7 @@ static bool ap_supports_sae(struct wps_scan_ie *scan) return false; } -static bool -is_wps_pbc_overlap(struct wps_sm *sm, const u8 *sel_uuid) +static bool is_wps_pbc_overlap(struct wps_sm *sm, const u8 *sel_uuid) { if (!sel_uuid) { wpa_printf(MSG_DEBUG, "WPS: null uuid field"); @@ -353,7 +219,7 @@ is_wps_pbc_overlap(struct wps_sm *sm, const u8 *sel_uuid) } if (os_memcmp(sel_uuid, sm->uuid_r, WPS_UUID_LEN) != 0) { - wpa_printf(MSG_DEBUG, "uuid is not same"); + wpa_printf(MSG_DEBUG, "WPS: Scanned BSS UUID does not match"); wpa_hexdump(MSG_DEBUG, "WPS: UUID of scanned BSS is", sel_uuid, WPS_UUID_LEN); wpa_hexdump(MSG_DEBUG, "WPS: UUID of sm BSS is", @@ -364,12 +230,15 @@ is_wps_pbc_overlap(struct wps_sm *sm, const u8 *sel_uuid) return false; } -static bool -wps_parse_scan_result(struct wps_scan_ie *scan) +static bool wps_parse_scan_result(struct wps_scan_ie *scan) { - struct wps_sm *sm = gWpsSm; + struct wps_sm *sm = wps_sm_get(); wifi_mode_t op_mode = 0; + if (!sm) { + return false; + } + if (sm->wps_pbc_overlap) { return false; } @@ -395,40 +264,22 @@ wps_parse_scan_result(struct wps_scan_ie *scan) } if (!scan->rsn && !scan->wpa && (scan->capinfo & WLAN_CAPABILITY_PRIVACY)) { - wpa_printf(MSG_DEBUG, "WEP not suppported in WPS"); - return false; - } - - if (sm->ignore_sel_reg && !is_zero_ether_addr(sm->bssid)) { - /* We have selected candidate for this scan */ + wpa_printf(MSG_DEBUG, "WPS: WEP not supported, skipping AP"); return false; } if (scan->wps) { bool ap_found = false; struct wpabuf *buf = wpabuf_alloc_copy(scan->wps + 6, scan->wps[1] - 4); - int count; const u8 *scan_uuid; if ((wps_get_type() == WPS_TYPE_PBC && wps_is_selected_pbc_registrar(buf)) || (wps_get_type() == WPS_TYPE_PIN && wps_is_addr_authorized(buf, sm->ownaddr, 1))) { /* Found one AP with selected registrar true */ - sm->ignore_sel_reg = false; - sm->discard_ap_cnt = 0; ap_found = true; } - if (wps_get_type() == WPS_TYPE_PIN && sm->ignore_sel_reg) { - /* AP is in discard list? */ - for (count = 0; count < WPS_MAX_DIS_AP_NUM; count++) { - if (os_memcmp(sm->dis_ap_list[count].bssid, scan->bssid, ETH_ALEN) == 0) { - wpa_printf(MSG_INFO, "discard ap bssid "MACSTR, MAC2STR(scan->bssid)); - wpabuf_free(buf); - return false; - } - } - } - if (ap_found || sm->ignore_sel_reg) { + if (ap_found) { if (scan->ssid[1] > SSID_MAX_LEN) { wpabuf_free(buf); return false; @@ -438,15 +289,15 @@ wps_parse_scan_result(struct wps_scan_ie *scan) os_memcpy(sm->creds[0].ssid, (char *)&scan->ssid[2], (int)scan->ssid[1]); sm->creds[0].ssid_len = scan->ssid[1]; if (scan->bssid && memcmp(sm->bssid, scan->bssid, ETH_ALEN) != 0) { - wpa_printf(MSG_INFO, "sm BSSid: "MACSTR " scan BSSID " MACSTR, + wpa_printf(MSG_DEBUG, "WPS: BSSID changed from " MACSTR " to " MACSTR, MAC2STR(sm->bssid), MAC2STR(scan->bssid)); sm->discover_ssid_cnt++; - wpa_printf(MSG_INFO, "discoverd cnt is %d and chan is %d ", sm->discover_ssid_cnt, scan->chan); + wpa_printf(MSG_DEBUG, "WPS: AP discovery count: %d, channel: %d ", sm->discover_ssid_cnt, scan->chan); os_memcpy(sm->bssid, scan->bssid, ETH_ALEN); scan_uuid = wps_get_uuid_e(buf); if (sm->discover_ssid_cnt > 1 && wps_get_type() == WPS_TYPE_PBC && is_wps_pbc_overlap(sm, scan_uuid) == true) { - wpa_printf(MSG_INFO, "pbc_overlap flag is true"); + wpa_printf(MSG_WARNING, "WPS: PBC overlap detected"); sm->wps_pbc_overlap = true; wpabuf_free(buf); return false; @@ -455,8 +306,8 @@ wps_parse_scan_result(struct wps_scan_ie *scan) os_memcpy(sm->uuid_r, scan_uuid, WPS_UUID_LEN); } - if (ap_supports_sae(scan)) { - wpa_printf(MSG_INFO, "AP supports SAE, get password in passphrase"); + if (is_ap_supports_sae(scan)) { + wpa_printf(MSG_INFO, "WPS: AP supports SAE"); sm->dev->config_methods |= WPS_CONFIG_DISPLAY | WPS_CONFIG_VIRT_DISPLAY; sm->wps->wps->config_methods |= WPS_CONFIG_DISPLAY | WPS_CONFIG_VIRT_DISPLAY; /* Reset assoc req, probe reset not needed */ @@ -464,7 +315,7 @@ wps_parse_scan_result(struct wps_scan_ie *scan) } } wpabuf_free(buf); - wpa_printf(MSG_DEBUG, "wps discover [%s] ", (char *)sm->creds[0].ssid); + wpa_printf(MSG_INFO, "WPS AP discovered: %s", (char *)sm->creds[0].ssid); sm->channel = scan->chan; return true; @@ -475,54 +326,39 @@ wps_parse_scan_result(struct wps_scan_ie *scan) return false; } -int wps_send_eap_identity_rsp(u8 id) +static int wps_send_eap_identity_rsp(u8 id) { - struct wps_sm *sm = gWpsSm; + struct wps_sm *sm = wps_sm_get(); struct wpabuf *eap_buf = NULL; - u8 *buf = NULL; - int len; int ret = ESP_OK; - wpa_printf(MSG_DEBUG, "wps send eapol id rsp"); + if (!sm) { + return ESP_FAIL; + } + + wpa_printf(MSG_DEBUG, "WPS: Sending EAP-Identity Response"); eap_buf = eap_msg_alloc(EAP_VENDOR_IETF, EAP_TYPE_IDENTITY, sm->identity_len, EAP_CODE_RESPONSE, id); if (!eap_buf) { - wpa_printf(MSG_ERROR, "eap buf allocation failed"); - ret = ESP_FAIL; - goto _err; + wpa_printf(MSG_ERROR, "WPS: EAP buffer allocation failed"); + return ESP_ERR_NO_MEM; } wpabuf_put_data(eap_buf, sm->identity, sm->identity_len); - buf = wps_sm_alloc_eapol(sm, IEEE802_1X_TYPE_EAP_PACKET, wpabuf_head_u8(eap_buf), wpabuf_len(eap_buf), (size_t *)&len, NULL); - if (!buf) { - wpa_printf(MSG_ERROR, "buf allocation failed"); - ret = ESP_ERR_NO_MEM; - goto _err; - } + ret = wps_send_eapol_frame(IEEE802_1X_TYPE_EAP_PACKET, wpabuf_head(eap_buf), wpabuf_len(eap_buf)); - ret = wps_sm_ether_send(sm, ETH_P_EAPOL, buf, len); - if (ret) { - wpa_printf(MSG_ERROR, "wps sm ether send failed ret=%d", ret); - ret = ESP_FAIL; - goto _err; - } - -_err: - wps_sm_free_eapol(buf); wpabuf_free(eap_buf); return ret; } -int wps_send_frag_ack(u8 id) +static int wps_send_frag_ack(u8 id) { - struct wps_sm *sm = gWpsSm; + struct wps_sm *sm = wps_sm_get(); struct wpabuf *eap_buf = NULL; - u8 *buf; - int len; - int ret = 0; + int ret = ESP_OK; - wpa_printf(MSG_DEBUG, "send frag ack id:%d", id); + wpa_printf(MSG_DEBUG, "WPS: Sending EAP-WSC Frag-ACK (id:%d)", id); if (!sm) { return ESP_FAIL; @@ -530,47 +366,31 @@ int wps_send_frag_ack(u8 id) eap_buf = eap_wsc_build_frag_ack(id, EAP_CODE_RESPONSE); if (!eap_buf) { - ret = ESP_ERR_NO_MEM; - goto _err; - } - - buf = wps_sm_alloc_eapol(sm, IEEE802_1X_TYPE_EAP_PACKET, wpabuf_head_u8(eap_buf), wpabuf_len(eap_buf), (size_t *)&len, NULL); - if (!buf) { - ret = ESP_ERR_NO_MEM; - goto _err; + return ESP_ERR_NO_MEM; } - ret = wps_sm_ether_send(sm, ETH_P_EAPOL, buf, len); - wps_sm_free_eapol(buf); - if (ret) { - ret = ESP_ERR_NO_MEM; - goto _err; - } + ret = wps_send_eapol_frame(IEEE802_1X_TYPE_EAP_PACKET, wpabuf_head(eap_buf), wpabuf_len(eap_buf)); -_err: wpabuf_free(eap_buf); + return ret; } -int wps_enrollee_process_msg_frag(struct wpabuf **buf, int tot_len, u8 *frag_data, int frag_len, u8 flag) +static int wps_enrollee_process_msg_frag(struct wpabuf **buf, int tot_len, u8 *frag_data, int frag_len, u8 flag) { - struct wps_sm *sm = gWpsSm; + struct wps_sm *sm = wps_sm_get(); u8 identifier; - if (!sm) { + if (!sm || !buf || !frag_data) { + wpa_printf(MSG_ERROR, "WPS: %s: Invalid arguments", __func__); return ESP_FAIL; } identifier = sm->current_identifier; - if (buf == NULL || frag_data == NULL) { - wpa_printf(MSG_ERROR, "fun:%s. line:%d, frag buf or frag data is null", __FUNCTION__, __LINE__); - return ESP_FAIL; - } - if (*buf == NULL) { if (0 == (flag & WPS_MSG_FLAG_LEN) || tot_len < frag_len) { - wpa_printf(MSG_ERROR, "fun:%s. line:%d, flag error:%02x", __FUNCTION__, __LINE__, flag); + wpa_printf(MSG_ERROR, "WPS: %s: Invalid fragment flag: 0x%02x", __FUNCTION__, flag); return ESP_FAIL; } @@ -584,7 +404,7 @@ int wps_enrollee_process_msg_frag(struct wpabuf **buf, int tot_len, u8 *frag_dat } if (flag & WPS_MSG_FLAG_LEN) { - wpa_printf(MSG_ERROR, "fun:%s. line:%d, flag error:%02x", __FUNCTION__, __LINE__, flag); + wpa_printf(MSG_ERROR, "WPS: %s: Invalid fragment flag: 0x%02x", __func__, flag); return ESP_FAIL; } @@ -597,9 +417,22 @@ int wps_enrollee_process_msg_frag(struct wpabuf **buf, int tot_len, u8 *frag_dat return ESP_OK; } -int wps_process_wps_mX_req(u8 *ubuf, int len, enum wps_process_res *res) +static void wifi_station_wps_post_m8_timeout(void *data, void *user_ctx) { - struct wps_sm *sm = gWpsSm; + struct wps_sm *sm = wps_sm_get(); + + if (sm && sm->post_m8_recv) { + wpa_printf(MSG_DEBUG, "WPS: M8 workaround timeout, success!"); + sm->wps->state = WPS_FINISHED; + /* Reset it here so that deauth won't call wps finish again */ + sm->post_m8_recv = false; + wps_finish(); + } +}; + +static int wps_process_wps_mX_req(u8 *ubuf, int len, enum wps_process_res *res) +{ + struct wps_sm *sm = wps_sm_get(); static struct wpabuf *wps_buf = NULL; struct eap_expand *expd; int tlen = 0; @@ -613,18 +446,17 @@ int wps_process_wps_mX_req(u8 *ubuf, int len, enum wps_process_res *res) } expd = (struct eap_expand *) ubuf; - wpa_printf(MSG_DEBUG, "wps process mX req: len %d, tlen %d", len, tlen); + wpa_printf(MSG_DEBUG, "WPS: Processing WSC message (len=%d, total_len=%d)", len, tlen); if (sm->state == WAIT_START) { if (expd->opcode != WSC_Start) { - wpa_printf(MSG_DEBUG, "EAP-WSC: Unexpected Op-Code %d " - "in WAIT_START state", expd->opcode); + wpa_printf(MSG_WARNING, "WPS: Unexpected Op-Code %d in WAIT_START state", expd->opcode); return ESP_ERR_INVALID_STATE; } - wpa_printf(MSG_DEBUG, "EAP-WSC: Received start"); + wpa_printf(MSG_DEBUG, "WPS: Received EAP-WSC Start"); sm->state = WPA_MESG; } else if (expd->opcode == WSC_Start) { - wpa_printf(MSG_DEBUG, "EAP-WSC: Unexpected Op-Code %d", + wpa_printf(MSG_WARNING, "WPS: Unexpected Op-Code %d", expd->opcode); return ESP_ERR_INVALID_STATE; } @@ -642,11 +474,11 @@ int wps_process_wps_mX_req(u8 *ubuf, int len, enum wps_process_res *res) } if (tlen > 50000) { - wpa_printf(MSG_ERROR, "EAP-WSC: Invalid Message Length"); + wpa_printf(MSG_ERROR, "WPS: Invalid EAP-WSC message length"); return ESP_FAIL; } if ((flag & WPS_MSG_FLAG_MORE) || wps_buf != NULL) {//frag msg - wpa_printf(MSG_DEBUG, "rx frag msg id:%d, flag:%d, frag_len: %d, tot_len: %d, be_tot_len:%d", sm->current_identifier, flag, frag_len, tlen, be_tot_len); + wpa_printf(MSG_DEBUG, "WPS: Received fragment (id=%d, flag=0x%x, frag_len=%d, total_len=%d)", sm->current_identifier, flag, frag_len, tlen); if (ESP_OK != wps_enrollee_process_msg_frag(&wps_buf, tlen, tbuf, frag_len, flag)) { if (wps_buf) { wpabuf_free(wps_buf); @@ -660,7 +492,7 @@ int wps_process_wps_mX_req(u8 *ubuf, int len, enum wps_process_res *res) } } else { //not frag msg if (wps_buf) {//if something wrong, frag msg buf is not freed, free first - wpa_printf(MSG_ERROR, "something is wrong, frag buf is not freed"); + wpa_printf(MSG_ERROR, "WPS: Fragment buffer not freed before receiving new message"); wpabuf_free(wps_buf); wps_buf = NULL; } @@ -675,6 +507,13 @@ int wps_process_wps_mX_req(u8 *ubuf, int len, enum wps_process_res *res) *res = wps_enrollee_process_msg(sm->wps, expd->opcode, wps_buf); + if (*res == WPS_CONTINUE && sm->wps->state == WPS_MSG_DONE) { + wpa_printf(MSG_DEBUG, "WPS: M8 processed, starting workaround timer"); + sm->post_m8_recv = true; + eloop_cancel_timeout(wifi_station_wps_post_m8_timeout, NULL, NULL); + eloop_register_timeout(WPS_POST_M8_WORKAROUND_SECS, 0, wifi_station_wps_post_m8_timeout, NULL, NULL); + } + if (*res == WPS_FAILURE) { sm->state = WPA_FAIL; } @@ -686,17 +525,15 @@ int wps_process_wps_mX_req(u8 *ubuf, int len, enum wps_process_res *res) return ESP_OK; } -int wps_send_wps_mX_rsp(u8 id) +static int wps_send_wps_mX_rsp(u8 id) { - struct wps_sm *sm = gWpsSm; + struct wps_sm *sm = wps_sm_get(); struct wpabuf *eap_buf = NULL; struct wpabuf *wps_buf = NULL; - u8 *buf; - int len; - int ret = 0; + int ret = ESP_OK; enum wsc_op_code opcode; - wpa_printf(MSG_DEBUG, "wps send wps mX rsp"); + wpa_printf(MSG_DEBUG, "WPS: Sending WSC Message"); if (!sm) { return ESP_FAIL; @@ -704,131 +541,131 @@ int wps_send_wps_mX_rsp(u8 id) wps_buf = wps_enrollee_get_msg(sm->wps, &opcode); if (!wps_buf) { - ret = ESP_FAIL; - goto _err; + return ESP_FAIL; } eap_buf = eap_msg_alloc(EAP_VENDOR_WFA, 0x00000001, wpabuf_len(wps_buf) + 2, EAP_CODE_RESPONSE, id); if (!eap_buf) { - ret = ESP_FAIL; - goto _err; + wpabuf_free(wps_buf); + return ESP_ERR_NO_MEM; } wpabuf_put_u8(eap_buf, opcode); wpabuf_put_u8(eap_buf, 0x00); /* flags */ - wpabuf_put_data(eap_buf, wpabuf_head_u8(wps_buf), wpabuf_len(wps_buf)); - + wpabuf_put_data(eap_buf, wpabuf_head(wps_buf), wpabuf_len(wps_buf)); wpabuf_free(wps_buf); - buf = wps_sm_alloc_eapol(sm, IEEE802_1X_TYPE_EAP_PACKET, wpabuf_head_u8(eap_buf), wpabuf_len(eap_buf), (size_t *)&len, NULL); - if (!buf) { - ret = ESP_FAIL; - goto _err; - } - - ret = wps_sm_ether_send(sm, ETH_P_EAPOL, buf, len); - wps_sm_free_eapol(buf); - if (ret) { - ret = ESP_FAIL; - goto _err; - } + ret = wps_send_eapol_frame(IEEE802_1X_TYPE_EAP_PACKET, wpabuf_head(eap_buf), wpabuf_len(eap_buf)); -_err: wpabuf_free(eap_buf); return ret; } -int wps_tx_start(void) +static int wps_tx_start(void) { - struct wps_sm *sm = gWpsSm; - u8 *buf; - int len; + wpa_printf(MSG_DEBUG, "WPS: Sending EAPOL-Start"); - if (!sm) { + if (wps_send_eapol_frame(IEEE802_1X_TYPE_EAPOL_START, (u8 *)"", 0) != ESP_OK) { return ESP_FAIL; } - wpa_printf(MSG_DEBUG, "WPS: Send EAPOL START."); - buf = wps_sm_alloc_eapol(sm, IEEE802_1X_TYPE_EAPOL_START, (u8 *)"", 0, (size_t *)&len, NULL); - if (!buf) { - return ESP_ERR_NO_MEM; - } - - wps_sm_ether_send(sm, ETH_P_EAPOL, buf, len); - wps_sm_free_eapol(buf); - - eloop_register_timeout(3, 0, wifi_station_wps_eapol_start_handle, NULL, NULL); + eloop_cancel_timeout(wifi_station_wps_eapol_start_handle, NULL, NULL); + eloop_register_timeout(EAPOL_START_HANDLE_TIMEOUT_SECS, 0, wifi_station_wps_eapol_start_handle, NULL, NULL); return ESP_OK; } -int wps_start_pending(void) +static int wps_start_pending(void) { - if (!gWpsSm) { + if (!wps_sm_get()) { return ESP_FAIL; } - wpa_printf(MSG_DEBUG, "wps start pending"); + wpa_printf(MSG_DEBUG, "WPS: Pending start, sending EAPOL-Start"); return wps_tx_start(); } -static void wps_stop_connection_timers(struct wps_sm *sm) +static int wps_send_event_and_disable(int32_t event_id, void* event_data, size_t data_len) { - esp_wifi_disarm_sta_connection_timer_internal(); - eloop_cancel_timeout(wifi_station_wps_msg_timeout, NULL, NULL); - eloop_cancel_timeout(wifi_station_wps_success, NULL, NULL); -} + if (gWpsSm == NULL) { + return 0; + } -static int wps_sm_init(struct wps_sm *sm) -{ - if (!sm) { - return -1; +#ifdef CONFIG_WPS_RECONNECT_ON_FAIL + /* On failure, reconnect to the previous AP if one was saved */ + if (s_previous_wifi_config) { + wpa_printf(MSG_INFO, "WPS failed, reconnecting to previous AP: %s", (char *)s_previous_wifi_config->sta.ssid); + esp_wifi_set_config(WIFI_IF_STA, s_previous_wifi_config); + esp_wifi_connect(); + os_free(s_previous_wifi_config); + s_previous_wifi_config = NULL; } - sm->ignore_sel_reg = false; - sm->discard_ap_cnt = 0; - sm->scan_cnt = 0; - sm->discover_ssid_cnt = 0; - os_bzero(sm->bssid, ETH_ALEN); - os_bzero(sm->creds, sizeof(sm->creds)); - sm->ap_cred_cnt = 0; +#endif + + esp_event_post(WIFI_EVENT, event_id, event_data, data_len, OS_BLOCK); + + wps_set_type(WPS_TYPE_DISABLE); + wifi_wps_disable_internal(NULL, NULL); + + API_MUTEX_TAKE(); + s_wps_enabled = false; + API_MUTEX_GIVE(); return 0; } -int wps_stop_process(wifi_event_sta_wps_fail_reason_t reason_code) +static int wps_handle_failure(wifi_event_sta_wps_fail_reason_t reason_code) { - struct wps_sm *sm = gWpsSm; + struct wps_sm *sm = wps_sm_get(); - if (!gWpsSm) { + if (!sm) { return ESP_FAIL; } - wps_set_status(WPS_STATUS_DISABLE); - wps_sm_init(sm); + wpa_printf(MSG_INFO, "WPS process stopping."); - sm->wps->state = SEND_M1; - wps_stop_connection_timers(sm); + /* Disconnect from AP before disabling WPS */ esp_wifi_disconnect(); - sm->state = WPA_FAIL; - wpa_printf(MSG_DEBUG, "Write wps_fail_information"); - - esp_event_post(WIFI_EVENT, WIFI_EVENT_STA_WPS_ER_FAILED, &reason_code, sizeof(reason_code), OS_BLOCK); + wps_send_event_and_disable(WIFI_EVENT_STA_WPS_ER_FAILED, &reason_code, sizeof(reason_code)); return ESP_OK; } -int wps_finish(void) +static void wifi_station_fill_event_info(struct wps_sm *sm, wifi_event_sta_wps_er_success_t *evt) { - struct wps_sm *sm = gWpsSm; + int i; + + os_memset(evt, 0, sizeof(*evt)); + if (sm && sm->ap_cred_cnt > 1) { + evt->ap_cred_cnt = sm->ap_cred_cnt < MAX_WPS_AP_CRED ? sm->ap_cred_cnt : MAX_WPS_AP_CRED; + for (i = 0; i < evt->ap_cred_cnt; i++) { + os_memcpy(evt->ap_cred[i].ssid, sm->creds[i].ssid, sm->creds[i].ssid_len); + os_memcpy(evt->ap_cred[i].passphrase, sm->creds[i].key, sm->creds[i].key_len); + } + } +} + +static int wps_finish(void) +{ + struct wps_sm *sm = wps_sm_get(); int ret = ESP_FAIL; - if (!gWpsSm) { + if (!sm) { return ESP_FAIL; } if (sm->wps->state == WPS_FINISHED) { - wpa_printf(MSG_DEBUG, "wps finished------>"); + bool connect = (sm->ap_cred_cnt == 1); + +#ifdef CONFIG_WPS_RECONNECT_ON_FAIL + if (s_previous_wifi_config) { + os_free(s_previous_wifi_config); + s_previous_wifi_config = NULL; + } +#endif + + wpa_printf(MSG_INFO, "WPS: Succeeded"); wps_set_status(WPS_STATUS_SUCCESS); /* WPS finished, dequeue all timers */ wps_delete_timer(); @@ -840,15 +677,13 @@ int wps_finish(void) if (sm->ap_cred_cnt == 1) { wifi_config_t *config = os_zalloc(sizeof(wifi_config_t)); - if (config == NULL) { + if (!config) { return ESP_FAIL; } esp_wifi_get_config(WIFI_IF_STA, config); - esp_wifi_disconnect(); os_memcpy(config->sta.ssid, sm->creds[0].ssid, sm->creds[0].ssid_len); os_memcpy(config->sta.password, sm->creds[0].key, sm->creds[0].key_len); - os_memcpy(config->sta.bssid, sm->bssid, ETH_ALEN); #ifndef CONFIG_WPS_STRICT /* Some APs support AES in WPA IE, enable connection with them */ if (sm->creds[0].auth_type == WPS_AUTH_WPAPSK && @@ -858,80 +693,77 @@ int wps_finish(void) #endif config->sta.bssid_set = 0; config->sta.sae_pwe_h2e = 0; + esp_wifi_disconnect(); esp_wifi_set_config(WIFI_IF_STA, config); - esp_wifi_connect(); - os_free(config); } + + /* fill event info */ + wifi_station_fill_event_info(sm, &s_wps_success_evt); + + /* Disable WPS when success */ + wps_set_type(WPS_TYPE_DISABLE); + wifi_wps_disable_internal(NULL, NULL); + + if (connect) { + esp_wifi_connect(); + } + + /* wait for 1 sec before sending WPS success event to give connection time */ + /* TODO: Remove disconnection event during WPS session to make it cleaner */ eloop_cancel_timeout(wifi_station_wps_success, NULL, NULL); - eloop_register_timeout(1, 0, wifi_station_wps_success, NULL, NULL); + eloop_register_timeout(WPS_SUCCESS_EVENT_TIMEOUT_SECS, 0, wifi_station_wps_success, NULL, NULL); ret = 0; } else { - wpa_printf(MSG_ERROR, "wps failed-----> ignore_sel_reg=%d", sm->ignore_sel_reg); - if (sm->ignore_sel_reg) { - sm->discover_ssid_cnt = 0; - esp_wifi_disconnect(); - os_bzero(sm->creds, sizeof(sm->creds)); - wps_add_discard_ap(sm->bssid); - } else { - ret = wps_stop_process(WPS_FAIL_REASON_NORMAL); - } + wpa_printf(MSG_ERROR, "WPS failed with state %d", sm->wps->state); + ret = wps_handle_failure(WPS_FAIL_REASON_NORMAL); } + API_MUTEX_TAKE(); + s_wps_enabled = false; + API_MUTEX_GIVE(); + return ret; } /* This will get executed in the wifi task's context */ static void wps_sm_notify_deauth(void) { - if (gWpsSm && gWpsSm->wps->state != WPS_FINISHED && - !gWpsSm->intermediate_disconnect) { - wps_stop_process(WPS_FAIL_REASON_RECV_DEAUTH); - } -} - -/* Add current ap to discard ap list */ -void wps_add_discard_ap(u8 *bssid) -{ - struct wps_sm *sm = gWpsSm; - u8 cnt = sm->discard_ap_cnt; + struct wps_sm *sm = wps_sm_get(); - if (!gWpsSm || !bssid) { + if (sm && sm->post_m8_recv) { + wpa_printf(MSG_DEBUG, "WPS: deauth after M8, considering success"); + eloop_cancel_timeout(wifi_station_wps_post_m8_timeout, NULL, NULL); + sm->wps->state = WPS_FINISHED; + wps_finish(); return; } - - if (sm->discard_ap_cnt < WPS_MAX_DIS_AP_NUM) { - sm->discard_ap_cnt++; - } else { - for (cnt = 0; cnt < WPS_MAX_DIS_AP_NUM - 2; cnt++) { - os_memcpy(sm->dis_ap_list[cnt].bssid, sm->dis_ap_list[cnt + 1].bssid, 6); - } - sm->discard_ap_cnt = WPS_MAX_DIS_AP_NUM; + if (sm && sm->wps && sm->wps->state != WPS_FINISHED) { + wpa_printf(MSG_ERROR, "WPS: Deauthenticated during handshake"); + wps_handle_failure(WPS_FAIL_REASON_RECV_DEAUTH); } - os_memcpy(sm->dis_ap_list[cnt].bssid, bssid, ETH_ALEN); - wpa_printf(MSG_INFO, "Added BSSID:"MACSTR" to discard list cnt=%d" , MAC2STR(bssid), sm->discard_ap_cnt); } int wps_start_msg_timer(void) { - struct wps_sm *sm = gWpsSm; + struct wps_sm *sm = wps_sm_get(); uint32_t msg_timeout; int ret = ESP_FAIL; - if (!gWpsSm) { + if (!sm) { return ESP_FAIL; } if (sm->wps->state == WPS_FINISHED) { - msg_timeout = 5; - wpa_printf(MSG_DEBUG, "start msg timer WPS_FINISHED %" PRId32 " ms", msg_timeout); + msg_timeout = WPS_MSG_TIMEOUT_FINISH_SECS; + wpa_printf(MSG_DEBUG, "WPS: Starting M-Done timer (%u s)", msg_timeout); eloop_cancel_timeout(wifi_station_wps_msg_timeout, NULL, NULL); eloop_register_timeout(msg_timeout, 0, wifi_station_wps_msg_timeout, NULL, NULL); ret = 0; } else if (sm->wps->state == RECV_M2) { - msg_timeout = 20; - wpa_printf(MSG_DEBUG, "start msg timer RECV_M2 %" PRId32 " s", msg_timeout); + msg_timeout = WPS_MSG_TIMEOUT_M2_SECS; + wpa_printf(MSG_DEBUG, "WPS: Starting M2 timer (%u s)", msg_timeout); eloop_cancel_timeout(wifi_station_wps_msg_timeout, NULL, NULL); eloop_register_timeout(msg_timeout, 0, wifi_station_wps_msg_timeout, NULL, NULL); ret = 0; @@ -956,40 +788,9 @@ int wps_start_msg_timer(void) * successful key handshake. * buf begin from version, so remove mac header ,snap header and ether_type */ -int wps_sm_rx_eapol(u8 *src_addr, u8 *buf, u32 len) +static int wps_sm_rx_eapol(u8 *src_addr, u8 *buf, u32 len) { - if (!gWpsSm) { - return ESP_FAIL; - } - -#ifdef USE_WPS_TASK - { - struct wps_rx_param *param = os_zalloc(sizeof(struct wps_rx_param)); /* free in task */ - - if (!param) { - return ESP_ERR_NO_MEM; - } - - param->buf = os_zalloc(len); /* free in task */ - if (!param->buf) { - os_free(param); - return ESP_ERR_NO_MEM; - } - os_memcpy(param->buf, buf, len); - param->len = len; - os_memcpy(param->sa, src_addr, ETH_ALEN); - - wps_rxq_enqueue(param); - return wps_post(SIG_WPS_RX, 0); - } -#else - return wps_sm_rx_eapol_internal(src_addr, buf, len); -#endif -} - -int wps_sm_rx_eapol_internal(u8 *src_addr, u8 *buf, u32 len) -{ - struct wps_sm *sm = gWpsSm; + struct wps_sm *sm = wps_sm_get(); u32 plen, data_len, eap_len; struct ieee802_1x_hdr *hdr; struct eap_hdr *ehdr; @@ -999,56 +800,49 @@ int wps_sm_rx_eapol_internal(u8 *src_addr, u8 *buf, u32 len) int ret = ESP_FAIL; enum wps_process_res res = WPS_DONE; - if (!gWpsSm) { + if (!sm) { return ESP_FAIL; } if (len < sizeof(*hdr) + sizeof(*ehdr)) { - wpa_printf(MSG_DEBUG, "WPA: EAPOL frame too short to be a WPA " - "EAPOL-Key (len %lu, expecting at least %lu)", - (unsigned long) len, - (unsigned long) sizeof(*hdr) + sizeof(*ehdr)); + wpa_printf(MSG_DEBUG, "WPS: EAPOL frame too short (len=%lu)", + (unsigned long) len); return ESP_OK; } tmp = buf; hdr = (struct ieee802_1x_hdr *) tmp; - ehdr = (struct eap_hdr *) (hdr + 1); + ehdr = (struct eap_hdr *)(hdr + 1); plen = be_to_host16(hdr->length); data_len = plen + sizeof(*hdr); eap_len = be_to_host16(ehdr->length); - wpa_printf(MSG_DEBUG, "IEEE 802.1X RX: version=%d type=%d length=%" PRId32 "", - hdr->version, hdr->type, plen); + wpa_printf(MSG_DEBUG, "WPS: RX IEEE 802.1X: version=%d type=%d length=%u", hdr->version, hdr->type, plen); if (hdr->version < EAPOL_VERSION) { /* TODO: backwards compatibility */ } if (hdr->type != IEEE802_1X_TYPE_EAP_PACKET) { - wpa_printf(MSG_DEBUG, "WPS: EAP frame (type %u) discarded, " - "not a EAP PACKET frame", hdr->type); + wpa_printf(MSG_DEBUG, "WPS: Discarding non-EAP-PACKET frame (type %u)", hdr->type); ret = 0; goto out; } if (plen > len - sizeof(*hdr) || plen < sizeof(*ehdr)) { - wpa_printf(MSG_DEBUG, "WPA: EAPOL frame payload size %lu " - "invalid (frame size %lu)", + wpa_printf(MSG_DEBUG, "WPS: Invalid EAPOL payload size %lu (frame size %lu)", (unsigned long) plen, (unsigned long) len); ret = 0; goto out; } - wpa_hexdump(MSG_MSGDUMP, "WPA: RX EAPOL-EAP PACKET", tmp, len); + wpa_hexdump(MSG_MSGDUMP, "WPS: RX EAPOL-EAP Packet", tmp, len); if (data_len < len) { - wpa_printf(MSG_DEBUG, "WPA: ignoring %lu bytes after the IEEE " - "802.1X data", (unsigned long) len - data_len); + wpa_printf(MSG_DEBUG, "WPS: Ignoring %lu extra bytes in EAPOL frame", (unsigned long) len - data_len); } if (eap_len != plen) { - wpa_printf(MSG_DEBUG, "WPA: EAPOL length %lu " - "invalid (eapol length %lu)", + wpa_printf(MSG_DEBUG, "WPS: Invalid EAP length %lu in EAPOL frame (total payload %lu)", (unsigned long) eap_len, (unsigned long) plen); ret = 0; goto out; @@ -1057,36 +851,36 @@ int wps_sm_rx_eapol_internal(u8 *src_addr, u8 *buf, u32 len) eap_code = ehdr->code; switch (eap_code) { case EAP_CODE_SUCCESS: - wpa_printf(MSG_DEBUG, "error: receive eapol success frame!"); + wpa_printf(MSG_WARNING, "WPS: Unexpected EAP-Success frame received"); ret = 0; break; case EAP_CODE_FAILURE: - wpa_printf(MSG_DEBUG, "receive eap code failure!"); + wpa_printf(MSG_INFO, "WPS: Received EAP-Failure frame."); ret = wps_finish(); break; case EAP_CODE_RESPONSE: - wpa_printf(MSG_DEBUG, "error: receive eapol response frame!"); + wpa_printf(MSG_WARNING, "WPS: Unexpected EAP-Response frame received"); ret = 0; break; case EAP_CODE_REQUEST: eap_type = ((u8 *)ehdr)[sizeof(*ehdr)]; switch (eap_type) { case EAP_TYPE_IDENTITY: - wpa_printf(MSG_DEBUG, "=========identity==========="); + wpa_printf(MSG_DEBUG, "WPS: Received EAP-Request-Identity"); sm->current_identifier = ehdr->identifier; eloop_cancel_timeout(wifi_station_wps_eapol_start_handle, NULL, NULL); - wpa_printf(MSG_DEBUG, "WPS: Build EAP Identity."); + wpa_printf(MSG_DEBUG, "WPS: Building EAP-Identity Response."); ret = wps_send_eap_identity_rsp(ehdr->identifier); - eloop_register_timeout(3, 0, wifi_station_wps_eapol_start_handle, NULL, NULL); + eloop_register_timeout(EAPOL_START_HANDLE_TIMEOUT_SECS, 0, wifi_station_wps_eapol_start_handle, NULL, NULL); break; case EAP_TYPE_EXPANDED: - wpa_printf(MSG_DEBUG, "=========expanded plen[%" PRId32 "], %d===========", plen, sizeof(*ehdr)); + wpa_printf(MSG_DEBUG, "WPS: Received EAP-WSC message (len=%u)", plen); sm->current_identifier = ehdr->identifier; tmp = (u8 *)(ehdr + 1) + 1; ret = wps_process_wps_mX_req(tmp, plen - sizeof(*ehdr) - 1, &res); if (res == WPS_FRAGMENT) { - wpa_printf(MSG_DEBUG, "wps frag, silently exit", res); + wpa_printf(MSG_DEBUG, "WPS fragment received, waiting for more."); ret = ESP_OK; break; } @@ -1094,7 +888,7 @@ int wps_sm_rx_eapol_internal(u8 *src_addr, u8 *buf, u32 len) ret = wps_send_wps_mX_rsp(ehdr->identifier); if (ret == ESP_OK) { - wpa_printf(MSG_DEBUG, "sm->wps->state = %d", sm->wps->state); + wpa_printf(MSG_DEBUG, "WPS: State updated to %d", sm->wps->state); wps_start_msg_timer(); } } else if (ret == ESP_ERR_INVALID_STATE) { @@ -1111,29 +905,22 @@ int wps_sm_rx_eapol_internal(u8 *src_addr, u8 *buf, u32 len) break; } out: - if (ret != 0 && sm->ignore_sel_reg) { - wifi_wps_scan(NULL, NULL); - } else if ((ret != 0 || res == WPS_FAILURE)) { - wifi_event_sta_wps_fail_reason_t reason_code = WPS_FAIL_REASON_NORMAL; - wpa_printf(MSG_DEBUG, "wpa rx eapol internal: fail ret=%d", ret); - wps_set_status(WPS_STATUS_DISABLE); - esp_wifi_disarm_sta_connection_timer_internal(); - eloop_cancel_timeout(wifi_station_wps_timeout, NULL, NULL); + if ((ret != 0 || res == WPS_FAILURE)) { + wpa_printf(MSG_ERROR, "WPS: EAPOL processing failed (ret=%d)", ret); + wps_handle_failure(WPS_FAIL_REASON_NORMAL); - esp_event_post(WIFI_EVENT, WIFI_EVENT_STA_WPS_ER_FAILED, &reason_code, sizeof(reason_code), OS_BLOCK); - - return ret; + return ESP_FAIL; } return ret; } -int wps_set_default_factory(void) +static int wps_set_default_factory(void) { if (!s_factory_info) { s_factory_info = os_zalloc(sizeof(wps_factory_information_t)); if (!s_factory_info) { - wpa_printf(MSG_ERROR, "wps factory info malloc failed"); + wpa_printf(MSG_ERROR, "WPS: Failed to allocate memory for factory info"); return ESP_ERR_NO_MEM; } } @@ -1171,17 +958,16 @@ int wps_set_factory_info(const esp_wps_config_t *config) os_memcpy(s_factory_info->device_name, config->factory_info.device_name, WPS_MAX_DEVICE_NAME_LEN - 1); } - wpa_printf(MSG_INFO, "manufacturer: %s, model number: %s, model name: %s, device name: %s", s_factory_info->manufacturer, + wpa_printf(MSG_INFO, "WPS: Manufacturer: %s, Model: %s, Model-Num: %s, Device: %s", s_factory_info->manufacturer, s_factory_info->model_number, s_factory_info->model_name, s_factory_info->device_name); return ESP_OK; } - int wps_dev_init(void) { int ret = 0; - struct wps_sm *sm = gWpsSm; + struct wps_sm *sm = wps_sm_get(); struct wps_device_data *dev = NULL; if (!sm) { @@ -1247,8 +1033,8 @@ int wps_dev_init(void) goto _out; } os_snprintf(dev->serial_number, 16, "%02x%02x%02x%02x%02x%02x", - sm->ownaddr[0], sm->ownaddr[1], sm->ownaddr[2], - sm->ownaddr[3], sm->ownaddr[4], sm->ownaddr[5]); + sm->ownaddr[0], sm->ownaddr[1], sm->ownaddr[2], + sm->ownaddr[3], sm->ownaddr[4], sm->ownaddr[5]); uuid_gen_mac_addr(sm->ownaddr, sm->uuid); os_memcpy(dev->mac_addr, sm->ownaddr, ETH_ALEN); @@ -1260,11 +1046,8 @@ int wps_dev_init(void) return ret; } - int wps_dev_deinit(struct wps_device_data *dev) { - int ret = 0; - if (!dev) { return ESP_FAIL; } @@ -1275,137 +1058,74 @@ int wps_dev_deinit(struct wps_device_data *dev) s_factory_info = NULL; } - return ret; + return ESP_OK; } -void -wifi_station_wps_timeout_internal(void) +static void wifi_station_wps_timeout(void *data, void *user_ctx) { - struct wps_sm *sm = gWpsSm; - + struct wps_sm *sm = wps_sm_get(); if (!sm) { return; } + wpa_printf(MSG_ERROR, "WPS overall timeout!"); - esp_wifi_disarm_sta_connection_timer_internal(); - - wps_set_status(WPS_STATUS_DISABLE); - - esp_event_post(WIFI_EVENT, WIFI_EVENT_STA_WPS_ER_TIMEOUT, 0, 0, OS_BLOCK); -} - -void wifi_station_wps_timeout(void *data, void *user_ctx) -{ -#ifdef USE_WPS_TASK - wps_post(SIG_WPS_TIMER_TIMEOUT, 0); - return; -#else - wifi_station_wps_timeout_internal(); -#endif + wps_send_event_and_disable(WIFI_EVENT_STA_WPS_ER_TIMEOUT, 0, 0); } -void -wifi_station_wps_msg_timeout_internal(void) +static void wifi_station_wps_msg_timeout(void *data, void *user_ctx) { - struct wps_sm *sm = gWpsSm; + struct wps_sm *sm = wps_sm_get(); if (!sm) { return; } if (sm->wps->state == WPS_FINISHED) { - wpa_printf(MSG_DEBUG, "wps msg timeout WPS_FINISHED"); + wpa_printf(MSG_DEBUG, "WPS: M-Done timer expired, finishing."); wps_finish(); return; } else if (sm->wps->state == RECV_M2) { - wpa_printf(MSG_DEBUG, "wps msg timeout RECV_M2"); - if (!sm->ignore_sel_reg) { - wps_stop_process(WPS_FAIL_REASON_RECV_M2D); - } - } - if (sm->ignore_sel_reg) { - esp_wifi_disconnect(); - wps_add_discard_ap(sm->bssid); - os_bzero(sm->creds, sizeof(sm->creds)); - os_bzero(sm->bssid, ETH_ALEN); - sm->discover_ssid_cnt = 0; - wifi_wps_scan(NULL, NULL); + wpa_printf(MSG_ERROR, "WPS: Timed out waiting for M2/M2D"); + wps_handle_failure(WPS_FAIL_REASON_RECV_M2D); } } -void wifi_station_wps_msg_timeout(void *data, void *user_ctx) +static void wifi_station_wps_success(void *data, void *user_ctx) { -#ifdef USE_WPS_TASK - wps_post(SIG_WPS_TIMER_MSG_TIMEOUT, 0); - return; -#else - wifi_station_wps_msg_timeout_internal(); -#endif -} - -void wifi_station_wps_success_internal(void) -{ - wifi_event_sta_wps_er_success_t evt = {0}; - struct wps_sm *sm = gWpsSm; - int i; - /* * For only one AP credential don't send event data, wps_finish() has already set * the config. This is for backward compatibility. */ - if (sm->ap_cred_cnt > 1) { - evt.ap_cred_cnt = sm->ap_cred_cnt; - for (i = 0; i < MAX_WPS_AP_CRED; i++) { - os_memcpy(evt.ap_cred[i].ssid, sm->creds[i].ssid, sm->creds[i].ssid_len); - os_memcpy(evt.ap_cred[i].passphrase, sm->creds[i].key, sm->creds[i].key_len); - } - esp_event_post(WIFI_EVENT, WIFI_EVENT_STA_WPS_ER_SUCCESS, &evt, - sizeof(evt), OS_BLOCK); + if (s_wps_success_evt.ap_cred_cnt > 1) { + esp_event_post(WIFI_EVENT, WIFI_EVENT_STA_WPS_ER_SUCCESS, &s_wps_success_evt, + sizeof(s_wps_success_evt), OS_BLOCK); } else { esp_event_post(WIFI_EVENT, WIFI_EVENT_STA_WPS_ER_SUCCESS, - 0, 0, OS_BLOCK); + 0, 0, OS_BLOCK); } -} - -void wifi_station_wps_success(void *data, void *user_ctx) -{ -#ifdef USE_WPS_TASK - wps_post(SIG_WPS_TIMER_SUCCESS_CB, 0); - return; -#else - wifi_station_wps_success_internal(); -#endif -} - -void wifi_station_wps_eapol_start_handle_internal(void) -{ - wpa_printf(MSG_DEBUG, "Resend EAPOL-Start."); - wps_tx_start(); + os_memset(&s_wps_success_evt, 0, sizeof(s_wps_success_evt)); } void wifi_station_wps_eapol_start_handle(void *data, void *user_ctx) { -#ifdef USE_WPS_TASK - wps_post(SIG_WPS_TIMER_EAPOL_START, 0); - return; -#else - wifi_station_wps_eapol_start_handle_internal(); -#endif + wpa_printf(MSG_DEBUG, "WPS: Resending EAPOL-Start"); + wps_tx_start(); } static int save_credentials_cb(void *ctx, const struct wps_credential *cred) { + struct wps_sm *sm = wps_sm_get(); struct wps_credential *creds; - if (!gWpsSm || !cred || gWpsSm->ap_cred_cnt >= MAX_CRED_COUNT) { + if (!sm || !cred || sm->ap_cred_cnt >= MAX_CRED_COUNT) { return ESP_FAIL; } - creds = &gWpsSm->creds[gWpsSm->ap_cred_cnt]; + creds = &sm->creds[sm->ap_cred_cnt]; memcpy(creds, cred, sizeof(*creds)); - gWpsSm->ap_cred_cnt++; + sm->ap_cred_cnt++; - wpa_hexdump_ascii(MSG_DEBUG, "ssid ", cred->ssid, cred->ssid_len); - wpa_hexdump_ascii(MSG_DEBUG, "key ", cred->key, cred->key_len); + wpa_hexdump_ascii(MSG_DEBUG, "WPS: Received credential - SSID ", cred->ssid, cred->ssid_len); + wpa_hexdump_ascii(MSG_DEBUG, "WPS: Received credential - Key ", cred->key, cred->key_len); return ESP_OK; } @@ -1426,8 +1146,8 @@ int wps_init_cfg_pin(struct wps_config *cfg) cfg->pin_len = 8; if (wps_generate_pin(&spin) < 0) { return -1; - } - wpa_printf(MSG_INFO, "Provided PIN %s is not valid, generated a new PIN %08d", (char *)cfg->pin, spin); + } + wpa_printf(MSG_INFO, "WPS: Invalid PIN provided, generated new PIN: %08d", spin); os_snprintf((char *)cfg->pin, 9, "%08d", spin); } @@ -1449,7 +1169,7 @@ static int wifi_station_wps_init(const esp_wps_config_t *config) goto _out; } - wpa_printf(MSG_DEBUG, "wifi sta wps init"); + wpa_printf(MSG_DEBUG, "WPS: Initializing"); gWpsSm = os_zalloc(sizeof(struct wps_sm)); /* alloc Wps_sm */ if (!gWpsSm) { @@ -1493,37 +1213,33 @@ static int wifi_station_wps_init(const esp_wps_config_t *config) } sm->wps->wps->cred_cb = save_credentials_cb; - /**************80211 reference***************/ - if (esp_wifi_get_appie_internal(WIFI_APPIE_WPS_PR) == NULL) { /* alloc probe req wps ie */ + if (esp_wifi_get_appie_internal(WIFI_APPIE_WPS_PR) == NULL) { wps_build_ic_appie_wps_pr(); } - if (esp_wifi_get_appie_internal(WIFI_APPIE_WPS_AR) == NULL) { /* alloc assoc req wps ie */ + if (esp_wifi_get_appie_internal(WIFI_APPIE_WPS_AR) == NULL) { wps_build_ic_appie_wps_ar(); } - eloop_cancel_timeout(wifi_station_wps_timeout, NULL, NULL); - eloop_cancel_timeout(wifi_station_wps_msg_timeout, NULL, NULL); - eloop_cancel_timeout(wifi_station_wps_success, NULL, NULL); - eloop_cancel_timeout(wifi_wps_scan, NULL, NULL); - eloop_cancel_timeout(wifi_station_wps_eapol_start_handle, NULL, NULL); + /* Cancel any pending timers from previous WPS attempts */ + wps_delete_timer(); wps_cb = os_malloc(sizeof(struct wps_funcs)); if (wps_cb == NULL) { goto _err; } wps_cb->wps_parse_scan_result = wps_parse_scan_result; - wps_cb->wifi_station_wps_start = wifi_station_wps_start; + wps_cb->wifi_station_wps_start = NULL; wps_cb->wps_sm_rx_eapol = wps_sm_rx_eapol; wps_cb->wps_start_pending = wps_start_pending; esp_wifi_set_wps_cb_internal(wps_cb); - s_wps_sm_cb = os_malloc(sizeof(struct wps_sm_funcs)); - if (s_wps_sm_cb == NULL) { + s_wps_sm_cb = os_zalloc(sizeof(struct wps_sm_funcs)); + if (!s_wps_sm_cb) { goto _err; } - s_wps_sm_cb->wps_sm_notify_deauth = wps_sm_notify_deauth; + os_memset(&s_wps_success_evt, 0, sizeof(s_wps_success_evt)); return ESP_OK; @@ -1553,9 +1269,9 @@ static int wifi_station_wps_init(const esp_wps_config_t *config) return ESP_FAIL; } -int wps_delete_timer(void) +static int wps_delete_timer(void) { - struct wps_sm *sm = gWpsSm; + struct wps_sm *sm = wps_sm_get(); if (!sm) { return ESP_OK; @@ -1566,12 +1282,12 @@ int wps_delete_timer(void) eloop_cancel_timeout(wifi_station_wps_msg_timeout, NULL, NULL); eloop_cancel_timeout(wifi_wps_scan, NULL, NULL); eloop_cancel_timeout(wifi_station_wps_eapol_start_handle, NULL, NULL); + eloop_cancel_timeout(wifi_station_wps_post_m8_timeout, NULL, NULL); esp_wifi_disarm_sta_connection_timer_internal(); return ESP_OK; } -int -wifi_station_wps_deinit(void) +static int wifi_station_wps_deinit(void) { struct wps_sm *sm = gWpsSm; @@ -1609,16 +1325,14 @@ wifi_station_wps_deinit(void) return ESP_OK; } -struct wps_sm * -wps_sm_get(void) +struct wps_sm *wps_sm_get(void) { return gWpsSm; } -void -wifi_wps_scan_done(void *arg, ETS_STATUS status) +static void wifi_wps_scan_done(void *arg, ETS_STATUS status) { - struct wps_sm *sm = gWpsSm; + struct wps_sm *sm = wps_sm_get(); wifi_config_t wifi_config = {0}; wpa_printf(MSG_INFO, "WPS: scan done"); @@ -1637,22 +1351,19 @@ wifi_wps_scan_done(void *arg, ETS_STATUS status) } else { if (sm->wps_pbc_overlap) { sm->wps_pbc_overlap = false; - wpa_printf(MSG_INFO, "PBC session overlap!"); - wps_set_status(WPS_STATUS_DISABLE); - esp_event_post(WIFI_EVENT, WIFI_EVENT_STA_WPS_ER_PBC_OVERLAP, 0, 0, OS_BLOCK); + wpa_printf(MSG_ERROR, "WPS: PBC session overlap detected!"); + wps_send_event_and_disable(WIFI_EVENT_STA_WPS_ER_PBC_OVERLAP, 0, 0); + return; /* WPS is disabled, no further processing */ } else { wps_set_status(WPS_STATUS_PENDING); } } - wpa_printf(MSG_DEBUG, "wps scan_done discover_ssid_cnt = %d", sm->discover_ssid_cnt); + wpa_printf(MSG_DEBUG, "WPS: Scan done, %d APs discovered.", sm->discover_ssid_cnt); sm->discover_ssid_cnt = 0; if (wps_get_status() == WPS_STATUS_PENDING) { - sm->intermediate_disconnect = true; - esp_wifi_disconnect(); - sm->intermediate_disconnect = false; os_memcpy(wifi_config.sta.bssid, sm->bssid, ETH_ALEN); os_memcpy(wifi_config.sta.ssid, (char *)sm->creds[0].ssid, sm->creds[0].ssid_len); @@ -1662,62 +1373,68 @@ wifi_wps_scan_done(void *arg, ETS_STATUS status) (char *)sm->creds[0].ssid, MAC2STR(wifi_config.sta.bssid)); esp_wifi_set_config(0, &wifi_config); - wpa_printf(MSG_DEBUG, "WPS: neg start"); + wpa_printf(MSG_DEBUG, "WPS: Starting negotiation"); wifi_config.sta.failure_retry_cnt = 2; esp_wifi_connect(); sm->state = WAIT_START; eloop_cancel_timeout(wifi_station_wps_msg_timeout, NULL, NULL); - eloop_register_timeout(20, 0, wifi_station_wps_msg_timeout, NULL, NULL); + eloop_register_timeout(WPS_CONNECT_TIMEOUT_SECS, 0, wifi_station_wps_msg_timeout, NULL, NULL); } else if (wps_get_status() == WPS_STATUS_SCANNING) { - if (wps_get_type() == WPS_TYPE_PIN && sm->scan_cnt > WPS_IGNORE_SEL_REG_MAX_CNT) { - wpa_printf(MSG_INFO, "WPS: ignore selected registrar after %d scans", sm->scan_cnt); - sm->ignore_sel_reg = true; - } eloop_cancel_timeout(wifi_wps_scan, NULL, NULL); - eloop_register_timeout(2, 0, wifi_wps_scan, NULL, NULL); + eloop_register_timeout(WPS_SCAN_RETRY_TIMEOUT_SECS, 0, wifi_wps_scan, NULL, NULL); } else { return; } } -void -wifi_wps_scan_internal(void) +static void wifi_wps_scan(void *data, void *user_ctx) { - struct wps_sm *sm = gWpsSm; + struct wps_sm *sm = wps_sm_get(); + + if (!sm) { + return; + } - sm->scan_cnt++; - wpa_printf(MSG_DEBUG, "wifi_wps_scan : %d", sm->scan_cnt); + wpa_printf(MSG_DEBUG, "WPS: Starting scan"); typedef void (* scan_done_cb_t)(void *arg, ETS_STATUS status); extern int esp_wifi_promiscuous_scan_start(wifi_scan_config_t *config, scan_done_cb_t cb); esp_wifi_promiscuous_scan_start(NULL, wifi_wps_scan_done); } -void wifi_wps_scan(void *data, void *user_ctx) -{ -#ifdef USE_WPS_TASK - wps_post(SIG_WPS_TIMER_SCAN, 0); - return; -#else - wifi_wps_scan_internal(); -#endif -} - static int wps_rf_band_cb(void *ctx) { - return WPS_RF_24GHZ; + wifi_band_mode_t band_mode; + esp_err_t ret = esp_wifi_get_band_mode(&band_mode); + + if (ret != ESP_OK) { + wpa_printf(MSG_ERROR, "WPS: failed to get band mode"); + } + + switch (band_mode) { + case WIFI_BAND_MODE_2G_ONLY: + return WPS_RF_24GHZ; + case WIFI_BAND_MODE_5G_ONLY: + return WPS_RF_50GHZ; + case WIFI_BAND_MODE_AUTO: + return WPS_RF_24GHZ | WPS_RF_50GHZ; + default: + return WPS_RF_24GHZ; + } + return WPS_RF_24GHZ; } -int wifi_station_wps_start(void) +static int wifi_station_wps_start(void *data, void *user_ctx) { struct wps_sm *sm = wps_sm_get(); if (!sm) { - wpa_printf(MSG_ERROR, "WPS: wps is not initialized"); + wpa_printf(MSG_ERROR, "WPS: Not initialized"); return ESP_FAIL; } - eloop_register_timeout(120, 0, wifi_station_wps_timeout, NULL, NULL); + eloop_cancel_timeout(wifi_station_wps_timeout, NULL, NULL); + eloop_register_timeout(WPS_TOTAL_TIMEOUT_SECS, 0, wifi_station_wps_timeout, NULL, NULL); switch (wps_get_status()) { case WPS_STATUS_DISABLE: @@ -1732,140 +1449,54 @@ int wifi_station_wps_start(void) sm->wps->wps->dh_pubkey = sm->wps->dh_pubkey_e; sm->wps->wps->rf_band_cb = wps_rf_band_cb; sm->wps->dh_privkey = NULL; +#ifdef CONFIG_WPS_RECONNECT_ON_FAIL + if (s_previous_wifi_config) { + os_free(s_previous_wifi_config); + s_previous_wifi_config = NULL; + } + wifi_ap_record_t ap_info; + /* Check if we are connected to an AP */ + if (esp_wifi_sta_get_ap_info(&ap_info) == ESP_OK) { + s_previous_wifi_config = (wifi_config_t *)os_zalloc(sizeof(wifi_config_t)); + if (s_previous_wifi_config) { + if (esp_wifi_get_config(WIFI_IF_STA, s_previous_wifi_config) != ESP_OK || + s_previous_wifi_config->sta.ssid[0] == 0) { + os_free(s_previous_wifi_config); + s_previous_wifi_config = NULL; + } else { + wpa_printf(MSG_INFO, "WPS: Stored previous AP to reconnect on failure: %s", + (char *)s_previous_wifi_config->sta.ssid); + } + } + } +#endif esp_wifi_disconnect(); wifi_wps_scan(NULL, NULL); + if (s_wps_sm_cb) { + s_wps_sm_cb->wps_sm_notify_deauth = wps_sm_notify_deauth; + } break; case WPS_STATUS_SCANNING: - sm->scan_cnt = 0; eloop_cancel_timeout(wifi_station_wps_timeout, NULL, NULL); - eloop_register_timeout(120, 0, wifi_station_wps_timeout, NULL, NULL); + eloop_register_timeout(WPS_TOTAL_TIMEOUT_SECS, 0, wifi_station_wps_timeout, NULL, NULL); break; default: break; } os_memset(sm->uuid_r, 0, sizeof(sm->uuid_r)); sm->wps_pbc_overlap = false; - sm->discard_ap_cnt = 0; - os_memset(&sm->dis_ap_list, 0, WPS_MAX_DIS_AP_NUM * sizeof(struct discard_ap_list_t)); esp_wifi_set_wps_start_flag_internal(true); return ESP_OK; } -int wps_task_deinit(void) -{ - wpa_printf(MSG_DEBUG, "wps task deinit"); - - if (s_wps_api_sem) { - os_semphr_delete(s_wps_api_sem); - s_wps_api_sem = NULL; - wpa_printf(MSG_DEBUG, "wps task deinit: free api sem"); - } - - if (s_wps_task_create_sem) { - os_semphr_delete(s_wps_task_create_sem); - s_wps_task_create_sem = NULL; - wpa_printf(MSG_DEBUG, "wps task deinit: free task create sem"); - } - - if (s_wps_queue) { - os_queue_delete(s_wps_queue); - s_wps_queue = NULL; - wpa_printf(MSG_DEBUG, "wps task deinit: free queue"); - } - - if (STAILQ_FIRST(&s_wps_rxq) != NULL){ - wps_rxq_deinit(); - } - - if (s_wps_data_lock) { - os_mutex_delete(s_wps_data_lock); - s_wps_data_lock = NULL; - } - - return ESP_OK; -} - -int wps_task_init(void) -{ - int ret = 0; - - /* Call wps_task_deinit() first in case esp_wifi_wps_disable() fails - */ - wps_task_deinit(); - - if (!s_wps_data_lock) { - s_wps_data_lock = os_recursive_mutex_create(); - if (!s_wps_data_lock) { - wpa_printf(MSG_ERROR, "wps task init: failed to alloc data lock"); - goto _wps_no_mem; - } - } - - s_wps_api_sem = os_semphr_create(1, 0); - if (!s_wps_api_sem) { - wpa_printf(MSG_ERROR, "wps task init: failed to create api sem"); - goto _wps_no_mem; - } - - s_wps_task_create_sem = os_semphr_create(1, 0); - if (!s_wps_task_create_sem) { - wpa_printf(MSG_ERROR, "wps task init: failed to create task sem"); - goto _wps_no_mem; - } - - os_bzero(s_wps_sig_cnt, SIG_WPS_NUM); - s_wps_queue = os_queue_create(SIG_WPS_NUM, sizeof(ETSEvent)); - if (!s_wps_queue) { - wpa_printf(MSG_ERROR, "wps task init: failed to alloc queue"); - goto _wps_no_mem; - } - - wps_rxq_init(); - - ret = os_task_create(wps_task, "wpsT", WPS_TASK_STACK_SIZE, NULL, 2, &s_wps_task_hdl); - if (TRUE != ret) { - wpa_printf(MSG_ERROR, "wps enable: failed to create task"); - goto _wps_no_mem; - } - - os_semphr_take(s_wps_task_create_sem, OS_BLOCK); - os_semphr_delete(s_wps_task_create_sem); - s_wps_task_create_sem = NULL; - - wpa_printf(MSG_DEBUG, "wifi wps enable: task prio:%d, stack:%d", 2, WPS_TASK_STACK_SIZE); - return ESP_OK; - -_wps_no_mem: - wps_task_deinit(); - return ESP_ERR_NO_MEM; -} - -int wps_post_block(uint32_t sig, void *arg) -{ - wps_ioctl_param_t param; - - param.ret = ESP_FAIL; - param.arg = arg; - - if (ESP_OK != wps_post(sig, (uint32_t)¶m)) { - return ESP_FAIL; - } - - if (TRUE == os_semphr_take(s_wps_api_sem, OS_BLOCK)) { - return param.ret; - } else { - return ESP_FAIL; - } -} - -int wps_check_wifi_mode(void) +static int wps_check_wifi_mode(void) { wifi_mode_t mode; int ret; ret = esp_wifi_get_mode(&mode); if (ESP_OK != ret) { - wpa_printf(MSG_ERROR, "wps check wifi mode: failed to get wifi mode ret=%d", ret); + wpa_printf(MSG_ERROR, "WPS: Failed to get Wi-Fi mode (ret=%d)", ret); return ESP_FAIL; } @@ -1874,7 +1505,7 @@ int wps_check_wifi_mode(void) mode == WIFI_MODE_AP || #endif mode == WIFI_MODE_NULL) { - wpa_printf(MSG_ERROR, "wps check wifi mode: wrong wifi mode=%d ", mode); + wpa_printf(MSG_ERROR, "WPS: Invalid Wi-Fi mode for WPS: %d ", mode); return ESP_ERR_WIFI_MODE; } @@ -1887,7 +1518,7 @@ int esp_wifi_wps_enable(const esp_wps_config_t *config) struct wps_sm *sm = gWpsSm; if (esp_wifi_get_user_init_flag_internal() == 0) { - wpa_printf(MSG_ERROR, "wps enable: wifi not started cannot disable wpsreg"); + wpa_printf(MSG_ERROR, "WPS: Wi-Fi not started, cannot enable"); return ESP_ERR_WIFI_STATE; } @@ -1896,69 +1527,64 @@ int esp_wifi_wps_enable(const esp_wps_config_t *config) } if (is_dpp_enabled()) { - wpa_printf(MSG_ERROR, "wps enabled failed since DPP is initialized"); + wpa_printf(MSG_ERROR, "WPS: Cannot enable, DPP is already initialized"); return ESP_FAIL; } API_MUTEX_TAKE(); if (s_wps_enabled) { if (sm && os_memcmp(sm->identity, WSC_ID_REGISTRAR, sm->identity_len) == 0) { - wpa_printf(MSG_ERROR, "wps enable: wpsreg already enabled cannot enable wps enrollee"); + wpa_printf(MSG_ERROR, "WPS: Cannot enable Enrollee, Registrar is already enabled"); ret = ESP_ERR_WIFI_MODE; } else { - wpa_printf(MSG_DEBUG, "wps enable: already enabled"); + wpa_printf(MSG_DEBUG, "WPS: Already enabled"); } API_MUTEX_GIVE(); return ret; } -#ifdef USE_WPS_TASK - ret = wps_task_init(); - if (ESP_OK != ret) { - API_MUTEX_GIVE(); - return ret; - } - - ret = wps_post_block(SIG_WPS_ENABLE, (esp_wps_config_t *)config); - if (ESP_OK != ret) { - wps_task_deinit(); - API_MUTEX_GIVE(); - return ret; - } - + ret = eloop_register_timeout_blocking(wifi_wps_enable_internal, NULL, (void *)config); s_wps_enabled = true; - wpa_printf(MSG_DEBUG, "wifi wps task: prio:%d, stack:%d", 2, WPS_TASK_STACK_SIZE); API_MUTEX_GIVE(); return ret; -#else - ret = wifi_wps_enable_internal(config); - API_MUTEX_GIVE(); - return ret; -#endif } bool is_wps_enabled(void) { - return s_wps_enabled; + bool enabled; + + API_MUTEX_TAKE(); + enabled = s_wps_enabled; + API_MUTEX_GIVE(); + + return enabled; } -int wifi_wps_enable_internal(const esp_wps_config_t *config) +static int wifi_wps_disable(void) { + wps_set_type(WPS_TYPE_DISABLE); + wifi_wps_disable_internal(NULL, NULL); + + return 0; +} + +static int wifi_wps_enable_internal(void *ctx, void *data) +{ + const esp_wps_config_t *config = (const esp_wps_config_t *)data; int ret = 0; struct wpa_sm *wpa_sm = &gWpaSm; - wpa_printf(MSG_DEBUG, "ESP WPS crypto initialize!"); if (config->wps_type == WPS_TYPE_DISABLE) { - wpa_printf(MSG_ERROR, "wps enable: invalid wps type"); + wpa_printf(MSG_ERROR, "WPS: Invalid WPS type for enabling"); return ESP_ERR_WIFI_WPS_TYPE; } - wpa_printf(MSG_DEBUG, "Set factory information."); + wpa_printf(MSG_DEBUG, "WPS: Setting factory information"); ret = wps_set_factory_info(config); if (ret != 0) { return ret; } - wpa_printf(MSG_INFO, "wifi_wps_enable"); + wpa_printf(MSG_INFO, "WPS: Enabling"); wps_set_type(config->wps_type); wps_set_status(WPS_STATUS_DISABLE); @@ -1970,12 +1596,16 @@ int wifi_wps_enable_internal(const esp_wps_config_t *config) wps_set_status(WPS_STATUS_DISABLE); return ESP_FAIL; } - wpa_sm->wpa_sm_wps_disable = esp_wifi_wps_disable; + wpa_sm->wpa_sm_wps_disable = wifi_wps_disable; return ESP_OK; } -int wifi_wps_disable_internal(void) +static int wifi_wps_disable_internal(void *ctx, void *data) { + /* Only disconnect in case of WPS pending */ + if (wps_get_status() == WPS_STATUS_PENDING) { + esp_wifi_disconnect(); + } wps_set_status(WPS_STATUS_DISABLE); /* Call wps_delete_timer to delete all WPS timer, no timer will call wps_post() @@ -1983,13 +1613,19 @@ int wifi_wps_disable_internal(void) */ wps_delete_timer(); wifi_station_wps_deinit(); +#ifdef CONFIG_WPS_RECONNECT_ON_FAIL + /* If the config exists, it means WPS was cancelled by the user */ + if (s_previous_wifi_config) { + os_free(s_previous_wifi_config); + s_previous_wifi_config = NULL; + } +#endif return ESP_OK; } int esp_wifi_wps_disable(void) { int ret = 0; - int wps_status; struct wps_sm *wps_sm = gWpsSm; struct wpa_sm *wpa_sm = &gWpaSm; @@ -2000,31 +1636,20 @@ int esp_wifi_wps_disable(void) API_MUTEX_TAKE(); if (!s_wps_enabled) { - wpa_printf(MSG_DEBUG, "wps disable: already disabled"); + wpa_printf(MSG_DEBUG, "WPS: Already disabled"); API_MUTEX_GIVE(); return ESP_OK; } - wps_status = wps_get_status(); - wpa_printf(MSG_INFO, "wifi_wps_disable"); + wpa_printf(MSG_INFO, "WPS: Disabling"); wps_set_type(WPS_TYPE_DISABLE); /* Notify WiFi task */ -#ifdef USE_WPS_TASK - ret = wps_post_block(SIG_WPS_DISABLE, 0); -#else - ret = wifi_wps_disable_internal(); -#endif + ret = eloop_register_timeout_blocking(wifi_wps_disable_internal, NULL, NULL); if (ESP_OK != ret) { - wpa_printf(MSG_ERROR, "wps disable: failed to disable wps, ret=%d", ret); - } - - /* Only disconnect in case of WPS pending/done */ - if ((wps_status == WPS_STATUS_PENDING) || (wps_status == WPS_STATUS_SUCCESS)) { - esp_wifi_disconnect(); + wpa_printf(MSG_ERROR, "WPS: Failed to disable (ret=%d)", ret); } esp_wifi_set_wps_start_flag_internal(false); - wps_task_deinit(); s_wps_enabled = false; API_MUTEX_GIVE(); wpa_sm->wpa_sm_wps_disable = NULL; @@ -2033,6 +1658,8 @@ int esp_wifi_wps_disable(void) int esp_wifi_wps_start(int timeout_ms) { + int ret; + if (ESP_OK != wps_check_wifi_mode()) { return ESP_ERR_WIFI_MODE; } @@ -2040,27 +1667,17 @@ int esp_wifi_wps_start(int timeout_ms) API_MUTEX_TAKE(); if (!s_wps_enabled) { - wpa_printf(MSG_ERROR, "wps start: wps not enabled"); + wpa_printf(MSG_ERROR, "WPS: Cannot start, not enabled"); API_MUTEX_GIVE(); return ESP_ERR_WIFI_WPS_SM; } - if (wps_get_type() == WPS_TYPE_DISABLE || (wps_get_status() != WPS_STATUS_DISABLE && wps_get_status() != WPS_STATUS_SCANNING)) { - API_MUTEX_GIVE(); - return ESP_ERR_WIFI_WPS_TYPE; - } - if (esp_wifi_get_user_init_flag_internal() == 0) { API_MUTEX_GIVE(); return ESP_ERR_WIFI_STATE; } - wpa_printf(MSG_DEBUG, "wps scan"); -#ifdef USE_WPS_TASK - wps_post_block(SIG_WPS_START, 0); -#else - ic_pp_post(SIG_PP_WPS, 0); -#endif + ret = eloop_register_timeout_blocking(wifi_station_wps_start, NULL, NULL); API_MUTEX_GIVE(); - return ESP_OK; + return ret; } diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_wps_i.h b/components/wpa_supplicant/esp_supplicant/src/esp_wps_i.h index 1058da26b7c7..d32b1c4334f4 100644 --- a/components/wpa_supplicant/esp_supplicant/src/esp_wps_i.h +++ b/components/wpa_supplicant/esp_supplicant/src/esp_wps_i.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,21 +15,6 @@ enum wps_msg_flag { WPS_MSG_FLAG_LEN = 0x02 }; -#ifdef USE_WPS_TASK -enum wps_sig_type { - SIG_WPS_ENABLE = 1, //1 - SIG_WPS_DISABLE, //2 - SIG_WPS_START, //3 - SIG_WPS_RX, //4 - SIG_WPS_TIMER_TIMEOUT, //5 - SIG_WPS_TIMER_MSG_TIMEOUT, //6 - SIG_WPS_TIMER_SUCCESS_CB, //7 - SIG_WPS_TIMER_SCAN, //8 - SIG_WPS_TIMER_EAPOL_START, //9 - SIG_WPS_NUM, //10 -}; -#endif - enum wps_reg_sig_type { SIG_WPS_REG_ENABLE = 1, //1 SIG_WPS_REG_DISABLE, //2 @@ -50,10 +35,6 @@ enum wps_sm_state { }; #endif /* ESP_SUPPLICANT */ -#define WPS_IGNORE_SEL_REG_MAX_CNT 10 - -#define WPS_MAX_DIS_AP_NUM 10 - /* Bssid of the discard AP which is discarded for not select reg or other reason */ struct discard_ap_list_t { u8 bssid[6]; @@ -76,16 +57,9 @@ struct wps_sm { u8 current_identifier; bool is_wps_scan; u8 channel; - u8 scan_cnt; -#ifdef USE_WPS_TASK - u8 wps_sig_cnt[SIG_WPS_NUM]; -#endif u8 discover_ssid_cnt; - bool ignore_sel_reg; bool wps_pbc_overlap; - struct discard_ap_list_t dis_ap_list[WPS_MAX_DIS_AP_NUM]; - u8 discard_ap_cnt; - bool intermediate_disconnect; + bool post_m8_recv; }; #define API_MUTEX_TAKE() do {\ @@ -105,8 +79,6 @@ struct wps_sm { struct wps_sm *wps_sm_get(void); int wps_station_wps_unregister_cb(void); -int wps_start_pending(void); -int wps_sm_rx_eapol(u8 *src_addr, u8 *buf, u32 len); int wps_dev_deinit(struct wps_device_data *dev); int wps_dev_init(void); diff --git a/components/wpa_supplicant/test_apps/main/Kconfig.projbuild b/components/wpa_supplicant/test_apps/main/Kconfig.projbuild new file mode 100644 index 000000000000..56c375789c64 --- /dev/null +++ b/components/wpa_supplicant/test_apps/main/Kconfig.projbuild @@ -0,0 +1,3 @@ +config ESP_WIFI_TESTING_OPTIONS + bool + default y diff --git a/components/wpa_supplicant/test_apps/main/test_eloop.c b/components/wpa_supplicant/test_apps/main/test_eloop.c index c32b635f7dd0..dbbb38475a71 100644 --- a/components/wpa_supplicant/test_apps/main/test_eloop.c +++ b/components/wpa_supplicant/test_apps/main/test_eloop.c @@ -37,6 +37,10 @@ static void callback(void *a, void *b) int32_t ms_diff = (age.sec - timeouts_sec[*i]) * 1000 + (age.usec - timeouts_usec[*i]) / 1000; + if (t > 5) { + TEST_ASSERT(0); + } + /* let's give 50 ms offset for this small block */ if (ms_diff > 50) { executed_order[t] = -1; @@ -80,6 +84,7 @@ TEST_CASE("Test eloop timers run", "[eloop]") /* check the execution order, this will also check whether they were fired at correct time */ TEST_ASSERT(memcmp(execution_order, executed_order, 6 * sizeof(int)) == 0); + t = 0; /* Add timers to check deinit happens gracefully */ for (int i = 0; i < 6; i++) { eloop_register_timeout(timeouts_sec[i], timeouts_usec[i], diff --git a/components/wpa_supplicant/test_apps/main/test_fast_pbkdf2.c b/components/wpa_supplicant/test_apps/main/test_fast_pbkdf2.c index 0bedd60ab46b..29f8977bb638 100644 --- a/components/wpa_supplicant/test_apps/main/test_fast_pbkdf2.c +++ b/components/wpa_supplicant/test_apps/main/test_fast_pbkdf2.c @@ -89,10 +89,12 @@ TEST_CASE("Test pbkdf2", "[crypto-pbkdf2]") } TEST_ASSERT(memcmp(PMK, expected_pmk, PMK_LEN) == 0); +#if 0 start_time = esp_timer_get_time(); fastpbkdf2_hmac_sha1((const u8 *)passphrase, os_strlen((char *)passphrase), ssid, ssid_len, 4096, PMK, PMK_LEN); end_time = esp_timer_get_time(); total_time_fast_pbkdf2 += (end_time - start_time); +#endif } // Calculate average time for pbkdf2_sha1 diff --git a/components/wpa_supplicant/test_apps/main/test_offchannel.c b/components/wpa_supplicant/test_apps/main/test_offchannel.c index b616c19961c6..e0ded0b572b8 100644 --- a/components/wpa_supplicant/test_apps/main/test_offchannel.c +++ b/components/wpa_supplicant/test_apps/main/test_offchannel.c @@ -28,16 +28,13 @@ #include "test_wpa_supplicant_common.h" #include "sdkconfig.h" -#define WIFI_START_EVENT 0x00000001 -#define WIFI_ROC_DONE_EVENT 0x00000002 -#define WIFI_ACTION_RX_EVENT 0x00000003 -#define WIFI_SCAN_DONE_EVENT 0x00000004 +#define WIFI_START_EVENT BIT(0) +#define WIFI_ROC_DONE_EVENT BIT(1) +#define WIFI_ACTION_RX_EVENT BIT(2) +#define WIFI_SCAN_DONE_EVENT BIT(3) #define TEST_LISTEN_CHANNEL 6 -/* No runners; IDF-5046 */ -#if CONFIG_IDF_TARGET_ESP32 - static const char *TAG = "test_offchan"; esp_netif_t *wifi_netif; static EventGroupHandle_t wifi_event; @@ -268,5 +265,3 @@ static void test_wifi_roc(void) } TEST_CASE_MULTIPLE_DEVICES("test ROC and Offchannel Action Frame Tx", "[Offchan][test_env=wifi_two_dut][timeout=90]", test_wifi_roc, test_wifi_offchan_tx); - -#endif //CONFIG_IDF_TARGET_ESP32 diff --git a/components/wpa_supplicant/test_apps/pytest_wpa_supplicant_ut.py b/components/wpa_supplicant/test_apps/pytest_wpa_supplicant_ut.py index 65e7132b5c27..576624e8395d 100644 --- a/components/wpa_supplicant/test_apps/pytest_wpa_supplicant_ut.py +++ b/components/wpa_supplicant/test_apps/pytest_wpa_supplicant_ut.py @@ -19,6 +19,12 @@ def test_wpa_supplicant_ut(dut: Dut) -> None: @pytest.mark.esp32 +@pytest.mark.esp32c3 +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.esp32c5 +@pytest.mark.esp32c6 +@pytest.mark.esp32c61 @pytest.mark.wifi_two_dut @pytest.mark.parametrize( 'count', diff --git a/components/wpa_supplicant/test_apps/sdkconfig.ci b/components/wpa_supplicant/test_apps/sdkconfig.ci new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/docs/conf_common.py b/docs/conf_common.py index c530326f2273..0bcba0101272 100644 --- a/docs/conf_common.py +++ b/docs/conf_common.py @@ -34,6 +34,7 @@ 'api-guides/ble/get-started/ble-device-discovery.rst', 'api-guides/ble/get-started/ble-connection.rst', 'api-guides/ble/get-started/ble-data-exchange.rst', + 'api-guides/low-power-mode/low-power-mode-ble.rst', 'api-reference/bluetooth/bt_le.rst', 'api-reference/bluetooth/esp_gap_ble.rst', 'api-reference/bluetooth/esp_gatt_defs.rst', @@ -103,6 +104,8 @@ UART_DOCS = ['api-reference/peripherals/uart.rst'] +UHCI_DOCS = ['api-reference/peripherals/uhci.rst'] + SDMMC_DOCS = ['api-reference/peripherals/sdmmc_host.rst'] SDIO_SLAVE_DOCS = ['api-reference/peripherals/sdio_slave.rst', @@ -267,6 +270,7 @@ 'SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE':MM_SYNC_DOCS, 'SOC_CLK_TREE_SUPPORTED':CLK_TREE_DOCS, 'SOC_UART_SUPPORTED':UART_DOCS, + 'SOC_UHCI_SUPPORTED':UHCI_DOCS, 'SOC_SDMMC_HOST_SUPPORTED':SDMMC_DOCS, 'SOC_SDIO_SLAVE_SUPPORTED':SDIO_SLAVE_DOCS, 'SOC_MCPWM_SUPPORTED':MCPWM_DOCS, diff --git a/docs/doxygen/Doxyfile b/docs/doxygen/Doxyfile index b1265bfd9f9d..0caa57f88fe1 100644 --- a/docs/doxygen/Doxyfile +++ b/docs/doxygen/Doxyfile @@ -146,6 +146,8 @@ INPUT = \ $(PROJECT_PATH)/components/esp_driver_tsens/include/driver/temperature_sensor_etm.h \ $(PROJECT_PATH)/components/esp_driver_uart/include/driver/uart.h \ $(PROJECT_PATH)/components/esp_driver_uart/include/driver/uart_vfs.h \ + $(PROJECT_PATH)/components/esp_driver_uart/include/driver/uhci.h \ + $(PROJECT_PATH)/components/esp_driver_uart/include/driver/uhci_types.h \ $(PROJECT_PATH)/components/esp_eth/include/esp_eth_com.h \ $(PROJECT_PATH)/components/esp_eth/include/esp_eth_driver.h \ $(PROJECT_PATH)/components/esp_eth/include/esp_eth_mac.h \ @@ -267,6 +269,7 @@ INPUT = \ $(PROJECT_PATH)/components/hal/include/hal/efuse_hal.h \ $(PROJECT_PATH)/components/hal/include/hal/eth_types.h \ $(PROJECT_PATH)/components/hal/include/hal/lp_core_types.h \ + $(PROJECT_PATH)/components/hal/include/hal/uhci_types.h \ $(PROJECT_PATH)/components/heap/include/esp_heap_caps_init.h \ $(PROJECT_PATH)/components/heap/include/esp_heap_caps.h \ $(PROJECT_PATH)/components/heap/include/esp_heap_trace.h \ diff --git a/docs/en/api-guides/ble/ble-feature-support-status.rst b/docs/en/api-guides/ble/ble-feature-support-status.rst index 8cbe9ed1e259..706d1bb04a68 100644 --- a/docs/en/api-guides/ble/ble-feature-support-status.rst +++ b/docs/en/api-guides/ble/ble-feature-support-status.rst @@ -407,7 +407,7 @@ If none of our chip series meet your needs, please contact `customer support tea please consult `SIG Bluetooth Product Database `__. For certain features, if the majority of the development is completed on the Controller, the Host's support status will be limited by the Controller's support status. -If you want BLE Controller and Host to run on different Espressif chips, the functionality of the Host will not be limited by the Controller's support status on the chip running the Host, +If you want Bluetooth LE Controller and Host to run on different Espressif chips, the functionality of the Host will not be limited by the Controller's support status on the chip running the Host, please check the :doc:`ESP Host Feature Support Status Table ` . It is important to clarify that this document is not a binding commitment to our customers. diff --git a/docs/en/api-guides/ble/get-started/ble-data-exchange.rst b/docs/en/api-guides/ble/get-started/ble-data-exchange.rst index e8a00f57ef17..006c134438fb 100644 --- a/docs/en/api-guides/ble/get-started/ble-data-exchange.rst +++ b/docs/en/api-guides/ble/get-started/ble-data-exchange.rst @@ -296,7 +296,7 @@ If you have not completed the ESP-IDF development environment setup, please refe Try It Out ^^^^^^^^^^^^^^^^^^ -Please refer to :ref:`BLE Introduction Try It Out ` 。 +Please refer to :ref:`Bluetooth LE Introduction Try It Out `. Code Explanation diff --git a/docs/en/api-guides/ble/host-feature-support-status.rst b/docs/en/api-guides/ble/host-feature-support-status.rst index 4855371bda67..d17a95bbf9b1 100644 --- a/docs/en/api-guides/ble/host-feature-support-status.rst +++ b/docs/en/api-guides/ble/host-feature-support-status.rst @@ -6,7 +6,7 @@ ESP Host Major Feature Support Status :link_to_translation:`zh_CN:[中文]` The table below shows the support status of major features on ESP-Bluedroid and ESP-NimBLE Host. -If you plan to run the BLE Controller and Host on {IDF_TARGET_NAME} together, the functionality of the Host may be limited by the support status of the Controller, +If you plan to run the Bluetooth LE Controller and Host on {IDF_TARGET_NAME} together, the functionality of the Host may be limited by the support status of the Controller, please check the :doc:`{IDF_TARGET_NAME} Major Feature Support Status Table ` . |supported_def| **This feature has completed development and internal testing.** [1]_ diff --git a/docs/en/api-guides/ble/index.rst b/docs/en/api-guides/ble/index.rst index 2b855e43a1ed..6f203b767e69 100644 --- a/docs/en/api-guides/ble/index.rst +++ b/docs/en/api-guides/ble/index.rst @@ -13,6 +13,7 @@ Overview overview ble-feature-support-status ble-qualification + Low Power Mode Introduction <../low-power-mode/low-power-mode-ble> *************** Get Started diff --git a/docs/en/api-guides/low-power-mode/index.rst b/docs/en/api-guides/low-power-mode/index.rst index c8d4734efb16..6b216535646f 100644 --- a/docs/en/api-guides/low-power-mode/index.rst +++ b/docs/en/api-guides/low-power-mode/index.rst @@ -13,3 +13,4 @@ The standby power consumption plays an important role in embedded IoT applicatio low-power-mode-soc :SOC_WIFI_SUPPORTED: low-power-mode-wifi + :SOC_BLE_SUPPORTED: low-power-mode-ble diff --git a/docs/en/api-guides/low-power-mode/low-power-mode-ble.rst b/docs/en/api-guides/low-power-mode/low-power-mode-ble.rst new file mode 100644 index 000000000000..6a2760507f61 --- /dev/null +++ b/docs/en/api-guides/low-power-mode/low-power-mode-ble.rst @@ -0,0 +1,143 @@ +Introduction to Low Power Mode in Bluetooth\ :sup:`®` Low Energy Scenarios +================================================================================ + +:link_to_translation:`zh_CN:[中文]` + +This section introduces clock source selection in low power modes for Bluetooth Low Energy (Bluetooth LE), along with common related issues. + +Clock Source Selection in Low Power Mode +-------------------------------------------- + +According to the Bluetooth specification, the sleep clock accuracy must be within 500 PPM. Make sure the clock source selected for Bluetooth LE low power mode meets this requirement. Otherwise, Bluetooth LE may not perform normally and can cause a series of problems, such as ACL connection establishment failure or ACL connection timeout. + +Selecting Main XTAL +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +To select the main XTAL as the Bluetooth LE internal clock source, configure the following option: + +.. only:: esp32 + + :ref:`CONFIG_BTDM_CTRL_LOW_POWER_CLOCK` = Main crystal (`CONFIG_BTDM_CTRL_LPCLK_SEL_MAIN_XTAL`) + +.. only:: esp32c3 or esp32s3 + + :ref:`CONFIG_BT_CTRL_LOW_POWER_CLOCK` = Main crystal (`CONFIG_BT_CTRL_LPCLK_SEL_MAIN_XTAL`) + +.. only:: esp32c2 or esp32c6 or esp32h2 or esp32c5 or esp32c61 + + :ref:`CONFIG_BT_LE_LP_CLK_SRC` = Use main XTAL as RTC clock source (`CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL`) + +When this is selected, the main XTAL remains powered on during light-sleep, resulting in higher current consumption. Please refer to :example_file:`Power Save README ` for the typical current consumption in light-sleep using XTAL versus a 32 kHz external crystal. + +Selecting 32 kHz External Crystal +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +To use a 32 kHz external crystal as the Bluetooth LE internal clock source, configure the following options: + +**Configuration Path 1:** + +.. only:: esp32 + + :ref:`CONFIG_BTDM_CTRL_LOW_POWER_CLOCK` = External 32 kHz crystal/oscillator (`CONFIG_BTDM_CTRL_LPCLK_SEL_EXT_32K_XTAL`) + +.. only:: esp32c3 or esp32s3 + + :ref:`CONFIG_BT_CTRL_LOW_POWER_CLOCK` = External 32 kHz crystal/oscillator (`CONFIG_BT_CTRL_LPCLK_SEL_EXT_32K_XTAL`) + +.. only:: esp32c2 or esp32c6 or esp32h2 or esp32c5 or esp32c61 + + :ref:`CONFIG_BT_LE_LP_CLK_SRC` = Use system RTC slow clock source (`CONFIG_BT_LE_LP_CLK_SRC_DEFAULT`) + +**Configuration Path 2:** + +:ref:`CONFIG_RTC_CLK_SRC` = External 32 kHz crystal (`CONFIG_RTC_CLK_SRC_EXT_CRYS`) + +**Note:** Even if 32 kHz is selected in menuconfig, the system will fall back to the main XTAL if the external crystal is not detected during Bluetooth LE initialization. This may lead to unexpected current consumption in light-sleep mode. + +Selecting 136 kHz RC Oscillator +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. only:: esp32c3 or esp32s3 + + To use a 136 kHz internal RC oscillator as the Bluetooth LE internal clock source, configure the following option: + + **Configuration Path 1:** + + :ref:`CONFIG_BT_CTRL_LOW_POWER_CLOCK` = Internal 136kHz RC oscillator (`CONFIG_BT_CTRL_LPCLK_SEL_RTC_SLOW`) + + Generally, the 136 kHz RC oscillator cannot meet the accuracy requirement of Bluetooth LE. It is only suitable for scenarios with low clock accuracy requirements, such as legacy advertising (ADV) or scanning. It does not support connections in central or peripheral roles. + +.. only:: esp32 + + **Note:** ESP32 does not support using 136 kHz RC oscillator as the Bluetooth LE clock source. + +.. only:: esp32c2 or esp32c6 or esp32h2 or esp32c5 or esp32c61 + + To use a 136 kHz internal RC oscillator as the Bluetooth LE internal clock source, configure the following options: + + **Configuration Path 1:** + + :ref:`CONFIG_BT_LE_LP_CLK_SRC` = Use system RTC slow clock source (`CONFIG_BT_LE_LP_CLK_SRC_DEFAULT`) + +.. only:: not esp32 + + **Configuration Path 2:** + + :ref:`CONFIG_RTC_CLK_SRC` = Internal 136 kHz RC oscillator (`CONFIG_RTC_CLK_SRC_INT_RC`) + +.. only:: esp32c2 or esp32c6 or esp32h2 or esp32c5 or esp32c61 + + If low current consumption is required but there is no access to the External 32 kHz Crystal, this clock source is recommended. However, this clock source has a sleep clock accuracy exceeding 500 PPM, which is only supported when pairing with another ESP chip. For non-ESP peer devices, the following Bluetooth LE features are not supported: + + 1. Central role of Connection + 2. Advertiser of Periodic Advertising + + If the peer device also uses 136 kHz RC as the clock source, the following configuration should be set: + + **Configuration Path:** + + - :ref:`CONFIG_BT_LE_LL_PEER_SCA_SET_ENABLE` = y + - :ref:`CONFIG_BT_LE_LL_PEER_SCA` = 3000 + + **Note:** Using the 136 kHz RC oscillator may occasionally cause issues such as connection establishment failures or connection timeouts. + + +How to Check the Current Clock Source Used by Bluetooth LE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +You can check the current Bluetooth LE clock source from the initialization logs: + +.. list-table:: Bluetooth LE Initialization Logs and Clock Sources + :widths: 50 50 + :header-rows: 1 + + * - Log Message + - Clock Source + * - Using main XTAL as clock source + - Main XTAL + * - Using 136 kHz RC as clock source + - Internal 136 kHz RC oscillator + * - Using external 32.768 kHz crystal as clock source + - External 32 kHz crystal + * - Using external 32.768 kHz oscillator at 32K_XP pin as clock source + - External 32 kHz oscillator at 32K_XP pin + + +FAQ +-------------------------------------- + +1. Bluetooth LE ACL Connection Fails or Disconnects in Low Power Mode +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +As explained in the clock source selection section above, when ACL connections fail to establish or unexpectedly disconnect in low power mode, first verify whether the current clock source meets Bluetooth LE accuracy requirements. + + +2. Measured light-sleep Current Higher Than Expected +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +As described in the clock source selection section above, if the main XTAL is used as the clock source, it remains powered on during light-sleep, resulting in higher current consumption than other clock sources. The average current may vary depending on the specific application, Bluetooth LE configuration, and the duration spent in light-sleep. Some applications may have higher average current because Bluetooth LE is active for a larger proportion of the time transmitting and receiving. + +3. Unable to Enter light-sleep Mode +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +If Auto light-sleep is enabled but the device fails to enter light-sleep, it's usually due to insufficient IDLE time, which prevents the automatic entry conditions from being met. This can be caused by excessive logging or Bluetooth LE configurations that reduce IDLE time, such as continuous scanning. diff --git a/docs/en/api-guides/low-power-mode/low-power-mode-soc.rst b/docs/en/api-guides/low-power-mode/low-power-mode-soc.rst index 460a5c7bf5c9..2cc3315a8aef 100644 --- a/docs/en/api-guides/low-power-mode/low-power-mode-soc.rst +++ b/docs/en/api-guides/low-power-mode/low-power-mode-soc.rst @@ -271,6 +271,9 @@ This section introduces the recommended configuration and configuration steps fo - Power down CPU (:ref:`CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP`) + .. only:: esp32p4 + + For ESP32P4, only revisions greater than 3.0 support the CPU power domain individual power-down. .. only:: SOC_PM_SUPPORT_TAGMEM_PD diff --git a/docs/en/api-guides/performance/ram-usage.rst b/docs/en/api-guides/performance/ram-usage.rst index 61d3da465480..f51d9cb6a2d0 100644 --- a/docs/en/api-guides/performance/ram-usage.rst +++ b/docs/en/api-guides/performance/ram-usage.rst @@ -83,7 +83,7 @@ The Stack Canary Bytes feature adds a set of magic bytes at the end of each task Run-time Methods to Determine Stack Size ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -- The :cpp:func:`uxTaskGetStackHighWaterMark` returns the minimum free stack memory of a task throughout the task's lifetime, which gives a good indication of how much stack memory is left unused by a task. +- The :cpp:func:`uxTaskGetStackHighWaterMark` returns the minimum free stack memory of a task throughout the task's lifetime in bytes, which gives a good indication of how much stack memory is left unused by a task. Note that on {IDF_TARGET_NAME}, the function returns the value in bytes (not words as stated in the standard FreeRTOS documentation). - The easiest time to call :cpp:func:`uxTaskGetStackHighWaterMark` is from the task itself: call ``uxTaskGetStackHighWaterMark(NULL)`` to get the current task's high water mark after the time that the task has achieved its peak stack usage, i.e., if there is a main loop, execute the main loop a number of times with all possible states, and then call :cpp:func:`uxTaskGetStackHighWaterMark`. - Often, it is possible to subtract almost the entire value returned here from the total stack size of a task, but allow some safety margin to account for unexpected small increases in stack usage at runtime. diff --git a/docs/en/api-guides/tools/idf-docker-image.rst b/docs/en/api-guides/tools/idf-docker-image.rst index 9d1ca753da61..37e1ed8785b6 100644 --- a/docs/en/api-guides/tools/idf-docker-image.rst +++ b/docs/en/api-guides/tools/idf-docker-image.rst @@ -150,6 +150,7 @@ The Docker file in ESP-IDF repository provides several build arguments which can - ``IDF_CLONE_SHALLOW``: If this argument is set to a non-empty value, ``--depth=1 --shallow-submodules`` arguments are used when performing ``git clone``. Depth can be customized using ``IDF_CLONE_SHALLOW_DEPTH``. Doing a shallow clone significantly reduces the amount of data downloaded and the size of the resulting Docker image. However, if switching to a different branch in such a "shallow" repository is necessary, an additional ``git fetch origin `` command must be executed first. - ``IDF_CLONE_SHALLOW_DEPTH``: This argument specifies the depth value to use when doing a shallow clone. If not set, ``--depth=1`` will be used. This argument has effect only if ``IDF_CLONE_SHALLOW`` is used. Use this argument if you are building a Docker image for a branch, and the image has to contain the latest tag on that branch. To determine the required depth, run ``git describe`` for the given branch and note the offset number. Increment it by 1, then use it as the value of this argument. The resulting image will contain the latest tag on the branch, and consequently ``git describe`` command inside the Docker image will work as expected. - ``IDF_INSTALL_TARGETS``: Comma-separated list of ESP-IDF targets to install toolchains for, or ``all`` to install toolchains for all targets. Selecting specific targets reduces the amount of data downloaded and the size of the resulting Docker image. The default is ``all``. +- ``IDF_GITHUB_ASSETS``: Hostname used to download ESP-IDF tools from a mirror server instead of directly from ``github.com``. This is useful when ``github.com`` is not accessible from your network. The default value is empty. To use these arguments, pass them via the ``--build-arg`` command line option. For example, the following command builds a Docker image with a shallow clone of ESP-IDF v4.4.1 and tools for ESP32-C3 only: diff --git a/docs/en/api-reference/peripherals/lcd/dsi_lcd.rst b/docs/en/api-reference/peripherals/lcd/dsi_lcd.rst index c44c288bfa05..b1a47b664021 100644 --- a/docs/en/api-reference/peripherals/lcd/dsi_lcd.rst +++ b/docs/en/api-reference/peripherals/lcd/dsi_lcd.rst @@ -11,7 +11,6 @@ MIPI DSI Interfaced LCD esp_lcd_dsi_bus_config_t bus_config = { .bus_id = 0, // index from 0, specify the DSI host to use .num_data_lanes = 2, // Number of data lanes to use, can't set a value that exceeds the chip's capability - .phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT, // Clock source for the DPHY .lane_bit_rate_mbps = EXAMPLE_MIPI_DSI_LANE_BITRATE_MBPS, // Bit rate of the data lanes, in Mbps }; ESP_ERROR_CHECK(esp_lcd_new_dsi_bus(&bus_config, &mipi_dsi_bus)); diff --git a/docs/en/api-reference/peripherals/rmt.rst b/docs/en/api-reference/peripherals/rmt.rst index 07f868a07096..b30c94f1db41 100644 --- a/docs/en/api-reference/peripherals/rmt.rst +++ b/docs/en/api-reference/peripherals/rmt.rst @@ -257,7 +257,7 @@ Once you created an encoder, you can initiate a TX transaction by calling :cpp:f .. note:: - There is a limitation in the transmission size if the :cpp:member:`rmt_transmit_config_t::loop_count` is set to non-zero, i.e., to enable the loop feature. The encoded RMT symbols should not exceed the capacity of the RMT hardware memory block size, or you might see an error message like ``encoding artifacts can't exceed hw memory block for loop transmission``. If you have to start a large transaction by loop, you can try either of the following methods. + There is a limitation in the transmission size if the :cpp:member:`rmt_transmit_config_t::loop_count` is set to non-zero, i.e., to enable the loop feature. The total amount of symbols returned by the encoder should not exceed the capacity of :c:macro:`SOC_RMT_MEM_WORDS_PER_CHANNEL`, or you might see an error message like ``encoding artifacts can't exceed hw memory block for loop transmission``. If you have to start a large transaction by loop, you can try either of the following methods. - Increase the :cpp:member:`rmt_tx_channel_config_t::mem_block_symbols`. This approach does not work if the DMA backend is also enabled. - Customize an encoder and construct an infinite loop in the encoding function. See also :ref:`rmt-rmt-encoder`. diff --git a/docs/en/api-reference/peripherals/temp_sensor.rst b/docs/en/api-reference/peripherals/temp_sensor.rst index ca7231e6e1e2..1c2ca965c5ef 100644 --- a/docs/en/api-reference/peripherals/temp_sensor.rst +++ b/docs/en/api-reference/peripherals/temp_sensor.rst @@ -8,29 +8,9 @@ Introduction The {IDF_TARGET_NAME} has a built-in sensor used to measure the chip's internal temperature. The temperature sensor module contains an 8-bit Sigma-Delta analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) to compensate for the temperature measurement. -Due to restrictions of hardware, the sensor has predefined measurement ranges with specific measurement errors. See the table below for details. - -.. list-table:: - :header-rows: 1 - :widths: 50 50 - :align: center - - * - Predefined Range (°C) - - Error (°C) - * - 50 ~ 125 - - < 3 - * - 20 ~ 100 - - < 2 - * - -10 ~ 80 - - < 1 - * - -30 ~ 50 - - < 2 - * - -40 ~ 20 - - < 3 - .. note:: - The temperature sensor is designed primarily to measure the temperature changes inside the chip. The internal temperature of a chip is usually higher than the ambient temperature, and is affected by factors such as the microcontroller's clock frequency or I/O load, and the external thermal environment. + The temperature sensor is designed primarily to measure the temperature **inside** the silicon. The sensor can reflect the temperature changes very well but it can't give a precise measurement value. So it's not recommended to use it for ambient temperature measurement. Functional Overview ------------------- diff --git a/docs/en/api-reference/peripherals/uart.rst b/docs/en/api-reference/peripherals/uart.rst index 5187f7cd8cc1..02484734397c 100644 --- a/docs/en/api-reference/peripherals/uart.rst +++ b/docs/en/api-reference/peripherals/uart.rst @@ -18,6 +18,15 @@ Each UART controller is independently configurable with parameters such as baud Additionally, the {IDF_TARGET_NAME} chip has one low-power (LP) UART controller. It is the cut-down version of regular UART. Usually, the LP UART controller only support basic UART functionality with a much smaller RAM size, and does not support IrDA or RS485 protocols. For a full list of difference between UART and LP UART, please refer to the **{IDF_TARGET_NAME} Technical Reference Manual** > **UART Controller (UART)** > **Features** [`PDF <{IDF_TARGET_TRM_EN_URL}#uart>`__]). +.. only:: SOC_UHCI_SUPPORTED + + .. toctree:: + :hidden: + + uhci + + The {IDF_TARGET_NAME} chip also supports using DMA with UART. For details, see to :doc:`uhci`. + Functional Overview ------------------- @@ -230,7 +239,7 @@ The UART controller supports a number of communication modes. A mode can be sele Use Interrupts ^^^^^^^^^^^^^^^^ -There are many interrupts that can be generated depending on specific UART states or detected errors. The full list of available interrupts is provided in *{IDF_TARGET_NAME} Technical Reference Manual* > *UART Controller (UART)* > *UART Interrupts* and *UHCI Interrupts* [`PDF <{IDF_TARGET_TRM_EN_URL}#uart>`__]. You can enable or disable specific interrupts by calling :cpp:func:`uart_enable_intr_mask` or :cpp:func:`uart_disable_intr_mask` respectively. +There are many interrupts that can be generated depending on specific UART states or detected errors. The full list of available interrupts is provided in *{IDF_TARGET_NAME} Technical Reference Manual* > *UART Controller (UART)* > *UART Interrupts* [`PDF <{IDF_TARGET_TRM_EN_URL}#uart>`__]. You can enable or disable specific interrupts by calling :cpp:func:`uart_enable_intr_mask` or :cpp:func:`uart_disable_intr_mask` respectively. The UART driver provides a convenient way to handle specific interrupts by wrapping them into corresponding events. Events defined in :cpp:type:`uart_event_type_t` can be reported to a user application using the FreeRTOS queue functionality. diff --git a/docs/en/api-reference/peripherals/uhci.rst b/docs/en/api-reference/peripherals/uhci.rst new file mode 100644 index 000000000000..a3e4dab66cda --- /dev/null +++ b/docs/en/api-reference/peripherals/uhci.rst @@ -0,0 +1,299 @@ +UART DMA (UHCI) +=============== + +:link_to_translation:`zh_CN:[中文]` + +This document describes the functionality of the UART DMA(UHCI) driver in ESP-IDF. The table of contents is as follows: + +.. contents:: + :local: + :depth: 2 + +Introduction +------------ + +This document shows how to use UART and DMA together for transmitting or receiving large data volumes using high baud rates. {IDF_TARGET_SOC_UART_HP_NUM} HP UART controllers on {IDF_TARGET_NAME} share one group of DMA TX/RX channels via host controller interface (HCI). This document assumes that UART DMA is controlled by UHCI entity. + +.. note:: + + The UART DMA shares the HCI hardware with Bluetooth, so please don't use BT HCI together with UART DMA, even if they use different UART ports. + +Quick Start +----------- + +This section will quickly guide you on how to use the UHCI driver. Through a simple example including transmitting and receiving, it demonstrates how to create and start a UHCI, initiate a transmit and receive transactions, and register event callback functions. The general usage process is as follows: + +Creating and Enabling the UHCI controller +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +UHCI controller requires the configuration specified by :cpp:type:`uhci_controller_config_t`. + +If the configurations in :cpp:type:`uhci_controller_config_t` is specified, users can call :cpp:func:`uhci_new_controller` to allocate and initialize a uhci controller. This function will return a uhci controller handle if it runs correctly. Besides, UHCI must work with the installed UART driver. As a reference, see the code below. + +.. code:: c + + #define EX_UART_NUM 1 // Define UART port number + + // For uart port configuration, please refer to UART programming guide. + // Please double-check as the baud rate might be limited by serial port chips. + uart_config_t uart_config = { + .baud_rate = 1 * 1000 * 1000, + .data_bits = UART_DATA_8_BITS, + .parity = UART_PARITY_DISABLE, + .stop_bits = UART_STOP_BITS_1, + .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, + .source_clk = UART_SCLK_DEFAULT, + }; + + //UART parameter config + ESP_ERROR_CHECK(uart_param_config(EX_UART_NUM, &uart_config)); + ESP_ERROR_CHECK(uart_set_pin(EX_UART_NUM, UART_TX_IO, UART_RX_IO, -1, -1)); + + uhci_controller_config_t uhci_cfg = { + .uart_port = EX_UART_NUM, // Connect uart port to UHCI hardware. + .tx_trans_queue_depth = 30, // Queue depth of transaction queue. + .max_receive_internal_mem = 10 * 1024, // internal memory usage, for more information, please refer to API reference. + .max_transmit_size = 10 * 1024, // Maximum transfer size in one transaction, in bytes. + .dma_burst_size = 32, // Burst size. + .rx_eof_flags.idle_eof = 1, // When to trigger a end of frame event, you can choose `idle_eof`, `rx_brk_eof`, `length_eof`, for more information, please refer to API reference. + }; + + uhci_controller_handle_t uhci_ctrl; + + ESP_ERROR_CHECK(uhci_new_controller(&uhci_cfg, &uhci_ctrl)); + +Register Event Callbacks +^^^^^^^^^^^^^^^^^^^^^^^^ + +When an event occurs on the UHCI controller (e.g., transmission or receiving is completed), the CPU is notified of this event via an interrupt. If there is a function that needs to be called when a particular events occur, you can register a callback for that event with the ISR for UHCI (Interrupt Service Routine) by calling :cpp:func:`uhci_register_event_callbacks` for both TX and RX respectively. Since the registered callback functions are called in the interrupt context, the user should ensure that the callback function is non-blocking, e.g., by making sure that only FreeRTOS APIs with the ``FromISR`` suffix are called from within the function. The callback function has a boolean return value used to indicate whether a higher priority task has been unblocked by the callback. + +The UHCI event callbacks are listed in the :cpp:type:`uhci_event_callbacks_t`: + +- :cpp:member:`uhci_event_callbacks_t::on_tx_trans_done` sets a callback function for the "trans-done" event. The function prototype is declared in :cpp:type:`uhci_tx_done_callback_t`. + +- :cpp:member:`uhci_event_callbacks_t::on_rx_trans_event` sets a callback function for "receive" event. The function prototype is declared in :cpp:type:`uhci_rx_event_callback_t`. + +.. note:: + + The "rx-trans-event" is not equivalent to "receive-finished". This callback can also be called at a "partial-received" time, for many times during one receive transaction, which can be notified by :cpp:member:`uhci_rx_event_data_t::flags::totally_received`. + +Users can save their own context in :cpp:func:`uhci_register_event_callbacks` as well, via the parameter ``user_data``. The user data is directly passed to each callback function. + +In the callback function, users can fetch the event-specific data that is filled by the driver in the ``edata``. Note that the ``edata`` pointer is **only** valid during the callback, please do not try to save this pointer and use that outside of the callback function. + +The TX event data is defined in :cpp:type:`uhci_tx_done_event_data_t`: + +- :cpp:member:`uhci_tx_done_event_data_t::buffer` indicates the buffer has been sent out. + +The RX event data is defined in :cpp:type:`uhci_rx_event_data_t`: + +- :cpp:member:`uhci_rx_event_data_t::data` points to the received data. The data is saved in the ``buffer`` parameter of the :cpp:func:`uhci_receive` function. Users should not free this receive buffer before the callback returns. +- :cpp:member:`uhci_rx_event_data_t::recv_size` indicates the number of received data. This value is not larger than the ``buffer_size`` parameter of :cpp:func:`uhci_receive` function. +- :cpp:member:`uhci_rx_event_data_t::flags::totally_received` indicates whether the current received buffer is the last one in the transaction. + +Initiating UHCI Transmission +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +:cpp:func:`uhci_transmit` is a non-blocking function, which means this function will immediately return after you call it. The related callback can be obtained via :cpp:member:`uhci_event_callbacks_t::on_tx_trans_done` to indicate that the transaction is done. The function :cpp:func:`uhci_wait_all_tx_transaction_done` can be used to indicate that all transactions are finished. + +Data can be transmitted via UHCI as follows: + +.. code:: c + + uint8_t data_wr[DATA_LENGTH]; + for (int i = 0; i < DATA_LENGTH; i++) { + data_wr[i] = i; + } + ESP_ERROR_CHECK(uhci_transmit(uhci_ctrl, data_wr, DATA_LENGTH)); + // Wait all transaction finishes + ESP_ERROR_CHECK(uhci_wait_all_tx_transaction_done(uhci_ctrl, -1)); + +Initiating UHCI Reception +^^^^^^^^^^^^^^^^^^^^^^^^^ + +:cpp:func:`uhci_receive` is a non-blocking function, which means this function will immediately return after it is called. The related callback can be obtained via :cpp:member:`uhci_rx_event_data_t::recv_size` to indicate the receive event. It can be useful to determine if a transaction has been finished. + +Data can be transmitted via UHCI as follows: + +.. code:: c + + // global variable: handle of queue. + QueueHandle_t uhci_queue; + + IRAM_ATTR static bool s_uhci_rx_event_cbs(uhci_controller_handle_t uhci_ctrl, const uhci_rx_event_data_t *edata, void *user_ctx) + { + // parameter `user_ctx` is parsed by the third parameter of function `uhci_register_event_callbacks` + uhci_context_t *ctx = (uhci_context_t *)user_ctx; + BaseType_t xTaskWoken = 0; + uhci_event_t evt = 0; + if (edata->flags.totally_received) { + evt = UHCI_EVT_EOF; + ctx->receive_size += edata->recv_size; + memcpy(ctx->p_receive_data, edata->data, edata->recv_size); + } else { + evt = UHCI_EVT_PARTIAL_DATA; + ctx->receive_size += edata->recv_size; + memcpy(ctx->p_receive_data, edata->data, edata->recv_size); + ctx->p_receive_data += edata->recv_size; + } + + xQueueSendFromISR(ctx->uhci_queue, &evt, &xTaskWoken); + return xTaskWoken; + } + + // In task + uhci_event_callbacks_t uhci_cbs = { + .on_rx_trans_event = s_uhci_rx_event_cbs, + }; + + // Register callback and start reception. + ESP_ERROR_CHECK(uhci_register_event_callbacks(uhci_ctrl, &uhci_cbs, ctx)); + ESP_ERROR_CHECK(uhci_receive(uhci_ctrl, pdata, 100)); + + uhci_event_t evt; + while (1) { + // A queue in task for receiving event triggered by UHCI. + if (xQueueReceive(ctx->uhci_queue, &evt, portMAX_DELAY) == pdTRUE) { + if (evt == UHCI_EVT_EOF) { + printf("Received size: %d\n", ctx->receive_size); + break; + } + } + } + +In the API :cpp:func:`uhci_receive` interface, the parameter `read_buffer` is a buffer that must be provided by the user, and parameter `buffer_size` represents the size of the buffer supplied by the user. In the configuration structure of the UHCI controller, the parameter :cpp:member:`uhci_controller_config_t::max_receive_internal_mem` specifies the desired size of the internal DMA working space. The software allocates a certain number of DMA nodes based on this working space size. These nodes form a circular linked list. + +When a node is filled, but the reception has not yet completed, the event :cpp:member:`uhci_event_callbacks_t::on_rx_trans_event` will be triggered, accompanied by :cpp:member:`uhci_rx_event_data_t::flags::totally_received` set to 0. When all the data has been fully received, the :cpp:member:`uhci_event_callbacks_t::on_rx_trans_event` event will be triggered again with :cpp:member:`uhci_rx_event_data_t::flags::totally_received` set to 1. + +This mechanism allows the user to achieve continuous and fast reception using a relatively small buffer, without needing to allocate a buffer the same size as the total data being received. + +.. note:: + + The parameter `read_buffer` of :cpp:func:`uhci_receive` cannot be freed until receive finishes. + +Uninstall UHCI controller +^^^^^^^^^^^^^^^^^^^^^^^^^ + +If a previously installed UHCI controller is no longer needed, it's recommended to recycle the resource by calling :cpp:func:`uhci_del_controller`, so that the underlying hardware is released. + +.. code:: c + + ESP_ERROR_CHECK(uhci_del_controller(uhci_ctrl)); + +Advanced Features +----------------- + +As the basic usage has been covered, it's time to explore more advanced features of the UHCI driver. + +Power Management +^^^^^^^^^^^^^^^^ + +When power management is enabled, i.e., :ref:`CONFIG_PM_ENABLE` is on, the system may adjust or disable the clock source before going to sleep. As a result, the FIFO inside the UHCI can't work as expected. + +The driver can prevent the above issue by creating a power management lock. The lock type is set based on different clock sources. The driver will acquire the lock in :cpp:func:`uhci_receive` or :cpp:func:`uhci_transmit`, and release it in the transaction-done interrupt. That means, any UHCI transactions between these two functions are guaranteed to work correctly and stably. + +Cache Safe +^^^^^^^^^^ + +By default, the interrupt on which UHCI relies is deferred when the Cache is disabled for reasons such as writing or erasing the main flash. Thus, the transaction-done interrupt fails to be handled in time, which is unacceptable in a real-time application. What is worse, when the UHCI transaction relies on **ping-pong** interrupt to successively encode or copy the UHCI buffer, a delayed interrupt can lead to an unpredictable result. + +There is a Kconfig option :ref:`CONFIG_UHCI_ISR_CACHE_SAFE` that has the following features: + +1. Enable the interrupt being serviced even when the cache is disabled +2. Place all functions used by the ISR into IRAM [1]_ +3. Place the driver object into DRAM in case it is mapped to PSRAM by accident + +This Kconfig option allows the interrupt handler to run while the cache is disabled but comes at the cost of increased IRAM consumption. + +Resource Consumption +^^^^^^^^^^^^^^^^^^^^ + +Use the :doc:`/api-guides/tools/idf-size` tool to check the code and data consumption of the UHCI driver. The following are the test results under 2 different conditions (using ESP32-C3 as an example): + +**Note that the following data are not exact values and are for reference only; they may differ on different chip models.** + +Resource consumption when :ref:`CONFIG_UHCI_ISR_CACHE_SAFE` is enabled: + +.. list-table:: Resource Consumption + :widths: 10 10 10 10 10 10 10 10 10 + :header-rows: 1 + + * - Component Layer + - Total Size + - DIRAM + - .bss + - .data + - .text + - Flash Code + - Flash Data + - .rodata + * - UHCI + - 5733 + - 680 + - 8 + - 34 + - 638 + - 4878 + - 175 + - 175 + +Resource consumption when :ref:`CONFIG_UHCI_ISR_CACHE_SAFE` is disabled: + +.. list-table:: Resource Consumption + :widths: 10 10 10 10 10 10 10 10 10 10 + :header-rows: 1 + + * - Component Layer + - Total Size + - DIRAM + - .bss + - .data + - .text + - Flash Code + - .text + - Flash Data + - .rodata + * - UHCI + - 5479 + - 42 + - 8 + - 34 + - 0 + - 5262 + - 5262 + - 175 + - 175 + +Performance +^^^^^^^^^^^ + +To improve the real-time response capability of interrupt handling, the UHCI driver provides the :ref:`CONFIG_UHCI_ISR_HANDLER_IN_IRAM` option. Enabling this option will place the interrupt handler in internal RAM, reducing the latency caused by cache misses when loading instructions from Flash. + +.. note:: + + However, user callback functions and context data called by the interrupt handler may still be located in Flash, and cache miss issues will still exist. Users need to place callback functions and data in internal RAM, for example, using :c:macro:`IRAM_ATTR` and :c:macro:`DRAM_ATTR`. + +Thread Safety +^^^^^^^^^^^^^ + +The factory function :cpp:func:`uhci_new_controller`, :cpp:func:`uhci_register_event_callbacks` and :cpp:func:`uhci_del_controller` are guaranteed to be thread safe by the driver, which means, user can call them from different RTOS tasks without protection by extra locks. + +Other Kconfig Options +^^^^^^^^^^^^^^^^^^^^^ + +- :ref:`CONFIG_UHCI_ENABLE_DEBUG_LOG` is allowed for the forced enabling of all debug logs for the UHCI driver, regardless of the global log level setting. Enabling this option can help developers obtain more detailed log information during the debugging process, making it easier to locate and resolve issues, but it will increase the size of the firmware binary. + +Application Examples +-------------------- + +- :example:`peripherals/uart/uart_dma_ota` demonstrates how to use the uart dma for fast OTA the chip firmware with 1M baud rate speed. + +API Reference +------------- + +.. include-build-file:: inc/uhci.inc +.. include-build-file:: inc/components/esp_driver_uart/include/driver/uhci_types.inc +.. include-build-file:: inc/components/hal/include/hal/uhci_types.inc + +.. [1] + The callback function, e.g., :cpp:member:`uhci_event_callbacks_t::on_tx_trans_done`, :cpp:member:`uhci_event_callbacks_t::on_rx_trans_event` and the functions invoked by itself should also reside in IRAM, users need to take care of this by themselves. diff --git a/docs/en/api-reference/system/power_management.rst b/docs/en/api-reference/system/power_management.rst index c21ecde46860..4e997705d434 100644 --- a/docs/en/api-reference/system/power_management.rst +++ b/docs/en/api-reference/system/power_management.rst @@ -116,7 +116,7 @@ The following drivers hold the ``ESP_PM_APB_FREQ_MAX`` lock while the driver is - **Ethernet**: between calls to :cpp:func:`esp_eth_driver_install` and :cpp:func:`esp_eth_driver_uninstall`. :SOC_WIFI_SUPPORTED: - **WiFi**: between calls to :cpp:func:`esp_wifi_start` and :cpp:func:`esp_wifi_stop`. If modem sleep is enabled, the lock will be released for the periods of time when radio is disabled. :SOC_TWAI_SUPPORTED: - **TWAI**: between calls to :cpp:func:`twai_driver_install` and :cpp:func:`twai_driver_uninstall` (only when the clock source is set to :cpp:enumerator:`TWAI_CLK_SRC_APB`). - :SOC_BT_SUPPORTED and esp32: - **Bluetooth**: between calls to :cpp:func:`esp_bt_controller_enable` and :cpp:func:`esp_bt_controller_disable`. If Bluetooth Modem-sleep is enabled, the ``ESP_PM_APB_FREQ_MAX`` lock will be released for the periods of time when radio is disabled. However the ``ESP_PM_NO_LIGHT_SLEEP`` lock will still be held, unless :ref:`CONFIG_BTDM_CTRL_LOW_POWER_CLOCK` option is set to "External 32kHz crystal". + :SOC_BT_SUPPORTED and esp32: - **Bluetooth**: between calls to :cpp:func:`esp_bt_controller_enable` and :cpp:func:`esp_bt_controller_disable`. If Bluetooth Modem-sleep is enabled, the ``ESP_PM_APB_FREQ_MAX`` lock will be released for the periods of time when radio is disabled. However the ``ESP_PM_NO_LIGHT_SLEEP`` lock will still be held, unless :ref:`CONFIG_BTDM_CTRL_LOW_POWER_CLOCK` option is set to "External 32 kHz crystal". :SOC_BT_SUPPORTED and not esp32: - **Bluetooth**: between calls to :cpp:func:`esp_bt_controller_enable` and :cpp:func:`esp_bt_controller_disable`. If Bluetooth Modem-sleep is enabled, the ``ESP_PM_APB_FREQ_MAX`` lock will be released for the periods of time when radio is disabled. However the ``ESP_PM_NO_LIGHT_SLEEP`` lock will still be held. :SOC_PCNT_SUPPORTED: - **PCNT**: between calls to :cpp:func:`pcnt_unit_enable` and :cpp:func:`pcnt_unit_disable`. :SOC_SDM_SUPPORTED: - **Sigma-delta**: between calls to :cpp:func:`sdm_channel_enable` and :cpp:func:`sdm_channel_disable`. diff --git a/docs/zh_CN/api-guides/ble/blufi.rst b/docs/zh_CN/api-guides/ble/blufi.rst index d747c1b4dd35..a8c697721b0c 100644 --- a/docs/zh_CN/api-guides/ble/blufi.rst +++ b/docs/zh_CN/api-guides/ble/blufi.rst @@ -223,9 +223,9 @@ ACK 帧格式 (8 bit)： - * - 0x8 (b’001000) - - 断开 BLE GATT 连接。 + - 断开低功耗蓝牙 GATT 连接。 - - - ESP 设备收到该指令后主动断开 BLE GATT 连接。 + - ESP 设备收到该指令后主动断开低功耗蓝牙 GATT 连接。 * - 0x9 (b’001001) - 获取 Wi-Fi 列表。 diff --git a/docs/zh_CN/api-guides/ble/get-started/ble-data-exchange.rst b/docs/zh_CN/api-guides/ble/get-started/ble-data-exchange.rst index dc0450ccb6f1..e4fa437d9662 100644 --- a/docs/zh_CN/api-guides/ble/get-started/ble-data-exchange.rst +++ b/docs/zh_CN/api-guides/ble/get-started/ble-data-exchange.rst @@ -296,7 +296,7 @@ GATT 数据操作 动手试试 ^^^^^^^^^^^^^^^^^^ -请参考 :ref:`BLE 介绍 动手试试 ` 。 +请参考 :ref:`低功耗蓝牙介绍 动手试试 ` 。 代码详解 diff --git a/docs/zh_CN/api-guides/ble/index.rst b/docs/zh_CN/api-guides/ble/index.rst index c785a73c7e6c..05b87f9d144c 100644 --- a/docs/zh_CN/api-guides/ble/index.rst +++ b/docs/zh_CN/api-guides/ble/index.rst @@ -13,6 +13,7 @@ overview ble-feature-support-status ble-qualification + 低功耗模式介绍 <../low-power-mode/low-power-mode-ble> ********** 快速入门 diff --git a/docs/zh_CN/api-guides/low-power-mode/index.rst b/docs/zh_CN/api-guides/low-power-mode/index.rst index 8c1d526cfe41..efa345c3becf 100644 --- a/docs/zh_CN/api-guides/low-power-mode/index.rst +++ b/docs/zh_CN/api-guides/low-power-mode/index.rst @@ -13,3 +13,4 @@ low-power-mode-soc :SOC_WIFI_SUPPORTED: low-power-mode-wifi + :SOC_BLE_SUPPORTED: low-power-mode-ble diff --git a/docs/zh_CN/api-guides/low-power-mode/low-power-mode-ble.rst b/docs/zh_CN/api-guides/low-power-mode/low-power-mode-ble.rst new file mode 100644 index 000000000000..0f2aabe1ef53 --- /dev/null +++ b/docs/zh_CN/api-guides/low-power-mode/low-power-mode-ble.rst @@ -0,0 +1,143 @@ +低功耗蓝牙\ :sup:`®` 场景下低功耗模式介绍 +======================================================================== + +:link_to_translation:`en:[English]` + +本节介绍低功耗蓝牙 (Bluetooth LE) 在低功耗模式下的时钟源选择，以及常见相关问题。 + +低功耗模式下的时钟源选择 +-------------------------------------------- + +在低功耗蓝牙应用场景中，由于协议要求休眠时钟精度需在 500 PPM 以内，light-sleep 和 modem-sleep 模式下所用的时钟源必须满足该要求。如果时钟精度不足，可能会出现 ACL 连接失败或超时断开等问题。**因此在使用前请确保所选时钟源及其精度满足要求。** + +选择主晶振 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +要选择主晶振作为低功耗蓝牙内部时钟源，请配置以下选项： + +.. only:: esp32 + + :ref:`CONFIG_BTDM_CTRL_LOW_POWER_CLOCK` = Main crystal (`CONFIG_BTDM_CTRL_LPCLK_SEL_MAIN_XTAL`) + +.. only:: esp32c3 or esp32s3 + + :ref:`CONFIG_BT_CTRL_LOW_POWER_CLOCK` = Main crystal (`CONFIG_BT_CTRL_LPCLK_SEL_MAIN_XTAL`) + +.. only:: esp32c2 or esp32c6 or esp32h2 or esp32c5 or esp32c61 + + :ref:`CONFIG_BT_LE_LP_CLK_SRC` = Use main XTAL as RTC clock source (`CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL`) + +选择主晶振后，light-sleep 模式下主晶振电源不会关闭，因此电流消耗更高。有关使用主晶振与 32 kHz 外部晶振在 light-sleep 模式下的典型电流消耗，请参考 :example_file:`Power Save README ` 。 + +选择 32 kHz 外部晶振 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +要使用 32 kHz 外部晶振作为低功耗蓝牙内部时钟源，请配置以下选项： + +**配置路径 1：** + +.. only:: esp32 + + :ref:`CONFIG_BTDM_CTRL_LOW_POWER_CLOCK` = External 32 kHz crystal/oscillator (`CONFIG_BTDM_CTRL_LPCLK_SEL_EXT_32K_XTAL`) + +.. only:: esp32c3 or esp32s3 + + :ref:`CONFIG_BT_CTRL_LOW_POWER_CLOCK` = External 32 kHz crystal/oscillator (`CONFIG_BT_CTRL_LPCLK_SEL_EXT_32K_XTAL`) + +.. only:: esp32c2 or esp32c6 or esp32h2 or esp32c5 or esp32c61 + + :ref:`CONFIG_BT_LE_LP_CLK_SRC` = Use system RTC slow clock source (`CONFIG_BT_LE_LP_CLK_SRC_DEFAULT`) + +**配置路径 2：** + +:ref:`CONFIG_RTC_CLK_SRC` = External 32 kHz crystal (`CONFIG_RTC_CLK_SRC_EXT_CRYS`) + +**注意：** 即使在 menuconfig 中选择了 32 kHz 外部晶振，如果低功耗蓝牙初始化时未检测到外部晶振，系统会自动切换为主晶振，可能导致 light-sleep 电流高于预期。 + +选择 136 kHz RC 振荡器 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. only:: esp32c3 or esp32s3 + + 要使用 136 kHz 内部 RC 振荡器作为低功耗蓝牙内部时钟源，请配置以下选项： + + **配置路径 1：** + + :ref:`CONFIG_BT_CTRL_LOW_POWER_CLOCK` = Internal 136kHz RC oscillator (`CONFIG_BT_CTRL_LPCLK_SEL_RTC_SLOW`) + + 一般来说，136 kHz RC 振荡器难以满足低功耗蓝牙的精度要求，仅适用于对时钟精度要求不高的场景，如传统广播 (ADV) 或扫描 (SCAN)。它不支持以中心角色或外设角色建立连接。 + +.. only:: esp32 + + **注意：** ESP32 不支持 136 kHz RC 振荡器作为低功耗蓝牙时钟源。 + +.. only:: esp32c2 or esp32c6 or esp32h2 or esp32c5 or esp32c61 + + 要使用 136 kHz 内部 RC 振荡器作为低功耗蓝牙内部时钟源，请配置以下选项： + + **配置路径 1：** + + :ref:`CONFIG_BT_LE_LP_CLK_SRC` = Use system RTC slow clock source (`CONFIG_BT_LE_LP_CLK_SRC_DEFAULT`) + +.. only:: not esp32 + + **配置路径 2：** + + :ref:`CONFIG_RTC_CLK_SRC` = Internal 136 kHz RC oscillator (`CONFIG_RTC_CLK_SRC_INT_RC`) + +.. only:: esp32c2 or esp32c6 or esp32h2 or esp32c5 or esp32c61 + + 对于需要低功耗且没有 32 kHz 外部晶振的场景，可以选择 136 kHz RC 振荡器。然而，该时钟无法满足低功耗蓝牙的 500 PPM 的休眠时钟精度需求。如果对端设备使用 ESP 芯片，低功耗蓝牙功能仍可正常工作；但如果对端设备不是 ESP 芯片，则以下低功耗蓝牙行为将无法支持： + + 1. 作为连接的 Central 方 + 2. 作为 Periodic Advertising 的广播方 + + 如果对端设备也用 136 kHz RC 作为时钟源，需要如下配置: + + **配置路径：** + + - :ref:`CONFIG_BT_LE_LL_PEER_SCA_SET_ENABLE` = y + - :ref:`CONFIG_BT_LE_LL_PEER_SCA` = 3000 + + **注意：** 使用 136 kHz RC 振荡器可能偶发连接断开或连接失败。 + + +如何确认当前低功耗蓝牙使用的时钟源 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +可通过低功耗蓝牙初始化时的日志判断当前时钟源： + +.. list-table:: 低功耗蓝牙初始化日志与时钟源对应关系 + :widths: 50 50 + :header-rows: 1 + + * - 日志内容 + - 时钟源 + * - Using main XTAL as clock source + - 主晶振 (Main XTAL) + * - Using 136 kHz RC as clock source + - 内部 136 kHz RC 振荡器 (Internal 136 kHz RC oscillator) + * - Using external 32.768 kHz crystal as clock source + - 外部 32 kHz 晶振 (External 32 kHz crystal) + * - Using external 32.768 kHz oscillator at 32K_XP pin as clock source + - 外部 32 kHz 振荡器 (32K_XP 引脚) (External 32 kHz oscillator at 32K_XP pin) + + +常见问题 +-------------------------------------- + +1. 低功耗蓝牙 ACL 连接在低功耗模式下建立失败或断开 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +如时钟源选择部分所述，ACL 连接建立失败或断开时，请首先检查当前时钟源是否满足低功耗蓝牙精度要求。 + + +2. 实测 light-sleep 电流高于预期 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +如时钟源选择部分所述，若主晶振为时钟源，light-sleep 模式下主晶振持续供电，电流消耗高于其他时钟源。平均电流可能会因具体应用而异，并取决于低功耗蓝牙的配置以及处于 light-sleep 模式的时间周期。某些应用的平均电流可能会更大，这是因为低功耗蓝牙在其中花费了更高比例的时间进行发射和接收。 + +3. 无法进入 light-sleep 模式 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +启用 Auto light-sleep 后，若设备无法进入 light-sleep，通常是 IDLE 时间不足，未满足自动进入条件。这可能由日志过多或低功耗蓝牙配置导致 IDLE 时间过短（如连续扫描）引起。 diff --git a/docs/zh_CN/api-guides/low-power-mode/low-power-mode-soc.rst b/docs/zh_CN/api-guides/low-power-mode/low-power-mode-soc.rst index 24c36f23d4cc..8bc7eebd7fd7 100644 --- a/docs/zh_CN/api-guides/low-power-mode/low-power-mode-soc.rst +++ b/docs/zh_CN/api-guides/low-power-mode/low-power-mode-soc.rst @@ -271,6 +271,9 @@ Light-sleep 模式配置 - 关闭 CPU (:ref:`CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP`) + .. only:: esp32p4 + + 对于 ESP32P4 芯片, 只有大于 3.0 的芯片版本才支持单独掉电 CPU 电源域。 .. only:: SOC_PM_SUPPORT_TAGMEM_PD diff --git a/docs/zh_CN/api-guides/performance/ram-usage.rst b/docs/zh_CN/api-guides/performance/ram-usage.rst index 2e8295c49c03..e76b57b7ec59 100644 --- a/docs/zh_CN/api-guides/performance/ram-usage.rst +++ b/docs/zh_CN/api-guides/performance/ram-usage.rst @@ -83,7 +83,7 @@ ESP-IDF 包含一系列堆 API，可以在运行时测量空闲堆内存，请 任务运行时确定栈内存大小的方法 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -- 调用 :cpp:func:`uxTaskGetStackHighWaterMark` 会返回任务整个生命周期中空闲栈内存的最小值，从而较好地显示出任务未使用的栈内存量。 +- 调用 :cpp:func:`uxTaskGetStackHighWaterMark` 会返回任务整个生命周期中空闲栈内存的最小值（以字节为单位），从而较好地显示出任务未使用的栈内存量。注意：在 {IDF_TARGET_NAME} 上，该函数返回字节数（而不是标准 FreeRTOS 文档中所述的字数）。 - 从任务本身内部调用 :cpp:func:`uxTaskGetStackHighWaterMark` 是调用该函数最容易的方式：在任务达到其栈内存使用峰值后，调用 ``uxTaskGetStackHighWaterMark(NULL)`` 获取当前任务的高水位标记，换言之，如果有主循环，请多次执行主循环来覆盖各种状态，随后调用 :cpp:func:`uxTaskGetStackHighWaterMark`。 - 通常可以用任务的栈内存总大小减去调用 :cpp:func:`uxTaskGetStackHighWaterMark` 的返回值，计算任务实际使用的栈内存大小，但应留出一定的安全余量，应对运行时栈内存使用量的小幅意外增长。 diff --git a/docs/zh_CN/api-guides/tools/idf-docker-image.rst b/docs/zh_CN/api-guides/tools/idf-docker-image.rst index d771d0253f04..630a0eac6969 100644 --- a/docs/zh_CN/api-guides/tools/idf-docker-image.rst +++ b/docs/zh_CN/api-guides/tools/idf-docker-image.rst @@ -150,6 +150,7 @@ ESP-IDF 库中的 Docker 文件提供了以下构建参数，可用于构建自 - ``IDF_CLONE_SHALLOW``：如果将此参数设置为非空值，则会在执行 ``git clone`` 时使用 ``--depth=1 --shallow-submodules`` 参数。浅克隆的深度可以使用 ``IDF_CLONE_SHALLOW_DEPTH`` 设置。浅克隆可以极大减少下载的数据量及生成的 Docker 镜像大小。然而，如果需要切换到此类“浅层”存储库中的其他分支，必须先执行额外的 ``git fetch origin `` 命令。 - ``IDF_CLONE_SHALLOW_DEPTH``：此参数指定进行浅克隆时要使用的深度值。如未设置，将使用 ``--depth=1``。此参数仅在使用 ``IDF_CLONE_SHALLOW`` 时有效。如果要为分支构建 Docker 镜像，并且该镜像必须包含该分支上的最新标签，则需使用此参数。要确定所需的深度，请在特定的分支运行 ``git describe`` 命令，并注意偏移值。将偏移值加 1 后即可将其用作 ``IDF_CLONE_SHALLOW_DEPTH`` 参数的值。此过程将确保生成的镜像包含分支上的最新标签，且 Docker 镜像内部的 ``git describe`` 命令也会按预期工作。 - ``IDF_INSTALL_TARGETS``：以逗号分隔的 ESP-IDF 目标列表，用于安装工具链，或者使用 ``all`` 安装所有目标的工具链。选择特定目标可以减少下载的数据量和生成的 Docker 镜像的大小。该参数默认值为 ``all``。 +- ``IDF_GITHUB_ASSETS``：如果将此参数设置为非空值，则会从设置的镜像站点下载 ESP-IDF 工具，而不是从 ``github.com`` 下载。这样可以在网络无法访问 ``github.com`` 时使用镜像站点。该参数的默认值为空。 要使用以上参数，请通过 ``--build-arg`` 命令行选项传递。例如，以下命令使用 ESP-IDF v4.4.1 的浅克隆以及仅适用于 ESP32-C3 的工具链构建了 Docker 镜像： diff --git a/docs/zh_CN/api-reference/bluetooth/esp_gap_ble.rst b/docs/zh_CN/api-reference/bluetooth/esp_gap_ble.rst index a215413f16cc..53a0e24718db 100644 --- a/docs/zh_CN/api-reference/bluetooth/esp_gap_ble.rst +++ b/docs/zh_CN/api-reference/bluetooth/esp_gap_ble.rst @@ -6,9 +6,9 @@ GAP API 应用示例 ------------------- -- :example:`bluetooth/bluedroid/ble/gatt_security_client` 演示使用 ESP BLE security API，{IDF_TARGET_NAME} 作为 GATT 客户端时如何建立安全连接并加密与对等设备的通信。 +- :example:`bluetooth/bluedroid/ble/gatt_security_client` 演示使用 ESP 低功耗蓝牙 security API，{IDF_TARGET_NAME} 作为 GATT 客户端时如何建立安全连接并加密与对等设备的通信。 -- :example:`bluetooth/bluedroid/ble/gatt_security_server` 演示使用 ESP BLE security API，{IDF_TARGET_NAME} 作为 GATT 服务器时如何建立安全连接并加密与对等设备的通信。 +- :example:`bluetooth/bluedroid/ble/gatt_security_server` 演示使用 ESP 低功耗蓝牙 security API，{IDF_TARGET_NAME} 作为 GATT 服务器时如何建立安全连接并加密与对等设备的通信。 API 参考 ------------- diff --git a/docs/zh_CN/api-reference/peripherals/lcd/dsi_lcd.rst b/docs/zh_CN/api-reference/peripherals/lcd/dsi_lcd.rst index ace7b536cab5..63118e9ae42a 100644 --- a/docs/zh_CN/api-reference/peripherals/lcd/dsi_lcd.rst +++ b/docs/zh_CN/api-reference/peripherals/lcd/dsi_lcd.rst @@ -11,7 +11,6 @@ MIPI DSI 接口的 LCD esp_lcd_dsi_bus_config_t bus_config = { .bus_id = 0, // 从 0 开始编号，指定要使用的 DSI 主机 .num_data_lanes = 2, // 要使用的数据通道数，不能超过芯片支持的数量 - .phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT, // DPHY 的时钟源 .lane_bit_rate_mbps = EXAMPLE_MIPI_DSI_LANE_BITRATE_MBPS, // 数据通道的比特率 (Mbps) }; ESP_ERROR_CHECK(esp_lcd_new_dsi_bus(&bus_config, &mipi_dsi_bus)); diff --git a/docs/zh_CN/api-reference/peripherals/rmt.rst b/docs/zh_CN/api-reference/peripherals/rmt.rst index 7989aeda8657..0b59cd51b9e7 100644 --- a/docs/zh_CN/api-reference/peripherals/rmt.rst +++ b/docs/zh_CN/api-reference/peripherals/rmt.rst @@ -257,7 +257,7 @@ RMT 是一种特殊的通信外设，无法像 SPI 和 I2C 那样发送原始字 .. note:: - 如果将 :cpp:member:`rmt_transmit_config_t::loop_count` 设置为非零值，即启用循环功能，则传输的大小将受到限制。编码的 RMT 符号不应超过 RMT 硬件内存块容量，否则会出现类似 ``encoding artifacts can't exceed hw memory block for loop transmission`` 的报错信息。如需通过循环启动大型事务，请尝试以下任一方法： + 如果将 :cpp:member:`rmt_transmit_config_t::loop_count` 设置为非零值，即启用循环功能，则传输的大小将受到限制。编码器返回的符号总量不能超过 :c:macro:`SOC_RMT_MEM_WORDS_PER_CHANNEL`，否则会出现类似 ``encoding artifacts can't exceed hw memory block for loop transmission`` 的报错信息。如需通过循环启动大型事务，请尝试以下任一方法： - 增加 :cpp:member:`rmt_tx_channel_config_t::mem_block_symbols`。若此时启用了 DMA 后端，该方法将失效。 - 自定义编码器，并在编码函数中构造一个无限循环，详情请参阅 :ref:`rmt-rmt-encoder`。 diff --git a/docs/zh_CN/api-reference/peripherals/temp_sensor.rst b/docs/zh_CN/api-reference/peripherals/temp_sensor.rst index a53aace2fbd3..912e0c48d159 100644 --- a/docs/zh_CN/api-reference/peripherals/temp_sensor.rst +++ b/docs/zh_CN/api-reference/peripherals/temp_sensor.rst @@ -8,29 +8,9 @@ {IDF_TARGET_NAME} 内置传感器，用于测量芯片内部的温度。该温度传感器模组包含一个 8 位 Sigma-Delta 模拟-数字转换器 (ADC) 和一个数字-模拟转换器 (DAC)，可以补偿测量结果，减少温度测量的误差。 -由于硬件限制，温度传感器存在预定义的测量范围及其对应误差，详见下表： - -.. list-table:: - :header-rows: 1 - :widths: 50 50 - :align: center - - * - 预定义测量范围 (°C) - - 测量误差 (°C) - * - 50 ~ 125 - - < 3 - * - 20 ~ 100 - - < 2 - * - -10 ~ 80 - - < 1 - * - -30 ~ 50 - - < 2 - * - -40 ~ 20 - - < 3 - .. note:: - 温度传感器主要用于测量芯片内部的温度变化。芯片内部温度通常高于环境温度，并且受到微控制器的时钟频率或 I/O 负载、外部散热环境等因素影响。 + 温度传感器主要用于测量芯片内部的温度变化。温度值可用作衡量温度变化趋势，但无法提供精确的温度数值，因此不建议用作精准测量温度。 功能概述 ------------------- diff --git a/docs/zh_CN/api-reference/peripherals/uart.rst b/docs/zh_CN/api-reference/peripherals/uart.rst index 90da2e4811a6..b3eb726c8c72 100644 --- a/docs/zh_CN/api-reference/peripherals/uart.rst +++ b/docs/zh_CN/api-reference/peripherals/uart.rst @@ -18,6 +18,15 @@ 此外，{IDF_TARGET_NAME} 芯片还有一个满足低功耗需求的 LP UART 控制器。LP UART 是原 UART 的功能剪裁版本。它只支持基础 UART 功能，不支持 IrDA 或 RS485 协议，并且只有一块较小的 RAM 存储空间。想要全面了解的 UART 及 LP UART 功能区别，请参考 **{IDF_TARGET_NAME} 技术参考手册** > UART 控制器 (UART) > 主要特性 [`PDF <{IDF_TARGET_TRM_EN_URL}#uart>`__]。 +.. only:: SOC_UHCI_SUPPORTED + + .. toctree:: + :hidden: + + uhci + + {IDF_TARGET_NAME} 芯片也支持 UART DMA 模式, 请参考 :doc:`uhci` 以获得更多信息. + 功能概述 ------------------- @@ -230,7 +239,7 @@ UART 控制器支持多种通信模式，使用函数 :cpp:func:`uart_set_mode` 使用中断 ^^^^^^^^^^^^^^^^^ -根据特定的 UART 状态或检测到的错误，可以生成许多不同的中断。**{IDF_TARGET_NAME} 技术参考手册** > UART 控制器 (UART) > UART 中断 和 UHCI 中断 [`PDF <{IDF_TARGET_TRM_EN_URL}#uart>`__] 中提供了可用中断的完整列表。调用 :cpp:func:`uart_enable_intr_mask` 或 :cpp:func:`uart_disable_intr_mask` 能够分别启用或禁用特定中断。 +根据特定的 UART 状态或检测到的错误，可以生成许多不同的中断。**{IDF_TARGET_NAME} 技术参考手册** > UART 控制器 (UART) > UART 中断 [`PDF <{IDF_TARGET_TRM_EN_URL}#uart>`__] 中提供了可用中断的完整列表。调用 :cpp:func:`uart_enable_intr_mask` 或 :cpp:func:`uart_disable_intr_mask` 能够分别启用或禁用特定中断。 UART 驱动提供了一种便利的方法来处理特定的中断，即将中断包装成相应的事件。这些事件定义在 :cpp:type:`uart_event_type_t` 中，FreeRTOS 队列功能可将这些事件报告给用户应用程序。 diff --git a/docs/zh_CN/api-reference/peripherals/uhci.rst b/docs/zh_CN/api-reference/peripherals/uhci.rst new file mode 100644 index 000000000000..6e53e3a75e92 --- /dev/null +++ b/docs/zh_CN/api-reference/peripherals/uhci.rst @@ -0,0 +1,299 @@ +UART DMA (UHCI) +=============== + +:link_to_translation:`en:[English]` + +本文档描述了 ESP-IDF 中 UART DMA（UHCI）驱动的功能。目录如下： + +.. contents:: + :local: + :depth: 2 + +概述 +------------ + +本文档将介绍如何将 UART 与 DMA 结合使用，以在高波特率下传输或接收大数据量。 {IDF_TARGET_NAME} 的 {IDF_TARGET_SOC_UART_HP_NUM} 个 UART 控制器通过主机控制接口（HCI）共享一组 DMA TX/RX 通道。在以下文档中，UHCI 是指控制 UART DMA 的实体。 + +.. note:: + + UART DMA 与 BT 共享 HCI 硬件，因此请勿同时使用 BT HCI 和 UART DMA，哪怕它们使用的是不同的 UART 端口。 + +快速入门 +----------- + +本节将快速指导您如何使用 UHCI 驱动。通过一个简单的传输和接收示例，展示了如何创建和启动 UHCI、启动传输和接收事务以及注册事件回调函数。一般使用流程如下： + +创建并启用 UHCI 控制器 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +UHCI 控制器需要通过 :cpp:type:`uhci_controller_config_t` 进行配置。 + +如果在 :cpp:type:`uhci_controller_config_t` 完成了配置，用户可以调用 :cpp:func:`uhci_new_controller` 来分配并初始化一个 UHCI 控制器。此函数如果运行正常，将返回一个 UHCI 控制器句柄。此外，UHCI 必须与已初始化的 UART 驱动程序一起工作。以下代码可供参考。 + +.. code:: c + + #define EX_UART_NUM 1 // 定义 UART 端口 + + // 关于 UART 端口配置项，请参考 UART 编程指南 + // 请注意波特率有可能受限于串口芯片 + uart_config_t uart_config = { + .baud_rate = 1 * 1000 * 1000, + .data_bits = UART_DATA_8_BITS, + .parity = UART_PARITY_DISABLE, + .stop_bits = UART_STOP_BITS_1, + .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, + .source_clk = UART_SCLK_DEFAULT, + }; + + // UART 参数配置 + ESP_ERROR_CHECK(uart_param_config(EX_UART_NUM, &uart_config)); + ESP_ERROR_CHECK(uart_set_pin(EX_UART_NUM, UART_TX_IO, UART_RX_IO, -1, -1)); + + uhci_controller_config_t uhci_cfg = { + .uart_port = EX_UART_NUM, // 将指定 UART 端口连接到 UHCI 硬件 + .tx_trans_queue_depth = 30, // 发送队列的队列深度 + .max_receive_internal_mem = 10 * 1024, // 内部接收内存大小，更多信息请参考 API 注释。 + .max_transmit_size = 10 * 1024, // 单次传输的最大传输量，单位是字节 + .dma_burst_size = 32, // 突发传输大小 + .rx_eof_flags.idle_eof = 1, // 结束帧的条件，用户可以选择 `idle_eof`, `rx_brk_eof` 和 `length_eof`, 关于更多信息请参考 API 注释. + }; + + uhci_controller_handle_t uhci_ctrl; + + ESP_ERROR_CHECK(uhci_new_controller(&uhci_cfg, &uhci_ctrl)); + +注册事件回调 +^^^^^^^^^^^^^^^^^^^^^^^^ + +当 UHCI 控制器上发生事件（例如传输或接收完成）时，CPU通过中断被通知此事件。如果在某些事件发生时需要调用特定函数，可以通过调用 :cpp:func:`uhci_register_event_callbacks` 为 TX 和 RX 方向分别注册回调。 由于注册的回调函数在中断上下文中调用，用户应确保回调函数不会阻塞，例如仅调用带有 `FromISR` 后缀的 FreeRTOS API。回调函数具有布尔返回值，指示回调是否解除了更高优先级任务的阻塞状态。 + +UHCI 事件回调在 :cpp:type:`uhci_event_callbacks_t` 中列出： + +- :cpp:member:`uhci_event_callbacks_t::on_tx_trans_done` 为“传输完成”事件设置回调函数。函数原型声明为 :cpp:type:`uhci_tx_done_callback_t`。 + +- :cpp:member:`uhci_event_callbacks_t::on_rx_trans_event` 为“接收事件”设置回调函数。函数原型声明为 :cpp:type:`uhci_rx_event_callback_t`。 + +.. note:: + + “rx-trans-event” 事件并不等同于“接收完成”。在一次接收事务中，该回调函数也可能在“部分接收”时被多次调用，此时可以通过 :cpp:member:`uhci_rx_event_data_t::flags::totally_received` 标志区分“部分接收”和“接收完成”。 + +用户还可以通过 :cpp:func:`uhci_register_event_callbacks` 中的参数 `user_data` 保存自己的上下文。用户数据会直接传递给每个回调函数。 + +在回调函数中，用户可以获取由驱动填充的事件特定数据，该数据保存在 ``edata`` 中。注意， ``edata`` 指针仅在回调期间有效，请勿尝试保存该指针并在回调函数外部使用。 + +TX 事件数据在 :cpp:type:`uhci_tx_done_event_data_t` 中定义： + +- :cpp:member:`uhci_tx_done_event_data_t::buffer` 表示 ``buffer`` 已经发送完成。 + +RX 事件数据在 :cpp:type:`uhci_rx_event_data_t` 中定义： + +- :cpp:member:`uhci_rx_event_data_t::data` 指向接收到的数据。数据保存在 :cpp:func:`uhci_receive` 函数的 ``buffer`` 参数中。用户在回调返回之前不应释放此接收缓冲区。 +- :cpp:member:`uhci_rx_event_data_t::recv_size` 表示接收到的数据大小。此值不会大于 :cpp:func:`uhci_receive` 函数的 ``buffer_size`` 参数。 +- :cpp:member:`uhci_rx_event_data_t::flags::totally_received` 指示当前接收缓冲区是否是事务中的最后一个。 + +启动 UHCI 传输 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +:cpp:func:`uhci_transmit` 是一个非阻塞函数，这意味着在调用后会立即返回。您可以通过 :cpp:member:`uhci_event_callbacks_t::on_tx_trans_done` 相关回调指示事务完成。我们还提供了一个函数 :cpp:func:`uhci_wait_all_tx_transaction_done` 来阻塞线程，等待所有事务完成。 + +以下代码显示了如何通过 UHCI 接收数据： + +.. code:: c + + uint8_t data_wr[DATA_LENGTH]; + for (int i = 0; i < DATA_LENGTH; i++) { + data_wr[i] = i; + } + ESP_ERROR_CHECK(uhci_transmit(uhci_ctrl, data_wr, DATA_LENGTH)); + // 等待所有传输完成 + ESP_ERROR_CHECK(uhci_wait_all_tx_transaction_done(uhci_ctrl, -1)); + +启动 UHCI 接收 +^^^^^^^^^^^^^^^^^^^^^^^^^ + +:cpp:func:`uhci_receive` 是一个非阻塞函数，这意味着该函数在调用后会立即返回。用户可以通过 :cpp:member:`uhci_rx_event_data_t::recv_size` 获取相关的回调，以指示接收事件并判断事务是否完成。 + +以下代码展示了如何通过 UHCI 传输数据： + +.. code:: c + + // 全局变量：队列的句柄 + QueueHandle_t uhci_queue; + + IRAM_ATTR static bool s_uhci_rx_event_cbs(uhci_controller_handle_t uhci_ctrl, const uhci_rx_event_data_t *edata, void *user_ctx) + { + // 参数 `user_ctx` 是由函数 `uhci_register_event_callbacks` 的第三个参数传递的。 + uhci_context_t *ctx = (uhci_context_t *)user_ctx; + BaseType_t xTaskWoken = 0; + uhci_event_t evt = 0; + if (edata->flags.totally_received) { + evt = UHCI_EVT_EOF; + ctx->receive_size += edata->recv_size; + memcpy(ctx->p_receive_data, edata->data, edata->recv_size); + } else { + evt = UHCI_EVT_PARTIAL_DATA; + ctx->receive_size += edata->recv_size; + memcpy(ctx->p_receive_data, edata->data, edata->recv_size); + ctx->p_receive_data += edata->recv_size; + } + + xQueueSendFromISR(uhci_queue, &evt, &xTaskWoken); + return xTaskWoken; + } + + // 在任务中 + uhci_event_callbacks_t uhci_cbs = { + .on_rx_trans_event = s_uhci_rx_event_cbs, + }; + + // 注册回调，并开始启动回收 + ESP_ERROR_CHECK(uhci_register_event_callbacks(uhci_ctrl, &uhci_cbs, ctx)); + ESP_ERROR_CHECK(uhci_receive(uhci_ctrl, pdata, 100)); + + uhci_event_t evt; + while (1) { + // 一个在任务中的队列用来接收 UHCI 抛出的事件 + if (xQueueReceive(uhci_queue, &evt, portMAX_DELAY) == pdTRUE) { + if (evt == UHCI_EVT_EOF) { + printf("Received size: %d\n", ctx->receive_size); + break; + } + } + } + +在 API :cpp:func:`uhci_receive` 接口中，参数 ``read_buffer`` 是用户必须提供的缓冲区，参数 ``buffer_size`` 表示用户提供的缓冲区大小。在 UHCI 控制器的配置结构中，参数 :cpp:member:`uhci_controller_config_t::max_receive_internal_mem` 指定了内部 DMA 工作空间的期望大小。软件将根据此工作空间大小分配一定数量的 DMA 节点，这些节点形成一个循环链表。 + +当一个节点被填满，但接收尚未完成时，将触发 :cpp:member:`uhci_event_callbacks_t::on_rx_trans_event` 事件，且 :cpp:member:`uhci_rx_event_data_t::flags::totally_received` 的值为 0。 当所有数据接收完成时，该事件将再次被触发，并且 :cpp:member:`uhci_rx_event_data_t::flags::totally_received` 的值为 1。 + +此机制允许用户使用相对较小的缓冲区实现连续且快速的接收，而无需分配与接收总数据量相等大小的缓冲区。 + +.. note:: + + 在接收完成之前，:cpp:func:`uhci_receive` 的参数 ``read_buffer`` 不可被释放。 + +卸载 UHCI 控制器 +^^^^^^^^^^^^^^^^^^^^^^^^^ + +如果不再需要已安装的 UHCI 控制器，建议通过调用 :cpp:func:`uhci_del_controller` 回收资源，以释放底层硬件。 + +.. code:: c + + ESP_ERROR_CHECK(uhci_del_controller(uhci_ctrl)); + +高级功能 +----------------- + +在理解了基本用法后，我们可以进一步探索 UHCI 驱动的高级功能。 + +关于低功耗 +^^^^^^^^^^^^^^^^ + +当启用电源管理时（即开启 :ref:`CONFIG_PM_ENABLE`），系统在进入睡眠前可能会调整或禁用时钟源。因此，UHCI 内部的 FIFO 可能无法正常工作。 + +通过创建电源管理锁，驱动程序可以避免上述问题. 驱动会根据不同的时钟源设置锁的类型. 驱动程序将在 :cpp:func:`uhci_receive` 或 :cpp:func:`uhci_transmit` 中获取锁，并在事务完成中断中释放锁。这意味着，这两个函数之间的任何 UHCI 事务都能保证正常稳定运行。 + +缓存安全 +^^^^^^^^^^ + +默认情况下，当由于写入或擦除主 Flash 导致缓存被禁用时，UHCI 所依赖的中断会被延迟. 因此，事务完成中断可能无法及时处理，这在实时应用中是不可接受的。更糟糕的是，当 UHCI 事务依赖 **乒乓** 中断来连续编码或复制 UHCI 缓冲区时，延迟的中断可能会导致不可预测的结果。 + +通过启用 Kconfig 选项 :ref:`CONFIG_UHCI_ISR_CACHE_SAFE`，可实现以下功能： + +1. 即使缓存被禁用，中断也能被服务。 +2. 将 ISR 使用的所有函数放入 IRAM [1]_ +3. 将驱动对象放入 DRAM，防止其意外映射到 PSRAM。 + +此选项允许中断处理程序在缓存禁用时运行，但代价是增加了 IRAM 的消耗。 + +资源消耗 +^^^^^^^^^^^^^^^^^^^^ + +使用 :doc:`/api-guides/tools/idf-size` 工具检查 UHCI 驱动的代码和数据消耗。以下是基于 ESP32-C3 的测试结果（仅供参考，不同芯片型号可能会有所不同）: + +**请注意以下数据仅供参考，不同芯片型号可能会有所不同.** + +启用 :ref:`CONFIG_UHCI_ISR_CACHE_SAFE` 时的资源消耗： + +.. list-table:: 资源消耗 + :widths: 10 10 10 10 10 10 10 10 10 + :header-rows: 1 + + * - Component Layer + - Total Size + - DIRAM + - .bss + - .data + - .text + - Flash Code + - Flash Data + - .rodata + * - UHCI + - 5733 + - 680 + - 8 + - 34 + - 638 + - 4878 + - 175 + - 175 + +禁用 :ref:`CONFIG_UHCI_ISR_CACHE_SAFE` 时的资源消耗： + +.. list-table:: 资源消耗 + :widths: 10 10 10 10 10 10 10 10 10 10 + :header-rows: 1 + + * - Component Layer + - Total Size + - DIRAM + - .bss + - .data + - .text + - Flash Code + - .text + - Flash Data + - .rodata + * - UHCI + - 5479 + - 42 + - 8 + - 34 + - 0 + - 5262 + - 5262 + - 175 + - 175 + +关于性能 +^^^^^^^^ + +为了提升中断处理的实时响应能力， UHCI 驱动提供了 :ref:`CONFIG_UHCI_ISR_HANDLER_IN_IRAM` 选项。启用该选项后，中断处理程序将被放置在内部 RAM 中运行，从而减少了从 Flash 加载指令时可能出现的缓存丢失带来的延迟。 + +.. note:: + + 但是，中断处理程序调用的用户回调函数和用户上下文数据仍然可能位于 Flash 中，缓存缺失的问题还是会存在，这需要用户自己将回调函数和数据放入内部 RAM 中，比如使用 :c:macro:`IRAM_ATTR` 和 :c:macro:`DRAM_ATTR`。 + +线程安全 +^^^^^^^^^^^^^ + +驱动程序保证工厂函数 :cpp:func:`uhci_new_controller`、:cpp:func:`uhci_register_event_callbacks` 和 :cpp:func:`uhci_del_controller` 的线程安全。这意味着用户可以从不同的 RTOS 任务中调用它们，而无需额外的锁保护。 + +其他 Kconfig 选项 +^^^^^^^^^^^^^^^^^^^^^ + +- :ref:`CONFIG_UHCI_ENABLE_DEBUG_LOG` 选项允许强制启用 UHCI 驱动的所有调试日志，无论全局日志级别设置如何。启用此选项可以帮助开发人员在调试过程中获取更详细的日志信息，从而更容易定位和解决问题，但会增加固件二进制文件的大小。 + +应用示例 +-------------------- + +- :example:`peripherals/uart/uart_dma_ota` 演示了如何使用 UART DMA 以 1Mbps 波特率快速 OTA 更新芯片固件。 + +API 参考 +------------- + +.. include-build-file:: inc/uhci.inc +.. include-build-file:: inc/components/esp_driver_uart/include/driver/uhci_types.inc +.. include-build-file:: inc/components/hal/include/hal/uhci_types.inc + +.. [1] + 回调函数（例如 :cpp:member:`uhci_event_callbacks_t::on_tx_trans_done` 、:cpp:member:`uhci_event_callbacks_t::on_rx_trans_event`）及其调用的函数也应驻留在 IRAM 中，用户需要自行注意这一点。 diff --git a/examples/bluetooth/.build-test-rules.yml b/examples/bluetooth/.build-test-rules.yml index f30e7b52066d..036df2f84307 100644 --- a/examples/bluetooth/.build-test-rules.yml +++ b/examples/bluetooth/.build-test-rules.yml @@ -188,6 +188,25 @@ examples/bluetooth/nimble/ble_ancs: depends_filepatterns: - examples/bluetooth/nimble/common/**/* +examples/bluetooth/nimble/ble_chan_sound_initiator: + <<: *bt_default_depends + enable: + - if: SOC_BLE_SUPPORTED == 1 and IDF_TARGET == "esp32c6" + temporary: true + reason: Channel Sounding example only supported on ESP32-C6 + depends_filepatterns: + - examples/bluetooth/nimble/ble_chan_sound_initiator/**/* + - examples/bluetooth/nimble/common/**/* + +examples/bluetooth/nimble/ble_chan_sound_reflector: + <<: *bt_default_depends + enable: + - if: SOC_BLE_SUPPORTED == 1 and IDF_TARGET == "esp32c6" + temporary: true + reason: Channel Sounding example only supported on ESP32-C6 + depends_filepatterns: + - examples/bluetooth/nimble/ble_chan_sound_reflector/**/* + - examples/bluetooth/nimble/common/**/* examples/bluetooth/nimble/ble_cte: <<: *bt_default_depends enable: @@ -225,12 +244,12 @@ examples/bluetooth/nimble/ble_multi_conn: examples/bluetooth/nimble/ble_pawr_adv: <<: *bt_default_depends enable: - - if: IDF_TARGET == "esp32c6" + - if: SOC_ESP_NIMBLE_CONTROLLER == 1 and IDF_TARGET != "esp32c2" examples/bluetooth/nimble/ble_pawr_adv_conn: <<: *bt_default_depends enable: - - if: IDF_TARGET == "esp32c6" + - if: SOC_ESP_NIMBLE_CONTROLLER == 1 and IDF_TARGET != "esp32c2" examples/bluetooth/nimble/ble_periodic_adv: <<: *bt_default_depends diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/main.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/main.c index 2903a67c02fc..d4c871e96492 100644 --- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/main.c +++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/main.c @@ -78,12 +78,14 @@ void app_main(void) { return; } +#if CONFIG_BT_NIMBLE_GAP_SERVICE /* GAP service initialization */ rc = gap_init(); if (rc != 0) { ESP_LOGE(TAG, "failed to initialize GAP service, error code: %d", rc); return; } +#endif /* NimBLE host configuration initialization */ nimble_host_config_init(); diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/main.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/main.c index b3fa8a9012e5..6fc6c414a015 100644 --- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/main.c +++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/main.c @@ -82,12 +82,14 @@ void app_main(void) { return; } +#if CONFIG_BT_NIMBLE_GAP_SERVICE /* GAP service initialization */ rc = gap_init(); if (rc != 0) { ESP_LOGE(TAG, "failed to initialize GAP service, error code: %d", rc); return; } +#endif /* NimBLE host configuration initialization */ nimble_host_config_init(); diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c index 8788b66f267e..d2689f9230fa 100644 --- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c +++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c @@ -251,6 +251,7 @@ int gap_init(void) { /* Local variables */ int rc = 0; + /* Initialize GAP service */ ble_svc_gap_init(); diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/main.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/main.c index aa804b209951..5283e2e7856e 100644 --- a/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/main.c +++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/main.c @@ -109,12 +109,14 @@ void app_main(void) { return; } +#if CONFIG_BT_NIMBLE_GAP_SERVICE /* GAP service initialization */ rc = gap_init(); if (rc != 0) { ESP_LOGE(TAG, "failed to initialize GAP service, error code: %d", rc); return; } +#endif /* GATT server initialization */ rc = gatt_svc_init(); diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/main.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/main.c index 26541056a6c7..dfe997eb080c 100644 --- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/main.c +++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/main.c @@ -118,12 +118,14 @@ void app_main(void) { return; } +#if CONFIG_BT_NIMBLE_GAP_SERVICE /* GAP service initialization */ rc = gap_init(); if (rc != 0) { ESP_LOGE(TAG, "failed to initialize GAP service, error code: %d", rc); return; } +#endif /* GATT server initialization */ rc = gatt_svc_init(); diff --git a/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/main/console_uart.c b/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/main/console_uart.c index 4bd1b2a0e195..13a3ee4d87cb 100644 --- a/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/main/console_uart.c +++ b/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/main/console_uart.c @@ -119,7 +119,7 @@ esp_err_t console_uart_init(void) uart_set_pin(CONSOLE_UART_NUM, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); uart_driver_install(CONSOLE_UART_NUM, 1024, 1024, 8, &uart_queue, 0); - xTaskCreate(console_uart_task, "uTask", 2048, NULL, 8, NULL); + xTaskCreate(console_uart_task, "uTask", 4 * 1024, NULL, 8, NULL); return ESP_OK; } diff --git a/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_acceptor/main/spp_task.c b/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_acceptor/main/spp_task.c index 275df04fda81..4bb4f2347821 100644 --- a/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_acceptor/main/spp_task.c +++ b/examples/bluetooth/bluedroid/classic_bt/bt_spp_vfs_acceptor/main/spp_task.c @@ -93,7 +93,7 @@ static void spp_task_task_handler(void *arg) void spp_task_task_start_up(void) { spp_task_task_queue = xQueueCreate(10, sizeof(spp_task_msg_t)); - xTaskCreate(spp_task_task_handler, "SPPAppT", 2048, NULL, 10, &spp_task_task_handle); + xTaskCreate(spp_task_task_handler, "SPPAppT", 4 * 1024, NULL, 10, &spp_task_task_handle); return; } diff --git a/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_hf.c b/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_hf.c index 5267bce64457..c60bde9997cf 100644 --- a/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_hf.c +++ b/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_hf.c @@ -259,7 +259,7 @@ static void bt_app_send_data_task(void *arg) void bt_app_send_data(void) { s_send_data_Semaphore = xSemaphoreCreateBinary(); - xTaskCreate(bt_app_send_data_task, "BtAppSendDataTask", 2048, NULL, configMAX_PRIORITIES - 3, &s_bt_app_send_data_task_handler); + xTaskCreate(bt_app_send_data_task, "BtAppSendDataTask", 4 * 1024, NULL, configMAX_PRIORITIES - 3, &s_bt_app_send_data_task_handler); s_m_rb = xRingbufferCreate(ESP_HFP_RINGBUF_SIZE, RINGBUF_TYPE_BYTEBUF); const esp_timer_create_args_t c_periodic_timer_args = { .callback = &bt_app_send_data_timer_cb, diff --git a/examples/bluetooth/bluedroid/classic_bt/hfp_hf/main/bt_app_core.c b/examples/bluetooth/bluedroid/classic_bt/hfp_hf/main/bt_app_core.c index c8762d8313d7..3d0d8d11c6ee 100644 --- a/examples/bluetooth/bluedroid/classic_bt/hfp_hf/main/bt_app_core.c +++ b/examples/bluetooth/bluedroid/classic_bt/hfp_hf/main/bt_app_core.c @@ -96,7 +96,7 @@ static void bt_app_task_handler(void *arg) void bt_app_task_start_up(void) { bt_app_task_queue = xQueueCreate(10, sizeof(bt_app_msg_t)); - xTaskCreate(bt_app_task_handler, "BtAppT", 2048, NULL, configMAX_PRIORITIES - 3, &bt_app_task_handle); + xTaskCreate(bt_app_task_handler, "BtAppT", 4 * 1024, NULL, configMAX_PRIORITIES - 3, &bt_app_task_handle); return; } diff --git a/examples/bluetooth/nimble/ble_chan_sound_initiator/CMakeLists.txt b/examples/bluetooth/nimble/ble_chan_sound_initiator/CMakeLists.txt new file mode 100644 index 000000000000..8f3dc69e26c8 --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_initiator/CMakeLists.txt @@ -0,0 +1,8 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +# "Trim" the build. Include the minimal set of components, main, and anything it depends on. +idf_build_set_property(MINIMAL_BUILD ON) +project(ble_chan_sound_initiator) diff --git a/examples/bluetooth/nimble/ble_chan_sound_initiator/README.md b/examples/bluetooth/nimble/ble_chan_sound_initiator/README.md new file mode 100644 index 000000000000..0b8c8757e623 --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_initiator/README.md @@ -0,0 +1,70 @@ +| Supported Targets | ESP32-C6 | +| ----------------- | -------- | + +# BLE Channel sounding example +(See the README.md file in the upper-level 'examples' directory for more information about examples.) +* This example demonstrates the capability of the CS procedure to be executed on the ESP host + external controller. +* It is important to note that the current example does not provide support for distance calculation, and it is currently under development. + +## Example output + +I (372) hal_uart: set baud_rate:115200. + +I (382) NimBLE_RAS_INITIATOR: BLE Host Task Started +I (382) main_task: Returned from app_main() + +I (432) NimBLE: GAP procedure initiated: extended discovery; + +I (157332) NimBLE: GAP procedure initiated: extended connect; +I (157552) NimBLE: Connection established +I (157562) NimBLE: Connection secured +I (162222) NimBLE: encryption change event; status=0 + +I (162372) NimBLE: CS capabilities exchanged +I (162372) NimBLE: Set default CS settings +I (162392) NimBLE: create CS config +I (162392) NimBLE: Setup phase completed + +## Note: +* This example currently requires an external Bluetooth controller supporting BLE Channel sounding functionality,as the ESP chips listed above do not have native controller support for BLE channel sounding feature and is under development phase + +* To install the dependency packages needed, please refer to the top level [README file](../../../README.md#running-test-python-script-pytest). + +## How to Use Example + +Before project configuration and build, be sure to set the correct chip target using: + +```bash +idf.py set-target +``` + +### Hardware Required + +* A development board with ESP32/ESP32-C2/ESP32-C3/ESP32-S3/ESP32-C6 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A USB cable for Power supply and programming + +See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. + +### Configure the Project + +Open the project configuration menu: + +```bash +idf.py menuconfig +``` + +In the `Example Configuration` menu: + +* Change the `Peer Address` option if needed. + +### Build and Flash + +Run `idf.py -p PORT flash monitor` to build, flash and monitor the project. + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the [Getting Started Guide](https://idf.espressif.com/) for full steps to configure and use ESP-IDF to build projects. + +## Troubleshooting + +For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. diff --git a/examples/bluetooth/nimble/ble_chan_sound_initiator/main/CMakeLists.txt b/examples/bluetooth/nimble/ble_chan_sound_initiator/main/CMakeLists.txt new file mode 100644 index 000000000000..106e25cd73b0 --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_initiator/main/CMakeLists.txt @@ -0,0 +1,4 @@ +set(srcs "main.c") + +idf_component_register(SRCS "gatt_svr.c" "${srcs}" + INCLUDE_DIRS ".") diff --git a/examples/bluetooth/nimble/ble_chan_sound_initiator/main/Kconfig.projbuild b/examples/bluetooth/nimble/ble_chan_sound_initiator/main/Kconfig.projbuild new file mode 100644 index 000000000000..0de1a5a66fa4 --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_initiator/main/Kconfig.projbuild @@ -0,0 +1,14 @@ +menu "Example Configuration" + + + config EXAMPLE_EXTENDED_ADV + bool + depends on SOC_BLE_50_SUPPORTED && BT_NIMBLE_50_FEATURE_SUPPORT + default y + select BT_NIMBLE_EXT_ADV + prompt "Enable Extended Adv" + help + Use this option to enable extended advertising in the example. + If this option is disabled, ensure config BT_NIMBLE_EXT_ADV is + also disabled from Nimble stack menuconfig +endmenu diff --git a/examples/bluetooth/nimble/ble_chan_sound_initiator/main/ble_chan_initiator.h b/examples/bluetooth/nimble/ble_chan_sound_initiator/main/ble_chan_initiator.h new file mode 100644 index 000000000000..4997060d65c1 --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_initiator/main/ble_chan_initiator.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD +* SPDX-License-Identifier: Unlicense OR CC0-1.0 +*/ + +#ifndef H_BLE_CHAN_INITIATOR_ +#define H_BLE_CHAN_INITIATOR_ + +#include "modlog/modlog.h" +#include "esp_central.h" +#ifdef __cplusplus +extern "C" { +#endif + +struct ble_hs_adv_fields; +struct ble_gap_conn_desc; +struct ble_hs_cfg; +union ble_store_value; +union ble_store_key; + + +#define BLE_HCI_LE_CS_SUBEVENT_DONE_STATUS_COMPLETE 0x0 +#define BLE_HCI_LE_CS_SUBEVENT_DONE_STATUS_PARTIAL 0x1 +#define BLE_HCI_LE_CS_SUBEVENT_DONE_STATUS_ABORTED 0xF + +#define LOCAL_PROCEDURE_MEM 1024 // Replace with an appropriate constant value +struct ble_hs_cfg; +struct ble_gatt_register_ctxt; + +/** GATT server. */ + +#define BLE_UUID_RANGING_SERVICE_VAL (0x185B) + +/** @brief UUID of the RAS Features Characteristic. **/ +#define BLE_UUID_RAS_FEATURES_VAL (0x2C14) + +/** @brief UUID of the Real-time Ranging Data Characteristic. **/ +#define BLE_UUID_RAS_REALTIME_RD_VAL (0x2C15) + +/** @brief UUID of the On-demand Ranging Data Characteristic. **/ +#define BLE_UUID_RAS_ONDEMAND_RD_VAL (0x2C16) + +/** @brief UUID of the RAS Control Point Characteristic. **/ +#define BLE_UUID_RAS_CP_VAL (0x2C17) + +/** @brief UUID of the Ranging Data Ready Characteristic. **/ +#define BLE_UUID_RAS_RD_READY_VAL (0x2C18) + +/** @brief UUID of the Ranging Data Overwritten Characteristic. **/ +#define BLE_UUID_RAS_RD_OVERWRITTEN_VAL (0x2C19) + +void gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg); +int gatt_svr_init(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/bluetooth/nimble/ble_chan_sound_initiator/main/gatt_svr.c b/examples/bluetooth/nimble/ble_chan_sound_initiator/main/gatt_svr.c new file mode 100644 index 000000000000..03636644900d --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_initiator/main/gatt_svr.c @@ -0,0 +1,33 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "services/gap/ble_svc_gap.h" +#include "services/gatt/ble_svc_gatt.h" +#include "services/ans/ble_svc_ans.h" +#include "services/ras/ble_svc_ras.h" + +int +gatt_svr_init(void) +{ + ble_svc_gap_init(); + ble_svc_gatt_init(); + ble_svc_ras_init(); + + return 0; +} diff --git a/examples/bluetooth/nimble/ble_chan_sound_initiator/main/idf_component.yml b/examples/bluetooth/nimble/ble_chan_sound_initiator/main/idf_component.yml new file mode 100644 index 000000000000..db8886afea48 --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_initiator/main/idf_component.yml @@ -0,0 +1,3 @@ +dependencies: + nimble_central_utils: + path: ${IDF_PATH}/examples/bluetooth/nimble/common/nimble_central_utils diff --git a/examples/bluetooth/nimble/ble_chan_sound_initiator/main/main.c b/examples/bluetooth/nimble/ble_chan_sound_initiator/main/main.c new file mode 100644 index 000000000000..736791372ce6 --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_initiator/main/main.c @@ -0,0 +1,721 @@ +/* + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD +* SPDX-License-Identifier: Unlicense OR CC0-1.0 +*/ + +#include "esp_log.h" +#include "nvs_flash.h" +/* BLE */ +#include "nimble/nimble_port.h" +#include "nimble/nimble_port_freertos.h" +#include "host/ble_hs.h" +#include "host/ble_cs.h" +#include "host/util/util.h" +#include "console/console.h" +#include "services/gap/ble_svc_gap.h" +#include "services/hid/ble_svc_hid.h" +#include "services/ras/ble_svc_ras.h" +#include "ble_chan_initiator.h" + +#define REAL_TIME_RANGING_DATA_BIT (1<<0) + +#define BLE_UUID_RANGING_SERVICE_VAL (0x185B) +/** @brief UUID of the RAS Features Characteristic. **/ +#define BLE_UUID_RAS_FEATURES_VAL (0x2C14) + +/** @brief UUID of the Real-time Ranging Data Characteristic. **/ +#define BLE_UUID_RAS_REALTIME_RD_VAL (0x2C15) + +/** @brief UUID of the On-demand Ranging Data Characteristic. **/ +#define BLE_UUID_RAS_ONDEMAND_RD_VAL (0x2C16) + +/** @brief UUID of the RAS Control Point Characteristic. **/ +#define BLE_UUID_RAS_CP_VAL (0x2C17) + +/** @brief UUID of the Ranging Data Ready Characteristic. **/ +#define BLE_UUID_RAS_RD_READY_VAL (0x2C18) + +/** @brief UUID of the Ranging Data Overwritten Characteristic. **/ +#define BLE_UUID_RAS_RD_OVERWRITTEN_VAL (0x2C19) + +static const char *tag = "NimBLE_RAS_INITIATOR"; +static int blecent_gap_event(struct ble_gap_event *event, void *arg); + +void ble_store_config_init(void); + +static uint8_t connh; +static uint16_t ble_svc_ras_feat_val_handle; +static uint16_t ble_svc_ras_rd_val_handle; +static uint16_t ble_svc_ras_rd_ov_val_handle; +static uint16_t ble_svc_ras_cp_val_handle; +static uint16_t ble_svc_ras_od_val_handle; + +static int32_t most_recent_peer_ranging_counter = -1; +static int32_t most_recent_local_ranging_counter= -1 ; +static int32_t dropped_ranging_counter = -1; + +static uint8_t subscribe_all = 0; +static struct cs_steps_data local_cs_steps_data[LOCAL_PROCEDURE_MEM]; +static uint8_t nap; + +static void +blecent_on_disc_complete(const struct peer *peer, int status, void *arg); +static int blecs_gap_event(struct ble_cs_event *event, void *arg); +int blecent_on_subscribe(uint16_t conn_handle, + const struct ble_gatt_error *error, + struct ble_gatt_attr *attr, + void *arg) +{ + MODLOG_DFLT(INFO, "Subscribe complete; status=%d conn_handle=%d " + "attr_handle=%d\n", + error->status, conn_handle, attr->handle); + subscribe_all++; + if (subscribe_all == 4){ + struct ble_cs_initiator_procedure_start_params param; + memset(¶m,0,sizeof param); + param.conn_handle=conn_handle; + param.cb=blecs_gap_event; + param.cb_arg=NULL; + ble_cs_initiator_procedure_start(¶m); + } + + return 0; +} +static int ble_chan_ras_subsribe_by_uuid(ble_uuid_t *char_uuid,const struct peer *peer, uint16_t conn_handle) + { + int rc; + uint8_t value[2]; + const struct peer_dsc *dsc; + dsc = peer_dsc_find_uuid(peer, + BLE_UUID16_DECLARE(BLE_UUID_RANGING_SERVICE_VAL), + char_uuid, + BLE_UUID16_DECLARE(BLE_GATT_DSC_CLT_CFG_UUID16)); + if (dsc == NULL) { + MODLOG_DFLT(ERROR, "Error: Peer lacks a CCCD for RAS Feature characteristic\n"); + return 1; + } + + value[0] = 2; + value[1] = 0; + rc = ble_gattc_write_flat(conn_handle, dsc->dsc.handle, + value, sizeof value, blecent_on_subscribe, NULL); + + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error: Failed to subscribe to characteristic ,rc=%d\n", rc); + return 1; + } + return 0; + } + +void +ble_chan_ras_subscribe(const struct peer *peer, uint16_t conn_handle) +{ + int rc; + const struct peer_svc* svc = peer_svc_find_uuid(peer,BLE_UUID16_DECLARE(BLE_UUID_RANGING_SERVICE_VAL)); + if (svc == NULL) { + MODLOG_DFLT(ERROR, "Error: Peer doesn't support the RAS \n"); + goto err; + } + + rc = ble_chan_ras_subsribe_by_uuid(BLE_UUID16_DECLARE(BLE_UUID_RAS_CP_VAL),peer,conn_handle); + + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error: Peer doesn't support the RAS CP or fail to subscribe \n"); + goto err; + } else { + MODLOG_DFLT(INFO, "Subscribed to the RAS Control Point characteristic\n"); + } + + rc = ble_chan_ras_subsribe_by_uuid(BLE_UUID16_DECLARE(BLE_UUID_RAS_RD_READY_VAL),peer,conn_handle); + + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error: Peer doesn't support the RAS Data Ready or fail to subscribe \n"); + goto err; + } else { + MODLOG_DFLT(INFO, "Subscribed to the RAS Data Ready characteristic\n"); + } + + rc = ble_chan_ras_subsribe_by_uuid(BLE_UUID16_DECLARE(BLE_UUID_RAS_RD_OVERWRITTEN_VAL),peer,conn_handle); + + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error: Peer doesn't support the RAS Data overwritten or fail to subscribe \n"); + goto err; + } else { + MODLOG_DFLT(INFO, "Subscribed to the RAS Data Overwritten characteristic\n"); + } + + return ; + +err: + /* Terminate the connection. */ + ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); +} + +static int +blecent_on_custom_read(uint16_t conn_handle, + const struct ble_gatt_error *error, + struct ble_gatt_attr *attr, + void *arg) +{ + struct peer *peer = (struct peer *)arg; + MODLOG_DFLT(INFO, "Read complete RAS FEATURES; status=%d conn_handle=%d", error->status, conn_handle); + + if (error->status == 0) { + uint32_t var; + int rc = 0; + if (attr->om && OS_MBUF_PKTLEN(attr->om) > 0) { + os_mbuf_copydata(attr->om, 0, OS_MBUF_PKTLEN(attr->om), &var); + } else { + MODLOG_DFLT(ERROR, "Error: No data in the attribute\n"); + } + MODLOG_DFLT(INFO, " attr_handle = %u value = %" PRIu32, attr->handle, var); + + if (var & REAL_TIME_RANGING_DATA_BIT) { + /* Subscribe real time ranging data char */ + rc = ble_chan_ras_subsribe_by_uuid(BLE_UUID16_DECLARE(BLE_UUID_RAS_REALTIME_RD_VAL), peer, conn_handle); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error: Peer doesn't support the RAS on demand raging data or fail to subscribe \n"); + return -1; + } else { + MODLOG_DFLT(INFO, "Subscribed to the RAS Realtime Ranging Data characteristic\n"); + } + } else { + /* Subscribe On demand ranging data */ + rc = ble_chan_ras_subsribe_by_uuid(BLE_UUID16_DECLARE(BLE_UUID_RAS_ONDEMAND_RD_VAL), peer, conn_handle); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error: Peer doesn't support the RAS on demand ranging data or fail to subscribe \n"); + return -1; + } else { + MODLOG_DFLT(INFO, "Subscribed to the RAS On Demand Ranging Data characteristic\n"); + } + } + ble_chan_ras_subscribe(peer, conn_handle); + } else if (error->status == BLE_ATT_ERR_INSUFFICIENT_AUTHEN) { + MODLOG_DFLT(INFO, "Error: Insufficient authentication to read the characteristic\n"); + return -1; + } + return 0; +} + +/** + * Called when service discovery of the specified peer has completed. + */ +static void +blecent_on_disc_complete(const struct peer *peer, int status, void *arg) +{ + int rc; + if (status != 0) { + /* Service discovery failed. Terminate the connection. */ + MODLOG_DFLT(ERROR, "Error: Service discovery failed; status=%d " + "conn_handle=%d\n", status, peer->conn_handle); + ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); + return; + } + + /* Service discovery has completed successfully. Now we have a complete + * list of services, characteristics, and descriptors that the peer + * supports. + */ + MODLOG_DFLT(INFO, "Service discovery complete; status=%d " + "conn_handle=%d\n", status, peer->conn_handle); + + const struct peer_chr * chr = peer_chr_find_uuid(peer, + BLE_UUID16_DECLARE(BLE_UUID_RANGING_SERVICE_VAL), + BLE_UUID16_DECLARE(BLE_UUID_RAS_CP_VAL)); + if (chr == NULL) { + MODLOG_DFLT(ERROR, "Error: Peer lacks the RAS Control Point characteristic\n"); + ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); + return; + } + + ble_svc_ras_cp_val_handle = chr->chr.val_handle; + + chr = peer_chr_find_uuid(peer, + BLE_UUID16_DECLARE(BLE_UUID_RANGING_SERVICE_VAL), + BLE_UUID16_DECLARE(BLE_UUID_RAS_RD_READY_VAL)); + if (chr == NULL) { + MODLOG_DFLT(ERROR, "Error: Peer lacks the RAS Data Ready characteristic\n"); + ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); + return; + } + ble_svc_ras_rd_val_handle = chr->chr.val_handle; + + chr = peer_chr_find_uuid(peer, + BLE_UUID16_DECLARE(BLE_UUID_RANGING_SERVICE_VAL), + BLE_UUID16_DECLARE(BLE_UUID_RAS_RD_OVERWRITTEN_VAL)); + if (chr == NULL) { + MODLOG_DFLT(ERROR, "Error: Peer lacks the RAS Data Overwritten characteristic\n"); + ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); + return; + } + ble_svc_ras_rd_ov_val_handle = chr->chr.val_handle; + + chr = peer_chr_find_uuid(peer, + BLE_UUID16_DECLARE(BLE_UUID_RANGING_SERVICE_VAL), + BLE_UUID16_DECLARE(BLE_UUID_RAS_FEATURES_VAL)); + if (chr == NULL) { + MODLOG_DFLT(ERROR, "Error: Peer lacks the RAS Feature characteristic\n"); + ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); + return; + } + ble_svc_ras_feat_val_handle = chr->chr.val_handle; + + chr = peer_chr_find_uuid(peer, + BLE_UUID16_DECLARE(BLE_UUID_RANGING_SERVICE_VAL), + BLE_UUID16_DECLARE(BLE_UUID_RAS_ONDEMAND_RD_VAL)); + if (chr == NULL) { + MODLOG_DFLT(ERROR, "Error: Peer lacks the RAS On Demand Ranging Data characteristic\n"); + ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); + return; + } + ble_svc_ras_od_val_handle = chr->chr.val_handle; + + rc = ble_gattc_read(peer->conn_handle, ble_svc_ras_feat_val_handle, + blecent_on_custom_read, (void *)peer); + if (rc != 0) { + MODLOG_DFLT(ERROR, "2 Error: Failed to read the custom subscribable characteristic; ""rc=%d\n", rc); + } +} + +/** + * Initiates the GAP general discovery procedure. + */ +static void +blecent_scan(void) +{ + uint8_t own_addr_type; + struct ble_gap_disc_params disc_params; + int rc; + + /* Figure out address to use while advertising (no privacy for now) */ + rc = ble_hs_id_infer_auto(0, &own_addr_type); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error determining address type; rc=%d\n", rc); + return; + } + + /* Tell the controller to filter duplicates; we don't want to process + * repeated advertisements from the same device. + */ + disc_params.filter_duplicates = 1; + + /** + * Perform a passive scan. I.e., don't send follow-up scan requests to + * each advertiser. + */ + disc_params.passive = 1; + + /* Use defaults for the rest of the parameters. */ + disc_params.itvl = 0; + disc_params.window = 0; + disc_params.filter_policy = 0; + disc_params.limited = 0; + + rc = ble_gap_disc(own_addr_type, BLE_HS_FOREVER, &disc_params, + blecent_gap_event, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error initiating GAP discovery procedure; rc=%d\n", + rc); + } +} + +/** + * Connects to the sender of the specified advertisement of it looks + * interesting. A device is "interesting" if it advertises connectability and + * support for the Alert Notification service. + */ +static void +blecent_connect_if_interesting(void *disc) +{ + uint8_t own_addr_type; + int rc; + ble_addr_t *addr; + const uint8_t *adv_data = NULL; + int adv_data_len = 0; + int found = 0; + +#if CONFIG_EXAMPLE_EXTENDED_ADV + struct ble_gap_ext_disc_desc *ext = (struct ble_gap_ext_disc_desc *)disc; + addr = &ext->addr; + adv_data = ext->data; + adv_data_len = ext->length_data; +#else + struct ble_gap_disc_desc *d = (struct ble_gap_disc_desc *)disc; + addr = &d->addr; + adv_data = d->data; + adv_data_len = d->length_data; +#endif + + for (int i = 1; i < adv_data_len - 1; i++) { + if (adv_data[i-1] == 0x03 && adv_data[i] == 0x5b && adv_data[i+1] == 0x18) { + found = 1; + MODLOG_DFLT(DEBUG, "Found 0x5b18 at index %d\n", i); + break; + } + } + if (!found) { + MODLOG_DFLT(DEBUG, "0x5b18 not found in adv_data, skipping connect.\n"); + return; + } +#if !(MYNEWT_VAL(BLE_HOST_ALLOW_CONNECT_WITH_SCAN)) + /* Scanning must be stopped before a connection can be initiated. */ + rc = ble_gap_disc_cancel(); + if (rc != 0) { + MODLOG_DFLT(DEBUG, "Failed to cancel scan; rc=%d\n", rc); + return; + } +#endif + + rc = ble_hs_id_infer_auto(0, &own_addr_type); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error determining address type; rc=%d\n", rc); + return; + } + rc = ble_gap_connect(own_addr_type, addr, 30000, NULL, + blecent_gap_event, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Connection failed.\n"); + return; + } +} + +static int blecs_gap_event(struct ble_cs_event *event, void *arg){ + + switch(event->type){ + + case BLE_CS_EVENT_CS_PROCEDURE_COMPLETE: + MODLOG_DFLT(INFO, "LE CS Procedure Complete ,procedure counter"); + break; + case BLE_CS_EVENT_SUBEVET_RESULT: + MODLOG_DFLT(INFO, "LE CS Subevent Result ,procedure counter: %d\n", event->subev_result.procedure_counter); + MODLOG_DFLT(INFO, "event->subev_result.procedure_done_status =%d\n",event->subev_result.procedure_done_status); + if (event->subev_result.subevent_done_status == BLE_HCI_LE_CS_SUBEVENT_DONE_STATUS_ABORTED) { + MODLOG_DFLT(INFO, "LE CS Subevent Result , status: Aborted\n"); + dropped_ranging_counter=event->subev_result.procedure_counter; + return 0; + } + + if (dropped_ranging_counter == event->subev_result.procedure_counter) { + MODLOG_DFLT(INFO, "Ranging procedure was aborted\n"); + return 0; + } + if (event->subev_result.num_steps_reported) { + memcpy(&local_cs_steps_data, event->subev_result.steps, sizeof local_cs_steps_data); + + } + nap=event->subev_result.num_antenna_paths; + most_recent_local_ranging_counter=event->subev_result.procedure_counter; + if (event->subev_result.procedure_done_status == BLE_HCI_LE_CS_SUBEVENT_DONE_STATUS_COMPLETE) { + most_recent_local_ranging_counter=event->subev_result.procedure_counter; + } else if (event->subev_result.procedure_done_status == BLE_HCI_LE_CS_SUBEVENT_DONE_STATUS_ABORTED) { + MODLOG_DFLT(INFO, "LE CS Procedure , status: Aborted\n"); + memset(&local_cs_steps_data,0,sizeof local_cs_steps_data); + } + + break; + + case BLE_CS_EVENT_SUBEVET_RESULT_CONTINUE: + MODLOG_DFLT(INFO, "event->subev_result_continue.procedure_done_status =%d\n",event->subev_result_continue.procedure_done_status); + break; + default: + return 0; + + } + return 0; +} + +static int exchange_func(uint16_t conn_handle, const struct ble_gatt_error *error, uint16_t mtu, void *arg) +{ + MODLOG_DFLT(INFO, "MTU exchange complete; status=%d conn_handle=%d mtu=%d\n", + error->status, conn_handle, mtu); + return 0; +} + +/** + * The nimble host executes this callback when a GAP event occurs. The + * application associates a GAP event callback with each connection that is + * established. blecent uses the same callback for all connections. + * + * @param event The event being signalled. + * @param arg Application-specified argument; unused by + * blecent. + * + * @return 0 if the application successfully handled the + * event; nonzero on failure. The semantics + * of the return code is specific to the + * particular GAP event being signalled. + */ +static int +blecent_gap_event(struct ble_gap_event *event, void *arg) +{ + struct ble_gap_conn_desc desc; + struct ble_hs_adv_fields fields; + + int rc; + + switch (event->type) { + case BLE_GAP_EVENT_DISC: + rc = ble_hs_adv_parse_fields(&fields, event->disc.data, + event->disc.length_data); + if (rc != 0) { + return 0; + } + + /* An advertisement report was received during GAP discovery. */ + print_adv_fields(&fields); + + /* Try to connect to the advertiser if it looks interesting. */ + blecent_connect_if_interesting(&event->disc); + return 0; + + case BLE_GAP_EVENT_CONNECT: + /* A new connection was established or a connection attempt failed. */ + if (event->connect.status == 0) { + /* Connection successfully established. */ + MODLOG_DFLT(INFO, "Connection established "); + + rc = ble_gap_conn_find(event->connect.conn_handle, &desc); + assert(rc == 0); + print_conn_desc(&desc); + MODLOG_DFLT(INFO, "\n"); + + /* Remember peer. */ + rc = peer_add(event->connect.conn_handle); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Failed to add peer; rc=%d\n", rc); + return 0; + } + connh = event->connect.conn_handle; + rc = ble_gap_security_initiate(event->connect.conn_handle); + if (rc != 0) { + MODLOG_DFLT(INFO, "Security could not be initiated, rc = %d\n", rc); + return ble_gap_terminate(event->connect.conn_handle, + BLE_ERR_REM_USER_CONN_TERM); + } + + } else { + /* Connection attempt failed; resume scanning. */ + MODLOG_DFLT(ERROR, "Error: Connection failed; status=%d\n", + event->connect.status); + blecent_scan(); + } + + return 0; + + case BLE_GAP_EVENT_DISCONNECT: + /* Connection terminated. */ + MODLOG_DFLT(INFO, "disconnect; reason=%d ", event->disconnect.reason); + print_conn_desc(&event->disconnect.conn); + MODLOG_DFLT(INFO, "\n"); + + /* Forget about peer. */ + peer_delete(event->disconnect.conn.conn_handle); + + /* Resume scanning. */ + blecent_scan(); + return 0; + + case BLE_GAP_EVENT_DISC_COMPLETE: + MODLOG_DFLT(INFO, "discovery complete; reason=%d\n", + event->disc_complete.reason); + return 0; + + case BLE_GAP_EVENT_ENC_CHANGE: + /* Encryption has been enabled or disabled for this connection. */ + MODLOG_DFLT(INFO, "encryption change event; status=%d ", + event->enc_change.status); + rc = ble_gap_conn_find(event->enc_change.conn_handle, &desc); + assert(rc == 0); + print_conn_desc(&desc); + ble_gattc_exchange_mtu(event->enc_change.conn_handle, exchange_func, NULL); + rc = peer_disc_all(event->enc_change.conn_handle,blecent_on_disc_complete, NULL); + if(rc != 0) { + MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); + return 0; + } + return 0; + + case BLE_GAP_EVENT_NOTIFY_RX: + /* Peer sent us a notification or indication. */ + MODLOG_DFLT(INFO, "received %s; conn_handle=%d attr_handle=%d " + "attr_len=%d\n", + event->notify_rx.indication ? + "indication" : + "notification", + event->notify_rx.conn_handle, + event->notify_rx.attr_handle, + OS_MBUF_PKTLEN(event->notify_rx.om)); + + /* Attribute data is contained in event->notify_rx.om. Use + * `os_mbuf_copydata` to copy the data received in notification mbuf */ + + if(ble_svc_ras_cp_val_handle == event->notify_rx.attr_handle){ + MODLOG_DFLT(INFO, "RAS Control Point Indication\n"); + uint8_t value[RASCP_CMD_OPCODE_LEN + sizeof(uint16_t)] = {0}; + int len = OS_MBUF_PKTLEN(event->notify_rx.om); + if (len < RASCP_CMD_OPCODE_LEN + sizeof(uint16_t)) { + MODLOG_DFLT(ERROR, "Error: Invalid RAS Control Point Indication length %d\n", len); + return 0; + } + os_mbuf_copydata(event->notify_rx.om, 0, RASCP_CMD_OPCODE_LEN + sizeof(uint16_t), &value); + + MODLOG_DFLT(INFO, "Received RAS Control Point Indication, ranging counter = %d\n", *(uint16_t *)&value[RASCP_CMD_OPCODE_LEN]); + MODLOG_DFLT(INFO, "Received RAS Control Point Indication, opcode = %d\n", value[0]); + + if (value[0] == RASCP_RSP_OPCODE_COMPLETE_RD_RSP) { + // Reuse the same + value[0] =RASCP_OPCODE_ACK_RD ; + uint16_t ranging_counter=most_recent_peer_ranging_counter; + // copy ranging counter to the value + memcpy(&value[RASCP_CMD_OPCODE_LEN], &ranging_counter, sizeof(uint16_t)); + rc = ble_gattc_write_no_rsp_flat(event->notify_rx.conn_handle, ble_svc_ras_cp_val_handle, &value, sizeof value); + } else if( value[0] == RASCP_RSP_OPCODE_RSP_CODE) { + MODLOG_DFLT(INFO, "Sucssefully completed the Ranging procedure\n"); + vTaskDelay(1000 / portTICK_PERIOD_MS); + + } + } + else if(ble_svc_ras_rd_val_handle == event->notify_rx.attr_handle){ + MODLOG_DFLT(INFO, "Received Ranging Data Ready Indication\n"); + uint16_t ranging_counter; + os_mbuf_copydata(event->notify_rx.om, 0, sizeof(uint16_t), &ranging_counter); + most_recent_peer_ranging_counter=ranging_counter; + most_recent_local_ranging_counter=0; + + if (most_recent_peer_ranging_counter!=most_recent_local_ranging_counter) { + MODLOG_DFLT(INFO, "Ranging counter mismatch : %" PRId32 " , %" PRId32, + most_recent_peer_ranging_counter,most_recent_local_ranging_counter); + return 0; + } + + uint8_t value[RASCP_CMD_OPCODE_LEN + sizeof(uint16_t)] = {0}; + value[0] = RASCP_OPCODE_GET_RD; + + memcpy(&value[RASCP_CMD_OPCODE_LEN], &ranging_counter, sizeof(uint16_t)); + rc = ble_gattc_write_no_rsp_flat(event->notify_rx.conn_handle, ble_svc_ras_cp_val_handle, &value, sizeof value); + + } else if (ble_svc_ras_rd_ov_val_handle == event->notify_rx.attr_handle) { + /* + handle the incoming notification + */ + } else if (ble_svc_ras_od_val_handle == event->notify_rx.attr_handle) { + MODLOG_DFLT(INFO, "Received On Demand Ranging Data\n"); + + struct segment ras_segment; + int notif_len = OS_MBUF_PKTLEN(event->notify_rx.om); + os_mbuf_copydata(event->notify_rx.om, 0,notif_len , &ras_segment); + MODLOG_DFLT(INFO, "Received On Demand Ranging Data , len = %d\n",notif_len); + uint8_t * data= (uint8_t *)ras_segment.data; + for(int i=0;imtu.conn_handle, + event->mtu.channel_id, + event->mtu.value); + return 0; + + case BLE_GAP_EVENT_REPEAT_PAIRING: + /* We already have a bond with the peer, but it is attempting to + * establish a new secure link. This app sacrifices security for + * convenience: just throw away the old bond and accept the new link. + */ + + /* Delete the old bond. */ + rc = ble_gap_conn_find(event->repeat_pairing.conn_handle, &desc); + assert(rc == 0); + ble_store_util_delete_peer(&desc.peer_id_addr); + + /* Return BLE_GAP_REPEAT_PAIRING_RETRY to indicate that the host should + * continue with the pairing operation. + */ + return BLE_GAP_REPEAT_PAIRING_RETRY; + +#if CONFIG_EXAMPLE_EXTENDED_ADV + case BLE_GAP_EVENT_EXT_DISC: + + ext_print_adv_report(&event->ext_disc); + blecent_connect_if_interesting(&event->ext_disc); + return 0; +#endif + return 0; + default: + return 0; + } +} + +static void +blecent_on_reset(int reason) +{ + MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason); +} + +static void +blecent_on_sync(void) +{ + /* Make sure we have set Host feature bit for Channel Sounding*/ + int rc; + rc = ble_gap_set_host_feat(47,0x01); + /* Make sure we have proper identity address set (public preferred) */ + rc = ble_hs_util_ensure_addr(0); + assert(rc == 0); + + /* Begin scanning for a peripheral to connect to. */ + blecent_scan(); +} + +void blecent_host_task(void *param) +{ + ESP_LOGI(tag, "BLE Host Task Started"); + /* This function will return only when nimble_port_stop() is executed */ + nimble_port_run(); + + nimble_port_freertos_deinit(); +} + +void +app_main(void) +{ + int rc; + /* Initialize NVS — it is used to store PHY calibration data */ + esp_err_t ret = nvs_flash_init(); + if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_ERROR_CHECK(nvs_flash_erase()); + ret = nvs_flash_init(); + } + ESP_ERROR_CHECK(ret); + + ret = nimble_port_init(); + if (ret != ESP_OK) { + ESP_LOGE(tag, "Failed to init nimble %d ", ret); + return; + } + + /* Configure the host. */ + ble_hs_cfg.reset_cb = blecent_on_reset; + ble_hs_cfg.sync_cb = blecent_on_sync; + ble_hs_cfg.store_status_cb = ble_store_util_status_rr; + + /* Initialize data structures to track connected peers. */ + rc = peer_init(MYNEWT_VAL(BLE_MAX_CONNECTIONS), 64, 64, 64); + assert(rc == 0); + + /* Set the default device name. */ + rc = ble_svc_gap_device_name_set("nimble_ble_channel_sounding"); + assert(rc == 0); + + /* XXX Need to have template for store */ + ble_store_config_init(); + + nimble_port_freertos_init(blecent_host_task); + +} diff --git a/examples/bluetooth/nimble/ble_chan_sound_initiator/sdkconfig.ci b/examples/bluetooth/nimble/ble_chan_sound_initiator/sdkconfig.ci new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/examples/bluetooth/nimble/ble_chan_sound_initiator/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/nimble/ble_chan_sound_initiator/sdkconfig.ci.esp32c2_xtal26m new file mode 100644 index 000000000000..172f022b67ea --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_initiator/sdkconfig.ci.esp32c2_xtal26m @@ -0,0 +1,2 @@ +CONFIG_IDF_TARGET="esp32c2" +CONFIG_XTAL_FREQ_26=y diff --git a/examples/bluetooth/nimble/ble_chan_sound_initiator/sdkconfig.defaults b/examples/bluetooth/nimble/ble_chan_sound_initiator/sdkconfig.defaults new file mode 100644 index 000000000000..7f17246e2007 --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_initiator/sdkconfig.defaults @@ -0,0 +1,19 @@ +# Override some defaults so BT stack is enabled +# in this example + +# +# BT config +# +CONFIG_BT_ENABLED=y +CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y +CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n +CONFIG_BTDM_CTRL_MODE_BTDM=n +CONFIG_BT_BLUEDROID_ENABLED=n +CONFIG_BT_CONTROLLER_DISABLED=y +CONFIG_BT_NIMBLE_60_FEATURE_SUPPORT=y +CONFIG_BT_NIMBLE_ENABLED=y +CONFIG_BT_NIMBLE_EXT_ADV=y +CONFIG_BT_NIMBLE_CHANNEL_SOUNDING=y +CONFIG_BT_NIMBLE_TRANSPORT_EVT_SIZE=78 +CONFIG_BT_NIMBLE_ATT_PREFERRED_MTU=498 +CONFIG_BT_NIMBLE_GATT_MAX_PROCS=6 diff --git a/examples/bluetooth/nimble/ble_chan_sound_initiator/sdkconfig.defaults.esp32c2 b/examples/bluetooth/nimble/ble_chan_sound_initiator/sdkconfig.defaults.esp32c2 new file mode 100644 index 000000000000..bae6ee2eea06 --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_initiator/sdkconfig.defaults.esp32c2 @@ -0,0 +1,8 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_IDF_TARGET="esp32c2" +CONFIG_BT_NIMBLE_EXT_ADV=y +CONFIG_BT_ENABLED=y +CONFIG_BT_NIMBLE_ENABLED=y +CONFIG_BT_NIMBLE_50_FEATURE_SUPPORT=y diff --git a/examples/bluetooth/nimble/ble_chan_sound_initiator/sdkconfig.defaults.esp32c6 b/examples/bluetooth/nimble/ble_chan_sound_initiator/sdkconfig.defaults.esp32c6 new file mode 100644 index 000000000000..0751474dc402 --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_initiator/sdkconfig.defaults.esp32c6 @@ -0,0 +1,8 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_BT_NIMBLE_EXT_ADV=y +CONFIG_BT_ENABLED=y +CONFIG_BT_NIMBLE_ENABLED=y +CONFIG_BT_NIMBLE_50_FEATURE_SUPPORT=y +CONFIG_BT_NIMBLE_CHANNEL_SOUNDING=y diff --git a/examples/bluetooth/nimble/ble_chan_sound_initiator/tutorial/blecent_walkthrough.md b/examples/bluetooth/nimble/ble_chan_sound_initiator/tutorial/blecent_walkthrough.md new file mode 100644 index 000000000000..3192c30d92be --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_initiator/tutorial/blecent_walkthrough.md @@ -0,0 +1,995 @@ +# BLE Central Example Walkthrough + +## Introduction + +In this tutorial, we will explore the blecent example code provided by Espressif's ESP-IDF framework. The primary goal of the blecent example is to illustrate how a BLE Central device can interact with multiple BLE Peripheral devices in the vicinity. The Central device initiates the communication by scanning for nearby Peripherals and establishing connections with them. By the end of this tutorial, you will have a comprehensive understanding of how the blecent example code operates as a BLE Central application. + +## Includes + +This example is located in the examples folder of the ESP-IDF under the [blecent/main](../main). The [main.c](../main/main.c) file located in the main folder contains all the functionality that we are going to review. The header files contained in [main.c](../main/main.c) are: + +```c +#include "esp_log.h" +#include "nvs_flash.h" +/* BLE */ +#include "nimble/nimble_port.h" +#include "nimble/nimble_port_freertos.h" +#include "host/ble_hs.h" +#include "host/util/util.h" +#include "console/console.h" +#include "services/gap/ble_svc_gap.h" +#include "blecent.h" +``` +These `includes` are required for the FreeRTOS and underlying system components to run, including the logging functionality and a library to store data in non-volatile flash memory. We are interested in `“nimble_port.h”`, `“nimble_port_freertos.h”`, `"ble_hs.h"`, `“ble_svc_gap.h”` and `“blecent.h”` which expose the BLE APIs required to implement this example. + +* `nimble_port.h`: Includes the declaration of functions required for the initialization of the nimble stack. +* `nimble_port_freertos.h`: Initializes and enables nimble host task. +* `ble_hs.h`: Defines the functionalities to handle the host event. +* `ble_svc_gap.h`: Defines the macros for device name, and device appearance and declares the function to set them. +* `blecent.h`: Provides necessary definitions and forward declarations for the blecent example's functionality, specifically for interacting with BLE services and characteristics related to Alert Notifications. + +## Main Entry Point + +The program's entry point is the app_main() function: +```c +void +app_main(void) +{ + int rc; + /* Initialize NVS — it is used to store PHY calibration data */ + esp_err_t ret = nvs_flash_init(); + if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_ERROR_CHECK(nvs_flash_erase()); + ret = nvs_flash_init(); + } + ESP_ERROR_CHECK(ret); + + ret = nimble_port_init(); + if (ret != ESP_OK) { + ESP_LOGE(tag, "Failed to init nimble %d ", ret); + return; + } + + /* Configure the host. */ + ble_hs_cfg.reset_cb = blecent_on_reset; + ble_hs_cfg.sync_cb = blecent_on_sync; + ble_hs_cfg.store_status_cb = ble_store_util_status_rr; + + /* Initialize data structures to track connected peers. */ + rc = peer_init(MYNEWT_VAL(BLE_MAX_CONNECTIONS), 64, 64, 64); + assert(rc == 0); + + /* Set the default device name. */ + rc = ble_svc_gap_device_name_set("nimble-blecent"); + assert(rc == 0); + + /* XXX Need to have template for store */ + ble_store_config_init(); + + nimble_port_freertos_init(blecent_host_task); + +#if CONFIG_EXAMPLE_INIT_DEINIT_LOOP + stack_init_deinit(); +#endif + +} +``` +The main function starts by initializing the non-volatile storage library. This library allows us to save the key-value pairs in flash memory. `nvs_flash_init()` stores the PHY calibration data. In a Bluetooth Low Energy (BLE) device, cryptographic keys used for encryption and authentication are often stored in Non-Volatile Storage (NVS). BLE stores the peer keys, CCCD keys, peer records, etc on NVS. By storing these keys in NVS, the BLE device can quickly retrieve them when needed, without the need for time-consuming key generations. +```c +esp_err_t ret = nvs_flash_init(); +if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_ERROR_CHECK(nvs_flash_erase()); + ret = nvs_flash_init(); +} +ESP_ERROR_CHECK(ret); +``` + +## BT Controller and Stack Initialization + +The main function calls `nimble_port_init()` to initialize BT Controller and nimble stack. This function initializes the BT controller by first creating its configuration structure named `esp_bt_controller_config_t` with default settings generated by the `BT_CONTROLLER_INIT_CONFIG_DEFAULT()` macro. It implements the Host Controller Interface (HCI) on the controller side, the Link Layer (LL), and the Physical Layer (PHY). The BT Controller is invisible to the user applications and deals with the lower layers of the BLE stack. The controller configuration includes setting the BT controller stack size, priority, and HCI baud rate. With the settings created, the BT controller is initialized and enabled with the `esp_bt_controller_init()` and `esp_bt_controller_enable()` functions: + +```c +esp_bt_controller_config_t config_opts = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); +ret = esp_bt_controller_init(&config_opts); +``` +Next, the controller is enabled in BLE Mode. + +```c +ret = esp_bt_controller_enable(ESP_BT_MODE_BLE); +``` +The controller should be enabled in `ESP_BT_MODE_BLE` if you want to use the BLE mode. + +There are four Bluetooth modes supported: + +1. `ESP_BT_MODE_IDLE`: Bluetooth not running +2. `ESP_BT_MODE_BLE`: BLE mode +3. `ESP_BT_MODE_CLASSIC_BT`: BT Classic mode +4. `ESP_BT_MODE_BTDM`: Dual mode (BLE + BT Classic) + +After the initialization of the BT controller, the nimble stack, which includes the common definitions and APIs for BLE, is initialized by using `esp_nimble_init()`: + +```c +esp_err_t esp_nimble_init(void) +{ +#if !SOC_ESP_NIMBLE_CONTROLLER + /* Initialize the function pointers for OS porting */ + npl_freertos_funcs_init(); + + npl_freertos_mempool_init(); + + if(esp_nimble_hci_init() != ESP_OK) { + ESP_LOGE(NIMBLE_PORT_LOG_TAG, "hci inits failed\n"); + return ESP_FAIL; + } + + /* Initialize default event queue */ + ble_npl_eventq_init(&g_eventq_dflt); + /* Initialize the global memory pool */ + os_mempool_module_init(); + os_msys_init(); + +#endif + /* Initialize the host */ + ble_transport_hs_init(); + + return ESP_OK; +} +``` + +The host is configured by setting up the callbacks for Stack-reset, Stack-sync, and Storage status. +```c +ble_hs_cfg.reset_cb = blecent_on_reset; +ble_hs_cfg.sync_cb = blecent_on_sync; +ble_hs_cfg.store_status_cb = ble_store_util_status_rr; +``` + +The main function invokes `peer_init()` to initialize memory pools to manage peer, service, characteristics, and descriptor objects in BLE. +```c +rc = peer_init(MYNEWT_VAL(BLE_MAX_CONNECTIONS), 64, 64, 64); +``` + +The main function calls `ble_svc_gap_device_name_set()` to set the default device name. +```c +rc = ble_svc_gap_device_name_set("nimble-blecent"); +``` + +The main function calls `ble_store_config_init()` to configure the host by setting up the storage callbacks which handle the read, write, and deletion of security material. +```c +/* XXX Need to have a template for store */ + ble_store_config_init(); +``` + +The main function ends by creating a task where nimble will run using `nimble_port_freertos_init()`. This enables the nimble stack by using `esp_nimble_enable()`. + +```c +nimble_port_freertos_init(blecent_host_task); +``` + +`esp_nimble_enable()` create a task where the nimble host will run. It is not strictly necessary to have a separate task for the nimble host, but to handle the default queue, it is easier to create a separate task. + + +## CONFIG_EXAMPLE_INIT_DEINIT_LOOP + +```c +#if CONFIG_EXAMPLE_INIT_DEINIT_LOOP +/* This function showcases stack init and deinit procedure. */ +static void stack_init_deinit(void) +{ + int rc; + while(1) { + + vTaskDelay(1000); + + ESP_LOGI(tag, "Deinit host"); + + rc = nimble_port_stop(); + if (rc == 0) { + nimble_port_deinit(); + } else { + ESP_LOGI(tag, "Nimble port stop failed, rc = %d", rc); + break; + } + + vTaskDelay(1000); + + ESP_LOGI(tag, "Init host"); + + rc = nimble_port_init(); + if (rc != ESP_OK) { + ESP_LOGI(tag, "Failed to init nimble %d ", rc); + break; + } + + nimble_port_freertos_init(blecent_host_task); + + ESP_LOGI(tag, "Waiting for 1 second"); + } +} +#endif +``` + +The `stack_init_deinit` function provides a demonstration of the initialization and deinitialization procedure for the NimBLE stack. It operates within a loop that showcases the following steps: + +* **Delay**: The function starts by introducing a delay of 1000 tick periods using the vTaskDelay function. This allows time for certain operations to complete before moving on. + +* **Deinitialization**: The function logs that the host deinitialization process is beginning. It calls `nimble_port_stop` to halt the NimBLE stack's operation. If the stop operation is successful (returning 0), the function then calls `nimble_port_deinit` to deinitialize the NimBLE stack. If the stop operation fails, an error message is logged, and the loop breaks. + +* **Delay**: Another 1000 tick periods delay is introduced before proceeding with initialization. + +* **Initialization**: The function logs that the host initialization process is starting. It calls `nimble_port_init` to initialize the NimBLE stack. If the initialization fails (returning anything other than `ESP_OK`), an error message is logged, and the loop breaks. + +* **FreeRTOS Initialization**: After successful NimBLE stack initialization, the function calls `nimble_port_freertos_init` and provides the `blecent_host_task` as a parameter. This step sets up the NimBLE stack to work within the FreeRTOS environment. + + +## blecent_scan() + +```c +static void +blecent_scan(void) +{ + uint8_t own_addr_type; + struct ble_gap_disc_params disc_params; + int rc; + + /* Figure out address to use while advertising (no privacy for now) */ + rc = ble_hs_id_infer_auto(0, &own_addr_type); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error determining address type; rc=%d\n", rc); + return; + } + + /* Tell the controller to filter duplicates; we don't want to process + * repeated advertisements from the same device. + */ + disc_params.filter_duplicates = 1; + + /** + * Perform a passive scan. I.e., don't send follow-up scan requests to + * each advertiser. + */ + disc_params.passive = 1; + + /* Use defaults for the rest of the parameters. */ + disc_params.itvl = 0; + disc_params.window = 0; + disc_params.filter_policy = 0; + disc_params.limited = 0; + + rc = ble_gap_disc(own_addr_type, BLE_HS_FOREVER, &disc_params, + blecent_gap_event, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error initiating GAP discovery procedure; rc=%d\n", + rc); + } +} +``` + +The function `blecent_scan()` initiates the General Discovery Procedure for scanning nearby BLE devices. The function starts by declaring several variables used in the scanning process. These variable include: +* `own_addr_type`: A uint8_t variable that stores the type of address (public or random) that the device will use while scanning. +* `disc_params`: A struct of type `ble_gap_disc_params` that holds the parameters for the GAP (Generic Access Profile) discovery procedure. + +The function uses `ble_hs_id_infer_auto()` to determine the address type (public or random) that the device should use for scanning. The result is stored in the own_addr_type variable. + +Configure Discovery Parameters: The function configures the disc_params struct with the following settings: + +* `filter_duplicates`: Set to 1, indicating that the controller should filter out duplicate advertisements from the same device. This reduces unnecessary processing of repeated advertisements. +* `passive`: Set to 1, indicating that the scan will be a passive scan. In a passive scan, the scanning device only listens for advertisements without sending any follow-up scan requests to advertisers. It's used for general device discovery. + +The function sets some other parameters in the disc_params struct to their default values: + +* `itvl`: The scan interval is set to 0, using the default value. +* `window`: The scan window is set to 0, using the default value. +* `filter_policy`: The filter policy is set to 0, using the default value. +* `limited`: The limited discovery mode is set to 0, using the default value. + +The function then calls `ble_gap_disc()` to initiate the BLE scanning procedure. It passes the following parameters: + +* `own_addr_type`: The address type to use for scanning (determined earlier). +* `BLE_HS_FOREVER`: The duration for which the scan should continue (in this case, indefinitely). +* `&disc_params`: A pointer to the ble_gap_disc_params struct containing the scan parameters. +* `blecent_gap_event`: The callback function to handle the scan events (such as receiving advertisements from nearby devices). +* `NULL`: The argument for the callback context, which is not used in this example. + +If an error occurs during the initiation of the scanning procedure, the function prints an error message. + + +## blecent_gap_event + +The function `blecent_gap_event` is in responsible of managing various GAP (Generic Access Profile) events that arise during the BLE communication. + +The function employs a switch statement to manage diverse types of GAP events that can be received. + +* `BLE_GAP_EVENT_DISC`: This case is activated when a new advertisement report is detected during scanning. The function extracts the advertisement data using `ble_hs_adv_parse_fields` and then displays the advertisement fields using the print_adv_fields function. It subsequently verifies if the discovered device is of interest and attempts to establish a connection with it. + +* `BLE_GAP_EVENT_CONNECT`: This case is triggered when a new connection is established or when a connection attempt fails. If the Connection was established then the connection descriptor is initiated using the `ble_gap_conn_find()` method else advertisement is resumed. If the connection is successful, it displays the connection descriptor through `print_conn_desc` and stores the peer information. Additionally, it handles optional features such as BLE power control, vendor-specific commands, and security initiation. In the event of a connection attempt failure, it resumes scanning. + +* `BLE_GAP_EVENT_DISCONNECT`: This case is activated when a connection is terminated. It prints the reason for disconnection and the connection descriptor before removing information about the peer and resuming scanning. + +* `BLE_GAP_EVENT_DISC_COMPLETE`: This case is triggered upon the completion of the GAP discovery process. It displays the reason for the discovery's completion. + +* `BLE_GAP_EVENT_ENC_CHANGE`: This case is activated when encryption is enabled or disabled for a connection. It displays the status of the encryption change and the connection descriptor. If encryption is enabled (when CONFIG_EXAMPLE_ENCRYPTION is defined), it initiates service discovery. + +* `BLE_GAP_EVENT_NOTIFY_RX`: This case is triggered when the Central device receives a notification or indication from the Peripheral device. It displays information about the received data. + +* `BLE_GAP_EVENT_MTU`: This case is activated when the Maximum Transmission Unit (MTU) is updated for a connection. It prints the new MTU value and related information. + +* `BLE_GAP_EVENT_REPEAT_PAIRING`: This case is triggered when the Peripheral device attempts to establish a new secure link with the Central despite an existing bond. The app prioritizes convenience over security and deletes the old bond, accepting the new link. + + So, event handler function effectively manages various GAP events, handles connection-related tasks, initiates security procedures, performs service discovery, and accommodates optional features based on the configuration settings. + + +## blecent_should_connect + +```c +static int +blecent_should_connect(const struct ble_gap_disc_desc *disc) +{ + struct ble_hs_adv_fields fields; + int rc; + int i; + + /* The device has to be advertising connectability. */ + if (disc->event_type != BLE_HCI_ADV_RPT_EVTYPE_ADV_IND && + disc->event_type != BLE_HCI_ADV_RPT_EVTYPE_DIR_IND) { + + return 0; + } + + rc = ble_hs_adv_parse_fields(&fields, disc->data, disc->length_data); + if (rc != 0) { + return 0; + } + + if (strlen(CONFIG_EXAMPLE_PEER_ADDR) && (strncmp(CONFIG_EXAMPLE_PEER_ADDR, "ADDR_ANY", strlen("ADDR_ANY")) != 0)) { + ESP_LOGI(tag, "Peer address from menuconfig: %s", CONFIG_EXAMPLE_PEER_ADDR); + /* Convert string to address */ + sscanf(CONFIG_EXAMPLE_PEER_ADDR, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", + &peer_addr[5], &peer_addr[4], &peer_addr[3], + &peer_addr[2], &peer_addr[1], &peer_addr[0]); + if (memcmp(peer_addr, disc->addr.val, sizeof(disc->addr.val)) != 0) { + return 0; + } + } + + /* The device has to advertise support for the Alert Notification + * service (0x1811). + */ + for (i = 0; i < fields.num_uuids16; i++) { + if (ble_uuid_u16(&fields.uuids16[i].u) == BLECENT_SVC_ALERT_UUID) { + return 1; + } + } + + return 0; +} +``` + +This function is responsible for determining whether the Central device should establish a connection with a discovered Peripheral device based on the advertisement data received during scanning. Let's break down the code step by step: + +* **Local Variables**: The function declares several local variables, including `fields` of type `struct ble_hs_adv_fields` to hold the parsed advertisement data, `rc` to store the return code of function calls, and `i` for loop iteration. + +* **Checking Advertisement Event Type**: The function begins by checking the event type of the advertisement report stored in the `disc` structure. It verifies whether the event type indicates that the device is advertising its connectability. Specifically, it checks for two event types: `BLE_HCI_ADV_RPT_EVTYPE_ADV_IND` (Connectable Undirected Advertising) and `BLE_HCI_ADV_RPT_EVTYPE_DIR_IND` (Directed Advertising). If the event type is neither of these, it means the device is not connectable, and the function returns 0, indicating that the Central device should not attempt to connect. + +* **Parsing Advertisement Data**: The function then attempts to parse the advertisement data using the `ble_hs_adv_parse_fields` function. The advertisement data is stored in the `disc->data` buffer, and its length is specified by `disc->length_data`. The parsed data is then stored in the `fields` struct. + +* **Checking Peer Address**: This section of the code handles an optional feature where the Central device can specify a specific peer address it wants to connect to. It checks whether the configuration option `CONFIG_EXAMPLE_PEER_ADDR` is set and not equal to `ADDR_ANY` (a special value). If this configuration is set, it means the Central device wants to connect to a specific device based on its address. The function converts the specified peer address from a string representation to a byte array `peer_addr` using the `sscanf` function. If the received device's address (in `disc->addr.val`) does not match the specified peer address, the function returns 0, indicating that the Central device should not connect to this device. + +* **Checking for Alert Notification Service**: Next, the function examines the parsed advertisement data to check for the presence of the Alert Notification service (UUID: 0x1811). The Alert Notification service is used to notify the Central device about alerts or notifications from the Peripheral device. If the advertised service is found in the advertisement data, the function returns 1, indicating that the Central device should proceed with connecting to this device. + +* **Returning 0**: If none of the conditions mentioned above are met (i.e., the event type is not connectable, the peer address check is not enabled, and the Alert Notification service is not advertised), the function returns 0, signaling that the Central device should not establish a connection with this device. + + +## blecent_connect_if_interesting + +```c +/** + * Connects to the sender of the specified advertisement of it looks + * interesting. A device is "interesting" if it advertises connectability and + * support for the Alert Notification service. + */ +static void +blecent_connect_if_interesting(void *disc) +{ + uint8_t own_addr_type; + int rc; + ble_addr_t *addr; + + /* Don't do anything if we don't care about this advertiser. */ +#if CONFIG_EXAMPLE_EXTENDED_ADV + if (!ext_blecent_should_connect((struct ble_gap_ext_disc_desc *)disc)) { + return; + } +#else + if (!blecent_should_connect((struct ble_gap_disc_desc *)disc)) { + return; + } +#endif + + /* Scanning must be stopped before a connection can be initiated. */ + rc = ble_gap_disc_cancel(); + if (rc != 0) { + MODLOG_DFLT(DEBUG, "Failed to cancel scan; rc=%d\n", rc); + return; + } + + /* Figure out address to use for connect (no privacy for now) */ + rc = ble_hs_id_infer_auto(0, &own_addr_type); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error determining address type; rc=%d\n", rc); + return; + } + + /* Try to connect the the advertiser. Allow 30 seconds (30000 ms) for + * timeout. + */ +#if CONFIG_EXAMPLE_EXTENDED_ADV + addr = &((struct ble_gap_ext_disc_desc *)disc)->addr; +#else + addr = &((struct ble_gap_disc_desc *)disc)->addr; +#endif + + rc = ble_gap_connect(own_addr_type, addr, 30000, NULL, + blecent_gap_event, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error: Failed to connect to device; addr_type=%d " + "addr=%s; rc=%d\n", + addr->type, addr_str(addr->val), rc); + return; + } +} +``` + +Function `blecent_connect_if_interesting` is to handle the connection process to a BLE Peripheral device if certain criteria are met, making the device interesting for the Central to connect to. Let's summarize the code step by step: + +* **Local Variables**: The function declares local variables, including `own_addr_type` of type `uint8_t` to store the own address type of the Central device, `rc` to store the return code of function calls, and `addr` of type `ble_addr_t*` to store the address of the discovered advertiser. + +* **Checking Device Interest**: The function checks if the advertiser meets the criteria for an interesting device to connect to. The criteria are evaluated using either `blecent_should_connect` or `ext_blecent_should_connect`, depending on the presence of the `CONFIG_EXAMPLE_EXTENDED_ADV` configuration. If the advertiser doesn't meet the criteria, the function returns without attempting a connection. + +* **Stopping Scanning**: Before initiating a connection, the function cancels any ongoing BLE scanning using `ble_gap_disc_cancel()`. Scanning must be halted to establish a connection. + +* **Determining Address Type**: The function infers the address type of the Central device for the connection by calling `ble_hs_id_infer_auto`, and the inferred type is stored in `own_addr_type`. If there's an error during address type determination, the function exits without attempting a connection. + +* **Initiating Connection**: With scanning stopped and the address type determined, the function is ready to initiate the connection. It retrieves the advertiser's address from the provided `disc` argument (of type `struct ble_gap_disc_desc*` or `struct ble_gap_ext_disc_desc*`, depending on configuration). + +* **Connecting to the Advertiser**: The function uses `ble_gap_connect` to establish the connection with the advertiser device. It provides the Central's own address type, the advertiser's address, and sets a timeout of 30 seconds (30000 ms) for the connection attempt. Additionally, it designates the `blecent_gap_event` function as the event callback to manage connection-related events. + +* **Error Handling**: If the connection attempt fails (`rc != 0`), the function logs an error message with details about the failed connection attempt and returns. + + +## blecent_on_disc_complete + +```c +/** + * Called when service discovery of the specified peer has completed. + */ +static void +blecent_on_disc_complete(const struct peer *peer, int status, void *arg) +{ + + if (status != 0) { + /* Service discovery failed. Terminate the connection. */ + MODLOG_DFLT(ERROR, "Error: Service discovery failed; status=%d " + "conn_handle=%d\n", status, peer->conn_handle); + ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); + return; + } + + /* Service discovery has completed successfully. Now we have a complete + * list of services, characteristics, and descriptors that the peer + * supports. + */ + MODLOG_DFLT(INFO, "Service discovery complete; status=%d " + "conn_handle=%d\n", status, peer->conn_handle); + + /* Now perform three GATT procedures against the peer: read, + * write, and subscribe to notifications for the ANS service. + */ + blecent_read_write_subscribe(peer); +} +``` + +The function `blecent_on_disc_complete` is essential for managing service discovery completion and GATT procedures. It's invoked after service discovery on a peer device concludes. The function takes three arguments: a pointer to the `peer` structure (containing peer information), an integer `status` indicating success or failure, and a generic `arg` pointer for potential extra data (not used here). + +* **Handling Discovery Status**: Upon initiation, the function checks the `status` of the service discovery operation. Non-zero status indicates failure. In such cases, an error message is logged using `MODLOG_DFLT(ERROR, ...)` and the connection with the peer is terminated via `ble_gap_terminate()`, assigning the error reason code `BLE_ERR_REM_USER_CONN_TERM`. This ensures a proper connection termination due to the unsuccessful service discovery. + +* **Success Path**: For a status of zero, denoting successful service discovery, a log message is generated, signifying the completion of service discovery. It includes the `status` and the peer's connection handle (`conn_handle`). + +* **GATT Procedures**: Upon successful service discovery, the function proceeds with three GATT (Generic Attribute Profile) procedures performed on the peer. These encompass reading, writing, and subscribing to notifications for the Alert Notification Service (ANS). These specific GATT actions are typically implemented within the `blecent_read_write_subscribe()` function. + + +## blecent_read_write_subscribe + +```c +/** + * Performs three GATT operations against the specified peer: + * 1. Reads the ANS Supported New Alert Category characteristic. + * 2. After read is completed, writes the ANS Alert Notification Control Point characteristic. + * 3. After write is completed, subscribes to notifications for the ANS Unread Alert Status + * characteristic. + * + * If the peer does not support a required service, characteristic, or + * descriptor, then the peer lied when it claimed support for the alert + * notification service! When this happens, or if a GATT procedure fails, + * this function immediately terminates the connection. + */ +static void +blecent_read_write_subscribe(const struct peer *peer) +{ + const struct peer_chr *chr; + int rc; + + /* Read the supported-new-alert-category characteristic. */ + chr = peer_chr_find_uuid(peer, + BLE_UUID16_DECLARE(BLECENT_SVC_ALERT_UUID), + BLE_UUID16_DECLARE(BLECENT_CHR_SUP_NEW_ALERT_CAT_UUID)); + if (chr == NULL) { + MODLOG_DFLT(ERROR, "Error: Peer doesn't support the Supported New " + "Alert Category characteristic\n"); + goto err; + } + + rc = ble_gattc_read(peer->conn_handle, chr->chr.val_handle, + blecent_on_read, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error: Failed to read characteristic; rc=%d\n", + rc); + goto err; + } + + return; +err: + /* Terminate the connection. */ + ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); +} +``` + +This function executes the following sequence of actions: + +* **Reading Supported New Alert Category Characteristic:** It initiates by attempting to read the *"Supported New Alert Category"* characteristic within the *"Alert Notification Service"* (ANS). To accomplish this, it employs the `peer_chr_find_uuid` function, which searches for the specified characteristic using its UUID. If the characteristic isn't located within the peer's attributes, the function logs an error message and discontinues the connection. + +* **Carrying Out Characteristic Read**: If the *"Supported New Alert Category"* characteristic is successfully identified, the function endeavors to read its value utilizing the `ble_gattc_read` function. In the event of a failed read operation, an error is logged, and the connection is terminated. + + +## blecent_on_custom_read + +```c +/** + * Application Callback. Called when the custom subscribable chatacteristic + * in the remote GATT server is read. + * Expect to get the recently written data. + **/ +static int +blecent_on_custom_read(uint16_t conn_handle, + const struct ble_gatt_error *error, + struct ble_gatt_attr *attr, + void *arg) +{ + MODLOG_DFLT(INFO, + "Read complete for the subscribable characteristic; " + "status=%d conn_handle=%d", error->status, conn_handle); + if (error->status == 0) { + MODLOG_DFLT(INFO, " attr_handle=%d value=", attr->handle); + print_mbuf(attr->om); + } + MODLOG_DFLT(INFO, "\n"); + + return 0; +} +``` + +`blecent_on_custom_read` function is triggered when data is read from a custom subscribable characteristic in a distant Generic Attribute Profile (GATT) server. + +* **Function Definition**: The callback function `blecent_on_custom_read` is defined with specific parameters. These parameters are supplied by the BLE stack when the callback is invoked: + - `uint16_t conn_handle`: The BLE connection handle associated with the read operation. + - `const struct ble_gatt_error *error`: A pointer to a structure that holds error information, if any, during the read. + - `struct ble_gatt_attr *attr`: A pointer to the read attribute, encompassing its handle and data. + - `void *arg`: An optional argument that can be included when registering the callback (not used in this example). + +* **Logging Usage**: The function utilizes the `MODLOG_DFLT` macro to log insights regarding the read operation. This includes details such as the connection handle, operation status (via `error->status`), and attribute handle (via `attr->handle`). + +* **Successful Read Check**: The code assesses the read operation's success by inspecting the status stored in `error->status`. A status of `0` indicates a successful read with no errors. + +* **Value Logging**: If the read operation succeeds, the function logs the attribute's value. This is achieved by employing the `print_mbuf` function, which prints the content of `attr->om` (mbuf) data, representing the read attribute's value. + + +## blecent_on_custom_write + +```c +/** + * Application Callback. Called when the custom subscribable characteristic + * in the remote GATT server is written to. + * Client has previously subscribed to this characeteristic, + * so expect a notification from the server. + **/ +static int +blecent_on_custom_write(uint16_t conn_handle, + const struct ble_gatt_error *error, + struct ble_gatt_attr *attr, + void *arg) +{ + const struct peer_chr *chr; + const struct peer *peer; + int rc; + + MODLOG_DFLT(INFO, + "Write to the custom subscribable characteristic complete; " + "status=%d conn_handle=%d attr_handle=%d\n", + error->status, conn_handle, attr->handle); + + peer = peer_find(conn_handle); + chr = peer_chr_find_uuid(peer, + remote_svc_uuid, + remote_chr_uuid); + if (chr == NULL) { + MODLOG_DFLT(ERROR, + "Error: Peer doesn't have the custom subscribable characteristic\n"); + goto err; + } + + /*** Performs a read on the characteristic, the result is handled in blecent_on_new_read callback ***/ + rc = ble_gattc_read(conn_handle, chr->chr.val_handle, + blecent_on_custom_read, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, + "Error: Failed to read the custom subscribable characteristic; " + "rc=%d\n", rc); + goto err; + } + + return 0; +err: + /* Terminate the connection */ + return ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); +} +``` + +`blecent_on_custom_write` function is invoked when a remote GATT server's (Generic Attribute Profile) custom subscribable characteristic is successfully written to by the Central device. + +* **Parameters**: + - `conn_handle`: BLE connection handle where the write operation took place. + - `error`: Contains write operation details, including the status code. + - `attr`: Represents the written attribute (characteristic). + - `arg`: Optional user-defined argument (unused here). + +* **Logging**: + This function logs write operation completion, displaying write status, connection handle, and attribute handle. + +* **Locating Peer and Characteristic**: + - The function seeks the relevant `peer` using the connection handle through `peer_find`. + - It also searches for a `chr` (characteristic) within the peer's attributes using `remote_svc_uuid` and `remote_chr_uuid`. + - If the characteristic isn't found, an error message is logged, and the function proceeds to the error handling section. + +* **Initiating Characteristic Read**: + - Upon locating the characteristic, the function begins a read operation using `ble_gattc_read`. + - It supplies connection handle, characteristic's value handle (`chr->chr.val_handle`), read handler (`blecent_on_custom_read`), and no user-defined argument (`NULL`). + +* **Error Handling**: + - If the read operation faces an issue (non-zero return value), an error message is logged. + - The function then navigates to the error handling section (`err`), ending the BLE connection with the remote device via `ble_gap_terminate`. + - The termination rationale is marked as `BLE_ERR_REM_USER_CONN_TERM`. + +* **Return Value**: + - Successful write and subsequent read return `0`. + - Write or read errors lead to connection termination, with the result of `ble_gap_terminate`. + + +## blecent_on_custom_subscribe + +```c +/** + * Application Callback. Called when the custom subscribable characteristic + * is subscribed to. + **/ +static int +blecent_on_custom_subscribe(uint16_t conn_handle, + const struct ble_gatt_error *error, + struct ble_gatt_attr *attr, + void *arg) +{ + const struct peer_chr *chr; + uint8_t value; + int rc; + const struct peer *peer; + + MODLOG_DFLT(INFO, + "Subscribe to the custom subscribable characteristic complete; " + "status=%d conn_handle=%d", error->status, conn_handle); + + if (error->status == 0) { + MODLOG_DFLT(INFO, " attr_handle=%d value=", attr->handle); + print_mbuf(attr->om); + } + MODLOG_DFLT(INFO, "\n"); + + peer = peer_find(conn_handle); + chr = peer_chr_find_uuid(peer, + remote_svc_uuid, + remote_chr_uuid); + if (chr == NULL) { + MODLOG_DFLT(ERROR, "Error: Peer doesn't have the subscribable characteristic\n"); + goto err; + } + + /* Write 1 byte to the new characteristic to test if it notifies after subscribing */ + value = 0x19; + rc = ble_gattc_write_flat(conn_handle, chr->chr.val_handle, + &value, sizeof(value), blecent_on_custom_write, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, + "Error: Failed to write to the subscribable characteristic; " + "rc=%d\n", rc); + goto err; + } + + return 0; +err: + /* Terminate the connection */ + return ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); +} +``` + +`blecent_on_custom_subscribe` function is triggered when a custom subscribable characteristic is subscribed to. Here's a concise breakdown of the code's key aspects: + +* **Function and Parameters**: The function receives parameters including the connection handle `conn_handle`, an error structure `error` for status details, a GATT attribute structure `attr` representing the subscribed attribute, and a generic argument `arg`. + +* **Subscription Log**: Information about the subscription process is logged, including the subscription status, connection handle, and attribute handle. If the subscription is successful (`error->status == 0`), the subscribed attribute's value is printed using the `print_mbuf` function. + +* **Peer and Characteristic Search**: The function searches for a peer structure using `conn_handle` and attempts to locate a specific characteristic within that peer. The desired characteristic is identified by `remote_svc_uuid` and `remote_chr_uuid`. + +* **Characteristic Validation**: If the characteristic isn't found within the peer, an error message is logged to indicate the absence of the expected subscribable characteristic. + +* **Characteristic Write**: Assuming the characteristic is found, the function tries to write a single byte (0x19) to it. This test is performed to determine if the characteristic will notify the Central device after subscribing. The `ble_gattc_write_flat` function handles this operation. + +* **Write Outcome Check**: In case the write operation fails (`rc != 0`), an error message is logged to indicate the failure in writing to the subscribable characteristic. + +* **Return Value**: The function returns `0` to signal the completion of processing. In case of errors, connection termination is initiated within the error-handling segments. + + +## blecent_custom_gatt_operations +```c +/** + * Performs 3 operations on the remote GATT server. + * 1. Subscribes to a characteristic by writing 0x10 to it's CCCD. + * 2. Writes to the characteristic and expect a notification from remote. + * 3. Reads the characteristic and expect to get the recently written information. + **/ +static void +blecent_custom_gatt_operations(const struct peer* peer) +{ + const struct peer_dsc *dsc; + int rc; + uint8_t value[2]; + + dsc = peer_dsc_find_uuid(peer, + remote_svc_uuid, + remote_chr_uuid, + BLE_UUID16_DECLARE(BLE_GATT_DSC_CLT_CFG_UUID16)); + if (dsc == NULL) { + MODLOG_DFLT(ERROR, "Error: Peer lacks a CCCD for the subscribable characteristic\n"); + goto err; + } + + /*** Write 0x00 and 0x01 (The subscription code) to the CCCD ***/ + value[0] = 1; + value[1] = 0; + rc = ble_gattc_write_flat(peer->conn_handle, dsc->dsc.handle, + value, sizeof(value), blecent_on_custom_subscribe, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, + "Error: Failed to subscribe to the subscribable characteristic; " + "rc=%d\n", rc); + goto err; + } + + return; +err: + /* Terminate the connection */ + ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); +} +``` + +`blecent_custom_gatt_operations` function demonstrates various GATT interactions, including subscribing to a characteristic, writing to it, and reading from it. + +* **Finding CCCD Descriptor**: The function begins by searching for a specific Client Characteristic Configuration Descriptor (CCCD) associated with a subscribable characteristic. This search employs the `peer_dsc_find_uuid` function using provided UUIDs. + +* **Checking CCCD Availability**: If the CCCD is not found (`dsc` is `NULL`), an error message is logged, and the connection is terminated. + +* **Subscribing to Characteristic**: The function assembles a two-byte value array with `value[0]` indicating subscription (set to 1) and `value[1]` set to 0. It utilizes `ble_gattc_write_flat` to write this value to the CCCD, subscribing to characteristic notifications. If the write operation fails (returns non-zero), an error message is logged, and the connection is terminated. + +* **Successful Execution**: If the subscription write succeeds, the function returns without further actions. + +* **Error Handling**: In case of any failures, the code proceeds to the `err` label, terminating the BLE connection using `ble_gap_terminate` with the relevant error code. + + +## blecent_on_subscribe + +```c +/** + * Application callback. Called when the attempt to subscribe to notifications + * for the ANS Unread Alert Status characteristic has completed. + */ +static int +blecent_on_subscribe(uint16_t conn_handle, + const struct ble_gatt_error *error, + struct ble_gatt_attr *attr, + void *arg) +{ + struct peer *peer; + + MODLOG_DFLT(INFO, "Subscribe complete; status=%d conn_handle=%d " + "attr_handle=%d\n", + error->status, conn_handle, attr->handle); + + peer = peer_find(conn_handle); + if (peer == NULL) { + MODLOG_DFLT(ERROR, "Error in finding peer, aborting..."); + ble_gap_terminate(conn_handle, BLE_ERR_REM_USER_CONN_TERM); + } + /* Subscribe to, write to, and read the custom characteristic*/ + blecent_custom_gatt_operations(peer); + + return 0; +} +``` + +`blecent_on_subscribe` function's purpose is to handle the completion of subscribing to notifications for a specific characteristic in a BLE Peripheral device. + +* **Parameters**: + - `conn_handle`: Corresponds to the BLE connection's handle. + - `error`: Points to a `struct ble_gatt_error` indicating the outcome of the subscription attempt. + - `attr`: Points to the GATT attribute linked with the subscribed characteristic. + - `arg`: Represents a user-defined argument passed into the callback. + +* **Logging**: The function logs subscription completion details utilizing `MODLOG_DFLT(INFO, ...)`. It reports subscription status, connection handle, and attribute handle. + +* **Peer Identification**: The function endeavors to locate the associated `peer` (Peripheral device) linked with the provided `conn_handle`. If the peer can't be located, it logs an error message and terminates the BLE connection with the peripheral using `ble_gap_terminate`, coupled with error code `BLE_ERR_REM_USER_CONN_TERM`. + +* **Custom GATT Operations**: Presuming the peer is successfully identified, the code implies the existence of a function named `blecent_custom_gatt_operations`. This function likely performs extra custom GATT (Generic Attribute Profile) operations on the peripheral. Such operations could encompass writing to or reading from custom characteristics or attributes. + + +## blecent_on_write + +```c +/** + * Application callback. Called when the write to the ANS Alert Notification + * Control Point characteristic has completed. + */ +static int +blecent_on_write(uint16_t conn_handle, + const struct ble_gatt_error *error, + struct ble_gatt_attr *attr, + void *arg) +{ + MODLOG_DFLT(INFO, + "Write complete; status=%d conn_handle=%d attr_handle=%d\n", + error->status, conn_handle, attr->handle); + + /* Subscribe to notifications for the Unread Alert Status characteristic. + * A central enables notifications by writing two bytes (1, 0) to the + * characteristic's client-characteristic-configuration-descriptor (CCCD). + */ + const struct peer_dsc *dsc; + uint8_t value[2]; + int rc; + const struct peer *peer = peer_find(conn_handle); + + dsc = peer_dsc_find_uuid(peer, + BLE_UUID16_DECLARE(BLECENT_SVC_ALERT_UUID), + BLE_UUID16_DECLARE(BLECENT_CHR_UNR_ALERT_STAT_UUID), + BLE_UUID16_DECLARE(BLE_GATT_DSC_CLT_CFG_UUID16)); + if (dsc == NULL) { + MODLOG_DFLT(ERROR, "Error: Peer lacks a CCCD for the Unread Alert " + "Status characteristic\n"); + goto err; + } + + value[0] = 1; + value[1] = 0; + rc = ble_gattc_write_flat(conn_handle, dsc->dsc.handle, + value, sizeof value, blecent_on_subscribe, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error: Failed to subscribe to characteristic; " + "rc=%d\n", rc); + goto err; + } + + return 0; +err: + /* Terminate the connection. */ + return ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); +} +``` + +This function gets triggered upon the completion of a write operation to the ANS (Alert Notification Service) Alert Notification Control Point characteristic. Here's a breakdown of the code's components: + +* **Subscription to Notifications**: The primary objective of the function is to subscribe to notifications for the Unread Alert Status characteristic. Notifications are enabled by writing two bytes (1, 0) to the Client Characteristic Configuration Descriptor (CCCD) of the characteristic. + +* **Locating CCCD Descriptor**: The `peer_dsc_find_uuid` function is employed to find the CCCD descriptor associated with the Unread Alert Status characteristic. This entails locating a specific descriptor with a particular UUID linked to CCCD. In case the descriptor isn't found, an error message is logged, and the code proceeds to the `err` label. + +* **Preparing Subscription Value**: The code prepares the subscription value as an array of two bytes: [1, 0]. This value's purpose is to enable notifications for the characteristic. + +* **Initiating Write Operation**: The function then uses `ble_gattc_write_flat` to execute a flat write operation. It writes the subscription value to the CCCD descriptor's handle. The `blecent_on_subscribe` callback function is designated to manage the completion of the subscription write operation. + +* **Error Handling for Write**: If the write operation encounters a failure (as indicated by a non-zero return value from `ble_gattc_write_flat`), an error message is logged, and the code proceeds to the `err` label. + + +## blecent_on_read + +```c +/** + * Application callback. Called when the read of the ANS Supported New Alert + * Category characteristic has completed. + */ +static int +blecent_on_read(uint16_t conn_handle, + const struct ble_gatt_error *error, + struct ble_gatt_attr *attr, + void *arg) +{ + MODLOG_DFLT(INFO, "Read complete; status=%d conn_handle=%d", error->status, + conn_handle); + if (error->status == 0) { + MODLOG_DFLT(INFO, " attr_handle=%d value=", attr->handle); + print_mbuf(attr->om); + } + MODLOG_DFLT(INFO, "\n"); + + /* Write two bytes (99, 100) to the alert-notification-control-point + * characteristic. + */ + const struct peer_chr *chr; + uint8_t value[2]; + int rc; + const struct peer *peer = peer_find(conn_handle); + + chr = peer_chr_find_uuid(peer, + BLE_UUID16_DECLARE(BLECENT_SVC_ALERT_UUID), + BLE_UUID16_DECLARE(BLECENT_CHR_ALERT_NOT_CTRL_PT)); + if (chr == NULL) { + MODLOG_DFLT(ERROR, "Error: Peer doesn't support the Alert " + "Notification Control Point characteristic\n"); + goto err; + } + + value[0] = 99; + value[1] = 100; + rc = ble_gattc_write_flat(conn_handle, chr->chr.val_handle, + value, sizeof value, blecent_on_write, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error: Failed to write characteristic; rc=%d\n", + rc); + goto err; + } + + return 0; +err: + /* Terminate the connection. */ + return ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); +} +``` + +The `blecent_on_read` function is called when a read operation for a certain characteristic is completed. + +* **Logging Read Status**: The function logs information regarding the read operation, including its status and the connection handle. If the read operation is successful (status equals `0`), it also logs the attribute handle and the value read from the characteristic using the `print_mbuf` function. + +* **Writing to a Characteristic**: The code proceeds to write two bytes (`99` and `100`) to the Alert Notification Control Point characteristic. It locates the characteristic using `peer_chr_find_uuid` based on its UUID values. If the characteristic is not found (i.e., `chr` is `NULL`), it logs an error message and proceeds to the `err` label. + +* **Write Operation**: When the Alert Notification Control Point characteristic is found, the code prepares the data to be written (an array called `value` containing two bytes) and employs `ble_gattc_write_flat` to execute the write operation. The completion of the write operation triggers the `blecent_on_write` callback function. If the write operation encounters an error (return code `rc` is non-zero), the code logs an error message and proceeds to the `err` label. + +* **Handling Errors**: If an error occurs (such as not finding the characteristic or a failed write operation), the code terminates the connection using `ble_gap_terminate` with the reason code `BLE_ERR_REM_USER_CONN_TERM`. + +In essence, this callback function handles reading a characteristic's value, logs the result, and potentially performs a subsequent write operation to another characteristic. + + +## Conclusion + +In this example code, we've explored how to initiate BLE scanning, discover nearby Peripheral devices, establish connections, and interact with their services and characteristics. + +**Key Takeaways**: + +- **Initialization**: The code initializes the BLE stack and sets up event handlers. +- **Scanning**: The Central device scans for nearby BLE Peripheral devices and filters interesting devices based on criteria like service UUIDs or peer addresses. +- **Connection Management**: When a suitable Peripheral is found, the Central initiates a connection and handles connection events. +- **Service Discovery**: After connection, the Central performs service discovery to identify the services and characteristics supported by the Peripheral. +- **GATT Procedures**: The code showcases read, write, and subscription procedures with the discovered services and characteristics. +- **Error Handling**: Proper error handling ensures termination of connections in case of failures. diff --git a/examples/bluetooth/nimble/ble_chan_sound_reflector/CMakeLists.txt b/examples/bluetooth/nimble/ble_chan_sound_reflector/CMakeLists.txt new file mode 100644 index 000000000000..3b7c5faa2956 --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_reflector/CMakeLists.txt @@ -0,0 +1,8 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +# "Trim" the build. Include the minimal set of components, main, and anything it depends on. +idf_build_set_property(MINIMAL_BUILD ON) +project(ble_chan_sound_reflector) diff --git a/examples/bluetooth/nimble/ble_chan_sound_reflector/README.md b/examples/bluetooth/nimble/ble_chan_sound_reflector/README.md new file mode 100644 index 000000000000..6ff5843a187b --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_reflector/README.md @@ -0,0 +1,66 @@ +| Supported Targets | ESP32-C6 | +| ----------------- | -------- | + +# BLE Channel Sounding reflector Example + +(See the README.md file in the upper-level 'examples' directory for more information about examples.) +* This example demonstrates the capability of the CS procedure to be executed on the ESP host + external controller. +* It is important to note that the current example does not provide support for distance calculation, and it is currently under development. +* Ble channel sounding reflector example uses the RAS service defined in [ble_svc_ras.c](../../../../components/bt/host/nimble/nimble/nimble/host/services/ras/src/ble_svc_ras.c) + +I (372) hal_uart: set baud_rate:115200. + +I (382) NimBLE_RAS_INITIATOR: BLE Host Task Started +I (382) main_task: Returned from app_main() + +I (157562) NimBLE: GAP procedure initiated: extended advertise; instance=0 + +I (157562) NimBLE: Connection secured +I (162222) NimBLE: encryption change event; status=0 + +I (162372) NimBLE: CS capabilities exchanged +I (162372) NimBLE: Set default CS settings + +I (162392) NimBLE: Setup phase completed + +To test this demo, any BLE channel sounding initiator app can be used. + +## Note + +* This example currently requires an external Bluetooth controller supporting BLE Channel sounding functionality, as the ESP chips listed above do not have native controller support for BLE channel sounding feature and is under development phase + +* To install the dependency packages needed, please refer to the top level [README file](../../../README.md#running-test-python-script-pytest). + +## How to Use Example + +Before project configuration and build, be sure to set the correct chip target using: + +```bash +idf.py set-target +``` + +### Configure the project + +Open the project configuration menu: + +```bash +idf.py menuconfig +``` + +In the `Example Configuration` menu: + +* Select I/O capabilities of device from `Example Configuration --> I/O Capability`, default is `Just_works`. +* Enable/Disable other security related parameters `Bonding, MITM option, secure connection(SM SC)`. + +### Build and Flash + +Run `idf.py -p PORT flash monitor` to build, flash and monitor the project. + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the [Getting Started Guide](https://idf.espressif.com/) for full steps to configure and use ESP-IDF to build projects. + + +## Troubleshooting + +For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. diff --git a/examples/bluetooth/nimble/ble_chan_sound_reflector/main/CMakeLists.txt b/examples/bluetooth/nimble/ble_chan_sound_reflector/main/CMakeLists.txt new file mode 100644 index 000000000000..9e539a9fc046 --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_reflector/main/CMakeLists.txt @@ -0,0 +1,5 @@ +set(srcs "main.c" + "gatt_svr.c") + +idf_component_register(SRCS "${srcs}" + INCLUDE_DIRS ".") diff --git a/examples/bluetooth/nimble/ble_chan_sound_reflector/main/Kconfig.projbuild b/examples/bluetooth/nimble/ble_chan_sound_reflector/main/Kconfig.projbuild new file mode 100644 index 000000000000..0de1a5a66fa4 --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_reflector/main/Kconfig.projbuild @@ -0,0 +1,14 @@ +menu "Example Configuration" + + + config EXAMPLE_EXTENDED_ADV + bool + depends on SOC_BLE_50_SUPPORTED && BT_NIMBLE_50_FEATURE_SUPPORT + default y + select BT_NIMBLE_EXT_ADV + prompt "Enable Extended Adv" + help + Use this option to enable extended advertising in the example. + If this option is disabled, ensure config BT_NIMBLE_EXT_ADV is + also disabled from Nimble stack menuconfig +endmenu diff --git a/examples/bluetooth/nimble/ble_chan_sound_reflector/main/ble_chan_reflector.h b/examples/bluetooth/nimble/ble_chan_sound_reflector/main/ble_chan_reflector.h new file mode 100644 index 000000000000..3d9ccdbd857c --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_reflector/main/ble_chan_reflector.h @@ -0,0 +1,69 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef H_BLE_CHAN_REFLECTOR_ +#define H_BLE_CHAN_REFLECTOR_ + +#include +#include "nimble/ble.h" +#include "modlog/modlog.h" +#include "esp_peripheral.h" +#ifdef __cplusplus +extern "C" { +#endif + + +#define BLE_HCI_LE_CS_SUBEVENT_DONE_STATUS_COMPLETE 0x0 +#define BLE_HCI_LE_CS_SUBEVENT_DONE_STATUS_PARTIAL 0x1 +#define BLE_HCI_LE_CS_SUBEVENT_DONE_STATUS_ABORTED 0xF + +#define LOCAL_PROCEDURE_MEM 1024 // Replace with an appropriate constant value +struct ble_hs_cfg; +struct ble_gatt_register_ctxt; + +/** GATT server. */ + +#define BLE_UUID_RANGING_SERVICE_VAL (0x185B) + +/** @brief UUID of the RAS Features Characteristic. **/ +#define BLE_UUID_RAS_FEATURES_VAL (0x2C14) + +/** @brief UUID of the Real-time Ranging Data Characteristic. **/ +#define BLE_UUID_RAS_REALTIME_RD_VAL (0x2C15) + +/** @brief UUID of the On-demand Ranging Data Characteristic. **/ +#define BLE_UUID_RAS_ONDEMAND_RD_VAL (0x2C16) + +/** @brief UUID of the RAS Control Point Characteristic. **/ +#define BLE_UUID_RAS_CP_VAL (0x2C17) + +/** @brief UUID of the Ranging Data Ready Characteristic. **/ +#define BLE_UUID_RAS_RD_READY_VAL (0x2C18) + +/** @brief UUID of the Ranging Data Overwritten Characteristic. **/ +#define BLE_UUID_RAS_RD_OVERWRITTEN_VAL (0x2C19) + +void custom_gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg); +int custom_gatt_svr_init(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/bluetooth/nimble/ble_chan_sound_reflector/main/gatt_svr.c b/examples/bluetooth/nimble/ble_chan_sound_reflector/main/gatt_svr.c new file mode 100644 index 000000000000..f0829469ec7f --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_reflector/main/gatt_svr.c @@ -0,0 +1,33 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "services/gap/ble_svc_gap.h" +#include "services/gatt/ble_svc_gatt.h" +#include "services/ans/ble_svc_ans.h" +#include "services/ras/ble_svc_ras.h" + +int +custom_gatt_svr_init(void) +{ + ble_svc_gap_init(); + ble_svc_gatt_init(); + ble_svc_ras_init(); + + return 0; +} diff --git a/examples/bluetooth/nimble/ble_chan_sound_reflector/main/idf_component.yml b/examples/bluetooth/nimble/ble_chan_sound_reflector/main/idf_component.yml new file mode 100644 index 000000000000..d6e735fe7706 --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_reflector/main/idf_component.yml @@ -0,0 +1,3 @@ +dependencies: + nimble_peripheral_utils: + path: ${IDF_PATH}/examples/bluetooth/nimble/common/nimble_peripheral_utils diff --git a/examples/bluetooth/nimble/ble_chan_sound_reflector/main/main.c b/examples/bluetooth/nimble/ble_chan_sound_reflector/main/main.c new file mode 100644 index 000000000000..5ad76841a9de --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_reflector/main/main.c @@ -0,0 +1,498 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "esp_log.h" +#include "nvs_flash.h" +/* BLE */ +#include "nimble/nimble_port.h" +#include "nimble/nimble_port_freertos.h" +#include "host/ble_hs.h" +#include "host/util/util.h" +#include "console/console.h" +#include "services/gap/ble_svc_gap.h" +#include "services/ras/ble_svc_ras.h" +#include "ble_chan_reflector.h" +#include "host/ble_cs.h" + +#if CONFIG_EXAMPLE_EXTENDED_ADV +static uint8_t ext_adv_pattern_1[] = { + 0x02, 0x01, 0x06, + 0x03, 0x03, 0xab, 0xcd, + 0x03, 0x03, 0x5B, 0x18, + 0x11, 0X09, 'n', 'i', 'm', 'b', 'l', 'e', '-', 'b', 'l', 'e', 'p', 'r', 'p', 'h', '-', 'e', +}; +#endif +static const char *tag = "NimBLE_BLE_CHAN_REFLECTOR"; +static int bleprph_gap_event(struct ble_gap_event *event, void *arg); +void ble_store_config_init(void); + +struct ble_cs_event ranging_subevent; +static int32_t most_recent_local_ranging_counter= -1 ; + +static int ind; +static int idx; + +void print_cs_event(const struct ble_cs_event *event) +{ + MODLOG_DFLT(INFO, "ble_cs_event.type = %u\n", event->type); + + switch (event->type) { + case BLE_CS_EVENT_CS_PROCEDURE_COMPLETE: + MODLOG_DFLT(INFO, "procedure_complete.conn_handle = %u\n", event->procedure_complete.conn_handle); + MODLOG_DFLT(INFO, "procedure_complete.status = %u\n", event->procedure_complete.status); + break; + case BLE_CS_EVENT_SUBEVET_RESULT: + MODLOG_DFLT(INFO, "subev_result.conn_handle = %u\n", event->subev_result.conn_handle); + MODLOG_DFLT(INFO, "subev_result.config_id = %u\n", event->subev_result.config_id); + MODLOG_DFLT(INFO, "subev_result.start_acl_conn_event_counter = %u\n", event->subev_result.start_acl_conn_event_counter); + MODLOG_DFLT(INFO, "subev_result.procedure_counter = %u\n", event->subev_result.procedure_counter); + MODLOG_DFLT(INFO, "subev_result.frequency_compensation = %u\n", event->subev_result.frequency_compensation); + MODLOG_DFLT(INFO, "subev_result.reference_power_level = %u\n", event->subev_result.reference_power_level); + MODLOG_DFLT(INFO, "subev_result.procedure_done_status = %u\n", event->subev_result.procedure_done_status); + MODLOG_DFLT(INFO, "subev_result.subevent_done_status = %u\n", event->subev_result.subevent_done_status); + MODLOG_DFLT(INFO, "subev_result.abort_reason = %u\n", event->subev_result.abort_reason); + MODLOG_DFLT(INFO, "subev_result.num_antenna_paths = %u\n", event->subev_result.num_antenna_paths); + MODLOG_DFLT(INFO, "subev_result.num_steps_reported = %u\n", event->subev_result.num_steps_reported); + + for (int i = 0; i < event->subev_result.num_steps_reported; i++) { + const struct cs_steps_data *step = &event->subev_result.steps[i]; + MODLOG_DFLT(INFO, "steps[%d]: mode=%u, channel=%u, data_len=%u, data=", i, step->mode, step->channel, step->data_len); + for (int j = 0; j < step->data_len; j++) { + esp_rom_printf("%02x ", step->data[j]); + } + esp_rom_printf("\n"); + } + break; + case BLE_CS_EVENT_SUBEVET_RESULT_CONTINUE: + MODLOG_DFLT(INFO, "subev_result_continue.conn_handle = %u\n", event->subev_result_continue.conn_handle); + MODLOG_DFLT(INFO, "subev_result_continue.config_id = %u\n", event->subev_result_continue.config_id); + MODLOG_DFLT(INFO, "subev_result_continue.procedure_done_status = %u\n", event->subev_result_continue.procedure_done_status); + MODLOG_DFLT(INFO, "subev_result_continue.subevent_done_status = %u\n", event->subev_result_continue.subevent_done_status); + MODLOG_DFLT(INFO, "subev_result_continue.abort_reason = %u\n", event->subev_result_continue.abort_reason); + MODLOG_DFLT(INFO, "subev_result_continue.num_antenna_paths = %u\n", event->subev_result_continue.num_antenna_paths); + MODLOG_DFLT(INFO, "subev_result_continue.num_steps_reported = %u\n", event->subev_result_continue.num_steps_reported); + + for (int i = 0; i < event->subev_result_continue.num_steps_reported; i++) { + const struct cs_steps_data *step = &event->subev_result_continue.steps[i]; + MODLOG_DFLT(INFO, "steps[%d]: mode=%u, channel=%u, data_len=%u, data=", i, step->mode, step->channel, step->data_len); + for (int j = 0; j < step->data_len; j++) { + esp_rom_printf("%02x ", step->data[j]); + } + esp_rom_printf("\n"); + } + + break; + default: + MODLOG_DFLT(INFO, "Unknown event type\n"); + break; + } +} + +static int blecs_gap_event(struct ble_cs_event *event, void *arg) +{ + switch(event->type){ + + case BLE_CS_EVENT_SUBEVET_RESULT: + MODLOG_DFLT(INFO, "LE CS Subevent Result ,procedure counter: %d\n", event->subev_result.procedure_counter); + + if (event->subev_result.procedure_done_status == BLE_HCI_LE_CS_SUBEVENT_DONE_STATUS_COMPLETE) { + MODLOG_DFLT(INFO, "LE CS Subevent Result , status: Complete, procedure counter %d\n", event->subev_result.procedure_counter); + most_recent_local_ranging_counter=event->subev_result.procedure_counter; + + } else if(event->subev_result.procedure_done_status == BLE_HCI_LE_CS_SUBEVENT_DONE_STATUS_PARTIAL) { + ranging_subevent.type=BLE_CS_EVENT_SUBEVET_RESULT; + ranging_subevent.subev_result= event->subev_result; + idx++; + if (idx==1) { + most_recent_local_ranging_counter=event->subev_result.procedure_counter; + } + MODLOG_DFLT(INFO, "LE CS Subevent Result , status: Partial, procedure counter %d\n", event->subev_result.procedure_counter); + } else { + MODLOG_DFLT(INFO, "LE CS Subevent Result , status: Unknown\n"); + } + break; + + case BLE_CS_EVENT_SUBEVET_RESULT_CONTINUE: + if( event->subev_result_continue.procedure_done_status == BLE_HCI_LE_CS_SUBEVENT_DONE_STATUS_ABORTED) { + MODLOG_DFLT(INFO, "LE CS Subevent Result Continue , status: Aborted\n"); + } else if ( event->subev_result_continue.procedure_done_status == BLE_HCI_LE_CS_SUBEVENT_DONE_STATUS_COMPLETE) { + MODLOG_DFLT(INFO, "LE CS Subevent Result Continue , status: Complete\n"); + ranging_subevent.subev_result_continue = event->subev_result_continue; + /* To + * Get total number of CS procedure from CS enable event and then accordigly indicate to most recent ranging counter + Currently we are considering only one CS procedure + */ + ind ++; + if (ind==1) { + ble_gatts_store_ranging_data(ranging_subevent); + ble_gatts_indicate_ranging_data_ready(most_recent_local_ranging_counter); + } + } + + break; + default: + return 0; + + } + return 0; +} + +static void +bleprph_print_conn_desc(struct ble_gap_conn_desc *desc) +{ + MODLOG_DFLT(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=", + desc->conn_handle, desc->our_ota_addr.type); + print_addr(desc->our_ota_addr.val); + MODLOG_DFLT(INFO, " our_id_addr_type=%d our_id_addr=", + desc->our_id_addr.type); + print_addr(desc->our_id_addr.val); + MODLOG_DFLT(INFO, " peer_ota_addr_type=%d peer_ota_addr=", + desc->peer_ota_addr.type); + print_addr(desc->peer_ota_addr.val); + MODLOG_DFLT(INFO, " peer_id_addr_type=%d peer_id_addr=", + desc->peer_id_addr.type); + print_addr(desc->peer_id_addr.val); + MODLOG_DFLT(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d " + "encrypted=%d authenticated=%d bonded=%d\n", + desc->conn_itvl, desc->conn_latency, + desc->supervision_timeout, + desc->sec_state.encrypted, + desc->sec_state.authenticated, + desc->sec_state.bonded); +} +#if CONFIG_EXAMPLE_EXTENDED_ADV +/** + * Enables advertising with the following parameters: + * o General discoverable mode. + * o Undirected connectable mode. + */ +static void +ext_bleprph_advertise(void) +{ + struct ble_gap_ext_adv_params params; + struct os_mbuf *data; + uint8_t instance = 0; + int rc; + /* First check if any instance is already active */ + if(ble_gap_ext_adv_active(instance)) { + return; + } + /* use defaults for non-set params */ + memset (¶ms, 0, sizeof(params)); + /* enable connectable advertising */ + params.connectable = 1; + /* advertise using random addr */ + params.own_addr_type = BLE_OWN_ADDR_PUBLIC; + params.primary_phy = BLE_HCI_LE_PHY_1M; + params.secondary_phy = BLE_HCI_LE_PHY_2M; + params.sid = 1; + params.itvl_min = BLE_GAP_ADV_FAST_INTERVAL1_MIN; + params.itvl_max = BLE_GAP_ADV_FAST_INTERVAL1_MIN; + /* configure instance 0 */ + rc = ble_gap_ext_adv_configure(instance, ¶ms, NULL, + bleprph_gap_event, NULL); + assert (rc == 0); + /* in this case only scan response is allowed */ + + /* get mbuf for scan rsp data */ + data = os_msys_get_pkthdr(sizeof(ext_adv_pattern_1), 0); + assert(data); + + /* fill mbuf with scan rsp data */ + rc = os_mbuf_append(data, ext_adv_pattern_1, sizeof(ext_adv_pattern_1)); + assert(rc == 0); + + rc = ble_gap_ext_adv_set_data(instance, data); + assert (rc == 0); + + /* start advertising */ + rc = ble_gap_ext_adv_start(instance, 0, 0); +} +#else +/** + * Enables advertising with the following parameters: + * o General discoverable mode. + * o Undirected connectable mode. + */ +static void +bleprph_advertise(void) +{ + struct ble_gap_adv_params adv_params; + struct ble_hs_adv_fields fields; + const char *name; + int rc; + /** + * Set the advertisement data included in our advertisements: + * o Flags (indicates advertisement type and other general info). + * o Advertising tx power. + * o Device name. + * o 16-bit service UUIDs (alert notifications). + */ + memset(&fields, 0, sizeof fields); + /* Advertise two flags: + * o Discoverability in forthcoming advertisement (general) + * o BLE-only (BR/EDR unsupported). + */ + fields.flags = BLE_HS_ADV_F_DISC_GEN | + BLE_HS_ADV_F_BREDR_UNSUP; + /* Indicate that the TX power level field should be included; have the + * stack fill this value automatically. This is done by assigning the + * special value BLE_HS_ADV_TX_PWR_LVL_AUTO. + */ + fields.tx_pwr_lvl_is_present = 1; + fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO; + name = ble_svc_gap_device_name(); + fields.name = (uint8_t *)name; + fields.name_len = strlen(name); + fields.name_is_complete = 1; + fields.uuids16 = (ble_uuid16_t[]) { + BLE_UUID16_INIT(BLE_UUID_RANGING_SERVICE_VAL) + }; + fields.num_uuids16 = 1; + fields.uuids16_is_complete = 1; + rc = ble_gap_adv_set_fields(&fields); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error setting advertisement data; rc=%d\n", rc); + return; + } + /* Begin advertising. */ + memset(&adv_params, 0, sizeof adv_params); + adv_params.conn_mode = BLE_GAP_CONN_MODE_UND; + adv_params.disc_mode = BLE_GAP_DISC_MODE_GEN; + rc = ble_gap_adv_start(0, NULL, BLE_HS_FOREVER, + &adv_params, bleprph_gap_event, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error enabling advertisement; rc=%d\n", rc); + return; + } +} +#endif + +/** + * The nimble host executes this callback when a GAP event occurs. The + * application associates a GAP event callback with each connection that forms. + * bleprph uses the same callback for all connections. + * + * @param event The type of event being signalled. + * @param ctxt Various information pertaining to the event. + * @param arg Application-specified argument; unused by + * bleprph. + * + * @return 0 if the application successfully handled the + * event; nonzero on failure. The semantics + * of the return code is specific to the + * particular GAP event being signalled. + */ +static int +bleprph_gap_event(struct ble_gap_event *event, void *arg) +{ + struct ble_gap_conn_desc desc; + int rc; + switch (event->type) { + case BLE_GAP_EVENT_CONNECT: + /* A new connection was established or a connection attempt failed. */ + MODLOG_DFLT(INFO, "connection %s; status=%d ", + event->connect.status == 0 ? "established" : "failed", + event->connect.status); + if (event->connect.status == 0) { + rc = ble_gap_conn_find(event->connect.conn_handle, &desc); + assert(rc == 0); + bleprph_print_conn_desc(&desc); + } + MODLOG_DFLT(INFO, "\n"); + if (event->connect.status != 0) { + /* Connection failed; resume advertising. */ +#if CONFIG_EXAMPLE_EXTENDED_ADV + ext_bleprph_advertise(); +#else + bleprph_advertise(); +#endif + } + + return 0; + case BLE_GAP_EVENT_DISCONNECT: + MODLOG_DFLT(INFO, "disconnect; reason=%d ", event->disconnect.reason); + bleprph_print_conn_desc(&event->disconnect.conn); + MODLOG_DFLT(INFO, "\n"); + /* Connection terminated; resume advertising. */ +#if CONFIG_EXAMPLE_EXTENDED_ADV + ext_bleprph_advertise(); +#else + bleprph_advertise(); +#endif + return 0; + case BLE_GAP_EVENT_CONN_UPDATE: + /* The central has updated the connection parameters. */ + MODLOG_DFLT(INFO, "connection updated; status=%d ", + event->conn_update.status); + rc = ble_gap_conn_find(event->conn_update.conn_handle, &desc); + assert(rc == 0); + bleprph_print_conn_desc(&desc); + MODLOG_DFLT(INFO, "\n"); + return 0; + case BLE_GAP_EVENT_ADV_COMPLETE: + MODLOG_DFLT(INFO, "advertise complete; reason=%d", + event->adv_complete.reason); +#if CONFIG_EXAMPLE_EXTENDED_ADV + ext_bleprph_advertise(); +#else + bleprph_advertise(); +#endif + return 0; + case BLE_GAP_EVENT_ENC_CHANGE: + /* Encryption has been enabled or disabled for this connection. */ + MODLOG_DFLT(INFO, "encryption change event; status=%d ", + event->enc_change.status); + rc = ble_gap_conn_find(event->enc_change.conn_handle, &desc); + assert(rc == 0); + bleprph_print_conn_desc(&desc); + struct ble_cs_reflector_setup_params params; + params.cb=blecs_gap_event; + ble_cs_reflector_setup(¶ms); + + return 0; + case BLE_GAP_EVENT_NOTIFY_TX: + MODLOG_DFLT(INFO, "notify_tx event; conn_handle=%d attr_handle=%d " + "status=%d is_indication=%d", + event->notify_tx.conn_handle, + event->notify_tx.attr_handle, + event->notify_tx.status, + event->notify_tx.indication); + + if (event->notify_tx.status == BLE_HS_EDONE) { + vTaskDelay(4000 / portTICK_PERIOD_MS); + ble_gatts_indicate_control_point_response(event->notify_tx.attr_handle,most_recent_local_ranging_counter); + } + return 0; + case BLE_GAP_EVENT_SUBSCRIBE: + MODLOG_DFLT(INFO, "subscribe event; conn_handle=%d attr_handle=%d " + "reason=%d prevn=%d curn=%d previ=%d curi=%d\n", + event->subscribe.conn_handle, + event->subscribe.attr_handle, + event->subscribe.reason, + event->subscribe.prev_notify, + event->subscribe.cur_notify, + event->subscribe.prev_indicate, + event->subscribe.cur_indicate); + return 0; + case BLE_GAP_EVENT_MTU: + MODLOG_DFLT(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n", + event->mtu.conn_handle, + event->mtu.channel_id, + event->mtu.value); + return 0; + } + return 0; +} +static void +bleprph_on_reset(int reason) +{ + MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason); +} + +static void +bleprph_on_sync(void) +{ + int rc; + uint8_t own_addr_type = 0; + /* Make sure we have set Host feature bit for Channel Sounding*/ + rc = ble_gap_set_host_feat(47,0x01); + /* Make sure we have proper identity address set (public preferred) */ + rc = ble_hs_util_ensure_addr(0); + + assert(rc == 0); + /* Figure out address to use while advertising (no privacy for now) */ + rc = ble_hs_id_infer_auto(0, &own_addr_type); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error determining address type; rc=%d\n", rc); + return; + } + /* Printing ADDR */ + uint8_t addr_val[6] = {0}; + rc = ble_hs_id_copy_addr(own_addr_type, addr_val, NULL); + MODLOG_DFLT(INFO, "Device Address: "); + print_addr(addr_val); + MODLOG_DFLT(INFO, "\n"); + /* Begin advertising. */ +#if CONFIG_EXAMPLE_EXTENDED_ADV + ext_bleprph_advertise(); +#else + bleprph_advertise(); +#endif +} +void bleprph_host_task(void *param) +{ + ESP_LOGI(tag, "BLE Host Task Started"); + /* This function will return only when nimble_port_stop() is executed */ + nimble_port_run(); + nimble_port_freertos_deinit(); +} +void +app_main(void) +{ + int rc; + /* Initialize NVS — it is used to store PHY calibration data */ + esp_err_t ret = nvs_flash_init(); + if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_ERROR_CHECK(nvs_flash_erase()); + ret = nvs_flash_init(); + } + ESP_ERROR_CHECK(ret); + ret = nimble_port_init(); + if (ret != ESP_OK) { + ESP_LOGE(tag, "Failed to init nimble %d ", ret); + return; + } + /* Initialize the NimBLE host configuration. */ + ble_hs_cfg.reset_cb = bleprph_on_reset; + ble_hs_cfg.sync_cb = bleprph_on_sync; + ble_hs_cfg.gatts_register_cb = custom_gatt_svr_register_cb; + ble_hs_cfg.store_status_cb = ble_store_util_status_rr; + ble_hs_cfg.sm_io_cap = 0x03; +#ifdef CONFIG_EXAMPLE_BONDING + ble_hs_cfg.sm_bonding = 1; + /* Enable the appropriate bit masks to make sure the keys + * that are needed are exchanged + */ + ble_hs_cfg.sm_our_key_dist |= BLE_SM_PAIR_KEY_DIST_ENC; + ble_hs_cfg.sm_their_key_dist |= BLE_SM_PAIR_KEY_DIST_ENC; +#endif +#ifdef CONFIG_EXAMPLE_MITM + ble_hs_cfg.sm_mitm = 1; +#endif +#ifdef CONFIG_EXAMPLE_USE_SC + ble_hs_cfg.sm_sc = 1; +#else + ble_hs_cfg.sm_sc = 0; +#endif +#ifdef CONFIG_EXAMPLE_RESOLVE_PEER_ADDR + /* Stores the IRK */ + ble_hs_cfg.sm_our_key_dist |= BLE_SM_PAIR_KEY_DIST_ID; + ble_hs_cfg.sm_their_key_dist |= BLE_SM_PAIR_KEY_DIST_ID; +#endif + rc = custom_gatt_svr_init(); + assert(rc == 0); + /* Set the default device name. */ + rc = ble_svc_gap_device_name_set("nimble-ble_chan_reflector"); + assert(rc == 0); + /* XXX Need to have template for store */ + ble_store_config_init(); + nimble_port_freertos_init(bleprph_host_task); + +} diff --git a/examples/bluetooth/nimble/ble_chan_sound_reflector/sdkconfig.defaults b/examples/bluetooth/nimble/ble_chan_sound_reflector/sdkconfig.defaults new file mode 100644 index 000000000000..ccd144ad765e --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_reflector/sdkconfig.defaults @@ -0,0 +1,17 @@ +# Override some defaults so BT stack is enabled +# in this example + +# +# BT config +# +CONFIG_BT_ENABLED=y +CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y +CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n +CONFIG_BTDM_CTRL_MODE_BTDM=n +CONFIG_BT_BLUEDROID_ENABLED=n +CONFIG_BT_CONTROLLER_DISABLED=y +CONFIG_BT_NIMBLE_60_FEATURE_SUPPORT=y +CONFIG_BT_NIMBLE_ENABLED=y +CONFIG_BT_NIMBLE_EXT_ADV=y +CONFIG_BT_NIMBLE_CHANNEL_SOUNDING=y +CONFIG_BT_NIMBLE_ATT_PREFERRED_MTU=498 diff --git a/examples/bluetooth/nimble/ble_chan_sound_reflector/sdkconfig.defaults.esp32c2 b/examples/bluetooth/nimble/ble_chan_sound_reflector/sdkconfig.defaults.esp32c2 new file mode 100644 index 000000000000..b26cbfd4374a --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_reflector/sdkconfig.defaults.esp32c2 @@ -0,0 +1,8 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_IDF_TARGET="esp32c2" +CONFIG_BT_ENABLED=y +CONFIG_BT_NIMBLE_ENABLED=y +CONFIG_BT_NIMBLE_TRANSPORT_EVT_SIZE=70 +CONFIG_BT_NIMBLE_EXT_ADV=y diff --git a/examples/bluetooth/nimble/ble_chan_sound_reflector/sdkconfig.defaults.esp32c6 b/examples/bluetooth/nimble/ble_chan_sound_reflector/sdkconfig.defaults.esp32c6 new file mode 100644 index 000000000000..aa44a69ff352 --- /dev/null +++ b/examples/bluetooth/nimble/ble_chan_sound_reflector/sdkconfig.defaults.esp32c6 @@ -0,0 +1,7 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_BT_ENABLED=y +CONFIG_BT_NIMBLE_ENABLED=y +CONFIG_BT_NIMBLE_TRANSPORT_EVT_SIZE=70 +CONFIG_BT_NIMBLE_EXT_ADV=y diff --git a/examples/bluetooth/nimble/ble_cts/cts_cent/main/main.c b/examples/bluetooth/nimble/ble_cts/cts_cent/main/main.c index 0a99776f2cba..128b6afd3ac8 100644 --- a/examples/bluetooth/nimble/ble_cts/cts_cent/main/main.c +++ b/examples/bluetooth/nimble/ble_cts/cts_cent/main/main.c @@ -44,6 +44,7 @@ void printtime(struct ble_svc_cts_curr_time ctime) { ESP_LOGI(tag, "fractions : %d\n", ctime.et_256.fractions_256); } +#if MYNEWT_VAL(BLE_GATTC) /** * Application callback. Called when the read of the cts current time * characteristic has completed. @@ -137,6 +138,7 @@ ble_cts_cent_on_disc_complete(const struct peer *peer, int status, void *arg) */ ble_cts_cent_read_time(peer); } +#endif /** * Initiates the GAP general discovery procedure. @@ -434,6 +436,7 @@ ble_cts_cent_gap_event(struct ble_gap_event *event, void *arg) return 0; } #else +#if MYNEWT_VAL(BLE_GATTC) /* Perform service discovery */ rc = peer_disc_all(event->connect.conn_handle, ble_cts_cent_on_disc_complete, NULL); @@ -441,6 +444,7 @@ ble_cts_cent_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif #endif // BLE_GATT_CACHING_ASSOC_ENABLE #endif } else { @@ -485,6 +489,7 @@ ble_cts_cent_gap_event(struct ble_gap_event *event, void *arg) return 0; } #else +#if MYNEWT_VAL(BLE_GATTC) /*** Go for service discovery after encryption has been successfully enabled ***/ rc = peer_disc_all(event->connect.conn_handle, ble_cts_cent_on_disc_complete, NULL); @@ -492,6 +497,7 @@ ble_cts_cent_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif #endif // BLE_GATT_CACHING_ASSOC_ENABLE #endif return 0; diff --git a/examples/bluetooth/nimble/ble_cts/cts_prph/main/main.c b/examples/bluetooth/nimble/ble_cts/cts_prph/main/main.c index 2da3a66ad69f..04ee0c3eadd2 100644 --- a/examples/bluetooth/nimble/ble_cts/cts_prph/main/main.c +++ b/examples/bluetooth/nimble/ble_cts/cts_prph/main/main.c @@ -28,7 +28,6 @@ static uint8_t ext_adv_pattern_1[] = { static const char *tag = "NimBLE_CTS_PRPH"; static const char *device_name = "ble_cts_prph"; - static int ble_cts_prph_gap_event(struct ble_gap_event *event, void *arg); static uint8_t ble_cts_prph_addr_type; @@ -274,8 +273,6 @@ void ble_cts_prph_host_task(void *param) void app_main(void) { - int rc; - /* Initialize NVS — it is used to store PHY calibration data */ esp_err_t ret = nvs_flash_init(); if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { @@ -302,12 +299,15 @@ void app_main(void) ble_hs_cfg.sm_sc = 1; ble_hs_cfg.sm_mitm = 1; +#if MYNEWT_VAL(BLE_GATTS) + int rc; rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name */ rc = ble_svc_gap_device_name_set(device_name); assert(rc == 0); +#endif /* Start the task */ nimble_port_freertos_init(ble_cts_prph_host_task); diff --git a/examples/bluetooth/nimble/ble_dynamic_service/main/main.c b/examples/bluetooth/nimble/ble_dynamic_service/main/main.c index d99326f81d3e..02a7ed07271e 100644 --- a/examples/bluetooth/nimble/ble_dynamic_service/main/main.c +++ b/examples/bluetooth/nimble/ble_dynamic_service/main/main.c @@ -280,12 +280,14 @@ app_main(void) ble_hs_cfg.gatts_register_cb = gatt_svr_register_cb; ble_hs_cfg.store_status_cb = ble_store_util_status_rr; +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name. */ rc = ble_svc_gap_device_name_set("ble-dynamic-service"); assert(rc == 0); +#endif nimble_port_freertos_init(dynamic_service_host_task); diff --git a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/README.md b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/README.md index 38e4a0c5eae2..0f10cfea7dbb 100644 --- a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/README.md +++ b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/README.md @@ -52,7 +52,7 @@ idf.py menuconfig ``` In the `Component config` menu: -* Select encrypted adv data from `Component config -> Bluetooth -> NimBLE Options -> BT_NIMBLE_ENC_ADV_DATA` +* Select encrypted adv data from `Component config -> Bluetooth -> NimBLE Options -> Extra Features -> Encrypted Advertising Data` In the `Example Configuration` menu: diff --git a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/main/main.c b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/main/main.c index 1b3e77574d69..a141d0f2e0fd 100644 --- a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/main/main.c +++ b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/main/main.c @@ -22,7 +22,10 @@ static struct km_peer kmp[CONFIG_BT_NIMBLE_MAX_CONNECTIONS + 1] = {0}; static const char *tag = "ENC_ADV_DATA_CENT"; static int enc_adv_data_cent_gap_event(struct ble_gap_event *event, void *arg); + +#if MYNEWT_VAL(BLE_GATTC) static int mtu_def = 512; +#endif void ble_store_config_init(void); @@ -37,6 +40,7 @@ enc_adv_data_find_peer(const uint8_t *peer_addr) return -1; } +#if MYNEWT_VAL(BLE_GATTC) static int enc_adv_data_set_km_exist(const uint8_t *peer_addr) { @@ -47,6 +51,7 @@ enc_adv_data_set_km_exist(const uint8_t *peer_addr) kmp[ind].key_material_exist = true; return 0; } +#endif static bool enc_adv_data_check_km_exist(const uint8_t *peer_addr) @@ -60,6 +65,7 @@ enc_adv_data_check_km_exist(const uint8_t *peer_addr) return kmp[ind].key_material_exist; } +#if MYNEWT_VAL(BLE_GATTC) /** * Application callback. Called when the read has completed. */ @@ -175,6 +181,7 @@ enc_adv_data_cent_on_disc_complete(const struct peer *peer, int status, void *ar enc_adv_data_cent_read(peer); } } +#endif /** * Initiates the GAP general discovery procedure. @@ -444,6 +451,7 @@ enc_adv_data_cent_gap_event(struct ble_gap_event *event, void *arg) print_conn_desc(&desc); MODLOG_DFLT(INFO, ""); +#if MYNEWT_VAL(BLE_GATTC) rc = ble_att_set_preferred_mtu(mtu_def); if (rc != 0) { ESP_LOGE(tag, "Failed to set preferred MTU; rc = %d", rc); @@ -453,6 +461,7 @@ enc_adv_data_cent_gap_event(struct ble_gap_event *event, void *arg) if (rc != 0) { ESP_LOGE(tag, "Failed to negotiate MTU; rc = %d", rc); } +#endif /* Remember peer. */ rc = peer_add(event->connect.conn_handle); @@ -511,12 +520,14 @@ enc_adv_data_cent_gap_event(struct ble_gap_event *event, void *arg) assert(rc == 0); print_conn_desc(&desc); +#if MYNEWT_VAL(BLE_GATTC) /* Perform service discovery */ rc = peer_disc_all(event->enc_change.conn_handle, enc_adv_data_cent_on_disc_complete, NULL); if (rc != 0) { MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); } +#endif return 0; case BLE_GAP_EVENT_NOTIFY_RX: diff --git a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/README.md b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/README.md index 8c75a5645d9e..ceb55e0060d2 100644 --- a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/README.md +++ b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/README.md @@ -28,7 +28,7 @@ idf.py menuconfig ``` In the `Component config` menu: -* Select encrypted adv data from `Component config -> Bluetooth -> NimBLE Options -> BT_NIMBLE_ENC_ADV_DATA` +* Select encrypted adv data from `Component config -> Bluetooth -> NimBLE Options -> Extra Features -> Encrypted Advertising Data` In the `Example Configuration` menu: diff --git a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/main/main.c b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/main/main.c index e0c87902583b..78a3159eb40e 100644 --- a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/main/main.c +++ b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/main/main.c @@ -413,15 +413,16 @@ app_main(void) ble_hs_cfg.sm_their_key_dist |= BLE_SM_PAIR_KEY_DIST_ID; #endif +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name. */ rc = ble_svc_gap_device_name_set("enc_adv_data_prph"); assert(rc == 0); +#endif /* Set the session key and initialization vector */ - rc = ble_svc_gap_device_key_material_set(km.session_key, km.iv); assert(rc == 0); diff --git a/examples/bluetooth/nimble/ble_htp/htp_cent/main/main.c b/examples/bluetooth/nimble/ble_htp/htp_cent/main/main.c index 2e47880916b8..281dadc61030 100644 --- a/examples/bluetooth/nimble/ble_htp/htp_cent/main/main.c +++ b/examples/bluetooth/nimble/ble_htp/htp_cent/main/main.c @@ -20,6 +20,8 @@ static int ble_htp_cent_gap_event(struct ble_gap_event *event, void *arg); void ble_store_config_init(void); static void ble_htp_cent_scan(void); + +#if MYNEWT_VAL(BLE_GATTC) /** * Application callback. Called when the attempt to subscribe to notifications * for the HTP intermediate temperature characteristic has completed. @@ -255,7 +257,7 @@ ble_htp_cent_on_disc_complete(const struct peer *peer, int status, void *arg) */ ble_htp_cent_read_write_subscribe(peer); } - +#endif /** * Initiates the GAP general discovery procedure. */ @@ -548,6 +550,7 @@ ble_htp_cent_gap_event(struct ble_gap_event *event, void *arg) return 0; } #else +#if MYNEWT_VAL(BLE_GATTC) /* Perform service discovery */ rc = peer_disc_all(event->connect.conn_handle, ble_htp_cent_on_disc_complete, NULL); @@ -555,6 +558,7 @@ ble_htp_cent_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif #endif // BLE_GATT_CACHING_ASSOC_ENABLE #endif } else { @@ -599,6 +603,7 @@ ble_htp_cent_gap_event(struct ble_gap_event *event, void *arg) return 0; } #else +#if MYNEWT_VAL(BLE_GATTC) /*** Go for service discovery after encryption has been successfully enabled ***/ rc = peer_disc_all(event->connect.conn_handle, ble_htp_cent_on_disc_complete, NULL); @@ -606,6 +611,7 @@ ble_htp_cent_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif #endif // BLE_GATT_CACHING_ASSOC_ENABLE #endif return 0; diff --git a/examples/bluetooth/nimble/ble_htp/htp_prph/main/main.c b/examples/bluetooth/nimble/ble_htp/htp_prph/main/main.c index 01bece43a40e..896c1d6fd4e2 100644 --- a/examples/bluetooth/nimble/ble_htp/htp_prph/main/main.c +++ b/examples/bluetooth/nimble/ble_htp/htp_prph/main/main.c @@ -201,6 +201,8 @@ ble_htp_prph_tx_htp_reset(void) static void ble_htp_prph_tx(TimerHandle_t ev) { + +#if CONFIG_BT_NIMBLE_HTP_SERVICE int rc; float temp; @@ -222,6 +224,7 @@ ble_htp_prph_tx(TimerHandle_t ev) } else { MODLOG_DFLT(INFO, "Error in sending notification"); } +#endif ble_htp_prph_tx_htp_reset(); } @@ -259,7 +262,9 @@ ble_htp_prph_gap_event(struct ble_gap_event *event, void *arg) #endif ble_htp_prph_tx_htp_stop(); +#if CONFIG_BT_NIMBLE_HTP_SERVICE ble_svc_htp_on_disconnect(event->disconnect.conn.conn_handle); +#endif break; case BLE_GAP_EVENT_ADV_COMPLETE: @@ -276,7 +281,9 @@ ble_htp_prph_gap_event(struct ble_gap_event *event, void *arg) "val_handle=%d\n", event->subscribe.cur_notify, event->subscribe.attr_handle); +#if CONFIG_BT_NIMBLE_HTP_SERVICE ble_svc_htp_subscribe(event->subscribe.conn_handle, event->subscribe.attr_handle); +#endif if (event->subscribe.cur_notify) { ble_htp_prph_tx_htp_reset(); @@ -336,8 +343,6 @@ void ble_htp_prph_host_task(void *param) void app_main(void) { - int rc; - /* Initialize NVS — it is used to store PHY calibration data */ esp_err_t ret = nvs_flash_init(); if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { @@ -368,12 +373,15 @@ void app_main(void) ble_htp_prph_tx_timer = xTimerCreate("ble_htp_prph_tx_timer", pdMS_TO_TICKS(1000), pdTRUE, (void *)0, ble_htp_prph_tx); +#if MYNEWT_VAL(BLE_GATTS) + int rc; rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name */ rc = ble_svc_gap_device_name_set(device_name); assert(rc == 0); +#endif /* Start the task */ nimble_port_freertos_init(ble_htp_prph_host_task); diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md b/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md index abba49d40d7f..2958e70e760c 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md @@ -48,7 +48,7 @@ idf.py menuconfig In the `Component Config` menu: -* Change Component config → Bluetooth → NimBLE Options → Maximum number of connection oriented channels to a value greater than 0 +* Change Component config → Bluetooth → NimBLE Options → L2CAP → Maximum number of connection oriented channels to a value greater than 0 * Change Component config → Bluetooth → NimBLE Options → Memory Settings → MSYS_1 Block Size to 536 (For maximum transmission of data) ### Build and Flash diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md index 6a66024f1015..a21c7dd6f172 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md @@ -48,7 +48,7 @@ idf.py menuconfig In the `Component Config` menu: -* Change Component config → Bluetooth → NimBLE Options → Maximum number of connection oriented channels to a value greater than 0 +* Change Component config → Bluetooth → NimBLE Options → L2CAP → Maximum number of connection oriented channels to a value greater than 0 * Change Component config → Bluetooth → NimBLE Options → Memory Settings → MSYS_1 Block Size to 536 (For maximum transmission of data) ### Build and Flash diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/main.c b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/main.c index 010ea85a1541..641a2f43bc21 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/main.c +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/main.c @@ -133,7 +133,6 @@ bleprph_advertise(void) { struct ble_gap_adv_params adv_params; struct ble_hs_adv_fields fields; - const char *name; int rc; /** @@ -160,6 +159,7 @@ bleprph_advertise(void) fields.tx_pwr_lvl_is_present = 1; fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO; + const char *name; name = ble_svc_gap_device_name(); fields.name = (uint8_t *)name; fields.name_len = strlen(name); diff --git a/examples/bluetooth/nimble/ble_multi_adv/README.md b/examples/bluetooth/nimble/ble_multi_adv/README.md index b485d51198e9..7038099d9424 100644 --- a/examples/bluetooth/nimble/ble_multi_adv/README.md +++ b/examples/bluetooth/nimble/ble_multi_adv/README.md @@ -30,7 +30,7 @@ idf.py menuconfig To configure number of advertising instances: -* Component config → Bluetooth → NimBLE Options → Enable BLE 5 feature → Maximum number of extended advertising instances +* Component config → Bluetooth → NimBLE Options → BLE 5.x Features → Enable BLE 5 feature → Enable extended advertising → Maximum number of extended advertising instances ### Hardware Required diff --git a/examples/bluetooth/nimble/ble_multi_adv/main/main.c b/examples/bluetooth/nimble/ble_multi_adv/main/main.c index b8393aa806f2..03f93210fd9d 100644 --- a/examples/bluetooth/nimble/ble_multi_adv/main/main.c +++ b/examples/bluetooth/nimble/ble_multi_adv/main/main.c @@ -459,8 +459,6 @@ void ble_multi_adv_host_task(void *param) void app_main(void) { - int rc; - /* Initialize NVS — it is used to store PHY calibration data */ esp_err_t ret = nvs_flash_init(); if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { @@ -495,6 +493,8 @@ app_main(void) ble_instance_cb[i].cb = NULL; } +#if MYNEWT_VAL(BLE_GATTS) + int rc; rc = gatt_svr_init(); assert(rc == 0); @@ -502,6 +502,7 @@ app_main(void) /* Set the default device name. */ rc = ble_svc_gap_device_name_set("nimble-multi-adv"); assert(rc == 0); +#endif #endif /* XXX Need to have template for store */ diff --git a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/main/main.c b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/main/main.c index 6acd00750c52..c324092aee35 100644 --- a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/main/main.c +++ b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/main/main.c @@ -461,13 +461,17 @@ app_main(void) rc = peer_init(BLE_PEER_MAX_NUM, BLE_PEER_MAX_NUM, BLE_PEER_MAX_NUM, BLE_PEER_MAX_NUM); assert(rc == 0); #endif - /* Set the default device name. We will act as both central and peripheral. */ - rc = ble_svc_gap_device_name_set("esp-ble-role-coex"); - assert(rc == 0); + +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); + /* Set the default device name. We will act as both central and peripheral. */ + rc = ble_svc_gap_device_name_set("esp-ble-role-coex"); + assert(rc == 0); +#endif + /* XXX Need to have template for store */ ble_store_config_init(); diff --git a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/main/main.c b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/main/main.c index 47f6461572ae..e4b0f4686ae1 100644 --- a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/main/main.c +++ b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/main/main.c @@ -287,12 +287,14 @@ app_main(void) ble_hs_cfg.gatts_register_cb = gatt_svr_register_cb; ble_hs_cfg.store_status_cb = ble_store_util_status_rr; +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name. */ rc = ble_svc_gap_device_name_set("esp-multi-conn"); assert(rc == 0); +#endif /* XXX Need to have template for store */ ble_store_config_init(); diff --git a/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_adv/README.md b/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_adv/README.md index 70d5c1bce2bb..7fce880ce116 100644 --- a/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_adv/README.md +++ b/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_adv/README.md @@ -1,9 +1,5 @@ -| Supported Targets | ESP32-C6 | -| ----------------- | -------- | - - -# Important Note -*This example currently requires an external Bluetooth controller supporting PAwR functionality, as the ESP chips listed above do not have native controller support for PAwR features and under development phase* +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | +| ----------------- | -------- | -------- | --------- | -------- | # BLE Periodic Advertiser With Response (PAwR) Advertiser Example @@ -14,7 +10,7 @@ This example starts PAwR advertising with configurable subevents and response slots. -It uses external Bluetooth controller and NimBLE stack based BLE host. +It uses Bluetooth controller and NimBLE stack based BLE host. This example aims at understanding PAwR advertisement and related NimBLE APIs. diff --git a/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_adv/main/main.c b/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_adv/main/main.c index a9539b543263..06f104f8d4c0 100644 --- a/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_adv/main/main.c +++ b/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_adv/main/main.c @@ -11,6 +11,7 @@ #include "host/ble_hs.h" #define BLE_PAWR_EVENT_INTERVAL (600) +#define BLE_PAWR_PERIODIC_EVENT_INTERVAL_MS (3000) #define BLE_PAWR_NUM_SUBEVTS (10) #define BLE_PAWR_SUB_INTERVAL (44) /*!< Interval between subevents (N * 1.25 ms) */ #define BLE_PAWR_RSP_SLOT_DELAY (20) /*!< The first response slot delay (N * 1.25 ms)*/ @@ -135,8 +136,8 @@ start_periodic_adv(void) /* configure periodic advertising */ memset(&pparams, 0, sizeof(pparams)); pparams.include_tx_power = 0; - pparams.itvl_min = BLE_GAP_PERIODIC_ITVL_MS(3000); - pparams.itvl_max = BLE_GAP_PERIODIC_ITVL_MS(3000); + pparams.itvl_min = BLE_GAP_PERIODIC_ITVL_MS(BLE_PAWR_PERIODIC_EVENT_INTERVAL_MS); + pparams.itvl_max = BLE_GAP_PERIODIC_ITVL_MS(BLE_PAWR_PERIODIC_EVENT_INTERVAL_MS); /* Configure the parameters of PAwR. */ pparams.num_subevents = BLE_PAWR_NUM_SUBEVTS; pparams.subevent_interval = BLE_PAWR_SUB_INTERVAL; diff --git a/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_adv/tutorial/BLE_pawr_adv_walkthrough.md b/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_adv/tutorial/BLE_pawr_adv_walkthrough.md index 146d981b6e12..e609cbd24a97 100644 --- a/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_adv/tutorial/BLE_pawr_adv_walkthrough.md +++ b/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_adv/tutorial/BLE_pawr_adv_walkthrough.md @@ -2,7 +2,7 @@ ## Introduction -This tutorial examines the BLE Periodic Advertisement with Responses (PAwR) example code for ESP32 chipsets with BLE 5.0+ support. The code demonstrates how to implement PAwR functionality using NimBLE APIs, which enables bidirectional communication between advertiser and scanner devices in a power-efficient manner. +This tutorial examines the BLE Periodic Advertisement with Responses (PAwR) example code for ESP32 chipsets with BLE 5.0+ support. The code demonstrates how to implement PAwR functionality using NimBLE APIs, which enables bidirectional communication between advertiser and scanner devices. ## Includes @@ -123,7 +123,7 @@ esp_err_t esp_nimble_init(void) The example defines several PAwR parameters ```c -#define BLE_PAWR_EVENT_INTERVAL (600) +#define BLE_PAWR_PERIODIC_EVENT_INTERVAL_MS (3000) #define BLE_PAWR_NUM_SUBEVTS (10) #define BLE_PAWR_SUB_INTERVAL (44) /*!< Interval between subevents (N * 1.25 ms) */ #define BLE_PAWR_RSP_SLOT_DELAY (20) /*!< The first response slot delay (N * 1.25 ms) */ @@ -142,22 +142,6 @@ These parameters control: - Data length for subevent payloads - -## Periodic Advertising Configuration -```c -memset(&pparams, 0, sizeof(pparams)); -pparams.include_tx_power = 0; -pparams.itvl_min = BLE_GAP_PERIODIC_ITVL_MS(3000); -pparams.itvl_max = BLE_GAP_PERIODIC_ITVL_MS(3000); -pparams.num_subevents = BLE_PAWR_NUM_SUBEVTS; -pparams.subevent_interval = BLE_PAWR_SUB_INTERVAL; -pparams.response_slot_delay = BLE_PAWR_RSP_SLOT_DELAY; -pparams.response_slot_spacing = BLE_PAWR_RSP_SLOT_SPACING; -pparams.num_response_slots = BLE_PAWR_NUM_RSP_SLOTS; - -rc = ble_gap_periodic_adv_configure(instance, &pparams); -assert(rc == 0); -``` ## Key PAwR Parameters: - num_subevents: Number of subevents per periodic interval (10) @@ -226,8 +210,8 @@ start_periodic_adv(void) /* configure periodic advertising */ memset(&pparams, 0, sizeof(pparams)); pparams.include_tx_power = 0; - pparams.itvl_min = BLE_GAP_PERIODIC_ITVL_MS(3000); - pparams.itvl_max = BLE_GAP_PERIODIC_ITVL_MS(3000); + pparams.itvl_min = BLE_GAP_PERIODIC_ITVL_MS(BLE_PAWR_PERIODIC_EVENT_INTERVAL_MS); + pparams.itvl_max = BLE_GAP_PERIODIC_ITVL_MS(BLE_PAWR_PERIODIC_EVENT_INTERVAL_MS); /* Configure the parameters of PAwR. */ pparams.num_subevents = BLE_PAWR_NUM_SUBEVTS; pparams.subevent_interval = BLE_PAWR_SUB_INTERVAL; @@ -312,9 +296,7 @@ This PAwR example demonstrates: 2. Bidirectional communication between advertiser and scanners -3. Efficient power usage through scheduled communication windows - -4. Use of extended advertising to announce PAwR capabilities +3. Use of extended advertising to announce PAwR capabilities The implementation shows how to: @@ -326,4 +308,4 @@ The implementation shows how to: - Manage the advertising lifecycle -PAwR is particularly useful for applications requiring periodic, bidirectional communication with multiple devices while maintaining low power consumption. \ No newline at end of file +PAwR is particularly useful for applications requiring periodic, bidirectional communication with multiple devices \ No newline at end of file diff --git a/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_sync/README.md b/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_sync/README.md index 6b3336727464..23198ac9dc3c 100644 --- a/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_sync/README.md +++ b/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_sync/README.md @@ -1,8 +1,5 @@ -| Supported Targets | ESP32-C6 | -| ----------------- | -------- | - -# Important Note -*This example currently requires an external Bluetooth controller supporting PAwR functionality, as the ESP chips listed above do not have native controller support for PAwR features and under development phase* +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | +| ----------------- | -------- | -------- | --------- | -------- | # BLE Periodic Advertiser With Response (PAwR) Sync Example @@ -20,6 +17,7 @@ To test this demo, any BLE advertiser supporting PAwR can be used.(check /exampl - Configurable synchronization parameters (skip factor, timeout) - Detailed reporting of PAwR advertisement data - Handling of synchronization loss events +- Configuration of PAwR response data Note : diff --git a/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_sync/main/main.c b/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_sync/main/main.c index dc9d1b83e2f4..12b517af515f 100644 --- a/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_sync/main/main.c +++ b/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_sync/main/main.c @@ -13,7 +13,9 @@ #define TAG "NimBLE_BLE_PAwR" #define TARGET_NAME "Nimble_PAwR" +#define BLE_PAWR_RSP_DATA_IDX (2) #define BLE_PAWR_RSP_DATA_LEN (16) + static uint8_t sub_data_pattern[BLE_PAWR_RSP_DATA_LEN] = {0}; static int create_periodic_sync(struct ble_gap_ext_disc_desc *disc); @@ -60,7 +62,7 @@ gap_event_cb(struct ble_gap_event *event, void *arg) .request_event = event->periodic_report.event_counter, .request_subevent = event->periodic_report.subevent, .response_subevent = event->periodic_report.subevent, - .response_slot = 2, + .response_slot = BLE_PAWR_RSP_DATA_IDX, }; struct os_mbuf *data = os_msys_get_pkthdr(BLE_PAWR_RSP_DATA_LEN, 0); diff --git a/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_sync/tutorial/BLE_pawr_sync_walkthrough.md b/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_sync/tutorial/BLE_pawr_sync_walkthrough.md index fade095b1f2f..5543acaa7ed1 100644 --- a/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_sync/tutorial/BLE_pawr_sync_walkthrough.md +++ b/examples/bluetooth/nimble/ble_pawr_adv/ble_pawr_sync/tutorial/BLE_pawr_sync_walkthrough.md @@ -140,6 +140,7 @@ The example defines several key parameters: ```c #define TAG "NimBLE_BLE_PAwR" #define TARGET_NAME "Nimble_PAwR" +#define BLE_PAWR_RSP_DATA_IDX (2) #define BLE_PAWR_RSP_DATA_LEN (16) static uint8_t sub_data_pattern[BLE_PAWR_RSP_DATA_LEN] = {0}; ``` @@ -147,6 +148,8 @@ These parameters control: - Target advertiser name to sync with +- Response slot index to send response data at + - Response data length - Data pattern for responses @@ -232,7 +235,7 @@ case BLE_GAP_EVENT_PERIODIC_REPORT: .request_event = event->periodic_report.event_counter, .request_subevent = event->periodic_report.subevent, .response_subevent = event->periodic_report.subevent, - .response_slot = rsp_slot_idx + .response_slot = BLE_PAWR_RSP_DATA_IDX }; // Prepare response data @@ -245,9 +248,12 @@ case BLE_GAP_EVENT_PERIODIC_REPORT: event->periodic_report.sync_handle, ¶m, data); break; ``` + +By default the response data will be sent within the same subevent where the periodic advertising report is received. + ## Subevent Configuration -After sync establishment: +After sync establishment, sync to configurable subevents: ```c // Choose subevents to listen to @@ -256,6 +262,8 @@ int result = ble_gap_periodic_adv_sync_subev( event->periodic_sync.sync_handle, 0, sizeof(subevents), subevents); ``` +The subevents sync selection depends on the subevent number of the Periodic Advertising device. + ## Error Handling When sync is lost: ```c @@ -270,4 +278,4 @@ case BLE_GAP_EVENT_PERIODIC_SYNC_LOST: ## Conclusion -This implementation demonstrates a complete PAwR synchronization solution, showcasing advertiser discovery via extended scanning, periodic sync establishment with configurable subevents (0-4), and efficient bidirectional communication through managed response slots. The robust architecture handles sync loss recovery while maintaining low-power operation, making it ideal for IoT applications requiring scheduled, bidirectional communication with multiple endpoints. The solution leverages BLE 5.0's PAwR features to optimize power efficiency and reliability in dense RF environments. \ No newline at end of file +This implementation demonstrates a complete PAwR synchronization solution, showcasing advertiser discovery via extended scanning, periodic sync establishment with configurable subevents (0-4), and efficient bidirectional communication through managed response slots. The robust architecture handles sync loss recovery, making it ideal for IoT applications requiring scheduled, bidirectional communication with multiple endpoints. \ No newline at end of file diff --git a/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_adv_conn/README.md b/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_adv_conn/README.md index 648c6b8b66c3..a8bc010ff374 100644 --- a/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_adv_conn/README.md +++ b/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_adv_conn/README.md @@ -1,8 +1,5 @@ -| Supported Targets | ESP32-C6 | -| ----------------- | -------- | - -# Important Note -*This example currently requires an external Bluetooth controller supporting PAwR functionality, as the ESP chips listed above do not have native controller support for PAwR features and under development phase* +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | +| ----------------- | -------- | -------- | --------- | -------- | # BLE Periodic Advertiser With Response (PAwR) Advertiser Connection Example diff --git a/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_adv_conn/main/main.c b/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_adv_conn/main/main.c index bf034cf1422d..b88e82538dd6 100644 --- a/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_adv_conn/main/main.c +++ b/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_adv_conn/main/main.c @@ -10,7 +10,7 @@ #include "nimble/nimble_port_freertos.h" #include "host/ble_hs.h" -#define BLE_PAWR_EVENT_INTERVAL (520) +#define BLE_PAWR_EVENT_PERIODIC_INTERVAL_MS (3000) #define BLE_PAWR_NUM_SUBEVTS (10) #define BLE_PAWR_SUB_INTERVAL (52) /*!< Interval between subevents (N * 1.25 ms) */ #define BLE_PAWR_RSP_SLOT_DELAY (5) /*!< The first response slot delay (N * 1.25 ms)*/ @@ -217,8 +217,8 @@ start_periodic_adv(void) /* configure periodic advertising */ memset(&pparams, 0, sizeof(pparams)); pparams.include_tx_power = 0; - pparams.itvl_min = BLE_GAP_PERIODIC_ITVL_MS(3000); - pparams.itvl_max = BLE_GAP_PERIODIC_ITVL_MS(3000); + pparams.itvl_min = BLE_GAP_PERIODIC_ITVL_MS(BLE_PAWR_EVENT_PERIODIC_INTERVAL_MS); + pparams.itvl_max = BLE_GAP_PERIODIC_ITVL_MS(BLE_PAWR_EVENT_PERIODIC_INTERVAL_MS); /* Configure the parameters of PAwR. */ pparams.num_subevents = BLE_PAWR_NUM_SUBEVTS; pparams.subevent_interval = BLE_PAWR_SUB_INTERVAL; diff --git a/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_adv_conn/tutorial/BLE_pawr_adv_conn_walkthrough.md b/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_adv_conn/tutorial/BLE_pawr_adv_conn_walkthrough.md index 94d8f0d2b014..0cd708f4a390 100644 --- a/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_adv_conn/tutorial/BLE_pawr_adv_conn_walkthrough.md +++ b/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_adv_conn/tutorial/BLE_pawr_adv_conn_walkthrough.md @@ -123,6 +123,7 @@ esp_err_t esp_nimble_init(void) ## PAwR Configuration ```c #define BLE_PAWR_EVENT_INTERVAL (520) +#define BLE_PAWR_EVENT_PERIODIC_INTERVAL_MS (3000) #define BLE_PAWR_NUM_SUBEVTS (10) #define BLE_PAWR_SUB_INTERVAL (52) #define BLE_PAWR_RSP_SLOT_DELAY (5) @@ -130,33 +131,123 @@ esp_err_t esp_nimble_init(void) #define BLE_PAWR_NUM_RSP_SLOTS (25) #define BLE_PAWR_SUB_DATA_LEN (20) ``` -These parameters configure PAwR interval, subevents, response slot timing, and payload length. +These parameters control: -## Periodic Advertising Configuration +- The interval between periodic advertising events +- Number of subevents per periodic interval + +- Timing of response slots + +- Data length for subevent payloads + +## Key PAwR Parameters: + +- num_subevents: Number of subevents per periodic interval (10) + +- subevent_interval: Time between subevents (44 × 1.25ms = 55ms) + +- response_slot_delay: First response slot delay (20 × 1.25ms = 25ms) + +- response_slot_spacing: Time between slots (32 × 0.125ms = 4ms) + +- num_response_slots: Number of response slots per subevent (5) + +## PAwR Advertisement + +The start_periodic_adv() function configures and starts PAwR: ```c -memset(&pparams, 0, sizeof(pparams)); -pparams.include_tx_power = 0; -pparams.itvl_min = BLE_GAP_PERIODIC_ITVL_MS(3000); -pparams.itvl_max = BLE_GAP_PERIODIC_ITVL_MS(3000); -pparams.num_subevents = BLE_PAWR_NUM_SUBEVTS; -pparams.subevent_interval = BLE_PAWR_SUB_INTERVAL; -pparams.response_slot_delay = BLE_PAWR_RSP_SLOT_DELAY; -pparams.response_slot_spacing = BLE_PAWR_RSP_SLOT_SPACING; -pparams.num_response_slots = BLE_PAWR_NUM_RSP_SLOTS; +static void +start_periodic_adv(void) +{ + int rc; + uint8_t addr[6]; + struct ble_gap_periodic_adv_params pparams; + struct ble_gap_ext_adv_params params; + struct ble_hs_adv_fields adv_fields; + struct os_mbuf *data; + uint8_t instance = 0; + +#if MYNEWT_VAL(BLE_PERIODIC_ADV_ENH) + struct ble_gap_periodic_adv_enable_params eparams; + memset(&eparams, 0, sizeof(eparams)); +#endif + + /* Get the local public address. */ + rc = ble_hs_id_copy_addr(BLE_ADDR_PUBLIC, addr, NULL); + assert (rc == 0); + + ESP_LOGI(TAG, "Device Address %02x:%02x:%02x:%02x:%02x:%02x", addr[5], addr[4], addr[3], + addr[2], addr[1], addr[0]); + + /* For periodic we use instance with non-connectable advertising */ + memset (¶ms, 0, sizeof(params)); + params.own_addr_type = BLE_OWN_ADDR_PUBLIC; + params.primary_phy = BLE_HCI_LE_PHY_CODED; + params.secondary_phy = BLE_HCI_LE_PHY_1M; + params.sid = 0; + params.itvl_min = BLE_GAP_ADV_ITVL_MS(50); + params.itvl_max = BLE_GAP_ADV_ITVL_MS(50); + + rc = ble_gap_ext_adv_configure(instance, ¶ms, NULL, gap_event_cb, NULL); + assert (rc == 0); + + memset(&adv_fields, 0, sizeof(adv_fields)); + adv_fields.name = (const uint8_t *)"Nimble_PAwR_CONN"; + adv_fields.name_len = strlen((char *)adv_fields.name); + + /* mbuf chain will be increased if needed */ + data = os_msys_get_pkthdr(BLE_HCI_MAX_ADV_DATA_LEN, 0); + assert(data); + + rc = ble_hs_adv_set_fields_mbuf(&adv_fields, data); + assert(rc == 0); + + rc = ble_gap_ext_adv_set_data(instance, data); + assert(rc == 0); + + /* configure periodic advertising */ + memset(&pparams, 0, sizeof(pparams)); + pparams.include_tx_power = 0; + pparams.itvl_min = BLE_GAP_PERIODIC_ITVL_MS(BLE_PAWR_EVENT_PERIODIC_INTERVAL_MS); + pparams.itvl_max = BLE_GAP_PERIODIC_ITVL_MS(BLE_PAWR_EVENT_PERIODIC_INTERVAL_MS); + /* Configure the parameters of PAwR. */ + pparams.num_subevents = BLE_PAWR_NUM_SUBEVTS; + pparams.subevent_interval = BLE_PAWR_SUB_INTERVAL; + pparams.response_slot_delay = BLE_PAWR_RSP_SLOT_DELAY; + pparams.response_slot_spacing = BLE_PAWR_RSP_SLOT_SPACING; + pparams.num_response_slots = BLE_PAWR_NUM_RSP_SLOTS; + + rc = ble_gap_periodic_adv_configure(instance, &pparams); + assert(rc == 0); + + /* start periodic advertising */ +#if MYNEWT_VAL(BLE_PERIODIC_ADV_ENH) + eparams.include_adi = 1; + rc = ble_gap_periodic_adv_start(instance, &eparams); +#else + rc = ble_gap_periodic_adv_start(instance); +#endif + assert (rc == 0); + + /* start advertising */ + rc = ble_gap_ext_adv_start(instance, 0, 0); + assert (rc == 0); + + ESP_LOGI(TAG, "instance %u started (periodic)\n", instance); +} ``` +Key steps: -These values are passed to ble_gap_periodic_adv_configure() to start PAwR. +- Configure extended advertising parameters -## PAwR Advertisement -The start_periodic_adv() function: -- Configures extended advertising parameters -- Sets up periodic advertising using subevent and slot parameters -- Starts extended + periodic advertising +- Set up periodic advertising with subevent and response slot parameters + +- Start both periodic and extended advertising ## Need of Extended Advertisement in Periodic Advertisement -Extended advertisements contain synchronization info that lets scanners align with periodic advertising. This enables precise subevent-based communicati +Extended advertisements contain synchronization info that lets scanners align with periodic advertising. This enables precise subevent-based communication. ## GAP Event Callback @@ -175,7 +266,7 @@ case BLE_GAP_EVENT_DISCONNECT: ## Using ble_gap_connect_with_synced() -The API ble_gap_connect_with_synced() is a NimBLE API used by a PAwR Advertiser to initiate a BLE connection with a synced scanner. This allows the advertiser to transition from scheduled subevent-based communication to a higher-throughput, lower-latency connection with a specific scanner. +The API ble_gap_connect_with_synced() is a NimBLE API used by a PAwR Advertiser to initiate a BLE connection with a synced scanner as central role. This allows the advertiser to transition from scheduled subevent-based communication to a higher-throughput, lower-latency connection with a specific scanner. This is especially useful in use cases where on-demand, peer-to-peer data exchange is needed. ```c @@ -207,41 +298,6 @@ void pawr_host_task(void *param) nimble_port_freertos_deinit(); } ``` -## Parameter Configuration - -The below snippets represent the parameter configuration for extended and periodic advertisement. - -### For Extended Advertisement - -```c - params.own_addr_type = BLE_OWN_ADDR_RANDOM; //Own address type is set to Random - params.primary_phy = BLE_HCI_LE_PHY_1M; // Primary advertising PHY is set to 1M - params.secondary_phy = BLE_HCI_LE_PHY_2M; // Secondary advertising PHY is set to 2M - params.sid = 2; // Advertising set Id is assigned with value 2. -``` - -### For Periodic Advertisement - -```c - memset(&pparams, 0, sizeof(pparams)); - pparams.include_tx_power = 0; // Indicates that TX power is not included in advertising PDU - pparams.itvl_min = BLE_GAP_ADV_ITVL_MS(120); // Minimum advertising interval of 240ms - pparams.itvl_max = BLE_GAP_ADV_ITVL_MS(240); //Maximum advertising interval of 480ms -``` - -Periodic advertisement is started for a particular advertisement instance by calling the API `ble_gap_periodic_adv_start(instance)`. This function takes instance-id as an input parameter. It defines the hci command by initializing the command parameters which are represented in the following lines. - -```c - struct ble_hci_le_set_periodic_adv_enable_cp cmd; - cmd.enable = 0x01; - cmd.adv_handle = instance; -``` - -Extended advertising is invoked for a particular instance using the API call `ble_gap_ext_adv_start(instance, 0, 0)`.Instance-id, duration, and max_events are input parameters for this API call respectively. - -Duration represents the time for which the adverteiment will take place. Upon expiration, the advertising procedure ends, and the BLE_GAP_EVENT_ADV_COMPLETE event is reported.0 value is used for no expiration. - -max_events Number of advertising events that should be sent before advertising ends and a BLE_GAP_EVENT_ADV_COMPLETE event is reported.0 value is used for no limit. ## Conclusion @@ -252,5 +308,5 @@ This PAwR with connection example demonstrates: - Periodic advertising with subevents and response slots - Dynamic connection initiation based on scanner responses - Use of extended advertisement for synchronization -- Efficient, scalable, low-power bidirectional communication +- Efficient, scalable, bidirectional communication diff --git a/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_sync_conn/README.md b/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_sync_conn/README.md index 86cbb85598a0..a6858b0dbf5a 100644 --- a/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_sync_conn/README.md +++ b/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_sync_conn/README.md @@ -1,8 +1,5 @@ -| Supported Targets | ESP32-C6 | -| ----------------- | -------- | - -## Important Note -*This example currently requires an external Bluetooth controller supporting PAwR functionality, as the ESP chips listed above do not have native controller support for PAwR features and under development phase* +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | +| ----------------- | -------- | -------- | --------- | -------- | # BLE Periodic Advertiser With Response (PAwR) Sync Connection Example diff --git a/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_sync_conn/main/main.c b/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_sync_conn/main/main.c index e43a975ce43e..539d7b540a66 100644 --- a/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_sync_conn/main/main.c +++ b/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_sync_conn/main/main.c @@ -13,6 +13,7 @@ #define TAG "NimBLE_BLE_PAwR_CONN" #define TARGET_NAME "Nimble_PAwR_CONN" +#define BLE_PAWR_RSP_SLOT_INDEX (2) #define BLE_PAWR_RSP_DATA_LEN (10) static uint8_t sub_data_pattern[BLE_PAWR_RSP_DATA_LEN] = {0}; @@ -114,7 +115,7 @@ gap_event_cb(struct ble_gap_event *event, void *arg) .request_event = event->periodic_report.event_counter, .request_subevent = event->periodic_report.subevent, .response_subevent = event->periodic_report.subevent, - .response_slot = 2, + .response_slot = BLE_PAWR_RSP_SLOT_INDEX, }; struct os_mbuf *data = os_msys_get_pkthdr(BLE_PAWR_RSP_DATA_LEN, 0); diff --git a/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_sync_conn/tutorial/BLE_pawr_sync_conn_walkthrough.md b/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_sync_conn/tutorial/BLE_pawr_sync_conn_walkthrough.md index 2a476e3eb6f0..1f608d67ec14 100644 --- a/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_sync_conn/tutorial/BLE_pawr_sync_conn_walkthrough.md +++ b/examples/bluetooth/nimble/ble_pawr_adv_conn/ble_pawr_sync_conn/tutorial/BLE_pawr_sync_conn_walkthrough.md @@ -114,19 +114,14 @@ esp_err_t esp_nimble_init(void) Configures a passive extended scan to detect periodic advertisers: ```c -static void start_scan(void) { - struct ble_gap_ext_disc_params d = { - .itvl = BLE_GAP_SCAN_ITVL_MS(600), // Scan every 600ms - .window = BLE_GAP_SCAN_ITVL_MS(300), // Listen for 300ms - .passive= 1 // Do not send scan requests - }; - // Start discovery; gap_event_cb handles each advertisement - ble_gap_ext_disc(BLE_OWN_ADDR_PUBLIC, 0, 0, 1, 0, 0, - NULL, &d, gap_event_cb, NULL); -} -``` + memset(&disc_params, 0, sizeof(disc_params)); + disc_params.itvl = BLE_GAP_SCAN_ITVL_MS(600); + disc_params.window = BLE_GAP_SCAN_ITVL_MS(300); + disc_params.passive = 1; -- BLE_OWN_ADDR_PUBLIC: Use the device’s public address. + rc = ble_gap_ext_disc(BLE_OWN_ADDR_PUBLIC, 0, 0, 1, 0, 0, NULL, &disc_params, + gap_event_cb, NULL); +``` - gap_event_cb: Processes discovery events (EXT_DISC) to find our target.` @@ -151,60 +146,54 @@ static int create_periodic_sync(struct ble_gap_ext_disc_desc *disc) { ``` - disc->addr / sid: Address and Sync ID identify the PAwR train. -- ble_gap_periodic_adv_sync_create: Starts low-power sync to periodic events. +- ble_gap_periodic_adv_sync_create: Starts sync to periodic events. -## Sending Response Data +## Subevent Synchronization -Once synchronized, respond during periodic reports: +After sync establishment, sync to configurable subevents: ```c +// Choose subevents to listen to +uint8_t subevents[] = {0, 1, 2, 3, 4}; +int result = ble_gap_periodic_adv_sync_subev( + event->periodic_sync.sync_handle, 0, sizeof(subevents), subevents); +``` -case BLE_GAPCreate Periodic Sync - -When a periodic advertiser is found, request synchronization: - -static int create_periodic_sync(struct ble_gap_ext_disc_desc *disc) { - struct ble_gap_periodic_sync_params p = { - .skip = 0, // Do not skip any events - .sync_timeout = 4000, // Give 4000ms to establish sync - .reports_disabled= 0, // Keep reports enabled -#if CONFIG_EXAMPLE_PERIODIC_ADV_ENH - .filter_duplicates = 1, // Only receive when data-id changes -#endif - }; - // Initiate sync; callback will receive PERIODIC_SYNC - return ble_gap_periodic_adv_sync_create( - &disc->addr, disc->sid, &p, - gap_event_cb, NULL); -} +The subevents sync selection depends on the subevent number of the Periodic Advertising device. -disc->addr / sid: Address and Sync ID identify the PAwR train. +## Sending Response Data -ble_gap_periodic_adv_sync_create: Starts low-power sync to periodic events. +Respond after receiving periodic reports: -_EVENT_PERIODIC_REPORT: { - struct ble_gap_periodic_adv_response_params r = { - .request_event = event->periodic_report.event_counter, - .request_subevent = event->periodic_report.subevent, - .response_subevent= event->periodic_report.subevent, - .response_slot = 2, // Always use slot 2 - }; - // Allocate buffer for response payload - struct os_mbuf *m = os_msys_get_pkthdr(BLE_PAWR_RSP_DATA_LEN, 0); - // First byte: subevent index - sub_data_pattern[0] = event->periodic_report.subevent; - // Next 6 bytes: our public address - ble_hs_id_copy_addr(BLE_ADDR_PUBLIC, device_addr, NULL); - memcpy(&sub_data_pattern[1], device_addr, BLE_DEV_ADDR_LEN); - // Fill remaining bytes with slot index - sub_data_pattern[7] = r.response_slot; - os_mbuf_append(m, sub_data_pattern, BLE_PAWR_RSP_DATA_LEN); - // Send response data back to advertiser - ble_gap_periodic_adv_set_response_data( - event->periodic_report.sync_handle, - &r, m); - break; -} +```c +case BLE_GAP_EVENT_PERIODIC_REPORT: + ESP_LOGI(TAG, "[Periodic Adv Report] handle:%d, event_counter(%d), subevent(%d)", + event->periodic_report.sync_handle, + event->periodic_report.event_counter, + event->periodic_report.subevent); + + struct ble_gap_periodic_adv_response_params param = { + .request_event = event->periodic_report.event_counter, + .request_subevent = event->periodic_report.subevent, + .response_subevent = event->periodic_report.subevent, + .response_slot = BLE_PAWR_RSP_SLOT_INDEX, + }; + + struct os_mbuf *data = os_msys_get_pkthdr(BLE_PAWR_RSP_DATA_LEN, 0); + if (!data) { + ESP_LOGE(TAG, "No memory"); + return 0; + } + // create a special data for checking manually in ADV side + + sub_data_pattern[0] = event->periodic_report.subevent; + rc = ble_hs_id_copy_addr(BLE_ADDR_PUBLIC, device_addr, NULL); + sub_data_pattern[1] = param.response_slot; + memcpy(&sub_data_pattern[2],device_addr,BLE_DEV_ADDR_LEN); + + os_mbuf_append(data, sub_data_pattern, BLE_PAWR_RSP_DATA_LEN); + + rc = ble_gap_periodic_adv_set_response_data(event->periodic_report.sync_handle, ¶m, data); ``` - os_msys_get_pkthdr: Allocates memory for the response. @@ -263,7 +252,7 @@ This PAwR Sync + Conn example demonstrates: - Passive discovery of periodic advertisers. -- Low-power synchronization to scheduled subevents. +- Synchronization to scheduled subevents. - Slot-based responses with custom payload. diff --git a/examples/bluetooth/nimble/ble_phy/phy_cent/main/main.c b/examples/bluetooth/nimble/ble_phy/phy_cent/main/main.c index 09eb5f6cc615..cec4bcaa3a77 100644 --- a/examples/bluetooth/nimble/ble_phy/phy_cent/main/main.c +++ b/examples/bluetooth/nimble/ble_phy/phy_cent/main/main.c @@ -24,6 +24,7 @@ static void blecent_scan(void); static uint8_t s_current_phy; void ble_store_config_init(void); +#if MYNEWT_VAL(BLE_GATTC) /** * Performs GATT operation against the specified peer: * 1. Reads the Supported LE PHY characteristic. @@ -167,6 +168,7 @@ blecent_on_disc_complete(const struct peer *peer, int status, void *arg) blecent_read(peer); } +#endif /* Set default LE PHY before establishing connection */ void set_default_le_phy(uint8_t tx_phys_mask, uint8_t rx_phys_mask) @@ -388,6 +390,7 @@ blecent_gap_event(struct ble_gap_event *event, void *arg) return 0; } +#if MYNEWT_VAL(BLE_GATTC) /* Perform service discovery. */ rc = peer_disc_all(event->connect.conn_handle, blecent_on_disc_complete, NULL); @@ -395,6 +398,7 @@ blecent_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif } else { /* Connection attempt failed; resume scanning. */ MODLOG_DFLT(ERROR, "Error: Connection failed; status=%d\n", diff --git a/examples/bluetooth/nimble/ble_phy/phy_prph/main/main.c b/examples/bluetooth/nimble/ble_phy/phy_prph/main/main.c index b43e8f649fd6..4fce3bedb36f 100644 --- a/examples/bluetooth/nimble/ble_phy/phy_prph/main/main.c +++ b/examples/bluetooth/nimble/ble_phy/phy_prph/main/main.c @@ -342,8 +342,10 @@ app_main(void) ble_hs_cfg.sm_their_key_dist = 1; #endif +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init_le_phy(); assert(rc == 0); +#endif /* Set the default device name. */ rc = ble_svc_gap_device_name_set("bleprph-phy"); diff --git a/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_cent/main/main.c b/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_cent/main/main.c index 0f6f9b309d58..108988328003 100644 --- a/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_cent/main/main.c +++ b/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_cent/main/main.c @@ -33,6 +33,7 @@ void ble_store_config_init(void); static void ble_prox_cent_scan(void); static int ble_prox_cent_gap_event(struct ble_gap_event *event, void *arg); +#if MYNEWT_VAL(BLE_GATTC) static int ble_prox_cent_on_read(uint16_t conn_handle, const struct ble_gatt_error *error, @@ -172,6 +173,7 @@ ble_prox_cent_on_disc_complete(const struct peer *peer, int status, void *arg) */ ble_prox_cent_read_write_subscribe(peer); } +#endif /** * Initiates the GAP general discovery procedure. @@ -480,6 +482,7 @@ ble_prox_cent_gap_event(struct ble_gap_event *event, void *arg) return 0; } #else +#if MYNEWT_VAL(BLE_GATTC) /* Perform service discovery */ rc = peer_disc_all(event->connect.conn_handle, ble_prox_cent_on_disc_complete, NULL); @@ -487,6 +490,7 @@ ble_prox_cent_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif #endif // BLE_GATT_CACHING_ASSOC_ENABLE #endif } else { @@ -547,6 +551,7 @@ ble_prox_cent_gap_event(struct ble_gap_event *event, void *arg) return 0; } #else +#if MYNEWT_VAL(BLE_GATTC) /*** Go for service discovery after encryption has been successfully enabled ***/ rc = peer_disc_all(event->connect.conn_handle, ble_prox_cent_on_disc_complete, NULL); @@ -554,6 +559,7 @@ ble_prox_cent_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif #endif // BLE_GATT_CACHING_ASSOC_ENABLE #endif return 0; @@ -656,6 +662,7 @@ ble_prox_cent_path_loss_task(void *pvParameters) path_loss = 0; } +#if MYNEWT_VAL(BLE_GATTC) rc = ble_gattc_write_no_rsp_flat(i, conn_peer[i].val_handle, &path_loss, sizeof(path_loss)); if (rc != 0) { @@ -664,6 +671,7 @@ ble_prox_cent_path_loss_task(void *pvParameters) } else { MODLOG_DFLT(INFO, "Write to alert level characteristis done"); } +#endif } } } @@ -743,7 +751,6 @@ app_main(void) /* Initialize a task to keep checking path loss of the link */ ble_prox_cent_init(); - for (int i = 0; i <= MYNEWT_VAL(BLE_MAX_CONNECTIONS); i++) { disconn_peer[i].addr = NULL; disconn_peer[i].link_lost = true; diff --git a/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/main/main.c b/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/main/main.c index 7eb301cdb25d..336f80c72297 100644 --- a/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/main/main.c +++ b/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/main/main.c @@ -270,8 +270,6 @@ void ble_prox_prph_host_task(void *param) void app_main(void) { - int rc; - /* Initialize NVS — it is used to store PHY calibration data */ esp_err_t ret = nvs_flash_init(); if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { @@ -286,9 +284,10 @@ void app_main(void) return; } +#if CONFIG_BT_NIMBLE_PROX_SERVICE /* Initialize a task to keep checking path loss of the link */ ble_svc_prox_init(); - +#endif /* Initialize the NimBLE host configuration */ ble_hs_cfg.sync_cb = ble_prox_prph_on_sync; ble_hs_cfg.reset_cb = ble_prox_prph_on_reset; @@ -301,6 +300,7 @@ void app_main(void) ble_hs_cfg.sm_sc = 1; ble_hs_cfg.sm_mitm = 1; + int rc; /* Set the default device name */ rc = ble_svc_gap_device_name_set(device_name); assert(rc == 0); diff --git a/examples/bluetooth/nimble/ble_spp/spp_client/main/main.c b/examples/bluetooth/nimble/ble_spp/spp_client/main/main.c index 4b479214c394..5b5fb206e5f2 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_client/main/main.c +++ b/examples/bluetooth/nimble/ble_spp/spp_client/main/main.c @@ -26,6 +26,7 @@ uint16_t attribute_handle[CONFIG_BT_NIMBLE_MAX_CONNECTIONS + 1]; static void ble_spp_client_scan(void); static ble_addr_t connected_addr[CONFIG_BT_NIMBLE_MAX_CONNECTIONS + 1]; +#if MYNEWT_VAL(BLE_GATTC) static void ble_spp_client_write_subscribe(const struct peer *peer) { uint8_t value[2]; @@ -90,7 +91,6 @@ ble_spp_client_set_handle(const struct peer *peer) value, sizeof(value), NULL, NULL); } - /** * Called when service discovery of the specified peer has completed. */ @@ -119,6 +119,7 @@ ble_spp_client_on_disc_complete(const struct peer *peer, int status, void *arg) ble_spp_client_scan(); #endif } +#endif /** * Initiates the GAP general discovery procedure. @@ -306,6 +307,7 @@ ble_spp_client_gap_event(struct ble_gap_event *event, void *arg) return 0; } +#if MYNEWT_VAL(BLE_GATTC) /* Perform service discovery. */ rc = peer_disc_all(event->connect.conn_handle, ble_spp_client_on_disc_complete, NULL); @@ -313,6 +315,7 @@ ble_spp_client_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif } else { /* Connection attempt failed; resume scanning. */ MODLOG_DFLT(ERROR, "Error: Connection failed; status=%d\n", @@ -421,12 +424,14 @@ void ble_client_uart_task(void *pvParameters) uart_read_bytes(UART_NUM_0, temp, event.size, portMAX_DELAY); for ( i = 0; i <= CONFIG_BT_NIMBLE_MAX_CONNECTIONS; i++) { if (attribute_handle[i] != 0) { +#if MYNEWT_VAL(BLE_GATTC) rc = ble_gattc_write_flat(i, attribute_handle[i], temp, event.size, NULL, NULL); if (rc == 0) { ESP_LOGI(tag, "Write in uart task success!"); } else { ESP_LOGI(tag, "Error in writing characteristic rc=%d", rc); } +#endif vTaskDelay(10); } } diff --git a/examples/bluetooth/nimble/ble_spp/spp_server/main/main.c b/examples/bluetooth/nimble/ble_spp/spp_server/main/main.c index b61cc2247d90..b79521be6956 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_server/main/main.c +++ b/examples/bluetooth/nimble/ble_spp/spp_server/main/main.c @@ -63,7 +63,6 @@ ble_spp_server_advertise(void) { struct ble_gap_adv_params adv_params; struct ble_hs_adv_fields fields; - const char *name; int rc; /** @@ -90,6 +89,7 @@ ble_spp_server_advertise(void) fields.tx_pwr_lvl_is_present = 1; fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO; + const char *name; name = ble_svc_gap_device_name(); fields.name = (uint8_t *)name; fields.name_len = strlen(name); @@ -412,8 +412,6 @@ static void ble_spp_uart_init(void) void app_main(void) { - int rc; - /* Initialize NVS — it is used to store PHY calibration data */ esp_err_t ret = nvs_flash_init(); if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { @@ -459,6 +457,8 @@ app_main(void) ble_hs_cfg.sm_their_key_dist = 1; #endif +#if MYNEWT_VAL(BLE_GATTS) + int rc; /* Register custom service */ rc = gatt_svr_init(); assert(rc == 0); @@ -466,6 +466,7 @@ app_main(void) /* Set the default device name. */ rc = ble_svc_gap_device_name_set("nimble-ble-spp-svr"); assert(rc == 0); +#endif /* XXX Need to have template for store */ ble_store_config_init(); diff --git a/examples/bluetooth/nimble/blecent/sdkconfig.ci.esp32c3eco7 b/examples/bluetooth/nimble/blecent/sdkconfig.ci.esp32c3eco7 index bfdd97290d25..6cf7e827068e 100644 --- a/examples/bluetooth/nimble/blecent/sdkconfig.ci.esp32c3eco7 +++ b/examples/bluetooth/nimble/blecent/sdkconfig.ci.esp32c3eco7 @@ -10,3 +10,7 @@ CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n CONFIG_BTDM_CTRL_MODE_BTDM=n CONFIG_BT_BLUEDROID_ENABLED=n CONFIG_BT_NIMBLE_ENABLED=y + +# Test Config +CONFIG_EXAMPLE_USE_CI_ADDRESS=y +CONFIG_EXAMPLE_PEER_ADDR="${CI_PIPELINE_ID}" diff --git a/examples/bluetooth/nimble/blecsc/main/main.c b/examples/bluetooth/nimble/blecsc/main/main.c index 3b69a930dc17..73c30906d96c 100644 --- a/examples/bluetooth/nimble/blecsc/main/main.c +++ b/examples/bluetooth/nimble/blecsc/main/main.c @@ -324,12 +324,14 @@ app_main(void) rc = ble_npl_callout_reset(&blecsc_measure_timer, portTICK_PERIOD_MS * 100); assert(rc == 0); +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(&csc_measurement_state); assert(rc == 0); /* Set the default device name */ rc = ble_svc_gap_device_name_set(device_name); assert(rc == 0); +#endif nimble_port_freertos_init(blecsc_host_task); diff --git a/examples/bluetooth/nimble/blehr/main/main.c b/examples/bluetooth/nimble/blehr/main/main.c index b9c7ea991f91..94b7b495fd52 100644 --- a/examples/bluetooth/nimble/blehr/main/main.c +++ b/examples/bluetooth/nimble/blehr/main/main.c @@ -293,12 +293,14 @@ void app_main(void) /* name, period/time, auto reload, timer ID, callback */ blehr_tx_timer = xTimerCreate("blehr_tx_timer", pdMS_TO_TICKS(1000), pdTRUE, (void *)0, blehr_tx_hrate); +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name */ rc = ble_svc_gap_device_name_set(device_name); assert(rc == 0); +#endif /* Start the task */ nimble_port_freertos_init(blehr_host_task); diff --git a/examples/bluetooth/nimble/bleprph_host_only/main/main.c b/examples/bluetooth/nimble/bleprph_host_only/main/main.c index 756863565a90..a03b3157ead7 100644 --- a/examples/bluetooth/nimble/bleprph_host_only/main/main.c +++ b/examples/bluetooth/nimble/bleprph_host_only/main/main.c @@ -131,7 +131,6 @@ bleprph_advertise(void) { struct ble_gap_adv_params adv_params; struct ble_hs_adv_fields fields; - const char *name; int rc; /** @@ -158,6 +157,7 @@ bleprph_advertise(void) fields.tx_pwr_lvl_is_present = 1; fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO; + const char *name; name = ble_svc_gap_device_name(); fields.name = (uint8_t *)name; fields.name_len = strlen(name); @@ -528,12 +528,14 @@ app_main(void) ble_hs_cfg.sm_their_key_dist |= BLE_SM_PAIR_KEY_DIST_ID; #endif +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name. */ rc = ble_svc_gap_device_name_set("nimble-bleprph"); assert(rc == 0); +#endif /* XXX Need to have template for store */ ble_store_config_init(); diff --git a/examples/bluetooth/nimble/bleprph_wifi_coex/main/main.c b/examples/bluetooth/nimble/bleprph_wifi_coex/main/main.c index bd2af71daa53..4d31b9d3086b 100644 --- a/examples/bluetooth/nimble/bleprph_wifi_coex/main/main.c +++ b/examples/bluetooth/nimble/bleprph_wifi_coex/main/main.c @@ -311,7 +311,6 @@ bleprph_advertise(void) { struct ble_gap_adv_params adv_params; struct ble_hs_adv_fields fields; - const char *name; int rc; /** @@ -338,6 +337,7 @@ bleprph_advertise(void) fields.tx_pwr_lvl_is_present = 1; fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO; + const char *name; name = ble_svc_gap_device_name(); fields.name = (uint8_t *)name; fields.name_len = strlen(name); @@ -525,8 +525,6 @@ void bleprph_host_task(void *param) void app_main(void) { - int rc; - /* Initialize NVS — it is used to store PHY calibration data */ esp_err_t ret = nvs_flash_init(); if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { @@ -550,12 +548,15 @@ app_main(void) ble_hs_cfg.gatts_register_cb = gatt_svr_register_cb; ble_hs_cfg.store_status_cb = ble_store_util_status_rr; +#if MYNEWT_VAL(BLE_GATTS) + int rc; rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name. */ rc = ble_svc_gap_device_name_set("nimble-bleprph"); assert(rc == 0); +#endif /* XXX Need to have template for store */ ble_store_config_init(); diff --git a/examples/bluetooth/nimble/power_save/main/main.c b/examples/bluetooth/nimble/power_save/main/main.c index 166d83de37f4..0e7e9bcf5b6a 100644 --- a/examples/bluetooth/nimble/power_save/main/main.c +++ b/examples/bluetooth/nimble/power_save/main/main.c @@ -169,7 +169,6 @@ bleprph_advertise(void) { struct ble_gap_adv_params adv_params; struct ble_hs_adv_fields fields; - const char *name; int rc; /** @@ -196,6 +195,7 @@ bleprph_advertise(void) fields.tx_pwr_lvl_is_present = 1; fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO; + const char *name; name = ble_svc_gap_device_name(); fields.name = (uint8_t *)name; fields.name_len = strlen(name); @@ -622,6 +622,7 @@ app_main(void) ble_hs_cfg.sm_their_key_dist |= BLE_SM_PAIR_KEY_DIST_ID; #endif +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); @@ -629,6 +630,7 @@ app_main(void) /* Set the default device name. */ rc = ble_svc_gap_device_name_set("nimble-bleprph"); assert(rc == 0); +#endif #endif /* XXX Need to have template for store */ diff --git a/examples/bluetooth/nimble/power_save/sdkconfig.ci.esp32c3eco7 b/examples/bluetooth/nimble/power_save/sdkconfig.ci.esp32c3eco7 index 2e432310113c..f170f0a35d12 100644 --- a/examples/bluetooth/nimble/power_save/sdkconfig.ci.esp32c3eco7 +++ b/examples/bluetooth/nimble/power_save/sdkconfig.ci.esp32c3eco7 @@ -12,3 +12,7 @@ CONFIG_BT_CTRL_MAIN_XTAL_PU_DURING_LIGHT_SLEEP=y # Enable power down of MAC and baseband in light sleep mode CONFIG_ESP_PHY_MAC_BB_PD=y + +# Test Config +CONFIG_EXAMPLE_USE_CI_ADDRESS=y +CONFIG_EXAMPLE_CI_ADDRESS_OFFSET="${CI_PIPELINE_ID}" diff --git a/examples/bluetooth/nimble/throughput_app/blecent_throughput/main/main.c b/examples/bluetooth/nimble/throughput_app/blecent_throughput/main/main.c index 49d1007a94a8..1177a9fb0ea9 100644 --- a/examples/bluetooth/nimble/throughput_app/blecent_throughput/main/main.c +++ b/examples/bluetooth/nimble/throughput_app/blecent_throughput/main/main.c @@ -945,6 +945,7 @@ app_main(void) rc = peer_init(MYNEWT_VAL(BLE_MAX_CONNECTIONS), 64, 64, 64); assert(rc == 0); #endif + /* Set the default device name. */ rc = ble_svc_gap_device_name_set("gattc-throughput"); assert(rc == 0); diff --git a/examples/bluetooth/nimble/throughput_app/bleprph_throughput/main/main.c b/examples/bluetooth/nimble/throughput_app/bleprph_throughput/main/main.c index 5ccfd6291459..e15042207fe3 100644 --- a/examples/bluetooth/nimble/throughput_app/bleprph_throughput/main/main.c +++ b/examples/bluetooth/nimble/throughput_app/bleprph_throughput/main/main.c @@ -26,10 +26,10 @@ static uint8_t ext_adv_pattern[] = { }; static uint8_t s_current_phy; -#else -static const char *device_name = "nimble_prph"; #endif +static const char *device_name = "nimble_prph"; + #define NOTIFY_THROUGHPUT_PAYLOAD 495 #define MIN_REQUIRED_MBUF 2 /* Assuming payload of 500Bytes and each mbuf can take 292Bytes. */ #define PREFERRED_MTU_VALUE 512 @@ -509,10 +509,10 @@ void app_main(void) /* Initialize Notify Task */ xTaskCreate(notify_task, "notify_task", 4096, NULL, 10, NULL); +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); -#if !(CONFIG_EXAMPLE_EXTENDED_ADV) /* Set the default device name */ rc = ble_svc_gap_device_name_set(device_name); assert(rc == 0); diff --git a/examples/openthread/ot_br/README.md b/examples/openthread/ot_br/README.md index 718fbd86d4ab..e61ed3d5e69f 100644 --- a/examples/openthread/ot_br/README.md +++ b/examples/openthread/ot_br/README.md @@ -56,11 +56,11 @@ In order to run the example on single SoC which supports both Wi-Fi and Thread, Two ways are provided to setup the Thread Border Router in this example: - Auto Start -Enable `OPENTHREAD_BR_AUTO_START`, configure the `CONFIG_EXAMPLE_WIFI_SSID` and `CONFIG_EXAMPLE_WIFI_PASSWORD` with your access point's ssid and psk. +Enable `OPENTHREAD_NETWORK_AUTO_START`, configure the `CONFIG_EXAMPLE_WIFI_SSID` and `CONFIG_EXAMPLE_WIFI_PASSWORD` with your access point's ssid and psk. The device will connect to Wi-Fi and form a Thread network automatically after boot up. - Manual mode -Disable `OPENTHREAD_BR_AUTO_START` and enable `OPENTHREAD_CLI_ESP_EXTENSION`. `wifi` command will be added for connecting the device to the Wi-Fi network. +Disable `OPENTHREAD_NETWORK_AUTO_START` and enable `OPENTHREAD_CLI_ESP_EXTENSION`. `wifi` command will be added for connecting the device to the Wi-Fi network. If the `CONFIG_EXAMPLE_CONNECT_ETHERNET` option is enabled, the device will connect to `Ethernet`, form a Thread network and act as a Ethernet based Thread Border Router. @@ -71,14 +71,14 @@ Build the project and flash it to the board, then run monitor tool to view seria ``` idf.py -p PORT build flash monitor ``` -If the `OPENTHREAD_BR_AUTO_START` option is enabled, The device will be connected to the configured Wi-Fi and Thread network automatically then act as the border router. +If the `OPENTHREAD_NETWORK_AUTO_START` option is enabled, The device will be connected to the configured Wi-Fi and Thread network automatically then act as the border router. Otherwise, you need to manually configure the networks with CLI commands. `wifi` command can be used to configure the Wi-Fi network. ```bash -> wifi +esp32s3> ot wifi --wifi parameter--- connect -s : wifi ssid @@ -96,7 +96,7 @@ Done To join a Wi-Fi network, please use the `wifi connect` command: ```bash -> wifi connect -s threadcertAP -p threadcertAP +esp32s3> ot wifi connect -s threadcertAP -p threadcertAP ssid: threadcertAP psk: threadcertAP I (11331) wifi:wifi driver task: 3ffd06e4, prio:23, stack:6656, core=0 @@ -117,7 +117,7 @@ Done To get the state of the Wi-Fi network: ```bash -> wifi state +esp32s3> ot wifi state connected Done ``` @@ -165,7 +165,7 @@ For mobile devices, the route table rules will be automatically configured after Now in the Thread end device, check the IP addresses: ``` -> ipaddr +esp32h2> ot ipaddr fde6:75ff:def4:3bc3:9e9e:3ef:4245:28b5 fdde:ad00:beef:0:0:ff:fe00:c402 fdde:ad00:beef:0:ad4a:9a9a:3cd6:e423 @@ -192,13 +192,13 @@ The newly introduced service registration protocol([SRP](https://datatracker.iet Now we'll publish the service `my-service._test._udp` with hostname `test0` and port 12345 ``` -> srp client host name test0 +esp32h2> ot srp client host name test0 Done -> srp client host address fde6:75ff:def4:3bc3:9e9e:3ef:4245:28b5 +esp32h2> ot srp client host address fde6:75ff:def4:3bc3:9e9e:3ef:4245:28b5 Done -> srp client service add my-service _test._udp 12345 +esp32h2> ot srp client service add my-service _test._udp 12345 Done -> srp client autostart enable +esp32h2> ot srp client autostart enable Done ``` @@ -233,7 +233,7 @@ Then get the border router's OMR prefix global unicast address(or ML-EID), and c On the border router: ``` -> ipaddr +esp32s3> ot ipaddr fdde:ad00:beef:0:0:ff:fe00:fc10 fd9b:347f:93f7:1:1003:8f00:bcc1:3038 fdde:ad00:beef:0:0:ff:fe00:fc00 @@ -245,19 +245,19 @@ Done On the Thread end device: ``` -> dns config fd9b:347f:93f7:1:1003:8f00:bcc1:3038 +esp32h2> ot dns config fd9b:347f:93f7:1:1003:8f00:bcc1:3038 (or -> dns config fdde:ad00:beef:0:f891:287:866:776) +esp32h2> ot dns config fdde:ad00:beef:0:f891:287:866:776) Done ``` Now the service published on the Host can be discovered on the Thread end device. ``` -> dns resolve FA001208.default.service.arpa. +esp32h2> ot dns resolve FA001208.default.service.arpa. DNS response for FA001208.default.service.arpa. - fdde:ad00:beef:cafe:b939:26be:7516:b87e TTL:120 Done -> dns browse _test._udp.default.service.arpa. +esp32h2> ot dns browse _test._udp.default.service.arpa. DNS browse response for _test._udp.default.service.arpa. testhost Port:5683, Priority:0, Weight:0, TTL:120 @@ -266,7 +266,7 @@ testhost TXT:[test=31, dn=616162626262] TTL:120 Done -> dns service testhost _test._udp.default.service.arpa. +esp32h2> ot dns service testhost _test._udp.default.service.arpa. DNS service resolution response for testhost for service _test._udp.default.service.arpa. Port:5683, Priority:0, Weight:0, TTL:120 Host:FA001208.default.service.arpa. diff --git a/examples/openthread/ot_br/main/Kconfig.projbuild b/examples/openthread/ot_br/main/Kconfig.projbuild index 45e682cb925e..ca427f349845 100644 --- a/examples/openthread/ot_br/main/Kconfig.projbuild +++ b/examples/openthread/ot_br/main/Kconfig.projbuild @@ -1,13 +1,5 @@ menu "OpenThread Border Router Example" - config OPENTHREAD_BR_AUTO_START - bool 'Enable the automatic start mode in Thread Border Router.' - default n - help - If enabled, The Thread Border Router will connect to Wi-Fi with pre-configured - SSID and PSK, and then form a Thread network automatically. Otherwise, user need - to configure Wi-Fi and Thread manually. - config OPENTHREAD_SUPPORT_HW_RESET_RCP bool 'Enable hardware RCP resetting' default n @@ -20,33 +12,4 @@ menu "OpenThread Border Router Example" depends on OPENTHREAD_SUPPORT_HW_RESET_RCP default 7 - menu "External coexist wire type and pin config" - config EXTERNAL_COEX_WIRE_TYPE - int "The wire_type of external coexist" - depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE - default 3 - range 0 3 - help - Select wire_type for external coexist, the wire_type define in external_coex_wire_t. - - config EXTERNAL_COEX_REQUEST_PIN - int "The number of external coexist request pin" - depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE && (EXTERNAL_COEX_WIRE_TYPE >= 0) - default 0 - - config EXTERNAL_COEX_GRANT_PIN - int "The number of external coexist grant pin" - depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE && (EXTERNAL_COEX_WIRE_TYPE >= 1) - default 1 - - config EXTERNAL_COEX_PRIORITY_PIN - int "The number of external coexist priority pin" - depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE && (EXTERNAL_COEX_WIRE_TYPE >= 2) - default 2 - - config EXTERNAL_COEX_TX_LINE_PIN - int "The number of external coexist tx_line pin" - depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE && (EXTERNAL_COEX_WIRE_TYPE = 3) - default 3 - endmenu # External coexist wire type and pin config endmenu diff --git a/examples/openthread/ot_br/main/esp_ot_br.c b/examples/openthread/ot_br/main/esp_ot_br.c index ffcfd3915791..7cfcca642bb7 100644 --- a/examples/openthread/ot_br/main/esp_ot_br.c +++ b/examples/openthread/ot_br/main/esp_ot_br.c @@ -17,50 +17,31 @@ #include "sdkconfig.h" #include "esp_check.h" +#include "esp_coexist.h" #include "esp_err.h" #include "esp_event.h" #include "esp_log.h" #include "esp_netif.h" #include "esp_openthread.h" -#include "esp_openthread_border_router.h" -#include "esp_openthread_cli.h" #include "esp_openthread_lock.h" #include "esp_openthread_netif_glue.h" +#include "esp_openthread_spinel.h" #include "esp_openthread_types.h" #if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION #include "esp_ot_cli_extension.h" #endif // CONFIG_OPENTHREAD_CLI_ESP_EXTENSION #include "esp_ot_config.h" -#include "esp_ot_wifi_cmd.h" #include "esp_vfs_dev.h" #include "esp_vfs_eventfd.h" -#include "esp_wifi.h" #include "mdns.h" #include "nvs_flash.h" -#include "protocol_examples_common.h" -#include "driver/gpio.h" -#include "driver/uart.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "hal/uart_types.h" -#include "openthread/error.h" -#include "openthread/logging.h" -#include "openthread/tasklet.h" +#include "ot_examples_br.h" +#include "ot_examples_common.h" #if CONFIG_OPENTHREAD_STATE_INDICATOR_ENABLE #include "ot_led_strip.h" #endif -#if CONFIG_OPENTHREAD_BR_AUTO_START -#include "example_common_private.h" -#include "protocol_examples_common.h" -#endif - -#if !CONFIG_OPENTHREAD_BR_AUTO_START && CONFIG_EXAMPLE_CONNECT_ETHERNET -// TZ-1109: Add a menchanism for connecting ETH manually. -#error Currently we do not support a manual way to connect ETH, if you want to use ETH, please enable OPENTHREAD_BR_AUTO_START. -#endif - #define TAG "esp_ot_br" #if CONFIG_OPENTHREAD_SUPPORT_HW_RESET_RCP @@ -83,116 +64,6 @@ static void rcp_failure_hardware_reset_handler(void) } #endif -#if CONFIG_EXTERNAL_COEX_ENABLE -static void ot_br_external_coexist_init(void) -{ - esp_external_coex_gpio_set_t gpio_pin = ESP_OPENTHREAD_DEFAULT_EXTERNAL_COEX_CONFIG(); - esp_external_coex_set_work_mode(EXTERNAL_COEX_LEADER_ROLE); - ESP_ERROR_CHECK(esp_enable_extern_coex_gpio_pin(CONFIG_EXTERNAL_COEX_WIRE_TYPE, gpio_pin)); -} -#endif /* CONFIG_EXTERNAL_COEX_ENABLE */ - -static void ot_task_worker(void *aContext) -{ - esp_openthread_platform_config_t config = { - .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(), - .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(), - .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(), - }; - - esp_netif_config_t cfg = ESP_NETIF_DEFAULT_OPENTHREAD(); - esp_netif_t *openthread_netif = esp_netif_new(&cfg); - assert(openthread_netif != NULL); - - // Initialize the OpenThread stack - ESP_ERROR_CHECK(esp_openthread_init(&config)); - ESP_ERROR_CHECK(esp_netif_attach(openthread_netif, esp_openthread_netif_glue_init(&config))); - esp_openthread_lock_acquire(portMAX_DELAY); -#if CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC - // The OpenThread log level directly matches ESP log level - (void)otLoggingSetLevel(CONFIG_LOG_DEFAULT_LEVEL); -#endif // CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC -#if CONFIG_OPENTHREAD_CLI - esp_openthread_cli_init(); -#if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION - esp_cli_custom_command_init(); -#endif // CONFIG_OPENTHREAD_CLI_ESP_EXTENSION - esp_openthread_cli_create_task(); -#endif // CONFIG_OPENTHREAD_CLI - esp_openthread_lock_release(); - - // Run the main loop - esp_openthread_launch_mainloop(); - - // Clean up - esp_openthread_netif_glue_deinit(); - esp_netif_destroy(openthread_netif); - esp_vfs_eventfd_unregister(); - vTaskDelete(NULL); -} - -void ot_br_init(void *ctx) -{ -#if CONFIG_OPENTHREAD_CLI_WIFI - ESP_ERROR_CHECK(esp_ot_wifi_config_init()); -#endif -#if CONFIG_OPENTHREAD_BR_AUTO_START -#if CONFIG_EXAMPLE_CONNECT_WIFI || CONFIG_EXAMPLE_CONNECT_ETHERNET - bool wifi_or_ethernet_connected = false; -#else -#error No backbone netif! -#endif -#if CONFIG_EXAMPLE_CONNECT_WIFI - char wifi_ssid[32] = ""; - char wifi_password[64] = ""; - if (esp_ot_wifi_config_get_ssid(wifi_ssid) == ESP_OK) { - ESP_LOGI(TAG, "use the Wi-Fi config from NVS"); - esp_ot_wifi_config_get_password(wifi_password); - } else { - ESP_LOGI(TAG, "use the Wi-Fi config from Kconfig"); - strcpy(wifi_ssid, CONFIG_EXAMPLE_WIFI_SSID); - strcpy(wifi_password, CONFIG_EXAMPLE_WIFI_PASSWORD); - } - if (esp_ot_wifi_connect(wifi_ssid, wifi_password) == ESP_OK) { - wifi_or_ethernet_connected = true; - } else { - ESP_LOGE(TAG, "Fail to connect to Wi-Fi, please try again manually"); - } -#endif -#if CONFIG_EXAMPLE_CONNECT_ETHERNET - ESP_ERROR_CHECK(example_ethernet_connect()); - wifi_or_ethernet_connected = true; -#endif -#endif // CONFIG_OPENTHREAD_BR_AUTO_START - -#if CONFIG_EXTERNAL_COEX_ENABLE - ot_br_external_coexist_init(); -#endif // CONFIG_EXTERNAL_COEX_ENABLE - ESP_ERROR_CHECK(mdns_init()); - ESP_ERROR_CHECK(mdns_hostname_set("esp-ot-br")); - - esp_openthread_lock_acquire(portMAX_DELAY); -#if CONFIG_OPENTHREAD_STATE_INDICATOR_ENABLE - ESP_ERROR_CHECK(esp_openthread_state_indicator_init(esp_openthread_get_instance())); -#endif -#if CONFIG_OPENTHREAD_BR_AUTO_START - if (wifi_or_ethernet_connected) { - esp_openthread_set_backbone_netif(get_example_netif()); - ESP_ERROR_CHECK(esp_openthread_border_router_init()); -#if CONFIG_EXAMPLE_CONNECT_WIFI - esp_ot_wifi_border_router_init_flag_set(true); -#endif - otOperationalDatasetTlvs dataset; - otError error = otDatasetGetActiveTlvs(esp_openthread_get_instance(), &dataset); - ESP_ERROR_CHECK(esp_openthread_auto_start((error == OT_ERROR_NONE) ? &dataset : NULL)); - } else { - ESP_LOGE(TAG, "Auto-start mode failed, please try to start manually"); - } -#endif // CONFIG_OPENTHREAD_BR_AUTO_START - esp_openthread_lock_release(); - vTaskDelete(NULL); -} - void app_main(void) { // Used eventfds: @@ -218,9 +89,41 @@ void app_main(void) ESP_ERROR_CHECK(nvs_flash_init()); ESP_ERROR_CHECK(esp_netif_init()); ESP_ERROR_CHECK(esp_event_loop_create_default()); + ESP_ERROR_CHECK(mdns_init()); + ESP_ERROR_CHECK(mdns_hostname_set("esp-ot-br")); #if CONFIG_OPENTHREAD_SUPPORT_HW_RESET_RCP esp_openthread_register_rcp_failure_handler(rcp_failure_hardware_reset_handler); #endif - xTaskCreate(ot_task_worker, "ot_br_main", 8192, xTaskGetCurrentTaskHandle(), 5, NULL); - xTaskCreate(ot_br_init, "ot_br_init", 6144, NULL, 4, NULL); + +#if CONFIG_OPENTHREAD_CLI + ot_console_start(); +#endif + +#if CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE + ot_external_coexist_init(); +#endif + + static esp_openthread_config_t config = { + .netif_config = ESP_NETIF_DEFAULT_OPENTHREAD(), + .platform_config = { + .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(), + .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(), + .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(), + }, + }; + + ESP_ERROR_CHECK(esp_openthread_start(&config)); + esp_netif_set_default_netif(esp_openthread_get_netif()); +#if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION + esp_cli_custom_command_init(); +#endif +#if CONFIG_OPENTHREAD_BORDER_ROUTER_AUTO_START + ESP_ERROR_CHECK(esp_openthread_border_router_start()); +#if CONFIG_ESP_COEX_SW_COEXIST_ENABLE && CONFIG_SOC_IEEE802154_SUPPORTED + ESP_ERROR_CHECK(esp_coex_wifi_i154_enable()); +#endif +#endif +#if CONFIG_OPENTHREAD_NETWORK_AUTO_START + ot_network_auto_start(); +#endif } diff --git a/examples/openthread/ot_br/main/esp_ot_config.h b/examples/openthread/ot_br/main/esp_ot_config.h index b7372f49439c..a1670b0c189c 100644 --- a/examples/openthread/ot_br/main/esp_ot_config.h +++ b/examples/openthread/ot_br/main/esp_ot_config.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: CC0-1.0 * @@ -68,39 +68,10 @@ } #endif // CONFIG_OPENTHREAD_RADIO_SPINEL_UART OR CONFIG_OPENTHREAD_RADIO_SPINEL_SPI -#if CONFIG_IDF_TARGET_ESP32C2 && CONFIG_XTAL_FREQ_26 -#define HOST_BAUD_RATE 74880 -#else -#define HOST_BAUD_RATE 115200 -#endif - -#if CONFIG_OPENTHREAD_CONSOLE_TYPE_UART -#define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ - { \ - .host_connection_mode = HOST_CONNECTION_MODE_CLI_UART, \ - .host_uart_config = { \ - .port = 0, \ - .uart_config = \ - { \ - .baud_rate = HOST_BAUD_RATE, \ - .data_bits = UART_DATA_8_BITS, \ - .parity = UART_PARITY_DISABLE, \ - .stop_bits = UART_STOP_BITS_1, \ - .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, \ - .rx_flow_ctrl_thresh = 0, \ - .source_clk = UART_SCLK_DEFAULT, \ - }, \ - .rx_pin = UART_PIN_NO_CHANGE, \ - .tx_pin = UART_PIN_NO_CHANGE, \ - }, \ - } -#elif CONFIG_OPENTHREAD_CONSOLE_TYPE_USB_SERIAL_JTAG #define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ { \ - .host_connection_mode = HOST_CONNECTION_MODE_CLI_USB, \ - .host_usb_config = USB_SERIAL_JTAG_DRIVER_CONFIG_DEFAULT(), \ + .host_connection_mode = HOST_CONNECTION_MODE_NONE, \ } -#endif #define ESP_OPENTHREAD_DEFAULT_PORT_CONFIG() \ { \ @@ -108,33 +79,3 @@ .netif_queue_size = 10, \ .task_queue_size = 10, \ } - -#if CONFIG_EXTERNAL_COEX_ENABLE -#if CONFIG_EXTERNAL_COEX_WIRE_TYPE == EXTERNAL_COEXIST_WIRE_1 -#define ESP_OPENTHREAD_DEFAULT_EXTERNAL_COEX_CONFIG() \ - { \ - .request = CONFIG_EXTERNAL_COEX_REQUEST_PIN, \ - } -#elif CONFIG_EXTERNAL_COEX_WIRE_TYPE == EXTERNAL_COEXIST_WIRE_2 -#define ESP_OPENTHREAD_DEFAULT_EXTERNAL_COEX_CONFIG() \ - { \ - .request = CONFIG_EXTERNAL_COEX_REQUEST_PIN, \ - .grant = CONFIG_EXTERNAL_COEX_GRANT_PIN, \ - } -#elif CONFIG_EXTERNAL_COEX_WIRE_TYPE == EXTERNAL_COEXIST_WIRE_3 -#define ESP_OPENTHREAD_DEFAULT_EXTERNAL_COEX_CONFIG() \ - { \ - .request = CONFIG_EXTERNAL_COEX_REQUEST_PIN, \ - .priority = CONFIG_EXTERNAL_COEX_PRIORITY_PIN, \ - .grant = CONFIG_EXTERNAL_COEX_GRANT_PIN, \ - } -#elif CONFIG_EXTERNAL_COEX_WIRE_TYPE == EXTERNAL_COEXIST_WIRE_4 -#define ESP_OPENTHREAD_DEFAULT_EXTERNAL_COEX_CONFIG() \ - { \ - .request = CONFIG_EXTERNAL_COEX_REQUEST_PIN, \ - .priority = CONFIG_EXTERNAL_COEX_PRIORITY_PIN, \ - .grant = CONFIG_EXTERNAL_COEX_GRANT_PIN, \ - .tx_line = CONFIG_EXTERNAL_COEX_TX_LINE_PIN, \ - } -#endif -#endif // CONFIG_EXTERNAL_COEX_ENABLE diff --git a/examples/openthread/ot_br/main/idf_component.yml b/examples/openthread/ot_br/main/idf_component.yml index dff9291048a8..b00b26c7bb34 100644 --- a/examples/openthread/ot_br/main/idf_component.yml +++ b/examples/openthread/ot_br/main/idf_component.yml @@ -1,7 +1,7 @@ ## IDF Component Manager Manifest File dependencies: espressif/esp_ot_cli_extension: - version: "~1.3.0" + version: "~1.4.0" espressif/mdns: "^1.0.3" ## Required IDF version idf: @@ -10,3 +10,7 @@ dependencies: path: ${IDF_PATH}/examples/common_components/protocol_examples_common ot_led: path: ${IDF_PATH}/examples/openthread/ot_common_components/ot_led + ot_examples_br: + path: ${IDF_PATH}/examples/openthread/ot_common_components/ot_examples_br + ot_examples_common: + path: ${IDF_PATH}/examples/openthread/ot_common_components/ot_examples_common diff --git a/examples/openthread/ot_br/partitions.csv b/examples/openthread/ot_br/partitions.csv index 46c7857278a7..376458ad8b8a 100644 --- a/examples/openthread/ot_br/partitions.csv +++ b/examples/openthread/ot_br/partitions.csv @@ -2,4 +2,4 @@ # Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap nvs, data, nvs, 0x9000, 0x6000, phy_init, data, phy, 0xf000, 0x1000, -factory, app, factory, 0x10000, 1800K, +factory, app, factory, 0x10000, 1900K, diff --git a/examples/openthread/ot_br/sdkconfig.ci.ext_coex b/examples/openthread/ot_br/sdkconfig.ci.ext_coex index 10e03f180efd..aa3956957560 100644 --- a/examples/openthread/ot_br/sdkconfig.ci.ext_coex +++ b/examples/openthread/ot_br/sdkconfig.ci.ext_coex @@ -1,2 +1,2 @@ -CONFIG_EXTERNAL_COEX_ENABLE=y +CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE=y CONFIG_ESP_COEX_SW_COEXIST_ENABLE=n diff --git a/examples/openthread/ot_br/sdkconfig.ci.spinel_trel_ext_coex b/examples/openthread/ot_br/sdkconfig.ci.spinel_trel_ext_coex index 571881d7f6cc..8fd4485992b1 100644 --- a/examples/openthread/ot_br/sdkconfig.ci.spinel_trel_ext_coex +++ b/examples/openthread/ot_br/sdkconfig.ci.spinel_trel_ext_coex @@ -1,2 +1,2 @@ CONFIG_OPENTHREAD_RADIO_TREL=y -CONFIG_EXTERNAL_COEX_ENABLE=y +CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE=y diff --git a/examples/openthread/ot_br/sdkconfig.defaults b/examples/openthread/ot_br/sdkconfig.defaults index 2b17031c2bfb..7fe886d91f3f 100644 --- a/examples/openthread/ot_br/sdkconfig.defaults +++ b/examples/openthread/ot_br/sdkconfig.defaults @@ -25,6 +25,8 @@ CONFIG_MBEDTLS_ECJPAKE_C=y CONFIG_OPENTHREAD_ENABLED=y CONFIG_OPENTHREAD_BORDER_ROUTER=y CONFIG_OPENTHREAD_RADIO_SPINEL_UART=y +CONFIG_OPENTHREAD_TASK_SIZE=8192 +CONFIG_OPENTHREAD_CONSOLE_ENABLE=n # end of OpenThread # @@ -54,4 +56,5 @@ CONFIG_EXAMPLE_CONNECT_THREAD=n # ESP System Settings # CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=3584 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=6144 # end of ESP System Settings diff --git a/examples/openthread/ot_br/sdkconfig.defaults.esp32p4 b/examples/openthread/ot_br/sdkconfig.defaults.esp32p4 index 0bf7855bcc00..3b161864c7f3 100644 --- a/examples/openthread/ot_br/sdkconfig.defaults.esp32p4 +++ b/examples/openthread/ot_br/sdkconfig.defaults.esp32p4 @@ -1,5 +1,6 @@ # Enable BR auto start for Ethernet builds -CONFIG_OPENTHREAD_BR_AUTO_START=y +CONFIG_OPENTHREAD_NETWORK_AUTO_START=y +CONFIG_OPENTHREAD_BORDER_ROUTER_AUTO_START=y # Enable PPP support as a workaround to ensure LWIP thread-lib compatibility for Ethernet builds CONFIG_LWIP_PPP_SUPPORT=y diff --git a/examples/openthread/ot_ci_function.py b/examples/openthread/ot_ci_function.py index 6b8e9567f56b..0c438e9f601c 100644 --- a/examples/openthread/ot_ci_function.py +++ b/examples/openthread/ot_ci_function.py @@ -168,7 +168,7 @@ def getDataset(dut: IdfDut) -> str: def init_thread(dut: IdfDut) -> None: - dut.expect('>', timeout=10) + dut.expect('OpenThread attached to netif', timeout=10) wait(dut, 3) reset_thread(dut) @@ -176,7 +176,6 @@ def init_thread(dut: IdfDut) -> None: def reset_thread(dut: IdfDut) -> None: execute_command(dut, 'factoryreset') dut.expect('OpenThread attached to netif', timeout=20) - dut.expect('>', timeout=10) wait(dut, 3) clean_buffer(dut) @@ -636,9 +635,9 @@ def get_nat64prefix(br: IdfDut) -> str: return str(nat64prefix) -def execute_command(dut: IdfDut, command: str) -> None: +def execute_command(dut: IdfDut, command: str, prefix: str = 'ot ') -> None: clean_buffer(dut) - dut.write(command) + dut.write(prefix + command) def get_ouput_string(dut: IdfDut, command: str, wait_time: int) -> str: diff --git a/examples/openthread/ot_cli/README.md b/examples/openthread/ot_cli/README.md index 2a02e8b89b70..4ffe0a0131e2 100644 --- a/examples/openthread/ot_cli/README.md +++ b/examples/openthread/ot_cli/README.md @@ -37,7 +37,7 @@ Now you'll get an OpenThread command line shell. The `help` command will print all of the supported commands. ```bash -> help +esp32h2> ot help I(7058) OPENTHREAD:[INFO]-CLI-----: execute command: help bbr bufferinfo @@ -71,51 +71,51 @@ To run this example, at least two ESP32-H2 boards flashed with this ot_cli examp On the first device, run the following commands: ```bash -> factoryreset +esp32h2> ot factoryreset ... # the device will reboot -> dataset init new +esp32h2> ot dataset init new Done -> dataset commit active +esp32h2> ot dataset commit active Done -> ifconfig up +esp32h2> ot ifconfig up Done -> thread start +esp32h2> ot thread start Done # After some seconds -> state +esp32h2> ot state leader Done ``` Now the first device has formed a Thread network as a leader. Get some information which will be used in next steps: ```bash -> ipaddr +esp32h2> ot ipaddr fdde:ad00:beef:0:0:ff:fe00:fc00 fdde:ad00:beef:0:0:ff:fe00:8000 fdde:ad00:beef:0:a7c6:6311:9c8c:271b fe80:0:0:0:5c27:a723:7115:c8f8 # Get the Active Dataset -> dataset active -x +esp32h2> ot dataset active -x 0e080000000000010000000300001835060004001fffe00208fe7bb701f5f1125d0708fd75cbde7c6647bd0510b3914792d44f45b6c7d76eb9306eec94030f4f70656e5468726561642d35383332010258320410e35c581af5029b054fc904a24c2b27700c0402a0fff8 ``` On the second device, set the active dataset from leader, and start Thread interface: ```bash -> factoryreset +esp32h2> ot factoryreset ... # the device will reboot -> dataset set active 0e080000000000010000000300001835060004001fffe00208fe7bb701f5f1125d0708fd75cbde7c6647bd0510b3914792d44f45b6c7d76eb9306eec94030f4f70656e5468726561642d35383332010258320410e35c581af5029b054fc904a24c2b27700c0402a0fff8 -> ifconfig up +esp32h2> ot dataset set active 0e080000000000010000000300001835060004001fffe00208fe7bb701f5f1125d0708fd75cbde7c6647bd0510b3914792d44f45b6c7d76eb9306eec94030f4f70656e5468726561642d35383332010258320410e35c581af5029b054fc904a24c2b27700c0402a0fff8 +esp32h2> ot ifconfig up Done -> thread start +esp32h2> ot thread start Done # After some seconds -> state +esp32h2> ot state router # child is also a valid state Done ``` diff --git a/examples/openthread/ot_cli/main/Kconfig.projbuild b/examples/openthread/ot_cli/main/Kconfig.projbuild deleted file mode 100644 index 23aba5e8ceb0..000000000000 --- a/examples/openthread/ot_cli/main/Kconfig.projbuild +++ /dev/null @@ -1,9 +0,0 @@ -menu "OpenThread CLI Example" - - config OPENTHREAD_AUTO_START - bool 'Enable the automatic start mode.' - default n - help - If enabled, the Openthread Device will create or connect to thread network with pre-configured - network parameters automatically. Otherwise, user need to configure Thread via CLI command manually. -endmenu diff --git a/examples/openthread/ot_cli/main/esp_ot_cli.c b/examples/openthread/ot_cli/main/esp_ot_cli.c index 96a8d1e22ccd..ee83bcc22de7 100644 --- a/examples/openthread/ot_cli/main/esp_ot_cli.c +++ b/examples/openthread/ot_cli/main/esp_ot_cli.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: CC0-1.0 * @@ -23,21 +23,13 @@ #include "esp_netif.h" #include "esp_netif_types.h" #include "esp_openthread.h" -#include "esp_openthread_cli.h" #include "esp_openthread_lock.h" #include "esp_openthread_netif_glue.h" #include "esp_openthread_types.h" #include "esp_ot_config.h" #include "esp_vfs_eventfd.h" -#include "driver/uart.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "hal/uart_types.h" #include "nvs_flash.h" -#include "openthread/cli.h" -#include "openthread/instance.h" -#include "openthread/logging.h" -#include "openthread/tasklet.h" +#include "ot_examples_common.h" #if CONFIG_OPENTHREAD_STATE_INDICATOR_ENABLE #include "ot_led_strip.h" @@ -49,68 +41,6 @@ #define TAG "ot_esp_cli" -static esp_netif_t *init_openthread_netif(const esp_openthread_platform_config_t *config) -{ - esp_netif_config_t cfg = ESP_NETIF_DEFAULT_OPENTHREAD(); - esp_netif_t *netif = esp_netif_new(&cfg); - assert(netif != NULL); - ESP_ERROR_CHECK(esp_netif_attach(netif, esp_openthread_netif_glue_init(config))); - - return netif; -} - -static void ot_task_worker(void *aContext) -{ - esp_openthread_platform_config_t config = { - .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(), - .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(), - .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(), - }; - - // Initialize the OpenThread stack - ESP_ERROR_CHECK(esp_openthread_init(&config)); - -#if CONFIG_OPENTHREAD_STATE_INDICATOR_ENABLE - ESP_ERROR_CHECK(esp_openthread_state_indicator_init(esp_openthread_get_instance())); -#endif - -#if CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC - // The OpenThread log level directly matches ESP log level - (void)otLoggingSetLevel(CONFIG_LOG_DEFAULT_LEVEL); -#endif - // Initialize the OpenThread cli -#if CONFIG_OPENTHREAD_CLI - esp_openthread_cli_init(); -#endif - - esp_netif_t *openthread_netif; - // Initialize the esp_netif bindings - openthread_netif = init_openthread_netif(&config); - esp_netif_set_default_netif(openthread_netif); - -#if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION - esp_cli_custom_command_init(); -#endif // CONFIG_OPENTHREAD_CLI_ESP_EXTENSION - - // Run the main loop -#if CONFIG_OPENTHREAD_CLI - esp_openthread_cli_create_task(); -#endif -#if CONFIG_OPENTHREAD_AUTO_START - otOperationalDatasetTlvs dataset; - otError error = otDatasetGetActiveTlvs(esp_openthread_get_instance(), &dataset); - ESP_ERROR_CHECK(esp_openthread_auto_start((error == OT_ERROR_NONE) ? &dataset : NULL)); -#endif - esp_openthread_launch_mainloop(); - - // Clean up - esp_openthread_netif_glue_deinit(); - esp_netif_destroy(openthread_netif); - - esp_vfs_eventfd_unregister(); - vTaskDelete(NULL); -} - void app_main(void) { // Used eventfds: @@ -125,5 +55,25 @@ void app_main(void) ESP_ERROR_CHECK(esp_event_loop_create_default()); ESP_ERROR_CHECK(esp_netif_init()); ESP_ERROR_CHECK(esp_vfs_eventfd_register(&eventfd_config)); - xTaskCreate(ot_task_worker, "ot_cli_main", 10240, xTaskGetCurrentTaskHandle(), 5, NULL); + +#if CONFIG_OPENTHREAD_CLI + ot_console_start(); +#endif + + static esp_openthread_config_t config = { + .netif_config = ESP_NETIF_DEFAULT_OPENTHREAD(), + .platform_config = { + .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(), + .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(), + .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(), + }, + }; + + ESP_ERROR_CHECK(esp_openthread_start(&config)); +#if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION + esp_cli_custom_command_init(); +#endif +#if CONFIG_OPENTHREAD_NETWORK_AUTO_START + ot_network_auto_start(); +#endif } diff --git a/examples/openthread/ot_cli/main/esp_ot_config.h b/examples/openthread/ot_cli/main/esp_ot_config.h index 0248a39af187..cd509e9e1707 100644 --- a/examples/openthread/ot_cli/main/esp_ot_config.h +++ b/examples/openthread/ot_cli/main/esp_ot_config.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: CC0-1.0 * @@ -44,33 +44,10 @@ } #endif -#if CONFIG_OPENTHREAD_CONSOLE_TYPE_UART -#define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ - { \ - .host_connection_mode = HOST_CONNECTION_MODE_CLI_UART, \ - .host_uart_config = { \ - .port = 0, \ - .uart_config = \ - { \ - .baud_rate = 115200, \ - .data_bits = UART_DATA_8_BITS, \ - .parity = UART_PARITY_DISABLE, \ - .stop_bits = UART_STOP_BITS_1, \ - .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, \ - .rx_flow_ctrl_thresh = 0, \ - .source_clk = UART_SCLK_DEFAULT, \ - }, \ - .rx_pin = UART_PIN_NO_CHANGE, \ - .tx_pin = UART_PIN_NO_CHANGE, \ - }, \ - } -#elif CONFIG_OPENTHREAD_CONSOLE_TYPE_USB_SERIAL_JTAG #define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ { \ - .host_connection_mode = HOST_CONNECTION_MODE_CLI_USB, \ - .host_usb_config = USB_SERIAL_JTAG_DRIVER_CONFIG_DEFAULT(), \ + .host_connection_mode = HOST_CONNECTION_MODE_NONE, \ } -#endif #define ESP_OPENTHREAD_DEFAULT_PORT_CONFIG() \ { \ diff --git a/examples/openthread/ot_cli/main/idf_component.yml b/examples/openthread/ot_cli/main/idf_component.yml index 06b75f0c81d6..079266490f06 100644 --- a/examples/openthread/ot_cli/main/idf_component.yml +++ b/examples/openthread/ot_cli/main/idf_component.yml @@ -1,8 +1,10 @@ ## IDF Component Manager Manifest File dependencies: espressif/esp_ot_cli_extension: - version: "~1.2.0" + version: "~1.4.0" idf: version: ">=4.1.0" ot_led: path: ${IDF_PATH}/examples/openthread/ot_common_components/ot_led + ot_examples_common: + path: ${IDF_PATH}/examples/openthread/ot_common_components/ot_examples_common diff --git a/examples/openthread/ot_cli/sdkconfig.ci.ext_coex b/examples/openthread/ot_cli/sdkconfig.ci.ext_coex index 55c9b2374fee..6b04e74e9d4d 100644 --- a/examples/openthread/ot_cli/sdkconfig.ci.ext_coex +++ b/examples/openthread/ot_cli/sdkconfig.ci.ext_coex @@ -1 +1 @@ -CONFIG_EXTERNAL_COEX_ENABLE=y +CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE=y diff --git a/examples/openthread/ot_cli/sdkconfig.defaults b/examples/openthread/ot_cli/sdkconfig.defaults index 7b724c1c89d1..f8fd9ed374ce 100644 --- a/examples/openthread/ot_cli/sdkconfig.defaults +++ b/examples/openthread/ot_cli/sdkconfig.defaults @@ -23,6 +23,8 @@ CONFIG_MBEDTLS_ECJPAKE_C=y CONFIG_OPENTHREAD_ENABLED=y CONFIG_OPENTHREAD_BORDER_ROUTER=n CONFIG_OPENTHREAD_DNS64_CLIENT=y +CONFIG_OPENTHREAD_TASK_SIZE=10240 +CONFIG_OPENTHREAD_CONSOLE_ENABLE=n # end of OpenThread # @@ -33,3 +35,9 @@ CONFIG_LWIP_IPV6_NUM_ADDRESSES=8 CONFIG_LWIP_MULTICAST_PING=y CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM=y # end of lwIP + +# +# ESP System Settings +# +CONFIG_ESP_MAIN_TASK_STACK_SIZE=6144 +# end of ESP System Settings diff --git a/examples/openthread/ot_common_components/ot_examples_br/CMakeLists.txt b/examples/openthread/ot_common_components/ot_examples_br/CMakeLists.txt new file mode 100644 index 000000000000..fbda672d96de --- /dev/null +++ b/examples/openthread/ot_common_components/ot_examples_br/CMakeLists.txt @@ -0,0 +1,9 @@ +set(srcs "") + +if(CONFIG_OPENTHREAD_BORDER_ROUTER_AUTO_START) + list(APPEND srcs "ot_examples_br.c") +endif() + +idf_component_register(SRCS "${srcs}" + INCLUDE_DIRS "include" + PRIV_REQUIRES openthread protocol_examples_common) diff --git a/examples/openthread/ot_common_components/ot_examples_br/Kconfig.projbuild b/examples/openthread/ot_common_components/ot_examples_br/Kconfig.projbuild new file mode 100644 index 000000000000..2835110a1f53 --- /dev/null +++ b/examples/openthread/ot_common_components/ot_examples_br/Kconfig.projbuild @@ -0,0 +1,12 @@ +menu "OpenThread Border Router Config" + depends on OPENTHREAD_BORDER_ROUTER + + config OPENTHREAD_BORDER_ROUTER_AUTO_START + depends on OPENTHREAD_BORDER_ROUTER + bool 'Enable the border router auto start' + default n + help + If enabled, the program will automatically connect to the backbone network and + initialize the border router at startup. + +endmenu diff --git a/examples/openthread/ot_common_components/ot_examples_br/include/ot_examples_br.h b/examples/openthread/ot_common_components/ot_examples_br/include/ot_examples_br.h new file mode 100644 index 000000000000..6851bfdbb744 --- /dev/null +++ b/examples/openthread/ot_common_components/ot_examples_br/include/ot_examples_br.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: CC0-1.0 + * + * OpenThread Command Line Example + * + * This example code is in the Public Domain (or CC0 licensed, at your option.) + * + * Unless required by applicable law or agreed to in writing, this + * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. +*/ + +#include "esp_err.h" +#include "esp_openthread.h" + +/** + * @brief Start the border router features of OpenThread. + * + * @note Calling this function will make the device connect to the Wi-Fi or Ethernet, + * and initialize the border router feature. + * + * @return + * - ESP_OK on success. + * - ESP_FAIL on failure. + * + */ +esp_err_t esp_openthread_border_router_start(void); + +/** + * @brief Stop the border router features of OpenThread. + * + * @note Calling this function will make the device deinitialize the border router feature. + * + */ +void esp_openthread_border_router_stop(void); diff --git a/examples/openthread/ot_common_components/ot_examples_br/ot_examples_br.c b/examples/openthread/ot_common_components/ot_examples_br/ot_examples_br.c new file mode 100644 index 000000000000..77ef1d1900af --- /dev/null +++ b/examples/openthread/ot_common_components/ot_examples_br/ot_examples_br.c @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: CC0-1.0 + * + * OpenThread Command Line Example + * + * This example code is in the Public Domain (or CC0 licensed, at your option.) + * + * Unless required by applicable law or agreed to in writing, this + * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. +*/ + +#include "ot_examples_br.h" +#include "esp_check.h" +#include "esp_err.h" +#include "esp_openthread.h" +#include "esp_openthread_lock.h" +#include "esp_openthread_border_router.h" +#include "protocol_examples_common.h" + +#define TAG "ot_examples_br" + +#if CONFIG_OPENTHREAD_CLI_WIFI +#error "CONFIG_OPENTHREAD_CLI_WIFI conflicts with the border router auto-initialization feature" +#endif + +static bool s_border_router_started = false; + +static void ot_br_init(void *ctx) +{ + ESP_ERROR_CHECK(example_connect()); + esp_openthread_lock_acquire(portMAX_DELAY); + esp_openthread_set_backbone_netif(get_example_netif()); + ESP_ERROR_CHECK(esp_openthread_border_router_init()); + esp_openthread_lock_release(); + s_border_router_started = true; + vTaskDelete(NULL); +} + +esp_err_t esp_openthread_border_router_start(void) +{ + return (xTaskCreate(ot_br_init, "ot_br_init", 6144, NULL, 4, NULL) == pdPASS) ? ESP_OK : ESP_FAIL; +} + +void esp_openthread_border_router_stop(void) +{ + if (s_border_router_started) { + esp_openthread_lock_acquire(portMAX_DELAY); + ESP_ERROR_CHECK(esp_openthread_border_router_deinit()); + esp_openthread_lock_release(); + s_border_router_started =false; + } +} diff --git a/examples/openthread/ot_common_components/ot_examples_common/CMakeLists.txt b/examples/openthread/ot_common_components/ot_examples_common/CMakeLists.txt new file mode 100644 index 000000000000..321063eb9489 --- /dev/null +++ b/examples/openthread/ot_common_components/ot_examples_common/CMakeLists.txt @@ -0,0 +1,19 @@ +set(srcs "") + +if(CONFIG_OPENTHREAD_FTD OR CONFIG_OPENTHREAD_MTD) + list(APPEND srcs "ot_network.c") +endif() + +if(CONFIG_OPENTHREAD_CLI) + list(APPEND srcs "ot_console.c") +endif() + +if(CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE) + list(APPEND srcs "ot_external_coexist.c") +endif() + +idf_component_register( + SRCS "${srcs}" + INCLUDE_DIRS "include" + PRIV_REQUIRES console cmd_system esp_coex openthread +) diff --git a/examples/openthread/ot_common_components/ot_examples_common/Kconfig.projbuild b/examples/openthread/ot_common_components/ot_examples_common/Kconfig.projbuild new file mode 100644 index 000000000000..94e38cf6c103 --- /dev/null +++ b/examples/openthread/ot_common_components/ot_examples_common/Kconfig.projbuild @@ -0,0 +1,67 @@ +menu "Config for OpenThread Examples" + depends on OPENTHREAD_ENABLED + + config OPENTHREAD_NETWORK_AUTO_START + bool 'Enable the automatic start mode of Thread network.' + depends on OPENTHREAD_FTD || OPENTHREAD_MTD + default n + help + If enabled, the Openthread Device will create or connect to Thread network with pre-configured + network parameters automatically. Otherwise, user need to configure Thread via CLI command manually. + + menu "External coexist wire type and pin config" + depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE + + choice EXTERNAL_COEX_WORK_MODE + prompt "The work mode of external coexist" + default EXTERNAL_COEX_WORK_MODE_FOLLOWER if SOC_IEEE802154_SUPPORTED + default EXTERNAL_COEX_WORK_MODE_LEADER if !SOC_IEEE802154_SUPPORTED && SOC_WIFI_SUPPORTED + help + Select work mode for external coexist, the work mode defined in esp_extern_coex_work_mode_t. + + config EXTERNAL_COEX_WORK_MODE_LEADER + bool "Leader mode" + help + Select this to set the external coexistence work mode to leader mode. + + config EXTERNAL_COEX_WORK_MODE_FOLLOWER + bool "Follower mode" + help + Select this to set the external coexistence work mode to follower mode. + + config EXTERNAL_COEX_WORK_MODE_UNKNOWN + bool "Unknown mode" + help + Select this to set the external coexistence work mode to unknown mode. + endchoice + + config EXTERNAL_COEX_WIRE_TYPE + int "The wire_type of external coexist" + depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE + default 3 + range 0 3 + help + Select wire_type for external coexist, the wire_type define in external_coex_wire_t. + + config EXTERNAL_COEX_REQUEST_PIN + int "The number of external coexist request pin" + depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE && (EXTERNAL_COEX_WIRE_TYPE >= 0) + default 0 + + config EXTERNAL_COEX_GRANT_PIN + int "The number of external coexist grant pin" + depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE && (EXTERNAL_COEX_WIRE_TYPE >= 1) + default 1 + + config EXTERNAL_COEX_PRIORITY_PIN + int "The number of external coexist priority pin" + depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE && (EXTERNAL_COEX_WIRE_TYPE >= 2) + default 2 + + config EXTERNAL_COEX_TX_LINE_PIN + int "The number of external coexist tx_line pin" + depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE && (EXTERNAL_COEX_WIRE_TYPE = 3) + default 3 + endmenu # External coexist wire type and pin config + +endmenu diff --git a/examples/openthread/ot_common_components/ot_examples_common/idf_component.yml b/examples/openthread/ot_common_components/ot_examples_common/idf_component.yml new file mode 100644 index 000000000000..77b231f2a7fa --- /dev/null +++ b/examples/openthread/ot_common_components/ot_examples_common/idf_component.yml @@ -0,0 +1,4 @@ +## IDF Component Manager Manifest File +dependencies: + cmd_system: + path: ${IDF_PATH}/examples/system/console/advanced/components/cmd_system diff --git a/examples/openthread/ot_common_components/ot_examples_common/include/ot_examples_common.h b/examples/openthread/ot_common_components/ot_examples_common/include/ot_examples_common.h new file mode 100644 index 000000000000..9c7ab229643c --- /dev/null +++ b/examples/openthread/ot_common_components/ot_examples_common/include/ot_examples_common.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: CC0-1.0 + * + * OpenThread Command Line Example + * + * This example code is in the Public Domain (or CC0 licensed, at your option.) + * + * Unless required by applicable law or agreed to in writing, this + * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. +*/ + +#include "sdkconfig.h" + +#if CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE +#if CONFIG_EXTERNAL_COEX_WIRE_TYPE == EXTERNAL_COEXIST_WIRE_1 +#define ESP_OPENTHREAD_DEFAULT_EXTERNAL_COEX_CONFIG() \ + { \ + .request = CONFIG_EXTERNAL_COEX_REQUEST_PIN, \ + } +#elif CONFIG_EXTERNAL_COEX_WIRE_TYPE == EXTERNAL_COEXIST_WIRE_2 +#define ESP_OPENTHREAD_DEFAULT_EXTERNAL_COEX_CONFIG() \ + { \ + .request = CONFIG_EXTERNAL_COEX_REQUEST_PIN, \ + .grant = CONFIG_EXTERNAL_COEX_GRANT_PIN, \ + } +#elif CONFIG_EXTERNAL_COEX_WIRE_TYPE == EXTERNAL_COEXIST_WIRE_3 +#define ESP_OPENTHREAD_DEFAULT_EXTERNAL_COEX_CONFIG() \ + { \ + .request = CONFIG_EXTERNAL_COEX_REQUEST_PIN, \ + .priority = CONFIG_EXTERNAL_COEX_PRIORITY_PIN, \ + .grant = CONFIG_EXTERNAL_COEX_GRANT_PIN, \ + } +#elif CONFIG_EXTERNAL_COEX_WIRE_TYPE == EXTERNAL_COEXIST_WIRE_4 +#define ESP_OPENTHREAD_DEFAULT_EXTERNAL_COEX_CONFIG() \ + { \ + .request = CONFIG_EXTERNAL_COEX_REQUEST_PIN, \ + .priority = CONFIG_EXTERNAL_COEX_PRIORITY_PIN, \ + .grant = CONFIG_EXTERNAL_COEX_GRANT_PIN, \ + .tx_line = CONFIG_EXTERNAL_COEX_TX_LINE_PIN, \ + } +#endif +#endif // CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE + +/** + * @brief Initializes the external coexistence. + * + */ +void ot_external_coexist_init(void); + +/** + * @brief Initializes the console. + * + */ +void ot_console_start(void); + +/** + * @brief Form or join the Thread network automatically. + * + */ +void ot_network_auto_start(void); diff --git a/examples/openthread/ot_common_components/ot_examples_common/ot_console.c b/examples/openthread/ot_common_components/ot_examples_common/ot_console.c new file mode 100644 index 000000000000..a293adf38c49 --- /dev/null +++ b/examples/openthread/ot_common_components/ot_examples_common/ot_console.c @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: CC0-1.0 + * + * OpenThread Command Line Example + * + * This example code is in the Public Domain (or CC0 licensed, at your option.) + * + * Unless required by applicable law or agreed to in writing, this + * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. +*/ + +#include "ot_examples_common.h" +#include "esp_check.h" +#include "esp_err.h" +#include "esp_console.h" +#include "cmd_system.h" + +void ot_console_start(void) +{ + esp_console_repl_t *repl = NULL; + esp_console_repl_config_t repl_config = ESP_CONSOLE_REPL_CONFIG_DEFAULT(); + /* Prompt to be printed before each line. + * This can be customized, made dynamic, etc. + */ + repl_config.prompt = CONFIG_IDF_TARGET ">"; + repl_config.max_cmdline_length = 256; + repl_config.max_history_len = 10; + +#if defined(CONFIG_ESP_CONSOLE_UART_DEFAULT) || defined(CONFIG_ESP_CONSOLE_UART_CUSTOM) + esp_console_dev_uart_config_t hw_config = ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT(); + ESP_ERROR_CHECK(esp_console_new_repl_uart(&hw_config, &repl_config, &repl)); +#elif defined(CONFIG_ESP_CONSOLE_USB_CDC) + esp_console_dev_usb_cdc_config_t hw_config = ESP_CONSOLE_DEV_CDC_CONFIG_DEFAULT(); + ESP_ERROR_CHECK(esp_console_new_repl_usb_cdc(&hw_config, &repl_config, &repl)); + +#elif defined(CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG) + esp_console_dev_usb_serial_jtag_config_t hw_config = ESP_CONSOLE_DEV_USB_SERIAL_JTAG_CONFIG_DEFAULT(); + ESP_ERROR_CHECK(esp_console_new_repl_usb_serial_jtag(&hw_config, &repl_config, &repl)); +#else +#error Unsupported console type +#endif + ESP_ERROR_CHECK(esp_console_start_repl(repl)); + + register_system(); +} diff --git a/examples/openthread/ot_common_components/ot_examples_common/ot_external_coexist.c b/examples/openthread/ot_common_components/ot_examples_common/ot_external_coexist.c new file mode 100644 index 000000000000..463ee56d8f79 --- /dev/null +++ b/examples/openthread/ot_common_components/ot_examples_common/ot_external_coexist.c @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: CC0-1.0 + * + * OpenThread Command Line Example + * + * This example code is in the Public Domain (or CC0 licensed, at your option.) + * + * Unless required by applicable law or agreed to in writing, this + * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. +*/ + +#include "sdkconfig.h" +#include "esp_check.h" +#include "esp_err.h" +#include "esp_coexist.h" +#include "ot_examples_common.h" + +void ot_external_coexist_init(void) +{ + esp_extern_coex_work_mode_t mode = +#if CONFIG_EXTERNAL_COEX_WORK_MODE_LEADER + EXTERNAL_COEX_LEADER_ROLE; +#elif CONFIG_EXTERNAL_COEX_WORK_MODE_FOLLOWER + EXTERNAL_COEX_FOLLOWER_ROLE; +#else + EXTERNAL_COEX_UNKNOWN_ROLE; +#endif + + esp_external_coex_gpio_set_t gpio_pin = ESP_OPENTHREAD_DEFAULT_EXTERNAL_COEX_CONFIG(); + ESP_ERROR_CHECK(esp_external_coex_set_work_mode(mode)); + ESP_ERROR_CHECK(esp_enable_extern_coex_gpio_pin(CONFIG_EXTERNAL_COEX_WIRE_TYPE, gpio_pin)); +} diff --git a/examples/openthread/ot_common_components/ot_examples_common/ot_network.c b/examples/openthread/ot_common_components/ot_examples_common/ot_network.c new file mode 100644 index 000000000000..1b4fe9c872c8 --- /dev/null +++ b/examples/openthread/ot_common_components/ot_examples_common/ot_network.c @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: CC0-1.0 + * + * OpenThread Command Line Example + * + * This example code is in the Public Domain (or CC0 licensed, at your option.) + * + * Unless required by applicable law or agreed to in writing, this + * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. +*/ + +#include "ot_examples_common.h" +#include "esp_check.h" +#include "esp_err.h" +#include "esp_openthread.h" +#include "esp_openthread_lock.h" + +void ot_network_auto_start(void) +{ + otOperationalDatasetTlvs dataset; + esp_openthread_lock_acquire(portMAX_DELAY); + otError error = otDatasetGetActiveTlvs(esp_openthread_get_instance(), &dataset); + ESP_ERROR_CHECK(esp_openthread_auto_start((error == OT_ERROR_NONE) ? &dataset : NULL)); + esp_openthread_lock_release(); +} diff --git a/examples/openthread/ot_rcp/main/Kconfig.projbuild b/examples/openthread/ot_rcp/main/Kconfig.projbuild index 2fa5dc99ddc7..3bff9f092003 100644 --- a/examples/openthread/ot_rcp/main/Kconfig.projbuild +++ b/examples/openthread/ot_rcp/main/Kconfig.projbuild @@ -18,33 +18,4 @@ menu "OpenThread RCP Example" default 5 range 0 25 - menu "External coexist wire type and pin config" - config EXTERNAL_COEX_WIRE_TYPE - int "The wire_type of external coexist" - depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE - default 3 - range 0 3 - help - Select wire_type for external coexist, the wire_type define in external_coex_wire_t. - - config EXTERNAL_COEX_REQUEST_PIN - int "The number of external coexist request pin" - depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE && (EXTERNAL_COEX_WIRE_TYPE >= 0) - default 0 - - config EXTERNAL_COEX_GRANT_PIN - int "The number of external coexist grant pin" - depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE && (EXTERNAL_COEX_WIRE_TYPE >= 1) - default 1 - - config EXTERNAL_COEX_PRIORITY_PIN - int "The number of external coexist priority pin" - depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE && (EXTERNAL_COEX_WIRE_TYPE >= 2) - default 2 - - config EXTERNAL_COEX_TX_LINE_PIN - int "The number of external coexist tx_line pin" - depends on ESP_COEX_EXTERNAL_COEXIST_ENABLE && (EXTERNAL_COEX_WIRE_TYPE = 3) - default 3 - endmenu # External coexist wire type and pin config endmenu diff --git a/examples/openthread/ot_rcp/main/esp_ot_config.h b/examples/openthread/ot_rcp/main/esp_ot_config.h index d7a11503297b..69e1805e962c 100644 --- a/examples/openthread/ot_rcp/main/esp_ot_config.h +++ b/examples/openthread/ot_rcp/main/esp_ot_config.h @@ -14,10 +14,6 @@ #pragma once -#if CONFIG_EXTERNAL_COEX_ENABLE -#include "esp_coexist.h" -#endif - #include "esp_openthread_types.h" #define ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG() \ { \ @@ -89,33 +85,3 @@ .netif_queue_size = 10, \ .task_queue_size = 10, \ } - -#if CONFIG_EXTERNAL_COEX_ENABLE -#if CONFIG_EXTERNAL_COEX_WIRE_TYPE == EXTERNAL_COEXIST_WIRE_1 -#define ESP_OPENTHREAD_DEFAULT_EXTERNAL_COEX_CONFIG() \ - { \ - .request = CONFIG_EXTERNAL_COEX_REQUEST_PIN, \ - } -#elif CONFIG_EXTERNAL_COEX_WIRE_TYPE == EXTERNAL_COEXIST_WIRE_2 -#define ESP_OPENTHREAD_DEFAULT_EXTERNAL_COEX_CONFIG() \ - { \ - .request = CONFIG_EXTERNAL_COEX_REQUEST_PIN, \ - .grant = CONFIG_EXTERNAL_COEX_GRANT_PIN, \ - } -#elif CONFIG_EXTERNAL_COEX_WIRE_TYPE == EXTERNAL_COEXIST_WIRE_3 -#define ESP_OPENTHREAD_DEFAULT_EXTERNAL_COEX_CONFIG() \ - { \ - .request = CONFIG_EXTERNAL_COEX_REQUEST_PIN, \ - .priority = CONFIG_EXTERNAL_COEX_PRIORITY_PIN, \ - .grant = CONFIG_EXTERNAL_COEX_GRANT_PIN, \ - } -#elif CONFIG_EXTERNAL_COEX_WIRE_TYPE == EXTERNAL_COEXIST_WIRE_4 -#define ESP_OPENTHREAD_DEFAULT_EXTERNAL_COEX_CONFIG() \ - { \ - .request = CONFIG_EXTERNAL_COEX_REQUEST_PIN, \ - .priority = CONFIG_EXTERNAL_COEX_PRIORITY_PIN, \ - .grant = CONFIG_EXTERNAL_COEX_GRANT_PIN, \ - .tx_line = CONFIG_EXTERNAL_COEX_TX_LINE_PIN, \ - } -#endif -#endif // CONFIG_EXTERNAL_COEX_ENABLE diff --git a/examples/openthread/ot_rcp/main/esp_ot_rcp.c b/examples/openthread/ot_rcp/main/esp_ot_rcp.c index ccb9988f676a..fddd77668469 100644 --- a/examples/openthread/ot_rcp/main/esp_ot_rcp.c +++ b/examples/openthread/ot_rcp/main/esp_ot_rcp.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: CC0-1.0 * @@ -20,10 +20,9 @@ #include "esp_openthread.h" #include "esp_ot_config.h" #include "esp_vfs_eventfd.h" -#include "driver/uart.h" -#if CONFIG_EXTERNAL_COEX_ENABLE -#include "esp_coexist.h" +#if CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE +#include "ot_examples_common.h" #endif #if !SOC_IEEE802154_SUPPORTED @@ -34,43 +33,6 @@ extern void otAppNcpInit(otInstance *instance); -#if CONFIG_EXTERNAL_COEX_ENABLE -#if SOC_EXTERNAL_COEX_ADVANCE -static void ot_external_coexist_init(void) -{ - esp_external_coex_gpio_set_t gpio_pin = ESP_OPENTHREAD_DEFAULT_EXTERNAL_COEX_CONFIG(); - esp_external_coex_set_work_mode(EXTERNAL_COEX_FOLLOWER_ROLE); - ESP_ERROR_CHECK(esp_enable_extern_coex_gpio_pin(CONFIG_EXTERNAL_COEX_WIRE_TYPE, gpio_pin)); -} -#endif // SOC_EXTERNAL_COEX_ADVANCE -#endif // CONFIG_EXTERNAL_COEX_ENABLE - -static void ot_task_worker(void *aContext) -{ - esp_openthread_platform_config_t config = { - .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(), - .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(), - .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(), - }; - - // Initialize the OpenThread stack - ESP_ERROR_CHECK(esp_openthread_init(&config)); - -#if CONFIG_EXTERNAL_COEX_ENABLE - ot_external_coexist_init(); -#endif // CONFIG_EXTERNAL_COEX_ENABLE - - // Initialize the OpenThread ncp - otAppNcpInit(esp_openthread_get_instance()); - - // Run the main loop - esp_openthread_launch_mainloop(); - - // Clean up - esp_vfs_eventfd_unregister(); - vTaskDelete(NULL); -} - void app_main(void) { // Used eventfds: @@ -83,5 +45,19 @@ void app_main(void) ESP_ERROR_CHECK(nvs_flash_init()); ESP_ERROR_CHECK(esp_event_loop_create_default()); ESP_ERROR_CHECK(esp_vfs_eventfd_register(&eventfd_config)); - xTaskCreate(ot_task_worker, "ot_rcp_main", 3072, xTaskGetCurrentTaskHandle(), 5, NULL); + +#if CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE + ot_external_coexist_init(); +#endif + + static esp_openthread_config_t config = { + .netif_config = {0}, + .platform_config = { + .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(), + .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(), + .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(), + }, + }; + + ESP_ERROR_CHECK(esp_openthread_start(&config)); } diff --git a/examples/openthread/ot_rcp/main/idf_component.yml b/examples/openthread/ot_rcp/main/idf_component.yml new file mode 100644 index 000000000000..92e0e5b649f4 --- /dev/null +++ b/examples/openthread/ot_rcp/main/idf_component.yml @@ -0,0 +1,4 @@ +## IDF Component Manager Manifest File +dependencies: + ot_examples_common: + path: ${IDF_PATH}/examples/openthread/ot_common_components/ot_examples_common diff --git a/examples/openthread/ot_rcp/sdkconfig.ci.ext_coex b/examples/openthread/ot_rcp/sdkconfig.ci.ext_coex index 10e03f180efd..fdd48dc0bc95 100644 --- a/examples/openthread/ot_rcp/sdkconfig.ci.ext_coex +++ b/examples/openthread/ot_rcp/sdkconfig.ci.ext_coex @@ -1,2 +1,3 @@ -CONFIG_EXTERNAL_COEX_ENABLE=y +CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE=y CONFIG_ESP_COEX_SW_COEXIST_ENABLE=n +CONFIG_EXTERNAL_COEX_WORK_MODE_FOLLOWER=y diff --git a/examples/openthread/ot_rcp/sdkconfig.defaults b/examples/openthread/ot_rcp/sdkconfig.defaults index 914395913458..e2612686e424 100644 --- a/examples/openthread/ot_rcp/sdkconfig.defaults +++ b/examples/openthread/ot_rcp/sdkconfig.defaults @@ -25,14 +25,16 @@ CONFIG_OPENTHREAD_BORDER_ROUTER=n CONFIG_OPENTHREAD_CLI=n CONFIG_OPENTHREAD_SRP_CLIENT=n CONFIG_OPENTHREAD_DNS_CLIENT=n +CONFIG_OPENTHREAD_TASK_SIZE=3072 +CONFIG_OPENTHREAD_CONSOLE_ENABLE=n # end of OpenThread # # Deprecated options for backward compatibility # -CONFIG_LOG_BOOTLOADER_LEVEL_ERROR=y -CONFIG_LOG_BOOTLOADER_LEVEL_INFO=n +CONFIG_BOOTLOADER_LOG_LEVEL_ERROR=y +CONFIG_BOOTLOADER_LOG_LEVEL_INFO=n # End of deprecated options # @@ -48,3 +50,5 @@ CONFIG_LOG_DEFAULT_LEVEL_NONE=y CONFIG_NEWLIB_NANO_FORMAT=y CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC=n CONFIG_OPENTHREAD_LOG_LEVEL_NONE=y +CONFIG_OPENTHREAD_TIMING_OPTIMIZATION=y +CONFIG_FREERTOS_HZ=1000 diff --git a/examples/openthread/ot_sleepy_device/deep_sleep/main/esp_ot_sleepy_device.c b/examples/openthread/ot_sleepy_device/deep_sleep/main/esp_ot_sleepy_device.c index c77114060115..bfdf9fe0d97e 100644 --- a/examples/openthread/ot_sleepy_device/deep_sleep/main/esp_ot_sleepy_device.c +++ b/examples/openthread/ot_sleepy_device/deep_sleep/main/esp_ot_sleepy_device.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: CC0-1.0 * @@ -27,9 +27,6 @@ #include "esp_vfs_eventfd.h" #include "nvs_flash.h" #include "driver/rtc_io.h" -#include "driver/uart.h" -#include "openthread/logging.h" -#include "openthread/thread.h" #if !SOC_IEEE802154_SUPPORTED #error "Openthread sleepy device is only supported for the SoCs which have IEEE 802.15.4 module" @@ -60,16 +57,6 @@ static void create_config_network(otInstance *instance) ESP_ERROR_CHECK(esp_openthread_auto_start(NULL)); } -static esp_netif_t *init_openthread_netif(const esp_openthread_platform_config_t *config) -{ - esp_netif_config_t cfg = ESP_NETIF_DEFAULT_OPENTHREAD(); - esp_netif_t *netif = esp_netif_new(&cfg); - assert(netif != NULL); - ESP_ERROR_CHECK(esp_netif_attach(netif, esp_openthread_netif_glue_init(config))); - - return netif; -} - static void ot_state_change_callback(otChangedFlags changed_flags, void* ctx) { OT_UNUSED_VARIABLE(ctx); @@ -163,44 +150,6 @@ static void ot_deep_sleep_init(void) ESP_ERROR_CHECK(gpio_pulldown_dis(gpio_wakeup_pin)); } - -static void ot_task_worker(void *aContext) -{ - esp_openthread_platform_config_t config = { - .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(), - .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(), - .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(), - }; - - // Initialize the OpenThread stack - ESP_ERROR_CHECK(esp_openthread_init(&config)); - - ot_deep_sleep_init(); - -#if CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC - // The OpenThread log level directly matches ESP log level - (void)otLoggingSetLevel(CONFIG_LOG_DEFAULT_LEVEL); -#endif - esp_netif_t *openthread_netif; - // Initialize the esp_netif bindings - openthread_netif = init_openthread_netif(&config); - esp_netif_set_default_netif(openthread_netif); - otSetStateChangedCallback(esp_openthread_get_instance(), ot_state_change_callback, NULL); - - create_config_network(esp_openthread_get_instance()); - - // Run the main loop - esp_openthread_launch_mainloop(); - - // Clean up - esp_openthread_netif_glue_deinit(); - esp_netif_destroy(openthread_netif); - - esp_vfs_eventfd_unregister(); - vTaskDelete(NULL); -} - - void app_main(void) { // Used eventfds: @@ -215,6 +164,19 @@ void app_main(void) ESP_ERROR_CHECK(esp_event_loop_create_default()); ESP_ERROR_CHECK(esp_netif_init()); ESP_ERROR_CHECK(esp_vfs_eventfd_register(&eventfd_config)); + ot_deep_sleep_init(); + + static esp_openthread_config_t config = { + .netif_config = ESP_NETIF_DEFAULT_OPENTHREAD(), + .platform_config = { + .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(), + .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(), + .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(), + }, + }; + ESP_ERROR_CHECK(esp_openthread_start(&config)); + esp_netif_set_default_netif(esp_openthread_get_netif()); - xTaskCreate(ot_task_worker, "ot_power_save_main", 4096, NULL, 5, NULL); + otSetStateChangedCallback(esp_openthread_get_instance(), ot_state_change_callback, NULL); + create_config_network(esp_openthread_get_instance()); } diff --git a/examples/openthread/ot_sleepy_device/deep_sleep/main/esp_ot_sleepy_device_config.h b/examples/openthread/ot_sleepy_device/deep_sleep/main/esp_ot_sleepy_device_config.h index 145bb245ccc2..5f82ae0ed61e 100644 --- a/examples/openthread/ot_sleepy_device/deep_sleep/main/esp_ot_sleepy_device_config.h +++ b/examples/openthread/ot_sleepy_device/deep_sleep/main/esp_ot_sleepy_device_config.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: CC0-1.0 * @@ -25,24 +25,9 @@ } #endif -#define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ - { \ - .host_connection_mode = HOST_CONNECTION_MODE_CLI_UART, \ - .host_uart_config = { \ - .port = 0, \ - .uart_config = \ - { \ - .baud_rate = 115200, \ - .data_bits = UART_DATA_8_BITS, \ - .parity = UART_PARITY_DISABLE, \ - .stop_bits = UART_STOP_BITS_1, \ - .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, \ - .rx_flow_ctrl_thresh = 0, \ - .source_clk = UART_SCLK_DEFAULT, \ - }, \ - .rx_pin = UART_PIN_NO_CHANGE, \ - .tx_pin = UART_PIN_NO_CHANGE, \ - }, \ +#define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ + { \ + .host_connection_mode = HOST_CONNECTION_MODE_NONE, \ } #define ESP_OPENTHREAD_DEFAULT_PORT_CONFIG() \ diff --git a/examples/openthread/ot_sleepy_device/deep_sleep/sdkconfig.defaults b/examples/openthread/ot_sleepy_device/deep_sleep/sdkconfig.defaults index b76a1dcd330b..3edc9e3663e1 100644 --- a/examples/openthread/ot_sleepy_device/deep_sleep/sdkconfig.defaults +++ b/examples/openthread/ot_sleepy_device/deep_sleep/sdkconfig.defaults @@ -21,6 +21,7 @@ CONFIG_MBEDTLS_ECJPAKE_C=y CONFIG_OPENTHREAD_ENABLED=y CONFIG_OPENTHREAD_BORDER_ROUTER=n CONFIG_OPENTHREAD_DNS64_CLIENT=y +CONFIG_OPENTHREAD_CONSOLE_ENABLE=n # end of OpenThread # diff --git a/examples/openthread/ot_sleepy_device/light_sleep/README.md b/examples/openthread/ot_sleepy_device/light_sleep/README.md index 01e8259d2bbd..24ed4aa1925f 100644 --- a/examples/openthread/ot_sleepy_device/light_sleep/README.md +++ b/examples/openthread/ot_sleepy_device/light_sleep/README.md @@ -15,8 +15,8 @@ Set the chip target: `idf.py set-target `, then configure the project There are two options to configure Openthread Dataset: -* Auto start mode: Enable `OPENTHREAD_AUTO_START` under `OpenThread Sleepy Example---> Enable the automatic start mode`, and configure the dataset under `Component config ---> Openthread ---> Thread Operation Dataset`. -* Manual mode: Disable `OPENTHREAD_AUTO_START`, use the CLI command to configure the dataset and start network. +* Auto start mode: Enable `OPENTHREAD_NETWORK_AUTO_START` under `OpenThread Sleepy Example---> Enable the automatic start mode`, and configure the dataset under `Component config ---> Openthread ---> Thread Operation Dataset`. +* Manual mode: Disable `OPENTHREAD_NETWORK_AUTO_START`, use the CLI command to configure the dataset and start network. ### Build and Flash @@ -24,11 +24,11 @@ Build the project and flash it to the board. Use the following command: `idf.py ### Configure the Openthread sleepy device ``` -> mode - -> pollperiod 3000 -> dataset set active -> ifconfig up -> thread start +esp32h2> ot mode - +esp32h2> ot pollperiod 3000 +esp32h2> ot dataset set active +esp32h2> ot ifconfig up +esp32h2> ot thread start ``` ### Example Output @@ -62,23 +62,23 @@ I (652) gdma: GDMA pair (0, 0) retention initialization I(660) OPENTHREAD:[I] ChildSupervsn-: Timeout: 0 -> 190 > I (664) OPENTHREAD: OpenThread attached to netif I (635) main_task: Returned from app_main() -> mode - +esp32h2> ot mode - I(2250683) OPENTHREAD:[N] Mle-----------: Mode 0x0f -> 0x04 [rx-on:no ftd:no full-net:no] Done -> pollperiod 3000 +esp32h2> ot pollperiod 3000 Done -> dataset set active 0e080000000000010000000300001a35060004001fffe00208dead00beef00cafe0708fd000db800a00000051000112233445566778899aabbccdd0000030e4f70656e5468726561642d455350010212340410104810e2315100afd6bc9215a6bfac530c0402a0f7f8 +esp32h2> ot dataset set active 0e080000000000010000000300001a35060004001fffe00208dead00beef00cafe0708fd000db800a00000051000112233445566778899aabbccdd0000030e4f70656e5468726561642d455350010212340410104810e2315100afd6bc9215a6bfac530c0402a0f7f8 Done -> ifconfig up +esp32h2> ot ifconfig up Done I (2274801) OT_STATE: netif up -> thread start +esp32h2> ot thread start I(2279917) OPENTHREAD:[N] Mle-----------: Role disabled -> detached Done diff --git a/examples/openthread/ot_sleepy_device/light_sleep/main/Kconfig.projbuild b/examples/openthread/ot_sleepy_device/light_sleep/main/Kconfig.projbuild deleted file mode 100644 index 27aa83ff0c7f..000000000000 --- a/examples/openthread/ot_sleepy_device/light_sleep/main/Kconfig.projbuild +++ /dev/null @@ -1,9 +0,0 @@ -menu "OpenThread Sleepy Example" - - config OPENTHREAD_AUTO_START - bool 'Enable the automatic start mode.' - default n - help - If enabled, the Openthread Device will create or connect to thread network with pre-configured - network parameters automatically. Otherwise, user need to configure Thread via CLI command manually. -endmenu diff --git a/examples/openthread/ot_sleepy_device/light_sleep/main/esp_ot_sleepy_device.c b/examples/openthread/ot_sleepy_device/light_sleep/main/esp_ot_sleepy_device.c index d4e1892273d8..b54b2680424e 100644 --- a/examples/openthread/ot_sleepy_device/light_sleep/main/esp_ot_sleepy_device.c +++ b/examples/openthread/ot_sleepy_device/light_sleep/main/esp_ot_sleepy_device.c @@ -19,17 +19,15 @@ #include "esp_err.h" #include "esp_event.h" #include "esp_log.h" +#include "esp_netif.h" #include "esp_openthread.h" -#include "esp_openthread_cli.h" #include "esp_openthread_lock.h" #include "esp_openthread_netif_glue.h" #include "esp_ot_sleepy_device_config.h" #include "esp_vfs_eventfd.h" #include "esp_private/esp_clk.h" -#include "driver/uart.h" #include "nvs_flash.h" -#include "openthread/logging.h" -#include "openthread/thread.h" +#include "ot_examples_common.h" #if CONFIG_ESP_SLEEP_DEBUG #include "esp_private/esp_pmu.h" #include "esp_private/esp_sleep_internal.h" @@ -50,7 +48,7 @@ static esp_pm_lock_handle_t s_cli_pm_lock = NULL; TimerHandle_t xTimer; -#if CONFIG_OPENTHREAD_AUTO_START +#if CONFIG_OPENTHREAD_NETWORK_AUTO_START static void create_config_network(otInstance *instance) { otLinkModeConfig linkMode = { 0 }; @@ -73,7 +71,7 @@ static void create_config_network(otInstance *instance) otError error = otDatasetGetActiveTlvs(esp_openthread_get_instance(), &dataset); ESP_ERROR_CHECK(esp_openthread_auto_start((error == OT_ERROR_NONE) ? &dataset : NULL)); } -#endif // CONFIG_OPENTHREAD_AUTO_START +#endif // CONFIG_OPENTHREAD_NETWORK_AUTO_START static esp_err_t esp_openthread_sleep_device_init(void) { @@ -105,16 +103,6 @@ static void process_state_change(otChangedFlags flags, void* context) } } -static esp_netif_t *init_openthread_netif(const esp_openthread_platform_config_t *config) -{ - esp_netif_config_t cfg = ESP_NETIF_DEFAULT_OPENTHREAD(); - esp_netif_t *netif = esp_netif_new(&cfg); - assert(netif != NULL); - ESP_ERROR_CHECK(esp_netif_attach(netif, esp_openthread_netif_glue_init(config))); - - return netif; -} - #if CONFIG_ESP_SLEEP_DEBUG static esp_sleep_context_t s_sleep_ctx; @@ -128,63 +116,6 @@ void vTimerCallback( TimerHandle_t xTimer ) } #endif -static void ot_task_worker(void *aContext) -{ - otError ret; - esp_openthread_platform_config_t config = { - .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(), - .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(), - .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(), - }; - - // Initialize the OpenThread stack - ESP_ERROR_CHECK(esp_openthread_init(&config)); - - esp_openthread_lock_acquire(portMAX_DELAY); - ret = otSetStateChangedCallback(esp_openthread_get_instance(), process_state_change, esp_openthread_get_instance()); - esp_openthread_lock_release(); - if(ret != OT_ERROR_NONE) { - ESP_LOGE(TAG, "Failed to set state changed callback"); - } -#if CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC - // The OpenThread log level directly matches ESP log level - (void)otLoggingSetLevel(CONFIG_LOG_DEFAULT_LEVEL); -#endif - // Initialize the OpenThread cli -#if CONFIG_OPENTHREAD_CLI - esp_openthread_cli_init(); -#endif - esp_netif_t *openthread_netif; - // Initialize the esp_netif bindings - openthread_netif = init_openthread_netif(&config); - esp_netif_set_default_netif(openthread_netif); -#if CONFIG_OPENTHREAD_AUTO_START - create_config_network(esp_openthread_get_instance()); -#endif // CONFIG_OPENTHREAD_AUTO_START - -#if CONFIG_OPENTHREAD_CLI - esp_openthread_cli_create_task(); -#endif -#if CONFIG_ESP_SLEEP_DEBUG - esp_sleep_set_sleep_context(&s_sleep_ctx); - esp_log_level_set(TAG, ESP_LOG_DEBUG); - - // Use freeRTOS timer so that it is lower priority than OpenThread - xTimer = xTimerCreate("print_sleep_flag", pdMS_TO_TICKS(2000), pdTRUE, NULL, vTimerCallback); - xTimerStart( xTimer, 0 ); -#endif - - // Run the main loop - esp_openthread_launch_mainloop(); - - // Clean up - esp_openthread_netif_glue_deinit(); - esp_netif_destroy(openthread_netif); - - esp_vfs_eventfd_unregister(); - vTaskDelete(NULL); -} - static esp_err_t ot_power_save_init(void) { esp_err_t rc = ESP_OK; @@ -227,5 +158,34 @@ void app_main(void) ESP_ERROR_CHECK(esp_vfs_eventfd_register(&eventfd_config)); ESP_ERROR_CHECK(ot_power_save_init()); ESP_ERROR_CHECK(esp_openthread_sleep_device_init()); - xTaskCreate(ot_task_worker, "ot_power_save_main", 4096, NULL, 5, NULL); + +#if CONFIG_OPENTHREAD_CLI + ot_console_start(); +#endif + + static esp_openthread_config_t config = { + .netif_config = ESP_NETIF_DEFAULT_OPENTHREAD(), + .platform_config = { + .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(), + .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(), + .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(), + }, + }; + ESP_ERROR_CHECK(esp_openthread_start(&config)); + esp_netif_set_default_netif(esp_openthread_get_netif()); + + otSetStateChangedCallback(esp_openthread_get_instance(), process_state_change, esp_openthread_get_instance()); + +#if CONFIG_OPENTHREAD_NETWORK_AUTO_START + create_config_network(esp_openthread_get_instance()); +#endif + +#if CONFIG_ESP_SLEEP_DEBUG + esp_sleep_set_sleep_context(&s_sleep_ctx); + esp_log_level_set(TAG, ESP_LOG_DEBUG); + + // Use freeRTOS timer so that it is lower priority than OpenThread + xTimer = xTimerCreate("print_sleep_flag", pdMS_TO_TICKS(2000), pdTRUE, NULL, vTimerCallback); + xTimerStart( xTimer, 0 ); +#endif } diff --git a/examples/openthread/ot_sleepy_device/light_sleep/main/esp_ot_sleepy_device_config.h b/examples/openthread/ot_sleepy_device/light_sleep/main/esp_ot_sleepy_device_config.h index 73bd029b275e..716433c60545 100644 --- a/examples/openthread/ot_sleepy_device/light_sleep/main/esp_ot_sleepy_device_config.h +++ b/examples/openthread/ot_sleepy_device/light_sleep/main/esp_ot_sleepy_device_config.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: CC0-1.0 * @@ -25,25 +25,9 @@ } #endif -// When JIRA PM-3 is fixed, the UART clock will automatically switch. -#define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ - { \ - .host_connection_mode = HOST_CONNECTION_MODE_CLI_UART, \ - .host_uart_config = { \ - .port = 0, \ - .uart_config = \ - { \ - .baud_rate = 115200, \ - .data_bits = UART_DATA_8_BITS, \ - .parity = UART_PARITY_DISABLE, \ - .stop_bits = UART_STOP_BITS_1, \ - .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, \ - .rx_flow_ctrl_thresh = 0, \ - .source_clk = UART_SCLK_XTAL, \ - }, \ - .rx_pin = UART_PIN_NO_CHANGE, \ - .tx_pin = UART_PIN_NO_CHANGE, \ - }, \ +#define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ + { \ + .host_connection_mode = HOST_CONNECTION_MODE_NONE, \ } #define ESP_OPENTHREAD_DEFAULT_PORT_CONFIG() \ diff --git a/examples/openthread/ot_sleepy_device/light_sleep/main/idf_component.yml b/examples/openthread/ot_sleepy_device/light_sleep/main/idf_component.yml new file mode 100644 index 000000000000..72f76924fe03 --- /dev/null +++ b/examples/openthread/ot_sleepy_device/light_sleep/main/idf_component.yml @@ -0,0 +1,6 @@ +## IDF Component Manager Manifest File +dependencies: + idf: + version: ">=4.1.0" + ot_examples_common: + path: ${IDF_PATH}/examples/openthread/ot_common_components/ot_examples_common diff --git a/examples/openthread/ot_sleepy_device/light_sleep/sdkconfig.defaults b/examples/openthread/ot_sleepy_device/light_sleep/sdkconfig.defaults index 1b7c25c723be..355e9dd3aa41 100644 --- a/examples/openthread/ot_sleepy_device/light_sleep/sdkconfig.defaults +++ b/examples/openthread/ot_sleepy_device/light_sleep/sdkconfig.defaults @@ -23,6 +23,8 @@ CONFIG_OPENTHREAD_BORDER_ROUTER=n CONFIG_OPENTHREAD_MTD=y CONFIG_OPENTHREAD_DNS64_CLIENT=y CONFIG_OPENTHREAD_CLI=y +CONFIG_OPENTHREAD_TASK_SIZE=4096 +CONFIG_OPENTHREAD_CONSOLE_ENABLE=n # end of OpenThread # @@ -51,3 +53,9 @@ CONFIG_IEEE802154_SLEEP_ENABLE=y CONFIG_FREERTOS_HZ=1000 CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y # end of light sleep + +# +# ESP System Settings +# +CONFIG_ESP_MAIN_TASK_STACK_SIZE=6144 +# end of ESP System Settings diff --git a/examples/openthread/ot_trel/README.md b/examples/openthread/ot_trel/README.md index 5cc60dfa2f12..6fcb37e96e96 100644 --- a/examples/openthread/ot_trel/README.md +++ b/examples/openthread/ot_trel/README.md @@ -44,7 +44,7 @@ Now you'll get an OpenThread command line shell. The `help` command will print all of the supported commands. ```bash -> help +esp32s3> ot help I(7058) OPENTHREAD:[INFO]-CLI-----: execute command: help bbr bufferinfo @@ -78,51 +78,51 @@ To run this example, at least two ESP32-S3 boards flashed with this ot_trel exam On the first device, run the following commands: ```bash -> factoryreset +esp32s3> ot factoryreset ... # the device will reboot -> dataset init new +esp32s3> ot dataset init new Done -> dataset commit active +esp32s3> ot dataset commit active Done -> ifconfig up +esp32s3> ot ifconfig up Done -> thread start +esp32s3> ot thread start Done # After some seconds -> state +esp32s3> ot state leader Done ``` Now the first device has formed a Thread network as a leader. Get some information which will be used in next steps: ```bash -> ipaddr +esp32s3> ot ipaddr fdde:ad00:beef:0:0:ff:fe00:fc00 fdde:ad00:beef:0:0:ff:fe00:8000 fdde:ad00:beef:0:a7c6:6311:9c8c:271b fe80:0:0:0:5c27:a723:7115:c8f8 # Get the Active Dataset -> dataset active -x +esp32s3> ot dataset active -x 0e080000000000010000000300001835060004001fffe00208fe7bb701f5f1125d0708fd75cbde7c6647bd0510b3914792d44f45b6c7d76eb9306eec94030f4f70656e5468726561642d35383332010258320410e35c581af5029b054fc904a24c2b27700c0402a0fff8 ``` On the second device, set the active dataset from leader, and start Thread interface: ```bash -> factoryreset +esp32s3> ot factoryreset ... # the device will reboot -> dataset set active 0e080000000000010000000300001835060004001fffe00208fe7bb701f5f1125d0708fd75cbde7c6647bd0510b3914792d44f45b6c7d76eb9306eec94030f4f70656e5468726561642d35383332010258320410e35c581af5029b054fc904a24c2b27700c0402a0fff8 -> ifconfig up +esp32s3> ot dataset set active 0e080000000000010000000300001835060004001fffe00208fe7bb701f5f1125d0708fd75cbde7c6647bd0510b3914792d44f45b6c7d76eb9306eec94030f4f70656e5468726561642d35383332010258320410e35c581af5029b054fc904a24c2b27700c0402a0fff8 +esp32s3> ot ifconfig up Done -> thread start +esp32s3> ot thread start Done # After some seconds -> state +esp32s3> ot state router # child is also a valid state Done ``` diff --git a/examples/openthread/ot_trel/main/Kconfig.projbuild b/examples/openthread/ot_trel/main/Kconfig.projbuild deleted file mode 100644 index a00fd8759180..000000000000 --- a/examples/openthread/ot_trel/main/Kconfig.projbuild +++ /dev/null @@ -1,9 +0,0 @@ -menu "OpenThread TREL Example" - - config OPENTHREAD_AUTO_START - bool 'Enable the automatic start mode.' - default n - help - If enabled, the Openthread Device will create or connect to thread network with pre-configured - network parameters automatically. Otherwise, user need to configure Thread via CLI command manually. -endmenu diff --git a/examples/openthread/ot_trel/main/esp_ot_config.h b/examples/openthread/ot_trel/main/esp_ot_config.h index be8eff0e21cb..f72a321ee6c0 100644 --- a/examples/openthread/ot_trel/main/esp_ot_config.h +++ b/examples/openthread/ot_trel/main/esp_ot_config.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: CC0-1.0 * @@ -22,33 +22,10 @@ .radio_mode = RADIO_MODE_TREL, \ } -#if CONFIG_OPENTHREAD_CONSOLE_TYPE_UART -#define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ - { \ - .host_connection_mode = HOST_CONNECTION_MODE_CLI_UART, \ - .host_uart_config = { \ - .port = 0, \ - .uart_config = \ - { \ - .baud_rate = 115200, \ - .data_bits = UART_DATA_8_BITS, \ - .parity = UART_PARITY_DISABLE, \ - .stop_bits = UART_STOP_BITS_1, \ - .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, \ - .rx_flow_ctrl_thresh = 0, \ - .source_clk = UART_SCLK_DEFAULT, \ - }, \ - .rx_pin = UART_PIN_NO_CHANGE, \ - .tx_pin = UART_PIN_NO_CHANGE, \ - }, \ - } -#elif CONFIG_OPENTHREAD_CONSOLE_TYPE_USB_SERIAL_JTAG #define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ { \ - .host_connection_mode = HOST_CONNECTION_MODE_CLI_USB, \ - .host_usb_config = USB_SERIAL_JTAG_DRIVER_CONFIG_DEFAULT(), \ + .host_connection_mode = HOST_CONNECTION_MODE_NONE, \ } -#endif #define ESP_OPENTHREAD_DEFAULT_PORT_CONFIG() \ { \ diff --git a/examples/openthread/ot_trel/main/esp_ot_trel.c b/examples/openthread/ot_trel/main/esp_ot_trel.c index a333eface5f5..d45b211b7b6b 100644 --- a/examples/openthread/ot_trel/main/esp_ot_trel.c +++ b/examples/openthread/ot_trel/main/esp_ot_trel.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: CC0-1.0 * @@ -23,23 +23,14 @@ #include "esp_netif.h" #include "esp_netif_types.h" #include "esp_openthread.h" -#include "esp_openthread_cli.h" #include "esp_openthread_lock.h" #include "esp_openthread_netif_glue.h" -#include "esp_openthread_types.h" #include "esp_ot_config.h" #include "esp_vfs_eventfd.h" -#include "driver/uart.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "hal/uart_types.h" #include "nvs_flash.h" -#include "openthread/cli.h" -#include "openthread/instance.h" -#include "openthread/logging.h" -#include "openthread/tasklet.h" #include "protocol_examples_common.h" #include "mdns.h" +#include "ot_examples_common.h" #if !CONFIG_EXAMPLE_CONNECT_WIFI && !CONFIG_EXAMPLE_CONNECT_ETHERNET #error No netif for TREL! @@ -56,70 +47,6 @@ #define TAG "ot_esp_trel" -static esp_netif_t *init_openthread_netif(const esp_openthread_platform_config_t *config) -{ - esp_netif_config_t cfg = ESP_NETIF_DEFAULT_OPENTHREAD(); - esp_netif_t *netif = esp_netif_new(&cfg); - assert(netif != NULL); - ESP_ERROR_CHECK(esp_netif_attach(netif, esp_openthread_netif_glue_init(config))); - - return netif; -} - -static void ot_task_worker(void *aContext) -{ - esp_openthread_platform_config_t config = { - .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(), - .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(), - .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(), - }; - - ESP_ERROR_CHECK(example_connect()); - - // Initialize the OpenThread stack - ESP_ERROR_CHECK(esp_openthread_init(&config)); - -#if CONFIG_OPENTHREAD_STATE_INDICATOR_ENABLE - ESP_ERROR_CHECK(esp_openthread_state_indicator_init(esp_openthread_get_instance())); -#endif - -#if CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC - // The OpenThread log level directly matches ESP log level - (void)otLoggingSetLevel(CONFIG_LOG_DEFAULT_LEVEL); -#endif - // Initialize the OpenThread cli -#if CONFIG_OPENTHREAD_CLI - esp_openthread_cli_init(); -#endif - - esp_netif_t *openthread_netif; - // Initialize the esp_netif bindings - openthread_netif = init_openthread_netif(&config); - esp_netif_set_default_netif(openthread_netif); - -#if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION - esp_cli_custom_command_init(); -#endif // CONFIG_OPENTHREAD_CLI_ESP_EXTENSION - - // Run the main loop -#if CONFIG_OPENTHREAD_CLI - esp_openthread_cli_create_task(); -#endif -#if CONFIG_OPENTHREAD_AUTO_START - otOperationalDatasetTlvs dataset; - otError error = otDatasetGetActiveTlvs(esp_openthread_get_instance(), &dataset); - ESP_ERROR_CHECK(esp_openthread_auto_start((error == OT_ERROR_NONE) ? &dataset : NULL)); -#endif - esp_openthread_launch_mainloop(); - - // Clean up - esp_openthread_netif_glue_deinit(); - esp_netif_destroy(openthread_netif); - - esp_vfs_eventfd_unregister(); - vTaskDelete(NULL); -} - void app_main(void) { // Used eventfds: @@ -136,5 +63,27 @@ void app_main(void) ESP_ERROR_CHECK(esp_vfs_eventfd_register(&eventfd_config)); ESP_ERROR_CHECK(mdns_init()); ESP_ERROR_CHECK(mdns_hostname_set("esp-ot-trel")); - xTaskCreate(ot_task_worker, "ot_trel_main", 8192, xTaskGetCurrentTaskHandle(), 5, NULL); + + ESP_ERROR_CHECK(example_connect()); + +#if CONFIG_OPENTHREAD_CLI + ot_console_start(); +#endif + + static esp_openthread_config_t config = { + .netif_config = ESP_NETIF_DEFAULT_OPENTHREAD(), + .platform_config = { + .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(), + .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(), + .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(), + }, + }; + ESP_ERROR_CHECK(esp_openthread_start(&config)); + esp_netif_set_default_netif(esp_openthread_get_netif()); +#if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION + esp_cli_custom_command_init(); +#endif +#if CONFIG_OPENTHREAD_NETWORK_AUTO_START + ot_network_auto_start(); +#endif } diff --git a/examples/openthread/ot_trel/main/idf_component.yml b/examples/openthread/ot_trel/main/idf_component.yml index a52a17085f02..4318a416301b 100644 --- a/examples/openthread/ot_trel/main/idf_component.yml +++ b/examples/openthread/ot_trel/main/idf_component.yml @@ -1,7 +1,7 @@ ## IDF Component Manager Manifest File dependencies: espressif/esp_ot_cli_extension: - version: "~1.2.0" + version: "~1.4.0" espressif/mdns: "^1.0.3" idf: version: ">=4.1.0" @@ -9,3 +9,5 @@ dependencies: path: ${IDF_PATH}/examples/common_components/protocol_examples_common ot_led: path: ${IDF_PATH}/examples/openthread/ot_common_components/ot_led + ot_examples_common: + path: ${IDF_PATH}/examples/openthread/ot_common_components/ot_examples_common diff --git a/examples/openthread/ot_trel/sdkconfig.defaults b/examples/openthread/ot_trel/sdkconfig.defaults index 0e5eb34891f5..92fc2c7df0df 100644 --- a/examples/openthread/ot_trel/sdkconfig.defaults +++ b/examples/openthread/ot_trel/sdkconfig.defaults @@ -25,6 +25,8 @@ CONFIG_OPENTHREAD_BORDER_ROUTER=n CONFIG_OPENTHREAD_DNS64_CLIENT=y CONFIG_OPENTHREAD_RADIO_154_NONE=y CONFIG_OPENTHREAD_RADIO_TREL=y +CONFIG_OPENTHREAD_TASK_SIZE=10240 +CONFIG_OPENTHREAD_CONSOLE_ENABLE=n # end of OpenThread # @@ -49,4 +51,10 @@ CONFIG_EXAMPLE_CONNECT_THREAD=n # Wireless Coexistence # CONFIG_ESP_COEX_SW_COEXIST_ENABLE=n -CONFIG_EXTERNAL_COEX_ENABLE=n +CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE=n + +# +# ESP System Settings +# +CONFIG_ESP_MAIN_TASK_STACK_SIZE=6144 +# end of ESP System Settings diff --git a/examples/peripherals/camera/common_components/dsi_init/example_dsi_init.c b/examples/peripherals/camera/common_components/dsi_init/example_dsi_init.c index 3cd506cfc0c2..3b2413b9888f 100644 --- a/examples/peripherals/camera/common_components/dsi_init/example_dsi_init.c +++ b/examples/peripherals/camera/common_components/dsi_init/example_dsi_init.c @@ -21,7 +21,6 @@ void example_dsi_resource_alloc(esp_lcd_dsi_bus_handle_t *mipi_dsi_bus, esp_lcd_ esp_lcd_dsi_bus_config_t bus_config = { .bus_id = 0, .num_data_lanes = 2, - .phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT, .lane_bit_rate_mbps = 1000, // 1000 Mbps }; ESP_ERROR_CHECK(esp_lcd_new_dsi_bus(&bus_config, mipi_dsi_bus)); diff --git a/examples/peripherals/lcd/mipi_dsi/main/mipi_dsi_lcd_example_main.c b/examples/peripherals/lcd/mipi_dsi/main/mipi_dsi_lcd_example_main.c index a51828a783a3..01cf4f7dfee5 100644 --- a/examples/peripherals/lcd/mipi_dsi/main/mipi_dsi_lcd_example_main.c +++ b/examples/peripherals/lcd/mipi_dsi/main/mipi_dsi_lcd_example_main.c @@ -197,7 +197,6 @@ void app_main(void) esp_lcd_dsi_bus_config_t bus_config = { .bus_id = 0, .num_data_lanes = EXAMPLE_MIPI_DSI_LANE_NUM, - .phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT, .lane_bit_rate_mbps = EXAMPLE_MIPI_DSI_LANE_BITRATE_MBPS, }; ESP_ERROR_CHECK(esp_lcd_new_dsi_bus(&bus_config, &mipi_dsi_bus)); diff --git a/examples/peripherals/temperature_sensor/temp_sensor/README.md b/examples/peripherals/temperature_sensor/temp_sensor/README.md index e798628a4bb4..fe363c9cadd7 100644 --- a/examples/peripherals/temperature_sensor/temp_sensor/README.md +++ b/examples/peripherals/temperature_sensor/temp_sensor/README.md @@ -7,13 +7,13 @@ The ESP32-S2/C3/S3/C2 has a built-in temperature sensor. The temperature sensor The conversion relationship is the first two columns of the table below. Among them, `offset = 0`(default) is the main measurement option, and other values are extended measurement options. -| DAC level | offset | measure range(℃) | measure error(℃) | -| :-------: | :----: | :--------------: | :--------------: | -| 0 | -2 | 50 ~ 125 | < 3 | -| 1 | -1 | 20 ~ 100 | < 2 | -| 2 | 0 | -10 ~ 80 | < 1 | -| 3 | 1 | -30 ~ 50 | < 2 | -| 4 | 2 | -40 ~ 20 | < 3 | +| DAC level | offset | measure range(℃) | +| :-------: | :----: | :--------------: | +| 0 | -2 | 50 ~ 125 | +| 1 | -1 | 20 ~ 100 | +| 2 | 0 | -10 ~ 80 | +| 3 | 1 | -30 ~ 50 | +| 4 | 2 | -40 ~ 20 | ## How to use example diff --git a/examples/peripherals/timer_group/gptimer/pytest_gptimer_example.py b/examples/peripherals/timer_group/gptimer/pytest_gptimer_example.py index 29a534d6110a..db52faffe3b7 100644 --- a/examples/peripherals/timer_group/gptimer/pytest_gptimer_example.py +++ b/examples/peripherals/timer_group/gptimer/pytest_gptimer_example.py @@ -1,6 +1,5 @@ # SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 - import pytest from pytest_embedded import Dut @@ -10,25 +9,25 @@ def test_gptimer_example(dut: Dut) -> None: dut.expect_exact('Create timer handle', timeout=5) dut.expect_exact('Start timer, stop it at alarm event', timeout=5) - res = dut.expect(r'Timer stopped, count=(\d+)', timeout=30) + res = dut.expect(r'Timer stopped, count=(\d+)\D', timeout=30) stopped_count = res.group(1).decode('utf8') assert (1000000 - 20) < int(stopped_count) < (1000000 + 20) dut.expect_exact('Set count value') dut.expect_exact('Get count value') - res = dut.expect(r'Timer count value=(\d+)', timeout=5) + res = dut.expect(r'Timer count value=(\d+)\D', timeout=5) count_val = res.group(1).decode('utf8') assert int(count_val) == 100 dut.expect_exact('Start timer, auto-reload at alarm event', timeout=5) - res = dut.expect(r'Timer reloaded, count=(\d+)', timeout=5) + res = dut.expect(r'Timer reloaded, count=(\d+)\D', timeout=5) reloaded_count = res.group(1).decode('utf8') assert 0 <= int(reloaded_count) < 20 dut.expect_exact('Stop timer') dut.expect_exact('Start timer, update alarm value dynamically') - for i in range(1,5): - res = dut.expect(r'Timer alarmed, count=(\d+)', timeout=5) + for i in range(1, 5): + res = dut.expect(r'Timer alarmed, count=(\d+)\D', timeout=5) alarm_count = res.group(1).decode('utf8') assert (i * 1000000 - 20) < int(alarm_count) < (i * 1000000 + 20) diff --git a/examples/protocols/http_server/captive_portal/main/main.c b/examples/protocols/http_server/captive_portal/main/main.c index 8fd8ef3adea4..ee0d13d5d1de 100644 --- a/examples/protocols/http_server/captive_portal/main/main.c +++ b/examples/protocols/http_server/captive_portal/main/main.c @@ -127,7 +127,7 @@ static const httpd_uri_t root = { esp_err_t http_404_error_handler(httpd_req_t *req, httpd_err_code_t err) { // Set status - httpd_resp_set_status(req, "302 Temporary Redirect"); + httpd_resp_set_status(req, "303 See Other"); // Redirect to the "/" root directory httpd_resp_set_hdr(req, "Location", "/"); // iOS requires content in the response to detect a captive portal, simply redirecting is not sufficient. diff --git a/examples/protocols/static_ip/main/idf_component.yml b/examples/protocols/static_ip/main/idf_component.yml index 4ca406cdcd2a..bab543d22745 100644 --- a/examples/protocols/static_ip/main/idf_component.yml +++ b/examples/protocols/static_ip/main/idf_component.yml @@ -2,4 +2,4 @@ dependencies: idf: version: '>=5.0' espressif/ethernet_init: - version: '*' + version: '1.0.0' diff --git a/examples/system/deep_sleep/sdkconfig.ci.basic b/examples/system/deep_sleep/sdkconfig.ci.basic index 87020672f4c0..a24028f22217 100644 --- a/examples/system/deep_sleep/sdkconfig.ci.basic +++ b/examples/system/deep_sleep/sdkconfig.ci.basic @@ -4,8 +4,7 @@ CONFIG_EXAMPLE_EXT1_WAKEUP=n CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80=y CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=80 -CONFIG_ULP_COPROC_ENABLED=y -CONFIG_ULP_COPROC_RESERVE_MEM=512 + CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y CONFIG_RTC_CLK_SRC_INT_RC=y CONFIG_PARTITION_TABLE_CUSTOM=y diff --git a/examples/system/deep_sleep/sdkconfig.ci.esp32_singlecore b/examples/system/deep_sleep/sdkconfig.ci.esp32_singlecore index 0cabcb5f0277..b5e8d898248b 100644 --- a/examples/system/deep_sleep/sdkconfig.ci.esp32_singlecore +++ b/examples/system/deep_sleep/sdkconfig.ci.esp32_singlecore @@ -9,8 +9,6 @@ CONFIG_EXAMPLE_EXT1_WAKEUP=n CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80=y CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=80 -CONFIG_ULP_COPROC_ENABLED=y -CONFIG_ULP_COPROC_RESERVE_MEM=512 CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y CONFIG_RTC_CLK_SRC_INT_RC=y CONFIG_PARTITION_TABLE_CUSTOM=y diff --git a/examples/system/deep_sleep/sdkconfig.defaults b/examples/system/deep_sleep/sdkconfig.defaults index b508ab21b76f..227ad1e14d75 100644 --- a/examples/system/deep_sleep/sdkconfig.defaults +++ b/examples/system/deep_sleep/sdkconfig.defaults @@ -1,7 +1,5 @@ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80=y CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=80 -CONFIG_ULP_COPROC_ENABLED=y -CONFIG_ULP_COPROC_RESERVE_MEM=512 CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y CONFIG_RTC_CLK_SRC_INT_RC=y CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y diff --git a/examples/wifi/ftm/main/ftm_main.c b/examples/wifi/ftm/main/ftm_main.c index b6eb413ab769..98c02c98dbd0 100644 --- a/examples/wifi/ftm/main/ftm_main.c +++ b/examples/wifi/ftm/main/ftm_main.c @@ -82,7 +82,6 @@ static const char *TAG_AP = "ftm_ap"; static EventGroupHandle_t s_wifi_event_group; static const int CONNECTED_BIT = BIT0; -static const int DISCONNECTED_BIT = BIT1; static EventGroupHandle_t s_ftm_event_group; static const int FTM_REPORT_BIT = BIT0; @@ -90,8 +89,6 @@ static const int FTM_FAILURE_BIT = BIT1; static uint8_t s_ftm_report_num_entries; static uint32_t s_rtt_est, s_dist_est; static bool s_ap_started; -static uint8_t s_ap_channel; -static uint8_t s_ap_bssid[ETH_ALEN]; const int g_report_lvl = #ifdef CONFIG_ESP_FTM_REPORT_SHOW_DIAG @@ -120,9 +117,6 @@ static void event_handler(void *arg, esp_event_base_t event_base, ESP_LOGI(TAG_STA, "Connected to %s (BSSID: "MACSTR", Channel: %d)", event->ssid, MAC2STR(event->bssid), event->channel); - memcpy(s_ap_bssid, event->bssid, ETH_ALEN); - s_ap_channel = event->channel; - xEventGroupClearBits(s_wifi_event_group, DISCONNECTED_BIT); xEventGroupSetBits(s_wifi_event_group, CONNECTED_BIT); } else if (event_id == WIFI_EVENT_STA_DISCONNECTED) { if (s_reconnect && ++s_retry_num < MAX_CONNECT_RETRY_ATTEMPTS) { @@ -132,7 +126,6 @@ static void event_handler(void *arg, esp_event_base_t event_base, ESP_LOGI(TAG_STA, "sta disconnected"); } xEventGroupClearBits(s_wifi_event_group, CONNECTED_BIT); - xEventGroupSetBits(s_wifi_event_group, DISCONNECTED_BIT); } else if (event_id == WIFI_EVENT_FTM_REPORT) { wifi_event_ftm_report_t *event = (wifi_event_ftm_report_t *) event_data; @@ -269,12 +262,12 @@ esp_err_t wifi_add_mode(wifi_mode_t mode) if (mode == WIFI_MODE_STA) { if (cur_mode == WIFI_MODE_STA || cur_mode == WIFI_MODE_APSTA) { - int bits = xEventGroupWaitBits(s_wifi_event_group, CONNECTED_BIT, 0, 1, 0); - if (bits & CONNECTED_BIT) { + wifi_ap_record_t ap_info; + esp_err_t ret = esp_wifi_sta_get_ap_info(&ap_info); + if (ret == ESP_OK) { s_reconnect = false; xEventGroupClearBits(s_wifi_event_group, CONNECTED_BIT); ESP_ERROR_CHECK( esp_wifi_disconnect() ); - xEventGroupWaitBits(s_wifi_event_group, DISCONNECTED_BIT, 0, 1, portMAX_DELAY); } return ESP_OK; } else if (cur_mode == WIFI_MODE_AP) { @@ -314,7 +307,7 @@ static bool wifi_cmd_sta_join(const char *ssid, const char *pass) s_reconnect = true; s_retry_num = 0; - xEventGroupWaitBits(s_wifi_event_group, CONNECTED_BIT, 0, 1, 5000 / portTICK_PERIOD_MS); + xEventGroupWaitBits(s_wifi_event_group, CONNECTED_BIT, pdTRUE, pdTRUE, 5000 / portTICK_PERIOD_MS); return true; } @@ -329,9 +322,14 @@ static int wifi_cmd_sta(int argc, char **argv) } if (sta_args.disconnect->count) { s_reconnect = false; + wifi_ap_record_t ap_info; + esp_err_t ret = esp_wifi_sta_get_ap_info(&ap_info); + if (ret != ESP_OK) { + ESP_LOGE(TAG_STA, "Sta Already disconnected"); + return 0; + } xEventGroupClearBits(s_wifi_event_group, CONNECTED_BIT); esp_wifi_disconnect(); - xEventGroupWaitBits(s_wifi_event_group, DISCONNECTED_BIT, 0, 1, portMAX_DELAY); return 0; } @@ -469,19 +467,30 @@ static int wifi_cmd_query(int argc, char **argv) { wifi_config_t cfg; wifi_mode_t mode; + wifi_ap_record_t ap_info; esp_wifi_get_mode(&mode); if (WIFI_MODE_AP == mode) { esp_wifi_get_config(WIFI_IF_AP, &cfg); ESP_LOGI(TAG_AP, "AP mode, %s %s", cfg.ap.ssid, cfg.ap.password); } else if (WIFI_MODE_STA == mode) { - int bits = xEventGroupWaitBits(s_wifi_event_group, CONNECTED_BIT, 0, 1, 0); - if (bits & CONNECTED_BIT) { - esp_wifi_get_config(WIFI_IF_STA, &cfg); - ESP_LOGI(TAG_STA, "sta mode, connected %s", cfg.ap.ssid); + esp_err_t ret = esp_wifi_sta_get_ap_info(&ap_info); + if (ret == ESP_OK) { + ESP_LOGI(TAG_STA, "sta mode, connected %s", ap_info.ssid); + } else { + ESP_LOGI(TAG_STA, "sta mode, disconnected"); + } + } else if (WIFI_MODE_APSTA == mode) { + ESP_LOGI(TAG_STA, "AP-Sta mode"); + esp_wifi_get_config(WIFI_IF_AP, &cfg); + ESP_LOGI(TAG_AP, "AP mode, %s %s", cfg.ap.ssid, cfg.ap.password); + esp_err_t ret = esp_wifi_sta_get_ap_info(&ap_info); + if (ret == ESP_OK) { + ESP_LOGI(TAG_STA, "sta mode, connected %s", ap_info.ssid); } else { ESP_LOGI(TAG_STA, "sta mode, disconnected"); } + } else { ESP_LOGI(TAG_STA, "NULL mode"); return 0; @@ -528,7 +537,7 @@ wifi_ap_record_t *find_ftm_responder_ap(const char *ssid) static int wifi_cmd_ftm(int argc, char **argv) { int nerrors = arg_parse(argc, argv, (void **) &ftm_args); - wifi_ap_record_t *ap_record; + wifi_ap_record_t *ap_record, ap_info; uint32_t wait_time_ms = DEFAULT_WAIT_TIME_MS; EventBits_t bits; @@ -551,10 +560,10 @@ static int wifi_cmd_ftm(int argc, char **argv) if (ftm_args.responder->count != 0) goto ftm_responder; - bits = xEventGroupWaitBits(s_wifi_event_group, CONNECTED_BIT, 0, 1, 0); - if (bits & CONNECTED_BIT && !ftm_args.ssid->count) { - memcpy(ftmi_cfg.resp_mac, s_ap_bssid, ETH_ALEN); - ftmi_cfg.channel = s_ap_channel; + esp_err_t ret = esp_wifi_sta_get_ap_info(&ap_info); + if (ret == ESP_OK && !ftm_args.ssid->count) { + memcpy(ftmi_cfg.resp_mac, ap_info.bssid, ETH_ALEN); + ftmi_cfg.channel = ap_info.primary; } else if (ftm_args.ssid->count == 1) { ap_record = find_ftm_responder_ap(ftm_args.ssid->sval[0]); if (ap_record) { diff --git a/examples/wifi/wps/main/wps.c b/examples/wifi/wps/main/wps.c index 8ba96a3c20d5..882a1f7201d5 100644 --- a/examples/wifi/wps/main/wps.c +++ b/examples/wifi/wps/main/wps.c @@ -7,27 +7,28 @@ CONDITIONS OF ANY KIND, either express or implied. */ -/* - This example demonstrates how to use WPS. - It supports two modes, which can be selected in menuconfig. - - WPS_TYPE_PBC: - Start ESP32 and it will enter WPS PBC mode. Then push WPS button on the router. - ESP32 will receive SSID and password, and connect to the router. - - WPS_TYPE_PIN: - Start ESP32, you'll see an eight-digit PIN number in log output. - Enter the PIN code on the router and then the ESP32 will get connected to router. -*/ - +/** + * @brief Demonstrates how to use WPS. + * + * This example supports two modes, which can be selected in menuconfig: + * + * - WPS_TYPE_PBC: + * Start the ESP device and it will enter WPS PBC mode. Then push the WPS button on the router. + * The ESP device will receive the SSID and password and connect to the router. + * + * - WPS_TYPE_PIN: + * Start the ESP device, and you'll see an eight-digit PIN number in the log output. + * Enter this PIN code on the router, and the ESP device will connect. + * + */ +#include #include "freertos/FreeRTOS.h" #include "freertos/event_groups.h" -#include "esp_wifi.h" +#include "esp_event.h" #include "esp_log.h" +#include "esp_wifi.h" #include "esp_wps.h" -#include "esp_event.h" #include "nvs_flash.h" -#include /*set wps mode via project configuration */ @@ -48,9 +49,50 @@ static const char *TAG = "example_wps"; static esp_wps_config_t config = WPS_CONFIG_INIT_DEFAULT(WPS_MODE); -static wifi_config_t wps_ap_creds[MAX_WPS_AP_CRED]; +static wifi_config_t s_wps_ap_creds[MAX_WPS_AP_CRED]; static int s_ap_creds_num = 0; static int s_retry_num = 0; +static bool s_wps_done = false; + +static void wps_restart(void) +{ + ESP_ERROR_CHECK(esp_wifi_wps_disable()); + ESP_ERROR_CHECK(esp_wifi_wps_enable(&config)); + ESP_ERROR_CHECK(esp_wifi_wps_start(0)); +} + +static void handle_wps_success(void *event_data) +{ + wifi_event_sta_wps_er_success_t *evt = (wifi_event_sta_wps_er_success_t *)event_data; + if (evt) { + s_ap_creds_num = evt->ap_cred_cnt; + for (int idx = 0; idx < s_ap_creds_num; idx++) { + memcpy(s_wps_ap_creds[idx].sta.ssid, evt->ap_cred[idx].ssid, + sizeof(evt->ap_cred[idx].ssid)); + memcpy(s_wps_ap_creds[idx].sta.password, evt->ap_cred[idx].passphrase, + sizeof(evt->ap_cred[idx].passphrase)); + } + /* If multiple AP credentials are received from WPS, connect with first one */ + ESP_LOGI(TAG, "Connecting to SSID: %s, Passphrase: %s", + s_wps_ap_creds[0].sta.ssid, s_wps_ap_creds[0].sta.password); + ESP_ERROR_CHECK(esp_wifi_set_config(WIFI_IF_STA, &s_wps_ap_creds[0])); + } + /* + * If only one AP credential is received from WPS, there will be no event data and + * esp_wifi_set_config() is already called by WPS modules for backward compatibility + * with legacy apps. So directly attempt connection here. + */ + ESP_ERROR_CHECK(esp_wifi_wps_disable()); + s_wps_done = true; + esp_wifi_connect(); +} + +static void handle_wps_pin(void *event_data) +{ + /* display the PIN code */ + wifi_event_sta_wps_er_pin_t* event = (wifi_event_sta_wps_er_pin_t*) event_data; + ESP_LOGI(TAG, "WPS_PIN = " PINSTR, PIN2STR(event->pin_code)); +} static void wifi_event_handler(void* arg, esp_event_base_t event_base, int32_t event_id, void* event_data) @@ -58,78 +100,46 @@ static void wifi_event_handler(void* arg, esp_event_base_t event_base, static int ap_idx = 1; switch (event_id) { - case WIFI_EVENT_STA_START: - ESP_LOGI(TAG, "WIFI_EVENT_STA_START"); - break; - case WIFI_EVENT_STA_DISCONNECTED: - ESP_LOGI(TAG, "WIFI_EVENT_STA_DISCONNECTED"); + case WIFI_EVENT_STA_START: + ESP_LOGI(TAG, "WIFI_EVENT_STA_START"); + break; + case WIFI_EVENT_STA_DISCONNECTED: + ESP_LOGI(TAG, "WIFI_EVENT_STA_DISCONNECTED"); + if (s_wps_done) { if (s_retry_num < MAX_RETRY_ATTEMPTS) { esp_wifi_connect(); s_retry_num++; + ESP_LOGI(TAG, "retrying to connect to the AP"); } else if (ap_idx < s_ap_creds_num) { /* Try the next AP credential if first one fails */ - - if (ap_idx < s_ap_creds_num) { - ESP_LOGI(TAG, "Connecting to SSID: %s, Passphrase: %s", - wps_ap_creds[ap_idx].sta.ssid, wps_ap_creds[ap_idx].sta.password); - ESP_ERROR_CHECK(esp_wifi_set_config(WIFI_IF_STA, &wps_ap_creds[ap_idx++]) ); - esp_wifi_connect(); - } + ESP_LOGI(TAG, "Connecting to SSID: %s, Passphrase: %s", + s_wps_ap_creds[ap_idx].sta.ssid, s_wps_ap_creds[ap_idx].sta.password); + ESP_ERROR_CHECK(esp_wifi_set_config(WIFI_IF_STA, &s_wps_ap_creds[ap_idx++])); + esp_wifi_connect(); s_retry_num = 0; } else { ESP_LOGI(TAG, "Failed to connect!"); } - - break; - case WIFI_EVENT_STA_WPS_ER_SUCCESS: - ESP_LOGI(TAG, "WIFI_EVENT_STA_WPS_ER_SUCCESS"); - { - wifi_event_sta_wps_er_success_t *evt = - (wifi_event_sta_wps_er_success_t *)event_data; - int i; - - if (evt) { - s_ap_creds_num = evt->ap_cred_cnt; - for (i = 0; i < s_ap_creds_num; i++) { - memcpy(wps_ap_creds[i].sta.ssid, evt->ap_cred[i].ssid, - sizeof(evt->ap_cred[i].ssid)); - memcpy(wps_ap_creds[i].sta.password, evt->ap_cred[i].passphrase, - sizeof(evt->ap_cred[i].passphrase)); - } - /* If multiple AP credentials are received from WPS, connect with first one */ - ESP_LOGI(TAG, "Connecting to SSID: %s, Passphrase: %s", - wps_ap_creds[0].sta.ssid, wps_ap_creds[0].sta.password); - ESP_ERROR_CHECK(esp_wifi_set_config(WIFI_IF_STA, &wps_ap_creds[0]) ); - } - /* - * If only one AP credential is received from WPS, there will be no event data and - * esp_wifi_set_config() is already called by WPS modules for backward compatibility - * with legacy apps. So directly attempt connection here. - */ - ESP_ERROR_CHECK(esp_wifi_wps_disable()); - esp_wifi_connect(); - } - break; - case WIFI_EVENT_STA_WPS_ER_FAILED: - ESP_LOGI(TAG, "WIFI_EVENT_STA_WPS_ER_FAILED"); - ESP_ERROR_CHECK(esp_wifi_wps_disable()); - ESP_ERROR_CHECK(esp_wifi_wps_enable(&config)); - ESP_ERROR_CHECK(esp_wifi_wps_start(0)); - break; - case WIFI_EVENT_STA_WPS_ER_TIMEOUT: - ESP_LOGI(TAG, "WIFI_EVENT_STA_WPS_ER_TIMEOUT"); - ESP_ERROR_CHECK(esp_wifi_wps_disable()); - ESP_ERROR_CHECK(esp_wifi_wps_enable(&config)); - ESP_ERROR_CHECK(esp_wifi_wps_start(0)); - break; - case WIFI_EVENT_STA_WPS_ER_PIN: - ESP_LOGI(TAG, "WIFI_EVENT_STA_WPS_ER_PIN"); - /* display the PIN code */ - wifi_event_sta_wps_er_pin_t* event = (wifi_event_sta_wps_er_pin_t*) event_data; - ESP_LOGI(TAG, "WPS_PIN = " PINSTR, PIN2STR(event->pin_code)); - break; - default: - break; + } + break; + case WIFI_EVENT_STA_WPS_ER_SUCCESS: + ESP_LOGI(TAG, "WIFI_EVENT_STA_WPS_ER_SUCCESS"); + handle_wps_success(event_data); + break; + case WIFI_EVENT_STA_WPS_ER_FAILED: + ESP_LOGI(TAG, "WIFI_EVENT_STA_WPS_ER_FAILED"); + wps_restart(); + break; + case WIFI_EVENT_STA_WPS_ER_TIMEOUT: + ESP_LOGI(TAG, "WIFI_EVENT_STA_WPS_ER_TIMEOUT"); + wps_restart(); + break; + case WIFI_EVENT_STA_WPS_ER_PIN: + ESP_LOGI(TAG, "WIFI_EVENT_STA_WPS_ER_PIN"); + handle_wps_pin(event_data); + break; + default: + break; } } @@ -140,7 +150,9 @@ static void got_ip_event_handler(void* arg, esp_event_base_t event_base, ESP_LOGI(TAG, "got ip: " IPSTR, IP2STR(&event->ip_info.ip)); } -/*init wifi as sta and start wps*/ +/** + * @brief Start WPS registration + */ static void start_wps(void) { ESP_ERROR_CHECK(esp_netif_init()); diff --git a/examples/zigbee/light_sample/HA_on_off_light/main/CMakeLists.txt b/examples/zigbee/light_sample/HA_on_off_light/main/CMakeLists.txt index 15343efb83ce..1242c913d4df 100644 --- a/examples/zigbee/light_sample/HA_on_off_light/main/CMakeLists.txt +++ b/examples/zigbee/light_sample/HA_on_off_light/main/CMakeLists.txt @@ -1,4 +1,4 @@ idf_component_register( - SRC_DIRS "." "../../../common/zcl_utility/src" - INCLUDE_DIRS "." "../../../common/zcl_utility/include" + SRC_DIRS "." + INCLUDE_DIRS "." ) diff --git a/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.c b/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.c index 4f3256c5578c..916baa2fc5e2 100644 --- a/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.c +++ b/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.c @@ -17,6 +17,7 @@ #include "esp_log.h" #include "nvs_flash.h" #include "ha/esp_zigbee_ha_standard.h" +#include "zcl_utility.h" #include "esp_zb_light.h" #if !defined ZB_ED_ROLE diff --git a/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.h b/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.h index 3f4a751c6729..ed2da9d632da 100644 --- a/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.h +++ b/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.h @@ -14,7 +14,6 @@ #include "esp_zigbee_core.h" #include "light_driver.h" -#include "zcl_utility.h" /* Zigbee configuration */ #define INSTALLCODE_POLICY_ENABLE false /* enable the install code policy for security */ diff --git a/examples/zigbee/light_sample/HA_on_off_light/main/idf_component.yml b/examples/zigbee/light_sample/HA_on_off_light/main/idf_component.yml index 198da019c3d5..bfdc772840da 100644 --- a/examples/zigbee/light_sample/HA_on_off_light/main/idf_component.yml +++ b/examples/zigbee/light_sample/HA_on_off_light/main/idf_component.yml @@ -6,3 +6,5 @@ dependencies: ## Required IDF version idf: version: ">=5.0.0" + examples_utils: + path: ${IDF_PATH}/examples/zigbee/zb_common_components/examples_utils diff --git a/examples/zigbee/light_sample/HA_on_off_switch/main/CMakeLists.txt b/examples/zigbee/light_sample/HA_on_off_switch/main/CMakeLists.txt index 15343efb83ce..1242c913d4df 100644 --- a/examples/zigbee/light_sample/HA_on_off_switch/main/CMakeLists.txt +++ b/examples/zigbee/light_sample/HA_on_off_switch/main/CMakeLists.txt @@ -1,4 +1,4 @@ idf_component_register( - SRC_DIRS "." "../../../common/zcl_utility/src" - INCLUDE_DIRS "." "../../../common/zcl_utility/include" + SRC_DIRS "." + INCLUDE_DIRS "." ) diff --git a/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.c b/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.c index 64459f04b310..fbf140207c78 100644 --- a/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.c +++ b/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.c @@ -20,6 +20,7 @@ #include "esp_log.h" #include "nvs_flash.h" #include "ha/esp_zigbee_ha_standard.h" +#include "zcl_utility.h" #include "esp_zb_switch.h" #if defined ZB_ED_ROLE diff --git a/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.h b/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.h index 32a6dc9edf08..8993eb969e67 100644 --- a/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.h +++ b/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.h @@ -13,7 +13,6 @@ */ #include "esp_zigbee_core.h" #include "switch_driver.h" -#include "zcl_utility.h" /* Zigbee configuration */ #define MAX_CHILDREN 10 /* the max amount of connected devices */ diff --git a/examples/zigbee/light_sample/HA_on_off_switch/main/idf_component.yml b/examples/zigbee/light_sample/HA_on_off_switch/main/idf_component.yml index ad32c63b48e5..bfb3027106a0 100644 --- a/examples/zigbee/light_sample/HA_on_off_switch/main/idf_component.yml +++ b/examples/zigbee/light_sample/HA_on_off_switch/main/idf_component.yml @@ -5,3 +5,5 @@ dependencies: ## Required IDF version idf: version: ">=5.0.0" + examples_utils: + path: ${IDF_PATH}/examples/zigbee/zb_common_components/examples_utils diff --git a/examples/zigbee/zb_common_components/examples_utils/CMakeLists.txt b/examples/zigbee/zb_common_components/examples_utils/CMakeLists.txt new file mode 100644 index 000000000000..7eafd7b4d21d --- /dev/null +++ b/examples/zigbee/zb_common_components/examples_utils/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRCS "zcl_utility.c" + INCLUDE_DIRS "include" + PRIV_REQUIRES espressif__esp-zigbee-lib) diff --git a/examples/zigbee/common/zcl_utility/include/zcl_utility.h b/examples/zigbee/zb_common_components/examples_utils/include/zcl_utility.h similarity index 76% rename from examples/zigbee/common/zcl_utility/include/zcl_utility.h rename to examples/zigbee/zb_common_components/examples_utils/include/zcl_utility.h index 760bf7e10b50..afd1293a869c 100644 --- a/examples/zigbee/common/zcl_utility/include/zcl_utility.h +++ b/examples/zigbee/zb_common_components/examples_utils/include/zcl_utility.h @@ -1,27 +1,26 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: LicenseRef-Included * - * Zigbee Common + * ZCL utility functions for Zigbee examples * * This example code is in the Public Domain (or CC0 licensed, at your option.) * * Unless required by applicable law or agreed to in writing, this * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR * CONDITIONS OF ANY KIND, either express or implied. - */ +*/ #pragma once +#include "esp_err.h" +#include "esp_zigbee_core.h" + #ifdef __cplusplus extern "C" { #endif -#include "esp_err.h" -#include "esp_check.h" -#include "esp_zigbee_core.h" - /*! Maximum length of ManufacturerName string field */ #define ESP_ZB_ZCL_CLUSTER_ID_BASIC_MANUFACTURER_NAME_MAX_LEN 32 @@ -37,9 +36,9 @@ typedef struct zcl_basic_manufacturer_info_s { /** * @brief Adds manufacturer information to the ZCL basic cluster of endpoint * - * @param[in] ep_list The pointer to the endpoint list with @p endpoint_id - * @param[in] endpoint_id The endpoint identifier indicating where the ZCL basic cluster resides - * @param[in] info The pointer to the basic manufacturer information + * @param ep_list The pointer to the endpoint list with @p endpoint_id + * @param endpoint_id The endpoint identifier indicating where the ZCL basic cluster resides + * @param info The pointer to the basic manufacturer information, @see zcl_basic_manufacturer_info_t * @return * - ESP_OK: On success * - ESP_ERR_INVALID_ARG: Invalid argument diff --git a/examples/zigbee/common/zcl_utility/src/zcl_utility.c b/examples/zigbee/zb_common_components/examples_utils/zcl_utility.c similarity index 91% rename from examples/zigbee/common/zcl_utility/src/zcl_utility.c rename to examples/zigbee/zb_common_components/examples_utils/zcl_utility.c index c88d6cd8bc8f..65c6fdec9d61 100644 --- a/examples/zigbee/common/zcl_utility/src/zcl_utility.c +++ b/examples/zigbee/zb_common_components/examples_utils/zcl_utility.c @@ -1,21 +1,24 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: LicenseRef-Included * - * Zigbee Common + * ZCL utility functions for Zigbee examples * * This example code is in the Public Domain (or CC0 licensed, at your option.) * * Unless required by applicable law or agreed to in writing, this * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR * CONDITIONS OF ANY KIND, either express or implied. - */ +*/ + +#include +#include + #include "esp_check.h" -#include "stdio.h" -#include "string.h" +#include "esp_zigbee_core.h" + #include "zcl_utility.h" -#include static const char *TAG = "ZCL_UTILITY"; diff --git a/tools/ci/astyle-rules.yml b/tools/ci/astyle-rules.yml index 12da05ef74e8..1e8b4ebd6094 100644 --- a/tools/ci/astyle-rules.yml +++ b/tools/ci/astyle-rules.yml @@ -156,6 +156,7 @@ components_not_formatted_permanent: - "/components/rt/" # SoC header files (generated) - "/components/soc/*/include/soc/" + - "/components/soc/*/register/hw_ver*/soc/" # Example resource files (generated) - "/examples/peripherals/lcd/i80_controller/main/images/" - "/examples/peripherals/dac/dac_continuous/dac_audio/main/audio_example_file.h" diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 283a618310c8..80c5bc024dd9 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -824,6 +824,10 @@ examples/bluetooth/esp_ble_mesh/aligenie_demo/components/vendor_model/include/ge examples/bluetooth/esp_ble_mesh/aligenie_demo/components/vendor_model/include/genie_timer.h examples/bluetooth/esp_ble_mesh/aligenie_demo/components/vendor_model/include/genie_util.h examples/bluetooth/nimble/ble_ancs/main/main.c +examples/bluetooth/nimble/ble_chan_sound_initiator/main/gatt_svr.c +examples/bluetooth/nimble/ble_chan_sound_reflector/main/ble_chan_reflector.h +examples/bluetooth/nimble/ble_chan_sound_reflector/main/gatt_svr.c +examples/bluetooth/nimble/ble_chan_sound_reflector/main/main.c examples/bluetooth/nimble/blecent/main/blecent.h examples/bluetooth/nimble/blecent/main/main.c examples/bluetooth/nimble/blecsc/main/blecsc_sens.h diff --git a/tools/ci/dynamic_pipelines/scripts/generate_target_test_child_pipeline.py b/tools/ci/dynamic_pipelines/scripts/generate_target_test_child_pipeline.py index 54fffd1d0be1..46e934f8a4de 100644 --- a/tools/ci/dynamic_pipelines/scripts/generate_target_test_child_pipeline.py +++ b/tools/ci/dynamic_pipelines/scripts/generate_target_test_child_pipeline.py @@ -1,4 +1,4 @@ -# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 """This file is used for generating the child pipeline for target test jobs. @@ -48,7 +48,7 @@ def get_tags_with_amount(s: str) -> t.List[str]: def get_target_test_jobs( - paths: str, apps: t.List[App], exclude_runner_tags: t.Set[str] + paths: str, apps: t.List[App], exclude_runner_tags: t.Set[str], exclude_runner_tags_matching: t.List[t.Set] ) -> t.Tuple[t.List[Job], t.List[str], t.List[str]]: """ Return the target test jobs and the extra yaml files to include @@ -82,6 +82,10 @@ def get_target_test_jobs( print('WARNING: excluding test cases with runner tags:', runner_tags) continue + if any(set(runner_tags) & group for group in exclude_runner_tags_matching): + print(f'WARNING: Excluding test cases with runner tags (wildcard match): {runner_tags}') + continue + target_test_job = TargetTestJob( name=f'{target_selector} - {",".join(env_markers)}', tags=runner_tags, @@ -116,16 +120,38 @@ def generate_target_test_child_pipeline( with open(KNOWN_GENERATE_TEST_CHILD_PIPELINE_WARNINGS_FILEPATH) as fr: known_warnings_dict = yaml.safe_load(fr) or dict() - exclude_runner_tags_set = set(known_warnings_dict.get('no_runner_tags', [])) + def _process_match_group(runner_tags: str) -> t.Union[t.Set, None]: + match_group = {_el for _el in runner_tags.split(',') if _el != '*'} + if len(match_group) == 0: + print('WARNING: wildcard exclusion requires at least one specific tag — skipped') + return None + return match_group + + exclude_runner_tags_set = set() + exclude_runner_tags_matching = [] + for _tag in known_warnings_dict.get('no_runner_tags', []): + if '*' not in _tag: + exclude_runner_tags_set.add(_tag) + else: + if res := _process_match_group(_tag): + exclude_runner_tags_matching.append(res) + # EXCLUDE_RUNNER_TAGS is a string separated by ';' # like 'esp32,generic;esp32c3,wifi' + # or with wildcard like 'esp32,*; esp32p4,wifi,*' if exclude_runner_tags := os.getenv('EXCLUDE_RUNNER_TAGS'): - exclude_runner_tags_set.update(exclude_runner_tags.split(';')) + for _tag in exclude_runner_tags.split(';'): + if '*' not in _tag: + exclude_runner_tags_set.add(_tag) + else: + if res := _process_match_group(_tag): + exclude_runner_tags_matching.append(res) target_test_jobs, extra_include_yml, no_env_marker_test_cases = get_target_test_jobs( paths=paths, apps=apps, exclude_runner_tags=exclude_runner_tags_set, + exclude_runner_tags_matching=exclude_runner_tags_matching, ) known_no_env_marker_test_cases = set(known_warnings_dict.get('no_env_marker_test_cases', [])) diff --git a/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml b/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml index 09dc5aae94c5..c9314a7b59f5 100644 --- a/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml +++ b/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml @@ -28,5 +28,7 @@ no_runner_tags: - esp32c61,generic - esp32c61,jtag - esp32h2,jtag + - esp32p4,* - esp32p4,jtag + - esp32p4_2,* - esp32s2,usb_host_flash_disk diff --git a/tools/cmake/depgraph.cmake b/tools/cmake/depgraph.cmake index fc312db7adef..9e806662653a 100644 --- a/tools/cmake/depgraph.cmake +++ b/tools/cmake/depgraph.cmake @@ -35,10 +35,10 @@ function(depgraph_add_edge dep_from dep_to) # However, show which components are "common" by adding an edge from a node named "common". # If necessary, add a new build property to customize this behavior. if(NOT dep_from IN_LIST common_reqs) - idf_build_set_property(__BUILD_COMPONENT_DEPGRAPH "common -> ${dep_to}" APPEND) + idf_build_set_property(__BUILD_COMPONENT_DEPGRAPH "\"common\" -> \"${dep_to}\"" APPEND) endif() else() - idf_build_set_property(__BUILD_COMPONENT_DEPGRAPH "${dep_from} -> ${dep_to} ${attr}" APPEND) + idf_build_set_property(__BUILD_COMPONENT_DEPGRAPH "\"${dep_from}\" -> \"${dep_to}\" ${attr}" APPEND) endif() endfunction() diff --git a/tools/cmake/kconfig.cmake b/tools/cmake/kconfig.cmake index 22bb1b9063a4..fe96443e65c3 100644 --- a/tools/cmake/kconfig.cmake +++ b/tools/cmake/kconfig.cmake @@ -253,6 +253,9 @@ function(__kconfig_generate_config sdkconfig sdkconfig_defaults) endif() # Generate the menuconfig target + # WARNING: If you change anything here, please ensure that only the necessary files are touched! + # If unnecessary files (those not affected by the change from menuconfig) are touched + # (their timestamp changed), it will cause unnecessary rebuilds of the whole project! add_custom_target(menuconfig ${menuconfig_depends} # create any missing config file, with defaults if necessary @@ -263,7 +266,7 @@ function(__kconfig_generate_config sdkconfig sdkconfig_defaults) --env "IDF_ENV_FPGA=${idf_env_fpga}" --env "IDF_INIT_VERSION=${idf_init_version}" --dont-write-deprecated - ${kconfgen_output_options} + --output config ${sdkconfig} # Do NOT regenerate the rest of the config files! COMMAND ${TERM_CHECK_CMD} COMMAND ${CMAKE_COMMAND} -E env "COMPONENT_KCONFIGS_SOURCE_FILE=${kconfigs_path}" @@ -275,8 +278,8 @@ function(__kconfig_generate_config sdkconfig sdkconfig_defaults) "IDF_INIT_VERSION=${idf_init_version}" ${MENUCONFIG_CMD} ${root_kconfig} USES_TERMINAL - # additional run of kconfgen esures that the deprecated options will be inserted into sdkconfig (for backward - # compatibility) + # additional run of kconfgen ensures that the deprecated options will be inserted into config files + # (for backward compatibility) COMMAND ${kconfgen_basecommand} --env "IDF_TARGET=${idf_target}" --env "IDF_TOOLCHAIN=${idf_toolchain}" diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index 9493dd6bdb6f..77288bd758f6 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -54,9 +54,11 @@ ARG IDF_CHECKOUT_REF= ARG IDF_CLONE_SHALLOW= ARG IDF_CLONE_SHALLOW_DEPTH=1 ARG IDF_INSTALL_TARGETS=all +ARG IDF_GITHUB_ASSETS= ENV IDF_PATH=/opt/esp/idf ENV IDF_TOOLS_PATH=/opt/esp +ENV IDF_GITHUB_ASSETS=${IDF_GITHUB_ASSETS} # install build essential needed for linux target apps, which is a preview target so it is installed with "all" only RUN if [ "$IDF_INSTALL_TARGETS" = "all" ]; then \ diff --git a/tools/idf_py_actions/core_ext.py b/tools/idf_py_actions/core_ext.py index 93d34461a56b..51f52262ca59 100644 --- a/tools/idf_py_actions/core_ext.py +++ b/tools/idf_py_actions/core_ext.py @@ -1,4 +1,4 @@ -# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 import fnmatch import glob @@ -49,6 +49,37 @@ def build_target(target_name: str, ctx: Context, args: PropertyDict) -> None: ensure_build_directory(args, ctx.info_name) run_target(target_name, args, force_progression=GENERATORS[args.generator].get('force_progression', False)) + def confserver_target(target_name: str, ctx: Context, args: PropertyDict, buffer_size: int) -> None: + """ + Execute the idf.py confserver command with the specified buffer size. + """ + ensure_build_directory(args, ctx.info_name) + if buffer_size < 2048: + yellow_print( + f'WARNING: The specified buffer size {buffer_size} KB is less than the ' + 'recommended minimum of 2048 KB for idf.py confserver. Consider increasing it to at least 2048 KB ' + 'by setting environment variable IDF_CONFSERVER_BUFFER_SIZE= or by calling ' + 'idf.py confserver --buffer-size .' + ) + try: + run_target( + target_name, + args, + force_progression=GENERATORS[args.generator].get('force_progression', False), + buffer_size=buffer_size, + ) + except ValueError as e: + if str(e) == 'Separator is not found, and chunk exceed the limit': + # Buffer size too small/one-line output of the command too long + raise FatalError( + f'ERROR: Command failed with an error message "{e}". ' + 'Try increasing the buffer size to 2048 (or higher) by setting environment variable ' + 'IDF_CONFSERVER_BUFFER_SIZE= or by calling ' + 'idf.py confserver --buffer-size .' + ) + else: + raise + def size_target(target_name: str, ctx: Context, args: PropertyDict, output_format: str, output_file: str, diff_map_file: str, legacy: bool) -> None: """ @@ -467,9 +498,22 @@ def help_and_exit(action: str, ctx: Context, param: List, json_option: bool, add ], }, 'confserver': { - 'callback': build_target, + 'callback': confserver_target, 'help': 'Run JSON configuration server.', - 'options': global_options, + 'options': global_options + + [ + { + 'names': ['--buffer-size'], + 'help': ( + 'Set the buffer size (in KB) in order to accommodate initial confserver response.' + 'Default value and recommended minimum is 2048 (KB), but it might need to be ' + 'increased for very large projects.' + ), + 'type': int, + 'default': 2048, + 'envvar': 'IDF_CONFSERVER_BUFFER_SIZE', + } + ], }, 'size': { 'callback': size_target, diff --git a/tools/idf_py_actions/tools.py b/tools/idf_py_actions/tools.py index 1b065ddc8f6a..834de0954903 100644 --- a/tools/idf_py_actions/tools.py +++ b/tools/idf_py_actions/tools.py @@ -1,4 +1,4 @@ -# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 import asyncio import importlib @@ -284,9 +284,20 @@ def fit_text_in_terminal(out: str) -> str: class RunTool: - def __init__(self, tool_name: str, args: List, cwd: str, env: Optional[Dict]=None, custom_error_handler: Optional[FunctionType]=None, - build_dir: Optional[str]=None, hints: bool=True, force_progression: bool=False, interactive: bool=False, convert_output: bool=False - ) -> None: + def __init__( + self, + tool_name: str, + args: list, + cwd: str, + env: Optional[Dict] = None, + custom_error_handler: Optional[FunctionType] = None, + build_dir: Optional[str] = None, + hints: bool = True, + force_progression: bool = False, + interactive: bool = False, + convert_output: bool = False, + buffer_size: Optional[int] = None, + ) -> None: self.tool_name = tool_name self.args = args self.cwd = cwd @@ -298,6 +309,7 @@ def __init__(self, tool_name: str, args: List, cwd: str, env: Optional[Dict]=Non self.force_progression = force_progression self.interactive = interactive self.convert_output = convert_output + self.buffer_size = buffer_size or 256 def __call__(self) -> None: def quote_arg(arg: str) -> str: @@ -348,8 +360,14 @@ async def run_command(self, cmd: List, env_copy: Dict) -> Tuple[Process, Optiona # Note: we explicitly pass in os.environ here, as we may have set IDF_PATH there during startup # limit was added for avoiding error in idf.py confserver try: - p = await asyncio.create_subprocess_exec(*cmd, env=env_copy, limit=1024 * 256, cwd=self.cwd, stdout=asyncio.subprocess.PIPE, - stderr=asyncio.subprocess.PIPE) + p = await asyncio.create_subprocess_exec( + *cmd, + env=env_copy, + limit=1024 * self.buffer_size, + cwd=self.cwd, + stdout=asyncio.subprocess.PIPE, + stderr=asyncio.subprocess.PIPE, + ) except NotImplementedError: message = f'ERROR: {sys.executable} doesn\'t support asyncio. The issue can be worked around by re-running idf.py with the "--no-hints" argument.' if sys.platform == 'win32': @@ -478,8 +496,15 @@ def run_tool(*args: Any, **kwargs: Any) -> None: return RunTool(*args, **kwargs)() -def run_target(target_name: str, args: 'PropertyDict', env: Optional[Dict]=None, - custom_error_handler: Optional[FunctionType]=None, force_progression: bool=False, interactive: bool=False) -> None: +def run_target( + target_name: str, + args: 'PropertyDict', + env: Optional[Dict] = None, + custom_error_handler: Optional[FunctionType] = None, + force_progression: bool = False, + interactive: bool = False, + buffer_size: Optional[int] = None, +) -> None: """Run target in build directory.""" if env is None: env = {} @@ -496,8 +521,17 @@ def run_target(target_name: str, args: 'PropertyDict', env: Optional[Dict]=None, if 'CLICOLOR_FORCE' not in env: env['CLICOLOR_FORCE'] = '1' - RunTool(generator_cmd[0], generator_cmd + [target_name], args.build_dir, env, custom_error_handler, hints=not args.no_hints, - force_progression=force_progression, interactive=interactive)() + RunTool( + generator_cmd[0], + generator_cmd + [target_name], + args.build_dir, + env, + custom_error_handler, + hints=not args.no_hints, + force_progression=force_progression, + interactive=interactive, + buffer_size=buffer_size, + )() def _strip_quotes(value: str, regexp: re.Pattern=re.compile(r"^\"(.*)\"$|^'(.*)'$|^(.*)$")) -> Optional[str]: diff --git a/tools/requirements/requirements.core.txt b/tools/requirements/requirements.core.txt index 9e12cd16e284..fb9ba1b82720 100644 --- a/tools/requirements/requirements.core.txt +++ b/tools/requirements/requirements.core.txt @@ -26,5 +26,9 @@ construct rich psutil +# ble's compressed log testing tool +tree_sitter +tree_sitter_c + # gdb extensions dependencies freertos_gdb diff --git a/tools/test_apps/build_system/.build-test-rules.yml b/tools/test_apps/build_system/.build-test-rules.yml index 1344b5636f4e..34dbd7995b33 100644 --- a/tools/test_apps/build_system/.build-test-rules.yml +++ b/tools/test_apps/build_system/.build-test-rules.yml @@ -18,4 +18,4 @@ tools/test_apps/build_system/embed_test: tools/test_apps/build_system/ld_non_contiguous_memory: disable: - - if: SOC_MEM_NON_CONTIGUOUS_SRAM != 1 + - if: SOC_MEM_NON_CONTIGUOUS_SRAM != 1 # TODO: IDF-13411, since P4 REV2, the SRAM is contiguous diff --git a/tools/test_apps/system/build_test/sdkconfig.ci.esp32p4_rev3 b/tools/test_apps/system/build_test/sdkconfig.ci.esp32p4_rev3 new file mode 100644 index 000000000000..2b6fa5463f4f --- /dev/null +++ b/tools/test_apps/system/build_test/sdkconfig.ci.esp32p4_rev3 @@ -0,0 +1,3 @@ +CONFIG_IDF_TARGET="esp32p4" +# To be replaced to P4 rev0/1 +CONFIG_ESP32P4_SELECTS_REV_LESS_V3=n diff --git a/tools/test_apps/system/g1_components/check_dependencies.py b/tools/test_apps/system/g1_components/check_dependencies.py index 3f0e8e7c1b24..08a7f310f254 100644 --- a/tools/test_apps/system/g1_components/check_dependencies.py +++ b/tools/test_apps/system/g1_components/check_dependencies.py @@ -26,8 +26,8 @@ def parse_dependencies(file_path: str) -> Tuple[Dict[str, List[str]], List[str]] parts = line.split(' -> ') if (len(parts) >= 2): - source = parts[0] - target = parts[1].split()[0] # Extracting the target component + source = parts[0].strip('"') + target = parts[1].split()[0].strip('"') # Extracting the target component logging.debug(f'Parsed dependency: {source} -> {target}') # Check that g1/g0 dependencies are either on the list of expected violations