diff --git a/components/bt/common/ble_log/Kconfig.in b/components/bt/common/ble_log/Kconfig.in
index dfbd47117831..f3a5e5348a72 100644
--- a/components/bt/common/ble_log/Kconfig.in
+++ b/components/bt/common/ble_log/Kconfig.in
@@ -5,6 +5,12 @@ config BLE_LOG_ENABLED
         Enable BLE Log Module
 
 if BLE_LOG_ENABLED
+    config BLE_LOG_TASK_STACK_SIZE
+        int "Stack size for BLE Log Task"
+        default 1024
+        help
+            Stack size for BLE Log Task
+
     config BLE_LOG_LBM_TRANS_SIZE
         int "Buffer size for each peripheral transport"
         default 512
diff --git a/components/bt/common/ble_log/ble_log_spi_out.c b/components/bt/common/ble_log/ble_log_spi_out.c
index 2a96fec6a3c0..79c0087226a8 100644
--- a/components/bt/common/ble_log/ble_log_spi_out.c
+++ b/components/bt/common/ble_log/ble_log_spi_out.c
@@ -247,9 +247,9 @@ extern uint32_t r_ble_lll_timer_current_tick_get(void);
 #elif defined(CONFIG_IDF_TARGET_ESP32C2)
 extern uint32_t r_os_cputime_get32(void);
 #define SPI_OUT_GET_LC_TIME r_os_cputime_get32()
-// #elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
-// extern uint32_t lld_read_clock_us(void);
-// #define SPI_OUT_GET_LC_TIME lld_read_clock_us()
+#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
+extern uint32_t lld_read_clock_us(void);
+#define SPI_OUT_GET_LC_TIME lld_read_clock_us()
 #else
 #define SPI_OUT_GET_LC_TIME esp_timer_get_time()
 #endif
diff --git a/components/bt/common/ble_log/src/internal_include/ble_log_rt.h b/components/bt/common/ble_log/src/internal_include/ble_log_rt.h
index f053049339fc..ae8b4b05a37a 100644
--- a/components/bt/common/ble_log/src/internal_include/ble_log_rt.h
+++ b/components/bt/common/ble_log/src/internal_include/ble_log_rt.h
@@ -21,7 +21,7 @@
 
 /* MACRO */
 #define BLE_LOG_TASK_PRIO                       (ESP_TASK_PRIO_MAX - 1)
-#define BLE_LOG_TASK_STACK_SIZE                 (1024)
+#define BLE_LOG_TASK_STACK_SIZE                 CONFIG_BLE_LOG_TASK_STACK_SIZE
 #define BLE_LOG_TASK_HOOK_TIMEOUT_MS            (1000)
 
 /* INTERFACE */
diff --git a/components/bt/controller/esp32c3/Kconfig.in b/components/bt/controller/esp32c3/Kconfig.in
index 0cd77b951b3b..5c9c74c0b9ef 100644
--- a/components/bt/controller/esp32c3/Kconfig.in
+++ b/components/bt/controller/esp32c3/Kconfig.in
@@ -614,15 +614,15 @@ menu "Controller debug log Options (Experimental)"
 
     config BT_CTRL_LE_LOG_MODE_EN
         depends on BT_CTRL_LE_LOG_EN
-        int "Enable log for specified BLE mode"
-        range 0 4095
-        default 4093
+        hex "Enable log for specified BLE mode"
+        range 0 0xFFFF
+        default 0xDB7F
 
     config BT_CTRL_LE_LOG_LEVEL
         depends on BT_CTRL_LE_LOG_EN
         int "The level of BLE log"
         range 0 5
-        default 2
+        default 1
 
     config BT_CTRL_LE_LOG_BUF1_SIZE
         depends on BT_CTRL_LE_LOG_EN
diff --git a/components/bt/controller/esp32c3/bt.c b/components/bt/controller/esp32c3/bt.c
index d975c0e2107e..da2810ff73e2 100644
--- a/components/bt/controller/esp32c3/bt.c
+++ b/components/bt/controller/esp32c3/bt.c
@@ -241,7 +241,12 @@ struct osi_funcs_t {
 };
 
 #if CONFIG_BT_CTRL_LE_LOG_EN
-typedef void (*interface_func_t) (uint32_t len, const uint8_t*addr, bool end);
+typedef void (*interface_func_t) (uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag);
+
+enum {
+    BLE_LOG_INTERFACE_FLAG_CONTINUE = 0,
+    BLE_LOG_INTERFACE_FLAG_END,
+};
 #endif // CONFIG_BT_CTRL_LE_LOG_EN
 
 /* External functions or values
@@ -311,11 +316,14 @@ extern void chanSel_stack_enableSetCsaVsCmd(bool en);
 
 /* BLE Log module */
 #if CONFIG_BT_CTRL_LE_LOG_EN
+extern int r_ble_log_init_simple(interface_func_t interface, void *handler);
+extern void r_ble_log_deinit_simple(void);
 extern int r_ble_log_init_async(interface_func_t bt_controller_log_interface, bool task_create, uint8_t buffers, uint32_t *bufs_size);
 extern int r_ble_log_deinit_async(void);
 extern void r_ble_log_async_select_dump_buffers(uint8_t buffers);
 extern void r_ble_log_async_output_dump_all(bool output);
 extern void esp_panic_handler_feed_wdts(void);
+extern int r_ble_log_ctrl_level_and_mod(uint8_t level, uint32_t mod_en);
 #endif // CONFIG_BT_CTRL_LE_LOG_EN
 
 extern void ble_dtm_funcs_reset(void);
@@ -400,12 +408,13 @@ static esp_err_t try_heap_caps_add_region(intptr_t start, intptr_t end);
 static void bt_controller_deinit_internal(void);
 
 #if CONFIG_BT_CTRL_LE_LOG_EN
-static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end);
+#if !CONFIG_BT_CTRL_LE_LOG_MODE_BLE_LOG_V2
 #if CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
 void esp_bt_read_ctrl_log_from_flash(bool output);
 static int esp_bt_controller_log_storage(uint32_t len, const uint8_t *addr, bool end);
 static void esp_bt_ctrl_log_partition_get_and_erase_first_block(void);
-#endif // #if CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
+#endif // CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
+#endif // !CONFIG_BT_CTRL_LE_LOG_MODE_BLE_LOG_V2
 #endif // CONFIG_BT_CTRL_LE_LOG_EN
 
 /* Local variable definition
@@ -539,18 +548,14 @@ static bool is_filled = false;
 #endif // CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
 
 #if CONFIG_BT_CTRL_LE_LOG_MODE_BLE_LOG_V2
-static IRAM_ATTR void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end)
-{
-    ble_log_write_hex_ll(len, addr, 0, NULL, 0);
-}
-
 void esp_ble_controller_log_dump_all(bool output)
 {
     ble_log_dump_to_console();
 }
 #else /* !CONFIG_BT_CTRL_LE_LOG_MODE_BLE_LOG_V2 */
-static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end)
+static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag)
 {
+    bool end = (flag & BIT(BLE_LOG_INTERFACE_FLAG_END));
     if (log_output_mode == LOG_STORAGE_TO_FLASH) {
 #if CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
         esp_bt_controller_log_storage(len, addr, end);
@@ -559,24 +564,19 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b
         portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
         portENTER_CRITICAL_SAFE(&spinlock);
         esp_panic_handler_feed_wdts();
-        for (int i = 0; i < len; i++) {
-            esp_rom_printf("%02x ", addr[i]);
-        }
 
-        if (end) {
-            esp_rom_printf("\n");
+        if (len && addr) {
+            for (int i = 0; i < len; i++) { esp_rom_printf("%02x ", addr[i]); }
+        }
+        if (len_append && addr_append) {
+            for (int i = 0; i < len_append; i++) { esp_rom_printf("%02x ", addr_append[i]); }
         }
+        if (end) { esp_rom_printf("\n"); }
+
         portEXIT_CRITICAL_SAFE(&spinlock);
     }
 }
 
-#if CONFIG_BT_CTRL_LE_LOG_SPI_OUT_EN
-static IRAM_ATTR void esp_bt_controller_spi_log_interface(uint32_t len, const uint8_t *addr, bool end)
-{
-    ble_log_spi_out_ll_write(len, addr, 0, NULL, 0);
-}
-#endif // CONFIG_BT_CTRL_LE_LOG_SPI_OUT_EN
-
 void esp_ble_controller_log_dump_all(bool output)
 {
     if (log_output_mode == LOG_STORAGE_TO_FLASH) {
@@ -613,16 +613,13 @@ esp_err_t esp_bt_controller_log_init(uint8_t log_output_mode)
     }
 
     esp_err_t ret = ESP_OK;
-    uint8_t buffers = 0;
 
-#if CONFIG_BT_CTRL_LE_LOG_EN
-    buffers |= ESP_BLE_LOG_BUF_CONTROLLER;
-#endif // CONFIG_BT_CTRL_LE_LOG_EN
-#if CONFIG_BT_CTRL_LE_HCI_LOG_EN
-    buffers |= ESP_BLE_LOG_BUF_HCI;
-#endif // CONFIG_BT_CTRL_LE_HCI_LOG_EN
+    ret = r_ble_log_init_simple(ble_log_write_hex_ll, NULL);
+    if (ret != ESP_OK) {
+        return ret;
+    }
 
-    ret = r_ble_log_init_async(esp_bt_controller_log_interface, true, buffers, (uint32_t *)log_bufs_size);
+    ret = r_ble_log_ctrl_level_and_mod(BLE_LOG_LEVEL, BLE_LOG_MODE_EN);
     if (ret == ESP_OK) {
         log_is_inited = true;
     }
@@ -665,7 +662,7 @@ esp_err_t esp_bt_controller_log_init(uint8_t log_output_mode)
         case LOG_SPI_OUT:
             task_create = true;
 #if CONFIG_BT_CTRL_LE_LOG_SPI_OUT_EN
-            bt_controller_log_interface = esp_bt_controller_spi_log_interface;
+            bt_controller_log_interface = ble_log_spi_out_ll_write;
 #endif // CONFIG_BT_CTRL_LE_LOG_SPI_OUT_EN
             break;
         default:
@@ -673,6 +670,11 @@ esp_err_t esp_bt_controller_log_init(uint8_t log_output_mode)
     }
 
     ret = r_ble_log_init_async(bt_controller_log_interface, task_create, buffers, (uint32_t *)log_bufs_size);
+    if (ret != ESP_OK) {
+        return ret;
+    }
+
+    ret = r_ble_log_ctrl_level_and_mod(BLE_LOG_LEVEL, BLE_LOG_MODE_EN);
     if (ret == ESP_OK) {
         log_is_inited = true;
     }
diff --git a/components/bt/controller/lib_esp32c3_family b/components/bt/controller/lib_esp32c3_family
index 42c965137ecc..099a7e1ab87d 160000
--- a/components/bt/controller/lib_esp32c3_family
+++ b/components/bt/controller/lib_esp32c3_family
@@ -1 +1 @@
-Subproject commit 42c965137ecc3c6cf3d38ecece7ce71ffc461353
+Subproject commit 099a7e1ab87dd977754fc4ad35678ab7ebf2f2a2
diff --git a/components/bt/include/esp32c3/include/esp_bt.h b/components/bt/include/esp32c3/include/esp_bt.h
index 7e2d96aaff5d..92bbf09831da 100644
--- a/components/bt/include/esp32c3/include/esp_bt.h
+++ b/components/bt/include/esp32c3/include/esp_bt.h
@@ -30,7 +30,7 @@ extern "C" {
 *
 * @note Please do not modify this value
 */
-#define ESP_BT_CTRL_CONFIG_VERSION      0x02505080
+#define ESP_BT_CTRL_CONFIG_VERSION      0x02509280
 
 /**
 * @brief Internal use only
@@ -376,8 +376,6 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status);
     .connect_en = BT_CTRL_BLE_MASTER,                                      \
     .scan_en = BT_CTRL_BLE_SCAN,                                           \
     .ble_aa_check = BLE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS_ENABLED,     \
-    .ble_log_mode_en = BLE_LOG_MODE_EN,                                    \
-    .ble_log_level = BLE_LOG_LEVEL,                                        \
     .adv_en = BT_CTRL_BLE_ADV,                                             \
 }
 
@@ -502,8 +500,6 @@ typedef struct {
     bool connect_en;                        /*!< True if the connection feature is enabled (default); false otherwise. Configurable in menuconfig.*/
     bool scan_en;                           /*!< True if the scan feature is enabled (default); false otherwise. Configurable in menuconfig.*/
     bool ble_aa_check;                      /*!< True if adds a verification step for the Access Address within the CONNECT_IND PDU; false otherwise. Configurable in menuconfig */
-    uint32_t ble_log_mode_en;               /*!< BLE log mode enable */
-    uint8_t ble_log_level;                  /*!< BLE log level */
     bool adv_en;                            /*!< True if the ADV feature is enabled (default); false otherwise. Configurable in menuconfig.*/
 } esp_bt_controller_config_t;
 
diff --git a/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c b/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c
index 6491fe440695..cd5d9d1ea2d3 100644
--- a/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c
+++ b/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c
@@ -52,6 +52,7 @@ static esp_err_t s_ctlr_csi_stop(esp_cam_ctlr_handle_t handle);
 static esp_err_t s_csi_ctlr_disable(esp_cam_ctlr_handle_t ctlr);
 static esp_err_t s_ctlr_csi_receive(esp_cam_ctlr_handle_t handle, esp_cam_ctlr_trans_t *trans, uint32_t timeout_ms);
 static void *s_csi_ctlr_alloc_buffer(esp_cam_ctlr_t *handle, size_t size, uint32_t buf_caps);
+static esp_err_t s_csi_ctlr_format_conversion(esp_cam_ctlr_t *handle, const cam_ctlr_format_conv_config_t *config);
 
 static esp_err_t s_csi_claim_controller(csi_controller_t *controller)
 {
@@ -223,6 +224,7 @@ esp_err_t esp_cam_new_csi_ctlr(const esp_cam_ctlr_csi_config_t *config, esp_cam_
     ctlr->base.get_internal_buffer = s_csi_ctlr_get_internal_buffer;
     ctlr->base.get_buffer_len = s_csi_ctlr_get_buffer_length;
     ctlr->base.alloc_buffer = s_csi_ctlr_alloc_buffer;
+    ctlr->base.format_conversion = s_csi_ctlr_format_conversion;
 
     *ret_handle = &(ctlr->base);
 
@@ -540,3 +542,10 @@ static void *s_csi_ctlr_alloc_buffer(esp_cam_ctlr_t *handle, size_t size, uint32
 
     return buffer;
 }
+
+static esp_err_t s_csi_ctlr_format_conversion(esp_cam_ctlr_t *handle, const cam_ctlr_format_conv_config_t *config)
+{
+    ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
+    // CSI controller doesn't support format conversion yet
+    return ESP_ERR_NOT_SUPPORTED;
+}
diff --git a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c
index cb1e8f87169b..b5eb54ee282c 100644
--- a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c
+++ b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c
@@ -766,6 +766,31 @@ static void *esp_cam_ctlr_dvp_cam_alloc_buffer(esp_cam_ctlr_t *handle, size_t si
     return buffer;
 }
 
+/**
+ * @brief Configure format conversion
+ *
+ * @param cam_handle Camera controller handle
+ * @param src_format Source format
+ * @param dst_format Destination format
+ * @return ESP_OK on success, ESP_FAIL on failure
+ */
+esp_err_t esp_cam_ctlr_dvp_format_conversion(esp_cam_ctlr_handle_t cam_handle,
+                                             const cam_ctlr_format_conv_config_t *config)
+{
+    if (cam_handle == NULL) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    esp_cam_ctlr_dvp_cam_t *ctlr = (esp_cam_ctlr_dvp_cam_t *)cam_handle;
+
+    ESP_LOGD(TAG, "Configure format conversion: %d -> %d", config->src_format, config->dst_format);
+
+    // Configure color format conversion
+    cam_hal_color_format_convert(&ctlr->hal, config);
+
+    return ESP_OK;
+}
+
 /**
  * @brief New ESP CAM DVP controller
  *
@@ -856,6 +881,7 @@ esp_err_t esp_cam_new_dvp_ctlr(const esp_cam_ctlr_dvp_config_t *config, esp_cam_
     ctlr->base.get_internal_buffer = esp_cam_ctlr_dvp_cam_get_internal_buffer;
     ctlr->base.get_buffer_len = esp_cam_ctlr_get_dvp_cam_frame_buffer_len;
     ctlr->base.alloc_buffer = esp_cam_ctlr_dvp_cam_alloc_buffer;
+    ctlr->base.format_conversion = esp_cam_ctlr_dvp_format_conversion;
 
     *ret_handle = &ctlr->base;
 
diff --git a/components/esp_driver_cam/esp_cam_ctlr.c b/components/esp_driver_cam/esp_cam_ctlr.c
index 43361addc9b1..eb9f78d329b2 100644
--- a/components/esp_driver_cam/esp_cam_ctlr.c
+++ b/components/esp_driver_cam/esp_cam_ctlr.c
@@ -99,3 +99,13 @@ void *esp_cam_ctlr_alloc_buffer(esp_cam_ctlr_handle_t handle, size_t size, uint3
 
     return handle->alloc_buffer(handle, size, buf_caps);
 }
+
+esp_err_t esp_cam_ctlr_format_conversion(esp_cam_ctlr_handle_t handle,
+                                         const cam_ctlr_format_conv_config_t *conv_cfg)
+{
+    ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
+    ESP_RETURN_ON_FALSE(conv_cfg, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null conv_cfg");
+    ESP_RETURN_ON_FALSE(handle->format_conversion, ESP_ERR_NOT_SUPPORTED, TAG, "format conversion function not supported");
+
+    return handle->format_conversion(handle, conv_cfg);
+}
diff --git a/components/esp_driver_cam/include/esp_cam_ctlr.h b/components/esp_driver_cam/include/esp_cam_ctlr.h
index ed01642ad6fb..0e0860c41214 100644
--- a/components/esp_driver_cam/include/esp_cam_ctlr.h
+++ b/components/esp_driver_cam/include/esp_cam_ctlr.h
@@ -11,6 +11,7 @@
 #include "esp_err.h"
 #include "esp_heap_caps.h"
 #include "esp_cam_ctlr_types.h"
+#include "hal/cam_ctlr_types.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -150,6 +151,20 @@ esp_err_t esp_cam_ctlr_get_frame_buffer_len(esp_cam_ctlr_handle_t handle, size_t
  */
 void *esp_cam_ctlr_alloc_buffer(esp_cam_ctlr_handle_t handle, size_t size, uint32_t buf_caps);
 
+/**
+ * @brief Configure format conversion
+ *
+ * @param[in] handle      ESP CAM controller handle
+ * @param[in] conv_cfg    Color conversion configuration, contains source and destination formats
+ *
+ * @return
+ *        - ESP_OK on success
+ *        - ESP_ERR_INVALID_ARG:   Invalid argument
+ *        - ESP_ERR_NOT_SUPPORTED: Format conversion not supported by this controller
+ */
+esp_err_t esp_cam_ctlr_format_conversion(esp_cam_ctlr_handle_t handle,
+                                         const cam_ctlr_format_conv_config_t *conv_cfg);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_driver_cam/interface/esp_cam_ctlr_interface.h b/components/esp_driver_cam/interface/esp_cam_ctlr_interface.h
index 893e48413d98..eac65df17858 100644
--- a/components/esp_driver_cam/interface/esp_cam_ctlr_interface.h
+++ b/components/esp_driver_cam/interface/esp_cam_ctlr_interface.h
@@ -8,6 +8,7 @@
 #include <stdbool.h>
 #include "esp_err.h"
 #include "esp_cam_ctlr_types.h"
+#include "hal/cam_ctlr_types.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -146,6 +147,19 @@ struct esp_cam_ctlr_t {
      */
     void *(*alloc_buffer)(esp_cam_ctlr_t *, size_t, uint32_t);
 
+    /**
+     * @brief Configure format conversion
+     *
+     * @param[in] esp_cam_ctlr_t *      ESP CAM controller handle
+     * @param[in] const cam_ctlr_format_conv_config_t * Color conversion configuration
+     *
+     * @return
+     *        - ESP_OK on success
+     *        - ESP_ERR_INVALID_ARG:   Invalid argument
+     *        - ESP_ERR_NOT_SUPPORTED: Format conversion not supported by this controller
+     */
+    esp_err_t (*format_conversion)(esp_cam_ctlr_t *, const cam_ctlr_format_conv_config_t *);
+
     void *user_data;  ///< User data
 };
 
diff --git a/components/esp_driver_cam/isp_dvp/src/esp_cam_ctlr_isp_dvp.c b/components/esp_driver_cam/isp_dvp/src/esp_cam_ctlr_isp_dvp.c
index ec20be674f77..ef607849d393 100644
--- a/components/esp_driver_cam/isp_dvp/src/esp_cam_ctlr_isp_dvp.c
+++ b/components/esp_driver_cam/isp_dvp/src/esp_cam_ctlr_isp_dvp.c
@@ -80,6 +80,7 @@ static esp_err_t s_isp_dvp_stop(esp_cam_ctlr_handle_t handle);
 static esp_err_t s_isp_dvp_receive(esp_cam_ctlr_handle_t handle, esp_cam_ctlr_trans_t *trans, uint32_t timeout_ms);
 static bool s_dvp_dma_trans_done_callback(dw_gdma_channel_handle_t chan, const dw_gdma_trans_done_event_data_t *event_data, void *user_data);
 static void *s_isp_dvp_alloc_buffer(esp_cam_ctlr_t *handle, size_t size, uint32_t buf_caps);
+static esp_err_t s_isp_dvp_format_conversion(esp_cam_ctlr_t *handle, const cam_ctlr_format_conv_config_t *config);
 
 esp_err_t esp_cam_new_isp_dvp_ctlr(isp_proc_handle_t isp_proc, const esp_cam_ctlr_isp_dvp_cfg_t *ctlr_config, esp_cam_ctlr_handle_t *ret_handle)
 {
@@ -191,6 +192,7 @@ esp_err_t esp_cam_new_isp_dvp_ctlr(isp_proc_handle_t isp_proc, const esp_cam_ctl
     cam_ctlr->get_internal_buffer = s_isp_dvp_get_frame_buffer;
     cam_ctlr->get_buffer_len = s_isp_dvp_get_frame_buffer_length;
     cam_ctlr->alloc_buffer = s_isp_dvp_alloc_buffer;
+    cam_ctlr->format_conversion = s_isp_dvp_format_conversion;
     *ret_handle = cam_ctlr;
 
     return ESP_OK;
@@ -589,3 +591,10 @@ static void *s_isp_dvp_alloc_buffer(esp_cam_ctlr_t *handle, size_t size, uint32_
 
     return buffer;
 }
+
+static esp_err_t s_isp_dvp_format_conversion(esp_cam_ctlr_t *handle, const cam_ctlr_format_conv_config_t *config)
+{
+    ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
+    // ISP DVP controller doesn't support format conversion yet
+    return ESP_ERR_NOT_SUPPORTED;
+}
diff --git a/components/esp_driver_i2s/i2s_common.c b/components/esp_driver_i2s/i2s_common.c
index c89cd245cb6e..4f6f720dd2b9 100644
--- a/components/esp_driver_i2s/i2s_common.c
+++ b/components/esp_driver_i2s/i2s_common.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -296,12 +296,6 @@ static inline bool i2s_take_available_channel(i2s_controller_t *i2s_obj, uint8_t
 {
     bool is_available = false;
 
-#if SOC_I2S_HW_VERSION_1
-    /* In ESP32 and ESP32-S2, tx channel and rx channel are not totally separated
-     * Take both two channels in case one channel can affect another
-     */
-    chan_search_mask = I2S_DIR_RX | I2S_DIR_TX;
-#endif
     portENTER_CRITICAL(&g_i2s.spinlock);
     if (!(chan_search_mask & i2s_obj->chan_occupancy)) {
         i2s_obj->chan_occupancy |= chan_search_mask;
@@ -886,12 +880,12 @@ void i2s_gpio_check_and_set(i2s_chan_handle_t handle, int gpio, uint32_t signal_
     if (gpio != (int)I2S_GPIO_UNUSED) {
         gpio_func_sel(gpio, PIN_FUNC_GPIO);
         if (is_input) {
-            /* Set direction, for some GPIOs, the input function are not enabled as default */
-            gpio_set_direction(gpio, GPIO_MODE_INPUT);
+            /* Enable the input, for some GPIOs, the input function are not enabled as default */
+            gpio_input_enable(gpio);
             esp_rom_gpio_connect_in_signal(gpio, signal_idx, is_invert);
         } else {
             i2s_output_gpio_reserve(handle, gpio);
-            gpio_set_direction(gpio, GPIO_MODE_OUTPUT);
+            /* output will be enabled in esp_rom_gpio_connect_out_signal */
             esp_rom_gpio_connect_out_signal(gpio, signal_idx, is_invert, 0);
         }
     }
@@ -902,7 +896,7 @@ void i2s_gpio_loopback_set(i2s_chan_handle_t handle, int gpio, uint32_t out_sig_
     if (gpio != (int)I2S_GPIO_UNUSED) {
         i2s_output_gpio_reserve(handle,  gpio);
         gpio_func_sel(gpio, PIN_FUNC_GPIO);
-        gpio_set_direction(gpio, GPIO_MODE_INPUT_OUTPUT);
+        gpio_input_enable(gpio);
         esp_rom_gpio_connect_out_signal(gpio, out_sig_idx, 0, 0);
         esp_rom_gpio_connect_in_signal(gpio, in_sig_idx, 0);
     }
@@ -1304,7 +1298,12 @@ esp_err_t i2s_channel_write(i2s_chan_handle_t handle, const void *src, size_t si
     ESP_RETURN_ON_FALSE(xSemaphoreTake(handle->binary, pdMS_TO_TICKS(timeout_ms)) == pdTRUE, ESP_ERR_INVALID_STATE, TAG, "The channel is not enabled");
     src_byte = (char *)src;
     while (size > 0 && handle->state == I2S_CHAN_STATE_RUNNING) {
-        if (handle->dma.rw_pos == handle->dma.buf_size || handle->dma.curr_ptr == NULL) {
+        /* Acquire the new DMA buffer while:
+         * 1. The current buffer is fully filled
+         * 2. The current buffer is not set
+         * 3. The queue is almost full, i.e., the curr_ptr is nearly to be invalid
+         */
+        if (handle->dma.rw_pos == handle->dma.buf_size || handle->dma.curr_ptr == NULL || uxQueueSpacesAvailable(handle->msg_queue) <= (handle->dma.desc_num > 2 ? 1 : 0)) {
             if (xQueueReceive(handle->msg_queue, &(handle->dma.curr_ptr), pdMS_TO_TICKS(timeout_ms)) == pdFALSE) {
                 ret = ESP_ERR_TIMEOUT;
                 break;
@@ -1349,7 +1348,12 @@ esp_err_t i2s_channel_read(i2s_chan_handle_t handle, void *dest, size_t size, si
     /* The binary semaphore can only be taken when the channel has been enabled and no other reading operation in progress */
     ESP_RETURN_ON_FALSE(xSemaphoreTake(handle->binary, pdMS_TO_TICKS(timeout_ms)) == pdTRUE, ESP_ERR_INVALID_STATE, TAG, "The channel is not enabled");
     while (size > 0 && handle->state == I2S_CHAN_STATE_RUNNING) {
-        if (handle->dma.rw_pos == handle->dma.buf_size || handle->dma.curr_ptr == NULL) {
+        /* Acquire the new DMA buffer while:
+         * 1. The current buffer is fully filled
+         * 2. The current buffer is not set
+         * 3. The queue is almost full, i.e., the curr_ptr is nearly to be invalid
+         */
+        if (handle->dma.rw_pos == handle->dma.buf_size || handle->dma.curr_ptr == NULL || uxQueueSpacesAvailable(handle->msg_queue) <= (handle->dma.desc_num > 2 ? 1 : 0)) {
             if (xQueueReceive(handle->msg_queue, &(handle->dma.curr_ptr), pdMS_TO_TICKS(timeout_ms)) == pdFALSE) {
                 ret = ESP_ERR_TIMEOUT;
                 break;
diff --git a/components/esp_driver_i2s/i2s_private.h b/components/esp_driver_i2s/i2s_private.h
index ba1319fe18b2..a65bd2440d69 100644
--- a/components/esp_driver_i2s/i2s_private.h
+++ b/components/esp_driver_i2s/i2s_private.h
@@ -161,6 +161,8 @@ struct i2s_channel_obj_t {
     void                    *mode_info;     /*!< Slot, clock and gpio information of each mode */
     bool                    is_etm_start;   /*!< Whether start by etm tasks */
     bool                    is_etm_stop;    /*!< Whether stop by etm tasks */
+    bool                    full_duplex_slave; /*!< whether the channel is forced to switch to slave role for full duplex */
+
 #if SOC_I2S_SUPPORTS_APLL
     bool                    apll_en;        /*!< Flag of whether APLL enabled */
 #endif
diff --git a/components/esp_driver_i2s/i2s_std.c b/components/esp_driver_i2s/i2s_std.c
index acc71e95c5cf..60b2f90ae5bf 100644
--- a/components/esp_driver_i2s/i2s_std.c
+++ b/components/esp_driver_i2s/i2s_std.c
@@ -33,9 +33,10 @@ static esp_err_t i2s_std_calculate_clock(i2s_chan_handle_t handle, const i2s_std
     uint32_t slot_bits = (slot_cfg->slot_bit_width == I2S_SLOT_BIT_WIDTH_AUTO) ||
                          ((int)slot_cfg->slot_bit_width < (int)slot_cfg->data_bit_width) ?
                          slot_cfg->data_bit_width : slot_cfg->slot_bit_width;
+    slot_cfg->slot_bit_width = slot_bits;
     /* Calculate multiple
      * Fmclk = bck_div*fbck = fsclk/(mclk_div+b/a) */
-    if (handle->role == I2S_ROLE_MASTER) {
+    if (handle->role == I2S_ROLE_MASTER || handle->full_duplex_slave) {
         clk_info->bclk = rate * handle->total_slot * slot_bits;
         clk_info->mclk = rate * clk_cfg->mclk_multiple;
         clk_info->bclk_div = clk_info->mclk / clk_info->bclk;
@@ -111,18 +112,13 @@ static esp_err_t i2s_std_set_slot(i2s_chan_handle_t handle, const i2s_std_slot_c
         ESP_RETURN_ON_ERROR(i2s_alloc_dma_desc(handle, buf_size),
                             TAG, "allocate memory for dma descriptor failed");
     }
-    bool is_slave = handle->role == I2S_ROLE_SLAVE;
     /* Share bck and ws signal in full-duplex mode */
     if (handle->controller->full_duplex) {
         i2s_ll_share_bck_ws(handle->controller->hal.dev, true);
-        /* Since bck and ws are shared, only tx or rx can be master
-           Force to set rx as slave to avoid conflict of clock signal */
-        if (handle->dir == I2S_DIR_RX) {
-            is_slave = true;
-        }
     } else {
         i2s_ll_share_bck_ws(handle->controller->hal.dev, false);
     }
+    bool is_slave = handle->role == I2S_ROLE_SLAVE;
 
     portENTER_CRITICAL(&g_i2s.spinlock);
     /* Configure the hardware to apply STD format */
@@ -167,43 +163,101 @@ static esp_err_t i2s_std_set_gpio(i2s_chan_handle_t handle, const i2s_std_gpio_c
     /* Set mclk pin */
     ESP_RETURN_ON_ERROR(i2s_check_set_mclk(handle, id, gpio_cfg->mclk, std_cfg->clk_cfg.clk_src, gpio_cfg->invert_flags.mclk_inv), TAG, "mclk config failed");
 
-    if (handle->role == I2S_ROLE_SLAVE) {
-        /* For "tx + slave" mode, select TX signal index for ws and bck */
-        if (handle->dir == I2S_DIR_TX && !handle->controller->full_duplex) {
 #if SOC_I2S_HW_VERSION_2
+    /* Bind the MCLK signal to the TX or RX clock source */
+    if (!handle->controller->full_duplex) {
+        if (handle->dir == I2S_DIR_TX) {
             I2S_CLOCK_SRC_ATOMIC() {
                 i2s_ll_mclk_bind_to_tx_clk(handle->controller->hal.dev);
             }
-#endif
-            i2s_gpio_check_and_set(handle, gpio_cfg->ws, i2s_periph_signal[id].s_tx_ws_sig, true, gpio_cfg->invert_flags.ws_inv);
-            i2s_gpio_check_and_set(handle, gpio_cfg->bclk, i2s_periph_signal[id].s_tx_bck_sig, true, gpio_cfg->invert_flags.bclk_inv);
-            /* For "tx + rx + slave" or "rx + slave" mode, select RX signal index for ws and bck */
         } else {
-            i2s_gpio_check_and_set(handle, gpio_cfg->ws, i2s_periph_signal[id].s_rx_ws_sig, true, gpio_cfg->invert_flags.ws_inv);
-            i2s_gpio_check_and_set(handle, gpio_cfg->bclk, i2s_periph_signal[id].s_rx_bck_sig, true, gpio_cfg->invert_flags.bclk_inv);
+            I2S_CLOCK_SRC_ATOMIC() {
+                i2s_ll_mclk_bind_to_rx_clk(handle->controller->hal.dev);
+            }
         }
-    } else {
-        /* For "rx + master" mode, select RX signal index for ws and bck */
-        if (handle->dir == I2S_DIR_RX && !handle->controller->full_duplex) {
-#if SOC_I2S_HW_VERSION_2
+    } else if (handle->role == I2S_ROLE_MASTER) {
+        if (handle->dir == I2S_DIR_TX) {
+            I2S_CLOCK_SRC_ATOMIC() {
+                i2s_ll_mclk_bind_to_tx_clk(handle->controller->hal.dev);
+            }
+        } else {
             I2S_CLOCK_SRC_ATOMIC() {
                 i2s_ll_mclk_bind_to_rx_clk(handle->controller->hal.dev);
             }
+        }
+    }
 #endif
-            i2s_gpio_check_and_set(handle, gpio_cfg->ws, i2s_periph_signal[id].m_rx_ws_sig, false, gpio_cfg->invert_flags.ws_inv);
-            i2s_gpio_check_and_set(handle, gpio_cfg->bclk, i2s_periph_signal[id].m_rx_bck_sig, false, gpio_cfg->invert_flags.bclk_inv);
-            /* For "tx + rx + master" or "tx + master" mode, select TX signal index for ws and bck */
+
+    uint32_t ws_sig = 0;
+    uint32_t bck_sig = 0;
+    bool is_input = handle->role == I2S_ROLE_SLAVE;
+    if (handle->role == I2S_ROLE_SLAVE) {
+        // Assign slave signals
+        if (handle->dir == I2S_DIR_TX) {
+            ws_sig = i2s_periph_signal[id].s_tx_ws_sig;
+            bck_sig = i2s_periph_signal[id].s_tx_bck_sig;
+        } else {
+            ws_sig = i2s_periph_signal[id].s_rx_ws_sig;
+            bck_sig = i2s_periph_signal[id].s_rx_bck_sig;
+        }
+    } else {
+        // Assign master signals
+        if (handle->dir == I2S_DIR_TX) {
+            ws_sig = i2s_periph_signal[id].m_tx_ws_sig;
+            bck_sig = i2s_periph_signal[id].m_tx_bck_sig;
         } else {
-            i2s_gpio_check_and_set(handle, gpio_cfg->ws, i2s_periph_signal[id].m_tx_ws_sig, false, gpio_cfg->invert_flags.ws_inv);
-            i2s_gpio_check_and_set(handle, gpio_cfg->bclk, i2s_periph_signal[id].m_tx_bck_sig, false, gpio_cfg->invert_flags.bclk_inv);
+            ws_sig = i2s_periph_signal[id].m_rx_ws_sig;
+            bck_sig = i2s_periph_signal[id].m_rx_bck_sig;
         }
     }
+    i2s_gpio_check_and_set(handle, gpio_cfg->ws, ws_sig, is_input, gpio_cfg->invert_flags.ws_inv);
+    i2s_gpio_check_and_set(handle, gpio_cfg->bclk, bck_sig, is_input, gpio_cfg->invert_flags.bclk_inv);
+
     /* Update the mode info: gpio configuration */
     memcpy(&(std_cfg->gpio_cfg), gpio_cfg, sizeof(i2s_std_gpio_config_t));
 
     return ESP_OK;
 }
 
+static esp_err_t s_i2s_channel_try_to_constitude_std_duplex(i2s_chan_handle_t handle, const i2s_std_config_t *std_cfg)
+{
+    /* Get another direction handle */
+    i2s_chan_handle_t another_handle = handle->dir == I2S_DIR_RX ? handle->controller->tx_chan : handle->controller->rx_chan;
+    /* Condition: 1. Another direction channel is registered
+     *            2. Not a full-duplex channel yet
+     *            3. Another channel is initialized, try to compare the configurations */
+    if (another_handle && another_handle->state >= I2S_CHAN_STATE_READY) {
+        /* Judge if the two channels can constitute full-duplex */
+        if (!handle->controller->full_duplex) {
+            i2s_std_config_t curr_cfg = *std_cfg;
+            /* Override the slot bit width to the actual slot bit width */
+            curr_cfg.slot_cfg.slot_bit_width = (int)curr_cfg.slot_cfg.slot_bit_width < (int)curr_cfg.slot_cfg.data_bit_width ?
+                                               curr_cfg.slot_cfg.data_bit_width : curr_cfg.slot_cfg.slot_bit_width;
+            /* Compare the hardware configurations of the two channels, constitute the full-duplex if they are the same */
+            if (memcmp(another_handle->mode_info, &curr_cfg, sizeof(i2s_std_config_t)) == 0) {
+                handle->controller->full_duplex = true;
+                ESP_LOGD(TAG, "Constitude full-duplex on port %d", handle->controller->id);
+            }
+#if SOC_I2S_HW_VERSION_1
+            else {
+                ESP_LOGE(TAG, "Can't set different channel configurations on a same port");
+                return ESP_ERR_INVALID_ARG;
+            }
+#endif
+        }
+        /* Switch to the slave role if needed */
+        if (handle->controller->full_duplex &&
+                handle->role == I2S_ROLE_MASTER &&
+                another_handle->role == I2S_ROLE_MASTER) {
+            /* The later initialized channel must be slave for full duplex */
+            handle->role = I2S_ROLE_SLAVE;
+            handle->full_duplex_slave = true;
+        }
+    }
+
+    return ESP_OK;
+}
+
 esp_err_t i2s_channel_init_std_mode(i2s_chan_handle_t handle, const i2s_std_config_t *std_cfg)
 {
 #if CONFIG_I2S_ENABLE_DEBUG_LOG
@@ -221,6 +275,11 @@ esp_err_t i2s_channel_init_std_mode(i2s_chan_handle_t handle, const i2s_std_conf
     handle->mode_info = calloc(1, sizeof(i2s_std_config_t));
     ESP_GOTO_ON_FALSE(handle->mode_info, ESP_ERR_NO_MEM, err, TAG, "no memory for storing the configurations");
     ESP_GOTO_ON_FALSE(handle->state == I2S_CHAN_STATE_REGISTER, ESP_ERR_INVALID_STATE, err, TAG, "the channel has initialized already");
+    /* Try to constitute full-duplex mode if the STD configuration is totally same as another channel */
+    ret = s_i2s_channel_try_to_constitude_std_duplex(handle, std_cfg);
+#if SOC_I2S_HW_VERSION_1
+    ESP_GOTO_ON_ERROR(ret, err, TAG, "Failed to constitute full-duplex mode");
+#endif
     /* i2s_set_std_slot should be called before i2s_set_std_clock while initializing, because clock is relay on the slot */
     ESP_GOTO_ON_ERROR(i2s_std_set_slot(handle, &std_cfg->slot_cfg), err, TAG, "initialize channel failed while setting slot");
 #if SOC_I2S_SUPPORTS_APLL
diff --git a/components/esp_driver_i2s/i2s_tdm.c b/components/esp_driver_i2s/i2s_tdm.c
index 84dc30df746d..d7d7fd351038 100644
--- a/components/esp_driver_i2s/i2s_tdm.c
+++ b/components/esp_driver_i2s/i2s_tdm.c
@@ -34,9 +34,10 @@ static esp_err_t i2s_tdm_calculate_clock(i2s_chan_handle_t handle, const i2s_tdm
     uint32_t slot_bits = (slot_cfg->slot_bit_width == I2S_SLOT_BIT_WIDTH_AUTO) ||
                          ((int)slot_cfg->slot_bit_width < (int)slot_cfg->data_bit_width) ?
                          slot_cfg->data_bit_width : slot_cfg->slot_bit_width;
+    slot_cfg->slot_bit_width = slot_bits;
     /* Calculate multiple
      * Fmclk = bck_div*fbck = fsclk/(mclk_div+b/a) */
-    if (handle->role == I2S_ROLE_MASTER) {
+    if (handle->role == I2S_ROLE_MASTER || handle->full_duplex_slave) {
         clk_info->bclk = rate * handle->total_slot * slot_bits;
         clk_info->mclk = rate * clk_cfg->mclk_multiple;
         clk_info->bclk_div = clk_info->mclk / clk_info->bclk;
@@ -119,18 +120,13 @@ static esp_err_t i2s_tdm_set_slot(i2s_chan_handle_t handle, const i2s_tdm_slot_c
         ESP_RETURN_ON_ERROR(i2s_alloc_dma_desc(handle, buf_size),
                             TAG, "allocate memory for dma descriptor failed");
     }
-    bool is_slave = handle->role == I2S_ROLE_SLAVE;
     /* Share bck and ws signal in full-duplex mode */
     if (handle->controller->full_duplex) {
         i2s_ll_share_bck_ws(handle->controller->hal.dev, true);
-        /* Since bck and ws are shared, only tx or rx can be master
-           Force to set rx as slave to avoid conflict of clock signal */
-        if (handle->dir == I2S_DIR_RX) {
-            is_slave = true;
-        }
     } else {
         i2s_ll_share_bck_ws(handle->controller->hal.dev, false);
     }
+    bool is_slave = handle->role == I2S_ROLE_SLAVE;
 
     portENTER_CRITICAL(&g_i2s.spinlock);
     /* Configure the hardware to apply TDM format */
@@ -176,43 +172,92 @@ static esp_err_t i2s_tdm_set_gpio(i2s_chan_handle_t handle, const i2s_tdm_gpio_c
     /* Set mclk pin */
     ESP_RETURN_ON_ERROR(i2s_check_set_mclk(handle, id, gpio_cfg->mclk, tdm_cfg->clk_cfg.clk_src, gpio_cfg->invert_flags.mclk_inv), TAG, "mclk config failed");
 
-    if (handle->role == I2S_ROLE_SLAVE) {
-        /* For "tx + slave" mode, select TX signal index for ws and bck */
-        if (handle->dir == I2S_DIR_TX && !handle->controller->full_duplex) {
 #if SOC_I2S_HW_VERSION_2
+    /* Bind the MCLK signal to the TX or RX clock source */
+    if (!handle->controller->full_duplex) {
+        if (handle->dir == I2S_DIR_TX) {
             I2S_CLOCK_SRC_ATOMIC() {
                 i2s_ll_mclk_bind_to_tx_clk(handle->controller->hal.dev);
             }
-#endif
-            i2s_gpio_check_and_set(handle, gpio_cfg->ws, i2s_periph_signal[id].s_tx_ws_sig, true, gpio_cfg->invert_flags.ws_inv);
-            i2s_gpio_check_and_set(handle, gpio_cfg->bclk, i2s_periph_signal[id].s_tx_bck_sig, true, gpio_cfg->invert_flags.bclk_inv);
-            /* For "tx + rx + slave" or "rx + slave" mode, select RX signal index for ws and bck */
         } else {
-            i2s_gpio_check_and_set(handle, gpio_cfg->ws, i2s_periph_signal[id].s_rx_ws_sig, true, gpio_cfg->invert_flags.ws_inv);
-            i2s_gpio_check_and_set(handle, gpio_cfg->bclk, i2s_periph_signal[id].s_rx_bck_sig, true, gpio_cfg->invert_flags.bclk_inv);
+            I2S_CLOCK_SRC_ATOMIC() {
+                i2s_ll_mclk_bind_to_rx_clk(handle->controller->hal.dev);
+            }
         }
-    } else {
-        /* For "rx + master" mode, select RX signal index for ws and bck */
-        if (handle->dir == I2S_DIR_RX && !handle->controller->full_duplex) {
-#if SOC_I2S_HW_VERSION_2
+    } else if (handle->role == I2S_ROLE_MASTER) {
+        if (handle->dir == I2S_DIR_TX) {
+            I2S_CLOCK_SRC_ATOMIC() {
+                i2s_ll_mclk_bind_to_tx_clk(handle->controller->hal.dev);
+            }
+        } else {
             I2S_CLOCK_SRC_ATOMIC() {
                 i2s_ll_mclk_bind_to_rx_clk(handle->controller->hal.dev);
             }
+        }
+    }
 #endif
-            i2s_gpio_check_and_set(handle, gpio_cfg->ws, i2s_periph_signal[id].m_rx_ws_sig, false, gpio_cfg->invert_flags.ws_inv);
-            i2s_gpio_check_and_set(handle, gpio_cfg->bclk, i2s_periph_signal[id].m_rx_bck_sig, false, gpio_cfg->invert_flags.bclk_inv);
-            /* For "tx + rx + master" or "tx + master" mode, select TX signal index for ws and bck */
+
+    uint32_t ws_sig = 0;
+    uint32_t bck_sig = 0;
+    bool is_input = handle->role == I2S_ROLE_SLAVE;
+    if (handle->role == I2S_ROLE_SLAVE) {
+        // Assign slave signals
+        if (handle->dir == I2S_DIR_TX) {
+            ws_sig = i2s_periph_signal[id].s_tx_ws_sig;
+            bck_sig = i2s_periph_signal[id].s_tx_bck_sig;
+        } else {
+            ws_sig = i2s_periph_signal[id].s_rx_ws_sig;
+            bck_sig = i2s_periph_signal[id].s_rx_bck_sig;
+        }
+    } else {
+        // Assign master signals
+        if (handle->dir == I2S_DIR_TX) {
+            ws_sig = i2s_periph_signal[id].m_tx_ws_sig;
+            bck_sig = i2s_periph_signal[id].m_tx_bck_sig;
         } else {
-            i2s_gpio_check_and_set(handle, gpio_cfg->ws, i2s_periph_signal[id].m_tx_ws_sig, false, gpio_cfg->invert_flags.ws_inv);
-            i2s_gpio_check_and_set(handle, gpio_cfg->bclk, i2s_periph_signal[id].m_tx_bck_sig, false, gpio_cfg->invert_flags.bclk_inv);
+            ws_sig = i2s_periph_signal[id].m_rx_ws_sig;
+            bck_sig = i2s_periph_signal[id].m_rx_bck_sig;
         }
     }
+    i2s_gpio_check_and_set(handle, gpio_cfg->ws, ws_sig, is_input, gpio_cfg->invert_flags.ws_inv);
+    i2s_gpio_check_and_set(handle, gpio_cfg->bclk, bck_sig, is_input, gpio_cfg->invert_flags.bclk_inv);
+
     /* Update the mode info: gpio configuration */
     memcpy(&(tdm_cfg->gpio_cfg), gpio_cfg, sizeof(i2s_tdm_gpio_config_t));
 
     return ESP_OK;
 }
 
+static void s_i2s_channel_try_to_constitude_tdm_duplex(i2s_chan_handle_t handle, const i2s_tdm_config_t *tdm_cfg)
+{
+    /* Get another direction handle */
+    i2s_chan_handle_t another_handle = handle->dir == I2S_DIR_RX ? handle->controller->tx_chan : handle->controller->rx_chan;
+    /* Condition: 1. Another direction channel is registered
+     *            2. Not a full-duplex channel yet
+     *            3. Another channel is initialized, try to compare the configurations */
+    if (another_handle && another_handle->state >= I2S_CHAN_STATE_READY) {
+        if (!handle->controller->full_duplex) {
+            i2s_tdm_config_t curr_cfg = *tdm_cfg;
+            /* Override the slot bit width to the actual slot bit width */
+            curr_cfg.slot_cfg.slot_bit_width = (int)curr_cfg.slot_cfg.slot_bit_width < (int)curr_cfg.slot_cfg.data_bit_width ?
+                                               curr_cfg.slot_cfg.data_bit_width : curr_cfg.slot_cfg.slot_bit_width;
+            /* Compare the hardware configurations of the two channels, constitute the full-duplex if they are the same */
+            if (memcmp(another_handle->mode_info, &curr_cfg, sizeof(i2s_tdm_config_t)) == 0) {
+                handle->controller->full_duplex = true;
+                ESP_LOGD(TAG, "Constitude full-duplex on port %d", handle->controller->id);
+            }
+        }
+        /* Switch to the slave role if needed */
+        if (handle->controller->full_duplex &&
+                handle->role == I2S_ROLE_MASTER &&
+                another_handle->role == I2S_ROLE_MASTER) {
+            /* The later initialized channel must be slave for full duplex */
+            handle->role = I2S_ROLE_SLAVE;
+            handle->full_duplex_slave = true;
+        }
+    }
+}
+
 esp_err_t i2s_channel_init_tdm_mode(i2s_chan_handle_t handle, const i2s_tdm_config_t *tdm_cfg)
 {
 #if CONFIG_I2S_ENABLE_DEBUG_LOG
@@ -230,6 +275,8 @@ esp_err_t i2s_channel_init_tdm_mode(i2s_chan_handle_t handle, const i2s_tdm_conf
     }
     handle->mode_info = calloc(1, sizeof(i2s_tdm_config_t));
     ESP_GOTO_ON_FALSE(handle->mode_info, ESP_ERR_NO_MEM, err, TAG, "no memory for storing the configurations");
+    /* Try to constitute full-duplex mode if the TDM configuration is totally same as another channel */
+    s_i2s_channel_try_to_constitude_tdm_duplex(handle, tdm_cfg);
     /* i2s_set_tdm_slot should be called before i2s_set_tdm_clock while initializing, because clock is relay on the slot */
     ESP_GOTO_ON_ERROR(i2s_tdm_set_slot(handle, &tdm_cfg->slot_cfg), err, TAG, "initialize channel failed while setting slot");
 #if SOC_I2S_SUPPORTS_APLL
diff --git a/components/esp_driver_i2s/include/driver/i2s_std.h b/components/esp_driver_i2s/include/driver/i2s_std.h
index 038ff2825a10..b039c9ce5719 100644
--- a/components/esp_driver_i2s/include/driver/i2s_std.h
+++ b/components/esp_driver_i2s/include/driver/i2s_std.h
@@ -296,6 +296,8 @@ typedef struct {
  * @brief Initialize I2S channel to standard mode
  * @note  Only allowed to be called when the channel state is REGISTERED, (i.e., channel has been allocated, but not initialized)
  *        and the state will be updated to READY if initialization success, otherwise the state will return to REGISTERED.
+ * @note  When initialize the STD mode with a same configuration as another channel on a same port,
+ *        these two channels can constitude as full-duplex mode automatically
  *
  * @param[in]   handle      I2S channel handler
  * @param[in]   std_cfg     Configurations for standard mode, including clock, slot and GPIO
diff --git a/components/esp_driver_i2s/include/driver/i2s_tdm.h b/components/esp_driver_i2s/include/driver/i2s_tdm.h
index ae07a244756d..b8db9cc138fc 100644
--- a/components/esp_driver_i2s/include/driver/i2s_tdm.h
+++ b/components/esp_driver_i2s/include/driver/i2s_tdm.h
@@ -196,6 +196,8 @@ typedef struct {
  * @brief Initialize I2S channel to TDM mode
  * @note  Only allowed to be called when the channel state is REGISTERED, (i.e., channel has been allocated, but not initialized)
  *        and the state will be updated to READY if initialization success, otherwise the state will return to REGISTERED.
+ * @note  When initialize the TDM mode with a same configuration as another channel on a same port,
+ *        these two channels can constitude as full-duplex mode automatically
  *
  * @param[in]   handle      I2S channel handler
  * @param[in]   tdm_cfg     Configurations for TDM mode, including clock, slot and GPIO
diff --git a/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c b/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c
index 323db87653a6..2a2ba431be5b 100644
--- a/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c
+++ b/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c
@@ -192,6 +192,38 @@ TEST_CASE("I2S_basic_channel_allocation_reconfig_deleting_test", "[i2s]")
     TEST_ESP_OK(i2s_del_channel(tx_handle));
     TEST_ESP_OK(i2s_del_channel(rx_handle));
 
+    /* Lazy initialize std duplex test */
+    chan_cfg.id = I2S_NUM_0;    // Specify port id to I2S port 0
+    TEST_ESP_OK(i2s_new_channel(&chan_cfg, &tx_handle, NULL));
+    TEST_ESP_OK(i2s_new_channel(&chan_cfg, NULL, &rx_handle));
+    TEST_ESP_OK(i2s_channel_get_info(tx_handle, &chan_info));
+    TEST_ASSERT(chan_info.pair_chan == NULL);
+    TEST_ESP_OK(i2s_channel_init_std_mode(tx_handle, &std_cfg));
+    TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg));
+    TEST_ESP_OK(i2s_channel_get_info(tx_handle, &chan_info));
+    TEST_ASSERT(chan_info.pair_chan == rx_handle);
+    TEST_ESP_OK(i2s_del_channel(tx_handle));
+    TEST_ESP_OK(i2s_del_channel(rx_handle));
+
+#if SOC_I2S_SUPPORTS_TDM
+    /* Lazy initialize tdm duplex test */
+    TEST_ESP_OK(i2s_new_channel(&chan_cfg, NULL, &rx_handle));
+    TEST_ESP_OK(i2s_new_channel(&chan_cfg, &tx_handle, NULL));
+    TEST_ESP_OK(i2s_channel_get_info(tx_handle, &chan_info));
+    TEST_ASSERT(chan_info.pair_chan == NULL);
+    i2s_tdm_config_t tdm_cfg = {
+        .clk_cfg = I2S_TDM_CLK_DEFAULT_CONFIG(SAMPLE_RATE),
+        .slot_cfg = I2S_TDM_PHILIPS_SLOT_DEFAULT_CONFIG(SAMPLE_BITS, I2S_SLOT_MODE_STEREO, 0x0F),
+        .gpio_cfg = I2S_TEST_MASTER_DEFAULT_PIN,
+    };
+    TEST_ESP_OK(i2s_channel_init_tdm_mode(tx_handle, &tdm_cfg));
+    TEST_ESP_OK(i2s_channel_init_tdm_mode(rx_handle, &tdm_cfg));
+    TEST_ESP_OK(i2s_channel_get_info(tx_handle, &chan_info));
+    TEST_ASSERT(chan_info.pair_chan == rx_handle);
+    TEST_ESP_OK(i2s_del_channel(tx_handle));
+    TEST_ESP_OK(i2s_del_channel(rx_handle));
+#endif
+
     /* Repeat to check if a same port can be allocated again */
     TEST_ESP_OK(i2s_new_channel(&chan_cfg, NULL, &rx_handle));
     TEST_ESP_OK(i2s_del_channel(rx_handle));
@@ -207,6 +239,24 @@ TEST_CASE("I2S_basic_channel_allocation_reconfig_deleting_test", "[i2s]")
 
 static volatile bool task_run_flag;
 
+#define TEST_I2S_DATA 0x78
+
+static void i2s_read_check_task(void *args)
+{
+    i2s_chan_handle_t rx_handle = (i2s_chan_handle_t)args;
+    uint8_t *recv_buf = (uint8_t *)calloc(1, 2000);
+    TEST_ASSERT(recv_buf);
+    size_t recv_size = 0;
+
+    while (task_run_flag) {
+        TEST_ASSERT_EQUAL(i2s_channel_read(rx_handle, recv_buf, 2000, &recv_size, 300), ESP_OK);
+        TEST_ASSERT_EQUAL(recv_buf[0], TEST_I2S_DATA);
+    }
+
+    free(recv_buf);
+    vTaskDelete(NULL);
+}
+
 static void i2s_read_task(void *args)
 {
     i2s_chan_handle_t rx_handle = (i2s_chan_handle_t)args;
@@ -232,6 +282,7 @@ static void i2s_write_task(void *args)
     i2s_chan_handle_t tx_handle = (i2s_chan_handle_t)args;
     uint8_t *send_buf = (uint8_t *)calloc(1, 2000);
     TEST_ASSERT(send_buf);
+    memset(send_buf, TEST_I2S_DATA, 2000);
     size_t send_size = 0;
     esp_err_t ret = ESP_OK;
     uint32_t cnt = 1;
@@ -359,6 +410,65 @@ TEST_CASE("I2S_thread_concurrent_safety_test", "[i2s]")
     TEST_ESP_OK(i2s_del_channel(rx_handle));
 }
 
+TEST_CASE("I2S_lazy_duplex_test", "[i2s]")
+{
+    i2s_chan_handle_t tx_handle;
+    i2s_chan_handle_t rx_handle;
+    i2s_chan_config_t chan_cfg = I2S_CHANNEL_DEFAULT_CONFIG(I2S_NUM_0, I2S_ROLE_MASTER);
+    i2s_std_config_t std_cfg = {
+        .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(SAMPLE_RATE),
+        .slot_cfg = I2S_STD_MSB_SLOT_DEFAULT_CONFIG(SAMPLE_BITS, I2S_SLOT_MODE_STEREO),
+        .gpio_cfg = {
+            .mclk = MASTER_MCK_IO,
+            .bclk = MASTER_BCK_IO,
+            .ws = MASTER_WS_IO,
+            .dout = DATA_OUT_IO,
+            .din = DATA_OUT_IO,
+            .invert_flags = {
+                .mclk_inv = false,
+                .bclk_inv = false,
+                .ws_inv = false,
+            },
+        },
+    };
+    TEST_ESP_OK(i2s_new_channel(&chan_cfg, &tx_handle, NULL));
+    TEST_ESP_OK(i2s_channel_init_std_mode(tx_handle, &std_cfg));
+    TEST_ESP_OK(i2s_channel_enable(tx_handle));
+    printf("Enabled TX channel\n");
+
+    TEST_ESP_OK(i2s_new_channel(&chan_cfg, NULL, &rx_handle));
+    TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg));
+    /* Enable the channels before creating reading/writing task*/
+    TEST_ESP_OK(i2s_channel_enable(rx_handle));
+    printf("Enabled RX channel\n");
+
+    task_run_flag = true;
+    /* writing task to keep writing */
+    xTaskCreate(i2s_write_task, "i2s_write_task", 4096, tx_handle, 5, NULL);
+    printf("TX started\n");
+    vTaskDelay(pdMS_TO_TICKS(1000));
+    /* reading task to keep reading */
+    xTaskCreate(i2s_read_check_task, "i2s_read_check_task", 4096, rx_handle, 5, NULL);
+    printf("RX started\n");
+
+    /* Wait 3 seconds to see if any failures occur */
+    vTaskDelay(pdMS_TO_TICKS(1000));
+    printf("Finished\n");
+
+    /* Stop those three tasks */
+    task_run_flag = false;
+
+    /* Wait for the three thread deleted */
+    vTaskDelay(pdMS_TO_TICKS(1000));
+
+    /* Disable the channels, they will keep waiting until the current reading / writing finished */
+    TEST_ESP_OK(i2s_channel_disable(tx_handle));
+    TEST_ESP_OK(i2s_channel_disable(rx_handle));
+    /* Delete the channels */
+    TEST_ESP_OK(i2s_del_channel(tx_handle));
+    TEST_ESP_OK(i2s_del_channel(rx_handle));
+}
+
 static bool whether_contains_exapected_data(uint16_t *src, uint32_t src_len, uint32_t src_step, uint32_t start_val, uint32_t val_step)
 {
     uint32_t val = start_val;
diff --git a/components/esp_driver_spi/src/gpspi/spi_common.c b/components/esp_driver_spi/src/gpspi/spi_common.c
index cf1bb1e2841d..4319aac029be 100644
--- a/components/esp_driver_spi/src/gpspi/spi_common.c
+++ b/components/esp_driver_spi/src/gpspi/spi_common.c
@@ -588,7 +588,8 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
     }
     //set flags for DUAL mode according to output-capability of MOSI and MISO pins.
     if ((bus_config->mosi_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->mosi_io_num)) &&
-            (bus_config->miso_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->miso_io_num))) {
+            (bus_config->miso_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->miso_io_num)) &&
+            (bus_config->miso_io_num != bus_config->mosi_io_num)) {
         temp_flag |= SPICOMMON_BUSFLAG_DUAL;
     }
 
diff --git a/components/esp_driver_spi/src/gpspi/spi_master.c b/components/esp_driver_spi/src/gpspi/spi_master.c
index 5c4b38852c5a..44d09edf9354 100644
--- a/components/esp_driver_spi/src/gpspi/spi_master.c
+++ b/components/esp_driver_spi/src/gpspi/spi_master.c
@@ -632,9 +632,7 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle)
 
 esp_err_t spi_device_get_actual_freq(spi_device_handle_t handle, int* freq_khz)
 {
-    if ((spi_device_t *)handle == NULL || freq_khz == NULL) {
-        return ESP_ERR_INVALID_ARG;
-    }
+    SPI_CHECK(handle && freq_khz, "invalid arg", ESP_ERR_INVALID_ARG);
 
     *freq_khz = handle->hal_dev.timing_conf.real_freq / 1000;
     return ESP_OK;
diff --git a/components/esp_driver_spi/src/gpspi/spi_slave.c b/components/esp_driver_spi/src/gpspi/spi_slave.c
index 7b6a26df20b6..268f17f40842 100644
--- a/components/esp_driver_spi/src/gpspi/spi_slave.c
+++ b/components/esp_driver_spi/src/gpspi/spi_slave.c
@@ -100,20 +100,26 @@ static inline bool SPI_SLAVE_ISR_ATTR bus_is_iomux(spi_slave_t *host)
     return host->flags & SPICOMMON_BUSFLAG_IOMUX_PINS;
 }
 
-static void SPI_SLAVE_ISR_ATTR freeze_cs(spi_slave_t *host)
+static inline void SPI_SLAVE_ISR_ATTR freeze_cs(spi_slave_t *host)
 {
+#if SPI_LL_SLAVE_NEEDS_CS_WORKAROUND
+    // This workaround only for ESP32 due to old hardware design, see MR !3207
     esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, host->cs_in_signal, false);
+#endif
 }
 
 // Use this function instead of cs_initial to avoid overwrite the output config
 // This is used in test by internal gpio matrix connections
 static inline void SPI_SLAVE_ISR_ATTR restore_cs(spi_slave_t *host)
 {
+#if SPI_LL_SLAVE_NEEDS_CS_WORKAROUND
+    // This workaround only for ESP32 due to old hardware design, see MR !3207
     if (host->cs_iomux) {
         gpio_ll_iomux_in(GPIO_HAL_GET_HW(GPIO_PORT_0), host->cfg.spics_io_num, host->cs_in_signal);
     } else {
         esp_rom_gpio_connect_in_signal(host->cfg.spics_io_num, host->cs_in_signal, false);
     }
+#endif
 }
 
 #if (SOC_CPU_CORES_NUM > 1) && (!CONFIG_FREERTOS_UNICORE)
diff --git a/components/esp_eth/test_apps/main/esp_eth_test_apps.c b/components/esp_eth/test_apps/main/esp_eth_test_apps.c
index 392abe105866..c3793e20eeec 100644
--- a/components/esp_eth/test_apps/main/esp_eth_test_apps.c
+++ b/components/esp_eth/test_apps/main/esp_eth_test_apps.c
@@ -94,6 +94,82 @@ TEST_CASE("ethernet io test", "[ethernet]")
     extra_cleanup();
 }
 
+#ifdef CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720
+esp_err_t set_phy_reg_bits(esp_eth_handle_t eth_handle, uint32_t reg_addr, uint32_t bitmask, uint32_t max_attempts)
+{
+    esp_eth_phy_reg_rw_data_t reg = {
+        .reg_addr = reg_addr,
+        .reg_value_p = NULL
+    };
+    uint32_t reg_value, reg_value_rb;
+
+    for (uint32_t i = 0; i < max_attempts; i++) {
+        reg.reg_value_p = &reg_value;
+        esp_err_t ret = esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, &reg);
+        if (ret != ESP_OK) {
+            return ret;
+        }
+        reg_value |= bitmask;
+        ret = esp_eth_ioctl(eth_handle, ETH_CMD_WRITE_PHY_REG, &reg);
+        if (ret != ESP_OK) {
+            return ret;
+        }
+        reg.reg_value_p = &reg_value_rb;
+        ret = esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, &reg);
+        if (ret != ESP_OK) {
+            return ret;
+        }
+        // Check if the write was successful
+        if ((reg_value_rb & bitmask) == bitmask) {
+            return ESP_OK;
+        }
+        // Add delay only if not the last attempt
+        if (i < max_attempts - 1) {
+            ESP_LOGW(TAG, "Setting PHY register %04"PRIx32" failed, retrying... (attempt %"PRIu32" of %"PRIu32")", reg_addr, i + 1, max_attempts);
+            vTaskDelay(pdMS_TO_TICKS(10));
+        }
+    }
+    return ESP_ERR_TIMEOUT;
+}
+
+esp_err_t clear_phy_reg_bits(esp_eth_handle_t eth_handle, uint32_t reg_addr, uint32_t bitmask, uint32_t max_attempts)
+{
+    esp_eth_phy_reg_rw_data_t reg = {
+        .reg_addr = reg_addr,
+        .reg_value_p = NULL
+    };
+    uint32_t reg_value, reg_value_rb;
+
+    for (uint32_t i = 0; i < max_attempts; i++) {
+        reg.reg_value_p = &reg_value;
+        esp_err_t ret = esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, &reg);
+        if (ret != ESP_OK) {
+            return ret;
+        }
+        reg_value &= ~bitmask;
+        ret = esp_eth_ioctl(eth_handle, ETH_CMD_WRITE_PHY_REG, &reg);
+        if (ret != ESP_OK) {
+            return ret;
+        }
+        reg.reg_value_p = &reg_value_rb;
+        ret = esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, &reg);
+        if (ret != ESP_OK) {
+            return ret;
+        }
+        // Check if the write was successful
+        if ((reg_value_rb & bitmask) == 0) {
+            return ESP_OK;
+        }
+        // Add delay only if not the last attempt
+        if (i < max_attempts - 1) {
+            ESP_LOGW(TAG, "Clearing PHY register %04"PRIx32" failed, retrying... (attempt %"PRIu32" of %"PRIu32")", reg_addr, i + 1, max_attempts);
+            vTaskDelay(pdMS_TO_TICKS(10));
+        }
+    }
+    return ESP_ERR_TIMEOUT;
+}
+#endif // CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720
+
 // This test expects autonegotiation to be enabled on the other node.
 TEST_CASE("ethernet io speed/duplex/autonegotiation", "[ethernet]")
 {
@@ -168,17 +244,7 @@ TEST_CASE("ethernet io speed/duplex/autonegotiation", "[ethernet]")
 // Rationale: When the device is in manual 100BASE-TX or 10BASE-T modes with Auto-MDIX enabled, the PHY does not link to a
 //            link partner that is configured for auto-negotiation. See LAN8720 errata for more details.
 #ifdef CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720
-    esp_eth_phy_reg_rw_data_t reg;
-    uint32_t reg_val;
-    reg.reg_addr = 27;
-    reg.reg_value_p = &reg_val;
-    TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, &reg));
-    reg_val |= 0x8000;
-    TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_WRITE_PHY_REG, &reg));
-    uint32_t reg_val_act;
-    reg.reg_value_p = &reg_val_act;
-    TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, &reg));
-    TEST_ASSERT_EQUAL(reg_val, reg_val_act);
+    TEST_ESP_OK(set_phy_reg_bits(eth_handle, 27, 0x8000, 3));
 #endif
 
     // start the driver and wait for connection establish
@@ -263,13 +329,7 @@ TEST_CASE("ethernet io speed/duplex/autonegotiation", "[ethernet]")
 // *** LAN8720 deviation ***
 // Rationale: See above
 #ifdef CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720
-    reg.reg_value_p = &reg_val;
-    TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, &reg));
-    reg_val &= ~0x8000;
-    TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_WRITE_PHY_REG, &reg));
-    reg.reg_value_p = &reg_val_act;
-    TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, &reg));
-    TEST_ASSERT_EQUAL(reg_val, reg_val_act);
+    TEST_ESP_OK(clear_phy_reg_bits(eth_handle, 27, 0x8000, 3));
 #endif
 
     esp_eth_start(eth_handle);
@@ -568,17 +628,7 @@ TEST_CASE("ethernet start/stop stress test with IP stack", "[ethernet]")
 // Rationale: When the device is in manual 100BASE-TX or 10BASE-T modes with Auto-MDIX enabled, the PHY does not link to a
 //            link partner that is configured for auto-negotiation. See LAN8720 errata for more details.
 #ifdef CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720
-            esp_eth_phy_reg_rw_data_t reg;
-            uint32_t reg_val;
-            reg.reg_addr = 27;
-            reg.reg_value_p = &reg_val;
-            TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, &reg));
-            reg_val |= 0x8000;
-            TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_WRITE_PHY_REG, &reg));
-            uint32_t reg_val_act;
-            reg.reg_value_p = &reg_val_act;
-            TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, &reg));
-            TEST_ASSERT_EQUAL(reg_val, reg_val_act);
+            TEST_ESP_OK(set_phy_reg_bits(eth_handle, 27, 0x8000, 3));
 #endif
         }
         for (int i = 0; i < 10; i++) {
diff --git a/components/esp_psram/esp_psram.c b/components/esp_psram/esp_psram.c
index e9b2a55ad3d8..f1290548bfdc 100644
--- a/components/esp_psram/esp_psram.c
+++ b/components/esp_psram/esp_psram.c
@@ -138,6 +138,35 @@ static void IRAM_ATTR s_mapping(int v_start, int size)
 }
 #endif  //CONFIG_IDF_TARGET_ESP32
 
+#if CONFIG_ESP32P4_REV_MIN_FULL == 300
+#include "hal/psram_ctrlr_ll.h"
+static void IRAM_ATTR esp_psram_p4_rev3_workaround(void)
+{
+    spi_mem_s_dev_t backup_reg = {};
+    psram_ctrlr_ll_backup_registers(PSRAM_CTRLR_LL_MSPI_ID_2, &backup_reg);
+
+    __attribute__((unused)) volatile uint32_t val = 0;
+    psram_ctrlr_ll_disable_core_err_resp();
+
+    /**
+     * this workaround is to have two dummy reads, therefore
+     * - map 1 page
+     * - read 2 times
+     * - delay 1us
+     *
+     * The mapping will be overwritten by the real mapping in `s_psram_mapping`
+     */
+    mmu_ll_write_entry(1, 0, 0, MMU_TARGET_PSRAM0);
+    val = *(uint32_t *)(0x88000000);
+    val = *(uint32_t *)(0x88000080);
+    esp_rom_delay_us(1);
+
+    _psram_ctrlr_ll_reset_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2);
+    psram_ctrlr_ll_enable_core_err_resp();
+    psram_ctrlr_ll_restore_registers(PSRAM_CTRLR_LL_MSPI_ID_2, &backup_reg);
+}
+#endif
+
 static esp_err_t s_psram_chip_init(uint32_t *out_available_size)
 {
     if (s_psram_ctx.is_initialised) {
@@ -358,6 +387,10 @@ esp_err_t esp_psram_init(void)
         return ret;
     }
 
+#if CONFIG_ESP32P4_REV_MIN_FULL == 300
+    esp_psram_p4_rev3_workaround();
+#endif
+
     /**
      * `start_page` is the psram physical address in MMU page size.
      * MMU page size on ESP32S2 is 64KB
diff --git a/components/esp_system/linker.lf b/components/esp_system/linker.lf
index 666714c4952d..6aaa16b8838c 100644
--- a/components/esp_system/linker.lf
+++ b/components/esp_system/linker.lf
@@ -33,13 +33,6 @@ entries:
     if APP_BUILD_TYPE_RAM = n:
         image_process (noflash)
 
-[mapping:vfs_cdcacm]
-archive: libvfs.a
-entries:
-    if ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF:
-        vfs_cdcacm:cdcacm_tx_cb (noflash)
-        vfs_cdcacm:cdcacm_rx_cb (noflash)
-
 [mapping:esp_system_hal]
 archive: libhal.a
 entries:
diff --git a/components/esp_system/port/usb_console.c b/components/esp_system/port/usb_console.c
index 9ea95a34ed13..6e0849808a0b 100644
--- a/components/esp_system/port/usb_console.c
+++ b/components/esp_system/port/usb_console.c
@@ -494,11 +494,13 @@ void esp_usb_console_write_char(char c)
         esp_usb_console_write_buf(&c, 1);
     }
 }
-static inline void write_lock_acquire(void)
+
+static inline __attribute__((always_inline)) void write_lock_acquire(void)
 {
     portENTER_CRITICAL_SAFE(&s_lock);
 }
-static inline void write_lock_release(void)
+
+static inline __attribute__((always_inline)) void write_lock_release(void)
 {
     portEXIT_CRITICAL_SAFE(&s_lock);
 }
diff --git a/components/esp_vfs_console/CMakeLists.txt b/components/esp_vfs_console/CMakeLists.txt
index 50954747a70a..b5ee171f5f8b 100644
--- a/components/esp_vfs_console/CMakeLists.txt
+++ b/components/esp_vfs_console/CMakeLists.txt
@@ -9,7 +9,7 @@ set(srcs "vfs_console.c")
 idf_component_register(SRCS ${srcs}
                        INCLUDE_DIRS include
                        PRIV_REQUIRES vfs esp_driver_uart esp_driver_usb_serial_jtag
-                      )
+                       LDFRAGMENTS linker.lf)
 
 if(CONFIG_ESP_CONSOLE_USB_CDC)
     target_sources(${COMPONENT_LIB} PRIVATE "vfs_cdcacm.c")
diff --git a/components/esp_vfs_console/linker.lf b/components/esp_vfs_console/linker.lf
new file mode 100644
index 000000000000..e5d817a1e5d5
--- /dev/null
+++ b/components/esp_vfs_console/linker.lf
@@ -0,0 +1,6 @@
+[mapping:esp_vfs_console]
+archive: libesp_vfs_console.a
+entries:
+    if ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF:
+        vfs_cdcacm:cdcacm_tx_cb (noflash)
+        vfs_cdcacm:cdcacm_rx_cb (noflash)
diff --git a/components/esp_vfs_console/test_apps/usb_cdc_vfs/CMakeLists.txt b/components/esp_vfs_console/test_apps/usb_cdc_vfs/CMakeLists.txt
index 0f63d0caaa45..86ac25a3ab85 100644
--- a/components/esp_vfs_console/test_apps/usb_cdc_vfs/CMakeLists.txt
+++ b/components/esp_vfs_console/test_apps/usb_cdc_vfs/CMakeLists.txt
@@ -7,3 +7,17 @@ set(COMPONENTS main)
 
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 project(usb_cdc_vfs_test)
+
+idf_build_get_property(elf EXECUTABLE)
+if(CONFIG_COMPILER_DUMP_RTL_FILES)
+    add_custom_target(check_test_app_sections ALL
+                        COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
+                        --rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/driver/,${CMAKE_BINARY_DIR}/esp-idf/hal/
+                        --elf-file ${CMAKE_BINARY_DIR}/*.elf
+                        find-refs
+                        --from-sections=.iram0.text
+                        --to-sections=.flash.text,.flash.rodata
+                        --exit-code
+                        DEPENDS ${elf}
+                        )
+endif()
diff --git a/components/esp_vfs_console/test_apps/usb_cdc_vfs/main/test_app_main.c b/components/esp_vfs_console/test_apps/usb_cdc_vfs/main/test_app_main.c
index a82a7a6d1839..1d14ed505cb3 100644
--- a/components/esp_vfs_console/test_apps/usb_cdc_vfs/main/test_app_main.c
+++ b/components/esp_vfs_console/test_apps/usb_cdc_vfs/main/test_app_main.c
@@ -8,8 +8,10 @@
 #include <fcntl.h>
 #include <sys/errno.h>
 #include "unity.h"
+#include "unity_test_utils_cache.h"
 #include "esp_private/usb_console.h"
 #include "esp_vfs_cdcacm.h"
+#include "esp_rom_sys.h"
 
 static void flush_write(void)
 {
@@ -263,6 +265,39 @@ static void test_usb_cdc_read_no_exit_on_newline_reception(void)
     vTaskDelay(2);  // wait for tasks to exit
 }
 
+static void IRAM_ATTR test_input_output_post_cache_disable(void *args)
+{
+    static DRAM_ATTR const char test_msg[] = "test_message\n";
+    esp_rom_printf(test_msg);
+}
+
+/**
+ * @brief Test that the tx and rx cb are placed in IRAM correctly
+ */
+static void test_usb_cdc_ets_printf_cache_disabled(void)
+{
+    test_setup(__func__, sizeof(__func__));
+
+    /* make sure blocking mode is enabled */
+    int flags = fcntl(STDIN_FILENO, F_GETFL, 0);
+    fcntl(STDIN_FILENO, F_SETFL, flags & (~O_NONBLOCK));
+
+#if CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
+    unity_utils_run_cache_disable_stub(test_input_output_post_cache_disable, NULL);
+#else
+#error This test must run with CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF enabled
+#endif
+
+    // send message to the test environment to report successful test
+    char ready_msg[] = "successful test\n";
+    write(fileno(stdout), ready_msg, sizeof(ready_msg));
+
+    fcntl(STDIN_FILENO, F_SETFL, flags);
+    esp_vfs_dev_cdcacm_set_rx_line_endings(ESP_LINE_ENDINGS_CRLF);
+    esp_vfs_dev_cdcacm_set_tx_line_endings(ESP_LINE_ENDINGS_CRLF);
+    vTaskDelay(2);  // wait for tasks to exit
+}
+
 /* Always make sure that the function calling sequence in the main
  * function matches the expected order in the pytest function.
  */
@@ -272,4 +307,5 @@ void app_main(void)
     test_usb_cdc_read_non_blocking();
     test_usb_cdc_read_blocking();
     test_usb_cdc_read_no_exit_on_newline_reception();
+    test_usb_cdc_ets_printf_cache_disabled();
 }
diff --git a/components/esp_vfs_console/test_apps/usb_cdc_vfs/pytest_usb_cdc_vfs.py b/components/esp_vfs_console/test_apps/usb_cdc_vfs/pytest_usb_cdc_vfs.py
index 8693a8b0b9fb..434dfbab7704 100644
--- a/components/esp_vfs_console/test_apps/usb_cdc_vfs/pytest_usb_cdc_vfs.py
+++ b/components/esp_vfs_console/test_apps/usb_cdc_vfs/pytest_usb_cdc_vfs.py
@@ -37,3 +37,8 @@ def test_usb_cdc_vfs_default(dut: Dut) -> None:
     dut.expect_exact('test_usb_cdc_read_no_exit_on_newline_reception', timeout=2)
     dut.expect_exact('ready to receive', timeout=2)
     dut.write('!(@*#&(!*@&#((SDasdkjhad\nce')
+
+    # test run: test_usb_cdc_ets_printf_cache_disabled
+    dut.expect_exact('test_usb_cdc_ets_printf_cache_disabled', timeout=2)
+    dut.expect_exact('test_message', timeout=2)
+    dut.expect_exact('successful test', timeout=2)
diff --git a/components/esp_vfs_console/test_apps/usb_cdc_vfs/sdkconfig.defaults b/components/esp_vfs_console/test_apps/usb_cdc_vfs/sdkconfig.defaults
index 9f592f746371..308212da8406 100644
--- a/components/esp_vfs_console/test_apps/usb_cdc_vfs/sdkconfig.defaults
+++ b/components/esp_vfs_console/test_apps/usb_cdc_vfs/sdkconfig.defaults
@@ -1,8 +1,12 @@
 # Enable Unity fixture support
 CONFIG_UNITY_ENABLE_FIXTURE=n
 CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
+CONFIG_COMPILER_DUMP_RTL_FILES=y
 
 # Custom partition table for this test app
 CONFIG_ESP_TASK_WDT_INIT=n
 
 CONFIG_ESP_CONSOLE_USB_CDC=y
+
+# one test requires this option to be enabled
+CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF=y
diff --git a/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_psram.c b/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_psram.c
index 866b4e4bba4a..ea6413883e39 100644
--- a/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_psram.c
+++ b/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_psram.c
@@ -140,6 +140,9 @@ TEST_CASE("Task on specific core works", "[freertos][psram]")
         TEST_ASSERT_EQUAL((size_t) corenum, corenum_info.recorded_core_num);
 
         vTaskDelete(task_handle);
+
+        // Add a short delay to allow the idle task to free any remaining task memory
+        vTaskDelay(10);
     }
 }
 #endif // !CONFIG_FREERTOS_UNICORE
diff --git a/components/freertos/test_apps/freertos/kernel/tasks/test_vTaskSuspendAll_xTaskResumeAll.c b/components/freertos/test_apps/freertos/kernel/tasks/test_vTaskSuspendAll_xTaskResumeAll.c
index 97acb852571a..5bc1ae55b70c 100644
--- a/components/freertos/test_apps/freertos/kernel/tasks/test_vTaskSuspendAll_xTaskResumeAll.c
+++ b/components/freertos/test_apps/freertos/kernel/tasks/test_vTaskSuspendAll_xTaskResumeAll.c
@@ -387,6 +387,7 @@ TEST_CASE("Test vTaskSuspendAll allows scheduling on other cores", "[freertos]")
         // Cleanup tasks
         vTaskDelete(a1_task_hdl);
         vTaskDelete(b1_task_hdl);
+        vTaskDelay(10);
     }
 
     vSemaphoreDelete(test_unblk_done_sem);
diff --git a/components/freertos/test_apps/freertos/kernel/tasks/test_yielding.c b/components/freertos/test_apps/freertos/kernel/tasks/test_yielding.c
index 6da218976f75..9d5d7b2c5e6a 100644
--- a/components/freertos/test_apps/freertos/kernel/tasks/test_yielding.c
+++ b/components/freertos/test_apps/freertos/kernel/tasks/test_yielding.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -34,6 +34,9 @@ static volatile uint32_t count;
 // Lock variable to create a blocked task scenario
 static volatile SemaphoreHandle_t task_mutex;
 
+// Semaphore to synchronize yield test tasks
+static SemaphoreHandle_t yield_sync_sem;
+
 // This helper macro is used to store the task id atomically
 #define STORE_TASK_ID(task_id)  ({ \
         portENTER_CRITICAL(&idx_lock); \
@@ -56,10 +59,11 @@ static void yield_task1(void *arg)
     /* Store task_id in the sequence array */
     STORE_TASK_ID(task_id);
 
-    /* Notify the yield_task2 to run */
-    task_sequence_ready = true;
+    /* Give semaphore to unblock yield_task2, making it READY (not just setting a flag).
+     * This ensures task2 is in the ready queue when we yield. */
+    xSemaphoreGive(yield_sync_sem);
 
-    /* Yield */
+    /* Yield - now task2 is guaranteed to be READY and should run next */
     taskYIELD();
 
     /* Increment task count to notify unity task */
@@ -73,10 +77,9 @@ static void yield_task2(void *arg)
 {
     uint32_t task_id = (uint32_t)arg;
 
-    /* Wait for the other task to run for the test to begin */
-    while (!task_sequence_ready) {
-        vTaskDelay(10);
-    };
+    /* Block on semaphore - this ensures task1 runs first and we don't poll.
+     * When task1 gives the semaphore, we transition directly to READY state. */
+    xSemaphoreTake(yield_sync_sem, portMAX_DELAY);
 
     /* Store task_id in the sequence array */
     STORE_TASK_ID(task_id);
@@ -108,9 +111,16 @@ TEST_CASE("Task yield must run the next ready task of the same priority", "[free
     /* Reset task sequence flag */
     task_sequence_ready = false;
 
-    /* Create test tasks */
-    xTaskCreatePinnedToCore(yield_task1, "yield_task1", 2048, (void *)1, UNITY_FREERTOS_PRIORITY - 1, NULL, UNITY_FREERTOS_CPU);
+    /* Create semaphore for synchronization - start empty so task2 blocks */
+    yield_sync_sem = xSemaphoreCreateBinary();
+    TEST_ASSERT_NOT_NULL(yield_sync_sem);
+
+    /* Create test tasks - order matters!
+     * Task2 is created first and will immediately block on the semaphore.
+     * Task1 is created second and will run first since task2 is blocked. */
     xTaskCreatePinnedToCore(yield_task2, "yield_task2", 2048, (void *)2, UNITY_FREERTOS_PRIORITY - 1, NULL, UNITY_FREERTOS_CPU);
+    vTaskDelay(1); /* Ensure task2 has blocked on semaphore before creating task1 */
+    xTaskCreatePinnedToCore(yield_task1, "yield_task1", 2048, (void *)1, UNITY_FREERTOS_PRIORITY - 1, NULL, UNITY_FREERTOS_CPU);
 
     /* Wait for the tasks to finish up */
     while (count != 2) {
@@ -122,6 +132,9 @@ TEST_CASE("Task yield must run the next ready task of the same priority", "[free
     /* Verify that the yield is successful and the next ready task is run */
     TEST_ASSERT_EQUAL(1, task_yield_sequence[idx++]);
     TEST_ASSERT_EQUAL(2, task_yield_sequence[idx++]);
+
+    /* Clean up semaphore */
+    vSemaphoreDelete(yield_sync_sem);
 }
 
 /*
diff --git a/components/freertos/test_apps/freertos/misc/test_tickless_idle.c b/components/freertos/test_apps/freertos/misc/test_tickless_idle.c
index 7ed64ddf354e..aa73b5346c5d 100644
--- a/components/freertos/test_apps/freertos/misc/test_tickless_idle.c
+++ b/components/freertos/test_apps/freertos/misc/test_tickless_idle.c
@@ -10,6 +10,7 @@
 #include "freertos/semphr.h"
 #include "esp_pm.h"
 #include "esp_private/esp_clk.h"
+#include "esp_clk_tree.h"
 
 #include "sdkconfig.h"
 
@@ -66,9 +67,11 @@ static void consumer_task(void *arg)
 TEST_CASE("Test semaphore timeout during tickless idle", "[freertos]")
 {
     // Configure tickless idle
+    uint32_t xtal_hz = 0;
+    esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_XTAL, ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT, &xtal_hz);
     esp_pm_config_t pm_config = {
-        .max_freq_mhz = esp_clk_cpu_freq() / MHZ,
-        .min_freq_mhz = esp_clk_cpu_freq() / MHZ,
+        .max_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ,
+        .min_freq_mhz = xtal_hz / MHZ,
         .light_sleep_enable = true,
     };
     TEST_ESP_OK(esp_pm_configure(&pm_config));
diff --git a/components/hal/cam_hal.c b/components/hal/cam_hal.c
index 101cf3bfcbe9..c739f05d91f8 100644
--- a/components/hal/cam_hal.c
+++ b/components/hal/cam_hal.c
@@ -1,14 +1,25 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include "hal/cam_ll.h"
 #include "hal/cam_hal.h"
+#include "hal/color_types.h"
 #include "soc/soc_caps.h"
 #include "soc/cam_periph.h"
 
+/**
+ * @brief Default format conversion configuration
+ */
+#define CAM_HAL_DEFAULT_FORMAT_CONV_CONFIG { \
+    .conv_std = COLOR_CONV_STD_RGB_YUV_BT601, \
+    .data_width = 8, \
+    .input_range = COLOR_RANGE_LIMIT, \
+    .output_range = COLOR_RANGE_LIMIT \
+}
+
 /**
  * @brief Configure line number to trigger interrupt
  *
@@ -119,3 +130,59 @@ void cam_hal_stop_streaming(cam_hal_context_t *hal)
 {
     cam_ll_stop(hal->hw);
 }
+
+/**
+ * @brief Configure color format conversion
+ *
+ * This function handles all types of color format conversions:
+ * - YUV to RGB conversion
+ * - RGB to YUV conversion
+ * - YUV to YUV conversion
+ *
+ * Color range support:
+ * - Full range: 0-255 for both RGB and YUV
+ * - Limited range: RGB 16-240, YUV Y:16-240, U-V:16-235
+ *
+ * @param hal    CAM HAL context pointer
+ * @param config Color conversion configuration. If NULL, default config is used.
+ */
+void cam_hal_color_format_convert(cam_hal_context_t *hal,
+                                 const cam_ctlr_format_conv_config_t *config)
+{
+    // Use provided config or default
+    const cam_ctlr_format_conv_config_t *cfg = config;
+    if (cfg == NULL) {
+        static const cam_ctlr_format_conv_config_t default_config = CAM_HAL_DEFAULT_FORMAT_CONV_CONFIG;
+        cfg = &default_config;
+    }
+
+    cam_ll_enable_rgb_yuv_convert(hal->hw, false);
+
+    // Extract color space from source and destination formats
+    color_space_t src_space = COLOR_SPACE_TYPE(cfg->src_format);
+    color_space_t dst_space = COLOR_SPACE_TYPE(cfg->dst_format);
+
+    // Configure conversion based on color space types
+    if (src_space == COLOR_SPACE_YUV && dst_space == COLOR_SPACE_RGB) {
+        // YUV to RGB conversion
+        color_pixel_yuv_format_t yuv_format = COLOR_PIXEL_FORMAT(cfg->src_format);
+        cam_ll_set_convert_mode_yuv_to_rgb(hal->hw, yuv_format);
+    } else if (src_space == COLOR_SPACE_RGB && dst_space == COLOR_SPACE_YUV) {
+        // RGB to YUV conversion
+        color_pixel_yuv_format_t yuv_format = COLOR_PIXEL_FORMAT(cfg->dst_format);
+        cam_ll_set_convert_mode_rgb_to_yuv(hal->hw, yuv_format);
+    } else if (src_space == COLOR_SPACE_YUV && dst_space == COLOR_SPACE_YUV) {
+        // YUV to YUV conversion
+        color_pixel_yuv_format_t src_yuv_format = COLOR_PIXEL_FORMAT(cfg->src_format);
+        color_pixel_yuv_format_t dst_yuv_format = COLOR_PIXEL_FORMAT(cfg->dst_format);
+        cam_ll_set_convert_mode_yuv_to_yuv(hal->hw, src_yuv_format, dst_yuv_format);
+    }
+
+    // Common configuration for all conversion types
+    cam_ll_set_yuv_convert_std(hal->hw, cfg->conv_std);
+    cam_ll_set_convert_data_width(hal->hw, cfg->data_width);
+    cam_ll_set_input_color_range(hal->hw, cfg->input_range);
+    cam_ll_set_output_color_range(hal->hw, cfg->output_range);
+
+    cam_ll_enable_rgb_yuv_convert(hal->hw, true);
+}
diff --git a/components/hal/esp32/include/hal/spi_ll.h b/components/hal/esp32/include/hal/spi_ll.h
index 84113565176e..b7f907877c1c 100644
--- a/components/hal/esp32/include/hal/spi_ll.h
+++ b/components/hal/esp32/include/hal/spi_ll.h
@@ -44,6 +44,12 @@ extern "C" {
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_MOSI_FREE_LEVEL    0            //Default level after bus initialized
 
+// CS_WORKAROUND: SPI slave with using DMA, the rx dma suffers from unexpected transactions
+// before slave is ready, need disconnect CS before and after each transaction
+#define SPI_LL_SLAVE_NEEDS_CS_WORKAROUND    1
+#define SPI_LL_SLAVE_NEEDS_RESET_WORKAROUND 1
+#define SPI_LL_SUPPORT_TIME_TUNING          1
+
 /**
  * The data structure holding calculated clock configuration. Since the
  * calculation needs long time, it should be calculated during initialization and
diff --git a/components/hal/esp32p4/include/hal/psram_ctrlr_ll.h b/components/hal/esp32p4/include/hal/psram_ctrlr_ll.h
index 7579bd674e86..e0109ac02147 100644
--- a/components/hal/esp32p4/include/hal/psram_ctrlr_ll.h
+++ b/components/hal/esp32p4/include/hal/psram_ctrlr_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,12 +17,14 @@
 #include <sys/param.h>
 #include "hal/assert.h"
 #include "hal/misc.h"
+#include "hal/config.h"
 #include "soc/spi_mem_s_struct.h"
 #include "soc/spi_mem_s_reg.h"
 #include "soc/spi1_mem_s_reg.h"
 #include "soc/spi1_mem_s_struct.h"
 #include "soc/hp_sys_clkrst_struct.h"
 #include "soc/clk_tree_defs.h"
+#include "soc/hp_system_struct.h"
 #include "rom/opi_flash.h"
 
 #ifdef __cplusplus
@@ -256,6 +258,52 @@ static inline void psram_ctrlr_ll_enable_axi_access(uint32_t mspi_id, bool en)
     SPIMEM2.mem_cache_fctrl.close_axi_inf_en = !en;
 }
 
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+/**
+ * @brief Enable PSRAM AXI weight arbiter for TX / RX AXI requests
+ *
+ * @param mspi_id      mspi_id
+ * @param en           enable / disable
+ */
+__attribute__((always_inline))
+static inline void psram_ctrlr_ll_enable_axi_req_weight_arbiter(uint32_t mspi_id, bool en)
+{
+    (void)mspi_id;
+    SPIMEM2.mem_cache_fctrl.mem_arb_wei_en = en;
+}
+
+/**
+ * @brief Set PSRAM AXI request weight
+ *
+ * @param mspi_id      mspi_id
+ * @param rd_weight    read weight
+ * @param wr_weight    write weight
+ */
+__attribute__((always_inline))
+static inline void psram_ctrlr_ll_set_axi_req_weight(uint32_t mspi_id, uint32_t rd_weight, uint32_t wr_weight)
+{
+    //1~15
+    HAL_ASSERT(rd_weight && rd_weight < 16);
+    HAL_ASSERT(wr_weight && wr_weight < 16);
+
+    SPIMEM2.mem_cache_fctrl.mem_arb_req0_wei = rd_weight;
+    SPIMEM2.mem_cache_fctrl.mem_arb_req1_wei = wr_weight;
+}
+
+/**
+ * @brief Set PSRAM AXI request priority
+ *
+ * @param mspi_id      mspi_id
+ * @param rd_prio      read priority
+ * @param wr_prio      write priority
+ */
+static inline void psram_ctrlr_ll_set_axi_req_priority(uint32_t mspi_id, uint32_t rd_prio, uint32_t wr_prio)
+{
+    SPIMEM2.mem_cache_fctrl.mem_arb_req0_pri = rd_prio;
+    SPIMEM2.mem_cache_fctrl.mem_arb_req1_pri = wr_prio;
+}
+#endif
+
 /**
  * @brief Enable PSRAM write splice transfer
  *
@@ -306,18 +354,18 @@ static inline void _psram_ctrlr_ll_enable_module_clock(uint32_t mspi_id, bool en
  * @param mspi_id      mspi_id
  */
 __attribute__((always_inline))
-static inline void psram_ctrlr_ll_reset_module_clock(uint32_t mspi_id)
+static inline void _psram_ctrlr_ll_reset_module_clock(uint32_t mspi_id)
 {
     (void)mspi_id;
     HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_dual_mspi_axi = 1;
-    HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_dual_mspi_axi = 0;
     HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_dual_mspi_apb = 1;
     HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_dual_mspi_apb = 0;
+    HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_dual_mspi_axi = 0;
 }
 
 /// use a macro to wrap the function, force the caller to use it in a critical section
 /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
-#define psram_ctrlr_ll_reset_module_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; psram_ctrlr_ll_reset_module_clock(__VA_ARGS__)
+#define psram_ctrlr_ll_reset_module_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _psram_ctrlr_ll_reset_module_clock(__VA_ARGS__)
 
 /**
  * @brief Select PSRAM clock source
@@ -767,6 +815,48 @@ static inline void psram_ctrlr_ll_wait_all_transaction_done(void)
     }
 }
 
+/**
+ * @brief Backup PSRAM controller registers
+ *
+ * @param mspi_id     mspi_id
+ * @param reg         registers
+ */
+__attribute__((always_inline))
+static inline void psram_ctrlr_ll_backup_registers(uint32_t mspi_id, spi_mem_s_dev_t *reg)
+{
+    memcpy(reg, &SPIMEM2, sizeof(spi_mem_s_dev_t));
+}
+
+/**
+ * @brief Restore PSRAM controller registers
+ *
+ * @param mspi_id     mspi_id
+ * @param reg         registers
+ */
+__attribute__((always_inline))
+static inline void psram_ctrlr_ll_restore_registers(uint32_t mspi_id, spi_mem_s_dev_t *reg)
+{
+    memcpy(&SPIMEM2, reg, sizeof(spi_mem_s_dev_t));
+}
+
+/**
+ * @brief Disable core error response
+ */
+__attribute__((always_inline))
+static inline void psram_ctrlr_ll_disable_core_err_resp(void)
+{
+    HP_SYSTEM.core_err_resp_dis.val = 0x7;
+}
+
+/**
+ * @brief Enable core error response
+ */
+__attribute__((always_inline))
+static inline void psram_ctrlr_ll_enable_core_err_resp(void)
+{
+    HP_SYSTEM.core_err_resp_dis.val = 0x0;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32p4/include/hal/spi_ll.h b/components/hal/esp32p4/include/hal/spi_ll.h
index ecceb158a477..60c14f2161f1 100644
--- a/components/hal/esp32p4/include/hal/spi_ll.h
+++ b/components/hal/esp32p4/include/hal/spi_ll.h
@@ -16,6 +16,7 @@
 
 #include <stdlib.h> //for abs()
 #include <string.h>
+#include "hal/config.h"
 #include "esp_types.h"
 #include "soc/spi_periph.h"
 #include "soc/spi_struct.h"
@@ -247,6 +248,10 @@ static inline void spi_ll_master_init(spi_dev_t *hw)
     hw->slave.val = 0;
     hw->user.val = 0;
 
+    //Disable unused error_end condition
+    hw->user1.mst_wfull_err_end_en = 0;
+    hw->user2.mst_rempty_err_end_en = 0;
+
     hw->dma_conf.val = 0;
     hw->dma_conf.slv_tx_seg_trans_clr_en = 1;
     hw->dma_conf.slv_rx_seg_trans_clr_en = 1;
@@ -748,13 +753,16 @@ static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active)
  *----------------------------------------------------------------------------*/
 /**
  * Set the standard clock mode for master.
+ * This config take effect only when SPI_CLK (pre-div before periph) div >=2
  *
  * @param hw  Beginning address of the peripheral registers.
  * @param enable_std True for std timing, False for half cycle delay sampling.
  */
 static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_point_t sample_point)
 {
-    //This is not supported
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    hw->clock.clk_edge_sel = (sample_point == SPI_SAMPLING_POINT_PHASE_1);
+#endif
 }
 
 /**
@@ -762,7 +770,11 @@ static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_
  */
 static inline bool spi_ll_master_is_rx_std_sample_supported(void)
 {
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    return true;
+#else
     return false;
+#endif
 }
 
 /**
diff --git a/components/hal/include/hal/cam_ctlr_types.h b/components/hal/include/hal/cam_ctlr_types.h
index 65ba68c29d6c..7b0001e9792e 100644
--- a/components/hal/include/hal/cam_ctlr_types.h
+++ b/components/hal/include/hal/cam_ctlr_types.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -39,6 +39,18 @@ typedef enum {
     CAM_CTLR_DATA_WIDTH_16 = 16,    ///< 16-bit data width
 } cam_ctlr_data_width_t;
 
+/**
+ * @brief Camera Controller format conversion configuration
+ */
+typedef struct {
+    cam_ctlr_color_t src_format;           /*!< Source format */
+    cam_ctlr_color_t dst_format;           /*!< Destination format */
+    color_conv_std_rgb_yuv_t conv_std;     /*!< Conversion standard */
+    uint32_t data_width;                   /*!< Data width in bits */
+    color_range_t input_range;             /*!< Input color range */
+    color_range_t output_range;            /*!< Output color range */
+} cam_ctlr_format_conv_config_t;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/include/hal/cam_hal.h b/components/hal/include/hal/cam_hal.h
index 2b1c9229b6ca..e63e6440e5cd 100644
--- a/components/hal/include/hal/cam_hal.h
+++ b/components/hal/include/hal/cam_hal.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -68,6 +68,24 @@ void cam_hal_start_streaming(cam_hal_context_t *hal);
  */
 void cam_hal_stop_streaming(cam_hal_context_t *hal);
 
+/**
+ * @brief Configure color format conversion
+ *
+ * This function handles all types of color format conversions:
+ * - YUV to RGB conversion
+ * - RGB to YUV conversion
+ * - YUV to YUV conversion
+ *
+ * Color range support:
+ * - Full range: 0-255 for both RGB and YUV
+ * - Limited range: RGB 16-240, YUV Y:16-240, U-V:16-235
+ *
+ * @param hal    CAM HAL context pointer
+ * @param config Color conversion configuration. If NULL, default config is used.
+ */
+void cam_hal_color_format_convert(cam_hal_context_t *hal,
+                                 const cam_ctlr_format_conv_config_t *config);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h
index e48b0e6b4309..86a980f8e0e6 100644
--- a/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h
+++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h
@@ -2123,7 +2123,7 @@ typedef union {
 } hp_hp2lp_intr_group3_st_reg_t;
 
 
-typedef struct {
+typedef struct hp_system_dev_t {
     volatile hp_sys_ver_date_reg_t sys_ver_date;
     volatile hp_clk_en_reg_t clk_en;
     uint32_t reserved_008[2];
@@ -2244,12 +2244,12 @@ typedef struct {
     volatile hp_hp2lp_wakeup_group1_en_reg_t hp2lp_wakeup_group1_en;
     volatile hp_hp2lp_wakeup_group2_en_reg_t hp2lp_wakeup_group2_en;
     volatile hp_hp2lp_wakeup_group3_en_reg_t hp2lp_wakeup_group3_en;
-} hp_dev_t;
+} hp_system_dev_t;
 
-extern hp_dev_t HP_SYSTEM;
+extern hp_system_dev_t HP_SYSTEM;
 
 #ifndef __cplusplus
-_Static_assert(sizeof(hp_dev_t) == 0x220, "Invalid size of hp_dev_t structure");
+_Static_assert(sizeof(hp_system_dev_t) == 0x220, "Invalid size of hp_dev_t structure");
 #endif
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_eco5_struct.h
deleted file mode 100644
index c94e6559ab50..000000000000
--- a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_eco5_struct.h
+++ /dev/null
@@ -1,452 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: csi bridge regbank clock gating control register. */
-/** Type of clk_en register
- *  csi bridge register mapping unit clock gating.
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  0: enable clock gating. 1: disable clock gating, clock always on.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} csi_brg_clk_en_reg_t;
-
-
-/** Group: csi bridge control registers. */
-/** Type of csi_en register
- *  csi bridge enable.
- */
-typedef union {
-    struct {
-        /** csi_brg_en : R/W; bitpos: [0]; default: 0;
-         *  0: disable csi bridge. 1: enable csi bridge.
-         */
-        uint32_t csi_brg_en:1;
-        /** csi_brg_rst : R/W; bitpos: [1]; default: 0;
-         *  0: release csi bridge reset. 1: enable csi bridge reset.
-         */
-        uint32_t csi_brg_rst:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} csi_brg_csi_en_reg_t;
-
-/** Type of buf_flow_ctl register
- *  csi bridge buffer control.
- */
-typedef union {
-    struct {
-        /** csi_buf_afull_thrd : R/W; bitpos: [13:0]; default: 2040;
-         *  buffer almost full threshold.
-         */
-        uint32_t csi_buf_afull_thrd:14;
-        uint32_t reserved_14:2;
-        /** csi_buf_depth : RO; bitpos: [29:16]; default: 0;
-         *  buffer data count.
-         */
-        uint32_t csi_buf_depth:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} csi_brg_buf_flow_ctl_reg_t;
-
-
-/** Group: csi bridge dma control registers. */
-/** Type of dma_req_cfg register
- *  dma request configuration.
- */
-typedef union {
-    struct {
-        /** dma_burst_len : R/W; bitpos: [11:0]; default: 128;
-         *  DMA burst length.
-         */
-        uint32_t dma_burst_len:12;
-        /** dma_cfg_upd_by_blk : R/W; bitpos: [12]; default: 0;
-         *  1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0:
-         *  updated by frame.
-         */
-        uint32_t dma_cfg_upd_by_blk:1;
-        uint32_t reserved_13:3;
-        /** dma_force_rd_status : R/W; bitpos: [16]; default: 0;
-         *  1: mask dma request when reading frame info. 0: disable mask.
-         */
-        uint32_t dma_force_rd_status:1;
-        /** csi_dma_flow_controller : R/W; bitpos: [17]; default: 1;
-         *  0: dma as flow controller. 1: csi_bridge as flow controller
-         */
-        uint32_t csi_dma_flow_controller:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} csi_brg_dma_req_cfg_reg_t;
-
-/** Type of dma_req_interval register
- *  DMA interval configuration.
- */
-typedef union {
-    struct {
-        /** dma_req_interval : R/W; bitpos: [15:0]; default: 1;
-         *  16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle.
-         */
-        uint32_t dma_req_interval:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_brg_dma_req_interval_reg_t;
-
-/** Type of dmablk_size register
- *  DMA block size configuration.
- */
-typedef union {
-    struct {
-        /** dmablk_size : R/W; bitpos: [12:0]; default: 8191;
-         *  the number of reg_dma_burst_len in a block
-         */
-        uint32_t dmablk_size:13;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} csi_brg_dmablk_size_reg_t;
-
-
-/** Group: csi bridge frame format configuration registers. */
-/** Type of data_type_cfg register
- *  pixel data type configuration.
- */
-typedef union {
-    struct {
-        /** data_type_min : R/W; bitpos: [5:0]; default: 24;
-         *  the min value of data type used for pixel filter.
-         */
-        uint32_t data_type_min:6;
-        uint32_t reserved_6:2;
-        /** data_type_max : R/W; bitpos: [13:8]; default: 47;
-         *  the max value of data type used for pixel filter.
-         */
-        uint32_t data_type_max:6;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} csi_brg_data_type_cfg_reg_t;
-
-/** Type of frame_cfg register
- *  frame configuration.
- */
-typedef union {
-    struct {
-        /** vadr_num : R/W; bitpos: [11:0]; default: 480;
-         *  vadr of frame data.
-         */
-        uint32_t vadr_num:12;
-        /** hadr_num : R/W; bitpos: [23:12]; default: 480;
-         *  hadr of frame data.
-         */
-        uint32_t hadr_num:12;
-        /** has_hsync_e : R/W; bitpos: [24]; default: 1;
-         *  0: frame data doesn't contain hsync. 1: frame data contains hsync.
-         */
-        uint32_t has_hsync_e:1;
-        /** vadr_num_check : R/W; bitpos: [25]; default: 0;
-         *  0: disable vadr check. 1: enable vadr check.
-         */
-        uint32_t vadr_num_check:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} csi_brg_frame_cfg_reg_t;
-
-/** Type of endian_mode register
- *  data endianness order configuration.
- */
-typedef union {
-    struct {
-        /** byte_endian_order : R/W; bitpos: [0]; default: 0;
-         *  endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy)
-         *  when isp is bapassed.
-         */
-        uint32_t byte_endian_order:1;
-        /** bit_endian_order : R/W; bitpos: [1]; default: 0;
-         *  N/A
-         */
-        uint32_t bit_endian_order:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} csi_brg_endian_mode_reg_t;
-
-
-/** Group: csi bridge interrupt registers. */
-/** Type of int_raw register
- *  csi bridge interrupt raw.
- */
-typedef union {
-    struct {
-        /** vadr_num_gt_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  reg_vadr_num is greater than real interrupt raw.
-         */
-        uint32_t vadr_num_gt_int_raw:1;
-        /** vadr_num_lt_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  reg_vadr_num is less than real interrupt raw.
-         */
-        uint32_t vadr_num_lt_int_raw:1;
-        /** discard_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  an incomplete frame of data was sent interrupt raw.
-         */
-        uint32_t discard_int_raw:1;
-        /** csi_buf_overrun_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  buffer overrun interrupt raw.
-         */
-        uint32_t csi_buf_overrun_int_raw:1;
-        /** csi_async_fifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  buffer overflow interrupt raw.
-         */
-        uint32_t csi_async_fifo_ovf_int_raw:1;
-        /** dma_cfg_has_updated_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  dma configuration update complete interrupt raw.
-         */
-        uint32_t dma_cfg_has_updated_int_raw:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} csi_brg_int_raw_reg_t;
-
-/** Type of int_clr register
- *  csi bridge interrupt clr.
- */
-typedef union {
-    struct {
-        /** vadr_num_gt_real_int_clr : WT; bitpos: [0]; default: 0;
-         *  reg_vadr_num is greater than real interrupt clr.
-         */
-        uint32_t vadr_num_gt_real_int_clr:1;
-        /** vadr_num_lt_real_int_clr : WT; bitpos: [1]; default: 0;
-         *  reg_vadr_num is less than real interrupt clr.
-         */
-        uint32_t vadr_num_lt_real_int_clr:1;
-        /** discard_int_clr : WT; bitpos: [2]; default: 0;
-         *  an incomplete frame of data was sent interrupt clr.
-         */
-        uint32_t discard_int_clr:1;
-        /** csi_buf_overrun_int_clr : WT; bitpos: [3]; default: 0;
-         *  buffer overrun interrupt clr.
-         */
-        uint32_t csi_buf_overrun_int_clr:1;
-        /** csi_async_fifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
-         *  buffer overflow interrupt clr.
-         */
-        uint32_t csi_async_fifo_ovf_int_clr:1;
-        /** dma_cfg_has_updated_int_clr : WT; bitpos: [5]; default: 0;
-         *  dma configuration update complete interrupt clr.
-         */
-        uint32_t dma_cfg_has_updated_int_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} csi_brg_int_clr_reg_t;
-
-/** Type of int_st register
- *  csi bridge interrupt st.
- */
-typedef union {
-    struct {
-        /** vadr_num_gt_int_st : RO; bitpos: [0]; default: 0;
-         *  reg_vadr_num is greater than real interrupt st.
-         */
-        uint32_t vadr_num_gt_int_st:1;
-        /** vadr_num_lt_int_st : RO; bitpos: [1]; default: 0;
-         *  reg_vadr_num is less than real interrupt st.
-         */
-        uint32_t vadr_num_lt_int_st:1;
-        /** discard_int_st : RO; bitpos: [2]; default: 0;
-         *  an incomplete frame of data was sent interrupt st.
-         */
-        uint32_t discard_int_st:1;
-        /** csi_buf_overrun_int_st : RO; bitpos: [3]; default: 0;
-         *  buffer overrun interrupt st.
-         */
-        uint32_t csi_buf_overrun_int_st:1;
-        /** csi_async_fifo_ovf_int_st : RO; bitpos: [4]; default: 0;
-         *  buffer overflow interrupt st.
-         */
-        uint32_t csi_async_fifo_ovf_int_st:1;
-        /** dma_cfg_has_updated_int_st : RO; bitpos: [5]; default: 0;
-         *  dma configuration update complete interrupt st.
-         */
-        uint32_t dma_cfg_has_updated_int_st:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} csi_brg_int_st_reg_t;
-
-/** Type of int_ena register
- *  csi bridge interrupt enable.
- */
-typedef union {
-    struct {
-        /** vadr_num_gt_int_ena : R/W; bitpos: [0]; default: 0;
-         *  reg_vadr_num is greater than real interrupt enable.
-         */
-        uint32_t vadr_num_gt_int_ena:1;
-        /** vadr_num_lt_int_ena : R/W; bitpos: [1]; default: 0;
-         *  reg_vadr_num is less than real interrupt enable.
-         */
-        uint32_t vadr_num_lt_int_ena:1;
-        /** discard_int_ena : R/W; bitpos: [2]; default: 0;
-         *  an incomplete frame of data was sent interrupt enable.
-         */
-        uint32_t discard_int_ena:1;
-        /** csi_buf_overrun_int_ena : R/W; bitpos: [3]; default: 0;
-         *  buffer overrun interrupt enable.
-         */
-        uint32_t csi_buf_overrun_int_ena:1;
-        /** csi_async_fifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
-         *  buffer overflow interrupt enable.
-         */
-        uint32_t csi_async_fifo_ovf_int_ena:1;
-        /** dma_cfg_has_updated_int_ena : R/W; bitpos: [5]; default: 0;
-         *  dma configuration update complete interrupt enable.
-         */
-        uint32_t dma_cfg_has_updated_int_ena:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} csi_brg_int_ena_reg_t;
-
-
-/** Group: csi-host control registers from csi bridge regbank. */
-/** Type of host_ctrl register
- *  csi host control by csi bridge.
- */
-typedef union {
-    struct {
-        /** csi_enableclk : R/W; bitpos: [0]; default: 1;
-         *  enable clock lane module of csi phy.
-         */
-        uint32_t csi_enableclk:1;
-        /** csi_cfg_clk_en : R/W; bitpos: [1]; default: 1;
-         *  enable cfg_clk of csi host module.
-         */
-        uint32_t csi_cfg_clk_en:1;
-        /** loopbk_test_en : R/W; bitpos: [2]; default: 0;
-         *  for phy test by loopback dsi phy to csi phy.
-         */
-        uint32_t loopbk_test_en:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} csi_brg_host_ctrl_reg_t;
-
-
-/** Group: csi host color mode control registers. */
-/** Type of host_cm_ctrl register
- *  CSI HOST color mode convert configuration.
- */
-typedef union {
-    struct {
-        /** csi_host_cm_en : R/W; bitpos: [0]; default: 1;
-         *  Configures whether to enable cm output
-         */
-        uint32_t csi_host_cm_en:1;
-        /** csi_host_cm_bypass : R/W; bitpos: [1]; default: 1;
-         *  Configures whether to bypass cm
-         */
-        uint32_t csi_host_cm_bypass:1;
-        /** csi_host_cm_rx : R/W; bitpos: [3:2]; default: 0;
-         *  Configures whether to bypass cm
-         */
-        uint32_t csi_host_cm_rx:2;
-        /** csi_host_cm_rx_rgb_format : R/W; bitpos: [6:4]; default: 0;
-         *  Configures whether to bypass cm
-         */
-        uint32_t csi_host_cm_rx_rgb_format:3;
-        /** csi_host_cm_rx_yuv422_format : R/W; bitpos: [8:7]; default: 0;
-         *  Configures whether to bypass cm
-         */
-        uint32_t csi_host_cm_rx_yuv422_format:2;
-        /** csi_host_cm_tx : R/W; bitpos: [10:9]; default: 0;
-         *  Configures whether to bypass cm
-         */
-        uint32_t csi_host_cm_tx:2;
-        /** csi_host_cm_lane_num : R/W; bitpos: [11]; default: 1;
-         *  Configures lane number that csi used, valid only rgb888 to rgb888. 0: 1-lane, 1:
-         *  2-lane
-         */
-        uint32_t csi_host_cm_lane_num:1;
-        /** csi_host_cm_16bit_swap : R/W; bitpos: [12]; default: 0;
-         *  Configures whether to swap idi32 high and low 16-bit
-         */
-        uint32_t csi_host_cm_16bit_swap:1;
-        /** csi_host_cm_8bit_swap : R/W; bitpos: [13]; default: 0;
-         *  Configures whether to swap idi32 high and low 8-bit
-         */
-        uint32_t csi_host_cm_8bit_swap:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} csi_brg_host_cm_ctrl_reg_t;
-
-/** Type of host_size_ctrl register
- *  CSI HOST color mode convert configuration.
- */
-typedef union {
-    struct {
-        /** csi_host_cm_vnum : R/W; bitpos: [11:0]; default: 0;
-         *  Configures idi32 image size in y-direction, row_num - 1, valid only when
-         *  yuv422_to_yuv420_en = 1
-         */
-        uint32_t csi_host_cm_vnum:12;
-        /** csi_host_cm_hnum : R/W; bitpos: [23:12]; default: 0;
-         *  Configures idi32 image size in x-direction, line_pix_num*bits_per_pix/32 - 1, valid
-         *  only when yuv422_to_yuv420_en = 1
-         */
-        uint32_t csi_host_cm_hnum:12;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} csi_brg_host_size_ctrl_reg_t;
-
-
-typedef struct {
-    volatile csi_brg_clk_en_reg_t clk_en;
-    volatile csi_brg_csi_en_reg_t csi_en;
-    volatile csi_brg_dma_req_cfg_reg_t dma_req_cfg;
-    volatile csi_brg_buf_flow_ctl_reg_t buf_flow_ctl;
-    volatile csi_brg_data_type_cfg_reg_t data_type_cfg;
-    volatile csi_brg_frame_cfg_reg_t frame_cfg;
-    volatile csi_brg_endian_mode_reg_t endian_mode;
-    volatile csi_brg_int_raw_reg_t int_raw;
-    volatile csi_brg_int_clr_reg_t int_clr;
-    volatile csi_brg_int_st_reg_t int_st;
-    volatile csi_brg_int_ena_reg_t int_ena;
-    volatile csi_brg_dma_req_interval_reg_t dma_req_interval;
-    volatile csi_brg_dmablk_size_reg_t dmablk_size;
-    uint32_t reserved_034[3];
-    volatile csi_brg_host_ctrl_reg_t host_ctrl;
-    uint32_t reserved_044;
-    volatile csi_brg_host_cm_ctrl_reg_t host_cm_ctrl;
-    volatile csi_brg_host_size_ctrl_reg_t host_size_ctrl;
-} csi_brg_dev_t;
-
-extern csi_brg_dev_t MIPI_CSI_BRIDGE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(csi_brg_dev_t) == 0x50, "Invalid size of csi_brg_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_struct.h
index 20b393afdbd7..7856dd37406b 100644
--- a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_struct.h
+++ b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_struct.h
@@ -36,7 +36,11 @@ typedef union {
          *  0: disable csi bridge. 1: enable csi bridge.
          */
         uint32_t csi_brg_en:1;
-        uint32_t reserved_1:31;
+        /** csi_brg_rst : R/W; bitpos: [1]; default: 0;
+         *  0: release csi bridge reset. 1: enable csi bridge reset.
+         */
+        uint32_t csi_brg_rst:1;
+        uint32_t reserved_2:30;
     };
     uint32_t val;
 } csi_brg_csi_en_reg_t;
@@ -81,7 +85,11 @@ typedef union {
          *  1: mask dma request when reading frame info. 0: disable mask.
          */
         uint32_t dma_force_rd_status:1;
-        uint32_t reserved_17:15;
+        /** csi_dma_flow_controller : R/W; bitpos: [17]; default: 1;
+         *  0: dma as flow controller. 1: csi_bridge as flow controller
+         */
+        uint32_t csi_dma_flow_controller:1;
+        uint32_t reserved_18:14;
     };
     uint32_t val;
 } csi_brg_dma_req_cfg_reg_t;
@@ -170,11 +178,11 @@ typedef union {
          *  endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy)
          *  when isp is bapassed.
          */
-        uint32_t byte_endian_order:1;    //byte_swap_en
+        uint32_t byte_endian_order:1;
         /** bit_endian_order : R/W; bitpos: [1]; default: 0;
          *  N/A
          */
-        uint32_t bit_endian_order:1;     //reserved
+        uint32_t bit_endian_order:1;
         uint32_t reserved_2:30;
     };
     uint32_t val;
@@ -343,6 +351,75 @@ typedef union {
 } csi_brg_host_ctrl_reg_t;
 
 
+/** Group: csi host color mode control registers. */
+/** Type of host_cm_ctrl register
+ *  CSI HOST color mode convert configuration.
+ */
+typedef union {
+    struct {
+        /** csi_host_cm_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to enable cm output
+         */
+        uint32_t csi_host_cm_en:1;
+        /** csi_host_cm_bypass : R/W; bitpos: [1]; default: 1;
+         *  Configures whether to bypass cm
+         */
+        uint32_t csi_host_cm_bypass:1;
+        /** csi_host_cm_rx : R/W; bitpos: [3:2]; default: 0;
+         *  Configures whether to bypass cm
+         */
+        uint32_t csi_host_cm_rx:2;
+        /** csi_host_cm_rx_rgb_format : R/W; bitpos: [6:4]; default: 0;
+         *  Configures whether to bypass cm
+         */
+        uint32_t csi_host_cm_rx_rgb_format:3;
+        /** csi_host_cm_rx_yuv422_format : R/W; bitpos: [8:7]; default: 0;
+         *  Configures whether to bypass cm
+         */
+        uint32_t csi_host_cm_rx_yuv422_format:2;
+        /** csi_host_cm_tx : R/W; bitpos: [10:9]; default: 0;
+         *  Configures whether to bypass cm
+         */
+        uint32_t csi_host_cm_tx:2;
+        /** csi_host_cm_lane_num : R/W; bitpos: [11]; default: 1;
+         *  Configures lane number that csi used, valid only rgb888 to rgb888. 0: 1-lane, 1:
+         *  2-lane
+         */
+        uint32_t csi_host_cm_lane_num:1;
+        /** csi_host_cm_16bit_swap : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to swap idi32 high and low 16-bit
+         */
+        uint32_t csi_host_cm_16bit_swap:1;
+        /** csi_host_cm_8bit_swap : R/W; bitpos: [13]; default: 0;
+         *  Configures whether to swap idi32 high and low 8-bit
+         */
+        uint32_t csi_host_cm_8bit_swap:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} csi_brg_host_cm_ctrl_reg_t;
+
+/** Type of host_size_ctrl register
+ *  CSI HOST color mode convert configuration.
+ */
+typedef union {
+    struct {
+        /** csi_host_cm_vnum : R/W; bitpos: [11:0]; default: 0;
+         *  Configures idi32 image size in y-direction, row_num - 1, valid only when
+         *  yuv422_to_yuv420_en = 1
+         */
+        uint32_t csi_host_cm_vnum:12;
+        /** csi_host_cm_hnum : R/W; bitpos: [23:12]; default: 0;
+         *  Configures idi32 image size in x-direction, line_pix_num*bits_per_pix/32 - 1, valid
+         *  only when yuv422_to_yuv420_en = 1
+         */
+        uint32_t csi_host_cm_hnum:12;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} csi_brg_host_size_ctrl_reg_t;
+
+
 typedef struct csi_brg_dev_t {
     volatile csi_brg_clk_en_reg_t clk_en;
     volatile csi_brg_csi_en_reg_t csi_en;
@@ -359,12 +436,15 @@ typedef struct csi_brg_dev_t {
     volatile csi_brg_dmablk_size_reg_t dmablk_size;
     uint32_t reserved_034[3];
     volatile csi_brg_host_ctrl_reg_t host_ctrl;
+    uint32_t reserved_044;
+    volatile csi_brg_host_cm_ctrl_reg_t host_cm_ctrl;
+    volatile csi_brg_host_size_ctrl_reg_t host_size_ctrl;
 } csi_brg_dev_t;
 
 extern csi_brg_dev_t MIPI_CSI_BRIDGE;
 
 #ifndef __cplusplus
-_Static_assert(sizeof(csi_brg_dev_t) == 0x44, "Invalid size of csi_brg_dev_t structure");
+_Static_assert(sizeof(csi_brg_dev_t) == 0x50, "Invalid size of csi_brg_dev_t structure");
 #endif
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_eco5_struct.h
deleted file mode 100644
index 1c4ade584f2a..000000000000
--- a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_eco5_struct.h
+++ /dev/null
@@ -1,1883 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Version Register */
-/** Type of version register
- *  NA
- */
-typedef union {
-    struct {
-        /** version : RO; bitpos: [31:0]; default: 825569322;
-         *  NA
-         */
-        uint32_t version:32;
-    };
-    uint32_t val;
-} csi_host_version_reg_t;
-
-
-/** Group: Configuration Registers */
-/** Type of n_lanes register
- *  NA
- */
-typedef union {
-    struct {
-        /** n_lanes : R/W; bitpos: [2:0]; default: 1;
-         *  NA
-         */
-        uint32_t n_lanes:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} csi_host_n_lanes_reg_t;
-
-/** Type of csi2_resetn register
- *  NA
- */
-typedef union {
-    struct {
-        /** csi2_resetn : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t csi2_resetn:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} csi_host_csi2_resetn_reg_t;
-
-/** Type of phy_shutdownz register
- *  NA
- */
-typedef union {
-    struct {
-        /** phy_shutdownz : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t phy_shutdownz:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} csi_host_phy_shutdownz_reg_t;
-
-/** Type of dphy_rstz register
- *  NA
- */
-typedef union {
-    struct {
-        /** dphy_rstz : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t dphy_rstz:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} csi_host_dphy_rstz_reg_t;
-
-/** Type of phy_rx register
- *  NA
- */
-typedef union {
-    struct {
-        /** phy_rxulpsesc_0 : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t phy_rxulpsesc_0:1;
-        /** phy_rxulpsesc_1 : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t phy_rxulpsesc_1:1;
-        uint32_t reserved_2:14;
-        /** phy_rxulpsclknot : RO; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t phy_rxulpsclknot:1;
-        /** phy_rxclkactivehs : RO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t phy_rxclkactivehs:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} csi_host_phy_rx_reg_t;
-
-/** Type of phy_test_ctrl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** phy_testclr : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t phy_testclr:1;
-        /** phy_testclk : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t phy_testclk:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} csi_host_phy_test_ctrl0_reg_t;
-
-/** Type of phy_test_ctrl1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** phy_testdin : R/W; bitpos: [7:0]; default: 0;
-         *  NA
-         */
-        uint32_t phy_testdin:8;
-        /** phy_testdout : RO; bitpos: [15:8]; default: 0;
-         *  NA
-         */
-        uint32_t phy_testdout:8;
-        /** phy_testen : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t phy_testen:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} csi_host_phy_test_ctrl1_reg_t;
-
-/** Type of vc_extension register
- *  NA
- */
-typedef union {
-    struct {
-        /** vcx : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t vcx:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} csi_host_vc_extension_reg_t;
-
-/** Type of phy_cal register
- *  NA
- */
-typedef union {
-    struct {
-        /** rxskewcalhs : RC; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t rxskewcalhs:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} csi_host_phy_cal_reg_t;
-
-/** Type of scrambling register
- *  NA
- */
-typedef union {
-    struct {
-        /** scramble_enable : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t scramble_enable:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} csi_host_scrambling_reg_t;
-
-/** Type of scrambling_seed1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** scramble_seed_lane1 : R/W; bitpos: [15:0]; default: 4104;
-         *  NA
-         */
-        uint32_t scramble_seed_lane1:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_scrambling_seed1_reg_t;
-
-/** Type of scrambling_seed2 register
- *  NA
- */
-typedef union {
-    struct {
-        /** scramble_seed_lane2 : R/W; bitpos: [15:0]; default: 4488;
-         *  NA
-         */
-        uint32_t scramble_seed_lane2:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_scrambling_seed2_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of int_st_main register
- *  NA
- */
-typedef union {
-    struct {
-        /** st_status_int_phy_fatal : RC; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t st_status_int_phy_fatal:1;
-        /** st_status_int_pkt_fatal : RC; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t st_status_int_pkt_fatal:1;
-        /** st_status_int_bndry_frame_fatal : RC; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t st_status_int_bndry_frame_fatal:1;
-        /** st_status_int_seq_frame_fatal : RC; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t st_status_int_seq_frame_fatal:1;
-        /** st_status_int_crc_frame_fatal : RC; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t st_status_int_crc_frame_fatal:1;
-        /** st_status_int_pld_crc_fatal : RC; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t st_status_int_pld_crc_fatal:1;
-        /** st_status_int_data_id : RC; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t st_status_int_data_id:1;
-        /** st_status_int_ecc_corrected : RC; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t st_status_int_ecc_corrected:1;
-        uint32_t reserved_8:8;
-        /** st_status_int_phy : RC; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t st_status_int_phy:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} csi_host_int_st_main_reg_t;
-
-/** Type of int_st_phy_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** st_phy_errsotsynchs_0 : RC; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t st_phy_errsotsynchs_0:1;
-        /** st_phy_errsotsynchs_1 : RC; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t st_phy_errsotsynchs_1:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} csi_host_int_st_phy_fatal_reg_t;
-
-/** Type of int_msk_phy_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** mask_phy_errsotsynchs_0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t mask_phy_errsotsynchs_0:1;
-        /** mask_phy_errsotsynchs_1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t mask_phy_errsotsynchs_1:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} csi_host_int_msk_phy_fatal_reg_t;
-
-/** Type of int_force_phy_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** force_phy_errsotsynchs_0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t force_phy_errsotsynchs_0:1;
-        /** force_phy_errsotsynchs_1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t force_phy_errsotsynchs_1:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} csi_host_int_force_phy_fatal_reg_t;
-
-/** Type of int_st_pkt_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** st_err_ecc_double : RC; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_double:1;
-        /** st_shorter_payload : RC; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t st_shorter_payload:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} csi_host_int_st_pkt_fatal_reg_t;
-
-/** Type of int_msk_pkt_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** mask_err_ecc_double : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_double:1;
-        /** mask_shorter_payload : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t mask_shorter_payload:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} csi_host_int_msk_pkt_fatal_reg_t;
-
-/** Type of int_force_pkt_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** force_err_ecc_double : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_double:1;
-        /** force_shorter_payload : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t force_shorter_payload:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} csi_host_int_force_pkt_fatal_reg_t;
-
-/** Type of int_st_phy register
- *  NA
- */
-typedef union {
-    struct {
-        /** st_phy_errsoths_0 : RC; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t st_phy_errsoths_0:1;
-        /** st_phy_errsoths_1 : RC; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t st_phy_errsoths_1:1;
-        uint32_t reserved_2:14;
-        /** st_phy_erresc_0 : RC; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t st_phy_erresc_0:1;
-        /** st_phy_erresc_1 : RC; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t st_phy_erresc_1:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} csi_host_int_st_phy_reg_t;
-
-/** Type of int_msk_phy register
- *  NA
- */
-typedef union {
-    struct {
-        /** mask_phy_errsoths_0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t mask_phy_errsoths_0:1;
-        /** mask_phy_errsoths_1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t mask_phy_errsoths_1:1;
-        uint32_t reserved_2:14;
-        /** mask_phy_erresc_0 : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t mask_phy_erresc_0:1;
-        /** mask_phy_erresc_1 : R/W; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t mask_phy_erresc_1:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} csi_host_int_msk_phy_reg_t;
-
-/** Type of int_force_phy register
- *  NA
- */
-typedef union {
-    struct {
-        /** force_phy_errsoths_0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t force_phy_errsoths_0:1;
-        /** force_phy_errsoths_1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t force_phy_errsoths_1:1;
-        uint32_t reserved_2:14;
-        /** force_phy_erresc_0 : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t force_phy_erresc_0:1;
-        /** force_phy_erresc_1 : R/W; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t force_phy_erresc_1:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} csi_host_int_force_phy_reg_t;
-
-/** Type of int_st_bndry_frame_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** st_err_f_bndry_match_vc0 : RC; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc0:1;
-        /** st_err_f_bndry_match_vc1 : RC; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc1:1;
-        /** st_err_f_bndry_match_vc2 : RC; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc2:1;
-        /** st_err_f_bndry_match_vc3 : RC; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc3:1;
-        /** st_err_f_bndry_match_vc4 : RC; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc4:1;
-        /** st_err_f_bndry_match_vc5 : RC; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc5:1;
-        /** st_err_f_bndry_match_vc6 : RC; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc6:1;
-        /** st_err_f_bndry_match_vc7 : RC; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc7:1;
-        /** st_err_f_bndry_match_vc8 : RC; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc8:1;
-        /** st_err_f_bndry_match_vc9 : RC; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc9:1;
-        /** st_err_f_bndry_match_vc10 : RC; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc10:1;
-        /** st_err_f_bndry_match_vc11 : RC; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc11:1;
-        /** st_err_f_bndry_match_vc12 : RC; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc12:1;
-        /** st_err_f_bndry_match_vc13 : RC; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc13:1;
-        /** st_err_f_bndry_match_vc14 : RC; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc14:1;
-        /** st_err_f_bndry_match_vc15 : RC; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_bndry_match_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_st_bndry_frame_fatal_reg_t;
-
-/** Type of int_msk_bndry_frame_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** mask_err_f_bndry_match_vc0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc0:1;
-        /** mask_err_f_bndry_match_vc1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc1:1;
-        /** mask_err_f_bndry_match_vc2 : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc2:1;
-        /** mask_err_f_bndry_match_vc3 : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc3:1;
-        /** mask_err_f_bndry_match_vc4 : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc4:1;
-        /** mask_err_f_bndry_match_vc5 : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc5:1;
-        /** mask_err_f_bndry_match_vc6 : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc6:1;
-        /** mask_err_f_bndry_match_vc7 : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc7:1;
-        /** mask_err_f_bndry_match_vc8 : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc8:1;
-        /** mask_err_f_bndry_match_vc9 : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc9:1;
-        /** mask_err_f_bndry_match_vc10 : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc10:1;
-        /** mask_err_f_bndry_match_vc11 : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc11:1;
-        /** mask_err_f_bndry_match_vc12 : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc12:1;
-        /** mask_err_f_bndry_match_vc13 : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc13:1;
-        /** mask_err_f_bndry_match_vc14 : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc14:1;
-        /** mask_err_f_bndry_match_vc15 : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_bndry_match_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_msk_bndry_frame_fatal_reg_t;
-
-/** Type of int_force_bndry_frame_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** force_err_f_bndry_match_vc0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc0:1;
-        /** force_err_f_bndry_match_vc1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc1:1;
-        /** force_err_f_bndry_match_vc2 : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc2:1;
-        /** force_err_f_bndry_match_vc3 : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc3:1;
-        /** force_err_f_bndry_match_vc4 : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc4:1;
-        /** force_err_f_bndry_match_vc5 : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc5:1;
-        /** force_err_f_bndry_match_vc6 : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc6:1;
-        /** force_err_f_bndry_match_vc7 : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc7:1;
-        /** force_err_f_bndry_match_vc8 : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc8:1;
-        /** force_err_f_bndry_match_vc9 : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc9:1;
-        /** force_err_f_bndry_match_vc10 : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc10:1;
-        /** force_err_f_bndry_match_vc11 : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc11:1;
-        /** force_err_f_bndry_match_vc12 : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc12:1;
-        /** force_err_f_bndry_match_vc13 : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc13:1;
-        /** force_err_f_bndry_match_vc14 : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc14:1;
-        /** force_err_f_bndry_match_vc15 : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_bndry_match_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_force_bndry_frame_fatal_reg_t;
-
-/** Type of int_st_seq_frame_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** st_err_f_seq_vc0 : RC; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc0:1;
-        /** st_err_f_seq_vc1 : RC; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc1:1;
-        /** st_err_f_seq_vc2 : RC; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc2:1;
-        /** st_err_f_seq_vc3 : RC; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc3:1;
-        /** st_err_f_seq_vc4 : RC; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc4:1;
-        /** st_err_f_seq_vc5 : RC; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc5:1;
-        /** st_err_f_seq_vc6 : RC; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc6:1;
-        /** st_err_f_seq_vc7 : RC; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc7:1;
-        /** st_err_f_seq_vc8 : RC; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc8:1;
-        /** st_err_f_seq_vc9 : RC; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc9:1;
-        /** st_err_f_seq_vc10 : RC; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc10:1;
-        /** st_err_f_seq_vc11 : RC; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc11:1;
-        /** st_err_f_seq_vc12 : RC; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc12:1;
-        /** st_err_f_seq_vc13 : RC; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc13:1;
-        /** st_err_f_seq_vc14 : RC; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc14:1;
-        /** st_err_f_seq_vc15 : RC; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_f_seq_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_st_seq_frame_fatal_reg_t;
-
-/** Type of int_msk_seq_frame_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** mask_err_f_seq_vc0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc0:1;
-        /** mask_err_f_seq_vc1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc1:1;
-        /** mask_err_f_seq_vc2 : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc2:1;
-        /** mask_err_f_seq_vc3 : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc3:1;
-        /** mask_err_f_seq_vc4 : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc4:1;
-        /** mask_err_f_seq_vc5 : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc5:1;
-        /** mask_err_f_seq_vc6 : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc6:1;
-        /** mask_err_f_seq_vc7 : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc7:1;
-        /** mask_err_f_seq_vc8 : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc8:1;
-        /** mask_err_f_seq_vc9 : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc9:1;
-        /** mask_err_f_seq_vc10 : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc10:1;
-        /** mask_err_f_seq_vc11 : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc11:1;
-        /** mask_err_f_seq_vc12 : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc12:1;
-        /** mask_err_f_seq_vc13 : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc13:1;
-        /** mask_err_f_seq_vc14 : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc14:1;
-        /** mask_err_f_seq_vc15 : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_f_seq_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_msk_seq_frame_fatal_reg_t;
-
-/** Type of int_force_seq_frame_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** force_err_f_seq_vc0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc0:1;
-        /** force_err_f_seq_vc1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc1:1;
-        /** force_err_f_seq_vc2 : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc2:1;
-        /** force_err_f_seq_vc3 : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc3:1;
-        /** force_err_f_seq_vc4 : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc4:1;
-        /** force_err_f_seq_vc5 : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc5:1;
-        /** force_err_f_seq_vc6 : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc6:1;
-        /** force_err_f_seq_vc7 : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc7:1;
-        /** force_err_f_seq_vc8 : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc8:1;
-        /** force_err_f_seq_vc9 : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc9:1;
-        /** force_err_f_seq_vc10 : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc10:1;
-        /** force_err_f_seq_vc11 : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc11:1;
-        /** force_err_f_seq_vc12 : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc12:1;
-        /** force_err_f_seq_vc13 : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc13:1;
-        /** force_err_f_seq_vc14 : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc14:1;
-        /** force_err_f_seq_vc15 : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_f_seq_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_force_seq_frame_fatal_reg_t;
-
-/** Type of int_st_crc_frame_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** st_err_frame_data_vc0 : RC; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc0:1;
-        /** st_err_frame_data_vc1 : RC; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc1:1;
-        /** st_err_frame_data_vc2 : RC; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc2:1;
-        /** st_err_frame_data_vc3 : RC; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc3:1;
-        /** st_err_frame_data_vc4 : RC; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc4:1;
-        /** st_err_frame_data_vc5 : RC; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc5:1;
-        /** st_err_frame_data_vc6 : RC; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc6:1;
-        /** st_err_frame_data_vc7 : RC; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc7:1;
-        /** st_err_frame_data_vc8 : RC; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc8:1;
-        /** st_err_frame_data_vc9 : RC; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc9:1;
-        /** st_err_frame_data_vc10 : RC; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc10:1;
-        /** st_err_frame_data_vc11 : RC; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc11:1;
-        /** st_err_frame_data_vc12 : RC; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc12:1;
-        /** st_err_frame_data_vc13 : RC; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc13:1;
-        /** st_err_frame_data_vc14 : RC; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc14:1;
-        /** st_err_frame_data_vc15 : RC; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_frame_data_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_st_crc_frame_fatal_reg_t;
-
-/** Type of int_msk_crc_frame_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** mask_err_frame_data_vc0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc0:1;
-        /** mask_err_frame_data_vc1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc1:1;
-        /** mask_err_frame_data_vc2 : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc2:1;
-        /** mask_err_frame_data_vc3 : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc3:1;
-        /** mask_err_frame_data_vc4 : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc4:1;
-        /** mask_err_frame_data_vc5 : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc5:1;
-        /** mask_err_frame_data_vc6 : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc6:1;
-        /** mask_err_frame_data_vc7 : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc7:1;
-        /** mask_err_frame_data_vc8 : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc8:1;
-        /** mask_err_frame_data_vc9 : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc9:1;
-        /** mask_err_frame_data_vc10 : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc10:1;
-        /** mask_err_frame_data_vc11 : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc11:1;
-        /** mask_err_frame_data_vc12 : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc12:1;
-        /** mask_err_frame_data_vc13 : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc13:1;
-        /** mask_err_frame_data_vc14 : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc14:1;
-        /** mask_err_frame_data_vc15 : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_frame_data_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_msk_crc_frame_fatal_reg_t;
-
-/** Type of int_force_crc_frame_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** force_err_frame_data_vc0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc0:1;
-        /** force_err_frame_data_vc1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc1:1;
-        /** force_err_frame_data_vc2 : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc2:1;
-        /** force_err_frame_data_vc3 : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc3:1;
-        /** force_err_frame_data_vc4 : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc4:1;
-        /** force_err_frame_data_vc5 : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc5:1;
-        /** force_err_frame_data_vc6 : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc6:1;
-        /** force_err_frame_data_vc7 : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc7:1;
-        /** force_err_frame_data_vc8 : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc8:1;
-        /** force_err_frame_data_vc9 : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc9:1;
-        /** force_err_frame_data_vc10 : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc10:1;
-        /** force_err_frame_data_vc11 : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc11:1;
-        /** force_err_frame_data_vc12 : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc12:1;
-        /** force_err_frame_data_vc13 : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc13:1;
-        /** force_err_frame_data_vc14 : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc14:1;
-        /** force_err_frame_data_vc15 : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_frame_data_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_force_crc_frame_fatal_reg_t;
-
-/** Type of int_st_pld_crc_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** st_err_crc_vc0 : RC; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc0:1;
-        /** st_err_crc_vc1 : RC; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc1:1;
-        /** st_err_crc_vc2 : RC; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc2:1;
-        /** st_err_crc_vc3 : RC; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc3:1;
-        /** st_err_crc_vc4 : RC; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc4:1;
-        /** st_err_crc_vc5 : RC; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc5:1;
-        /** st_err_crc_vc6 : RC; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc6:1;
-        /** st_err_crc_vc7 : RC; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc7:1;
-        /** st_err_crc_vc8 : RC; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc8:1;
-        /** st_err_crc_vc9 : RC; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc9:1;
-        /** st_err_crc_vc10 : RC; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc10:1;
-        /** st_err_crc_vc11 : RC; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc11:1;
-        /** st_err_crc_vc12 : RC; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc12:1;
-        /** st_err_crc_vc13 : RC; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc13:1;
-        /** st_err_crc_vc14 : RC; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc14:1;
-        /** st_err_crc_vc15 : RC; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_crc_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_st_pld_crc_fatal_reg_t;
-
-/** Type of int_msk_pld_crc_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** mask_err_crc_vc0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc0:1;
-        /** mask_err_crc_vc1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc1:1;
-        /** mask_err_crc_vc2 : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc2:1;
-        /** mask_err_crc_vc3 : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc3:1;
-        /** mask_err_crc_vc4 : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc4:1;
-        /** mask_err_crc_vc5 : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc5:1;
-        /** mask_err_crc_vc6 : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc6:1;
-        /** mask_err_crc_vc7 : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc7:1;
-        /** mask_err_crc_vc8 : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc8:1;
-        /** mask_err_crc_vc9 : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc9:1;
-        /** mask_err_crc_vc10 : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc10:1;
-        /** mask_err_crc_vc11 : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc11:1;
-        /** mask_err_crc_vc12 : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc12:1;
-        /** mask_err_crc_vc13 : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc13:1;
-        /** mask_err_crc_vc14 : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc14:1;
-        /** mask_err_crc_vc15 : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_crc_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_msk_pld_crc_fatal_reg_t;
-
-/** Type of int_force_pld_crc_fatal register
- *  NA
- */
-typedef union {
-    struct {
-        /** force_err_crc_vc0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc0:1;
-        /** force_err_crc_vc1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc1:1;
-        /** force_err_crc_vc2 : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc2:1;
-        /** force_err_crc_vc3 : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc3:1;
-        /** force_err_crc_vc4 : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc4:1;
-        /** force_err_crc_vc5 : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc5:1;
-        /** force_err_crc_vc6 : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc6:1;
-        /** force_err_crc_vc7 : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc7:1;
-        /** force_err_crc_vc8 : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc8:1;
-        /** force_err_crc_vc9 : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc9:1;
-        /** force_err_crc_vc10 : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc10:1;
-        /** force_err_crc_vc11 : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc11:1;
-        /** force_err_crc_vc12 : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc12:1;
-        /** force_err_crc_vc13 : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc13:1;
-        /** force_err_crc_vc14 : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc14:1;
-        /** force_err_crc_vc15 : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_crc_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_force_pld_crc_fatal_reg_t;
-
-/** Type of int_st_data_id register
- *  NA
- */
-typedef union {
-    struct {
-        /** st_err_id_vc0 : RC; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc0:1;
-        /** st_err_id_vc1 : RC; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc1:1;
-        /** st_err_id_vc2 : RC; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc2:1;
-        /** st_err_id_vc3 : RC; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc3:1;
-        /** st_err_id_vc4 : RC; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc4:1;
-        /** st_err_id_vc5 : RC; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc5:1;
-        /** st_err_id_vc6 : RC; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc6:1;
-        /** st_err_id_vc7 : RC; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc7:1;
-        /** st_err_id_vc8 : RC; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc8:1;
-        /** st_err_id_vc9 : RC; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc9:1;
-        /** st_err_id_vc10 : RC; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc10:1;
-        /** st_err_id_vc11 : RC; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc11:1;
-        /** st_err_id_vc12 : RC; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc12:1;
-        /** st_err_id_vc13 : RC; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc13:1;
-        /** st_err_id_vc14 : RC; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc14:1;
-        /** st_err_id_vc15 : RC; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_id_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_st_data_id_reg_t;
-
-/** Type of int_msk_data_id register
- *  NA
- */
-typedef union {
-    struct {
-        /** mask_err_id_vc0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc0:1;
-        /** mask_err_id_vc1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc1:1;
-        /** mask_err_id_vc2 : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc2:1;
-        /** mask_err_id_vc3 : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc3:1;
-        /** mask_err_id_vc4 : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc4:1;
-        /** mask_err_id_vc5 : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc5:1;
-        /** mask_err_id_vc6 : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc6:1;
-        /** mask_err_id_vc7 : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc7:1;
-        /** mask_err_id_vc8 : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc8:1;
-        /** mask_err_id_vc9 : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc9:1;
-        /** mask_err_id_vc10 : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc10:1;
-        /** mask_err_id_vc11 : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc11:1;
-        /** mask_err_id_vc12 : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc12:1;
-        /** mask_err_id_vc13 : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc13:1;
-        /** mask_err_id_vc14 : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc14:1;
-        /** mask_err_id_vc15 : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_id_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_msk_data_id_reg_t;
-
-/** Type of int_force_data_id register
- *  NA
- */
-typedef union {
-    struct {
-        /** force_err_id_vc0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc0:1;
-        /** force_err_id_vc1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc1:1;
-        /** force_err_id_vc2 : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc2:1;
-        /** force_err_id_vc3 : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc3:1;
-        /** force_err_id_vc4 : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc4:1;
-        /** force_err_id_vc5 : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc5:1;
-        /** force_err_id_vc6 : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc6:1;
-        /** force_err_id_vc7 : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc7:1;
-        /** force_err_id_vc8 : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc8:1;
-        /** force_err_id_vc9 : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc9:1;
-        /** force_err_id_vc10 : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc10:1;
-        /** force_err_id_vc11 : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc11:1;
-        /** force_err_id_vc12 : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc12:1;
-        /** force_err_id_vc13 : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc13:1;
-        /** force_err_id_vc14 : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc14:1;
-        /** force_err_id_vc15 : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_id_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_force_data_id_reg_t;
-
-/** Type of int_st_ecc_corrected register
- *  NA
- */
-typedef union {
-    struct {
-        /** st_err_ecc_corrected_vc0 : RC; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc0:1;
-        /** st_err_ecc_corrected_vc1 : RC; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc1:1;
-        /** st_err_ecc_corrected_vc2 : RC; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc2:1;
-        /** st_err_ecc_corrected_vc3 : RC; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc3:1;
-        /** st_err_ecc_corrected_vc4 : RC; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc4:1;
-        /** st_err_ecc_corrected_vc5 : RC; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc5:1;
-        /** st_err_ecc_corrected_vc6 : RC; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc6:1;
-        /** st_err_ecc_corrected_vc7 : RC; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc7:1;
-        /** st_err_ecc_corrected_vc8 : RC; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc8:1;
-        /** st_err_ecc_corrected_vc9 : RC; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc9:1;
-        /** st_err_ecc_corrected_vc10 : RC; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc10:1;
-        /** st_err_ecc_corrected_vc11 : RC; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc11:1;
-        /** st_err_ecc_corrected_vc12 : RC; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc12:1;
-        /** st_err_ecc_corrected_vc13 : RC; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc13:1;
-        /** st_err_ecc_corrected_vc14 : RC; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc14:1;
-        /** st_err_ecc_corrected_vc15 : RC; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t st_err_ecc_corrected_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_st_ecc_corrected_reg_t;
-
-/** Type of int_msk_ecc_corrected register
- *  NA
- */
-typedef union {
-    struct {
-        /** mask_err_ecc_corrected_vc0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc0:1;
-        /** mask_err_ecc_corrected_vc1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc1:1;
-        /** mask_err_ecc_corrected_vc2 : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc2:1;
-        /** mask_err_ecc_corrected_vc3 : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc3:1;
-        /** mask_err_ecc_corrected_vc4 : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc4:1;
-        /** mask_err_ecc_corrected_vc5 : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc5:1;
-        /** mask_err_ecc_corrected_vc6 : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc6:1;
-        /** mask_err_ecc_corrected_vc7 : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc7:1;
-        /** mask_err_ecc_corrected_vc8 : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc8:1;
-        /** mask_err_ecc_corrected_vc9 : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc9:1;
-        /** mask_err_ecc_corrected_vc10 : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc10:1;
-        /** mask_err_ecc_corrected_vc11 : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc11:1;
-        /** mask_err_ecc_corrected_vc12 : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc12:1;
-        /** mask_err_ecc_corrected_vc13 : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc13:1;
-        /** mask_err_ecc_corrected_vc14 : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc14:1;
-        /** mask_err_ecc_corrected_vc15 : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t mask_err_ecc_corrected_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_msk_ecc_corrected_reg_t;
-
-/** Type of int_force_ecc_corrected register
- *  NA
- */
-typedef union {
-    struct {
-        /** force_err_ecc_corrected_vc0 : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc0:1;
-        /** force_err_ecc_corrected_vc1 : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc1:1;
-        /** force_err_ecc_corrected_vc2 : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc2:1;
-        /** force_err_ecc_corrected_vc3 : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc3:1;
-        /** force_err_ecc_corrected_vc4 : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc4:1;
-        /** force_err_ecc_corrected_vc5 : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc5:1;
-        /** force_err_ecc_corrected_vc6 : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc6:1;
-        /** force_err_ecc_corrected_vc7 : R/W; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc7:1;
-        /** force_err_ecc_corrected_vc8 : R/W; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc8:1;
-        /** force_err_ecc_corrected_vc9 : R/W; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc9:1;
-        /** force_err_ecc_corrected_vc10 : R/W; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc10:1;
-        /** force_err_ecc_corrected_vc11 : R/W; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc11:1;
-        /** force_err_ecc_corrected_vc12 : R/W; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc12:1;
-        /** force_err_ecc_corrected_vc13 : R/W; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc13:1;
-        /** force_err_ecc_corrected_vc14 : R/W; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc14:1;
-        /** force_err_ecc_corrected_vc15 : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t force_err_ecc_corrected_vc15:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} csi_host_int_force_ecc_corrected_reg_t;
-
-
-/** Group: Status Registers */
-/** Type of phy_stopstate register
- *  NA
- */
-typedef union {
-    struct {
-        /** phy_stopstatedata_0 : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t phy_stopstatedata_0:1;
-        /** phy_stopstatedata_1 : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t phy_stopstatedata_1:1;
-        uint32_t reserved_2:14;
-        /** phy_stopstateclk : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t phy_stopstateclk:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} csi_host_phy_stopstate_reg_t;
-
-
-typedef struct {
-    volatile csi_host_version_reg_t version;
-    volatile csi_host_n_lanes_reg_t n_lanes;
-    volatile csi_host_csi2_resetn_reg_t csi2_resetn;
-    volatile csi_host_int_st_main_reg_t int_st_main;
-    uint32_t reserved_010[12];
-    volatile csi_host_phy_shutdownz_reg_t phy_shutdownz;
-    volatile csi_host_dphy_rstz_reg_t dphy_rstz;
-    volatile csi_host_phy_rx_reg_t phy_rx;
-    volatile csi_host_phy_stopstate_reg_t phy_stopstate;
-    volatile csi_host_phy_test_ctrl0_reg_t phy_test_ctrl0;
-    volatile csi_host_phy_test_ctrl1_reg_t phy_test_ctrl1;
-    uint32_t reserved_058[28];
-    volatile csi_host_vc_extension_reg_t vc_extension;
-    volatile csi_host_phy_cal_reg_t phy_cal;
-    uint32_t reserved_0d0[4];
-    volatile csi_host_int_st_phy_fatal_reg_t int_st_phy_fatal;
-    volatile csi_host_int_msk_phy_fatal_reg_t int_msk_phy_fatal;
-    volatile csi_host_int_force_phy_fatal_reg_t int_force_phy_fatal;
-    uint32_t reserved_0ec;
-    volatile csi_host_int_st_pkt_fatal_reg_t int_st_pkt_fatal;
-    volatile csi_host_int_msk_pkt_fatal_reg_t int_msk_pkt_fatal;
-    volatile csi_host_int_force_pkt_fatal_reg_t int_force_pkt_fatal;
-    uint32_t reserved_0fc[5];
-    volatile csi_host_int_st_phy_reg_t int_st_phy;
-    volatile csi_host_int_msk_phy_reg_t int_msk_phy;
-    volatile csi_host_int_force_phy_reg_t int_force_phy;
-    uint32_t reserved_11c[89];
-    volatile csi_host_int_st_bndry_frame_fatal_reg_t int_st_bndry_frame_fatal;
-    volatile csi_host_int_msk_bndry_frame_fatal_reg_t int_msk_bndry_frame_fatal;
-    volatile csi_host_int_force_bndry_frame_fatal_reg_t int_force_bndry_frame_fatal;
-    uint32_t reserved_28c;
-    volatile csi_host_int_st_seq_frame_fatal_reg_t int_st_seq_frame_fatal;
-    volatile csi_host_int_msk_seq_frame_fatal_reg_t int_msk_seq_frame_fatal;
-    volatile csi_host_int_force_seq_frame_fatal_reg_t int_force_seq_frame_fatal;
-    uint32_t reserved_29c;
-    volatile csi_host_int_st_crc_frame_fatal_reg_t int_st_crc_frame_fatal;
-    volatile csi_host_int_msk_crc_frame_fatal_reg_t int_msk_crc_frame_fatal;
-    volatile csi_host_int_force_crc_frame_fatal_reg_t int_force_crc_frame_fatal;
-    uint32_t reserved_2ac;
-    volatile csi_host_int_st_pld_crc_fatal_reg_t int_st_pld_crc_fatal;
-    volatile csi_host_int_msk_pld_crc_fatal_reg_t int_msk_pld_crc_fatal;
-    volatile csi_host_int_force_pld_crc_fatal_reg_t int_force_pld_crc_fatal;
-    uint32_t reserved_2bc;
-    volatile csi_host_int_st_data_id_reg_t int_st_data_id;
-    volatile csi_host_int_msk_data_id_reg_t int_msk_data_id;
-    volatile csi_host_int_force_data_id_reg_t int_force_data_id;
-    uint32_t reserved_2cc;
-    volatile csi_host_int_st_ecc_corrected_reg_t int_st_ecc_corrected;
-    volatile csi_host_int_msk_ecc_corrected_reg_t int_msk_ecc_corrected;
-    volatile csi_host_int_force_ecc_corrected_reg_t int_force_ecc_corrected;
-    uint32_t reserved_2dc[9];
-    volatile csi_host_scrambling_reg_t scrambling;
-    volatile csi_host_scrambling_seed1_reg_t scrambling_seed1;
-    volatile csi_host_scrambling_seed2_reg_t scrambling_seed2;
-} csi_host_dev_t;
-
-extern csi_host_dev_t MIPI_CSI_HOST;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(csi_host_dev_t) == 0x30c, "Invalid size of csi_host_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_eco5_struct.h
deleted file mode 100644
index 1263f22ba535..000000000000
--- a/components/soc/esp32p4/register/hw_ver3/soc/spi_eco5_struct.h
+++ /dev/null
@@ -1,1623 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: User-defined control registers */
-/** Type of cmd register
- *  Command control register
- */
-typedef union {
-    struct {
-        /** conf_bitlen : R/W; bitpos: [17:0]; default: 0;
-         *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
-         */
-        uint32_t conf_bitlen:18;
-        uint32_t reserved_18:5;
-        /** update : WT; bitpos: [23]; default: 0;
-         *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
-         *  clock domain, which is only used in SPI master mode.
-         */
-        uint32_t update:1;
-        /** usr : R/W/SC; bitpos: [24]; default: 0;
-         *  User define command enable.  An operation will be triggered when the bit is set.
-         *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
-         *  changed by CONF_buf.
-         */
-        uint32_t usr:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} spi_cmd_reg_t;
-
-/** Type of addr register
- *  Address value register
- */
-typedef union {
-    struct {
-        /** usr_addr_value : R/W; bitpos: [31:0]; default: 0;
-         *  Address to slave. Can be configured in CONF state.
-         */
-        uint32_t usr_addr_value:32;
-    };
-    uint32_t val;
-} spi_addr_reg_t;
-
-/** Type of user register
- *  SPI USER control register
- */
-typedef union {
-    struct {
-        /** doutdin : R/W; bitpos: [0]; default: 0;
-         *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
-         *  configured in CONF state.
-         */
-        uint32_t doutdin:1;
-        uint32_t reserved_1:2;
-        /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0;
-         *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
-         *  Can be configured in CONF state.
-         */
-        uint32_t qpi_mode:1;
-        /** opi_mode : R/W; bitpos: [4]; default: 0;
-         *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
-         *  Can be configured in CONF state.
-         */
-        uint32_t opi_mode:1;
-        /** tsck_i_edge : R/W; bitpos: [5]; default: 0;
-         *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
-         *  spi_ck_i. 1:tsck = !spi_ck_i.
-         */
-        uint32_t tsck_i_edge:1;
-        /** cs_hold : R/W; bitpos: [6]; default: 1;
-         *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cs_hold:1;
-        /** cs_setup : R/W; bitpos: [7]; default: 1;
-         *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cs_setup:1;
-        /** rsck_i_edge : R/W; bitpos: [8]; default: 0;
-         *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
-         *  !spi_ck_i. 1:rsck = spi_ck_i.
-         */
-        uint32_t rsck_i_edge:1;
-        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
-         *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
-         *  be configured in CONF state.
-         */
-        uint32_t ck_out_edge:1;
-        uint32_t reserved_10:2;
-        /** fwrite_dual : R/W; bitpos: [12]; default: 0;
-         *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_dual:1;
-        /** fwrite_quad : R/W; bitpos: [13]; default: 0;
-         *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_quad:1;
-        /** fwrite_oct : R/W; bitpos: [14]; default: 0;
-         *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_oct:1;
-        /** usr_conf_nxt : R/W; bitpos: [15]; default: 0;
-         *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
-         *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
-         *  not seg-trans mode. Can be configured in CONF state.
-         */
-        uint32_t usr_conf_nxt:1;
-        uint32_t reserved_16:1;
-        /** sio : R/W; bitpos: [17]; default: 0;
-         *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
-         *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
-         */
-        uint32_t sio:1;
-        uint32_t reserved_18:6;
-        /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
-         *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
-         *  disable. Can be configured in CONF state.
-         */
-        uint32_t usr_miso_highpart:1;
-        /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
-         *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
-         *  0: disable.  Can be configured in CONF state.
-         */
-        uint32_t usr_mosi_highpart:1;
-        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
-         *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
-         *  CONF state.
-         */
-        uint32_t usr_dummy_idle:1;
-        /** usr_mosi : R/W; bitpos: [27]; default: 0;
-         *  This bit enable the write-data phase of an operation. Can be configured in CONF
-         *  state.
-         */
-        uint32_t usr_mosi:1;
-        /** usr_miso : R/W; bitpos: [28]; default: 0;
-         *  This bit enable the read-data phase of an operation. Can be configured in CONF
-         *  state.
-         */
-        uint32_t usr_miso:1;
-        /** usr_dummy : R/W; bitpos: [29]; default: 0;
-         *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
-         */
-        uint32_t usr_dummy:1;
-        /** usr_addr : R/W; bitpos: [30]; default: 0;
-         *  This bit enable the address phase of an operation. Can be configured in CONF state.
-         */
-        uint32_t usr_addr:1;
-        /** usr_command : R/W; bitpos: [31]; default: 1;
-         *  This bit enable the command phase of an operation. Can be configured in CONF state.
-         */
-        uint32_t usr_command:1;
-    };
-    uint32_t val;
-} spi_user_reg_t;
-
-/** Type of user1 register
- *  SPI USER control register 1
- */
-typedef union {
-    struct {
-        /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7;
-         *  The length in spi_clk cycles of dummy phase. The register value shall be
-         *  (cycle_num-1). Can be configured in CONF state.
-         */
-        uint32_t usr_dummy_cyclelen:8;
-        uint32_t reserved_8:8;
-        /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1;
-         *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
-         *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
-         *  GP-SPI master FD/HD-mode.
-         */
-        uint32_t mst_wfull_err_end_en:1;
-        /** cs_setup_time : R/W; bitpos: [21:17]; default: 0;
-         *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
-         *  bit. Can be configured in CONF state.
-         */
-        uint32_t cs_setup_time:5;
-        /** cs_hold_time : R/W; bitpos: [26:22]; default: 1;
-         *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
-         *  Can be configured in CONF state.
-         */
-        uint32_t cs_hold_time:5;
-        /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23;
-         *  The length in bits of address phase. The register value shall be (bit_num-1). Can
-         *  be configured in CONF state.
-         */
-        uint32_t usr_addr_bitlen:5;
-    };
-    uint32_t val;
-} spi_user1_reg_t;
-
-/** Type of user2 register
- *  SPI USER control register 2
- */
-typedef union {
-    struct {
-        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
-         *  The value of  command. Can be configured in CONF state.
-         */
-        uint32_t usr_command_value:16;
-        uint32_t reserved_16:11;
-        /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1;
-         *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
-         *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
-         *  is valid in GP-SPI master FD/HD-mode.
-         */
-        uint32_t mst_rempty_err_end_en:1;
-        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
-         *  The length in bits of command phase. The register value shall be (bit_num-1). Can
-         *  be configured in CONF state.
-         */
-        uint32_t usr_command_bitlen:4;
-    };
-    uint32_t val;
-} spi_user2_reg_t;
-
-
-/** Group: Control and configuration registers */
-/** Type of ctrl register
- *  SPI control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** dummy_out : R/W; bitpos: [3]; default: 0;
-         *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
-         *  the FSPI bus signals are output. Can be configured in CONF state.
-         */
-        uint32_t dummy_out:1;
-        uint32_t reserved_4:1;
-        /** faddr_dual : R/W; bitpos: [5]; default: 0;
-         *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t faddr_dual:1;
-        /** faddr_quad : R/W; bitpos: [6]; default: 0;
-         *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t faddr_quad:1;
-        /** faddr_oct : R/W; bitpos: [7]; default: 0;
-         *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t faddr_oct:1;
-        /** fcmd_dual : R/W; bitpos: [8]; default: 0;
-         *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fcmd_dual:1;
-        /** fcmd_quad : R/W; bitpos: [9]; default: 0;
-         *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fcmd_quad:1;
-        /** fcmd_oct : R/W; bitpos: [10]; default: 0;
-         *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fcmd_oct:1;
-        uint32_t reserved_11:3;
-        /** fread_dual : R/W; bitpos: [14]; default: 0;
-         *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
-         *  be configured in CONF state.
-         */
-        uint32_t fread_dual:1;
-        /** fread_quad : R/W; bitpos: [15]; default: 0;
-         *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
-         *  be configured in CONF state.
-         */
-        uint32_t fread_quad:1;
-        /** fread_oct : R/W; bitpos: [16]; default: 0;
-         *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
-         *  be configured in CONF state.
-         */
-        uint32_t fread_oct:1;
-        uint32_t reserved_17:1;
-        /** q_pol : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
-         *  CONF state.
-         */
-        uint32_t q_pol:1;
-        /** d_pol : R/W; bitpos: [19]; default: 1;
-         *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
-         *  CONF state.
-         */
-        uint32_t d_pol:1;
-        /** hold_pol : R/W; bitpos: [20]; default: 1;
-         *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
-         *  configured in CONF state.
-         */
-        uint32_t hold_pol:1;
-        /** wp_pol : R/W; bitpos: [21]; default: 1;
-         *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
-         *  be configured in CONF state.
-         */
-        uint32_t wp_pol:1;
-        uint32_t reserved_22:1;
-        /** rd_bit_order : R/W; bitpos: [24:23]; default: 0;
-         *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
-         *  state.
-         */
-        uint32_t rd_bit_order:2;
-        /** wr_bit_order : R/W; bitpos: [26:25]; default: 0;
-         *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
-         *  configured in CONF state.
-         */
-        uint32_t wr_bit_order:2;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} spi_ctrl_reg_t;
-
-/** Type of ms_dlen register
- *  SPI data bit length control register
- */
-typedef union {
-    struct {
-        /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0;
-         *  The value of these bits is the configured SPI transmission data bit length in
-         *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
-         *  the configured bit length in slave mode DMA RX controlled transfer. The register
-         *  value shall be (bit_num-1). Can be configured in CONF state.
-         */
-        uint32_t ms_data_bitlen:18;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} spi_ms_dlen_reg_t;
-
-/** Type of misc register
- *  SPI misc register
- */
-typedef union {
-    struct {
-        /** cs0_dis : R/W; bitpos: [0]; default: 0;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs0_dis:1;
-        /** cs1_dis : R/W; bitpos: [1]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs1_dis:1;
-        /** cs2_dis : R/W; bitpos: [2]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs2_dis:1;
-        /** cs3_dis : R/W; bitpos: [3]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs3_dis:1;
-        /** cs4_dis : R/W; bitpos: [4]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs4_dis:1;
-        /** cs5_dis : R/W; bitpos: [5]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs5_dis:1;
-        /** ck_dis : R/W; bitpos: [6]; default: 0;
-         *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
-         */
-        uint32_t ck_dis:1;
-        /** master_cs_pol : R/W; bitpos: [12:7]; default: 0;
-         *  In the master mode the bits are the polarity of spi cs line, the value is
-         *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
-         */
-        uint32_t master_cs_pol:6;
-        uint32_t reserved_13:3;
-        /** clk_data_dtr_en : R/W; bitpos: [16]; default: 0;
-         *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
-         *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
-         */
-        uint32_t clk_data_dtr_en:1;
-        /** data_dtr_en : R/W; bitpos: [17]; default: 0;
-         *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
-         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
-         *  Can be configured in CONF state.
-         */
-        uint32_t data_dtr_en:1;
-        /** addr_dtr_en : R/W; bitpos: [18]; default: 0;
-         *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
-         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
-         *  configured in CONF state.
-         */
-        uint32_t addr_dtr_en:1;
-        /** cmd_dtr_en : R/W; bitpos: [19]; default: 0;
-         *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
-         *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cmd_dtr_en:1;
-        uint32_t reserved_20:3;
-        /** slave_cs_pol : R/W; bitpos: [23]; default: 0;
-         *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
-         *  CONF state.
-         */
-        uint32_t slave_cs_pol:1;
-        /** dqs_idle_edge : R/W; bitpos: [24]; default: 0;
-         *  The default value of spi_dqs. Can be configured in CONF state.
-         */
-        uint32_t dqs_idle_edge:1;
-        uint32_t reserved_25:4;
-        /** ck_idle_edge : R/W; bitpos: [29]; default: 0;
-         *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
-         *  configured in CONF state.
-         */
-        uint32_t ck_idle_edge:1;
-        /** cs_keep_active : R/W; bitpos: [30]; default: 0;
-         *  spi cs line keep low when the bit is set. Can be configured in CONF state.
-         */
-        uint32_t cs_keep_active:1;
-        /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0;
-         *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
-         *  spi quad input swap disable. Can be configured in CONF state.
-         */
-        uint32_t quad_din_pin_swap:1;
-    };
-    uint32_t val;
-} spi_misc_reg_t;
-
-/** Type of dma_conf register
- *  SPI DMA control register
- */
-typedef union {
-    struct {
-        /** dma_outfifo_empty : RO; bitpos: [0]; default: 1;
-         *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
-         *  DMA TX FIFO is ready for sending data.
-         */
-        uint32_t dma_outfifo_empty:1;
-        /** dma_infifo_full : RO; bitpos: [1]; default: 1;
-         *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
-         *  0: DMA RX FIFO is ready for receiving data.
-         */
-        uint32_t dma_infifo_full:1;
-        uint32_t reserved_2:16;
-        /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0;
-         *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
-         */
-        uint32_t dma_slv_seg_trans_en:1;
-        /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0;
-         *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
-         *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
-         */
-        uint32_t slv_rx_seg_trans_clr_en:1;
-        /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0;
-         *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
-         *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
-         */
-        uint32_t slv_tx_seg_trans_clr_en:1;
-        /** rx_eof_en : R/W; bitpos: [21]; default: 0;
-         *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
-         *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
-         *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
-         *  spi_dma_seg_trans_done in seg-trans.
-         */
-        uint32_t rx_eof_en:1;
-        uint32_t reserved_22:5;
-        /** dma_rx_ena : R/W; bitpos: [27]; default: 0;
-         *  Set this bit to enable SPI DMA controlled receive data mode.
-         */
-        uint32_t dma_rx_ena:1;
-        /** dma_tx_ena : R/W; bitpos: [28]; default: 0;
-         *  Set this bit to enable SPI DMA controlled send data mode.
-         */
-        uint32_t dma_tx_ena:1;
-        /** rx_afifo_rst : WT; bitpos: [29]; default: 0;
-         *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
-         *  slave mode transfer.
-         */
-        uint32_t rx_afifo_rst:1;
-        /** buf_afifo_rst : WT; bitpos: [30]; default: 0;
-         *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
-         *  controlled mode transfer and master mode transfer.
-         */
-        uint32_t buf_afifo_rst:1;
-        /** dma_afifo_rst : WT; bitpos: [31]; default: 0;
-         *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
-         *  controlled mode transfer.
-         */
-        uint32_t dma_afifo_rst:1;
-    };
-    uint32_t val;
-} spi_dma_conf_reg_t;
-
-/** Type of slave register
- *  SPI slave control register
- */
-typedef union {
-    struct {
-        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
-         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
-         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
-         *  SPI clock is always on. Can be configured in CONF state.
-         */
-        uint32_t clk_mode:2;
-        /** clk_mode_13 : R/W; bitpos: [2]; default: 0;
-         *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
-         *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
-         */
-        uint32_t clk_mode_13:1;
-        /** rsck_data_out : R/W; bitpos: [3]; default: 0;
-         *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
-         *  0: output data at tsck posedge
-         */
-        uint32_t rsck_data_out:1;
-        uint32_t reserved_4:4;
-        /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
-         *  DMA controlled mode(Rd_DMA). 0: others
-         */
-        uint32_t slv_rddma_bitlen_en:1;
-        /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
-         *  in DMA controlled mode(Wr_DMA). 0: others
-         */
-        uint32_t slv_wrdma_bitlen_en:1;
-        /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
-         *  CPU controlled mode(Rd_BUF). 0: others
-         */
-        uint32_t slv_rdbuf_bitlen_en:1;
-        /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
-         *  in CPU controlled mode(Wr_BUF). 0: others
-         */
-        uint32_t slv_wrbuf_bitlen_en:1;
-        /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0;
-         *  Represents the effective bit of the last received data byte in SPI slave FD and HD
-         *  mode.
-         */
-        uint32_t slv_last_byte_strb:8;
-        uint32_t reserved_20:2;
-        /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10;
-         *  The magic value of BM table in master DMA seg-trans.
-         */
-        uint32_t dma_seg_magic_value:4;
-        /** slave_mode : R/W; bitpos: [26]; default: 0;
-         *  Set SPI work mode. 1: slave mode 0: master mode.
-         */
-        uint32_t slave_mode:1;
-        /** soft_reset : WT; bitpos: [27]; default: 0;
-         *  Software reset enable, reset the spi clock line cs line and data lines. Can be
-         *  configured in CONF state.
-         */
-        uint32_t soft_reset:1;
-        /** usr_conf : R/W; bitpos: [28]; default: 0;
-         *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
-         *  will start. 0: This is not seg-trans mode.
-         */
-        uint32_t usr_conf:1;
-        /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0;
-         *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
-         *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
-         *  transfer.
-         */
-        uint32_t mst_fd_wait_dma_tx_data:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} spi_slave_reg_t;
-
-/** Type of slave1 register
- *  SPI slave control register 1
- */
-typedef union {
-    struct {
-        /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0;
-         *  The transferred data bit length in SPI slave FD and HD mode.
-         */
-        uint32_t slv_data_bitlen:18;
-        /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0;
-         *  In the slave mode it is the value of command.
-         */
-        uint32_t slv_last_command:8;
-        /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0;
-         *  In the slave mode it is the value of address.
-         */
-        uint32_t slv_last_addr:6;
-    };
-    uint32_t val;
-} spi_slave1_reg_t;
-
-
-/** Group: Clock control registers */
-/** Type of clock register
- *  SPI clock control register
- */
-typedef union {
-    struct {
-        /** clkcnt_l : R/W; bitpos: [5:0]; default: 3;
-         *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
-         *  0. Can be configured in CONF state.
-         */
-        uint32_t clkcnt_l:6;
-        /** clkcnt_h : R/W; bitpos: [11:6]; default: 1;
-         *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
-         *  must be 0. Can be configured in CONF state.
-         */
-        uint32_t clkcnt_h:6;
-        /** clkcnt_n : R/W; bitpos: [17:12]; default: 3;
-         *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
-         *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
-         */
-        uint32_t clkcnt_n:6;
-        /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0;
-         *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
-         */
-        uint32_t clkdiv_pre:4;
-        uint32_t reserved_22:8;
-        /** clk_edge_sel : R/W; bitpos: [30]; default: 0;
-         *  Configures use standard clock sampling edge or delay the sampling edge by half a
-         *  cycle in master transfer.
-         *  0: clock sampling edge is delayed by half a cycle.
-         *  1: clock sampling edge is standard.
-         *  Can be configured in CONF state.
-         */
-        uint32_t clk_edge_sel:1;
-        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
-         *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
-         *  clock. Can be configured in CONF state.
-         */
-        uint32_t clk_equ_sysclk:1;
-    };
-    uint32_t val;
-} spi_clock_reg_t;
-
-/** Type of clk_gate register
- *  SPI module clock and register clock control
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable clk gate
-         */
-        uint32_t clk_en:1;
-        /** mst_clk_active : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to power on the SPI module clock.
-         */
-        uint32_t mst_clk_active:1;
-        /** mst_clk_sel : R/W; bitpos: [2]; default: 0;
-         *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
-         *  0: XTAL CLK.
-         */
-        uint32_t mst_clk_sel:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} spi_clk_gate_reg_t;
-
-
-/** Group: Timing registers */
-/** Type of din_mode register
- *  SPI input delay mode configuration
- */
-typedef union {
-    struct {
-        /** din0_mode : R/W; bitpos: [1:0]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din0_mode:2;
-        /** din1_mode : R/W; bitpos: [3:2]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din1_mode:2;
-        /** din2_mode : R/W; bitpos: [5:4]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din2_mode:2;
-        /** din3_mode : R/W; bitpos: [7:6]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din3_mode:2;
-        /** din4_mode : R/W; bitpos: [9:8]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din4_mode:2;
-        /** din5_mode : R/W; bitpos: [11:10]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din5_mode:2;
-        /** din6_mode : R/W; bitpos: [13:12]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din6_mode:2;
-        /** din7_mode : R/W; bitpos: [15:14]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din7_mode:2;
-        /** timing_hclk_active : R/W; bitpos: [16]; default: 0;
-         *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
-         *  state.
-         */
-        uint32_t timing_hclk_active:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} spi_din_mode_reg_t;
-
-/** Type of din_num register
- *  SPI input delay number configuration
- */
-typedef union {
-    struct {
-        /** din0_num : R/W; bitpos: [1:0]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din0_num:2;
-        /** din1_num : R/W; bitpos: [3:2]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din1_num:2;
-        /** din2_num : R/W; bitpos: [5:4]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din2_num:2;
-        /** din3_num : R/W; bitpos: [7:6]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din3_num:2;
-        /** din4_num : R/W; bitpos: [9:8]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din4_num:2;
-        /** din5_num : R/W; bitpos: [11:10]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din5_num:2;
-        /** din6_num : R/W; bitpos: [13:12]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din6_num:2;
-        /** din7_num : R/W; bitpos: [15:14]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din7_num:2;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} spi_din_num_reg_t;
-
-/** Type of dout_mode register
- *  SPI output delay mode configuration
- */
-typedef union {
-    struct {
-        /** dout0_mode : R/W; bitpos: [0]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout0_mode:1;
-        /** dout1_mode : R/W; bitpos: [1]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout1_mode:1;
-        /** dout2_mode : R/W; bitpos: [2]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout2_mode:1;
-        /** dout3_mode : R/W; bitpos: [3]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout3_mode:1;
-        /** dout4_mode : R/W; bitpos: [4]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout4_mode:1;
-        /** dout5_mode : R/W; bitpos: [5]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout5_mode:1;
-        /** dout6_mode : R/W; bitpos: [6]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout6_mode:1;
-        /** dout7_mode : R/W; bitpos: [7]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout7_mode:1;
-        /** d_dqs_mode : R/W; bitpos: [8]; default: 0;
-         *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
-         *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t d_dqs_mode:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} spi_dout_mode_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of dma_int_ena register
- *  SPI interrupt enable register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err_int_ena:1;
-        /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err_int_ena:1;
-        /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The enable bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi_int_ena:1;
-        /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi_int_ena:1;
-        /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7_int_ena:1;
-        /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The enable bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8_int_ena:1;
-        /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The enable bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9_int_ena:1;
-        /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The enable bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda_int_ena:1;
-        /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done_int_ena:1;
-        /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done_int_ena:1;
-        /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done_int_ena:1;
-        /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done_int_ena:1;
-        /** trans_done_int_ena : R/W; bitpos: [12]; default: 0;
-         *  The enable bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done_int_ena:1;
-        /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done_int_ena:1;
-        /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0;
-         *  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err_int_ena:1;
-        /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0;
-         *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err_int_ena:1;
-        /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0;
-         *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err_int_ena:1;
-        /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0;
-         *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_ena:1;
-        /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0;
-         *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_ena:1;
-        /** app2_int_ena : R/W; bitpos: [19]; default: 0;
-         *  The enable bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2_int_ena:1;
-        /** app1_int_ena : R/W; bitpos: [20]; default: 0;
-         *  The enable bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1_int_ena:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_ena_reg_t;
-
-/** Type of dma_int_clr register
- *  SPI interrupt clear register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err_int_clr:1;
-        /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err_int_clr:1;
-        /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0;
-         *  The clear bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi_int_clr:1;
-        /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0;
-         *  The clear bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi_int_clr:1;
-        /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0;
-         *  The clear bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7_int_clr:1;
-        /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0;
-         *  The clear bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8_int_clr:1;
-        /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0;
-         *  The clear bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9_int_clr:1;
-        /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0;
-         *  The clear bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda_int_clr:1;
-        /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0;
-         *  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done_int_clr:1;
-        /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0;
-         *  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done_int_clr:1;
-        /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0;
-         *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done_int_clr:1;
-        /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0;
-         *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done_int_clr:1;
-        /** trans_done_int_clr : WT; bitpos: [12]; default: 0;
-         *  The clear bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done_int_clr:1;
-        /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0;
-         *  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done_int_clr:1;
-        /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0;
-         *  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err_int_clr:1;
-        /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0;
-         *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err_int_clr:1;
-        /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0;
-         *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err_int_clr:1;
-        /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0;
-         *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_clr:1;
-        /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0;
-         *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_clr:1;
-        /** app2_int_clr : WT; bitpos: [19]; default: 0;
-         *  The clear bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2_int_clr:1;
-        /** app1_int_clr : WT; bitpos: [20]; default: 0;
-         *  The clear bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1_int_clr:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_clr_reg_t;
-
-/** Type of dma_int_raw register
- *  SPI interrupt raw register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
-         *  receive data.  0: Others.
-         */
-        uint32_t dma_infifo_full_err_int_raw:1;
-        /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
-         *  master mode and send out all 0 in slave mode.  0: Others.
-         */
-        uint32_t dma_outfifo_empty_err_int_raw:1;
-        /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
-         *  is ended. 0: Others.
-         */
-        uint32_t slv_ex_qpi_int_raw:1;
-        /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
-         *  is ended. 0: Others.
-         */
-        uint32_t slv_en_qpi_int_raw:1;
-        /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmd7_int_raw:1;
-        /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmd8_int_raw:1;
-        /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmd9_int_raw:1;
-        /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmda_int_raw:1;
-        /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_rd_dma_done_int_raw:1;
-        /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_wr_dma_done_int_raw:1;
-        /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_rd_buf_done_int_raw:1;
-        /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_wr_buf_done_int_raw:1;
-        /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
-         *  ended. 0: others.
-         */
-        uint32_t trans_done_int_raw:1;
-        /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
-         *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
-         *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
-         *  is not ended or not occurred.
-         */
-        uint32_t dma_seg_trans_done_int_raw:1;
-        /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
-         *  is error in the DMA seg-conf-trans. 0: others.
-         */
-        uint32_t seg_magic_err_int_raw:1;
-        /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
-         *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
-         *  bigger than 63. 0: Others.
-         */
-        uint32_t slv_buf_addr_err_int_raw:1;
-        /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
-         *  current SPI slave HD mode transmission is not supported. 0: Others.
-         */
-        uint32_t slv_cmd_err_int_raw:1;
-        /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
-         *  write-full error when SPI inputs data in master mode. 0: Others.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_raw:1;
-        /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
-         *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_raw:1;
-        /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
-         */
-        uint32_t app2_int_raw:1;
-        /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
-         */
-        uint32_t app1_int_raw:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_raw_reg_t;
-
-/** Type of dma_int_st register
- *  SPI interrupt status register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0;
-         *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err_int_st:1;
-        /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0;
-         *  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err_int_st:1;
-        /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0;
-         *  The status bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi_int_st:1;
-        /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0;
-         *  The status bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi_int_st:1;
-        /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0;
-         *  The status bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7_int_st:1;
-        /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0;
-         *  The status bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8_int_st:1;
-        /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0;
-         *  The status bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9_int_st:1;
-        /** slv_cmda_int_st : RO; bitpos: [7]; default: 0;
-         *  The status bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda_int_st:1;
-        /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0;
-         *  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done_int_st:1;
-        /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0;
-         *  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done_int_st:1;
-        /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0;
-         *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done_int_st:1;
-        /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0;
-         *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done_int_st:1;
-        /** trans_done_int_st : RO; bitpos: [12]; default: 0;
-         *  The status bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done_int_st:1;
-        /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0;
-         *  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done_int_st:1;
-        /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0;
-         *  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err_int_st:1;
-        /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0;
-         *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err_int_st:1;
-        /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0;
-         *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err_int_st:1;
-        /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0;
-         *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_st:1;
-        /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0;
-         *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_st:1;
-        /** app2_int_st : RO; bitpos: [19]; default: 0;
-         *  The status bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2_int_st:1;
-        /** app1_int_st : RO; bitpos: [20]; default: 0;
-         *  The status bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1_int_st:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_st_reg_t;
-
-/** Type of dma_int_set register
- *  SPI interrupt software set register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0;
-         *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err_int_set:1;
-        /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0;
-         *  The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err_int_set:1;
-        /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0;
-         *  The software set bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi_int_set:1;
-        /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0;
-         *  The software set bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi_int_set:1;
-        /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0;
-         *  The software set bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7_int_set:1;
-        /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0;
-         *  The software set bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8_int_set:1;
-        /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0;
-         *  The software set bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9_int_set:1;
-        /** slv_cmda_int_set : WT; bitpos: [7]; default: 0;
-         *  The software set bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda_int_set:1;
-        /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0;
-         *  The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done_int_set:1;
-        /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0;
-         *  The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done_int_set:1;
-        /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0;
-         *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done_int_set:1;
-        /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0;
-         *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done_int_set:1;
-        /** trans_done_int_set : WT; bitpos: [12]; default: 0;
-         *  The software set bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done_int_set:1;
-        /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0;
-         *  The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done_int_set:1;
-        /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0;
-         *  The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err_int_set:1;
-        /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0;
-         *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err_int_set:1;
-        /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0;
-         *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err_int_set:1;
-        /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0;
-         *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_set:1;
-        /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0;
-         *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_set:1;
-        /** app2_int_set : WT; bitpos: [19]; default: 0;
-         *  The software set bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2_int_set:1;
-        /** app1_int_set : WT; bitpos: [20]; default: 0;
-         *  The software set bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1_int_set:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_set_reg_t;
-
-
-/** Group: CPU-controlled data buffer */
-/** Type of w0 register
- *  SPI CPU-controlled buffer0
- */
-typedef union {
-    struct {
-        /** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf0:32;
-    };
-    uint32_t val;
-} spi_w0_reg_t;
-
-/** Type of w1 register
- *  SPI CPU-controlled buffer1
- */
-typedef union {
-    struct {
-        /** buf1 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf1:32;
-    };
-    uint32_t val;
-} spi_w1_reg_t;
-
-/** Type of w2 register
- *  SPI CPU-controlled buffer2
- */
-typedef union {
-    struct {
-        /** buf2 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf2:32;
-    };
-    uint32_t val;
-} spi_w2_reg_t;
-
-/** Type of w3 register
- *  SPI CPU-controlled buffer3
- */
-typedef union {
-    struct {
-        /** buf3 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf3:32;
-    };
-    uint32_t val;
-} spi_w3_reg_t;
-
-/** Type of w4 register
- *  SPI CPU-controlled buffer4
- */
-typedef union {
-    struct {
-        /** buf4 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf4:32;
-    };
-    uint32_t val;
-} spi_w4_reg_t;
-
-/** Type of w5 register
- *  SPI CPU-controlled buffer5
- */
-typedef union {
-    struct {
-        /** buf5 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf5:32;
-    };
-    uint32_t val;
-} spi_w5_reg_t;
-
-/** Type of w6 register
- *  SPI CPU-controlled buffer6
- */
-typedef union {
-    struct {
-        /** buf6 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf6:32;
-    };
-    uint32_t val;
-} spi_w6_reg_t;
-
-/** Type of w7 register
- *  SPI CPU-controlled buffer7
- */
-typedef union {
-    struct {
-        /** buf7 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf7:32;
-    };
-    uint32_t val;
-} spi_w7_reg_t;
-
-/** Type of w8 register
- *  SPI CPU-controlled buffer8
- */
-typedef union {
-    struct {
-        /** buf8 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf8:32;
-    };
-    uint32_t val;
-} spi_w8_reg_t;
-
-/** Type of w9 register
- *  SPI CPU-controlled buffer9
- */
-typedef union {
-    struct {
-        /** buf9 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf9:32;
-    };
-    uint32_t val;
-} spi_w9_reg_t;
-
-/** Type of w10 register
- *  SPI CPU-controlled buffer10
- */
-typedef union {
-    struct {
-        /** buf10 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf10:32;
-    };
-    uint32_t val;
-} spi_w10_reg_t;
-
-/** Type of w11 register
- *  SPI CPU-controlled buffer11
- */
-typedef union {
-    struct {
-        /** buf11 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf11:32;
-    };
-    uint32_t val;
-} spi_w11_reg_t;
-
-/** Type of w12 register
- *  SPI CPU-controlled buffer12
- */
-typedef union {
-    struct {
-        /** buf12 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf12:32;
-    };
-    uint32_t val;
-} spi_w12_reg_t;
-
-/** Type of w13 register
- *  SPI CPU-controlled buffer13
- */
-typedef union {
-    struct {
-        /** buf13 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf13:32;
-    };
-    uint32_t val;
-} spi_w13_reg_t;
-
-/** Type of w14 register
- *  SPI CPU-controlled buffer14
- */
-typedef union {
-    struct {
-        /** buf14 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf14:32;
-    };
-    uint32_t val;
-} spi_w14_reg_t;
-
-/** Type of w15 register
- *  SPI CPU-controlled buffer15
- */
-typedef union {
-    struct {
-        /** buf15 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf15:32;
-    };
-    uint32_t val;
-} spi_w15_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 37761424;
-         *  SPI register version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} spi_date_reg_t;
-
-
-typedef struct {
-    volatile spi_cmd_reg_t cmd;
-    volatile spi_addr_reg_t addr;
-    volatile spi_ctrl_reg_t ctrl;
-    volatile spi_clock_reg_t clock;
-    volatile spi_user_reg_t user;
-    volatile spi_user1_reg_t user1;
-    volatile spi_user2_reg_t user2;
-    volatile spi_ms_dlen_reg_t ms_dlen;
-    volatile spi_misc_reg_t misc;
-    volatile spi_din_mode_reg_t din_mode;
-    volatile spi_din_num_reg_t din_num;
-    volatile spi_dout_mode_reg_t dout_mode;
-    volatile spi_dma_conf_reg_t dma_conf;
-    volatile spi_dma_int_ena_reg_t dma_int_ena;
-    volatile spi_dma_int_clr_reg_t dma_int_clr;
-    volatile spi_dma_int_raw_reg_t dma_int_raw;
-    volatile spi_dma_int_st_reg_t dma_int_st;
-    volatile spi_dma_int_set_reg_t dma_int_set;
-    uint32_t reserved_048[20];
-    volatile spi_w0_reg_t w0;
-    volatile spi_w1_reg_t w1;
-    volatile spi_w2_reg_t w2;
-    volatile spi_w3_reg_t w3;
-    volatile spi_w4_reg_t w4;
-    volatile spi_w5_reg_t w5;
-    volatile spi_w6_reg_t w6;
-    volatile spi_w7_reg_t w7;
-    volatile spi_w8_reg_t w8;
-    volatile spi_w9_reg_t w9;
-    volatile spi_w10_reg_t w10;
-    volatile spi_w11_reg_t w11;
-    volatile spi_w12_reg_t w12;
-    volatile spi_w13_reg_t w13;
-    volatile spi_w14_reg_t w14;
-    volatile spi_w15_reg_t w15;
-    uint32_t reserved_0d8[2];
-    volatile spi_slave_reg_t slave;
-    volatile spi_slave1_reg_t slave1;
-    volatile spi_clk_gate_reg_t clk_gate;
-    uint32_t reserved_0ec;
-    volatile spi_date_reg_t date;
-} spi_dev_t;
-
-extern spi_dev_t GPSPI2;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/spi_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/spi_struct.h
index 64da6d07f3b5..99be51bc31fc 100644
--- a/components/soc/esp32p4/register/hw_ver3/soc/spi_struct.h
+++ b/components/soc/esp32p4/register/hw_ver3/soc/spi_struct.h
@@ -627,7 +627,15 @@ typedef union {
          *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
          */
         uint32_t clkdiv_pre:4;
-        uint32_t reserved_22:9;
+        uint32_t reserved_22:8;
+        /** clk_edge_sel : R/W; bitpos: [30]; default: 0;
+         *  Configures use standard clock sampling edge or delay the sampling edge by half a
+         *  cycle in master transfer.
+         *  0: clock sampling edge is delayed by half a cycle.
+         *  1: clock sampling edge is standard.
+         *  Can be configured in CONF state.
+         */
+        uint32_t clk_edge_sel:1;
         /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
          *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
          *  clock. Can be configured in CONF state.
@@ -975,7 +983,7 @@ typedef union {
  */
 typedef union {
     struct {
-        /** date : R/W; bitpos: [27:0]; default: 35680770;
+        /** date : R/W; bitpos: [27:0]; default: 37761424;
          *  SPI register version.
          */
         uint32_t date:28;
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/twai_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/twai_eco5_struct.h
deleted file mode 100644
index 429a1a71458b..000000000000
--- a/components/soc/esp32p4/register/hw_ver3/soc/twai_eco5_struct.h
+++ /dev/null
@@ -1,799 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Registers */
-/** Type of mode register
- *  TWAI mode register.
- */
-typedef union {
-    struct {
-        /** reset_mode : R/W; bitpos: [0]; default: 1;
-         *  1: reset, detection of a set reset mode bit results in aborting the current
-         *  transmission/reception of a message and entering the reset mode. 0: normal, on the
-         *  '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
-         *  operating mode.
-         */
-        uint32_t reset_mode:1;
-        /** listen_only_mode : R/W; bitpos: [1]; default: 0;
-         *  1: listen only, in this mode the TWAI controller would give no acknowledge to the
-         *  TWAI-bus, even if a message is received successfully. The error counters are
-         *  stopped at the current value. 0: normal.
-         */
-        uint32_t listen_only_mode:1;
-        /** self_test_mode : R/W; bitpos: [2]; default: 0;
-         *  1: self test, in this mode a full node test is possible without any other active
-         *  node on the bus using the self reception request command. The TWAI controller will
-         *  perform a successful transmission, even if there is no acknowledge received. 0:
-         *  normal, an acknowledge is required for successful transmission.
-         */
-        uint32_t self_test_mode:1;
-        /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0;
-         *  1:single, the single acceptance filter option is enabled (one filter with the
-         *  length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
-         *  (two filters, each with the length of 16 bit are active).
-         */
-        uint32_t acceptance_filter_mode:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} twai_mode_reg_t;
-
-/** Type of cmd register
- *  TWAI command register.
- */
-typedef union {
-    struct {
-        /** tx_request : WO; bitpos: [0]; default: 0;
-         *  1: present, a message shall be transmitted. 0: absent
-         */
-        uint32_t tx_request:1;
-        /** abort_tx : WO; bitpos: [1]; default: 0;
-         *  1: present, if not already in progress, a pending transmission request is
-         *  cancelled. 0: absent
-         */
-        uint32_t abort_tx:1;
-        /** release_buffer : WO; bitpos: [2]; default: 0;
-         *  1: released, the receive buffer, representing the message memory space in the
-         *  RXFIFO is released. 0: no action
-         */
-        uint32_t release_buffer:1;
-        /** clear_data_overrun : WO; bitpos: [3]; default: 0;
-         *  1: clear, the data overrun status bit is cleared. 0: no action.
-         */
-        uint32_t clear_data_overrun:1;
-        /** self_rx_request : WO; bitpos: [4]; default: 0;
-         *  1: present, a message shall be transmitted and received simultaneously. 0: absent.
-         */
-        uint32_t self_rx_request:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} twai_cmd_reg_t;
-
-/** Type of bus_timing_0 register
- *  Bit timing configuration register 0.
- */
-typedef union {
-    struct {
-        /** baud_presc : R/W; bitpos: [13:0]; default: 0;
-         *  The period of the TWAI system clock is programmable and determines the individual
-         *  bit timing. Software has R/W permission in reset mode and RO permission in
-         *  operation mode.
-         */
-        uint32_t baud_presc:14;
-        /** sync_jump_width : R/W; bitpos: [15:14]; default: 0;
-         *  The synchronization jump width defines the maximum number of clock cycles a bit
-         *  period may be shortened or lengthened. Software has R/W permission in reset mode
-         *  and RO in operation mode.
-         */
-        uint32_t sync_jump_width:2;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} twai_bus_timing_0_reg_t;
-
-/** Type of bus_timing_1 register
- *  Bit timing configuration register 1.
- */
-typedef union {
-    struct {
-        /** time_segment1 : R/W; bitpos: [3:0]; default: 0;
-         *  The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
-         *  reset mode and RO in operation mode.
-         */
-        uint32_t time_segment1:4;
-        /** time_segment2 : R/W; bitpos: [6:4]; default: 0;
-         *  The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
-         *  reset mode and RO in operation mode.
-         */
-        uint32_t time_segment2:3;
-        /** time_sampling : R/W; bitpos: [7]; default: 0;
-         *  1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
-         *  Software has R/W permission in reset mode and RO in operation mode.
-         */
-        uint32_t time_sampling:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_bus_timing_1_reg_t;
-
-/** Type of err_warning_limit register
- *  TWAI error threshold configuration register.
- */
-typedef union {
-    struct {
-        /** err_warning_limit : R/W; bitpos: [7:0]; default: 96;
-         *  The threshold that trigger error warning interrupt when this interrupt is enabled.
-         *  Software has R/W permission in reset mode and RO in operation mode.
-         */
-        uint32_t err_warning_limit:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_err_warning_limit_reg_t;
-
-/** Type of clock_divider register
- *  Clock divider register.
- */
-typedef union {
-    struct {
-        /** cd : R/W; bitpos: [7:0]; default: 0;
-         *  These bits are used to define the frequency at the external CLKOUT pin.
-         */
-        uint32_t cd:8;
-        /** clock_off : R/W; bitpos: [8]; default: 0;
-         *  1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
-         *  R/W permission in reset mode and RO in operation mode.
-         */
-        uint32_t clock_off:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} twai_clock_divider_reg_t;
-
-/** Type of sw_standby_cfg register
- *  Software configure standby pin directly.
- */
-typedef union {
-    struct {
-        /** sw_standby_en : R/W; bitpos: [0]; default: 0;
-         *  Enable standby pin.
-         */
-        uint32_t sw_standby_en:1;
-        /** sw_standby_clr : R/W; bitpos: [1]; default: 1;
-         *  Clear standby pin.
-         */
-        uint32_t sw_standby_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} twai_sw_standby_cfg_reg_t;
-
-/** Type of hw_cfg register
- *  Hardware configure standby pin.
- */
-typedef union {
-    struct {
-        /** hw_standby_en : R/W; bitpos: [0]; default: 0;
-         *  Enable function that hardware control standby pin.
-         */
-        uint32_t hw_standby_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} twai_hw_cfg_reg_t;
-
-/** Type of hw_standby_cnt register
- *  Configure standby counter.
- */
-typedef union {
-    struct {
-        /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1;
-         *  Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
-         *  is enabled.
-         */
-        uint32_t standby_wait_cnt:32;
-    };
-    uint32_t val;
-} twai_hw_standby_cnt_reg_t;
-
-/** Type of idle_intr_cnt register
- *  Configure idle interrupt counter.
- */
-typedef union {
-    struct {
-        /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1;
-         *  Configure the number of cycles before triggering idle interrupt.
-         */
-        uint32_t idle_intr_cnt:32;
-    };
-    uint32_t val;
-} twai_idle_intr_cnt_reg_t;
-
-/** Type of eco_cfg register
- *  ECO configuration register.
- */
-typedef union {
-    struct {
-        /** rdn_ena : R/W; bitpos: [0]; default: 0;
-         *  Enable eco module.
-         */
-        uint32_t rdn_ena:1;
-        /** rdn_result : RO; bitpos: [1]; default: 1;
-         *  Output of eco module.
-         */
-        uint32_t rdn_result:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} twai_eco_cfg_reg_t;
-
-
-/** Group: Status Registers */
-/** Type of status register
- *  TWAI status register.
- */
-typedef union {
-    struct {
-        /** status_receive_buffer : RO; bitpos: [0]; default: 0;
-         *  1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
-         *  message is available
-         */
-        uint32_t status_receive_buffer:1;
-        /** status_overrun : RO; bitpos: [1]; default: 0;
-         *  1: overrun, a message was lost because there was not enough space for that message
-         *  in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
-         *  overrun command was given
-         */
-        uint32_t status_overrun:1;
-        /** status_transmit_buffer : RO; bitpos: [2]; default: 0;
-         *  1: released, the CPU may write a message into the transmit buffer. 0: locked, the
-         *  CPU cannot access the transmit buffer, a message is either waiting for transmission
-         *  or is in the process of being transmitted
-         */
-        uint32_t status_transmit_buffer:1;
-        /** status_transmission_complete : RO; bitpos: [3]; default: 0;
-         *  1: complete, last requested transmission has been successfully completed. 0:
-         *  incomplete, previously requested transmission is not yet completed
-         */
-        uint32_t status_transmission_complete:1;
-        /** status_receive : RO; bitpos: [4]; default: 0;
-         *  1: receive, the TWAI controller is receiving a message. 0: idle
-         */
-        uint32_t status_receive:1;
-        /** status_transmit : RO; bitpos: [5]; default: 0;
-         *  1: transmit, the TWAI controller is transmitting a message. 0: idle
-         */
-        uint32_t status_transmit:1;
-        /** status_err : RO; bitpos: [6]; default: 0;
-         *  1: error, at least one of the error counters has reached or exceeded the CPU
-         *  warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
-         *  counters are below the warning limit
-         */
-        uint32_t status_err:1;
-        /** status_node_bus_off : RO; bitpos: [7]; default: 0;
-         *  1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
-         *  TWAI controller is involved in bus activities
-         */
-        uint32_t status_node_bus_off:1;
-        /** status_miss : RO; bitpos: [8]; default: 0;
-         *  1: current message is destroyed because of FIFO overflow.
-         */
-        uint32_t status_miss:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} twai_status_reg_t;
-
-/** Type of arb_lost_cap register
- *  TWAI arbiter lost capture register.
- */
-typedef union {
-    struct {
-        /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0;
-         *  This register contains information about the bit position of losing arbitration.
-         */
-        uint32_t arbitration_lost_capture:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} twai_arb_lost_cap_reg_t;
-
-/** Type of err_code_cap register
- *  TWAI error info capture register.
- */
-typedef union {
-    struct {
-        /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0;
-         *  This register contains information about the location of errors on the bus.
-         */
-        uint32_t err_capture_code_segment:5;
-        /** err_capture_code_direction : RO; bitpos: [5]; default: 0;
-         *  1: RX, error occurred during reception. 0: TX, error occurred during transmission.
-         */
-        uint32_t err_capture_code_direction:1;
-        /** err_capture_code_type : RO; bitpos: [7:6]; default: 0;
-         *  00: bit error. 01: form error. 10:stuff error. 11:other type of error.
-         */
-        uint32_t err_capture_code_type:2;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_err_code_cap_reg_t;
-
-/** Type of rx_err_cnt register
- *  Rx error counter register.
- */
-typedef union {
-    struct {
-        /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0;
-         *  The RX error counter register reflects the current value of the transmit error
-         *  counter. Software has R/W permission in reset mode and RO in operation mode.
-         */
-        uint32_t rx_err_cnt:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_rx_err_cnt_reg_t;
-
-/** Type of tx_err_cnt register
- *  Tx error counter register.
- */
-typedef union {
-    struct {
-        /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0;
-         *  The TX error counter register reflects the current value of the transmit error
-         *  counter. Software has R/W permission in reset mode and RO in operation mode.
-         */
-        uint32_t tx_err_cnt:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_tx_err_cnt_reg_t;
-
-/** Type of rx_message_counter register
- *  Received message counter register.
- */
-typedef union {
-    struct {
-        /** rx_message_counter : RO; bitpos: [6:0]; default: 0;
-         *  Reflects the number of messages available within the RXFIFO. The value is
-         *  incremented with each receive event and decremented by the release receive buffer
-         *  command.
-         */
-        uint32_t rx_message_counter:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} twai_rx_message_counter_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of interrupt register
- *  Interrupt signals' register.
- */
-typedef union {
-    struct {
-        /** receive_int_st : RO; bitpos: [0]; default: 0;
-         *  1: this bit is set while the receive FIFO is not empty and the RIE bit is set
-         *  within the interrupt enable register. 0: reset
-         */
-        uint32_t receive_int_st:1;
-        /** transmit_int_st : RO; bitpos: [1]; default: 0;
-         *  1: this bit is set whenever the transmit buffer status changes from '0-to-1'
-         *  (released) and the TIE bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t transmit_int_st:1;
-        /** err_warning_int_st : RO; bitpos: [2]; default: 0;
-         *  1: this bit is set on every change (set and clear) of either the error status or
-         *  bus status bits and the EIE bit is set within the interrupt enable register. 0:
-         *  reset
-         */
-        uint32_t err_warning_int_st:1;
-        /** data_overrun_int_st : RO; bitpos: [3]; default: 0;
-         *  1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
-         *  DOIE bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t data_overrun_int_st:1;
-        /** ts_counter_ovfl_int_st : RO; bitpos: [4]; default: 0;
-         *  1: this bit is set then the timestamp counter reaches the maximum value and
-         *  overflow.
-         */
-        uint32_t ts_counter_ovfl_int_st:1;
-        /** err_passive_int_st : RO; bitpos: [5]; default: 0;
-         *  1: this bit is set whenever the TWAI controller has reached the error passive
-         *  status (at least one error counter exceeds the protocol-defined level of 127) or if
-         *  the TWAI controller is in the error passive status and enters the error active
-         *  status again and the EPIE bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t err_passive_int_st:1;
-        /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0;
-         *  1: this bit is set when the TWAI controller lost the arbitration and becomes a
-         *  receiver and the ALIE bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t arbitration_lost_int_st:1;
-        /** bus_err_int_st : RO; bitpos: [7]; default: 0;
-         *  1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
-         *  the BEIE bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t bus_err_int_st:1;
-        /** idle_int_st : RO; bitpos: [8]; default: 0;
-         *  1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
-         *  this interrupt enable bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t idle_int_st:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} twai_interrupt_reg_t;
-
-/** Type of interrupt_enable register
- *  Interrupt enable register.
- */
-typedef union {
-    struct {
-        /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0;
-         *  1: enabled, when the receive buffer status is 'full' the TWAI controller requests
-         *  the respective interrupt. 0: disable
-         */
-        uint32_t ext_receive_int_ena:1;
-        /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0;
-         *  1: enabled, when a message has been successfully transmitted or the transmit buffer
-         *  is accessible again (e.g. after an abort transmission command), the TWAI controller
-         *  requests the respective interrupt. 0: disable
-         */
-        uint32_t ext_transmit_int_ena:1;
-        /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0;
-         *  1: enabled, if the error or bus status change (see status register. Table 14), the
-         *  TWAI controllerrequests the respective interrupt. 0: disable
-         */
-        uint32_t ext_err_warning_int_ena:1;
-        /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0;
-         *  1: enabled, if the data overrun status bit is set (see status register. Table 14),
-         *  the TWAI controllerrequests the respective interrupt. 0: disable
-         */
-        uint32_t ext_data_overrun_int_ena:1;
-        /** ts_counter_ovfl_int_ena : R/W; bitpos: [4]; default: 0;
-         *  enable the timestamp counter overflow interrupt request.
-         */
-        uint32_t ts_counter_ovfl_int_ena:1;
-        /** err_passive_int_ena : R/W; bitpos: [5]; default: 0;
-         *  1: enabled, if the error status of the TWAI controller changes from error active to
-         *  error passive or vice versa, the respective interrupt is requested. 0: disable
-         */
-        uint32_t err_passive_int_ena:1;
-        /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0;
-         *  1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
-         *  is requested. 0: disable
-         */
-        uint32_t arbitration_lost_int_ena:1;
-        /** bus_err_int_ena : R/W; bitpos: [7]; default: 0;
-         *  1: enabled, if an bus error has been detected, the TWAI controller requests the
-         *  respective interrupt. 0: disable
-         */
-        uint32_t bus_err_int_ena:1;
-        /** idle_int_ena : RO; bitpos: [8]; default: 0;
-         *  1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
-         *  respective interrupt. 0: disable
-         */
-        uint32_t idle_int_ena:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} twai_interrupt_enable_reg_t;
-
-
-/** Group: Data Registers */
-/** Type of data_0 register
- *  Data register 0.
- */
-typedef union {
-    struct {
-        /** data_0 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance code register 0 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 0 and when
-         *  software initiate read operation, it is rx data register 0.
-         */
-        uint32_t data_0:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_0_reg_t;
-
-/** Type of data_1 register
- *  Data register 1.
- */
-typedef union {
-    struct {
-        /** data_1 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance code register 1 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 1 and when
-         *  software initiate read operation, it is rx data register 1.
-         */
-        uint32_t data_1:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_1_reg_t;
-
-/** Type of data_2 register
- *  Data register 2.
- */
-typedef union {
-    struct {
-        /** data_2 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance code register 2 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 2 and when
-         *  software initiate read operation, it is rx data register 2.
-         */
-        uint32_t data_2:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_2_reg_t;
-
-/** Type of data_3 register
- *  Data register 3.
- */
-typedef union {
-    struct {
-        /** data_3 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance code register 3 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 3 and when
-         *  software initiate read operation, it is rx data register 3.
-         */
-        uint32_t data_3:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_3_reg_t;
-
-/** Type of data_4 register
- *  Data register 4.
- */
-typedef union {
-    struct {
-        /** data_4 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 4 and when
-         *  software initiate read operation, it is rx data register 4.
-         */
-        uint32_t data_4:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_4_reg_t;
-
-/** Type of data_5 register
- *  Data register 5.
- */
-typedef union {
-    struct {
-        /** data_5 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 5 and when
-         *  software initiate read operation, it is rx data register 5.
-         */
-        uint32_t data_5:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_5_reg_t;
-
-/** Type of data_6 register
- *  Data register 6.
- */
-typedef union {
-    struct {
-        /** data_6 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 6 and when
-         *  software initiate read operation, it is rx data register 6.
-         */
-        uint32_t data_6:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_6_reg_t;
-
-/** Type of data_7 register
- *  Data register 7.
- */
-typedef union {
-    struct {
-        /** data_7 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 7 and when
-         *  software initiate read operation, it is rx data register 7.
-         */
-        uint32_t data_7:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_7_reg_t;
-
-/** Type of data_8 register
- *  Data register 8.
- */
-typedef union {
-    struct {
-        /** data_8 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, reserved with RO. In operation mode, when software initiate write
-         *  operation, it is tx data register 8 and when software initiate read operation, it
-         *  is rx data register 8.
-         */
-        uint32_t data_8:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_8_reg_t;
-
-/** Type of data_9 register
- *  Data register 9.
- */
-typedef union {
-    struct {
-        /** data_9 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, reserved with RO. In operation mode, when software initiate write
-         *  operation, it is tx data register 9 and when software initiate read operation, it
-         *  is rx data register 9.
-         */
-        uint32_t data_9:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_9_reg_t;
-
-/** Type of data_10 register
- *  Data register 10.
- */
-typedef union {
-    struct {
-        /** data_10 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, reserved with RO. In operation mode, when software initiate write
-         *  operation, it is tx data register 10 and when software initiate read operation, it
-         *  is rx data register 10.
-         */
-        uint32_t data_10:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_10_reg_t;
-
-/** Type of data_11 register
- *  Data register 11.
- */
-typedef union {
-    struct {
-        /** data_11 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, reserved with RO. In operation mode, when software initiate write
-         *  operation, it is tx data register 11 and when software initiate read operation, it
-         *  is rx data register 11.
-         */
-        uint32_t data_11:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_11_reg_t;
-
-/** Type of data_12 register
- *  Data register 12.
- */
-typedef union {
-    struct {
-        /** data_12 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, reserved with RO. In operation mode, when software initiate write
-         *  operation, it is tx data register 12 and when software initiate read operation, it
-         *  is rx data register 12.
-         */
-        uint32_t data_12:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_12_reg_t;
-
-
-/** Group: Timestamp Register */
-/** Type of timestamp_data register
- *  Timestamp data register
- */
-typedef union {
-    struct {
-        /** timestamp_data : RO; bitpos: [31:0]; default: 0;
-         *  Data of timestamp of a CAN frame.
-         */
-        uint32_t timestamp_data:32;
-    };
-    uint32_t val;
-} twai_timestamp_data_reg_t;
-
-/** Type of timestamp_prescaler register
- *  Timestamp configuration register
- */
-typedef union {
-    struct {
-        /** ts_div_num : R/W; bitpos: [15:0]; default: 31;
-         *  Configures the clock division number of timestamp counter.
-         */
-        uint32_t ts_div_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} twai_timestamp_prescaler_reg_t;
-
-/** Type of timestamp_cfg register
- *  Timestamp configuration register
- */
-typedef union {
-    struct {
-        /** ts_enable : R/W; bitpos: [0]; default: 0;
-         *  enable the timestamp collection function.
-         */
-        uint32_t ts_enable:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} twai_timestamp_cfg_reg_t;
-
-
-typedef struct {
-    volatile twai_mode_reg_t mode;
-    volatile twai_cmd_reg_t cmd;
-    volatile twai_status_reg_t status;
-    volatile twai_interrupt_reg_t interrupt;
-    volatile twai_interrupt_enable_reg_t interrupt_enable;
-    uint32_t reserved_014;
-    volatile twai_bus_timing_0_reg_t bus_timing_0;
-    volatile twai_bus_timing_1_reg_t bus_timing_1;
-    uint32_t reserved_020[3];
-    volatile twai_arb_lost_cap_reg_t arb_lost_cap;
-    volatile twai_err_code_cap_reg_t err_code_cap;
-    volatile twai_err_warning_limit_reg_t err_warning_limit;
-    volatile twai_rx_err_cnt_reg_t rx_err_cnt;
-    volatile twai_tx_err_cnt_reg_t tx_err_cnt;
-    volatile twai_data_0_reg_t data_0;
-    volatile twai_data_1_reg_t data_1;
-    volatile twai_data_2_reg_t data_2;
-    volatile twai_data_3_reg_t data_3;
-    volatile twai_data_4_reg_t data_4;
-    volatile twai_data_5_reg_t data_5;
-    volatile twai_data_6_reg_t data_6;
-    volatile twai_data_7_reg_t data_7;
-    volatile twai_data_8_reg_t data_8;
-    volatile twai_data_9_reg_t data_9;
-    volatile twai_data_10_reg_t data_10;
-    volatile twai_data_11_reg_t data_11;
-    volatile twai_data_12_reg_t data_12;
-    volatile twai_rx_message_counter_reg_t rx_message_counter;
-    uint32_t reserved_078;
-    volatile twai_clock_divider_reg_t clock_divider;
-    volatile twai_sw_standby_cfg_reg_t sw_standby_cfg;
-    volatile twai_hw_cfg_reg_t hw_cfg;
-    volatile twai_hw_standby_cnt_reg_t hw_standby_cnt;
-    volatile twai_idle_intr_cnt_reg_t idle_intr_cnt;
-    volatile twai_eco_cfg_reg_t eco_cfg;
-    volatile twai_timestamp_data_reg_t timestamp_data;
-    volatile twai_timestamp_prescaler_reg_t timestamp_prescaler;
-    volatile twai_timestamp_cfg_reg_t timestamp_cfg;
-} twai_dev_t;
-
-extern twai_dev_t TWAI0;
-extern twai_dev_t TWAI1;
-extern twai_dev_t TWAI2;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(twai_dev_t) == 0xa0, "Invalid size of twai_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/docs/en/api-reference/peripherals/camera_driver.rst b/docs/en/api-reference/peripherals/camera_driver.rst
index dee4dddc76dd..51e7c5fc6ae4 100644
--- a/docs/en/api-reference/peripherals/camera_driver.rst
+++ b/docs/en/api-reference/peripherals/camera_driver.rst
@@ -114,6 +114,16 @@ Camera controller driver can be implemented in one of following ways:
 
     After calling :cpp:func:`esp_cam_new_dvp_ctlr`, you should allocate a camera buffer that meets the alignment constraints, or call :cpp:func:`esp_cam_ctlr_alloc_buffer` to automatically allocate.
 
+    You can call :cpp:func:`esp_cam_ctlr_format_conversion` to configure format conversion. The driver supports the following conversion types:
+
+    * YUV to RGB conversion
+    * RGB to YUV conversion
+    * YUV to YUV conversion
+
+    Color range support:
+    * Full range: 0-255 for both RGB and YUV
+    * Limited range: RGB 16-240, YUV Y:16-240, U-V:16-235
+
     .. code:: c
 
         esp_cam_ctlr_handle_t cam_handle = NULL;
@@ -148,6 +158,16 @@ Camera controller driver can be implemented in one of following ways:
 
         ESP_ERROR_CHECK(esp_cam_new_dvp_ctlr(&dvp_config, &cam_handle));
 
+        const cam_ctlr_format_conv_config_t conv_cfg = {
+            .src_format = CAM_CTLR_COLOR_YUV422,      // Source format: YUV422
+            .dst_format = CAM_CTLR_COLOR_RGB565,      // Destination format: RGB565
+            .conv_std = COLOR_CONV_STD_RGB_YUV_BT601,
+            .data_width = 8,
+            .input_range = COLOR_RANGE_LIMIT,
+            .output_range = COLOR_RANGE_LIMIT,
+        };
+        ESP_ERROR_CHECK(esp_cam_ctlr_format_conversion(cam_handle, &conv_cfg));
+
 Uninstall Camera Controller Driver
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
diff --git a/docs/en/api-reference/peripherals/i2s.rst b/docs/en/api-reference/peripherals/i2s.rst
index e68ab6092c31..4ce6a4be55a4 100644
--- a/docs/en/api-reference/peripherals/i2s.rst
+++ b/docs/en/api-reference/peripherals/i2s.rst
@@ -841,7 +841,9 @@ Full-duplex mode registers TX and RX channel in an I2S port at the same time, an
 
 Note that one handle can only stand for one channel. Therefore, it is still necessary to configure the slot and clock for both TX and RX channels one by one.
 
-Here is an example of how to allocate a pair of full-duplex channels:
+There are two methods to allocate a pair of full-duplex channels:
+
+1. Allocate both TX and RX handles in a single call of :cpp:func:`i2s_new_channel`.
 
 .. code-block:: c
 
@@ -881,6 +883,48 @@ Here is an example of how to allocate a pair of full-duplex channels:
 
     ...
 
+2. Allocate TX and RX handles separately, and initialize them with the same configuration.
+
+.. code-block:: c
+
+    #include "driver/i2s_std.h"
+    #include "driver/gpio.h"
+
+    i2s_chan_handle_t tx_handle;
+    i2s_chan_handle_t rx_handle;
+
+    /* Allocate a pair of I2S channels on a same port */
+    i2s_chan_config_t chan_cfg = I2S_CHANNEL_DEFAULT_CONFIG(I2S_NUM_0, I2S_ROLE_MASTER);
+    /* Allocate for TX and RX channel separately, they are not full-duplex yet */
+    ESP_ERROR_CHECK(i2s_new_channel(&chan_cfg, &tx_handle, NULL));
+
+    /* Set the configurations for BOTH TWO channels, they will constitute in full-duplex mode automatically */
+    i2s_std_config_t std_cfg = {
+        .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(32000),
+        .slot_cfg = I2S_STD_PHILIPS_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO),
+        .gpio_cfg = {
+            .mclk = I2S_GPIO_UNUSED,
+            .bclk = GPIO_NUM_4,
+            .ws = GPIO_NUM_5,
+            .dout = GPIO_NUM_18,
+            .din = GPIO_NUM_19,
+            .invert_flags = {
+                .mclk_inv = false,
+                .bclk_inv = false,
+                .ws_inv = false,
+            },
+        },
+    };
+    ESP_ERROR_CHECK(i2s_channel_init_std_mode(tx_handle, &std_cfg));
+    ESP_ERROR_CHECK(i2s_channel_enable(tx_handle));
+    // ...
+    ESP_ERROR_CHECK(i2s_new_channel(&chan_cfg, NULL, &rx_handle));
+    ESP_ERROR_CHECK(i2s_channel_init_std_mode(rx_handle, &std_cfg));
+    ESP_ERROR_CHECK(i2s_channel_enable(rx_handle));
+
+    ...
+
+
 .. only:: SOC_I2S_HW_VERSION_1
 
     Simplex Mode
@@ -897,7 +941,7 @@ Here is an example of how to allocate a pair of full-duplex channels:
         i2s_chan_handle_t rx_handle;
 
         i2s_chan_config_t chan_cfg = I2S_CHANNEL_DEFAULT_CONFIG(I2S_NUM_AUTO, I2S_ROLE_MASTER);
-        i2s_new_channel(&chan_cfg, &tx_handle, NULL);
+        ESP_ERROR_CHECK(i2s_new_channel(&chan_cfg, &tx_handle, NULL));
         i2s_std_config_t std_tx_cfg = {
             .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(48000),
             .slot_cfg = I2S_STD_PHILIPS_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO),
@@ -915,12 +959,12 @@ Here is an example of how to allocate a pair of full-duplex channels:
             },
         };
         /* Initialize the channel */
-        i2s_channel_init_std_mode(tx_handle, &std_tx_cfg);
-        i2s_channel_enable(tx_handle);
+        ESP_ERROR_CHECK(i2s_channel_init_std_mode(tx_handle, &std_tx_cfg));
+        ESP_ERROR_CHECK(i2s_channel_enable(tx_handle));
 
         /* RX channel will be registered on another I2S, if no other available I2S unit found
          * it will return ESP_ERR_NOT_FOUND */
-        i2s_new_channel(&chan_cfg, NULL, &rx_handle);
+        ESP_ERROR_CHECK(i2s_new_channel(&chan_cfg, NULL, &rx_handle));
         i2s_std_config_t std_rx_cfg = {
             .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(16000),
             .slot_cfg = I2S_STD_MSB_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_32BIT, I2S_SLOT_MODE_STEREO),
@@ -937,8 +981,8 @@ Here is an example of how to allocate a pair of full-duplex channels:
                 },
             },
         };
-        i2s_channel_init_std_mode(rx_handle, &std_rx_cfg);
-        i2s_channel_enable(rx_handle);
+        ESP_ERROR_CHECK(i2s_channel_init_std_mode(rx_handle, &std_rx_cfg));
+        ESP_ERROR_CHECK(i2s_channel_enable(rx_handle));
 
 .. only:: SOC_I2S_HW_VERSION_2
 
@@ -957,7 +1001,7 @@ Here is an example of how to allocate a pair of full-duplex channels:
         i2s_chan_handle_t tx_handle;
         i2s_chan_handle_t rx_handle;
         i2s_chan_config_t chan_cfg = I2S_CHANNEL_DEFAULT_CONFIG(I2S_NUM_0, I2S_ROLE_MASTER);
-        i2s_new_channel(&chan_cfg, &tx_handle, NULL);
+        ESP_ERROR_CHECK(i2s_new_channel(&chan_cfg, &tx_handle, NULL));
         i2s_std_config_t std_tx_cfg = {
             .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(48000),
             .slot_cfg = I2S_STD_PHILIPS_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO),
@@ -975,12 +1019,12 @@ Here is an example of how to allocate a pair of full-duplex channels:
             },
         };
         /* Initialize the channel */
-        i2s_channel_init_std_mode(tx_handle, &std_tx_cfg);
-        i2s_channel_enable(tx_handle);
+        ESP_ERROR_CHECK(i2s_channel_init_std_mode(tx_handle, &std_tx_cfg));
+        ESP_ERROR_CHECK(i2s_channel_enable(tx_handle));
 
         /* RX channel will be registered on another I2S, if no other available I2S unit found
          * it will return ESP_ERR_NOT_FOUND */
-        i2s_new_channel(&chan_cfg, NULL, &rx_handle); // Both RX and TX channel will be registered on I2S0, but they can work with different configurations.
+        ESP_ERROR_CHECK(i2s_new_channel(&chan_cfg, NULL, &rx_handle)); // Both RX and TX channel will be registered on I2S0, but they can work with different configurations.
         i2s_std_config_t std_rx_cfg = {
             .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(16000),
             .slot_cfg = I2S_STD_MSB_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_32BIT, I2S_SLOT_MODE_STEREO),
@@ -997,8 +1041,8 @@ Here is an example of how to allocate a pair of full-duplex channels:
                 },
             },
         };
-        i2s_channel_init_std_mode(rx_handle, &std_rx_cfg);
-        i2s_channel_enable(rx_handle);
+        ESP_ERROR_CHECK(i2s_channel_init_std_mode(rx_handle, &std_rx_cfg));
+        ESP_ERROR_CHECK(i2s_channel_enable(rx_handle));
 
 .. only:: SOC_I2S_SUPPORTS_ETM
 
diff --git a/docs/zh_CN/api-reference/peripherals/camera_driver.rst b/docs/zh_CN/api-reference/peripherals/camera_driver.rst
index e49af5b44e80..8fa2ccfd073d 100644
--- a/docs/zh_CN/api-reference/peripherals/camera_driver.rst
+++ b/docs/zh_CN/api-reference/peripherals/camera_driver.rst
@@ -114,6 +114,16 @@
 
     在调用 :cpp:func:`esp_cam_new_dvp_ctlr` 之后，需要分配符合对齐约束的摄像头缓冲区，或调用 :cpp:func:`esp_cam_ctlr_alloc_buffer` 来自动分配。
 
+    可以调用 :cpp:func:`esp_cam_ctlr_format_conversion` 来配置格式转换。驱动程序支持以下转换类型：
+
+    * YUV 到 RGB 转换
+    * RGB 到 YUV 转换
+    * YUV 到 YUV 转换
+
+    色彩空间范围支持：
+    * 全色彩空间：RGB 和 YUV 的取值范围为 0-255
+    * 有限色彩空间：RGB 取值范围为 16-240，YUV Y 分量取值范围为 16-240，U-V 分量取值范围为 16-235
+
     .. code:: c
 
         esp_cam_ctlr_handle_t cam_handle = NULL;
@@ -148,6 +158,16 @@
 
         ESP_ERROR_CHECK(esp_cam_new_dvp_ctlr(&dvp_config, &cam_handle));
 
+        const cam_ctlr_format_conv_config_t conv_cfg = {
+            .src_format = CAM_CTLR_COLOR_YUV422,      // 源格式：YUV422
+            .dst_format = CAM_CTLR_COLOR_RGB565,      // 目标格式：RGB565
+            .conv_std = COLOR_CONV_STD_RGB_YUV_BT601,
+            .data_width = 8,
+            .input_range = COLOR_RANGE_LIMIT,
+            .output_range = COLOR_RANGE_LIMIT,
+        };
+        ESP_ERROR_CHECK(esp_cam_ctlr_format_conversion(cam_handle, &conv_cfg));
+
 卸载摄像头控制器驱动程序
 ~~~~~~~~~~~~~~~~~~~~~~~~
 
diff --git a/docs/zh_CN/api-reference/peripherals/i2s.rst b/docs/zh_CN/api-reference/peripherals/i2s.rst
index 7e0385a3804a..df7b97cd9172 100644
--- a/docs/zh_CN/api-reference/peripherals/i2s.rst
+++ b/docs/zh_CN/api-reference/peripherals/i2s.rst
@@ -835,7 +835,9 @@ STD RX 模式
 
 请注意，一个句柄只能代表一个通道，因此仍然需要对 TX 和 RX 通道逐个进行声道和时钟配置。
 
-以下示例展示了如何分配两个全双工通道：
+驱动支持两种分配全双工通道的方法：
+
+1. 在调用 :cpp:func:`i2s_new_channel` 函数时，同时分配 TX 和 RX 通道两个通道。
 
 .. code-block:: c
 
@@ -875,6 +877,47 @@ STD RX 模式
 
     ...
 
+2. 调用两次 :cpp:func:`i2s_new_channel` 函数分别分配 TX 和 RX 通道，但使用相同配置初始化 TX 和 RX 通道。
+
+.. code-block:: c
+
+    #include "driver/i2s_std.h"
+    #include "driver/gpio.h"
+
+    i2s_chan_handle_t tx_handle;
+    i2s_chan_handle_t rx_handle;
+
+    /* 分配两个 I2S 通道 */
+    i2s_chan_config_t chan_cfg = I2S_CHANNEL_DEFAULT_CONFIG(I2S_NUM_0, I2S_ROLE_MASTER);
+    /* 分别分配给 TX 和 RX 通道 */
+    ESP_ERROR_CHECK(i2s_new_channel(&chan_cfg, &tx_handle, NULL));
+
+    /* 为两个通道设置完全相同的配置，TX 和 RX 将自动组成全双工模式 */
+    i2s_std_config_t std_cfg = {
+        .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(32000),
+        .slot_cfg = I2S_STD_PHILIPS_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO),
+        .gpio_cfg = {
+            .mclk = I2S_GPIO_UNUSED,
+            .bclk = GPIO_NUM_4,
+            .ws = GPIO_NUM_5,
+            .dout = GPIO_NUM_18,
+            .din = GPIO_NUM_19,
+            .invert_flags = {
+                .mclk_inv = false,
+                .bclk_inv = false,
+                .ws_inv = false,
+            },
+        },
+    };
+    ESP_ERROR_CHECK(i2s_channel_init_std_mode(tx_handle, &std_cfg));
+    ESP_ERROR_CHECK(i2s_channel_enable(tx_handle));
+    // ...
+    ESP_ERROR_CHECK(i2s_new_channel(&chan_cfg, NULL, &rx_handle));
+    ESP_ERROR_CHECK(i2s_channel_init_std_mode(rx_handle, &std_cfg));
+    ESP_ERROR_CHECK(i2s_channel_enable(rx_handle));
+
+    ...
+
 .. only:: SOC_I2S_HW_VERSION_1
 
     单工模式
@@ -891,7 +934,7 @@ STD RX 模式
         i2s_chan_handle_t rx_handle;
 
         i2s_chan_config_t chan_cfg = I2S_CHANNEL_DEFAULT_CONFIG(I2S_NUM_AUTO, I2S_ROLE_MASTER);
-        i2s_new_channel(&chan_cfg, &tx_handle, NULL);
+        ESP_ERROR_CHECK(i2s_new_channel(&chan_cfg, &tx_handle, NULL));
         i2s_std_config_t std_tx_cfg = {
             .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(48000),
             .slot_cfg = I2S_STD_PHILIPS_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO),
@@ -909,12 +952,12 @@ STD RX 模式
             },
         };
         /* 初始化通道 */
-        i2s_channel_init_std_mode(tx_handle, &std_tx_cfg);
-        i2s_channel_enable(tx_handle);
+        ESP_ERROR_CHECK(i2s_channel_init_std_mode(tx_handle, &std_tx_cfg));
+        ESP_ERROR_CHECK(i2s_channel_enable(tx_handle));
 
         /* 如果没有找到其他可用的 I2S 设备，RX 通道将被注册在另一个 I2S 上
          * 并返回 ESP_ERR_NOT_FOUND */
-        i2s_new_channel(&chan_cfg, NULL, &rx_handle);
+        ESP_ERROR_CHECK(i2s_new_channel(&chan_cfg, NULL, &rx_handle));
         i2s_std_config_t std_rx_cfg = {
             .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(16000),
             .slot_cfg = I2S_STD_MSB_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_32BIT, I2S_SLOT_MODE_STEREO),
@@ -931,8 +974,8 @@ STD RX 模式
                 },
             },
         };
-        i2s_channel_init_std_mode(rx_handle, &std_rx_cfg);
-        i2s_channel_enable(rx_handle);
+        ESP_ERROR_CHECK(i2s_channel_init_std_mode(rx_handle, &std_rx_cfg));
+        ESP_ERROR_CHECK(i2s_channel_enable(rx_handle));
 
 .. only:: SOC_I2S_HW_VERSION_2
 
@@ -951,7 +994,7 @@ STD RX 模式
         i2s_chan_handle_t tx_handle;
         i2s_chan_handle_t rx_handle;
         i2s_chan_config_t chan_cfg = I2S_CHANNEL_DEFAULT_CONFIG(I2S_NUM_0, I2S_ROLE_MASTER);
-        i2s_new_channel(&chan_cfg, &tx_handle, NULL);
+        ESP_ERROR_CHECK(i2s_new_channel(&chan_cfg, &tx_handle, NULL));
         i2s_std_config_t std_tx_cfg = {
             .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(48000),
             .slot_cfg = I2S_STD_PHILIPS_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO),
@@ -969,12 +1012,12 @@ STD RX 模式
             },
         };
         /* 初始化通道 */
-        i2s_channel_init_std_mode(tx_handle, &std_tx_cfg);
-        i2s_channel_enable(tx_handle);
+        ESP_ERROR_CHECK(i2s_channel_init_std_mode(tx_handle, &std_tx_cfg));
+        ESP_ERROR_CHECK(i2s_channel_enable(tx_handle));
 
         /* 如果没有找到其他可用的 I2S 设备，RX 通道将被注册在另一个 I2S 上
          * 并返回 ESP_ERR_NOT_FOUND */
-        i2s_new_channel(&chan_cfg, NULL, &rx_handle); // RX 和 TX 通道都将注册在 I2S0 上，但配置可以不同
+        ESP_ERROR_CHECK(i2s_new_channel(&chan_cfg, NULL, &rx_handle)); // RX 和 TX 通道都将注册在 I2S0 上，但配置可以不同
         i2s_std_config_t std_rx_cfg = {
             .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(16000),
             .slot_cfg = I2S_STD_MSB_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_32BIT, I2S_SLOT_MODE_STEREO),
@@ -991,8 +1034,8 @@ STD RX 模式
                 },
             },
         };
-        i2s_channel_init_std_mode(rx_handle, &std_rx_cfg);
-        i2s_channel_enable(rx_handle);
+        ESP_ERROR_CHECK(i2s_channel_init_std_mode(rx_handle, &std_rx_cfg));
+        ESP_ERROR_CHECK(i2s_channel_enable(rx_handle));
 
 .. only:: SOC_I2S_SUPPORTS_ETM
 
diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/src/gap.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/src/gap.c
index 71e03ba7c2aa..8243ecf3341c 100644
--- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/src/gap.c
+++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/src/gap.c
@@ -51,7 +51,7 @@ static void start_advertising(void) {
     adv_fields.le_role = BLE_GAP_LE_ROLE_PERIPHERAL;
     adv_fields.le_role_is_present = 1;
 
-    /* Set advertiement fields */
+    /* Set advertisement fields */
     rc = ble_gap_adv_set_fields(&adv_fields);
     if (rc != 0) {
         ESP_LOGE(TAG, "failed to set advertising data, error code: %d", rc);
@@ -74,7 +74,7 @@ static void start_advertising(void) {
         return;
     }
 
-    /* Set non-connetable and general discoverable mode to be a beacon */
+    /* Set non-connectable and general discoverable mode to be a beacon */
     adv_params.conn_mode = BLE_GAP_CONN_MODE_NON;
     adv_params.disc_mode = BLE_GAP_DISC_MODE_GEN;
 
diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c
index d2689f9230fa..d4d220d9fc17 100644
--- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c
+++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c
@@ -80,7 +80,7 @@ static void start_advertising(void) {
     adv_fields.le_role = BLE_GAP_LE_ROLE_PERIPHERAL;
     adv_fields.le_role_is_present = 1;
 
-    /* Set advertiement fields */
+    /* Set advertisement fields */
     rc = ble_gap_adv_set_fields(&adv_fields);
     if (rc != 0) {
         ESP_LOGE(TAG, "failed to set advertising data, error code: %d", rc);
@@ -107,7 +107,7 @@ static void start_advertising(void) {
         return;
     }
 
-    /* Set non-connetable and general discoverable mode to be a beacon */
+    /* Set undirected connectable and general discoverable mode */
     adv_params.conn_mode = BLE_GAP_CONN_MODE_UND;
     adv_params.disc_mode = BLE_GAP_DISC_MODE_GEN;
 
diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/src/gap.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/src/gap.c
index 8519028a5d0e..7c7b3dde2ade 100644
--- a/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/src/gap.c
+++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/src/gap.c
@@ -80,7 +80,7 @@ static void start_advertising(void) {
     adv_fields.le_role = BLE_GAP_LE_ROLE_PERIPHERAL;
     adv_fields.le_role_is_present = 1;
 
-    /* Set advertiement fields */
+    /* Set advertisement fields */
     rc = ble_gap_adv_set_fields(&adv_fields);
     if (rc != 0) {
         ESP_LOGE(TAG, "failed to set advertising data, error code: %d", rc);
@@ -107,7 +107,7 @@ static void start_advertising(void) {
         return;
     }
 
-    /* Set non-connetable and general discoverable mode to be a beacon */
+    /* Set undirected connectable and general discoverable mode */
     adv_params.conn_mode = BLE_GAP_CONN_MODE_UND;
     adv_params.disc_mode = BLE_GAP_DISC_MODE_GEN;
 
diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/src/gap.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/src/gap.c
index d4e7c249b68c..55c34487eb9d 100644
--- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/src/gap.c
+++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/src/gap.c
@@ -95,7 +95,7 @@ static void start_advertising(void) {
     adv_fields.le_role = BLE_GAP_LE_ROLE_PERIPHERAL;
     adv_fields.le_role_is_present = 1;
 
-    /* Set advertiement fields */
+    /* Set advertisement fields */
     rc = ble_gap_adv_set_fields(&adv_fields);
     if (rc != 0) {
         ESP_LOGE(TAG, "failed to set advertising data, error code: %d", rc);
@@ -122,7 +122,7 @@ static void start_advertising(void) {
         return;
     }
 
-    /* Set non-connetable and general discoverable mode to be a beacon */
+    /* Set undirected connectable and general discoverable mode */
     adv_params.conn_mode = BLE_GAP_CONN_MODE_UND;
     adv_params.disc_mode = BLE_GAP_DISC_MODE_GEN;
 
diff --git a/examples/peripherals/camera/dvp_spi_lcd/main/Kconfig.projbuild b/examples/peripherals/camera/dvp_spi_lcd/main/Kconfig.projbuild
index d44ca3210ba8..de1d53bbbeae 100644
--- a/examples/peripherals/camera/dvp_spi_lcd/main/Kconfig.projbuild
+++ b/examples/peripherals/camera/dvp_spi_lcd/main/Kconfig.projbuild
@@ -30,4 +30,15 @@ menu "Example Configuration"
         int
         default 480 if EXAMPLE_CAM_VRES_480
         default 240 if EXAMPLE_CAM_VRES_240
+
+    choice EXAMPLE_CAM_INPUT_FORMAT
+        bool "Set camera input format"
+        default EXAMPLE_CAM_INPUT_FORMAT_YUV422
+
+        config EXAMPLE_CAM_INPUT_FORMAT_RGB565
+            bool "RGB565"
+        config EXAMPLE_CAM_INPUT_FORMAT_YUV422
+            bool "YUV422"
+    endchoice
+
 endmenu
diff --git a/examples/peripherals/camera/dvp_spi_lcd/main/dvp_spi_lcd_main.c b/examples/peripherals/camera/dvp_spi_lcd/main/dvp_spi_lcd_main.c
index bd9b1855fac2..eacaf2dff745 100644
--- a/examples/peripherals/camera/dvp_spi_lcd/main/dvp_spi_lcd_main.c
+++ b/examples/peripherals/camera/dvp_spi_lcd/main/dvp_spi_lcd_main.c
@@ -146,7 +146,11 @@ void app_main(void)
         .clk_src = CAM_CLK_SRC_DEFAULT,
         .h_res = CONFIG_EXAMPLE_CAM_HRES,
         .v_res = CONFIG_EXAMPLE_CAM_VRES,
+#if CONFIG_EXAMPLE_CAM_INPUT_FORMAT_YUV422
+        .input_data_color_type = CAM_CTLR_COLOR_YUV422,
+#else
         .input_data_color_type = CAM_CTLR_COLOR_RGB565,
+#endif
         .dma_burst_size = 64,
         .pin = &pin_cfg,
         .bk_buffer_dis = 1,
@@ -200,6 +204,20 @@ void app_main(void)
     //--------Enable and start Camera Controller----------//
     ESP_ERROR_CHECK(esp_cam_ctlr_enable(cam_handle));
 
+#if CONFIG_EXAMPLE_CAM_INPUT_FORMAT_YUV422
+    ESP_LOGI(TAG, "Configure format conversion: YUV422 -> RGB565");
+    // Configure format conversion
+    const cam_ctlr_format_conv_config_t conv_cfg = {
+        .src_format = CAM_CTLR_COLOR_YUV422,      // Source format: YUV422
+        .dst_format = CAM_CTLR_COLOR_RGB565,      // Destination format: RGB565
+        .conv_std = COLOR_CONV_STD_RGB_YUV_BT601,
+        .data_width = 8,
+        .input_range = COLOR_RANGE_LIMIT,
+        .output_range = COLOR_RANGE_LIMIT,
+    };
+    ESP_ERROR_CHECK(esp_cam_ctlr_format_conversion(cam_handle, &conv_cfg));
+#endif
+
     if (esp_cam_ctlr_start(cam_handle) != ESP_OK) {
         ESP_LOGE(TAG, "Driver start fail");
         return;
diff --git a/examples/peripherals/camera/dvp_spi_lcd/main/example_config.h b/examples/peripherals/camera/dvp_spi_lcd/main/example_config.h
index 2925ac9542fe..5609ef560cb6 100644
--- a/examples/peripherals/camera/dvp_spi_lcd/main/example_config.h
+++ b/examples/peripherals/camera/dvp_spi_lcd/main/example_config.h
@@ -43,7 +43,11 @@ extern "C" {
 #define EXAMPLE_DVP_CAM_BUF_ALLOC_CAPS     (MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA)
 #endif
 
+#if CONFIG_EXAMPLE_CAM_INPUT_FORMAT_YUV422
+#define EXAMPLE_CAM_FORMAT                  "DVP_8bit_20Minput_YUV422_240x240_25fps" // ov2640
+#elif CONFIG_EXAMPLE_CAM_INPUT_FORMAT_RGB565
 #define EXAMPLE_CAM_FORMAT                  "DVP_8bit_20Minput_RGB565_240x240_25fps" // ov2640
+#endif
 
 #ifndef EXAMPLE_CAM_FORMAT
 #error "Unsupported camera format! Please adjust EXAMPLE_CAM_HRES and EXAMPLE_CAM_VRES in menuconfig"
diff --git a/examples/peripherals/pcnt/rotary_encoder/pytest_rotary_encoder.py b/examples/peripherals/pcnt/rotary_encoder/pytest_rotary_encoder.py
index 29d17f4c81e7..144fa82be34c 100644
--- a/examples/peripherals/pcnt/rotary_encoder/pytest_rotary_encoder.py
+++ b/examples/peripherals/pcnt/rotary_encoder/pytest_rotary_encoder.py
@@ -20,6 +20,6 @@ def test_rotary_encoder(dut: Dut) -> None:
     dut.expect_exact('add watch points and register callbacks')
     dut.expect_exact('clear pcnt unit')
     dut.expect_exact('start pcnt unit')
-    res = dut.expect(r'Pulse count: (\d+)')
+    res = dut.expect(r'(?:Pulse count|Watch point event, count): (-?\d+)')
     count_val = res.group(1).decode('utf8')
     assert -100 <= int(count_val) <= 100