diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild
index e648a39a9af4..d0fed3bf6f27 100644
--- a/components/bootloader/Kconfig.projbuild
+++ b/components/bootloader/Kconfig.projbuild
@@ -967,7 +967,7 @@ menu "Security features"
 
         config SECURE_BOOT_SKIP_WRITE_PROTECTION_SCA
             bool "Skip write-protection of SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH"
-            default y if SECURE_FLASH_PSEUDO_ROUND_FUNC
+            default y if SECURE_FLASH_PSEUDO_ROUND_FUNC && !SECURE_FLASH_ENCRYPTION_MODE_RELEASE
             default n
             depends on SOC_ECDSA_SUPPORT_CURVE_P384 && SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
             help
diff --git a/components/bt/common/ble_log/Kconfig.in b/components/bt/common/ble_log/Kconfig.in
index dfbd47117831..2bb05ede5af5 100644
--- a/components/bt/common/ble_log/Kconfig.in
+++ b/components/bt/common/ble_log/Kconfig.in
@@ -5,6 +5,14 @@ config BLE_LOG_ENABLED
         Enable BLE Log Module
 
 if BLE_LOG_ENABLED
+    config BLE_LOG_TASK_STACK_SIZE
+        int "Stack size for BLE Log Task"
+        default 1024 if IDF_TARGET_ARCH_RISCV
+        default 2048 if IDF_TARGET_ARCH_XTENSA
+        default 1024
+        help
+            Stack size for BLE Log Task
+
     config BLE_LOG_LBM_TRANS_SIZE
         int "Buffer size for each peripheral transport"
         default 512
diff --git a/components/bt/common/ble_log/ble_log_spi_out.c b/components/bt/common/ble_log/ble_log_spi_out.c
index d2441431831c..bff68af46bb7 100644
--- a/components/bt/common/ble_log/ble_log_spi_out.c
+++ b/components/bt/common/ble_log/ble_log_spi_out.c
@@ -41,7 +41,14 @@
 #define SPI_OUT_LOG_STR_BUF_SIZE                (100)
 #define SPI_OUT_MALLOC(size)                    heap_caps_malloc(size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
 #define SPI_OUT_TASK_PRIORITY                   (ESP_TASK_PRIO_MAX - 1)
+
+#if CONFIG_IDF_TARGET_ARCH_RISCV
 #define SPI_OUT_TASK_STACK_SIZE                 (1024)
+#elif CONFIG_IDF_TARGET_ARCH_XTENSA
+#define SPI_OUT_TASK_STACK_SIZE                 (2048)
+#else
+static_assert(false, "BLE Log SPI Out: Unsupported target architecture");
+#endif /* CONFIG_IDF_TARGET_ARCH_RISCV */
 
 #if SPI_OUT_TS_SYNC_ENABLED
 #define SPI_OUT_TS_SYNC_TIMEOUT_MS              (1000)
@@ -247,9 +254,9 @@ extern uint32_t r_ble_lll_timer_current_tick_get(void);
 #elif defined(CONFIG_IDF_TARGET_ESP32C2)
 extern uint32_t r_os_cputime_get32(void);
 #define SPI_OUT_GET_LC_TIME r_os_cputime_get32()
-// #elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
-// extern uint32_t lld_read_clock_us(void);
-// #define SPI_OUT_GET_LC_TIME lld_read_clock_us()
+#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
+extern uint32_t lld_read_clock_us(void);
+#define SPI_OUT_GET_LC_TIME lld_read_clock_us()
 #else
 #define SPI_OUT_GET_LC_TIME esp_timer_get_time()
 #endif
@@ -1365,12 +1372,13 @@ int ble_log_spi_out_hci_write(uint8_t source, const uint8_t *addr, uint16_t len)
         return -1;
     }
 
-    if (source == BLE_LOG_SPI_OUT_SOURCE_HCI_UPSTREAM) {
 #if SPI_OUT_LL_ENABLED
+    if (source == BLE_LOG_SPI_OUT_SOURCE_HCI_UPSTREAM) {
         ble_log_spi_out_ll_write(len, addr, 0, NULL, BIT(LL_LOG_FLAG_HCI_UPSTREAM));
-#endif // SPI_OUT_LL_ENABLED
     }
-    if (source == BLE_LOG_SPI_OUT_SOURCE_HCI_DOWNSTREAM) {
+    if (source == BLE_LOG_SPI_OUT_SOURCE_HCI_DOWNSTREAM)
+#endif /* SPI_OUT_LL_ENABLED */
+    {
         spi_out_log_cb_t *log_cb;
         bool fallback = false;
         if (!spi_out_get_task_mapping(LOG_MODULE_TASK_MAP(hci),
diff --git a/components/bt/common/ble_log/src/internal_include/ble_log_rt.h b/components/bt/common/ble_log/src/internal_include/ble_log_rt.h
index f053049339fc..ae8b4b05a37a 100644
--- a/components/bt/common/ble_log/src/internal_include/ble_log_rt.h
+++ b/components/bt/common/ble_log/src/internal_include/ble_log_rt.h
@@ -21,7 +21,7 @@
 
 /* MACRO */
 #define BLE_LOG_TASK_PRIO                       (ESP_TASK_PRIO_MAX - 1)
-#define BLE_LOG_TASK_STACK_SIZE                 (1024)
+#define BLE_LOG_TASK_STACK_SIZE                 CONFIG_BLE_LOG_TASK_STACK_SIZE
 #define BLE_LOG_TASK_HOOK_TIMEOUT_MS            (1000)
 
 /* INTERFACE */
diff --git a/components/bt/common/osi/allocator.c b/components/bt/common/osi/allocator.c
index 86fb705b071d..0293daa8c4e0 100644
--- a/components/bt/common/osi/allocator.c
+++ b/components/bt/common/osi/allocator.c
@@ -241,8 +241,5 @@ void *osi_calloc_func(size_t size)
 
 void osi_free_func(void *ptr)
 {
-#if HEAP_MEMORY_DEBUG
-    osi_mem_dbg_clean(ptr, __func__, __LINE__);
-#endif
-    free(ptr);
+    osi_free(ptr);
 }
diff --git a/components/bt/controller/esp32c3/Kconfig.in b/components/bt/controller/esp32c3/Kconfig.in
index d9f1bcc05d73..6a7b91071718 100644
--- a/components/bt/controller/esp32c3/Kconfig.in
+++ b/components/bt/controller/esp32c3/Kconfig.in
@@ -616,15 +616,15 @@ menu "Controller debug log Options (Experimental)"
 
     config BT_CTRL_LE_LOG_MODE_EN
         depends on BT_CTRL_LE_LOG_EN
-        int "Enable log for specified BLE mode"
-        range 0 4095
-        default 4093
+        hex "Enable log for specified BLE mode"
+        range 0 0xFFFF
+        default 0xDB7F
 
     config BT_CTRL_LE_LOG_LEVEL
         depends on BT_CTRL_LE_LOG_EN
         int "The level of BLE log"
         range 0 5
-        default 2
+        default 1
 
     config BT_CTRL_LE_LOG_BUF1_SIZE
         depends on BT_CTRL_LE_LOG_EN
diff --git a/components/bt/controller/esp32c3/bt.c b/components/bt/controller/esp32c3/bt.c
index ea2bffaec665..b3aa8def98b7 100644
--- a/components/bt/controller/esp32c3/bt.c
+++ b/components/bt/controller/esp32c3/bt.c
@@ -241,7 +241,12 @@ struct osi_funcs_t {
 };
 
 #if CONFIG_BT_CTRL_LE_LOG_EN
-typedef void (*interface_func_t) (uint32_t len, const uint8_t*addr, bool end);
+typedef void (*interface_func_t) (uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag);
+
+enum {
+    BLE_LOG_INTERFACE_FLAG_CONTINUE = 0,
+    BLE_LOG_INTERFACE_FLAG_END,
+};
 #endif // CONFIG_BT_CTRL_LE_LOG_EN
 
 /* External functions or values
@@ -304,11 +309,14 @@ extern void btdm_aa_check_enhance_enable(void);
 
 /* BLE Log module */
 #if CONFIG_BT_CTRL_LE_LOG_EN
+extern int r_ble_log_init_simple(interface_func_t interface, void *handler);
+extern void r_ble_log_deinit_simple(void);
 extern int r_ble_log_init_async(interface_func_t bt_controller_log_interface, bool task_create, uint8_t buffers, uint32_t *bufs_size);
 extern int r_ble_log_deinit_async(void);
 extern void r_ble_log_async_select_dump_buffers(uint8_t buffers);
 extern void r_ble_log_async_output_dump_all(bool output);
 extern void esp_panic_handler_feed_wdts(void);
+extern int r_ble_log_ctrl_level_and_mod(uint8_t level, uint32_t mod_en);
 #endif // CONFIG_BT_CTRL_LE_LOG_EN
 #if (CONFIG_BT_BLUEDROID_ENABLED || CONFIG_BT_NIMBLE_ENABLED)
 extern void scan_stack_enableAdvFlowCtrlVsCmd(bool en);
@@ -399,12 +407,13 @@ static esp_err_t try_heap_caps_add_region(intptr_t start, intptr_t end);
 static void bt_controller_deinit_internal(void);
 
 #if CONFIG_BT_CTRL_LE_LOG_EN
-static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end);
+#if !CONFIG_BT_CTRL_LE_LOG_MODE_BLE_LOG_V2
 #if CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
 void esp_bt_read_ctrl_log_from_flash(bool output);
 static int esp_bt_controller_log_storage(uint32_t len, const uint8_t *addr, bool end);
 static void esp_bt_ctrl_log_partition_get_and_erase_first_block(void);
-#endif // #if CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
+#endif // CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
+#endif // !CONFIG_BT_CTRL_LE_LOG_MODE_BLE_LOG_V2
 #endif // CONFIG_BT_CTRL_LE_LOG_EN
 
 /* Local variable definition
@@ -538,18 +547,14 @@ static bool is_filled = false;
 #endif // CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
 
 #if CONFIG_BT_CTRL_LE_LOG_MODE_BLE_LOG_V2
-static IRAM_ATTR void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end)
-{
-    ble_log_write_hex_ll(len, addr, 0, NULL, 0);
-}
-
 void esp_ble_controller_log_dump_all(bool output)
 {
     ble_log_dump_to_console();
 }
 #else /* !CONFIG_BT_CTRL_LE_LOG_MODE_BLE_LOG_V2 */
-static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end)
+static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, uint32_t len_append, const uint8_t *addr_append, uint32_t flag)
 {
+    bool end = (flag & BIT(BLE_LOG_INTERFACE_FLAG_END));
     if (log_output_mode == LOG_STORAGE_TO_FLASH) {
 #if CONFIG_BT_CTRL_LE_LOG_STORAGE_EN
         esp_bt_controller_log_storage(len, addr, end);
@@ -558,24 +563,19 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b
         portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
         portENTER_CRITICAL_SAFE(&spinlock);
         esp_panic_handler_feed_wdts();
-        for (int i = 0; i < len; i++) {
-            esp_rom_printf("%02x ", addr[i]);
-        }
 
-        if (end) {
-            esp_rom_printf("\n");
+        if (len && addr) {
+            for (int i = 0; i < len; i++) { esp_rom_printf("%02x ", addr[i]); }
+        }
+        if (len_append && addr_append) {
+            for (int i = 0; i < len_append; i++) { esp_rom_printf("%02x ", addr_append[i]); }
         }
+        if (end) { esp_rom_printf("\n"); }
+
         portEXIT_CRITICAL_SAFE(&spinlock);
     }
 }
 
-#if CONFIG_BT_CTRL_LE_LOG_SPI_OUT_EN
-static IRAM_ATTR void esp_bt_controller_spi_log_interface(uint32_t len, const uint8_t *addr, bool end)
-{
-    ble_log_spi_out_ll_write(len, addr, 0, NULL, 0);
-}
-#endif // CONFIG_BT_CTRL_LE_LOG_SPI_OUT_EN
-
 void esp_ble_controller_log_dump_all(bool output)
 {
     if (log_output_mode == LOG_STORAGE_TO_FLASH) {
@@ -612,16 +612,13 @@ esp_err_t esp_bt_controller_log_init(uint8_t log_output_mode)
     }
 
     esp_err_t ret = ESP_OK;
-    uint8_t buffers = 0;
 
-#if CONFIG_BT_CTRL_LE_LOG_EN
-    buffers |= ESP_BLE_LOG_BUF_CONTROLLER;
-#endif // CONFIG_BT_CTRL_LE_LOG_EN
-#if CONFIG_BT_CTRL_LE_HCI_LOG_EN
-    buffers |= ESP_BLE_LOG_BUF_HCI;
-#endif // CONFIG_BT_CTRL_LE_HCI_LOG_EN
+    ret = r_ble_log_init_simple(ble_log_write_hex_ll, NULL);
+    if (ret != ESP_OK) {
+        return ret;
+    }
 
-    ret = r_ble_log_init_async(esp_bt_controller_log_interface, true, buffers, (uint32_t *)log_bufs_size);
+    ret = r_ble_log_ctrl_level_and_mod(BLE_LOG_LEVEL, BLE_LOG_MODE_EN);
     if (ret == ESP_OK) {
         log_is_inited = true;
     }
@@ -664,7 +661,7 @@ esp_err_t esp_bt_controller_log_init(uint8_t log_output_mode)
         case LOG_SPI_OUT:
             task_create = true;
 #if CONFIG_BT_CTRL_LE_LOG_SPI_OUT_EN
-            bt_controller_log_interface = esp_bt_controller_spi_log_interface;
+            bt_controller_log_interface = ble_log_spi_out_ll_write;
 #endif // CONFIG_BT_CTRL_LE_LOG_SPI_OUT_EN
             break;
         default:
@@ -672,6 +669,11 @@ esp_err_t esp_bt_controller_log_init(uint8_t log_output_mode)
     }
 
     ret = r_ble_log_init_async(bt_controller_log_interface, task_create, buffers, (uint32_t *)log_bufs_size);
+    if (ret != ESP_OK) {
+        return ret;
+    }
+
+    ret = r_ble_log_ctrl_level_and_mod(BLE_LOG_LEVEL, BLE_LOG_MODE_EN);
     if (ret == ESP_OK) {
         log_is_inited = true;
     }
diff --git a/components/bt/controller/lib_esp32c3_family b/components/bt/controller/lib_esp32c3_family
index 42c965137ecc..099a7e1ab87d 160000
--- a/components/bt/controller/lib_esp32c3_family
+++ b/components/bt/controller/lib_esp32c3_family
@@ -1 +1 @@
-Subproject commit 42c965137ecc3c6cf3d38ecece7ce71ffc461353
+Subproject commit 099a7e1ab87dd977754fc4ad35678ab7ebf2f2a2
diff --git a/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c b/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c
index d6f51bfc9d7f..fd42502fdaf6 100644
--- a/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c
+++ b/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c
@@ -223,7 +223,7 @@ void bt_mesh_ble_ext_adv_report(tBTM_BLE_EXT_ADV_REPORT *ext_adv_report)
         memcpy(adv_rpt.dir_addr, ext_adv_report->dir_addr, BLE_MESH_ADDR_LEN);
 
         adv_rpt.addr_type           = ext_adv_report->addr_type;
-        adv_rpt.data                = ext_adv_report->adv_data;
+        adv_rpt.data                = ext_adv_report->adv_data_len ? ext_adv_report->adv_data : NULL;
         adv_rpt.length              = ext_adv_report->adv_data_len;
         adv_rpt.rssi                = ext_adv_report->rssi;
         adv_rpt.event_type          = ext_adv_report->event_type;
diff --git a/components/bt/esp_ble_mesh/core/nimble_host/adapter.c b/components/bt/esp_ble_mesh/core/nimble_host/adapter.c
index 60478e93e787..f5fd0279fc43 100644
--- a/components/bt/esp_ble_mesh/core/nimble_host/adapter.c
+++ b/components/bt/esp_ble_mesh/core/nimble_host/adapter.c
@@ -474,7 +474,7 @@ void bt_mesh_ble_ext_adv_report(struct ble_gap_ext_disc_desc *desc)
 
         /* Here, only a shallow copy needs to be implemented;
          * deep copying behavior occurs in btc_ble_mesh_ble_copy_req_data. */
-        adv_rpt.data                = desc->data;
+        adv_rpt.data                = desc->length_data ? desc->data : NULL;
 
         adv_rpt.event_type          = desc->props;
         adv_rpt.addr_type           = desc->addr.type;
diff --git a/components/bt/esp_ble_mesh/core/scan.c b/components/bt/esp_ble_mesh/core/scan.c
index d161061ca748..df6f22e117ec 100644
--- a/components/bt/esp_ble_mesh/core/scan.c
+++ b/components/bt/esp_ble_mesh/core/scan.c
@@ -380,7 +380,7 @@ static void inline callback_ble_adv_pkt(const bt_mesh_addr_t *addr,
         adv_rpt.addr_type = addr->type;
         adv_rpt.adv_type = adv_type;
         adv_rpt.length = length;
-        adv_rpt.data = data;
+        adv_rpt.data = length ? data : NULL;
         adv_rpt.rssi = rssi;
         bt_mesh_ble_scan_cb_evt_to_btc(&adv_rpt);
     }
diff --git a/components/bt/host/bluedroid/api/esp_hidd_api.c b/components/bt/host/bluedroid/api/esp_hidd_api.c
index d7c043666d15..483ba4129196 100644
--- a/components/bt/host/bluedroid/api/esp_hidd_api.c
+++ b/components/bt/host/bluedroid/api/esp_hidd_api.c
@@ -133,7 +133,7 @@ esp_err_t esp_bt_hid_device_send_report(esp_hidd_report_type_t type, uint8_t id,
     args.send_report.data = data;
 
     bt_status_t stat = btc_transfer_context(&msg, &args, sizeof(btc_hidd_args_t),
-                                                btc_hd_arg_deep_copy, btc_hd_cb_arg_deep_free);
+                                                btc_hd_arg_deep_copy, btc_hd_call_arg_deep_free);
     return (stat == BT_STATUS_SUCCESS) ? ESP_OK : ESP_FAIL;
 }
 
diff --git a/components/bt/host/bluedroid/api/esp_hidh_api.c b/components/bt/host/bluedroid/api/esp_hidh_api.c
index e029ee654a0b..f1c39bded884 100644
--- a/components/bt/host/bluedroid/api/esp_hidh_api.c
+++ b/components/bt/host/bluedroid/api/esp_hidh_api.c
@@ -117,7 +117,7 @@ esp_err_t esp_bt_hid_host_set_info(esp_bd_addr_t bd_addr, esp_hidh_hid_info_t *h
     arg.set_info.hid_info = hid_info;
 
     bt_status_t stat = btc_transfer_context(&msg, &arg, sizeof(btc_hidh_args_t),
-                                                btc_hh_arg_deep_copy, btc_hh_cb_arg_deep_free);
+                                                btc_hh_arg_deep_copy, btc_hh_call_arg_deep_free);
     return (stat == BT_STATUS_SUCCESS) ? ESP_OK : ESP_FAIL;
 }
 
@@ -224,7 +224,7 @@ esp_err_t esp_bt_hid_host_set_report(esp_bd_addr_t bd_addr, esp_hidh_report_type
     arg.set_report.report = report;
 
     bt_status_t stat = btc_transfer_context(&msg, &arg, sizeof(btc_hidh_args_t),
-                                                btc_hh_arg_deep_copy, btc_hh_cb_arg_deep_free);
+                                                btc_hh_arg_deep_copy, btc_hh_call_arg_deep_free);
     return (stat == BT_STATUS_SUCCESS) ? ESP_OK : ESP_FAIL;
 }
 
@@ -243,7 +243,7 @@ esp_err_t esp_bt_hid_host_send_data(esp_bd_addr_t bd_addr, uint8_t *data, size_t
     arg.send_data.data = data;
 
     bt_status_t stat = btc_transfer_context(&msg, &arg, sizeof(btc_hidh_args_t),
-                                                btc_hh_arg_deep_copy, btc_hh_cb_arg_deep_free);
+                                                btc_hh_arg_deep_copy, btc_hh_call_arg_deep_free);
     return (stat == BT_STATUS_SUCCESS) ? ESP_OK : ESP_FAIL;
 }
 
diff --git a/components/bt/host/bluedroid/btc/profile/std/hid/btc_hd.c b/components/bt/host/bluedroid/btc/profile/std/hid/btc_hd.c
index 82ff2b8d5c8e..29019fc88135 100644
--- a/components/bt/host/bluedroid/btc/profile/std/hid/btc_hd.c
+++ b/components/bt/host/bluedroid/btc/profile/std/hid/btc_hd.c
@@ -75,6 +75,8 @@ btc_hd_cb_t btc_hd_cb = {0};
 
 typedef void (bt_hid_copy_cb_t)(btc_msg_t *msg, void *p_dest, void *p_src);
 
+static void btc_hd_cb_arg_deep_free(btc_msg_t *msg);
+
 static inline void btc_hd_cb_to_app(esp_hidd_cb_event_t event, esp_hidd_cb_param_t *param)
 {
     esp_hd_cb_t btc_hd_cb = (esp_hd_cb_t)btc_profile_cb_get(BTC_PID_HD);
@@ -705,7 +707,7 @@ static void btc_hd_virtual_cable_unplug(void)
     }
 }
 
-static void btc_hd_call_arg_deep_free(btc_msg_t *msg)
+void btc_hd_call_arg_deep_free(btc_msg_t *msg)
 {
     btc_hidd_args_t *arg = (btc_hidd_args_t *)msg->arg;
 
@@ -756,7 +758,7 @@ void btc_hd_call_handler(btc_msg_t *msg)
     btc_hd_call_arg_deep_free(msg);
 }
 
-void btc_hd_cb_arg_deep_free(btc_msg_t *msg)
+static void btc_hd_cb_arg_deep_free(btc_msg_t *msg)
 {
     tBTA_HD *arg = (tBTA_HD *)msg->arg;
 
diff --git a/components/bt/host/bluedroid/btc/profile/std/hid/btc_hh.c b/components/bt/host/bluedroid/btc/profile/std/hid/btc_hh.c
index 55fe3f69b379..c7adef20069b 100644
--- a/components/bt/host/bluedroid/btc/profile/std/hid/btc_hh.c
+++ b/components/bt/host/bluedroid/btc/profile/std/hid/btc_hh.c
@@ -64,6 +64,8 @@ static bdstr_t bdstr;
 #define is_hidh_init() (btc_hh_cb.status > BTC_HH_DISABLED)
 #define BTC_TIMEOUT_VUP_MS (3 * 1000)
 
+static void btc_hh_cb_arg_deep_free(btc_msg_t *msg);
+
 static inline void btc_hh_cb_to_app(esp_hidh_cb_event_t event, esp_hidh_cb_param_t *param)
 {
     esp_hh_cb_t btc_hh_cb = (esp_hh_cb_t)btc_profile_cb_get(BTC_PID_HH);
@@ -1097,7 +1099,7 @@ static void btc_hh_set_idle_time(btc_hidh_args_t *arg)
     }
 }
 
-static void btc_hh_call_arg_deep_free(btc_msg_t *msg)
+void btc_hh_call_arg_deep_free(btc_msg_t *msg)
 {
     btc_hidh_args_t *arg = (btc_hidh_args_t *)msg->arg;
 
@@ -1166,7 +1168,7 @@ void btc_hh_call_handler(btc_msg_t *msg)
     btc_hh_call_arg_deep_free(msg);
 }
 
-void btc_hh_cb_arg_deep_free(btc_msg_t *msg)
+static void btc_hh_cb_arg_deep_free(btc_msg_t *msg)
 {
     tBTA_HH *arg = (tBTA_HH *)msg->arg;
 
diff --git a/components/bt/host/bluedroid/btc/profile/std/include/btc_hd.h b/components/bt/host/bluedroid/btc/profile/std/include/btc_hd.h
index 15b59393a327..fa01953e8426 100644
--- a/components/bt/host/bluedroid/btc/profile/std/include/btc_hd.h
+++ b/components/bt/host/bluedroid/btc/profile/std/include/btc_hd.h
@@ -99,7 +99,7 @@ void btc_hd_call_handler(btc_msg_t *msg);
 void btc_hd_cb_handler(btc_msg_t *msg);
 
 void btc_hd_arg_deep_copy(btc_msg_t *msg, void *p_dest, void *p_src);
-void btc_hd_cb_arg_deep_free(btc_msg_t *msg);
+void btc_hd_call_arg_deep_free(btc_msg_t *msg);
 
 void btc_hd_get_profile_status(esp_hidd_profile_status_t *param);
 
diff --git a/components/bt/host/bluedroid/btc/profile/std/include/btc_hh.h b/components/bt/host/bluedroid/btc/profile/std/include/btc_hh.h
index f1158c6fddf7..827cd095c752 100644
--- a/components/bt/host/bluedroid/btc/profile/std/include/btc_hh.h
+++ b/components/bt/host/bluedroid/btc/profile/std/include/btc_hh.h
@@ -181,8 +181,7 @@ void btc_hh_call_handler(btc_msg_t *msg);
 void btc_hh_cb_handler(btc_msg_t *msg);
 
 void btc_hh_arg_deep_copy(btc_msg_t *msg, void *p_dest, void *p_src);
-
-void btc_hh_cb_arg_deep_free(btc_msg_t *msg);
+void btc_hh_call_arg_deep_free(btc_msg_t *msg);
 
 bool btc_hh_add_added_dev(BD_ADDR bd_addr, uint16_t attr_mask);
 
diff --git a/components/bt/host/bluedroid/stack/btm/btm_inq.c b/components/bt/host/bluedroid/stack/btm/btm_inq.c
index 4456140df93f..41a47300e729 100644
--- a/components/bt/host/bluedroid/stack/btm/btm_inq.c
+++ b/components/bt/host/bluedroid/stack/btm/btm_inq.c
@@ -240,13 +240,6 @@ tBTM_STATUS BTM_SetDiscoverability (UINT16 inq_mode, UINT16 window, UINT16 inter
         scan_mode |= HCI_PAGE_SCAN_ENABLED;
     }
 
-    if (btsnd_hcic_write_scan_enable (scan_mode)) {
-        btm_cb.btm_inq_vars.discoverable_mode &= (~BTM_DISCOVERABLE_MASK);
-        btm_cb.btm_inq_vars.discoverable_mode |= inq_mode;
-    } else {
-        return (BTM_NO_RESOURCES);
-    }
-
     /* Change the service class bit if mode has changed */
     p_cod = BTM_ReadDeviceClass();
     BTM_COD_SERVICE_CLASS(service_class, p_cod);
@@ -266,6 +259,13 @@ tBTM_STATUS BTM_SetDiscoverability (UINT16 inq_mode, UINT16 window, UINT16 inter
         (void) BTM_SetDeviceClass (cod);
     }
 
+    if (btsnd_hcic_write_scan_enable (scan_mode)) {
+        btm_cb.btm_inq_vars.discoverable_mode &= (~BTM_DISCOVERABLE_MASK);
+        btm_cb.btm_inq_vars.discoverable_mode |= inq_mode;
+    } else {
+        return (BTM_NO_RESOURCES);
+    }
+
     return (BTM_SUCCESS);
 }
 
diff --git a/components/bt/host/bluedroid/stack/hid/hidd_conn.c b/components/bt/host/bluedroid/stack/hid/hidd_conn.c
index 5a8e36ee599c..5c9164c2c539 100644
--- a/components/bt/host/bluedroid/stack/hid/hidd_conn.c
+++ b/components/bt/host/bluedroid/stack/hid/hidd_conn.c
@@ -775,6 +775,7 @@ tHID_STATUS hidd_conn_send_data(uint8_t channel, uint8_t msg_type, uint8_t param
             }
             return HID_SUCCESS;
         }
+        osi_free(p_buf);
         return HID_ERR_NO_CONNECTION;
     }
 #ifdef REPORT_TRANSFER_TIMESTAMP
diff --git a/components/bt/host/bluedroid/stack/l2cap/l2c_utils.c b/components/bt/host/bluedroid/stack/l2cap/l2c_utils.c
index 64ebcbd4363c..a48eb0d1506f 100644
--- a/components/bt/host/bluedroid/stack/l2cap/l2c_utils.c
+++ b/components/bt/host/bluedroid/stack/l2cap/l2c_utils.c
@@ -25,7 +25,6 @@
 #include <stdlib.h>
 #include <string.h>
 
-#include "osi/allocator.h"
 #include "device/controller.h"
 #include "stack/bt_types.h"
 #include "stack/hcimsgs.h"
@@ -36,6 +35,7 @@
 #include "stack/btm_api.h"
 #include "btm_int.h"
 #include "stack/hcidefs.h"
+#include "bt_common.h"
 #include "osi/allocator.h"
 #include "osi/list.h"
 
diff --git a/components/bt/include/esp32c3/include/esp_bt.h b/components/bt/include/esp32c3/include/esp_bt.h
index 86c902fc9bbc..78daf08428ec 100644
--- a/components/bt/include/esp32c3/include/esp_bt.h
+++ b/components/bt/include/esp32c3/include/esp_bt.h
@@ -30,7 +30,7 @@ extern "C" {
 *
 * @note Please do not modify this value
 */
-#define ESP_BT_CTRL_CONFIG_VERSION      0x02505080
+#define ESP_BT_CTRL_CONFIG_VERSION      0x02509280
 
 /**
 * @brief Internal use only
@@ -376,8 +376,6 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status);
     .connect_en = BT_CTRL_BLE_MASTER,                                      \
     .scan_en = BT_CTRL_BLE_SCAN,                                           \
     .ble_aa_check = BLE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS_ENABLED,     \
-    .ble_log_mode_en = BLE_LOG_MODE_EN,                                    \
-    .ble_log_level = BLE_LOG_LEVEL,                                        \
     .adv_en = BT_CTRL_BLE_ADV,                                             \
 }
 
@@ -504,8 +502,6 @@ typedef struct {
     bool connect_en;                        /*!< True if the connection feature is enabled (default); false otherwise. Configurable in menuconfig.*/
     bool scan_en;                           /*!< True if the scan feature is enabled (default); false otherwise. Configurable in menuconfig.*/
     bool ble_aa_check;                      /*!< True if adds a verification step for the Access Address within the CONNECT_IND PDU; false otherwise. Configurable in menuconfig */
-    uint32_t ble_log_mode_en;               /*!< BLE log mode enable */
-    uint8_t ble_log_level;                  /*!< BLE log level */
     bool adv_en;                            /*!< True if the ADV feature is enabled (default); false otherwise. Configurable in menuconfig.*/
 } esp_bt_controller_config_t;
 
diff --git a/components/efuse/esp32p4/esp_efuse_table_v3.0.c b/components/efuse/esp32p4/esp_efuse_table_v3.0.c
new file mode 100644
index 000000000000..1051c0d9cf59
--- /dev/null
+++ b/components/efuse/esp32p4/esp_efuse_table_v3.0.c
@@ -0,0 +1,2732 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "sdkconfig.h"
+#include "esp_efuse.h"
+#include <assert.h>
+#include "esp_efuse_table_v3.0.h"
+
+// md5_digest_table d471a4221faaafb88f091d4549ecac55
+// This file was generated from the file esp_efuse_table_v3.0.csv. DO NOT CHANGE THIS FILE MANUALLY.
+// If you want to change some fields, you need to change esp_efuse_table_v3.0.csv file
+// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
+// To show efuse_table run the command 'show_efuse_table'.
+
+static const esp_efuse_desc_t WR_DIS[] = {
+    {EFUSE_BLK0, 0, 32}, 	 // [] Disable programming of individual eFuses,
+};
+
+static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
+    {EFUSE_BLK0, 0, 1}, 	 // [] wr_dis of RD_DIS,
+};
+
+static const esp_efuse_desc_t WR_DIS_KM_RND_SWITCH_CYCLE[] = {
+    {EFUSE_BLK0, 1, 1}, 	 // [] wr_dis of KM_RND_SWITCH_CYCLE,
+};
+
+static const esp_efuse_desc_t WR_DIS_KM_DEPLOY_ONLY_ONCE[] = {
+    {EFUSE_BLK0, 1, 1}, 	 // [] wr_dis of KM_DEPLOY_ONLY_ONCE,
+};
+
+static const esp_efuse_desc_t WR_DIS_FORCE_USE_KEY_MANAGER_KEY[] = {
+    {EFUSE_BLK0, 1, 1}, 	 // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY,
+};
+
+static const esp_efuse_desc_t WR_DIS_FORCE_DISABLE_SW_INIT_KEY[] = {
+    {EFUSE_BLK0, 1, 1}, 	 // [] wr_dis of FORCE_DISABLE_SW_INIT_KEY,
+};
+
+static const esp_efuse_desc_t WR_DIS_KM_XTS_KEY_LENGTH_256[] = {
+    {EFUSE_BLK0, 1, 1}, 	 // [] wr_dis of KM_XTS_KEY_LENGTH_256,
+};
+
+static const esp_efuse_desc_t WR_DIS_KM_DEPLOY_ONLY_ONCE_H[] = {
+    {EFUSE_BLK0, 1, 1}, 	 // [] wr_dis of KM_DEPLOY_ONLY_ONCE_H,
+};
+
+static const esp_efuse_desc_t WR_DIS_FORCE_USE_KEY_MANAGER_KEY_H[] = {
+    {EFUSE_BLK0, 1, 1}, 	 // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY_H,
+};
+
+static const esp_efuse_desc_t WR_DIS_LOCK_KM_KEY[] = {
+    {EFUSE_BLK0, 1, 1}, 	 // [] wr_dis of LOCK_KM_KEY,
+};
+
+static const esp_efuse_desc_t WR_DIS_KM_DISABLE_DEPLOY_MODE_H[] = {
+    {EFUSE_BLK0, 1, 1}, 	 // [] wr_dis of KM_DISABLE_DEPLOY_MODE_H,
+};
+
+static const esp_efuse_desc_t WR_DIS_KM_DISABLE_DEPLOY_MODE[] = {
+    {EFUSE_BLK0, 1, 1}, 	 // [] wr_dis of KM_DISABLE_DEPLOY_MODE,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_USB_JTAG,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_FORCE_DOWNLOAD,
+};
+
+static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_TWAI,
+};
+
+static const esp_efuse_desc_t WR_DIS_JTAG_SEL_ENABLE[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of JTAG_SEL_ENABLE,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_PAD_JTAG[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_PAD_JTAG,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT,
+};
+
+static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of WDT_DELAY_SEL,
+};
+
+static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of HYS_EN_PAD,
+};
+
+static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_0[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of PXA0_TIEH_SEL_0,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_WDT[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_WDT,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_SWD[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_SWD,
+};
+
+static const esp_efuse_desc_t WR_DIS_PVT_GLITCH_EN[] = {
+    {EFUSE_BLK0, 3, 1}, 	 // [] wr_dis of PVT_GLITCH_EN,
+};
+
+static const esp_efuse_desc_t WR_DIS_PVT_GLITCH_MODE[] = {
+    {EFUSE_BLK0, 3, 1}, 	 // [] wr_dis of PVT_GLITCH_MODE,
+};
+
+static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
+    {EFUSE_BLK0, 4, 1}, 	 // [] wr_dis of SPI_BOOT_CRYPT_CNT,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
+    {EFUSE_BLK0, 5, 1}, 	 // [] wr_dis of SECURE_BOOT_KEY_REVOKE0,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
+    {EFUSE_BLK0, 6, 1}, 	 // [] wr_dis of SECURE_BOOT_KEY_REVOKE1,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
+    {EFUSE_BLK0, 7, 1}, 	 // [] wr_dis of SECURE_BOOT_KEY_REVOKE2,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0[] = {
+    {EFUSE_BLK0, 8, 1}, 	 // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0_H[] = {
+    {EFUSE_BLK0, 8, 1}, 	 // [] wr_dis of KEY_PURPOSE_0_H,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1[] = {
+    {EFUSE_BLK0, 9, 1}, 	 // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1_H[] = {
+    {EFUSE_BLK0, 9, 1}, 	 // [] wr_dis of KEY_PURPOSE_1_H,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2[] = {
+    {EFUSE_BLK0, 10, 1}, 	 // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2_H[] = {
+    {EFUSE_BLK0, 10, 1}, 	 // [] wr_dis of KEY_PURPOSE_2_H,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3[] = {
+    {EFUSE_BLK0, 11, 1}, 	 // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3_H[] = {
+    {EFUSE_BLK0, 11, 1}, 	 // [] wr_dis of KEY_PURPOSE_3_H,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4[] = {
+    {EFUSE_BLK0, 12, 1}, 	 // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4_H[] = {
+    {EFUSE_BLK0, 12, 1}, 	 // [] wr_dis of KEY_PURPOSE_4_H,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = {
+    {EFUSE_BLK0, 13, 1}, 	 // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5_H[] = {
+    {EFUSE_BLK0, 13, 1}, 	 // [] wr_dis of KEY_PURPOSE_5_H,
+};
+
+static const esp_efuse_desc_t WR_DIS_ECC_FORCE_CONST_TIME[] = {
+    {EFUSE_BLK0, 14, 1}, 	 // [] wr_dis of ECC_FORCE_CONST_TIME,
+};
+
+static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = {
+    {EFUSE_BLK0, 14, 1}, 	 // [] wr_dis of SEC_DPA_LEVEL,
+};
+
+static const esp_efuse_desc_t WR_DIS_XTS_DPA_CLK_ENABLE[] = {
+    {EFUSE_BLK0, 14, 1}, 	 // [] wr_dis of XTS_DPA_CLK_ENABLE,
+};
+
+static const esp_efuse_desc_t WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = {
+    {EFUSE_BLK0, 14, 1}, 	 // [] wr_dis of XTS_DPA_PSEUDO_LEVEL,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
+    {EFUSE_BLK0, 15, 1}, 	 // [] wr_dis of SECURE_BOOT_EN,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
+    {EFUSE_BLK0, 16, 1}, 	 // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE,
+};
+
+static const esp_efuse_desc_t WR_DIS_HP_PWR_SRC_SEL[] = {
+    {EFUSE_BLK0, 17, 1}, 	 // [] wr_dis of HP_PWR_SRC_SEL,
+};
+
+static const esp_efuse_desc_t WR_DIS_FLASH_ECC_EN[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of FLASH_ECC_EN,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE,
+};
+
+static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of FLASH_TPUW,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MODE[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of DIS_DOWNLOAD_MODE,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of DIS_DIRECT_BOOT,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,
+};
+
+static const esp_efuse_desc_t WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of ENABLE_SECURITY_DOWNLOAD,
+};
+
+static const esp_efuse_desc_t WR_DIS_UART_PRINT_CONTROL[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of UART_PRINT_CONTROL,
+};
+
+static const esp_efuse_desc_t WR_DIS_FORCE_SEND_RESUME[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of FORCE_SEND_RESUME,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of SECURE_VERSION,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE,
+};
+
+static const esp_efuse_desc_t WR_DIS_HUK_GEN_STATE[] = {
+    {EFUSE_BLK0, 19, 1}, 	 // [] wr_dis of HUK_GEN_STATE,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLK1[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of BLOCK1,
+};
+
+static const esp_efuse_desc_t WR_DIS_MAC[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [WR_DIS.MAC_FACTORY] wr_dis of MAC,
+};
+
+static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of WAFER_VERSION_MINOR,
+};
+
+static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR_LO[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of WAFER_VERSION_MAJOR_LO,
+};
+
+static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR,
+};
+
+static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of DISABLE_BLK_VERSION_MAJOR,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of BLK_VERSION_MINOR,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of BLK_VERSION_MAJOR,
+};
+
+static const esp_efuse_desc_t WR_DIS_PSRAM_CAP[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of PSRAM_CAP,
+};
+
+static const esp_efuse_desc_t WR_DIS_TEMP[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of TEMP,
+};
+
+static const esp_efuse_desc_t WR_DIS_PSRAM_VENDOR[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of PSRAM_VENDOR,
+};
+
+static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of PKG_VERSION,
+};
+
+static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of BLOCK2,
+};
+
+static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR_HI[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of WAFER_VERSION_MAJOR_HI,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO1_DREF[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO1_DREF,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO2_DREF[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO2_DREF,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO1_MUL[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO1_MUL,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO2_MUL[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO2_MUL,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO3_K[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO3_K,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO3_VOS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO3_VOS,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO3_C[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO3_C,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO4_K[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO4_K,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO4_VOS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO4_VOS,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO4_C[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO4_C,
+};
+
+static const esp_efuse_desc_t WR_DIS_ACTIVE_HP_DBIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of ACTIVE_HP_DBIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_ACTIVE_LP_DBIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of ACTIVE_LP_DBIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_DSLP_DBG[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of DSLP_DBG,
+};
+
+static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of DSLP_LP_DBIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_LP_DCDC_DBIAS_VOL_GAP[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LP_DCDC_DBIAS_VOL_GAP,
+};
+
+static const esp_efuse_desc_t WR_DIS_PVT_400M_BIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of PVT_400M_BIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_PVT_40M_BIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of PVT_40M_BIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_PVT_100M_BIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of PVT_100M_BIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of OPTIONAL_UNIQUE_ID,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_AVE_INITCODE_ATTEN0[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC2_AVE_INITCODE_ATTEN0,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_AVE_INITCODE_ATTEN1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC2_AVE_INITCODE_ATTEN1,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_AVE_INITCODE_ATTEN2[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC2_AVE_INITCODE_ATTEN2,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_AVE_INITCODE_ATTEN3[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC2_AVE_INITCODE_ATTEN3,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN0,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN1,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN2,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN3,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
+    {EFUSE_BLK0, 22, 1}, 	 // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
+};
+
+static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC[] = {
+    {EFUSE_BLK0, 22, 1}, 	 // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0[] = {
+    {EFUSE_BLK0, 23, 1}, 	 // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY1[] = {
+    {EFUSE_BLK0, 24, 1}, 	 // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY2[] = {
+    {EFUSE_BLK0, 25, 1}, 	 // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY3[] = {
+    {EFUSE_BLK0, 26, 1}, 	 // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY4[] = {
+    {EFUSE_BLK0, 27, 1}, 	 // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY5[] = {
+    {EFUSE_BLK0, 28, 1}, 	 // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_HI_DOUT_ATTEN0,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_HI_DOUT_ATTEN1,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_HI_DOUT_ATTEN2,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_HI_DOUT_ATTEN3,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_TEMPERATURE_SENSOR[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of TEMPERATURE_SENSOR,
+};
+
+static const esp_efuse_desc_t WR_DIS_USB_DEVICE_EXCHG_PINS[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of USB_DEVICE_EXCHG_PINS,
+};
+
+static const esp_efuse_desc_t WR_DIS_USB_OTG11_EXCHG_PINS[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of USB_OTG11_EXCHG_PINS,
+};
+
+static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = {
+    {EFUSE_BLK0, 31, 1}, 	 // [] wr_dis of SOFT_DIS_JTAG,
+};
+
+static const esp_efuse_desc_t RD_DIS[] = {
+    {EFUSE_BLK0, 32, 7}, 	 // [] Disable reading from BlOCK4-10,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0[] = {
+    {EFUSE_BLK0, 32, 1}, 	 // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY1[] = {
+    {EFUSE_BLK0, 33, 1}, 	 // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY2[] = {
+    {EFUSE_BLK0, 34, 1}, 	 // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY3[] = {
+    {EFUSE_BLK0, 35, 1}, 	 // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4[] = {
+    {EFUSE_BLK0, 36, 1}, 	 // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY5[] = {
+    {EFUSE_BLK0, 37, 1}, 	 // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_HI_DOUT_ATTEN0,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_HI_DOUT_ATTEN1,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_HI_DOUT_ATTEN2,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_HI_DOUT_ATTEN3,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_TEMPERATURE_SENSOR[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of TEMPERATURE_SENSOR,
+};
+
+static const esp_efuse_desc_t RD_DIS_USB_DEVICE_EXCHG_PINS[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of USB_DEVICE_EXCHG_PINS,
+};
+
+static const esp_efuse_desc_t RD_DIS_USB_OTG11_EXCHG_PINS[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of USB_OTG11_EXCHG_PINS,
+};
+
+static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1[] = {
+    {EFUSE_BLK0, 39, 2}, 	 // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled,
+};
+
+static const esp_efuse_desc_t DIS_USB_JTAG[] = {
+    {EFUSE_BLK0, 41, 1}, 	 // [] Set this bit to disable function of usb switch to jtag in module of usb device,
+};
+
+static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2[] = {
+    {EFUSE_BLK0, 42, 1}, 	 // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled,
+};
+
+static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
+    {EFUSE_BLK0, 44, 1}, 	 // [] Set this bit to disable the function that forces chip into download mode,
+};
+
+static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = {
+    {EFUSE_BLK0, 45, 1}, 	 // [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download,
+};
+
+static const esp_efuse_desc_t DIS_TWAI[] = {
+    {EFUSE_BLK0, 46, 1}, 	 // [] Set this bit to disable TWAI function,
+};
+
+static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = {
+    {EFUSE_BLK0, 47, 1}, 	 // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0,
+};
+
+static const esp_efuse_desc_t SOFT_DIS_JTAG[] = {
+    {EFUSE_BLK0, 48, 3}, 	 // [] Set odd bits to disable JTAG in the soft way. JTAG can be enabled in HMAC module,
+};
+
+static const esp_efuse_desc_t DIS_PAD_JTAG[] = {
+    {EFUSE_BLK0, 51, 1}, 	 // [] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently,
+};
+
+static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
+    {EFUSE_BLK0, 52, 1}, 	 // [] Set this bit to disable flash manual encrypt function (except in SPI boot mode),
+};
+
+static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6[] = {
+    {EFUSE_BLK0, 53, 4}, 	 // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled,
+};
+
+static const esp_efuse_desc_t USB_PHY_SEL[] = {
+    {EFUSE_BLK0, 57, 1}, 	 // [] 0: intphy(gpio24/25) <---> usb_device 1: intphy(26/27) <---> usb_otg11.1: intphy(gpio26/27) <---> usb_device 1: intphy(24/25) <---> usb_otg11,
+};
+
+static const esp_efuse_desc_t HUK_GEN_STATE[] = {
+    {EFUSE_BLK0, 58, 5}, 	 // [] Set the bits to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid,
+};
+
+static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7[] = {
+    {EFUSE_BLK0, 63, 1}, 	 // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled,
+};
+
+static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10[] = {
+    {EFUSE_BLK0, 64, 3}, 	 // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled,
+};
+
+static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11[] = {
+    {EFUSE_BLK0, 67, 1}, 	 // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled,
+};
+
+static const esp_efuse_desc_t KM_RND_SWITCH_CYCLE[] = {
+    {EFUSE_BLK0, 68, 1}, 	 // [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles,
+};
+
+static const esp_efuse_desc_t KM_DEPLOY_ONLY_ONCE[] = {
+    {EFUSE_BLK0, 69, 4}, 	 // [] EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: {EFUSE_KM_DEPLOY_ONLY_ONCE_H; EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram,
+    {EFUSE_BLK0, 118, 1}, 	 // [] EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: {EFUSE_KM_DEPLOY_ONLY_ONCE_H; EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram,
+};
+
+static const esp_efuse_desc_t FORCE_USE_KEY_MANAGER_KEY[] = {
+    {EFUSE_BLK0, 73, 4}, 	 // [] EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H; EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram,
+    {EFUSE_BLK0, 119, 1}, 	 // [] EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H; EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram,
+};
+
+static const esp_efuse_desc_t FORCE_DISABLE_SW_INIT_KEY[] = {
+    {EFUSE_BLK0, 77, 1}, 	 // [] Set this bit to disable software written init key; and force use efuse_init_key,
+};
+
+static const esp_efuse_desc_t KM_XTS_KEY_LENGTH_256[] = {
+    {EFUSE_BLK0, 78, 1}, 	 // [] Set this bit to config flash encryption xts-512 key; else use xts-256 key when using the key manager,
+};
+
+static const esp_efuse_desc_t ECC_FORCE_CONST_TIME[] = {
+    {EFUSE_BLK0, 79, 1}, 	 // [] Set this bit to permanently turn on ECC const-time mode,
+};
+
+static const esp_efuse_desc_t WDT_DELAY_SEL[] = {
+    {EFUSE_BLK0, 81, 1}, 	 // [] Select lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1)),
+};
+
+static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = {
+    {EFUSE_BLK0, 82, 3}, 	 // [] Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"},
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = {
+    {EFUSE_BLK0, 85, 1}, 	 // [] Revoke 1st secure boot key,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = {
+    {EFUSE_BLK0, 86, 1}, 	 // [] Revoke 2nd secure boot key,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = {
+    {EFUSE_BLK0, 87, 1}, 	 // [] Revoke 3rd secure boot key,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_0[] = {
+    {EFUSE_BLK0, 88, 4}, 	 // [KEY0_PURPOSE] Purpose of Key0,
+    {EFUSE_BLK0, 155, 1}, 	 // [] Purpose of Key0. The 5-th bit,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_1[] = {
+    {EFUSE_BLK0, 92, 4}, 	 // [KEY1_PURPOSE] Purpose of Key1,
+    {EFUSE_BLK0, 156, 1}, 	 // [] Purpose of Key1. The 5-th bit,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_2[] = {
+    {EFUSE_BLK0, 96, 4}, 	 // [KEY2_PURPOSE] Purpose of Key2,
+    {EFUSE_BLK0, 157, 1}, 	 // [] Purpose of Key2. The 5-th bit,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_3[] = {
+    {EFUSE_BLK0, 100, 4}, 	 // [KEY3_PURPOSE] Purpose of Key3,
+    {EFUSE_BLK0, 158, 1}, 	 // [] Purpose of Key3. The 5-th bit,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_4[] = {
+    {EFUSE_BLK0, 104, 4}, 	 // [KEY4_PURPOSE] Purpose of Key4,
+    {EFUSE_BLK0, 159, 1}, 	 // [] Purpose of Key4. The 5-th bit,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_5[] = {
+    {EFUSE_BLK0, 108, 4}, 	 // [KEY5_PURPOSE] Purpose of Key5,
+    {EFUSE_BLK0, 164, 1}, 	 // [] Purpose of Key5. The 5-th bit,
+};
+
+static const esp_efuse_desc_t SEC_DPA_LEVEL[] = {
+    {EFUSE_BLK0, 112, 2}, 	 // [] Configures the clock random divide mode to determine the dpa secure level,
+};
+
+static const esp_efuse_desc_t XTS_DPA_CLK_ENABLE[] = {
+    {EFUSE_BLK0, 115, 1}, 	 // [] Sets this bit to enable xts clock anti-dpa attack function,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_EN[] = {
+    {EFUSE_BLK0, 116, 1}, 	 // [] Set this bit to enable secure boot,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
+    {EFUSE_BLK0, 117, 1}, 	 // [] Set this bit to enable revoking aggressive secure boot,
+};
+
+static const esp_efuse_desc_t FLASH_ECC_EN[] = {
+    {EFUSE_BLK0, 122, 1}, 	 // [] Set this bit to enable ECC for flash boot,
+};
+
+static const esp_efuse_desc_t DIS_USB_OTG_DOWNLOAD_MODE[] = {
+    {EFUSE_BLK0, 123, 1}, 	 // [] Set this bit to disable download via USB-OTG,
+};
+
+static const esp_efuse_desc_t FLASH_TPUW[] = {
+    {EFUSE_BLK0, 124, 4}, 	 // [] Configures flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the configurable value. Otherwise; the waiting time is 30,
+};
+
+static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = {
+    {EFUSE_BLK0, 128, 1}, 	 // [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 4; 5; 6; 7),
+};
+
+static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = {
+    {EFUSE_BLK0, 129, 1}, 	 // [] Set this bit to disable direct boot mode,
+};
+
+static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
+    {EFUSE_BLK0, 130, 1}, 	 // [] Set this bit to disable USB-Serial-JTAG print during rom boot,
+};
+
+static const esp_efuse_desc_t LOCK_KM_KEY[] = {
+    {EFUSE_BLK0, 131, 1}, 	 // [] set this bit to lock the key manager key after deploy,
+};
+
+static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
+    {EFUSE_BLK0, 132, 1}, 	 // [] Set this bit to disable the USB-Serial-JTAG download function,
+};
+
+static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = {
+    {EFUSE_BLK0, 133, 1}, 	 // [] Set this bit to enable security download mode,
+};
+
+static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
+    {EFUSE_BLK0, 134, 2}, 	 // [] Set the type of UART printing; 00: force enable printing; 01: enable printing when GPIO8 is reset at low level; 10: enable printing when GPIO8 is reset at high level; 11: force disable printing,
+};
+
+static const esp_efuse_desc_t FORCE_SEND_RESUME[] = {
+    {EFUSE_BLK0, 136, 1}, 	 // [] Set this bit to force ROM code to send a resume command during SPI boot,
+};
+
+static const esp_efuse_desc_t SECURE_VERSION[] = {
+    {EFUSE_BLK0, 137, 16}, 	 // [] Secure version used by ESP-IDF anti-rollback feature,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = {
+    {EFUSE_BLK0, 153, 1}, 	 // [] Represents whether secure boot do fast verification on wake is disabled. 0: enabled 1: disabled,
+};
+
+static const esp_efuse_desc_t HYS_EN_PAD[] = {
+    {EFUSE_BLK0, 154, 1}, 	 // [] Set bits to enable hysteresis function of PAD0~27,
+};
+
+static const esp_efuse_desc_t PXA0_TIEH_SEL_0[] = {
+    {EFUSE_BLK0, 160, 2}, 	 // [] Output LDO VO0 tieh source select. 0: 1'b1 1: sdmmc1 2: reg 3:sdmmc0,
+};
+
+static const esp_efuse_desc_t PVT_GLITCH_EN[] = {
+    {EFUSE_BLK0, 162, 1}, 	 // [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable,
+};
+
+static const esp_efuse_desc_t KM_DISABLE_DEPLOY_MODE[] = {
+    {EFUSE_BLK0, 168, 4}, 	 // [] EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H; EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set each bit to control whether corresponding key's deploy mode of new value deployment is disabled. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram,
+    {EFUSE_BLK0, 167, 1}, 	 // [] EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H; EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set each bit to control whether corresponding key's deploy mode of new value deployment is disabled. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram,
+};
+
+static const esp_efuse_desc_t XTS_DPA_PSEUDO_LEVEL[] = {
+    {EFUSE_BLK0, 176, 2}, 	 // [] Sets this bit to control the xts pseudo-round anti-dpa attack function. 0: controlled by register. 1-3: the higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation,
+};
+
+static const esp_efuse_desc_t HP_PWR_SRC_SEL[] = {
+    {EFUSE_BLK0, 178, 1}, 	 // [] HP system power source select. 0:LDO  1: DCDC,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_SHA384_EN[] = {
+    {EFUSE_BLK0, 179, 1}, 	 // [] Represents whether secure boot using SHA-384 is enabled. 0: disable 1: enable,
+};
+
+static const esp_efuse_desc_t DIS_WDT[] = {
+    {EFUSE_BLK0, 180, 1}, 	 // [] Set this bit to disable watch dog,
+};
+
+static const esp_efuse_desc_t DIS_SWD[] = {
+    {EFUSE_BLK0, 181, 1}, 	 // [] Set bit to disable super-watchdog,
+};
+
+static const esp_efuse_desc_t PVT_GLITCH_MODE[] = {
+    {EFUSE_BLK0, 182, 2}, 	 // [] Use to configure glitch mode,
+};
+
+static const esp_efuse_desc_t MAC[] = {
+    {EFUSE_BLK1, 40, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 32, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 24, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 16, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 8, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 0, 8}, 	 // [MAC_FACTORY] MAC address,
+};
+
+static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
+    {EFUSE_BLK1, 64, 4}, 	 // [] Minor chip version,
+};
+
+static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
+    {EFUSE_BLK1, 68, 2}, 	 // [] Major chip version (lower 2 bits),
+    {EFUSE_BLK1, 87, 1}, 	 // [] Major chip version (MSB),
+};
+
+static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
+    {EFUSE_BLK1, 70, 1}, 	 // [] Disables check of wafer version major,
+};
+
+static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
+    {EFUSE_BLK1, 71, 1}, 	 // [] Disables check of blk version major,
+};
+
+static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
+    {EFUSE_BLK1, 72, 3}, 	 // [] BLK_VERSION_MINOR of BLOCK2,
+};
+
+static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
+    {EFUSE_BLK1, 75, 2}, 	 // [] BLK_VERSION_MAJOR of BLOCK2,
+};
+
+static const esp_efuse_desc_t PSRAM_CAP[] = {
+    {EFUSE_BLK1, 77, 3}, 	 // [] PSRAM capacity,
+};
+
+static const esp_efuse_desc_t TEMP[] = {
+    {EFUSE_BLK1, 80, 2}, 	 // [] Operating temperature of the ESP chip,
+};
+
+static const esp_efuse_desc_t PSRAM_VENDOR[] = {
+    {EFUSE_BLK1, 82, 2}, 	 // [] PSRAM vendor,
+};
+
+static const esp_efuse_desc_t PKG_VERSION[] = {
+    {EFUSE_BLK1, 84, 3}, 	 // [] Package version,
+};
+
+static const esp_efuse_desc_t LDO_VO1_DREF[] = {
+    {EFUSE_BLK1, 88, 4}, 	 // [] Output VO1 parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO2_DREF[] = {
+    {EFUSE_BLK1, 92, 4}, 	 // [] Output VO2 parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO1_MUL[] = {
+    {EFUSE_BLK1, 96, 3}, 	 // [] Output VO1 parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO2_MUL[] = {
+    {EFUSE_BLK1, 99, 3}, 	 // [] Output VO2 parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO3_K[] = {
+    {EFUSE_BLK1, 102, 8}, 	 // [] Output VO3 calibration parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO3_VOS[] = {
+    {EFUSE_BLK1, 110, 6}, 	 // [] Output VO3 calibration parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO3_C[] = {
+    {EFUSE_BLK1, 116, 6}, 	 // [] Output VO3 calibration parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO4_K[] = {
+    {EFUSE_BLK1, 122, 8}, 	 // [] Output VO4 calibration parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO4_VOS[] = {
+    {EFUSE_BLK1, 130, 6}, 	 // [] Output VO4 calibration parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO4_C[] = {
+    {EFUSE_BLK1, 136, 6}, 	 // [] Output VO4 calibration parameter,
+};
+
+static const esp_efuse_desc_t ACTIVE_HP_DBIAS[] = {
+    {EFUSE_BLK1, 144, 4}, 	 // [] Active HP DBIAS of fixed voltage,
+};
+
+static const esp_efuse_desc_t ACTIVE_LP_DBIAS[] = {
+    {EFUSE_BLK1, 148, 4}, 	 // [] Active LP DBIAS of fixed voltage,
+};
+
+static const esp_efuse_desc_t DSLP_DBG[] = {
+    {EFUSE_BLK1, 156, 4}, 	 // [] DSLP BDG of fixed voltage,
+};
+
+static const esp_efuse_desc_t DSLP_LP_DBIAS[] = {
+    {EFUSE_BLK1, 160, 5}, 	 // [] DSLP LP DBIAS of fixed voltage,
+};
+
+static const esp_efuse_desc_t LP_DCDC_DBIAS_VOL_GAP[] = {
+    {EFUSE_BLK1, 165, 5}, 	 // [] DBIAS gap between LP and DCDC,
+};
+
+static const esp_efuse_desc_t PVT_400M_BIAS[] = {
+    {EFUSE_BLK1, 171, 5}, 	 // [] PVT_DCM_VSET when the CPU is at 400M,
+};
+
+static const esp_efuse_desc_t PVT_40M_BIAS[] = {
+    {EFUSE_BLK1, 176, 5}, 	 // [] PVT_DCM_VSET corresponding to about 0.9V fixed voltage when the CPU is at 40M,
+};
+
+static const esp_efuse_desc_t PVT_100M_BIAS[] = {
+    {EFUSE_BLK1, 181, 5}, 	 // [] PVT_DCM_VSET corresponding to about 1.0V fixed voltage when the CPU is at 100M,
+};
+
+static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
+    {EFUSE_BLK2, 0, 128}, 	 // [] Optional unique 128-bit ID,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN0[] = {
+    {EFUSE_BLK2, 128, 10}, 	 // [] Average initcode of ADC1 atten0,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN1[] = {
+    {EFUSE_BLK2, 138, 10}, 	 // [] Average initcode of ADC1 atten1,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN2[] = {
+    {EFUSE_BLK2, 148, 10}, 	 // [] Average initcode of ADC1 atten2,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN3[] = {
+    {EFUSE_BLK2, 158, 10}, 	 // [] Average initcode of ADC1 atten3,
+};
+
+static const esp_efuse_desc_t ADC2_AVE_INITCODE_ATTEN0[] = {
+    {EFUSE_BLK2, 168, 10}, 	 // [] Average initcode of ADC2 atten0,
+};
+
+static const esp_efuse_desc_t ADC2_AVE_INITCODE_ATTEN1[] = {
+    {EFUSE_BLK2, 178, 10}, 	 // [] Average initcode of ADC2 atten1,
+};
+
+static const esp_efuse_desc_t ADC2_AVE_INITCODE_ATTEN2[] = {
+    {EFUSE_BLK2, 188, 10}, 	 // [] Average initcode of ADC2 atten2,
+};
+
+static const esp_efuse_desc_t ADC2_AVE_INITCODE_ATTEN3[] = {
+    {EFUSE_BLK2, 198, 10}, 	 // [] Average initcode of ADC2 atten3,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK2, 208, 10}, 	 // [] HI_DOUT of ADC1 atten0,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK2, 218, 10}, 	 // [] HI_DOUT of ADC1 atten1,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK2, 228, 10}, 	 // [] HI_DOUT of ADC1 atten2,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK2, 238, 10}, 	 // [] HI_DOUT of ADC1 atten3,
+};
+
+static const esp_efuse_desc_t USER_DATA[] = {
+    {EFUSE_BLK3, 0, 256}, 	 // [BLOCK_USR_DATA] User data,
+};
+
+static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = {
+    {EFUSE_BLK3, 200, 48}, 	 // [MAC_CUSTOM CUSTOM_MAC] Custom MAC,
+};
+
+static const esp_efuse_desc_t KEY0[] = {
+    {EFUSE_BLK4, 0, 256}, 	 // [BLOCK_KEY0] Key0 or user data,
+};
+
+static const esp_efuse_desc_t KEY1[] = {
+    {EFUSE_BLK5, 0, 256}, 	 // [BLOCK_KEY1] Key1 or user data,
+};
+
+static const esp_efuse_desc_t KEY2[] = {
+    {EFUSE_BLK6, 0, 256}, 	 // [BLOCK_KEY2] Key2 or user data,
+};
+
+static const esp_efuse_desc_t KEY3[] = {
+    {EFUSE_BLK7, 0, 256}, 	 // [BLOCK_KEY3] Key3 or user data,
+};
+
+static const esp_efuse_desc_t KEY4[] = {
+    {EFUSE_BLK8, 0, 256}, 	 // [BLOCK_KEY4] Key4 or user data,
+};
+
+static const esp_efuse_desc_t KEY5[] = {
+    {EFUSE_BLK9, 0, 256}, 	 // [BLOCK_KEY5] Key5 or user data,
+};
+
+static const esp_efuse_desc_t ADC2_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK10, 0, 10}, 	 // [] HI_DOUT of ADC2 atten0,
+};
+
+static const esp_efuse_desc_t ADC2_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK10, 10, 10}, 	 // [] HI_DOUT of ADC2 atten1,
+};
+
+static const esp_efuse_desc_t ADC2_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK10, 20, 10}, 	 // [] HI_DOUT of ADC2 atten2,
+};
+
+static const esp_efuse_desc_t ADC2_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK10, 30, 10}, 	 // [] HI_DOUT of ADC2 atten3,
+};
+
+static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 40, 4}, 	 // [] Gap between ADC1_ch0 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 44, 4}, 	 // [] Gap between ADC1_ch1 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 48, 4}, 	 // [] Gap between ADC1_ch2 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 52, 4}, 	 // [] Gap between ADC1_ch3 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 56, 4}, 	 // [] Gap between ADC1_ch4 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 60, 4}, 	 // [] Gap between ADC1_ch5 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH6_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 64, 4}, 	 // [] Gap between ADC1_ch6 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH7_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 68, 4}, 	 // [] Gap between ADC1_ch7 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC2_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 72, 4}, 	 // [] Gap between ADC2_ch0 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC2_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 76, 4}, 	 // [] Gap between ADC2_ch1 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC2_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 80, 4}, 	 // [] Gap between ADC2_ch2 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC2_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 84, 4}, 	 // [] Gap between ADC2_ch3 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC2_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 88, 4}, 	 // [] Gap between ADC2_ch4 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC2_CH5_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 92, 4}, 	 // [] Gap between ADC2_ch5 and average initcode,
+};
+
+static const esp_efuse_desc_t TEMPERATURE_SENSOR[] = {
+    {EFUSE_BLK10, 96, 10}, 	 // [] Temperature calibration data,
+};
+
+static const esp_efuse_desc_t USB_DEVICE_EXCHG_PINS[] = {
+    {EFUSE_BLK10, 228, 1}, 	 // [] Enable usb device exchange pins of D+ and D-,
+};
+
+static const esp_efuse_desc_t USB_OTG11_EXCHG_PINS[] = {
+    {EFUSE_BLK10, 229, 1}, 	 // [] Enable usb otg11 exchange pins of D+ and D-,
+};
+
+
+
+
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = {
+    &WR_DIS[0],    		// [] Disable programming of individual eFuses
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
+    &WR_DIS_RD_DIS[0],    		// [] wr_dis of RD_DIS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[] = {
+    &WR_DIS_KM_RND_SWITCH_CYCLE[0],    		// [] wr_dis of KM_RND_SWITCH_CYCLE
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[] = {
+    &WR_DIS_KM_DEPLOY_ONLY_ONCE[0],    		// [] wr_dis of KM_DEPLOY_ONLY_ONCE
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[] = {
+    &WR_DIS_FORCE_USE_KEY_MANAGER_KEY[0],    		// [] wr_dis of FORCE_USE_KEY_MANAGER_KEY
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[] = {
+    &WR_DIS_FORCE_DISABLE_SW_INIT_KEY[0],    		// [] wr_dis of FORCE_DISABLE_SW_INIT_KEY
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_XTS_KEY_LENGTH_256[] = {
+    &WR_DIS_KM_XTS_KEY_LENGTH_256[0],    		// [] wr_dis of KM_XTS_KEY_LENGTH_256
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE_H[] = {
+    &WR_DIS_KM_DEPLOY_ONLY_ONCE_H[0],    		// [] wr_dis of KM_DEPLOY_ONLY_ONCE_H
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY_H[] = {
+    &WR_DIS_FORCE_USE_KEY_MANAGER_KEY_H[0],    		// [] wr_dis of FORCE_USE_KEY_MANAGER_KEY_H
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[] = {
+    &WR_DIS_LOCK_KM_KEY[0],    		// [] wr_dis of LOCK_KM_KEY
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE_H[] = {
+    &WR_DIS_KM_DISABLE_DEPLOY_MODE_H[0],    		// [] wr_dis of KM_DISABLE_DEPLOY_MODE_H
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[] = {
+    &WR_DIS_KM_DISABLE_DEPLOY_MODE[0],    		// [] wr_dis of KM_DISABLE_DEPLOY_MODE
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = {
+    &WR_DIS_DIS_USB_JTAG[0],    		// [] wr_dis of DIS_USB_JTAG
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = {
+    &WR_DIS_DIS_FORCE_DOWNLOAD[0],    		// [] wr_dis of DIS_FORCE_DOWNLOAD
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
+    &WR_DIS_SPI_DOWNLOAD_MSPI_DIS[0],    		// [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = {
+    &WR_DIS_DIS_TWAI[0],    		// [] wr_dis of DIS_TWAI
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[] = {
+    &WR_DIS_JTAG_SEL_ENABLE[0],    		// [] wr_dis of JTAG_SEL_ENABLE
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[] = {
+    &WR_DIS_DIS_PAD_JTAG[0],    		// [] wr_dis of DIS_PAD_JTAG
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
+    &WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[0],    		// [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = {
+    &WR_DIS_WDT_DELAY_SEL[0],    		// [] wr_dis of WDT_DELAY_SEL
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[] = {
+    &WR_DIS_HYS_EN_PAD[0],    		// [] wr_dis of HYS_EN_PAD
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[] = {
+    &WR_DIS_PXA0_TIEH_SEL_0[0],    		// [] wr_dis of PXA0_TIEH_SEL_0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[] = {
+    &WR_DIS_DIS_WDT[0],    		// [] wr_dis of DIS_WDT
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[] = {
+    &WR_DIS_DIS_SWD[0],    		// [] wr_dis of DIS_SWD
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_EN[] = {
+    &WR_DIS_PVT_GLITCH_EN[0],    		// [] wr_dis of PVT_GLITCH_EN
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_MODE[] = {
+    &WR_DIS_PVT_GLITCH_MODE[0],    		// [] wr_dis of PVT_GLITCH_MODE
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
+    &WR_DIS_SPI_BOOT_CRYPT_CNT[0],    		// [] wr_dis of SPI_BOOT_CRYPT_CNT
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
+    &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0],    		// [] wr_dis of SECURE_BOOT_KEY_REVOKE0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
+    &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0],    		// [] wr_dis of SECURE_BOOT_KEY_REVOKE1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
+    &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0],    		// [] wr_dis of SECURE_BOOT_KEY_REVOKE2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[] = {
+    &WR_DIS_KEY_PURPOSE_0[0],    		// [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0_H[] = {
+    &WR_DIS_KEY_PURPOSE_0_H[0],    		// [] wr_dis of KEY_PURPOSE_0_H
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[] = {
+    &WR_DIS_KEY_PURPOSE_1[0],    		// [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1_H[] = {
+    &WR_DIS_KEY_PURPOSE_1_H[0],    		// [] wr_dis of KEY_PURPOSE_1_H
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[] = {
+    &WR_DIS_KEY_PURPOSE_2[0],    		// [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2_H[] = {
+    &WR_DIS_KEY_PURPOSE_2_H[0],    		// [] wr_dis of KEY_PURPOSE_2_H
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[] = {
+    &WR_DIS_KEY_PURPOSE_3[0],    		// [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3_H[] = {
+    &WR_DIS_KEY_PURPOSE_3_H[0],    		// [] wr_dis of KEY_PURPOSE_3_H
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[] = {
+    &WR_DIS_KEY_PURPOSE_4[0],    		// [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4_H[] = {
+    &WR_DIS_KEY_PURPOSE_4_H[0],    		// [] wr_dis of KEY_PURPOSE_4_H
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = {
+    &WR_DIS_KEY_PURPOSE_5[0],    		// [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5_H[] = {
+    &WR_DIS_KEY_PURPOSE_5_H[0],    		// [] wr_dis of KEY_PURPOSE_5_H
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[] = {
+    &WR_DIS_ECC_FORCE_CONST_TIME[0],    		// [] wr_dis of ECC_FORCE_CONST_TIME
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = {
+    &WR_DIS_SEC_DPA_LEVEL[0],    		// [] wr_dis of SEC_DPA_LEVEL
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[] = {
+    &WR_DIS_XTS_DPA_CLK_ENABLE[0],    		// [] wr_dis of XTS_DPA_CLK_ENABLE
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = {
+    &WR_DIS_XTS_DPA_PSEUDO_LEVEL[0],    		// [] wr_dis of XTS_DPA_PSEUDO_LEVEL
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
+    &WR_DIS_SECURE_BOOT_EN[0],    		// [] wr_dis of SECURE_BOOT_EN
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
+    &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[] = {
+    &WR_DIS_HP_PWR_SRC_SEL[0],    		// [] wr_dis of HP_PWR_SRC_SEL
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[] = {
+    &WR_DIS_FLASH_ECC_EN[0],    		// [] wr_dis of FLASH_ECC_EN
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[] = {
+    &WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[0],    		// [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = {
+    &WR_DIS_FLASH_TPUW[0],    		// [] wr_dis of FLASH_TPUW
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[] = {
+    &WR_DIS_DIS_DOWNLOAD_MODE[0],    		// [] wr_dis of DIS_DOWNLOAD_MODE
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = {
+    &WR_DIS_DIS_DIRECT_BOOT[0],    		// [] wr_dis of DIS_DIRECT_BOOT
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
+    &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0],    		// [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
+    &WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0],    		// [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = {
+    &WR_DIS_ENABLE_SECURITY_DOWNLOAD[0],    		// [] wr_dis of ENABLE_SECURITY_DOWNLOAD
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[] = {
+    &WR_DIS_UART_PRINT_CONTROL[0],    		// [] wr_dis of UART_PRINT_CONTROL
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[] = {
+    &WR_DIS_FORCE_SEND_RESUME[0],    		// [] wr_dis of FORCE_SEND_RESUME
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = {
+    &WR_DIS_SECURE_VERSION[0],    		// [] wr_dis of SECURE_VERSION
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
+    &WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[0],    		// [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[] = {
+    &WR_DIS_HUK_GEN_STATE[0],    		// [] wr_dis of HUK_GEN_STATE
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
+    &WR_DIS_BLK1[0],    		// [] wr_dis of BLOCK1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = {
+    &WR_DIS_MAC[0],    		// [WR_DIS.MAC_FACTORY] wr_dis of MAC
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = {
+    &WR_DIS_WAFER_VERSION_MINOR[0],    		// [] wr_dis of WAFER_VERSION_MINOR
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_LO[] = {
+    &WR_DIS_WAFER_VERSION_MAJOR_LO[0],    		// [] wr_dis of WAFER_VERSION_MAJOR_LO
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
+    &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0],    		// [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
+    &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0],    		// [] wr_dis of DISABLE_BLK_VERSION_MAJOR
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = {
+    &WR_DIS_BLK_VERSION_MINOR[0],    		// [] wr_dis of BLK_VERSION_MINOR
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = {
+    &WR_DIS_BLK_VERSION_MAJOR[0],    		// [] wr_dis of BLK_VERSION_MAJOR
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[] = {
+    &WR_DIS_PSRAM_CAP[0],    		// [] wr_dis of PSRAM_CAP
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[] = {
+    &WR_DIS_TEMP[0],    		// [] wr_dis of TEMP
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[] = {
+    &WR_DIS_PSRAM_VENDOR[0],    		// [] wr_dis of PSRAM_VENDOR
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = {
+    &WR_DIS_PKG_VERSION[0],    		// [] wr_dis of PKG_VERSION
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
+    &WR_DIS_SYS_DATA_PART1[0],    		// [] wr_dis of BLOCK2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_HI[] = {
+    &WR_DIS_WAFER_VERSION_MAJOR_HI[0],    		// [] wr_dis of WAFER_VERSION_MAJOR_HI
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[] = {
+    &WR_DIS_LDO_VO1_DREF[0],    		// [] wr_dis of LDO_VO1_DREF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[] = {
+    &WR_DIS_LDO_VO2_DREF[0],    		// [] wr_dis of LDO_VO2_DREF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[] = {
+    &WR_DIS_LDO_VO1_MUL[0],    		// [] wr_dis of LDO_VO1_MUL
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[] = {
+    &WR_DIS_LDO_VO2_MUL[0],    		// [] wr_dis of LDO_VO2_MUL
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[] = {
+    &WR_DIS_LDO_VO3_K[0],    		// [] wr_dis of LDO_VO3_K
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[] = {
+    &WR_DIS_LDO_VO3_VOS[0],    		// [] wr_dis of LDO_VO3_VOS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[] = {
+    &WR_DIS_LDO_VO3_C[0],    		// [] wr_dis of LDO_VO3_C
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[] = {
+    &WR_DIS_LDO_VO4_K[0],    		// [] wr_dis of LDO_VO4_K
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[] = {
+    &WR_DIS_LDO_VO4_VOS[0],    		// [] wr_dis of LDO_VO4_VOS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[] = {
+    &WR_DIS_LDO_VO4_C[0],    		// [] wr_dis of LDO_VO4_C
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[] = {
+    &WR_DIS_ACTIVE_HP_DBIAS[0],    		// [] wr_dis of ACTIVE_HP_DBIAS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[] = {
+    &WR_DIS_ACTIVE_LP_DBIAS[0],    		// [] wr_dis of ACTIVE_LP_DBIAS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[] = {
+    &WR_DIS_DSLP_DBG[0],    		// [] wr_dis of DSLP_DBG
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[] = {
+    &WR_DIS_DSLP_LP_DBIAS[0],    		// [] wr_dis of DSLP_LP_DBIAS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[] = {
+    &WR_DIS_LP_DCDC_DBIAS_VOL_GAP[0],    		// [] wr_dis of LP_DCDC_DBIAS_VOL_GAP
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_400M_BIAS[] = {
+    &WR_DIS_PVT_400M_BIAS[0],    		// [] wr_dis of PVT_400M_BIAS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_40M_BIAS[] = {
+    &WR_DIS_PVT_40M_BIAS[0],    		// [] wr_dis of PVT_40M_BIAS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_100M_BIAS[] = {
+    &WR_DIS_PVT_100M_BIAS[0],    		// [] wr_dis of PVT_100M_BIAS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
+    &WR_DIS_OPTIONAL_UNIQUE_ID[0],    		// [] wr_dis of OPTIONAL_UNIQUE_ID
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN0[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN1[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN2[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN3[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[] = {
+    &WR_DIS_ADC2_AVE_INITCODE_ATTEN0[0],    		// [] wr_dis of ADC2_AVE_INITCODE_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[] = {
+    &WR_DIS_ADC2_AVE_INITCODE_ATTEN1[0],    		// [] wr_dis of ADC2_AVE_INITCODE_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[] = {
+    &WR_DIS_ADC2_AVE_INITCODE_ATTEN2[0],    		// [] wr_dis of ADC2_AVE_INITCODE_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[] = {
+    &WR_DIS_ADC2_AVE_INITCODE_ATTEN3[0],    		// [] wr_dis of ADC2_AVE_INITCODE_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN0[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN1[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN2[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN3[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
+    &WR_DIS_BLOCK_USR_DATA[0],    		// [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = {
+    &WR_DIS_CUSTOM_MAC[0],    		// [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = {
+    &WR_DIS_BLOCK_KEY0[0],    		// [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[] = {
+    &WR_DIS_BLOCK_KEY1[0],    		// [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[] = {
+    &WR_DIS_BLOCK_KEY2[0],    		// [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[] = {
+    &WR_DIS_BLOCK_KEY3[0],    		// [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = {
+    &WR_DIS_BLOCK_KEY4[0],    		// [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = {
+    &WR_DIS_BLOCK_KEY5[0],    		// [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = {
+    &WR_DIS_BLOCK_SYS_DATA2[0],    		// [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[] = {
+    &WR_DIS_ADC2_HI_DOUT_ATTEN0[0],    		// [] wr_dis of ADC2_HI_DOUT_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[] = {
+    &WR_DIS_ADC2_HI_DOUT_ATTEN1[0],    		// [] wr_dis of ADC2_HI_DOUT_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[] = {
+    &WR_DIS_ADC2_HI_DOUT_ATTEN2[0],    		// [] wr_dis of ADC2_HI_DOUT_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[] = {
+    &WR_DIS_ADC2_HI_DOUT_ATTEN3[0],    		// [] wr_dis of ADC2_HI_DOUT_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[] = {
+    &WR_DIS_TEMPERATURE_SENSOR[0],    		// [] wr_dis of TEMPERATURE_SENSOR
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[] = {
+    &WR_DIS_USB_DEVICE_EXCHG_PINS[0],    		// [] wr_dis of USB_DEVICE_EXCHG_PINS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[] = {
+    &WR_DIS_USB_OTG11_EXCHG_PINS[0],    		// [] wr_dis of USB_OTG11_EXCHG_PINS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = {
+    &WR_DIS_SOFT_DIS_JTAG[0],    		// [] wr_dis of SOFT_DIS_JTAG
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = {
+    &RD_DIS[0],    		// [] Disable reading from BlOCK4-10
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[] = {
+    &RD_DIS_BLOCK_KEY0[0],    		// [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[] = {
+    &RD_DIS_BLOCK_KEY1[0],    		// [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[] = {
+    &RD_DIS_BLOCK_KEY2[0],    		// [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[] = {
+    &RD_DIS_BLOCK_KEY3[0],    		// [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[] = {
+    &RD_DIS_BLOCK_KEY4[0],    		// [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[] = {
+    &RD_DIS_BLOCK_KEY5[0],    		// [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = {
+    &RD_DIS_BLOCK_SYS_DATA2[0],    		// [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[] = {
+    &RD_DIS_ADC2_HI_DOUT_ATTEN0[0],    		// [] rd_dis of ADC2_HI_DOUT_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[] = {
+    &RD_DIS_ADC2_HI_DOUT_ATTEN1[0],    		// [] rd_dis of ADC2_HI_DOUT_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[] = {
+    &RD_DIS_ADC2_HI_DOUT_ATTEN2[0],    		// [] rd_dis of ADC2_HI_DOUT_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[] = {
+    &RD_DIS_ADC2_HI_DOUT_ATTEN3[0],    		// [] rd_dis of ADC2_HI_DOUT_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[] = {
+    &RD_DIS_TEMPERATURE_SENSOR[0],    		// [] rd_dis of TEMPERATURE_SENSOR
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_USB_DEVICE_EXCHG_PINS[] = {
+    &RD_DIS_USB_DEVICE_EXCHG_PINS[0],    		// [] rd_dis of USB_DEVICE_EXCHG_PINS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_USB_OTG11_EXCHG_PINS[] = {
+    &RD_DIS_USB_OTG11_EXCHG_PINS[0],    		// [] rd_dis of USB_OTG11_EXCHG_PINS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1[] = {
+    &RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1[0],    		// [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = {
+    &DIS_USB_JTAG[0],    		// [] Set this bit to disable function of usb switch to jtag in module of usb device
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2[] = {
+    &RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2[0],    		// [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
+    &DIS_FORCE_DOWNLOAD[0],    		// [] Set this bit to disable the function that forces chip into download mode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = {
+    &SPI_DOWNLOAD_MSPI_DIS[0],    		// [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = {
+    &DIS_TWAI[0],    		// [] Set this bit to disable TWAI function
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = {
+    &JTAG_SEL_ENABLE[0],    		// [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = {
+    &SOFT_DIS_JTAG[0],    		// [] Set odd bits to disable JTAG in the soft way. JTAG can be enabled in HMAC module
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = {
+    &DIS_PAD_JTAG[0],    		// [] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
+    &DIS_DOWNLOAD_MANUAL_ENCRYPT[0],    		// [] Set this bit to disable flash manual encrypt function (except in SPI boot mode)
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6[] = {
+    &RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6[0],    		// [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[] = {
+    &USB_PHY_SEL[0],    		// [] 0: intphy(gpio24/25) <---> usb_device 1: intphy(26/27) <---> usb_otg11.1: intphy(gpio26/27) <---> usb_device 1: intphy(24/25) <---> usb_otg11
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[] = {
+    &HUK_GEN_STATE[0],    		// [] Set the bits to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7[] = {
+    &RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7[0],    		// [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10[] = {
+    &RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10[0],    		// [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11[] = {
+    &RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11[0],    		// [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[] = {
+    &KM_RND_SWITCH_CYCLE[0],    		// [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[] = {
+    &KM_DEPLOY_ONLY_ONCE[0],    		// [] EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: {EFUSE_KM_DEPLOY_ONLY_ONCE_H; EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
+    &KM_DEPLOY_ONLY_ONCE[1],    		// [] EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: {EFUSE_KM_DEPLOY_ONLY_ONCE_H; EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[] = {
+    &FORCE_USE_KEY_MANAGER_KEY[0],    		// [] EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H; EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
+    &FORCE_USE_KEY_MANAGER_KEY[1],    		// [] EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H; EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[] = {
+    &FORCE_DISABLE_SW_INIT_KEY[0],    		// [] Set this bit to disable software written init key; and force use efuse_init_key
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[] = {
+    &KM_XTS_KEY_LENGTH_256[0],    		// [] Set this bit to config flash encryption xts-512 key; else use xts-256 key when using the key manager
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = {
+    &ECC_FORCE_CONST_TIME[0],    		// [] Set this bit to permanently turn on ECC const-time mode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = {
+    &WDT_DELAY_SEL[0],    		// [] Select lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1))
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = {
+    &SPI_BOOT_CRYPT_CNT[0],    		// [] Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = {
+    &SECURE_BOOT_KEY_REVOKE0[0],    		// [] Revoke 1st secure boot key
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = {
+    &SECURE_BOOT_KEY_REVOKE1[0],    		// [] Revoke 2nd secure boot key
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = {
+    &SECURE_BOOT_KEY_REVOKE2[0],    		// [] Revoke 3rd secure boot key
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = {
+    &KEY_PURPOSE_0[0],    		// [KEY0_PURPOSE] Purpose of Key0
+    &KEY_PURPOSE_0[1],    		// [] Purpose of Key0. The 5-th bit
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = {
+    &KEY_PURPOSE_1[0],    		// [KEY1_PURPOSE] Purpose of Key1
+    &KEY_PURPOSE_1[1],    		// [] Purpose of Key1. The 5-th bit
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = {
+    &KEY_PURPOSE_2[0],    		// [KEY2_PURPOSE] Purpose of Key2
+    &KEY_PURPOSE_2[1],    		// [] Purpose of Key2. The 5-th bit
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = {
+    &KEY_PURPOSE_3[0],    		// [KEY3_PURPOSE] Purpose of Key3
+    &KEY_PURPOSE_3[1],    		// [] Purpose of Key3. The 5-th bit
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = {
+    &KEY_PURPOSE_4[0],    		// [KEY4_PURPOSE] Purpose of Key4
+    &KEY_PURPOSE_4[1],    		// [] Purpose of Key4. The 5-th bit
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = {
+    &KEY_PURPOSE_5[0],    		// [KEY5_PURPOSE] Purpose of Key5
+    &KEY_PURPOSE_5[1],    		// [] Purpose of Key5. The 5-th bit
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = {
+    &SEC_DPA_LEVEL[0],    		// [] Configures the clock random divide mode to determine the dpa secure level
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[] = {
+    &XTS_DPA_CLK_ENABLE[0],    		// [] Sets this bit to enable xts clock anti-dpa attack function
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = {
+    &SECURE_BOOT_EN[0],    		// [] Set this bit to enable secure boot
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
+    &SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// [] Set this bit to enable revoking aggressive secure boot
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[] = {
+    &FLASH_ECC_EN[0],    		// [] Set this bit to enable ECC for flash boot
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[] = {
+    &DIS_USB_OTG_DOWNLOAD_MODE[0],    		// [] Set this bit to disable download via USB-OTG
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = {
+    &FLASH_TPUW[0],    		// [] Configures flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the configurable value. Otherwise; the waiting time is 30
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = {
+    &DIS_DOWNLOAD_MODE[0],    		// [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 4; 5; 6; 7)
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = {
+    &DIS_DIRECT_BOOT[0],    		// [] Set this bit to disable direct boot mode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
+    &DIS_USB_SERIAL_JTAG_ROM_PRINT[0],    		// [] Set this bit to disable USB-Serial-JTAG print during rom boot
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[] = {
+    &LOCK_KM_KEY[0],    		// [] set this bit to lock the key manager key after deploy
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
+    &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0],    		// [] Set this bit to disable the USB-Serial-JTAG download function
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
+    &ENABLE_SECURITY_DOWNLOAD[0],    		// [] Set this bit to enable security download mode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = {
+    &UART_PRINT_CONTROL[0],    		// [] Set the type of UART printing; 00: force enable printing; 01: enable printing when GPIO8 is reset at low level; 10: enable printing when GPIO8 is reset at high level; 11: force disable printing
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = {
+    &FORCE_SEND_RESUME[0],    		// [] Set this bit to force ROM code to send a resume command during SPI boot
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
+    &SECURE_VERSION[0],    		// [] Secure version used by ESP-IDF anti-rollback feature
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
+    &SECURE_BOOT_DISABLE_FAST_WAKE[0],    		// [] Represents whether secure boot do fast verification on wake is disabled. 0: enabled 1: disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[] = {
+    &HYS_EN_PAD[0],    		// [] Set bits to enable hysteresis function of PAD0~27
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_0[] = {
+    &PXA0_TIEH_SEL_0[0],    		// [] Output LDO VO0 tieh source select. 0: 1'b1 1: sdmmc1 2: reg 3:sdmmc0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_EN[] = {
+    &PVT_GLITCH_EN[0],    		// [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[] = {
+    &KM_DISABLE_DEPLOY_MODE[0],    		// [] EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H; EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set each bit to control whether corresponding key's deploy mode of new value deployment is disabled. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
+    &KM_DISABLE_DEPLOY_MODE[1],    		// [] EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H; EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set each bit to control whether corresponding key's deploy mode of new value deployment is disabled. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[] = {
+    &XTS_DPA_PSEUDO_LEVEL[0],    		// [] Sets this bit to control the xts pseudo-round anti-dpa attack function. 0: controlled by register. 1-3: the higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_HP_PWR_SRC_SEL[] = {
+    &HP_PWR_SRC_SEL[0],    		// [] HP system power source select. 0:LDO  1: DCDC
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_SHA384_EN[] = {
+    &SECURE_BOOT_SHA384_EN[0],    		// [] Represents whether secure boot using SHA-384 is enabled. 0: disable 1: enable
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[] = {
+    &DIS_WDT[0],    		// [] Set this bit to disable watch dog
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[] = {
+    &DIS_SWD[0],    		// [] Set bit to disable super-watchdog
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_MODE[] = {
+    &PVT_GLITCH_MODE[0],    		// [] Use to configure glitch mode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_MAC[] = {
+    &MAC[0],    		// [MAC_FACTORY] MAC address
+    &MAC[1],    		// [MAC_FACTORY] MAC address
+    &MAC[2],    		// [MAC_FACTORY] MAC address
+    &MAC[3],    		// [MAC_FACTORY] MAC address
+    &MAC[4],    		// [MAC_FACTORY] MAC address
+    &MAC[5],    		// [MAC_FACTORY] MAC address
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
+    &WAFER_VERSION_MINOR[0],    		// [] Minor chip version
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
+    &WAFER_VERSION_MAJOR[0],    		// [] Major chip version (lower 2 bits)
+    &WAFER_VERSION_MAJOR[1],    		// [] Major chip version (MSB)
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
+    &DISABLE_WAFER_VERSION_MAJOR[0],    		// [] Disables check of wafer version major
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
+    &DISABLE_BLK_VERSION_MAJOR[0],    		// [] Disables check of blk version major
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
+    &BLK_VERSION_MINOR[0],    		// [] BLK_VERSION_MINOR of BLOCK2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
+    &BLK_VERSION_MAJOR[0],    		// [] BLK_VERSION_MAJOR of BLOCK2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = {
+    &PSRAM_CAP[0],    		// [] PSRAM capacity
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_TEMP[] = {
+    &TEMP[0],    		// [] Operating temperature of the ESP chip
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[] = {
+    &PSRAM_VENDOR[0],    		// [] PSRAM vendor
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
+    &PKG_VERSION[0],    		// [] Package version
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[] = {
+    &LDO_VO1_DREF[0],    		// [] Output VO1 parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[] = {
+    &LDO_VO2_DREF[0],    		// [] Output VO2 parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[] = {
+    &LDO_VO1_MUL[0],    		// [] Output VO1 parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[] = {
+    &LDO_VO2_MUL[0],    		// [] Output VO2 parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[] = {
+    &LDO_VO3_K[0],    		// [] Output VO3 calibration parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[] = {
+    &LDO_VO3_VOS[0],    		// [] Output VO3 calibration parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[] = {
+    &LDO_VO3_C[0],    		// [] Output VO3 calibration parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[] = {
+    &LDO_VO4_K[0],    		// [] Output VO4 calibration parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[] = {
+    &LDO_VO4_VOS[0],    		// [] Output VO4 calibration parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[] = {
+    &LDO_VO4_C[0],    		// [] Output VO4 calibration parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[] = {
+    &ACTIVE_HP_DBIAS[0],    		// [] Active HP DBIAS of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[] = {
+    &ACTIVE_LP_DBIAS[0],    		// [] Active LP DBIAS of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[] = {
+    &DSLP_DBG[0],    		// [] DSLP BDG of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[] = {
+    &DSLP_LP_DBIAS[0],    		// [] DSLP LP DBIAS of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[] = {
+    &LP_DCDC_DBIAS_VOL_GAP[0],    		// [] DBIAS gap between LP and DCDC
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_PVT_400M_BIAS[] = {
+    &PVT_400M_BIAS[0],    		// [] PVT_DCM_VSET when the CPU is at 400M
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_PVT_40M_BIAS[] = {
+    &PVT_40M_BIAS[0],    		// [] PVT_DCM_VSET corresponding to about 0.9V fixed voltage when the CPU is at 40M
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_PVT_100M_BIAS[] = {
+    &PVT_100M_BIAS[0],    		// [] PVT_DCM_VSET corresponding to about 1.0V fixed voltage when the CPU is at 100M
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
+    &OPTIONAL_UNIQUE_ID[0],    		// [] Optional unique 128-bit ID
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[] = {
+    &ADC1_AVE_INITCODE_ATTEN0[0],    		// [] Average initcode of ADC1 atten0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[] = {
+    &ADC1_AVE_INITCODE_ATTEN1[0],    		// [] Average initcode of ADC1 atten1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[] = {
+    &ADC1_AVE_INITCODE_ATTEN2[0],    		// [] Average initcode of ADC1 atten2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[] = {
+    &ADC1_AVE_INITCODE_ATTEN3[0],    		// [] Average initcode of ADC1 atten3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[] = {
+    &ADC2_AVE_INITCODE_ATTEN0[0],    		// [] Average initcode of ADC2 atten0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[] = {
+    &ADC2_AVE_INITCODE_ATTEN1[0],    		// [] Average initcode of ADC2 atten1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[] = {
+    &ADC2_AVE_INITCODE_ATTEN2[0],    		// [] Average initcode of ADC2 atten2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[] = {
+    &ADC2_AVE_INITCODE_ATTEN3[0],    		// [] Average initcode of ADC2 atten3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = {
+    &ADC1_HI_DOUT_ATTEN0[0],    		// [] HI_DOUT of ADC1 atten0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = {
+    &ADC1_HI_DOUT_ATTEN1[0],    		// [] HI_DOUT of ADC1 atten1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = {
+    &ADC1_HI_DOUT_ATTEN2[0],    		// [] HI_DOUT of ADC1 atten2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = {
+    &ADC1_HI_DOUT_ATTEN3[0],    		// [] HI_DOUT of ADC1 atten3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
+    &USER_DATA[0],    		// [BLOCK_USR_DATA] User data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = {
+    &USER_DATA_MAC_CUSTOM[0],    		// [MAC_CUSTOM CUSTOM_MAC] Custom MAC
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = {
+    &KEY0[0],    		// [BLOCK_KEY0] Key0 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = {
+    &KEY1[0],    		// [BLOCK_KEY1] Key1 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = {
+    &KEY2[0],    		// [BLOCK_KEY2] Key2 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = {
+    &KEY3[0],    		// [BLOCK_KEY3] Key3 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = {
+    &KEY4[0],    		// [BLOCK_KEY4] Key4 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = {
+    &KEY5[0],    		// [BLOCK_KEY5] Key5 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[] = {
+    &ADC2_HI_DOUT_ATTEN0[0],    		// [] HI_DOUT of ADC2 atten0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[] = {
+    &ADC2_HI_DOUT_ATTEN1[0],    		// [] HI_DOUT of ADC2 atten1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[] = {
+    &ADC2_HI_DOUT_ATTEN2[0],    		// [] HI_DOUT of ADC2 atten2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[] = {
+    &ADC2_HI_DOUT_ATTEN3[0],    		// [] HI_DOUT of ADC2 atten3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch0 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch1 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch2 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch3 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch4 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH5_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch5 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH6_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch6 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH7_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch7 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &ADC2_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC2_ch0 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &ADC2_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC2_ch1 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &ADC2_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC2_ch2 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &ADC2_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC2_ch3 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &ADC2_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC2_ch4 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[] = {
+    &ADC2_CH5_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC2_ch5 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[] = {
+    &TEMPERATURE_SENSOR[0],    		// [] Temperature calibration data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[] = {
+    &USB_DEVICE_EXCHG_PINS[0],    		// [] Enable usb device exchange pins of D+ and D-
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[] = {
+    &USB_OTG11_EXCHG_PINS[0],    		// [] Enable usb otg11 exchange pins of D+ and D-
+    NULL
+};
diff --git a/components/efuse/esp32p4/esp_efuse_table_v3.0.csv b/components/efuse/esp32p4/esp_efuse_table_v3.0.csv
new file mode 100644
index 000000000000..a4bbe3a1d464
--- /dev/null
+++ b/components/efuse/esp32p4/esp_efuse_table_v3.0.csv
@@ -0,0 +1,326 @@
+
+# field_name,       |    efuse_block, | bit_start, | bit_count, |comment #
+#                   |    (EFUSE_BLK0  | (0..255)   | (1-256)    |        #
+#                   |     EFUSE_BLK1  |            |            |        #
+#                   |        ...)     |            |            |        #
+##########################################################################
+# !!!!!!!!!!! #
+# After editing this file, run the command manually "idf.py efuse-common-table"
+# this will generate new source files, next rebuild all the sources.
+# !!!!!!!!!!! #
+
+# This file was generated by regtools.py based on the efuses.yaml file with the version: 0b11fcae5408d9e48251cefb10178c11
+
+WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
+WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
+WR_DIS.KM_RND_SWITCH_CYCLE,                      EFUSE_BLK0,   1,   1, [] wr_dis of KM_RND_SWITCH_CYCLE
+WR_DIS.KM_DEPLOY_ONLY_ONCE,                      EFUSE_BLK0,   1,   1, [] wr_dis of KM_DEPLOY_ONLY_ONCE
+WR_DIS.FORCE_USE_KEY_MANAGER_KEY,                EFUSE_BLK0,   1,   1, [] wr_dis of FORCE_USE_KEY_MANAGER_KEY
+WR_DIS.FORCE_DISABLE_SW_INIT_KEY,                EFUSE_BLK0,   1,   1, [] wr_dis of FORCE_DISABLE_SW_INIT_KEY
+WR_DIS.KM_XTS_KEY_LENGTH_256,                    EFUSE_BLK0,   1,   1, [] wr_dis of KM_XTS_KEY_LENGTH_256
+WR_DIS.KM_DEPLOY_ONLY_ONCE_H,                    EFUSE_BLK0,   1,   1, [] wr_dis of KM_DEPLOY_ONLY_ONCE_H
+WR_DIS.FORCE_USE_KEY_MANAGER_KEY_H,              EFUSE_BLK0,   1,   1, [] wr_dis of FORCE_USE_KEY_MANAGER_KEY_H
+WR_DIS.LOCK_KM_KEY,                              EFUSE_BLK0,   1,   1, [] wr_dis of LOCK_KM_KEY
+WR_DIS.KM_DISABLE_DEPLOY_MODE_H,                 EFUSE_BLK0,   1,   1, [] wr_dis of KM_DISABLE_DEPLOY_MODE_H
+WR_DIS.KM_DISABLE_DEPLOY_MODE,                   EFUSE_BLK0,   1,   1, [] wr_dis of KM_DISABLE_DEPLOY_MODE
+WR_DIS.DIS_USB_JTAG,                             EFUSE_BLK0,   2,   1, [] wr_dis of DIS_USB_JTAG
+WR_DIS.DIS_FORCE_DOWNLOAD,                       EFUSE_BLK0,   2,   1, [] wr_dis of DIS_FORCE_DOWNLOAD
+WR_DIS.SPI_DOWNLOAD_MSPI_DIS,                    EFUSE_BLK0,   2,   1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
+WR_DIS.DIS_TWAI,                                 EFUSE_BLK0,   2,   1, [] wr_dis of DIS_TWAI
+WR_DIS.JTAG_SEL_ENABLE,                          EFUSE_BLK0,   2,   1, [] wr_dis of JTAG_SEL_ENABLE
+WR_DIS.DIS_PAD_JTAG,                             EFUSE_BLK0,   2,   1, [] wr_dis of DIS_PAD_JTAG
+WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT,              EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
+WR_DIS.WDT_DELAY_SEL,                            EFUSE_BLK0,   2,   1, [] wr_dis of WDT_DELAY_SEL
+WR_DIS.HYS_EN_PAD,                               EFUSE_BLK0,   2,   1, [] wr_dis of HYS_EN_PAD
+WR_DIS.PXA0_TIEH_SEL_0,                          EFUSE_BLK0,   2,   1, [] wr_dis of PXA0_TIEH_SEL_0
+WR_DIS.DIS_WDT,                                  EFUSE_BLK0,   2,   1, [] wr_dis of DIS_WDT
+WR_DIS.DIS_SWD,                                  EFUSE_BLK0,   2,   1, [] wr_dis of DIS_SWD
+WR_DIS.PVT_GLITCH_EN,                            EFUSE_BLK0,   3,   1, [] wr_dis of PVT_GLITCH_EN
+WR_DIS.PVT_GLITCH_MODE,                          EFUSE_BLK0,   3,   1, [] wr_dis of PVT_GLITCH_MODE
+WR_DIS.SPI_BOOT_CRYPT_CNT,                       EFUSE_BLK0,   4,   1, [] wr_dis of SPI_BOOT_CRYPT_CNT
+WR_DIS.SECURE_BOOT_KEY_REVOKE0,                  EFUSE_BLK0,   5,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
+WR_DIS.SECURE_BOOT_KEY_REVOKE1,                  EFUSE_BLK0,   6,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
+WR_DIS.SECURE_BOOT_KEY_REVOKE2,                  EFUSE_BLK0,   7,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
+WR_DIS.KEY_PURPOSE_0,                            EFUSE_BLK0,   8,   1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
+WR_DIS.KEY_PURPOSE_0_H,                          EFUSE_BLK0,   8,   1, [] wr_dis of KEY_PURPOSE_0_H
+WR_DIS.KEY_PURPOSE_1,                            EFUSE_BLK0,   9,   1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
+WR_DIS.KEY_PURPOSE_1_H,                          EFUSE_BLK0,   9,   1, [] wr_dis of KEY_PURPOSE_1_H
+WR_DIS.KEY_PURPOSE_2,                            EFUSE_BLK0,  10,   1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
+WR_DIS.KEY_PURPOSE_2_H,                          EFUSE_BLK0,  10,   1, [] wr_dis of KEY_PURPOSE_2_H
+WR_DIS.KEY_PURPOSE_3,                            EFUSE_BLK0,  11,   1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
+WR_DIS.KEY_PURPOSE_3_H,                          EFUSE_BLK0,  11,   1, [] wr_dis of KEY_PURPOSE_3_H
+WR_DIS.KEY_PURPOSE_4,                            EFUSE_BLK0,  12,   1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
+WR_DIS.KEY_PURPOSE_4_H,                          EFUSE_BLK0,  12,   1, [] wr_dis of KEY_PURPOSE_4_H
+WR_DIS.KEY_PURPOSE_5,                            EFUSE_BLK0,  13,   1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
+WR_DIS.KEY_PURPOSE_5_H,                          EFUSE_BLK0,  13,   1, [] wr_dis of KEY_PURPOSE_5_H
+WR_DIS.ECC_FORCE_CONST_TIME,                     EFUSE_BLK0,  14,   1, [] wr_dis of ECC_FORCE_CONST_TIME
+WR_DIS.SEC_DPA_LEVEL,                            EFUSE_BLK0,  14,   1, [] wr_dis of SEC_DPA_LEVEL
+WR_DIS.XTS_DPA_CLK_ENABLE,                       EFUSE_BLK0,  14,   1, [] wr_dis of XTS_DPA_CLK_ENABLE
+WR_DIS.XTS_DPA_PSEUDO_LEVEL,                     EFUSE_BLK0,  14,   1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL
+WR_DIS.SECURE_BOOT_EN,                           EFUSE_BLK0,  15,   1, [] wr_dis of SECURE_BOOT_EN
+WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,            EFUSE_BLK0,  16,   1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
+WR_DIS.HP_PWR_SRC_SEL,                           EFUSE_BLK0,  17,   1, [] wr_dis of HP_PWR_SRC_SEL
+WR_DIS.FLASH_ECC_EN,                             EFUSE_BLK0,  18,   1, [] wr_dis of FLASH_ECC_EN
+WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE,                EFUSE_BLK0,  18,   1, [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE
+WR_DIS.FLASH_TPUW,                               EFUSE_BLK0,  18,   1, [] wr_dis of FLASH_TPUW
+WR_DIS.DIS_DOWNLOAD_MODE,                        EFUSE_BLK0,  18,   1, [] wr_dis of DIS_DOWNLOAD_MODE
+WR_DIS.DIS_DIRECT_BOOT,                          EFUSE_BLK0,  18,   1, [] wr_dis of DIS_DIRECT_BOOT
+WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT,            EFUSE_BLK0,  18,   1, [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
+WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,        EFUSE_BLK0,  18,   1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
+WR_DIS.ENABLE_SECURITY_DOWNLOAD,                 EFUSE_BLK0,  18,   1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
+WR_DIS.UART_PRINT_CONTROL,                       EFUSE_BLK0,  18,   1, [] wr_dis of UART_PRINT_CONTROL
+WR_DIS.FORCE_SEND_RESUME,                        EFUSE_BLK0,  18,   1, [] wr_dis of FORCE_SEND_RESUME
+WR_DIS.SECURE_VERSION,                           EFUSE_BLK0,  18,   1, [] wr_dis of SECURE_VERSION
+WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE,            EFUSE_BLK0,  18,   1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
+WR_DIS.HUK_GEN_STATE,                            EFUSE_BLK0,  19,   1, [] wr_dis of HUK_GEN_STATE
+WR_DIS.BLK1,                                     EFUSE_BLK0,  20,   1, [] wr_dis of BLOCK1
+WR_DIS.MAC,                                      EFUSE_BLK0,  20,   1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
+WR_DIS.WAFER_VERSION_MINOR,                      EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MINOR
+WR_DIS.WAFER_VERSION_MAJOR_LO,                   EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MAJOR_LO
+WR_DIS.DISABLE_WAFER_VERSION_MAJOR,              EFUSE_BLK0,  20,   1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
+WR_DIS.DISABLE_BLK_VERSION_MAJOR,                EFUSE_BLK0,  20,   1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
+WR_DIS.BLK_VERSION_MINOR,                        EFUSE_BLK0,  20,   1, [] wr_dis of BLK_VERSION_MINOR
+WR_DIS.BLK_VERSION_MAJOR,                        EFUSE_BLK0,  20,   1, [] wr_dis of BLK_VERSION_MAJOR
+WR_DIS.PSRAM_CAP,                                EFUSE_BLK0,  20,   1, [] wr_dis of PSRAM_CAP
+WR_DIS.TEMP,                                     EFUSE_BLK0,  20,   1, [] wr_dis of TEMP
+WR_DIS.PSRAM_VENDOR,                             EFUSE_BLK0,  20,   1, [] wr_dis of PSRAM_VENDOR
+WR_DIS.PKG_VERSION,                              EFUSE_BLK0,  20,   1, [] wr_dis of PKG_VERSION
+WR_DIS.SYS_DATA_PART1,                           EFUSE_BLK0,  21,   1, [] wr_dis of BLOCK2
+WR_DIS.WAFER_VERSION_MAJOR_HI,                   EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MAJOR_HI
+WR_DIS.LDO_VO1_DREF,                             EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO1_DREF
+WR_DIS.LDO_VO2_DREF,                             EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO2_DREF
+WR_DIS.LDO_VO1_MUL,                              EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO1_MUL
+WR_DIS.LDO_VO2_MUL,                              EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO2_MUL
+WR_DIS.LDO_VO3_K,                                EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO3_K
+WR_DIS.LDO_VO3_VOS,                              EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO3_VOS
+WR_DIS.LDO_VO3_C,                                EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO3_C
+WR_DIS.LDO_VO4_K,                                EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO4_K
+WR_DIS.LDO_VO4_VOS,                              EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO4_VOS
+WR_DIS.LDO_VO4_C,                                EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO4_C
+WR_DIS.ACTIVE_HP_DBIAS,                          EFUSE_BLK0,  20,   1, [] wr_dis of ACTIVE_HP_DBIAS
+WR_DIS.ACTIVE_LP_DBIAS,                          EFUSE_BLK0,  20,   1, [] wr_dis of ACTIVE_LP_DBIAS
+WR_DIS.DSLP_DBG,                                 EFUSE_BLK0,  20,   1, [] wr_dis of DSLP_DBG
+WR_DIS.DSLP_LP_DBIAS,                            EFUSE_BLK0,  20,   1, [] wr_dis of DSLP_LP_DBIAS
+WR_DIS.LP_DCDC_DBIAS_VOL_GAP,                    EFUSE_BLK0,  20,   1, [] wr_dis of LP_DCDC_DBIAS_VOL_GAP
+WR_DIS.PVT_400M_BIAS,                            EFUSE_BLK0,  20,   1, [] wr_dis of PVT_400M_BIAS
+WR_DIS.PVT_40M_BIAS,                             EFUSE_BLK0,  20,   1, [] wr_dis of PVT_40M_BIAS
+WR_DIS.PVT_100M_BIAS,                            EFUSE_BLK0,  20,   1, [] wr_dis of PVT_100M_BIAS
+WR_DIS.OPTIONAL_UNIQUE_ID,                       EFUSE_BLK0,  21,   1, [] wr_dis of OPTIONAL_UNIQUE_ID
+WR_DIS.ADC1_AVE_INITCODE_ATTEN0,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
+WR_DIS.ADC1_AVE_INITCODE_ATTEN1,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
+WR_DIS.ADC1_AVE_INITCODE_ATTEN2,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
+WR_DIS.ADC1_AVE_INITCODE_ATTEN3,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
+WR_DIS.ADC2_AVE_INITCODE_ATTEN0,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN0
+WR_DIS.ADC2_AVE_INITCODE_ATTEN1,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN1
+WR_DIS.ADC2_AVE_INITCODE_ATTEN2,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN2
+WR_DIS.ADC2_AVE_INITCODE_ATTEN3,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN3
+WR_DIS.ADC1_HI_DOUT_ATTEN0,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
+WR_DIS.ADC1_HI_DOUT_ATTEN1,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
+WR_DIS.ADC1_HI_DOUT_ATTEN2,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
+WR_DIS.ADC1_HI_DOUT_ATTEN3,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
+WR_DIS.BLOCK_USR_DATA,                           EFUSE_BLK0,  22,   1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
+WR_DIS.CUSTOM_MAC,                               EFUSE_BLK0,  22,   1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
+WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  23,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
+WR_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  24,   1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
+WR_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  25,   1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
+WR_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  26,   1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
+WR_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  27,   1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
+WR_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  28,   1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
+WR_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  29,   1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
+WR_DIS.ADC2_HI_DOUT_ATTEN0,                      EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_HI_DOUT_ATTEN0
+WR_DIS.ADC2_HI_DOUT_ATTEN1,                      EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_HI_DOUT_ATTEN1
+WR_DIS.ADC2_HI_DOUT_ATTEN2,                      EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_HI_DOUT_ATTEN2
+WR_DIS.ADC2_HI_DOUT_ATTEN3,                      EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_HI_DOUT_ATTEN3
+WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
+WR_DIS.TEMPERATURE_SENSOR,                       EFUSE_BLK0,  29,   1, [] wr_dis of TEMPERATURE_SENSOR
+WR_DIS.USB_DEVICE_EXCHG_PINS,                    EFUSE_BLK0,  29,   1, [] wr_dis of USB_DEVICE_EXCHG_PINS
+WR_DIS.USB_OTG11_EXCHG_PINS,                     EFUSE_BLK0,  29,   1, [] wr_dis of USB_OTG11_EXCHG_PINS
+WR_DIS.SOFT_DIS_JTAG,                            EFUSE_BLK0,  31,   1, [] wr_dis of SOFT_DIS_JTAG
+RD_DIS,                                          EFUSE_BLK0,  32,   7, [] Disable reading from BlOCK4-10
+RD_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  32,   1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
+RD_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  33,   1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
+RD_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  34,   1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
+RD_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  35,   1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
+RD_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  36,   1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
+RD_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  37,   1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
+RD_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  38,   1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
+RD_DIS.ADC2_HI_DOUT_ATTEN0,                      EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_HI_DOUT_ATTEN0
+RD_DIS.ADC2_HI_DOUT_ATTEN1,                      EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_HI_DOUT_ATTEN1
+RD_DIS.ADC2_HI_DOUT_ATTEN2,                      EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_HI_DOUT_ATTEN2
+RD_DIS.ADC2_HI_DOUT_ATTEN3,                      EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_HI_DOUT_ATTEN3
+RD_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
+RD_DIS.TEMPERATURE_SENSOR,                       EFUSE_BLK0,  38,   1, [] rd_dis of TEMPERATURE_SENSOR
+RD_DIS.USB_DEVICE_EXCHG_PINS,                    EFUSE_BLK0,  38,   1, [] rd_dis of USB_DEVICE_EXCHG_PINS
+RD_DIS.USB_OTG11_EXCHG_PINS,                     EFUSE_BLK0,  38,   1, [] rd_dis of USB_OTG11_EXCHG_PINS
+RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1,            EFUSE_BLK0,  39,   2, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
+DIS_USB_JTAG,                                    EFUSE_BLK0,  41,   1, [] Set this bit to disable function of usb switch to jtag in module of usb device
+RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2,            EFUSE_BLK0,  42,   1, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
+DIS_FORCE_DOWNLOAD,                              EFUSE_BLK0,  44,   1, [] Set this bit to disable the function that forces chip into download mode
+SPI_DOWNLOAD_MSPI_DIS,                           EFUSE_BLK0,  45,   1, [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download
+DIS_TWAI,                                        EFUSE_BLK0,  46,   1, [] Set this bit to disable TWAI function
+JTAG_SEL_ENABLE,                                 EFUSE_BLK0,  47,   1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+SOFT_DIS_JTAG,                                   EFUSE_BLK0,  48,   3, [] Set odd bits to disable JTAG in the soft way. JTAG can be enabled in HMAC module
+DIS_PAD_JTAG,                                    EFUSE_BLK0,  51,   1, [] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently
+DIS_DOWNLOAD_MANUAL_ENCRYPT,                     EFUSE_BLK0,  52,   1, [] Set this bit to disable flash manual encrypt function (except in SPI boot mode)
+RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6,            EFUSE_BLK0,  53,   4, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
+USB_PHY_SEL,                                     EFUSE_BLK0,  57,   1, [] 0: intphy(gpio24/25) <---> usb_device 1: intphy(26/27) <---> usb_otg11.1: intphy(gpio26/27) <---> usb_device 1: intphy(24/25) <---> usb_otg11
+HUK_GEN_STATE,                                   EFUSE_BLK0,  58,   5, [] Set the bits to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid
+RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7,            EFUSE_BLK0,  63,   1, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
+RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10,           EFUSE_BLK0,  64,   3, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
+RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11,          EFUSE_BLK0,  67,   1, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
+KM_RND_SWITCH_CYCLE,                             EFUSE_BLK0,  68,   1, [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
+KM_DEPLOY_ONLY_ONCE,                             EFUSE_BLK0,  69,   4, [] EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: {EFUSE_KM_DEPLOY_ONLY_ONCE_H; EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
+,                                                EFUSE_BLK0, 118,   1, [] EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: {EFUSE_KM_DEPLOY_ONLY_ONCE_H; EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
+FORCE_USE_KEY_MANAGER_KEY,                       EFUSE_BLK0,  73,   4, [] EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H; EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
+,                                                EFUSE_BLK0, 119,   1, [] EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H; EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
+FORCE_DISABLE_SW_INIT_KEY,                       EFUSE_BLK0,  77,   1, [] Set this bit to disable software written init key; and force use efuse_init_key
+KM_XTS_KEY_LENGTH_256,                           EFUSE_BLK0,  78,   1, [] Set this bit to config flash encryption xts-512 key; else use xts-256 key when using the key manager
+ECC_FORCE_CONST_TIME,                            EFUSE_BLK0,  79,   1, [] Set this bit to permanently turn on ECC const-time mode
+WDT_DELAY_SEL,                                   EFUSE_BLK0,  81,   1, [] Select lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1))
+SPI_BOOT_CRYPT_CNT,                              EFUSE_BLK0,  82,   3, [] Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
+SECURE_BOOT_KEY_REVOKE0,                         EFUSE_BLK0,  85,   1, [] Revoke 1st secure boot key
+SECURE_BOOT_KEY_REVOKE1,                         EFUSE_BLK0,  86,   1, [] Revoke 2nd secure boot key
+SECURE_BOOT_KEY_REVOKE2,                         EFUSE_BLK0,  87,   1, [] Revoke 3rd secure boot key
+KEY_PURPOSE_0,                                   EFUSE_BLK0,  88,   4, [KEY0_PURPOSE] Purpose of Key0
+,                                                EFUSE_BLK0, 155,   1, [] Purpose of Key0. The 5-th bit
+KEY_PURPOSE_1,                                   EFUSE_BLK0,  92,   4, [KEY1_PURPOSE] Purpose of Key1
+,                                                EFUSE_BLK0, 156,   1, [] Purpose of Key1. The 5-th bit
+KEY_PURPOSE_2,                                   EFUSE_BLK0,  96,   4, [KEY2_PURPOSE] Purpose of Key2
+,                                                EFUSE_BLK0, 157,   1, [] Purpose of Key2. The 5-th bit
+KEY_PURPOSE_3,                                   EFUSE_BLK0, 100,   4, [KEY3_PURPOSE] Purpose of Key3
+,                                                EFUSE_BLK0, 158,   1, [] Purpose of Key3. The 5-th bit
+KEY_PURPOSE_4,                                   EFUSE_BLK0, 104,   4, [KEY4_PURPOSE] Purpose of Key4
+,                                                EFUSE_BLK0, 159,   1, [] Purpose of Key4. The 5-th bit
+KEY_PURPOSE_5,                                   EFUSE_BLK0, 108,   4, [KEY5_PURPOSE] Purpose of Key5
+,                                                EFUSE_BLK0, 164,   1, [] Purpose of Key5. The 5-th bit
+SEC_DPA_LEVEL,                                   EFUSE_BLK0, 112,   2, [] Configures the clock random divide mode to determine the dpa secure level
+XTS_DPA_CLK_ENABLE,                              EFUSE_BLK0, 115,   1, [] Sets this bit to enable xts clock anti-dpa attack function
+SECURE_BOOT_EN,                                  EFUSE_BLK0, 116,   1, [] Set this bit to enable secure boot
+SECURE_BOOT_AGGRESSIVE_REVOKE,                   EFUSE_BLK0, 117,   1, [] Set this bit to enable revoking aggressive secure boot
+FLASH_ECC_EN,                                    EFUSE_BLK0, 122,   1, [] Set this bit to enable ECC for flash boot
+DIS_USB_OTG_DOWNLOAD_MODE,                       EFUSE_BLK0, 123,   1, [] Set this bit to disable download via USB-OTG
+FLASH_TPUW,                                      EFUSE_BLK0, 124,   4, [] Configures flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the configurable value. Otherwise; the waiting time is 30
+DIS_DOWNLOAD_MODE,                               EFUSE_BLK0, 128,   1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 4; 5; 6; 7)
+DIS_DIRECT_BOOT,                                 EFUSE_BLK0, 129,   1, [] Set this bit to disable direct boot mode
+DIS_USB_SERIAL_JTAG_ROM_PRINT,                   EFUSE_BLK0, 130,   1, [] Set this bit to disable USB-Serial-JTAG print during rom boot
+LOCK_KM_KEY,                                     EFUSE_BLK0, 131,   1, [] set this bit to lock the key manager key after deploy
+DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,               EFUSE_BLK0, 132,   1, [] Set this bit to disable the USB-Serial-JTAG download function
+ENABLE_SECURITY_DOWNLOAD,                        EFUSE_BLK0, 133,   1, [] Set this bit to enable security download mode
+UART_PRINT_CONTROL,                              EFUSE_BLK0, 134,   2, [] Set the type of UART printing; 00: force enable printing; 01: enable printing when GPIO8 is reset at low level; 10: enable printing when GPIO8 is reset at high level; 11: force disable printing
+FORCE_SEND_RESUME,                               EFUSE_BLK0, 136,   1, [] Set this bit to force ROM code to send a resume command during SPI boot
+SECURE_VERSION,                                  EFUSE_BLK0, 137,  16, [] Secure version used by ESP-IDF anti-rollback feature
+SECURE_BOOT_DISABLE_FAST_WAKE,                   EFUSE_BLK0, 153,   1, [] Represents whether secure boot do fast verification on wake is disabled. 0: enabled 1: disabled
+HYS_EN_PAD,                                      EFUSE_BLK0, 154,   1, [] Set bits to enable hysteresis function of PAD0~27
+PXA0_TIEH_SEL_0,                                 EFUSE_BLK0, 160,   2, [] Output LDO VO0 tieh source select. 0: 1'b1 1: sdmmc1 2: reg 3:sdmmc0
+PVT_GLITCH_EN,                                   EFUSE_BLK0, 162,   1, [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable
+KM_DISABLE_DEPLOY_MODE,                          EFUSE_BLK0, 168,   4, [] EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H; EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set each bit to control whether corresponding key's deploy mode of new value deployment is disabled. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
+,                                                EFUSE_BLK0, 167,   1, [] EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H; EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set each bit to control whether corresponding key's deploy mode of new value deployment is disabled. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram
+XTS_DPA_PSEUDO_LEVEL,                            EFUSE_BLK0, 176,   2, [] Sets this bit to control the xts pseudo-round anti-dpa attack function. 0: controlled by register. 1-3: the higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation
+HP_PWR_SRC_SEL,                                  EFUSE_BLK0, 178,   1, [] HP system power source select. 0:LDO  1: DCDC
+SECURE_BOOT_SHA384_EN,                           EFUSE_BLK0, 179,   1, [] Represents whether secure boot using SHA-384 is enabled. 0: disable 1: enable
+DIS_WDT,                                         EFUSE_BLK0, 180,   1, [] Set this bit to disable watch dog
+DIS_SWD,                                         EFUSE_BLK0, 181,   1, [] Set bit to disable super-watchdog
+PVT_GLITCH_MODE,                                 EFUSE_BLK0, 182,   2, [] Use to configure glitch mode
+MAC,                                             EFUSE_BLK1,  40,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,  32,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,  24,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,  16,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,   8,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,   0,   8, [MAC_FACTORY] MAC address
+WAFER_VERSION_MINOR,                             EFUSE_BLK1,  64,   4, [] Minor chip version
+WAFER_VERSION_MAJOR,                             EFUSE_BLK1,  68,   2, [] Major chip version (lower 2 bits)
+,                                                EFUSE_BLK1,  87,   1, [] Major chip version (MSB)
+DISABLE_WAFER_VERSION_MAJOR,                     EFUSE_BLK1,  70,   1, [] Disables check of wafer version major
+DISABLE_BLK_VERSION_MAJOR,                       EFUSE_BLK1,  71,   1, [] Disables check of blk version major
+BLK_VERSION_MINOR,                               EFUSE_BLK1,  72,   3, [] BLK_VERSION_MINOR of BLOCK2
+BLK_VERSION_MAJOR,                               EFUSE_BLK1,  75,   2, [] BLK_VERSION_MAJOR of BLOCK2
+PSRAM_CAP,                                       EFUSE_BLK1,  77,   3, [] PSRAM capacity
+TEMP,                                            EFUSE_BLK1,  80,   2, [] Operating temperature of the ESP chip
+PSRAM_VENDOR,                                    EFUSE_BLK1,  82,   2, [] PSRAM vendor
+PKG_VERSION,                                     EFUSE_BLK1,  84,   3, [] Package version
+LDO_VO1_DREF,                                    EFUSE_BLK1,  88,   4, [] Output VO1 parameter
+LDO_VO2_DREF,                                    EFUSE_BLK1,  92,   4, [] Output VO2 parameter
+LDO_VO1_MUL,                                     EFUSE_BLK1,  96,   3, [] Output VO1 parameter
+LDO_VO2_MUL,                                     EFUSE_BLK1,  99,   3, [] Output VO2 parameter
+LDO_VO3_K,                                       EFUSE_BLK1, 102,   8, [] Output VO3 calibration parameter
+LDO_VO3_VOS,                                     EFUSE_BLK1, 110,   6, [] Output VO3 calibration parameter
+LDO_VO3_C,                                       EFUSE_BLK1, 116,   6, [] Output VO3 calibration parameter
+LDO_VO4_K,                                       EFUSE_BLK1, 122,   8, [] Output VO4 calibration parameter
+LDO_VO4_VOS,                                     EFUSE_BLK1, 130,   6, [] Output VO4 calibration parameter
+LDO_VO4_C,                                       EFUSE_BLK1, 136,   6, [] Output VO4 calibration parameter
+ACTIVE_HP_DBIAS,                                 EFUSE_BLK1, 144,   4, [] Active HP DBIAS of fixed voltage
+ACTIVE_LP_DBIAS,                                 EFUSE_BLK1, 148,   4, [] Active LP DBIAS of fixed voltage
+DSLP_DBG,                                        EFUSE_BLK1, 156,   4, [] DSLP BDG of fixed voltage
+DSLP_LP_DBIAS,                                   EFUSE_BLK1, 160,   5, [] DSLP LP DBIAS of fixed voltage
+LP_DCDC_DBIAS_VOL_GAP,                           EFUSE_BLK1, 165,   5, [] DBIAS gap between LP and DCDC
+PVT_400M_BIAS,                                   EFUSE_BLK1, 171,   5, [] PVT_DCM_VSET when the CPU is at 400M
+PVT_40M_BIAS,                                    EFUSE_BLK1, 176,   5, [] PVT_DCM_VSET corresponding to about 0.9V fixed voltage when the CPU is at 40M
+PVT_100M_BIAS,                                   EFUSE_BLK1, 181,   5, [] PVT_DCM_VSET corresponding to about 1.0V fixed voltage when the CPU is at 100M
+OPTIONAL_UNIQUE_ID,                              EFUSE_BLK2,   0, 128, [] Optional unique 128-bit ID
+ADC1_AVE_INITCODE_ATTEN0,                        EFUSE_BLK2, 128,  10, [] Average initcode of ADC1 atten0
+ADC1_AVE_INITCODE_ATTEN1,                        EFUSE_BLK2, 138,  10, [] Average initcode of ADC1 atten1
+ADC1_AVE_INITCODE_ATTEN2,                        EFUSE_BLK2, 148,  10, [] Average initcode of ADC1 atten2
+ADC1_AVE_INITCODE_ATTEN3,                        EFUSE_BLK2, 158,  10, [] Average initcode of ADC1 atten3
+ADC2_AVE_INITCODE_ATTEN0,                        EFUSE_BLK2, 168,  10, [] Average initcode of ADC2 atten0
+ADC2_AVE_INITCODE_ATTEN1,                        EFUSE_BLK2, 178,  10, [] Average initcode of ADC2 atten1
+ADC2_AVE_INITCODE_ATTEN2,                        EFUSE_BLK2, 188,  10, [] Average initcode of ADC2 atten2
+ADC2_AVE_INITCODE_ATTEN3,                        EFUSE_BLK2, 198,  10, [] Average initcode of ADC2 atten3
+ADC1_HI_DOUT_ATTEN0,                             EFUSE_BLK2, 208,  10, [] HI_DOUT of ADC1 atten0
+ADC1_HI_DOUT_ATTEN1,                             EFUSE_BLK2, 218,  10, [] HI_DOUT of ADC1 atten1
+ADC1_HI_DOUT_ATTEN2,                             EFUSE_BLK2, 228,  10, [] HI_DOUT of ADC1 atten2
+ADC1_HI_DOUT_ATTEN3,                             EFUSE_BLK2, 238,  10, [] HI_DOUT of ADC1 atten3
+USER_DATA,                                       EFUSE_BLK3,   0, 256, [BLOCK_USR_DATA] User data
+USER_DATA.MAC_CUSTOM,                            EFUSE_BLK3, 200,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
+KEY0,                                            EFUSE_BLK4,   0, 256, [BLOCK_KEY0] Key0 or user data
+KEY1,                                            EFUSE_BLK5,   0, 256, [BLOCK_KEY1] Key1 or user data
+KEY2,                                            EFUSE_BLK6,   0, 256, [BLOCK_KEY2] Key2 or user data
+KEY3,                                            EFUSE_BLK7,   0, 256, [BLOCK_KEY3] Key3 or user data
+KEY4,                                            EFUSE_BLK8,   0, 256, [BLOCK_KEY4] Key4 or user data
+KEY5,                                            EFUSE_BLK9,   0, 256, [BLOCK_KEY5] Key5 or user data
+ADC2_HI_DOUT_ATTEN0,                             EFUSE_BLK10,   0,  10, [] HI_DOUT of ADC2 atten0
+ADC2_HI_DOUT_ATTEN1,                             EFUSE_BLK10,  10,  10, [] HI_DOUT of ADC2 atten1
+ADC2_HI_DOUT_ATTEN2,                             EFUSE_BLK10,  20,  10, [] HI_DOUT of ADC2 atten2
+ADC2_HI_DOUT_ATTEN3,                             EFUSE_BLK10,  30,  10, [] HI_DOUT of ADC2 atten3
+ADC1_CH0_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  40,   4, [] Gap between ADC1_ch0 and average initcode
+ADC1_CH1_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  44,   4, [] Gap between ADC1_ch1 and average initcode
+ADC1_CH2_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  48,   4, [] Gap between ADC1_ch2 and average initcode
+ADC1_CH3_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  52,   4, [] Gap between ADC1_ch3 and average initcode
+ADC1_CH4_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  56,   4, [] Gap between ADC1_ch4 and average initcode
+ADC1_CH5_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  60,   4, [] Gap between ADC1_ch5 and average initcode
+ADC1_CH6_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  64,   4, [] Gap between ADC1_ch6 and average initcode
+ADC1_CH7_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  68,   4, [] Gap between ADC1_ch7 and average initcode
+ADC2_CH0_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  72,   4, [] Gap between ADC2_ch0 and average initcode
+ADC2_CH1_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  76,   4, [] Gap between ADC2_ch1 and average initcode
+ADC2_CH2_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  80,   4, [] Gap between ADC2_ch2 and average initcode
+ADC2_CH3_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  84,   4, [] Gap between ADC2_ch3 and average initcode
+ADC2_CH4_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  88,   4, [] Gap between ADC2_ch4 and average initcode
+ADC2_CH5_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  92,   4, [] Gap between ADC2_ch5 and average initcode
+TEMPERATURE_SENSOR,                              EFUSE_BLK10,  96,  10, [] Temperature calibration data
+USB_DEVICE_EXCHG_PINS,                           EFUSE_BLK10, 228,   1, [] Enable usb device exchange pins of D+ and D-
+USB_OTG11_EXCHG_PINS,                            EFUSE_BLK10, 229,   1, [] Enable usb otg11 exchange pins of D+ and D-
diff --git a/components/efuse/esp32p4/include/esp_efuse_chip.h b/components/efuse/esp32p4/include/esp_efuse_chip.h
index 3b065c517ce4..b9e6bcc23443 100644
--- a/components/efuse/esp32p4/include/esp_efuse_chip.h
+++ b/components/efuse/esp32p4/include/esp_efuse_chip.h
@@ -1,11 +1,13 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
 
+#include "sdkconfig.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -63,6 +65,11 @@ typedef enum {
 typedef enum {
     ESP_EFUSE_KEY_PURPOSE_USER = 0,                         /**< User purposes (software-only use) */
     ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1,                    /**< ECDSA private key (Expected in little endian order)*/
+
+#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
+    ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P256 = ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY, /**< ECDSA private key (P256) (Expected in little endian order)*/
+#endif
+
     ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 = 2,            /**< XTS_AES_256_KEY_1 (flash/PSRAM encryption) */
     ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 = 3,            /**< XTS_AES_256_KEY_2 (flash/PSRAM encryption) */
     ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4,              /**< XTS_AES_128_KEY (flash/PSRAM encryption) */
@@ -74,7 +81,18 @@ typedef enum {
     ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10,         /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */
     ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11,         /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */
     ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY = 12,                 /**< KM_INIT_KEY */
+
+#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
+    ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 = 13,     /**< PSRAM encryption key (XTS_AES_256_KEY_1) */
+    ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 = 14,     /**< PSRAM encryption key (XTS_AES_256_KEY_2) */
+    ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY = 15,       /**< PSRAM encryption key (XTS_AES_128_KEY) */
+    ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 = 16,              /**< ECDSA private key (P192) */
+    ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L = 17,            /**< ECDSA private key (P384_L) */
+    ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H = 18,            /**< ECDSA private key (P384_H) */
+    ESP_EFUSE_KEY_PURPOSE_MAX = 32,                          /**< MAX PURPOSE */
+#else
     ESP_EFUSE_KEY_PURPOSE_MAX = 16,                         /**< MAX PURPOSE */
+#endif
 } esp_efuse_purpose_t;
 
 #ifdef __cplusplus
diff --git a/components/efuse/esp32p4/include/esp_efuse_table.h b/components/efuse/esp32p4/include/esp_efuse_table.h
index 4366f8541db2..fed2072d5b46 100644
--- a/components/efuse/esp32p4/include/esp_efuse_table.h
+++ b/components/efuse/esp32p4/include/esp_efuse_table.h
@@ -8,340 +8,13 @@
 extern "C" {
 #endif
 
-#include "esp_efuse.h"
+#include "sdkconfig.h"
 
-// md5_digest_table 665d4d3a1354653f8e46869d49df1a2f
-// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
-// If you want to change some fields, you need to change esp_efuse_table.csv file
-// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
-// To show efuse_table run the command 'show_efuse_table'.
-
-
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
-#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
-#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
-#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
-#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
-#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
-#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_ENABLE_SOFT_K[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_HUK_GEN_STATE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
-#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_LO[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_HI[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
-#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
-#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
-#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
-#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
-#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
-#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
-#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
-#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
-#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
-#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
-#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
-#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
-#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
-#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
-#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
-#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
-#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
-extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
-extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[];
-extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[];
-extern const esp_efuse_desc_t* ESP_EFUSE_XTS_KEY_LENGTH_256[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
-#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
-extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
-#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
-extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
-#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
-extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
-#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
-extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
-#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
-extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
-#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
-extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_ENABLE_SOFT_K[];
-extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
-extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET[];
-extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_HP_PWR_SRC_SEL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET_EN[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[];
-extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
-#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
-extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR_LO[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
-extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
-extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR_HI[];
-extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[];
-extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[];
-extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[];
-extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[];
-extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
-#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
-extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
-#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
-#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
-extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
-#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
-extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
-#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
-extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
-#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
-extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
-#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
-extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
-#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
-extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
-#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
+#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
+#include "esp_efuse_table_v3.0.h"
+#else
+#include "esp_efuse_table_v0.0_v2.0.h"
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/components/efuse/esp32p4/include/esp_efuse_table_v0.0_v2.0.h b/components/efuse/esp32p4/include/esp_efuse_table_v0.0_v2.0.h
new file mode 100644
index 000000000000..5cdada4fc144
--- /dev/null
+++ b/components/efuse/esp32p4/include/esp_efuse_table_v0.0_v2.0.h
@@ -0,0 +1,348 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "esp_efuse.h"
+
+// md5_digest_table 665d4d3a1354653f8e46869d49df1a2f
+// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
+// If you want to change some fields, you need to change esp_efuse_table.csv file
+// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
+// To show efuse_table run the command 'show_efuse_table'.
+
+
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
+#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
+#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
+#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
+#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
+#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
+#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_ENABLE_SOFT_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_HUK_GEN_STATE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
+#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_LO[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_HI[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
+#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
+#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
+#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
+#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
+#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
+#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
+#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
+#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
+#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
+#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
+#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
+#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
+#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
+#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
+#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
+#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
+#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
+extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_XTS_KEY_LENGTH_256[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
+#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
+#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
+#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
+#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
+#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
+#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
+extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_ENABLE_SOFT_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_HP_PWR_SRC_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
+#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
+extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR_LO[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR_HI[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
+#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
+extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
+#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
+#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
+#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
+#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
+#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
+#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
+#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
+#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/efuse/esp32p4/include/esp_efuse_table_v3.0.h b/components/efuse/esp32p4/include/esp_efuse_table_v3.0.h
new file mode 100644
index 000000000000..3c3ea8920c0b
--- /dev/null
+++ b/components/efuse/esp32p4/include/esp_efuse_table_v3.0.h
@@ -0,0 +1,361 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "esp_efuse.h"
+
+// md5_digest_table d471a4221faaafb88f091d4549ecac55
+// This file was generated from the file esp_efuse_table_v3.0.csv. DO NOT CHANGE THIS FILE MANUALLY.
+// If you want to change some fields, you need to change esp_efuse_table_v3.0.csv file
+// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
+// To show efuse_table run the command 'show_efuse_table'.
+
+
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_XTS_KEY_LENGTH_256[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE_H[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY_H[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE_H[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
+#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0_H[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
+#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1_H[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
+#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2_H[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
+#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3_H[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
+#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4_H[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
+#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5_H[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
+#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_LO[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_HI[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_400M_BIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_40M_BIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_100M_BIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
+#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
+#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
+#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
+#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
+#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
+#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
+#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
+#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
+#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
+#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
+#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
+#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
+#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
+#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
+#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
+#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
+#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_USB_DEVICE_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_USB_OTG11_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
+extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
+#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
+#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
+#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
+#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
+#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
+#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
+extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_HP_PWR_SRC_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_SHA384_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
+#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
+extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PVT_400M_BIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PVT_40M_BIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PVT_100M_BIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
+#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
+extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
+#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
+#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
+#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
+#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
+#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
+#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
+#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
+#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[];
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/efuse/esp32p4/sources.cmake b/components/efuse/esp32p4/sources.cmake
index 9dffd72008d3..c05edde11921 100644
--- a/components/efuse/esp32p4/sources.cmake
+++ b/components/efuse/esp32p4/sources.cmake
@@ -1,4 +1,15 @@
-set(EFUSE_SOC_SRCS  "esp_efuse_table.c"
-                    "esp_efuse_fields.c"
-                    "esp_efuse_rtc_calib.c"
-                    "esp_efuse_utility.c")
+set(EFUSE_SOC_SRCS
+    "esp_efuse_utility.c"
+    "esp_efuse_fields.c"
+)
+
+if(CONFIG_ESP32P4_REV_MIN_FULL GREATER_EQUAL 300)
+    list(APPEND EFUSE_SOC_SRCS
+        "esp_efuse_table_v3.0.c"
+    )
+else()
+    list(APPEND EFUSE_SOC_SRCS
+        "esp_efuse_table.c"
+        "esp_efuse_rtc_calib.c"
+    )
+endif()
diff --git a/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c b/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c
index 1fa4b07a6792..292ac0436425 100644
--- a/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c
+++ b/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c
@@ -177,7 +177,7 @@ esp_efuse_purpose_t esp_efuse_get_key_purpose(esp_efuse_block_t block)
     }
     unsigned idx = block - EFUSE_BLK_KEY0;
     uint8_t value = 0;
-    esp_err_t err = esp_efuse_read_field_blob(s_table[idx].keypurpose, &value, s_table[idx].keypurpose[0]->bit_count);
+    esp_err_t err = esp_efuse_read_field_blob(s_table[idx].keypurpose, &value, esp_efuse_get_field_size(s_table[idx].keypurpose));
     if (err != ESP_OK) {
         return ESP_EFUSE_KEY_PURPOSE_MAX;
     }
@@ -190,7 +190,7 @@ esp_err_t esp_efuse_set_key_purpose(esp_efuse_block_t block, esp_efuse_purpose_t
         return ESP_ERR_INVALID_ARG;
     }
     unsigned idx = block - EFUSE_BLK_KEY0;
-    return esp_efuse_write_field_blob(s_table[idx].keypurpose, &purpose, s_table[idx].keypurpose[0]->bit_count);
+    return esp_efuse_write_field_blob(s_table[idx].keypurpose, &purpose, esp_efuse_get_field_size(s_table[idx].keypurpose));
 }
 
 bool esp_efuse_get_keypurpose_dis_write(esp_efuse_block_t block)
diff --git a/components/esp-tls/Kconfig b/components/esp-tls/Kconfig
index b56f3bbf0411..80e9606089de 100644
--- a/components/esp-tls/Kconfig
+++ b/components/esp-tls/Kconfig
@@ -25,7 +25,7 @@ menu "ESP-TLS"
 
     config ESP_TLS_USE_DS_PERIPHERAL
         bool "Use Digital Signature (DS) Peripheral with ESP-TLS"
-        depends on ESP_TLS_USING_MBEDTLS && SOC_DIG_SIGN_SUPPORTED
+        depends on ESP_TLS_USING_MBEDTLS && SOC_DIG_SIGN_SUPPORTED && MBEDTLS_PK_RSA_ALT_SUPPORT
         default y
         help
             Enable use of the Digital Signature Peripheral for ESP-TLS.The DS peripheral
diff --git a/components/esp_adc/adc_continuous.c b/components/esp_adc/adc_continuous.c
index 6078ce58ac8b..ef59ad567127 100644
--- a/components/esp_adc/adc_continuous.c
+++ b/components/esp_adc/adc_continuous.c
@@ -475,17 +475,16 @@ esp_err_t adc_continuous_config(adc_continuous_handle_t handle, const adc_contin
     }
 
     ESP_RETURN_ON_FALSE(config->sample_freq_hz <= SOC_ADC_SAMPLE_FREQ_THRES_HIGH && config->sample_freq_hz >= SOC_ADC_SAMPLE_FREQ_THRES_LOW, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC sampling frequency out of range");
-
 #if CONFIG_IDF_TARGET_ESP32
-    ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE1, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type1");
+    handle->format = ADC_DIGI_OUTPUT_FORMAT_TYPE1;
 #elif CONFIG_IDF_TARGET_ESP32S2
     if (config->conv_mode == ADC_CONV_BOTH_UNIT || config->conv_mode == ADC_CONV_ALTER_UNIT) {
-        ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE2, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type2");
+        handle->format = ADC_DIGI_OUTPUT_FORMAT_TYPE2;
     } else if (config->conv_mode == ADC_CONV_SINGLE_UNIT_1 || config->conv_mode == ADC_CONV_SINGLE_UNIT_2) {
-        ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE1, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type1");
+        handle->format = ADC_DIGI_OUTPUT_FORMAT_TYPE1;
     }
 #else
-    ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE2, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type2");
+    handle->format = ADC_DIGI_OUTPUT_FORMAT_TYPE2;
 #endif
 
     uint32_t clk_src_freq_hz = 0;
@@ -583,3 +582,88 @@ esp_err_t adc_continuous_channel_to_io(adc_unit_t unit_id, adc_channel_t channel
 {
     return adc_channel_to_io(unit_id, channel, io_num);
 }
+
+esp_err_t adc_continuous_parse_data(adc_continuous_handle_t handle,
+                                    const uint8_t *raw_data,
+                                    uint32_t raw_data_size,
+                                    adc_continuous_data_t *parsed_data,
+                                    uint32_t *num_parsed_samples)
+{
+    // Parameter validation
+    ESP_RETURN_ON_FALSE(handle && raw_data && parsed_data && num_parsed_samples, ESP_ERR_INVALID_ARG, ADC_TAG, "invalid argument");
+
+    // Buffer size validation
+    if (raw_data_size == 0 || raw_data_size % SOC_ADC_DIGI_RESULT_BYTES != 0) {
+        *num_parsed_samples = 0;
+        return ESP_ERR_INVALID_SIZE;
+    }
+
+    // Calculate number of samples
+    uint32_t samples_to_parse = raw_data_size / SOC_ADC_DIGI_RESULT_BYTES;
+
+    for (uint32_t i = 0; i < samples_to_parse; i++) {
+        adc_digi_output_data_t *p = (adc_digi_output_data_t*)&raw_data[i * SOC_ADC_DIGI_RESULT_BYTES];
+#if CONFIG_IDF_TARGET_ESP32
+        parsed_data[i].unit = ADC_UNIT_1;
+        parsed_data[i].channel = p->type1.channel;
+        parsed_data[i].raw_data = p->type1.data;
+        parsed_data[i].valid = (parsed_data[i].channel < SOC_ADC_CHANNEL_NUM(parsed_data[i].unit));
+#elif CONFIG_IDF_TARGET_ESP32S2
+        if (handle->format == ADC_DIGI_OUTPUT_FORMAT_TYPE2) {
+            parsed_data[i].unit = p->type2.unit ? ADC_UNIT_2 : ADC_UNIT_1;
+            parsed_data[i].channel = p->type2.channel;
+            parsed_data[i].raw_data = p->type2.data;
+            parsed_data[i].valid = (parsed_data[i].channel < SOC_ADC_CHANNEL_NUM(parsed_data[i].unit));
+        } else if (handle->format == ADC_DIGI_OUTPUT_FORMAT_TYPE1) {
+            parsed_data[i].unit = handle->use_adc1 ? ADC_UNIT_1 : ADC_UNIT_2;
+            parsed_data[i].channel = p->type1.channel;
+            parsed_data[i].raw_data = p->type1.data;
+            parsed_data[i].valid = (parsed_data[i].channel < SOC_ADC_CHANNEL_NUM(parsed_data[i].unit));
+        }
+#else
+#if CONFIG_SOC_ADC_PERIPH_NUM == 1
+        parsed_data[i].unit = ADC_UNIT_1;
+#else
+        parsed_data[i].unit = p->type2.unit ? ADC_UNIT_2 : ADC_UNIT_1;
+#endif
+        parsed_data[i].channel = (parsed_data[i].unit == ADC_UNIT_2) ? p->type2.channel - ADC_LL_UNIT2_CHANNEL_SUBSTRATION : p->type2.channel;
+        parsed_data[i].raw_data = p->type2.data;
+        parsed_data[i].valid = (parsed_data[i].channel < SOC_ADC_CHANNEL_NUM(parsed_data[i].unit));
+#endif
+    }
+
+    *num_parsed_samples = samples_to_parse;
+    return ESP_OK;
+}
+
+esp_err_t adc_continuous_read_parse(adc_continuous_handle_t handle,
+                                    adc_continuous_data_t *parsed_data,
+                                    uint32_t max_samples,
+                                    uint32_t *num_samples,
+                                    uint32_t timeout_ms)
+{
+    // Parameter validation
+    ESP_RETURN_ON_FALSE(handle && parsed_data && num_samples, ESP_ERR_INVALID_ARG, ADC_TAG, "invalid argument");
+
+    // Allocate raw data buffer based on max_samples
+    uint32_t raw_buffer_size = max_samples * SOC_ADC_DIGI_RESULT_BYTES;
+    uint8_t *raw_data = malloc(raw_buffer_size);
+    if (raw_data == NULL) {
+        *num_samples = 0;
+        return ESP_ERR_NO_MEM;
+    }
+
+    uint32_t out_length = 0;
+    esp_err_t read_ret = adc_continuous_read(handle, raw_data, raw_buffer_size, &out_length, timeout_ms);
+    if (read_ret != ESP_OK) {
+        free(raw_data);
+        *num_samples = 0;
+        return read_ret;
+    }
+
+    esp_err_t parse_ret = adc_continuous_parse_data(handle, raw_data, out_length, parsed_data, num_samples);
+
+    free(raw_data);
+
+    return parse_ret;
+}
diff --git a/components/esp_adc/adc_continuous_internal.h b/components/esp_adc/adc_continuous_internal.h
index a2fb28dfac60..3f3f171da7b2 100644
--- a/components/esp_adc/adc_continuous_internal.h
+++ b/components/esp_adc/adc_continuous_internal.h
@@ -87,6 +87,7 @@ struct adc_continuous_ctx_t {
     adc_atten_t                     adc1_atten;                 //Attenuation for ADC1. On this chip each ADC can only support one attenuation.
     adc_atten_t                     adc2_atten;                 //Attenuation for ADC2. On this chip each ADC can only support one attenuation.
     adc_hal_digi_ctrlr_cfg_t        hal_digi_ctrlr_cfg;         //Hal digital controller configuration
+    adc_digi_output_format_t        format;                     //ADC DMA conversion output format
     adc_continuous_evt_cbs_t        cbs;                        //Callbacks
     void                            *user_data;                 //User context
     esp_pm_lock_handle_t            pm_lock;                    //For power management
diff --git a/components/esp_adc/include/esp_adc/adc_continuous.h b/components/esp_adc/include/esp_adc/adc_continuous.h
index 422e46e4db88..90318e5b1a27 100644
--- a/components/esp_adc/include/esp_adc/adc_continuous.h
+++ b/components/esp_adc/include/esp_adc/adc_continuous.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -238,6 +238,66 @@ esp_err_t adc_continuous_io_to_channel(int io_num, adc_unit_t * const unit_id, a
  */
 esp_err_t adc_continuous_channel_to_io(adc_unit_t unit_id, adc_channel_t channel, int * const io_num);
 
+/**
+ * @brief Parsed ADC continuous mode data structure
+ */
+typedef struct {
+    adc_unit_t unit;        ///< ADC unit (ADC_UNIT_1 or ADC_UNIT_2)
+    adc_channel_t channel;  ///< ADC channel number (0-9)
+    uint32_t raw_data;      ///< ADC raw data value (0-4095, 12-bit resolution)
+    bool valid;             ///< Whether the data is valid
+} adc_continuous_data_t;
+
+/**
+ * @brief Parse ADC continuous mode raw data
+ *
+ * @param[in] handle        ADC continuous mode driver handle
+ * @param[in] raw_data      Raw data buffer obtained from adc_continuous_read()
+ * @param[in] raw_data_size Size of raw data buffer in bytes
+ * @param[out] parsed_data  Parsed data array
+ * @param[out] num_parsed_samples Number of samples actually parsed and stored in parsed_data
+ *
+ * @note The function will parse all available samples from raw_data. User should ensure
+ *       parsed_data array is large enough to hold raw_data_size/SOC_ADC_DIGI_RESULT_BYTES samples.
+ *       The function includes comprehensive bounds checking to prevent buffer overflow and integer overflow.
+ *
+ * @return
+ *         - ESP_OK: Success
+ *         - ESP_ERR_INVALID_ARG: Invalid arguments
+ *         - ESP_ERR_INVALID_SIZE: raw_data_size is not aligned to SOC_ADC_DIGI_RESULT_BYTES,
+ *                                 integer overflow detected, or buffer overflow detected
+ */
+esp_err_t adc_continuous_parse_data(adc_continuous_handle_t handle,
+                                    const uint8_t *raw_data,
+                                    uint32_t raw_data_size,
+                                    adc_continuous_data_t *parsed_data,
+                                    uint32_t *num_parsed_samples);
+
+/**
+ * @brief Read and parse ADC continuous mode data in one call
+ *
+ * @param[in] handle        ADC continuous mode driver handle
+ * @param[out] parsed_data  Parsed data array
+ * @param[in] max_samples   Maximum number of samples that can be stored in parsed_data array
+ * @param[out] num_samples  Number of samples actually parsed and stored in parsed_data
+ * @param[in] timeout_ms    Timeout in milliseconds
+ *
+ * @note This function automatically handles raw data buffer allocation and cleanup.
+ *       User only needs to provide parsed_data array and specify max_samples.
+ *
+ * @return
+ *         - ESP_OK: Success
+ *         - ESP_ERR_INVALID_ARG: Invalid arguments
+ *         - ESP_ERR_INVALID_SIZE: Buffer size issues or overflow detected
+ *         - ESP_ERR_TIMEOUT: Operation timed out
+ *         - ESP_ERR_NO_MEM: Memory allocation failed
+ */
+esp_err_t adc_continuous_read_parse(adc_continuous_handle_t handle,
+                                    adc_continuous_data_t *parsed_data,
+                                    uint32_t max_samples,
+                                    uint32_t *num_samples,
+                                    uint32_t timeout_ms);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_coex/src/coexist.c b/components/esp_coex/src/coexist.c
index 22d482c7e849..41b3db3f27a1 100644
--- a/components/esp_coex/src/coexist.c
+++ b/components/esp_coex/src/coexist.c
@@ -189,6 +189,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
             {
                 gpio_func_sel(gpio_pin.priority, PIN_FUNC_GPIO);
                 gpio_set_direction(gpio_pin.priority, GPIO_MODE_INPUT);
+                gpio_set_pull_mode(gpio_pin.priority, GPIO_PULLDOWN_ONLY);
                 esp_rom_gpio_connect_in_signal(gpio_pin.priority, EXTERNAL_COEX_SIGNAL_I1_IDX, false);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.priority), GPIO_PIN1_SYNC1_BYPASS, 2);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.priority), GPIO_PIN1_SYNC2_BYPASS, 2);
@@ -206,6 +207,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
             {
                 gpio_func_sel(gpio_pin.request, PIN_FUNC_GPIO);
                 gpio_set_direction(gpio_pin.request, GPIO_MODE_INPUT);
+                gpio_set_pull_mode(gpio_pin.request, GPIO_PULLDOWN_ONLY);
                 esp_rom_gpio_connect_in_signal(gpio_pin.request, EXTERNAL_COEX_SIGNAL_I0_IDX, false);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.request), GPIO_PIN1_SYNC1_BYPASS, 2);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.request), GPIO_PIN1_SYNC2_BYPASS, 2);
@@ -224,6 +226,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
             {
                 gpio_func_sel(gpio_pin.tx_line, PIN_FUNC_GPIO);
                 gpio_set_direction(gpio_pin.tx_line, GPIO_MODE_INPUT);
+                gpio_set_pull_mode(gpio_pin.tx_line, GPIO_PULLDOWN_ONLY);
                 esp_rom_gpio_connect_in_signal(gpio_pin.tx_line, EXTERNAL_COEX_SIGNAL_I1_IDX, false);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.tx_line), GPIO_PIN1_SYNC1_BYPASS, 2);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.tx_line), GPIO_PIN1_SYNC2_BYPASS, 2);
@@ -241,6 +244,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
             {
                 gpio_func_sel(gpio_pin.grant, PIN_FUNC_GPIO);
                 gpio_set_direction(gpio_pin.grant, GPIO_MODE_INPUT);
+                gpio_set_pull_mode(gpio_pin.grant, GPIO_PULLUP_ONLY);
                 esp_rom_gpio_connect_in_signal(gpio_pin.grant, EXTERNAL_COEX_SIGNAL_I0_IDX, false);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.grant), GPIO_PIN1_SYNC1_BYPASS, 2);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.grant), GPIO_PIN1_SYNC2_BYPASS, 2);
diff --git a/components/esp_driver_cam/dvp/include/esp_cam_ctlr_dvp.h b/components/esp_driver_cam/dvp/include/esp_cam_ctlr_dvp.h
index 032ab47a21ef..53cb812846e3 100644
--- a/components/esp_driver_cam/dvp/include/esp_cam_ctlr_dvp.h
+++ b/components/esp_driver_cam/dvp/include/esp_cam_ctlr_dvp.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -38,8 +38,33 @@ typedef struct esp_cam_ctlr_dvp_config {
     uint32_t h_res;                             /*!< Input horizontal resolution, i.e. the number of pixels in a line */
     uint32_t v_res;                             /*!< Input vertical resolution, i.e. the number of lines in a frame */
     cam_ctlr_color_t input_data_color_type;     /*!< Input pixel format */
+    uint32_t cam_data_width;                        /*!< Byte width, 8, 16 or 24 bit, default to 8 */
     struct {
-        uint32_t byte_swap_en : 1;              /*!< Enable byte swap */
+        uint32_t bit_swap_en : 1;               /*!< Enable bit swap */
+        uint32_t byte_swap_en : 1;              /*!< Enable byte swap
+                                                    *
+                                                    * GDMA Data Byte Order Table (input: B0,B1,B2,B3,B4,B5, addresses from low to high)
+                                                    *
+                                                    * | cam_data_width | bit_swap_en | byte_swap_en | Stage 1 Output Data Sequence   |
+                                                    * |----------------|-------------|--------------|------------------------------  |
+                                                    * | 8-bit          | 0           | 0            | {B0}{B1}{B2}{B3}{B4}{B5}       |
+                                                    * | 8-bit          | 0           | 1            | {B1,B0}{B3,B2}{B5,B4}          |
+                                                    * | 8-bit          | 1           | 0            | {B0'}{B1'}{B2'}{B3'}{B4'}{B5'} |
+                                                    * | 8-bit          | 1           | 1            | {B1',B0'}{B3',B2'}{B5',B4'}    |
+                                                    *
+                                                    * | 16-bit         | 0           | 0            | {B1,B0}{B3,B2}{B5,B4}          |
+                                                    * | 16-bit         | 0           | 1            | {B0,B1}{B2,B3}{B4,B5}          |
+                                                    * | 16-bit         | 1           | 0            | {B1',B0'}{B3',B2'}{B5',B4'}    |
+                                                    * | 16-bit         | 1           | 1            | {B0',B1'}{B2',B3'}{B4',B5'}    |
+                                                    *
+                                                    * | 24-bit         | 0           | 0            | {B2,B1,B0}{B5,B4,B3}           |
+                                                    * | 24-bit         | 0           | 1            | {B0,B1,B2}{B3,B4,B5}           |
+                                                    * | 24-bit         | 1           | 0            | {B2',B1',B0'}{B5',B4',B3'}     |
+                                                    * | 24-bit         | 1           | 1            | {B0',B1',B2'}{B3',B4',B5'}     |
+                                                    *
+                                                    * Where B0' = bit-reversed B0，Bn'[7:0] = Bn[0:7]
+                                                    * Each {} contains big-endian parallel data, {} are in serial relationship, output order is left to right
+                                                    */
         uint32_t bk_buffer_dis  : 1;            /*!< Disable backup buffer */
         uint32_t pin_dont_init : 1;             /*!< Don't initialize DVP pins if users have called "esp_cam_ctlr_dvp_init" before */
         uint32_t pic_format_jpeg : 1;           /*!< Input picture format is JPEG, if set this flag and "input_data_color_type" will be ignored */
diff --git a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c
index ff96ed07b41c..8a9df05c5615 100644
--- a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c
+++ b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c
@@ -771,7 +771,9 @@ static void *esp_cam_ctlr_dvp_cam_alloc_buffer(esp_cam_ctlr_t *handle, size_t si
  * @param cam_handle Camera controller handle
  * @param src_format Source format
  * @param dst_format Destination format
- * @return ESP_OK on success, ESP_FAIL on failure
+ * @return
+ *        - ESP_OK on success
+ *        - ESP_ERR_INVALID_ARG: Invalid argument
  */
 esp_err_t esp_cam_ctlr_dvp_format_conversion(esp_cam_ctlr_handle_t cam_handle,
                                              const cam_ctlr_format_conv_config_t *config)
@@ -784,6 +786,12 @@ esp_err_t esp_cam_ctlr_dvp_format_conversion(esp_cam_ctlr_handle_t cam_handle,
 
     ESP_LOGD(TAG, "Configure format conversion: %d -> %d", config->src_format, config->dst_format);
 
+#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
+    if (config->src_format == CAM_CTLR_COLOR_YUV420) {
+        ESP_LOGE(TAG, "YUV420 is not allowed for source format");
+        return ESP_ERR_INVALID_ARG;
+    }
+#endif
     // Configure color format conversion
     cam_hal_color_format_convert(&ctlr->hal, config);
 
@@ -845,9 +853,17 @@ esp_err_t esp_cam_new_dvp_ctlr(const esp_cam_ctlr_dvp_config_t *config, esp_cam_
 
     cam_hal_config_t cam_hal_config = {
         .port = config->ctlr_id,
+        .cam_data_width = config->cam_data_width == 0 ? 8 : config->cam_data_width,
+        .bit_swap_en = config->bit_swap_en,
         .byte_swap_en = config->byte_swap_en,
     };
 
+    ESP_RETURN_ON_FALSE(cam_hal_config.cam_data_width == 8 || cam_hal_config.cam_data_width == 16 || cam_hal_config.cam_data_width == 24, ESP_ERR_INVALID_ARG, TAG, "invalid argument: cam_data_width is not 8 or 16 or 24");
+
+#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
+    ESP_RETURN_ON_FALSE(cam_hal_config.cam_data_width != 8 || cam_hal_config.byte_swap_en == 0, ESP_ERR_INVALID_ARG, TAG, "invalid argument: byte swap is not supported when cam_data_width is 8");
+#endif
+
     if (!config->pin_dont_init) {
         // Initialzie DVP clock and GPIO internally
         ESP_GOTO_ON_ERROR(esp_cam_ctlr_dvp_init(config->ctlr_id, config->clk_src, config->pin),
diff --git a/components/esp_driver_rmt/src/rmt_common.c b/components/esp_driver_rmt/src/rmt_common.c
index 6bd08bf63bdd..e64208053769 100644
--- a/components/esp_driver_rmt/src/rmt_common.c
+++ b/components/esp_driver_rmt/src/rmt_common.c
@@ -226,15 +226,9 @@ esp_err_t rmt_select_periph_clock(rmt_channel_handle_t chan, rmt_clock_source_t
     // if the CPU frequency goes down, the transfer+encoding scheme could be unstable because CPU can't fill the data in time
     // so, choose ESP_PM_CPU_FREQ_MAX lock for non-dma mode
     // otherwise, chose lock type based on the clock source
+    // note, even if the clock source is APB, we still use CPU_FREQ_MAX lock to ensure the stability of the RMT operation.
     esp_pm_lock_type_t pm_lock_type = chan->dma_chan ? ESP_PM_NO_LIGHT_SLEEP : ESP_PM_CPU_FREQ_MAX;
 
-#if SOC_RMT_SUPPORT_APB
-    if (clk_src == RMT_CLK_SRC_APB) {
-        // APB clock frequency can be changed during DFS
-        pm_lock_type = ESP_PM_APB_FREQ_MAX;
-    }
-#endif // SOC_RMT_SUPPORT_APB
-
     sprintf(chan->pm_lock_name, "rmt_%d_%d", group->group_id, chan->channel_id); // e.g. rmt_0_0
     ret  = esp_pm_lock_create(pm_lock_type, 0, chan->pm_lock_name, &chan->pm_lock);
     ESP_RETURN_ON_ERROR(ret, TAG, "create pm lock failed");
diff --git a/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c b/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c
index 704e8c60affe..a43b84a20d84 100644
--- a/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c
+++ b/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c
@@ -50,6 +50,7 @@
 #define UART_BAUD_RATE          (115200)
 #define BUF_SIZE                (1024)
 #define TIMER_WAKEUP_TIME_US    (1 * 100 * 1000)
+#define UART_READ_TOUT          (pdMS_TO_TICKS(500))
 
 static void force_stdout(void)
 {
@@ -125,14 +126,15 @@ void send_and_verify_recived_data(const char* message, uint8_t length, bool shou
     uart_flush_input(MASTER_UART_NUM);
     uart_write_bytes(MASTER_UART_NUM, message, length);
     /* Wait for uart write finish */
-    uart_wait_tx_idle_polling(MASTER_UART_NUM);
+    uart_wait_tx_done(MASTER_UART_NUM, portMAX_DELAY);
 
     bool wake_up_detected = false;
     const char *target = "Wakeup OK!";
     int target_len = 11;
     bool match = true;
     char *data = (char *) malloc(BUF_SIZE);
-    int len = uart_read_bytes(MASTER_UART_NUM, data, target_len, 5000 / portTICK_PERIOD_MS);
+    int len = uart_read_bytes(MASTER_UART_NUM, data, target_len, UART_READ_TOUT);
+    *(data + len) = '\0';
 
     if (len > 0) {
         if (len != target_len) {
@@ -212,7 +214,10 @@ static void enter_sleep_and_send_respond(void)
     }
 
     /* Wait for uart write finish */
-    uart_wait_tx_idle_polling(SLAVE_UART_NUM);
+    uart_wait_tx_done(MASTER_UART_NUM, portMAX_DELAY);
+
+    /* Wait for Master read data, otherwise the UART_INTR_TX_BRK_DONE intr will be triggered*/
+    vTaskDelay(UART_READ_TOUT);
 }
 
 // slave
diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt
index 5fefa8d78030..6fe325a1c1fb 100644
--- a/components/esp_hw_support/CMakeLists.txt
+++ b/components/esp_hw_support/CMakeLists.txt
@@ -198,6 +198,17 @@ if(CONFIG_IDF_TARGET_ESP32H4)
     )
 endif()
 
+
+if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
+    if(CMAKE_C_COMPILER_ID MATCHES "GNU")
+        idf_build_set_property(COMPILE_OPTIONS "-march=rv32imafc_zicsr_zifencei_xesppie" APPEND)
+    endif()
+elseif(CONFIG_IDF_TARGET_ESP32P4)
+    if(CMAKE_C_COMPILER_ID MATCHES "Clang") # TODO: LLVM-478
+        message(FATAL_ERROR "ESP32-P4 rev. 3.0 or higher is not supported in Clang-based toolchain")
+    endif()
+endif()
+
 idf_component_register(SRCS ${srcs}
                        INCLUDE_DIRS ${public_include_dirs}
                        PRIV_INCLUDE_DIRS port/include include/esp_private
diff --git a/components/esp_partition/host_test/partition_api_test/main/partition_api_test.c b/components/esp_partition/host_test/partition_api_test/main/partition_api_test.c
index 8d57d5d09f1a..5bd4a15c0114 100644
--- a/components/esp_partition/host_test/partition_api_test/main/partition_api_test.c
+++ b/components/esp_partition/host_test/partition_api_test/main/partition_api_test.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -155,6 +155,29 @@ TEST(partition_api, test_partition_mmap)
     TEST_ASSERT_EQUAL(err, ESP_ERR_INVALID_SIZE);
 }
 
+TEST(partition_api, test_partition_mmap_support_for_greater_than_4M)
+{
+    // Scenario: Not specified flash size but provided partition table > 4M (default size supported)
+    // esp_partition_mmap should calculate partition size from the binary, create mmap_flash_file and return ESP_OK
+
+    // unmap file to have correct initial conditions, regardless of result
+    esp_partition_file_munmap();
+
+    // get and initialize the control structure for file mmap
+    esp_partition_file_mmap_ctrl_t *p_file_mmap_ctrl = esp_partition_get_file_mmap_ctrl_input();
+    TEST_ASSERT_NOT_NULL(p_file_mmap_ctrl);
+
+    memset(p_file_mmap_ctrl, 0, sizeof(*p_file_mmap_ctrl));
+    strlcpy(p_file_mmap_ctrl->partition_file_name, BUILD_DIR"/partition_table/partition-table_8M.bin", sizeof(p_file_mmap_ctrl->partition_file_name));
+
+    // esp_partition_find_first calls the esp_partition_file_mmap in the background
+    const esp_partition_t *partition_data = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, "storage");
+    TEST_ASSERT_NOT_NULL(partition_data);
+
+    // cleanup after test
+    esp_partition_file_munmap();
+}
+
 TEST(partition_api, test_partition_mmap_diff_size)
 {
     // Scenario: default temporary flash file, explicitly specified size and file with partition table
@@ -336,14 +359,10 @@ TEST(partition_api, test_partition_mmap_name_size)
     memset(p_file_mmap_ctrl_input, 0, sizeof(*p_file_mmap_ctrl_input));
 }
 
-/* Negative TC to ensure mmap setup checks presence of partition file name (partition table binary file)
- * if flash size parameter was specified.
- * This test case specifies just flash file size but omits partition table binary file name.
- */
 TEST(partition_api, test_partition_mmap_size_no_partition)
 {
-    // Negative Scenario: conflicting settings - flash_file_name empty, flash_file_size set and partition_file_name not set
-    // esp_partition_file_mmap should return ESP_ERR_INVALID_ARG
+    // Scenario: flash_file_name empty, incorrect flash_file_size set and partition_file_name not set
+    // esp_partition_file_mmap should calculate correct flash_file_size based on default partition table and return ESP_OK
 
     // unmap file to have correct initial conditions, regardless of result
     esp_partition_file_munmap();
@@ -357,22 +376,17 @@ TEST(partition_api, test_partition_mmap_size_no_partition)
 
     const uint8_t *p_mem_block = NULL;
     esp_err_t err = esp_partition_file_mmap(&p_mem_block);
-
-    // expected result is invalid argument
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, err);
+    TEST_ESP_OK(err);
 
     // cleanup after test
     esp_partition_file_munmap();
     memset(p_file_mmap_ctrl_input, 0, sizeof(*p_file_mmap_ctrl_input));
 }
 
-/* Negative TC to ensure mmap setup checks presence of flash size parameter if partition file name (partition table binary file) was specified.
- * This test case specifies just partition table binary file name but omits flash file size.
- */
 TEST(partition_api, test_partition_mmap_no_size_partition)
 {
-    // Negative Scenario: conflicting settings - flash_file_name empty, flash_file_size not set and partition_file_name set
-    // esp_partition_file_mmap should return ESP_ERR_INVALID_ARG
+    // Scenario: - flash_file_name empty, flash_file_size not set and partition_file_name set
+    // esp_partition_file_mmap() will calculate flash_file_size based on given partition_table and return ESP_OK
 
     // unmap file to have correct initial conditions, regardless of result
     esp_partition_file_munmap();
@@ -382,14 +396,12 @@ TEST(partition_api, test_partition_mmap_no_size_partition)
     TEST_ASSERT_NOT_NULL(p_file_mmap_ctrl_input);
 
     memset(p_file_mmap_ctrl_input, 0, sizeof(*p_file_mmap_ctrl_input));
-    const char *partition_file_name = "/tmp/xyz.bin";
+    const char *partition_file_name = BUILD_DIR"/partition_table/partition-table.bin";
     strlcpy(p_file_mmap_ctrl_input->partition_file_name, partition_file_name, sizeof(p_file_mmap_ctrl_input->partition_file_name));
 
     const uint8_t *p_mem_block = NULL;
     esp_err_t err = esp_partition_file_mmap(&p_mem_block);
-
-    // expected result is invalid argument
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, err);
+    TEST_ESP_OK(err);
 
     // cleanup after test
     esp_partition_file_munmap();
@@ -463,38 +475,6 @@ TEST(partition_api, test_partition_mmap_pfile_nf)
     memset(p_file_mmap_ctrl_input, 0, sizeof(*p_file_mmap_ctrl_input));
 }
 
-/* Negative TC to check that requested size of emulated flash is at least so big to be able to load binary partition table.
- * Too small emulated flash size is introduced and respective error code is evaluated after mmap call.
- */
-TEST(partition_api, test_partition_mmap_size_too_small)
-{
-    // Negative Scenario: specified flash file size too small to hold at least partition table at default offset
-    // esp_partition_file_mmap should return ESP_ERR_INVALID_SIZE
-
-    // unmap file to have correct initial conditions, regardless of result
-    esp_partition_file_munmap();
-
-    // get and initialize the control structure for file mmap
-    esp_partition_file_mmap_ctrl_t *p_file_mmap_ctrl_input = esp_partition_get_file_mmap_ctrl_input();
-    TEST_ASSERT_NOT_NULL(p_file_mmap_ctrl_input);
-
-    memset(p_file_mmap_ctrl_input, 0, sizeof(*p_file_mmap_ctrl_input));
-
-    // set valid partition table name and very small flash size
-    strlcpy(p_file_mmap_ctrl_input->partition_file_name, BUILD_DIR "/partition_table/partition-table.bin", sizeof(p_file_mmap_ctrl_input->partition_file_name));
-    p_file_mmap_ctrl_input->flash_file_size = 1;
-
-    const uint8_t *p_mem_block = NULL;
-    esp_err_t err = esp_partition_file_mmap(&p_mem_block);
-
-    // expected result is invalid argument
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_SIZE, err);
-
-    // cleanup after test
-    esp_partition_file_munmap();
-    memset(p_file_mmap_ctrl_input, 0, sizeof(*p_file_mmap_ctrl_input));
-}
-
 typedef struct {
     size_t read_ops;
     size_t write_ops;
@@ -772,6 +752,7 @@ TEST_GROUP_RUNNER(partition_api)
     RUN_TEST_CASE(partition_api, test_partition_find_first);
     RUN_TEST_CASE(partition_api, test_partition_ops);
     RUN_TEST_CASE(partition_api, test_partition_mmap);
+    RUN_TEST_CASE(partition_api, test_partition_mmap_support_for_greater_than_4M);
     RUN_TEST_CASE(partition_api, test_partition_mmap_diff_size);
     RUN_TEST_CASE(partition_api, test_partition_mmap_reopen);
     RUN_TEST_CASE(partition_api, test_partition_mmap_remove);
@@ -780,7 +761,6 @@ TEST_GROUP_RUNNER(partition_api)
     RUN_TEST_CASE(partition_api, test_partition_mmap_no_size_partition);
     RUN_TEST_CASE(partition_api, test_partition_mmap_ffile_nf);
     RUN_TEST_CASE(partition_api, test_partition_mmap_pfile_nf);
-    RUN_TEST_CASE(partition_api, test_partition_mmap_size_too_small);
     RUN_TEST_CASE(partition_api, test_partition_stats);
     RUN_TEST_CASE(partition_api, test_partition_power_off_emulation);
     RUN_TEST_CASE(partition_api, test_partition_copy);
diff --git a/components/esp_partition/partition_linux.c b/components/esp_partition/partition_linux.c
index 530100276080..ec8947399d74 100644
--- a/components/esp_partition/partition_linux.c
+++ b/components/esp_partition/partition_linux.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,6 +8,7 @@
 #include <assert.h>
 #include <string.h>
 #include <inttypes.h>
+#include <stdio.h>
 #include <sys/mman.h>
 #include <sys/stat.h>
 #include <fcntl.h>
@@ -110,6 +111,64 @@ const char *esp_partition_subtype_to_str(const uint32_t type, const uint32_t sub
     }
 }
 
+// Calculate required emulated flash size from a partition table binary.
+// Returns 0 on failure.
+static size_t esp_partition_calc_required_flash_size_from_file(const char *partition_file_path)
+{
+    if (partition_file_path == NULL || partition_file_path[0] == '\0') {
+        return 0;
+    }
+
+    FILE *fp = fopen(partition_file_path, "rb");
+    if (fp == NULL) {
+        return 0;
+    }
+
+    // Determine file size as an additional lower bound
+    if (fseek(fp, 0L, SEEK_END) != 0) {
+        fclose(fp);
+        return 0;
+    }
+    long file_size = ftell(fp);
+    if (file_size < 0) {
+        fclose(fp);
+        return 0;
+    }
+    if (fseek(fp, 0L, SEEK_SET) != 0) {
+        fclose(fp);
+        return 0;
+    }
+
+    size_t max_end = 0;
+    size_t max_entries = file_size / sizeof(esp_partition_info_t);
+    for (size_t i = 0; i < max_entries; i++) {
+        esp_partition_info_t entry;
+        size_t r = fread(&entry, 1, sizeof(entry), fp);
+        if (r != sizeof(entry) || entry.magic != ESP_PARTITION_MAGIC) {
+            break;
+        }
+        uint32_t end = entry.pos.offset + entry.pos.size;
+        if (end > max_end) {
+            max_end = end;
+        }
+    }
+
+    fclose(fp);
+
+    // Also ensure the flash holds the partition table itself at its offset
+    size_t min_from_table_blob = (size_t)file_size + ESP_PARTITION_TABLE_OFFSET;
+    size_t required = (max_end > min_from_table_blob) ? max_end : min_from_table_blob;
+
+    // Round up to emulated sector size
+    size_t sector = ESP_PARTITION_EMULATED_SECTOR_SIZE;
+    size_t rem = required % sector;
+    if (rem != 0) {
+        required += (sector - rem);
+    }
+
+    return required;
+}
+
 esp_err_t esp_partition_file_mmap(const uint8_t **part_desc_addr_start)
 {
     // temporary file is used only if control structure doesn't specify file name.
@@ -136,21 +195,10 @@ esp_err_t esp_partition_file_mmap(const uint8_t **part_desc_addr_start)
 
         open_existing_file = true;
     } else {
-        // Open temporary file. If size was specified, also partition table has to be specified, otherwise raise error.
-        // If none of size, partition table were specified, defaults are used.
-        // Name of temporary file is available in s_esp_partition_file_mmap_ctrl.flash_file_name
-
+        // name of temporary file and its size is available in s_esp_partition_file_mmap_ctrl.flash_file_name and s_esp_partition_file_mmap_ctrl_input.flash_file_size respectively
         bool has_partfile = (strlen(s_esp_partition_file_mmap_ctrl_input.partition_file_name) > 0);
         bool has_len = (s_esp_partition_file_mmap_ctrl_input.flash_file_size > 0);
 
-        // conflicting input
-        if (has_partfile != has_len) {
-            ESP_LOGE(TAG, "Invalid combination of Partition file name: %s flash file size: %" PRIu32 " was specified. Use either both parameters or none.",
-                     s_esp_partition_file_mmap_ctrl_input.partition_file_name,
-                     (uint32_t) s_esp_partition_file_mmap_ctrl_input.flash_file_size);
-            return ESP_ERR_INVALID_ARG;
-        }
-
         // check if partition file is present, if not, use default
         if (!has_partfile) {
             strlcpy(s_esp_partition_file_mmap_ctrl_act.partition_file_name, BUILD_DIR "/partition_table/partition-table.bin", sizeof(s_esp_partition_file_mmap_ctrl_act.partition_file_name));
@@ -158,10 +206,13 @@ esp_err_t esp_partition_file_mmap(const uint8_t **part_desc_addr_start)
             strlcpy(s_esp_partition_file_mmap_ctrl_act.partition_file_name, s_esp_partition_file_mmap_ctrl_input.partition_file_name, sizeof(s_esp_partition_file_mmap_ctrl_act.partition_file_name));
         }
 
-        // check if flash size is present, if not set to default
-        if (!has_len) {
-            s_esp_partition_file_mmap_ctrl_act.flash_file_size = ESP_PARTITION_DEFAULT_EMULATED_FLASH_SIZE;
-        } else {
+        // derive the partition size from the s_esp_partition_file_mmap_ctrl_act.partition_file_name
+        size_t derived_size = esp_partition_calc_required_flash_size_from_file(s_esp_partition_file_mmap_ctrl_act.partition_file_name);
+        // if derived size is zero, use default partition size
+        s_esp_partition_file_mmap_ctrl_act.flash_file_size = (derived_size > 0) ? derived_size : ESP_PARTITION_DEFAULT_EMULATED_FLASH_SIZE;
+
+        // if the size of the temporary file is specified, check if the given partition size fits within it
+        if (has_len && s_esp_partition_file_mmap_ctrl_input.flash_file_size > derived_size) {
             s_esp_partition_file_mmap_ctrl_act.flash_file_size = s_esp_partition_file_mmap_ctrl_input.flash_file_size;
         }
 
@@ -382,7 +433,7 @@ esp_err_t esp_partition_file_munmap(void)
 
 esp_err_t esp_partition_write(const esp_partition_t *partition, size_t dst_offset, const void *src, size_t size)
 {
-    assert(partition != NULL && s_spiflash_mem_file_buf != NULL);
+    assert(partition != NULL && s_spiflash_mem_file_buf != NULL && src != NULL);
 
     if (partition->readonly) {
         return ESP_ERR_NOT_ALLOWED;
@@ -397,6 +448,15 @@ esp_err_t esp_partition_write(const esp_partition_t *partition, size_t dst_offse
         return ESP_ERR_INVALID_SIZE;
     }
 
+    // Ensure write stays within mapped flash file size
+    if (s_esp_partition_file_mmap_ctrl_act.flash_file_size > 0) {
+        size_t start = (size_t)partition->address + dst_offset;
+        size_t max_len = s_esp_partition_file_mmap_ctrl_act.flash_file_size;
+        if ((start > max_len) || ((size + start) > max_len)) {
+            return ESP_ERR_INVALID_SIZE;
+        }
+    }
+
     void *dst_addr = s_spiflash_mem_file_buf + partition->address + dst_offset;
     ESP_LOGV(TAG, "esp_partition_write(): partition=%s dst_offset=%" PRIu32 " src=%p size=%" PRIu32 " (real dst address: %p)", partition->label, (uint32_t) dst_offset, src, (uint32_t) size, dst_addr);
 
@@ -432,7 +492,7 @@ esp_err_t esp_partition_write(const esp_partition_t *partition, size_t dst_offse
 
 esp_err_t esp_partition_read(const esp_partition_t *partition, size_t src_offset, void *dst, size_t size)
 {
-    assert(partition != NULL && s_spiflash_mem_file_buf != NULL);
+    assert(partition != NULL && s_spiflash_mem_file_buf != NULL && dst != NULL);
 
     if (partition->encrypted) {
         return  ESP_ERR_NOT_SUPPORTED;
@@ -444,6 +504,15 @@ esp_err_t esp_partition_read(const esp_partition_t *partition, size_t src_offset
         return ESP_ERR_INVALID_SIZE;
     }
 
+    // Ensure read stays within mapped flash file size
+    if (s_esp_partition_file_mmap_ctrl_act.flash_file_size > 0) {
+        size_t start = (size_t)partition->address + src_offset;
+        size_t max_len = s_esp_partition_file_mmap_ctrl_act.flash_file_size;
+        if ((start > max_len) || ((size + start) > max_len)) {
+            return ESP_ERR_INVALID_SIZE;
+        }
+    }
+
     void *src_addr = s_spiflash_mem_file_buf + partition->address + src_offset;
     ESP_LOGV(TAG, "esp_partition_read(): partition=%s src_offset=%" PRIu32 " dst=%p size=%" PRIu32 " (real src address: %p)", partition->label, (uint32_t) src_offset, dst, (uint32_t) size, src_addr);
 
@@ -468,7 +537,7 @@ esp_err_t esp_partition_write_raw(const esp_partition_t *partition, size_t dst_o
 
 esp_err_t esp_partition_erase_range(const esp_partition_t *partition, size_t offset, size_t size)
 {
-    assert(partition != NULL);
+    assert(partition != NULL && s_spiflash_mem_file_buf != NULL);
 
     if (partition->readonly) {
         return ESP_ERR_NOT_ALLOWED;
@@ -480,6 +549,15 @@ esp_err_t esp_partition_erase_range(const esp_partition_t *partition, size_t off
         return ESP_ERR_INVALID_SIZE;
     }
 
+    // Ensure erase stays within mapped flash file size
+    if (s_esp_partition_file_mmap_ctrl_act.flash_file_size > 0) {
+        size_t start = (size_t)partition->address + offset;
+        size_t max_len = s_esp_partition_file_mmap_ctrl_act.flash_file_size;
+        if ((start > max_len) || ((size + start) > max_len)) {
+            return ESP_ERR_INVALID_SIZE;
+        }
+    }
+
     void *target_addr = s_spiflash_mem_file_buf + partition->address + offset;
     ESP_LOGV(TAG, "esp_partition_erase_range(): partition=%s offset=%" PRIu32 " size=%" PRIu32 " (real target address: %p)", partition->label, (uint32_t) offset, (uint32_t) size, target_addr);
 
diff --git a/components/esp_phy/lib b/components/esp_phy/lib
index 45ce27034037..218d3e79a323 160000
--- a/components/esp_phy/lib
+++ b/components/esp_phy/lib
@@ -1 +1 @@
-Subproject commit 45ce2703403784b4c3983a52e453988d61eb0e9d
+Subproject commit 218d3e79a323a437b5f994c32fe7b2144f54ca8c
diff --git a/components/esp_psram/Kconfig.spiram.common b/components/esp_psram/Kconfig.spiram.common
index b04cacbd9293..ea16849a521b 100644
--- a/components/esp_psram/Kconfig.spiram.common
+++ b/components/esp_psram/Kconfig.spiram.common
@@ -69,7 +69,6 @@ choice SPIRAM_USE
         return SPI RAM pointers.
 
     config SPIRAM_USE_MEMMAP
-        depends on IDF_TARGET_ESP32
         bool "Integrate RAM into memory map"
     config SPIRAM_USE_CAPS_ALLOC
         bool "Make RAM allocatable using heap_caps_malloc(..., MALLOC_CAP_SPIRAM)"
diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
index 6742c76aba97..3a0dafc1e46d 100644
--- a/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
+++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
@@ -156,7 +156,7 @@ systimer_hal_set_tick_rate_ops = 0x40002eac;
 /* Functions */
 sta_reset_beacon_timeout = 0x40003024;
 ieee80211_post_hmac_tx = 0x40003028;
-sta_rx_eapol = 0x4000302c;
+//sta_rx_eapol = 0x4000302c;
 /* Data (.data, .bss, .rodata) */
 len_dh_ie_ptr = 0x3fcdfa6c;
 g_authmode_threshold_failure_ptr = 0x3fcdfa68;
diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld
index b10a95bf2528..b83061f0c58b 100644
--- a/components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld
+++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld
@@ -66,7 +66,7 @@ wifi_rf_phy_disable = 0x40000bc8;
 wifi_rf_phy_enable = 0x40000bcc;
 wifi_is_started = 0x40000bd0;
 /*sta_input = 0x40000bd4;*/
-sta_rx_eapol = 0x40000bd8;
+//sta_rx_eapol = 0x40000bd8;
 //sta_reset_beacon_timeout = 0x40000bdc;
 sta_get_beacon_timeout = 0x40000be0;
 ampdu_process_multicast_address_qos_frame = 0x40000be4;
diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld
index 93c0457081db..4abb61d6e500 100644
--- a/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld
+++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld
@@ -62,7 +62,7 @@ wifi_rf_phy_disable = 0x40000b30;
 wifi_rf_phy_enable = 0x40000b34;
 wifi_is_started = 0x40000b38;
 /*sta_input = 0x40000b3c;*/
-sta_rx_eapol = 0x40000b40;
+//sta_rx_eapol = 0x40000b40;
 //sta_reset_beacon_timeout = 0x40000b44;
 sta_get_beacon_timeout = 0x40000b48;
 ampdu_process_multicast_address_qos_frame = 0x40000b4c;
diff --git a/components/esp_security/src/init.c b/components/esp_security/src/init.c
index 237bb03753cc..16ef897badd4 100644
--- a/components/esp_security/src/init.c
+++ b/components/esp_security/src/init.c
@@ -90,7 +90,7 @@ ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103)
 #if CONFIG_SECURE_BOOT_V2_ENABLED
 // H2, H21
 #if SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
-    // Also write protects the ECDSA_CURVE_MODE efuse bit.
+    // Also write protects the ECC_FORCE_CONST_TIME efuse bit.
     if (ecdsa_ll_is_configurable_curve_supported()) {
         err = esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_ECDSA_CURVE_MODE);
         if (err != ESP_OK) {
@@ -102,10 +102,13 @@ ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103)
 
 #if !CONFIG_SECURE_BOOT_SKIP_WRITE_PROTECTION_SCA
 // C5
-#if SOC_ECDSA_SUPPORT_CURVE_P384 && !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
+#if SOC_ECDSA_SUPPORT_CURVE_P384 && !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS && !CONFIG_IDF_TARGET_ESP32P4
     // Since SECURE_BOOT_SHA384_EN, XTS_DPA_PSEUDO_LEVEL, and ECC_FORCE_CONST_TIME share the
     // same write-protection bit, these efuses should only be write-protected after all of
     // them have been programmed.
+    // Note: ESP32-P4 lacks WR_DIS_SECURE_BOOT_SHA384_EN bit, so it relies on software protection
+    // in the efuse write APIs (see esp_efuse_api.c) to prevent unauthorized programming of
+    // SECURE_BOOT_SHA384_EN when Secure Boot using SHA-256 is enabled.
     err = esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_SECURE_BOOT_SHA384_EN);
     if (err != ESP_OK) {
         ESP_LOGE(TAG, "Failed to write protect the SECURE_BOOT_SHA384_EN efuse bit.");
diff --git a/components/esp_tee/subproject/components/tee_sec_storage/tee_sec_storage.c b/components/esp_tee/subproject/components/tee_sec_storage/tee_sec_storage.c
index ff6ef16cfd3a..0868e386066a 100644
--- a/components/esp_tee/subproject/components/tee_sec_storage/tee_sec_storage.c
+++ b/components/esp_tee/subproject/components/tee_sec_storage/tee_sec_storage.c
@@ -643,11 +643,12 @@ esp_err_t esp_tee_sec_storage_ecdsa_sign_pbkdf2(const esp_tee_sec_storage_pbkdf2
         return ESP_ERR_INVALID_ARG;
     }
 
-    hmac_key_id_t key_id = (hmac_key_id_t)(CONFIG_SECURE_TEE_PBKDF2_EFUSE_HMAC_KEY_ID);
-    if (key_id < 0 || key_id >= HMAC_KEY_MAX) {
+    int cfg_key_id = (int)CONFIG_SECURE_TEE_PBKDF2_EFUSE_HMAC_KEY_ID;
+    if (cfg_key_id < 0 || cfg_key_id >= HMAC_KEY_MAX) {
         return ESP_ERR_INVALID_ARG;
     }
 
+    hmac_key_id_t key_id = (hmac_key_id_t)cfg_key_id;
     esp_efuse_block_t blk = (esp_efuse_block_t)(EFUSE_BLK_KEY0 + key_id);
     if (esp_efuse_get_key_purpose(blk) != ESP_EFUSE_KEY_PURPOSE_HMAC_UP) {
         ESP_LOGE(TAG, "HMAC key is not burnt in the specified eFuse block ID");
diff --git a/components/esp_tee/test_apps/tee_test_fw/main/test_esp_tee_flash_prot.c b/components/esp_tee/test_apps/tee_test_fw/main/test_esp_tee_flash_prot.c
index 9a7e68afc491..030e6ff1c8ca 100644
--- a/components/esp_tee/test_apps/tee_test_fw/main/test_esp_tee_flash_prot.c
+++ b/components/esp_tee/test_apps/tee_test_fw/main/test_esp_tee_flash_prot.c
@@ -48,12 +48,6 @@ __attribute__((unused)) static const uint32_t mmu_op_fail_seq[8] = {[0 ... 7] =
     } while (0)
 #endif
 
-#if SOC_TEE_FLASH_OP_FAIL_FAULT
-#define CHECK_FLASH_OP_FAIL(err) TEST_ESP_ERR(ESP_FAIL, err)
-#else
-#define CHECK_FLASH_OP_FAIL(err) do { (void)(err); esp_restart(); } while (0)
-#endif
-
 static const char *TAG = "test_esp_tee_flash_prot";
 
 static void set_boot_count_in_nvs(uint8_t boot_count)
@@ -146,8 +140,7 @@ static void test_esp_partition_api_r(const esp_partition_t *part)
     TEST_ASSERT_NOT_NULL(part);
     uint8_t buf_r[128];
     memset(buf_r, 0x00, sizeof(buf_r));
-    esp_err_t err = esp_partition_read(part, 0x00, buf_r, sizeof(buf_r));
-    CHECK_FLASH_OP_FAIL(err);
+    esp_partition_read(part, 0x00, buf_r, sizeof(buf_r));
 }
 
 static void test_esp_partition_api_w(const esp_partition_t *part)
@@ -155,15 +148,13 @@ static void test_esp_partition_api_w(const esp_partition_t *part)
     TEST_ASSERT_NOT_NULL(part);
     uint8_t buf_w[128];
     memset(buf_w, 0xA5, sizeof(buf_w));
-    esp_err_t err = esp_partition_write(part, 0x00, buf_w, sizeof(buf_w));
-    CHECK_FLASH_OP_FAIL(err);
+    esp_partition_write(part, 0x00, buf_w, sizeof(buf_w));
 }
 
 static void test_esp_partition_api_e(const esp_partition_t *part)
 {
     TEST_ASSERT_NOT_NULL(part);
-    esp_err_t err = esp_partition_erase_range(part, 0x00, SPI_FLASH_SEC_SIZE);
-    CHECK_FLASH_OP_FAIL(err);
+    esp_partition_erase_range(part, 0x00, SPI_FLASH_SEC_SIZE);
 }
 
 static void test_esp_partition_api(void)
@@ -267,22 +258,19 @@ static void test_esp_flash_api_r(uint32_t paddr)
 {
     uint8_t buf_r[128];
     memset(buf_r, 0x00, sizeof(buf_r));
-    esp_err_t err = esp_flash_read(NULL, buf_r, paddr, sizeof(buf_r));
-    CHECK_FLASH_OP_FAIL(err);
+    esp_flash_read(NULL, buf_r, paddr, sizeof(buf_r));
 }
 
 static void test_esp_flash_api_w(uint32_t paddr)
 {
     uint8_t buf_w[128];
     memset(buf_w, 0xA5, sizeof(buf_w));
-    esp_err_t err = esp_flash_write(NULL, buf_w, paddr, sizeof(buf_w));
-    CHECK_FLASH_OP_FAIL(err);
+    esp_flash_write(NULL, buf_w, paddr, sizeof(buf_w));
 }
 
 static void test_esp_flash_api_e(uint32_t paddr)
 {
-    esp_err_t err = esp_flash_erase_region(NULL, paddr, SPI_FLASH_SEC_SIZE);
-    CHECK_FLASH_OP_FAIL(err);
+    esp_flash_erase_region(NULL, paddr, SPI_FLASH_SEC_SIZE);
 }
 
 static void test_esp_flash_api(void)
diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib
index f1df1ec2879a..3fa82c561aa1 160000
--- a/components/esp_wifi/lib
+++ b/components/esp_wifi/lib
@@ -1 +1 @@
-Subproject commit f1df1ec2879aeec855bd97f7c584404b43acd673
+Subproject commit 3fa82c561aa1722d92c1da8b571a09c466629bdd
diff --git a/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_psram.c b/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_psram.c
index 866b4e4bba4a..ea6413883e39 100644
--- a/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_psram.c
+++ b/components/freertos/test_apps/freertos/kernel/tasks/test_freertos_psram.c
@@ -140,6 +140,9 @@ TEST_CASE("Task on specific core works", "[freertos][psram]")
         TEST_ASSERT_EQUAL((size_t) corenum, corenum_info.recorded_core_num);
 
         vTaskDelete(task_handle);
+
+        // Add a short delay to allow the idle task to free any remaining task memory
+        vTaskDelay(10);
     }
 }
 #endif // !CONFIG_FREERTOS_UNICORE
diff --git a/components/freertos/test_apps/freertos/kernel/tasks/test_vTaskSuspendAll_xTaskResumeAll.c b/components/freertos/test_apps/freertos/kernel/tasks/test_vTaskSuspendAll_xTaskResumeAll.c
index e6dd88c7aa6a..746540bc0209 100644
--- a/components/freertos/test_apps/freertos/kernel/tasks/test_vTaskSuspendAll_xTaskResumeAll.c
+++ b/components/freertos/test_apps/freertos/kernel/tasks/test_vTaskSuspendAll_xTaskResumeAll.c
@@ -394,6 +394,7 @@ TEST_CASE("Test vTaskSuspendAll allows scheduling on other cores", "[freertos]")
         // Cleanup tasks
         vTaskDelete(a1_task_hdl);
         vTaskDelete(b1_task_hdl);
+        vTaskDelay(10);
     }
 
     vSemaphoreDelete(test_unblk_done_sem);
diff --git a/components/freertos/test_apps/freertos/kernel/tasks/test_yielding.c b/components/freertos/test_apps/freertos/kernel/tasks/test_yielding.c
index 6da218976f75..9d5d7b2c5e6a 100644
--- a/components/freertos/test_apps/freertos/kernel/tasks/test_yielding.c
+++ b/components/freertos/test_apps/freertos/kernel/tasks/test_yielding.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -34,6 +34,9 @@ static volatile uint32_t count;
 // Lock variable to create a blocked task scenario
 static volatile SemaphoreHandle_t task_mutex;
 
+// Semaphore to synchronize yield test tasks
+static SemaphoreHandle_t yield_sync_sem;
+
 // This helper macro is used to store the task id atomically
 #define STORE_TASK_ID(task_id)  ({ \
         portENTER_CRITICAL(&idx_lock); \
@@ -56,10 +59,11 @@ static void yield_task1(void *arg)
     /* Store task_id in the sequence array */
     STORE_TASK_ID(task_id);
 
-    /* Notify the yield_task2 to run */
-    task_sequence_ready = true;
+    /* Give semaphore to unblock yield_task2, making it READY (not just setting a flag).
+     * This ensures task2 is in the ready queue when we yield. */
+    xSemaphoreGive(yield_sync_sem);
 
-    /* Yield */
+    /* Yield - now task2 is guaranteed to be READY and should run next */
     taskYIELD();
 
     /* Increment task count to notify unity task */
@@ -73,10 +77,9 @@ static void yield_task2(void *arg)
 {
     uint32_t task_id = (uint32_t)arg;
 
-    /* Wait for the other task to run for the test to begin */
-    while (!task_sequence_ready) {
-        vTaskDelay(10);
-    };
+    /* Block on semaphore - this ensures task1 runs first and we don't poll.
+     * When task1 gives the semaphore, we transition directly to READY state. */
+    xSemaphoreTake(yield_sync_sem, portMAX_DELAY);
 
     /* Store task_id in the sequence array */
     STORE_TASK_ID(task_id);
@@ -108,9 +111,16 @@ TEST_CASE("Task yield must run the next ready task of the same priority", "[free
     /* Reset task sequence flag */
     task_sequence_ready = false;
 
-    /* Create test tasks */
-    xTaskCreatePinnedToCore(yield_task1, "yield_task1", 2048, (void *)1, UNITY_FREERTOS_PRIORITY - 1, NULL, UNITY_FREERTOS_CPU);
+    /* Create semaphore for synchronization - start empty so task2 blocks */
+    yield_sync_sem = xSemaphoreCreateBinary();
+    TEST_ASSERT_NOT_NULL(yield_sync_sem);
+
+    /* Create test tasks - order matters!
+     * Task2 is created first and will immediately block on the semaphore.
+     * Task1 is created second and will run first since task2 is blocked. */
     xTaskCreatePinnedToCore(yield_task2, "yield_task2", 2048, (void *)2, UNITY_FREERTOS_PRIORITY - 1, NULL, UNITY_FREERTOS_CPU);
+    vTaskDelay(1); /* Ensure task2 has blocked on semaphore before creating task1 */
+    xTaskCreatePinnedToCore(yield_task1, "yield_task1", 2048, (void *)1, UNITY_FREERTOS_PRIORITY - 1, NULL, UNITY_FREERTOS_CPU);
 
     /* Wait for the tasks to finish up */
     while (count != 2) {
@@ -122,6 +132,9 @@ TEST_CASE("Task yield must run the next ready task of the same priority", "[free
     /* Verify that the yield is successful and the next ready task is run */
     TEST_ASSERT_EQUAL(1, task_yield_sequence[idx++]);
     TEST_ASSERT_EQUAL(2, task_yield_sequence[idx++]);
+
+    /* Clean up semaphore */
+    vSemaphoreDelete(yield_sync_sem);
 }
 
 /*
diff --git a/components/freertos/test_apps/freertos/misc/test_tickless_idle.c b/components/freertos/test_apps/freertos/misc/test_tickless_idle.c
index 7ed64ddf354e..aa73b5346c5d 100644
--- a/components/freertos/test_apps/freertos/misc/test_tickless_idle.c
+++ b/components/freertos/test_apps/freertos/misc/test_tickless_idle.c
@@ -10,6 +10,7 @@
 #include "freertos/semphr.h"
 #include "esp_pm.h"
 #include "esp_private/esp_clk.h"
+#include "esp_clk_tree.h"
 
 #include "sdkconfig.h"
 
@@ -66,9 +67,11 @@ static void consumer_task(void *arg)
 TEST_CASE("Test semaphore timeout during tickless idle", "[freertos]")
 {
     // Configure tickless idle
+    uint32_t xtal_hz = 0;
+    esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_XTAL, ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT, &xtal_hz);
     esp_pm_config_t pm_config = {
-        .max_freq_mhz = esp_clk_cpu_freq() / MHZ,
-        .min_freq_mhz = esp_clk_cpu_freq() / MHZ,
+        .max_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ,
+        .min_freq_mhz = xtal_hz / MHZ,
         .light_sleep_enable = true,
     };
     TEST_ESP_OK(esp_pm_configure(&pm_config));
diff --git a/components/hal/cam_hal.c b/components/hal/cam_hal.c
index c739f05d91f8..f4f8ee8577ff 100644
--- a/components/hal/cam_hal.c
+++ b/components/hal/cam_hal.c
@@ -74,7 +74,7 @@ void cam_hal_init(cam_hal_context_t *hal, const cam_hal_config_t *config)
 
     cam_ll_enable_stop_signal(hal->hw, 0);
     cam_ll_swap_dma_data_byte_order(hal->hw, config->byte_swap_en);
-    cam_ll_reverse_dma_data_bit_order(hal->hw, 0);
+    cam_ll_reverse_dma_data_bit_order(hal->hw, config->bit_swap_en);
     cam_ll_enable_vsync_generate_eof(hal->hw, 1);
 
     cam_hal_set_line_int_num(hal, 0);
diff --git a/components/hal/esp32/include/hal/adc_ll.h b/components/hal/esp32/include/hal/adc_ll.h
index 97cc5de8c789..d4cca33a47d7 100644
--- a/components/hal/esp32/include/hal/adc_ll.h
+++ b/components/hal/esp32/include/hal/adc_ll.h
@@ -26,6 +26,8 @@ extern "C" {
 #define ADC_LL_EVENT_ADC1_ONESHOT_DONE    (1 << 0)
 #define ADC_LL_EVENT_ADC2_ONESHOT_DONE    (1 << 1)
 
+#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
+
 /*---------------------------------------------------------------
                     Oneshot
 ---------------------------------------------------------------*/
diff --git a/components/hal/esp32c3/include/hal/adc_ll.h b/components/hal/esp32c3/include/hal/adc_ll.h
index d273eaf70f3b..93ef061fd299 100644
--- a/components/hal/esp32c3/include/hal/adc_ll.h
+++ b/components/hal/esp32c3/include/hal/adc_ll.h
@@ -38,6 +38,8 @@ extern "C" {
 #define ADC_LL_GET_HIGH_THRES_MASK(monitor_id)    ((monitor_id == 0) ? APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_THRES1_HIGH_INT_ST_M)
 #define ADC_LL_GET_LOW_THRES_MASK(monitor_id)     ((monitor_id == 0) ? APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_THRES1_LOW_INT_ST_M)
 
+#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
+
 /*---------------------------------------------------------------
                     Oneshot
 ---------------------------------------------------------------*/
diff --git a/components/hal/esp32c5/include/hal/adc_ll.h b/components/hal/esp32c5/include/hal/adc_ll.h
index f0e914e7bcd1..aebb2557cff1 100644
--- a/components/hal/esp32c5/include/hal/adc_ll.h
+++ b/components/hal/esp32c5/include/hal/adc_ll.h
@@ -40,6 +40,8 @@ extern "C" {
 #define ADC_LL_GET_LOW_THRES_MASK(monitor_id)     ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
 
 #define ADC_LL_ADC_FE_ON_MODEM_DOMAIN               (1)
+
+#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
 /*---------------------------------------------------------------
                     Oneshot
 ---------------------------------------------------------------*/
diff --git a/components/hal/esp32c6/include/hal/adc_ll.h b/components/hal/esp32c6/include/hal/adc_ll.h
index 11c89c5cde8c..185fe69af493 100644
--- a/components/hal/esp32c6/include/hal/adc_ll.h
+++ b/components/hal/esp32c6/include/hal/adc_ll.h
@@ -39,6 +39,8 @@ extern "C" {
 #define ADC_LL_GET_LOW_THRES_MASK(monitor_id)     ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
 
 #define ADC_LL_ADC_FE_ON_MODEM_DOMAIN               (1)
+
+#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
 /*---------------------------------------------------------------
                     Oneshot
 ---------------------------------------------------------------*/
diff --git a/components/hal/esp32c61/include/hal/adc_ll.h b/components/hal/esp32c61/include/hal/adc_ll.h
index 5f1d12c93385..9e14aaf3a897 100644
--- a/components/hal/esp32c61/include/hal/adc_ll.h
+++ b/components/hal/esp32c61/include/hal/adc_ll.h
@@ -40,6 +40,8 @@ extern "C" {
 #define ADC_LL_GET_LOW_THRES_MASK(monitor_id)     ((monitor_id == 0) ? SARADC_THRES0_LOW_INT_ST_M : SARADC_THRES1_LOW_INT_ST_M)
 
 #define ADC_LL_ADC_FE_ON_MODEM_DOMAIN               (1)
+
+#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
 /*---------------------------------------------------------------
                     Oneshot
 ---------------------------------------------------------------*/
diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h
index 8e0791bc4e8e..b0b47b913f57 100644
--- a/components/hal/esp32h2/include/hal/adc_ll.h
+++ b/components/hal/esp32h2/include/hal/adc_ll.h
@@ -39,6 +39,8 @@ extern "C" {
 #define ADC_LL_GET_LOW_THRES_MASK(monitor_id)     ((monitor_id == 0) ? APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M)
 
 #define ADC_LL_ADC_FE_ON_MODEM_DOMAIN               (1)
+
+#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
 /*---------------------------------------------------------------
                     Oneshot
 ---------------------------------------------------------------*/
diff --git a/components/hal/esp32p4/include/hal/adc_ll.h b/components/hal/esp32p4/include/hal/adc_ll.h
index faffd7a9cd3a..b52394bfc0dc 100644
--- a/components/hal/esp32p4/include/hal/adc_ll.h
+++ b/components/hal/esp32p4/include/hal/adc_ll.h
@@ -34,6 +34,11 @@ extern "C" {
 #define LP_ADC_FORCE_XPD_SAR_PD  2 // Force power down
 #define LP_ADC_FORCE_XPD_SAR_PU  3 // Force power up
 
+// ESP32P4 ADC2 channel is 2-7, so we need to subtract 2 to get the correct channel
+#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 2
+
+#define ADC_LL_NEED_APB_PERIPH_CLAIM(ADC_UNIT)      (((ADC_UNIT) == ADC_UNIT_1) ? 0 : 1)
+
 /*---------------------------------------------------------------
                     Oneshot
 ---------------------------------------------------------------*/
@@ -352,13 +357,14 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
     uint8_t offset = (pattern_index % 4) * 6;
     adc_ll_digi_pattern_table_t pattern = {0};
 
-    pattern.val = (table.atten & 0x3) | ((table.channel & 0xF) << 2);
     if (table.unit == ADC_UNIT_1){
+        pattern.val = (table.atten & 0x3) | ((table.channel & 0xF) << 2);
         tab = ADC.sar1_patt_tab[index].sar1_patt_tab;               //Read old register value
         tab &= (~(0xFC0000 >> offset));                             //Clear old data
         tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset;    //Fill in the new data
         ADC.sar1_patt_tab[index].sar1_patt_tab = tab;               //Write back
     } else {
+        pattern.val = (table.atten & 0x3) | (((table.channel + 2) & 0xF) << 2);
         tab = ADC.sar2_patt_tab[index].sar2_patt_tab;               //Read old register value
         tab &= (~(0xFC0000 >> offset));                             //clear old data
         tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset;    //Fill in the new data
diff --git a/components/hal/esp32p4/include/hal/ecdsa_ll.h b/components/hal/esp32p4/include/hal/ecdsa_ll.h
index b7d16aae0e7c..02dbadd3e212 100644
--- a/components/hal/esp32p4/include/hal/ecdsa_ll.h
+++ b/components/hal/esp32p4/include/hal/ecdsa_ll.h
@@ -11,6 +11,8 @@
 #include "soc/ecdsa_reg.h"
 #include "soc/hp_sys_clkrst_struct.h"
 #include "soc/soc_caps.h"
+#include "soc/efuse_reg.h"
+#include "soc/efuse_struct.h"
 #include "hal/ecdsa_types.h"
 
 #ifdef __cplusplus
@@ -440,6 +442,41 @@ static inline bool ecdsa_ll_is_deterministic_mode_supported(void)
     return true;
 }
 
+/**
+ * @brief Set the ECDSA key block in eFuse
+ *
+ * @param curve    ECDSA curve type
+ * @param efuse_blk eFuse block number
+ */
+__attribute__((always_inline)) static inline void ecdsa_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk)
+{
+#ifdef EFUSE_CFG_ECDSA_BLK
+    (void) curve;
+    EFUSE.conf.cfg_ecdsa_blk = efuse_blk;
+#else
+    uint8_t efuse_blk_low = 0;
+    uint8_t efuse_blk_high = 0;
+    switch (curve) {
+        case ECDSA_CURVE_SECP192R1:
+            EFUSE.ecdsa.cfg_ecdsa_p192_blk = efuse_blk;
+            break;
+        case ECDSA_CURVE_SECP256R1:
+            EFUSE.ecdsa.cfg_ecdsa_p256_blk = efuse_blk;
+            break;
+        case ECDSA_CURVE_SECP384R1:
+            // ECDSA-p384 uses two efuse blocks to store the key. These two blocks are stored in a single integer
+            // where the least significant 4 bits store the low key block number and the next 4 more significant bits store the high key block number.
+            HAL_ECDSA_EXTRACT_KEY_BLOCKS(efuse_blk, efuse_blk_high, efuse_blk_low);
+            EFUSE.ecdsa.cfg_ecdsa_p384_h_blk = efuse_blk_high;
+            EFUSE.ecdsa.cfg_ecdsa_p384_l_blk = efuse_blk_low;
+            break;
+        default:
+            HAL_ASSERT(false && "Unsupported curve");
+            break;
+    }
+#endif
+}
+
 /**
  * @brief Check if the ECDSA peripheral uses MPI module's memory
  */
diff --git a/components/hal/esp32p4/include/hal/efuse_ll.h b/components/hal/esp32p4/include/hal/efuse_ll.h
index 9011a8c50cbb..b2d6223ff47f 100644
--- a/components/hal/esp32p4/include/hal/efuse_ll.h
+++ b/components/hal/esp32p4/include/hal/efuse_ll.h
@@ -12,6 +12,7 @@
 #include "hal/assert.h"
 #include "rom/efuse.h"
 #include "hal/ecdsa_types.h"
+#include "hal/ecdsa_ll.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -94,8 +95,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(
 
 __attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk)
 {
-    (void) curve;
-    EFUSE.conf.cfg_ecdsa_blk = efuse_blk;
+    ecdsa_ll_set_ecdsa_key_blk(curve, efuse_blk);
 }
 
 /******************* eFuse control functions *************************/
diff --git a/components/hal/esp32p4/include/hal/temperature_sensor_ll.h b/components/hal/esp32p4/include/hal/temperature_sensor_ll.h
index 72c76d227327..760a09d668f5 100644
--- a/components/hal/esp32p4/include/hal/temperature_sensor_ll.h
+++ b/components/hal/esp32p4/include/hal/temperature_sensor_ll.h
@@ -25,6 +25,8 @@
 #include "soc/soc_caps.h"
 #include "soc/interrupts.h"
 #include "soc/soc_etm_source.h"
+#include "soc/efuse_reg.h"
+#include "soc/efuse_struct.h"
 #include "hal/temperature_sensor_types.h"
 #include "hal/assert.h"
 #include "hal/misc.h"
@@ -258,6 +260,23 @@ static inline void temperature_sensor_ll_set_sample_rate(uint16_t rate)
     HAL_FORCE_MODIFY_U32_REG_FIELD(LP_TSENS.sample_rate, sample_rate, rate);
 }
 
+/**
+ * @brief Retrieve and calculate the temperature sensor calibration value.
+ *
+ * @return Temperature calibration value.
+ */
+static inline int temperature_sensor_ll_load_calib_param(void)
+{
+#ifdef EFUSE_TEMPERATURE_SENSOR
+    uint32_t cal_temp = EFUSE.rd_sys_part2_data3.temperature_sensor;
+    // BIT(8) stands for sign: 1: negative, 0: positive
+    int tsens_cal = ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp;
+    return tsens_cal;
+#else
+    return 0;
+#endif
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32s2/include/hal/adc_ll.h b/components/hal/esp32s2/include/hal/adc_ll.h
index 50fe537ade45..bde4116bde67 100644
--- a/components/hal/esp32s2/include/hal/adc_ll.h
+++ b/components/hal/esp32s2/include/hal/adc_ll.h
@@ -36,6 +36,8 @@ extern "C" {
 #define ADC_LL_GET_HIGH_THRES_MASK(monitor_id)    ((monitor_id == 0) ? APB_SARADC_ADC1_THRES_INT_ST_M : APB_SARADC_ADC2_THRES_INT_ST_M)
 #define ADC_LL_GET_LOW_THRES_MASK(monitor_id)     ((monitor_id == 0) ? APB_SARADC_ADC1_THRES_INT_ST_M : APB_SARADC_ADC2_THRES_INT_ST_M)
 
+#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
+
 /*---------------------------------------------------------------
                     Oneshot
 ---------------------------------------------------------------*/
diff --git a/components/hal/esp32s3/include/hal/adc_ll.h b/components/hal/esp32s3/include/hal/adc_ll.h
index dafc5a0b81e9..2e14adad1c4f 100644
--- a/components/hal/esp32s3/include/hal/adc_ll.h
+++ b/components/hal/esp32s3/include/hal/adc_ll.h
@@ -38,6 +38,8 @@ extern "C" {
 #define ADC_LL_GET_HIGH_THRES_MASK(monitor_id)    ((monitor_id == 0) ? APB_SARADC_THRES0_HIGH_INT_ST_M : APB_SARADC_THRES1_HIGH_INT_ST_M)
 #define ADC_LL_GET_LOW_THRES_MASK(monitor_id)     ((monitor_id == 0) ? APB_SARADC_THRES0_LOW_INT_ST_M : APB_SARADC_THRES1_LOW_INT_ST_M)
 
+#define ADC_LL_UNIT2_CHANNEL_SUBSTRATION 0
+
 /*---------------------------------------------------------------
                     Oneshot
 ---------------------------------------------------------------*/
diff --git a/components/hal/include/hal/cam_hal.h b/components/hal/include/hal/cam_hal.h
index e63e6440e5cd..79901c3ee649 100644
--- a/components/hal/include/hal/cam_hal.h
+++ b/components/hal/include/hal/cam_hal.h
@@ -28,6 +28,8 @@ typedef struct cam_hal_context {
  */
 typedef struct cam_hal_config {
     int port;                               /*!< CAM port */
+    uint32_t cam_data_width;                /*!< CAM data width, 8 or 16 or 24 bit, default to 8 */
+    bool bit_swap_en;                       /*!< CAM enable bit swap */
     bool byte_swap_en;                      /*!< CAM enable byte swap */
 } cam_hal_config_t;
 
diff --git a/components/idf_test/include/esp32/idf_performance_target.h b/components/idf_test/include/esp32/idf_performance_target.h
index ca772c685f7e..9f39fefe9c81 100644
--- a/components/idf_test/include/esp32/idf_performance_target.h
+++ b/components/idf_test/include/esp32/idf_performance_target.h
@@ -22,11 +22,11 @@
 #define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB                                    4500
 
 #define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP                               19000
-#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP                              450000
+#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP                              750000
 #define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP                               33000
 #define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP                              950000
 #define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP                               90000
-#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP                              1900000
+#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP                              3000000
 
 // floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround)
 #define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV                                      70
diff --git a/components/idf_test/include/esp32s2/idf_performance_target.h b/components/idf_test/include/esp32s2/idf_performance_target.h
index 07baf2ca51d2..0d2b6f0dd36f 100644
--- a/components/idf_test/include/esp32s2/idf_performance_target.h
+++ b/components/idf_test/include/esp32s2/idf_performance_target.h
@@ -17,11 +17,11 @@
 #define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB                                    900
 
 #define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP                               13500
-#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP                              420000
+#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP                              650000
 #define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP                               36000
 #define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP                              960000
 #define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP                               62000
-#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP                              1850000
+#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP                              2850000
 
 #define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_NO_FILTER                 3
 #define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_2                  3
diff --git a/components/idf_test/include/esp32s3/idf_performance_target.h b/components/idf_test/include/esp32s3/idf_performance_target.h
index 9f485b382c27..3b2bbe3b42f8 100644
--- a/components/idf_test/include/esp32s3/idf_performance_target.h
+++ b/components/idf_test/include/esp32s3/idf_performance_target.h
@@ -15,11 +15,11 @@
 #define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB                                    900
 
 #define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP                               18000
-#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP                              490000
+#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP                              700000
 #define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP                               45000
 #define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP                              1300000
 #define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP                               80000
-#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP                              2500000
+#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP                              3500000
 
 // floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround)
 #define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV                                      70
diff --git a/components/ieee802154/driver/esp_ieee802154_debug.c b/components/ieee802154/driver/esp_ieee802154_debug.c
index 21c315c4b9bf..8aa30f26cc3d 100644
--- a/components/ieee802154/driver/esp_ieee802154_debug.c
+++ b/components/ieee802154/driver/esp_ieee802154_debug.c
@@ -210,8 +210,8 @@ void ieee802154_record_print(void)
 #if CONFIG_IEEE802154_RECORD_STATE
     ESP_EARLY_LOGW(IEEE802154_TAG, "Print the record state, current state index: %d", g_ieee802154_probe.state_index);
     for (uint8_t i = 0; i < IEEE802154_ASSERT_RECORD_STATE_SIZE; i++) {
-        ESP_EARLY_LOGW(IEEE802154_TAG, "index %2d: line:%5s, state:%10s, timestamp: %lld",
-            i, g_ieee802154_probe.state[i].line_str,
+        ESP_EARLY_LOGW(IEEE802154_TAG, "index %2d: line:%5lu, state:%10s, timestamp: %lld",
+            i, g_ieee802154_probe.state[i].line,
             ieee802154_state_string[g_ieee802154_probe.state[i].state],
             g_ieee802154_probe.state[i].timestamp);
     }
@@ -221,8 +221,8 @@ void ieee802154_record_print(void)
 #if CONFIG_IEEE802154_RECORD_CMD
     ESP_EARLY_LOGW(IEEE802154_TAG, "Print the record cmd, current cmd index: %d", g_ieee802154_probe.cmd_index);
     for (uint8_t i = 0; i < IEEE802154_ASSERT_RECORD_CMD_SIZE; i++) {
-        ESP_EARLY_LOGW(IEEE802154_TAG, "index %2d: line:%5s, cmd:%10s, timestamp: %lld",
-            i, g_ieee802154_probe.cmd[i].line_str,
+        ESP_EARLY_LOGW(IEEE802154_TAG, "index %2d: line:%5lu, cmd:%10s, timestamp: %lld",
+            i, g_ieee802154_probe.cmd[i].line,
             ieee802154_get_cmd_string(g_ieee802154_probe.cmd[i].cmd),
             g_ieee802154_probe.cmd[i].timestamp);
     }
diff --git a/components/ieee802154/private_include/esp_ieee802154_util.h b/components/ieee802154/private_include/esp_ieee802154_util.h
index b323367b9ceb..5efdac1c26e2 100644
--- a/components/ieee802154/private_include/esp_ieee802154_util.h
+++ b/components/ieee802154/private_include/esp_ieee802154_util.h
@@ -78,7 +78,7 @@ typedef struct {
 #if CONFIG_IEEE802154_RECORD_STATE
 #define IEEE802154_ASSERT_RECORD_STATE_SIZE CONFIG_IEEE802154_RECORD_STATE_SIZE
 #define ieee802154_set_state(a) do { s_ieee802154_state = a; \
-            sprintf(g_ieee802154_probe.state[g_ieee802154_probe.state_index].line_str, "%d", __LINE__); \
+            g_ieee802154_probe.state[g_ieee802154_probe.state_index].line = __LINE__; \
             g_ieee802154_probe.state[g_ieee802154_probe.state_index].timestamp = esp_timer_get_time(); \
             g_ieee802154_probe.state[g_ieee802154_probe.state_index++].state = a; \
             g_ieee802154_probe.state_index = \
@@ -89,7 +89,7 @@ typedef struct {
  * @brief The table of recording IEEE802154 state command.
  */
 typedef struct {
-    char line_str[5];           /*!< record which line in esp_ieee802154_dev.c changes the state */
+    uint32_t line;           /*!< record which line in esp_ieee802154_dev.c changes the state */
     ieee802154_state_t state;   /*!< record current radio state */
     uint64_t timestamp;         /*!< record timestamp */
 } ieee802154_state_info_t;
@@ -100,7 +100,7 @@ typedef struct {
 #if CONFIG_IEEE802154_RECORD_CMD
 #define IEEE802154_ASSERT_RECORD_CMD_SIZE CONFIG_IEEE802154_RECORD_CMD_SIZE
 #define ieee802154_set_cmd(a) do { ieee802154_ll_set_cmd(a); \
-            sprintf(g_ieee802154_probe.cmd[g_ieee802154_probe.cmd_index].line_str, "%d", __LINE__); \
+            g_ieee802154_probe.cmd[g_ieee802154_probe.cmd_index].line = __LINE__; \
             g_ieee802154_probe.cmd[g_ieee802154_probe.cmd_index].timestamp = esp_timer_get_time(); \
             g_ieee802154_probe.cmd[g_ieee802154_probe.cmd_index++].cmd = a; \
             g_ieee802154_probe.cmd_index = \
@@ -111,7 +111,7 @@ typedef struct {
  * @brief The table of recording IEEE802154 radio command.
  */
 typedef struct {
-    char line_str[5];           /*!< record which line in esp_ieee802154_dev.c set the command */
+    uint32_t line;           /*!< record which line in esp_ieee802154_dev.c set the command */
     ieee802154_ll_cmd_t cmd;    /*!< record current command */
     uint64_t timestamp;         /*!< record timestamp */
 } ieee802154_cmd_info_t;
diff --git a/components/mbedtls/CMakeLists.txt b/components/mbedtls/CMakeLists.txt
index d7257fa7a926..e389a3f3077c 100644
--- a/components/mbedtls/CMakeLists.txt
+++ b/components/mbedtls/CMakeLists.txt
@@ -233,9 +233,6 @@ endif()
 if((SHA_PERIPHERAL_TYPE STREQUAL "core" AND CONFIG_SOC_SHA_SUPPORT_DMA) OR AES_PERIPHERAL_TYPE STREQUAL "dma")
     target_link_libraries(mbedcrypto PRIVATE idf::esp_mm)
     if(CONFIG_SOC_SHA_GDMA OR CONFIG_SOC_AES_GDMA)
-        if(CONFIG_SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT)
-            target_link_libraries(mbedcrypto PRIVATE idf::bootloader_support)
-        endif()
         target_sources(mbedcrypto PRIVATE "${COMPONENT_DIR}/port/crypto_shared_gdma/esp_crypto_shared_gdma.c")
     endif()
 endif()
diff --git a/components/mbedtls/mbedtls b/components/mbedtls/mbedtls
index b5d87eaa6748..ffb280bb63c7 160000
--- a/components/mbedtls/mbedtls
+++ b/components/mbedtls/mbedtls
@@ -1 +1 @@
-Subproject commit b5d87eaa6748b7a6fa70593178c08b4480e9b71e
+Subproject commit ffb280bb63c78bfec1e1ab55040671768c85c923
diff --git a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c
index a4a3d7c43bf3..4cb5cd4429c5 100644
--- a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c
+++ b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c
@@ -41,9 +41,9 @@
 #include "aes/esp_aes_gcm.h"
 #endif
 
-#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
-#include "esp_flash_encrypt.h"
-#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
+#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
+#include "hal/efuse_hal.h"
+#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
 
 /* Max size of each chunk to process when output buffer is in unaligned external ram
    must be a multiple of block size
@@ -241,17 +241,17 @@ static int esp_aes_process_dma_ext_ram(esp_aes_context *ctx, const unsigned char
 
 /* When AES-DMA operations are carried out using external memory with external memory encryption enabled,
    we need to make sure that the addresses and the sizes of the buffers on which the DMA operates are 16 byte-aligned. */
-#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
-    if (esp_flash_encryption_enabled()) {
+#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
+    if (efuse_hal_flash_encryption_enabled()) {
         if (esp_ptr_external_ram(input) || esp_ptr_external_ram(output) || esp_ptr_in_drom(input) || esp_ptr_in_drom(output)) {
-            input_alignment = MAX(get_cache_line_size(input), SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT);
-            output_alignment = MAX(get_cache_line_size(output), SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT);
+            input_alignment = MAX(get_cache_line_size(input), SOC_GDMA_EXT_MEM_ENC_ALIGNMENT);
+            output_alignment = MAX(get_cache_line_size(output), SOC_GDMA_EXT_MEM_ENC_ALIGNMENT);
 
             input_heap_caps = MALLOC_CAP_8BIT | (esp_ptr_external_ram(input) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
             output_heap_caps = MALLOC_CAP_8BIT | (esp_ptr_external_ram(output) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
         }
     }
-#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
+#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
 
     if (realloc_input) {
         input_buf = heap_caps_aligned_alloc(input_alignment, chunk_len, input_heap_caps);
@@ -537,19 +537,19 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
         return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH;
     }
 
-#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
-    if (esp_flash_encryption_enabled()) {
+#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
+    if (efuse_hal_flash_encryption_enabled()) {
         if (esp_ptr_external_ram(input) || esp_ptr_external_ram(output) || esp_ptr_in_drom(input) || esp_ptr_in_drom(output)) {
-            if (((intptr_t)(input) & (SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
+            if (((intptr_t)(input) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
                 input_needs_realloc = true;
             }
 
-            if (((intptr_t)(output) & (SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
+            if (((intptr_t)(output) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
                 output_needs_realloc = true;
             }
         }
     }
-#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
+#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
 
     /* DMA cannot access memory in the iCache range, copy input to internal ram */
     if (!s_check_dma_capable(input)) {
@@ -1002,6 +1002,20 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
     if (block_bytes > 0) {
         /* Flush cache if input in external ram */
 #if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE)
+#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
+        if (efuse_hal_flash_encryption_enabled()) {
+            if (esp_ptr_external_ram(input) || esp_ptr_external_ram(output) || esp_ptr_in_drom(input) || esp_ptr_in_drom(output)) {
+                if (((intptr_t)(input) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
+                    input_needs_realloc = true;
+                }
+
+                if (((intptr_t)(output) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
+                    output_needs_realloc = true;
+                }
+            }
+        }
+#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
+
         if (esp_ptr_external_ram(input)) {
             if (esp_cache_msync((void *)input, len, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED) != ESP_OK) {
                 mbedtls_platform_zeroize(output, len);
@@ -1049,12 +1063,18 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
         block_in_desc = block_desc;
         block_out_desc = block_desc + crypto_dma_desc_num;
 
+#if SOC_AHB_GDMA_VERSION == 2
+        // Limit max inlink descriptor length to be 16 byte aligned, as buffer sizes need to be 16 byte aligned
+        // when Flash Encryption is enabled.
+        dma_desc_setup_link(block_in_desc, input, block_bytes, DMA_DESCRIPTOR_BUFFER_MAX_SIZE_16B_ALIGNED, 0);
+#else
         // the size field has 12 bits, but 0 not for 4096.
         // to avoid possible problem when the size is not word-aligned, we only use 4096-4 per desc.
         // Maximum size of data in the buffer that a DMA descriptor can hold.
         dma_desc_setup_link(block_in_desc, input, block_bytes, DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED, 0);
+#endif
 
-        //Limit max inlink descriptor length to be 16 byte aligned, require for EDMA
+        //Limit max outlink descriptor length to be 16 byte aligned, require for EDMA
         dma_desc_setup_link(block_out_desc, output, block_bytes, DMA_DESCRIPTOR_BUFFER_MAX_SIZE_16B_ALIGNED, 0);
 
         /* Setup in/out start descriptors */
diff --git a/components/mbedtls/port/crypto_shared_gdma/esp_crypto_shared_gdma.c b/components/mbedtls/port/crypto_shared_gdma/esp_crypto_shared_gdma.c
index 5abadc596532..394376070ef4 100644
--- a/components/mbedtls/port/crypto_shared_gdma/esp_crypto_shared_gdma.c
+++ b/components/mbedtls/port/crypto_shared_gdma/esp_crypto_shared_gdma.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,14 +17,16 @@
 #include "soc/soc_caps.h"
 #include "sdkconfig.h"
 
-#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
-#include "esp_flash_encrypt.h"
-#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
+#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
+#include "hal/efuse_hal.h"
+#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
 
-#if SOC_AHB_GDMA_VERSION == 1
-#include "hal/gdma_ll.h"
-#elif SOC_AXI_GDMA_SUPPORTED
+#if SOC_AXI_GDMA_SUPPORTED
 #include "hal/axi_dma_ll.h"
+#elif SOC_AHB_GDMA_VERSION == 1
+#include "hal/gdma_ll.h"
+#elif SOC_AHB_GDMA_VERSION == 2
+#include "hal/ahb_dma_ll.h"
 #endif /* SOC_AHB_GDMA_VERSION */
 
 #define NEW_CHANNEL_TIMEOUT_MS  1000
@@ -89,7 +91,16 @@ static esp_err_t crypto_shared_gdma_init(void)
         .access_ext_mem = true, // crypto peripheral may want to access PSRAM
     };
     gdma_config_transfer(tx_channel, &transfer_cfg);
+
+    /* When using AHB-GDMA version 1, the max data burst size must be 0, otherwise buffers need to be aligned as well.
+     * Whereas, in case of the other GDMA versions, the RX max burst size is default enabled, but with default burst size of 4,
+     * but it case of Flash Encryption, the buffers can be allocated from the external memory, which requires 16 byte alignment.
+     * Thus, we set the max data burst size to 16, similar to the TX channel.
+     */
+#if SOC_AHB_GDMA_VERSION == 1 || SOC_AXI_GDMA_SUPPORTED // IDF-14335: SOC_AXI_GDMA_SUPPORTED might not be needed here
     transfer_cfg.max_data_burst_size = 0;
+#endif
+
     gdma_config_transfer(rx_channel, &transfer_cfg);
 
 #ifdef SOC_AES_SUPPORTED
@@ -156,7 +167,7 @@ esp_err_t esp_crypto_shared_gdma_start(const lldesc_t *input, const lldesc_t *ou
 
 /* The external memory ecc-aes access must be enabled when there exists
    at least one buffer in the DMA descriptors that resides in external memory. */
-#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
+#if (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT && SOC_AXI_GDMA_SUPPORTED)
 static bool check_dma_descs_need_ext_mem_ecc_aes_access(const crypto_dma_desc_t *dmadesc)
 {
     crypto_dma_desc_t* desc = (crypto_dma_desc_t*) dmadesc;
@@ -168,7 +179,7 @@ static bool check_dma_descs_need_ext_mem_ecc_aes_access(const crypto_dma_desc_t
     }
     return false;
 }
-#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
+#endif /* (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT && SOC_AXI_GDMA_SUPPORTED) */
 
 esp_err_t esp_crypto_shared_gdma_start_axi_ahb(const crypto_dma_desc_t *input, const crypto_dma_desc_t *output, gdma_trigger_peripheral_t peripheral)
 {
@@ -203,16 +214,19 @@ esp_err_t esp_crypto_shared_gdma_start_axi_ahb(const crypto_dma_desc_t *input, c
     /* tx channel is reset by gdma_connect(), also reset rx to ensure a known state */
     gdma_get_channel_id(rx_channel, &rx_ch_id);
 
-#if SOC_AHB_GDMA_VERSION == 1
-    gdma_ll_rx_reset_channel(&GDMA, rx_ch_id);
-#elif SOC_AXI_GDMA_SUPPORTED
+    // IDF-14335: Use gdma_reset() instead
+#if SOC_AXI_GDMA_SUPPORTED
     axi_dma_ll_rx_reset_channel(&AXI_DMA, rx_ch_id);
-#endif /* SOC_AHB_GDMA_VERSION */
+#elif SOC_AHB_GDMA_VERSION == 1
+    gdma_ll_rx_reset_channel(&GDMA, rx_ch_id);
+#elif SOC_AHB_GDMA_VERSION == 2
+    ahb_dma_ll_rx_reset_channel(&AHB_DMA, rx_ch_id);
+#endif /* SOC_AXI_GDMA_SUPPORTED */
 
 /* When GDMA operations are carried out using external memory with external memory encryption enabled,
    we need to enable AXI-DMA's AES-ECC mean access bit. */
-#if (SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT)
-    if (esp_flash_encryption_enabled()) {
+#if (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT && SOC_AXI_GDMA_SUPPORTED)
+    if (efuse_hal_flash_encryption_enabled()) {
         int tx_ch_id = 0;
         gdma_get_channel_id(tx_channel, &tx_ch_id);
 
@@ -224,7 +238,7 @@ esp_err_t esp_crypto_shared_gdma_start_axi_ahb(const crypto_dma_desc_t *input, c
             axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(&AXI_DMA, tx_ch_id, false);
         }
     }
-#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
+#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
 
     gdma_start(tx_channel, (intptr_t)input);
     gdma_start(rx_channel, (intptr_t)output);
diff --git a/components/mbedtls/port/sha/core/sha.c b/components/mbedtls/port/sha/core/sha.c
index 8aa2f1e0e110..eb905d4bb50c 100644
--- a/components/mbedtls/port/sha/core/sha.c
+++ b/components/mbedtls/port/sha/core/sha.c
@@ -43,9 +43,9 @@
 #include "esp_sha_dma_priv.h"
 #include "sdkconfig.h"
 
-#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
-#include "esp_flash_encrypt.h"
-#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
+#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
+#include "hal/efuse_hal.h"
+#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
 
 #if SOC_SHA_CRYPTO_DMA
 #include "hal/crypto_dma_ll.h"
@@ -154,7 +154,7 @@ static DRAM_ATTR crypto_dma_desc_t s_dma_descr_buf;
 static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen,
                                      const void *buf, uint32_t buf_len, bool is_first_block);
 
-#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
+#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
 static esp_err_t esp_sha_dma_process_ext(esp_sha_type sha_type, const void *input, uint32_t ilen,
                                         const void *buf, uint32_t buf_len, bool is_first_block,
                                         bool realloc_input, bool realloc_buf)
@@ -170,7 +170,7 @@ static esp_err_t esp_sha_dma_process_ext(esp_sha_type sha_type, const void *inpu
 
     if (realloc_input) {
         heap_caps = MALLOC_CAP_8BIT | (esp_ptr_external_ram(input) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
-        input_copy = heap_caps_aligned_alloc(SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT, ilen, heap_caps);
+        input_copy = heap_caps_aligned_alloc(SOC_GDMA_EXT_MEM_ENC_ALIGNMENT, ilen, heap_caps);
         if (input_copy == NULL) {
             ESP_LOGE(TAG, "Failed to allocate aligned SPIRAM memory");
             return ret;
@@ -183,7 +183,7 @@ static esp_err_t esp_sha_dma_process_ext(esp_sha_type sha_type, const void *inpu
 
     if (realloc_buf) {
         heap_caps = MALLOC_CAP_8BIT | (esp_ptr_external_ram(buf) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
-        buf_copy = heap_caps_aligned_alloc(SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT, buf_len, heap_caps);
+        buf_copy = heap_caps_aligned_alloc(SOC_GDMA_EXT_MEM_ENC_ALIGNMENT, buf_len, heap_caps);
         if (buf_copy == NULL) {
             ESP_LOGE(TAG, "Failed to allocate aligned internal memory");
             return ret;
@@ -206,7 +206,7 @@ static esp_err_t esp_sha_dma_process_ext(esp_sha_type sha_type, const void *inpu
 
     return ret;
 }
-#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
+#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
 
 /* Performs SHA on multiple blocks at a time */
 static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen,
@@ -227,17 +227,17 @@ static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, u
 
 /* When SHA-DMA operations are carried out using external memory with external memory encryption enabled,
    we need to make sure that the addresses and the sizes of the buffers on which the DMA operates are 16 byte-aligned. */
-#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
-    if (esp_flash_encryption_enabled()) {
+#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
+    if (efuse_hal_flash_encryption_enabled()) {
         if (esp_ptr_external_ram(input) || esp_ptr_external_ram(buf) || esp_ptr_in_drom(input) || esp_ptr_in_drom(buf)) {
             bool input_needs_realloc = false;
             bool buf_needs_realloc = false;
 
-            if (ilen && ((intptr_t)(input) & (SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
+            if (ilen && ((intptr_t)(input) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
                 input_needs_realloc = true;
             }
 
-            if (buf_len && ((intptr_t)(buf) & (SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
+            if (buf_len && ((intptr_t)(buf) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
                 buf_needs_realloc = true;
             }
 
@@ -246,7 +246,7 @@ static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, u
             }
         }
     }
-#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
+#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
 
     /* DMA descriptor for Memory to DMA-SHA transfer */
     if (ilen) {
@@ -273,6 +273,19 @@ static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, u
         s_dma_descr_buf.next = (&s_dma_descr_input);
     }
 
+    /* Write back buffers to memory if they are in external RAM
+     * The writeback needs to be performed in esp_sha_dma_process() instead of esp_sha_dma() to make
+     * sure that if the buffers are reallocated, then the writeback is performed on the new buffers.
+     */
+#if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE)
+    if (esp_ptr_external_ram(input)) {
+        esp_cache_msync((void *)input, ilen, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED);
+    }
+    if (esp_ptr_external_ram(buf)) {
+        esp_cache_msync((void *)buf, buf_len, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED);
+    }
+#endif
+
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
     if (ilen) {
         ESP_ERROR_CHECK(esp_cache_msync(&s_dma_descr_input, sizeof(crypto_dma_desc_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED));
@@ -317,15 +330,6 @@ int esp_sha_dma(esp_sha_type sha_type, const void *input, uint32_t ilen,
         return 0;
     }
 
-#if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE)
-    if (esp_ptr_external_ram(input)) {
-        esp_cache_msync((void *)input, ilen, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED);
-    }
-    if (esp_ptr_external_ram(buf)) {
-        esp_cache_msync((void *)buf, buf_len, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED);
-    }
-#endif
-
     /* Copy to internal buf if buf is in non DMA capable memory */
     if (!s_check_dma_capable(buf) && (buf_len != 0)) {
         dma_cap_buf = heap_caps_malloc(sizeof(unsigned char) * buf_len, MALLOC_CAP_8BIT|MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
index b9ae7380b135..da6a3343d514 100644
--- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@@ -519,6 +519,10 @@ config SOC_AHB_GDMA_SUPPORT_PSRAM
     bool
     default y
 
+config SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
+    int
+    default 16
+
 config SOC_ETM_GROUPS
     int
     default 1
diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h
index 7ad40df50ee7..7fd8e84ffd05 100644
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@@ -196,6 +196,7 @@
 #define SOC_GDMA_SUPPORT_ETM            1
 #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1
 #define SOC_AHB_GDMA_SUPPORT_PSRAM 1
+#define SOC_GDMA_EXT_MEM_ENC_ALIGNMENT  (16)
 
 /*-------------------------- ETM CAPS --------------------------------------*/
 #define SOC_ETM_GROUPS                  1U  // Number of ETM groups
diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
index d6a869e95faa..e5aac8a1e09e 100644
--- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
@@ -399,6 +399,10 @@ config SOC_AHB_GDMA_SUPPORT_PSRAM
     bool
     default y
 
+config SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
+    int
+    default 16
+
 config SOC_ETM_GROUPS
     int
     default 1
diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h
index 2e99063f5e5c..c3648dcc6797 100644
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@@ -153,6 +153,7 @@
 #define SOC_GDMA_SUPPORT_ETM            1  // Support ETM submodule
 #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1
 #define SOC_AHB_GDMA_SUPPORT_PSRAM 1
+#define SOC_GDMA_EXT_MEM_ENC_ALIGNMENT  (16)
 
 /*-------------------------- ETM CAPS --------------------------------------*/
 #define SOC_ETM_GROUPS                  1U  // Number of ETM groups
diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
index cef08f1902fc..baf2ba116123 100644
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -623,7 +623,7 @@ config SOC_GDMA_SUPPORT_SLEEP_RETENTION
     bool
     default y
 
-config SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
+config SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
     int
     default 16
 
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
index b36e030dbf32..b33af78bdbd8 100644
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -222,7 +222,7 @@
 #define SOC_AXI_GDMA_SUPPORT_PSRAM          1
 #define SOC_GDMA_SUPPORT_ETM                1
 #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1
-#define SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT   (16)
+#define SOC_GDMA_EXT_MEM_ENC_ALIGNMENT   (16)
 
 /*-------------------------- 2D-DMA CAPS -------------------------------------*/
 #define SOC_DMA2D_GROUPS                            (1U) // Number of 2D-DMA groups
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/efuse_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/efuse_eco5_struct.h
deleted file mode 100644
index e24109ae081a..000000000000
--- a/components/soc/esp32p4/register/hw_ver3/soc/efuse_eco5_struct.h
+++ /dev/null
@@ -1,3689 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: program_data registers */
-/** Type of pgm_datan register
- *  Represents pgm_datan
- */
-typedef union {
-    struct {
-        /** pgm_data_n : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the nth 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_n:32;
-    };
-    uint32_t val;
-} efuse_pgm_datan_reg_t;
-
-/** Type of pgm_check_valuen register
- *  Represents pgm_check_valuen
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the nth RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_n:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_valuen_reg_t;
-
-
-/** Group: block0 registers */
-/** Type of rd_wr_dis register
- *  Represents rd_wr_dis
- */
-typedef union {
-    struct {
-        /** wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Represents whether programming of individual eFuse memory bit is disabled.  For
-         *  mapping between the bits of this field and the eFuse memory bits, please refer to
-         *  Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}.
-         *  1: Disabled
-         *  0: Enabled
-         */
-        uint32_t wr_dis:32;
-    };
-    uint32_t val;
-} efuse_rd_wr_dis_reg_t;
-
-/** Type of rd_repeat_data0 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** rd_dis : RO; bitpos: [6:0]; default: 0;
-         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
-         *  enabled.
-         *  1: disabled
-         *  0: enabled
-         */
-        uint32_t rd_dis:7;
-        /** recovery_bootloader_flash_sector_0_1 : RO; bitpos: [8:7]; default: 0;
-         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
-         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
-         *  - this feature is disabled.
-         */
-        uint32_t recovery_bootloader_flash_sector_0_1:2;
-        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
-         *  Set this bit to disable function of usb switch to jtag in module of usb device.
-         */
-        uint32_t dis_usb_jtag:1;
-        /** recovery_bootloader_flash_sector_2_2 : RO; bitpos: [10]; default: 0;
-         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
-         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
-         *  - this feature is disabled.
-         */
-        uint32_t recovery_bootloader_flash_sector_2_2:1;
-        uint32_t reserved_11:1;
-        /** dis_force_download : RO; bitpos: [12]; default: 0;
-         *  Set this bit to disable the function that forces chip into download mode.
-         */
-        uint32_t dis_force_download:1;
-        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
-         *  Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during
-         *  boot_mode_download.
-         */
-        uint32_t spi_download_mspi_dis:1;
-        /** dis_twai : RO; bitpos: [14]; default: 0;
-         *  Set this bit to disable TWAI function.
-         */
-        uint32_t dis_twai:1;
-        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
-         *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
-         *  strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0.
-         */
-        uint32_t jtag_sel_enable:1;
-        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
-         *  Set odd bits to disable JTAG in the soft way. JTAG can be enabled in HMAC module.
-         */
-        uint32_t soft_dis_jtag:3;
-        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
-         *  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
-         */
-        uint32_t dis_pad_jtag:1;
-        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
-         *  Set this bit to disable flash manual encrypt function (except in SPI boot mode).
-         */
-        uint32_t dis_download_manual_encrypt:1;
-        /** recovery_bootloader_flash_sector_3_6 : RO; bitpos: [24:21]; default: 0;
-         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
-         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
-         *  - this feature is disabled.
-         */
-        uint32_t recovery_bootloader_flash_sector_3_6:4;
-        /** usb_phy_sel : RO; bitpos: [25]; default: 0;
-         *  0: intphy(gpio24/25) <---> usb_device
-         *  1: intphy(26/27) <---> usb_otg11.1: intphy(gpio26/27) <---> usb_device
-         *  1: intphy(24/25) <---> usb_otg11.
-         */
-        uint32_t usb_phy_sel:1;
-        /** huk_gen_state : RO; bitpos: [30:26]; default: 0;
-         *  Set the bits to control validation of HUK generate mode. Odd of 1 is invalid, even
-         *  of 1 is valid.
-         */
-        uint32_t huk_gen_state:5;
-        /** recovery_bootloader_flash_sector_7_7 : RO; bitpos: [31]; default: 0;
-         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
-         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
-         *  - this feature is disabled.
-         */
-        uint32_t recovery_bootloader_flash_sector_7_7:1;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data0_reg_t;
-
-/** Type of rd_repeat_data1 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** recovery_bootloader_flash_sector_8_10 : RO; bitpos: [2:0]; default: 0;
-         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
-         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
-         *  - this feature is disabled.
-         */
-        uint32_t recovery_bootloader_flash_sector_8_10:3;
-        /** recovery_bootloader_flash_sector_11_11 : RO; bitpos: [3]; default: 0;
-         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
-         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
-         *  - this feature is disabled.
-         */
-        uint32_t recovery_bootloader_flash_sector_11_11:1;
-        /** km_rnd_switch_cycle : RO; bitpos: [4]; default: 0;
-         *  Set the bits to control key manager random number switch cycle. 0: control by
-         *  register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
-         */
-        uint32_t km_rnd_switch_cycle:1;
-        /** km_deploy_only_once : RO; bitpos: [8:5]; default: 0;
-         *  EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field:
-         *  {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to
-         *  control whether corresponding key can only be deployed once. 1 is true, 0 is false.
-         *  bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
-         */
-        uint32_t km_deploy_only_once:4;
-        /** force_use_key_manager_key : RO; bitpos: [12:9]; default: 0;
-         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form
-         *  one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H,
-         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether
-         *  corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda,
-         *  bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
-         */
-        uint32_t force_use_key_manager_key:4;
-        /** force_disable_sw_init_key : RO; bitpos: [13]; default: 0;
-         *  Set this bit to disable software written init key, and force use efuse_init_key.
-         */
-        uint32_t force_disable_sw_init_key:1;
-        /** km_xts_key_length_256 : RO; bitpos: [14]; default: 0;
-         *  Set this bit to config flash encryption xts-512 key, else use xts-256 key when
-         *  using the key manager
-         */
-        uint32_t km_xts_key_length_256:1;
-        /** ecc_force_const_time : RO; bitpos: [15]; default: 0;
-         *  Set this bit to permanently turn on ECC const-time mode.
-         */
-        uint32_t ecc_force_const_time:1;
-        uint32_t reserved_16:1;
-        /** wdt_delay_sel : RO; bitpos: [17]; default: 0;
-         *  Select lp wdt timeout threshold at startup = initial timeout value * (2 ^
-         *  (EFUSE_WDT_DELAY_SEL + 1))
-         */
-        uint32_t wdt_delay_sel:1;
-        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
-         *  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
-         *  number of 1: disable.
-         */
-        uint32_t spi_boot_crypt_cnt:3;
-        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
-         *  Set this bit to enable revoking first secure boot key.
-         */
-        uint32_t secure_boot_key_revoke0:1;
-        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
-         *  Set this bit to enable revoking second secure boot key.
-         */
-        uint32_t secure_boot_key_revoke1:1;
-        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
-         *  Set this bit to enable revoking third secure boot key.
-         */
-        uint32_t secure_boot_key_revoke2:1;
-        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
-         *  Purpose of Key0.
-         */
-        uint32_t key_purpose_0:4;
-        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
-         *  Purpose of Key1.
-         */
-        uint32_t key_purpose_1:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data1_reg_t;
-
-/** Type of rd_repeat_data2 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
-         *  Purpose of Key2.
-         */
-        uint32_t key_purpose_2:4;
-        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
-         *  Purpose of Key3.
-         */
-        uint32_t key_purpose_3:4;
-        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
-         *  Purpose of Key4.
-         */
-        uint32_t key_purpose_4:4;
-        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
-         *  Purpose of Key5.
-         */
-        uint32_t key_purpose_5:4;
-        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
-         *  Configures the clock random divide mode to determine the dpa secure level
-         */
-        uint32_t sec_dpa_level:2;
-        uint32_t reserved_18:1;
-        /** xts_dpa_clk_enable : RO; bitpos: [19]; default: 0;
-         *  Sets this bit to enable xts clock anti-dpa attack function.
-         */
-        uint32_t xts_dpa_clk_enable:1;
-        /** secure_boot_en : RO; bitpos: [20]; default: 0;
-         *  Set this bit to enable secure boot.
-         */
-        uint32_t secure_boot_en:1;
-        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
-         *  Set this bit to enable revoking aggressive secure boot.
-         */
-        uint32_t secure_boot_aggressive_revoke:1;
-        /** km_deploy_only_once_h : RO; bitpos: [22]; default: 0;
-         *  EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field:
-         *  {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to
-         *  control whether corresponding key can only be deployed once. 1 is true, 0 is false.
-         *  bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
-         */
-        uint32_t km_deploy_only_once_h:1;
-        /** force_use_key_manager_key_h : RO; bitpos: [23]; default: 0;
-         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form
-         *  one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H,
-         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether
-         *  corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda,
-         *  bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
-         */
-        uint32_t force_use_key_manager_key_h:1;
-        uint32_t reserved_24:2;
-        /** flash_ecc_en : RO; bitpos: [26]; default: 0;
-         *  Set this bit to enable ECC for flash boot.
-         */
-        uint32_t flash_ecc_en:1;
-        /** dis_usb_otg_download_mode : RO; bitpos: [27]; default: 0;
-         *  Set this bit to disable download via USB-OTG.
-         */
-        uint32_t dis_usb_otg_download_mode:1;
-        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
-         *  Configures flash waiting time after power-up, in unit of ms. When the value less
-         *  than 15, the waiting time is the configurable value. Otherwise, the waiting time is
-         *  30.
-         */
-        uint32_t flash_tpuw:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data2_reg_t;
-
-/** Type of rd_repeat_data3 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** dis_download_mode : RO; bitpos: [0]; default: 0;
-         *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7).
-         */
-        uint32_t dis_download_mode:1;
-        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
-         *  Set this bit to disable direct boot mode
-         */
-        uint32_t dis_direct_boot:1;
-        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
-         *  Set this bit to disable USB-Serial-JTAG print during rom boot.
-         */
-        uint32_t dis_usb_serial_jtag_rom_print:1;
-        /** lock_km_key : RO; bitpos: [3]; default: 0;
-         *  set this bit to lock the key manager key after deploy
-         */
-        uint32_t lock_km_key:1;
-        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
-         *  Set this bit to disable the USB-Serial-JTAG download function.
-         */
-        uint32_t dis_usb_serial_jtag_download_mode:1;
-        /** enable_security_download : RO; bitpos: [5]; default: 0;
-         *  Set this bit to enable security download mode.
-         */
-        uint32_t enable_security_download:1;
-        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
-         *  Set the type of UART printing, 00: force enable printing, 01: enable printing when
-         *  GPIO8 is reset at low level, 10: enable printing when GPIO8 is reset at high level,
-         *  11: force disable printing
-         */
-        uint32_t uart_print_control:2;
-        /** force_send_resume : RO; bitpos: [8]; default: 0;
-         *  Set this bit to force ROM code to send a resume command during SPI boot.
-         */
-        uint32_t force_send_resume:1;
-        /** secure_version : RO; bitpos: [24:9]; default: 0;
-         *  Secure version used by ESP-IDF anti-rollback feature.
-         */
-        uint32_t secure_version:16;
-        /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
-         *  Represents whether secure boot do fast verification on wake is disabled. 0: enabled
-         *  1: disabled
-         */
-        uint32_t secure_boot_disable_fast_wake:1;
-        /** hys_en_pad : RO; bitpos: [26]; default: 0;
-         *  Set bits to enable hysteresis function of PAD0~27
-         */
-        uint32_t hys_en_pad:1;
-        /** key_purpose_0_h : RO; bitpos: [27]; default: 0;
-         *  Purpose of Key0. The 5-th bit.
-         */
-        uint32_t key_purpose_0_h:1;
-        /** key_purpose_1_h : RO; bitpos: [28]; default: 0;
-         *  Purpose of Key1. The 5-th bit.
-         */
-        uint32_t key_purpose_1_h:1;
-        /** key_purpose_2_h : RO; bitpos: [29]; default: 0;
-         *  Purpose of Key2. The 5-th bit.
-         */
-        uint32_t key_purpose_2_h:1;
-        /** key_purpose_3_h : RO; bitpos: [30]; default: 0;
-         *  Purpose of Key3. The 5-th bit.
-         */
-        uint32_t key_purpose_3_h:1;
-        /** key_purpose_4_h : RO; bitpos: [31]; default: 0;
-         *  Purpose of Key4. The 5-th bit.
-         */
-        uint32_t key_purpose_4_h:1;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data3_reg_t;
-
-/** Type of rd_repeat_data4 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** pxa0_tieh_sel_0 : RO; bitpos: [1:0]; default: 0;
-         *  Output LDO VO0 tieh source select. 0: 1'b1 1: sdmmc1 2: reg 3:sdmmc0
-         */
-        uint32_t pxa0_tieh_sel_0:2;
-        /** pvt_glitch_en : RO; bitpos: [2]; default: 0;
-         *  Represents whether to enable PVT power glitch monitor function.
-         *  1:Enable.
-         *  0:Disable
-         */
-        uint32_t pvt_glitch_en:1;
-        uint32_t reserved_3:1;
-        /** key_purpose_5_h : RO; bitpos: [4]; default: 0;
-         *  Purpose of Key5. The 5-th bit.
-         */
-        uint32_t key_purpose_5_h:1;
-        uint32_t reserved_5:2;
-        /** km_disable_deploy_mode_h : RO; bitpos: [7]; default: 0;
-         *  EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one
-         *  field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set
-         *  each bit to control whether corresponding key's deploy mode of new value deployment
-         *  is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds,
-         *  bit4:psram
-         */
-        uint32_t km_disable_deploy_mode_h:1;
-        /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0;
-         *  EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one
-         *  field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set
-         *  each bit to control whether corresponding key's deploy mode of new value deployment
-         *  is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds,
-         *  bit4:psram
-         */
-        uint32_t km_disable_deploy_mode:4;
-        uint32_t reserved_12:4;
-        /** xts_dpa_pseudo_level : RO; bitpos: [17:16]; default: 0;
-         *  Sets this bit to control the xts pseudo-round anti-dpa attack function. 0:
-         *  controlled by register. 1-3: the higher the value is, the more pseudo-rounds are
-         *  inserted to the xts-aes calculation
-         */
-        uint32_t xts_dpa_pseudo_level:2;
-        /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0;
-         *  HP system power source select. 0:LDO  1: DCDC
-         */
-        uint32_t hp_pwr_src_sel:1;
-        /** secure_boot_sha384_en : RO; bitpos: [19]; default: 0;
-         *  Represents whether secure boot using SHA-384 is enabled. 0: disable 1: enable
-         */
-        uint32_t secure_boot_sha384_en:1;
-        /** dis_wdt : RO; bitpos: [20]; default: 0;
-         *  Set this bit to disable watch dog.
-         */
-        uint32_t dis_wdt:1;
-        /** dis_swd : RO; bitpos: [21]; default: 0;
-         *  Set bit to disable super-watchdog
-         */
-        uint32_t dis_swd:1;
-        /** pvt_glitch_mode : RO; bitpos: [23:22]; default: 0;
-         *  Use to configure glitch mode
-         */
-        uint32_t pvt_glitch_mode:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data4_reg_t;
-
-
-/** Group: block1 registers */
-/** Type of rd_mac_sys0 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** mac_0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents MAC address. Low 32-bit.
-         */
-        uint32_t mac_0:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys0_reg_t;
-
-/** Type of rd_mac_sys1 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** mac_1 : RO; bitpos: [15:0]; default: 0;
-         *  Represents MAC address. High 16-bit.
-         */
-        uint32_t mac_1:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys1_reg_t;
-
-/** Type of rd_mac_sys3 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:18;
-        /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
-         *  Represents the first 14-bit of zeroth part of system data.
-         */
-        uint32_t sys_data_part0_0:14;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys3_reg_t;
-
-/** Type of rd_mac_sys4 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the second 32-bit of zeroth part of system data.
-         */
-        uint32_t sys_data_part0_1:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys4_reg_t;
-
-/** Type of rd_mac_sys5 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the third 32-bit of zeroth part of system data.
-         */
-        uint32_t sys_data_part0_2:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys5_reg_t;
-
-
-/** Group: block2 registers */
-/** Type of rd_sys_part1_datan register
- *  Represents rd_sys_part1_datan
- */
-typedef union {
-    struct {
-        /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_n:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_datan_reg_t;
-
-
-/** Group: block3 registers */
-/** Type of rd_usr_datan register
- *  Represents rd_usr_datan
- */
-typedef union {
-    struct {
-        /** usr_datan : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_datan:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_datan_reg_t;
-
-
-/** Group: block4 registers */
-/** Type of rd_key0_datan register
- *  Represents rd_key0_datan
- */
-typedef union {
-    struct {
-        /** key0_datan : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_datan:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_datan_reg_t;
-
-
-/** Group: block5 registers */
-/** Type of rd_key1_datan register
- *  Represents rd_key1_datan
- */
-typedef union {
-    struct {
-        /** key1_datan : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_datan:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_datan_reg_t;
-
-
-/** Group: block6 registers */
-/** Type of rd_key2_datan register
- *  Represents rd_key2_datan
- */
-typedef union {
-    struct {
-        /** key2_datan : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_datan:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_datan_reg_t;
-
-
-/** Group: block7 registers */
-/** Type of rd_key3_datan register
- *  Represents rd_key3_datan
- */
-typedef union {
-    struct {
-        /** key3_datan : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_datan:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_datan_reg_t;
-
-
-/** Group: block8 registers */
-/** Type of rd_key4_datan register
- *  Represents rd_key4_datan
- */
-typedef union {
-    struct {
-        /** key4_datan : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_datan:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_datan_reg_t;
-
-
-/** Group: block9 registers */
-/** Type of rd_key5_datan register
- *  Represents rd_key5_datan
- */
-typedef union {
-    struct {
-        /** key5_datan : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_datan:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_datan_reg_t;
-
-
-/** Group: block10 registers */
-/** Type of rd_sys_part2_data0 register
- *  Represents rd_sys_part2_data
- */
-typedef union {
-    struct {
-        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the first 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_0:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data0_reg_t;
-
-/** Type of rd_sys_part2_data1 register
- *  Represents rd_sys_part2_data
- */
-typedef union {
-    struct {
-        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the first 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data1_reg_t;
-
-/** Type of rd_sys_part2_data2 register
- *  Represents rd_sys_part2_data
- */
-typedef union {
-    struct {
-        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the second 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data2_reg_t;
-
-/** Type of rd_sys_part2_data3 register
- *  Represents rd_sys_part2_data
- */
-typedef union {
-    struct {
-        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the third 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data3_reg_t;
-
-/** Type of rd_sys_part2_data4 register
- *  Represents rd_sys_part2_data
- */
-typedef union {
-    struct {
-        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the fourth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_4:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data4_reg_t;
-
-/** Type of rd_sys_part2_data5 register
- *  Represents rd_sys_part2_data
- */
-typedef union {
-    struct {
-        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the fifth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_5:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data5_reg_t;
-
-/** Type of rd_sys_part2_data7 register
- *  Represents rd_sys_part2_data
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** usb_device_exchg_pins : RO; bitpos: [4]; default: 0;
-         *  Enable usb device exchange pins of D+ and D-.
-         */
-        uint32_t usb_device_exchg_pins:1;
-        /** usb_otg11_exchg_pins : RO; bitpos: [5]; default: 0;
-         *  Enable usb otg11 exchange pins of D+ and D-.
-         */
-        uint32_t usb_otg11_exchg_pins:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data7_reg_t;
-
-
-/** Group: block0 error report registers */
-/** Type of rd_repeat_data_err0 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
-         *  Represents the programming error of EFUSE_RD_DIS
-         */
-        uint32_t rd_dis_err:7;
-        /** recovery_bootloader_flash_sector_0_1_err : RO; bitpos: [8:7]; default: 0;
-         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1
-         */
-        uint32_t recovery_bootloader_flash_sector_0_1_err:2;
-        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_JTAG
-         */
-        uint32_t dis_usb_jtag_err:1;
-        /** recovery_bootloader_flash_sector_2_2_err : RO; bitpos: [10]; default: 0;
-         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2
-         */
-        uint32_t recovery_bootloader_flash_sector_2_2_err:1;
-        uint32_t reserved_11:1;
-        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
-         */
-        uint32_t dis_force_download_err:1;
-        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
-         *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
-         */
-        uint32_t spi_download_mspi_dis_err:1;
-        /** dis_twai_err : RO; bitpos: [14]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_TWAI
-         */
-        uint32_t dis_twai_err:1;
-        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
-         *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
-         */
-        uint32_t jtag_sel_enable_err:1;
-        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
-         *  Represents the programming error of EFUSE_SOFT_DIS_JTAG
-         */
-        uint32_t soft_dis_jtag_err:3;
-        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_PAD_JTAG
-         */
-        uint32_t dis_pad_jtag_err:1;
-        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
-         */
-        uint32_t dis_download_manual_encrypt_err:1;
-        /** recovery_bootloader_flash_sector_3_6_err : RO; bitpos: [24:21]; default: 0;
-         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6
-         */
-        uint32_t recovery_bootloader_flash_sector_3_6_err:4;
-        /** usb_phy_sel_err : RO; bitpos: [25]; default: 0;
-         *  Represents the programming error of EFUSE_USB_PHY_SEL
-         */
-        uint32_t usb_phy_sel_err:1;
-        /** huk_gen_state_err : RO; bitpos: [30:26]; default: 0;
-         *  Represents the programming error of EFUSE_HUK_GEN_STATE
-         */
-        uint32_t huk_gen_state_err:5;
-        /** recovery_bootloader_flash_sector_7_7_err : RO; bitpos: [31]; default: 0;
-         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7
-         */
-        uint32_t recovery_bootloader_flash_sector_7_7_err:1;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err0_reg_t;
-
-/** Type of rd_repeat_data_err1 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** recovery_bootloader_flash_sector_8_10_err : RO; bitpos: [2:0]; default: 0;
-         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10
-         */
-        uint32_t recovery_bootloader_flash_sector_8_10_err:3;
-        /** recovery_bootloader_flash_sector_11_11_err : RO; bitpos: [3]; default: 0;
-         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11
-         */
-        uint32_t recovery_bootloader_flash_sector_11_11_err:1;
-        /** km_rnd_switch_cycle_err : RO; bitpos: [4]; default: 0;
-         *  Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE
-         */
-        uint32_t km_rnd_switch_cycle_err:1;
-        /** km_deploy_only_once_err : RO; bitpos: [8:5]; default: 0;
-         *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE
-         */
-        uint32_t km_deploy_only_once_err:4;
-        /** force_use_key_manager_key_err : RO; bitpos: [12:9]; default: 0;
-         *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY
-         */
-        uint32_t force_use_key_manager_key_err:4;
-        /** force_disable_sw_init_key_err : RO; bitpos: [13]; default: 0;
-         *  Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY
-         */
-        uint32_t force_disable_sw_init_key_err:1;
-        /** km_xts_key_length_256_err : RO; bitpos: [14]; default: 0;
-         *  Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256
-         */
-        uint32_t km_xts_key_length_256_err:1;
-        /** ecc_force_const_time_err : RO; bitpos: [15]; default: 0;
-         *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
-         */
-        uint32_t ecc_force_const_time_err:1;
-        uint32_t reserved_16:1;
-        /** wdt_delay_sel_err : RO; bitpos: [17]; default: 0;
-         *  Represents the programming error of EFUSE_WDT_DELAY_SEL
-         */
-        uint32_t wdt_delay_sel_err:1;
-        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
-         *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
-         */
-        uint32_t spi_boot_crypt_cnt_err:3;
-        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0
-         */
-        uint32_t secure_boot_key_revoke0_err:1;
-        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1
-         */
-        uint32_t secure_boot_key_revoke1_err:1;
-        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2
-         */
-        uint32_t secure_boot_key_revoke2_err:1;
-        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_0
-         */
-        uint32_t key_purpose_0_err:4;
-        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_1
-         */
-        uint32_t key_purpose_1_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err1_reg_t;
-
-/** Type of rd_repeat_data_err2 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_2
-         */
-        uint32_t key_purpose_2_err:4;
-        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_3
-         */
-        uint32_t key_purpose_3_err:4;
-        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_4
-         */
-        uint32_t key_purpose_4_err:4;
-        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_5
-         */
-        uint32_t key_purpose_5_err:4;
-        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
-         *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
-         */
-        uint32_t sec_dpa_level_err:2;
-        uint32_t reserved_18:1;
-        /** xts_dpa_clk_enable_err : RO; bitpos: [19]; default: 0;
-         *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
-         */
-        uint32_t xts_dpa_clk_enable_err:1;
-        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_EN
-         */
-        uint32_t secure_boot_en_err:1;
-        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
-         */
-        uint32_t secure_boot_aggressive_revoke_err:1;
-        /** km_deploy_only_once_h_err : RO; bitpos: [22]; default: 0;
-         *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE_H
-         */
-        uint32_t km_deploy_only_once_h_err:1;
-        /** force_use_key_manager_key_h_err : RO; bitpos: [23]; default: 0;
-         *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY_H
-         */
-        uint32_t force_use_key_manager_key_h_err:1;
-        uint32_t reserved_24:2;
-        /** flash_ecc_en_err : RO; bitpos: [26]; default: 0;
-         *  Represents the programming error of EFUSE_FLASH_ECC_EN
-         */
-        uint32_t flash_ecc_en_err:1;
-        /** dis_usb_otg_download_mode_err : RO; bitpos: [27]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_OTG_DOWNLOAD_MODE
-         */
-        uint32_t dis_usb_otg_download_mode_err:1;
-        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
-         *  Represents the programming error of EFUSE_FLASH_TPUW
-         */
-        uint32_t flash_tpuw_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err2_reg_t;
-
-/** Type of rd_repeat_data_err3 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
-         */
-        uint32_t dis_download_mode_err:1;
-        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
-         */
-        uint32_t dis_direct_boot_err:1;
-        /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
-         */
-        uint32_t dis_usb_serial_jtag_rom_print_err:1;
-        /** lock_km_key_err : RO; bitpos: [3]; default: 0;
-         *  Represents the programming error of EFUSE_LOCK_KM_KEY
-         */
-        uint32_t lock_km_key_err:1;
-        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
-         */
-        uint32_t dis_usb_serial_jtag_download_mode_err:1;
-        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
-         *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
-         */
-        uint32_t enable_security_download_err:1;
-        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
-         *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
-         */
-        uint32_t uart_print_control_err:2;
-        /** force_send_resume_err : RO; bitpos: [8]; default: 0;
-         *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
-         */
-        uint32_t force_send_resume_err:1;
-        /** secure_version_err : RO; bitpos: [24:9]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_VERSION
-         */
-        uint32_t secure_version_err:16;
-        /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
-         */
-        uint32_t secure_boot_disable_fast_wake_err:1;
-        /** hys_en_pad_err : RO; bitpos: [26]; default: 0;
-         *  Represents the programming error of EFUSE_HYS_EN_PAD
-         */
-        uint32_t hys_en_pad_err:1;
-        /** key_purpose_0_h_err : RO; bitpos: [27]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_0_H
-         */
-        uint32_t key_purpose_0_h_err:1;
-        /** key_purpose_1_h_err : RO; bitpos: [28]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_1_H
-         */
-        uint32_t key_purpose_1_h_err:1;
-        /** key_purpose_2_h_err : RO; bitpos: [29]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_2_H
-         */
-        uint32_t key_purpose_2_h_err:1;
-        /** key_purpose_3_h_err : RO; bitpos: [30]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_3_H
-         */
-        uint32_t key_purpose_3_h_err:1;
-        /** key_purpose_4_h_err : RO; bitpos: [31]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_4_H
-         */
-        uint32_t key_purpose_4_h_err:1;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err3_reg_t;
-
-/** Type of rd_repeat_data_err4 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** pxa0_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0;
-         *  Represents the programming error of 0PXA_TIEH_SEL_0
-         */
-        uint32_t pxa0_tieh_sel_0_err:2;
-        /** pvt_glitch_en_err : RO; bitpos: [2]; default: 0;
-         *  Represents the programming error of EFUSE_PVT_GLITCH_EN
-         */
-        uint32_t pvt_glitch_en_err:1;
-        uint32_t reserved_3:1;
-        /** key_purpose_5_h_err : RO; bitpos: [4]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_5_H
-         */
-        uint32_t key_purpose_5_h_err:1;
-        uint32_t reserved_5:2;
-        /** km_disable_deploy_mode_h_err : RO; bitpos: [7]; default: 0;
-         *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE_H
-         */
-        uint32_t km_disable_deploy_mode_h_err:1;
-        /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0;
-         *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE
-         */
-        uint32_t km_disable_deploy_mode_err:4;
-        uint32_t reserved_12:4;
-        /** xts_dpa_pseudo_level_err : RO; bitpos: [17:16]; default: 0;
-         *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
-         */
-        uint32_t xts_dpa_pseudo_level_err:2;
-        /** hp_pwr_src_sel_err : RO; bitpos: [18]; default: 0;
-         *  Represents the programming error of EFUSE_HP_PWR_SRC_SEL
-         */
-        uint32_t hp_pwr_src_sel_err:1;
-        /** secure_boot_sha384_en_err : RO; bitpos: [19]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_SHA384_EN
-         */
-        uint32_t secure_boot_sha384_en_err:1;
-        /** dis_wdt_err : RO; bitpos: [20]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_WDT
-         */
-        uint32_t dis_wdt_err:1;
-        /** dis_swd_err : RO; bitpos: [21]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_SWD
-         */
-        uint32_t dis_swd_err:1;
-        /** pvt_glitch_mode_err : RO; bitpos: [23:22]; default: 0;
-         *  Represents the programming error of EFUSE_PVT_GLITCH_MODE
-         */
-        uint32_t pvt_glitch_mode_err:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err4_reg_t;
-
-
-/** Group: EFUSE ECDSA Configure Registers */
-/** Type of ecdsa register
- *  eFuse status register.
- */
-typedef union {
-    struct {
-        /** cfg_ecdsa_p192_blk : R/W; bitpos: [3:0]; default: 0;
-         *  Configures which block to use for ECDSA P192 key output.
-         */
-        uint32_t cfg_ecdsa_p192_blk:4;
-        /** cfg_ecdsa_p256_blk : R/W; bitpos: [7:4]; default: 0;
-         *  Configures which block to use for ECDSA P256 key output.
-         */
-        uint32_t cfg_ecdsa_p256_blk:4;
-        /** cfg_ecdsa_p384_l_blk : R/W; bitpos: [11:8]; default: 0;
-         *  Configures which block to use for ECDSA P384 key low part output.
-         */
-        uint32_t cfg_ecdsa_p384_l_blk:4;
-        /** cfg_ecdsa_p384_h_blk : R/W; bitpos: [15:12]; default: 0;
-         *  Configures which block to use for ECDSA P256 key high part output.
-         */
-        uint32_t cfg_ecdsa_p384_h_blk:4;
-        /** cur_ecdsa_p192_blk : RO; bitpos: [19:16]; default: 0;
-         *  Represents which block is used for ECDSA P192 key output.
-         */
-        uint32_t cur_ecdsa_p192_blk:4;
-        /** cur_ecdsa_p256_blk : RO; bitpos: [23:20]; default: 0;
-         *  Represents which block is used for ECDSA P256 key output.
-         */
-        uint32_t cur_ecdsa_p256_blk:4;
-        /** cur_ecdsa_p384_l_blk : RO; bitpos: [27:24]; default: 0;
-         *  Represents which block is used for ECDSA P384 key low part output.
-         */
-        uint32_t cur_ecdsa_p384_l_blk:4;
-        /** cur_ecdsa_p384_h_blk : RO; bitpos: [31:28]; default: 0;
-         *  Represents which block is used for ECDSA P384 key high part output.
-         */
-        uint32_t cur_ecdsa_p384_h_blk:4;
-    };
-    uint32_t val;
-} efuse_ecdsa_reg_t;
-
-
-/** Group: RS block error report registers */
-/** Type of rd_rs_data_err0 register
- *  Represents rd_rs_data_err
- */
-typedef union {
-    struct {
-        /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
-         *  Represents the error number of registers.
-         *  The value of this signal means the number of error bytes in rd_mac_sys
-         */
-        uint32_t rd_mac_sys_err_num:3;
-        /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0;
-         *  Represents error status of register.
-         *  0: Means no failure and that the data of rd_mac_sys is reliable
-         *  1: Means that programming rd_mac_sys failed and the number of error bytes is over 6.
-         */
-        uint32_t rd_mac_sys_fail:1;
-        /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0;
-         *  Represents the error number of registers.
-         *  The value of this signal means the number of error bytes in rd_sys_part1_data
-         */
-        uint32_t rd_sys_part1_data_err_num:3;
-        /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0;
-         *  Represents error status of register.
-         *  0: Means no failure and that the data of rd_sys_part1_data is reliable
-         *  1: Means that programming rd_sys_part1_data failed and the number of error bytes is
-         *  over 6.
-         */
-        uint32_t rd_sys_part1_data_fail:1;
-        /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0;
-         *  Represents the error number of registers.
-         *  The value of this signal means the number of error bytes in rd_usr_data
-         */
-        uint32_t rd_usr_data_err_num:3;
-        /** rd_usr_data_fail : RO; bitpos: [11]; default: 0;
-         *  Represents error status of register.
-         *  0: Means no failure and that the data of rd_usr_data is reliable
-         *  1: Means that programming rd_usr_data failed and the number of error bytes is over
-         *  6.
-         */
-        uint32_t rd_usr_data_fail:1;
-        /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0;
-         *  Represents the error number of registers.
-         *  The value of this signal means the number of error bytes in rd_key0_data
-         */
-        uint32_t rd_key0_data_err_num:3;
-        /** rd_key0_data_fail : RO; bitpos: [15]; default: 0;
-         *  Represents error status of register.
-         *  0: Means no failure and that the data of rd_key0_data is reliable
-         *  1: Means that programming rd_key0_data failed and the number of error bytes is over
-         *  6.
-         */
-        uint32_t rd_key0_data_fail:1;
-        /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0;
-         *  Represents the error number of registers.
-         *  The value of this signal means the number of error bytes in rd_key1_data
-         */
-        uint32_t rd_key1_data_err_num:3;
-        /** rd_key1_data_fail : RO; bitpos: [19]; default: 0;
-         *  Represents error status of register.
-         *  0: Means no failure and that the data of rd_key1_data is reliable
-         *  1: Means that programming rd_key1_data failed and the number of error bytes is over
-         *  6.
-         */
-        uint32_t rd_key1_data_fail:1;
-        /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0;
-         *  Represents the error number of registers.
-         *  The value of this signal means the number of error bytes in rd_key2_data
-         */
-        uint32_t rd_key2_data_err_num:3;
-        /** rd_key2_data_fail : RO; bitpos: [23]; default: 0;
-         *  Represents error status of register.
-         *  0: Means no failure and that the data of rd_key2_data is reliable
-         *  1: Means that programming rd_key2_data failed and the number of error bytes is over
-         *  6.
-         */
-        uint32_t rd_key2_data_fail:1;
-        /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0;
-         *  Represents the error number of registers.
-         *  The value of this signal means the number of error bytes in rd_key3_data
-         */
-        uint32_t rd_key3_data_err_num:3;
-        /** rd_key3_data_fail : RO; bitpos: [27]; default: 0;
-         *  Represents error status of register.
-         *  0: Means no failure and that the data of rd_key3_data is reliable
-         *  1: Means that programming rd_key3_data failed and the number of error bytes is over
-         *  6.
-         */
-        uint32_t rd_key3_data_fail:1;
-        /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0;
-         *  Represents the error number of registers.
-         *  The value of this signal means the number of error bytes in rd_key4_data
-         */
-        uint32_t rd_key4_data_err_num:3;
-        /** rd_key4_data_fail : RO; bitpos: [31]; default: 0;
-         *  Represents error status of register.
-         *  0: Means no failure and that the data of rd_key4_data is reliable
-         *  1: Means that programming rd_key4_data failed and the number of error bytes is over
-         *  6.
-         */
-        uint32_t rd_key4_data_fail:1;
-    };
-    uint32_t val;
-} efuse_rd_rs_data_err0_reg_t;
-
-/** Type of rd_rs_data_err1 register
- *  Represents rd_rs_data_err
- */
-typedef union {
-    struct {
-        /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0;
-         *  Represents the error number of registers.
-         *  The value of this signal means the number of error bytes in rd_key5_data
-         */
-        uint32_t rd_key5_data_err_num:3;
-        /** rd_key5_data_fail : RO; bitpos: [3]; default: 0;
-         *  Represents error status of register.
-         *  0: Means no failure and that the data of rd_key5_data is reliable
-         *  1: Means that programming rd_key5_data failed and the number of error bytes is over
-         *  6.
-         */
-        uint32_t rd_key5_data_fail:1;
-        /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0;
-         *  Represents the error number of registers.
-         *  The value of this signal means the number of error bytes in rd_sys_part2_data
-         */
-        uint32_t rd_sys_part2_data_err_num:3;
-        /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0;
-         *  Represents error status of register.
-         *  0: Means no failure and that the data of rd_sys_part2_data is reliable
-         *  1: Means that programming rd_sys_part2_data failed and the number of error bytes is
-         *  over 6.
-         */
-        uint32_t rd_sys_part2_data_fail:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} efuse_rd_rs_data_err1_reg_t;
-
-
-/** Group: ******** Registers */
-/** Type of clk register
- *  eFuse clcok configuration register.
- */
-typedef union {
-    struct {
-        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to force eFuse SRAM into power-saving mode.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
-         *  Set this bit and force to activate clock signal of eFuse SRAM.
-         */
-        uint32_t mem_clk_force_on:1;
-        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force eFuse SRAM into working mode.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_3:13;
-        /** clk_en : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to force enable eFuse register configuration clock signal.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} efuse_clk_reg_t;
-
-/** Type of conf register
- *  eFuse operation mode configuration register
- */
-typedef union {
-    struct {
-        /** op_code : R/W; bitpos: [15:0]; default: 0;
-         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
-         */
-        uint32_t op_code:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} efuse_conf_reg_t;
-
-/** Type of status register
- *  eFuse status register.
- */
-typedef union {
-    struct {
-        /** state : RO; bitpos: [3:0]; default: 0;
-         *  Indicates the state of the eFuse state machine.
-         */
-        uint32_t state:4;
-        uint32_t reserved_4:6;
-        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
-         *  Indicates the number of block valid bit.
-         */
-        uint32_t blk0_valid_bit_cnt:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} efuse_status_reg_t;
-
-/** Type of cmd register
- *  eFuse command register.
- */
-typedef union {
-    struct {
-        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
-         *  Set this bit to send read command.
-         */
-        uint32_t read_cmd:1;
-        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
-         *  Set this bit to send programming command.
-         */
-        uint32_t pgm_cmd:1;
-        /** blk_num : R/W; bitpos: [5:2]; default: 0;
-         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
-         *  number 0-10, respectively.
-         */
-        uint32_t blk_num:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} efuse_cmd_reg_t;
-
-/** Type of int_raw register
- *  eFuse raw interrupt register.
- */
-typedef union {
-    struct {
-        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  The raw bit signal for read_done interrupt.
-         */
-        uint32_t read_done_int_raw:1;
-        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
-         *  The raw bit signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_raw_reg_t;
-
-/** Type of int_st register
- *  eFuse interrupt status register.
- */
-typedef union {
-    struct {
-        /** read_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The status signal for read_done interrupt.
-         */
-        uint32_t read_done_int_st:1;
-        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The status signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_st_reg_t;
-
-/** Type of int_ena register
- *  eFuse interrupt enable register.
- */
-typedef union {
-    struct {
-        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable signal for read_done interrupt.
-         */
-        uint32_t read_done_int_ena:1;
-        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_ena_reg_t;
-
-/** Type of int_clr register
- *  eFuse interrupt clear register.
- */
-typedef union {
-    struct {
-        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear signal for read_done interrupt.
-         */
-        uint32_t read_done_int_clr:1;
-        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_clr_reg_t;
-
-/** Type of dac_conf register
- *  Controls the eFuse programming voltage.
- */
-typedef union {
-    struct {
-        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
-         *  Controls the division factor of the rising clock of the programming voltage.
-         */
-        uint32_t dac_clk_div:8;
-        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
-         *  Don't care.
-         */
-        uint32_t dac_clk_pad_sel:1;
-        /** dac_num : R/W; bitpos: [16:9]; default: 255;
-         *  Controls the rising period of the programming voltage.
-         */
-        uint32_t dac_num:8;
-        /** oe_clr : R/W; bitpos: [17]; default: 0;
-         *  Reduces the power supply of the programming voltage.
-         */
-        uint32_t oe_clr:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} efuse_dac_conf_reg_t;
-
-/** Type of rd_tim_conf register
- *  Configures read timing parameters.
- */
-typedef union {
-    struct {
-        /** thr_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the read hold time.
-         */
-        uint32_t thr_a:8;
-        /** trd : R/W; bitpos: [15:8]; default: 2;
-         *  Configures the read time.
-         */
-        uint32_t trd:8;
-        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
-         *  Configures the read setup time.
-         */
-        uint32_t tsur_a:8;
-        /** read_init_num : R/W; bitpos: [31:24]; default: 15;
-         *  Configures the waiting time of reading eFuse memory.
-         */
-        uint32_t read_init_num:8;
-    };
-    uint32_t val;
-} efuse_rd_tim_conf_reg_t;
-
-/** Type of wr_tim_conf1 register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the programming setup time.
-         */
-        uint32_t tsup_a:8;
-        /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831;
-         *  Configures the power up time for VDDQ.
-         */
-        uint32_t pwr_on_num:16;
-        /** thp_a : R/W; bitpos: [31:24]; default: 1;
-         *  Configures the programming hold time.
-         */
-        uint32_t thp_a:8;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf1_reg_t;
-
-/** Type of wr_tim_conf2 register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** pwr_off_num : R/W; bitpos: [15:0]; default: 320;
-         *  Configures the power outage time for VDDQ.
-         */
-        uint32_t pwr_off_num:16;
-        /** tpgm : R/W; bitpos: [31:16]; default: 160;
-         *  Configures the active programming time.
-         */
-        uint32_t tpgm:16;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf2_reg_t;
-
-/** Type of wr_tim_conf0_rs_bypass register
- *  Configurarion register0 of eFuse programming time parameters and rs bypass
- *  operation.
- */
-typedef union {
-    struct {
-        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to bypass reed solomon correction step.
-         */
-        uint32_t bypass_rs_correction:1;
-        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
-         *  Configures block number of programming twice operation.
-         */
-        uint32_t bypass_rs_blk_num:11;
-        /** update : WT; bitpos: [12]; default: 0;
-         *  Set this bit to update multi-bit register signals.
-         */
-        uint32_t update:1;
-        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
-         *  Configures the inactive programming time.
-         */
-        uint32_t tpgm_inactive:8;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf0_rs_bypass_reg_t;
-
-
-/** Group: EFUSE Version Register */
-/** Type of date register
- *  eFuse version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 38805904;
-         *  Stores eFuse version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} efuse_date_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Write Disable Data */
-/** Type of apb2otp_wr_dis register
- *  eFuse apb2otp block0 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 write disable data.
-         */
-        uint32_t apb2otp_block0_wr_dis:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_wr_dis_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */
-/** Type of apb2otp_blk0_backup1_w1 register
- *  eFuse apb2otp block0 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word1 data.
-         */
-        uint32_t apb2otp_block0_backup1_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */
-/** Type of apb2otp_blk0_backup1_w2 register
- *  eFuse apb2otp block0 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word2 data.
-         */
-        uint32_t apb2otp_block0_backup1_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */
-/** Type of apb2otp_blk0_backup1_w3 register
- *  eFuse apb2otp block0 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word3 data.
-         */
-        uint32_t apb2otp_block0_backup1_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */
-/** Type of apb2otp_blk0_backup1_w4 register
- *  eFuse apb2otp block0 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word4 data.
-         */
-        uint32_t apb2otp_block0_backup1_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */
-/** Type of apb2otp_blk0_backup1_w5 register
- *  eFuse apb2otp block0 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word5 data.
-         */
-        uint32_t apb2otp_block0_backup1_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */
-/** Type of apb2otp_blk0_backup2_w1 register
- *  eFuse apb2otp block0 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word1 data.
-         */
-        uint32_t apb2otp_block0_backup2_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */
-/** Type of apb2otp_blk0_backup2_w2 register
- *  eFuse apb2otp block0 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word2 data.
-         */
-        uint32_t apb2otp_block0_backup2_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */
-/** Type of apb2otp_blk0_backup2_w3 register
- *  eFuse apb2otp block0 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word3 data.
-         */
-        uint32_t apb2otp_block0_backup2_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */
-/** Type of apb2otp_blk0_backup2_w4 register
- *  eFuse apb2otp block0 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word4 data.
-         */
-        uint32_t apb2otp_block0_backup2_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */
-/** Type of apb2otp_blk0_backup2_w5 register
- *  eFuse apb2otp block0 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word5 data.
-         */
-        uint32_t apb2otp_block0_backup2_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */
-/** Type of apb2otp_blk0_backup3_w1 register
- *  eFuse apb2otp block0 data register12.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word1 data.
-         */
-        uint32_t apb2otp_block0_backup3_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */
-/** Type of apb2otp_blk0_backup3_w2 register
- *  eFuse apb2otp block0 data register13.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word2 data.
-         */
-        uint32_t apb2otp_block0_backup3_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */
-/** Type of apb2otp_blk0_backup3_w3 register
- *  eFuse apb2otp block0 data register14.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word3 data.
-         */
-        uint32_t apb2otp_block0_backup3_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */
-/** Type of apb2otp_blk0_backup3_w4 register
- *  eFuse apb2otp block0 data register15.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word4 data.
-         */
-        uint32_t apb2otp_block0_backup3_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */
-/** Type of apb2otp_blk0_backup3_w5 register
- *  eFuse apb2otp block0 data register16.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word5 data.
-         */
-        uint32_t apb2otp_block0_backup3_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */
-/** Type of apb2otp_blk0_backup4_w1 register
- *  eFuse apb2otp block0 data register17.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word1 data.
-         */
-        uint32_t apb2otp_block0_backup4_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */
-/** Type of apb2otp_blk0_backup4_w2 register
- *  eFuse apb2otp block0 data register18.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word2 data.
-         */
-        uint32_t apb2otp_block0_backup4_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */
-/** Type of apb2otp_blk0_backup4_w3 register
- *  eFuse apb2otp block0 data register19.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word3 data.
-         */
-        uint32_t apb2otp_block0_backup4_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */
-/** Type of apb2otp_blk0_backup4_w4 register
- *  eFuse apb2otp block0 data register20.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word4 data.
-         */
-        uint32_t apb2otp_block0_backup4_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */
-/** Type of apb2otp_blk0_backup4_w5 register
- *  eFuse apb2otp block0 data register21.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word5 data.
-         */
-        uint32_t apb2otp_block0_backup4_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word1 Data */
-/** Type of apb2otp_blk1_w1 register
- *  eFuse apb2otp block1 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word1 data.
-         */
-        uint32_t apb2otp_block1_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word2 Data */
-/** Type of apb2otp_blk1_w2 register
- *  eFuse apb2otp block1 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word2 data.
-         */
-        uint32_t apb2otp_block1_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word3 Data */
-/** Type of apb2otp_blk1_w3 register
- *  eFuse apb2otp block1 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word3 data.
-         */
-        uint32_t apb2otp_block1_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word4 Data */
-/** Type of apb2otp_blk1_w4 register
- *  eFuse apb2otp block1 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word4 data.
-         */
-        uint32_t apb2otp_block1_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word5 Data */
-/** Type of apb2otp_blk1_w5 register
- *  eFuse apb2otp block1 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word5 data.
-         */
-        uint32_t apb2otp_block1_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word6 Data */
-/** Type of apb2otp_blk1_w6 register
- *  eFuse apb2otp block1 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word6 data.
-         */
-        uint32_t apb2otp_block1_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word7 Data */
-/** Type of apb2otp_blk1_w7 register
- *  eFuse apb2otp block1 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word7 data.
-         */
-        uint32_t apb2otp_block1_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word8 Data */
-/** Type of apb2otp_blk1_w8 register
- *  eFuse apb2otp block1 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word8 data.
-         */
-        uint32_t apb2otp_block1_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word9 Data */
-/** Type of apb2otp_blk1_w9 register
- *  eFuse apb2otp block1 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word9 data.
-         */
-        uint32_t apb2otp_block1_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word1 Data */
-/** Type of apb2otp_blk2_w1 register
- *  eFuse apb2otp block2 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word1 data.
-         */
-        uint32_t apb2otp_block2_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word2 Data */
-/** Type of apb2otp_blk2_w2 register
- *  eFuse apb2otp block2 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word2 data.
-         */
-        uint32_t apb2otp_block2_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word3 Data */
-/** Type of apb2otp_blk2_w3 register
- *  eFuse apb2otp block2 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word3 data.
-         */
-        uint32_t apb2otp_block2_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word4 Data */
-/** Type of apb2otp_blk2_w4 register
- *  eFuse apb2otp block2 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word4 data.
-         */
-        uint32_t apb2otp_block2_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word5 Data */
-/** Type of apb2otp_blk2_w5 register
- *  eFuse apb2otp block2 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word5 data.
-         */
-        uint32_t apb2otp_block2_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word6 Data */
-/** Type of apb2otp_blk2_w6 register
- *  eFuse apb2otp block2 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word6 data.
-         */
-        uint32_t apb2otp_block2_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word7 Data */
-/** Type of apb2otp_blk2_w7 register
- *  eFuse apb2otp block2 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word7 data.
-         */
-        uint32_t apb2otp_block2_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word8 Data */
-/** Type of apb2otp_blk2_w8 register
- *  eFuse apb2otp block2 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word8 data.
-         */
-        uint32_t apb2otp_block2_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word9 Data */
-/** Type of apb2otp_blk2_w9 register
- *  eFuse apb2otp block2 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word9 data.
-         */
-        uint32_t apb2otp_block2_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word10 Data */
-/** Type of apb2otp_blk2_w10 register
- *  eFuse apb2otp block2 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word10 data.
-         */
-        uint32_t apb2otp_block2_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word11 Data */
-/** Type of apb2otp_blk2_w11 register
- *  eFuse apb2otp block2 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word11 data.
-         */
-        uint32_t apb2otp_block2_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w11_reg_t;
-
-/** Type of apb2otp_blk10_w11 register
- *  eFuse apb2otp block10 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word11 data.
-         */
-        uint32_t apb2otp_block10_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word1 Data */
-/** Type of apb2otp_blk3_w1 register
- *  eFuse apb2otp block3 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word1 data.
-         */
-        uint32_t apb2otp_block3_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word2 Data */
-/** Type of apb2otp_blk3_w2 register
- *  eFuse apb2otp block3 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word2 data.
-         */
-        uint32_t apb2otp_block3_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word3 Data */
-/** Type of apb2otp_blk3_w3 register
- *  eFuse apb2otp block3 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word3 data.
-         */
-        uint32_t apb2otp_block3_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word4 Data */
-/** Type of apb2otp_blk3_w4 register
- *  eFuse apb2otp block3 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word4 data.
-         */
-        uint32_t apb2otp_block3_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word5 Data */
-/** Type of apb2otp_blk3_w5 register
- *  eFuse apb2otp block3 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word5 data.
-         */
-        uint32_t apb2otp_block3_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word6 Data */
-/** Type of apb2otp_blk3_w6 register
- *  eFuse apb2otp block3 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word6 data.
-         */
-        uint32_t apb2otp_block3_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word7 Data */
-/** Type of apb2otp_blk3_w7 register
- *  eFuse apb2otp block3 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word7 data.
-         */
-        uint32_t apb2otp_block3_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word8 Data */
-/** Type of apb2otp_blk3_w8 register
- *  eFuse apb2otp block3 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word8 data.
-         */
-        uint32_t apb2otp_block3_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word9 Data */
-/** Type of apb2otp_blk3_w9 register
- *  eFuse apb2otp block3 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word9 data.
-         */
-        uint32_t apb2otp_block3_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word10 Data */
-/** Type of apb2otp_blk3_w10 register
- *  eFuse apb2otp block3 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word10 data.
-         */
-        uint32_t apb2otp_block3_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word11 Data */
-/** Type of apb2otp_blk3_w11 register
- *  eFuse apb2otp block3 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word11 data.
-         */
-        uint32_t apb2otp_block3_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word1 Data */
-/** Type of apb2otp_blk4_w1 register
- *  eFuse apb2otp block4 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word1 data.
-         */
-        uint32_t apb2otp_block4_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word2 Data */
-/** Type of apb2otp_blk4_w2 register
- *  eFuse apb2otp block4 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word2 data.
-         */
-        uint32_t apb2otp_block4_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word3 Data */
-/** Type of apb2otp_blk4_w3 register
- *  eFuse apb2otp block4 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word3 data.
-         */
-        uint32_t apb2otp_block4_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word4 Data */
-/** Type of apb2otp_blk4_w4 register
- *  eFuse apb2otp block4 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word4 data.
-         */
-        uint32_t apb2otp_block4_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word5 Data */
-/** Type of apb2otp_blk4_w5 register
- *  eFuse apb2otp block4 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word5 data.
-         */
-        uint32_t apb2otp_block4_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word6 Data */
-/** Type of apb2otp_blk4_w6 register
- *  eFuse apb2otp block4 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word6 data.
-         */
-        uint32_t apb2otp_block4_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word7 Data */
-/** Type of apb2otp_blk4_w7 register
- *  eFuse apb2otp block4 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word7 data.
-         */
-        uint32_t apb2otp_block4_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word8 Data */
-/** Type of apb2otp_blk4_w8 register
- *  eFuse apb2otp block4 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word8 data.
-         */
-        uint32_t apb2otp_block4_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word9 Data */
-/** Type of apb2otp_blk4_w9 register
- *  eFuse apb2otp block4 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word9 data.
-         */
-        uint32_t apb2otp_block4_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word10 Data */
-/** Type of apb2otp_blk4_w10 register
- *  eFuse apb2otp block4 data registe10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word10 data.
-         */
-        uint32_t apb2otp_block4_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word11 Data */
-/** Type of apb2otp_blk4_w11 register
- *  eFuse apb2otp block4 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word11 data.
-         */
-        uint32_t apb2otp_block4_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word1 Data */
-/** Type of apb2otp_blk5_w1 register
- *  eFuse apb2otp block5 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word1 data.
-         */
-        uint32_t apb2otp_block5_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word2 Data */
-/** Type of apb2otp_blk5_w2 register
- *  eFuse apb2otp block5 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word2 data.
-         */
-        uint32_t apb2otp_block5_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word3 Data */
-/** Type of apb2otp_blk5_w3 register
- *  eFuse apb2otp block5 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word3 data.
-         */
-        uint32_t apb2otp_block5_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word4 Data */
-/** Type of apb2otp_blk5_w4 register
- *  eFuse apb2otp block5 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word4 data.
-         */
-        uint32_t apb2otp_block5_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word5 Data */
-/** Type of apb2otp_blk5_w5 register
- *  eFuse apb2otp block5 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word5 data.
-         */
-        uint32_t apb2otp_block5_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word6 Data */
-/** Type of apb2otp_blk5_w6 register
- *  eFuse apb2otp block5 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word6 data.
-         */
-        uint32_t apb2otp_block5_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word7 Data */
-/** Type of apb2otp_blk5_w7 register
- *  eFuse apb2otp block5 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word7 data.
-         */
-        uint32_t apb2otp_block5_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word8 Data */
-/** Type of apb2otp_blk5_w8 register
- *  eFuse apb2otp block5 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word8 data.
-         */
-        uint32_t apb2otp_block5_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word9 Data */
-/** Type of apb2otp_blk5_w9 register
- *  eFuse apb2otp block5 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word9 data.
-         */
-        uint32_t apb2otp_block5_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word10 Data */
-/** Type of apb2otp_blk5_w10 register
- *  eFuse apb2otp block5 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word10 data.
-         */
-        uint32_t apb2otp_block5_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word11 Data */
-/** Type of apb2otp_blk5_w11 register
- *  eFuse apb2otp block5 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word11 data.
-         */
-        uint32_t apb2otp_block5_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word1 Data */
-/** Type of apb2otp_blk6_w1 register
- *  eFuse apb2otp block6 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word1 data.
-         */
-        uint32_t apb2otp_block6_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word2 Data */
-/** Type of apb2otp_blk6_w2 register
- *  eFuse apb2otp block6 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word2 data.
-         */
-        uint32_t apb2otp_block6_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word3 Data */
-/** Type of apb2otp_blk6_w3 register
- *  eFuse apb2otp block6 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word3 data.
-         */
-        uint32_t apb2otp_block6_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word4 Data */
-/** Type of apb2otp_blk6_w4 register
- *  eFuse apb2otp block6 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word4 data.
-         */
-        uint32_t apb2otp_block6_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word5 Data */
-/** Type of apb2otp_blk6_w5 register
- *  eFuse apb2otp block6 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word5 data.
-         */
-        uint32_t apb2otp_block6_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word6 Data */
-/** Type of apb2otp_blk6_w6 register
- *  eFuse apb2otp block6 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word6 data.
-         */
-        uint32_t apb2otp_block6_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word7 Data */
-/** Type of apb2otp_blk6_w7 register
- *  eFuse apb2otp block6 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word7 data.
-         */
-        uint32_t apb2otp_block6_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word8 Data */
-/** Type of apb2otp_blk6_w8 register
- *  eFuse apb2otp block6 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word8 data.
-         */
-        uint32_t apb2otp_block6_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word9 Data */
-/** Type of apb2otp_blk6_w9 register
- *  eFuse apb2otp block6 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word9 data.
-         */
-        uint32_t apb2otp_block6_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word10 Data */
-/** Type of apb2otp_blk6_w10 register
- *  eFuse apb2otp block6 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word10 data.
-         */
-        uint32_t apb2otp_block6_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word11 Data */
-/** Type of apb2otp_blk6_w11 register
- *  eFuse apb2otp block6 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word11 data.
-         */
-        uint32_t apb2otp_block6_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word1 Data */
-/** Type of apb2otp_blk7_w1 register
- *  eFuse apb2otp block7 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word1 data.
-         */
-        uint32_t apb2otp_block7_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word2 Data */
-/** Type of apb2otp_blk7_w2 register
- *  eFuse apb2otp block7 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word2 data.
-         */
-        uint32_t apb2otp_block7_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word3 Data */
-/** Type of apb2otp_blk7_w3 register
- *  eFuse apb2otp block7 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word3 data.
-         */
-        uint32_t apb2otp_block7_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word4 Data */
-/** Type of apb2otp_blk7_w4 register
- *  eFuse apb2otp block7 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word4 data.
-         */
-        uint32_t apb2otp_block7_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word5 Data */
-/** Type of apb2otp_blk7_w5 register
- *  eFuse apb2otp block7 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word5 data.
-         */
-        uint32_t apb2otp_block7_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word6 Data */
-/** Type of apb2otp_blk7_w6 register
- *  eFuse apb2otp block7 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word6 data.
-         */
-        uint32_t apb2otp_block7_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word7 Data */
-/** Type of apb2otp_blk7_w7 register
- *  eFuse apb2otp block7 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word7 data.
-         */
-        uint32_t apb2otp_block7_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word8 Data */
-/** Type of apb2otp_blk7_w8 register
- *  eFuse apb2otp block7 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word8 data.
-         */
-        uint32_t apb2otp_block7_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word9 Data */
-/** Type of apb2otp_blk7_w9 register
- *  eFuse apb2otp block7 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word9 data.
-         */
-        uint32_t apb2otp_block7_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word10 Data */
-/** Type of apb2otp_blk7_w10 register
- *  eFuse apb2otp block7 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word10 data.
-         */
-        uint32_t apb2otp_block7_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word11 Data */
-/** Type of apb2otp_blk7_w11 register
- *  eFuse apb2otp block7 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word11 data.
-         */
-        uint32_t apb2otp_block7_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word1 Data */
-/** Type of apb2otp_blk8_w1 register
- *  eFuse apb2otp block8 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word1 data.
-         */
-        uint32_t apb2otp_block8_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word2 Data */
-/** Type of apb2otp_blk8_w2 register
- *  eFuse apb2otp block8 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word2 data.
-         */
-        uint32_t apb2otp_block8_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word3 Data */
-/** Type of apb2otp_blk8_w3 register
- *  eFuse apb2otp block8 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word3 data.
-         */
-        uint32_t apb2otp_block8_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word4 Data */
-/** Type of apb2otp_blk8_w4 register
- *  eFuse apb2otp block8 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word4 data.
-         */
-        uint32_t apb2otp_block8_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word5 Data */
-/** Type of apb2otp_blk8_w5 register
- *  eFuse apb2otp block8 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word5 data.
-         */
-        uint32_t apb2otp_block8_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word6 Data */
-/** Type of apb2otp_blk8_w6 register
- *  eFuse apb2otp block8 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word6 data.
-         */
-        uint32_t apb2otp_block8_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word7 Data */
-/** Type of apb2otp_blk8_w7 register
- *  eFuse apb2otp block8 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word7 data.
-         */
-        uint32_t apb2otp_block8_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word8 Data */
-/** Type of apb2otp_blk8_w8 register
- *  eFuse apb2otp block8 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word8 data.
-         */
-        uint32_t apb2otp_block8_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word9 Data */
-/** Type of apb2otp_blk8_w9 register
- *  eFuse apb2otp block8 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word9 data.
-         */
-        uint32_t apb2otp_block8_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word10 Data */
-/** Type of apb2otp_blk8_w10 register
- *  eFuse apb2otp block8 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word10 data.
-         */
-        uint32_t apb2otp_block8_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word11 Data */
-/** Type of apb2otp_blk8_w11 register
- *  eFuse apb2otp block8 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word11 data.
-         */
-        uint32_t apb2otp_block8_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word1 Data */
-/** Type of apb2otp_blk9_w1 register
- *  eFuse apb2otp block9 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word1 data.
-         */
-        uint32_t apb2otp_block9_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word2 Data */
-/** Type of apb2otp_blk9_w2 register
- *  eFuse apb2otp block9 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word2 data.
-         */
-        uint32_t apb2otp_block9_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word3 Data */
-/** Type of apb2otp_blk9_w3 register
- *  eFuse apb2otp block9 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word3 data.
-         */
-        uint32_t apb2otp_block9_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word4 Data */
-/** Type of apb2otp_blk9_w4 register
- *  eFuse apb2otp block9 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word4 data.
-         */
-        uint32_t apb2otp_block9_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word5 Data */
-/** Type of apb2otp_blk9_w5 register
- *  eFuse apb2otp block9 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word5 data.
-         */
-        uint32_t apb2otp_block9_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word6 Data */
-/** Type of apb2otp_blk9_w6 register
- *  eFuse apb2otp block9 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word6 data.
-         */
-        uint32_t apb2otp_block9_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word7 Data */
-/** Type of apb2otp_blk9_w7 register
- *  eFuse apb2otp block9 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word7 data.
-         */
-        uint32_t apb2otp_block9_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word8 Data */
-/** Type of apb2otp_blk9_w8 register
- *  eFuse apb2otp block9 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word8 data.
-         */
-        uint32_t apb2otp_block9_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word9 Data */
-/** Type of apb2otp_blk9_w9 register
- *  eFuse apb2otp block9 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word9 data.
-         */
-        uint32_t apb2otp_block9_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word10 Data */
-/** Type of apb2otp_blk9_w10 register
- *  eFuse apb2otp block9 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word10 data.
-         */
-        uint32_t apb2otp_block9_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word11 Data */
-/** Type of apb2otp_blk9_w11 register
- *  eFuse apb2otp block9 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word11 data.
-         */
-        uint32_t apb2otp_block9_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word1 Data */
-/** Type of apb2otp_blk10_w1 register
- *  eFuse apb2otp block10 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word1 data.
-         */
-        uint32_t apb2otp_block10_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word2 Data */
-/** Type of apb2otp_blk10_w2 register
- *  eFuse apb2otp block10 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word2 data.
-         */
-        uint32_t apb2otp_block10_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word3 Data */
-/** Type of apb2otp_blk10_w3 register
- *  eFuse apb2otp block10 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word3 data.
-         */
-        uint32_t apb2otp_block10_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word4 Data */
-/** Type of apb2otp_blk10_w4 register
- *  eFuse apb2otp block10 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word4 data.
-         */
-        uint32_t apb2otp_block10_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word5 Data */
-/** Type of apb2otp_blk10_w5 register
- *  eFuse apb2otp block10 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word5 data.
-         */
-        uint32_t apb2otp_block10_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word6 Data */
-/** Type of apb2otp_blk10_w6 register
- *  eFuse apb2otp block10 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word6 data.
-         */
-        uint32_t apb2otp_block10_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word7 Data */
-/** Type of apb2otp_blk10_w7 register
- *  eFuse apb2otp block10 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word7 data.
-         */
-        uint32_t apb2otp_block10_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word8 Data */
-/** Type of apb2otp_blk10_w8 register
- *  eFuse apb2otp block10 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word8 data.
-         */
-        uint32_t apb2otp_block10_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word9 Data */
-/** Type of apb2otp_blk10_w9 register
- *  eFuse apb2otp block10 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word9 data.
-         */
-        uint32_t apb2otp_block10_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word10 Data */
-/** Type of apb2otp_blk10_w10 register
- *  eFuse apb2otp block10 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block19_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word10 data.
-         */
-        uint32_t apb2otp_block19_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Function Enable Signal */
-/** Type of apb2otp_en register
- *  eFuse apb2otp enable configuration register.
- */
-typedef union {
-    struct {
-        /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0;
-         *  Apb2otp mode enable signal.
-         */
-        uint32_t apb2otp_apb2otp_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} efuse_apb2otp_en_reg_t;
-
-
-typedef struct {
-    volatile efuse_pgm_datan_reg_t pgm_datan[8];
-    volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3];
-    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
-    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
-    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
-    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
-    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
-    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
-    volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0;
-    volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1;
-    uint32_t reserved_04c;
-    volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3;
-    volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4;
-    volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5;
-    volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8];
-    volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8];
-    volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8];
-    volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8];
-    volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8];
-    volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8];
-    volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8];
-    volatile efuse_rd_key5_datan_reg_t rd_key5_datan[8];
-    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
-    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
-    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
-    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
-    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
-    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
-    uint32_t reserved_174;
-    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
-    volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0;
-    volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1;
-    volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2;
-    volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3;
-    volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4;
-    uint32_t reserved_190[8];
-    volatile efuse_ecdsa_reg_t ecdsa;
-    uint32_t reserved_1b4[3];
-    volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0;
-    volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1;
-    volatile efuse_clk_reg_t clk;
-    volatile efuse_conf_reg_t conf;
-    volatile efuse_status_reg_t status;
-    volatile efuse_cmd_reg_t cmd;
-    volatile efuse_int_raw_reg_t int_raw;
-    volatile efuse_int_st_reg_t int_st;
-    volatile efuse_int_ena_reg_t int_ena;
-    volatile efuse_int_clr_reg_t int_clr;
-    volatile efuse_dac_conf_reg_t dac_conf;
-    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
-    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
-    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
-    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
-    volatile efuse_date_reg_t date;
-    uint32_t reserved_200[384];
-    volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis;
-    volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1;
-    volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2;
-    volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3;
-    volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4;
-    volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5;
-    volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1;
-    volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2;
-    volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3;
-    volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4;
-    volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5;
-    volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1;
-    volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2;
-    volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3;
-    volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4;
-    volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5;
-    volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1;
-    volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2;
-    volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3;
-    volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4;
-    volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5;
-    volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1;
-    volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2;
-    volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3;
-    volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4;
-    volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5;
-    volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6;
-    volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7;
-    volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8;
-    volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9;
-    volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1;
-    volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2;
-    volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3;
-    volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4;
-    volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5;
-    volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6;
-    volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7;
-    volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8;
-    volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9;
-    volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10;
-    volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11;
-    volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1;
-    volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2;
-    volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3;
-    volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4;
-    volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5;
-    volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6;
-    volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7;
-    volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8;
-    volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9;
-    volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10;
-    volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11;
-    volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1;
-    volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2;
-    volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3;
-    volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4;
-    volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5;
-    volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6;
-    volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7;
-    volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8;
-    volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9;
-    volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10;
-    volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11;
-    volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1;
-    volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2;
-    volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3;
-    volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4;
-    volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5;
-    volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6;
-    volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7;
-    volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8;
-    volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9;
-    volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10;
-    volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11;
-    volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1;
-    volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2;
-    volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3;
-    volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4;
-    volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5;
-    volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6;
-    volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7;
-    volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8;
-    volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9;
-    volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10;
-    volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11;
-    volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1;
-    volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2;
-    volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3;
-    volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4;
-    volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5;
-    volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6;
-    volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7;
-    volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8;
-    volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9;
-    volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10;
-    volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11;
-    volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1;
-    volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2;
-    volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3;
-    volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4;
-    volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5;
-    volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6;
-    volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7;
-    volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8;
-    volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9;
-    volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10;
-    volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11;
-    volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1;
-    volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2;
-    volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3;
-    volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4;
-    volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5;
-    volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6;
-    volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7;
-    volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8;
-    volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9;
-    volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10;
-    volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11;
-    volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1;
-    volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2;
-    volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3;
-    volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4;
-    volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5;
-    volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6;
-    volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7;
-    volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8;
-    volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9;
-    volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10;
-    volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11;
-    uint32_t reserved_a04;
-    volatile efuse_apb2otp_en_reg_t apb2otp_en;
-} efuse_dev_t;
-
-extern efuse_dev_t EFUSE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(efuse_dev_t) == 0xa0c, "Invalid size of efuse_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/efuse_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/efuse_reg.h
index e0a0a82e4e9b..26cec8c6f127 100644
--- a/components/soc/esp32p4/register/hw_ver3/soc/efuse_reg.h
+++ b/components/soc/esp32p4/register/hw_ver3/soc/efuse_reg.h
@@ -12,10 +12,8 @@
 extern "C" {
 #endif
 
-//TODO: IDF-13421
-
 /** EFUSE_PGM_DATA0_REG register
- *  Register 0 that stores data to be programmed.
+ *  Represents pgm_data0
  */
 #define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
 /** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
@@ -27,11 +25,11 @@ extern "C" {
 #define EFUSE_PGM_DATA_0_S  0
 
 /** EFUSE_PGM_DATA1_REG register
- *  Register 1 that stores data to be programmed.
+ *  Represents pgm_data1
  */
 #define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
 /** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 1st 32-bit data to be programmed.
+ *  Configures the 0th 32-bit data to be programmed.
  */
 #define EFUSE_PGM_DATA_1    0xFFFFFFFFU
 #define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
@@ -39,11 +37,11 @@ extern "C" {
 #define EFUSE_PGM_DATA_1_S  0
 
 /** EFUSE_PGM_DATA2_REG register
- *  Register 2 that stores data to be programmed.
+ *  Represents pgm_data2
  */
 #define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
 /** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 2nd 32-bit data to be programmed.
+ *  Configures the 0th 32-bit data to be programmed.
  */
 #define EFUSE_PGM_DATA_2    0xFFFFFFFFU
 #define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
@@ -51,11 +49,11 @@ extern "C" {
 #define EFUSE_PGM_DATA_2_S  0
 
 /** EFUSE_PGM_DATA3_REG register
- *  Register 3 that stores data to be programmed.
+ *  Represents pgm_data3
  */
 #define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
 /** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 3rd 32-bit data to be programmed.
+ *  Configures the 0th 32-bit data to be programmed.
  */
 #define EFUSE_PGM_DATA_3    0xFFFFFFFFU
 #define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
@@ -63,11 +61,11 @@ extern "C" {
 #define EFUSE_PGM_DATA_3_S  0
 
 /** EFUSE_PGM_DATA4_REG register
- *  Register 4 that stores data to be programmed.
+ *  Represents pgm_data4
  */
 #define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
 /** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 4th 32-bit data to be programmed.
+ *  Configures the 0th 32-bit data to be programmed.
  */
 #define EFUSE_PGM_DATA_4    0xFFFFFFFFU
 #define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
@@ -75,11 +73,11 @@ extern "C" {
 #define EFUSE_PGM_DATA_4_S  0
 
 /** EFUSE_PGM_DATA5_REG register
- *  Register 5 that stores data to be programmed.
+ *  Represents pgm_data5
  */
 #define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
 /** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 5th 32-bit data to be programmed.
+ *  Configures the 0th 32-bit data to be programmed.
  */
 #define EFUSE_PGM_DATA_5    0xFFFFFFFFU
 #define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
@@ -87,11 +85,11 @@ extern "C" {
 #define EFUSE_PGM_DATA_5_S  0
 
 /** EFUSE_PGM_DATA6_REG register
- *  Register 6 that stores data to be programmed.
+ *  Represents pgm_data6
  */
 #define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
 /** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 6th 32-bit data to be programmed.
+ *  Configures the 0th 32-bit data to be programmed.
  */
 #define EFUSE_PGM_DATA_6    0xFFFFFFFFU
 #define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
@@ -99,11 +97,11 @@ extern "C" {
 #define EFUSE_PGM_DATA_6_S  0
 
 /** EFUSE_PGM_DATA7_REG register
- *  Register 7 that stores data to be programmed.
+ *  Represents pgm_data7
  */
 #define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
 /** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 7th 32-bit data to be programmed.
+ *  Configures the 0th 32-bit data to be programmed.
  */
 #define EFUSE_PGM_DATA_7    0xFFFFFFFFU
 #define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
@@ -111,11 +109,11 @@ extern "C" {
 #define EFUSE_PGM_DATA_7_S  0
 
 /** EFUSE_PGM_CHECK_VALUE0_REG register
- *  Register 0 that stores the RS code to be programmed.
+ *  Represents pgm_check_value0
  */
 #define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
 /** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit RS code to be programmed.
+ *  Configures the 0th RS code to be programmed.
  */
 #define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
 #define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
@@ -123,11 +121,11 @@ extern "C" {
 #define EFUSE_PGM_RS_DATA_0_S  0
 
 /** EFUSE_PGM_CHECK_VALUE1_REG register
- *  Register 1 that stores the RS code to be programmed.
+ *  Represents pgm_check_value1
  */
 #define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
 /** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 1st 32-bit RS code to be programmed.
+ *  Configures the 0th RS code to be programmed.
  */
 #define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
 #define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
@@ -135,11 +133,11 @@ extern "C" {
 #define EFUSE_PGM_RS_DATA_1_S  0
 
 /** EFUSE_PGM_CHECK_VALUE2_REG register
- *  Register 2 that stores the RS code to be programmed.
+ *  Represents pgm_check_value2
  */
 #define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
 /** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 2nd 32-bit RS code to be programmed.
+ *  Configures the 0th RS code to be programmed.
  */
 #define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
 #define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
@@ -147,12 +145,14 @@ extern "C" {
 #define EFUSE_PGM_RS_DATA_2_S  0
 
 /** EFUSE_RD_WR_DIS_REG register
- *  BLOCK0 data register 0.
+ *  Represents rd_wr_dis
  */
 #define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
 /** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Represents whether programming of individual eFuse memory bit is disabled or
- *  enabled. 1: Disabled. 0 Enabled.
+ *  Represents whether programming of individual eFuse memory bit is disabled.  For
+ *  mapping between the bits of this field and the eFuse memory bits, please refer to
+ *  Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}.\\1:
+ *  Disabled\\0: Enabled\\
  */
 #define EFUSE_WR_DIS    0xFFFFFFFFU
 #define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
@@ -160,56 +160,51 @@ extern "C" {
 #define EFUSE_WR_DIS_S  0
 
 /** EFUSE_RD_REPEAT_DATA0_REG register
- *  BLOCK0 data register 1.
+ *  Represents rd_repeat_data
  */
 #define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
 /** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
  *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
- *  enabled. 1: disabled. 0: enabled.
+ *  enabled.\\ 1: disabled\\ 0: enabled\\
  */
 #define EFUSE_RD_DIS    0x0000007FU
 #define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
 #define EFUSE_RD_DIS_V  0x0000007FU
 #define EFUSE_RD_DIS_S  0
-/** EFUSE_USB_DEVICE_EXCHG_PINS : RO; bitpos: [7]; default: 0;
- *  Enable usb device exchange pins of D+ and D-.
- */
-#define EFUSE_USB_DEVICE_EXCHG_PINS    (BIT(7))
-#define EFUSE_USB_DEVICE_EXCHG_PINS_M  (EFUSE_USB_DEVICE_EXCHG_PINS_V << EFUSE_USB_DEVICE_EXCHG_PINS_S)
-#define EFUSE_USB_DEVICE_EXCHG_PINS_V  0x00000001U
-#define EFUSE_USB_DEVICE_EXCHG_PINS_S  7
-/** EFUSE_USB_OTG11_EXCHG_PINS : RO; bitpos: [8]; default: 0;
- *  Enable usb otg11 exchange pins of D+ and D-.
- */
-#define EFUSE_USB_OTG11_EXCHG_PINS    (BIT(8))
-#define EFUSE_USB_OTG11_EXCHG_PINS_M  (EFUSE_USB_OTG11_EXCHG_PINS_V << EFUSE_USB_OTG11_EXCHG_PINS_S)
-#define EFUSE_USB_OTG11_EXCHG_PINS_V  0x00000001U
-#define EFUSE_USB_OTG11_EXCHG_PINS_S  8
+/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1 : RO; bitpos: [8:7]; default: 0;
+ *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+ *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+ *  - this feature is disabled.
+ */
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1    0x00000003U
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_M  (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_S)
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_V  0x00000003U
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_S  7
 /** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
- *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
- *  disabled. 0: enabled.
+ *  Set this bit to disable function of usb switch to jtag in module of usb device.
  */
 #define EFUSE_DIS_USB_JTAG    (BIT(9))
 #define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
 #define EFUSE_DIS_USB_JTAG_V  0x00000001U
 #define EFUSE_DIS_USB_JTAG_S  9
-/** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0;
- *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
- */
-#define EFUSE_POWERGLITCH_EN    (BIT(10))
-#define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
-#define EFUSE_POWERGLITCH_EN_V  0x00000001U
-#define EFUSE_POWERGLITCH_EN_S  10
+/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2 : RO; bitpos: [10]; default: 0;
+ *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+ *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+ *  - this feature is disabled.
+ */
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2    (BIT(10))
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_M  (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_S)
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_V  0x00000001U
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_S  10
 /** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
- *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+ *  Set this bit to disable USB-Serial-JTAG.
  */
 #define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
 #define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
 #define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
 #define EFUSE_DIS_USB_SERIAL_JTAG_S  11
 /** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
- *  Represents whether the function that forces chip into download mode is disabled or
- *  enabled. 1: disabled. 0: enabled.
+ *  Set this bit to disable the function that forces chip into download mode.
  */
 #define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
 #define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
@@ -224,106 +219,122 @@ extern "C" {
 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
 /** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
- *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
+ *  Set this bit to disable TWAI function.
  */
 #define EFUSE_DIS_TWAI    (BIT(14))
 #define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
 #define EFUSE_DIS_TWAI_V  0x00000001U
 #define EFUSE_DIS_TWAI_S  14
 /** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
- *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
- *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
- *  is enabled or disabled. 1: enabled. 0: disabled.
+ *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
+ *  strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0.
  */
 #define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
 #define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
 #define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
 #define EFUSE_JTAG_SEL_ENABLE_S  15
 /** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
- *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
- *  enabled.
+ *  Set odd bits to disable JTAG in the soft way. JTAG can be enabled in HMAC module.
  */
 #define EFUSE_SOFT_DIS_JTAG    0x00000007U
 #define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
 #define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
 #define EFUSE_SOFT_DIS_JTAG_S  16
 /** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
- *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
- *  enabled.
+ *  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
  */
 #define EFUSE_DIS_PAD_JTAG    (BIT(19))
 #define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
 #define EFUSE_DIS_PAD_JTAG_V  0x00000001U
 #define EFUSE_DIS_PAD_JTAG_S  19
 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
- *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
- *  mode). 1: disabled. 0: enabled.
+ *  Set this bit to disable flash manual encrypt function (except in SPI boot mode).
  */
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
-/** EFUSE_USB_DEVICE_DREFH : RO; bitpos: [22:21]; default: 0;
- *  USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV
- */
-#define EFUSE_USB_DEVICE_DREFH    0x00000003U
-#define EFUSE_USB_DEVICE_DREFH_M  (EFUSE_USB_DEVICE_DREFH_V << EFUSE_USB_DEVICE_DREFH_S)
-#define EFUSE_USB_DEVICE_DREFH_V  0x00000003U
-#define EFUSE_USB_DEVICE_DREFH_S  21
-/** EFUSE_USB_OTG11_DREFH : RO; bitpos: [24:23]; default: 0;
- *  USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV
- */
-#define EFUSE_USB_OTG11_DREFH    0x00000003U
-#define EFUSE_USB_OTG11_DREFH_M  (EFUSE_USB_OTG11_DREFH_V << EFUSE_USB_OTG11_DREFH_S)
-#define EFUSE_USB_OTG11_DREFH_V  0x00000003U
-#define EFUSE_USB_OTG11_DREFH_S  23
+/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6 : RO; bitpos: [24:21]; default: 0;
+ *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+ *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+ *  - this feature is disabled.
+ */
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6    0x0000000FU
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_M  (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_S)
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_V  0x0000000FU
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_S  21
 /** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0;
- *  TBD
+ *  0: intphy(gpio24/25) <---> usb_device\\ 1: intphy(26/27) <---> usb_otg11.1:
+ *  intphy(gpio26/27) <---> usb_device\\ 1: intphy(24/25) <---> usb_otg11.
  */
 #define EFUSE_USB_PHY_SEL    (BIT(25))
 #define EFUSE_USB_PHY_SEL_M  (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S)
 #define EFUSE_USB_PHY_SEL_V  0x00000001U
 #define EFUSE_USB_PHY_SEL_S  25
-/** EFUSE_KM_HUK_GEN_STATE_LOW : RO; bitpos: [31:26]; default: 0;
- *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+/** EFUSE_HUK_GEN_STATE : RO; bitpos: [30:26]; default: 0;
+ *  Set the bits to control validation of HUK generate mode. Odd of 1 is invalid, even
  *  of 1 is valid.
  */
-#define EFUSE_KM_HUK_GEN_STATE_LOW    0x0000003FU
-#define EFUSE_KM_HUK_GEN_STATE_LOW_M  (EFUSE_KM_HUK_GEN_STATE_LOW_V << EFUSE_KM_HUK_GEN_STATE_LOW_S)
-#define EFUSE_KM_HUK_GEN_STATE_LOW_V  0x0000003FU
-#define EFUSE_KM_HUK_GEN_STATE_LOW_S  26
+#define EFUSE_HUK_GEN_STATE    0x0000001FU
+#define EFUSE_HUK_GEN_STATE_M  (EFUSE_HUK_GEN_STATE_V << EFUSE_HUK_GEN_STATE_S)
+#define EFUSE_HUK_GEN_STATE_V  0x0000001FU
+#define EFUSE_HUK_GEN_STATE_S  26
+/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7 : RO; bitpos: [31]; default: 0;
+ *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+ *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+ *  - this feature is disabled.
+ */
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7    (BIT(31))
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_M  (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_S)
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_V  0x00000001U
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_S  31
 
 /** EFUSE_RD_REPEAT_DATA1_REG register
- *  BLOCK0 data register 2.
+ *  Represents rd_repeat_data
  */
 #define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
-/** EFUSE_KM_HUK_GEN_STATE_HIGH : RO; bitpos: [2:0]; default: 0;
- *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
- *  of 1 is valid.
- */
-#define EFUSE_KM_HUK_GEN_STATE_HIGH    0x00000007U
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_M  (EFUSE_KM_HUK_GEN_STATE_HIGH_V << EFUSE_KM_HUK_GEN_STATE_HIGH_S)
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_V  0x00000007U
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_S  0
-/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [4:3]; default: 0;
- *  Set bits to control key manager random number switch cycle. 0: control by register.
- *  1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.
- */
-#define EFUSE_KM_RND_SWITCH_CYCLE    0x00000003U
+/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10 : RO; bitpos: [2:0]; default: 0;
+ *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+ *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+ *  - this feature is disabled.
+ */
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10    0x00000007U
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_M  (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_S)
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_V  0x00000007U
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_S  0
+/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11 : RO; bitpos: [3]; default: 0;
+ *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+ *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+ *  - this feature is disabled.
+ */
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11    (BIT(3))
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_M  (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_S)
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_V  0x00000001U
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_S  3
+/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [4]; default: 0;
+ *  Set the bits to control key manager random number switch cycle. 0: control by
+ *  register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
+ */
+#define EFUSE_KM_RND_SWITCH_CYCLE    (BIT(4))
 #define EFUSE_KM_RND_SWITCH_CYCLE_M  (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S)
-#define EFUSE_KM_RND_SWITCH_CYCLE_V  0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_S  3
+#define EFUSE_KM_RND_SWITCH_CYCLE_V  0x00000001U
+#define EFUSE_KM_RND_SWITCH_CYCLE_S  4
 /** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [8:5]; default: 0;
- *  Set each bit to control whether corresponding key can only be deployed once. 1 is
- *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+ *  EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field:
+ *  {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to
+ *  control whether corresponding key can only be deployed once. 1 is true, 0 is false.
+ *  bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
  */
 #define EFUSE_KM_DEPLOY_ONLY_ONCE    0x0000000FU
 #define EFUSE_KM_DEPLOY_ONLY_ONCE_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S)
 #define EFUSE_KM_DEPLOY_ONLY_ONCE_V  0x0000000FU
 #define EFUSE_KM_DEPLOY_ONLY_ONCE_S  5
 /** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [12:9]; default: 0;
- *  Set each bit to control whether corresponding key must come from key manager.. 1 is
- *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+ *  EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form
+ *  one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H,
+ *  EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether
+ *  corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda,
+ *  bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
  */
 #define EFUSE_FORCE_USE_KEY_MANAGER_KEY    0x0000000FU
 #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S)
@@ -336,69 +347,74 @@ extern "C" {
 #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S)
 #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V  0x00000001U
 #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S  13
-/** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [14]; default: 0;
- *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
- */
-#define EFUSE_XTS_KEY_LENGTH_256    (BIT(14))
-#define EFUSE_XTS_KEY_LENGTH_256_M  (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S)
-#define EFUSE_XTS_KEY_LENGTH_256_V  0x00000001U
-#define EFUSE_XTS_KEY_LENGTH_256_S  14
-/** EFUSE_RD_RESERVE_0_79 : RW; bitpos: [15]; default: 0;
+/** EFUSE_KM_XTS_KEY_LENGTH_256 : RO; bitpos: [14]; default: 0;
+ *  Set this bit to config flash encryption xts-512 key, else use xts-256 key when
+ *  using the key manager
+ */
+#define EFUSE_KM_XTS_KEY_LENGTH_256    (BIT(14))
+#define EFUSE_KM_XTS_KEY_LENGTH_256_M  (EFUSE_KM_XTS_KEY_LENGTH_256_V << EFUSE_KM_XTS_KEY_LENGTH_256_S)
+#define EFUSE_KM_XTS_KEY_LENGTH_256_V  0x00000001U
+#define EFUSE_KM_XTS_KEY_LENGTH_256_S  14
+/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [15]; default: 0;
+ *  Set this bit to permanently turn on ECC const-time mode.
+ */
+#define EFUSE_ECC_FORCE_CONST_TIME    (BIT(15))
+#define EFUSE_ECC_FORCE_CONST_TIME_M  (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S)
+#define EFUSE_ECC_FORCE_CONST_TIME_V  0x00000001U
+#define EFUSE_ECC_FORCE_CONST_TIME_S  15
+/** EFUSE_RD_RESERVE_0_80 : RW; bitpos: [16]; default: 0;
  *  Reserved, it was created by set_missed_fields_in_regs func
  */
-#define EFUSE_RD_RESERVE_0_79    (BIT(15))
-#define EFUSE_RD_RESERVE_0_79_M  (EFUSE_RD_RESERVE_0_79_V << EFUSE_RD_RESERVE_0_79_S)
-#define EFUSE_RD_RESERVE_0_79_V  0x00000001U
-#define EFUSE_RD_RESERVE_0_79_S  15
-/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
- *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
- *  selected. 0: not selected.
+#define EFUSE_RD_RESERVE_0_80    (BIT(16))
+#define EFUSE_RD_RESERVE_0_80_M  (EFUSE_RD_RESERVE_0_80_V << EFUSE_RD_RESERVE_0_80_S)
+#define EFUSE_RD_RESERVE_0_80_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_80_S  16
+/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17]; default: 0;
+ *  Select lp wdt timeout threshold at startup = initial timeout value * (2 ^
+ *  (EFUSE_WDT_DELAY_SEL + 1))
  */
-#define EFUSE_WDT_DELAY_SEL    0x00000003U
+#define EFUSE_WDT_DELAY_SEL    (BIT(17))
 #define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
-#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_S  16
+#define EFUSE_WDT_DELAY_SEL_V  0x00000001U
+#define EFUSE_WDT_DELAY_SEL_S  17
 /** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
- *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
- *  1: enabled. Even number of 1: disabled.
+ *  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
+ *  number of 1: disable.
  */
 #define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
 #define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
 #define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
 #define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
 /** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
- *  Represents whether revoking first secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
+ *  Set this bit to enable revoking first secure boot key.
  */
 #define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
 /** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
- *  Represents whether revoking second secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
+ *  Set this bit to enable revoking second secure boot key.
  */
 #define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
 /** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
- *  Represents whether revoking third secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
+ *  Set this bit to enable revoking third secure boot key.
  */
 #define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
 /** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
- *  Represents the purpose of Key0.
+ *  Purpose of Key0.
  */
 #define EFUSE_KEY_PURPOSE_0    0x0000000FU
 #define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
 #define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
 #define EFUSE_KEY_PURPOSE_0_S  24
 /** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
- *  Represents the purpose of Key1.
+ *  Purpose of Key1.
  */
 #define EFUSE_KEY_PURPOSE_1    0x0000000FU
 #define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
@@ -406,97 +422,102 @@ extern "C" {
 #define EFUSE_KEY_PURPOSE_1_S  28
 
 /** EFUSE_RD_REPEAT_DATA2_REG register
- *  BLOCK0 data register 3.
+ *  Represents rd_repeat_data
  */
 #define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
 /** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
- *  Represents the purpose of Key2.
+ *  Purpose of Key2.
  */
 #define EFUSE_KEY_PURPOSE_2    0x0000000FU
 #define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
 #define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
 #define EFUSE_KEY_PURPOSE_2_S  0
 /** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
- *  Represents the purpose of Key3.
+ *  Purpose of Key3.
  */
 #define EFUSE_KEY_PURPOSE_3    0x0000000FU
 #define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
 #define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
 #define EFUSE_KEY_PURPOSE_3_S  4
 /** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
- *  Represents the purpose of Key4.
+ *  Purpose of Key4.
  */
 #define EFUSE_KEY_PURPOSE_4    0x0000000FU
 #define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
 #define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
 #define EFUSE_KEY_PURPOSE_4_S  8
 /** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
- *  Represents the purpose of Key5.
+ *  Purpose of Key5.
  */
 #define EFUSE_KEY_PURPOSE_5    0x0000000FU
 #define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
 #define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
 #define EFUSE_KEY_PURPOSE_5_S  12
 /** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
- *  Represents the spa secure level by configuring the clock random divide mode.
+ *  Configures the clock random divide mode to determine the dpa secure level
  */
 #define EFUSE_SEC_DPA_LEVEL    0x00000003U
 #define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
 #define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
 #define EFUSE_SEC_DPA_LEVEL_S  16
-/** EFUSE_ECDSA_ENABLE_SOFT_K : RO; bitpos: [18]; default: 0;
- *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
- *  0: not force used.
- */
-#define EFUSE_ECDSA_ENABLE_SOFT_K    (BIT(18))
-#define EFUSE_ECDSA_ENABLE_SOFT_K_M  (EFUSE_ECDSA_ENABLE_SOFT_K_V << EFUSE_ECDSA_ENABLE_SOFT_K_S)
-#define EFUSE_ECDSA_ENABLE_SOFT_K_V  0x00000001U
-#define EFUSE_ECDSA_ENABLE_SOFT_K_S  18
-/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1;
- *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
- */
-#define EFUSE_CRYPT_DPA_ENABLE    (BIT(19))
-#define EFUSE_CRYPT_DPA_ENABLE_M  (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S)
-#define EFUSE_CRYPT_DPA_ENABLE_V  0x00000001U
-#define EFUSE_CRYPT_DPA_ENABLE_S  19
+/** EFUSE_RD_RESERVE_0_114 : RW; bitpos: [18]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_114    (BIT(18))
+#define EFUSE_RD_RESERVE_0_114_M  (EFUSE_RD_RESERVE_0_114_V << EFUSE_RD_RESERVE_0_114_S)
+#define EFUSE_RD_RESERVE_0_114_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_114_S  18
+/** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [19]; default: 0;
+ *  Sets this bit to enable xts clock anti-dpa attack function.
+ */
+#define EFUSE_XTS_DPA_CLK_ENABLE    (BIT(19))
+#define EFUSE_XTS_DPA_CLK_ENABLE_M  (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S)
+#define EFUSE_XTS_DPA_CLK_ENABLE_V  0x00000001U
+#define EFUSE_XTS_DPA_CLK_ENABLE_S  19
 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
- *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
+ *  Set this bit to enable secure boot.
  */
 #define EFUSE_SECURE_BOOT_EN    (BIT(20))
 #define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
 #define EFUSE_SECURE_BOOT_EN_V  0x00000001U
 #define EFUSE_SECURE_BOOT_EN_S  20
 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
- *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
- *  enabled. 0: disabled.
+ *  Set this bit to enable revoking aggressive secure boot.
  */
 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
-/** EFUSE_RD_RESERVE_0_118 : RW; bitpos: [22]; default: 0;
+/** EFUSE_KM_DEPLOY_ONLY_ONCE_H : RO; bitpos: [22]; default: 0;
+ *  EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field:
+ *  {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to
+ *  control whether corresponding key can only be deployed once. 1 is true, 0 is false.
+ *  bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
+ */
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_H    (BIT(22))
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_H_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_H_V << EFUSE_KM_DEPLOY_ONLY_ONCE_H_S)
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_H_V  0x00000001U
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_H_S  22
+/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_H : RO; bitpos: [23]; default: 0;
+ *  EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form
+ *  one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H,
+ *  EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether
+ *  corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda,
+ *  bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
+ */
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H    (BIT(23))
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_S)
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_V  0x00000001U
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_S  23
+/** EFUSE_RD_RESERVE_0_120 : RW; bitpos: [25:24]; default: 0;
  *  Reserved, it was created by set_missed_fields_in_regs func
  */
-#define EFUSE_RD_RESERVE_0_118    (BIT(22))
-#define EFUSE_RD_RESERVE_0_118_M  (EFUSE_RD_RESERVE_0_118_V << EFUSE_RD_RESERVE_0_118_S)
-#define EFUSE_RD_RESERVE_0_118_V  0x00000001U
-#define EFUSE_RD_RESERVE_0_118_S  22
-/** EFUSE_FLASH_TYPE : RO; bitpos: [23]; default: 0;
- *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
- */
-#define EFUSE_FLASH_TYPE    (BIT(23))
-#define EFUSE_FLASH_TYPE_M  (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S)
-#define EFUSE_FLASH_TYPE_V  0x00000001U
-#define EFUSE_FLASH_TYPE_S  23
-/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [25:24]; default: 0;
- *  Set flash page size.
- */
-#define EFUSE_FLASH_PAGE_SIZE    0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_M  (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S)
-#define EFUSE_FLASH_PAGE_SIZE_V  0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_S  24
+#define EFUSE_RD_RESERVE_0_120    0x00000003U
+#define EFUSE_RD_RESERVE_0_120_M  (EFUSE_RD_RESERVE_0_120_V << EFUSE_RD_RESERVE_0_120_S)
+#define EFUSE_RD_RESERVE_0_120_V  0x00000003U
+#define EFUSE_RD_RESERVE_0_120_S  24
 /** EFUSE_FLASH_ECC_EN : RO; bitpos: [26]; default: 0;
- *  Set this bit to enable ecc for flash boot.
+ *  Set this bit to enable ECC for flash boot.
  */
 #define EFUSE_FLASH_ECC_EN    (BIT(26))
 #define EFUSE_FLASH_ECC_EN_M  (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S)
@@ -510,9 +531,9 @@ extern "C" {
 #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V  0x00000001U
 #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S  27
 /** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
- *  Represents the flash waiting time after power-up, in unit of ms. When the value
- *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
- *  is 2 times the programmed value.
+ *  Configures flash waiting time after power-up, in unit of ms. When the value less
+ *  than 15, the waiting time is the configurable value. Otherwise, the waiting time is
+ *  30.
  */
 #define EFUSE_FLASH_TPUW    0x0000000FU
 #define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
@@ -520,178 +541,217 @@ extern "C" {
 #define EFUSE_FLASH_TPUW_S  28
 
 /** EFUSE_RD_REPEAT_DATA3_REG register
- *  BLOCK0 data register 4.
+ *  Represents rd_repeat_data
  */
 #define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
 /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
- *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
+ *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7).
  */
 #define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
 #define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
 #define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
 #define EFUSE_DIS_DOWNLOAD_MODE_S  0
 /** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
- *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
+ *  Set this bit to disable direct boot mode
  */
 #define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
 #define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
 #define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
 #define EFUSE_DIS_DIRECT_BOOT_S  1
 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
- *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
- *  0: enabled.
+ *  Set this bit to disable USB-Serial-JTAG print during rom boot.
  */
 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
 /** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0;
- *  TBD
+ *  set this bit to lock the key manager key after deploy
  */
 #define EFUSE_LOCK_KM_KEY    (BIT(3))
 #define EFUSE_LOCK_KM_KEY_M  (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S)
 #define EFUSE_LOCK_KM_KEY_V  0x00000001U
 #define EFUSE_LOCK_KM_KEY_S  3
 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
- *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
- *  disabled. 0: enabled.
+ *  Set this bit to disable the USB-Serial-JTAG download function.
  */
 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
 /** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
- *  Represents whether security download is enabled or disabled. 1: enabled. 0:
- *  disabled.
+ *  Set this bit to enable security download mode.
  */
 #define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
 /** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
- *  Represents the type of UART printing. 00: force enable printing. 01: enable
- *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
- *  at high level. 11: force disable printing.
+ *  Set the type of UART printing, 00: force enable printing, 01: enable printing when
+ *  GPIO8 is reset at low level, 10: enable printing when GPIO8 is reset at high level,
+ *  11: force disable printing
  */
 #define EFUSE_UART_PRINT_CONTROL    0x00000003U
 #define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
 #define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
 #define EFUSE_UART_PRINT_CONTROL_S  6
 /** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0;
- *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
- *  forced. 0:not forced.
+ *  Set this bit to force ROM code to send a resume command during SPI boot.
  */
 #define EFUSE_FORCE_SEND_RESUME    (BIT(8))
 #define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
 #define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
 #define EFUSE_FORCE_SEND_RESUME_S  8
 /** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0;
- *  Represents the version used by ESP-IDF anti-rollback feature.
+ *  Secure version used by ESP-IDF anti-rollback feature.
  */
 #define EFUSE_SECURE_VERSION    0x0000FFFFU
 #define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
 #define EFUSE_SECURE_VERSION_V  0x0000FFFFU
 #define EFUSE_SECURE_VERSION_S  9
 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0;
- *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
- *  enabled. 1: disabled. 0: enabled.
+ *  Represents whether secure boot do fast verification on wake is disabled. 0: enabled
+ *  1: disabled
  */
 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(25))
 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  25
 /** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0;
- *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
- *  enabled. 0:disabled.
+ *  Set bits to enable hysteresis function of PAD0~27
  */
 #define EFUSE_HYS_EN_PAD    (BIT(26))
 #define EFUSE_HYS_EN_PAD_M  (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S)
 #define EFUSE_HYS_EN_PAD_V  0x00000001U
 #define EFUSE_HYS_EN_PAD_S  26
-/** EFUSE_DCDC_VSET : RO; bitpos: [31:27]; default: 0;
- *  Set the dcdc voltage default.
- */
-#define EFUSE_DCDC_VSET    0x0000001FU
-#define EFUSE_DCDC_VSET_M  (EFUSE_DCDC_VSET_V << EFUSE_DCDC_VSET_S)
-#define EFUSE_DCDC_VSET_V  0x0000001FU
-#define EFUSE_DCDC_VSET_S  27
+/** EFUSE_KEY_PURPOSE_0_H : RO; bitpos: [27]; default: 0;
+ *  Purpose of Key0. The 5-th bit.
+ */
+#define EFUSE_KEY_PURPOSE_0_H    (BIT(27))
+#define EFUSE_KEY_PURPOSE_0_H_M  (EFUSE_KEY_PURPOSE_0_H_V << EFUSE_KEY_PURPOSE_0_H_S)
+#define EFUSE_KEY_PURPOSE_0_H_V  0x00000001U
+#define EFUSE_KEY_PURPOSE_0_H_S  27
+/** EFUSE_KEY_PURPOSE_1_H : RO; bitpos: [28]; default: 0;
+ *  Purpose of Key1. The 5-th bit.
+ */
+#define EFUSE_KEY_PURPOSE_1_H    (BIT(28))
+#define EFUSE_KEY_PURPOSE_1_H_M  (EFUSE_KEY_PURPOSE_1_H_V << EFUSE_KEY_PURPOSE_1_H_S)
+#define EFUSE_KEY_PURPOSE_1_H_V  0x00000001U
+#define EFUSE_KEY_PURPOSE_1_H_S  28
+/** EFUSE_KEY_PURPOSE_2_H : RO; bitpos: [29]; default: 0;
+ *  Purpose of Key2. The 5-th bit.
+ */
+#define EFUSE_KEY_PURPOSE_2_H    (BIT(29))
+#define EFUSE_KEY_PURPOSE_2_H_M  (EFUSE_KEY_PURPOSE_2_H_V << EFUSE_KEY_PURPOSE_2_H_S)
+#define EFUSE_KEY_PURPOSE_2_H_V  0x00000001U
+#define EFUSE_KEY_PURPOSE_2_H_S  29
+/** EFUSE_KEY_PURPOSE_3_H : RO; bitpos: [30]; default: 0;
+ *  Purpose of Key3. The 5-th bit.
+ */
+#define EFUSE_KEY_PURPOSE_3_H    (BIT(30))
+#define EFUSE_KEY_PURPOSE_3_H_M  (EFUSE_KEY_PURPOSE_3_H_V << EFUSE_KEY_PURPOSE_3_H_S)
+#define EFUSE_KEY_PURPOSE_3_H_V  0x00000001U
+#define EFUSE_KEY_PURPOSE_3_H_S  30
+/** EFUSE_KEY_PURPOSE_4_H : RO; bitpos: [31]; default: 0;
+ *  Purpose of Key4. The 5-th bit.
+ */
+#define EFUSE_KEY_PURPOSE_4_H    (BIT(31))
+#define EFUSE_KEY_PURPOSE_4_H_M  (EFUSE_KEY_PURPOSE_4_H_V << EFUSE_KEY_PURPOSE_4_H_S)
+#define EFUSE_KEY_PURPOSE_4_H_V  0x00000001U
+#define EFUSE_KEY_PURPOSE_4_H_S  31
 
 /** EFUSE_RD_REPEAT_DATA4_REG register
- *  BLOCK0 data register 5.
+ *  Represents rd_repeat_data
  */
 #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
 /** EFUSE_PXA0_TIEH_SEL_0 : RO; bitpos: [1:0]; default: 0;
- *  TBD
+ *  Output LDO VO0 tieh source select. 0: 1'b1 1: sdmmc1 2: reg 3:sdmmc0
  */
 #define EFUSE_PXA0_TIEH_SEL_0    0x00000003U
 #define EFUSE_PXA0_TIEH_SEL_0_M  (EFUSE_PXA0_TIEH_SEL_0_V << EFUSE_PXA0_TIEH_SEL_0_S)
 #define EFUSE_PXA0_TIEH_SEL_0_V  0x00000003U
 #define EFUSE_PXA0_TIEH_SEL_0_S  0
-/** EFUSE_PXA0_TIEH_SEL_1 : RO; bitpos: [3:2]; default: 0;
- *  TBD.
- */
-#define EFUSE_PXA0_TIEH_SEL_1    0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_1_M  (EFUSE_PXA0_TIEH_SEL_1_V << EFUSE_PXA0_TIEH_SEL_1_S)
-#define EFUSE_PXA0_TIEH_SEL_1_V  0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_1_S  2
-/** EFUSE_PXA0_TIEH_SEL_2 : RO; bitpos: [5:4]; default: 0;
- *  TBD.
- */
-#define EFUSE_PXA0_TIEH_SEL_2    0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_2_M  (EFUSE_PXA0_TIEH_SEL_2_V << EFUSE_PXA0_TIEH_SEL_2_S)
-#define EFUSE_PXA0_TIEH_SEL_2_V  0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_2_S  4
-/** EFUSE_PXA0_TIEH_SEL_3 : RO; bitpos: [7:6]; default: 0;
- *  TBD.
- */
-#define EFUSE_PXA0_TIEH_SEL_3    0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_3_M  (EFUSE_PXA0_TIEH_SEL_3_V << EFUSE_PXA0_TIEH_SEL_3_S)
-#define EFUSE_PXA0_TIEH_SEL_3_V  0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_3_S  6
+/** EFUSE_PVT_GLITCH_EN : RO; bitpos: [2]; default: 0;
+ *  Represents whether to enable PVT power glitch monitor function.\\1:Enable.
+ *  \\0:Disable
+ */
+#define EFUSE_PVT_GLITCH_EN    (BIT(2))
+#define EFUSE_PVT_GLITCH_EN_M  (EFUSE_PVT_GLITCH_EN_V << EFUSE_PVT_GLITCH_EN_S)
+#define EFUSE_PVT_GLITCH_EN_V  0x00000001U
+#define EFUSE_PVT_GLITCH_EN_S  2
+/** EFUSE_RD_RESERVE_0_163 : RW; bitpos: [3]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_163    (BIT(3))
+#define EFUSE_RD_RESERVE_0_163_M  (EFUSE_RD_RESERVE_0_163_V << EFUSE_RD_RESERVE_0_163_S)
+#define EFUSE_RD_RESERVE_0_163_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_163_S  3
+/** EFUSE_KEY_PURPOSE_5_H : RO; bitpos: [4]; default: 0;
+ *  Purpose of Key5. The 5-th bit.
+ */
+#define EFUSE_KEY_PURPOSE_5_H    (BIT(4))
+#define EFUSE_KEY_PURPOSE_5_H_M  (EFUSE_KEY_PURPOSE_5_H_V << EFUSE_KEY_PURPOSE_5_H_S)
+#define EFUSE_KEY_PURPOSE_5_H_V  0x00000001U
+#define EFUSE_KEY_PURPOSE_5_H_S  4
+/** EFUSE_RD_RESERVE_0_165 : RW; bitpos: [6:5]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_165    0x00000003U
+#define EFUSE_RD_RESERVE_0_165_M  (EFUSE_RD_RESERVE_0_165_V << EFUSE_RD_RESERVE_0_165_S)
+#define EFUSE_RD_RESERVE_0_165_V  0x00000003U
+#define EFUSE_RD_RESERVE_0_165_S  5
+/** EFUSE_KM_DISABLE_DEPLOY_MODE_H : RO; bitpos: [7]; default: 0;
+ *  EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one
+ *  field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set
+ *  each bit to control whether corresponding key's deploy mode of new value deployment
+ *  is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds,
+ *  bit4:psram
+ */
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_H    (BIT(7))
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_H_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_H_V << EFUSE_KM_DISABLE_DEPLOY_MODE_H_S)
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_H_V  0x00000001U
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_H_S  7
 /** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [11:8]; default: 0;
- *  TBD.
+ *  EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one
+ *  field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set
+ *  each bit to control whether corresponding key's deploy mode of new value deployment
+ *  is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds,
+ *  bit4:psram
  */
 #define EFUSE_KM_DISABLE_DEPLOY_MODE    0x0000000FU
 #define EFUSE_KM_DISABLE_DEPLOY_MODE_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S)
 #define EFUSE_KM_DISABLE_DEPLOY_MODE_V  0x0000000FU
 #define EFUSE_KM_DISABLE_DEPLOY_MODE_S  8
-/** EFUSE_USB_DEVICE_DREFL : RO; bitpos: [13:12]; default: 0;
- *  Represents the usb device single-end input low threshold; 0.8 V to 1.04 V with step
- *  of 80 mV
- */
-#define EFUSE_USB_DEVICE_DREFL    0x00000003U
-#define EFUSE_USB_DEVICE_DREFL_M  (EFUSE_USB_DEVICE_DREFL_V << EFUSE_USB_DEVICE_DREFL_S)
-#define EFUSE_USB_DEVICE_DREFL_V  0x00000003U
-#define EFUSE_USB_DEVICE_DREFL_S  12
-/** EFUSE_USB_OTG11_DREFL : RO; bitpos: [15:14]; default: 0;
- *  Represents the usb otg11 single-end input low threshold; 0.8 V to 1.04 V with step
- *  of 80 mV
- */
-#define EFUSE_USB_OTG11_DREFL    0x00000003U
-#define EFUSE_USB_OTG11_DREFL_M  (EFUSE_USB_OTG11_DREFL_V << EFUSE_USB_OTG11_DREFL_S)
-#define EFUSE_USB_OTG11_DREFL_V  0x00000003U
-#define EFUSE_USB_OTG11_DREFL_S  14
-/** EFUSE_RD_RESERVE_0_176 : RW; bitpos: [17:16]; default: 0;
+/** EFUSE_RD_RESERVE_0_172 : RW; bitpos: [15:12]; default: 0;
  *  Reserved, it was created by set_missed_fields_in_regs func
  */
-#define EFUSE_RD_RESERVE_0_176    0x00000003U
-#define EFUSE_RD_RESERVE_0_176_M  (EFUSE_RD_RESERVE_0_176_V << EFUSE_RD_RESERVE_0_176_S)
-#define EFUSE_RD_RESERVE_0_176_V  0x00000003U
-#define EFUSE_RD_RESERVE_0_176_S  16
+#define EFUSE_RD_RESERVE_0_172    0x0000000FU
+#define EFUSE_RD_RESERVE_0_172_M  (EFUSE_RD_RESERVE_0_172_V << EFUSE_RD_RESERVE_0_172_S)
+#define EFUSE_RD_RESERVE_0_172_V  0x0000000FU
+#define EFUSE_RD_RESERVE_0_172_S  12
+/** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [17:16]; default: 0;
+ *  Sets this bit to control the xts pseudo-round anti-dpa attack function. 0:
+ *  controlled by register. 1-3: the higher the value is, the more pseudo-rounds are
+ *  inserted to the xts-aes calculation
+ */
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL    0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M  (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S)
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V  0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S  16
 /** EFUSE_HP_PWR_SRC_SEL : RO; bitpos: [18]; default: 0;
- *  HP system power source select. 0:LDO. 1: DCDC.
+ *  HP system power source select. 0:LDO  1: DCDC
  */
 #define EFUSE_HP_PWR_SRC_SEL    (BIT(18))
 #define EFUSE_HP_PWR_SRC_SEL_M  (EFUSE_HP_PWR_SRC_SEL_V << EFUSE_HP_PWR_SRC_SEL_S)
 #define EFUSE_HP_PWR_SRC_SEL_V  0x00000001U
 #define EFUSE_HP_PWR_SRC_SEL_S  18
-/** EFUSE_DCDC_VSET_EN : RO; bitpos: [19]; default: 0;
- *  Select dcdc vset use efuse_dcdc_vset.
+/** EFUSE_SECURE_BOOT_SHA384_EN : RO; bitpos: [19]; default: 0;
+ *  Represents whether secure boot using SHA-384 is enabled. 0: disable 1: enable
  */
-#define EFUSE_DCDC_VSET_EN    (BIT(19))
-#define EFUSE_DCDC_VSET_EN_M  (EFUSE_DCDC_VSET_EN_V << EFUSE_DCDC_VSET_EN_S)
-#define EFUSE_DCDC_VSET_EN_V  0x00000001U
-#define EFUSE_DCDC_VSET_EN_S  19
+#define EFUSE_SECURE_BOOT_SHA384_EN    (BIT(19))
+#define EFUSE_SECURE_BOOT_SHA384_EN_M  (EFUSE_SECURE_BOOT_SHA384_EN_V << EFUSE_SECURE_BOOT_SHA384_EN_S)
+#define EFUSE_SECURE_BOOT_SHA384_EN_V  0x00000001U
+#define EFUSE_SECURE_BOOT_SHA384_EN_S  19
 /** EFUSE_DIS_WDT : RO; bitpos: [20]; default: 0;
  *  Set this bit to disable watch dog.
  */
@@ -700,26 +760,33 @@ extern "C" {
 #define EFUSE_DIS_WDT_V  0x00000001U
 #define EFUSE_DIS_WDT_S  20
 /** EFUSE_DIS_SWD : RO; bitpos: [21]; default: 0;
- *  Set this bit to disable super-watchdog.
+ *  Set bit to disable super-watchdog
  */
 #define EFUSE_DIS_SWD    (BIT(21))
 #define EFUSE_DIS_SWD_M  (EFUSE_DIS_SWD_V << EFUSE_DIS_SWD_S)
 #define EFUSE_DIS_SWD_V  0x00000001U
 #define EFUSE_DIS_SWD_S  21
-/** EFUSE_RD_RESERVE_0_182 : RW; bitpos: [31:22]; default: 0;
+/** EFUSE_PVT_GLITCH_MODE : RO; bitpos: [23:22]; default: 0;
+ *  Use to configure glitch mode
+ */
+#define EFUSE_PVT_GLITCH_MODE    0x00000003U
+#define EFUSE_PVT_GLITCH_MODE_M  (EFUSE_PVT_GLITCH_MODE_V << EFUSE_PVT_GLITCH_MODE_S)
+#define EFUSE_PVT_GLITCH_MODE_V  0x00000003U
+#define EFUSE_PVT_GLITCH_MODE_S  22
+/** EFUSE_RD_RESERVE_0_184 : RW; bitpos: [31:24]; default: 0;
  *  Reserved, it was created by set_missed_fields_in_regs func
  */
-#define EFUSE_RD_RESERVE_0_182    0x000003FFU
-#define EFUSE_RD_RESERVE_0_182_M  (EFUSE_RD_RESERVE_0_182_V << EFUSE_RD_RESERVE_0_182_S)
-#define EFUSE_RD_RESERVE_0_182_V  0x000003FFU
-#define EFUSE_RD_RESERVE_0_182_S  22
+#define EFUSE_RD_RESERVE_0_184    0x000000FFU
+#define EFUSE_RD_RESERVE_0_184_M  (EFUSE_RD_RESERVE_0_184_V << EFUSE_RD_RESERVE_0_184_S)
+#define EFUSE_RD_RESERVE_0_184_V  0x000000FFU
+#define EFUSE_RD_RESERVE_0_184_S  24
 
 /** EFUSE_RD_MAC_SYS_0_REG register
- *  BLOCK1 data register $n.
+ *  Represents rd_mac_sys
  */
 #define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
 /** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the low 32 bits of MAC address.
+ *  Represents MAC address. Low 32-bit.
  */
 #define EFUSE_MAC_0    0xFFFFFFFFU
 #define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
@@ -727,26 +794,26 @@ extern "C" {
 #define EFUSE_MAC_0_S  0
 
 /** EFUSE_RD_MAC_SYS_1_REG register
- *  BLOCK1 data register $n.
+ *  Represents rd_mac_sys
  */
 #define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
 /** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
- *  Stores the high 16 bits of MAC address.
+ *  Represents MAC address. High 16-bit.
  */
 #define EFUSE_MAC_1    0x0000FFFFU
 #define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
 #define EFUSE_MAC_1_V  0x0000FFFFU
 #define EFUSE_MAC_1_S  0
-/** EFUSE_RESERVED_1_16 : RO; bitpos: [31:16]; default: 0;
- *  Stores the extended bits of MAC address.
+/** EFUSE_RD_RESERVE_1_48 : RW; bitpos: [31:16]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
  */
-#define EFUSE_RESERVED_1_16    0x0000FFFFU
-#define EFUSE_RESERVED_1_16_M  (EFUSE_RESERVED_1_16_V << EFUSE_RESERVED_1_16_S)
-#define EFUSE_RESERVED_1_16_V  0x0000FFFFU
-#define EFUSE_RESERVED_1_16_S  16
+#define EFUSE_RD_RESERVE_1_48    0x0000FFFFU
+#define EFUSE_RD_RESERVE_1_48_M  (EFUSE_RD_RESERVE_1_48_V << EFUSE_RD_RESERVE_1_48_S)
+#define EFUSE_RD_RESERVE_1_48_V  0x0000FFFFU
+#define EFUSE_RD_RESERVE_1_48_S  16
 
 /** EFUSE_RD_MAC_SYS_2_REG register
- *  BLOCK1 data register $n.
+ *  Represents rd_mac_sys
  */
 #define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
 /** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0;
@@ -842,7 +909,7 @@ extern "C" {
 #define EFUSE_LDO_VO2_DREF_S  28
 
 /** EFUSE_RD_MAC_SYS_3_REG register
- *  BLOCK1 data register $n.
+ *  Represents rd_mac_sys
  */
 #define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
 /** EFUSE_LDO_VO1_MUL : R; bitpos: [2:0]; default: 0;
@@ -889,7 +956,7 @@ extern "C" {
 #define EFUSE_LDO_VO4_K_S  26
 
 /** EFUSE_RD_MAC_SYS_4_REG register
- *  BLOCK1 data register $n.
+ *  Represents rd_mac_sys
  */
 #define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
 /** EFUSE_LDO_VO4_K_1 : R; bitpos: [1:0]; default: 0;
@@ -934,13 +1001,13 @@ extern "C" {
 #define EFUSE_ACTIVE_LP_DBIAS_M  (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S)
 #define EFUSE_ACTIVE_LP_DBIAS_V  0x0000000FU
 #define EFUSE_ACTIVE_LP_DBIAS_S  20
-/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [27:24]; default: 0;
- *  LSLP HP DBIAS of fixed voltage
+/** EFUSE_RESERVED_1_152 : R; bitpos: [27:24]; default: 0;
+ *  reserved
  */
-#define EFUSE_LSLP_HP_DBIAS    0x0000000FU
-#define EFUSE_LSLP_HP_DBIAS_M  (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S)
-#define EFUSE_LSLP_HP_DBIAS_V  0x0000000FU
-#define EFUSE_LSLP_HP_DBIAS_S  24
+#define EFUSE_RESERVED_1_152    0x0000000FU
+#define EFUSE_RESERVED_1_152_M  (EFUSE_RESERVED_1_152_V << EFUSE_RESERVED_1_152_S)
+#define EFUSE_RESERVED_1_152_V  0x0000000FU
+#define EFUSE_RESERVED_1_152_S  24
 /** EFUSE_DSLP_DBG : R; bitpos: [31:28]; default: 0;
  *  DSLP BDG of fixed voltage
  */
@@ -950,7 +1017,7 @@ extern "C" {
 #define EFUSE_DSLP_DBG_S  28
 
 /** EFUSE_RD_MAC_SYS_5_REG register
- *  BLOCK1 data register $n.
+ *  Represents rd_mac_sys
  */
 #define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
 /** EFUSE_DSLP_LP_DBIAS : R; bitpos: [4:0]; default: 0;
@@ -967,16 +1034,44 @@ extern "C" {
 #define EFUSE_LP_DCDC_DBIAS_VOL_GAP_M  (EFUSE_LP_DCDC_DBIAS_VOL_GAP_V << EFUSE_LP_DCDC_DBIAS_VOL_GAP_S)
 #define EFUSE_LP_DCDC_DBIAS_VOL_GAP_V  0x0000001FU
 #define EFUSE_LP_DCDC_DBIAS_VOL_GAP_S  5
-/** EFUSE_RESERVED_1_170 : R; bitpos: [31:10]; default: 0;
+/** EFUSE_RESERVED_1_170 : R; bitpos: [10]; default: 0;
  *  reserved
  */
-#define EFUSE_RESERVED_1_170    0x003FFFFFU
+#define EFUSE_RESERVED_1_170    (BIT(10))
 #define EFUSE_RESERVED_1_170_M  (EFUSE_RESERVED_1_170_V << EFUSE_RESERVED_1_170_S)
-#define EFUSE_RESERVED_1_170_V  0x003FFFFFU
+#define EFUSE_RESERVED_1_170_V  0x00000001U
 #define EFUSE_RESERVED_1_170_S  10
+/** EFUSE_PVT_400M_BIAS : R; bitpos: [15:11]; default: 0;
+ *  PVT_DCM_VSET when the CPU is at 400M
+ */
+#define EFUSE_PVT_400M_BIAS    0x0000001FU
+#define EFUSE_PVT_400M_BIAS_M  (EFUSE_PVT_400M_BIAS_V << EFUSE_PVT_400M_BIAS_S)
+#define EFUSE_PVT_400M_BIAS_V  0x0000001FU
+#define EFUSE_PVT_400M_BIAS_S  11
+/** EFUSE_PVT_40M_BIAS : R; bitpos: [20:16]; default: 0;
+ *  PVT_DCM_VSET corresponding to about 0.9V fixed voltage when the CPU is at 40M
+ */
+#define EFUSE_PVT_40M_BIAS    0x0000001FU
+#define EFUSE_PVT_40M_BIAS_M  (EFUSE_PVT_40M_BIAS_V << EFUSE_PVT_40M_BIAS_S)
+#define EFUSE_PVT_40M_BIAS_V  0x0000001FU
+#define EFUSE_PVT_40M_BIAS_S  16
+/** EFUSE_PVT_100M_BIAS : R; bitpos: [25:21]; default: 0;
+ *  PVT_DCM_VSET corresponding to about 1.0V fixed voltage when the CPU is at 100M
+ */
+#define EFUSE_PVT_100M_BIAS    0x0000001FU
+#define EFUSE_PVT_100M_BIAS_M  (EFUSE_PVT_100M_BIAS_V << EFUSE_PVT_100M_BIAS_S)
+#define EFUSE_PVT_100M_BIAS_V  0x0000001FU
+#define EFUSE_PVT_100M_BIAS_S  21
+/** EFUSE_RESERVED_1_186 : R; bitpos: [31:26]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_186    0x0000003FU
+#define EFUSE_RESERVED_1_186_M  (EFUSE_RESERVED_1_186_V << EFUSE_RESERVED_1_186_S)
+#define EFUSE_RESERVED_1_186_V  0x0000003FU
+#define EFUSE_RESERVED_1_186_S  26
 
 /** EFUSE_RD_SYS_PART1_DATA0_REG register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data0
  */
 #define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
 /** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
@@ -988,7 +1083,7 @@ extern "C" {
 #define EFUSE_OPTIONAL_UNIQUE_ID_S  0
 
 /** EFUSE_RD_SYS_PART1_DATA1_REG register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data1
  */
 #define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
 /** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
@@ -1000,7 +1095,7 @@ extern "C" {
 #define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
 
 /** EFUSE_RD_SYS_PART1_DATA2_REG register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data2
  */
 #define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
 /** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
@@ -1012,7 +1107,7 @@ extern "C" {
 #define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
 
 /** EFUSE_RD_SYS_PART1_DATA3_REG register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data3
  */
 #define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
 /** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
@@ -1024,7 +1119,7 @@ extern "C" {
 #define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
 
 /** EFUSE_RD_SYS_PART1_DATA4_REG register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data4
  */
 #define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
 /** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [9:0]; default: 0;
@@ -1057,7 +1152,7 @@ extern "C" {
 #define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S  30
 
 /** EFUSE_RD_SYS_PART1_DATA5_REG register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data5
  */
 #define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
 /** EFUSE_ADC1_AVE_INITCODE_ATTEN3_1 : R; bitpos: [7:0]; default: 0;
@@ -1090,7 +1185,7 @@ extern "C" {
 #define EFUSE_ADC2_AVE_INITCODE_ATTEN2_S  28
 
 /** EFUSE_RD_SYS_PART1_DATA6_REG register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data6
  */
 #define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
 /** EFUSE_ADC2_AVE_INITCODE_ATTEN2_1 : R; bitpos: [5:0]; default: 0;
@@ -1123,7 +1218,7 @@ extern "C" {
 #define EFUSE_ADC1_HI_DOUT_ATTEN1_S  26
 
 /** EFUSE_RD_SYS_PART1_DATA7_REG register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data7
  */
 #define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
 /** EFUSE_ADC1_HI_DOUT_ATTEN1_1 : R; bitpos: [3:0]; default: 0;
@@ -1156,11 +1251,11 @@ extern "C" {
 #define EFUSE_RESERVED_2_248_S  24
 
 /** EFUSE_RD_USR_DATA0_REG register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data0
  */
 #define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
 /** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of BLOCK3 (user).
+ *  Represents the zeroth 32-bit of block3 (user).
  */
 #define EFUSE_USR_DATA0    0xFFFFFFFFU
 #define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
@@ -1168,11 +1263,11 @@ extern "C" {
 #define EFUSE_USR_DATA0_S  0
 
 /** EFUSE_RD_USR_DATA1_REG register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data1
  */
 #define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
 /** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of BLOCK3 (user).
+ *  Represents the zeroth 32-bit of block3 (user).
  */
 #define EFUSE_USR_DATA1    0xFFFFFFFFU
 #define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
@@ -1180,11 +1275,11 @@ extern "C" {
 #define EFUSE_USR_DATA1_S  0
 
 /** EFUSE_RD_USR_DATA2_REG register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data2
  */
 #define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
 /** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of BLOCK3 (user).
+ *  Represents the zeroth 32-bit of block3 (user).
  */
 #define EFUSE_USR_DATA2    0xFFFFFFFFU
 #define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
@@ -1192,11 +1287,11 @@ extern "C" {
 #define EFUSE_USR_DATA2_S  0
 
 /** EFUSE_RD_USR_DATA3_REG register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data3
  */
 #define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
 /** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of BLOCK3 (user).
+ *  Represents the zeroth 32-bit of block3 (user).
  */
 #define EFUSE_USR_DATA3    0xFFFFFFFFU
 #define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
@@ -1204,11 +1299,11 @@ extern "C" {
 #define EFUSE_USR_DATA3_S  0
 
 /** EFUSE_RD_USR_DATA4_REG register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data4
  */
 #define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
 /** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of BLOCK3 (user).
+ *  Represents the zeroth 32-bit of block3 (user).
  */
 #define EFUSE_USR_DATA4    0xFFFFFFFFU
 #define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
@@ -1216,11 +1311,11 @@ extern "C" {
 #define EFUSE_USR_DATA4_S  0
 
 /** EFUSE_RD_USR_DATA5_REG register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data5
  */
 #define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
 /** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of BLOCK3 (user).
+ *  Represents the zeroth 32-bit of block3 (user).
  */
 #define EFUSE_USR_DATA5    0xFFFFFFFFU
 #define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
@@ -1228,7 +1323,7 @@ extern "C" {
 #define EFUSE_USR_DATA5_S  0
 
 /** EFUSE_RD_USR_DATA6_REG register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data6
  */
 #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
 /** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
@@ -1247,7 +1342,7 @@ extern "C" {
 #define EFUSE_CUSTOM_MAC_S  8
 
 /** EFUSE_RD_USR_DATA7_REG register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data7
  */
 #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
 /** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
@@ -1266,11 +1361,11 @@ extern "C" {
 #define EFUSE_RESERVED_3_248_S  24
 
 /** EFUSE_RD_KEY0_DATA0_REG register
- *  Register $n of BLOCK4 (KEY0).
+ *  Represents rd_key0_data0
  */
 #define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
 /** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY0.
+ *  Represents the zeroth 32-bit of key0.
  */
 #define EFUSE_KEY0_DATA0    0xFFFFFFFFU
 #define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
@@ -1278,11 +1373,11 @@ extern "C" {
 #define EFUSE_KEY0_DATA0_S  0
 
 /** EFUSE_RD_KEY0_DATA1_REG register
- *  Register $n of BLOCK4 (KEY0).
+ *  Represents rd_key0_data1
  */
 #define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
 /** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY0.
+ *  Represents the zeroth 32-bit of key0.
  */
 #define EFUSE_KEY0_DATA1    0xFFFFFFFFU
 #define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
@@ -1290,11 +1385,11 @@ extern "C" {
 #define EFUSE_KEY0_DATA1_S  0
 
 /** EFUSE_RD_KEY0_DATA2_REG register
- *  Register $n of BLOCK4 (KEY0).
+ *  Represents rd_key0_data2
  */
 #define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
 /** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY0.
+ *  Represents the zeroth 32-bit of key0.
  */
 #define EFUSE_KEY0_DATA2    0xFFFFFFFFU
 #define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
@@ -1302,11 +1397,11 @@ extern "C" {
 #define EFUSE_KEY0_DATA2_S  0
 
 /** EFUSE_RD_KEY0_DATA3_REG register
- *  Register $n of BLOCK4 (KEY0).
+ *  Represents rd_key0_data3
  */
 #define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
 /** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY0.
+ *  Represents the zeroth 32-bit of key0.
  */
 #define EFUSE_KEY0_DATA3    0xFFFFFFFFU
 #define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
@@ -1314,11 +1409,11 @@ extern "C" {
 #define EFUSE_KEY0_DATA3_S  0
 
 /** EFUSE_RD_KEY0_DATA4_REG register
- *  Register $n of BLOCK4 (KEY0).
+ *  Represents rd_key0_data4
  */
 #define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
 /** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY0.
+ *  Represents the zeroth 32-bit of key0.
  */
 #define EFUSE_KEY0_DATA4    0xFFFFFFFFU
 #define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
@@ -1326,11 +1421,11 @@ extern "C" {
 #define EFUSE_KEY0_DATA4_S  0
 
 /** EFUSE_RD_KEY0_DATA5_REG register
- *  Register $n of BLOCK4 (KEY0).
+ *  Represents rd_key0_data5
  */
 #define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
 /** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY0.
+ *  Represents the zeroth 32-bit of key0.
  */
 #define EFUSE_KEY0_DATA5    0xFFFFFFFFU
 #define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
@@ -1338,11 +1433,11 @@ extern "C" {
 #define EFUSE_KEY0_DATA5_S  0
 
 /** EFUSE_RD_KEY0_DATA6_REG register
- *  Register $n of BLOCK4 (KEY0).
+ *  Represents rd_key0_data6
  */
 #define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
 /** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY0.
+ *  Represents the zeroth 32-bit of key0.
  */
 #define EFUSE_KEY0_DATA6    0xFFFFFFFFU
 #define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
@@ -1350,11 +1445,11 @@ extern "C" {
 #define EFUSE_KEY0_DATA6_S  0
 
 /** EFUSE_RD_KEY0_DATA7_REG register
- *  Register $n of BLOCK4 (KEY0).
+ *  Represents rd_key0_data7
  */
 #define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
 /** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY0.
+ *  Represents the zeroth 32-bit of key0.
  */
 #define EFUSE_KEY0_DATA7    0xFFFFFFFFU
 #define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
@@ -1362,11 +1457,11 @@ extern "C" {
 #define EFUSE_KEY0_DATA7_S  0
 
 /** EFUSE_RD_KEY1_DATA0_REG register
- *  Register $n of BLOCK5 (KEY1).
+ *  Represents rd_key1_data0
  */
 #define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
 /** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY1.
+ *  Represents the zeroth 32-bit of key1.
  */
 #define EFUSE_KEY1_DATA0    0xFFFFFFFFU
 #define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
@@ -1374,11 +1469,11 @@ extern "C" {
 #define EFUSE_KEY1_DATA0_S  0
 
 /** EFUSE_RD_KEY1_DATA1_REG register
- *  Register $n of BLOCK5 (KEY1).
+ *  Represents rd_key1_data1
  */
 #define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
 /** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY1.
+ *  Represents the zeroth 32-bit of key1.
  */
 #define EFUSE_KEY1_DATA1    0xFFFFFFFFU
 #define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
@@ -1386,11 +1481,11 @@ extern "C" {
 #define EFUSE_KEY1_DATA1_S  0
 
 /** EFUSE_RD_KEY1_DATA2_REG register
- *  Register $n of BLOCK5 (KEY1).
+ *  Represents rd_key1_data2
  */
 #define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
 /** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY1.
+ *  Represents the zeroth 32-bit of key1.
  */
 #define EFUSE_KEY1_DATA2    0xFFFFFFFFU
 #define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
@@ -1398,11 +1493,11 @@ extern "C" {
 #define EFUSE_KEY1_DATA2_S  0
 
 /** EFUSE_RD_KEY1_DATA3_REG register
- *  Register $n of BLOCK5 (KEY1).
+ *  Represents rd_key1_data3
  */
 #define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
 /** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY1.
+ *  Represents the zeroth 32-bit of key1.
  */
 #define EFUSE_KEY1_DATA3    0xFFFFFFFFU
 #define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
@@ -1410,11 +1505,11 @@ extern "C" {
 #define EFUSE_KEY1_DATA3_S  0
 
 /** EFUSE_RD_KEY1_DATA4_REG register
- *  Register $n of BLOCK5 (KEY1).
+ *  Represents rd_key1_data4
  */
 #define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
 /** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY1.
+ *  Represents the zeroth 32-bit of key1.
  */
 #define EFUSE_KEY1_DATA4    0xFFFFFFFFU
 #define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
@@ -1422,11 +1517,11 @@ extern "C" {
 #define EFUSE_KEY1_DATA4_S  0
 
 /** EFUSE_RD_KEY1_DATA5_REG register
- *  Register $n of BLOCK5 (KEY1).
+ *  Represents rd_key1_data5
  */
 #define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
 /** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY1.
+ *  Represents the zeroth 32-bit of key1.
  */
 #define EFUSE_KEY1_DATA5    0xFFFFFFFFU
 #define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
@@ -1434,11 +1529,11 @@ extern "C" {
 #define EFUSE_KEY1_DATA5_S  0
 
 /** EFUSE_RD_KEY1_DATA6_REG register
- *  Register $n of BLOCK5 (KEY1).
+ *  Represents rd_key1_data6
  */
 #define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
 /** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY1.
+ *  Represents the zeroth 32-bit of key1.
  */
 #define EFUSE_KEY1_DATA6    0xFFFFFFFFU
 #define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
@@ -1446,11 +1541,11 @@ extern "C" {
 #define EFUSE_KEY1_DATA6_S  0
 
 /** EFUSE_RD_KEY1_DATA7_REG register
- *  Register $n of BLOCK5 (KEY1).
+ *  Represents rd_key1_data7
  */
 #define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
 /** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY1.
+ *  Represents the zeroth 32-bit of key1.
  */
 #define EFUSE_KEY1_DATA7    0xFFFFFFFFU
 #define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
@@ -1458,11 +1553,11 @@ extern "C" {
 #define EFUSE_KEY1_DATA7_S  0
 
 /** EFUSE_RD_KEY2_DATA0_REG register
- *  Register $n of BLOCK6 (KEY2).
+ *  Represents rd_key2_data0
  */
 #define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
 /** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY2.
+ *  Represents the zeroth 32-bit of key2.
  */
 #define EFUSE_KEY2_DATA0    0xFFFFFFFFU
 #define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
@@ -1470,11 +1565,11 @@ extern "C" {
 #define EFUSE_KEY2_DATA0_S  0
 
 /** EFUSE_RD_KEY2_DATA1_REG register
- *  Register $n of BLOCK6 (KEY2).
+ *  Represents rd_key2_data1
  */
 #define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
 /** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY2.
+ *  Represents the zeroth 32-bit of key2.
  */
 #define EFUSE_KEY2_DATA1    0xFFFFFFFFU
 #define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
@@ -1482,11 +1577,11 @@ extern "C" {
 #define EFUSE_KEY2_DATA1_S  0
 
 /** EFUSE_RD_KEY2_DATA2_REG register
- *  Register $n of BLOCK6 (KEY2).
+ *  Represents rd_key2_data2
  */
 #define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
 /** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY2.
+ *  Represents the zeroth 32-bit of key2.
  */
 #define EFUSE_KEY2_DATA2    0xFFFFFFFFU
 #define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
@@ -1494,11 +1589,11 @@ extern "C" {
 #define EFUSE_KEY2_DATA2_S  0
 
 /** EFUSE_RD_KEY2_DATA3_REG register
- *  Register $n of BLOCK6 (KEY2).
+ *  Represents rd_key2_data3
  */
 #define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
 /** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY2.
+ *  Represents the zeroth 32-bit of key2.
  */
 #define EFUSE_KEY2_DATA3    0xFFFFFFFFU
 #define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
@@ -1506,11 +1601,11 @@ extern "C" {
 #define EFUSE_KEY2_DATA3_S  0
 
 /** EFUSE_RD_KEY2_DATA4_REG register
- *  Register $n of BLOCK6 (KEY2).
+ *  Represents rd_key2_data4
  */
 #define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
 /** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY2.
+ *  Represents the zeroth 32-bit of key2.
  */
 #define EFUSE_KEY2_DATA4    0xFFFFFFFFU
 #define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
@@ -1518,11 +1613,11 @@ extern "C" {
 #define EFUSE_KEY2_DATA4_S  0
 
 /** EFUSE_RD_KEY2_DATA5_REG register
- *  Register $n of BLOCK6 (KEY2).
+ *  Represents rd_key2_data5
  */
 #define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
 /** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY2.
+ *  Represents the zeroth 32-bit of key2.
  */
 #define EFUSE_KEY2_DATA5    0xFFFFFFFFU
 #define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
@@ -1530,11 +1625,11 @@ extern "C" {
 #define EFUSE_KEY2_DATA5_S  0
 
 /** EFUSE_RD_KEY2_DATA6_REG register
- *  Register $n of BLOCK6 (KEY2).
+ *  Represents rd_key2_data6
  */
 #define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
 /** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY2.
+ *  Represents the zeroth 32-bit of key2.
  */
 #define EFUSE_KEY2_DATA6    0xFFFFFFFFU
 #define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
@@ -1542,11 +1637,11 @@ extern "C" {
 #define EFUSE_KEY2_DATA6_S  0
 
 /** EFUSE_RD_KEY2_DATA7_REG register
- *  Register $n of BLOCK6 (KEY2).
+ *  Represents rd_key2_data7
  */
 #define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
 /** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY2.
+ *  Represents the zeroth 32-bit of key2.
  */
 #define EFUSE_KEY2_DATA7    0xFFFFFFFFU
 #define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
@@ -1554,11 +1649,11 @@ extern "C" {
 #define EFUSE_KEY2_DATA7_S  0
 
 /** EFUSE_RD_KEY3_DATA0_REG register
- *  Register $n of BLOCK7 (KEY3).
+ *  Represents rd_key3_data0
  */
 #define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
 /** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY3.
+ *  Represents the zeroth 32-bit of key3.
  */
 #define EFUSE_KEY3_DATA0    0xFFFFFFFFU
 #define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
@@ -1566,11 +1661,11 @@ extern "C" {
 #define EFUSE_KEY3_DATA0_S  0
 
 /** EFUSE_RD_KEY3_DATA1_REG register
- *  Register $n of BLOCK7 (KEY3).
+ *  Represents rd_key3_data1
  */
 #define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
 /** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY3.
+ *  Represents the zeroth 32-bit of key3.
  */
 #define EFUSE_KEY3_DATA1    0xFFFFFFFFU
 #define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
@@ -1578,11 +1673,11 @@ extern "C" {
 #define EFUSE_KEY3_DATA1_S  0
 
 /** EFUSE_RD_KEY3_DATA2_REG register
- *  Register $n of BLOCK7 (KEY3).
+ *  Represents rd_key3_data2
  */
 #define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
 /** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY3.
+ *  Represents the zeroth 32-bit of key3.
  */
 #define EFUSE_KEY3_DATA2    0xFFFFFFFFU
 #define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
@@ -1590,11 +1685,11 @@ extern "C" {
 #define EFUSE_KEY3_DATA2_S  0
 
 /** EFUSE_RD_KEY3_DATA3_REG register
- *  Register $n of BLOCK7 (KEY3).
+ *  Represents rd_key3_data3
  */
 #define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
 /** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY3.
+ *  Represents the zeroth 32-bit of key3.
  */
 #define EFUSE_KEY3_DATA3    0xFFFFFFFFU
 #define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
@@ -1602,11 +1697,11 @@ extern "C" {
 #define EFUSE_KEY3_DATA3_S  0
 
 /** EFUSE_RD_KEY3_DATA4_REG register
- *  Register $n of BLOCK7 (KEY3).
+ *  Represents rd_key3_data4
  */
 #define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
 /** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY3.
+ *  Represents the zeroth 32-bit of key3.
  */
 #define EFUSE_KEY3_DATA4    0xFFFFFFFFU
 #define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
@@ -1614,11 +1709,11 @@ extern "C" {
 #define EFUSE_KEY3_DATA4_S  0
 
 /** EFUSE_RD_KEY3_DATA5_REG register
- *  Register $n of BLOCK7 (KEY3).
+ *  Represents rd_key3_data5
  */
 #define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
 /** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY3.
+ *  Represents the zeroth 32-bit of key3.
  */
 #define EFUSE_KEY3_DATA5    0xFFFFFFFFU
 #define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
@@ -1626,11 +1721,11 @@ extern "C" {
 #define EFUSE_KEY3_DATA5_S  0
 
 /** EFUSE_RD_KEY3_DATA6_REG register
- *  Register $n of BLOCK7 (KEY3).
+ *  Represents rd_key3_data6
  */
 #define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
 /** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY3.
+ *  Represents the zeroth 32-bit of key3.
  */
 #define EFUSE_KEY3_DATA6    0xFFFFFFFFU
 #define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
@@ -1638,11 +1733,11 @@ extern "C" {
 #define EFUSE_KEY3_DATA6_S  0
 
 /** EFUSE_RD_KEY3_DATA7_REG register
- *  Register $n of BLOCK7 (KEY3).
+ *  Represents rd_key3_data7
  */
 #define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
 /** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY3.
+ *  Represents the zeroth 32-bit of key3.
  */
 #define EFUSE_KEY3_DATA7    0xFFFFFFFFU
 #define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
@@ -1650,11 +1745,11 @@ extern "C" {
 #define EFUSE_KEY3_DATA7_S  0
 
 /** EFUSE_RD_KEY4_DATA0_REG register
- *  Register $n of BLOCK8 (KEY4).
+ *  Represents rd_key4_data0
  */
 #define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
 /** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY4.
+ *  Represents the zeroth 32-bit of key4.
  */
 #define EFUSE_KEY4_DATA0    0xFFFFFFFFU
 #define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
@@ -1662,11 +1757,11 @@ extern "C" {
 #define EFUSE_KEY4_DATA0_S  0
 
 /** EFUSE_RD_KEY4_DATA1_REG register
- *  Register $n of BLOCK8 (KEY4).
+ *  Represents rd_key4_data1
  */
 #define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
 /** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY4.
+ *  Represents the zeroth 32-bit of key4.
  */
 #define EFUSE_KEY4_DATA1    0xFFFFFFFFU
 #define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
@@ -1674,11 +1769,11 @@ extern "C" {
 #define EFUSE_KEY4_DATA1_S  0
 
 /** EFUSE_RD_KEY4_DATA2_REG register
- *  Register $n of BLOCK8 (KEY4).
+ *  Represents rd_key4_data2
  */
 #define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
 /** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY4.
+ *  Represents the zeroth 32-bit of key4.
  */
 #define EFUSE_KEY4_DATA2    0xFFFFFFFFU
 #define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
@@ -1686,11 +1781,11 @@ extern "C" {
 #define EFUSE_KEY4_DATA2_S  0
 
 /** EFUSE_RD_KEY4_DATA3_REG register
- *  Register $n of BLOCK8 (KEY4).
+ *  Represents rd_key4_data3
  */
 #define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
 /** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY4.
+ *  Represents the zeroth 32-bit of key4.
  */
 #define EFUSE_KEY4_DATA3    0xFFFFFFFFU
 #define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
@@ -1698,11 +1793,11 @@ extern "C" {
 #define EFUSE_KEY4_DATA3_S  0
 
 /** EFUSE_RD_KEY4_DATA4_REG register
- *  Register $n of BLOCK8 (KEY4).
+ *  Represents rd_key4_data4
  */
 #define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
 /** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY4.
+ *  Represents the zeroth 32-bit of key4.
  */
 #define EFUSE_KEY4_DATA4    0xFFFFFFFFU
 #define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
@@ -1710,11 +1805,11 @@ extern "C" {
 #define EFUSE_KEY4_DATA4_S  0
 
 /** EFUSE_RD_KEY4_DATA5_REG register
- *  Register $n of BLOCK8 (KEY4).
+ *  Represents rd_key4_data5
  */
 #define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
 /** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY4.
+ *  Represents the zeroth 32-bit of key4.
  */
 #define EFUSE_KEY4_DATA5    0xFFFFFFFFU
 #define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
@@ -1722,11 +1817,11 @@ extern "C" {
 #define EFUSE_KEY4_DATA5_S  0
 
 /** EFUSE_RD_KEY4_DATA6_REG register
- *  Register $n of BLOCK8 (KEY4).
+ *  Represents rd_key4_data6
  */
 #define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
 /** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY4.
+ *  Represents the zeroth 32-bit of key4.
  */
 #define EFUSE_KEY4_DATA6    0xFFFFFFFFU
 #define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
@@ -1734,11 +1829,11 @@ extern "C" {
 #define EFUSE_KEY4_DATA6_S  0
 
 /** EFUSE_RD_KEY4_DATA7_REG register
- *  Register $n of BLOCK8 (KEY4).
+ *  Represents rd_key4_data7
  */
 #define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
 /** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY4.
+ *  Represents the zeroth 32-bit of key4.
  */
 #define EFUSE_KEY4_DATA7    0xFFFFFFFFU
 #define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
@@ -1746,11 +1841,11 @@ extern "C" {
 #define EFUSE_KEY4_DATA7_S  0
 
 /** EFUSE_RD_KEY5_DATA0_REG register
- *  Register $n of BLOCK9 (KEY5).
+ *  Represents rd_key5_data0
  */
 #define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
 /** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY5.
+ *  Represents the zeroth 32-bit of key5.
  */
 #define EFUSE_KEY5_DATA0    0xFFFFFFFFU
 #define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
@@ -1758,11 +1853,11 @@ extern "C" {
 #define EFUSE_KEY5_DATA0_S  0
 
 /** EFUSE_RD_KEY5_DATA1_REG register
- *  Register $n of BLOCK9 (KEY5).
+ *  Represents rd_key5_data1
  */
 #define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
 /** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY5.
+ *  Represents the zeroth 32-bit of key5.
  */
 #define EFUSE_KEY5_DATA1    0xFFFFFFFFU
 #define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
@@ -1770,11 +1865,11 @@ extern "C" {
 #define EFUSE_KEY5_DATA1_S  0
 
 /** EFUSE_RD_KEY5_DATA2_REG register
- *  Register $n of BLOCK9 (KEY5).
+ *  Represents rd_key5_data2
  */
 #define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
 /** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY5.
+ *  Represents the zeroth 32-bit of key5.
  */
 #define EFUSE_KEY5_DATA2    0xFFFFFFFFU
 #define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
@@ -1782,11 +1877,11 @@ extern "C" {
 #define EFUSE_KEY5_DATA2_S  0
 
 /** EFUSE_RD_KEY5_DATA3_REG register
- *  Register $n of BLOCK9 (KEY5).
+ *  Represents rd_key5_data3
  */
 #define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
 /** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY5.
+ *  Represents the zeroth 32-bit of key5.
  */
 #define EFUSE_KEY5_DATA3    0xFFFFFFFFU
 #define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
@@ -1794,11 +1889,11 @@ extern "C" {
 #define EFUSE_KEY5_DATA3_S  0
 
 /** EFUSE_RD_KEY5_DATA4_REG register
- *  Register $n of BLOCK9 (KEY5).
+ *  Represents rd_key5_data4
  */
 #define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
 /** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY5.
+ *  Represents the zeroth 32-bit of key5.
  */
 #define EFUSE_KEY5_DATA4    0xFFFFFFFFU
 #define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
@@ -1806,11 +1901,11 @@ extern "C" {
 #define EFUSE_KEY5_DATA4_S  0
 
 /** EFUSE_RD_KEY5_DATA5_REG register
- *  Register $n of BLOCK9 (KEY5).
+ *  Represents rd_key5_data5
  */
 #define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
 /** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY5.
+ *  Represents the zeroth 32-bit of key5.
  */
 #define EFUSE_KEY5_DATA5    0xFFFFFFFFU
 #define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
@@ -1818,11 +1913,11 @@ extern "C" {
 #define EFUSE_KEY5_DATA5_S  0
 
 /** EFUSE_RD_KEY5_DATA6_REG register
- *  Register $n of BLOCK9 (KEY5).
+ *  Represents rd_key5_data6
  */
 #define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
 /** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY5.
+ *  Represents the zeroth 32-bit of key5.
  */
 #define EFUSE_KEY5_DATA6    0xFFFFFFFFU
 #define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
@@ -1830,11 +1925,11 @@ extern "C" {
 #define EFUSE_KEY5_DATA6_S  0
 
 /** EFUSE_RD_KEY5_DATA7_REG register
- *  Register $n of BLOCK9 (KEY5).
+ *  Represents rd_key5_data7
  */
 #define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
 /** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY5.
+ *  Represents the zeroth 32-bit of key5.
  */
 #define EFUSE_KEY5_DATA7    0xFFFFFFFFU
 #define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
@@ -1842,7 +1937,7 @@ extern "C" {
 #define EFUSE_KEY5_DATA7_S  0
 
 /** EFUSE_RD_SYS_PART2_DATA0_REG register
- *  Register $n of BLOCK10 (system).
+ *  Represents rd_sys_part2_data
  */
 #define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
 /** EFUSE_ADC2_HI_DOUT_ATTEN0 : R; bitpos: [9:0]; default: 0;
@@ -1875,7 +1970,7 @@ extern "C" {
 #define EFUSE_ADC2_HI_DOUT_ATTEN3_S  30
 
 /** EFUSE_RD_SYS_PART2_DATA1_REG register
- *  Register $n of BLOCK9 (KEY5).
+ *  Represents rd_sys_part2_data
  */
 #define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
 /** EFUSE_ADC2_HI_DOUT_ATTEN3_1 : R; bitpos: [7:0]; default: 0;
@@ -1929,7 +2024,7 @@ extern "C" {
 #define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S  28
 
 /** EFUSE_RD_SYS_PART2_DATA2_REG register
- *  Register $n of BLOCK10 (system).
+ *  Represents rd_sys_part2_data
  */
 #define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
 /** EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF : R; bitpos: [3:0]; default: 0;
@@ -1990,30 +2085,30 @@ extern "C" {
 #define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_S  28
 
 /** EFUSE_RD_SYS_PART2_DATA3_REG register
- *  Register $n of BLOCK10 (system).
+ *  Represents rd_sys_part2_data
  */
 #define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
-/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0;
+/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [9:0]; default: 0;
  *  Temperature calibration data
  */
-#define EFUSE_TEMPERATURE_SENSOR    0x000001FFU
+#define EFUSE_TEMPERATURE_SENSOR    0x000003FFU
 #define EFUSE_TEMPERATURE_SENSOR_M  (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S)
-#define EFUSE_TEMPERATURE_SENSOR_V  0x000001FFU
+#define EFUSE_TEMPERATURE_SENSOR_V  0x000003FFU
 #define EFUSE_TEMPERATURE_SENSOR_S  0
-/** EFUSE_RESERVED_10_105 : R; bitpos: [31:9]; default: 0;
+/** EFUSE_RESERVED_10_106 : R; bitpos: [31:10]; default: 0;
  *  reserved
  */
-#define EFUSE_RESERVED_10_105    0x007FFFFFU
-#define EFUSE_RESERVED_10_105_M  (EFUSE_RESERVED_10_105_V << EFUSE_RESERVED_10_105_S)
-#define EFUSE_RESERVED_10_105_V  0x007FFFFFU
-#define EFUSE_RESERVED_10_105_S  9
+#define EFUSE_RESERVED_10_106    0x003FFFFFU
+#define EFUSE_RESERVED_10_106_M  (EFUSE_RESERVED_10_106_V << EFUSE_RESERVED_10_106_S)
+#define EFUSE_RESERVED_10_106_V  0x003FFFFFU
+#define EFUSE_RESERVED_10_106_S  10
 
 /** EFUSE_RD_SYS_PART2_DATA4_REG register
- *  Register $n of BLOCK10 (system).
+ *  Represents rd_sys_part2_data
  */
 #define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
 /** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
+ *  Represents the fourth 32-bit of second part of system data.
  */
 #define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
@@ -2021,11 +2116,11 @@ extern "C" {
 #define EFUSE_SYS_DATA_PART2_4_S  0
 
 /** EFUSE_RD_SYS_PART2_DATA5_REG register
- *  Register $n of BLOCK10 (system).
+ *  Represents rd_sys_part2_data
  */
 #define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
 /** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
+ *  Represents the fifth 32-bit of second part of system data.
  */
 #define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
 #define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
@@ -2033,243 +2128,321 @@ extern "C" {
 #define EFUSE_SYS_DATA_PART2_5_S  0
 
 /** EFUSE_RD_SYS_PART2_DATA6_REG register
- *  Register $n of BLOCK10 (system).
+ *  Represents rd_sys_part2_data
  */
 #define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
-/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
+/** EFUSE_PVT_LIMIT : RO; bitpos: [15:0]; default: 0;
+ *  Power glitch monitor threthold.
+ */
+#define EFUSE_PVT_LIMIT    0x0000FFFFU
+#define EFUSE_PVT_LIMIT_M  (EFUSE_PVT_LIMIT_V << EFUSE_PVT_LIMIT_S)
+#define EFUSE_PVT_LIMIT_V  0x0000FFFFU
+#define EFUSE_PVT_LIMIT_S  0
+/** EFUSE_PVT_PUMP_LIMIT : RO; bitpos: [23:16]; default: 0;
+ *  Use to configure voltage monitor limit for charge pump
+ */
+#define EFUSE_PVT_PUMP_LIMIT    0x000000FFU
+#define EFUSE_PVT_PUMP_LIMIT_M  (EFUSE_PVT_PUMP_LIMIT_V << EFUSE_PVT_PUMP_LIMIT_S)
+#define EFUSE_PVT_PUMP_LIMIT_V  0x000000FFU
+#define EFUSE_PVT_PUMP_LIMIT_S  16
+/** EFUSE_PVT_CELL_SELECT : RO; bitpos: [30:24]; default: 0;
+ *  Power glitch monitor PVT cell select.
+ */
+#define EFUSE_PVT_CELL_SELECT    0x0000007FU
+#define EFUSE_PVT_CELL_SELECT_M  (EFUSE_PVT_CELL_SELECT_V << EFUSE_PVT_CELL_SELECT_S)
+#define EFUSE_PVT_CELL_SELECT_V  0x0000007FU
+#define EFUSE_PVT_CELL_SELECT_S  24
+/** EFUSE_RD_RESERVE_10_223 : RW; bitpos: [31]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
  */
-#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
-#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_S  0
+#define EFUSE_RD_RESERVE_10_223    (BIT(31))
+#define EFUSE_RD_RESERVE_10_223_M  (EFUSE_RD_RESERVE_10_223_V << EFUSE_RD_RESERVE_10_223_S)
+#define EFUSE_RD_RESERVE_10_223_V  0x00000001U
+#define EFUSE_RD_RESERVE_10_223_S  31
 
 /** EFUSE_RD_SYS_PART2_DATA7_REG register
- *  Register $n of BLOCK10 (system).
+ *  Represents rd_sys_part2_data
  */
 #define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
-/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
+/** EFUSE_PUMP_DRV : RO; bitpos: [3:0]; default: 0;
+ *  Use to configure charge pump voltage gain
+ */
+#define EFUSE_PUMP_DRV    0x0000000FU
+#define EFUSE_PUMP_DRV_M  (EFUSE_PUMP_DRV_V << EFUSE_PUMP_DRV_S)
+#define EFUSE_PUMP_DRV_V  0x0000000FU
+#define EFUSE_PUMP_DRV_S  0
+/** EFUSE_USB_DEVICE_EXCHG_PINS : RO; bitpos: [4]; default: 0;
+ *  Enable usb device exchange pins of D+ and D-.
+ */
+#define EFUSE_USB_DEVICE_EXCHG_PINS    (BIT(4))
+#define EFUSE_USB_DEVICE_EXCHG_PINS_M  (EFUSE_USB_DEVICE_EXCHG_PINS_V << EFUSE_USB_DEVICE_EXCHG_PINS_S)
+#define EFUSE_USB_DEVICE_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_DEVICE_EXCHG_PINS_S  4
+/** EFUSE_USB_OTG11_EXCHG_PINS : RO; bitpos: [5]; default: 0;
+ *  Enable usb otg11 exchange pins of D+ and D-.
+ */
+#define EFUSE_USB_OTG11_EXCHG_PINS    (BIT(5))
+#define EFUSE_USB_OTG11_EXCHG_PINS_M  (EFUSE_USB_OTG11_EXCHG_PINS_V << EFUSE_USB_OTG11_EXCHG_PINS_S)
+#define EFUSE_USB_OTG11_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_OTG11_EXCHG_PINS_S  5
+/** EFUSE_USB_DEVICE_DREFH : RO; bitpos: [7:6]; default: 0;
+ *  usb intphy of usb device single-end input high threshold, 1.76V to 2V. step by 80mV.
  */
-#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
-#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_S  0
+#define EFUSE_USB_DEVICE_DREFH    0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_M  (EFUSE_USB_DEVICE_DREFH_V << EFUSE_USB_DEVICE_DREFH_S)
+#define EFUSE_USB_DEVICE_DREFH_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_S  6
+/** EFUSE_USB_OTG11_DREFH : RO; bitpos: [9:8]; default: 0;
+ *  usb intphy of usb otg11 single-end input high threshold, 1.76V to 2V. step by 80mV.
+ */
+#define EFUSE_USB_OTG11_DREFH    0x00000003U
+#define EFUSE_USB_OTG11_DREFH_M  (EFUSE_USB_OTG11_DREFH_V << EFUSE_USB_OTG11_DREFH_S)
+#define EFUSE_USB_OTG11_DREFH_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFH_S  8
+/** EFUSE_USB_DEVICE_DREFL : RO; bitpos: [11:10]; default: 0;
+ *  usb intphy of usb device single-end input low threshold, 0.8V to 1.04V. step by
+ *  80mV.
+ */
+#define EFUSE_USB_DEVICE_DREFL    0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_M  (EFUSE_USB_DEVICE_DREFL_V << EFUSE_USB_DEVICE_DREFL_S)
+#define EFUSE_USB_DEVICE_DREFL_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_S  10
+/** EFUSE_USB_OTG11_DREFL : RO; bitpos: [13:12]; default: 0;
+ *  usb intphy of usb otg11 single-end input low threshold, 0.8V to 1.04V. step by 80mV.
+ */
+#define EFUSE_USB_OTG11_DREFL    0x00000003U
+#define EFUSE_USB_OTG11_DREFL_M  (EFUSE_USB_OTG11_DREFL_V << EFUSE_USB_OTG11_DREFL_S)
+#define EFUSE_USB_OTG11_DREFL_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFL_S  12
+/** EFUSE_RD_RESERVE_10_238 : RW; bitpos: [31:14]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_10_238    0x0003FFFFU
+#define EFUSE_RD_RESERVE_10_238_M  (EFUSE_RD_RESERVE_10_238_V << EFUSE_RD_RESERVE_10_238_S)
+#define EFUSE_RD_RESERVE_10_238_V  0x0003FFFFU
+#define EFUSE_RD_RESERVE_10_238_S  14
 
 /** EFUSE_RD_REPEAT_ERR0_REG register
- *  Programming error record register 0 of BLOCK0.
+ *  Represents rd_repeat_data_err
  */
 #define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
 /** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
- *  Indicates a programming error of RD_DIS.
+ *  Represents the programming error of EFUSE_RD_DIS
  */
 #define EFUSE_RD_DIS_ERR    0x0000007FU
 #define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
 #define EFUSE_RD_DIS_ERR_V  0x0000007FU
 #define EFUSE_RD_DIS_ERR_S  0
-/** EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR : RO; bitpos: [7]; default: 0;
- *  Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.
- */
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR    (BIT(7))
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_M  (EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S)
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S  7
-/** EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR : RO; bitpos: [8]; default: 0;
- *  Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.
- */
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR    (BIT(8))
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_M  (EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S)
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S  8
+/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_ERR : RO; bitpos: [8:7]; default: 0;
+ *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1
+ */
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_ERR    0x00000003U
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_ERR_M  (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_ERR_S)
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_ERR_V  0x00000003U
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_ERR_S  7
 /** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
- *  Indicates a programming error of DIS_USB_JTAG.
+ *  Represents the programming error of EFUSE_DIS_USB_JTAG
  */
 #define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
 #define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
 #define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
 #define EFUSE_DIS_USB_JTAG_ERR_S  9
-/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0;
- *  Indicates a programming error of POWERGLITCH_EN.
+/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_ERR : RO; bitpos: [10]; default: 0;
+ *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2
  */
-#define EFUSE_POWERGLITCH_EN_ERR    (BIT(10))
-#define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
-#define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
-#define EFUSE_POWERGLITCH_EN_ERR_S  10
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_ERR    (BIT(10))
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_ERR_M  (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_ERR_S)
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_ERR_V  0x00000001U
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_ERR_S  10
 /** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0;
- *  Indicates a programming error of DIS_USB_SERIAL_JTAG.
+ *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG
  */
 #define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
 #define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
 #define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
 #define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
 /** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
- *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
+ *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
  */
 #define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
 #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
 #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
 #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
 /** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0;
- *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
+ *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
  */
 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
 /** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
- *  Indicates a programming error of DIS_TWAI.
+ *  Represents the programming error of EFUSE_DIS_TWAI
  */
 #define EFUSE_DIS_TWAI_ERR    (BIT(14))
 #define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
 #define EFUSE_DIS_TWAI_ERR_V  0x00000001U
 #define EFUSE_DIS_TWAI_ERR_S  14
 /** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
- *  Indicates a programming error of JTAG_SEL_ENABLE.
+ *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
  */
 #define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
 #define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
 #define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
 #define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
 /** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
- *  Indicates a programming error of SOFT_DIS_JTAG.
+ *  Represents the programming error of EFUSE_SOFT_DIS_JTAG
  */
 #define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
 #define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
 #define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
 #define EFUSE_SOFT_DIS_JTAG_ERR_S  16
 /** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
- *  Indicates a programming error of DIS_PAD_JTAG.
+ *  Represents the programming error of EFUSE_DIS_PAD_JTAG
  */
 #define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
 #define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
 #define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
 #define EFUSE_DIS_PAD_JTAG_ERR_S  19
 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
- *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+ *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
  */
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
-/** EFUSE_USB_DEVICE_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
- *  Indicates a programming error of USB_DEVICE_DREFH.
- */
-#define EFUSE_USB_DEVICE_DREFH_ERR    0x00000003U
-#define EFUSE_USB_DEVICE_DREFH_ERR_M  (EFUSE_USB_DEVICE_DREFH_ERR_V << EFUSE_USB_DEVICE_DREFH_ERR_S)
-#define EFUSE_USB_DEVICE_DREFH_ERR_V  0x00000003U
-#define EFUSE_USB_DEVICE_DREFH_ERR_S  21
-/** EFUSE_USB_OTG11_DREFH_ERR : RO; bitpos: [24:23]; default: 0;
- *  Indicates a programming error of USB_OTG11_DREFH.
- */
-#define EFUSE_USB_OTG11_DREFH_ERR    0x00000003U
-#define EFUSE_USB_OTG11_DREFH_ERR_M  (EFUSE_USB_OTG11_DREFH_ERR_V << EFUSE_USB_OTG11_DREFH_ERR_S)
-#define EFUSE_USB_OTG11_DREFH_ERR_V  0x00000003U
-#define EFUSE_USB_OTG11_DREFH_ERR_S  23
+/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_ERR : RO; bitpos: [24:21]; default: 0;
+ *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6
+ */
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_ERR    0x0000000FU
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_ERR_M  (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_ERR_S)
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_ERR_V  0x0000000FU
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_ERR_S  21
 /** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0;
- *  Indicates a programming error of USB_PHY_SEL.
+ *  Represents the programming error of EFUSE_USB_PHY_SEL
  */
 #define EFUSE_USB_PHY_SEL_ERR    (BIT(25))
 #define EFUSE_USB_PHY_SEL_ERR_M  (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S)
 #define EFUSE_USB_PHY_SEL_ERR_V  0x00000001U
 #define EFUSE_USB_PHY_SEL_ERR_S  25
-/** EFUSE_HUK_GEN_STATE_LOW_ERR : RO; bitpos: [31:26]; default: 0;
- *  Indicates a programming error of HUK_GEN_STATE_LOW.
+/** EFUSE_HUK_GEN_STATE_ERR : RO; bitpos: [30:26]; default: 0;
+ *  Represents the programming error of EFUSE_HUK_GEN_STATE
+ */
+#define EFUSE_HUK_GEN_STATE_ERR    0x0000001FU
+#define EFUSE_HUK_GEN_STATE_ERR_M  (EFUSE_HUK_GEN_STATE_ERR_V << EFUSE_HUK_GEN_STATE_ERR_S)
+#define EFUSE_HUK_GEN_STATE_ERR_V  0x0000001FU
+#define EFUSE_HUK_GEN_STATE_ERR_S  26
+/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_ERR : RO; bitpos: [31]; default: 0;
+ *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7
  */
-#define EFUSE_HUK_GEN_STATE_LOW_ERR    0x0000003FU
-#define EFUSE_HUK_GEN_STATE_LOW_ERR_M  (EFUSE_HUK_GEN_STATE_LOW_ERR_V << EFUSE_HUK_GEN_STATE_LOW_ERR_S)
-#define EFUSE_HUK_GEN_STATE_LOW_ERR_V  0x0000003FU
-#define EFUSE_HUK_GEN_STATE_LOW_ERR_S  26
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_ERR    (BIT(31))
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_ERR_M  (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_ERR_S)
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_ERR_V  0x00000001U
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_ERR_S  31
 
 /** EFUSE_RD_REPEAT_ERR1_REG register
- *  Programming error record register 1 of BLOCK0.
+ *  Represents rd_repeat_data_err
  */
 #define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
-/** EFUSE_KM_HUK_GEN_STATE_HIGH_ERR : RO; bitpos: [2:0]; default: 0;
- *  Indicates a programming error of HUK_GEN_STATE_HIGH.
- */
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR    0x00000007U
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_M  (EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V << EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S)
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V  0x00000007U
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S  0
-/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [4:3]; default: 0;
- *  Indicates a programming error of KM_RND_SWITCH_CYCLE.
- */
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR    0x00000003U
+/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_ERR : RO; bitpos: [2:0]; default: 0;
+ *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10
+ */
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_ERR    0x00000007U
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_ERR_M  (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_ERR_S)
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_ERR_V  0x00000007U
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_ERR_S  0
+/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_ERR : RO; bitpos: [3]; default: 0;
+ *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11
+ */
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_ERR    (BIT(3))
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_ERR_M  (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_ERR_S)
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_ERR_V  0x00000001U
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_ERR_S  3
+/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [4]; default: 0;
+ *  Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE
+ */
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR    (BIT(4))
 #define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M  (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S)
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V  0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S  3
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V  0x00000001U
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S  4
 /** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [8:5]; default: 0;
- *  Indicates a programming error of KM_DEPLOY_ONLY_ONCE.
+ *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE
  */
 #define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR    0x0000000FU
 #define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S)
 #define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V  0x0000000FU
 #define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S  5
 /** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [12:9]; default: 0;
- *  Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.
+ *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY
  */
 #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR    0x0000000FU
 #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S)
 #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V  0x0000000FU
 #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S  9
 /** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [13]; default: 0;
- *  Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.
+ *  Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY
  */
 #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR    (BIT(13))
 #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S)
 #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V  0x00000001U
 #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S  13
-/** EFUSE_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [14]; default: 0;
- *  Indicates a programming error of XTS_KEY_LENGTH_256.
- */
-#define EFUSE_XTS_KEY_LENGTH_256_ERR    (BIT(14))
-#define EFUSE_XTS_KEY_LENGTH_256_ERR_M  (EFUSE_XTS_KEY_LENGTH_256_ERR_V << EFUSE_XTS_KEY_LENGTH_256_ERR_S)
-#define EFUSE_XTS_KEY_LENGTH_256_ERR_V  0x00000001U
-#define EFUSE_XTS_KEY_LENGTH_256_ERR_S  14
-/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  Indicates a programming error of WDT_DELAY_SEL.
- */
-#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
+/** EFUSE_KM_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [14]; default: 0;
+ *  Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256
+ */
+#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR    (BIT(14))
+#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_M  (EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V << EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S)
+#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V  0x00000001U
+#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S  14
+/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [15]; default: 0;
+ *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
+ */
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR    (BIT(15))
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR_M  (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S)
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR_V  0x00000001U
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S  15
+/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17]; default: 0;
+ *  Represents the programming error of EFUSE_WDT_DELAY_SEL
+ */
+#define EFUSE_WDT_DELAY_SEL_ERR    (BIT(17))
 #define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
-#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_S  16
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000001U
+#define EFUSE_WDT_DELAY_SEL_ERR_S  17
 /** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
- *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
+ *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
  */
 #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
 #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
 #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
 #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
 /** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
+ *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0
  */
 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
 /** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
+ *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1
  */
 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
 /** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
+ *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2
  */
 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
 /** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_0.
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_0
  */
 #define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
 #define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
 #define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
 #define EFUSE_KEY_PURPOSE_0_ERR_S  24
 /** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_1.
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_1
  */
 #define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
 #define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
@@ -2277,102 +2450,95 @@ extern "C" {
 #define EFUSE_KEY_PURPOSE_1_ERR_S  28
 
 /** EFUSE_RD_REPEAT_ERR2_REG register
- *  Programming error record register 2 of BLOCK0.
+ *  Represents rd_repeat_data_err
  */
 #define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
 /** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_2.
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_2
  */
 #define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
 #define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
 #define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
 #define EFUSE_KEY_PURPOSE_2_ERR_S  0
 /** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_3.
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_3
  */
 #define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
 #define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
 #define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
 #define EFUSE_KEY_PURPOSE_3_ERR_S  4
 /** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_4.
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_4
  */
 #define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
 #define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
 #define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
 #define EFUSE_KEY_PURPOSE_4_ERR_S  8
 /** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_5.
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_5
  */
 #define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
 #define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
 #define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
 #define EFUSE_KEY_PURPOSE_5_ERR_S  12
 /** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  Indicates a programming error of SEC_DPA_LEVEL.
+ *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
  */
 #define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
 #define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
 #define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
 #define EFUSE_SEC_DPA_LEVEL_ERR_S  16
-/** EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO; bitpos: [18]; default: 0;
- *  Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.
- */
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR    (BIT(18))
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M  (EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V << EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S)
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V  0x00000001U
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S  18
-/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0;
- *  Indicates a programming error of CRYPT_DPA_ENABLE.
- */
-#define EFUSE_CRYPT_DPA_ENABLE_ERR    (BIT(19))
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_M  (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S)
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_V  0x00000001U
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_S  19
+/** EFUSE_XTS_DPA_CLK_ENABLE_ERR : RO; bitpos: [19]; default: 0;
+ *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
+ */
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR    (BIT(19))
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_M  (EFUSE_XTS_DPA_CLK_ENABLE_ERR_V << EFUSE_XTS_DPA_CLK_ENABLE_ERR_S)
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_V  0x00000001U
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_S  19
 /** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_EN.
+ *  Represents the programming error of EFUSE_SECURE_BOOT_EN
  */
 #define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
 #define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
 #define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
 #define EFUSE_SECURE_BOOT_EN_ERR_S  20
 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
+ *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
  */
 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
-/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [23]; default: 0;
- *  Indicates a programming error of FLASH_TYPE.
- */
-#define EFUSE_FLASH_TYPE_ERR    (BIT(23))
-#define EFUSE_FLASH_TYPE_ERR_M  (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S)
-#define EFUSE_FLASH_TYPE_ERR_V  0x00000001U
-#define EFUSE_FLASH_TYPE_ERR_S  23
-/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [25:24]; default: 0;
- *  Indicates a programming error of FLASH_PAGE_SIZE.
- */
-#define EFUSE_FLASH_PAGE_SIZE_ERR    0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_ERR_M  (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S)
-#define EFUSE_FLASH_PAGE_SIZE_ERR_V  0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_ERR_S  24
+/** EFUSE_KM_DEPLOY_ONLY_ONCE_H_ERR : RO; bitpos: [22]; default: 0;
+ *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE_H
+ */
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_H_ERR    (BIT(22))
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_H_ERR_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_H_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_H_ERR_S)
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_H_ERR_V  0x00000001U
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_H_ERR_S  22
+/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_ERR : RO; bitpos: [23]; default: 0;
+ *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY_H
+ */
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_ERR    (BIT(23))
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_ERR_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_ERR_S)
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_ERR_V  0x00000001U
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_ERR_S  23
 /** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [26]; default: 0;
- *  Indicates a programming error of FLASH_ECC_EN.
+ *  Represents the programming error of EFUSE_FLASH_ECC_EN
  */
 #define EFUSE_FLASH_ECC_EN_ERR    (BIT(26))
 #define EFUSE_FLASH_ECC_EN_ERR_M  (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S)
 #define EFUSE_FLASH_ECC_EN_ERR_V  0x00000001U
 #define EFUSE_FLASH_ECC_EN_ERR_S  26
 /** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO; bitpos: [27]; default: 0;
- *  Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.
+ *  Represents the programming error of EFUSE_DIS_USB_OTG_DOWNLOAD_MODE
  */
 #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR    (BIT(27))
 #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S)
 #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V  0x00000001U
 #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S  27
 /** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
- *  Indicates a programming error of FLASH_TPUW.
+ *  Represents the programming error of EFUSE_FLASH_TPUW
  */
 #define EFUSE_FLASH_TPUW_ERR    0x0000000FU
 #define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
@@ -2380,335 +2546,444 @@ extern "C" {
 #define EFUSE_FLASH_TPUW_ERR_S  28
 
 /** EFUSE_RD_REPEAT_ERR3_REG register
- *  Programming error record register 3 of BLOCK0.
+ *  Represents rd_repeat_data_err
  */
 #define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
 /** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
- *  Indicates a programming error of DIS_DOWNLOAD_MODE.
+ *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
  */
 #define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
 #define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
 #define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
 #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
 /** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
- *  Indicates a programming error of DIS_DIRECT_BOOT.
+ *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
  */
 #define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
 #define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
 #define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
 #define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0;
- *  Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.
+ *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
  */
 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR    (BIT(2))
 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S)
 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V  0x00000001U
 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S  2
 /** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0;
- *  TBD
+ *  Represents the programming error of EFUSE_LOCK_KM_KEY
  */
 #define EFUSE_LOCK_KM_KEY_ERR    (BIT(3))
 #define EFUSE_LOCK_KM_KEY_ERR_M  (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S)
 #define EFUSE_LOCK_KM_KEY_ERR_V  0x00000001U
 #define EFUSE_LOCK_KM_KEY_ERR_S  3
 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
- *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
+ *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
  */
 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
 /** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
- *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
+ *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
  */
 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
 /** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
- *  Indicates a programming error of UART_PRINT_CONTROL.
+ *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
  */
 #define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
 #define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
 #define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
 #define EFUSE_UART_PRINT_CONTROL_ERR_S  6
 /** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0;
- *  Indicates a programming error of FORCE_SEND_RESUME.
+ *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
  */
 #define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(8))
 #define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
 #define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
 #define EFUSE_FORCE_SEND_RESUME_ERR_S  8
 /** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0;
- *  Indicates a programming error of SECURE VERSION.
+ *  Represents the programming error of EFUSE_SECURE_VERSION
  */
 #define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
 #define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
 #define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
 #define EFUSE_SECURE_VERSION_ERR_S  9
 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
+ *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
  */
 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(25))
 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S)
 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x00000001U
 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  25
 /** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0;
- *  Indicates a programming error of HYS_EN_PAD.
+ *  Represents the programming error of EFUSE_HYS_EN_PAD
  */
 #define EFUSE_HYS_EN_PAD_ERR    (BIT(26))
 #define EFUSE_HYS_EN_PAD_ERR_M  (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S)
 #define EFUSE_HYS_EN_PAD_ERR_V  0x00000001U
 #define EFUSE_HYS_EN_PAD_ERR_S  26
-/** EFUSE_DCDC_VSET_ERR : RO; bitpos: [31:27]; default: 0;
- *  Indicates a programming error of DCDC_VSET.
- */
-#define EFUSE_DCDC_VSET_ERR    0x0000001FU
-#define EFUSE_DCDC_VSET_ERR_M  (EFUSE_DCDC_VSET_ERR_V << EFUSE_DCDC_VSET_ERR_S)
-#define EFUSE_DCDC_VSET_ERR_V  0x0000001FU
-#define EFUSE_DCDC_VSET_ERR_S  27
+/** EFUSE_KEY_PURPOSE_0_H_ERR : RO; bitpos: [27]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_0_H
+ */
+#define EFUSE_KEY_PURPOSE_0_H_ERR    (BIT(27))
+#define EFUSE_KEY_PURPOSE_0_H_ERR_M  (EFUSE_KEY_PURPOSE_0_H_ERR_V << EFUSE_KEY_PURPOSE_0_H_ERR_S)
+#define EFUSE_KEY_PURPOSE_0_H_ERR_V  0x00000001U
+#define EFUSE_KEY_PURPOSE_0_H_ERR_S  27
+/** EFUSE_KEY_PURPOSE_1_H_ERR : RO; bitpos: [28]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_1_H
+ */
+#define EFUSE_KEY_PURPOSE_1_H_ERR    (BIT(28))
+#define EFUSE_KEY_PURPOSE_1_H_ERR_M  (EFUSE_KEY_PURPOSE_1_H_ERR_V << EFUSE_KEY_PURPOSE_1_H_ERR_S)
+#define EFUSE_KEY_PURPOSE_1_H_ERR_V  0x00000001U
+#define EFUSE_KEY_PURPOSE_1_H_ERR_S  28
+/** EFUSE_KEY_PURPOSE_2_H_ERR : RO; bitpos: [29]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_2_H
+ */
+#define EFUSE_KEY_PURPOSE_2_H_ERR    (BIT(29))
+#define EFUSE_KEY_PURPOSE_2_H_ERR_M  (EFUSE_KEY_PURPOSE_2_H_ERR_V << EFUSE_KEY_PURPOSE_2_H_ERR_S)
+#define EFUSE_KEY_PURPOSE_2_H_ERR_V  0x00000001U
+#define EFUSE_KEY_PURPOSE_2_H_ERR_S  29
+/** EFUSE_KEY_PURPOSE_3_H_ERR : RO; bitpos: [30]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_3_H
+ */
+#define EFUSE_KEY_PURPOSE_3_H_ERR    (BIT(30))
+#define EFUSE_KEY_PURPOSE_3_H_ERR_M  (EFUSE_KEY_PURPOSE_3_H_ERR_V << EFUSE_KEY_PURPOSE_3_H_ERR_S)
+#define EFUSE_KEY_PURPOSE_3_H_ERR_V  0x00000001U
+#define EFUSE_KEY_PURPOSE_3_H_ERR_S  30
+/** EFUSE_KEY_PURPOSE_4_H_ERR : RO; bitpos: [31]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_4_H
+ */
+#define EFUSE_KEY_PURPOSE_4_H_ERR    (BIT(31))
+#define EFUSE_KEY_PURPOSE_4_H_ERR_M  (EFUSE_KEY_PURPOSE_4_H_ERR_V << EFUSE_KEY_PURPOSE_4_H_ERR_S)
+#define EFUSE_KEY_PURPOSE_4_H_ERR_V  0x00000001U
+#define EFUSE_KEY_PURPOSE_4_H_ERR_S  31
 
 /** EFUSE_RD_REPEAT_ERR4_REG register
- *  Programming error record register 4 of BLOCK0.
+ *  Represents rd_repeat_data_err
  */
 #define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c)
 /** EFUSE_PXA0_TIEH_SEL_0_ERR : RO; bitpos: [1:0]; default: 0;
- *  Indicates a programming error of 0PXA_TIEH_SEL_0.
+ *  Represents the programming error of EFUSE_0PXA_TIEH_SEL_0
  */
 #define EFUSE_PXA0_TIEH_SEL_0_ERR    0x00000003U
 #define EFUSE_PXA0_TIEH_SEL_0_ERR_M  (EFUSE_PXA0_TIEH_SEL_0_ERR_V << EFUSE_PXA0_TIEH_SEL_0_ERR_S)
 #define EFUSE_PXA0_TIEH_SEL_0_ERR_V  0x00000003U
 #define EFUSE_PXA0_TIEH_SEL_0_ERR_S  0
-/** EFUSE_PXA0_TIEH_SEL_1_ERR : RO; bitpos: [3:2]; default: 0;
- *  Indicates a programming error of 0PXA_TIEH_SEL_1.
- */
-#define EFUSE_PXA0_TIEH_SEL_1_ERR    0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_1_ERR_M  (EFUSE_PXA0_TIEH_SEL_1_ERR_V << EFUSE_PXA0_TIEH_SEL_1_ERR_S)
-#define EFUSE_PXA0_TIEH_SEL_1_ERR_V  0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_1_ERR_S  2
-/** EFUSE_PXA0_TIEH_SEL_2_ERR : RO; bitpos: [5:4]; default: 0;
- *  Indicates a programming error of 0PXA_TIEH_SEL_2.
- */
-#define EFUSE_PXA0_TIEH_SEL_2_ERR    0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_2_ERR_M  (EFUSE_PXA0_TIEH_SEL_2_ERR_V << EFUSE_PXA0_TIEH_SEL_2_ERR_S)
-#define EFUSE_PXA0_TIEH_SEL_2_ERR_V  0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_2_ERR_S  4
-/** EFUSE_PXA0_TIEH_SEL_3_ERR : RO; bitpos: [7:6]; default: 0;
- *  Indicates a programming error of 0PXA_TIEH_SEL_3.
- */
-#define EFUSE_PXA0_TIEH_SEL_3_ERR    0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_3_ERR_M  (EFUSE_PXA0_TIEH_SEL_3_ERR_V << EFUSE_PXA0_TIEH_SEL_3_ERR_S)
-#define EFUSE_PXA0_TIEH_SEL_3_ERR_V  0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_3_ERR_S  6
+/** EFUSE_PVT_GLITCH_EN_ERR : RO; bitpos: [2]; default: 0;
+ *  Represents the programming error of EFUSE_PVT_GLITCH_EN
+ */
+#define EFUSE_PVT_GLITCH_EN_ERR    (BIT(2))
+#define EFUSE_PVT_GLITCH_EN_ERR_M  (EFUSE_PVT_GLITCH_EN_ERR_V << EFUSE_PVT_GLITCH_EN_ERR_S)
+#define EFUSE_PVT_GLITCH_EN_ERR_V  0x00000001U
+#define EFUSE_PVT_GLITCH_EN_ERR_S  2
+/** EFUSE_KEY_PURPOSE_5_H_ERR : RO; bitpos: [4]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_5_H
+ */
+#define EFUSE_KEY_PURPOSE_5_H_ERR    (BIT(4))
+#define EFUSE_KEY_PURPOSE_5_H_ERR_M  (EFUSE_KEY_PURPOSE_5_H_ERR_V << EFUSE_KEY_PURPOSE_5_H_ERR_S)
+#define EFUSE_KEY_PURPOSE_5_H_ERR_V  0x00000001U
+#define EFUSE_KEY_PURPOSE_5_H_ERR_S  4
+/** EFUSE_KM_DISABLE_DEPLOY_MODE_H_ERR : RO; bitpos: [7]; default: 0;
+ *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE_H
+ */
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_H_ERR    (BIT(7))
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_H_ERR_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_H_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_H_ERR_S)
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_H_ERR_V  0x00000001U
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_H_ERR_S  7
 /** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [11:8]; default: 0;
- *  TBD.
+ *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE
  */
 #define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR    0x0000000FU
 #define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S)
 #define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V  0x0000000FU
 #define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S  8
-/** EFUSE_USB_DEVICE_DREFL_ERR : RO; bitpos: [13:12]; default: 0;
- *  Indicates a programming error of USB_DEVICE_DREFL.
- */
-#define EFUSE_USB_DEVICE_DREFL_ERR    0x00000003U
-#define EFUSE_USB_DEVICE_DREFL_ERR_M  (EFUSE_USB_DEVICE_DREFL_ERR_V << EFUSE_USB_DEVICE_DREFL_ERR_S)
-#define EFUSE_USB_DEVICE_DREFL_ERR_V  0x00000003U
-#define EFUSE_USB_DEVICE_DREFL_ERR_S  12
-/** EFUSE_USB_OTG11_DREFL_ERR : RO; bitpos: [15:14]; default: 0;
- *  Indicates a programming error of USB_OTG11_DREFL.
- */
-#define EFUSE_USB_OTG11_DREFL_ERR    0x00000003U
-#define EFUSE_USB_OTG11_DREFL_ERR_M  (EFUSE_USB_OTG11_DREFL_ERR_V << EFUSE_USB_OTG11_DREFL_ERR_S)
-#define EFUSE_USB_OTG11_DREFL_ERR_V  0x00000003U
-#define EFUSE_USB_OTG11_DREFL_ERR_S  14
+/** EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
+ */
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR    0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_M  (EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S)
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V  0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S  16
 /** EFUSE_HP_PWR_SRC_SEL_ERR : RO; bitpos: [18]; default: 0;
- *  Indicates a programming error of HP_PWR_SRC_SEL.
+ *  Represents the programming error of EFUSE_HP_PWR_SRC_SEL
  */
 #define EFUSE_HP_PWR_SRC_SEL_ERR    (BIT(18))
 #define EFUSE_HP_PWR_SRC_SEL_ERR_M  (EFUSE_HP_PWR_SRC_SEL_ERR_V << EFUSE_HP_PWR_SRC_SEL_ERR_S)
 #define EFUSE_HP_PWR_SRC_SEL_ERR_V  0x00000001U
 #define EFUSE_HP_PWR_SRC_SEL_ERR_S  18
-/** EFUSE_DCDC_VSET_EN_ERR : RO; bitpos: [19]; default: 0;
- *  Indicates a programming error of DCDC_VSET_EN.
+/** EFUSE_SECURE_BOOT_SHA384_EN_ERR : RO; bitpos: [19]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_SHA384_EN
  */
-#define EFUSE_DCDC_VSET_EN_ERR    (BIT(19))
-#define EFUSE_DCDC_VSET_EN_ERR_M  (EFUSE_DCDC_VSET_EN_ERR_V << EFUSE_DCDC_VSET_EN_ERR_S)
-#define EFUSE_DCDC_VSET_EN_ERR_V  0x00000001U
-#define EFUSE_DCDC_VSET_EN_ERR_S  19
+#define EFUSE_SECURE_BOOT_SHA384_EN_ERR    (BIT(19))
+#define EFUSE_SECURE_BOOT_SHA384_EN_ERR_M  (EFUSE_SECURE_BOOT_SHA384_EN_ERR_V << EFUSE_SECURE_BOOT_SHA384_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_SHA384_EN_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_SHA384_EN_ERR_S  19
 /** EFUSE_DIS_WDT_ERR : RO; bitpos: [20]; default: 0;
- *  Indicates a programming error of DIS_WDT.
+ *  Represents the programming error of EFUSE_DIS_WDT
  */
 #define EFUSE_DIS_WDT_ERR    (BIT(20))
 #define EFUSE_DIS_WDT_ERR_M  (EFUSE_DIS_WDT_ERR_V << EFUSE_DIS_WDT_ERR_S)
 #define EFUSE_DIS_WDT_ERR_V  0x00000001U
 #define EFUSE_DIS_WDT_ERR_S  20
 /** EFUSE_DIS_SWD_ERR : RO; bitpos: [21]; default: 0;
- *  Indicates a programming error of DIS_SWD.
+ *  Represents the programming error of EFUSE_DIS_SWD
  */
 #define EFUSE_DIS_SWD_ERR    (BIT(21))
 #define EFUSE_DIS_SWD_ERR_M  (EFUSE_DIS_SWD_ERR_V << EFUSE_DIS_SWD_ERR_S)
 #define EFUSE_DIS_SWD_ERR_V  0x00000001U
 #define EFUSE_DIS_SWD_ERR_S  21
+/** EFUSE_PVT_GLITCH_MODE_ERR : RO; bitpos: [23:22]; default: 0;
+ *  Represents the programming error of EFUSE_PVT_GLITCH_MODE
+ */
+#define EFUSE_PVT_GLITCH_MODE_ERR    0x00000003U
+#define EFUSE_PVT_GLITCH_MODE_ERR_M  (EFUSE_PVT_GLITCH_MODE_ERR_V << EFUSE_PVT_GLITCH_MODE_ERR_S)
+#define EFUSE_PVT_GLITCH_MODE_ERR_V  0x00000003U
+#define EFUSE_PVT_GLITCH_MODE_ERR_S  22
+
+/** EFUSE_ECDSA_REG register
+ *  eFuse status register.
+ */
+#define EFUSE_ECDSA_REG (DR_REG_EFUSE_BASE + 0x1b0)
+/** EFUSE_CFG_ECDSA_P192_BLK : R/W; bitpos: [3:0]; default: 0;
+ *  Configures which block to use for ECDSA P192 key output.
+ */
+#define EFUSE_CFG_ECDSA_P192_BLK    0x0000000FU
+#define EFUSE_CFG_ECDSA_P192_BLK_M  (EFUSE_CFG_ECDSA_P192_BLK_V << EFUSE_CFG_ECDSA_P192_BLK_S)
+#define EFUSE_CFG_ECDSA_P192_BLK_V  0x0000000FU
+#define EFUSE_CFG_ECDSA_P192_BLK_S  0
+/** EFUSE_CFG_ECDSA_P256_BLK : R/W; bitpos: [7:4]; default: 0;
+ *  Configures which block to use for ECDSA P256 key output.
+ */
+#define EFUSE_CFG_ECDSA_P256_BLK    0x0000000FU
+#define EFUSE_CFG_ECDSA_P256_BLK_M  (EFUSE_CFG_ECDSA_P256_BLK_V << EFUSE_CFG_ECDSA_P256_BLK_S)
+#define EFUSE_CFG_ECDSA_P256_BLK_V  0x0000000FU
+#define EFUSE_CFG_ECDSA_P256_BLK_S  4
+/** EFUSE_CFG_ECDSA_P384_L_BLK : R/W; bitpos: [11:8]; default: 0;
+ *  Configures which block to use for ECDSA P384 key low part output.
+ */
+#define EFUSE_CFG_ECDSA_P384_L_BLK    0x0000000FU
+#define EFUSE_CFG_ECDSA_P384_L_BLK_M  (EFUSE_CFG_ECDSA_P384_L_BLK_V << EFUSE_CFG_ECDSA_P384_L_BLK_S)
+#define EFUSE_CFG_ECDSA_P384_L_BLK_V  0x0000000FU
+#define EFUSE_CFG_ECDSA_P384_L_BLK_S  8
+/** EFUSE_CFG_ECDSA_P384_H_BLK : R/W; bitpos: [15:12]; default: 0;
+ *  Configures which block to use for ECDSA P256 key high part output.
+ */
+#define EFUSE_CFG_ECDSA_P384_H_BLK    0x0000000FU
+#define EFUSE_CFG_ECDSA_P384_H_BLK_M  (EFUSE_CFG_ECDSA_P384_H_BLK_V << EFUSE_CFG_ECDSA_P384_H_BLK_S)
+#define EFUSE_CFG_ECDSA_P384_H_BLK_V  0x0000000FU
+#define EFUSE_CFG_ECDSA_P384_H_BLK_S  12
+/** EFUSE_CUR_ECDSA_P192_BLK : RO; bitpos: [19:16]; default: 0;
+ *  Represents which block is used for ECDSA P192 key output.
+ */
+#define EFUSE_CUR_ECDSA_P192_BLK    0x0000000FU
+#define EFUSE_CUR_ECDSA_P192_BLK_M  (EFUSE_CUR_ECDSA_P192_BLK_V << EFUSE_CUR_ECDSA_P192_BLK_S)
+#define EFUSE_CUR_ECDSA_P192_BLK_V  0x0000000FU
+#define EFUSE_CUR_ECDSA_P192_BLK_S  16
+/** EFUSE_CUR_ECDSA_P256_BLK : RO; bitpos: [23:20]; default: 0;
+ *  Represents which block is used for ECDSA P256 key output.
+ */
+#define EFUSE_CUR_ECDSA_P256_BLK    0x0000000FU
+#define EFUSE_CUR_ECDSA_P256_BLK_M  (EFUSE_CUR_ECDSA_P256_BLK_V << EFUSE_CUR_ECDSA_P256_BLK_S)
+#define EFUSE_CUR_ECDSA_P256_BLK_V  0x0000000FU
+#define EFUSE_CUR_ECDSA_P256_BLK_S  20
+/** EFUSE_CUR_ECDSA_P384_L_BLK : RO; bitpos: [27:24]; default: 0;
+ *  Represents which block is used for ECDSA P384 key low part output.
+ */
+#define EFUSE_CUR_ECDSA_P384_L_BLK    0x0000000FU
+#define EFUSE_CUR_ECDSA_P384_L_BLK_M  (EFUSE_CUR_ECDSA_P384_L_BLK_V << EFUSE_CUR_ECDSA_P384_L_BLK_S)
+#define EFUSE_CUR_ECDSA_P384_L_BLK_V  0x0000000FU
+#define EFUSE_CUR_ECDSA_P384_L_BLK_S  24
+/** EFUSE_CUR_ECDSA_P384_H_BLK : RO; bitpos: [31:28]; default: 0;
+ *  Represents which block is used for ECDSA P384 key high part output.
+ */
+#define EFUSE_CUR_ECDSA_P384_H_BLK    0x0000000FU
+#define EFUSE_CUR_ECDSA_P384_H_BLK_M  (EFUSE_CUR_ECDSA_P384_H_BLK_V << EFUSE_CUR_ECDSA_P384_H_BLK_S)
+#define EFUSE_CUR_ECDSA_P384_H_BLK_V  0x0000000FU
+#define EFUSE_CUR_ECDSA_P384_H_BLK_S  28
 
 /** EFUSE_RD_RS_ERR0_REG register
- *  Programming error record register 0 of BLOCK1-10.
+ *  Represents rd_rs_data_err
  */
 #define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
-/** EFUSE_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_MAC_SYS_ERR_NUM    0x00000007U
-#define EFUSE_MAC_SYS_ERR_NUM_M  (EFUSE_MAC_SYS_ERR_NUM_V << EFUSE_MAC_SYS_ERR_NUM_S)
-#define EFUSE_MAC_SYS_ERR_NUM_V  0x00000007U
-#define EFUSE_MAC_SYS_ERR_NUM_S  0
-/** EFUSE_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0;
- *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_MAC_SYS_FAIL    (BIT(3))
-#define EFUSE_MAC_SYS_FAIL_M  (EFUSE_MAC_SYS_FAIL_V << EFUSE_MAC_SYS_FAIL_S)
-#define EFUSE_MAC_SYS_FAIL_V  0x00000001U
-#define EFUSE_MAC_SYS_FAIL_S  3
-/** EFUSE_SYS_PART1_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_SYS_PART1_ERR_NUM    0x00000007U
-#define EFUSE_SYS_PART1_ERR_NUM_M  (EFUSE_SYS_PART1_ERR_NUM_V << EFUSE_SYS_PART1_ERR_NUM_S)
-#define EFUSE_SYS_PART1_ERR_NUM_V  0x00000007U
-#define EFUSE_SYS_PART1_ERR_NUM_S  4
-/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0;
- *  0: Means no failure and that the data of system part1 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_SYS_PART1_FAIL    (BIT(7))
-#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
-#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
-#define EFUSE_SYS_PART1_FAIL_S  7
-/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
-#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
-#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_USR_DATA_ERR_NUM_S  8
-/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
- *  0: Means no failure and that the user data is reliable 1: Means that programming
- *  user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_USR_DATA_FAIL    (BIT(11))
-#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
-#define EFUSE_USR_DATA_FAIL_V  0x00000001U
-#define EFUSE_USR_DATA_FAIL_S  11
-/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY0_ERR_NUM    0x00000007U
-#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
-#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY0_ERR_NUM_S  12
-/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0;
- *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
- *  key0 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY0_FAIL    (BIT(15))
-#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
-#define EFUSE_KEY0_FAIL_V  0x00000001U
-#define EFUSE_KEY0_FAIL_S  15
-/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY1_ERR_NUM    0x00000007U
-#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
-#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY1_ERR_NUM_S  16
-/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0;
- *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
- *  key1 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY1_FAIL    (BIT(19))
-#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
-#define EFUSE_KEY1_FAIL_V  0x00000001U
-#define EFUSE_KEY1_FAIL_S  19
-/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY2_ERR_NUM    0x00000007U
-#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
-#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY2_ERR_NUM_S  20
-/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0;
- *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
- *  key2 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY2_FAIL    (BIT(23))
-#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
-#define EFUSE_KEY2_FAIL_V  0x00000001U
-#define EFUSE_KEY2_FAIL_S  23
-/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY3_ERR_NUM    0x00000007U
-#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
-#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY3_ERR_NUM_S  24
-/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0;
- *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
- *  key3 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY3_FAIL    (BIT(27))
-#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
-#define EFUSE_KEY3_FAIL_V  0x00000001U
-#define EFUSE_KEY3_FAIL_S  27
-/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY4_ERR_NUM    0x00000007U
-#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
-#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY4_ERR_NUM_S  28
-/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0;
- *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
- *  key4 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY4_FAIL    (BIT(31))
-#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
-#define EFUSE_KEY4_FAIL_V  0x00000001U
-#define EFUSE_KEY4_FAIL_S  31
+/** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS_ERR_NUM    0x00000007U
+#define EFUSE_RD_MAC_SYS_ERR_NUM_M  (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S)
+#define EFUSE_RD_MAC_SYS_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_MAC_SYS_ERR_NUM_S  0
+/** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number
+ *  of error bytes is over 6.
+ */
+#define EFUSE_RD_MAC_SYS_FAIL    (BIT(3))
+#define EFUSE_RD_MAC_SYS_FAIL_M  (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S)
+#define EFUSE_RD_MAC_SYS_FAIL_V  0x00000001U
+#define EFUSE_RD_MAC_SYS_FAIL_S  3
+/** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_sys_part1_data
+ */
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M  (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S)
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S  4
+/** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed
+ *  and the number of error bytes is over 6.
+ */
+#define EFUSE_RD_SYS_PART1_DATA_FAIL    (BIT(7))
+#define EFUSE_RD_SYS_PART1_DATA_FAIL_M  (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S)
+#define EFUSE_RD_SYS_PART1_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_SYS_PART1_DATA_FAIL_S  7
+/** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_usr_data
+ */
+#define EFUSE_RD_USR_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_USR_DATA_ERR_NUM_M  (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S)
+#define EFUSE_RD_USR_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_USR_DATA_ERR_NUM_S  8
+/** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_USR_DATA_FAIL    (BIT(11))
+#define EFUSE_RD_USR_DATA_FAIL_M  (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S)
+#define EFUSE_RD_USR_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_USR_DATA_FAIL_S  11
+/** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key0_data
+ */
+#define EFUSE_RD_KEY0_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY0_DATA_ERR_NUM_M  (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY0_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY0_DATA_ERR_NUM_S  12
+/** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY0_DATA_FAIL    (BIT(15))
+#define EFUSE_RD_KEY0_DATA_FAIL_M  (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S)
+#define EFUSE_RD_KEY0_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY0_DATA_FAIL_S  15
+/** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key1_data
+ */
+#define EFUSE_RD_KEY1_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY1_DATA_ERR_NUM_M  (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY1_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY1_DATA_ERR_NUM_S  16
+/** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY1_DATA_FAIL    (BIT(19))
+#define EFUSE_RD_KEY1_DATA_FAIL_M  (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S)
+#define EFUSE_RD_KEY1_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY1_DATA_FAIL_S  19
+/** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key2_data
+ */
+#define EFUSE_RD_KEY2_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY2_DATA_ERR_NUM_M  (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY2_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY2_DATA_ERR_NUM_S  20
+/** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY2_DATA_FAIL    (BIT(23))
+#define EFUSE_RD_KEY2_DATA_FAIL_M  (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S)
+#define EFUSE_RD_KEY2_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY2_DATA_FAIL_S  23
+/** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key3_data
+ */
+#define EFUSE_RD_KEY3_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY3_DATA_ERR_NUM_M  (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY3_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY3_DATA_ERR_NUM_S  24
+/** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY3_DATA_FAIL    (BIT(27))
+#define EFUSE_RD_KEY3_DATA_FAIL_M  (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S)
+#define EFUSE_RD_KEY3_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY3_DATA_FAIL_S  27
+/** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key4_data
+ */
+#define EFUSE_RD_KEY4_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY4_DATA_ERR_NUM_M  (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY4_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY4_DATA_ERR_NUM_S  28
+/** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY4_DATA_FAIL    (BIT(31))
+#define EFUSE_RD_KEY4_DATA_FAIL_M  (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S)
+#define EFUSE_RD_KEY4_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY4_DATA_FAIL_S  31
 
 /** EFUSE_RD_RS_ERR1_REG register
- *  Programming error record register 1 of BLOCK1-10.
+ *  Represents rd_rs_data_err
  */
 #define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
-/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY5_ERR_NUM    0x00000007U
-#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
-#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY5_ERR_NUM_S  0
-/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0;
- *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
- *  key5 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY5_FAIL    (BIT(3))
-#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
-#define EFUSE_KEY5_FAIL_V  0x00000001U
-#define EFUSE_KEY5_FAIL_S  3
-/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
-#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
-#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
-#define EFUSE_SYS_PART2_ERR_NUM_S  4
-/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0;
- *  0: Means no failure and that the data of system part2 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_SYS_PART2_FAIL    (BIT(7))
-#define EFUSE_SYS_PART2_FAIL_M  (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S)
-#define EFUSE_SYS_PART2_FAIL_V  0x00000001U
-#define EFUSE_SYS_PART2_FAIL_S  7
+/** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key5_data
+ */
+#define EFUSE_RD_KEY5_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY5_DATA_ERR_NUM_M  (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY5_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY5_DATA_ERR_NUM_S  0
+/** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY5_DATA_FAIL    (BIT(3))
+#define EFUSE_RD_KEY5_DATA_FAIL_M  (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S)
+#define EFUSE_RD_KEY5_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY5_DATA_FAIL_S  3
+/** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_sys_part2_data
+ */
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M  (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S)
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S  4
+/** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed
+ *  and the number of error bytes is over 6.
+ */
+#define EFUSE_RD_SYS_PART2_DATA_FAIL    (BIT(7))
+#define EFUSE_RD_SYS_PART2_DATA_FAIL_M  (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S)
+#define EFUSE_RD_SYS_PART2_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_SYS_PART2_DATA_FAIL_S  7
 
 /** EFUSE_CLK_REG register
  *  eFuse clcok configuration register.
@@ -2754,13 +3029,6 @@ extern "C" {
 #define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
 #define EFUSE_OP_CODE_V  0x0000FFFFU
 #define EFUSE_OP_CODE_S  0
-/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
- *  Configures which block to use for ECDSA key output.
- */
-#define EFUSE_CFG_ECDSA_BLK    0x0000000FU
-#define EFUSE_CFG_ECDSA_BLK_M  (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S)
-#define EFUSE_CFG_ECDSA_BLK_V  0x0000000FU
-#define EFUSE_CFG_ECDSA_BLK_S  16
 
 /** EFUSE_STATUS_REG register
  *  eFuse status register.
@@ -2822,13 +3090,6 @@ extern "C" {
 #define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
 #define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
 #define EFUSE_BLK0_VALID_BIT_CNT_S  10
-/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0;
- *  Indicates which block is used for ECDSA key output.
- */
-#define EFUSE_CUR_ECDSA_BLK    0x0000000FU
-#define EFUSE_CUR_ECDSA_BLK_M  (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S)
-#define EFUSE_CUR_ECDSA_BLK_V  0x0000000FU
-#define EFUSE_CUR_ECDSA_BLK_S  20
 
 /** EFUSE_CMD_REG register
  *  eFuse command register.
@@ -3082,7 +3343,7 @@ extern "C" {
  *  eFuse version register.
  */
 #define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
-/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 36720720;
+/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 38805904;
  *  Stores eFuse version.
  */
 #define EFUSE_DATE    0x0FFFFFFFU
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/efuse_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/efuse_struct.h
index b153ab070f7b..74b58e8abbc5 100644
--- a/components/soc/esp32p4/register/hw_ver3/soc/efuse_struct.h
+++ b/components/soc/esp32p4/register/hw_ver3/soc/efuse_struct.h
@@ -10,162 +10,46 @@
 extern "C" {
 #endif
 
-// TODO: IDF-13421
-
-/** Group: PGM Data Register */
-/** Type of pgm_data0 register
- *  Register 0 that stores data to be programmed.
+/** Group: program_data registers */
+/** Type of pgm_datan register
+ *  Represents pgm_datan
  */
 typedef union {
     struct {
-        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
+        /** pgm_data_n : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the nth 32-bit data to be programmed.
          */
-        uint32_t pgm_data_0:32;
+        uint32_t pgm_data_n:32;
     };
     uint32_t val;
-} efuse_pgm_data0_reg_t;
+} efuse_pgm_datan_reg_t;
 
-/** Type of pgm_data1 register
- *  Register 1 that stores data to be programmed.
+/** Type of pgm_check_valuen register
+ *  Represents pgm_check_valuen
  */
 typedef union {
     struct {
-        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 1st 32-bit data to be programmed.
+        /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the nth RS code to be programmed.
          */
-        uint32_t pgm_data_1:32;
+        uint32_t pgm_rs_data_n:32;
     };
     uint32_t val;
-} efuse_pgm_data1_reg_t;
+} efuse_pgm_check_valuen_reg_t;
 
-/** Type of pgm_data2 register
- *  Register 2 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 2nd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_data2_reg_t;
 
-/** Type of pgm_data3 register
- *  Register 3 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 3rd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_3:32;
-    };
-    uint32_t val;
-} efuse_pgm_data3_reg_t;
-
-/** Type of pgm_data4 register
- *  Register 4 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 4th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_4:32;
-    };
-    uint32_t val;
-} efuse_pgm_data4_reg_t;
-
-/** Type of pgm_data5 register
- *  Register 5 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 5th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_5:32;
-    };
-    uint32_t val;
-} efuse_pgm_data5_reg_t;
-
-/** Type of pgm_data6 register
- *  Register 6 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 6th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_6:32;
-    };
-    uint32_t val;
-} efuse_pgm_data6_reg_t;
-
-/** Type of pgm_data7 register
- *  Register 7 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 7th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_7:32;
-    };
-    uint32_t val;
-} efuse_pgm_data7_reg_t;
-
-/** Type of pgm_check_value0 register
- *  Register 0 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value0_reg_t;
-
-/** Type of pgm_check_value1 register
- *  Register 1 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 1st 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value1_reg_t;
-
-/** Type of pgm_check_value2 register
- *  Register 2 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 2nd 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value2_reg_t;
-
-
-/** Group: ******** Registers */
+/** Group: block0 registers */
 /** Type of rd_wr_dis register
- *  BLOCK0 data register 0.
+ *  Represents rd_wr_dis
  */
 typedef union {
     struct {
         /** wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Represents whether programming of individual eFuse memory bit is disabled or
-         *  enabled. 1: Disabled. 0 Enabled.
+         *  Represents whether programming of individual eFuse memory bit is disabled.  For
+         *  mapping between the bits of this field and the eFuse memory bits, please refer to
+         *  Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}.
+         *  1: Disabled
+         *  0: Enabled
          */
         uint32_t wr_dis:32;
     };
@@ -173,39 +57,39 @@ typedef union {
 } efuse_rd_wr_dis_reg_t;
 
 /** Type of rd_repeat_data0 register
- *  BLOCK0 data register 1.
+ *  Represents rd_repeat_data
  */
 typedef union {
     struct {
         /** rd_dis : RO; bitpos: [6:0]; default: 0;
          *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
-         *  enabled. 1: disabled. 0: enabled.
+         *  enabled.
+         *  1: disabled
+         *  0: enabled
          */
         uint32_t rd_dis:7;
-        /** usb_device_exchg_pins : RO; bitpos: [7]; default: 0;
-         *  Enable usb device exchange pins of D+ and D-.
+        /** recovery_bootloader_flash_sector_0_1 : RO; bitpos: [8:7]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
          */
-        uint32_t usb_device_exchg_pins:1;
-        /** usb_otg11_exchg_pins : RO; bitpos: [8]; default: 0;
-         *  Enable usb otg11 exchange pins of D+ and D-.
-         */
-        uint32_t usb_otg11_exchg_pins:1;
+        uint32_t recovery_bootloader_flash_sector_0_1:2;
         /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
-         *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
-         *  disabled. 0: enabled.
+         *  Set this bit to disable function of usb switch to jtag in module of usb device.
          */
         uint32_t dis_usb_jtag:1;
-        /** powerglitch_en : RO; bitpos: [10]; default: 0;
-         *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
+        /** recovery_bootloader_flash_sector_2_2 : RO; bitpos: [10]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
          */
-        uint32_t powerglitch_en:1;
+        uint32_t recovery_bootloader_flash_sector_2_2:1;
         /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
-         *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+         *  Set this bit to disable USB-Serial-JTAG.
          */
         uint32_t dis_usb_serial_jtag:1;
         /** dis_force_download : RO; bitpos: [12]; default: 0;
-         *  Represents whether the function that forces chip into download mode is disabled or
-         *  enabled. 1: disabled. 0: enabled.
+         *  Set this bit to disable the function that forces chip into download mode.
          */
         uint32_t dis_force_download:1;
         /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
@@ -214,119 +98,135 @@ typedef union {
          */
         uint32_t spi_download_mspi_dis:1;
         /** dis_twai : RO; bitpos: [14]; default: 0;
-         *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
+         *  Set this bit to disable TWAI function.
          */
         uint32_t dis_twai:1;
         /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
-         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
-         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
-         *  is enabled or disabled. 1: enabled. 0: disabled.
+         *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
+         *  strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0.
          */
         uint32_t jtag_sel_enable:1;
         /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
-         *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
-         *  enabled.
+         *  Set odd bits to disable JTAG in the soft way. JTAG can be enabled in HMAC module.
          */
         uint32_t soft_dis_jtag:3;
         /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
-         *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
-         *  enabled.
+         *  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
          */
         uint32_t dis_pad_jtag:1;
         /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
-         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
-         *  mode). 1: disabled. 0: enabled.
+         *  Set this bit to disable flash manual encrypt function (except in SPI boot mode).
          */
         uint32_t dis_download_manual_encrypt:1;
-        /** usb_device_drefh : RO; bitpos: [22:21]; default: 0;
-         *  USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV
-         */
-        uint32_t usb_device_drefh:2;
-        /** usb_otg11_drefh : RO; bitpos: [24:23]; default: 0;
-         *  USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV
+        /** recovery_bootloader_flash_sector_3_6 : RO; bitpos: [24:21]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
          */
-        uint32_t usb_otg11_drefh:2;
+        uint32_t recovery_bootloader_flash_sector_3_6:4;
         /** usb_phy_sel : RO; bitpos: [25]; default: 0;
-         *  TBD
+         *  0: intphy(gpio24/25) <---> usb_device
+         *  1: intphy(26/27) <---> usb_otg11.1: intphy(gpio26/27) <---> usb_device
+         *  1: intphy(24/25) <---> usb_otg11.
          */
         uint32_t usb_phy_sel:1;
-        /** km_huk_gen_state_low : RO; bitpos: [31:26]; default: 0;
-         *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+        /** huk_gen_state : RO; bitpos: [30:26]; default: 0;
+         *  Set the bits to control validation of HUK generate mode. Odd of 1 is invalid, even
          *  of 1 is valid.
          */
-        uint32_t km_huk_gen_state_low:6;
+        uint32_t huk_gen_state:5;
+        /** recovery_bootloader_flash_sector_7_7 : RO; bitpos: [31]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
+         */
+        uint32_t recovery_bootloader_flash_sector_7_7:1;
     };
     uint32_t val;
 } efuse_rd_repeat_data0_reg_t;
 
 /** Type of rd_repeat_data1 register
- *  BLOCK0 data register 2.
+ *  Represents rd_repeat_data
  */
 typedef union {
     struct {
-        /** km_huk_gen_state_high : RO; bitpos: [2:0]; default: 0;
-         *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
-         *  of 1 is valid.
+        /** recovery_bootloader_flash_sector_8_10 : RO; bitpos: [2:0]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
          */
-        uint32_t km_huk_gen_state_high:3;
-        /** km_rnd_switch_cycle : RO; bitpos: [4:3]; default: 0;
-         *  Set bits to control key manager random number switch cycle. 0: control by register.
-         *  1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.
+        uint32_t recovery_bootloader_flash_sector_8_10:3;
+        /** recovery_bootloader_flash_sector_11_11 : RO; bitpos: [3]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
          */
-        uint32_t km_rnd_switch_cycle:2;
+        uint32_t recovery_bootloader_flash_sector_11_11:1;
+        /** km_rnd_switch_cycle : RO; bitpos: [4]; default: 0;
+         *  Set the bits to control key manager random number switch cycle. 0: control by
+         *  register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
+         */
+        uint32_t km_rnd_switch_cycle:1;
         /** km_deploy_only_once : RO; bitpos: [8:5]; default: 0;
-         *  Set each bit to control whether corresponding key can only be deployed once. 1 is
-         *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+         *  EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field:
+         *  {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to
+         *  control whether corresponding key can only be deployed once. 1 is true, 0 is false.
+         *  bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
          */
         uint32_t km_deploy_only_once:4;
         /** force_use_key_manager_key : RO; bitpos: [12:9]; default: 0;
-         *  Set each bit to control whether corresponding key must come from key manager.. 1 is
-         *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form
+         *  one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H,
+         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether
+         *  corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda,
+         *  bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
          */
         uint32_t force_use_key_manager_key:4;
         /** force_disable_sw_init_key : RO; bitpos: [13]; default: 0;
          *  Set this bit to disable software written init key, and force use efuse_init_key.
          */
         uint32_t force_disable_sw_init_key:1;
-        /** xts_key_length_256 : RO; bitpos: [14]; default: 0;
-         *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
+        /** km_xts_key_length_256 : RO; bitpos: [14]; default: 0;
+         *  Set this bit to config flash encryption xts-512 key, else use xts-256 key when
+         *  using the key manager
+         */
+        uint32_t km_xts_key_length_256:1;
+        /** ecc_force_const_time : RO; bitpos: [15]; default: 0;
+         *  Set this bit to permanently turn on ECC const-time mode.
          */
-        uint32_t xts_key_length_256:1;
-        /** rd_reserve_0_79 : RW; bitpos: [15]; default: 0;
+        uint32_t ecc_force_const_time:1;
+        /** rd_reserve_0_80 : RW; bitpos: [16]; default: 0;
          *  Reserved, it was created by set_missed_fields_in_regs func
          */
-        uint32_t rd_reserve_0_79:1;
-        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
-         *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
-         *  selected. 0: not selected.
+        uint32_t rd_reserve_0_80:1;
+        /** wdt_delay_sel : RO; bitpos: [17]; default: 0;
+         *  Select lp wdt timeout threshold at startup = initial timeout value * (2 ^
+         *  (EFUSE_WDT_DELAY_SEL + 1))
          */
-        uint32_t wdt_delay_sel:2;
+        uint32_t wdt_delay_sel:1;
         /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
-         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
-         *  1: enabled. Even number of 1: disabled.
+         *  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
+         *  number of 1: disable.
          */
         uint32_t spi_boot_crypt_cnt:3;
         /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
-         *  Represents whether revoking first secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
+         *  Set this bit to enable revoking first secure boot key.
          */
         uint32_t secure_boot_key_revoke0:1;
         /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
-         *  Represents whether revoking second secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
+         *  Set this bit to enable revoking second secure boot key.
          */
         uint32_t secure_boot_key_revoke1:1;
         /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
-         *  Represents whether revoking third secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
+         *  Set this bit to enable revoking third secure boot key.
          */
         uint32_t secure_boot_key_revoke2:1;
         /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
-         *  Represents the purpose of Key0.
+         *  Purpose of Key0.
          */
         uint32_t key_purpose_0:4;
         /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
-         *  Represents the purpose of Key1.
+         *  Purpose of Key1.
          */
         uint32_t key_purpose_1:4;
     };
@@ -334,62 +234,67 @@ typedef union {
 } efuse_rd_repeat_data1_reg_t;
 
 /** Type of rd_repeat_data2 register
- *  BLOCK0 data register 3.
+ *  Represents rd_repeat_data
  */
 typedef union {
     struct {
         /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
-         *  Represents the purpose of Key2.
+         *  Purpose of Key2.
          */
         uint32_t key_purpose_2:4;
         /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
-         *  Represents the purpose of Key3.
+         *  Purpose of Key3.
          */
         uint32_t key_purpose_3:4;
         /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
-         *  Represents the purpose of Key4.
+         *  Purpose of Key4.
          */
         uint32_t key_purpose_4:4;
         /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
-         *  Represents the purpose of Key5.
+         *  Purpose of Key5.
          */
         uint32_t key_purpose_5:4;
         /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
-         *  Represents the spa secure level by configuring the clock random divide mode.
+         *  Configures the clock random divide mode to determine the dpa secure level
          */
         uint32_t sec_dpa_level:2;
-        /** ecdsa_enable_soft_k : RO; bitpos: [18]; default: 0;
-         *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
-         *  0: not force used.
+        /** rd_reserve_0_114 : RW; bitpos: [18]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
          */
-        uint32_t ecdsa_enable_soft_k:1;
-        /** crypt_dpa_enable : RO; bitpos: [19]; default: 1;
-         *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
+        uint32_t rd_reserve_0_114:1;
+        /** xts_dpa_clk_enable : RO; bitpos: [19]; default: 0;
+         *  Sets this bit to enable xts clock anti-dpa attack function.
          */
-        uint32_t crypt_dpa_enable:1;
+        uint32_t xts_dpa_clk_enable:1;
         /** secure_boot_en : RO; bitpos: [20]; default: 0;
-         *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
+         *  Set this bit to enable secure boot.
          */
         uint32_t secure_boot_en:1;
         /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
-         *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
-         *  enabled. 0: disabled.
+         *  Set this bit to enable revoking aggressive secure boot.
          */
         uint32_t secure_boot_aggressive_revoke:1;
-        /** rd_reserve_0_118 : RW; bitpos: [22]; default: 0;
+        /** km_deploy_only_once_h : RO; bitpos: [22]; default: 0;
+         *  EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field:
+         *  {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to
+         *  control whether corresponding key can only be deployed once. 1 is true, 0 is false.
+         *  bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
+         */
+        uint32_t km_deploy_only_once_h:1;
+        /** force_use_key_manager_key_h : RO; bitpos: [23]; default: 0;
+         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form
+         *  one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H,
+         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether
+         *  corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda,
+         *  bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
+         */
+        uint32_t force_use_key_manager_key_h:1;
+        /** rd_reserve_0_120 : RW; bitpos: [25:24]; default: 0;
          *  Reserved, it was created by set_missed_fields_in_regs func
          */
-        uint32_t rd_reserve_0_118:1;
-        /** flash_type : RO; bitpos: [23]; default: 0;
-         *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
-         */
-        uint32_t flash_type:1;
-        /** flash_page_size : RO; bitpos: [25:24]; default: 0;
-         *  Set flash page size.
-         */
-        uint32_t flash_page_size:2;
+        uint32_t rd_reserve_0_120:2;
         /** flash_ecc_en : RO; bitpos: [26]; default: 0;
-         *  Set this bit to enable ecc for flash boot.
+         *  Set this bit to enable ECC for flash boot.
          */
         uint32_t flash_ecc_en:1;
         /** dis_usb_otg_download_mode : RO; bitpos: [27]; default: 0;
@@ -397,9 +302,9 @@ typedef union {
          */
         uint32_t dis_usb_otg_download_mode:1;
         /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
-         *  Represents the flash waiting time after power-up, in unit of ms. When the value
-         *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
-         *  is 2 times the programmed value.
+         *  Configures flash waiting time after power-up, in unit of ms. When the value less
+         *  than 15, the waiting time is the configurable value. Otherwise, the waiting time is
+         *  30.
          */
         uint32_t flash_tpuw:4;
     };
@@ -407,165 +312,196 @@ typedef union {
 } efuse_rd_repeat_data2_reg_t;
 
 /** Type of rd_repeat_data3 register
- *  BLOCK0 data register 4.
+ *  Represents rd_repeat_data
  */
 typedef union {
     struct {
         /** dis_download_mode : RO; bitpos: [0]; default: 0;
-         *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
+         *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7).
          */
         uint32_t dis_download_mode:1;
         /** dis_direct_boot : RO; bitpos: [1]; default: 0;
-         *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
+         *  Set this bit to disable direct boot mode
          */
         uint32_t dis_direct_boot:1;
         /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
-         *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
-         *  0: enabled.
+         *  Set this bit to disable USB-Serial-JTAG print during rom boot.
          */
         uint32_t dis_usb_serial_jtag_rom_print:1;
         /** lock_km_key : RO; bitpos: [3]; default: 0;
-         *  TBD
+         *  set this bit to lock the key manager key after deploy
          */
         uint32_t lock_km_key:1;
         /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
-         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
-         *  disabled. 0: enabled.
+         *  Set this bit to disable the USB-Serial-JTAG download function.
          */
         uint32_t dis_usb_serial_jtag_download_mode:1;
         /** enable_security_download : RO; bitpos: [5]; default: 0;
-         *  Represents whether security download is enabled or disabled. 1: enabled. 0:
-         *  disabled.
+         *  Set this bit to enable security download mode.
          */
         uint32_t enable_security_download:1;
         /** uart_print_control : RO; bitpos: [7:6]; default: 0;
-         *  Represents the type of UART printing. 00: force enable printing. 01: enable
-         *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
-         *  at high level. 11: force disable printing.
+         *  Set the type of UART printing, 00: force enable printing, 01: enable printing when
+         *  GPIO8 is reset at low level, 10: enable printing when GPIO8 is reset at high level,
+         *  11: force disable printing
          */
         uint32_t uart_print_control:2;
         /** force_send_resume : RO; bitpos: [8]; default: 0;
-         *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
-         *  forced. 0:not forced.
+         *  Set this bit to force ROM code to send a resume command during SPI boot.
          */
         uint32_t force_send_resume:1;
         /** secure_version : RO; bitpos: [24:9]; default: 0;
-         *  Represents the version used by ESP-IDF anti-rollback feature.
+         *  Secure version used by ESP-IDF anti-rollback feature.
          */
         uint32_t secure_version:16;
         /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
-         *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
-         *  enabled. 1: disabled. 0: enabled.
+         *  Represents whether secure boot do fast verification on wake is disabled. 0: enabled
+         *  1: disabled
          */
         uint32_t secure_boot_disable_fast_wake:1;
         /** hys_en_pad : RO; bitpos: [26]; default: 0;
-         *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
-         *  enabled. 0:disabled.
+         *  Set bits to enable hysteresis function of PAD0~27
          */
         uint32_t hys_en_pad:1;
-        /** dcdc_vset : RO; bitpos: [31:27]; default: 0;
-         *  Set the dcdc voltage default.
+        /** key_purpose_0_h : RO; bitpos: [27]; default: 0;
+         *  Purpose of Key0. The 5-th bit.
+         */
+        uint32_t key_purpose_0_h:1;
+        /** key_purpose_1_h : RO; bitpos: [28]; default: 0;
+         *  Purpose of Key1. The 5-th bit.
+         */
+        uint32_t key_purpose_1_h:1;
+        /** key_purpose_2_h : RO; bitpos: [29]; default: 0;
+         *  Purpose of Key2. The 5-th bit.
          */
-        uint32_t dcdc_vset:5;
+        uint32_t key_purpose_2_h:1;
+        /** key_purpose_3_h : RO; bitpos: [30]; default: 0;
+         *  Purpose of Key3. The 5-th bit.
+         */
+        uint32_t key_purpose_3_h:1;
+        /** key_purpose_4_h : RO; bitpos: [31]; default: 0;
+         *  Purpose of Key4. The 5-th bit.
+         */
+        uint32_t key_purpose_4_h:1;
     };
     uint32_t val;
 } efuse_rd_repeat_data3_reg_t;
 
 /** Type of rd_repeat_data4 register
- *  BLOCK0 data register 5.
+ *  Represents rd_repeat_data
  */
 typedef union {
     struct {
         /** pxa0_tieh_sel_0 : RO; bitpos: [1:0]; default: 0;
-         *  TBD
+         *  Output LDO VO0 tieh source select. 0: 1'b1 1: sdmmc1 2: reg 3:sdmmc0
          */
         uint32_t pxa0_tieh_sel_0:2;
-        /** pxa0_tieh_sel_1 : RO; bitpos: [3:2]; default: 0;
-         *  TBD.
+        /** pvt_glitch_en : RO; bitpos: [2]; default: 0;
+         *  Represents whether to enable PVT power glitch monitor function.
+         *  1:Enable.
+         *  0:Disable
          */
-        uint32_t pxa0_tieh_sel_1:2;
-        /** pxa0_tieh_sel_2 : RO; bitpos: [5:4]; default: 0;
-         *  TBD.
+        uint32_t pvt_glitch_en:1;
+        /** rd_reserve_0_163 : RW; bitpos: [3]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
          */
-        uint32_t pxa0_tieh_sel_2:2;
-        /** pxa0_tieh_sel_3 : RO; bitpos: [7:6]; default: 0;
-         *  TBD.
+        uint32_t rd_reserve_0_163:1;
+        /** key_purpose_5_h : RO; bitpos: [4]; default: 0;
+         *  Purpose of Key5. The 5-th bit.
          */
-        uint32_t pxa0_tieh_sel_3:2;
-        /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0;
-         *  TBD.
+        uint32_t key_purpose_5_h:1;
+        /** rd_reserve_0_165 : RW; bitpos: [6:5]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
          */
-        uint32_t km_disable_deploy_mode:4;
-        /** usb_device_drefl : RO; bitpos: [13:12]; default: 0;
-         *  Represents the usb device single-end input low threshold, 0.8 V to 1.04 V with step
-         *  of 80 mV.
+        uint32_t rd_reserve_0_165:2;
+        /** km_disable_deploy_mode_h : RO; bitpos: [7]; default: 0;
+         *  EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one
+         *  field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set
+         *  each bit to control whether corresponding key's deploy mode of new value deployment
+         *  is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds,
+         *  bit4:psram
          */
-        uint32_t usb_device_drefl:2;
-        /** usb_otg11_drefl : RO; bitpos: [15:14]; default: 0;
-         *  Represents the usb otg11 single-end input low threshold, 0.8 V to 1.04 V with step
-         *  of 80 mV.
+        uint32_t km_disable_deploy_mode_h:1;
+        /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0;
+         *  EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one
+         *  field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set
+         *  each bit to control whether corresponding key's deploy mode of new value deployment
+         *  is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds,
+         *  bit4:psram
          */
-        uint32_t usb_otg11_drefl:2;
-        /** rd_reserve_0_176 : RW; bitpos: [17:16]; default: 0;
+        uint32_t km_disable_deploy_mode:4;
+        /** rd_reserve_0_172 : RW; bitpos: [15:12]; default: 0;
          *  Reserved, it was created by set_missed_fields_in_regs func
          */
-        uint32_t rd_reserve_0_176:2;
+        uint32_t rd_reserve_0_172:4;
+        /** xts_dpa_pseudo_level : RO; bitpos: [17:16]; default: 0;
+         *  Sets this bit to control the xts pseudo-round anti-dpa attack function. 0:
+         *  controlled by register. 1-3: the higher the value is, the more pseudo-rounds are
+         *  inserted to the xts-aes calculation
+         */
+        uint32_t xts_dpa_pseudo_level:2;
         /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0;
-         *  HP system power source select. 0:LDO. 1: DCDC.
+         *  HP system power source select. 0:LDO  1: DCDC
          */
         uint32_t hp_pwr_src_sel:1;
-        /** dcdc_vset_en : RO; bitpos: [19]; default: 0;
-         *  Select dcdc vset use efuse_dcdc_vset.
+        /** secure_boot_sha384_en : RO; bitpos: [19]; default: 0;
+         *  Represents whether secure boot using SHA-384 is enabled. 0: disable 1: enable
          */
-        uint32_t dcdc_vset_en:1;
+        uint32_t secure_boot_sha384_en:1;
         /** dis_wdt : RO; bitpos: [20]; default: 0;
          *  Set this bit to disable watch dog.
          */
         uint32_t dis_wdt:1;
         /** dis_swd : RO; bitpos: [21]; default: 0;
-         *  Set this bit to disable super-watchdog.
+         *  Set bit to disable super-watchdog
          */
         uint32_t dis_swd:1;
-        /** rd_reserve_0_182 : RW; bitpos: [31:22]; default: 0;
+        /** pvt_glitch_mode : RO; bitpos: [23:22]; default: 0;
+         *  Use to configure glitch mode
+         */
+        uint32_t pvt_glitch_mode:2;
+        /** rd_reserve_0_184 : RW; bitpos: [31:24]; default: 0;
          *  Reserved, it was created by set_missed_fields_in_regs func
          */
-        uint32_t rd_reserve_0_182:10;
+        uint32_t rd_reserve_0_184:8;
     };
     uint32_t val;
 } efuse_rd_repeat_data4_reg_t;
 
-/** Type of rd_mac_sys_0 register
- *  BLOCK1 data register $n.
+
+/** Group: block1 registers */
+/** Type of rd_mac_sys0 register
+ *  Represents rd_mac_sys
  */
 typedef union {
     struct {
         /** mac_0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the low 32 bits of MAC address.
+         *  Represents MAC address. Low 32-bit.
          */
         uint32_t mac_0:32;
     };
     uint32_t val;
-} efuse_rd_mac_sys_0_reg_t;
+} efuse_rd_mac_sys0_reg_t;
 
-/** Type of rd_mac_sys_1 register
- *  BLOCK1 data register $n.
+/** Type of rd_mac_sys1 register
+ *  Represents rd_mac_sys
  */
 typedef union {
     struct {
         /** mac_1 : RO; bitpos: [15:0]; default: 0;
-         *  Stores the high 16 bits of MAC address.
+         *  Represents MAC address. High 16-bit.
          */
         uint32_t mac_1:16;
-        /** reserved_1_16 : RO; bitpos: [31:16]; default: 0;
-         *  Stores the extended bits of MAC address.
+        /** rd_reserve_1_48 : RW; bitpos: [31:16]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
          */
-        uint32_t reserved_1_16:16;
+        uint32_t rd_reserve_1_48:16;
     };
     uint32_t val;
-} efuse_rd_mac_sys_1_reg_t;
+} efuse_rd_mac_sys1_reg_t;
 
-/** Type of rd_mac_sys_2 register
- *  BLOCK1 data register $n.
+/** Type of rd_mac_sys2 register
+ *  Represents rd_mac_sys
  */
 typedef union {
     struct {
@@ -623,10 +559,10 @@ typedef union {
         uint32_t ldo_vo2_dref:4;
     };
     uint32_t val;
-} efuse_rd_mac_sys_2_reg_t;
+} efuse_rd_mac_sys2_reg_t;
 
-/** Type of rd_mac_sys_3 register
- *  BLOCK1 data register $n.
+/** Type of rd_mac_sys3 register
+ *  Represents rd_mac_sys
  */
 typedef union {
     struct {
@@ -656,10 +592,10 @@ typedef union {
         uint32_t ldo_vo4_k:6;
     };
     uint32_t val;
-} efuse_rd_mac_sys_3_reg_t;
+} efuse_rd_mac_sys3_reg_t;
 
-/** Type of rd_mac_sys_4 register
- *  BLOCK1 data register $n.
+/** Type of rd_mac_sys4 register
+ *  Represents rd_mac_sys
  */
 typedef union {
     struct {
@@ -687,20 +623,20 @@ typedef union {
          *  Active LP DBIAS of fixed voltage
          */
         uint32_t active_lp_dbias:4;
-        /** lslp_hp_dbias : R; bitpos: [27:24]; default: 0;
-         *  LSLP HP DBIAS of fixed voltage
+        /** reserved_1_152 : R; bitpos: [27:24]; default: 0;
+         *  reserved
          */
-        uint32_t lslp_hp_dbias:4;
+        uint32_t reserved_1_152:4;
         /** dslp_dbg : R; bitpos: [31:28]; default: 0;
          *  DSLP BDG of fixed voltage
          */
         uint32_t dslp_dbg:4;
     };
     uint32_t val;
-} efuse_rd_mac_sys_4_reg_t;
+} efuse_rd_mac_sys4_reg_t;
 
-/** Type of rd_mac_sys_5 register
- *  BLOCK1 data register $n.
+/** Type of rd_mac_sys5 register
+ *  Represents rd_mac_sys
  */
 typedef union {
     struct {
@@ -712,16 +648,34 @@ typedef union {
          *  DBIAS gap between LP and DCDC
          */
         uint32_t lp_dcdc_dbias_vol_gap:5;
-        /** reserved_1_170 : R; bitpos: [31:10]; default: 0;
+        /** reserved_1_170 : R; bitpos: [10]; default: 0;
          *  reserved
          */
-        uint32_t reserved_1_170:22;
+        uint32_t reserved_1_170:1;
+        /** pvt_400m_bias : R; bitpos: [15:11]; default: 0;
+         *  PVT_DCM_VSET when the CPU is at 400M
+         */
+        uint32_t pvt_400m_bias:5;
+        /** pvt_40m_bias : R; bitpos: [20:16]; default: 0;
+         *  PVT_DCM_VSET corresponding to about 0.9V fixed voltage when the CPU is at 40M
+         */
+        uint32_t pvt_40m_bias:5;
+        /** pvt_100m_bias : R; bitpos: [25:21]; default: 0;
+         *  PVT_DCM_VSET corresponding to about 1.0V fixed voltage when the CPU is at 100M
+         */
+        uint32_t pvt_100m_bias:5;
+        /** reserved_1_186 : R; bitpos: [31:26]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_186:6;
     };
     uint32_t val;
-} efuse_rd_mac_sys_5_reg_t;
+} efuse_rd_mac_sys5_reg_t;
+
 
+/** Group: block2 registers */
 /** Type of rd_sys_part1_data0 register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data0
  */
 typedef union {
     struct {
@@ -734,7 +688,7 @@ typedef union {
 } efuse_rd_sys_part1_data0_reg_t;
 
 /** Type of rd_sys_part1_data1 register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data1
  */
 typedef union {
     struct {
@@ -747,7 +701,7 @@ typedef union {
 } efuse_rd_sys_part1_data1_reg_t;
 
 /** Type of rd_sys_part1_data2 register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data2
  */
 typedef union {
     struct {
@@ -760,7 +714,7 @@ typedef union {
 } efuse_rd_sys_part1_data2_reg_t;
 
 /** Type of rd_sys_part1_data3 register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data3
  */
 typedef union {
     struct {
@@ -773,7 +727,7 @@ typedef union {
 } efuse_rd_sys_part1_data3_reg_t;
 
 /** Type of rd_sys_part1_data4 register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data4
  */
 typedef union {
     struct {
@@ -798,7 +752,7 @@ typedef union {
 } efuse_rd_sys_part1_data4_reg_t;
 
 /** Type of rd_sys_part1_data5 register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data5
  */
 typedef union {
     struct {
@@ -823,7 +777,7 @@ typedef union {
 } efuse_rd_sys_part1_data5_reg_t;
 
 /** Type of rd_sys_part1_data6 register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data6
  */
 typedef union {
     struct {
@@ -848,7 +802,7 @@ typedef union {
 } efuse_rd_sys_part1_data6_reg_t;
 
 /** Type of rd_sys_part1_data7 register
- *  Register $n of BLOCK2 (system).
+ *  Represents rd_sys_part1_data7
  */
 typedef union {
     struct {
@@ -872,13 +826,15 @@ typedef union {
     uint32_t val;
 } efuse_rd_sys_part1_data7_reg_t;
 
+
+/** Group: block3 registers */
 /** Type of rd_usr_data0 register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data0
  */
 typedef union {
     struct {
         /** usr_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of BLOCK3 (user).
+         *  Represents the zeroth 32-bit of block3 (user).
          */
         uint32_t usr_data0:32;
     };
@@ -886,12 +842,12 @@ typedef union {
 } efuse_rd_usr_data0_reg_t;
 
 /** Type of rd_usr_data1 register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data1
  */
 typedef union {
     struct {
         /** usr_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of BLOCK3 (user).
+         *  Represents the zeroth 32-bit of block3 (user).
          */
         uint32_t usr_data1:32;
     };
@@ -899,12 +855,12 @@ typedef union {
 } efuse_rd_usr_data1_reg_t;
 
 /** Type of rd_usr_data2 register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data2
  */
 typedef union {
     struct {
         /** usr_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of BLOCK3 (user).
+         *  Represents the zeroth 32-bit of block3 (user).
          */
         uint32_t usr_data2:32;
     };
@@ -912,12 +868,12 @@ typedef union {
 } efuse_rd_usr_data2_reg_t;
 
 /** Type of rd_usr_data3 register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data3
  */
 typedef union {
     struct {
         /** usr_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of BLOCK3 (user).
+         *  Represents the zeroth 32-bit of block3 (user).
          */
         uint32_t usr_data3:32;
     };
@@ -925,12 +881,12 @@ typedef union {
 } efuse_rd_usr_data3_reg_t;
 
 /** Type of rd_usr_data4 register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data4
  */
 typedef union {
     struct {
         /** usr_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of BLOCK3 (user).
+         *  Represents the zeroth 32-bit of block3 (user).
          */
         uint32_t usr_data4:32;
     };
@@ -938,12 +894,12 @@ typedef union {
 } efuse_rd_usr_data4_reg_t;
 
 /** Type of rd_usr_data5 register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data5
  */
 typedef union {
     struct {
         /** usr_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of BLOCK3 (user).
+         *  Represents the zeroth 32-bit of block3 (user).
          */
         uint32_t usr_data5:32;
     };
@@ -951,7 +907,7 @@ typedef union {
 } efuse_rd_usr_data5_reg_t;
 
 /** Type of rd_usr_data6 register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data6
  */
 typedef union {
     struct {
@@ -968,7 +924,7 @@ typedef union {
 } efuse_rd_usr_data6_reg_t;
 
 /** Type of rd_usr_data7 register
- *  Register $n of BLOCK3 (user).
+ *  Represents rd_usr_data7
  */
 typedef union {
     struct {
@@ -984,632 +940,100 @@ typedef union {
     uint32_t val;
 } efuse_rd_usr_data7_reg_t;
 
-/** Type of rd_key0_data0 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY0.
-         */
-        uint32_t key0_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data0_reg_t;
 
-/** Type of rd_key0_data1 register
- *  Register $n of BLOCK4 (KEY0).
+/** Group: block4 registers */
+/** Type of rd_key0_datan register
+ *  Represents rd_key0_datan
  */
 typedef union {
     struct {
-        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY0.
+        /** key0_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
          */
-        uint32_t key0_data1:32;
+        uint32_t key0_datan:32;
     };
     uint32_t val;
-} efuse_rd_key0_data1_reg_t;
+} efuse_rd_key0_datan_reg_t;
 
-/** Type of rd_key0_data2 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY0.
-         */
-        uint32_t key0_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data2_reg_t;
-
-/** Type of rd_key0_data3 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY0.
-         */
-        uint32_t key0_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data3_reg_t;
-
-/** Type of rd_key0_data4 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY0.
-         */
-        uint32_t key0_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data4_reg_t;
-
-/** Type of rd_key0_data5 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY0.
-         */
-        uint32_t key0_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data5_reg_t;
-
-/** Type of rd_key0_data6 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY0.
-         */
-        uint32_t key0_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data6_reg_t;
-
-/** Type of rd_key0_data7 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY0.
-         */
-        uint32_t key0_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data7_reg_t;
-
-/** Type of rd_key1_data0 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY1.
-         */
-        uint32_t key1_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data0_reg_t;
-
-/** Type of rd_key1_data1 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY1.
-         */
-        uint32_t key1_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data1_reg_t;
-
-/** Type of rd_key1_data2 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY1.
-         */
-        uint32_t key1_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data2_reg_t;
-
-/** Type of rd_key1_data3 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY1.
-         */
-        uint32_t key1_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data3_reg_t;
-
-/** Type of rd_key1_data4 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY1.
-         */
-        uint32_t key1_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data4_reg_t;
 
-/** Type of rd_key1_data5 register
- *  Register $n of BLOCK5 (KEY1).
+/** Group: block5 registers */
+/** Type of rd_key1_datan register
+ *  Represents rd_key1_datan
  */
 typedef union {
     struct {
-        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY1.
+        /** key1_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
          */
-        uint32_t key1_data5:32;
+        uint32_t key1_datan:32;
     };
     uint32_t val;
-} efuse_rd_key1_data5_reg_t;
+} efuse_rd_key1_datan_reg_t;
 
-/** Type of rd_key1_data6 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY1.
-         */
-        uint32_t key1_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data6_reg_t;
 
-/** Type of rd_key1_data7 register
- *  Register $n of BLOCK5 (KEY1).
+/** Group: block6 registers */
+/** Type of rd_key2_datan register
+ *  Represents rd_key2_datan
  */
 typedef union {
     struct {
-        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY1.
+        /** key2_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
          */
-        uint32_t key1_data7:32;
+        uint32_t key2_datan:32;
     };
     uint32_t val;
-} efuse_rd_key1_data7_reg_t;
+} efuse_rd_key2_datan_reg_t;
 
-/** Type of rd_key2_data0 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY2.
-         */
-        uint32_t key2_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data0_reg_t;
 
-/** Type of rd_key2_data1 register
- *  Register $n of BLOCK6 (KEY2).
+/** Group: block7 registers */
+/** Type of rd_key3_datan register
+ *  Represents rd_key3_datan
  */
 typedef union {
     struct {
-        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY2.
+        /** key3_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
          */
-        uint32_t key2_data1:32;
+        uint32_t key3_datan:32;
     };
     uint32_t val;
-} efuse_rd_key2_data1_reg_t;
+} efuse_rd_key3_datan_reg_t;
 
-/** Type of rd_key2_data2 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY2.
-         */
-        uint32_t key2_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data2_reg_t;
 
-/** Type of rd_key2_data3 register
- *  Register $n of BLOCK6 (KEY2).
+/** Group: block8 registers */
+/** Type of rd_key4_datan register
+ *  Represents rd_key4_datan
  */
 typedef union {
     struct {
-        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY2.
+        /** key4_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
          */
-        uint32_t key2_data3:32;
+        uint32_t key4_datan:32;
     };
     uint32_t val;
-} efuse_rd_key2_data3_reg_t;
+} efuse_rd_key4_datan_reg_t;
 
-/** Type of rd_key2_data4 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY2.
-         */
-        uint32_t key2_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data4_reg_t;
 
-/** Type of rd_key2_data5 register
- *  Register $n of BLOCK6 (KEY2).
+/** Group: block9 registers */
+/** Type of rd_key5_datan register
+ *  Represents rd_key5_datan
  */
 typedef union {
     struct {
-        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY2.
+        /** key5_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
          */
-        uint32_t key2_data5:32;
+        uint32_t key5_datan:32;
     };
     uint32_t val;
-} efuse_rd_key2_data5_reg_t;
+} efuse_rd_key5_datan_reg_t;
 
-/** Type of rd_key2_data6 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY2.
-         */
-        uint32_t key2_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data6_reg_t;
-
-/** Type of rd_key2_data7 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY2.
-         */
-        uint32_t key2_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data7_reg_t;
-
-/** Type of rd_key3_data0 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY3.
-         */
-        uint32_t key3_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data0_reg_t;
-
-/** Type of rd_key3_data1 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY3.
-         */
-        uint32_t key3_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data1_reg_t;
-
-/** Type of rd_key3_data2 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY3.
-         */
-        uint32_t key3_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data2_reg_t;
-
-/** Type of rd_key3_data3 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY3.
-         */
-        uint32_t key3_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data3_reg_t;
-
-/** Type of rd_key3_data4 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY3.
-         */
-        uint32_t key3_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data4_reg_t;
-
-/** Type of rd_key3_data5 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY3.
-         */
-        uint32_t key3_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data5_reg_t;
-
-/** Type of rd_key3_data6 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY3.
-         */
-        uint32_t key3_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data6_reg_t;
-
-/** Type of rd_key3_data7 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY3.
-         */
-        uint32_t key3_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data7_reg_t;
-
-/** Type of rd_key4_data0 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY4.
-         */
-        uint32_t key4_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data0_reg_t;
-
-/** Type of rd_key4_data1 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY4.
-         */
-        uint32_t key4_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data1_reg_t;
-
-/** Type of rd_key4_data2 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY4.
-         */
-        uint32_t key4_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data2_reg_t;
-
-/** Type of rd_key4_data3 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY4.
-         */
-        uint32_t key4_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data3_reg_t;
-
-/** Type of rd_key4_data4 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY4.
-         */
-        uint32_t key4_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data4_reg_t;
-
-/** Type of rd_key4_data5 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY4.
-         */
-        uint32_t key4_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data5_reg_t;
-
-/** Type of rd_key4_data6 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY4.
-         */
-        uint32_t key4_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data6_reg_t;
-
-/** Type of rd_key4_data7 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY4.
-         */
-        uint32_t key4_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data7_reg_t;
-
-/** Type of rd_key5_data0 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY5.
-         */
-        uint32_t key5_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data0_reg_t;
-
-/** Type of rd_key5_data1 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY5.
-         */
-        uint32_t key5_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data1_reg_t;
-
-/** Type of rd_key5_data2 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY5.
-         */
-        uint32_t key5_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data2_reg_t;
-
-/** Type of rd_key5_data3 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY5.
-         */
-        uint32_t key5_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data3_reg_t;
-
-/** Type of rd_key5_data4 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY5.
-         */
-        uint32_t key5_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data4_reg_t;
-
-/** Type of rd_key5_data5 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY5.
-         */
-        uint32_t key5_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data5_reg_t;
-
-/** Type of rd_key5_data6 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY5.
-         */
-        uint32_t key5_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data6_reg_t;
-
-/** Type of rd_key5_data7 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY5.
-         */
-        uint32_t key5_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data7_reg_t;
 
+/** Group: block10 registers */
 /** Type of rd_sys_part2_data0 register
- *  Register $n of BLOCK10 (system).
+ *  Represents rd_sys_part2_data
  */
 typedef union {
     struct {
@@ -1634,7 +1058,7 @@ typedef union {
 } efuse_rd_sys_part2_data0_reg_t;
 
 /** Type of rd_sys_part2_data1 register
- *  Register $n of BLOCK9 (KEY5).
+ *  Represents rd_sys_part2_data
  */
 typedef union {
     struct {
@@ -1671,7 +1095,7 @@ typedef union {
 } efuse_rd_sys_part2_data1_reg_t;
 
 /** Type of rd_sys_part2_data2 register
- *  Register $n of BLOCK10 (system).
+ *  Represents rd_sys_part2_data
  */
 typedef union {
     struct {
@@ -1712,29 +1136,29 @@ typedef union {
 } efuse_rd_sys_part2_data2_reg_t;
 
 /** Type of rd_sys_part2_data3 register
- *  Register $n of BLOCK10 (system).
+ *  Represents rd_sys_part2_data
  */
 typedef union {
     struct {
-        /** temperature_sensor : R; bitpos: [8:0]; default: 0;
+        /** temperature_sensor : R; bitpos: [9:0]; default: 0;
          *  Temperature calibration data
          */
-        uint32_t temperature_sensor:9;
-        /** reserved_10_105 : R; bitpos: [31:9]; default: 0;
+        uint32_t temperature_sensor:10;
+        /** reserved_10_106 : R; bitpos: [31:10]; default: 0;
          *  reserved
          */
-        uint32_t reserved_10_105:23;
+        uint32_t reserved_10_106:22;
     };
     uint32_t val;
 } efuse_rd_sys_part2_data3_reg_t;
 
 /** Type of rd_sys_part2_data4 register
- *  Register $n of BLOCK10 (system).
+ *  Represents rd_sys_part2_data
  */
 typedef union {
     struct {
         /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
+         *  Represents the fourth 32-bit of second part of system data.
          */
         uint32_t sys_data_part2_4:32;
     };
@@ -1742,12 +1166,12 @@ typedef union {
 } efuse_rd_sys_part2_data4_reg_t;
 
 /** Type of rd_sys_part2_data5 register
- *  Register $n of BLOCK10 (system).
+ *  Represents rd_sys_part2_data
  */
 typedef union {
     struct {
         /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
+         *  Represents the fifth 32-bit of second part of system data.
          */
         uint32_t sys_data_part2_5:32;
     };
@@ -1755,457 +1179,595 @@ typedef union {
 } efuse_rd_sys_part2_data5_reg_t;
 
 /** Type of rd_sys_part2_data6 register
- *  Register $n of BLOCK10 (system).
+ *  Represents rd_sys_part2_data
  */
 typedef union {
     struct {
-        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
+        /** pvt_limit : RO; bitpos: [15:0]; default: 0;
+         *  Power glitch monitor threthold.
+         */
+        uint32_t pvt_limit:16;
+        /** pvt_pump_limit : RO; bitpos: [23:16]; default: 0;
+         *  Use to configure voltage monitor limit for charge pump
          */
-        uint32_t sys_data_part2_6:32;
+        uint32_t pvt_pump_limit:8;
+        /** pvt_cell_select : RO; bitpos: [30:24]; default: 0;
+         *  Power glitch monitor PVT cell select.
+         */
+        uint32_t pvt_cell_select:7;
+        /** rd_reserve_10_223 : RW; bitpos: [31]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_10_223:1;
     };
     uint32_t val;
 } efuse_rd_sys_part2_data6_reg_t;
 
 /** Type of rd_sys_part2_data7 register
- *  Register $n of BLOCK10 (system).
+ *  Represents rd_sys_part2_data
  */
 typedef union {
     struct {
-        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
+        /** pump_drv : RO; bitpos: [3:0]; default: 0;
+         *  Use to configure charge pump voltage gain
+         */
+        uint32_t pump_drv:4;
+        /** usb_device_exchg_pins : RO; bitpos: [4]; default: 0;
+         *  Enable usb device exchange pins of D+ and D-.
+         */
+        uint32_t usb_device_exchg_pins:1;
+        /** usb_otg11_exchg_pins : RO; bitpos: [5]; default: 0;
+         *  Enable usb otg11 exchange pins of D+ and D-.
+         */
+        uint32_t usb_otg11_exchg_pins:1;
+        /** usb_device_drefh : RO; bitpos: [7:6]; default: 0;
+         *  usb intphy of usb device single-end input high threshold, 1.76V to 2V. step by 80mV.
+         */
+        uint32_t usb_device_drefh:2;
+        /** usb_otg11_drefh : RO; bitpos: [9:8]; default: 0;
+         *  usb intphy of usb otg11 single-end input high threshold, 1.76V to 2V. step by 80mV.
          */
-        uint32_t sys_data_part2_7:32;
+        uint32_t usb_otg11_drefh:2;
+        /** usb_device_drefl : RO; bitpos: [11:10]; default: 0;
+         *  usb intphy of usb device single-end input low threshold, 0.8V to 1.04V. step by
+         *  80mV.
+         */
+        uint32_t usb_device_drefl:2;
+        /** usb_otg11_drefl : RO; bitpos: [13:12]; default: 0;
+         *  usb intphy of usb otg11 single-end input low threshold, 0.8V to 1.04V. step by 80mV.
+         */
+        uint32_t usb_otg11_drefl:2;
+        /** rd_reserve_10_238 : RW; bitpos: [31:14]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_10_238:18;
     };
     uint32_t val;
 } efuse_rd_sys_part2_data7_reg_t;
 
-/** Type of rd_repeat_err0 register
- *  Programming error record register 0 of BLOCK0.
+
+/** Group: block0 error report registers */
+/** Type of rd_repeat_data_err0 register
+ *  Represents rd_repeat_data_err
  */
 typedef union {
     struct {
         /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
-         *  Indicates a programming error of RD_DIS.
+         *  Represents the programming error of EFUSE_RD_DIS
          */
         uint32_t rd_dis_err:7;
-        /** dis_usb_device_exchg_pins_err : RO; bitpos: [7]; default: 0;
-         *  Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.
-         */
-        uint32_t dis_usb_device_exchg_pins_err:1;
-        /** dis_usb_otg11_exchg_pins_err : RO; bitpos: [8]; default: 0;
-         *  Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.
+        /** recovery_bootloader_flash_sector_0_1_err : RO; bitpos: [8:7]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1
          */
-        uint32_t dis_usb_otg11_exchg_pins_err:1;
+        uint32_t recovery_bootloader_flash_sector_0_1_err:2;
         /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
-         *  Indicates a programming error of DIS_USB_JTAG.
+         *  Represents the programming error of EFUSE_DIS_USB_JTAG
          */
         uint32_t dis_usb_jtag_err:1;
-        /** powerglitch_en_err : RO; bitpos: [10]; default: 0;
-         *  Indicates a programming error of POWERGLITCH_EN.
+        /** recovery_bootloader_flash_sector_2_2_err : RO; bitpos: [10]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2
          */
-        uint32_t powerglitch_en_err:1;
+        uint32_t recovery_bootloader_flash_sector_2_2_err:1;
         /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0;
-         *  Indicates a programming error of DIS_USB_SERIAL_JTAG.
+         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG
          */
         uint32_t dis_usb_serial_jtag_err:1;
         /** dis_force_download_err : RO; bitpos: [12]; default: 0;
-         *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
+         *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
          */
         uint32_t dis_force_download_err:1;
         /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
-         *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
+         *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
          */
         uint32_t spi_download_mspi_dis_err:1;
         /** dis_twai_err : RO; bitpos: [14]; default: 0;
-         *  Indicates a programming error of DIS_TWAI.
+         *  Represents the programming error of EFUSE_DIS_TWAI
          */
         uint32_t dis_twai_err:1;
         /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
-         *  Indicates a programming error of JTAG_SEL_ENABLE.
+         *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
          */
         uint32_t jtag_sel_enable_err:1;
         /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
-         *  Indicates a programming error of SOFT_DIS_JTAG.
+         *  Represents the programming error of EFUSE_SOFT_DIS_JTAG
          */
         uint32_t soft_dis_jtag_err:3;
         /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
-         *  Indicates a programming error of DIS_PAD_JTAG.
+         *  Represents the programming error of EFUSE_DIS_PAD_JTAG
          */
         uint32_t dis_pad_jtag_err:1;
         /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
-         *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
          */
         uint32_t dis_download_manual_encrypt_err:1;
-        /** usb_device_drefh_err : RO; bitpos: [22:21]; default: 0;
-         *  Indicates a programming error of USB_DEVICE_DREFH.
+        /** recovery_bootloader_flash_sector_3_6_err : RO; bitpos: [24:21]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6
          */
-        uint32_t usb_device_drefh_err:2;
-        /** usb_otg11_drefh_err : RO; bitpos: [24:23]; default: 0;
-         *  Indicates a programming error of USB_OTG11_DREFH.
-         */
-        uint32_t usb_otg11_drefh_err:2;
+        uint32_t recovery_bootloader_flash_sector_3_6_err:4;
         /** usb_phy_sel_err : RO; bitpos: [25]; default: 0;
-         *  Indicates a programming error of USB_PHY_SEL.
+         *  Represents the programming error of EFUSE_USB_PHY_SEL
          */
         uint32_t usb_phy_sel_err:1;
-        /** huk_gen_state_low_err : RO; bitpos: [31:26]; default: 0;
-         *  Indicates a programming error of HUK_GEN_STATE_LOW.
+        /** huk_gen_state_err : RO; bitpos: [30:26]; default: 0;
+         *  Represents the programming error of EFUSE_HUK_GEN_STATE
+         */
+        uint32_t huk_gen_state_err:5;
+        /** recovery_bootloader_flash_sector_7_7_err : RO; bitpos: [31]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7
          */
-        uint32_t huk_gen_state_low_err:6;
+        uint32_t recovery_bootloader_flash_sector_7_7_err:1;
     };
     uint32_t val;
-} efuse_rd_repeat_err0_reg_t;
+} efuse_rd_repeat_data_err0_reg_t;
 
-/** Type of rd_repeat_err1 register
- *  Programming error record register 1 of BLOCK0.
+/** Type of rd_repeat_data_err1 register
+ *  Represents rd_repeat_data_err
  */
 typedef union {
     struct {
-        /** km_huk_gen_state_high_err : RO; bitpos: [2:0]; default: 0;
-         *  Indicates a programming error of HUK_GEN_STATE_HIGH.
+        /** recovery_bootloader_flash_sector_8_10_err : RO; bitpos: [2:0]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10
          */
-        uint32_t km_huk_gen_state_high_err:3;
-        /** km_rnd_switch_cycle_err : RO; bitpos: [4:3]; default: 0;
-         *  Indicates a programming error of KM_RND_SWITCH_CYCLE.
+        uint32_t recovery_bootloader_flash_sector_8_10_err:3;
+        /** recovery_bootloader_flash_sector_11_11_err : RO; bitpos: [3]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11
          */
-        uint32_t km_rnd_switch_cycle_err:2;
+        uint32_t recovery_bootloader_flash_sector_11_11_err:1;
+        /** km_rnd_switch_cycle_err : RO; bitpos: [4]; default: 0;
+         *  Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE
+         */
+        uint32_t km_rnd_switch_cycle_err:1;
         /** km_deploy_only_once_err : RO; bitpos: [8:5]; default: 0;
-         *  Indicates a programming error of KM_DEPLOY_ONLY_ONCE.
+         *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE
          */
         uint32_t km_deploy_only_once_err:4;
         /** force_use_key_manager_key_err : RO; bitpos: [12:9]; default: 0;
-         *  Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.
+         *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY
          */
         uint32_t force_use_key_manager_key_err:4;
         /** force_disable_sw_init_key_err : RO; bitpos: [13]; default: 0;
-         *  Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.
+         *  Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY
          */
         uint32_t force_disable_sw_init_key_err:1;
-        /** xts_key_length_256_err : RO; bitpos: [14]; default: 0;
-         *  Indicates a programming error of XTS_KEY_LENGTH_256.
+        /** km_xts_key_length_256_err : RO; bitpos: [14]; default: 0;
+         *  Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256
+         */
+        uint32_t km_xts_key_length_256_err:1;
+        /** ecc_force_const_time_err : RO; bitpos: [15]; default: 0;
+         *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
          */
-        uint32_t xts_key_length_256_err:1;
-        uint32_t reserved_15:1;
-        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
-         *  Indicates a programming error of WDT_DELAY_SEL.
+        uint32_t ecc_force_const_time_err:1;
+        uint32_t reserved_16:1;
+        /** wdt_delay_sel_err : RO; bitpos: [17]; default: 0;
+         *  Represents the programming error of EFUSE_WDT_DELAY_SEL
          */
-        uint32_t wdt_delay_sel_err:2;
+        uint32_t wdt_delay_sel_err:1;
         /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
-         *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
+         *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
          */
         uint32_t spi_boot_crypt_cnt_err:3;
         /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0
          */
         uint32_t secure_boot_key_revoke0_err:1;
         /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1
          */
         uint32_t secure_boot_key_revoke1_err:1;
         /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2
          */
         uint32_t secure_boot_key_revoke2_err:1;
         /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_0.
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_0
          */
         uint32_t key_purpose_0_err:4;
         /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_1.
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_1
          */
         uint32_t key_purpose_1_err:4;
     };
     uint32_t val;
-} efuse_rd_repeat_err1_reg_t;
+} efuse_rd_repeat_data_err1_reg_t;
 
-/** Type of rd_repeat_err2 register
- *  Programming error record register 2 of BLOCK0.
+/** Type of rd_repeat_data_err2 register
+ *  Represents rd_repeat_data_err
  */
 typedef union {
     struct {
         /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_2.
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_2
          */
         uint32_t key_purpose_2_err:4;
         /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_3.
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_3
          */
         uint32_t key_purpose_3_err:4;
         /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_4.
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_4
          */
         uint32_t key_purpose_4_err:4;
         /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_5.
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_5
          */
         uint32_t key_purpose_5_err:4;
         /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
-         *  Indicates a programming error of SEC_DPA_LEVEL.
+         *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
          */
         uint32_t sec_dpa_level_err:2;
-        /** ecdsa_enable_soft_k_err : RO; bitpos: [18]; default: 0;
-         *  Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.
-         */
-        uint32_t ecdsa_enable_soft_k_err:1;
-        /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0;
-         *  Indicates a programming error of CRYPT_DPA_ENABLE.
+        uint32_t reserved_18:1;
+        /** xts_dpa_clk_enable_err : RO; bitpos: [19]; default: 0;
+         *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
          */
-        uint32_t crypt_dpa_enable_err:1;
+        uint32_t xts_dpa_clk_enable_err:1;
         /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_EN.
+         *  Represents the programming error of EFUSE_SECURE_BOOT_EN
          */
         uint32_t secure_boot_en_err:1;
         /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
+         *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
          */
         uint32_t secure_boot_aggressive_revoke_err:1;
-        uint32_t reserved_22:1;
-        /** flash_type_err : RO; bitpos: [23]; default: 0;
-         *  Indicates a programming error of FLASH_TYPE.
+        /** km_deploy_only_once_h_err : RO; bitpos: [22]; default: 0;
+         *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE_H
          */
-        uint32_t flash_type_err:1;
-        /** flash_page_size_err : RO; bitpos: [25:24]; default: 0;
-         *  Indicates a programming error of FLASH_PAGE_SIZE.
+        uint32_t km_deploy_only_once_h_err:1;
+        /** force_use_key_manager_key_h_err : RO; bitpos: [23]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY_H
          */
-        uint32_t flash_page_size_err:2;
+        uint32_t force_use_key_manager_key_h_err:1;
+        uint32_t reserved_24:2;
         /** flash_ecc_en_err : RO; bitpos: [26]; default: 0;
-         *  Indicates a programming error of FLASH_ECC_EN.
+         *  Represents the programming error of EFUSE_FLASH_ECC_EN
          */
         uint32_t flash_ecc_en_err:1;
         /** dis_usb_otg_download_mode_err : RO; bitpos: [27]; default: 0;
-         *  Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.
+         *  Represents the programming error of EFUSE_DIS_USB_OTG_DOWNLOAD_MODE
          */
         uint32_t dis_usb_otg_download_mode_err:1;
         /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
-         *  Indicates a programming error of FLASH_TPUW.
+         *  Represents the programming error of EFUSE_FLASH_TPUW
          */
         uint32_t flash_tpuw_err:4;
     };
     uint32_t val;
-} efuse_rd_repeat_err2_reg_t;
+} efuse_rd_repeat_data_err2_reg_t;
 
-/** Type of rd_repeat_err3 register
- *  Programming error record register 3 of BLOCK0.
+/** Type of rd_repeat_data_err3 register
+ *  Represents rd_repeat_data_err
  */
 typedef union {
     struct {
         /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
-         *  Indicates a programming error of DIS_DOWNLOAD_MODE.
+         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
          */
         uint32_t dis_download_mode_err:1;
         /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
-         *  Indicates a programming error of DIS_DIRECT_BOOT.
+         *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
          */
         uint32_t dis_direct_boot_err:1;
         /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0;
-         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.
+         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
          */
         uint32_t dis_usb_serial_jtag_rom_print_err:1;
         /** lock_km_key_err : RO; bitpos: [3]; default: 0;
-         *  TBD
+         *  Represents the programming error of EFUSE_LOCK_KM_KEY
          */
         uint32_t lock_km_key_err:1;
         /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
-         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
+         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
          */
         uint32_t dis_usb_serial_jtag_download_mode_err:1;
         /** enable_security_download_err : RO; bitpos: [5]; default: 0;
-         *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
+         *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
          */
         uint32_t enable_security_download_err:1;
         /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
-         *  Indicates a programming error of UART_PRINT_CONTROL.
+         *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
          */
         uint32_t uart_print_control_err:2;
         /** force_send_resume_err : RO; bitpos: [8]; default: 0;
-         *  Indicates a programming error of FORCE_SEND_RESUME.
+         *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
          */
         uint32_t force_send_resume_err:1;
         /** secure_version_err : RO; bitpos: [24:9]; default: 0;
-         *  Indicates a programming error of SECURE VERSION.
+         *  Represents the programming error of EFUSE_SECURE_VERSION
          */
         uint32_t secure_version_err:16;
         /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
+         *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
          */
         uint32_t secure_boot_disable_fast_wake_err:1;
         /** hys_en_pad_err : RO; bitpos: [26]; default: 0;
-         *  Indicates a programming error of HYS_EN_PAD.
+         *  Represents the programming error of EFUSE_HYS_EN_PAD
          */
         uint32_t hys_en_pad_err:1;
-        /** dcdc_vset_err : RO; bitpos: [31:27]; default: 0;
-         *  Indicates a programming error of DCDC_VSET.
+        /** key_purpose_0_h_err : RO; bitpos: [27]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_0_H
          */
-        uint32_t dcdc_vset_err:5;
+        uint32_t key_purpose_0_h_err:1;
+        /** key_purpose_1_h_err : RO; bitpos: [28]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_1_H
+         */
+        uint32_t key_purpose_1_h_err:1;
+        /** key_purpose_2_h_err : RO; bitpos: [29]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_2_H
+         */
+        uint32_t key_purpose_2_h_err:1;
+        /** key_purpose_3_h_err : RO; bitpos: [30]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_3_H
+         */
+        uint32_t key_purpose_3_h_err:1;
+        /** key_purpose_4_h_err : RO; bitpos: [31]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_4_H
+         */
+        uint32_t key_purpose_4_h_err:1;
     };
     uint32_t val;
-} efuse_rd_repeat_err3_reg_t;
+} efuse_rd_repeat_data_err3_reg_t;
 
-/** Type of rd_repeat_err4 register
- *  Programming error record register 4 of BLOCK0.
+/** Type of rd_repeat_data_err4 register
+ *  Represents rd_repeat_data_err
  */
 typedef union {
     struct {
         /** pxa0_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0;
-         *  Indicates a programming error of 0PXA_TIEH_SEL_0.
+         *  Represents the programming error of EFUSE_0PXA_TIEH_SEL_0
          */
         uint32_t pxa0_tieh_sel_0_err:2;
-        /** pxa0_tieh_sel_1_err : RO; bitpos: [3:2]; default: 0;
-         *  Indicates a programming error of 0PXA_TIEH_SEL_1.
+        /** pvt_glitch_en_err : RO; bitpos: [2]; default: 0;
+         *  Represents the programming error of EFUSE_PVT_GLITCH_EN
          */
-        uint32_t pxa0_tieh_sel_1_err:2;
-        /** pxa0_tieh_sel_2_err : RO; bitpos: [5:4]; default: 0;
-         *  Indicates a programming error of 0PXA_TIEH_SEL_2.
+        uint32_t pvt_glitch_en_err:1;
+        uint32_t reserved_3:1;
+        /** key_purpose_5_h_err : RO; bitpos: [4]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_5_H
          */
-        uint32_t pxa0_tieh_sel_2_err:2;
-        /** pxa0_tieh_sel_3_err : RO; bitpos: [7:6]; default: 0;
-         *  Indicates a programming error of 0PXA_TIEH_SEL_3.
+        uint32_t key_purpose_5_h_err:1;
+        uint32_t reserved_5:2;
+        /** km_disable_deploy_mode_h_err : RO; bitpos: [7]; default: 0;
+         *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE_H
          */
-        uint32_t pxa0_tieh_sel_3_err:2;
+        uint32_t km_disable_deploy_mode_h_err:1;
         /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0;
-         *  TBD.
+         *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE
          */
         uint32_t km_disable_deploy_mode_err:4;
-        /** usb_device_drefl_err : RO; bitpos: [13:12]; default: 0;
-         *  Indicates a programming error of USB_DEVICE_DREFL.
+        uint32_t reserved_12:4;
+        /** xts_dpa_pseudo_level_err : RO; bitpos: [17:16]; default: 0;
+         *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
          */
-        uint32_t usb_device_drefl_err:2;
-        /** usb_otg11_drefl_err : RO; bitpos: [15:14]; default: 0;
-         *  Indicates a programming error of USB_OTG11_DREFL.
-         */
-        uint32_t usb_otg11_drefl_err:2;
-        uint32_t reserved_16:2;
+        uint32_t xts_dpa_pseudo_level_err:2;
         /** hp_pwr_src_sel_err : RO; bitpos: [18]; default: 0;
-         *  Indicates a programming error of HP_PWR_SRC_SEL.
+         *  Represents the programming error of EFUSE_HP_PWR_SRC_SEL
          */
         uint32_t hp_pwr_src_sel_err:1;
-        /** dcdc_vset_en_err : RO; bitpos: [19]; default: 0;
-         *  Indicates a programming error of DCDC_VSET_EN.
+        /** secure_boot_sha384_en_err : RO; bitpos: [19]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_SHA384_EN
          */
-        uint32_t dcdc_vset_en_err:1;
+        uint32_t secure_boot_sha384_en_err:1;
         /** dis_wdt_err : RO; bitpos: [20]; default: 0;
-         *  Indicates a programming error of DIS_WDT.
+         *  Represents the programming error of EFUSE_DIS_WDT
          */
         uint32_t dis_wdt_err:1;
         /** dis_swd_err : RO; bitpos: [21]; default: 0;
-         *  Indicates a programming error of DIS_SWD.
+         *  Represents the programming error of EFUSE_DIS_SWD
          */
         uint32_t dis_swd_err:1;
-        uint32_t reserved_22:10;
+        /** pvt_glitch_mode_err : RO; bitpos: [23:22]; default: 0;
+         *  Represents the programming error of EFUSE_PVT_GLITCH_MODE
+         */
+        uint32_t pvt_glitch_mode_err:2;
+        uint32_t reserved_24:8;
     };
     uint32_t val;
-} efuse_rd_repeat_err4_reg_t;
+} efuse_rd_repeat_data_err4_reg_t;
 
-/** Type of rd_rs_err0 register
- *  Programming error record register 0 of BLOCK1-10.
+
+/** Group: EFUSE ECDSA Configure Registers */
+/** Type of ecdsa register
+ *  eFuse status register.
  */
 typedef union {
     struct {
-        /** mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t mac_sys_err_num:3;
-        /** mac_sys_fail : RO; bitpos: [3]; default: 0;
-         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t mac_sys_fail:1;
-        /** sys_part1_err_num : RO; bitpos: [6:4]; default: 0;
-         *  The value of this signal means the number of error bytes.
+        /** cfg_ecdsa_p192_blk : R/W; bitpos: [3:0]; default: 0;
+         *  Configures which block to use for ECDSA P192 key output.
          */
-        uint32_t sys_part1_err_num:3;
-        /** sys_part1_fail : RO; bitpos: [7]; default: 0;
-         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
+        uint32_t cfg_ecdsa_p192_blk:4;
+        /** cfg_ecdsa_p256_blk : R/W; bitpos: [7:4]; default: 0;
+         *  Configures which block to use for ECDSA P256 key output.
          */
-        uint32_t sys_part1_fail:1;
-        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
-         *  The value of this signal means the number of error bytes.
+        uint32_t cfg_ecdsa_p256_blk:4;
+        /** cfg_ecdsa_p384_l_blk : R/W; bitpos: [11:8]; default: 0;
+         *  Configures which block to use for ECDSA P384 key low part output.
          */
-        uint32_t usr_data_err_num:3;
-        /** usr_data_fail : RO; bitpos: [11]; default: 0;
-         *  0: Means no failure and that the user data is reliable 1: Means that programming
-         *  user data failed and the number of error bytes is over 6.
+        uint32_t cfg_ecdsa_p384_l_blk:4;
+        /** cfg_ecdsa_p384_h_blk : R/W; bitpos: [15:12]; default: 0;
+         *  Configures which block to use for ECDSA P256 key high part output.
          */
-        uint32_t usr_data_fail:1;
-        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
-         *  The value of this signal means the number of error bytes.
+        uint32_t cfg_ecdsa_p384_h_blk:4;
+        /** cur_ecdsa_p192_blk : RO; bitpos: [19:16]; default: 0;
+         *  Represents which block is used for ECDSA P192 key output.
          */
-        uint32_t key0_err_num:3;
-        /** key0_fail : RO; bitpos: [15]; default: 0;
-         *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
-         *  key0 failed and the number of error bytes is over 6.
+        uint32_t cur_ecdsa_p192_blk:4;
+        /** cur_ecdsa_p256_blk : RO; bitpos: [23:20]; default: 0;
+         *  Represents which block is used for ECDSA P256 key output.
          */
-        uint32_t key0_fail:1;
-        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
-         *  The value of this signal means the number of error bytes.
+        uint32_t cur_ecdsa_p256_blk:4;
+        /** cur_ecdsa_p384_l_blk : RO; bitpos: [27:24]; default: 0;
+         *  Represents which block is used for ECDSA P384 key low part output.
          */
-        uint32_t key1_err_num:3;
-        /** key1_fail : RO; bitpos: [19]; default: 0;
-         *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
-         *  key1 failed and the number of error bytes is over 6.
+        uint32_t cur_ecdsa_p384_l_blk:4;
+        /** cur_ecdsa_p384_h_blk : RO; bitpos: [31:28]; default: 0;
+         *  Represents which block is used for ECDSA P384 key high part output.
          */
-        uint32_t key1_fail:1;
-        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key2_err_num:3;
-        /** key2_fail : RO; bitpos: [23]; default: 0;
-         *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
-         *  key2 failed and the number of error bytes is over 6.
+        uint32_t cur_ecdsa_p384_h_blk:4;
+    };
+    uint32_t val;
+} efuse_ecdsa_reg_t;
+
+
+/** Group: RS block error report registers */
+/** Type of rd_rs_data_err0 register
+ *  Represents rd_rs_data_err
+ */
+typedef union {
+    struct {
+        /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_mac_sys
          */
-        uint32_t key2_fail:1;
-        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
-         *  The value of this signal means the number of error bytes.
+        uint32_t rd_mac_sys_err_num:3;
+        /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_mac_sys is reliable
+         *  1: Means that programming rd_mac_sys failed and the number of error bytes is over 6.
          */
-        uint32_t key3_err_num:3;
-        /** key3_fail : RO; bitpos: [27]; default: 0;
-         *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
-         *  key3 failed and the number of error bytes is over 6.
+        uint32_t rd_mac_sys_fail:1;
+        /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_sys_part1_data
          */
-        uint32_t key3_fail:1;
-        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
-         *  The value of this signal means the number of error bytes.
+        uint32_t rd_sys_part1_data_err_num:3;
+        /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_sys_part1_data is reliable
+         *  1: Means that programming rd_sys_part1_data failed and the number of error bytes is
+         *  over 6.
          */
-        uint32_t key4_err_num:3;
-        /** key4_fail : RO; bitpos: [31]; default: 0;
-         *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
-         *  key4 failed and the number of error bytes is over 6.
+        uint32_t rd_sys_part1_data_fail:1;
+        /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_usr_data
          */
-        uint32_t key4_fail:1;
-    };
-    uint32_t val;
-} efuse_rd_rs_err0_reg_t;
-
-/** Type of rd_rs_err1 register
- *  Programming error record register 1 of BLOCK1-10.
- */
-typedef union {
-    struct {
-        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
-         *  The value of this signal means the number of error bytes.
+        uint32_t rd_usr_data_err_num:3;
+        /** rd_usr_data_fail : RO; bitpos: [11]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_usr_data is reliable
+         *  1: Means that programming rd_usr_data failed and the number of error bytes is over
+         *  6.
          */
-        uint32_t key5_err_num:3;
-        /** key5_fail : RO; bitpos: [3]; default: 0;
-         *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
-         *  key5 failed and the number of error bytes is over 6.
+        uint32_t rd_usr_data_fail:1;
+        /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key0_data
          */
-        uint32_t key5_fail:1;
-        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
-         *  The value of this signal means the number of error bytes.
+        uint32_t rd_key0_data_err_num:3;
+        /** rd_key0_data_fail : RO; bitpos: [15]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key0_data is reliable
+         *  1: Means that programming rd_key0_data failed and the number of error bytes is over
+         *  6.
          */
-        uint32_t sys_part2_err_num:3;
-        /** sys_part2_fail : RO; bitpos: [7]; default: 0;
-         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
+        uint32_t rd_key0_data_fail:1;
+        /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key1_data
          */
-        uint32_t sys_part2_fail:1;
+        uint32_t rd_key1_data_err_num:3;
+        /** rd_key1_data_fail : RO; bitpos: [19]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key1_data is reliable
+         *  1: Means that programming rd_key1_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key1_data_fail:1;
+        /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key2_data
+         */
+        uint32_t rd_key2_data_err_num:3;
+        /** rd_key2_data_fail : RO; bitpos: [23]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key2_data is reliable
+         *  1: Means that programming rd_key2_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key2_data_fail:1;
+        /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key3_data
+         */
+        uint32_t rd_key3_data_err_num:3;
+        /** rd_key3_data_fail : RO; bitpos: [27]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key3_data is reliable
+         *  1: Means that programming rd_key3_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key3_data_fail:1;
+        /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key4_data
+         */
+        uint32_t rd_key4_data_err_num:3;
+        /** rd_key4_data_fail : RO; bitpos: [31]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key4_data is reliable
+         *  1: Means that programming rd_key4_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key4_data_fail:1;
+    };
+    uint32_t val;
+} efuse_rd_rs_data_err0_reg_t;
+
+/** Type of rd_rs_data_err1 register
+ *  Represents rd_rs_data_err
+ */
+typedef union {
+    struct {
+        /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key5_data
+         */
+        uint32_t rd_key5_data_err_num:3;
+        /** rd_key5_data_fail : RO; bitpos: [3]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key5_data is reliable
+         *  1: Means that programming rd_key5_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key5_data_fail:1;
+        /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_sys_part2_data
+         */
+        uint32_t rd_sys_part2_data_err_num:3;
+        /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_sys_part2_data is reliable
+         *  1: Means that programming rd_sys_part2_data failed and the number of error bytes is
+         *  over 6.
+         */
+        uint32_t rd_sys_part2_data_fail:1;
         uint32_t reserved_8:24;
     };
     uint32_t val;
-} efuse_rd_rs_err1_reg_t;
+} efuse_rd_rs_data_err1_reg_t;
 
+
+/** Group: ******** Registers */
 /** Type of clk register
  *  eFuse clcok configuration register.
  */
@@ -2242,11 +1804,7 @@ typedef union {
          *  0x5A5A:  programming operation command 0x5AA5: read operation command.
          */
         uint32_t op_code:16;
-        /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0;
-         *  Configures which block to use for ECDSA key output.
-         */
-        uint32_t cfg_ecdsa_blk:4;
-        uint32_t reserved_20:12;
+        uint32_t reserved_16:16;
     };
     uint32_t val;
 } efuse_conf_reg_t;
@@ -2288,11 +1846,7 @@ typedef union {
          *  Indicates the number of block valid bit.
          */
         uint32_t blk0_valid_bit_cnt:10;
-        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
-         *  Indicates which block is used for ECDSA key output.
-         */
-        uint32_t cur_ecdsa_blk:4;
-        uint32_t reserved_24:8;
+        uint32_t reserved_20:12;
     };
     uint32_t val;
 } efuse_status_reg_t;
@@ -2515,7 +2069,7 @@ typedef union {
  */
 typedef union {
     struct {
-        /** date : R/W; bitpos: [27:0]; default: 36720720;
+        /** date : R/W; bitpos: [27:0]; default: 38805904;
          *  Stores eFuse version.
          */
         uint32_t date:28;
@@ -4475,29 +4029,20 @@ typedef union {
 
 
 typedef struct {
-    volatile efuse_pgm_data0_reg_t pgm_data0;
-    volatile efuse_pgm_data1_reg_t pgm_data1;
-    volatile efuse_pgm_data2_reg_t pgm_data2;
-    volatile efuse_pgm_data3_reg_t pgm_data3;
-    volatile efuse_pgm_data4_reg_t pgm_data4;
-    volatile efuse_pgm_data5_reg_t pgm_data5;
-    volatile efuse_pgm_data6_reg_t pgm_data6;
-    volatile efuse_pgm_data7_reg_t pgm_data7;
-    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
-    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
-    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
+    volatile efuse_pgm_datan_reg_t pgm_datan[8];
+    volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3];
     volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
     volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
     volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
     volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
     volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
     volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
-    volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0;
-    volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1;
-    volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2;
-    volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3;
-    volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4;
-    volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5;
+    volatile efuse_rd_mac_sys0_reg_t rd_mac_sys_0;
+    volatile efuse_rd_mac_sys1_reg_t rd_mac_sys_1;
+    volatile efuse_rd_mac_sys2_reg_t rd_mac_sys_2;
+    volatile efuse_rd_mac_sys3_reg_t rd_mac_sys_3;
+    volatile efuse_rd_mac_sys4_reg_t rd_mac_sys_4;
+    volatile efuse_rd_mac_sys5_reg_t rd_mac_sys_5;
     volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
     volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
     volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
@@ -4514,54 +4059,12 @@ typedef struct {
     volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
     volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
     volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
-    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
-    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
-    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
-    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
-    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
-    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
-    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
-    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
-    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
-    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
-    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
-    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
-    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
-    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
-    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
-    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
-    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
-    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
-    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
-    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
-    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
-    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
-    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
-    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
-    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
-    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
-    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
-    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
-    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
-    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
-    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
-    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
-    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
-    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
-    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
-    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
-    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
-    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
-    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
-    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
-    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
-    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
-    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
-    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
-    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
-    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
-    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
-    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
+    volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8];
+    volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8];
+    volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8];
+    volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8];
+    volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8];
+    volatile efuse_rd_key5_datan_reg_t rd_key5_datan[8];
     volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
     volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
     volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
@@ -4570,14 +4073,16 @@ typedef struct {
     volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
     volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
     volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
-    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
-    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
-    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
-    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
-    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
-    uint32_t reserved_190[12];
-    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
-    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
+    volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0;
+    volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1;
+    volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2;
+    volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3;
+    volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4;
+    uint32_t reserved_190[8];
+    volatile efuse_ecdsa_reg_t ecdsa;
+    uint32_t reserved_1b4[3];
+    volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0;
+    volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1;
     volatile efuse_clk_reg_t clk;
     volatile efuse_conf_reg_t conf;
     volatile efuse_status_reg_t status;
diff --git a/conftest.py b/conftest.py
index fef9ddf671d2..8c2407f8687a 100644
--- a/conftest.py
+++ b/conftest.py
@@ -380,27 +380,33 @@ def set_dut_log_url(record_xml_attribute: t.Callable[[str, object], None], _pexp
     # Record the "dut_log_url" attribute in the XML report once test execution finished
     yield
 
-    if not isinstance(_pexpect_logfile, str):
-        record_xml_attribute('dut_log_url', 'No log URL found')
-        return
+    def _attach_log_url_to_xml_attribute(log_file_path: str) -> str:
+        if not isinstance(log_file_path, str):
+            return 'No log URL found'
 
-    ci_pages_url = os.getenv('CI_PAGES_URL')
-    logdir_pattern = re.compile(rf'({DEFAULT_LOGDIR}/.*)')
-    match = logdir_pattern.search(_pexpect_logfile)
+        ci_pages_url = os.getenv('CI_PAGES_URL')
+        logdir_pattern = re.compile(rf'({DEFAULT_LOGDIR}/.*)')
+        match = logdir_pattern.search(log_file_path)
 
-    if not match:
-        record_xml_attribute('dut_log_url', 'No log URL found')
-        return
+        if not match:
+            return 'No log URL found'
 
-    if not ci_pages_url:
-        record_xml_attribute('dut_log_url', _pexpect_logfile)
-        return
+        if not ci_pages_url:
+            return log_file_path
 
-    job_id = os.getenv('CI_JOB_ID', '0')
-    modified_ci_pages_url = ci_pages_url.replace('esp-idf', '-/esp-idf')
-    log_url = f'{modified_ci_pages_url}/-/jobs/{job_id}/artifacts/{match.group(1)}'
+        job_id = os.getenv('CI_JOB_ID', '0')
+        modified_ci_pages_url = ci_pages_url.replace('esp-idf', '-/esp-idf')
+        log_url = f'{modified_ci_pages_url}/-/jobs/{job_id}/artifacts/{match.group(1)}'
 
-    record_xml_attribute('dut_log_url', log_url)
+        return log_url
+
+    xml_attribute = []
+    if isinstance(_pexpect_logfile, str):
+        xml_attribute.append(_attach_log_url_to_xml_attribute(_pexpect_logfile))
+    if isinstance(_pexpect_logfile, tuple):
+        for i, log_file in enumerate(_pexpect_logfile):
+            xml_attribute.append(_attach_log_url_to_xml_attribute(log_file))
+    record_xml_attribute('dut_log_url', ';'.join(xml_attribute))
 
 
 ######################
diff --git a/docs/en/api-reference/peripherals/adc_continuous.rst b/docs/en/api-reference/peripherals/adc_continuous.rst
index 2c4d7698d4da..759086b6b2d3 100644
--- a/docs/en/api-reference/peripherals/adc_continuous.rst
+++ b/docs/en/api-reference/peripherals/adc_continuous.rst
@@ -318,6 +318,71 @@ where:
 
 To do further calibration to convert the ADC raw result to voltage in mV, please refer to :doc:`adc_calibration`.
 
+Parse ADC Raw Data
+~~~~~~~~~~~~~~~~~~~~~
+
+The raw data read from ADC continuous mode needs to be further parsed to obtain usable ADC conversion results. The function :cpp:func:`adc_continuous_parse_data` provides the functionality to parse raw data into structured ADC data.
+
+.. note::
+
+    Input buffer requirements:
+
+    - **Length alignment**: `raw_data_size` must be a multiple of :c:macro:`SOC_ADC_DIGI_RESULT_BYTES`
+    - **Buffer size**: Ensure the `raw_data` buffer is large enough to hold `raw_data_size` bytes of data
+
+.. code:: c
+
+    // Read raw data
+    uint32_t ret_num = 0;
+    esp_err_t ret = adc_continuous_read(handle, result, EXAMPLE_READ_LEN, &ret_num, 0);
+    if (ret == ESP_OK) {
+        // Parse raw data
+        adc_continuous_data_t parsed_data[ret_num / SOC_ADC_DIGI_RESULT_BYTES];
+        uint32_t num_parsed_samples = 0;
+
+        esp_err_t parse_ret = adc_continuous_parse_data(handle, result, ret_num, parsed_data, &num_parsed_samples);
+        if (parse_ret == ESP_OK) {
+            for (int i = 0; i < num_parsed_samples; i++) {
+                if (parsed_data[i].valid) {
+                    ESP_LOGI(TAG, "ADC%d, Channel: %d, Value: %"PRIu32,
+                             parsed_data[i].unit + 1,
+                             parsed_data[i].channel,
+                             parsed_data[i].raw_data);
+                }
+            }
+        }
+    }
+
+The parsed data structure :cpp:type:`adc_continuous_data_t` contains the following information:
+
+- :cpp:member:`adc_continuous_data_t::unit`：ADC unit (ADC_UNIT_1 or ADC_UNIT_2)
+- :cpp:member:`adc_continuous_data_t::channel`：ADC channel number (0-9)
+- :cpp:member:`adc_continuous_data_t::raw_data`：ADC raw data value (0-4095, 12-bit resolution)
+- :cpp:member:`adc_continuous_data_t::valid`：Whether the data is valid
+
+Read and Parse ADC Data
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To simplify the usage flow, the function :cpp:func:`adc_continuous_read_parse` is provided, which merges the read and parse operations into a single function call.
+
+.. code:: c
+
+    // Using the read and parse function
+    adc_continuous_data_t parsed_data[64];  // User specifies maximum number of samples
+    uint32_t num_samples = 0;
+
+    esp_err_t ret = adc_continuous_read_parse(handle, parsed_data, 64, &num_samples, 1000);
+    if (ret == ESP_OK) {
+        for (int i = 0; i < num_samples; i++) {
+            if (parsed_data[i].valid) {
+                ESP_LOGI(TAG, "ADC%d, Channel: %d, Value: %"PRIu32,
+                         parsed_data[i].unit + 1,
+                         parsed_data[i].channel,
+                         parsed_data[i].raw_data);
+            }
+        }
+    }
+
 .. _adc-continuous-hardware-limitations:
 
 .. _hardware_limitations_adc_continuous:
diff --git a/docs/en/api-reference/protocols/mbedtls.rst b/docs/en/api-reference/protocols/mbedtls.rst
index 7179397414d6..d444db109eb0 100644
--- a/docs/en/api-reference/protocols/mbedtls.rst
+++ b/docs/en/api-reference/protocols/mbedtls.rst
@@ -118,5 +118,5 @@ Reducing Binary Size
 Under ``Component Config -> mbedTLS``, there are multiple Mbed TLS features which are enabled by default but can be disabled if not needed to save code size. More information can be about this can be found in :ref:`Minimizing Binary Size <minimizing_binary_mbedtls>` docs.
 
 
-.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.6.4/
+.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.6.5/
 .. _`Knowledge Base`: https://mbed-tls.readthedocs.io/en/latest/kb/
diff --git a/docs/zh_CN/api-reference/peripherals/adc_continuous.rst b/docs/zh_CN/api-reference/peripherals/adc_continuous.rst
index 154241eb5de2..6ff5ada78bdc 100644
--- a/docs/zh_CN/api-reference/peripherals/adc_continuous.rst
+++ b/docs/zh_CN/api-reference/peripherals/adc_continuous.rst
@@ -318,6 +318,71 @@ ADC 连续转换模式驱动使用内部缓冲池保存转换结果，缓冲池
 
 若需进一步校准，将 ADC 原始结果转换为以 mV 为单位的电压数据，请参考 :doc:`adc_calibration`。
 
+解析 ADC 原始数据
+~~~~~~~~~~~~~~~~~~~~~
+
+ADC 连续转换模式读取的原始数据需要进一步解析才能获得可用的 ADC 转换结果。函数 :cpp:func:`adc_continuous_parse_data` 提供了将原始数据解析为结构化 ADC 数据的功能。
+
+.. note::
+
+    输入缓冲区要求：
+
+    - **长度对齐**：`raw_data_size` 必须是 :c:macro:`SOC_ADC_DIGI_RESULT_BYTES` 的整数倍
+    - **缓冲区大小**：确保 `raw_data` 缓冲区足够大以容纳 `raw_data_size` 字节的数据
+
+.. code:: c
+
+    // 读取原始数据
+    uint32_t ret_num = 0;
+    esp_err_t ret = adc_continuous_read(handle, result, EXAMPLE_READ_LEN, &ret_num, 0);
+    if (ret == ESP_OK) {
+        // 解析原始数据
+        adc_continuous_data_t parsed_data[ret_num / SOC_ADC_DIGI_RESULT_BYTES];
+        uint32_t num_parsed_samples = 0;
+
+        esp_err_t parse_ret = adc_continuous_parse_data(handle, result, ret_num, parsed_data, &num_parsed_samples);
+        if (parse_ret == ESP_OK) {
+            for (int i = 0; i < num_parsed_samples; i++) {
+                if (parsed_data[i].valid) {
+                    ESP_LOGI(TAG, "ADC%d, Channel: %d, Value: %"PRIu32,
+                             parsed_data[i].unit + 1,
+                             parsed_data[i].channel,
+                             parsed_data[i].raw_data);
+                }
+            }
+        }
+    }
+
+解析后的数据结构 :cpp:type:`adc_continuous_data_t` 包含以下信息：
+
+- :cpp:member:`adc_continuous_data_t::unit`：ADC 单元（ADC_UNIT_1 或 ADC_UNIT_2）
+- :cpp:member:`adc_continuous_data_t::channel`：ADC 通道号（0-9）
+- :cpp:member:`adc_continuous_data_t::raw_data`：ADC 原始数据值（0-4095，12位分辨率）
+- :cpp:member:`adc_continuous_data_t::valid`：数据是否有效
+
+读取并解析 ADC 数据
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+为了简化使用流程，提供了 :cpp:func:`adc_continuous_read_parse` 函数，该函数将读取和解析操作合并为一个函数调用。
+
+.. code:: c
+
+    // 使用读取并解析函数
+    adc_continuous_data_t parsed_data[64];  // 用户指定最大样本数
+    uint32_t num_samples = 0;
+
+    esp_err_t ret = adc_continuous_read_parse(handle, parsed_data, 64, &num_samples, 1000);
+    if (ret == ESP_OK) {
+        for (int i = 0; i < num_samples; i++) {
+            if (parsed_data[i].valid) {
+                ESP_LOGI(TAG, "ADC%d, Channel: %d, Value: %"PRIu32,
+                         parsed_data[i].unit + 1,
+                         parsed_data[i].channel,
+                         parsed_data[i].raw_data);
+            }
+        }
+    }
+
 .. _adc-continuous-hardware-limitations:
 
 .. _hardware_limitations_adc_continuous:
diff --git a/docs/zh_CN/api-reference/protocols/mbedtls.rst b/docs/zh_CN/api-reference/protocols/mbedtls.rst
index 42a1622143c7..affcf46acedc 100644
--- a/docs/zh_CN/api-reference/protocols/mbedtls.rst
+++ b/docs/zh_CN/api-reference/protocols/mbedtls.rst
@@ -118,5 +118,5 @@ ESP-IDF 中的示例使用 :doc:`/api-reference/protocols/esp_tls`，为访问
 在 ``Component Config -> mbedTLS`` 中，有多个 Mbed TLS 功能默认为启用状态。如果不需要这些功能，可将其禁用以减小固件大小。要了解更多信息，请参考 :ref:`Minimizing Binary Size <minimizing_binary_mbedtls>` 文档。
 
 
-.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.6.4/
+.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.6.5/
 .. _`Knowledge Base`: https://mbed-tls.readthedocs.io/en/latest/kb/
diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/src/gap.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/src/gap.c
index 71e03ba7c2aa..8243ecf3341c 100644
--- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/src/gap.c
+++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/src/gap.c
@@ -51,7 +51,7 @@ static void start_advertising(void) {
     adv_fields.le_role = BLE_GAP_LE_ROLE_PERIPHERAL;
     adv_fields.le_role_is_present = 1;
 
-    /* Set advertiement fields */
+    /* Set advertisement fields */
     rc = ble_gap_adv_set_fields(&adv_fields);
     if (rc != 0) {
         ESP_LOGE(TAG, "failed to set advertising data, error code: %d", rc);
@@ -74,7 +74,7 @@ static void start_advertising(void) {
         return;
     }
 
-    /* Set non-connetable and general discoverable mode to be a beacon */
+    /* Set non-connectable and general discoverable mode to be a beacon */
     adv_params.conn_mode = BLE_GAP_CONN_MODE_NON;
     adv_params.disc_mode = BLE_GAP_DISC_MODE_GEN;
 
diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c
index 8788b66f267e..68fffcaafba5 100644
--- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c
+++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c
@@ -80,7 +80,7 @@ static void start_advertising(void) {
     adv_fields.le_role = BLE_GAP_LE_ROLE_PERIPHERAL;
     adv_fields.le_role_is_present = 1;
 
-    /* Set advertiement fields */
+    /* Set advertisement fields */
     rc = ble_gap_adv_set_fields(&adv_fields);
     if (rc != 0) {
         ESP_LOGE(TAG, "failed to set advertising data, error code: %d", rc);
@@ -107,7 +107,7 @@ static void start_advertising(void) {
         return;
     }
 
-    /* Set non-connetable and general discoverable mode to be a beacon */
+    /* Set undirected connectable and general discoverable mode */
     adv_params.conn_mode = BLE_GAP_CONN_MODE_UND;
     adv_params.disc_mode = BLE_GAP_DISC_MODE_GEN;
 
diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/src/gap.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/src/gap.c
index 8519028a5d0e..7c7b3dde2ade 100644
--- a/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/src/gap.c
+++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/src/gap.c
@@ -80,7 +80,7 @@ static void start_advertising(void) {
     adv_fields.le_role = BLE_GAP_LE_ROLE_PERIPHERAL;
     adv_fields.le_role_is_present = 1;
 
-    /* Set advertiement fields */
+    /* Set advertisement fields */
     rc = ble_gap_adv_set_fields(&adv_fields);
     if (rc != 0) {
         ESP_LOGE(TAG, "failed to set advertising data, error code: %d", rc);
@@ -107,7 +107,7 @@ static void start_advertising(void) {
         return;
     }
 
-    /* Set non-connetable and general discoverable mode to be a beacon */
+    /* Set undirected connectable and general discoverable mode */
     adv_params.conn_mode = BLE_GAP_CONN_MODE_UND;
     adv_params.disc_mode = BLE_GAP_DISC_MODE_GEN;
 
diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/src/gap.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/src/gap.c
index d4e7c249b68c..55c34487eb9d 100644
--- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/src/gap.c
+++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/src/gap.c
@@ -95,7 +95,7 @@ static void start_advertising(void) {
     adv_fields.le_role = BLE_GAP_LE_ROLE_PERIPHERAL;
     adv_fields.le_role_is_present = 1;
 
-    /* Set advertiement fields */
+    /* Set advertisement fields */
     rc = ble_gap_adv_set_fields(&adv_fields);
     if (rc != 0) {
         ESP_LOGE(TAG, "failed to set advertising data, error code: %d", rc);
@@ -122,7 +122,7 @@ static void start_advertising(void) {
         return;
     }
 
-    /* Set non-connetable and general discoverable mode to be a beacon */
+    /* Set undirected connectable and general discoverable mode */
     adv_params.conn_mode = BLE_GAP_CONN_MODE_UND;
     adv_params.disc_mode = BLE_GAP_DISC_MODE_GEN;
 
diff --git a/examples/network/bridge/pytest_example_bridge.py b/examples/network/bridge/pytest_example_bridge.py
index aa0108de7cb6..765e37c41d2d 100644
--- a/examples/network/bridge/pytest_example_bridge.py
+++ b/examples/network/bridge/pytest_example_bridge.py
@@ -55,7 +55,7 @@ def exec_cmd(self, cmd: str) -> str:
         error = stderr.read().decode().strip()
         if error:
             out = ''
-            logging.error('ssh_endnode_exec error: {}'.format(error))
+            logging.error(f'ssh_endnode_exec error: {error}')
 
         return out  # type: ignore
 
@@ -99,7 +99,7 @@ def exec_cmd(self, cmd: Union[str, List[str]]) -> str:
             error = stderr.read().decode().strip()
 
             if error != 'TSW Init OK!':
-                raise Exception('switch_5xp exec_cmd error: {}'.format(error))
+                raise Exception(f'switch_5xp exec_cmd error: {error}')
         else:
             out = self.ssh_client.send_config_set(cmd, cmd_verify=False, exit_config_mode=False)
         return out  # type: ignore
@@ -159,7 +159,7 @@ def get_host_interface_name_in_same_net(ip_addr: str) -> str:
 
 def get_host_mac_by_interface(interface_name: str, addr_type: int = netifaces.AF_LINK) -> str:
     for _addr in netifaces.ifaddresses(interface_name)[addr_type]:
-        host_mac = _addr['addr'].replace('%{}'.format(interface_name), '')
+        host_mac = _addr['addr'].replace(f'%{interface_name}', '')
         assert isinstance(host_mac, str)
         return host_mac
     return ''
@@ -167,7 +167,7 @@ def get_host_mac_by_interface(interface_name: str, addr_type: int = netifaces.AF
 
 def get_host_brcast_ip_by_interface(interface_name: str, ip_type: int = netifaces.AF_INET) -> str:
     for _addr in netifaces.ifaddresses(interface_name)[ip_type]:
-        host_ip = _addr['broadcast'].replace('%{}'.format(interface_name), '')
+        host_ip = _addr['broadcast'].replace(f'%{interface_name}', '')
         assert isinstance(host_ip, str)
         return host_ip
     return ''
@@ -190,7 +190,7 @@ def run_iperf(
     if ipaddress.ip_address(server_ip).is_multicast:
         # Configure Multicast Server
         server_proc = subprocess.Popen(
-            ['iperf', '-u', '-s', '-i', '1', '-t', '%i' % interval, '-B', '%s%%%s' % (server_ip, server_if)],
+            ['iperf', '-u', '-s', '-i', '1', '-t', str(interval), '-B', f'{server_ip}%{server_if}'],
             text=True,
             stdout=subprocess.PIPE,
             stderr=subprocess.PIPE,
@@ -200,20 +200,20 @@ def run_iperf(
         if endnode_ip == '':
             raise RuntimeError('End node IP address not found')
         client_res = endnode.exec_cmd(
-            'iperf -u -c %s -t %i -i 1 -b %iM --ttl 5 -B %s' % (server_ip, interval, bandwidth_lim, endnode_ip)
+            f'iperf -u -c {server_ip} -t {interval} -i 1 -b {bandwidth_lim}M --ttl 5 -B {endnode_ip}'
         )
         if server_proc.wait(10) is None:  # Process did not finish.
             server_proc.terminate()
     else:
         # Configure Server
         server_proc = subprocess.Popen(
-            ['iperf', '%s' % proto, '-s', '-i', '1', '-t', '%i' % interval],
+            ['iperf', proto, '-s', '-i', '1', '-t', str(interval)],
             text=True,
             stdout=subprocess.PIPE,
             stderr=subprocess.PIPE,
         )
         # Configure Client
-        client_res = endnode.exec_cmd('iperf %s -c %s -t %i -i 1 -b %iM' % (proto, server_ip, interval, bandwidth_lim))
+        client_res = endnode.exec_cmd(f'iperf {proto} -c {server_ip} -t {interval} -i 1 -b {bandwidth_lim}M')
         if server_proc.wait(10) is None:  # Process did not finish.
             server_proc.terminate()
 
@@ -243,8 +243,8 @@ def send_brcast_msg_host_to_endnode(endnode: EndnodeSsh, host_brcast_ip: str, te
     try:
         sock.setsockopt(socket.SOL_SOCKET, socket.SO_BROADCAST, 1)
         sock.sendto(test_msg.encode('utf-8'), (host_brcast_ip, 5100))
-    except socket.error as e:
-        raise Exception('Host brcast send failed %s' % e)
+    except OSError as e:
+        raise Exception(f'Host brcast send failed {e}')
 
     nc_endnode_out = endnode.get_async_res()
     sock.close()
@@ -253,18 +253,24 @@ def send_brcast_msg_host_to_endnode(endnode: EndnodeSsh, host_brcast_ip: str, te
 
 def send_brcast_msg_endnode_to_host(endnode: EndnodeSsh, host_brcast_ip: str, test_msg: str) -> str:
     sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
+    sock.setsockopt(socket.SOL_SOCKET, socket.SO_REUSEADDR, 1)  # Allow binding if port still in TIME_WAIT
     sock.settimeout(5)
     try:
         sock.bind(('', 5100))
-    except socket.error as e:
-        raise Exception('Host bind failed %s' % e)
+        # Give socket time to be fully ready to receive before we tell endnode to send.
+        # Even with SSH latency, there's a small window where a fast-received packet could be dropped.
+        time.sleep(0.1)
+    except OSError as e:
+        raise Exception(f'Host bind failed {e}')
 
-    endnode.exec_cmd('echo -n "%s" | nc -b -w0 -u %s 5100' % (test_msg, host_brcast_ip))
+    endnode.exec_cmd(f'echo -n "{test_msg}" | nc -b -w0 -u {host_brcast_ip} 5100')
 
     try:
         nc_host_out = sock.recv(1500).decode('utf-8')
-    except socket.error as e:
-        raise Exception('Host recv failed %s', e)
+    except TimeoutError:
+        raise Exception('Host recv timed out after 5 seconds')
+    except OSError as e:
+        raise Exception(f'Host recv failed {e}')
 
     sock.close()
     return nc_host_out
@@ -430,16 +436,15 @@ def test_esp_eth_bridge(dut: Dut, dev_user: str, dev_password: str) -> None:
 
     if bandwidth_udp < MIN_UDP_THROUGHPUT:
         raise RuntimeError(
-            'Unicast UDP throughput expected %.2f, actual %.2f' % (MIN_UDP_THROUGHPUT, bandwidth_udp) + ' Mbits/s'
+            f'Unicast UDP throughput expected {MIN_UDP_THROUGHPUT:.2f}, actual {bandwidth_udp:.2f} Mbits/s'
         )
     if bandwidth_tcp < MIN_TCP_THROUGHPUT:
         raise RuntimeError(
-            'Unicast TCP throughput expected %.2f, actual %.2f' % (MIN_TCP_THROUGHPUT, bandwidth_tcp) + ' Mbits/s'
+            f'Unicast TCP throughput expected {MIN_TCP_THROUGHPUT:.2f}, actual {bandwidth_tcp:.2f} Mbits/s'
         )
     if bandwidth_mcast_udp < MIN_UDP_THROUGHPUT:
         raise RuntimeError(
-            'Multicast UDP throughput expected %.2f, actual %.2f' % (MIN_UDP_THROUGHPUT, bandwidth_mcast_udp)
-            + ' Mbits/s'
+            f'Multicast UDP throughput expected {MIN_UDP_THROUGHPUT:.2f}, actual {bandwidth_mcast_udp:.2f} Mbits/s'
         )
 
     # ------------------------------------------------
@@ -493,7 +498,7 @@ def test_esp_eth_bridge(dut: Dut, dev_user: str, dev_password: str) -> None:
 
     # try to add more FDB entries than configured max number
     for i in range(BR_PORTS_NUM + 1):
-        dut.write('add --addr=01:02:03:00:00:%02x' % i + ' -d')
+        dut.write(f'add --addr=01:02:03:00:00:{i:02x} -d')
         if i < BR_PORTS_NUM:
             dut.expect_exact('Bridge Config OK!')
         else:
@@ -507,7 +512,7 @@ def test_esp_eth_bridge(dut: Dut, dev_user: str, dev_password: str) -> None:
 
     # remove dummy entries
     for i in range(BR_PORTS_NUM):
-        dut.write('remove --addr=01:02:03:00:00:%02x' % i)
+        dut.write(f'remove --addr=01:02:03:00:00:{i:02x}')
         dut.expect_exact('Bridge Config OK!')
 
     # valid multiple ports at once
diff --git a/examples/openthread/ot_ci_function.py b/examples/openthread/ot_ci_function.py
index 2b267e62ecad..5a706852e6b5 100644
--- a/examples/openthread/ot_ci_function.py
+++ b/examples/openthread/ot_ci_function.py
@@ -2,14 +2,17 @@
 # SPDX-License-Identifier: Unlicense OR CC0-1.0
 # !/usr/bin/env python3
 # this file defines some functions for testing cli and br under pytest framework
+import logging
 import os
 import re
 import socket
 import struct
 import subprocess
 import time
-from collections.abc import Callable
 from functools import wraps
+from typing import Callable
+from typing import Optional
+from typing import Tuple
 
 import netifaces
 import pexpect
@@ -18,19 +21,33 @@
 
 
 def extract_address(
-    command: str, pattern: str, default_return: str = ''
+    command: str,
+    pattern: str,
+    default_return: str = '',
+    retries: int = 3,
+    delay: int = 2,
 ) -> Callable[[Callable[[str], str]], Callable[[IdfDut], str]]:
     def decorator(func: Callable[[str], str]) -> Callable[[IdfDut], str]:
         @wraps(func)
         def wrapper(dut: IdfDut) -> str:
-            clean_buffer(dut)
-            execute_command(dut, command)
-            try:
-                result = dut.expect(pattern, timeout=5)[1].decode()
-            except Exception as e:
-                print(f'Error: {e}')
-                return default_return
-            return func(result)
+            # requires Python3.10
+            # last_exception: Exception | None = None
+            last_exception: Optional[Exception] = None
+            for attempt in range(1, retries + 1):
+                try:
+                    clean_buffer(dut)
+                    execute_command(dut, command)
+                    result = dut.expect(pattern, timeout=5)[1].decode()
+                    return func(result)
+                except Exception as e:
+                    logging.exception(f'[{command}] Attempt {attempt}/{retries} failed: {e}')
+                    last_exception = e
+                    if attempt < retries:
+                        time.sleep(delay)
+
+            if last_exception:
+                logging.exception(f'[{command}] Giving up after {retries} retries.')
+            return default_return
 
         return wrapper
 
@@ -132,7 +149,7 @@ def wait_for_join(dut: IdfDut, role: str) -> bool:
     return False
 
 
-def joinWiFiNetwork(dut: IdfDut, wifi: wifi_parameter) -> tuple[str, int]:
+def joinWiFiNetwork(dut: IdfDut, wifi: wifi_parameter) -> Tuple[str, int]:
     clean_buffer(dut)
     ip_address = ''
     for order in range(1, wifi.retry_times):
@@ -151,7 +168,7 @@ def getDeviceRole(dut: IdfDut) -> str:
     wait(dut, 1)
     execute_command(dut, 'state')
     role = dut.expect(r'\W+(\w+)\W+Done', timeout=5)[1].decode()
-    print(role)
+    logging.info(role)
     return str(role)
 
 
@@ -172,6 +189,12 @@ def init_thread(dut: IdfDut) -> None:
     reset_thread(dut)
 
 
+def stop_thread(dut: IdfDut) -> None:
+    execute_command(dut, 'thread stop')
+    dut.expect('disabled', timeout=20)
+    reset_thread(dut)
+
+
 def reset_thread(dut: IdfDut) -> None:
     execute_command(dut, 'factoryreset')
     dut.expect('OpenThread attached to netif', timeout=20)
@@ -179,28 +202,28 @@ def reset_thread(dut: IdfDut) -> None:
     clean_buffer(dut)
 
 
+def hardreset_dut(dut: IdfDut) -> None:
+    dut.serial.hard_reset()
+    time.sleep(5)
+    execute_command(dut, 'factoryreset')
+
+
 # get the mleid address of the thread
-def get_mleid_addr(dut: IdfDut) -> str:
-    dut_adress = ''
-    execute_command(dut, 'ipaddr mleid')
-    dut_adress = dut.expect(r'\n((?:\w+:){7}\w+)\r', timeout=5)[1].decode()
-    return str(dut_adress)
+@extract_address('ipaddr mleid', r'\n((?:\w+:){7}\w+)\r')
+def get_mleid_addr(addr: str) -> str:
+    return addr
 
 
 # get the rloc address of the thread
-def get_rloc_addr(dut: IdfDut) -> str:
-    dut_adress = ''
-    execute_command(dut, 'ipaddr rloc')
-    dut_adress = dut.expect(r'\n((?:\w+:){7}\w+)\r', timeout=5)[1].decode()
-    return str(dut_adress)
+@extract_address('ipaddr rloc', r'\n((?:\w+:){7}\w+)\r')
+def get_rloc_addr(addr: str) -> str:
+    return addr
 
 
 # get the linklocal address of the thread
-def get_linklocal_addr(dut: IdfDut) -> str:
-    dut_adress = ''
-    execute_command(dut, 'ipaddr linklocal')
-    dut_adress = dut.expect(r'\n((?:\w+:){7}\w+)\r', timeout=5)[1].decode()
-    return str(dut_adress)
+@extract_address('ipaddr linklocal', r'\n((?:\w+:){7}\w+)\r')
+def get_linklocal_addr(addr: str) -> str:
+    return addr
 
 
 # get the global unicast address of the thread:
@@ -221,7 +244,7 @@ def get_rloc16_addr(rloc16: str) -> str:
 # ping of thread
 def ot_ping(
     dut: IdfDut, target: str, timeout: int = 5, count: int = 1, size: int = 56, interval: int = 1, hoplimit: int = 64
-) -> tuple[int, int]:
+) -> Tuple[int, int]:
     command = f'ping {str(target)} {size} {count} {interval} {hoplimit} {str(timeout)}'
     execute_command(dut, command)
     transmitted = dut.expect(r'(\d+) packets transmitted', timeout=60)[1].decode()
@@ -310,7 +333,7 @@ def get_host_interface_name() -> str:
             interface_name = config.get('interface_name')
             if interface_name:
                 if interface_name == 'eth0':
-                    print(
+                    logging.warning(
                         f"Warning: 'eth0' is not recommended as a valid network interface. "
                         f"Please check and update the 'interface_name' in the configuration file: "
                         f'{config_path}'
@@ -318,9 +341,9 @@ def get_host_interface_name() -> str:
                 else:
                     return str(interface_name)
             else:
-                print("Warning: Configuration file found but 'interface_name' is not defined.")
+                logging.warning("Warning: Configuration file found but 'interface_name' is not defined.")
     except Exception as e:
-        print(f'Error: Failed to read or parse {config_path}. Details: {e}')
+        logging.error(f'Error: Failed to read or parse {config_path}. Details: {e}')
     if 'eth1' in netifaces.interfaces():
         return 'eth1'
 
@@ -338,8 +361,8 @@ def check_if_host_receive_ra(br: IdfDut) -> bool:
     omrprefix = get_omrprefix(br)
     command = 'ip -6 route | grep ' + str(interface_name)
     out_str = subprocess.getoutput(command)
-    print('br omrprefix: ', str(omrprefix))
-    print('host route table:\n', str(out_str))
+    logging.info(f'br omrprefix: {omrprefix}')
+    logging.info(f'host route table:\n {out_str}')
     return str(omrprefix) in str(out_str)
 
 
@@ -404,7 +427,7 @@ def create_host_udp_server(myudp: udp_parameter) -> None:
             AF_INET = socket.AF_INET6
         else:
             AF_INET = socket.AF_INET
-        print('The host start to create udp server!')
+        logging.info('The host start to create udp server!')
         if_index = socket.if_nametoindex(interface_name)
         sock = socket.socket(AF_INET, socket.SOCK_DGRAM)
         sock.bind((myudp.addr, myudp.port))
@@ -417,13 +440,14 @@ def create_host_udp_server(myudp: udp_parameter) -> None:
             )
         sock.settimeout(myudp.timeout)
         myudp.init_flag = True
-        print('The host start to receive message!')
+        logging.info('The host start to receive message!')
         myudp.udp_bytes = (sock.recvfrom(1024))[0]
-        print('The host has received message: ', myudp.udp_bytes)
+        udp_str = str(myudp.udp_bytes)
+        logging.info(f'The host has received message: {udp_str}')
     except OSError:
-        print('The host did not receive message!')
+        logging.error('The host did not receive message!')
     finally:
-        print('Close the socket.')
+        logging.info('Close the socket.')
         sock.close()
 
 
@@ -438,10 +462,10 @@ def host_udp_send_message(udp_target: udp_parameter) -> None:
         sock.bind(('::', 12350))
         sock.setsockopt(socket.SOL_SOCKET, socket.SO_BINDTODEVICE, interface_name.encode())
         sock.setsockopt(socket.IPPROTO_IPV6, socket.IPV6_MULTICAST_HOPS, 32)
-        print('Host is sending message')
+        logging.info('Host is sending message')
         sock.sendto(udp_target.udp_bytes, (udp_target.addr, udp_target.port))
     except OSError:
-        print('Host cannot send message')
+        logging.error('Host cannot send message')
     finally:
         sock.close()
 
@@ -481,13 +505,13 @@ def host_close_service() -> None:
     command = 'ps auxww | grep avahi-publish-s'
     out_bytes = subprocess.check_output(command, shell=True, timeout=5)
     out_str = out_bytes.decode('utf-8')
-    print('host close service avahi status:\n', out_str)
+    logging.info(f'host close service avahi status:\n {out_str}')
     service_info = [line for line in out_str.splitlines() if 'testxxx _testxxx._udp' in line]
     for line in service_info:
-        print('Process:', line)
+        logging.info(f'Process:{line}')
         pid = line.split()[1]
         command = 'kill -9 ' + pid
-        print('kill ', pid)
+        logging.info(f'kill {pid}')
         subprocess.call(command, shell=True, timeout=5)
         time.sleep(1)
 
@@ -520,24 +544,24 @@ def open_host_interface() -> None:
 
 def get_domain() -> str:
     hostname = socket.gethostname()
-    print('hostname is: ', hostname)
+    logging.info(f'hostname is: {hostname}')
     command = 'ps -auxww | grep avahi-daemon | grep running'
     out_str = subprocess.getoutput(command)
-    print('avahi status:\n', out_str)
+    logging.info(f'avahi status:\n {out_str}')
     role = re.findall(r'\[([\w\W]+)\.local\]', str(out_str))[0]
-    print('active host is: ', role)
+    logging.info(f'active host is: {role}')
     return str(role)
 
 
 def flush_ipv6_addr_by_interface() -> None:
     interface_name = get_host_interface_name()
-    print(f'flush ipv6 addr : {interface_name}')
+    logging.info(f'flush ipv6 addr : {interface_name}')
     command_show_addr = f'ip -6 addr show dev {interface_name}'
     command_show_route = f'ip -6 route show dev {interface_name}'
     addr_before = subprocess.getoutput(command_show_addr)
     route_before = subprocess.getoutput(command_show_route)
-    print(f'Before flush, IPv6 addresses: \n{addr_before}')
-    print(f'Before flush, IPv6 routes: \n{route_before}')
+    logging.info(f'Before flush, IPv6 addresses: \n{addr_before}')
+    logging.info(f'Before flush, IPv6 routes: \n{route_before}')
     subprocess.run(['ip', 'link', 'set', interface_name, 'down'])
     subprocess.run(['ip', '-6', 'addr', 'flush', 'dev', interface_name])
     subprocess.run(['ip', '-6', 'route', 'flush', 'dev', interface_name])
@@ -545,8 +569,8 @@ def flush_ipv6_addr_by_interface() -> None:
     time.sleep(5)
     addr_after = subprocess.getoutput(command_show_addr)
     route_after = subprocess.getoutput(command_show_route)
-    print(f'After flush, IPv6 addresses: \n{addr_after}')
-    print(f'After flush, IPv6 routes: \n{route_after}')
+    logging.info(f'After flush, IPv6 addresses: \n{addr_after}')
+    logging.info(f'After flush, IPv6 routes: \n{route_after}')
 
 
 class tcp_parameter:
@@ -575,28 +599,29 @@ def create_host_tcp_server(mytcp: tcp_parameter) -> None:
             AF_INET = socket.AF_INET6
         else:
             AF_INET = socket.AF_INET
-        print('The host start to create a tcp server!')
+        logging.info('The host start to create a tcp server!')
         sock = socket.socket(AF_INET, socket.SOCK_STREAM)
         sock.bind((mytcp.addr, mytcp.port))
         sock.listen(5)
         mytcp.listen_flag = True
 
-        print('The tcp server is waiting for connection!')
+        logging.info('The tcp server is waiting for connection!')
         sock.settimeout(mytcp.timeout)
         connfd, addr = sock.accept()
-        print('The tcp server connected with ', addr)
+        logging.info(f'The tcp server connected with {addr}')
         mytcp.recv_flag = True
 
         mytcp.tcp_bytes = connfd.recv(1024)
-        print('The tcp server has received message: ', mytcp.tcp_bytes)
+        tcp_str = str(mytcp.tcp_bytes)
+        logging.info(f'The tcp server has received message: {tcp_str}')
 
     except OSError:
         if mytcp.recv_flag:
-            print('The tcp server did not receive message!')
+            logging.error('The tcp server did not receive message!')
         else:
-            print('The tcp server fail to connect!')
+            logging.error('The tcp server fail to connect!')
     finally:
-        print('Close the socket.')
+        logging.info('Close the socket.')
         sock.close()
 
 
@@ -616,22 +641,19 @@ def decimal_to_hex(decimal_str: str) -> str:
     return hex_str
 
 
-def get_omrprefix(br: IdfDut) -> str:
-    execute_command(br, 'br omrprefix')
-    omrprefix = br.expect(r'Local: ((?:\w+:){4}):/\d+\r', timeout=5)[1].decode()
-    return str(omrprefix)
+@extract_address('br omrprefix', r'Local: ((?:\w+:){4}):/\d+\r')
+def get_omrprefix(addr: str) -> str:
+    return addr
 
 
-def get_onlinkprefix(br: IdfDut) -> str:
-    execute_command(br, 'br onlinkprefix')
-    onlinkprefix = br.expect(r'Local: ((?:\w+:){4}):/\d+\r', timeout=5)[1].decode()
-    return str(onlinkprefix)
+@extract_address('br onlinkprefix', r'Local: ((?:\w+:){4}):/\d+\r')
+def get_onlinkprefix(addr: str) -> str:
+    return addr
 
 
-def get_nat64prefix(br: IdfDut) -> str:
-    execute_command(br, 'br nat64prefix')
-    nat64prefix = br.expect(r'Local: ((?:\w+:){6}):/\d+', timeout=5)[1].decode()
-    return str(nat64prefix)
+@extract_address('br nat64prefix', r'Local: ((?:\w+:){6}):/\d+')
+def get_nat64prefix(addr: str) -> str:
+    return addr
 
 
 def execute_command(dut: IdfDut, command: str, prefix: str = 'ot ') -> None:
@@ -644,3 +666,17 @@ def get_ouput_string(dut: IdfDut, command: str, wait_time: int) -> str:
     tmp = dut.expect(pexpect.TIMEOUT, timeout=wait_time)
     clean_buffer(dut)
     return str(tmp)
+
+
+def wait_for_host_network(host: str = '8.8.8.8', retries: int = 6, interval: int = 10) -> None:
+    for attempt in range(1, retries + 1):
+        try:
+            subprocess.run(['ping', '-c', '1', '-W', '2', host], check=True)
+            logging.info(f'Host network reachable on attempt {attempt}')
+            return
+        except subprocess.CalledProcessError:
+            logging.info(f'Ping attempt {attempt} failed, retrying in {interval} seconds...')
+            if attempt < retries:
+                time.sleep(interval)
+            else:
+                raise RuntimeError(f'Host network is not reachable after {retries} attempts.')
diff --git a/examples/openthread/pytest_otbr.py b/examples/openthread/pytest_otbr.py
index e3a968eec736..6379f83d5e32 100644
--- a/examples/openthread/pytest_otbr.py
+++ b/examples/openthread/pytest_otbr.py
@@ -2,6 +2,7 @@
 # SPDX-License-Identifier: Unlicense OR CC0-1.0
 # !/usr/bin/env python3
 import copy
+import logging
 import os.path
 import random
 import re
@@ -76,7 +77,7 @@
 
 @pytest.fixture(scope='module', name='Init_avahi')
 def fixture_Init_avahi() -> bool:
-    print('Init Avahi')
+    logging.info('Init Avahi')
     ocf.start_avahi()
     time.sleep(10)
     return True
@@ -84,7 +85,7 @@ def fixture_Init_avahi() -> bool:
 
 @pytest.fixture(name='Init_interface')
 def fixture_Init_interface() -> bool:
-    print('Init interface')
+    logging.info('Init interface')
     ocf.flush_ipv6_addr_by_interface()
     # The sleep time is set based on experience; reducing it might cause the host to be unready.
     time.sleep(30)
@@ -104,7 +105,7 @@ def fixture_Init_interface() -> bool:
 
 # Case 1: Thread network formation and attaching
 @pytest.mark.openthread_br
-@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -159,9 +160,9 @@ def test_thread_connect(dut: Tuple[IdfDut, IdfDut, IdfDut]) -> None:
             rx_nums = ocf.ot_ping(br, cli_mleid_addr, count=5)[1]
             assert rx_nums == 5
     finally:
-        ocf.execute_command(br, 'factoryreset')
         for cli in cli_list:
-            ocf.execute_command(cli, 'factoryreset')
+            ocf.stop_thread(cli)
+        ocf.stop_thread(br)
         time.sleep(3)
 
 
@@ -187,7 +188,7 @@ def formBasicWiFiThreadNetwork(br: IdfDut, cli: IdfDut) -> None:
 
 # Case 2: Bidirectional IPv6 connectivity
 @pytest.mark.openthread_br
-@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -214,10 +215,10 @@ def test_Bidirectional_IPv6_connectivity(Init_interface: bool, dut: Tuple[IdfDut
     try:
         assert ocf.is_joined_wifi_network(br)
         cli_global_unicast_addr = ocf.get_global_unicast_addr(cli, br)
-        print('cli_global_unicast_addr', cli_global_unicast_addr)
+        logging.info(f'cli_global_unicast_addr {cli_global_unicast_addr}')
         command = 'ping ' + str(cli_global_unicast_addr) + ' -c 10'
         out_str = subprocess.getoutput(command)
-        print('ping result:\n', str(out_str))
+        logging.info(f'ping result:\n{out_str}')
         role = re.findall(r' (\d+)%', str(out_str))[0]
         assert role != '100'
         interface_name = ocf.get_host_interface_name()
@@ -225,21 +226,23 @@ def test_Bidirectional_IPv6_connectivity(Init_interface: bool, dut: Tuple[IdfDut
         out_bytes = subprocess.check_output(command, shell=True, timeout=5)
         out_str = out_bytes.decode('utf-8')
         onlinkprefix = ocf.get_onlinkprefix(br)
-        host_global_unicast_addr = re.findall(r'\W+(%s(?:\w+:){3}\w+)\W+' % onlinkprefix, str(out_str))
+        pattern = rf'\W+({onlinkprefix}(?:\w+:){{3}}\w+)\W+'
+        host_global_unicast_addr = re.findall(pattern, out_str)
         rx_nums = 0
         for ip_addr in host_global_unicast_addr:
-            txrx_nums = ocf.ot_ping(cli, str(ip_addr), count=5)
+            txrx_nums = ocf.ot_ping(cli, str(ip_addr), count=10)
             rx_nums = rx_nums + int(txrx_nums[1])
+        logging.debug(f'rx_nums: {rx_nums}')
         assert rx_nums != 0
     finally:
-        ocf.execute_command(br, 'factoryreset')
-        ocf.execute_command(cli, 'factoryreset')
+        ocf.stop_thread(cli)
+        ocf.stop_thread(br)
         time.sleep(3)
 
 
 # Case 3: Multicast forwarding from Wi-Fi to Thread network
 @pytest.mark.openthread_br
-@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -271,7 +274,7 @@ def test_multicast_forwarding_A(Init_interface: bool, dut: Tuple[IdfDut, IdfDut,
         interface_name = ocf.get_host_interface_name()
         command = 'ping -I ' + str(interface_name) + ' -t 64 ff04::125 -c 10'
         out_str = subprocess.getoutput(command)
-        print('ping result:\n', str(out_str))
+        logging.info(f'ping result:\n{out_str}')
         role = re.findall(r' (\d+)%', str(out_str))[0]
         assert role != '100'
         ocf.execute_command(cli, 'udp open')
@@ -285,14 +288,14 @@ def test_multicast_forwarding_A(Init_interface: bool, dut: Tuple[IdfDut, IdfDut,
         ocf.execute_command(cli, 'udp close')
         cli.expect('Done', timeout=5)
     finally:
-        ocf.execute_command(br, 'factoryreset')
-        ocf.execute_command(cli, 'factoryreset')
+        ocf.stop_thread(cli)
+        ocf.stop_thread(br)
         time.sleep(3)
 
 
 # Case 4: Multicast forwarding from Thread to Wi-Fi network
 @pytest.mark.openthread_br
-@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -338,15 +341,15 @@ def test_multicast_forwarding_B(Init_interface: bool, dut: Tuple[IdfDut, IdfDut,
         while udp_mission.is_alive():
             time.sleep(1)
     finally:
-        ocf.execute_command(br, 'factoryreset')
-        ocf.execute_command(cli, 'factoryreset')
+        ocf.stop_thread(cli)
+        ocf.stop_thread(br)
         time.sleep(3)
     assert b'hello' in myudp.udp_bytes
 
 
 # Case 5: discover dervice published by Thread device
 @pytest.mark.openthread_br
-@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -377,14 +380,14 @@ def test_service_discovery_of_Thread_device(
         assert ocf.is_joined_wifi_network(br)
         command = 'avahi-browse -rt _testyyy._udp'
         out_str = subprocess.getoutput(command)
-        print('avahi-browse:\n', str(out_str))
+        logging.info(f'avahi-browse:\n{out_str}')
         assert 'myTest' not in str(out_str)
         hostname = 'myTest'
         command = 'srp client host name ' + hostname
         ocf.execute_command(cli, command)
         cli.expect('Done', timeout=5)
         cli_global_unicast_addr = ocf.get_global_unicast_addr(cli, br)
-        print('cli_global_unicast_addr', cli_global_unicast_addr)
+        logging.info(f'cli_global_unicast_addr {cli_global_unicast_addr}')
         command = 'srp client host address ' + str(cli_global_unicast_addr)
         ocf.execute_command(cli, command)
         cli.expect('Done', timeout=5)
@@ -397,17 +400,17 @@ def test_service_discovery_of_Thread_device(
         ocf.wait(cli, 3)
         command = 'avahi-browse -rt _testyyy._udp'
         out_str = subprocess.getoutput(command)
-        print('avahi-browse:\n', str(out_str))
+        logging.info(f'avahi-browse:\n {out_str}')
         assert 'myTest' in str(out_str)
     finally:
-        ocf.execute_command(br, 'factoryreset')
-        ocf.execute_command(cli, 'factoryreset')
+        ocf.stop_thread(cli)
+        ocf.stop_thread(br)
         time.sleep(3)
 
 
 # Case 6: discover dervice published by Wi-Fi device
 @pytest.mark.openthread_br
-@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -442,7 +445,7 @@ def test_service_discovery_of_WiFi_device(
         cli.expect('Done', timeout=5)
         ocf.wait(cli, 1)
         domain_name = ocf.get_domain()
-        print('domain name is: ', domain_name)
+        logging.info(f'domain name is: {domain_name}')
         command = 'dns resolve ' + domain_name + '.default.service.arpa.'
 
         ocf.execute_command(cli, command)
@@ -470,14 +473,14 @@ def test_service_discovery_of_WiFi_device(
     finally:
         ocf.host_close_service()
         sp.terminate()
-        ocf.execute_command(br, 'factoryreset')
-        ocf.execute_command(cli, 'factoryreset')
+        ocf.stop_thread(cli)
+        ocf.stop_thread(br)
         time.sleep(3)
 
 
 # Case 7: ICMP communication via NAT64
 @pytest.mark.openthread_br
-@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -504,18 +507,18 @@ def test_ICMP_NAT64(Init_interface: bool, dut: Tuple[IdfDut, IdfDut, IdfDut]) ->
     try:
         assert ocf.is_joined_wifi_network(br)
         host_ipv4_address = ocf.get_host_ipv4_address()
-        print('host_ipv4_address: ', host_ipv4_address)
+        logging.info(f'host_ipv4_address: {host_ipv4_address}')
         rx_nums = ocf.ot_ping(cli, str(host_ipv4_address), count=5)[1]
         assert rx_nums != 0
     finally:
-        ocf.execute_command(br, 'factoryreset')
-        ocf.execute_command(cli, 'factoryreset')
+        ocf.stop_thread(cli)
+        ocf.stop_thread(br)
         time.sleep(3)
 
 
 # Case 8: UDP communication via NAT64
 @pytest.mark.openthread_br
-@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -547,7 +550,7 @@ def test_UDP_NAT64(Init_interface: bool, dut: Tuple[IdfDut, IdfDut, IdfDut]) ->
         cli.expect('Done', timeout=5)
         ocf.wait(cli, 3)
         host_ipv4_address = ocf.get_host_ipv4_address()
-        print('host_ipv4_address: ', host_ipv4_address)
+        logging.info(f'host_ipv4_address: {host_ipv4_address}')
         myudp = ocf.udp_parameter('INET4', host_ipv4_address, 5090, '', False, 15.0, b'')
         udp_mission = threading.Thread(target=ocf.create_host_udp_server, args=(myudp,))
         udp_mission.start()
@@ -563,15 +566,15 @@ def test_UDP_NAT64(Init_interface: bool, dut: Tuple[IdfDut, IdfDut, IdfDut]) ->
         while udp_mission.is_alive():
             time.sleep(1)
     finally:
-        ocf.execute_command(br, 'factoryreset')
-        ocf.execute_command(cli, 'factoryreset')
+        ocf.stop_thread(cli)
+        ocf.stop_thread(br)
         time.sleep(3)
     assert b'hello' in myudp.udp_bytes
 
 
 # Case 9: TCP communication via NAT64
 @pytest.mark.openthread_br
-@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -604,7 +607,7 @@ def test_TCP_NAT64(Init_interface: bool, dut: Tuple[IdfDut, IdfDut, IdfDut]) ->
         ocf.wait(cli, 3)
         host_ipv4_address = ocf.get_host_ipv4_address()
         connect_address = ocf.get_ipv6_from_ipv4(host_ipv4_address, br)
-        print('connect_address is: ', connect_address)
+        logging.info(f'connect_address is: {connect_address}')
         mytcp = ocf.tcp_parameter('INET4', host_ipv4_address, 12345, False, False, 15.0, b'')
         tcp_mission = threading.Thread(target=ocf.create_host_tcp_server, args=(mytcp,))
         tcp_mission.start()
@@ -625,14 +628,15 @@ def test_TCP_NAT64(Init_interface: bool, dut: Tuple[IdfDut, IdfDut, IdfDut]) ->
         while tcp_mission.is_alive():
             time.sleep(1)
     finally:
-        ocf.execute_command(br, 'factoryreset')
-        ocf.execute_command(cli, 'factoryreset')
+        ocf.stop_thread(cli)
+        ocf.stop_thread(br)
         time.sleep(3)
     assert b'hello' in mytcp.tcp_bytes
 
 
 # Case 10: Sleepy device test
 @pytest.mark.openthread_sleep
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -660,6 +664,7 @@ def test_TCP_NAT64(Init_interface: bool, dut: Tuple[IdfDut, IdfDut, IdfDut]) ->
 def test_ot_sleepy_device(dut: Tuple[IdfDut, IdfDut]) -> None:
     leader = dut[0]
     sleepy_device = dut[1]
+    ocf.hardreset_dut(sleepy_device)
     fail_info = re.compile(r'Core\W*?\d\W*?register dump')
     try:
         ocf.init_thread(leader)
@@ -686,12 +691,13 @@ def test_ot_sleepy_device(dut: Tuple[IdfDut, IdfDut]) -> None:
         assert not bool(fail_info.search(str(output)))
     finally:
         ocf.execute_command(leader, 'factoryreset')
+        ocf.hardreset_dut(sleepy_device)
         time.sleep(3)
 
 
 # Case 11: Basic startup Test of BR
 @pytest.mark.openthread_br
-@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -725,13 +731,13 @@ def test_basic_startup(dut: Tuple[IdfDut, IdfDut]) -> None:
         br.expect('Done', timeout=5)
         assert ocf.wait_for_join(br, 'leader')
     finally:
-        ocf.execute_command(br, 'factoryreset')
+        ocf.stop_thread(br)
         time.sleep(3)
 
 
 # Case 12: Curl a website via DNS and NAT64
 @pytest.mark.openthread_bbr
-@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -756,23 +762,24 @@ def test_NAT64_DNS(Init_interface: bool, dut: Tuple[IdfDut, IdfDut, IdfDut]) ->
 
     formBasicWiFiThreadNetwork(br, cli)
     try:
+        ocf.wait_for_host_network()
         ocf.execute_command(br, 'bbr')
         br.expect('server16', timeout=5)
         ocf.execute_command(cli, 'dns64server 8.8.8.8')
         cli.expect('Done', timeout=5)
         command = 'curl http://www.espressif.com'
         message = ocf.get_ouput_string(cli, command, 10)
-        assert '<html>' in str(message)
+        assert 'html' in str(message)
         assert '301 Moved Permanently' in str(message)
     finally:
-        ocf.execute_command(br, 'factoryreset')
-        ocf.execute_command(cli, 'factoryreset')
+        ocf.stop_thread(cli)
+        ocf.stop_thread(br)
         time.sleep(3)
 
 
 # Case 13: Meshcop discovery of Border Router
 @pytest.mark.openthread_br
-@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -813,9 +820,9 @@ def test_br_meshcop(Init_interface: bool, Init_avahi: bool, dut: Tuple[IdfDut, I
         except subprocess.CalledProcessError as e:
             output_bytes = e.stdout
         finally:
-            print('out_bytes: ', output_bytes)
+            logging.info(f'out_bytes: {output_bytes!r}')
             output_str = str(output_bytes)
-            print('out_str: ', output_str)
+            logging.info(f'out_str: {output_str}')
 
             assert 'hostname = [esp-ot-br.local]' in str(output_str)
             assert ('address = [' + ipv4_address + ']') in str(output_str)
@@ -826,13 +833,13 @@ def test_br_meshcop(Init_interface: bool, Init_avahi: bool, dut: Tuple[IdfDut, I
             assert 'vn=OpenThread' in str(output_str)
             assert 'rv=1' in str(output_str)
     finally:
-        ocf.execute_command(br, 'factoryreset')
+        ocf.stop_thread(br)
         time.sleep(3)
 
 
 # Case 14: Curl a website over HTTPS via DNS and NAT64
 @pytest.mark.openthread_bbr
-@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -857,21 +864,22 @@ def test_https_NAT64_DNS(Init_interface: bool, dut: Tuple[IdfDut, IdfDut, IdfDut
 
     formBasicWiFiThreadNetwork(br, cli)
     try:
+        ocf.wait_for_host_network()
         ocf.execute_command(cli, 'dns64server 8.8.8.8')
         cli.expect('Done', timeout=5)
         command = 'curl https://www.example.com/'
         message = ocf.get_ouput_string(cli, command, 20)
-        assert '<html>' in str(message)
-        assert 'This domain is for use in illustrative examples in documents' in str(message)
+        assert 'html' in str(message)
+        assert 'This domain is for use in' in str(message)
     finally:
-        ocf.execute_command(br, 'factoryreset')
-        ocf.execute_command(cli, 'factoryreset')
+        ocf.stop_thread(cli)
+        ocf.stop_thread(br)
         time.sleep(3)
 
 
 # Case 15: Thread network formation and attaching with TREL
 @pytest.mark.openthread_br
-@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -917,15 +925,15 @@ def test_trel_connect(dut: Tuple[IdfDut, IdfDut]) -> None:
             rx_nums = ocf.ot_ping(trel_s3, trel_mleid_addr, count=10)[1]
             assert rx_nums > 5
     finally:
-        ocf.execute_command(trel_s3, 'factoryreset')
         for trel in trel_list:
-            ocf.execute_command(trel, 'factoryreset')
+            ocf.stop_thread(trel)
+        ocf.stop_thread(trel_s3)
         time.sleep(3)
 
 
 # Case 16: Thread network BR lib check
 @pytest.mark.openthread_br
-@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -954,6 +962,7 @@ def test_br_lib_check(dut: Tuple[IdfDut, IdfDut]) -> None:
 
 # Case 17: SSED test
 @pytest.mark.openthread_sleep
+@pytest.mark.flaky(reruns=1, reruns_delay=5)
 @pytest.mark.parametrize(
     'config, count, app_path, target, port',
     [
@@ -982,6 +991,7 @@ def test_ot_ssed_device(dut: Tuple[IdfDut, IdfDut]) -> None:
     leader = dut[0]
     ssed_device = dut[1]
     try:
+        ocf.hardreset_dut(ssed_device)
         # CI device must have external XTAL to run SSED case, we will check this here first
         ssed_device.expect('32k XTAL in use', timeout=10)
         ocf.init_thread(leader)
@@ -1021,4 +1031,5 @@ def test_ot_ssed_device(dut: Tuple[IdfDut, IdfDut]) -> None:
         ocf.ping_and_check(dut=leader, target=ssed_address, tx_total=10, timeout=6)
     finally:
         ocf.execute_command(leader, 'factoryreset')
+        ocf.hardreset_dut(ssed_device)
         time.sleep(3)
diff --git a/examples/peripherals/adc/continuous_read/main/continuous_read_main.c b/examples/peripherals/adc/continuous_read/main/continuous_read_main.c
index 307b8da97958..514fb8c5cadd 100644
--- a/examples/peripherals/adc/continuous_read/main/continuous_read_main.c
+++ b/examples/peripherals/adc/continuous_read/main/continuous_read_main.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,22 +14,10 @@
 #include "esp_adc/adc_continuous.h"
 
 #define EXAMPLE_ADC_UNIT                    ADC_UNIT_1
-#define _EXAMPLE_ADC_UNIT_STR(unit)         #unit
-#define EXAMPLE_ADC_UNIT_STR(unit)          _EXAMPLE_ADC_UNIT_STR(unit)
 #define EXAMPLE_ADC_CONV_MODE               ADC_CONV_SINGLE_UNIT_1
-#define EXAMPLE_ADC_ATTEN                   ADC_ATTEN_DB_0
+#define EXAMPLE_ADC_ATTEN                   ADC_ATTEN_DB_12
 #define EXAMPLE_ADC_BIT_WIDTH               SOC_ADC_DIGI_MAX_BITWIDTH
 
-#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
-#define EXAMPLE_ADC_OUTPUT_TYPE             ADC_DIGI_OUTPUT_FORMAT_TYPE1
-#define EXAMPLE_ADC_GET_CHANNEL(p_data)     ((p_data)->type1.channel)
-#define EXAMPLE_ADC_GET_DATA(p_data)        ((p_data)->type1.data)
-#else
-#define EXAMPLE_ADC_OUTPUT_TYPE             ADC_DIGI_OUTPUT_FORMAT_TYPE2
-#define EXAMPLE_ADC_GET_CHANNEL(p_data)     ((p_data)->type2.channel)
-#define EXAMPLE_ADC_GET_DATA(p_data)        ((p_data)->type2.data)
-#endif
-
 #define EXAMPLE_READ_LEN                    256
 
 #if CONFIG_IDF_TARGET_ESP32
@@ -63,7 +51,6 @@ static void continuous_adc_init(adc_channel_t *channel, uint8_t channel_num, adc
     adc_continuous_config_t dig_cfg = {
         .sample_freq_hz = 20 * 1000,
         .conv_mode = EXAMPLE_ADC_CONV_MODE,
-        .format = EXAMPLE_ADC_OUTPUT_TYPE,
     };
 
     adc_digi_pattern_config_t adc_pattern[SOC_ADC_PATT_LEN_MAX] = {0};
@@ -114,23 +101,33 @@ void app_main(void)
          */
         ulTaskNotifyTake(pdTRUE, portMAX_DELAY);
 
-        char unit[] = EXAMPLE_ADC_UNIT_STR(EXAMPLE_ADC_UNIT);
-
         while (1) {
             ret = adc_continuous_read(handle, result, EXAMPLE_READ_LEN, &ret_num, 0);
             if (ret == ESP_OK) {
                 ESP_LOGI("TASK", "ret is %x, ret_num is %"PRIu32" bytes", ret, ret_num);
-                for (int i = 0; i < ret_num; i += SOC_ADC_DIGI_RESULT_BYTES) {
-                    adc_digi_output_data_t *p = (adc_digi_output_data_t*)&result[i];
-                    uint32_t chan_num = EXAMPLE_ADC_GET_CHANNEL(p);
-                    uint32_t data = EXAMPLE_ADC_GET_DATA(p);
-                    /* Check the channel number validation, the data is invalid if the channel num exceed the maximum channel */
-                    if (chan_num < SOC_ADC_CHANNEL_NUM(EXAMPLE_ADC_UNIT)) {
-                        ESP_LOGI(TAG, "Unit: %s, Channel: %"PRIu32", Value: %"PRIx32, unit, chan_num, data);
-                    } else {
-                        ESP_LOGW(TAG, "Invalid data [%s_%"PRIu32"_%"PRIx32"]", unit, chan_num, data);
+
+                adc_continuous_data_t parsed_data[ret_num / SOC_ADC_DIGI_RESULT_BYTES];
+                uint32_t num_parsed_samples = 0;
+
+                esp_err_t parse_ret = adc_continuous_parse_data(handle, result, ret_num, parsed_data, &num_parsed_samples);
+                if (parse_ret == ESP_OK) {
+                    for (int i = 0; i < num_parsed_samples; i++) {
+                        if (parsed_data[i].valid) {
+                            ESP_LOGI(TAG, "ADC%d, Channel: %d, Value: %"PRIu32,
+                                     parsed_data[i].unit + 1,
+                                     parsed_data[i].channel,
+                                     parsed_data[i].raw_data);
+                        } else {
+                            ESP_LOGW(TAG, "Invalid data [ADC%d_Ch%d_%"PRIu32"]",
+                                     parsed_data[i].unit + 1,
+                                     parsed_data[i].channel,
+                                     parsed_data[i].raw_data);
+                        }
                     }
+                } else {
+                    ESP_LOGE(TAG, "Data parsing failed: %s", esp_err_to_name(parse_ret));
                 }
+
                 /**
                  * Because printing is slow, so every time you call `ulTaskNotifyTake`, it will immediately return.
                  * To avoid a task watchdog timeout, add a delay here. When you replace the way you process the data,
diff --git a/examples/peripherals/camera/dvp_dsi/main/dvp_dsi_main.c b/examples/peripherals/camera/dvp_dsi/main/dvp_dsi_main.c
index a3392ca96568..8b27b2241a4d 100644
--- a/examples/peripherals/camera/dvp_dsi/main/dvp_dsi_main.c
+++ b/examples/peripherals/camera/dvp_dsi/main/dvp_dsi_main.c
@@ -96,6 +96,9 @@ void app_main(void)
         .pin = &pin_cfg,
         .bk_buffer_dis = 1,
         .xclk_freq = EXAMPLE_DVP_CAM_XCLK_FREQ_HZ,
+        .cam_data_width = EXAMPLE_DVP_CAM_DATA_WIDTH,
+        .bit_swap_en = false,
+        .byte_swap_en = false,
     };
 
     ret = esp_cam_new_dvp_ctlr(&dvp_config, &cam_handle);
diff --git a/examples/peripherals/camera/dvp_dsi/main/example_config.h b/examples/peripherals/camera/dvp_dsi/main/example_config.h
index b297650636c0..6ff0ec4137bf 100644
--- a/examples/peripherals/camera/dvp_dsi/main/example_config.h
+++ b/examples/peripherals/camera/dvp_dsi/main/example_config.h
@@ -13,13 +13,32 @@ extern "C" {
 #endif
 
 #define EXAMPLE_RGB565_BITS_PER_PIXEL      (16)
+#define EXAMPLE_DVP_CAM_XCLK_FREQ_HZ       (20000000)
+#define EXAMPLE_DVP_CAM_DATA_WIDTH         (8)
+
+#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
+#define EXAMPLE_DVP_CAM_SCCB_SCL_IO        (8)
+#define EXAMPLE_DVP_CAM_SCCB_SDA_IO        (7)
+
+#define EXAMPLE_DVP_CAM_D0_IO              (2)
+#define EXAMPLE_DVP_CAM_D1_IO              (32)
+#define EXAMPLE_DVP_CAM_D2_IO              (33)
+#define EXAMPLE_DVP_CAM_D3_IO              (23)
+#define EXAMPLE_DVP_CAM_D4_IO              (3)
+#define EXAMPLE_DVP_CAM_D5_IO              (6)
+#define EXAMPLE_DVP_CAM_D6_IO              (5)
+#define EXAMPLE_DVP_CAM_D7_IO              (21)
 
+#define EXAMPLE_DVP_CAM_XCLK_IO            (20)
+#define EXAMPLE_DVP_CAM_PCLK_IO            (4)
+#define EXAMPLE_DVP_CAM_DE_IO              (22)
+#define EXAMPLE_DVP_CAM_VSYNC_IO           (37)
+#define EXAMPLE_DVP_CAM_HSYNC_IO           (-1)
+
+#else
 #define EXAMPLE_DVP_CAM_SCCB_SCL_IO        (33)
 #define EXAMPLE_DVP_CAM_SCCB_SDA_IO        (32)
 
-#define EXAMPLE_DVP_CAM_XCLK_FREQ_HZ       (20000000)
-
-#define EXAMPLE_DVP_CAM_DATA_WIDTH         (8)
 #define EXAMPLE_DVP_CAM_D0_IO              (53)
 #define EXAMPLE_DVP_CAM_D1_IO              (54)
 #define EXAMPLE_DVP_CAM_D2_IO              (26)
@@ -28,11 +47,13 @@ extern "C" {
 #define EXAMPLE_DVP_CAM_D5_IO              (45)
 #define EXAMPLE_DVP_CAM_D6_IO              (46)
 #define EXAMPLE_DVP_CAM_D7_IO              (47)
+
 #define EXAMPLE_DVP_CAM_XCLK_IO            (20)
 #define EXAMPLE_DVP_CAM_PCLK_IO            (21)
 #define EXAMPLE_DVP_CAM_DE_IO              (22)
 #define EXAMPLE_DVP_CAM_VSYNC_IO           (23)
 #define EXAMPLE_DVP_CAM_HSYNC_IO           (-1)
+#endif
 
 #if CONFIG_EXAMPLE_CAM_HRES_640
 
diff --git a/examples/peripherals/pcnt/rotary_encoder/pytest_rotary_encoder.py b/examples/peripherals/pcnt/rotary_encoder/pytest_rotary_encoder.py
index 4d6c2271f713..b837cf0f62cd 100644
--- a/examples/peripherals/pcnt/rotary_encoder/pytest_rotary_encoder.py
+++ b/examples/peripherals/pcnt/rotary_encoder/pytest_rotary_encoder.py
@@ -17,6 +17,6 @@ def test_rotary_encoder(dut: Dut) -> None:
     dut.expect_exact('add watch points and register callbacks')
     dut.expect_exact('clear pcnt unit')
     dut.expect_exact('start pcnt unit')
-    res = dut.expect(r'Pulse count: (\d+)')
+    res = dut.expect(r'(?:Pulse count|Watch point event, count): (-?\d+)')
     count_val = res.group(1).decode('utf8')
     assert -100 <= int(count_val) <= 100
diff --git a/examples/protocols/http_server/captive_portal/main/main.c b/examples/protocols/http_server/captive_portal/main/main.c
index 8fd8ef3adea4..ee0d13d5d1de 100644
--- a/examples/protocols/http_server/captive_portal/main/main.c
+++ b/examples/protocols/http_server/captive_portal/main/main.c
@@ -127,7 +127,7 @@ static const httpd_uri_t root = {
 esp_err_t http_404_error_handler(httpd_req_t *req, httpd_err_code_t err)
 {
     // Set status
-    httpd_resp_set_status(req, "302 Temporary Redirect");
+    httpd_resp_set_status(req, "303 See Other");
     // Redirect to the "/" root directory
     httpd_resp_set_hdr(req, "Location", "/");
     // iOS requires content in the response to detect a captive portal, simply redirecting is not sufficient.
diff --git a/tools/cmake/toolchain-esp32p4.cmake b/tools/cmake/toolchain-esp32p4.cmake
index 631cacff54b1..b546ed96fd99 100644
--- a/tools/cmake/toolchain-esp32p4.cmake
+++ b/tools/cmake/toolchain-esp32p4.cmake
@@ -7,13 +7,17 @@ set(CMAKE_CXX_COMPILER riscv32-esp-elf-g++)
 set(CMAKE_ASM_COMPILER riscv32-esp-elf-gcc)
 set(_CMAKE_TOOLCHAIN_PREFIX riscv32-esp-elf-)
 
-remove_duplicated_flags("-march=rv32imafc_zicsr_zifencei_xesppie -mabi=ilp32f ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS)
+set(_CMAKE_TOOLCHAIN_COMMON_FLAGS "-march=rv32imafc_zicsr_zifencei_zaamo_zalrsc_xespv_xesploop -mabi=ilp32f")
+
+remove_duplicated_flags("${_CMAKE_TOOLCHAIN_COMMON_FLAGS} ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS)
 set(CMAKE_C_FLAGS "${UNIQ_CMAKE_C_FLAGS}" CACHE STRING "C Compiler Base Flags" FORCE)
-remove_duplicated_flags("-march=rv32imafc_zicsr_zifencei_xesppie -mabi=ilp32f ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS)
+
+remove_duplicated_flags("${_CMAKE_TOOLCHAIN_COMMON_FLAGS} ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS)
 set(CMAKE_CXX_FLAGS "${UNIQ_CMAKE_CXX_FLAGS}" CACHE STRING "C++ Compiler Base Flags" FORCE)
-remove_duplicated_flags("-march=rv32imafc_zicsr_zifencei_xesppie -mabi=ilp32f ${CMAKE_ASM_FLAGS}" UNIQ_CMAKE_ASM_FLAGS)
-set(CMAKE_ASM_FLAGS "${UNIQ_CMAKE_CXX_FLAGS}" CACHE STRING "Asm Compiler Base Flags" FORCE)
 
-remove_duplicated_flags("-nostartfiles -march=rv32imafc_zicsr_zifencei_xesppie -mabi=ilp32f ${CMAKE_EXE_LINKER_FLAGS}"
+remove_duplicated_flags("${_CMAKE_TOOLCHAIN_COMMON_FLAGS} ${CMAKE_ASM_FLAGS}" UNIQ_CMAKE_ASM_FLAGS)
+set(CMAKE_ASM_FLAGS "${UNIQ_CMAKE_ASM_FLAGS}" CACHE STRING "Asm Compiler Base Flags" FORCE)
+
+remove_duplicated_flags("-nostartfiles ${_CMAKE_TOOLCHAIN_COMMON_FLAGS} ${CMAKE_EXE_LINKER_FLAGS}"
                         UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS)
 set(CMAKE_EXE_LINKER_FLAGS "${UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS}" CACHE STRING "Linker Base Flags" FORCE)
diff --git a/tools/tools.json b/tools/tools.json
index 912dea0453b0..470577d889b5 100644
--- a/tools/tools.json
+++ b/tools/tools.json
@@ -182,51 +182,51 @@
       "versions": [
         {
           "linux-amd64": {
-            "sha256": "4fd6d2517f55161056b735cc53c7ccfa59c30a574a0f4decfad77cae4ca5f711",
-            "size": 175585776,
-            "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20250730/xtensa-esp-elf-14.2.0_20250730-x86_64-linux-gnu.tar.xz"
+            "sha256": "e3d77ad14544814527bbe7a2d0f79ec4592a4e23392c51c7388c0e686b6a6977",
+            "size": 121777696,
+            "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20250920/xtensa-esp-elf-15.2.0_20250920-x86_64-linux-gnu.tar.xz"
           },
           "linux-arm64": {
-            "sha256": "916a3007a75c6e4b252cb1857a00657cd0c90ebc60fc265cfa0f4cd7d18ace5c",
-            "size": 170915376,
-            "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20250730/xtensa-esp-elf-14.2.0_20250730-aarch64-linux-gnu.tar.xz"
+            "sha256": "66ae567726b9d7ab234b16dfebbe5a7ba8891463bfb3e28cc4a45c509c9b0b7b",
+            "size": 118382764,
+            "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20250920/xtensa-esp-elf-15.2.0_20250920-aarch64-linux-gnu.tar.xz"
           },
           "linux-armel": {
-            "sha256": "347f7bd53c45b568d25d0897b119c25e66f8487815fd3192d510c9bebea09d99",
-            "size": 170483528,
-            "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20250730/xtensa-esp-elf-14.2.0_20250730-arm-linux-gnueabi.tar.xz"
+            "sha256": "82602993fe169dc3a14719d16fa29935daf6997b91a50decbe2d53e8b6b6ef69",
+            "size": 114566612,
+            "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20250920/xtensa-esp-elf-15.2.0_20250920-arm-linux-gnueabi.tar.xz"
           },
           "linux-armhf": {
-            "sha256": "9817f0cb2157c17f950ab7de9f8a1af05f4a4147a78c5ab9059cad1a9d2eaa5f",
-            "size": 170230704,
-            "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20250730/xtensa-esp-elf-14.2.0_20250730-arm-linux-gnueabihf.tar.xz"
+            "sha256": "891a4a994b3f692539902af975a0281dce5ad56cc8033618ffe7936f2c2dd050",
+            "size": 121707780,
+            "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20250920/xtensa-esp-elf-15.2.0_20250920-arm-linux-gnueabihf.tar.xz"
           },
           "linux-i686": {
-            "sha256": "bf024e686913baa840f1d545d1c6fdc5d0e622bb79d3f3608648e01ee6170a30",
-            "size": 180427072,
-            "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20250730/xtensa-esp-elf-14.2.0_20250730-i586-linux-gnu.tar.xz"
+            "sha256": "cfcbbb858057f09315cca2444cd3669efded540b10257b775da01406bfe72705",
+            "size": 127186208,
+            "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20250920/xtensa-esp-elf-15.2.0_20250920-i586-linux-gnu.tar.xz"
           },
           "macos": {
-            "sha256": "96d6d8388ba0710b99a0659c1dee29a16dbd0c6c5cc49a5baf91dca634167205",
-            "size": 183740740,
-            "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20250730/xtensa-esp-elf-14.2.0_20250730-x86_64-apple-darwin.tar.xz"
+            "sha256": "ca20292e6d5b1f88e958aec99ea04401b86aa73316677c619edaa7342dd7c552",
+            "size": 118838208,
+            "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-15.2.0_20250920/xtensa-esp-elf-15.2.0_20250920-x86_64-apple-darwin.tar.xz"
           },
           "macos-arm64": {
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           },
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@@ -395,51 +395,51 @@
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