diff --git a/components/bt/controller/lib_esp32 b/components/bt/controller/lib_esp32
index 45910ee1e502..a184fa951eb3 160000
--- a/components/bt/controller/lib_esp32
+++ b/components/bt/controller/lib_esp32
@@ -1 +1 @@
-Subproject commit 45910ee1e50236e9d7219429666d7be7965427aa
+Subproject commit a184fa951eb366c3d99a968a4171feb33b99fb82
diff --git a/components/efuse/esp32p4/sources.cmake b/components/efuse/esp32p4/sources.cmake
index c05edde11921..7712caededc7 100644
--- a/components/efuse/esp32p4/sources.cmake
+++ b/components/efuse/esp32p4/sources.cmake
@@ -1,6 +1,7 @@
 set(EFUSE_SOC_SRCS
     "esp_efuse_utility.c"
     "esp_efuse_fields.c"
+    "esp_efuse_rtc_calib.c"
 )
 
 if(CONFIG_ESP32P4_REV_MIN_FULL GREATER_EQUAL 300)
@@ -10,6 +11,5 @@ if(CONFIG_ESP32P4_REV_MIN_FULL GREATER_EQUAL 300)
 else()
     list(APPEND EFUSE_SOC_SRCS
         "esp_efuse_table.c"
-        "esp_efuse_rtc_calib.c"
     )
 endif()
diff --git a/components/esp_driver_gpio/include/driver/gpio.h b/components/esp_driver_gpio/include/driver/gpio.h
index 04dff3e7ab10..12e166f39d4d 100644
--- a/components/esp_driver_gpio/include/driver/gpio.h
+++ b/components/esp_driver_gpio/include/driver/gpio.h
@@ -383,23 +383,25 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *stren
   * signal or the IO MUX/GPIO configuration is modified (including input enable, output enable, output value,
   * function, and drive strength values). This function can be used to retain the state of GPIOs when the power
   * domain of where GPIO/IOMUX belongs to becomes off. For example, chip or system is reset (e.g. watchdog
-  * time-out, deep-sleep events are triggered), or peripheral power-down in light-sleep.
+  * time-out, Deep-sleep events are triggered), or peripheral power-down in Light-sleep.
   *
   * This function works in both input and output modes, and only applicable to output-capable GPIOs.
   * If this function is enabled:
   *   in output mode: the output level of the GPIO will be locked and can not be changed.
   *   in input mode: the input read value can still reflect the changes of the input signal.
   *
+  * Power down or call `gpio_hold_dis` will disable this function.
+  *
   * Please be aware that,
   *
-  * On ESP32P4, the states of IOs can not be hold after waking up from Deep-sleep.
+  * 1. USB pads cannot hold at low level after waking up from Deep-sleep. The USB related registers are reset, so the USB pull-up is back.
+  *
+  * 2. For ESP32-P4 rev < 3.0, the states of IOs can not be hold after waking up from Deep-sleep.
   *
-  * Additionally, on ESP32/S2/C3/S3/C2, this function cannot be used to hold the state of a digital GPIO during Deep-sleep.
+  * 3. For ESP32/S2/C3/S3/C2, this function cannot be used to hold the state of a digital GPIO during Deep-sleep.
   * Even if this function is enabled, the digital GPIO will be reset to its default state when the chip wakes up from
   * Deep-sleep. If you want to hold the state of a digital GPIO during Deep-sleep, please call `gpio_deep_sleep_hold_en`.
   *
-  * Power down or call `gpio_hold_dis` will disable this function.
-  *
   * @param gpio_num GPIO number, only support output-capable GPIOs
   *
   * @return
@@ -427,7 +429,7 @@ esp_err_t gpio_hold_en(gpio_num_t gpio_num);
   */
 esp_err_t gpio_hold_dis(gpio_num_t gpio_num);
 
-#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 /**
   * @brief Enable all digital gpio pads hold function during Deep-sleep.
   *
@@ -451,7 +453,7 @@ void gpio_deep_sleep_hold_en(void);
   * @brief Disable all digital gpio pads hold function during Deep-sleep.
   */
 void gpio_deep_sleep_hold_dis(void);
-#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 
 /**
   * @brief Set pad input to a peripheral signal through the IOMUX.
diff --git a/components/esp_driver_gpio/src/gpio.c b/components/esp_driver_gpio/src/gpio.c
index c694558a00c2..eaf7909edb25 100644
--- a/components/esp_driver_gpio/src/gpio.c
+++ b/components/esp_driver_gpio/src/gpio.c
@@ -8,13 +8,13 @@
 #include "esp_err.h"
 #include "freertos/FreeRTOS.h"
 #include "esp_heap_caps.h"
+#include "sdkconfig.h"
 #include "driver/gpio.h"
 #include "driver/rtc_io.h"
 #include "soc/interrupts.h"
 #if !CONFIG_FREERTOS_UNICORE
 #include "esp_ipc.h"
 #endif
-
 #include "soc/soc_caps.h"
 #include "soc/gpio_periph.h"
 #include "esp_log.h"
@@ -775,7 +775,7 @@ esp_err_t gpio_hold_dis(gpio_num_t gpio_num)
     return ret;
 }
 
-#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 void gpio_deep_sleep_hold_en(void)
 {
     portENTER_CRITICAL(&gpio_context.gpio_spinlock);
@@ -789,7 +789,7 @@ void gpio_deep_sleep_hold_dis(void)
     gpio_hal_deep_sleep_hold_dis(gpio_context.gpio_hal);
     portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
 }
-#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 
 #if SOC_GPIO_SUPPORT_FORCE_HOLD
 esp_err_t IRAM_ATTR gpio_force_hold_all()
diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
index 83921559ba4a..31852fd2d360 100644
--- a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
+++ b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
@@ -884,7 +884,7 @@ TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]")
 }
 #endif
 
-#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
+#if SOC_DEEP_SLEEP_SUPPORTED
 // Pick one digital IO for each target to test is enough
 static void gpio_deep_sleep_hold_test_first_stage(void)
 {
@@ -902,7 +902,9 @@ static void gpio_deep_sleep_hold_test_first_stage(void)
         .pull_up_en = 0,
     };
     TEST_ESP_OK(gpio_config(&io_conf));
-    TEST_ESP_OK(gpio_set_level(io_num, 0));
+
+    const bool initial_level = gpio_get_level(io_num);
+    TEST_ESP_OK(gpio_set_level(io_num, !initial_level));
 
     // Enable global persistence
     TEST_ESP_OK(gpio_hold_en(io_num));
@@ -911,6 +913,10 @@ static void gpio_deep_sleep_hold_test_first_stage(void)
     // Extra step is required, so that all digital IOs can automatically get held when entering Deep-sleep
     gpio_deep_sleep_hold_en();
 #endif
+    vTaskDelay(pdMS_TO_TICKS(200));
+    TEST_ESP_OK(gpio_set_level(io_num, initial_level));
+    TEST_ASSERT_EQUAL_INT(!initial_level, gpio_get_level(io_num));
+    vTaskDelay(pdMS_TO_TICKS(200));
 
     esp_deep_sleep_start();
 }
@@ -921,16 +927,31 @@ static void gpio_deep_sleep_hold_test_second_stage(void)
     // Check reset reason is waking up from deepsleep
     TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
 
-    // Pin should stay at low level after the deep sleep
-    TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num));
+#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // DIG-399
+    bool level = gpio_get_level(io_num);
     // Set level should not take effect since hold is still active (and the INPUT_OUTPUT mode should still be held)
-    TEST_ESP_OK(gpio_set_level(io_num, 1));
-    TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num));
+    TEST_ESP_OK(gpio_set_level(io_num, !level));
+    TEST_ASSERT_EQUAL_INT(level, gpio_get_level(io_num));
+#endif
 
 #if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
     gpio_deep_sleep_hold_dis();
 #endif
     TEST_ESP_OK(gpio_hold_dis(io_num));
+
+    gpio_config_t io_conf = {
+        .intr_type = GPIO_INTR_DISABLE,
+        .mode = GPIO_MODE_INPUT_OUTPUT,
+        .pin_bit_mask = (1ULL << io_num),
+        .pull_down_en = GPIO_PULLDOWN_DISABLE,
+        .pull_up_en = GPIO_PULLUP_DISABLE,
+    };
+    TEST_ESP_OK(gpio_config(&io_conf));
+
+#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // DIG-399
+    // Check that the hold level after wakeup is the level before entering deep sleep
+    TEST_ASSERT_EQUAL_INT(!level, gpio_get_level(io_num));
+#endif
 }
 
 /*
@@ -942,4 +963,4 @@ static void gpio_deep_sleep_hold_test_second_stage(void)
 TEST_CASE_MULTIPLE_STAGES("GPIO_deep_sleep_output_hold_test", "[gpio]",
                           gpio_deep_sleep_hold_test_first_stage,
                           gpio_deep_sleep_hold_test_second_stage)
-#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
+#endif // SOC_DEEP_SLEEP_SUPPORTED
diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h
index 2000b19520d0..3caa9c2001f8 100644
--- a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h
+++ b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h
@@ -39,6 +39,7 @@ extern "C" {
 #define TEST_GPIO_EXT_IN_IO                (3)
 #define TEST_GPIO_INPUT_LEVEL_LOW_PIN      (1)
 #define TEST_GPIO_SIGNAL_IDX               (SIG_IN_FUNC250_IDX)
+#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN      (28)
 #elif CONFIG_IDF_TARGET_ESP32H2
 #define TEST_GPIO_EXT_OUT_IO               (2)
 #define TEST_GPIO_EXT_IN_IO                (3)
diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c
index 180fa89643ff..8956720dca5a 100644
--- a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c
+++ b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c
@@ -235,7 +235,7 @@ TEST_CASE("RTCIO_output_hold_test", "[rtcio]")
 #endif //SOC_RTCIO_HOLD_SUPPORTED
 #endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
 
-#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
+#if SOC_DEEP_SLEEP_SUPPORTED
 // It is not necessary to test every rtcio pin, it will take too much ci testing time for deep sleep
 // Only tests on s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX] pin
 // The default configuration of these pads is low level
@@ -268,8 +268,10 @@ static void rtcio_deep_sleep_hold_test_second_stage(void)
     int io_num = s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX];
     // Check reset reason is waking up from deepsleep
     TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
+#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // DIG-399
     // Pin should stay at high level after the deep sleep
     TEST_ASSERT_EQUAL_INT(1, gpio_get_level(io_num));
+#endif
 
     gpio_hold_dis(io_num);
 }
@@ -283,4 +285,4 @@ static void rtcio_deep_sleep_hold_test_second_stage(void)
 TEST_CASE_MULTIPLE_STAGES("RTCIO_deep_sleep_output_hold_test", "[rtcio]",
                           rtcio_deep_sleep_hold_test_first_stage,
                           rtcio_deep_sleep_hold_test_second_stage)
-#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
+#endif // SOC_DEEP_SLEEP_SUPPORTED
diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h
index bec0d96baa8c..5bd21422e41b 100644
--- a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h
+++ b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h
@@ -146,6 +146,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
     GPIO_NUM_14,   //GPIO14
     GPIO_NUM_15,   //GPIO15
 };
+#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO5
 #elif CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C5
 // Has no input-only rtcio pins, all pins support pull-up/down
 #define RTCIO_SUPPORT_PU_PD(num)    1
diff --git a/components/esp_driver_isp/src/isp_bf.c b/components/esp_driver_isp/src/isp_bf.c
index 066076624f02..1c71d0eefd0c 100644
--- a/components/esp_driver_isp/src/isp_bf.c
+++ b/components/esp_driver_isp/src/isp_bf.c
@@ -43,6 +43,9 @@ esp_err_t esp_isp_bf_configure(isp_proc_handle_t proc, const esp_isp_bf_config_t
         isp_hal_bf_config(&(proc->hal), NULL);
     }
 
+    bool valid = isp_ll_shadow_update_bf(proc->hal.hw);
+    ESP_RETURN_ON_FALSE_ISR(valid, ESP_ERR_INVALID_STATE, TAG, "failed to update bf shadow register");
+
     return ESP_OK;
 }
 
diff --git a/components/esp_driver_isp/src/isp_blc.c b/components/esp_driver_isp/src/isp_blc.c
index c808e66d04d1..f8faa2774bcf 100644
--- a/components/esp_driver_isp/src/isp_blc.c
+++ b/components/esp_driver_isp/src/isp_blc.c
@@ -58,6 +58,9 @@ esp_err_t esp_isp_blc_configure(isp_proc_handle_t isp_proc, const esp_isp_blc_co
     // Configure stretch enable for each channel
     isp_ll_blc_enable_stretch(isp_proc->hal.hw, config->stretch.top_left_chan_stretch_en, config->stretch.top_right_chan_stretch_en, config->stretch.bottom_left_chan_stretch_en, config->stretch.bottom_right_chan_stretch_en);
 
+    bool valid = isp_ll_shadow_update_blc(isp_proc->hal.hw);
+    ESP_RETURN_ON_FALSE_ISR(valid, ESP_ERR_INVALID_STATE, TAG, "failed to update blc shadow register");
+
     return ESP_OK;
 }
 
diff --git a/components/esp_driver_isp/src/isp_ccm.c b/components/esp_driver_isp/src/isp_ccm.c
index 6ee089c252f2..4168a1ad52e6 100644
--- a/components/esp_driver_isp/src/isp_ccm.c
+++ b/components/esp_driver_isp/src/isp_ccm.c
@@ -22,11 +22,14 @@ esp_err_t esp_isp_ccm_configure(isp_proc_handle_t proc, const esp_isp_ccm_config
     ESP_RETURN_ON_FALSE(proc && ccm_cfg, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
 
     bool ret = true;
+    bool valid = false;
     portENTER_CRITICAL(&proc->spinlock);
     isp_ll_ccm_set_clk_ctrl_mode(proc->hal.hw, ISP_LL_PIPELINE_CLK_CTRL_AUTO);
     ret = isp_hal_ccm_set_matrix(&proc->hal, ccm_cfg->saturation, ccm_cfg->matrix);
+    valid = isp_ll_shadow_update_ccm(proc->hal.hw);
     portEXIT_CRITICAL(&proc->spinlock);
     ESP_RETURN_ON_FALSE(ret, ESP_ERR_INVALID_ARG, TAG, "invalid argument: ccm matrix contain NaN or out of range");
+    ESP_RETURN_ON_FALSE(valid, ESP_ERR_INVALID_STATE, TAG, "failed to update ccm shadow register");
 
     return ESP_OK;
 }
diff --git a/components/esp_driver_isp/src/isp_color.c b/components/esp_driver_isp/src/isp_color.c
index d10504e3f2ff..c3da6d5cdc13 100644
--- a/components/esp_driver_isp/src/isp_color.c
+++ b/components/esp_driver_isp/src/isp_color.c
@@ -43,6 +43,9 @@ esp_err_t esp_isp_color_configure(isp_proc_handle_t proc, const esp_isp_color_co
         isp_hal_color_config(&(proc->hal), NULL);
     }
 
+    bool valid = isp_ll_shadow_update_color(proc->hal.hw);
+    ESP_RETURN_ON_FALSE_ISR(valid, ESP_ERR_INVALID_STATE, TAG, "failed to update color shadow register");
+
     return ESP_OK;
 }
 
diff --git a/components/esp_driver_isp/src/isp_core.c b/components/esp_driver_isp/src/isp_core.c
index b1d1b45e1477..2fb6510d091a 100644
--- a/components/esp_driver_isp/src/isp_core.c
+++ b/components/esp_driver_isp/src/isp_core.c
@@ -178,6 +178,8 @@ esp_err_t esp_isp_new_processor(const esp_isp_processor_cfg_t *proc_config, isp_
         isp_ll_set_byte_swap(proc->hal.hw, true);
     }
 
+    isp_ll_shadow_set_mode(proc->hal.hw, ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC);
+
     proc->in_color_format = in_color_format;
     proc->out_color_format = out_color_format;
     proc->h_res = proc_config->h_res;
diff --git a/components/esp_driver_isp/src/isp_sharpen.c b/components/esp_driver_isp/src/isp_sharpen.c
index b8ac88abeb9f..c0dd2fc25818 100644
--- a/components/esp_driver_isp/src/isp_sharpen.c
+++ b/components/esp_driver_isp/src/isp_sharpen.c
@@ -45,6 +45,9 @@ esp_err_t esp_isp_sharpen_configure(isp_proc_handle_t proc, const esp_isp_sharpe
         isp_hal_sharpen_config(&(proc->hal), NULL);
     }
 
+    bool valid = isp_ll_shadow_update_sharpen(proc->hal.hw);
+    ESP_RETURN_ON_FALSE_ISR(valid, ESP_ERR_INVALID_STATE, TAG, "failed to update sharp shadow register");
+
     return ESP_OK;
 }
 
diff --git a/components/esp_driver_isp/src/isp_wbg.c b/components/esp_driver_isp/src/isp_wbg.c
index e03d0eda52cd..96b809840c5a 100644
--- a/components/esp_driver_isp/src/isp_wbg.c
+++ b/components/esp_driver_isp/src/isp_wbg.c
@@ -61,6 +61,9 @@ esp_err_t esp_isp_wbg_set_wb_gain(isp_proc_handle_t isp_proc, isp_wbg_gain_t gai
     // Set WBG gain
     isp_ll_awb_set_wb_gain(isp_proc->hal.hw, gain);
 
+    bool valid = isp_ll_shadow_update_wbg(isp_proc->hal.hw);
+    ESP_RETURN_ON_FALSE_ISR(valid, ESP_ERR_INVALID_STATE, TAG, "failed to update wbg shadow register");
+
     return ESP_OK;
 }
 
diff --git a/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c b/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c
index c1d9faa340ef..cf0fc5fca86e 100644
--- a/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c
+++ b/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c
@@ -182,6 +182,10 @@ static int usb_serial_jtag_rx_char_no_driver(int fd)
 
 static ssize_t usb_serial_jtag_write(int fd, const void * data, size_t size)
 {
+    if (!usb_serial_jtag_is_connected()) {
+        // TODO: IDF-14303
+        return -1;
+    }
     const char *data_c = (const char *)data;
     /*  Even though newlib does stream locking on each individual stream, we need
      *  a dedicated lock if two streams (stdout and stderr) point to the
@@ -226,6 +230,10 @@ static void usb_serial_jtag_return_char(int fd, int c)
 
 static ssize_t usb_serial_jtag_read(int fd, void* data, size_t size)
 {
+    if (!usb_serial_jtag_is_connected()) {
+        // TODO: IDF-14303
+        return -1;
+    }
     assert(fd == USJ_LOCAL_FD);
     char *data_c = (char *) data;
     size_t received = 0;
@@ -349,6 +357,10 @@ static int usb_serial_jtag_wait_tx_done_no_driver(int fd)
 
 static int usb_serial_jtag_fsync(int fd)
 {
+    if (!usb_serial_jtag_is_connected()) {
+        // TODO: IDF-14303
+        return -1;
+    }
     _lock_acquire_recursive(&s_ctx.write_lock);
     int r = s_ctx.fsync_func(fd);
     _lock_release_recursive(&s_ctx.write_lock);
diff --git a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/main/test_usb_serial_jtag.c b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/main/test_usb_serial_jtag.c
index 9d5ced30117d..88e91fd68780 100644
--- a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/main/test_usb_serial_jtag.c
+++ b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/main/test_usb_serial_jtag.c
@@ -113,6 +113,7 @@ TEST_CASE("see if fsync appears to work", "[usb_serial_jtag]")
     start_us = esp_timer_get_time();
     fsync(0);
     end_us = esp_timer_get_time();
+    vTaskDelay(pdMS_TO_TICKS(500));
     printf("With data in queue: %d us\n", (int)(end_us - start_us));
     TEST_ASSERT_GREATER_THAN_INT(1000, end_us - start_us);
     TEST_ASSERT_LESS_THAN_INT(45000, end_us - start_us); //50ms means fsync hit a timeout
diff --git a/components/esp_hw_support/include/esp_private/esp_sleep_internal.h b/components/esp_hw_support/include/esp_private/esp_sleep_internal.h
index dc2d2f87fe86..7f984e947f86 100644
--- a/components/esp_hw_support/include/esp_private/esp_sleep_internal.h
+++ b/components/esp_hw_support/include/esp_private/esp_sleep_internal.h
@@ -75,7 +75,7 @@ esp_err_t esp_sleep_sub_mode_force_disable(esp_sleep_sub_mode_t mode);
  */
 int32_t* esp_sleep_sub_mode_dump_config(FILE *stream);
 
-#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 /**
  * @brief Isolate all digital IOs except those that are held during deep sleep
  *
diff --git a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
index 295c3f818075..41dc4c48873e 100644
--- a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
+++ b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
@@ -11,6 +11,7 @@
 #include <esp_types.h>
 #include "soc/pmu_struct.h"
 #include "hal/pmu_hal.h"
+#include "sdkconfig.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -330,6 +331,7 @@ typedef struct {
 } pmu_sleep_digital_config_t;
 
 
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 #define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags) {            \
     .syscntl = {                                                        \
         .dig_pad_slp_sel = 0,                                           \
@@ -343,6 +345,19 @@ typedef struct {
         .lp_pad_hold_all = (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
     }                                                                   \
 }
+#else // !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
+#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags) {            \
+    .syscntl = {                                                        \
+        .dig_pad_slp_sel = 0,                                           \
+    }                                                                   \
+}
+
+#define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags) {            \
+    .syscntl = {                                                        \
+        .dig_pad_slp_sel = 0,                                           \
+    }                                                                   \
+}
+#endif
 
 typedef struct {
     struct {
diff --git a/components/esp_hw_support/sleep_gpio.c b/components/esp_hw_support/sleep_gpio.c
index efea60ec3764..94720466a612 100644
--- a/components/esp_hw_support/sleep_gpio.c
+++ b/components/esp_hw_support/sleep_gpio.c
@@ -127,7 +127,7 @@ void esp_sleep_enable_gpio_switch(bool enable)
     }
 }
 
-#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 IRAM_ATTR void esp_sleep_isolate_digital_gpio(void)
 {
     gpio_hal_context_t gpio_hal = {
@@ -182,7 +182,7 @@ IRAM_ATTR void esp_sleep_isolate_digital_gpio(void)
         }
     }
 }
-#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 
 #if SOC_DEEP_SLEEP_SUPPORTED
 void esp_deep_sleep_wakeup_io_reset(void)
diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index 52d282043c91..768ef06a1f8d 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -861,7 +861,7 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint
     }
 #endif
     if (deep_sleep) {
-#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
         esp_sleep_isolate_digital_gpio();
 #endif
 
@@ -2748,6 +2748,13 @@ static SLEEP_FN_ATTR uint32_t get_power_down_flags(void)
         }
     }
 #endif
+
+#if CONFIG_IDF_TARGET_ESP32C6
+    if (!(pd_flags & PMU_SLEEP_PD_TOP)) {
+        // TOP power domain depends on the RTC_PERIPH power domain on ESP32C6, RTC_PERIPH should only be disabled when the TOP domain is down.
+        pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
+    }
+#endif
     return pd_flags;
 }
 
diff --git a/components/esp_phy/lib b/components/esp_phy/lib
index 218d3e79a323..fbc304747bc5 160000
--- a/components/esp_phy/lib
+++ b/components/esp_phy/lib
@@ -1 +1 @@
-Subproject commit 218d3e79a323a437b5f994c32fe7b2144f54ca8c
+Subproject commit fbc304747bc55b40ef7225130fcf87f43b981482
diff --git a/components/esp_pm/test_apps/esp_pm/main/CMakeLists.txt b/components/esp_pm/test_apps/esp_pm/main/CMakeLists.txt
index 48c7ad8ed7aa..8f23c7c05742 100644
--- a/components/esp_pm/test_apps/esp_pm/main/CMakeLists.txt
+++ b/components/esp_pm/test_apps/esp_pm/main/CMakeLists.txt
@@ -5,5 +5,5 @@ set(sources "test_app_main.c"
 # the component must be registered as a WHOLE_ARCHIVE
 idf_component_register(SRCS ${sources}
                        INCLUDE_DIRS "."
-                       PRIV_REQUIRES unity esp_pm ulp driver esp_timer esp_psram
+                       PRIV_REQUIRES unity esp_pm ulp driver esp_timer esp_psram esp_vfs_console
                        WHOLE_ARCHIVE)
diff --git a/components/esp_pm/test_apps/esp_pm/main/test_pm.c b/components/esp_pm/test_apps/esp_pm/main/test_pm.c
index 9f69163629b7..8d62c3cee66b 100644
--- a/components/esp_pm/test_apps/esp_pm/main/test_pm.c
+++ b/components/esp_pm/test_apps/esp_pm/main/test_pm.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -7,6 +7,7 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <stdint.h>
+#include <unistd.h>
 #include <time.h>
 #include <sys/time.h>
 #include <sys/param.h>
@@ -400,6 +401,29 @@ TEST_CASE("esp_timer with SKIP_UNHANDLED_EVENTS does not wake up CPU from sleep"
     TEST_ESP_OK(esp_timer_delete(periodic_timer));
 }
 
+TEST_CASE("Test USJ printing doesn't block CPU on chip wake-up", "[pm]")
+{
+    light_sleep_enable();
+    fflush(stdout);
+    fsync(fileno(stdout));
+    int64_t printing_time_cost_us = 0, time_end, time_start;
+
+    for (int i = 0; i < 20; ++i)
+    {
+        time_start = esp_timer_get_time();
+        printf("Dummy print %02d\n", i);
+        fflush(stdout);
+        fsync(fileno(stdout));
+        time_end = esp_timer_get_time();
+        printing_time_cost_us += time_end - time_start;
+        vTaskDelay(10);
+    }
+    int32_t avg_cost = (int32_t)(printing_time_cost_us / 20);
+    printf("Average cost per print %ld\n", avg_cost);
+    TEST_ASSERT_LESS_THAN(5000, avg_cost);
+    light_sleep_disable();
+}
+
 #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
 
 #endif // CONFIG_PM_ENABLE
diff --git a/components/esp_rom/esp32/ld/esp32.rom.ld b/components/esp_rom/esp32/ld/esp32.rom.ld
index 8fd3ab18c10a..6cca533158f7 100644
--- a/components/esp_rom/esp32/ld/esp32.rom.ld
+++ b/components/esp_rom/esp32/ld/esp32.rom.ld
@@ -1633,6 +1633,9 @@ PROVIDE ( ld_pscan_em_init = 0x4003e5e8 );
 PROVIDE ( ld_acl_rsw_start = 0x40032e90 );
 PROVIDE ( ld_acl_sniff_enter = 0x40031244 );
 PROVIDE ( ld_acl_sniff_trans_sched = 0x40033734 );
+PROVIDE ( ld_acl_afh_apply = 0x40030e94 );
+PROVIDE ( ld_acl_afh_switch_on_cbk = 0x40030fa8 );
+PROVIDE ( ld_acl_afh_switch_off_cbk = 0x400310c4 );
 PROVIDE ( lc_pwr_decr_ind_handler = 0x4002859c );
 PROVIDE ( lc_pwr_incr_ind_handler = 0x400284a8 );
 PROVIDE ( lc_pwr_max_ind_handler = 0x40028690 );
diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld
index 2977468580d6..620cc3cececf 100644
--- a/components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld
+++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld
@@ -31,7 +31,7 @@ coex_hw_timer_set = 0x40000a64;
 coex_schm_interval_set = 0x40000a68;
 coex_schm_lock = 0x40000a6c;
 coex_schm_unlock = 0x40000a70;
-coex_status_get = 0x40000a74;
+/* coex_status_get = 0x40000a74; */
 coex_wifi_release = 0x40000a78;
 esp_coex_ble_conn_dynamic_prio_get = 0x40000a7c;
 /* Data (.data, .bss, .rodata) */
diff --git a/components/esp_security/src/init.c b/components/esp_security/src/init.c
index 16ef897badd4..86cc0a6fd276 100644
--- a/components/esp_security/src/init.c
+++ b/components/esp_security/src/init.c
@@ -55,6 +55,16 @@ static void esp_key_mgr_init(void)
 
 ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103)
 {
+#if CONFIG_IDF_TARGET_ESP32C5
+    // Check for unsupported configuration: flash encryption with CPU frequency > 160MHz
+    // Manual encrypted flash writes are not stable at higher CPU clock.
+    // Please refer to the ESP32-C5 SoC Errata document for more details.
+    if (efuse_hal_flash_encryption_enabled() && CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ > 160) {
+        ESP_EARLY_LOGE(TAG, "Flash encryption with CPU frequency > 160MHz is not supported. Please reconfigure the CPU frequency.");
+        return ESP_ERR_NOT_SUPPORTED;
+    }
+#endif
+
     esp_crypto_clk_init();
     esp_key_mgr_init();
 #if CONFIG_ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP
diff --git a/components/esp_system/port/CMakeLists.txt b/components/esp_system/port/CMakeLists.txt
index 8ba4c6fce8e7..9e937b11cf31 100644
--- a/components/esp_system/port/CMakeLists.txt
+++ b/components/esp_system/port/CMakeLists.txt
@@ -6,6 +6,10 @@ endif()
 
 target_include_directories(${COMPONENT_LIB} PRIVATE ${INCLUDE_FILES} include/private)
 
+if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3 AND CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_400)
+    message(WARNING "400 MHz CPU frequency is not guaranteed to work on all chips with revision prior to rev 3!")
+endif()
+
 set(srcs "cpu_start.c" "panic_handler.c" "esp_system_chip.c")
 
 if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
index a6fadcda7fd2..ea59796c4441 100644
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@@ -656,6 +656,10 @@ NOINLINE_ATTR static void system_early_init(const soc_reset_reason_t *rst_reas)
     REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
 #endif
 #elif CONFIG_IDF_TARGET_ESP32P4
+#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
+    // In single core mode, the CPU system should ignore the WFI state of core1 when entering WFI autoclock gating mode.
+    REG_CLR_BIT(HP_SYS_CLKRST_CPU_WAITI_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN);
+#endif
     REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN);
     REG_SET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL);
 #endif // CONFIG_IDF_TARGET_ESP32
diff --git a/components/esp_system/port/soc/esp32c5/Kconfig.cpu b/components/esp_system/port/soc/esp32c5/Kconfig.cpu
index 0ce4f03b2bbd..cf4222222941 100644
--- a/components/esp_system/port/soc/esp32c5/Kconfig.cpu
+++ b/components/esp_system/port/soc/esp32c5/Kconfig.cpu
@@ -1,9 +1,12 @@
 choice ESP_DEFAULT_CPU_FREQ_MHZ
     prompt "CPU frequency"
     default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA
+    default ESP_DEFAULT_CPU_FREQ_MHZ_160 if SECURE_FLASH_ENC_ENABLED
     default ESP_DEFAULT_CPU_FREQ_MHZ_240
     help
-        CPU frequency to be set on application startup.
+        CPU frequency to be set on application startup. For flash encryption enabled case,
+        the default CPU frequency is 160MHz as the encrypted flash writes are not stable at
+        higher CPU clock. Please see SoC Errata document for details.
 
     config ESP_DEFAULT_CPU_FREQ_MHZ_40
         bool "40 MHz"
@@ -13,6 +16,9 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
     config ESP_DEFAULT_CPU_FREQ_MHZ_160
         bool "160 MHz"
     config ESP_DEFAULT_CPU_FREQ_MHZ_240
+        # Encrypted flash writes aren't supported at 240 MHz.
+        # Please see SoC Errata document for details.
+        depends on !SECURE_FLASH_ENC_ENABLED
         bool "240 MHz"
 endchoice
 
diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c
index 432b22dcd48a..871b7a2ab298 100644
--- a/components/esp_system/port/soc/esp32c5/clk.c
+++ b/components/esp_system/port/soc/esp32c5/clk.c
@@ -209,6 +209,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
             rtc_clk_32k_enable(false);
             rtc_clk_32k_disable_external();
         }
+        // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection.
+        pmu_lp_power_t lp_clk_power = {
+            .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW),
+            .xpd_rc32k = 0,
+            .xpd_fosc = 1,
+            .pd_osc = 0
+        };
+        pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val);
+
         if (SLOW_CLK_CAL_CYCLES > 0) {
             /* TODO: 32k XTAL oscillator has some frequency drift at startup.
              * Improve calibration routine to wait until the frequency is stable.
diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c
index a656425f1c42..711f6ab8c545 100644
--- a/components/esp_system/port/soc/esp32c6/clk.c
+++ b/components/esp_system/port/soc/esp32c6/clk.c
@@ -195,6 +195,14 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
         if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
             rtc_clk_rc32k_enable(false);
         }
+        // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection.
+        pmu_lp_power_t lp_clk_power = {
+            .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW),
+            .xpd_rc32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K),
+            .xpd_fosc = 1,
+            .pd_osc = 0
+        };
+        pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val);
 
         if (SLOW_CLK_CAL_CYCLES > 0) {
             /* TODO: 32k XTAL oscillator has some frequency drift at startup.
diff --git a/components/esp_system/port/soc/esp32c61/clk.c b/components/esp_system/port/soc/esp32c61/clk.c
index cb891009fd62..58b471495931 100644
--- a/components/esp_system/port/soc/esp32c61/clk.c
+++ b/components/esp_system/port/soc/esp32c61/clk.c
@@ -159,6 +159,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
             rtc_clk_32k_enable(false);
             rtc_clk_32k_disable_external();
         }
+        // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection.
+        pmu_lp_power_t lp_clk_power = {
+            .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW),
+            .xpd_rc32k = 0,
+            .xpd_fosc = 1,
+            .pd_osc = 0
+        };
+        pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val);
+
         if (SLOW_CLK_CAL_CYCLES > 0) {
             /* TODO: 32k XTAL oscillator has some frequency drift at startup.
              * Improve calibration routine to wait until the frequency is stable.
diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c
index 315e8cb97734..5794357622df 100644
--- a/components/esp_system/port/soc/esp32h2/clk.c
+++ b/components/esp_system/port/soc/esp32h2/clk.c
@@ -197,6 +197,14 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
         if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
             rtc_clk_rc32k_enable(false);
         }
+        // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection.
+        pmu_lp_power_t lp_clk_power = {
+            .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW),
+            .xpd_rc32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K),
+            .xpd_fosc = 1,
+            .pd_osc = 0
+        };
+        pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val);
 
         if (SLOW_CLK_CAL_CYCLES > 0) {
             /* TODO: 32k XTAL oscillator has some frequency drift at startup.
diff --git a/components/esp_system/port/soc/esp32p4/Kconfig.cpu b/components/esp_system/port/soc/esp32p4/Kconfig.cpu
index 47064a383ac8..d88464cc994d 100644
--- a/components/esp_system/port/soc/esp32p4/Kconfig.cpu
+++ b/components/esp_system/port/soc/esp32p4/Kconfig.cpu
@@ -14,7 +14,6 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
         depends on ESP32P4_SELECTS_REV_LESS_V3
     config ESP_DEFAULT_CPU_FREQ_MHZ_400
         bool "400 MHz"
-        depends on !ESP32P4_SELECTS_REV_LESS_V3
 endchoice
 
 config ESP_DEFAULT_CPU_FREQ_MHZ
diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c
index 8c7e59926636..34d220b7c53a 100644
--- a/components/esp_system/port/soc/esp32p4/clk.c
+++ b/components/esp_system/port/soc/esp32p4/clk.c
@@ -205,6 +205,14 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
         if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
             rtc_clk_rc32k_enable(false);
         }
+        // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection.
+        pmu_lp_power_t lp_clk_power = {
+            .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K),
+            .xpd_rc32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K),
+            .xpd_fosc = 1,
+            .pd_osc = 0
+        };
+        pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val);
 
         if (SLOW_CLK_CAL_CYCLES > 0) {
             /* TODO: 32k XTAL oscillator has some frequency drift at startup.
diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib
index 3fa82c561aa1..b21d04b63e76 160000
--- a/components/esp_wifi/lib
+++ b/components/esp_wifi/lib
@@ -1 +1 @@
-Subproject commit 3fa82c561aa1722d92c1da8b571a09c466629bdd
+Subproject commit b21d04b63e76d001ec5546fc336e7f5c091120fd
diff --git a/components/hal/esp32p4/include/hal/gpio_ll.h b/components/hal/esp32p4/include/hal/gpio_ll.h
index 565604d9672c..1ef00742681a 100644
--- a/components/hal/esp32p4/include/hal/gpio_ll.h
+++ b/components/hal/esp32p4/include/hal/gpio_ll.h
@@ -22,6 +22,7 @@
 #include "soc/io_mux_reg.h"
 #include "soc/io_mux_struct.h"
 #include "soc/hp_system_struct.h"
+#include "soc/lp_system_struct.h"
 #include "soc/lp_iomux_struct.h"
 #include "soc/hp_sys_clkrst_struct.h"
 #include "soc/pmu_struct.h"
@@ -31,6 +32,7 @@
 #include "hal/gpio_types.h"
 #include "hal/misc.h"
 #include "hal/assert.h"
+#include "hal/config.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -494,6 +496,13 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
 __attribute__((always_inline))
 static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    if (gpio_num < 32) {
+        LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 |= (1 << gpio_num);
+    } else {
+        LP_SYS.pad_rtc_hold_ctrl1.pad_rtc_hold_ctrl1 |= (1 << (gpio_num - 32));
+    }
+#else
     uint64_t bit_mask = 1ULL << gpio_num;
     if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
         // GPIO 0-15
@@ -509,6 +518,7 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
             HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high |= (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT));
         }
     }
+#endif
 }
 
 /**
@@ -520,6 +530,13 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
 __attribute__((always_inline))
 static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    if (gpio_num < 32) {
+        LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 &= ~(1 << gpio_num);
+    } else {
+        LP_SYS.pad_rtc_hold_ctrl1.pad_rtc_hold_ctrl1 &= ~(1 << (gpio_num - 32));
+    }
+#else
     uint64_t bit_mask = 1ULL << gpio_num;
     if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
         // GPIO 0-15
@@ -535,6 +552,7 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
             HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high &= ~(bit_mask >> (32 + SOC_RTCIO_PIN_COUNT));
         }
     }
+#endif
 }
 
 /**
@@ -557,6 +575,13 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
         // GPIO 0-15
         abort();
     } else {
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+        if (gpio_num < 32) {
+            return !!(LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 & (1 << gpio_num));
+        } else {
+            return !!(LP_SYS.pad_rtc_hold_ctrl1.pad_rtc_hold_ctrl1 & (1 << (gpio_num - 32)));
+        }
+#else
         if (gpio_num < 32 + SOC_RTCIO_PIN_COUNT) {
             // GPIO 16-47
             return !!(HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low & (bit_mask >> SOC_RTCIO_PIN_COUNT));
@@ -564,6 +589,7 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
             // GPIO 48-54
             return !!(HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high & (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT)));
         }
+#endif
     }
 }
 
diff --git a/components/hal/esp32p4/include/hal/isp_ll.h b/components/hal/esp32p4/include/hal/isp_ll.h
index 67ce434e941a..e4fa919634d5 100644
--- a/components/hal/esp32p4/include/hal/isp_ll.h
+++ b/components/hal/esp32p4/include/hal/isp_ll.h
@@ -190,6 +190,14 @@ typedef enum {
     ISP_LL_PIPELINE_CLK_CTRL_ALWAYS_ON,    ///< Always on
 } isp_ll_pipeline_clk_ctrl_t;
 
+/**
+ * @brief Shadow mode
+ */
+typedef enum {
+    ISP_SHADOW_MODE_DISABLE,
+    ISP_SHADOW_MODE_UPDATE_EVERY_VSYNC,
+    ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC,
+} isp_ll_shadow_mode_t;
 
 /*---------------------------------------------------------------
                       Clock
@@ -1830,6 +1838,224 @@ static inline void isp_ll_demosaic_set_padding_line_tail_valid_end_pixel(isp_dev
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->demosaic_matrix_ctrl, demosaic_tail_pixen_pulse_th, end_pixel);
 }
 
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+/*---------------------------------------------------------------
+                      Shadow
+---------------------------------------------------------------*/
+/**
+ * @brief Shadow mode
+ *
+ * @param[in] hw      Hardware instance address
+ * @param[in] mode    'isp_ll_shadow_mode_t`
+ */
+static inline void isp_ll_shadow_set_mode(isp_dev_t *hw, isp_ll_shadow_mode_t mode)
+{
+    hw->shadow_reg_ctrl.shadow_update_sel = mode;
+}
+
+/**
+ * @brief Update BLC shadow register
+ *
+ * @param[in] hw      Hardware instance address
+ * @return
+ *      - True if update is successful, False otherwise
+ */
+static inline bool isp_ll_shadow_update_blc(isp_dev_t *hw)
+{
+    //only valid when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
+    HAL_ASSERT(hw->shadow_reg_ctrl.shadow_update_sel == ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC);
+
+    if (hw->shadow_reg_ctrl.blc_update == 1) {
+        return false;
+    }
+
+    //self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
+    hw->shadow_reg_ctrl.blc_update = 1;
+
+    return true;
+}
+
+/**
+ * @brief Update DPC shadow register
+ *
+ * @param[in] hw      Hardware instance address
+ * @return
+ *      - True if update is successful, False otherwise
+ */
+static inline bool isp_ll_shadow_update_dpc(isp_dev_t *hw)
+{
+    //only valid when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
+    HAL_ASSERT(hw->shadow_reg_ctrl.shadow_update_sel == ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC);
+
+    if (hw->shadow_reg_ctrl.dpc_update == 1) {
+        return false;
+    }
+
+    //self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
+    hw->shadow_reg_ctrl.dpc_update = 1;
+
+    return true;
+}
+
+/**
+ * @brief Update BF shadow register
+ *
+ * @param[in] hw      Hardware instance address
+ * @return
+ *      - True if update is successful, False otherwise
+ */
+static inline bool isp_ll_shadow_update_bf(isp_dev_t *hw)
+{
+    //only valid when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
+    HAL_ASSERT(hw->shadow_reg_ctrl.shadow_update_sel == ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC);
+
+    if (hw->shadow_reg_ctrl.bf_update == 1) {
+        return false;
+    }
+
+    //self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
+    hw->shadow_reg_ctrl.bf_update = 1;
+
+    return true;
+}
+
+/**
+ * @brief Update WBG shadow register
+ *
+ * @param[in] hw      Hardware instance address
+ * @return
+ *      - True if update is successful, False otherwise
+ */
+static inline bool isp_ll_shadow_update_wbg(isp_dev_t *hw)
+{
+    //only valid when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
+    HAL_ASSERT(hw->shadow_reg_ctrl.shadow_update_sel == ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC);
+
+    if (hw->shadow_reg_ctrl.wbg_update == 1) {
+        return false;
+    }
+
+    //self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
+    hw->shadow_reg_ctrl.wbg_update = 1;
+
+    return true;
+}
+
+/**
+ * @brief Update CCM shadow register
+ *
+ * @param[in] hw      Hardware instance address
+ * @return
+ *      - True if update is successful, False otherwise
+ */
+static inline bool isp_ll_shadow_update_ccm(isp_dev_t *hw)
+{
+    //only valid when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
+    HAL_ASSERT(hw->shadow_reg_ctrl.shadow_update_sel == ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC);
+
+    if (hw->shadow_reg_ctrl.ccm_update == 1) {
+        return false;
+    }
+
+    //self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
+    hw->shadow_reg_ctrl.ccm_update = 1;
+
+    return true;
+}
+
+/**
+ * @brief Update Sharpen shadow register
+ *
+ * @param[in] hw      Hardware instance address
+ * @return
+ *      - True if update is successful, False otherwise
+ */
+static inline bool isp_ll_shadow_update_sharpen(isp_dev_t *hw)
+{
+    //only valid when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
+    HAL_ASSERT(hw->shadow_reg_ctrl.shadow_update_sel == ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC);
+
+    if (hw->shadow_reg_ctrl.sharp_update == 1) {
+        return false;
+    }
+
+    //self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
+    hw->shadow_reg_ctrl.sharp_update = 1;
+
+    return true;
+}
+
+/**
+ * @brief Update Color shadow register
+ *
+ * @param[in] hw      Hardware instance address
+ * @return
+ *      - True if update is successful, False otherwise
+ */
+static inline bool isp_ll_shadow_update_color(isp_dev_t *hw)
+{
+    //only valid when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
+    HAL_ASSERT(hw->shadow_reg_ctrl.shadow_update_sel == ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC);
+
+    if (hw->shadow_reg_ctrl.color_update == 1) {
+        return false;
+    }
+
+    //self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
+    hw->shadow_reg_ctrl.color_update = 1;
+
+    return true;
+}
+
+#else
+static inline void isp_ll_shadow_set_mode(isp_dev_t *hw, isp_ll_shadow_mode_t mode)
+{
+    //for compatibility
+}
+
+static inline bool isp_ll_shadow_update_blc(isp_dev_t *hw)
+{
+    //for compatibility
+    return true;
+}
+
+static inline bool isp_ll_shadow_update_dpc(isp_dev_t *hw)
+{
+    //for compatibility
+    return true;
+}
+
+static inline bool isp_ll_shadow_update_bf(isp_dev_t *hw)
+{
+    //for compatibility
+    return true;
+}
+
+static inline bool isp_ll_shadow_update_wbg(isp_dev_t *hw)
+{
+    //for compatibility
+    return true;
+}
+
+static inline bool isp_ll_shadow_update_ccm(isp_dev_t *hw)
+{
+    //for compatibility
+    return true;
+}
+
+static inline bool isp_ll_shadow_update_sharpen(isp_dev_t *hw)
+{
+    //for compatibility
+    return true;
+}
+
+static inline bool isp_ll_shadow_update_color(isp_dev_t *hw)
+{
+    //for compatibility
+    return true;
+}
+#endif
+
 /*---------------------------------------------------------------
                       Sharpen
 ---------------------------------------------------------------*/
diff --git a/components/hal/esp32p4/include/hal/rtc_io_ll.h b/components/hal/esp32p4/include/hal/rtc_io_ll.h
index f1261cae444b..c663e105b2db 100644
--- a/components/hal/esp32p4/include/hal/rtc_io_ll.h
+++ b/components/hal/esp32p4/include/hal/rtc_io_ll.h
@@ -18,10 +18,12 @@
 #include "soc/lp_gpio_struct.h"
 #include "soc/lp_iomux_struct.h"
 #include "soc/lp_gpio_sig_map.h"
+#include "soc/lp_system_struct.h"
 #include "soc/pmu_struct.h"
 #include "hal/gpio_types.h"
 #include "hal/misc.h"
 #include "hal/assert.h"
+#include "hal/config.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -309,9 +311,13 @@ static inline bool rtcio_ll_is_pulldown_enabled(int rtcio_num)
  */
 static inline void rtcio_ll_force_hold_enable(int rtcio_num)
 {
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 |= BIT(rtcio_num);
+#else
     uint32_t hold_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold);
     hold_mask |= BIT(rtcio_num);
     HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold, hold_mask);
+#endif
 }
 
 /**
@@ -322,9 +328,13 @@ static inline void rtcio_ll_force_hold_enable(int rtcio_num)
  */
 static inline void rtcio_ll_force_hold_disable(int rtcio_num)
 {
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 &= ~BIT(rtcio_num);
+#else
     uint32_t hold_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold);
     hold_mask &= ~BIT(rtcio_num);
     HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold, hold_mask);
+#endif
 }
 
 /**
diff --git a/components/hal/esp32p4/include/hal/usb_wrap_ll.h b/components/hal/esp32p4/include/hal/usb_wrap_ll.h
index d12c91b3dda4..71645076e281 100644
--- a/components/hal/esp32p4/include/hal/usb_wrap_ll.h
+++ b/components/hal/esp32p4/include/hal/usb_wrap_ll.h
@@ -59,8 +59,10 @@ FORCE_INLINE_ATTR void usb_wrap_ll_phy_select(usb_wrap_dev_t *hw, unsigned int p
     switch (phy_idx) {
     case 0:
         LP_SYS.usb_ctrl.sw_usb_phy_sel = true;
+        break;
     case 1:
         LP_SYS.usb_ctrl.sw_usb_phy_sel = false;
+        break;
     default:
         break;
     }
diff --git a/components/hal/include/hal/gpio_hal.h b/components/hal/include/hal/gpio_hal.h
index ee9901935095..ebc0090d946f 100644
--- a/components/hal/include/hal/gpio_hal.h
+++ b/components/hal/include/hal/gpio_hal.h
@@ -323,7 +323,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num);
   */
 #define gpio_hal_is_digital_io_hold(hal, gpio_num) gpio_ll_is_digital_io_hold((hal)->dev, gpio_num)
 
-#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 /**
   * @brief Enable all digital gpio pad hold function during Deep-sleep.
   *
@@ -354,7 +354,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num);
   *     - false deep sleep hold is disabled
   */
 #define gpio_hal_deep_sleep_hold_is_en(hal) gpio_ll_deep_sleep_hold_is_en((hal)->dev)
-#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 
 /**
   * @brief Set pad input to a peripheral signal through the IOMUX.
diff --git a/components/lwip/port/hooks/tcp_isn_default.c b/components/lwip/port/hooks/tcp_isn_default.c
index 71020cee515f..7996b2f3d908 100644
--- a/components/lwip/port/hooks/tcp_isn_default.c
+++ b/components/lwip/port/hooks/tcp_isn_default.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -82,6 +82,10 @@
 #include "esp_rom_md5.h"
 #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
 #include "esp_memory_utils.h"
+#if CONFIG_IDF_TARGET_ESP32
+#include "hal/efuse_hal.h"
+#include "soc/chip_revision.h"
+#endif
 #endif
 
 #ifdef CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT
@@ -169,13 +173,13 @@ lwip_hook_tcp_isn(const ip_addr_t *local_ip, u16_t local_port,
 
   /*
    * Generate the hash using ROM MD5 APIs
-   * This hook is invoked in the context of TCP/IP (tiT) task and
-   * it is unlikely that its stack would be placed in SPIRAM. Hence
-   * even with SPIRAM enabled case and ESP32 revision < 3, using ROM
-   * APIs should not create any issues.
+   * For ESP32 chips prior to ECO3, the stack pointer must not point to external RAM
+   * to use the ROM MD5 functions.
+   * Other chips (ESP32-S2, ESP32-S3, ESP32-C3, etc.) don't have this limitation.
    */
-#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
-  assert(!esp_ptr_external_ram(esp_cpu_get_sp()));
+#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY && CONFIG_IDF_TARGET_ESP32
+  /* Only assert for ESP32 revision < ECO3 (revision 300) */
+  assert(ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 300) || !esp_ptr_external_ram(esp_cpu_get_sp()));
 #endif
 
   md5_context_t ctx;
diff --git a/components/nvs_sec_provider/nvs_sec_provider.c b/components/nvs_sec_provider/nvs_sec_provider.c
index ab9a3e153365..8aaa545c0ce8 100644
--- a/components/nvs_sec_provider/nvs_sec_provider.c
+++ b/components/nvs_sec_provider/nvs_sec_provider.c
@@ -87,15 +87,14 @@ ESP_SYSTEM_INIT_FN(nvs_sec_provider_register_flash_enc_scheme, SECONDARY, BIT(0)
 
     nvs_sec_config_flash_enc_t sec_scheme_cfg = NVS_SEC_PROVIDER_CFG_FLASH_ENC_DEFAULT();
 
-     /*
+    /*
      * This checks partition with subtype nvs_keys from partition table, if NVS Encryption is enabled
-     * and "nvs_keys" do not exist in partition table, then execution gets aborted. To fix the problem,
+     * and "nvs_keys" do not exist in partition table, then warning message is printed. To fix the problem,
      * please introduce partition with subtype "nvs_keys" in the partition table.
      */
 
     if (sec_scheme_cfg.nvs_keys_part == NULL) {
-        ESP_EARLY_LOGE(TAG, "partition with subtype \"nvs_keys\" not found");
-        return ESP_FAIL;
+        ESP_EARLY_LOGW(TAG, "Partition with subtype \"nvs_keys\" not found");
     }
 
     nvs_sec_scheme_t *sec_scheme_handle_out = NULL;
diff --git a/components/openthread/lib b/components/openthread/lib
index bbfee0abaa9c..755f91eb8a13 160000
--- a/components/openthread/lib
+++ b/components/openthread/lib
@@ -1 +1 @@
-Subproject commit bbfee0abaa9c7b08bc55b70c2cc8a04483b41e1d
+Subproject commit 755f91eb8a138da577ea353c08c33eb700f9ac50
diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
index 345b02a59240..cd2ec309ed1e 100644
--- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
@@ -351,10 +351,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
     int
     default 3
 
-config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
-    bool
-    default y
-
 config SOC_I2C_NUM
     int
     default 2
diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h
index 1070c5ad2509..8137a4d1a836 100644
--- a/components/soc/esp32/include/soc/soc_caps.h
+++ b/components/soc/esp32/include/soc/soc_caps.h
@@ -193,9 +193,6 @@
 #define SOC_GPIO_CLOCKOUT_BY_IO_MUX    (1)
 #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM  (3)
 
-// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
-#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
-
 /*-------------------------- I2C CAPS ----------------------------------------*/
 // ESP32 has 2 I2C
 #define SOC_I2C_NUM                (2U)
diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
index ab19f7ca6aaf..c024a9ab021c 100644
--- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
@@ -331,10 +331,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
     int
     default 3
 
-config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
-    bool
-    default y
-
 config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
     int
     default 8
diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h
index 89189ee99611..6bd72b906fd9 100644
--- a/components/soc/esp32c2/include/soc/soc_caps.h
+++ b/components/soc/esp32c2/include/soc/soc_caps.h
@@ -145,9 +145,6 @@
 #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
 #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM       (3)
 
-// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up
-#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
-
 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
index ac62851a2ef6..17e001cf11fd 100644
--- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
@@ -427,10 +427,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
     int
     default 3
 
-config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
-    bool
-    default y
-
 config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
     int
     default 8
diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h
index 61cb2b8a5019..7f7de46c6109 100644
--- a/components/soc/esp32c3/include/soc/soc_caps.h
+++ b/components/soc/esp32c3/include/soc/soc_caps.h
@@ -184,9 +184,6 @@
 #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
 #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM       (3)
 
-// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up
-#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
-
 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
index da6a3343d514..3c63b50a5ceb 100644
--- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@@ -595,10 +595,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
     bool
     default y
 
-config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
-    bool
-    default y
-
 config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
     bool
     default y
diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h
index 7fd8e84ffd05..ad186c54e058 100644
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@@ -236,8 +236,6 @@
 
 // Support to force hold all IOs
 #define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
-// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
-#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
 // Support to hold a single digital I/O when the digital domain is powered off
 #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)
 
diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
index 83cd9d82c567..f365dc2ebdb4 100644
--- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
@@ -527,10 +527,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
     bool
     default y
 
-config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
-    bool
-    default y
-
 config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
     bool
     default y
diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h
index 78c91b2e4735..e0f696a26d7e 100644
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -214,8 +214,6 @@
 
 // Support to force hold all IOs
 #define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
-// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
-#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
 // Support to hold a single digital I/O when the digital domain is powered off
 #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)
 
diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
index e5aac8a1e09e..7469604368a3 100644
--- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
@@ -471,10 +471,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
     bool
     default y
 
-config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
-    bool
-    default y
-
 config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
     bool
     default y
diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h
index c3648dcc6797..6ca25d6febb9 100644
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@@ -193,8 +193,6 @@
 
 // Support to force hold all IOs
 #define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
-// "LP"_IOs and DIG_IOs can be hold during deep sleep and after waking up
-#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP         (1)
 // Support to hold a single digital I/O when the digital domain is powered off
 #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)
 
diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
index 5fcbbf212666..5ebc633d9830 100644
--- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
@@ -543,10 +543,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
     bool
     default y
 
-config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
-    bool
-    default y
-
 config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
     bool
     default y
diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h
index b8749734422d..c3fb45c68972 100644
--- a/components/soc/esp32h2/include/soc/soc_caps.h
+++ b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -238,8 +238,6 @@
 
 // Support to force hold all IOs
 #define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
-// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
-#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
 // Support to hold a single digital I/O when the digital domain is powered off
 #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)
 
diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
index 6db11d52bb03..e763e63460f4 100644
--- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
@@ -339,10 +339,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
     bool
     default y
 
-config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
-    bool
-    default y
-
 config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
     bool
     default y
diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h
index b3155843e6eb..53983e8a4987 100644
--- a/components/soc/esp32h21/include/soc/soc_caps.h
+++ b/components/soc/esp32h21/include/soc/soc_caps.h
@@ -219,8 +219,6 @@
 
 // Support to force hold all IOs
 #define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
-// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
-#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
 // Support to hold a single digital I/O when the digital domain is powered off
 #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)
 
diff --git a/components/soc/esp32p4/emac_periph.c b/components/soc/esp32p4/emac_periph.c
index 8482d97205ff..4d3c028c4f62 100644
--- a/components/soc/esp32p4/emac_periph.c
+++ b/components/soc/esp32p4/emac_periph.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,9 +13,9 @@ const emac_io_info_t emac_io_idx = {
     .mii_tx_clk_i_idx = EMAC_TX_CLK_PAD_IN_IDX,
     .mii_tx_en_o_idx = EMAC_PHY_TXEN_PAD_OUT_IDX,
     .mii_txd0_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX,
-    .mii_txd1_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX,
-    .mii_txd2_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX,
-    .mii_txd3_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX,
+    .mii_txd1_o_idx = EMAC_PHY_TXD1_PAD_OUT_IDX,
+    .mii_txd2_o_idx = EMAC_PHY_TXD2_PAD_OUT_IDX,
+    .mii_txd3_o_idx = EMAC_PHY_TXD3_PAD_OUT_IDX,
     .mii_rx_clk_i_idx = EMAC_RX_CLK_PAD_IN_IDX,
     .mii_rx_dv_i_idx = EMAC_PHY_RXDV_PAD_IN_IDX,
     .mii_rxd0_i_idx = EMAC_PHY_RXD0_PAD_IN_IDX,
diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
index baf2ba116123..2abc997658ae 100644
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -715,6 +715,14 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
     hex
     default 0x007FFFFFFFFF0000
 
+config SOC_GPIO_SUPPORT_FORCE_HOLD
+    bool
+    default y
+
+config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+    bool
+    default y
+
 config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
     bool
     default y
@@ -735,10 +743,6 @@ config SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH
     int
     default 16
 
-config SOC_GPIO_SUPPORT_FORCE_HOLD
-    bool
-    default y
-
 config SOC_RTCIO_PIN_COUNT
     int
     default 16
diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h
index 5d27663b2937..456b67b8b9c4 100644
--- a/components/soc/esp32p4/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h
@@ -463,10 +463,10 @@ typedef enum {
 /**
  * @brief For backward compatibility, old macro definitions are kept. Remove it in the next major release (esp-idf v7.0)
  */
-#define MIPI_DSI_PHY_CLK_SRC_RC_FAST SOC_MOD_CLK_RC_FAST
-#define MIPI_DSI_PHY_CLK_SRC_PLL_F25M SOC_MOD_CLK_PLL_F25M
-#define MIPI_DSI_PHY_CLK_SRC_PLL_F20M SOC_MOD_CLK_PLL_F20M
-#define MIPI_DSI_PHY_CLK_SRC_DEFAULT SOC_MOD_CLK_PLL_F20M
+#define MIPI_DSI_PHY_CLK_SRC_RC_FAST MIPI_DSI_PHY_PLLREF_CLK_SRC_RC_FAST
+#define MIPI_DSI_PHY_CLK_SRC_PLL_F25M MIPI_DSI_PHY_PLLREF_CLK_SRC_PLL_F25M
+#define MIPI_DSI_PHY_CLK_SRC_PLL_F20M MIPI_DSI_PHY_PLLREF_CLK_SRC_PLL_F20M
+#define MIPI_DSI_PHY_CLK_SRC_DEFAULT MIPI_DSI_PHY_PLLREF_CLK_SRC_DEFAULT_LEGACY
 
 /////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
 
diff --git a/components/soc/esp32p4/include/soc/gpio_sig_map.h b/components/soc/esp32p4/include/soc/gpio_sig_map.h
index 2f0560ca0d4f..e1979fb566d0 100644
--- a/components/soc/esp32p4/include/soc/gpio_sig_map.h
+++ b/components/soc/esp32p4/include/soc/gpio_sig_map.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -196,13 +196,9 @@
 #define PWM1_SYNC2_PAD_IN_IDX                              100
 #define PWM1_CH2_B_PAD_OUT_IDX                             100
 #define PWM1_F0_PAD_IN_IDX                                 101
-#define ADP_CHRG_PAD_OUT_IDX                               101
 #define PWM1_F1_PAD_IN_IDX                                 102
-#define ADP_DISCHRG_PAD_OUT_IDX                            102
 #define PWM1_F2_PAD_IN_IDX                                 103
-#define ADP_PRB_EN_PAD_OUT_IDX                             103
 #define PWM1_CAP0_PAD_IN_IDX                               104
-#define ADP_SNS_EN_PAD_OUT_IDX                             104
 #define PWM1_CAP1_PAD_IN_IDX                               105
 #define TWAI0_STANDBY_PAD_OUT_IDX                          105
 #define PWM1_CAP2_PAD_IN_IDX                               106
@@ -224,7 +220,6 @@
 #define USB_SRP_SESSEND_PAD_IN_IDX                         114
 #define USB_OTG11_DRVVBUS_PAD_OUT_IDX                      114
 #define USB_SRP_CHRGVBUS_PAD_OUT_IDX                       115
-#define OTG_DRVVBUS_PAD_OUT_IDX                            116
 #define ULPI_CLK_PAD_IN_IDX                                117
 #define RNG_CHAIN_CLK_PAD_OUT_IDX                          117
 #define USB_HSPHY_REFCLK_IN_IDX                            118
@@ -260,9 +255,7 @@
 #define I3C_SLV_SCL_PAD_OUT_IDX                            136
 #define I3C_SLV_SDA_PAD_IN_IDX                             137
 #define I3C_SLV_SDA_PAD_OUT_IDX                            137
-#define ADP_PRB_PAD_IN_IDX                                 138
 #define I3C_MST_SCL_PULLUP_EN_PAD_OUT_IDX                  138
-#define ADP_SNS_PAD_IN_IDX                                 139
 #define I3C_MST_SDA_PULLUP_EN_PAD_OUT_IDX                  139
 #define USB_JTAG_TDO_BRIDGE_PAD_IN_IDX                     140
 #define USB_JTAG_TDI_BRIDGE_PAD_OUT_IDX                    140
@@ -460,11 +453,11 @@
 #define CORE_GPIO_IN_PAD_IN28_IDX                          242
 #define PARLIO_TX_CS_PAD_OUT_IDX                           242    // only exists on ESP32P4 Rev. 3.0 and later
 #define CORE_GPIO_IN_PAD_IN29_IDX                          243
-#define CORE_GPIO_OUT_PAD_OUT29_IDX                        243
+#define EMAC_PTP_PPS_PAD_OUT_IDX                           243
 #define CORE_GPIO_IN_PAD_IN30_IDX                          244
-#define CORE_GPIO_OUT_PAD_OUT30_IDX                        244
+#define ANA_COMP0_OUT_IDX                                  244
 #define CORE_GPIO_IN_PAD_IN31_IDX                          245
-#define CORE_GPIO_OUT_PAD_OUT31_IDX                        245
+#define ANA_COMP1_OUT_IDX                                  245
 #define RMT_SIG_PAD_IN0_IDX                                246
 #define RMT_SIG_PAD_OUT0_IDX                               246
 #define RMT_SIG_PAD_IN1_IDX                                247
@@ -485,4 +478,5 @@
 #define SIG_IN_FUNC254_IDX                                 254
 #define SIG_IN_FUNC255_IDX                                 255
 #define SIG_IN_FUNC255_IDX                                 255
+// version date 230403
 #define SIG_GPIO_OUT_IDX                                   256
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
index b33af78bdbd8..af7dfdaabe86 100644
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -268,6 +268,11 @@
 // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54)
 #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL
 
+// Support to force hold all IOs
+#define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
+// Support to hold a single digital I/O when the digital domain is powered off
+#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)    // Supported only on ESP32P4 rev >= 3.0 (see DIG-399)
+
 // The Clock Out signal is route to the pin by GPIO matrix
 #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX         (1)
 #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM            (2)
@@ -276,9 +281,6 @@
 #define SOC_DEBUG_PROBE_NUM_UNIT                 (1U)  // Number of debug probe units
 #define SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH         (16) // Maximum width of the debug probe output in each unit
 
-// Support to force hold all IOs
-#define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
-
 /*-------------------------- RTCIO CAPS --------------------------------------*/
 #define SOC_RTCIO_PIN_COUNT                 16
 #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED    1   /* This macro indicates that the target has separate RTC IOMUX hardware feature,
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_eco5_struct.h
deleted file mode 100644
index a3b88516fa41..000000000000
--- a/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_eco5_struct.h
+++ /dev/null
@@ -1,772 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: SDM Configure Registers */
-/** Type of sigmadeltan register
- *  Duty Cycle Configure Register of SDMn
- */
-typedef union {
-    struct {
-        /** sdn_in : R/W; bitpos: [7:0]; default: 0;
-         *  This field is used to configure the duty cycle of sigma delta modulation output.
-         */
-        uint32_t sdn_in:8;
-        /** sdn_prescale : R/W; bitpos: [15:8]; default: 255;
-         *  This field is used to set a divider value to divide APB clock.
-         */
-        uint32_t sdn_prescale:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} gpiosd_sigmadeltan_reg_t;
-
-/** Type of sigmadelta_misc register
- *  MISC Register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** function_clk_en : R/W; bitpos: [30]; default: 0;
-         *  Clock enable bit of sigma delta modulation.
-         */
-        uint32_t function_clk_en:1;
-        /** spi_swap : R/W; bitpos: [31]; default: 0;
-         *  Reserved.
-         */
-        uint32_t spi_swap:1;
-    };
-    uint32_t val;
-} gpiosd_sigmadelta_misc_reg_t;
-
-
-/** Group: Glitch filter Configure Registers */
-/** Type of glitch_filter_chn register
- *  Glitch Filter Configure Register of Channeln
- */
-typedef union {
-    struct {
-        /** filter_ch0_en : R/W; bitpos: [0]; default: 0;
-         *  Glitch Filter channel enable bit.
-         */
-        uint32_t filter_ch0_en:1;
-        /** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
-         *  Glitch Filter input io number.
-         */
-        uint32_t filter_ch0_input_io_num:6;
-        /** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0;
-         *  Glitch Filter window threshold.
-         */
-        uint32_t filter_ch0_window_thres:6;
-        /** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0;
-         *  Glitch Filter window width.
-         */
-        uint32_t filter_ch0_window_width:6;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} gpiosd_glitch_filter_chn_reg_t;
-
-
-/** Group: Etm Configure Registers */
-/** Type of etm_event_chn_cfg register
- *  Etm Config register of Channeln
- */
-typedef union {
-    struct {
-        /** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0;
-         *  Etm event channel select gpio.
-         */
-        uint32_t etm_ch0_event_sel:6;
-        uint32_t reserved_6:1;
-        /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
-         *  Etm event send enable bit.
-         */
-        uint32_t etm_ch0_event_en:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} gpiosd_etm_event_chn_cfg_reg_t;
-
-/** Type of etm_task_p0_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio0_en:1;
-        /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio0_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio1_en:1;
-        /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio1_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio2_en:1;
-        /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio2_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio3_en:1;
-        /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio3_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p0_cfg_reg_t;
-
-/** Type of etm_task_p1_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio4_en:1;
-        /** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio4_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio5_en:1;
-        /** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio5_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio6_en:1;
-        /** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio6_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio7_en:1;
-        /** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio7_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p1_cfg_reg_t;
-
-/** Type of etm_task_p2_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio8_en:1;
-        /** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio8_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio9_en:1;
-        /** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio9_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio10_en:1;
-        /** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio10_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio11_en:1;
-        /** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio11_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p2_cfg_reg_t;
-
-/** Type of etm_task_p3_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio12_en:1;
-        /** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio12_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio13_en:1;
-        /** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio13_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio14_en:1;
-        /** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio14_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio15_en:1;
-        /** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio15_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p3_cfg_reg_t;
-
-/** Type of etm_task_p4_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio16_en:1;
-        /** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio16_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio17_en:1;
-        /** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio17_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio18_en:1;
-        /** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio18_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio19_en:1;
-        /** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio19_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p4_cfg_reg_t;
-
-/** Type of etm_task_p5_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio20_en:1;
-        /** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio20_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio21_en:1;
-        /** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio21_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio22_en:1;
-        /** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio22_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio23_en:1;
-        /** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio23_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p5_cfg_reg_t;
-
-/** Type of etm_task_p6_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio24_en:1;
-        /** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio24_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio25_en:1;
-        /** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio25_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio26_en:1;
-        /** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio26_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio27_en:1;
-        /** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio27_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p6_cfg_reg_t;
-
-/** Type of etm_task_p7_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio28_en:1;
-        /** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio28_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio29_en:1;
-        /** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio29_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio30_en:1;
-        /** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio30_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio31_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio31_en:1;
-        /** etm_task_gpio31_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio31_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p7_cfg_reg_t;
-
-/** Type of etm_task_p8_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio32_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio32_en:1;
-        /** etm_task_gpio32_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio32_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio33_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio33_en:1;
-        /** etm_task_gpio33_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio33_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio34_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio34_en:1;
-        /** etm_task_gpio34_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio34_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio35_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio35_en:1;
-        /** etm_task_gpio35_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio35_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p8_cfg_reg_t;
-
-/** Type of etm_task_p9_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio36_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio36_en:1;
-        /** etm_task_gpio36_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio36_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio37_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio37_en:1;
-        /** etm_task_gpio37_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio37_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio38_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio38_en:1;
-        /** etm_task_gpio38_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio38_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio39_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio39_en:1;
-        /** etm_task_gpio39_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio39_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p9_cfg_reg_t;
-
-/** Type of etm_task_p10_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio40_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio40_en:1;
-        /** etm_task_gpio40_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio40_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio41_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio41_en:1;
-        /** etm_task_gpio41_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio41_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio42_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio42_en:1;
-        /** etm_task_gpio42_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio42_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio43_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio43_en:1;
-        /** etm_task_gpio43_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio43_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p10_cfg_reg_t;
-
-/** Type of etm_task_p11_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio44_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio44_en:1;
-        /** etm_task_gpio44_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio44_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio45_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio45_en:1;
-        /** etm_task_gpio45_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio45_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio46_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio46_en:1;
-        /** etm_task_gpio46_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio46_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio47_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio47_en:1;
-        /** etm_task_gpio47_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio47_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p11_cfg_reg_t;
-
-/** Type of etm_task_p12_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio48_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio48_en:1;
-        /** etm_task_gpio48_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio48_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio49_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio49_en:1;
-        /** etm_task_gpio49_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio49_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio50_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio50_en:1;
-        /** etm_task_gpio50_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio50_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio51_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio51_en:1;
-        /** etm_task_gpio51_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio51_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p12_cfg_reg_t;
-
-/** Type of etm_task_p13_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio52_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio52_en:1;
-        /** etm_task_gpio52_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio52_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio53_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio53_en:1;
-        /** etm_task_gpio53_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio53_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio54_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio54_en:1;
-        /** etm_task_gpio54_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio54_sel:3;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} gpiosd_etm_task_p13_cfg_reg_t;
-
-
-/** Group: Version Register */
-/** Type of version register
- *  Version Control Register
- */
-typedef union {
-    struct {
-        /** gpio_sd_date : R/W; bitpos: [27:0]; default: 35663952;
-         *  Version control register.
-         */
-        uint32_t gpio_sd_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpiosd_version_reg_t;
-
-
-typedef struct {
-    volatile gpiosd_sigmadeltan_reg_t sigmadeltan[8];
-    uint32_t reserved_020;
-    volatile gpiosd_sigmadelta_misc_reg_t sigmadelta_misc;
-    uint32_t reserved_028[2];
-    volatile gpiosd_glitch_filter_chn_reg_t glitch_filter_chn[8];
-    uint32_t reserved_050[4];
-    volatile gpiosd_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
-    uint32_t reserved_080[8];
-    volatile gpiosd_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
-    volatile gpiosd_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
-    volatile gpiosd_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
-    volatile gpiosd_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
-    volatile gpiosd_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
-    volatile gpiosd_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
-    volatile gpiosd_etm_task_p6_cfg_reg_t etm_task_p6_cfg;
-    volatile gpiosd_etm_task_p7_cfg_reg_t etm_task_p7_cfg;
-    volatile gpiosd_etm_task_p8_cfg_reg_t etm_task_p8_cfg;
-    volatile gpiosd_etm_task_p9_cfg_reg_t etm_task_p9_cfg;
-    volatile gpiosd_etm_task_p10_cfg_reg_t etm_task_p10_cfg;
-    volatile gpiosd_etm_task_p11_cfg_reg_t etm_task_p11_cfg;
-    volatile gpiosd_etm_task_p12_cfg_reg_t etm_task_p12_cfg;
-    volatile gpiosd_etm_task_p13_cfg_reg_t etm_task_p13_cfg;
-    uint32_t reserved_0d8[9];
-    volatile gpiosd_version_reg_t version;
-} gpiosd_dev_t;
-
-extern gpiosd_dev_t GPIO;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(gpiosd_dev_t) == 0x100, "Invalid size of gpiosd_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/gpio_sig_map.h b/components/soc/esp32p4/register/hw_ver3/soc/gpio_sig_map.h
deleted file mode 100644
index 65c4a503c068..000000000000
--- a/components/soc/esp32p4/register/hw_ver3/soc/gpio_sig_map.h
+++ /dev/null
@@ -1,483 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#define SD_CARD_CCLK_2_PAD_OUT_IDX               0
-#define SD_CARD_CCMD_2_PAD_IN_IDX                1
-#define SD_CARD_CCMD_2_PAD_OUT_IDX               1
-#define SD_CARD_CDATA0_2_PAD_IN_IDX              2
-#define SD_CARD_CDATA0_2_PAD_OUT_IDX             2
-#define SD_CARD_CDATA1_2_PAD_IN_IDX              3
-#define SD_CARD_CDATA1_2_PAD_OUT_IDX             3
-#define SD_CARD_CDATA2_2_PAD_IN_IDX              4
-#define SD_CARD_CDATA2_2_PAD_OUT_IDX             4
-#define SD_CARD_CDATA3_2_PAD_IN_IDX              5
-#define SD_CARD_CDATA3_2_PAD_OUT_IDX             5
-#define SD_CARD_CDATA4_2_PAD_IN_IDX              6
-#define SD_CARD_CDATA4_2_PAD_OUT_IDX             6
-#define SD_CARD_CDATA5_2_PAD_IN_IDX              7
-#define SD_CARD_CDATA5_2_PAD_OUT_IDX             7
-#define SD_CARD_CDATA6_2_PAD_IN_IDX              8
-#define SD_CARD_CDATA6_2_PAD_OUT_IDX             8
-#define SD_CARD_CDATA7_2_PAD_IN_IDX              9
-#define SD_CARD_CDATA7_2_PAD_OUT_IDX             9
-#define UART0_RXD_PAD_IN_IDX                     10
-#define UART0_TXD_PAD_OUT_IDX                    10
-#define UART0_CTS_PAD_IN_IDX                     11
-#define UART0_RTS_PAD_OUT_IDX                    11
-#define UART0_DSR_PAD_IN_IDX                     12
-#define UART0_DTR_PAD_OUT_IDX                    12
-#define UART1_RXD_PAD_IN_IDX                     13
-#define UART1_TXD_PAD_OUT_IDX                    13
-#define UART1_CTS_PAD_IN_IDX                     14
-#define UART1_RTS_PAD_OUT_IDX                    14
-#define UART1_DSR_PAD_IN_IDX                     15
-#define UART1_DTR_PAD_OUT_IDX                    15
-#define UART2_RXD_PAD_IN_IDX                     16
-#define UART2_TXD_PAD_OUT_IDX                    16
-#define UART2_CTS_PAD_IN_IDX                     17
-#define UART2_RTS_PAD_OUT_IDX                    17
-#define UART2_DSR_PAD_IN_IDX                     18
-#define UART2_DTR_PAD_OUT_IDX                    18
-#define UART3_RXD_PAD_IN_IDX                     19
-#define UART3_TXD_PAD_OUT_IDX                    19
-#define UART3_CTS_PAD_IN_IDX                     20
-#define UART3_RTS_PAD_OUT_IDX                    20
-#define UART3_DSR_PAD_IN_IDX                     21
-#define UART3_DTR_PAD_OUT_IDX                    21
-#define UART4_RXD_PAD_IN_IDX                     22
-#define UART4_TXD_PAD_OUT_IDX                    22
-#define UART4_CTS_PAD_IN_IDX                     23
-#define UART4_RTS_PAD_OUT_IDX                    23
-#define UART4_DSR_PAD_IN_IDX                     24
-#define UART4_DTR_PAD_OUT_IDX                    24
-#define I2S0_O_BCK_PAD_IN_IDX                    25
-#define I2S0_O_BCK_PAD_OUT_IDX                   25
-#define I2S0_MCLK_PAD_IN_IDX                     26
-#define I2S0_MCLK_PAD_OUT_IDX                    26
-#define I2S0_O_WS_PAD_IN_IDX                     27
-#define I2S0_O_WS_PAD_OUT_IDX                    27
-#define I2S0_I_SD_PAD_IN_IDX                     28
-#define I2S0_O_SD_PAD_OUT_IDX                    28
-#define I2S0_I_BCK_PAD_IN_IDX                    29
-#define I2S0_I_BCK_PAD_OUT_IDX                   29
-#define I2S0_I_WS_PAD_IN_IDX                     30
-#define I2S0_I_WS_PAD_OUT_IDX                    30
-#define I2S1_O_BCK_PAD_IN_IDX                    31
-#define I2S1_O_BCK_PAD_OUT_IDX                   31
-#define I2S1_MCLK_PAD_IN_IDX                     32
-#define I2S1_MCLK_PAD_OUT_IDX                    32
-#define I2S1_O_WS_PAD_IN_IDX                     33
-#define I2S1_O_WS_PAD_OUT_IDX                    33
-#define I2S1_I_SD_PAD_IN_IDX                     34
-#define I2S1_O_SD_PAD_OUT_IDX                    34
-#define I2S1_I_BCK_PAD_IN_IDX                    35
-#define I2S1_I_BCK_PAD_OUT_IDX                   35
-#define I2S1_I_WS_PAD_IN_IDX                     36
-#define I2S1_I_WS_PAD_OUT_IDX                    36
-#define I2S2_O_BCK_PAD_IN_IDX                    37
-#define I2S2_O_BCK_PAD_OUT_IDX                   37
-#define I2S2_MCLK_PAD_IN_IDX                     38
-#define I2S2_MCLK_PAD_OUT_IDX                    38
-#define I2S2_O_WS_PAD_IN_IDX                     39
-#define I2S2_O_WS_PAD_OUT_IDX                    39
-#define I2S2_I_SD_PAD_IN_IDX                     40
-#define I2S2_O_SD_PAD_OUT_IDX                    40
-#define I2S2_I_BCK_PAD_IN_IDX                    41
-#define I2S2_I_BCK_PAD_OUT_IDX                   41
-#define I2S2_I_WS_PAD_IN_IDX                     42
-#define I2S2_I_WS_PAD_OUT_IDX                    42
-#define I2S0_I_SD1_PAD_IN_IDX                    43
-#define I2S0_O_SD1_PAD_OUT_IDX                   43
-#define I2S0_I_SD2_PAD_IN_IDX                    44
-#define SPI2_DQS_PAD_OUT_IDX                     44
-#define I2S0_I_SD3_PAD_IN_IDX                    45
-#define SPI3_CS2_PAD_OUT_IDX                     45
-#define SPI3_CS1_PAD_OUT_IDX                     46
-#define SPI3_CK_PAD_IN_IDX                       47
-#define SPI3_CK_PAD_OUT_IDX                      47
-#define SPI3_Q_PAD_IN_IDX                        48
-#define SPI3_QO_PAD_OUT_IDX                      48
-#define SPI3_D_PAD_IN_IDX                        49
-#define SPI3_D_PAD_OUT_IDX                       49
-#define SPI3_HOLD_PAD_IN_IDX                     50
-#define SPI3_HOLD_PAD_OUT_IDX                    50
-#define SPI3_WP_PAD_IN_IDX                       51
-#define SPI3_WP_PAD_OUT_IDX                      51
-#define SPI3_CS_PAD_IN_IDX                       52
-#define SPI3_CS_PAD_OUT_IDX                      52
-#define SPI2_CK_PAD_IN_IDX                       53
-#define SPI2_CK_PAD_OUT_IDX                      53
-#define SPI2_Q_PAD_IN_IDX                        54
-#define SPI2_Q_PAD_OUT_IDX                       54
-#define SPI2_D_PAD_IN_IDX                        55
-#define SPI2_D_PAD_OUT_IDX                       55
-#define SPI2_HOLD_PAD_IN_IDX                     56
-#define SPI2_HOLD_PAD_OUT_IDX                    56
-#define SPI2_WP_PAD_IN_IDX                       57
-#define SPI2_WP_PAD_OUT_IDX                      57
-#define SPI2_IO4_PAD_IN_IDX                      58
-#define SPI2_IO4_PAD_OUT_IDX                     58
-#define SPI2_IO5_PAD_IN_IDX                      59
-#define SPI2_IO5_PAD_OUT_IDX                     59
-#define SPI2_IO6_PAD_IN_IDX                      60
-#define SPI2_IO6_PAD_OUT_IDX                     60
-#define SPI2_IO7_PAD_IN_IDX                      61
-#define SPI2_IO7_PAD_OUT_IDX                     61
-#define SPI2_CS_PAD_IN_IDX                       62
-#define SPI2_CS_PAD_OUT_IDX                      62
-#define PCNT_RST_PAD_IN0_IDX                     63
-#define SPI2_CS1_PAD_OUT_IDX                     63
-#define PCNT_RST_PAD_IN1_IDX                     64
-#define SPI2_CS2_PAD_OUT_IDX                     64
-#define PCNT_RST_PAD_IN2_IDX                     65
-#define SPI2_CS3_PAD_OUT_IDX                     65
-#define PCNT_RST_PAD_IN3_IDX                     66
-#define SPI2_CS4_PAD_OUT_IDX                     66
-#define SPI2_CS5_PAD_OUT_IDX                     67
-#define I2C0_SCL_PAD_IN_IDX                      68
-#define I2C0_SCL_PAD_OUT_IDX                     68
-#define I2C0_SDA_PAD_IN_IDX                      69
-#define I2C0_SDA_PAD_OUT_IDX                     69
-#define I2C1_SCL_PAD_IN_IDX                      70
-#define I2C1_SCL_PAD_OUT_IDX                     70
-#define I2C1_SDA_PAD_IN_IDX                      71
-#define I2C1_SDA_PAD_OUT_IDX                     71
-#define GPIO_SD0_OUT_IDX                         72
-#define GPIO_SD1_OUT_IDX                         73
-#define UART0_SLP_CLK_PAD_IN_IDX                 74
-#define GPIO_SD2_OUT_IDX                         74
-#define UART1_SLP_CLK_PAD_IN_IDX                 75
-#define GPIO_SD3_OUT_IDX                         75
-#define UART2_SLP_CLK_PAD_IN_IDX                 76
-#define GPIO_SD4_OUT_IDX                         76
-#define UART3_SLP_CLK_PAD_IN_IDX                 77
-#define GPIO_SD5_OUT_IDX                         77
-#define UART4_SLP_CLK_PAD_IN_IDX                 78
-#define GPIO_SD6_OUT_IDX                         78
-#define GPIO_SD7_OUT_IDX                         79
-#define TWAI0_RX_PAD_IN_IDX                      80
-#define TWAI0_TX_PAD_OUT_IDX                     80
-#define TWAI0_BUS_OFF_ON_PAD_OUT_IDX             81
-#define TWAI0_CLKOUT_PAD_OUT_IDX                 82
-#define TWAI1_RX_PAD_IN_IDX                      83
-#define TWAI1_TX_PAD_OUT_IDX                     83
-#define TWAI1_BUS_OFF_ON_PAD_OUT_IDX             84
-#define TWAI1_CLKOUT_PAD_OUT_IDX                 85
-#define TWAI2_RX_PAD_IN_IDX                      86
-#define TWAI2_TX_PAD_OUT_IDX                     86
-#define TWAI2_BUS_OFF_ON_PAD_OUT_IDX             87
-#define TWAI2_CLKOUT_PAD_OUT_IDX                 88
-#define PWM0_SYNC0_PAD_IN_IDX                    89
-#define PWM0_CH0_A_PAD_OUT_IDX                   89
-#define PWM0_SYNC1_PAD_IN_IDX                    90
-#define PWM0_CH0_B_PAD_OUT_IDX                   90
-#define PWM0_SYNC2_PAD_IN_IDX                    91
-#define PWM0_CH1_A_PAD_OUT_IDX                   91
-#define PWM0_F0_PAD_IN_IDX                       92
-#define PWM0_CH1_B_PAD_OUT_IDX                   92
-#define PWM0_F1_PAD_IN_IDX                       93
-#define PWM0_CH2_A_PAD_OUT_IDX                   93
-#define PWM0_F2_PAD_IN_IDX                       94
-#define PWM0_CH2_B_PAD_OUT_IDX                   94
-#define PWM0_CAP0_PAD_IN_IDX                     95
-#define PWM1_CH0_A_PAD_OUT_IDX                   95
-#define PWM0_CAP1_PAD_IN_IDX                     96
-#define PWM1_CH0_B_PAD_OUT_IDX                   96
-#define PWM0_CAP2_PAD_IN_IDX                     97
-#define PWM1_CH1_A_PAD_OUT_IDX                   97
-#define PWM1_SYNC0_PAD_IN_IDX                    98
-#define PWM1_CH1_B_PAD_OUT_IDX                   98
-#define PWM1_SYNC1_PAD_IN_IDX                    99
-#define PWM1_CH2_A_PAD_OUT_IDX                   99
-#define PWM1_SYNC2_PAD_IN_IDX                    100
-#define PWM1_CH2_B_PAD_OUT_IDX                   100
-#define PWM1_F0_PAD_IN_IDX                       101
-#define PWM1_F1_PAD_IN_IDX                       102
-#define PWM1_F2_PAD_IN_IDX                       103
-#define PWM1_CAP0_PAD_IN_IDX                     104
-#define PWM1_CAP1_PAD_IN_IDX                     105
-#define TWAI0_STANDBY_PAD_OUT_IDX                105
-#define PWM1_CAP2_PAD_IN_IDX                     106
-#define TWAI1_STANDBY_PAD_OUT_IDX                106
-#define GMII_MDI_PAD_IN_IDX                      107
-#define TWAI2_STANDBY_PAD_OUT_IDX                107
-#define GMAC_PHY_COL_PAD_IN_IDX                  108
-#define GMII_MDC_PAD_OUT_IDX                     108
-#define GMAC_PHY_CRS_PAD_IN_IDX                  109
-#define GMII_MDO_PAD_OUT_IDX                     109
-#define USB_OTG11_IDDIG_PAD_IN_IDX               110
-#define USB_SRP_DISCHRGVBUS_PAD_OUT_IDX          110
-#define USB_OTG11_AVALID_PAD_IN_IDX              111
-#define USB_OTG11_IDPULLUP_PAD_OUT_IDX           111
-#define USB_SRP_BVALID_PAD_IN_IDX                112
-#define USB_OTG11_DPPULLDOWN_PAD_OUT_IDX         112
-#define USB_OTG11_VBUSVALID_PAD_IN_IDX           113
-#define USB_OTG11_DMPULLDOWN_PAD_OUT_IDX         113
-#define USB_SRP_SESSEND_PAD_IN_IDX               114
-#define USB_OTG11_DRVVBUS_PAD_OUT_IDX            114
-#define USB_SRP_CHRGVBUS_PAD_OUT_IDX             115
-#define ULPI_CLK_PAD_IN_IDX                      117
-#define RNG_CHAIN_CLK_PAD_OUT_IDX                117
-#define USB_HSPHY_REFCLK_IN_IDX                  118
-#define HP_PROBE_TOP_OUT0_IDX                    118
-#define HP_PROBE_TOP_OUT1_IDX                    119
-#define HP_PROBE_TOP_OUT2_IDX                    120
-#define HP_PROBE_TOP_OUT3_IDX                    121
-#define HP_PROBE_TOP_OUT4_IDX                    122
-#define HP_PROBE_TOP_OUT5_IDX                    123
-#define HP_PROBE_TOP_OUT6_IDX                    124
-#define HP_PROBE_TOP_OUT7_IDX                    125
-#define SD_CARD_DETECT_N_1_PAD_IN_IDX            126
-#define LEDC_LS_SIG_OUT_PAD_OUT0_IDX             126
-#define SD_CARD_DETECT_N_2_PAD_IN_IDX            127
-#define LEDC_LS_SIG_OUT_PAD_OUT1_IDX             127
-#define SD_CARD_INT_N_1_PAD_IN_IDX               128
-#define LEDC_LS_SIG_OUT_PAD_OUT2_IDX             128
-#define SD_CARD_INT_N_2_PAD_IN_IDX               129
-#define LEDC_LS_SIG_OUT_PAD_OUT3_IDX             129
-#define SD_CARD_WRITE_PRT_1_PAD_IN_IDX           130
-#define LEDC_LS_SIG_OUT_PAD_OUT4_IDX             130
-#define SD_CARD_WRITE_PRT_2_PAD_IN_IDX           131
-#define LEDC_LS_SIG_OUT_PAD_OUT5_IDX             131
-#define SD_DATA_STROBE_1_PAD_IN_IDX              132
-#define LEDC_LS_SIG_OUT_PAD_OUT6_IDX             132
-#define SD_DATA_STROBE_2_PAD_IN_IDX              133
-#define LEDC_LS_SIG_OUT_PAD_OUT7_IDX             133
-#define I3C_MST_SCL_PAD_IN_IDX                   134
-#define I3C_MST_SCL_PAD_OUT_IDX                  134
-#define I3C_MST_SDA_PAD_IN_IDX                   135
-#define I3C_MST_SDA_PAD_OUT_IDX                  135
-#define I3C_SLV_SCL_PAD_IN_IDX                   136
-#define I3C_SLV_SCL_PAD_OUT_IDX                  136
-#define I3C_SLV_SDA_PAD_IN_IDX                   137
-#define I3C_SLV_SDA_PAD_OUT_IDX                  137
-#define I3C_MST_SCL_PULLUP_EN_PAD_OUT_IDX        138
-#define I3C_MST_SDA_PULLUP_EN_PAD_OUT_IDX        139
-#define USB_JTAG_TDO_BRIDGE_PAD_IN_IDX           140
-#define USB_JTAG_TDI_BRIDGE_PAD_OUT_IDX          140
-#define PCNT_SIG_CH0_PAD_IN0_IDX                 141
-#define USB_JTAG_TMS_BRIDGE_PAD_OUT_IDX          141
-#define PCNT_SIG_CH0_PAD_IN1_IDX                 142
-#define USB_JTAG_TCK_BRIDGE_PAD_OUT_IDX          142
-#define PCNT_SIG_CH0_PAD_IN2_IDX                 143
-#define USB_JTAG_TRST_BRIDGE_PAD_OUT_IDX         143
-#define PCNT_SIG_CH0_PAD_IN3_IDX                 144
-#define LCD_CS_PAD_OUT_IDX                       144
-#define PCNT_SIG_CH1_PAD_IN0_IDX                 145
-#define LCD_DC_PAD_OUT_IDX                       145
-#define PCNT_SIG_CH1_PAD_IN1_IDX                 146
-#define SD_RST_N_1_PAD_OUT_IDX                   146
-#define PCNT_SIG_CH1_PAD_IN2_IDX                 147
-#define SD_RST_N_2_PAD_OUT_IDX                   147
-#define PCNT_SIG_CH1_PAD_IN3_IDX                 148
-#define SD_CCMD_OD_PULLUP_EN_N_PAD_OUT_IDX       148
-#define PCNT_CTRL_CH0_PAD_IN0_IDX                149
-#define LCD_PCLK_PAD_OUT_IDX                     149
-#define PCNT_CTRL_CH0_PAD_IN1_IDX                150
-#define CAM_CLK_PAD_OUT_IDX                      150
-#define PCNT_CTRL_CH0_PAD_IN2_IDX                151
-#define LCD_H_ENABLE_PAD_OUT_IDX                 151
-#define PCNT_CTRL_CH0_PAD_IN3_IDX                152
-#define LCD_H_SYNC_PAD_OUT_IDX                   152
-#define PCNT_CTRL_CH1_PAD_IN0_IDX                153
-#define LCD_V_SYNC_PAD_OUT_IDX                   153
-#define PCNT_CTRL_CH1_PAD_IN1_IDX                154
-#define LCD_DATA_OUT_PAD_OUT0_IDX                154
-#define PCNT_CTRL_CH1_PAD_IN2_IDX                155
-#define LCD_DATA_OUT_PAD_OUT1_IDX                155
-#define PCNT_CTRL_CH1_PAD_IN3_IDX                156
-#define LCD_DATA_OUT_PAD_OUT2_IDX                156
-#define LCD_DATA_OUT_PAD_OUT3_IDX                157
-#define CAM_PCLK_PAD_IN_IDX                      158
-#define LCD_DATA_OUT_PAD_OUT4_IDX                158
-#define CAM_H_ENABLE_PAD_IN_IDX                  159
-#define LCD_DATA_OUT_PAD_OUT5_IDX                159
-#define CAM_H_SYNC_PAD_IN_IDX                    160
-#define LCD_DATA_OUT_PAD_OUT6_IDX                160
-#define CAM_V_SYNC_PAD_IN_IDX                    161
-#define LCD_DATA_OUT_PAD_OUT7_IDX                161
-#define CAM_DATA_IN_PAD_IN0_IDX                  162
-#define LCD_DATA_OUT_PAD_OUT8_IDX                162
-#define CAM_DATA_IN_PAD_IN1_IDX                  163
-#define LCD_DATA_OUT_PAD_OUT9_IDX                163
-#define CAM_DATA_IN_PAD_IN2_IDX                  164
-#define LCD_DATA_OUT_PAD_OUT10_IDX               164
-#define CAM_DATA_IN_PAD_IN3_IDX                  165
-#define LCD_DATA_OUT_PAD_OUT11_IDX               165
-#define CAM_DATA_IN_PAD_IN4_IDX                  166
-#define LCD_DATA_OUT_PAD_OUT12_IDX               166
-#define CAM_DATA_IN_PAD_IN5_IDX                  167
-#define LCD_DATA_OUT_PAD_OUT13_IDX               167
-#define CAM_DATA_IN_PAD_IN6_IDX                  168
-#define LCD_DATA_OUT_PAD_OUT14_IDX               168
-#define CAM_DATA_IN_PAD_IN7_IDX                  169
-#define LCD_DATA_OUT_PAD_OUT15_IDX               169
-#define CAM_DATA_IN_PAD_IN8_IDX                  170
-#define LCD_DATA_OUT_PAD_OUT16_IDX               170
-#define CAM_DATA_IN_PAD_IN9_IDX                  171
-#define LCD_DATA_OUT_PAD_OUT17_IDX               171
-#define CAM_DATA_IN_PAD_IN10_IDX                 172
-#define LCD_DATA_OUT_PAD_OUT18_IDX               172
-#define CAM_DATA_IN_PAD_IN11_IDX                 173
-#define LCD_DATA_OUT_PAD_OUT19_IDX               173
-#define CAM_DATA_IN_PAD_IN12_IDX                 174
-#define LCD_DATA_OUT_PAD_OUT20_IDX               174
-#define CAM_DATA_IN_PAD_IN13_IDX                 175
-#define LCD_DATA_OUT_PAD_OUT21_IDX               175
-#define CAM_DATA_IN_PAD_IN14_IDX                 176
-#define LCD_DATA_OUT_PAD_OUT22_IDX               176
-#define CAM_DATA_IN_PAD_IN15_IDX                 177
-#define LCD_DATA_OUT_PAD_OUT23_IDX               177
-#define GMAC_PHY_RXDV_PAD_IN_IDX                 178
-#define GMAC_PHY_TXEN_PAD_OUT_IDX                178
-#define GMAC_PHY_RXD0_PAD_IN_IDX                 179
-#define GMAC_PHY_TXD0_PAD_OUT_IDX                179
-#define GMAC_PHY_RXD1_PAD_IN_IDX                 180
-#define GMAC_PHY_TXD1_PAD_OUT_IDX                180
-#define GMAC_PHY_RXD2_PAD_IN_IDX                 181
-#define GMAC_PHY_TXD2_PAD_OUT_IDX                181
-#define GMAC_PHY_RXD3_PAD_IN_IDX                 182
-#define GMAC_PHY_TXD3_PAD_OUT_IDX                182
-#define GMAC_PHY_RXER_PAD_IN_IDX                 183
-#define GMAC_PHY_TXER_PAD_OUT_IDX                183
-#define GMAC_RX_CLK_PAD_IN_IDX                   184
-#define DBG_CH0_CLK_IDX                          184
-#define GMAC_TX_CLK_PAD_IN_IDX                   185
-#define DBG_CH1_CLK_IDX                          185
-#define PARLIO_RX_CLK_PAD_IN_IDX                 186
-#define PARLIO_RX_CLK_PAD_OUT_IDX                186
-#define PARLIO_TX_CLK_PAD_IN_IDX                 187
-#define PARLIO_TX_CLK_PAD_OUT_IDX                187
-#define PARLIO_RX_DATA0_PAD_IN_IDX               188
-#define PARLIO_TX_DATA0_PAD_OUT_IDX              188
-#define PARLIO_RX_DATA1_PAD_IN_IDX               189
-#define PARLIO_TX_DATA1_PAD_OUT_IDX              189
-#define PARLIO_RX_DATA2_PAD_IN_IDX               190
-#define PARLIO_TX_DATA2_PAD_OUT_IDX              190
-#define PARLIO_RX_DATA3_PAD_IN_IDX               191
-#define PARLIO_TX_DATA3_PAD_OUT_IDX              191
-#define PARLIO_RX_DATA4_PAD_IN_IDX               192
-#define PARLIO_TX_DATA4_PAD_OUT_IDX              192
-#define PARLIO_RX_DATA5_PAD_IN_IDX               193
-#define PARLIO_TX_DATA5_PAD_OUT_IDX              193
-#define PARLIO_RX_DATA6_PAD_IN_IDX               194
-#define PARLIO_TX_DATA6_PAD_OUT_IDX              194
-#define PARLIO_RX_DATA7_PAD_IN_IDX               195
-#define PARLIO_TX_DATA7_PAD_OUT_IDX              195
-#define PARLIO_RX_DATA8_PAD_IN_IDX               196
-#define PARLIO_TX_DATA8_PAD_OUT_IDX              196
-#define PARLIO_RX_DATA9_PAD_IN_IDX               197
-#define PARLIO_TX_DATA9_PAD_OUT_IDX              197
-#define PARLIO_RX_DATA10_PAD_IN_IDX              198
-#define PARLIO_TX_DATA10_PAD_OUT_IDX             198
-#define PARLIO_RX_DATA11_PAD_IN_IDX              199
-#define PARLIO_TX_DATA11_PAD_OUT_IDX             199
-#define PARLIO_RX_DATA12_PAD_IN_IDX              200
-#define PARLIO_TX_DATA12_PAD_OUT_IDX             200
-#define PARLIO_RX_DATA13_PAD_IN_IDX              201
-#define PARLIO_TX_DATA13_PAD_OUT_IDX             201
-#define PARLIO_RX_DATA14_PAD_IN_IDX              202
-#define PARLIO_TX_DATA14_PAD_OUT_IDX             202
-#define PARLIO_RX_DATA15_PAD_IN_IDX              203
-#define PARLIO_TX_DATA15_PAD_OUT_IDX             203
-#define HP_PROBE_TOP_OUT8_IDX                    204
-#define HP_PROBE_TOP_OUT9_IDX                    205
-#define HP_PROBE_TOP_OUT10_IDX                   206
-#define HP_PROBE_TOP_OUT11_IDX                   207
-#define HP_PROBE_TOP_OUT12_IDX                   208
-#define HP_PROBE_TOP_OUT13_IDX                   209
-#define HP_PROBE_TOP_OUT14_IDX                   210
-#define HP_PROBE_TOP_OUT15_IDX                   211
-#define CONSTANT0_PAD_OUT_IDX                    212
-#define CONSTANT1_PAD_OUT_IDX                    213
-#define CORE_GPIO_IN_PAD_IN0_IDX                 214
-#define CORE_GPIO_OUT_PAD_OUT0_IDX               214
-#define CORE_GPIO_IN_PAD_IN1_IDX                 215
-#define CORE_GPIO_OUT_PAD_OUT1_IDX               215
-#define CORE_GPIO_IN_PAD_IN2_IDX                 216
-#define CORE_GPIO_OUT_PAD_OUT2_IDX               216
-#define CORE_GPIO_IN_PAD_IN3_IDX                 217
-#define CORE_GPIO_OUT_PAD_OUT3_IDX               217
-#define CORE_GPIO_IN_PAD_IN4_IDX                 218
-#define CORE_GPIO_OUT_PAD_OUT4_IDX               218
-#define CORE_GPIO_IN_PAD_IN5_IDX                 219
-#define CORE_GPIO_OUT_PAD_OUT5_IDX               219
-#define CORE_GPIO_IN_PAD_IN6_IDX                 220
-#define CORE_GPIO_OUT_PAD_OUT6_IDX               220
-#define CORE_GPIO_IN_PAD_IN7_IDX                 221
-#define CORE_GPIO_OUT_PAD_OUT7_IDX               221
-#define CORE_GPIO_IN_PAD_IN8_IDX                 222
-#define CORE_GPIO_OUT_PAD_OUT8_IDX               222
-#define CORE_GPIO_IN_PAD_IN9_IDX                 223
-#define CORE_GPIO_OUT_PAD_OUT9_IDX               223
-#define CORE_GPIO_IN_PAD_IN10_IDX                224
-#define CORE_GPIO_OUT_PAD_OUT10_IDX              224
-#define CORE_GPIO_IN_PAD_IN11_IDX                225
-#define CORE_GPIO_OUT_PAD_OUT11_IDX              225
-#define CORE_GPIO_IN_PAD_IN12_IDX                226
-#define CORE_GPIO_OUT_PAD_OUT12_IDX              226
-#define CORE_GPIO_IN_PAD_IN13_IDX                227
-#define CORE_GPIO_OUT_PAD_OUT13_IDX              227
-#define CORE_GPIO_IN_PAD_IN14_IDX                228
-#define CORE_GPIO_OUT_PAD_OUT14_IDX              228
-#define CORE_GPIO_IN_PAD_IN15_IDX                229
-#define CORE_GPIO_OUT_PAD_OUT15_IDX              229
-#define CORE_GPIO_IN_PAD_IN16_IDX                230
-#define CORE_GPIO_OUT_PAD_OUT16_IDX              230
-#define CORE_GPIO_IN_PAD_IN17_IDX                231
-#define CORE_GPIO_OUT_PAD_OUT17_IDX              231
-#define CORE_GPIO_IN_PAD_IN18_IDX                232
-#define CORE_GPIO_OUT_PAD_OUT18_IDX              232
-#define CORE_GPIO_IN_PAD_IN19_IDX                233
-#define CORE_GPIO_OUT_PAD_OUT19_IDX              233
-#define CORE_GPIO_IN_PAD_IN20_IDX                234
-#define CORE_GPIO_OUT_PAD_OUT20_IDX              234
-#define CORE_GPIO_IN_PAD_IN21_IDX                235
-#define CORE_GPIO_OUT_PAD_OUT21_IDX              235
-#define CORE_GPIO_IN_PAD_IN22_IDX                236
-#define CORE_GPIO_OUT_PAD_OUT22_IDX              236
-#define CORE_GPIO_IN_PAD_IN23_IDX                237
-#define CORE_GPIO_OUT_PAD_OUT23_IDX              237
-#define CORE_GPIO_IN_PAD_IN24_IDX                238
-#define CORE_GPIO_OUT_PAD_OUT24_IDX              238
-#define CORE_GPIO_IN_PAD_IN25_IDX                239
-#define CORE_GPIO_OUT_PAD_OUT25_IDX              239
-#define CORE_GPIO_IN_PAD_IN26_IDX                240
-#define CORE_GPIO_OUT_PAD_OUT26_IDX              240
-#define CORE_GPIO_IN_PAD_IN27_IDX                241
-#define CORE_GPIO_OUT_PAD_OUT27_IDX              241
-#define CORE_GPIO_IN_PAD_IN28_IDX                242
-#define PARLIO_TX_CS_PAD_OUT_IDX                 242
-#define CORE_GPIO_IN_PAD_IN29_IDX                243
-#define EMAC_PTP_PPS_PAD_OUT_IDX                 243
-#define CORE_GPIO_IN_PAD_IN30_IDX                244
-#define ANA_COMP0_OUT_IDX                        244
-#define CORE_GPIO_IN_PAD_IN31_IDX                245
-#define ANA_COMP1_OUT_IDX                        245
-#define RMT_SIG_PAD_IN0_IDX                      246
-#define RMT_SIG_PAD_OUT0_IDX                     246
-#define RMT_SIG_PAD_IN1_IDX                      247
-#define RMT_SIG_PAD_OUT1_IDX                     247
-#define RMT_SIG_PAD_IN2_IDX                      248
-#define RMT_SIG_PAD_OUT2_IDX                     248
-#define RMT_SIG_PAD_IN3_IDX                      249
-#define RMT_SIG_PAD_OUT3_IDX                     249
-#define SIG_IN_FUNC250_IDX                       250
-#define SIG_IN_FUNC250_IDX                       250
-#define SIG_IN_FUNC251_IDX                       251
-#define SIG_IN_FUNC251_IDX                       251
-#define SIG_IN_FUNC252_IDX                       252
-#define SIG_IN_FUNC252_IDX                       252
-#define SIG_IN_FUNC253_IDX                       253
-#define SIG_IN_FUNC253_IDX                       253
-#define SIG_IN_FUNC254_IDX                       254
-#define SIG_IN_FUNC254_IDX                       254
-#define SIG_IN_FUNC255_IDX                       255
-#define SIG_IN_FUNC255_IDX                       255
-// version date 230403
-#define SIG_GPIO_OUT_IDX                        256
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h
index 86a980f8e0e6..8e62f2bec847 100644
--- a/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h
+++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h
@@ -413,37 +413,6 @@ typedef union {
 } hp_crypto_ctrl_reg_t;
 
 
-/** Group: HP GPIO O HOLD CTRL0 REG */
-/** Type of gpio_o_hold_ctrl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_gpio_0_hold_low : R/W; bitpos: [31:0]; default: 0;
-         *  hold control for gpio47~16
-         */
-        uint32_t reg_gpio_0_hold_low:32;
-    };
-    uint32_t val;
-} hp_gpio_o_hold_ctrl0_reg_t;
-
-
-/** Group: HP GPIO O HOLD CTRL1 REG */
-/** Type of gpio_o_hold_ctrl1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_gpio_0_hold_high : R/W; bitpos: [8:0]; default: 0;
-         *  hold control for gpio56~48
-         */
-        uint32_t reg_gpio_0_hold_high:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} hp_gpio_o_hold_ctrl1_reg_t;
-
-
 /** Group: HP SYS RDN ECO CS REG */
 /** Type of sys_rdn_eco_cs register
  *  NA
@@ -2149,8 +2118,7 @@ typedef struct hp_system_dev_t {
     volatile hp_cpu_corestalled_st_reg_t cpu_corestalled_st;
     uint32_t reserved_068[2];
     volatile hp_crypto_ctrl_reg_t crypto_ctrl;
-    volatile hp_gpio_o_hold_ctrl0_reg_t gpio_o_hold_ctrl0;
-    volatile hp_gpio_o_hold_ctrl1_reg_t gpio_o_hold_ctrl1;
+    uint32_t reserved_074[2];
     volatile hp_sys_rdn_eco_cs_reg_t sys_rdn_eco_cs;
     volatile hp_cache_apb_postw_en_reg_t cache_apb_postw_en;
     volatile hp_l2_mem_subsize_reg_t l2_mem_subsize;
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_reg.h
deleted file mode 100644
index c651fb6e5613..000000000000
--- a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_reg.h
+++ /dev/null
@@ -1,5466 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// definitions below are generated from pin_txt.csv
-#define PERIPHS_IO_MUX_U_PAD_GPIO0                   (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO0_GPIO0_0                                                 0
-#define FUNC_GPIO0_GPIO0                                                   1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO1                   (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO1_GPIO1_0                                                 0
-#define FUNC_GPIO1_GPIO1                                                   1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO2                   (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO2_MTCK                                                    0
-#define FUNC_GPIO2_GPIO2                                                   1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO3                   (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO3_MTDI                                                    0
-#define FUNC_GPIO3_GPIO3                                                   1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO4                   (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO4_MTMS                                                    0
-#define FUNC_GPIO4_GPIO4                                                   1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO5                   (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO5_MTDO                                                    0
-#define FUNC_GPIO5_GPIO5                                                   1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO6                   (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO6_GPIO6_0                                                 0
-#define FUNC_GPIO6_GPIO6                                                   1
-#define FUNC_GPIO6_SPI2_HOLD_PAD                                           3
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO7                   (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO7_GPIO7_0                                                 0
-#define FUNC_GPIO7_GPIO7                                                   1
-#define FUNC_GPIO7_SPI2_CS_PAD                                             3
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO8                   (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO8_GPIO8_0                                                 0
-#define FUNC_GPIO8_GPIO8                                                   1
-#define FUNC_GPIO8_UART0_RTS_PAD                                           2
-#define FUNC_GPIO8_SPI2_D_PAD                                              3
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO9                   (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO9_GPIO9_0                                                 0
-#define FUNC_GPIO9_GPIO9                                                   1
-#define FUNC_GPIO9_UART0_CTS_PAD                                           2
-#define FUNC_GPIO9_SPI2_CK_PAD                                             3
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO10                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO10_GPIO10_0                                               0
-#define FUNC_GPIO10_GPIO10                                                 1
-#define FUNC_GPIO10_UART1_TXD_PAD                                          2
-#define FUNC_GPIO10_SPI2_Q_PAD                                             3
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO11                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO11_GPIO11_0                                               0
-#define FUNC_GPIO11_GPIO11                                                 1
-#define FUNC_GPIO11_UART1_RXD_PAD                                          2
-#define FUNC_GPIO11_SPI2_WP_PAD                                            3
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO12                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO12_GPIO12_0                                               0
-#define FUNC_GPIO12_GPIO12                                                 1
-#define FUNC_GPIO12_UART1_RTS_PAD                                          2
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO13                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO13_GPIO13_0                                               0
-#define FUNC_GPIO13_GPIO13                                                 1
-#define FUNC_GPIO13_UART1_CTS_PAD                                          2
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO14                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO14_GPIO14_0                                               0
-#define FUNC_GPIO14_GPIO14                                                 1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO15                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO15_GPIO15_0                                               0
-#define FUNC_GPIO15_GPIO15                                                 1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO16                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO16_GPIO16_0                                               0
-#define FUNC_GPIO16_GPIO16                                                 1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO17                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO17_GPIO17_0                                               0
-#define FUNC_GPIO17_GPIO17                                                 1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO18                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO18_GPIO18_0                                               0
-#define FUNC_GPIO18_GPIO18                                                 1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO19                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO19_GPIO19_0                                               0
-#define FUNC_GPIO19_GPIO19                                                 1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO20                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO20_GPIO20_0                                               0
-#define FUNC_GPIO20_GPIO20                                                 1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO21                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO21_GPIO21_0                                               0
-#define FUNC_GPIO21_GPIO21                                                 1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO22                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO22_GPIO22_0                                               0
-#define FUNC_GPIO22_GPIO22                                                 1
-#define FUNC_GPIO22_DBG_PSRAM_CK_PAD                                       4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO23                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO23_GPIO23_0                                               0
-#define FUNC_GPIO23_GPIO23                                                 1
-#define FUNC_GPIO23_REF_50M_CLK_PAD                                        3
-#define FUNC_GPIO23_DBG_PSRAM_CS_PAD                                       4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO24                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO24_GPIO24_0                                               0
-#define FUNC_GPIO24_GPIO24                                                 1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO25                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO25_GPIO25_0                                               0
-#define FUNC_GPIO25_GPIO25                                                 1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO26                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO26_GPIO26_0                                               0
-#define FUNC_GPIO26_GPIO26                                                 1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO27                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO27_GPIO27_0                                               0
-#define FUNC_GPIO27_GPIO27                                                 1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO28                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO28_GPIO28_0                                               0
-#define FUNC_GPIO28_GPIO28                                                 1
-#define FUNC_GPIO28_SPI2_CS_PAD                                            2
-#define FUNC_GPIO28_GMAC_PHY_RXDV_PAD                                      3
-#define FUNC_GPIO28_DBG_PSRAM_D_PAD                                        4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO29                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO29_GPIO29_0                                               0
-#define FUNC_GPIO29_GPIO29                                                 1
-#define FUNC_GPIO29_SPI2_D_PAD                                             2
-#define FUNC_GPIO29_GMAC_PHY_RXD0_PAD                                      3
-#define FUNC_GPIO29_DBG_PSRAM_Q_PAD                                        4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO30                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO30_GPIO30_0                                               0
-#define FUNC_GPIO30_GPIO30                                                 1
-#define FUNC_GPIO30_SPI2_CK_PAD                                            2
-#define FUNC_GPIO30_GMAC_PHY_RXD1_PAD                                      3
-#define FUNC_GPIO30_DBG_PSRAM_WP_PAD                                       4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO31                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO31_GPIO31_0                                               0
-#define FUNC_GPIO31_GPIO31                                                 1
-#define FUNC_GPIO31_SPI2_Q_PAD                                             2
-#define FUNC_GPIO31_GMAC_PHY_RXER_PAD                                      3
-#define FUNC_GPIO31_DBG_PSRAM_HOLD_PAD                                     4
-
-// Strapping: Diag Group Sel1
-#define PERIPHS_IO_MUX_U_PAD_GPIO32                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO32_GPIO32_0                                               0
-#define FUNC_GPIO32_GPIO32                                                 1
-#define FUNC_GPIO32_SPI2_HOLD_PAD                                          2
-#define FUNC_GPIO32_GMAC_RMII_CLK_PAD                                      3
-#define FUNC_GPIO32_DBG_PSRAM_DQ4_PAD                                      4
-
-// Strapping: Diag Group Sel0
-#define PERIPHS_IO_MUX_U_PAD_GPIO33                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO33_GPIO33_0                                               0
-#define FUNC_GPIO33_GPIO33                                                 1
-#define FUNC_GPIO33_SPI2_WP_PAD                                            2
-#define FUNC_GPIO33_GMAC_PHY_TXEN_PAD                                      3
-#define FUNC_GPIO33_DBG_PSRAM_DQ5_PAD                                      4
-
-// Strapping: USB2JTAG select: 1->usb2jtag 0-> pad_jtag
-#define PERIPHS_IO_MUX_U_PAD_GPIO34                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO34_GPIO34_0                                               0
-#define FUNC_GPIO34_GPIO34                                                 1
-#define FUNC_GPIO34_SPI2_IO4_PAD                                           2
-#define FUNC_GPIO34_GMAC_PHY_TXD0_PAD                                      3
-#define FUNC_GPIO34_DBG_PSRAM_DQ6_PAD                                      4
-
-// Strapping: Boot Mode select 3
-#define PERIPHS_IO_MUX_U_PAD_GPIO35                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO35_GPIO35_0                                               0
-#define FUNC_GPIO35_GPIO35                                                 1
-#define FUNC_GPIO35_SPI2_IO5_PAD                                           2
-#define FUNC_GPIO35_GMAC_PHY_TXD1_PAD                                      3
-#define FUNC_GPIO35_DBG_PSRAM_DQ7_PAD                                      4
-
-// Strapping: Boot Mode select 2
-#define PERIPHS_IO_MUX_U_PAD_GPIO36                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO36_GPIO36_0                                               0
-#define FUNC_GPIO36_GPIO36                                                 1
-#define FUNC_GPIO36_SPI2_IO6_PAD                                           2
-#define FUNC_GPIO36_GMAC_PHY_TXER_PAD                                      3
-#define FUNC_GPIO36_DBG_PSRAM_DQS_0_PAD                                    4
-
-// Strapping: Boot Mode select 1
-#define PERIPHS_IO_MUX_U_PAD_GPIO37                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO37_UART0_TXD_PAD                                          0
-#define FUNC_GPIO37_GPIO37                                                 1
-#define FUNC_GPIO37_SPI2_IO7_PAD                                           2
-
-// Strapping: Boot Mode select 0
-#define PERIPHS_IO_MUX_U_PAD_GPIO38                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO38_UART0_RXD_PAD                                          0
-#define FUNC_GPIO38_GPIO38                                                 1
-#define FUNC_GPIO38_SPI2_DQS_PAD                                           2
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO39                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO39_SD1_CDATA0_PAD                                         0
-#define FUNC_GPIO39_GPIO39                                                 1
-#define FUNC_GPIO39_BIST_PAD                                               2
-#define FUNC_GPIO39_REF_50M_CLK_PAD                                        3
-#define FUNC_GPIO39_DBG_PSRAM_DQ8_PAD                                      4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO40                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO40_SD1_CDATA1_PAD                                         0
-#define FUNC_GPIO40_GPIO40                                                 1
-#define FUNC_GPIO40_BIST_PAD                                               2
-#define FUNC_GPIO40_GMAC_PHY_TXEN_PAD                                      3
-#define FUNC_GPIO40_DBG_PSRAM_DQ9_PAD                                      4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO41                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO41_SD1_CDATA2_PAD                                         0
-#define FUNC_GPIO41_GPIO41                                                 1
-#define FUNC_GPIO41_BIST_PAD                                               2
-#define FUNC_GPIO41_GMAC_PHY_TXD0_PAD                                      3
-#define FUNC_GPIO41_DBG_PSRAM_DQ10_PAD                                     4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO42                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO42_SD1_CDATA3_PAD                                         0
-#define FUNC_GPIO42_GPIO42                                                 1
-#define FUNC_GPIO42_BIST_PAD                                               2
-#define FUNC_GPIO42_GMAC_PHY_TXD1_PAD                                      3
-#define FUNC_GPIO42_DBG_PSRAM_DQ11_PAD                                     4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO43                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO43_SD1_CCLK_PAD                                           0
-#define FUNC_GPIO43_GPIO43                                                 1
-#define FUNC_GPIO43_BIST_PAD                                               2
-#define FUNC_GPIO43_GMAC_PHY_TXER_PAD                                      3
-#define FUNC_GPIO43_DBG_PSRAM_DQ12_PAD                                     4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO44                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO44_SD1_CCMD_PAD                                           0
-#define FUNC_GPIO44_GPIO44                                                 1
-#define FUNC_GPIO44_BIST_PAD                                               2
-#define FUNC_GPIO44_GMAC_RMII_CLK_PAD                                      3
-#define FUNC_GPIO44_DBG_PSRAM_DQ13_PAD                                     4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO45                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO45_SD1_CDATA4_PAD                                         0
-#define FUNC_GPIO45_GPIO45                                                 1
-#define FUNC_GPIO45_BIST_PAD                                               2
-#define FUNC_GPIO45_GMAC_PHY_RXDV_PAD                                      3
-#define FUNC_GPIO45_DBG_PSRAM_DQ14_PAD                                     4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO46                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO46_SD1_CDATA5_PAD                                         0
-#define FUNC_GPIO46_GPIO46                                                 1
-#define FUNC_GPIO46_BIST_PAD                                               2
-#define FUNC_GPIO46_GMAC_PHY_RXD0_PAD                                      3
-#define FUNC_GPIO46_DBG_PSRAM_DQ15_PAD                                     4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO47                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO47_SD1_CDATA6_PAD                                         0
-#define FUNC_GPIO47_GPIO47                                                 1
-#define FUNC_GPIO47_BIST_PAD                                               2
-#define FUNC_GPIO47_GMAC_PHY_RXD1_PAD                                      3
-#define FUNC_GPIO47_DBG_PSRAM_DQS_1_PAD                                    4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO48                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO48_SD1_CDATA7_PAD                                         0
-#define FUNC_GPIO48_GPIO48                                                 1
-#define FUNC_GPIO48_BIST_PAD                                               2
-#define FUNC_GPIO48_GMAC_PHY_RXER_PAD                                      3
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO49                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO49_GPIO49_0                                               0
-#define FUNC_GPIO49_GPIO49                                                 1
-#define FUNC_GPIO49_GMAC_PHY_TXEN_PAD                                      3
-#define FUNC_GPIO49_DBG_FLASH_CS_PAD                                       4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO50                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO50_GPIO50_0                                               0
-#define FUNC_GPIO50_GPIO50                                                 1
-#define FUNC_GPIO50_GMAC_RMII_CLK_PAD                                      3
-#define FUNC_GPIO50_DBG_FLASH_Q_PAD                                        4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO51                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO51_GPIO51_0                                               0
-#define FUNC_GPIO51_GPIO51                                                 1
-#define FUNC_GPIO51_GMAC_PHY_RXDV_PAD                                      3
-#define FUNC_GPIO51_DBG_FLASH_WP_PAD                                       4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO52                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO52_GPIO52_0                                               0
-#define FUNC_GPIO52_GPIO52                                                 1
-#define FUNC_GPIO52_GMAC_PHY_RXD0_PAD                                      3
-#define FUNC_GPIO52_DBG_FLASH_HOLD_PAD                                     4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO53                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO53_GPIO53_0                                               0
-#define FUNC_GPIO53_GPIO53                                                 1
-#define FUNC_GPIO53_GMAC_PHY_RXD1_PAD                                      3
-#define FUNC_GPIO53_DBG_FLASH_CK_PAD                                       4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO54                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO54_GPIO54_0                                               0
-#define FUNC_GPIO54_GPIO54                                                 1
-#define FUNC_GPIO54_GMAC_PHY_RXER_PAD                                      3
-#define FUNC_GPIO54_DBG_FLASH_D_PAD                                        4
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO55                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO55_GPIO55_0                                               0
-#define FUNC_GPIO55_GPIO55                                                 1
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO56                  (REG_IO_MUX_BASE + 0x0)
-#define FUNC_GPIO56_GPIO56_0                                               0
-#define FUNC_GPIO56_GPIO56                                                 1
-
-
-/** IO_MUX_gpio0_REG register
- *  iomux control register for gpio0
- */
-#define IO_MUX_GPIO0_REG (DR_REG_IO_MUX_BASE + 0x4)
-/** IO_MUX_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO0_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO0_MCU_OE_M  (IO_MUX_GPIO0_MCU_OE_V << IO_MUX_GPIO0_MCU_OE_S)
-#define IO_MUX_GPIO0_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO0_MCU_OE_S  0
-/** IO_MUX_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO0_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO0_SLP_SEL_M  (IO_MUX_GPIO0_SLP_SEL_V << IO_MUX_GPIO0_SLP_SEL_S)
-#define IO_MUX_GPIO0_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO0_SLP_SEL_S  1
-/** IO_MUX_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO0_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO0_MCU_WPD_M  (IO_MUX_GPIO0_MCU_WPD_V << IO_MUX_GPIO0_MCU_WPD_S)
-#define IO_MUX_GPIO0_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO0_MCU_WPD_S  2
-/** IO_MUX_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO0_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO0_MCU_WPU_M  (IO_MUX_GPIO0_MCU_WPU_V << IO_MUX_GPIO0_MCU_WPU_S)
-#define IO_MUX_GPIO0_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO0_MCU_WPU_S  3
-/** IO_MUX_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO0_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO0_MCU_IE_M  (IO_MUX_GPIO0_MCU_IE_V << IO_MUX_GPIO0_MCU_IE_S)
-#define IO_MUX_GPIO0_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO0_MCU_IE_S  4
-/** IO_MUX_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO0_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO0_MCU_DRV_M  (IO_MUX_GPIO0_MCU_DRV_V << IO_MUX_GPIO0_MCU_DRV_S)
-#define IO_MUX_GPIO0_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO0_MCU_DRV_S  5
-/** IO_MUX_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO0_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO0_FUN_WPD_M  (IO_MUX_GPIO0_FUN_WPD_V << IO_MUX_GPIO0_FUN_WPD_S)
-#define IO_MUX_GPIO0_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO0_FUN_WPD_S  7
-/** IO_MUX_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO0_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO0_FUN_WPU_M  (IO_MUX_GPIO0_FUN_WPU_V << IO_MUX_GPIO0_FUN_WPU_S)
-#define IO_MUX_GPIO0_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO0_FUN_WPU_S  8
-/** IO_MUX_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO0_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO0_FUN_IE_M  (IO_MUX_GPIO0_FUN_IE_V << IO_MUX_GPIO0_FUN_IE_S)
-#define IO_MUX_GPIO0_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO0_FUN_IE_S  9
-/** IO_MUX_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO0_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO0_FUN_DRV_M  (IO_MUX_GPIO0_FUN_DRV_V << IO_MUX_GPIO0_FUN_DRV_S)
-#define IO_MUX_GPIO0_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO0_FUN_DRV_S  10
-/** IO_MUX_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO0_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO0_MCU_SEL_M  (IO_MUX_GPIO0_MCU_SEL_V << IO_MUX_GPIO0_MCU_SEL_S)
-#define IO_MUX_GPIO0_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO0_MCU_SEL_S  12
-/** IO_MUX_GPIO0_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO0_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO0_FILTER_EN_M  (IO_MUX_GPIO0_FILTER_EN_V << IO_MUX_GPIO0_FILTER_EN_S)
-#define IO_MUX_GPIO0_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO0_FILTER_EN_S  15
-
-/** IO_MUX_gpio1_REG register
- *  iomux control register for gpio1
- */
-#define IO_MUX_GPIO1_REG (DR_REG_IO_MUX_BASE + 0x8)
-/** IO_MUX_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO1_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO1_MCU_OE_M  (IO_MUX_GPIO1_MCU_OE_V << IO_MUX_GPIO1_MCU_OE_S)
-#define IO_MUX_GPIO1_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO1_MCU_OE_S  0
-/** IO_MUX_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO1_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO1_SLP_SEL_M  (IO_MUX_GPIO1_SLP_SEL_V << IO_MUX_GPIO1_SLP_SEL_S)
-#define IO_MUX_GPIO1_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO1_SLP_SEL_S  1
-/** IO_MUX_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO1_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO1_MCU_WPD_M  (IO_MUX_GPIO1_MCU_WPD_V << IO_MUX_GPIO1_MCU_WPD_S)
-#define IO_MUX_GPIO1_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO1_MCU_WPD_S  2
-/** IO_MUX_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO1_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO1_MCU_WPU_M  (IO_MUX_GPIO1_MCU_WPU_V << IO_MUX_GPIO1_MCU_WPU_S)
-#define IO_MUX_GPIO1_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO1_MCU_WPU_S  3
-/** IO_MUX_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO1_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO1_MCU_IE_M  (IO_MUX_GPIO1_MCU_IE_V << IO_MUX_GPIO1_MCU_IE_S)
-#define IO_MUX_GPIO1_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO1_MCU_IE_S  4
-/** IO_MUX_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO1_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO1_MCU_DRV_M  (IO_MUX_GPIO1_MCU_DRV_V << IO_MUX_GPIO1_MCU_DRV_S)
-#define IO_MUX_GPIO1_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO1_MCU_DRV_S  5
-/** IO_MUX_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO1_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO1_FUN_WPD_M  (IO_MUX_GPIO1_FUN_WPD_V << IO_MUX_GPIO1_FUN_WPD_S)
-#define IO_MUX_GPIO1_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO1_FUN_WPD_S  7
-/** IO_MUX_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO1_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO1_FUN_WPU_M  (IO_MUX_GPIO1_FUN_WPU_V << IO_MUX_GPIO1_FUN_WPU_S)
-#define IO_MUX_GPIO1_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO1_FUN_WPU_S  8
-/** IO_MUX_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO1_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO1_FUN_IE_M  (IO_MUX_GPIO1_FUN_IE_V << IO_MUX_GPIO1_FUN_IE_S)
-#define IO_MUX_GPIO1_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO1_FUN_IE_S  9
-/** IO_MUX_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO1_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO1_FUN_DRV_M  (IO_MUX_GPIO1_FUN_DRV_V << IO_MUX_GPIO1_FUN_DRV_S)
-#define IO_MUX_GPIO1_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO1_FUN_DRV_S  10
-/** IO_MUX_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO1_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO1_MCU_SEL_M  (IO_MUX_GPIO1_MCU_SEL_V << IO_MUX_GPIO1_MCU_SEL_S)
-#define IO_MUX_GPIO1_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO1_MCU_SEL_S  12
-/** IO_MUX_GPIO1_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO1_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO1_FILTER_EN_M  (IO_MUX_GPIO1_FILTER_EN_V << IO_MUX_GPIO1_FILTER_EN_S)
-#define IO_MUX_GPIO1_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO1_FILTER_EN_S  15
-
-/** IO_MUX_gpio2_REG register
- *  iomux control register for gpio2
- */
-#define IO_MUX_GPIO2_REG (DR_REG_IO_MUX_BASE + 0xc)
-/** IO_MUX_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO2_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO2_MCU_OE_M  (IO_MUX_GPIO2_MCU_OE_V << IO_MUX_GPIO2_MCU_OE_S)
-#define IO_MUX_GPIO2_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO2_MCU_OE_S  0
-/** IO_MUX_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO2_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO2_SLP_SEL_M  (IO_MUX_GPIO2_SLP_SEL_V << IO_MUX_GPIO2_SLP_SEL_S)
-#define IO_MUX_GPIO2_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO2_SLP_SEL_S  1
-/** IO_MUX_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO2_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO2_MCU_WPD_M  (IO_MUX_GPIO2_MCU_WPD_V << IO_MUX_GPIO2_MCU_WPD_S)
-#define IO_MUX_GPIO2_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO2_MCU_WPD_S  2
-/** IO_MUX_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO2_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO2_MCU_WPU_M  (IO_MUX_GPIO2_MCU_WPU_V << IO_MUX_GPIO2_MCU_WPU_S)
-#define IO_MUX_GPIO2_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO2_MCU_WPU_S  3
-/** IO_MUX_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO2_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO2_MCU_IE_M  (IO_MUX_GPIO2_MCU_IE_V << IO_MUX_GPIO2_MCU_IE_S)
-#define IO_MUX_GPIO2_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO2_MCU_IE_S  4
-/** IO_MUX_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO2_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO2_MCU_DRV_M  (IO_MUX_GPIO2_MCU_DRV_V << IO_MUX_GPIO2_MCU_DRV_S)
-#define IO_MUX_GPIO2_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO2_MCU_DRV_S  5
-/** IO_MUX_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO2_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO2_FUN_WPD_M  (IO_MUX_GPIO2_FUN_WPD_V << IO_MUX_GPIO2_FUN_WPD_S)
-#define IO_MUX_GPIO2_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO2_FUN_WPD_S  7
-/** IO_MUX_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO2_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO2_FUN_WPU_M  (IO_MUX_GPIO2_FUN_WPU_V << IO_MUX_GPIO2_FUN_WPU_S)
-#define IO_MUX_GPIO2_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO2_FUN_WPU_S  8
-/** IO_MUX_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO2_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO2_FUN_IE_M  (IO_MUX_GPIO2_FUN_IE_V << IO_MUX_GPIO2_FUN_IE_S)
-#define IO_MUX_GPIO2_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO2_FUN_IE_S  9
-/** IO_MUX_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO2_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO2_FUN_DRV_M  (IO_MUX_GPIO2_FUN_DRV_V << IO_MUX_GPIO2_FUN_DRV_S)
-#define IO_MUX_GPIO2_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO2_FUN_DRV_S  10
-/** IO_MUX_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO2_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO2_MCU_SEL_M  (IO_MUX_GPIO2_MCU_SEL_V << IO_MUX_GPIO2_MCU_SEL_S)
-#define IO_MUX_GPIO2_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO2_MCU_SEL_S  12
-/** IO_MUX_GPIO2_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO2_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO2_FILTER_EN_M  (IO_MUX_GPIO2_FILTER_EN_V << IO_MUX_GPIO2_FILTER_EN_S)
-#define IO_MUX_GPIO2_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO2_FILTER_EN_S  15
-
-/** IO_MUX_gpio3_REG register
- *  iomux control register for gpio3
- */
-#define IO_MUX_GPIO3_REG (DR_REG_IO_MUX_BASE + 0x10)
-/** IO_MUX_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO3_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO3_MCU_OE_M  (IO_MUX_GPIO3_MCU_OE_V << IO_MUX_GPIO3_MCU_OE_S)
-#define IO_MUX_GPIO3_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO3_MCU_OE_S  0
-/** IO_MUX_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO3_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO3_SLP_SEL_M  (IO_MUX_GPIO3_SLP_SEL_V << IO_MUX_GPIO3_SLP_SEL_S)
-#define IO_MUX_GPIO3_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO3_SLP_SEL_S  1
-/** IO_MUX_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO3_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO3_MCU_WPD_M  (IO_MUX_GPIO3_MCU_WPD_V << IO_MUX_GPIO3_MCU_WPD_S)
-#define IO_MUX_GPIO3_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO3_MCU_WPD_S  2
-/** IO_MUX_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO3_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO3_MCU_WPU_M  (IO_MUX_GPIO3_MCU_WPU_V << IO_MUX_GPIO3_MCU_WPU_S)
-#define IO_MUX_GPIO3_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO3_MCU_WPU_S  3
-/** IO_MUX_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO3_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO3_MCU_IE_M  (IO_MUX_GPIO3_MCU_IE_V << IO_MUX_GPIO3_MCU_IE_S)
-#define IO_MUX_GPIO3_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO3_MCU_IE_S  4
-/** IO_MUX_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO3_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO3_MCU_DRV_M  (IO_MUX_GPIO3_MCU_DRV_V << IO_MUX_GPIO3_MCU_DRV_S)
-#define IO_MUX_GPIO3_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO3_MCU_DRV_S  5
-/** IO_MUX_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO3_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO3_FUN_WPD_M  (IO_MUX_GPIO3_FUN_WPD_V << IO_MUX_GPIO3_FUN_WPD_S)
-#define IO_MUX_GPIO3_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO3_FUN_WPD_S  7
-/** IO_MUX_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO3_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO3_FUN_WPU_M  (IO_MUX_GPIO3_FUN_WPU_V << IO_MUX_GPIO3_FUN_WPU_S)
-#define IO_MUX_GPIO3_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO3_FUN_WPU_S  8
-/** IO_MUX_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO3_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO3_FUN_IE_M  (IO_MUX_GPIO3_FUN_IE_V << IO_MUX_GPIO3_FUN_IE_S)
-#define IO_MUX_GPIO3_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO3_FUN_IE_S  9
-/** IO_MUX_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO3_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO3_FUN_DRV_M  (IO_MUX_GPIO3_FUN_DRV_V << IO_MUX_GPIO3_FUN_DRV_S)
-#define IO_MUX_GPIO3_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO3_FUN_DRV_S  10
-/** IO_MUX_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO3_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO3_MCU_SEL_M  (IO_MUX_GPIO3_MCU_SEL_V << IO_MUX_GPIO3_MCU_SEL_S)
-#define IO_MUX_GPIO3_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO3_MCU_SEL_S  12
-/** IO_MUX_GPIO3_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO3_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO3_FILTER_EN_M  (IO_MUX_GPIO3_FILTER_EN_V << IO_MUX_GPIO3_FILTER_EN_S)
-#define IO_MUX_GPIO3_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO3_FILTER_EN_S  15
-
-/** IO_MUX_gpio4_REG register
- *  iomux control register for gpio4
- */
-#define IO_MUX_GPIO4_REG (DR_REG_IO_MUX_BASE + 0x14)
-/** IO_MUX_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO4_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO4_MCU_OE_M  (IO_MUX_GPIO4_MCU_OE_V << IO_MUX_GPIO4_MCU_OE_S)
-#define IO_MUX_GPIO4_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO4_MCU_OE_S  0
-/** IO_MUX_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO4_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO4_SLP_SEL_M  (IO_MUX_GPIO4_SLP_SEL_V << IO_MUX_GPIO4_SLP_SEL_S)
-#define IO_MUX_GPIO4_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO4_SLP_SEL_S  1
-/** IO_MUX_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO4_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO4_MCU_WPD_M  (IO_MUX_GPIO4_MCU_WPD_V << IO_MUX_GPIO4_MCU_WPD_S)
-#define IO_MUX_GPIO4_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO4_MCU_WPD_S  2
-/** IO_MUX_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO4_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO4_MCU_WPU_M  (IO_MUX_GPIO4_MCU_WPU_V << IO_MUX_GPIO4_MCU_WPU_S)
-#define IO_MUX_GPIO4_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO4_MCU_WPU_S  3
-/** IO_MUX_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO4_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO4_MCU_IE_M  (IO_MUX_GPIO4_MCU_IE_V << IO_MUX_GPIO4_MCU_IE_S)
-#define IO_MUX_GPIO4_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO4_MCU_IE_S  4
-/** IO_MUX_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO4_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO4_MCU_DRV_M  (IO_MUX_GPIO4_MCU_DRV_V << IO_MUX_GPIO4_MCU_DRV_S)
-#define IO_MUX_GPIO4_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO4_MCU_DRV_S  5
-/** IO_MUX_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO4_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO4_FUN_WPD_M  (IO_MUX_GPIO4_FUN_WPD_V << IO_MUX_GPIO4_FUN_WPD_S)
-#define IO_MUX_GPIO4_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO4_FUN_WPD_S  7
-/** IO_MUX_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO4_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO4_FUN_WPU_M  (IO_MUX_GPIO4_FUN_WPU_V << IO_MUX_GPIO4_FUN_WPU_S)
-#define IO_MUX_GPIO4_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO4_FUN_WPU_S  8
-/** IO_MUX_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO4_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO4_FUN_IE_M  (IO_MUX_GPIO4_FUN_IE_V << IO_MUX_GPIO4_FUN_IE_S)
-#define IO_MUX_GPIO4_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO4_FUN_IE_S  9
-/** IO_MUX_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO4_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO4_FUN_DRV_M  (IO_MUX_GPIO4_FUN_DRV_V << IO_MUX_GPIO4_FUN_DRV_S)
-#define IO_MUX_GPIO4_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO4_FUN_DRV_S  10
-/** IO_MUX_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO4_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO4_MCU_SEL_M  (IO_MUX_GPIO4_MCU_SEL_V << IO_MUX_GPIO4_MCU_SEL_S)
-#define IO_MUX_GPIO4_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO4_MCU_SEL_S  12
-/** IO_MUX_GPIO4_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO4_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO4_FILTER_EN_M  (IO_MUX_GPIO4_FILTER_EN_V << IO_MUX_GPIO4_FILTER_EN_S)
-#define IO_MUX_GPIO4_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO4_FILTER_EN_S  15
-
-/** IO_MUX_gpio5_REG register
- *  iomux control register for gpio5
- */
-#define IO_MUX_GPIO5_REG (DR_REG_IO_MUX_BASE + 0x18)
-/** IO_MUX_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO5_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO5_MCU_OE_M  (IO_MUX_GPIO5_MCU_OE_V << IO_MUX_GPIO5_MCU_OE_S)
-#define IO_MUX_GPIO5_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO5_MCU_OE_S  0
-/** IO_MUX_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO5_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO5_SLP_SEL_M  (IO_MUX_GPIO5_SLP_SEL_V << IO_MUX_GPIO5_SLP_SEL_S)
-#define IO_MUX_GPIO5_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO5_SLP_SEL_S  1
-/** IO_MUX_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO5_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO5_MCU_WPD_M  (IO_MUX_GPIO5_MCU_WPD_V << IO_MUX_GPIO5_MCU_WPD_S)
-#define IO_MUX_GPIO5_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO5_MCU_WPD_S  2
-/** IO_MUX_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO5_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO5_MCU_WPU_M  (IO_MUX_GPIO5_MCU_WPU_V << IO_MUX_GPIO5_MCU_WPU_S)
-#define IO_MUX_GPIO5_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO5_MCU_WPU_S  3
-/** IO_MUX_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO5_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO5_MCU_IE_M  (IO_MUX_GPIO5_MCU_IE_V << IO_MUX_GPIO5_MCU_IE_S)
-#define IO_MUX_GPIO5_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO5_MCU_IE_S  4
-/** IO_MUX_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO5_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO5_MCU_DRV_M  (IO_MUX_GPIO5_MCU_DRV_V << IO_MUX_GPIO5_MCU_DRV_S)
-#define IO_MUX_GPIO5_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO5_MCU_DRV_S  5
-/** IO_MUX_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO5_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO5_FUN_WPD_M  (IO_MUX_GPIO5_FUN_WPD_V << IO_MUX_GPIO5_FUN_WPD_S)
-#define IO_MUX_GPIO5_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO5_FUN_WPD_S  7
-/** IO_MUX_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO5_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO5_FUN_WPU_M  (IO_MUX_GPIO5_FUN_WPU_V << IO_MUX_GPIO5_FUN_WPU_S)
-#define IO_MUX_GPIO5_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO5_FUN_WPU_S  8
-/** IO_MUX_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO5_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO5_FUN_IE_M  (IO_MUX_GPIO5_FUN_IE_V << IO_MUX_GPIO5_FUN_IE_S)
-#define IO_MUX_GPIO5_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO5_FUN_IE_S  9
-/** IO_MUX_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO5_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO5_FUN_DRV_M  (IO_MUX_GPIO5_FUN_DRV_V << IO_MUX_GPIO5_FUN_DRV_S)
-#define IO_MUX_GPIO5_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO5_FUN_DRV_S  10
-/** IO_MUX_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO5_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO5_MCU_SEL_M  (IO_MUX_GPIO5_MCU_SEL_V << IO_MUX_GPIO5_MCU_SEL_S)
-#define IO_MUX_GPIO5_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO5_MCU_SEL_S  12
-/** IO_MUX_GPIO5_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO5_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO5_FILTER_EN_M  (IO_MUX_GPIO5_FILTER_EN_V << IO_MUX_GPIO5_FILTER_EN_S)
-#define IO_MUX_GPIO5_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO5_FILTER_EN_S  15
-
-/** IO_MUX_gpio6_REG register
- *  iomux control register for gpio6
- */
-#define IO_MUX_GPIO6_REG (DR_REG_IO_MUX_BASE + 0x1c)
-/** IO_MUX_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO6_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO6_MCU_OE_M  (IO_MUX_GPIO6_MCU_OE_V << IO_MUX_GPIO6_MCU_OE_S)
-#define IO_MUX_GPIO6_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO6_MCU_OE_S  0
-/** IO_MUX_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO6_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO6_SLP_SEL_M  (IO_MUX_GPIO6_SLP_SEL_V << IO_MUX_GPIO6_SLP_SEL_S)
-#define IO_MUX_GPIO6_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO6_SLP_SEL_S  1
-/** IO_MUX_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO6_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO6_MCU_WPD_M  (IO_MUX_GPIO6_MCU_WPD_V << IO_MUX_GPIO6_MCU_WPD_S)
-#define IO_MUX_GPIO6_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO6_MCU_WPD_S  2
-/** IO_MUX_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO6_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO6_MCU_WPU_M  (IO_MUX_GPIO6_MCU_WPU_V << IO_MUX_GPIO6_MCU_WPU_S)
-#define IO_MUX_GPIO6_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO6_MCU_WPU_S  3
-/** IO_MUX_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO6_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO6_MCU_IE_M  (IO_MUX_GPIO6_MCU_IE_V << IO_MUX_GPIO6_MCU_IE_S)
-#define IO_MUX_GPIO6_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO6_MCU_IE_S  4
-/** IO_MUX_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO6_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO6_MCU_DRV_M  (IO_MUX_GPIO6_MCU_DRV_V << IO_MUX_GPIO6_MCU_DRV_S)
-#define IO_MUX_GPIO6_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO6_MCU_DRV_S  5
-/** IO_MUX_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO6_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO6_FUN_WPD_M  (IO_MUX_GPIO6_FUN_WPD_V << IO_MUX_GPIO6_FUN_WPD_S)
-#define IO_MUX_GPIO6_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO6_FUN_WPD_S  7
-/** IO_MUX_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO6_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO6_FUN_WPU_M  (IO_MUX_GPIO6_FUN_WPU_V << IO_MUX_GPIO6_FUN_WPU_S)
-#define IO_MUX_GPIO6_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO6_FUN_WPU_S  8
-/** IO_MUX_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO6_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO6_FUN_IE_M  (IO_MUX_GPIO6_FUN_IE_V << IO_MUX_GPIO6_FUN_IE_S)
-#define IO_MUX_GPIO6_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO6_FUN_IE_S  9
-/** IO_MUX_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO6_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO6_FUN_DRV_M  (IO_MUX_GPIO6_FUN_DRV_V << IO_MUX_GPIO6_FUN_DRV_S)
-#define IO_MUX_GPIO6_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO6_FUN_DRV_S  10
-/** IO_MUX_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO6_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO6_MCU_SEL_M  (IO_MUX_GPIO6_MCU_SEL_V << IO_MUX_GPIO6_MCU_SEL_S)
-#define IO_MUX_GPIO6_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO6_MCU_SEL_S  12
-/** IO_MUX_GPIO6_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO6_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO6_FILTER_EN_M  (IO_MUX_GPIO6_FILTER_EN_V << IO_MUX_GPIO6_FILTER_EN_S)
-#define IO_MUX_GPIO6_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO6_FILTER_EN_S  15
-
-/** IO_MUX_gpio7_REG register
- *  iomux control register for gpio7
- */
-#define IO_MUX_GPIO7_REG (DR_REG_IO_MUX_BASE + 0x20)
-/** IO_MUX_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO7_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO7_MCU_OE_M  (IO_MUX_GPIO7_MCU_OE_V << IO_MUX_GPIO7_MCU_OE_S)
-#define IO_MUX_GPIO7_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO7_MCU_OE_S  0
-/** IO_MUX_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO7_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO7_SLP_SEL_M  (IO_MUX_GPIO7_SLP_SEL_V << IO_MUX_GPIO7_SLP_SEL_S)
-#define IO_MUX_GPIO7_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO7_SLP_SEL_S  1
-/** IO_MUX_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO7_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO7_MCU_WPD_M  (IO_MUX_GPIO7_MCU_WPD_V << IO_MUX_GPIO7_MCU_WPD_S)
-#define IO_MUX_GPIO7_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO7_MCU_WPD_S  2
-/** IO_MUX_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO7_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO7_MCU_WPU_M  (IO_MUX_GPIO7_MCU_WPU_V << IO_MUX_GPIO7_MCU_WPU_S)
-#define IO_MUX_GPIO7_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO7_MCU_WPU_S  3
-/** IO_MUX_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO7_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO7_MCU_IE_M  (IO_MUX_GPIO7_MCU_IE_V << IO_MUX_GPIO7_MCU_IE_S)
-#define IO_MUX_GPIO7_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO7_MCU_IE_S  4
-/** IO_MUX_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO7_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO7_MCU_DRV_M  (IO_MUX_GPIO7_MCU_DRV_V << IO_MUX_GPIO7_MCU_DRV_S)
-#define IO_MUX_GPIO7_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO7_MCU_DRV_S  5
-/** IO_MUX_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO7_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO7_FUN_WPD_M  (IO_MUX_GPIO7_FUN_WPD_V << IO_MUX_GPIO7_FUN_WPD_S)
-#define IO_MUX_GPIO7_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO7_FUN_WPD_S  7
-/** IO_MUX_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO7_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO7_FUN_WPU_M  (IO_MUX_GPIO7_FUN_WPU_V << IO_MUX_GPIO7_FUN_WPU_S)
-#define IO_MUX_GPIO7_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO7_FUN_WPU_S  8
-/** IO_MUX_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO7_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO7_FUN_IE_M  (IO_MUX_GPIO7_FUN_IE_V << IO_MUX_GPIO7_FUN_IE_S)
-#define IO_MUX_GPIO7_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO7_FUN_IE_S  9
-/** IO_MUX_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO7_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO7_FUN_DRV_M  (IO_MUX_GPIO7_FUN_DRV_V << IO_MUX_GPIO7_FUN_DRV_S)
-#define IO_MUX_GPIO7_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO7_FUN_DRV_S  10
-/** IO_MUX_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO7_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO7_MCU_SEL_M  (IO_MUX_GPIO7_MCU_SEL_V << IO_MUX_GPIO7_MCU_SEL_S)
-#define IO_MUX_GPIO7_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO7_MCU_SEL_S  12
-/** IO_MUX_GPIO7_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO7_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO7_FILTER_EN_M  (IO_MUX_GPIO7_FILTER_EN_V << IO_MUX_GPIO7_FILTER_EN_S)
-#define IO_MUX_GPIO7_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO7_FILTER_EN_S  15
-
-/** IO_MUX_gpio8_REG register
- *  iomux control register for gpio8
- */
-#define IO_MUX_GPIO8_REG (DR_REG_IO_MUX_BASE + 0x24)
-/** IO_MUX_GPIO8_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO8_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO8_MCU_OE_M  (IO_MUX_GPIO8_MCU_OE_V << IO_MUX_GPIO8_MCU_OE_S)
-#define IO_MUX_GPIO8_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO8_MCU_OE_S  0
-/** IO_MUX_GPIO8_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO8_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO8_SLP_SEL_M  (IO_MUX_GPIO8_SLP_SEL_V << IO_MUX_GPIO8_SLP_SEL_S)
-#define IO_MUX_GPIO8_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO8_SLP_SEL_S  1
-/** IO_MUX_GPIO8_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO8_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO8_MCU_WPD_M  (IO_MUX_GPIO8_MCU_WPD_V << IO_MUX_GPIO8_MCU_WPD_S)
-#define IO_MUX_GPIO8_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO8_MCU_WPD_S  2
-/** IO_MUX_GPIO8_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO8_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO8_MCU_WPU_M  (IO_MUX_GPIO8_MCU_WPU_V << IO_MUX_GPIO8_MCU_WPU_S)
-#define IO_MUX_GPIO8_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO8_MCU_WPU_S  3
-/** IO_MUX_GPIO8_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO8_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO8_MCU_IE_M  (IO_MUX_GPIO8_MCU_IE_V << IO_MUX_GPIO8_MCU_IE_S)
-#define IO_MUX_GPIO8_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO8_MCU_IE_S  4
-/** IO_MUX_GPIO8_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO8_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO8_MCU_DRV_M  (IO_MUX_GPIO8_MCU_DRV_V << IO_MUX_GPIO8_MCU_DRV_S)
-#define IO_MUX_GPIO8_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO8_MCU_DRV_S  5
-/** IO_MUX_GPIO8_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO8_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO8_FUN_WPD_M  (IO_MUX_GPIO8_FUN_WPD_V << IO_MUX_GPIO8_FUN_WPD_S)
-#define IO_MUX_GPIO8_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO8_FUN_WPD_S  7
-/** IO_MUX_GPIO8_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO8_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO8_FUN_WPU_M  (IO_MUX_GPIO8_FUN_WPU_V << IO_MUX_GPIO8_FUN_WPU_S)
-#define IO_MUX_GPIO8_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO8_FUN_WPU_S  8
-/** IO_MUX_GPIO8_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO8_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO8_FUN_IE_M  (IO_MUX_GPIO8_FUN_IE_V << IO_MUX_GPIO8_FUN_IE_S)
-#define IO_MUX_GPIO8_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO8_FUN_IE_S  9
-/** IO_MUX_GPIO8_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO8_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO8_FUN_DRV_M  (IO_MUX_GPIO8_FUN_DRV_V << IO_MUX_GPIO8_FUN_DRV_S)
-#define IO_MUX_GPIO8_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO8_FUN_DRV_S  10
-/** IO_MUX_GPIO8_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO8_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO8_MCU_SEL_M  (IO_MUX_GPIO8_MCU_SEL_V << IO_MUX_GPIO8_MCU_SEL_S)
-#define IO_MUX_GPIO8_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO8_MCU_SEL_S  12
-/** IO_MUX_GPIO8_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO8_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO8_FILTER_EN_M  (IO_MUX_GPIO8_FILTER_EN_V << IO_MUX_GPIO8_FILTER_EN_S)
-#define IO_MUX_GPIO8_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO8_FILTER_EN_S  15
-
-/** IO_MUX_gpio9_REG register
- *  iomux control register for gpio9
- */
-#define IO_MUX_GPIO9_REG (DR_REG_IO_MUX_BASE + 0x28)
-/** IO_MUX_GPIO9_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO9_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO9_MCU_OE_M  (IO_MUX_GPIO9_MCU_OE_V << IO_MUX_GPIO9_MCU_OE_S)
-#define IO_MUX_GPIO9_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO9_MCU_OE_S  0
-/** IO_MUX_GPIO9_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO9_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO9_SLP_SEL_M  (IO_MUX_GPIO9_SLP_SEL_V << IO_MUX_GPIO9_SLP_SEL_S)
-#define IO_MUX_GPIO9_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO9_SLP_SEL_S  1
-/** IO_MUX_GPIO9_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO9_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO9_MCU_WPD_M  (IO_MUX_GPIO9_MCU_WPD_V << IO_MUX_GPIO9_MCU_WPD_S)
-#define IO_MUX_GPIO9_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO9_MCU_WPD_S  2
-/** IO_MUX_GPIO9_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO9_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO9_MCU_WPU_M  (IO_MUX_GPIO9_MCU_WPU_V << IO_MUX_GPIO9_MCU_WPU_S)
-#define IO_MUX_GPIO9_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO9_MCU_WPU_S  3
-/** IO_MUX_GPIO9_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO9_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO9_MCU_IE_M  (IO_MUX_GPIO9_MCU_IE_V << IO_MUX_GPIO9_MCU_IE_S)
-#define IO_MUX_GPIO9_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO9_MCU_IE_S  4
-/** IO_MUX_GPIO9_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO9_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO9_MCU_DRV_M  (IO_MUX_GPIO9_MCU_DRV_V << IO_MUX_GPIO9_MCU_DRV_S)
-#define IO_MUX_GPIO9_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO9_MCU_DRV_S  5
-/** IO_MUX_GPIO9_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO9_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO9_FUN_WPD_M  (IO_MUX_GPIO9_FUN_WPD_V << IO_MUX_GPIO9_FUN_WPD_S)
-#define IO_MUX_GPIO9_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO9_FUN_WPD_S  7
-/** IO_MUX_GPIO9_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO9_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO9_FUN_WPU_M  (IO_MUX_GPIO9_FUN_WPU_V << IO_MUX_GPIO9_FUN_WPU_S)
-#define IO_MUX_GPIO9_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO9_FUN_WPU_S  8
-/** IO_MUX_GPIO9_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO9_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO9_FUN_IE_M  (IO_MUX_GPIO9_FUN_IE_V << IO_MUX_GPIO9_FUN_IE_S)
-#define IO_MUX_GPIO9_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO9_FUN_IE_S  9
-/** IO_MUX_GPIO9_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO9_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO9_FUN_DRV_M  (IO_MUX_GPIO9_FUN_DRV_V << IO_MUX_GPIO9_FUN_DRV_S)
-#define IO_MUX_GPIO9_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO9_FUN_DRV_S  10
-/** IO_MUX_GPIO9_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO9_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO9_MCU_SEL_M  (IO_MUX_GPIO9_MCU_SEL_V << IO_MUX_GPIO9_MCU_SEL_S)
-#define IO_MUX_GPIO9_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO9_MCU_SEL_S  12
-/** IO_MUX_GPIO9_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO9_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO9_FILTER_EN_M  (IO_MUX_GPIO9_FILTER_EN_V << IO_MUX_GPIO9_FILTER_EN_S)
-#define IO_MUX_GPIO9_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO9_FILTER_EN_S  15
-
-/** IO_MUX_gpio10_REG register
- *  iomux control register for gpio10
- */
-#define IO_MUX_GPIO10_REG (DR_REG_IO_MUX_BASE + 0x2c)
-/** IO_MUX_GPIO10_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO10_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO10_MCU_OE_M  (IO_MUX_GPIO10_MCU_OE_V << IO_MUX_GPIO10_MCU_OE_S)
-#define IO_MUX_GPIO10_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO10_MCU_OE_S  0
-/** IO_MUX_GPIO10_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO10_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO10_SLP_SEL_M  (IO_MUX_GPIO10_SLP_SEL_V << IO_MUX_GPIO10_SLP_SEL_S)
-#define IO_MUX_GPIO10_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO10_SLP_SEL_S  1
-/** IO_MUX_GPIO10_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO10_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO10_MCU_WPD_M  (IO_MUX_GPIO10_MCU_WPD_V << IO_MUX_GPIO10_MCU_WPD_S)
-#define IO_MUX_GPIO10_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO10_MCU_WPD_S  2
-/** IO_MUX_GPIO10_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO10_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO10_MCU_WPU_M  (IO_MUX_GPIO10_MCU_WPU_V << IO_MUX_GPIO10_MCU_WPU_S)
-#define IO_MUX_GPIO10_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO10_MCU_WPU_S  3
-/** IO_MUX_GPIO10_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO10_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO10_MCU_IE_M  (IO_MUX_GPIO10_MCU_IE_V << IO_MUX_GPIO10_MCU_IE_S)
-#define IO_MUX_GPIO10_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO10_MCU_IE_S  4
-/** IO_MUX_GPIO10_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO10_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO10_MCU_DRV_M  (IO_MUX_GPIO10_MCU_DRV_V << IO_MUX_GPIO10_MCU_DRV_S)
-#define IO_MUX_GPIO10_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO10_MCU_DRV_S  5
-/** IO_MUX_GPIO10_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO10_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO10_FUN_WPD_M  (IO_MUX_GPIO10_FUN_WPD_V << IO_MUX_GPIO10_FUN_WPD_S)
-#define IO_MUX_GPIO10_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO10_FUN_WPD_S  7
-/** IO_MUX_GPIO10_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO10_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO10_FUN_WPU_M  (IO_MUX_GPIO10_FUN_WPU_V << IO_MUX_GPIO10_FUN_WPU_S)
-#define IO_MUX_GPIO10_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO10_FUN_WPU_S  8
-/** IO_MUX_GPIO10_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO10_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO10_FUN_IE_M  (IO_MUX_GPIO10_FUN_IE_V << IO_MUX_GPIO10_FUN_IE_S)
-#define IO_MUX_GPIO10_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO10_FUN_IE_S  9
-/** IO_MUX_GPIO10_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO10_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO10_FUN_DRV_M  (IO_MUX_GPIO10_FUN_DRV_V << IO_MUX_GPIO10_FUN_DRV_S)
-#define IO_MUX_GPIO10_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO10_FUN_DRV_S  10
-/** IO_MUX_GPIO10_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO10_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO10_MCU_SEL_M  (IO_MUX_GPIO10_MCU_SEL_V << IO_MUX_GPIO10_MCU_SEL_S)
-#define IO_MUX_GPIO10_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO10_MCU_SEL_S  12
-/** IO_MUX_GPIO10_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO10_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO10_FILTER_EN_M  (IO_MUX_GPIO10_FILTER_EN_V << IO_MUX_GPIO10_FILTER_EN_S)
-#define IO_MUX_GPIO10_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO10_FILTER_EN_S  15
-
-/** IO_MUX_gpio11_REG register
- *  iomux control register for gpio11
- */
-#define IO_MUX_GPIO11_REG (DR_REG_IO_MUX_BASE + 0x30)
-/** IO_MUX_GPIO11_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO11_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO11_MCU_OE_M  (IO_MUX_GPIO11_MCU_OE_V << IO_MUX_GPIO11_MCU_OE_S)
-#define IO_MUX_GPIO11_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO11_MCU_OE_S  0
-/** IO_MUX_GPIO11_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO11_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO11_SLP_SEL_M  (IO_MUX_GPIO11_SLP_SEL_V << IO_MUX_GPIO11_SLP_SEL_S)
-#define IO_MUX_GPIO11_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO11_SLP_SEL_S  1
-/** IO_MUX_GPIO11_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO11_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO11_MCU_WPD_M  (IO_MUX_GPIO11_MCU_WPD_V << IO_MUX_GPIO11_MCU_WPD_S)
-#define IO_MUX_GPIO11_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO11_MCU_WPD_S  2
-/** IO_MUX_GPIO11_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO11_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO11_MCU_WPU_M  (IO_MUX_GPIO11_MCU_WPU_V << IO_MUX_GPIO11_MCU_WPU_S)
-#define IO_MUX_GPIO11_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO11_MCU_WPU_S  3
-/** IO_MUX_GPIO11_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO11_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO11_MCU_IE_M  (IO_MUX_GPIO11_MCU_IE_V << IO_MUX_GPIO11_MCU_IE_S)
-#define IO_MUX_GPIO11_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO11_MCU_IE_S  4
-/** IO_MUX_GPIO11_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO11_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO11_MCU_DRV_M  (IO_MUX_GPIO11_MCU_DRV_V << IO_MUX_GPIO11_MCU_DRV_S)
-#define IO_MUX_GPIO11_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO11_MCU_DRV_S  5
-/** IO_MUX_GPIO11_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO11_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO11_FUN_WPD_M  (IO_MUX_GPIO11_FUN_WPD_V << IO_MUX_GPIO11_FUN_WPD_S)
-#define IO_MUX_GPIO11_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO11_FUN_WPD_S  7
-/** IO_MUX_GPIO11_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO11_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO11_FUN_WPU_M  (IO_MUX_GPIO11_FUN_WPU_V << IO_MUX_GPIO11_FUN_WPU_S)
-#define IO_MUX_GPIO11_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO11_FUN_WPU_S  8
-/** IO_MUX_GPIO11_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO11_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO11_FUN_IE_M  (IO_MUX_GPIO11_FUN_IE_V << IO_MUX_GPIO11_FUN_IE_S)
-#define IO_MUX_GPIO11_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO11_FUN_IE_S  9
-/** IO_MUX_GPIO11_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO11_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO11_FUN_DRV_M  (IO_MUX_GPIO11_FUN_DRV_V << IO_MUX_GPIO11_FUN_DRV_S)
-#define IO_MUX_GPIO11_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO11_FUN_DRV_S  10
-/** IO_MUX_GPIO11_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO11_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO11_MCU_SEL_M  (IO_MUX_GPIO11_MCU_SEL_V << IO_MUX_GPIO11_MCU_SEL_S)
-#define IO_MUX_GPIO11_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO11_MCU_SEL_S  12
-/** IO_MUX_GPIO11_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO11_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO11_FILTER_EN_M  (IO_MUX_GPIO11_FILTER_EN_V << IO_MUX_GPIO11_FILTER_EN_S)
-#define IO_MUX_GPIO11_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO11_FILTER_EN_S  15
-
-/** IO_MUX_gpio12_REG register
- *  iomux control register for gpio12
- */
-#define IO_MUX_GPIO12_REG (DR_REG_IO_MUX_BASE + 0x34)
-/** IO_MUX_GPIO12_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO12_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO12_MCU_OE_M  (IO_MUX_GPIO12_MCU_OE_V << IO_MUX_GPIO12_MCU_OE_S)
-#define IO_MUX_GPIO12_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO12_MCU_OE_S  0
-/** IO_MUX_GPIO12_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO12_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO12_SLP_SEL_M  (IO_MUX_GPIO12_SLP_SEL_V << IO_MUX_GPIO12_SLP_SEL_S)
-#define IO_MUX_GPIO12_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO12_SLP_SEL_S  1
-/** IO_MUX_GPIO12_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO12_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO12_MCU_WPD_M  (IO_MUX_GPIO12_MCU_WPD_V << IO_MUX_GPIO12_MCU_WPD_S)
-#define IO_MUX_GPIO12_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO12_MCU_WPD_S  2
-/** IO_MUX_GPIO12_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO12_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO12_MCU_WPU_M  (IO_MUX_GPIO12_MCU_WPU_V << IO_MUX_GPIO12_MCU_WPU_S)
-#define IO_MUX_GPIO12_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO12_MCU_WPU_S  3
-/** IO_MUX_GPIO12_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO12_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO12_MCU_IE_M  (IO_MUX_GPIO12_MCU_IE_V << IO_MUX_GPIO12_MCU_IE_S)
-#define IO_MUX_GPIO12_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO12_MCU_IE_S  4
-/** IO_MUX_GPIO12_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO12_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO12_MCU_DRV_M  (IO_MUX_GPIO12_MCU_DRV_V << IO_MUX_GPIO12_MCU_DRV_S)
-#define IO_MUX_GPIO12_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO12_MCU_DRV_S  5
-/** IO_MUX_GPIO12_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO12_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO12_FUN_WPD_M  (IO_MUX_GPIO12_FUN_WPD_V << IO_MUX_GPIO12_FUN_WPD_S)
-#define IO_MUX_GPIO12_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO12_FUN_WPD_S  7
-/** IO_MUX_GPIO12_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO12_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO12_FUN_WPU_M  (IO_MUX_GPIO12_FUN_WPU_V << IO_MUX_GPIO12_FUN_WPU_S)
-#define IO_MUX_GPIO12_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO12_FUN_WPU_S  8
-/** IO_MUX_GPIO12_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO12_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO12_FUN_IE_M  (IO_MUX_GPIO12_FUN_IE_V << IO_MUX_GPIO12_FUN_IE_S)
-#define IO_MUX_GPIO12_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO12_FUN_IE_S  9
-/** IO_MUX_GPIO12_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO12_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO12_FUN_DRV_M  (IO_MUX_GPIO12_FUN_DRV_V << IO_MUX_GPIO12_FUN_DRV_S)
-#define IO_MUX_GPIO12_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO12_FUN_DRV_S  10
-/** IO_MUX_GPIO12_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO12_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO12_MCU_SEL_M  (IO_MUX_GPIO12_MCU_SEL_V << IO_MUX_GPIO12_MCU_SEL_S)
-#define IO_MUX_GPIO12_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO12_MCU_SEL_S  12
-/** IO_MUX_GPIO12_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO12_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO12_FILTER_EN_M  (IO_MUX_GPIO12_FILTER_EN_V << IO_MUX_GPIO12_FILTER_EN_S)
-#define IO_MUX_GPIO12_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO12_FILTER_EN_S  15
-
-/** IO_MUX_gpio13_REG register
- *  iomux control register for gpio13
- */
-#define IO_MUX_GPIO13_REG (DR_REG_IO_MUX_BASE + 0x38)
-/** IO_MUX_GPIO13_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO13_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO13_MCU_OE_M  (IO_MUX_GPIO13_MCU_OE_V << IO_MUX_GPIO13_MCU_OE_S)
-#define IO_MUX_GPIO13_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO13_MCU_OE_S  0
-/** IO_MUX_GPIO13_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO13_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO13_SLP_SEL_M  (IO_MUX_GPIO13_SLP_SEL_V << IO_MUX_GPIO13_SLP_SEL_S)
-#define IO_MUX_GPIO13_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO13_SLP_SEL_S  1
-/** IO_MUX_GPIO13_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO13_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO13_MCU_WPD_M  (IO_MUX_GPIO13_MCU_WPD_V << IO_MUX_GPIO13_MCU_WPD_S)
-#define IO_MUX_GPIO13_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO13_MCU_WPD_S  2
-/** IO_MUX_GPIO13_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO13_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO13_MCU_WPU_M  (IO_MUX_GPIO13_MCU_WPU_V << IO_MUX_GPIO13_MCU_WPU_S)
-#define IO_MUX_GPIO13_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO13_MCU_WPU_S  3
-/** IO_MUX_GPIO13_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO13_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO13_MCU_IE_M  (IO_MUX_GPIO13_MCU_IE_V << IO_MUX_GPIO13_MCU_IE_S)
-#define IO_MUX_GPIO13_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO13_MCU_IE_S  4
-/** IO_MUX_GPIO13_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO13_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO13_MCU_DRV_M  (IO_MUX_GPIO13_MCU_DRV_V << IO_MUX_GPIO13_MCU_DRV_S)
-#define IO_MUX_GPIO13_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO13_MCU_DRV_S  5
-/** IO_MUX_GPIO13_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO13_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO13_FUN_WPD_M  (IO_MUX_GPIO13_FUN_WPD_V << IO_MUX_GPIO13_FUN_WPD_S)
-#define IO_MUX_GPIO13_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO13_FUN_WPD_S  7
-/** IO_MUX_GPIO13_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO13_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO13_FUN_WPU_M  (IO_MUX_GPIO13_FUN_WPU_V << IO_MUX_GPIO13_FUN_WPU_S)
-#define IO_MUX_GPIO13_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO13_FUN_WPU_S  8
-/** IO_MUX_GPIO13_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO13_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO13_FUN_IE_M  (IO_MUX_GPIO13_FUN_IE_V << IO_MUX_GPIO13_FUN_IE_S)
-#define IO_MUX_GPIO13_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO13_FUN_IE_S  9
-/** IO_MUX_GPIO13_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO13_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO13_FUN_DRV_M  (IO_MUX_GPIO13_FUN_DRV_V << IO_MUX_GPIO13_FUN_DRV_S)
-#define IO_MUX_GPIO13_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO13_FUN_DRV_S  10
-/** IO_MUX_GPIO13_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO13_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO13_MCU_SEL_M  (IO_MUX_GPIO13_MCU_SEL_V << IO_MUX_GPIO13_MCU_SEL_S)
-#define IO_MUX_GPIO13_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO13_MCU_SEL_S  12
-/** IO_MUX_GPIO13_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO13_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO13_FILTER_EN_M  (IO_MUX_GPIO13_FILTER_EN_V << IO_MUX_GPIO13_FILTER_EN_S)
-#define IO_MUX_GPIO13_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO13_FILTER_EN_S  15
-
-/** IO_MUX_gpio14_REG register
- *  iomux control register for gpio14
- */
-#define IO_MUX_GPIO14_REG (DR_REG_IO_MUX_BASE + 0x3c)
-/** IO_MUX_GPIO14_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO14_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO14_MCU_OE_M  (IO_MUX_GPIO14_MCU_OE_V << IO_MUX_GPIO14_MCU_OE_S)
-#define IO_MUX_GPIO14_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO14_MCU_OE_S  0
-/** IO_MUX_GPIO14_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO14_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO14_SLP_SEL_M  (IO_MUX_GPIO14_SLP_SEL_V << IO_MUX_GPIO14_SLP_SEL_S)
-#define IO_MUX_GPIO14_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO14_SLP_SEL_S  1
-/** IO_MUX_GPIO14_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO14_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO14_MCU_WPD_M  (IO_MUX_GPIO14_MCU_WPD_V << IO_MUX_GPIO14_MCU_WPD_S)
-#define IO_MUX_GPIO14_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO14_MCU_WPD_S  2
-/** IO_MUX_GPIO14_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO14_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO14_MCU_WPU_M  (IO_MUX_GPIO14_MCU_WPU_V << IO_MUX_GPIO14_MCU_WPU_S)
-#define IO_MUX_GPIO14_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO14_MCU_WPU_S  3
-/** IO_MUX_GPIO14_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO14_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO14_MCU_IE_M  (IO_MUX_GPIO14_MCU_IE_V << IO_MUX_GPIO14_MCU_IE_S)
-#define IO_MUX_GPIO14_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO14_MCU_IE_S  4
-/** IO_MUX_GPIO14_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO14_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO14_MCU_DRV_M  (IO_MUX_GPIO14_MCU_DRV_V << IO_MUX_GPIO14_MCU_DRV_S)
-#define IO_MUX_GPIO14_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO14_MCU_DRV_S  5
-/** IO_MUX_GPIO14_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO14_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO14_FUN_WPD_M  (IO_MUX_GPIO14_FUN_WPD_V << IO_MUX_GPIO14_FUN_WPD_S)
-#define IO_MUX_GPIO14_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO14_FUN_WPD_S  7
-/** IO_MUX_GPIO14_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO14_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO14_FUN_WPU_M  (IO_MUX_GPIO14_FUN_WPU_V << IO_MUX_GPIO14_FUN_WPU_S)
-#define IO_MUX_GPIO14_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO14_FUN_WPU_S  8
-/** IO_MUX_GPIO14_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO14_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO14_FUN_IE_M  (IO_MUX_GPIO14_FUN_IE_V << IO_MUX_GPIO14_FUN_IE_S)
-#define IO_MUX_GPIO14_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO14_FUN_IE_S  9
-/** IO_MUX_GPIO14_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO14_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO14_FUN_DRV_M  (IO_MUX_GPIO14_FUN_DRV_V << IO_MUX_GPIO14_FUN_DRV_S)
-#define IO_MUX_GPIO14_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO14_FUN_DRV_S  10
-/** IO_MUX_GPIO14_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO14_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO14_MCU_SEL_M  (IO_MUX_GPIO14_MCU_SEL_V << IO_MUX_GPIO14_MCU_SEL_S)
-#define IO_MUX_GPIO14_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO14_MCU_SEL_S  12
-/** IO_MUX_GPIO14_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO14_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO14_FILTER_EN_M  (IO_MUX_GPIO14_FILTER_EN_V << IO_MUX_GPIO14_FILTER_EN_S)
-#define IO_MUX_GPIO14_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO14_FILTER_EN_S  15
-
-/** IO_MUX_gpio15_REG register
- *  iomux control register for gpio15
- */
-#define IO_MUX_GPIO15_REG (DR_REG_IO_MUX_BASE + 0x40)
-/** IO_MUX_GPIO15_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO15_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO15_MCU_OE_M  (IO_MUX_GPIO15_MCU_OE_V << IO_MUX_GPIO15_MCU_OE_S)
-#define IO_MUX_GPIO15_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO15_MCU_OE_S  0
-/** IO_MUX_GPIO15_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO15_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO15_SLP_SEL_M  (IO_MUX_GPIO15_SLP_SEL_V << IO_MUX_GPIO15_SLP_SEL_S)
-#define IO_MUX_GPIO15_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO15_SLP_SEL_S  1
-/** IO_MUX_GPIO15_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO15_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO15_MCU_WPD_M  (IO_MUX_GPIO15_MCU_WPD_V << IO_MUX_GPIO15_MCU_WPD_S)
-#define IO_MUX_GPIO15_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO15_MCU_WPD_S  2
-/** IO_MUX_GPIO15_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO15_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO15_MCU_WPU_M  (IO_MUX_GPIO15_MCU_WPU_V << IO_MUX_GPIO15_MCU_WPU_S)
-#define IO_MUX_GPIO15_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO15_MCU_WPU_S  3
-/** IO_MUX_GPIO15_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO15_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO15_MCU_IE_M  (IO_MUX_GPIO15_MCU_IE_V << IO_MUX_GPIO15_MCU_IE_S)
-#define IO_MUX_GPIO15_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO15_MCU_IE_S  4
-/** IO_MUX_GPIO15_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO15_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO15_MCU_DRV_M  (IO_MUX_GPIO15_MCU_DRV_V << IO_MUX_GPIO15_MCU_DRV_S)
-#define IO_MUX_GPIO15_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO15_MCU_DRV_S  5
-/** IO_MUX_GPIO15_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO15_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO15_FUN_WPD_M  (IO_MUX_GPIO15_FUN_WPD_V << IO_MUX_GPIO15_FUN_WPD_S)
-#define IO_MUX_GPIO15_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO15_FUN_WPD_S  7
-/** IO_MUX_GPIO15_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO15_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO15_FUN_WPU_M  (IO_MUX_GPIO15_FUN_WPU_V << IO_MUX_GPIO15_FUN_WPU_S)
-#define IO_MUX_GPIO15_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO15_FUN_WPU_S  8
-/** IO_MUX_GPIO15_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO15_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO15_FUN_IE_M  (IO_MUX_GPIO15_FUN_IE_V << IO_MUX_GPIO15_FUN_IE_S)
-#define IO_MUX_GPIO15_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO15_FUN_IE_S  9
-/** IO_MUX_GPIO15_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO15_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO15_FUN_DRV_M  (IO_MUX_GPIO15_FUN_DRV_V << IO_MUX_GPIO15_FUN_DRV_S)
-#define IO_MUX_GPIO15_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO15_FUN_DRV_S  10
-/** IO_MUX_GPIO15_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO15_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO15_MCU_SEL_M  (IO_MUX_GPIO15_MCU_SEL_V << IO_MUX_GPIO15_MCU_SEL_S)
-#define IO_MUX_GPIO15_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO15_MCU_SEL_S  12
-/** IO_MUX_GPIO15_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO15_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO15_FILTER_EN_M  (IO_MUX_GPIO15_FILTER_EN_V << IO_MUX_GPIO15_FILTER_EN_S)
-#define IO_MUX_GPIO15_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO15_FILTER_EN_S  15
-
-/** IO_MUX_gpio16_REG register
- *  iomux control register for gpio16
- */
-#define IO_MUX_GPIO16_REG (DR_REG_IO_MUX_BASE + 0x44)
-/** IO_MUX_GPIO16_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO16_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO16_MCU_OE_M  (IO_MUX_GPIO16_MCU_OE_V << IO_MUX_GPIO16_MCU_OE_S)
-#define IO_MUX_GPIO16_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO16_MCU_OE_S  0
-/** IO_MUX_GPIO16_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO16_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO16_SLP_SEL_M  (IO_MUX_GPIO16_SLP_SEL_V << IO_MUX_GPIO16_SLP_SEL_S)
-#define IO_MUX_GPIO16_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO16_SLP_SEL_S  1
-/** IO_MUX_GPIO16_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO16_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO16_MCU_WPD_M  (IO_MUX_GPIO16_MCU_WPD_V << IO_MUX_GPIO16_MCU_WPD_S)
-#define IO_MUX_GPIO16_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO16_MCU_WPD_S  2
-/** IO_MUX_GPIO16_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO16_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO16_MCU_WPU_M  (IO_MUX_GPIO16_MCU_WPU_V << IO_MUX_GPIO16_MCU_WPU_S)
-#define IO_MUX_GPIO16_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO16_MCU_WPU_S  3
-/** IO_MUX_GPIO16_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO16_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO16_MCU_IE_M  (IO_MUX_GPIO16_MCU_IE_V << IO_MUX_GPIO16_MCU_IE_S)
-#define IO_MUX_GPIO16_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO16_MCU_IE_S  4
-/** IO_MUX_GPIO16_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO16_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO16_MCU_DRV_M  (IO_MUX_GPIO16_MCU_DRV_V << IO_MUX_GPIO16_MCU_DRV_S)
-#define IO_MUX_GPIO16_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO16_MCU_DRV_S  5
-/** IO_MUX_GPIO16_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO16_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO16_FUN_WPD_M  (IO_MUX_GPIO16_FUN_WPD_V << IO_MUX_GPIO16_FUN_WPD_S)
-#define IO_MUX_GPIO16_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO16_FUN_WPD_S  7
-/** IO_MUX_GPIO16_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO16_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO16_FUN_WPU_M  (IO_MUX_GPIO16_FUN_WPU_V << IO_MUX_GPIO16_FUN_WPU_S)
-#define IO_MUX_GPIO16_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO16_FUN_WPU_S  8
-/** IO_MUX_GPIO16_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO16_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO16_FUN_IE_M  (IO_MUX_GPIO16_FUN_IE_V << IO_MUX_GPIO16_FUN_IE_S)
-#define IO_MUX_GPIO16_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO16_FUN_IE_S  9
-/** IO_MUX_GPIO16_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO16_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO16_FUN_DRV_M  (IO_MUX_GPIO16_FUN_DRV_V << IO_MUX_GPIO16_FUN_DRV_S)
-#define IO_MUX_GPIO16_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO16_FUN_DRV_S  10
-/** IO_MUX_GPIO16_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO16_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO16_MCU_SEL_M  (IO_MUX_GPIO16_MCU_SEL_V << IO_MUX_GPIO16_MCU_SEL_S)
-#define IO_MUX_GPIO16_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO16_MCU_SEL_S  12
-/** IO_MUX_GPIO16_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO16_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO16_FILTER_EN_M  (IO_MUX_GPIO16_FILTER_EN_V << IO_MUX_GPIO16_FILTER_EN_S)
-#define IO_MUX_GPIO16_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO16_FILTER_EN_S  15
-
-/** IO_MUX_gpio17_REG register
- *  iomux control register for gpio17
- */
-#define IO_MUX_GPIO17_REG (DR_REG_IO_MUX_BASE + 0x48)
-/** IO_MUX_GPIO17_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO17_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO17_MCU_OE_M  (IO_MUX_GPIO17_MCU_OE_V << IO_MUX_GPIO17_MCU_OE_S)
-#define IO_MUX_GPIO17_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO17_MCU_OE_S  0
-/** IO_MUX_GPIO17_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO17_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO17_SLP_SEL_M  (IO_MUX_GPIO17_SLP_SEL_V << IO_MUX_GPIO17_SLP_SEL_S)
-#define IO_MUX_GPIO17_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO17_SLP_SEL_S  1
-/** IO_MUX_GPIO17_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO17_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO17_MCU_WPD_M  (IO_MUX_GPIO17_MCU_WPD_V << IO_MUX_GPIO17_MCU_WPD_S)
-#define IO_MUX_GPIO17_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO17_MCU_WPD_S  2
-/** IO_MUX_GPIO17_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO17_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO17_MCU_WPU_M  (IO_MUX_GPIO17_MCU_WPU_V << IO_MUX_GPIO17_MCU_WPU_S)
-#define IO_MUX_GPIO17_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO17_MCU_WPU_S  3
-/** IO_MUX_GPIO17_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO17_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO17_MCU_IE_M  (IO_MUX_GPIO17_MCU_IE_V << IO_MUX_GPIO17_MCU_IE_S)
-#define IO_MUX_GPIO17_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO17_MCU_IE_S  4
-/** IO_MUX_GPIO17_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO17_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO17_MCU_DRV_M  (IO_MUX_GPIO17_MCU_DRV_V << IO_MUX_GPIO17_MCU_DRV_S)
-#define IO_MUX_GPIO17_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO17_MCU_DRV_S  5
-/** IO_MUX_GPIO17_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO17_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO17_FUN_WPD_M  (IO_MUX_GPIO17_FUN_WPD_V << IO_MUX_GPIO17_FUN_WPD_S)
-#define IO_MUX_GPIO17_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO17_FUN_WPD_S  7
-/** IO_MUX_GPIO17_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO17_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO17_FUN_WPU_M  (IO_MUX_GPIO17_FUN_WPU_V << IO_MUX_GPIO17_FUN_WPU_S)
-#define IO_MUX_GPIO17_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO17_FUN_WPU_S  8
-/** IO_MUX_GPIO17_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO17_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO17_FUN_IE_M  (IO_MUX_GPIO17_FUN_IE_V << IO_MUX_GPIO17_FUN_IE_S)
-#define IO_MUX_GPIO17_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO17_FUN_IE_S  9
-/** IO_MUX_GPIO17_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO17_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO17_FUN_DRV_M  (IO_MUX_GPIO17_FUN_DRV_V << IO_MUX_GPIO17_FUN_DRV_S)
-#define IO_MUX_GPIO17_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO17_FUN_DRV_S  10
-/** IO_MUX_GPIO17_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO17_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO17_MCU_SEL_M  (IO_MUX_GPIO17_MCU_SEL_V << IO_MUX_GPIO17_MCU_SEL_S)
-#define IO_MUX_GPIO17_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO17_MCU_SEL_S  12
-/** IO_MUX_GPIO17_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO17_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO17_FILTER_EN_M  (IO_MUX_GPIO17_FILTER_EN_V << IO_MUX_GPIO17_FILTER_EN_S)
-#define IO_MUX_GPIO17_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO17_FILTER_EN_S  15
-
-/** IO_MUX_gpio18_REG register
- *  iomux control register for gpio18
- */
-#define IO_MUX_GPIO18_REG (DR_REG_IO_MUX_BASE + 0x4c)
-/** IO_MUX_GPIO18_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO18_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO18_MCU_OE_M  (IO_MUX_GPIO18_MCU_OE_V << IO_MUX_GPIO18_MCU_OE_S)
-#define IO_MUX_GPIO18_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO18_MCU_OE_S  0
-/** IO_MUX_GPIO18_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO18_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO18_SLP_SEL_M  (IO_MUX_GPIO18_SLP_SEL_V << IO_MUX_GPIO18_SLP_SEL_S)
-#define IO_MUX_GPIO18_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO18_SLP_SEL_S  1
-/** IO_MUX_GPIO18_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO18_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO18_MCU_WPD_M  (IO_MUX_GPIO18_MCU_WPD_V << IO_MUX_GPIO18_MCU_WPD_S)
-#define IO_MUX_GPIO18_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO18_MCU_WPD_S  2
-/** IO_MUX_GPIO18_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO18_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO18_MCU_WPU_M  (IO_MUX_GPIO18_MCU_WPU_V << IO_MUX_GPIO18_MCU_WPU_S)
-#define IO_MUX_GPIO18_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO18_MCU_WPU_S  3
-/** IO_MUX_GPIO18_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO18_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO18_MCU_IE_M  (IO_MUX_GPIO18_MCU_IE_V << IO_MUX_GPIO18_MCU_IE_S)
-#define IO_MUX_GPIO18_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO18_MCU_IE_S  4
-/** IO_MUX_GPIO18_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO18_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO18_MCU_DRV_M  (IO_MUX_GPIO18_MCU_DRV_V << IO_MUX_GPIO18_MCU_DRV_S)
-#define IO_MUX_GPIO18_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO18_MCU_DRV_S  5
-/** IO_MUX_GPIO18_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO18_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO18_FUN_WPD_M  (IO_MUX_GPIO18_FUN_WPD_V << IO_MUX_GPIO18_FUN_WPD_S)
-#define IO_MUX_GPIO18_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO18_FUN_WPD_S  7
-/** IO_MUX_GPIO18_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO18_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO18_FUN_WPU_M  (IO_MUX_GPIO18_FUN_WPU_V << IO_MUX_GPIO18_FUN_WPU_S)
-#define IO_MUX_GPIO18_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO18_FUN_WPU_S  8
-/** IO_MUX_GPIO18_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO18_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO18_FUN_IE_M  (IO_MUX_GPIO18_FUN_IE_V << IO_MUX_GPIO18_FUN_IE_S)
-#define IO_MUX_GPIO18_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO18_FUN_IE_S  9
-/** IO_MUX_GPIO18_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO18_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO18_FUN_DRV_M  (IO_MUX_GPIO18_FUN_DRV_V << IO_MUX_GPIO18_FUN_DRV_S)
-#define IO_MUX_GPIO18_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO18_FUN_DRV_S  10
-/** IO_MUX_GPIO18_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO18_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO18_MCU_SEL_M  (IO_MUX_GPIO18_MCU_SEL_V << IO_MUX_GPIO18_MCU_SEL_S)
-#define IO_MUX_GPIO18_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO18_MCU_SEL_S  12
-/** IO_MUX_GPIO18_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO18_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO18_FILTER_EN_M  (IO_MUX_GPIO18_FILTER_EN_V << IO_MUX_GPIO18_FILTER_EN_S)
-#define IO_MUX_GPIO18_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO18_FILTER_EN_S  15
-
-/** IO_MUX_gpio19_REG register
- *  iomux control register for gpio19
- */
-#define IO_MUX_GPIO19_REG (DR_REG_IO_MUX_BASE + 0x50)
-/** IO_MUX_GPIO19_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO19_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO19_MCU_OE_M  (IO_MUX_GPIO19_MCU_OE_V << IO_MUX_GPIO19_MCU_OE_S)
-#define IO_MUX_GPIO19_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO19_MCU_OE_S  0
-/** IO_MUX_GPIO19_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO19_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO19_SLP_SEL_M  (IO_MUX_GPIO19_SLP_SEL_V << IO_MUX_GPIO19_SLP_SEL_S)
-#define IO_MUX_GPIO19_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO19_SLP_SEL_S  1
-/** IO_MUX_GPIO19_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO19_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO19_MCU_WPD_M  (IO_MUX_GPIO19_MCU_WPD_V << IO_MUX_GPIO19_MCU_WPD_S)
-#define IO_MUX_GPIO19_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO19_MCU_WPD_S  2
-/** IO_MUX_GPIO19_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO19_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO19_MCU_WPU_M  (IO_MUX_GPIO19_MCU_WPU_V << IO_MUX_GPIO19_MCU_WPU_S)
-#define IO_MUX_GPIO19_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO19_MCU_WPU_S  3
-/** IO_MUX_GPIO19_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO19_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO19_MCU_IE_M  (IO_MUX_GPIO19_MCU_IE_V << IO_MUX_GPIO19_MCU_IE_S)
-#define IO_MUX_GPIO19_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO19_MCU_IE_S  4
-/** IO_MUX_GPIO19_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO19_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO19_MCU_DRV_M  (IO_MUX_GPIO19_MCU_DRV_V << IO_MUX_GPIO19_MCU_DRV_S)
-#define IO_MUX_GPIO19_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO19_MCU_DRV_S  5
-/** IO_MUX_GPIO19_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO19_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO19_FUN_WPD_M  (IO_MUX_GPIO19_FUN_WPD_V << IO_MUX_GPIO19_FUN_WPD_S)
-#define IO_MUX_GPIO19_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO19_FUN_WPD_S  7
-/** IO_MUX_GPIO19_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO19_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO19_FUN_WPU_M  (IO_MUX_GPIO19_FUN_WPU_V << IO_MUX_GPIO19_FUN_WPU_S)
-#define IO_MUX_GPIO19_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO19_FUN_WPU_S  8
-/** IO_MUX_GPIO19_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO19_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO19_FUN_IE_M  (IO_MUX_GPIO19_FUN_IE_V << IO_MUX_GPIO19_FUN_IE_S)
-#define IO_MUX_GPIO19_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO19_FUN_IE_S  9
-/** IO_MUX_GPIO19_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO19_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO19_FUN_DRV_M  (IO_MUX_GPIO19_FUN_DRV_V << IO_MUX_GPIO19_FUN_DRV_S)
-#define IO_MUX_GPIO19_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO19_FUN_DRV_S  10
-/** IO_MUX_GPIO19_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO19_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO19_MCU_SEL_M  (IO_MUX_GPIO19_MCU_SEL_V << IO_MUX_GPIO19_MCU_SEL_S)
-#define IO_MUX_GPIO19_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO19_MCU_SEL_S  12
-/** IO_MUX_GPIO19_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO19_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO19_FILTER_EN_M  (IO_MUX_GPIO19_FILTER_EN_V << IO_MUX_GPIO19_FILTER_EN_S)
-#define IO_MUX_GPIO19_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO19_FILTER_EN_S  15
-
-/** IO_MUX_gpio20_REG register
- *  iomux control register for gpio20
- */
-#define IO_MUX_GPIO20_REG (DR_REG_IO_MUX_BASE + 0x54)
-/** IO_MUX_GPIO20_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO20_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO20_MCU_OE_M  (IO_MUX_GPIO20_MCU_OE_V << IO_MUX_GPIO20_MCU_OE_S)
-#define IO_MUX_GPIO20_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO20_MCU_OE_S  0
-/** IO_MUX_GPIO20_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO20_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO20_SLP_SEL_M  (IO_MUX_GPIO20_SLP_SEL_V << IO_MUX_GPIO20_SLP_SEL_S)
-#define IO_MUX_GPIO20_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO20_SLP_SEL_S  1
-/** IO_MUX_GPIO20_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO20_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO20_MCU_WPD_M  (IO_MUX_GPIO20_MCU_WPD_V << IO_MUX_GPIO20_MCU_WPD_S)
-#define IO_MUX_GPIO20_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO20_MCU_WPD_S  2
-/** IO_MUX_GPIO20_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO20_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO20_MCU_WPU_M  (IO_MUX_GPIO20_MCU_WPU_V << IO_MUX_GPIO20_MCU_WPU_S)
-#define IO_MUX_GPIO20_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO20_MCU_WPU_S  3
-/** IO_MUX_GPIO20_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO20_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO20_MCU_IE_M  (IO_MUX_GPIO20_MCU_IE_V << IO_MUX_GPIO20_MCU_IE_S)
-#define IO_MUX_GPIO20_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO20_MCU_IE_S  4
-/** IO_MUX_GPIO20_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO20_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO20_MCU_DRV_M  (IO_MUX_GPIO20_MCU_DRV_V << IO_MUX_GPIO20_MCU_DRV_S)
-#define IO_MUX_GPIO20_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO20_MCU_DRV_S  5
-/** IO_MUX_GPIO20_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO20_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO20_FUN_WPD_M  (IO_MUX_GPIO20_FUN_WPD_V << IO_MUX_GPIO20_FUN_WPD_S)
-#define IO_MUX_GPIO20_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO20_FUN_WPD_S  7
-/** IO_MUX_GPIO20_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO20_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO20_FUN_WPU_M  (IO_MUX_GPIO20_FUN_WPU_V << IO_MUX_GPIO20_FUN_WPU_S)
-#define IO_MUX_GPIO20_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO20_FUN_WPU_S  8
-/** IO_MUX_GPIO20_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO20_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO20_FUN_IE_M  (IO_MUX_GPIO20_FUN_IE_V << IO_MUX_GPIO20_FUN_IE_S)
-#define IO_MUX_GPIO20_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO20_FUN_IE_S  9
-/** IO_MUX_GPIO20_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO20_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO20_FUN_DRV_M  (IO_MUX_GPIO20_FUN_DRV_V << IO_MUX_GPIO20_FUN_DRV_S)
-#define IO_MUX_GPIO20_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO20_FUN_DRV_S  10
-/** IO_MUX_GPIO20_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO20_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO20_MCU_SEL_M  (IO_MUX_GPIO20_MCU_SEL_V << IO_MUX_GPIO20_MCU_SEL_S)
-#define IO_MUX_GPIO20_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO20_MCU_SEL_S  12
-/** IO_MUX_GPIO20_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO20_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO20_FILTER_EN_M  (IO_MUX_GPIO20_FILTER_EN_V << IO_MUX_GPIO20_FILTER_EN_S)
-#define IO_MUX_GPIO20_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO20_FILTER_EN_S  15
-
-/** IO_MUX_gpio21_REG register
- *  iomux control register for gpio21
- */
-#define IO_MUX_GPIO21_REG (DR_REG_IO_MUX_BASE + 0x58)
-/** IO_MUX_GPIO21_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO21_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO21_MCU_OE_M  (IO_MUX_GPIO21_MCU_OE_V << IO_MUX_GPIO21_MCU_OE_S)
-#define IO_MUX_GPIO21_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO21_MCU_OE_S  0
-/** IO_MUX_GPIO21_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO21_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO21_SLP_SEL_M  (IO_MUX_GPIO21_SLP_SEL_V << IO_MUX_GPIO21_SLP_SEL_S)
-#define IO_MUX_GPIO21_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO21_SLP_SEL_S  1
-/** IO_MUX_GPIO21_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO21_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO21_MCU_WPD_M  (IO_MUX_GPIO21_MCU_WPD_V << IO_MUX_GPIO21_MCU_WPD_S)
-#define IO_MUX_GPIO21_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO21_MCU_WPD_S  2
-/** IO_MUX_GPIO21_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO21_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO21_MCU_WPU_M  (IO_MUX_GPIO21_MCU_WPU_V << IO_MUX_GPIO21_MCU_WPU_S)
-#define IO_MUX_GPIO21_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO21_MCU_WPU_S  3
-/** IO_MUX_GPIO21_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO21_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO21_MCU_IE_M  (IO_MUX_GPIO21_MCU_IE_V << IO_MUX_GPIO21_MCU_IE_S)
-#define IO_MUX_GPIO21_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO21_MCU_IE_S  4
-/** IO_MUX_GPIO21_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO21_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO21_MCU_DRV_M  (IO_MUX_GPIO21_MCU_DRV_V << IO_MUX_GPIO21_MCU_DRV_S)
-#define IO_MUX_GPIO21_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO21_MCU_DRV_S  5
-/** IO_MUX_GPIO21_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO21_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO21_FUN_WPD_M  (IO_MUX_GPIO21_FUN_WPD_V << IO_MUX_GPIO21_FUN_WPD_S)
-#define IO_MUX_GPIO21_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO21_FUN_WPD_S  7
-/** IO_MUX_GPIO21_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO21_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO21_FUN_WPU_M  (IO_MUX_GPIO21_FUN_WPU_V << IO_MUX_GPIO21_FUN_WPU_S)
-#define IO_MUX_GPIO21_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO21_FUN_WPU_S  8
-/** IO_MUX_GPIO21_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO21_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO21_FUN_IE_M  (IO_MUX_GPIO21_FUN_IE_V << IO_MUX_GPIO21_FUN_IE_S)
-#define IO_MUX_GPIO21_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO21_FUN_IE_S  9
-/** IO_MUX_GPIO21_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO21_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO21_FUN_DRV_M  (IO_MUX_GPIO21_FUN_DRV_V << IO_MUX_GPIO21_FUN_DRV_S)
-#define IO_MUX_GPIO21_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO21_FUN_DRV_S  10
-/** IO_MUX_GPIO21_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO21_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO21_MCU_SEL_M  (IO_MUX_GPIO21_MCU_SEL_V << IO_MUX_GPIO21_MCU_SEL_S)
-#define IO_MUX_GPIO21_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO21_MCU_SEL_S  12
-/** IO_MUX_GPIO21_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO21_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO21_FILTER_EN_M  (IO_MUX_GPIO21_FILTER_EN_V << IO_MUX_GPIO21_FILTER_EN_S)
-#define IO_MUX_GPIO21_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO21_FILTER_EN_S  15
-
-/** IO_MUX_gpio22_REG register
- *  iomux control register for gpio22
- */
-#define IO_MUX_GPIO22_REG (DR_REG_IO_MUX_BASE + 0x5c)
-/** IO_MUX_GPIO22_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO22_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO22_MCU_OE_M  (IO_MUX_GPIO22_MCU_OE_V << IO_MUX_GPIO22_MCU_OE_S)
-#define IO_MUX_GPIO22_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO22_MCU_OE_S  0
-/** IO_MUX_GPIO22_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO22_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO22_SLP_SEL_M  (IO_MUX_GPIO22_SLP_SEL_V << IO_MUX_GPIO22_SLP_SEL_S)
-#define IO_MUX_GPIO22_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO22_SLP_SEL_S  1
-/** IO_MUX_GPIO22_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO22_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO22_MCU_WPD_M  (IO_MUX_GPIO22_MCU_WPD_V << IO_MUX_GPIO22_MCU_WPD_S)
-#define IO_MUX_GPIO22_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO22_MCU_WPD_S  2
-/** IO_MUX_GPIO22_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO22_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO22_MCU_WPU_M  (IO_MUX_GPIO22_MCU_WPU_V << IO_MUX_GPIO22_MCU_WPU_S)
-#define IO_MUX_GPIO22_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO22_MCU_WPU_S  3
-/** IO_MUX_GPIO22_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO22_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO22_MCU_IE_M  (IO_MUX_GPIO22_MCU_IE_V << IO_MUX_GPIO22_MCU_IE_S)
-#define IO_MUX_GPIO22_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO22_MCU_IE_S  4
-/** IO_MUX_GPIO22_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO22_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO22_MCU_DRV_M  (IO_MUX_GPIO22_MCU_DRV_V << IO_MUX_GPIO22_MCU_DRV_S)
-#define IO_MUX_GPIO22_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO22_MCU_DRV_S  5
-/** IO_MUX_GPIO22_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO22_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO22_FUN_WPD_M  (IO_MUX_GPIO22_FUN_WPD_V << IO_MUX_GPIO22_FUN_WPD_S)
-#define IO_MUX_GPIO22_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO22_FUN_WPD_S  7
-/** IO_MUX_GPIO22_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO22_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO22_FUN_WPU_M  (IO_MUX_GPIO22_FUN_WPU_V << IO_MUX_GPIO22_FUN_WPU_S)
-#define IO_MUX_GPIO22_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO22_FUN_WPU_S  8
-/** IO_MUX_GPIO22_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO22_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO22_FUN_IE_M  (IO_MUX_GPIO22_FUN_IE_V << IO_MUX_GPIO22_FUN_IE_S)
-#define IO_MUX_GPIO22_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO22_FUN_IE_S  9
-/** IO_MUX_GPIO22_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO22_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO22_FUN_DRV_M  (IO_MUX_GPIO22_FUN_DRV_V << IO_MUX_GPIO22_FUN_DRV_S)
-#define IO_MUX_GPIO22_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO22_FUN_DRV_S  10
-/** IO_MUX_GPIO22_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO22_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO22_MCU_SEL_M  (IO_MUX_GPIO22_MCU_SEL_V << IO_MUX_GPIO22_MCU_SEL_S)
-#define IO_MUX_GPIO22_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO22_MCU_SEL_S  12
-/** IO_MUX_GPIO22_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO22_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO22_FILTER_EN_M  (IO_MUX_GPIO22_FILTER_EN_V << IO_MUX_GPIO22_FILTER_EN_S)
-#define IO_MUX_GPIO22_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO22_FILTER_EN_S  15
-
-/** IO_MUX_gpio23_REG register
- *  iomux control register for gpio23
- */
-#define IO_MUX_GPIO23_REG (DR_REG_IO_MUX_BASE + 0x60)
-/** IO_MUX_GPIO23_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO23_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO23_MCU_OE_M  (IO_MUX_GPIO23_MCU_OE_V << IO_MUX_GPIO23_MCU_OE_S)
-#define IO_MUX_GPIO23_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO23_MCU_OE_S  0
-/** IO_MUX_GPIO23_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO23_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO23_SLP_SEL_M  (IO_MUX_GPIO23_SLP_SEL_V << IO_MUX_GPIO23_SLP_SEL_S)
-#define IO_MUX_GPIO23_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO23_SLP_SEL_S  1
-/** IO_MUX_GPIO23_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO23_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO23_MCU_WPD_M  (IO_MUX_GPIO23_MCU_WPD_V << IO_MUX_GPIO23_MCU_WPD_S)
-#define IO_MUX_GPIO23_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO23_MCU_WPD_S  2
-/** IO_MUX_GPIO23_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO23_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO23_MCU_WPU_M  (IO_MUX_GPIO23_MCU_WPU_V << IO_MUX_GPIO23_MCU_WPU_S)
-#define IO_MUX_GPIO23_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO23_MCU_WPU_S  3
-/** IO_MUX_GPIO23_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO23_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO23_MCU_IE_M  (IO_MUX_GPIO23_MCU_IE_V << IO_MUX_GPIO23_MCU_IE_S)
-#define IO_MUX_GPIO23_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO23_MCU_IE_S  4
-/** IO_MUX_GPIO23_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO23_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO23_MCU_DRV_M  (IO_MUX_GPIO23_MCU_DRV_V << IO_MUX_GPIO23_MCU_DRV_S)
-#define IO_MUX_GPIO23_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO23_MCU_DRV_S  5
-/** IO_MUX_GPIO23_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO23_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO23_FUN_WPD_M  (IO_MUX_GPIO23_FUN_WPD_V << IO_MUX_GPIO23_FUN_WPD_S)
-#define IO_MUX_GPIO23_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO23_FUN_WPD_S  7
-/** IO_MUX_GPIO23_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO23_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO23_FUN_WPU_M  (IO_MUX_GPIO23_FUN_WPU_V << IO_MUX_GPIO23_FUN_WPU_S)
-#define IO_MUX_GPIO23_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO23_FUN_WPU_S  8
-/** IO_MUX_GPIO23_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO23_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO23_FUN_IE_M  (IO_MUX_GPIO23_FUN_IE_V << IO_MUX_GPIO23_FUN_IE_S)
-#define IO_MUX_GPIO23_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO23_FUN_IE_S  9
-/** IO_MUX_GPIO23_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO23_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO23_FUN_DRV_M  (IO_MUX_GPIO23_FUN_DRV_V << IO_MUX_GPIO23_FUN_DRV_S)
-#define IO_MUX_GPIO23_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO23_FUN_DRV_S  10
-/** IO_MUX_GPIO23_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO23_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO23_MCU_SEL_M  (IO_MUX_GPIO23_MCU_SEL_V << IO_MUX_GPIO23_MCU_SEL_S)
-#define IO_MUX_GPIO23_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO23_MCU_SEL_S  12
-/** IO_MUX_GPIO23_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO23_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO23_FILTER_EN_M  (IO_MUX_GPIO23_FILTER_EN_V << IO_MUX_GPIO23_FILTER_EN_S)
-#define IO_MUX_GPIO23_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO23_FILTER_EN_S  15
-
-/** IO_MUX_gpio24_REG register
- *  iomux control register for gpio24
- */
-#define IO_MUX_GPIO24_REG (DR_REG_IO_MUX_BASE + 0x64)
-/** IO_MUX_GPIO24_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO24_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO24_MCU_OE_M  (IO_MUX_GPIO24_MCU_OE_V << IO_MUX_GPIO24_MCU_OE_S)
-#define IO_MUX_GPIO24_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO24_MCU_OE_S  0
-/** IO_MUX_GPIO24_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO24_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO24_SLP_SEL_M  (IO_MUX_GPIO24_SLP_SEL_V << IO_MUX_GPIO24_SLP_SEL_S)
-#define IO_MUX_GPIO24_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO24_SLP_SEL_S  1
-/** IO_MUX_GPIO24_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO24_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO24_MCU_WPD_M  (IO_MUX_GPIO24_MCU_WPD_V << IO_MUX_GPIO24_MCU_WPD_S)
-#define IO_MUX_GPIO24_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO24_MCU_WPD_S  2
-/** IO_MUX_GPIO24_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO24_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO24_MCU_WPU_M  (IO_MUX_GPIO24_MCU_WPU_V << IO_MUX_GPIO24_MCU_WPU_S)
-#define IO_MUX_GPIO24_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO24_MCU_WPU_S  3
-/** IO_MUX_GPIO24_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO24_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO24_MCU_IE_M  (IO_MUX_GPIO24_MCU_IE_V << IO_MUX_GPIO24_MCU_IE_S)
-#define IO_MUX_GPIO24_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO24_MCU_IE_S  4
-/** IO_MUX_GPIO24_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO24_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO24_MCU_DRV_M  (IO_MUX_GPIO24_MCU_DRV_V << IO_MUX_GPIO24_MCU_DRV_S)
-#define IO_MUX_GPIO24_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO24_MCU_DRV_S  5
-/** IO_MUX_GPIO24_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO24_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO24_FUN_WPD_M  (IO_MUX_GPIO24_FUN_WPD_V << IO_MUX_GPIO24_FUN_WPD_S)
-#define IO_MUX_GPIO24_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO24_FUN_WPD_S  7
-/** IO_MUX_GPIO24_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO24_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO24_FUN_WPU_M  (IO_MUX_GPIO24_FUN_WPU_V << IO_MUX_GPIO24_FUN_WPU_S)
-#define IO_MUX_GPIO24_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO24_FUN_WPU_S  8
-/** IO_MUX_GPIO24_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO24_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO24_FUN_IE_M  (IO_MUX_GPIO24_FUN_IE_V << IO_MUX_GPIO24_FUN_IE_S)
-#define IO_MUX_GPIO24_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO24_FUN_IE_S  9
-/** IO_MUX_GPIO24_FUN_DRV : R/W; bitpos: [11:10]; default: 3;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO24_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO24_FUN_DRV_M  (IO_MUX_GPIO24_FUN_DRV_V << IO_MUX_GPIO24_FUN_DRV_S)
-#define IO_MUX_GPIO24_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO24_FUN_DRV_S  10
-/** IO_MUX_GPIO24_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO24_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO24_MCU_SEL_M  (IO_MUX_GPIO24_MCU_SEL_V << IO_MUX_GPIO24_MCU_SEL_S)
-#define IO_MUX_GPIO24_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO24_MCU_SEL_S  12
-/** IO_MUX_GPIO24_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO24_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO24_FILTER_EN_M  (IO_MUX_GPIO24_FILTER_EN_V << IO_MUX_GPIO24_FILTER_EN_S)
-#define IO_MUX_GPIO24_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO24_FILTER_EN_S  15
-
-/** IO_MUX_gpio25_REG register
- *  iomux control register for gpio25
- */
-#define IO_MUX_GPIO25_REG (DR_REG_IO_MUX_BASE + 0x68)
-/** IO_MUX_GPIO25_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO25_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO25_MCU_OE_M  (IO_MUX_GPIO25_MCU_OE_V << IO_MUX_GPIO25_MCU_OE_S)
-#define IO_MUX_GPIO25_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO25_MCU_OE_S  0
-/** IO_MUX_GPIO25_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO25_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO25_SLP_SEL_M  (IO_MUX_GPIO25_SLP_SEL_V << IO_MUX_GPIO25_SLP_SEL_S)
-#define IO_MUX_GPIO25_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO25_SLP_SEL_S  1
-/** IO_MUX_GPIO25_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO25_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO25_MCU_WPD_M  (IO_MUX_GPIO25_MCU_WPD_V << IO_MUX_GPIO25_MCU_WPD_S)
-#define IO_MUX_GPIO25_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO25_MCU_WPD_S  2
-/** IO_MUX_GPIO25_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO25_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO25_MCU_WPU_M  (IO_MUX_GPIO25_MCU_WPU_V << IO_MUX_GPIO25_MCU_WPU_S)
-#define IO_MUX_GPIO25_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO25_MCU_WPU_S  3
-/** IO_MUX_GPIO25_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO25_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO25_MCU_IE_M  (IO_MUX_GPIO25_MCU_IE_V << IO_MUX_GPIO25_MCU_IE_S)
-#define IO_MUX_GPIO25_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO25_MCU_IE_S  4
-/** IO_MUX_GPIO25_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO25_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO25_MCU_DRV_M  (IO_MUX_GPIO25_MCU_DRV_V << IO_MUX_GPIO25_MCU_DRV_S)
-#define IO_MUX_GPIO25_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO25_MCU_DRV_S  5
-/** IO_MUX_GPIO25_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO25_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO25_FUN_WPD_M  (IO_MUX_GPIO25_FUN_WPD_V << IO_MUX_GPIO25_FUN_WPD_S)
-#define IO_MUX_GPIO25_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO25_FUN_WPD_S  7
-/** IO_MUX_GPIO25_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO25_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO25_FUN_WPU_M  (IO_MUX_GPIO25_FUN_WPU_V << IO_MUX_GPIO25_FUN_WPU_S)
-#define IO_MUX_GPIO25_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO25_FUN_WPU_S  8
-/** IO_MUX_GPIO25_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO25_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO25_FUN_IE_M  (IO_MUX_GPIO25_FUN_IE_V << IO_MUX_GPIO25_FUN_IE_S)
-#define IO_MUX_GPIO25_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO25_FUN_IE_S  9
-/** IO_MUX_GPIO25_FUN_DRV : R/W; bitpos: [11:10]; default: 3;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO25_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO25_FUN_DRV_M  (IO_MUX_GPIO25_FUN_DRV_V << IO_MUX_GPIO25_FUN_DRV_S)
-#define IO_MUX_GPIO25_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO25_FUN_DRV_S  10
-/** IO_MUX_GPIO25_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO25_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO25_MCU_SEL_M  (IO_MUX_GPIO25_MCU_SEL_V << IO_MUX_GPIO25_MCU_SEL_S)
-#define IO_MUX_GPIO25_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO25_MCU_SEL_S  12
-/** IO_MUX_GPIO25_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO25_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO25_FILTER_EN_M  (IO_MUX_GPIO25_FILTER_EN_V << IO_MUX_GPIO25_FILTER_EN_S)
-#define IO_MUX_GPIO25_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO25_FILTER_EN_S  15
-
-/** IO_MUX_gpio26_REG register
- *  iomux control register for gpio26
- */
-#define IO_MUX_GPIO26_REG (DR_REG_IO_MUX_BASE + 0x6c)
-/** IO_MUX_GPIO26_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO26_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO26_MCU_OE_M  (IO_MUX_GPIO26_MCU_OE_V << IO_MUX_GPIO26_MCU_OE_S)
-#define IO_MUX_GPIO26_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO26_MCU_OE_S  0
-/** IO_MUX_GPIO26_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO26_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO26_SLP_SEL_M  (IO_MUX_GPIO26_SLP_SEL_V << IO_MUX_GPIO26_SLP_SEL_S)
-#define IO_MUX_GPIO26_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO26_SLP_SEL_S  1
-/** IO_MUX_GPIO26_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO26_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO26_MCU_WPD_M  (IO_MUX_GPIO26_MCU_WPD_V << IO_MUX_GPIO26_MCU_WPD_S)
-#define IO_MUX_GPIO26_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO26_MCU_WPD_S  2
-/** IO_MUX_GPIO26_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO26_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO26_MCU_WPU_M  (IO_MUX_GPIO26_MCU_WPU_V << IO_MUX_GPIO26_MCU_WPU_S)
-#define IO_MUX_GPIO26_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO26_MCU_WPU_S  3
-/** IO_MUX_GPIO26_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO26_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO26_MCU_IE_M  (IO_MUX_GPIO26_MCU_IE_V << IO_MUX_GPIO26_MCU_IE_S)
-#define IO_MUX_GPIO26_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO26_MCU_IE_S  4
-/** IO_MUX_GPIO26_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO26_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO26_MCU_DRV_M  (IO_MUX_GPIO26_MCU_DRV_V << IO_MUX_GPIO26_MCU_DRV_S)
-#define IO_MUX_GPIO26_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO26_MCU_DRV_S  5
-/** IO_MUX_GPIO26_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO26_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO26_FUN_WPD_M  (IO_MUX_GPIO26_FUN_WPD_V << IO_MUX_GPIO26_FUN_WPD_S)
-#define IO_MUX_GPIO26_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO26_FUN_WPD_S  7
-/** IO_MUX_GPIO26_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO26_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO26_FUN_WPU_M  (IO_MUX_GPIO26_FUN_WPU_V << IO_MUX_GPIO26_FUN_WPU_S)
-#define IO_MUX_GPIO26_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO26_FUN_WPU_S  8
-/** IO_MUX_GPIO26_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO26_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO26_FUN_IE_M  (IO_MUX_GPIO26_FUN_IE_V << IO_MUX_GPIO26_FUN_IE_S)
-#define IO_MUX_GPIO26_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO26_FUN_IE_S  9
-/** IO_MUX_GPIO26_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO26_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO26_FUN_DRV_M  (IO_MUX_GPIO26_FUN_DRV_V << IO_MUX_GPIO26_FUN_DRV_S)
-#define IO_MUX_GPIO26_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO26_FUN_DRV_S  10
-/** IO_MUX_GPIO26_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO26_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO26_MCU_SEL_M  (IO_MUX_GPIO26_MCU_SEL_V << IO_MUX_GPIO26_MCU_SEL_S)
-#define IO_MUX_GPIO26_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO26_MCU_SEL_S  12
-/** IO_MUX_GPIO26_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO26_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO26_FILTER_EN_M  (IO_MUX_GPIO26_FILTER_EN_V << IO_MUX_GPIO26_FILTER_EN_S)
-#define IO_MUX_GPIO26_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO26_FILTER_EN_S  15
-
-/** IO_MUX_gpio27_REG register
- *  iomux control register for gpio27
- */
-#define IO_MUX_GPIO27_REG (DR_REG_IO_MUX_BASE + 0x70)
-/** IO_MUX_GPIO27_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO27_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO27_MCU_OE_M  (IO_MUX_GPIO27_MCU_OE_V << IO_MUX_GPIO27_MCU_OE_S)
-#define IO_MUX_GPIO27_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO27_MCU_OE_S  0
-/** IO_MUX_GPIO27_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO27_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO27_SLP_SEL_M  (IO_MUX_GPIO27_SLP_SEL_V << IO_MUX_GPIO27_SLP_SEL_S)
-#define IO_MUX_GPIO27_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO27_SLP_SEL_S  1
-/** IO_MUX_GPIO27_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO27_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO27_MCU_WPD_M  (IO_MUX_GPIO27_MCU_WPD_V << IO_MUX_GPIO27_MCU_WPD_S)
-#define IO_MUX_GPIO27_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO27_MCU_WPD_S  2
-/** IO_MUX_GPIO27_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO27_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO27_MCU_WPU_M  (IO_MUX_GPIO27_MCU_WPU_V << IO_MUX_GPIO27_MCU_WPU_S)
-#define IO_MUX_GPIO27_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO27_MCU_WPU_S  3
-/** IO_MUX_GPIO27_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO27_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO27_MCU_IE_M  (IO_MUX_GPIO27_MCU_IE_V << IO_MUX_GPIO27_MCU_IE_S)
-#define IO_MUX_GPIO27_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO27_MCU_IE_S  4
-/** IO_MUX_GPIO27_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO27_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO27_MCU_DRV_M  (IO_MUX_GPIO27_MCU_DRV_V << IO_MUX_GPIO27_MCU_DRV_S)
-#define IO_MUX_GPIO27_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO27_MCU_DRV_S  5
-/** IO_MUX_GPIO27_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO27_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO27_FUN_WPD_M  (IO_MUX_GPIO27_FUN_WPD_V << IO_MUX_GPIO27_FUN_WPD_S)
-#define IO_MUX_GPIO27_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO27_FUN_WPD_S  7
-/** IO_MUX_GPIO27_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO27_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO27_FUN_WPU_M  (IO_MUX_GPIO27_FUN_WPU_V << IO_MUX_GPIO27_FUN_WPU_S)
-#define IO_MUX_GPIO27_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO27_FUN_WPU_S  8
-/** IO_MUX_GPIO27_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO27_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO27_FUN_IE_M  (IO_MUX_GPIO27_FUN_IE_V << IO_MUX_GPIO27_FUN_IE_S)
-#define IO_MUX_GPIO27_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO27_FUN_IE_S  9
-/** IO_MUX_GPIO27_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO27_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO27_FUN_DRV_M  (IO_MUX_GPIO27_FUN_DRV_V << IO_MUX_GPIO27_FUN_DRV_S)
-#define IO_MUX_GPIO27_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO27_FUN_DRV_S  10
-/** IO_MUX_GPIO27_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO27_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO27_MCU_SEL_M  (IO_MUX_GPIO27_MCU_SEL_V << IO_MUX_GPIO27_MCU_SEL_S)
-#define IO_MUX_GPIO27_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO27_MCU_SEL_S  12
-/** IO_MUX_GPIO27_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO27_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO27_FILTER_EN_M  (IO_MUX_GPIO27_FILTER_EN_V << IO_MUX_GPIO27_FILTER_EN_S)
-#define IO_MUX_GPIO27_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO27_FILTER_EN_S  15
-
-/** IO_MUX_gpio28_REG register
- *  iomux control register for gpio28
- */
-#define IO_MUX_GPIO28_REG (DR_REG_IO_MUX_BASE + 0x74)
-/** IO_MUX_GPIO28_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO28_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO28_MCU_OE_M  (IO_MUX_GPIO28_MCU_OE_V << IO_MUX_GPIO28_MCU_OE_S)
-#define IO_MUX_GPIO28_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO28_MCU_OE_S  0
-/** IO_MUX_GPIO28_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO28_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO28_SLP_SEL_M  (IO_MUX_GPIO28_SLP_SEL_V << IO_MUX_GPIO28_SLP_SEL_S)
-#define IO_MUX_GPIO28_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO28_SLP_SEL_S  1
-/** IO_MUX_GPIO28_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO28_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO28_MCU_WPD_M  (IO_MUX_GPIO28_MCU_WPD_V << IO_MUX_GPIO28_MCU_WPD_S)
-#define IO_MUX_GPIO28_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO28_MCU_WPD_S  2
-/** IO_MUX_GPIO28_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO28_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO28_MCU_WPU_M  (IO_MUX_GPIO28_MCU_WPU_V << IO_MUX_GPIO28_MCU_WPU_S)
-#define IO_MUX_GPIO28_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO28_MCU_WPU_S  3
-/** IO_MUX_GPIO28_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO28_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO28_MCU_IE_M  (IO_MUX_GPIO28_MCU_IE_V << IO_MUX_GPIO28_MCU_IE_S)
-#define IO_MUX_GPIO28_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO28_MCU_IE_S  4
-/** IO_MUX_GPIO28_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO28_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO28_MCU_DRV_M  (IO_MUX_GPIO28_MCU_DRV_V << IO_MUX_GPIO28_MCU_DRV_S)
-#define IO_MUX_GPIO28_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO28_MCU_DRV_S  5
-/** IO_MUX_GPIO28_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO28_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO28_FUN_WPD_M  (IO_MUX_GPIO28_FUN_WPD_V << IO_MUX_GPIO28_FUN_WPD_S)
-#define IO_MUX_GPIO28_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO28_FUN_WPD_S  7
-/** IO_MUX_GPIO28_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO28_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO28_FUN_WPU_M  (IO_MUX_GPIO28_FUN_WPU_V << IO_MUX_GPIO28_FUN_WPU_S)
-#define IO_MUX_GPIO28_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO28_FUN_WPU_S  8
-/** IO_MUX_GPIO28_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO28_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO28_FUN_IE_M  (IO_MUX_GPIO28_FUN_IE_V << IO_MUX_GPIO28_FUN_IE_S)
-#define IO_MUX_GPIO28_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO28_FUN_IE_S  9
-/** IO_MUX_GPIO28_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO28_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO28_FUN_DRV_M  (IO_MUX_GPIO28_FUN_DRV_V << IO_MUX_GPIO28_FUN_DRV_S)
-#define IO_MUX_GPIO28_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO28_FUN_DRV_S  10
-/** IO_MUX_GPIO28_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO28_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO28_MCU_SEL_M  (IO_MUX_GPIO28_MCU_SEL_V << IO_MUX_GPIO28_MCU_SEL_S)
-#define IO_MUX_GPIO28_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO28_MCU_SEL_S  12
-/** IO_MUX_GPIO28_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO28_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO28_FILTER_EN_M  (IO_MUX_GPIO28_FILTER_EN_V << IO_MUX_GPIO28_FILTER_EN_S)
-#define IO_MUX_GPIO28_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO28_FILTER_EN_S  15
-
-/** IO_MUX_gpio29_REG register
- *  iomux control register for gpio29
- */
-#define IO_MUX_GPIO29_REG (DR_REG_IO_MUX_BASE + 0x78)
-/** IO_MUX_GPIO29_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO29_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO29_MCU_OE_M  (IO_MUX_GPIO29_MCU_OE_V << IO_MUX_GPIO29_MCU_OE_S)
-#define IO_MUX_GPIO29_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO29_MCU_OE_S  0
-/** IO_MUX_GPIO29_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO29_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO29_SLP_SEL_M  (IO_MUX_GPIO29_SLP_SEL_V << IO_MUX_GPIO29_SLP_SEL_S)
-#define IO_MUX_GPIO29_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO29_SLP_SEL_S  1
-/** IO_MUX_GPIO29_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO29_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO29_MCU_WPD_M  (IO_MUX_GPIO29_MCU_WPD_V << IO_MUX_GPIO29_MCU_WPD_S)
-#define IO_MUX_GPIO29_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO29_MCU_WPD_S  2
-/** IO_MUX_GPIO29_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO29_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO29_MCU_WPU_M  (IO_MUX_GPIO29_MCU_WPU_V << IO_MUX_GPIO29_MCU_WPU_S)
-#define IO_MUX_GPIO29_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO29_MCU_WPU_S  3
-/** IO_MUX_GPIO29_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO29_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO29_MCU_IE_M  (IO_MUX_GPIO29_MCU_IE_V << IO_MUX_GPIO29_MCU_IE_S)
-#define IO_MUX_GPIO29_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO29_MCU_IE_S  4
-/** IO_MUX_GPIO29_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO29_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO29_MCU_DRV_M  (IO_MUX_GPIO29_MCU_DRV_V << IO_MUX_GPIO29_MCU_DRV_S)
-#define IO_MUX_GPIO29_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO29_MCU_DRV_S  5
-/** IO_MUX_GPIO29_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO29_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO29_FUN_WPD_M  (IO_MUX_GPIO29_FUN_WPD_V << IO_MUX_GPIO29_FUN_WPD_S)
-#define IO_MUX_GPIO29_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO29_FUN_WPD_S  7
-/** IO_MUX_GPIO29_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO29_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO29_FUN_WPU_M  (IO_MUX_GPIO29_FUN_WPU_V << IO_MUX_GPIO29_FUN_WPU_S)
-#define IO_MUX_GPIO29_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO29_FUN_WPU_S  8
-/** IO_MUX_GPIO29_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO29_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO29_FUN_IE_M  (IO_MUX_GPIO29_FUN_IE_V << IO_MUX_GPIO29_FUN_IE_S)
-#define IO_MUX_GPIO29_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO29_FUN_IE_S  9
-/** IO_MUX_GPIO29_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO29_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO29_FUN_DRV_M  (IO_MUX_GPIO29_FUN_DRV_V << IO_MUX_GPIO29_FUN_DRV_S)
-#define IO_MUX_GPIO29_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO29_FUN_DRV_S  10
-/** IO_MUX_GPIO29_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO29_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO29_MCU_SEL_M  (IO_MUX_GPIO29_MCU_SEL_V << IO_MUX_GPIO29_MCU_SEL_S)
-#define IO_MUX_GPIO29_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO29_MCU_SEL_S  12
-/** IO_MUX_GPIO29_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO29_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO29_FILTER_EN_M  (IO_MUX_GPIO29_FILTER_EN_V << IO_MUX_GPIO29_FILTER_EN_S)
-#define IO_MUX_GPIO29_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO29_FILTER_EN_S  15
-
-/** IO_MUX_gpio30_REG register
- *  iomux control register for gpio30
- */
-#define IO_MUX_GPIO30_REG (DR_REG_IO_MUX_BASE + 0x7c)
-/** IO_MUX_GPIO30_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO30_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO30_MCU_OE_M  (IO_MUX_GPIO30_MCU_OE_V << IO_MUX_GPIO30_MCU_OE_S)
-#define IO_MUX_GPIO30_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO30_MCU_OE_S  0
-/** IO_MUX_GPIO30_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO30_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO30_SLP_SEL_M  (IO_MUX_GPIO30_SLP_SEL_V << IO_MUX_GPIO30_SLP_SEL_S)
-#define IO_MUX_GPIO30_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO30_SLP_SEL_S  1
-/** IO_MUX_GPIO30_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO30_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO30_MCU_WPD_M  (IO_MUX_GPIO30_MCU_WPD_V << IO_MUX_GPIO30_MCU_WPD_S)
-#define IO_MUX_GPIO30_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO30_MCU_WPD_S  2
-/** IO_MUX_GPIO30_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO30_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO30_MCU_WPU_M  (IO_MUX_GPIO30_MCU_WPU_V << IO_MUX_GPIO30_MCU_WPU_S)
-#define IO_MUX_GPIO30_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO30_MCU_WPU_S  3
-/** IO_MUX_GPIO30_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO30_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO30_MCU_IE_M  (IO_MUX_GPIO30_MCU_IE_V << IO_MUX_GPIO30_MCU_IE_S)
-#define IO_MUX_GPIO30_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO30_MCU_IE_S  4
-/** IO_MUX_GPIO30_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO30_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO30_MCU_DRV_M  (IO_MUX_GPIO30_MCU_DRV_V << IO_MUX_GPIO30_MCU_DRV_S)
-#define IO_MUX_GPIO30_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO30_MCU_DRV_S  5
-/** IO_MUX_GPIO30_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO30_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO30_FUN_WPD_M  (IO_MUX_GPIO30_FUN_WPD_V << IO_MUX_GPIO30_FUN_WPD_S)
-#define IO_MUX_GPIO30_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO30_FUN_WPD_S  7
-/** IO_MUX_GPIO30_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO30_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO30_FUN_WPU_M  (IO_MUX_GPIO30_FUN_WPU_V << IO_MUX_GPIO30_FUN_WPU_S)
-#define IO_MUX_GPIO30_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO30_FUN_WPU_S  8
-/** IO_MUX_GPIO30_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO30_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO30_FUN_IE_M  (IO_MUX_GPIO30_FUN_IE_V << IO_MUX_GPIO30_FUN_IE_S)
-#define IO_MUX_GPIO30_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO30_FUN_IE_S  9
-/** IO_MUX_GPIO30_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO30_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO30_FUN_DRV_M  (IO_MUX_GPIO30_FUN_DRV_V << IO_MUX_GPIO30_FUN_DRV_S)
-#define IO_MUX_GPIO30_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO30_FUN_DRV_S  10
-/** IO_MUX_GPIO30_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO30_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO30_MCU_SEL_M  (IO_MUX_GPIO30_MCU_SEL_V << IO_MUX_GPIO30_MCU_SEL_S)
-#define IO_MUX_GPIO30_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO30_MCU_SEL_S  12
-/** IO_MUX_GPIO30_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO30_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO30_FILTER_EN_M  (IO_MUX_GPIO30_FILTER_EN_V << IO_MUX_GPIO30_FILTER_EN_S)
-#define IO_MUX_GPIO30_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO30_FILTER_EN_S  15
-
-/** IO_MUX_gpio31_REG register
- *  iomux control register for gpio31
- */
-#define IO_MUX_GPIO31_REG (DR_REG_IO_MUX_BASE + 0x80)
-/** IO_MUX_GPIO31_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO31_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO31_MCU_OE_M  (IO_MUX_GPIO31_MCU_OE_V << IO_MUX_GPIO31_MCU_OE_S)
-#define IO_MUX_GPIO31_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO31_MCU_OE_S  0
-/** IO_MUX_GPIO31_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO31_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO31_SLP_SEL_M  (IO_MUX_GPIO31_SLP_SEL_V << IO_MUX_GPIO31_SLP_SEL_S)
-#define IO_MUX_GPIO31_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO31_SLP_SEL_S  1
-/** IO_MUX_GPIO31_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO31_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO31_MCU_WPD_M  (IO_MUX_GPIO31_MCU_WPD_V << IO_MUX_GPIO31_MCU_WPD_S)
-#define IO_MUX_GPIO31_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO31_MCU_WPD_S  2
-/** IO_MUX_GPIO31_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO31_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO31_MCU_WPU_M  (IO_MUX_GPIO31_MCU_WPU_V << IO_MUX_GPIO31_MCU_WPU_S)
-#define IO_MUX_GPIO31_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO31_MCU_WPU_S  3
-/** IO_MUX_GPIO31_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO31_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO31_MCU_IE_M  (IO_MUX_GPIO31_MCU_IE_V << IO_MUX_GPIO31_MCU_IE_S)
-#define IO_MUX_GPIO31_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO31_MCU_IE_S  4
-/** IO_MUX_GPIO31_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO31_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO31_MCU_DRV_M  (IO_MUX_GPIO31_MCU_DRV_V << IO_MUX_GPIO31_MCU_DRV_S)
-#define IO_MUX_GPIO31_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO31_MCU_DRV_S  5
-/** IO_MUX_GPIO31_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO31_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO31_FUN_WPD_M  (IO_MUX_GPIO31_FUN_WPD_V << IO_MUX_GPIO31_FUN_WPD_S)
-#define IO_MUX_GPIO31_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO31_FUN_WPD_S  7
-/** IO_MUX_GPIO31_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO31_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO31_FUN_WPU_M  (IO_MUX_GPIO31_FUN_WPU_V << IO_MUX_GPIO31_FUN_WPU_S)
-#define IO_MUX_GPIO31_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO31_FUN_WPU_S  8
-/** IO_MUX_GPIO31_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO31_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO31_FUN_IE_M  (IO_MUX_GPIO31_FUN_IE_V << IO_MUX_GPIO31_FUN_IE_S)
-#define IO_MUX_GPIO31_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO31_FUN_IE_S  9
-/** IO_MUX_GPIO31_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO31_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO31_FUN_DRV_M  (IO_MUX_GPIO31_FUN_DRV_V << IO_MUX_GPIO31_FUN_DRV_S)
-#define IO_MUX_GPIO31_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO31_FUN_DRV_S  10
-/** IO_MUX_GPIO31_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO31_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO31_MCU_SEL_M  (IO_MUX_GPIO31_MCU_SEL_V << IO_MUX_GPIO31_MCU_SEL_S)
-#define IO_MUX_GPIO31_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO31_MCU_SEL_S  12
-/** IO_MUX_GPIO31_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO31_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO31_FILTER_EN_M  (IO_MUX_GPIO31_FILTER_EN_V << IO_MUX_GPIO31_FILTER_EN_S)
-#define IO_MUX_GPIO31_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO31_FILTER_EN_S  15
-
-/** IO_MUX_gpio32_REG register
- *  iomux control register for gpio32
- */
-#define IO_MUX_GPIO32_REG (DR_REG_IO_MUX_BASE + 0x84)
-/** IO_MUX_GPIO32_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO32_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO32_MCU_OE_M  (IO_MUX_GPIO32_MCU_OE_V << IO_MUX_GPIO32_MCU_OE_S)
-#define IO_MUX_GPIO32_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO32_MCU_OE_S  0
-/** IO_MUX_GPIO32_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO32_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO32_SLP_SEL_M  (IO_MUX_GPIO32_SLP_SEL_V << IO_MUX_GPIO32_SLP_SEL_S)
-#define IO_MUX_GPIO32_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO32_SLP_SEL_S  1
-/** IO_MUX_GPIO32_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO32_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO32_MCU_WPD_M  (IO_MUX_GPIO32_MCU_WPD_V << IO_MUX_GPIO32_MCU_WPD_S)
-#define IO_MUX_GPIO32_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO32_MCU_WPD_S  2
-/** IO_MUX_GPIO32_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO32_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO32_MCU_WPU_M  (IO_MUX_GPIO32_MCU_WPU_V << IO_MUX_GPIO32_MCU_WPU_S)
-#define IO_MUX_GPIO32_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO32_MCU_WPU_S  3
-/** IO_MUX_GPIO32_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO32_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO32_MCU_IE_M  (IO_MUX_GPIO32_MCU_IE_V << IO_MUX_GPIO32_MCU_IE_S)
-#define IO_MUX_GPIO32_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO32_MCU_IE_S  4
-/** IO_MUX_GPIO32_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO32_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO32_MCU_DRV_M  (IO_MUX_GPIO32_MCU_DRV_V << IO_MUX_GPIO32_MCU_DRV_S)
-#define IO_MUX_GPIO32_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO32_MCU_DRV_S  5
-/** IO_MUX_GPIO32_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO32_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO32_FUN_WPD_M  (IO_MUX_GPIO32_FUN_WPD_V << IO_MUX_GPIO32_FUN_WPD_S)
-#define IO_MUX_GPIO32_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO32_FUN_WPD_S  7
-/** IO_MUX_GPIO32_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO32_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO32_FUN_WPU_M  (IO_MUX_GPIO32_FUN_WPU_V << IO_MUX_GPIO32_FUN_WPU_S)
-#define IO_MUX_GPIO32_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO32_FUN_WPU_S  8
-/** IO_MUX_GPIO32_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO32_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO32_FUN_IE_M  (IO_MUX_GPIO32_FUN_IE_V << IO_MUX_GPIO32_FUN_IE_S)
-#define IO_MUX_GPIO32_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO32_FUN_IE_S  9
-/** IO_MUX_GPIO32_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO32_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO32_FUN_DRV_M  (IO_MUX_GPIO32_FUN_DRV_V << IO_MUX_GPIO32_FUN_DRV_S)
-#define IO_MUX_GPIO32_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO32_FUN_DRV_S  10
-/** IO_MUX_GPIO32_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO32_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO32_MCU_SEL_M  (IO_MUX_GPIO32_MCU_SEL_V << IO_MUX_GPIO32_MCU_SEL_S)
-#define IO_MUX_GPIO32_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO32_MCU_SEL_S  12
-/** IO_MUX_GPIO32_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO32_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO32_FILTER_EN_M  (IO_MUX_GPIO32_FILTER_EN_V << IO_MUX_GPIO32_FILTER_EN_S)
-#define IO_MUX_GPIO32_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO32_FILTER_EN_S  15
-/** IO_MUX_GPIO32_RUE_I3C : R/W; bitpos: [16]; default: 0;
- *  NA
- */
-#define IO_MUX_GPIO32_RUE_I3C    (BIT(16))
-#define IO_MUX_GPIO32_RUE_I3C_M  (IO_MUX_GPIO32_RUE_I3C_V << IO_MUX_GPIO32_RUE_I3C_S)
-#define IO_MUX_GPIO32_RUE_I3C_V  0x00000001U
-#define IO_MUX_GPIO32_RUE_I3C_S  16
-/** IO_MUX_GPIO32_RU_I3C : R/W; bitpos: [18:17]; default: 0;
- *  NA
- */
-#define IO_MUX_GPIO32_RU_I3C    0x00000003U
-#define IO_MUX_GPIO32_RU_I3C_M  (IO_MUX_GPIO32_RU_I3C_V << IO_MUX_GPIO32_RU_I3C_S)
-#define IO_MUX_GPIO32_RU_I3C_V  0x00000003U
-#define IO_MUX_GPIO32_RU_I3C_S  17
-/** IO_MUX_GPIO32_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0;
- *  NA
- */
-#define IO_MUX_GPIO32_RUE_SEL_I3C    (BIT(19))
-#define IO_MUX_GPIO32_RUE_SEL_I3C_M  (IO_MUX_GPIO32_RUE_SEL_I3C_V << IO_MUX_GPIO32_RUE_SEL_I3C_S)
-#define IO_MUX_GPIO32_RUE_SEL_I3C_V  0x00000001U
-#define IO_MUX_GPIO32_RUE_SEL_I3C_S  19
-
-/** IO_MUX_gpio33_REG register
- *  iomux control register for gpio33
- */
-#define IO_MUX_GPIO33_REG (DR_REG_IO_MUX_BASE + 0x88)
-/** IO_MUX_GPIO33_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO33_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO33_MCU_OE_M  (IO_MUX_GPIO33_MCU_OE_V << IO_MUX_GPIO33_MCU_OE_S)
-#define IO_MUX_GPIO33_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO33_MCU_OE_S  0
-/** IO_MUX_GPIO33_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO33_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO33_SLP_SEL_M  (IO_MUX_GPIO33_SLP_SEL_V << IO_MUX_GPIO33_SLP_SEL_S)
-#define IO_MUX_GPIO33_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO33_SLP_SEL_S  1
-/** IO_MUX_GPIO33_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO33_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO33_MCU_WPD_M  (IO_MUX_GPIO33_MCU_WPD_V << IO_MUX_GPIO33_MCU_WPD_S)
-#define IO_MUX_GPIO33_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO33_MCU_WPD_S  2
-/** IO_MUX_GPIO33_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO33_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO33_MCU_WPU_M  (IO_MUX_GPIO33_MCU_WPU_V << IO_MUX_GPIO33_MCU_WPU_S)
-#define IO_MUX_GPIO33_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO33_MCU_WPU_S  3
-/** IO_MUX_GPIO33_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO33_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO33_MCU_IE_M  (IO_MUX_GPIO33_MCU_IE_V << IO_MUX_GPIO33_MCU_IE_S)
-#define IO_MUX_GPIO33_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO33_MCU_IE_S  4
-/** IO_MUX_GPIO33_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO33_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO33_MCU_DRV_M  (IO_MUX_GPIO33_MCU_DRV_V << IO_MUX_GPIO33_MCU_DRV_S)
-#define IO_MUX_GPIO33_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO33_MCU_DRV_S  5
-/** IO_MUX_GPIO33_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO33_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO33_FUN_WPD_M  (IO_MUX_GPIO33_FUN_WPD_V << IO_MUX_GPIO33_FUN_WPD_S)
-#define IO_MUX_GPIO33_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO33_FUN_WPD_S  7
-/** IO_MUX_GPIO33_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO33_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO33_FUN_WPU_M  (IO_MUX_GPIO33_FUN_WPU_V << IO_MUX_GPIO33_FUN_WPU_S)
-#define IO_MUX_GPIO33_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO33_FUN_WPU_S  8
-/** IO_MUX_GPIO33_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO33_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO33_FUN_IE_M  (IO_MUX_GPIO33_FUN_IE_V << IO_MUX_GPIO33_FUN_IE_S)
-#define IO_MUX_GPIO33_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO33_FUN_IE_S  9
-/** IO_MUX_GPIO33_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO33_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO33_FUN_DRV_M  (IO_MUX_GPIO33_FUN_DRV_V << IO_MUX_GPIO33_FUN_DRV_S)
-#define IO_MUX_GPIO33_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO33_FUN_DRV_S  10
-/** IO_MUX_GPIO33_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO33_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO33_MCU_SEL_M  (IO_MUX_GPIO33_MCU_SEL_V << IO_MUX_GPIO33_MCU_SEL_S)
-#define IO_MUX_GPIO33_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO33_MCU_SEL_S  12
-/** IO_MUX_GPIO33_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO33_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO33_FILTER_EN_M  (IO_MUX_GPIO33_FILTER_EN_V << IO_MUX_GPIO33_FILTER_EN_S)
-#define IO_MUX_GPIO33_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO33_FILTER_EN_S  15
-/** IO_MUX_GPIO33_RUE_I3C : R/W; bitpos: [16]; default: 0;
- *  NA
- */
-#define IO_MUX_GPIO33_RUE_I3C    (BIT(16))
-#define IO_MUX_GPIO33_RUE_I3C_M  (IO_MUX_GPIO33_RUE_I3C_V << IO_MUX_GPIO33_RUE_I3C_S)
-#define IO_MUX_GPIO33_RUE_I3C_V  0x00000001U
-#define IO_MUX_GPIO33_RUE_I3C_S  16
-/** IO_MUX_GPIO33_RU_I3C : R/W; bitpos: [18:17]; default: 0;
- *  NA
- */
-#define IO_MUX_GPIO33_RU_I3C    0x00000003U
-#define IO_MUX_GPIO33_RU_I3C_M  (IO_MUX_GPIO33_RU_I3C_V << IO_MUX_GPIO33_RU_I3C_S)
-#define IO_MUX_GPIO33_RU_I3C_V  0x00000003U
-#define IO_MUX_GPIO33_RU_I3C_S  17
-/** IO_MUX_GPIO33_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0;
- *  NA
- */
-#define IO_MUX_GPIO33_RUE_SEL_I3C    (BIT(19))
-#define IO_MUX_GPIO33_RUE_SEL_I3C_M  (IO_MUX_GPIO33_RUE_SEL_I3C_V << IO_MUX_GPIO33_RUE_SEL_I3C_S)
-#define IO_MUX_GPIO33_RUE_SEL_I3C_V  0x00000001U
-#define IO_MUX_GPIO33_RUE_SEL_I3C_S  19
-
-/** IO_MUX_gpio34_REG register
- *  iomux control register for gpio34
- */
-#define IO_MUX_GPIO34_REG (DR_REG_IO_MUX_BASE + 0x8c)
-/** IO_MUX_GPIO34_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO34_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO34_MCU_OE_M  (IO_MUX_GPIO34_MCU_OE_V << IO_MUX_GPIO34_MCU_OE_S)
-#define IO_MUX_GPIO34_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO34_MCU_OE_S  0
-/** IO_MUX_GPIO34_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO34_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO34_SLP_SEL_M  (IO_MUX_GPIO34_SLP_SEL_V << IO_MUX_GPIO34_SLP_SEL_S)
-#define IO_MUX_GPIO34_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO34_SLP_SEL_S  1
-/** IO_MUX_GPIO34_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO34_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO34_MCU_WPD_M  (IO_MUX_GPIO34_MCU_WPD_V << IO_MUX_GPIO34_MCU_WPD_S)
-#define IO_MUX_GPIO34_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO34_MCU_WPD_S  2
-/** IO_MUX_GPIO34_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO34_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO34_MCU_WPU_M  (IO_MUX_GPIO34_MCU_WPU_V << IO_MUX_GPIO34_MCU_WPU_S)
-#define IO_MUX_GPIO34_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO34_MCU_WPU_S  3
-/** IO_MUX_GPIO34_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO34_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO34_MCU_IE_M  (IO_MUX_GPIO34_MCU_IE_V << IO_MUX_GPIO34_MCU_IE_S)
-#define IO_MUX_GPIO34_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO34_MCU_IE_S  4
-/** IO_MUX_GPIO34_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO34_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO34_MCU_DRV_M  (IO_MUX_GPIO34_MCU_DRV_V << IO_MUX_GPIO34_MCU_DRV_S)
-#define IO_MUX_GPIO34_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO34_MCU_DRV_S  5
-/** IO_MUX_GPIO34_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO34_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO34_FUN_WPD_M  (IO_MUX_GPIO34_FUN_WPD_V << IO_MUX_GPIO34_FUN_WPD_S)
-#define IO_MUX_GPIO34_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO34_FUN_WPD_S  7
-/** IO_MUX_GPIO34_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO34_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO34_FUN_WPU_M  (IO_MUX_GPIO34_FUN_WPU_V << IO_MUX_GPIO34_FUN_WPU_S)
-#define IO_MUX_GPIO34_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO34_FUN_WPU_S  8
-/** IO_MUX_GPIO34_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO34_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO34_FUN_IE_M  (IO_MUX_GPIO34_FUN_IE_V << IO_MUX_GPIO34_FUN_IE_S)
-#define IO_MUX_GPIO34_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO34_FUN_IE_S  9
-/** IO_MUX_GPIO34_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO34_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO34_FUN_DRV_M  (IO_MUX_GPIO34_FUN_DRV_V << IO_MUX_GPIO34_FUN_DRV_S)
-#define IO_MUX_GPIO34_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO34_FUN_DRV_S  10
-/** IO_MUX_GPIO34_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO34_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO34_MCU_SEL_M  (IO_MUX_GPIO34_MCU_SEL_V << IO_MUX_GPIO34_MCU_SEL_S)
-#define IO_MUX_GPIO34_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO34_MCU_SEL_S  12
-/** IO_MUX_GPIO34_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO34_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO34_FILTER_EN_M  (IO_MUX_GPIO34_FILTER_EN_V << IO_MUX_GPIO34_FILTER_EN_S)
-#define IO_MUX_GPIO34_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO34_FILTER_EN_S  15
-
-/** IO_MUX_gpio35_REG register
- *  iomux control register for gpio35
- */
-#define IO_MUX_GPIO35_REG (DR_REG_IO_MUX_BASE + 0x90)
-/** IO_MUX_GPIO35_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO35_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO35_MCU_OE_M  (IO_MUX_GPIO35_MCU_OE_V << IO_MUX_GPIO35_MCU_OE_S)
-#define IO_MUX_GPIO35_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO35_MCU_OE_S  0
-/** IO_MUX_GPIO35_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO35_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO35_SLP_SEL_M  (IO_MUX_GPIO35_SLP_SEL_V << IO_MUX_GPIO35_SLP_SEL_S)
-#define IO_MUX_GPIO35_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO35_SLP_SEL_S  1
-/** IO_MUX_GPIO35_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO35_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO35_MCU_WPD_M  (IO_MUX_GPIO35_MCU_WPD_V << IO_MUX_GPIO35_MCU_WPD_S)
-#define IO_MUX_GPIO35_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO35_MCU_WPD_S  2
-/** IO_MUX_GPIO35_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO35_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO35_MCU_WPU_M  (IO_MUX_GPIO35_MCU_WPU_V << IO_MUX_GPIO35_MCU_WPU_S)
-#define IO_MUX_GPIO35_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO35_MCU_WPU_S  3
-/** IO_MUX_GPIO35_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO35_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO35_MCU_IE_M  (IO_MUX_GPIO35_MCU_IE_V << IO_MUX_GPIO35_MCU_IE_S)
-#define IO_MUX_GPIO35_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO35_MCU_IE_S  4
-/** IO_MUX_GPIO35_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO35_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO35_MCU_DRV_M  (IO_MUX_GPIO35_MCU_DRV_V << IO_MUX_GPIO35_MCU_DRV_S)
-#define IO_MUX_GPIO35_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO35_MCU_DRV_S  5
-/** IO_MUX_GPIO35_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO35_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO35_FUN_WPD_M  (IO_MUX_GPIO35_FUN_WPD_V << IO_MUX_GPIO35_FUN_WPD_S)
-#define IO_MUX_GPIO35_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO35_FUN_WPD_S  7
-/** IO_MUX_GPIO35_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO35_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO35_FUN_WPU_M  (IO_MUX_GPIO35_FUN_WPU_V << IO_MUX_GPIO35_FUN_WPU_S)
-#define IO_MUX_GPIO35_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO35_FUN_WPU_S  8
-/** IO_MUX_GPIO35_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO35_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO35_FUN_IE_M  (IO_MUX_GPIO35_FUN_IE_V << IO_MUX_GPIO35_FUN_IE_S)
-#define IO_MUX_GPIO35_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO35_FUN_IE_S  9
-/** IO_MUX_GPIO35_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO35_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO35_FUN_DRV_M  (IO_MUX_GPIO35_FUN_DRV_V << IO_MUX_GPIO35_FUN_DRV_S)
-#define IO_MUX_GPIO35_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO35_FUN_DRV_S  10
-/** IO_MUX_GPIO35_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO35_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO35_MCU_SEL_M  (IO_MUX_GPIO35_MCU_SEL_V << IO_MUX_GPIO35_MCU_SEL_S)
-#define IO_MUX_GPIO35_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO35_MCU_SEL_S  12
-/** IO_MUX_GPIO35_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO35_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO35_FILTER_EN_M  (IO_MUX_GPIO35_FILTER_EN_V << IO_MUX_GPIO35_FILTER_EN_S)
-#define IO_MUX_GPIO35_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO35_FILTER_EN_S  15
-
-/** IO_MUX_gpio36_REG register
- *  iomux control register for gpio36
- */
-#define IO_MUX_GPIO36_REG (DR_REG_IO_MUX_BASE + 0x94)
-/** IO_MUX_GPIO36_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO36_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO36_MCU_OE_M  (IO_MUX_GPIO36_MCU_OE_V << IO_MUX_GPIO36_MCU_OE_S)
-#define IO_MUX_GPIO36_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO36_MCU_OE_S  0
-/** IO_MUX_GPIO36_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO36_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO36_SLP_SEL_M  (IO_MUX_GPIO36_SLP_SEL_V << IO_MUX_GPIO36_SLP_SEL_S)
-#define IO_MUX_GPIO36_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO36_SLP_SEL_S  1
-/** IO_MUX_GPIO36_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO36_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO36_MCU_WPD_M  (IO_MUX_GPIO36_MCU_WPD_V << IO_MUX_GPIO36_MCU_WPD_S)
-#define IO_MUX_GPIO36_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO36_MCU_WPD_S  2
-/** IO_MUX_GPIO36_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO36_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO36_MCU_WPU_M  (IO_MUX_GPIO36_MCU_WPU_V << IO_MUX_GPIO36_MCU_WPU_S)
-#define IO_MUX_GPIO36_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO36_MCU_WPU_S  3
-/** IO_MUX_GPIO36_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO36_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO36_MCU_IE_M  (IO_MUX_GPIO36_MCU_IE_V << IO_MUX_GPIO36_MCU_IE_S)
-#define IO_MUX_GPIO36_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO36_MCU_IE_S  4
-/** IO_MUX_GPIO36_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO36_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO36_MCU_DRV_M  (IO_MUX_GPIO36_MCU_DRV_V << IO_MUX_GPIO36_MCU_DRV_S)
-#define IO_MUX_GPIO36_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO36_MCU_DRV_S  5
-/** IO_MUX_GPIO36_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO36_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO36_FUN_WPD_M  (IO_MUX_GPIO36_FUN_WPD_V << IO_MUX_GPIO36_FUN_WPD_S)
-#define IO_MUX_GPIO36_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO36_FUN_WPD_S  7
-/** IO_MUX_GPIO36_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO36_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO36_FUN_WPU_M  (IO_MUX_GPIO36_FUN_WPU_V << IO_MUX_GPIO36_FUN_WPU_S)
-#define IO_MUX_GPIO36_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO36_FUN_WPU_S  8
-/** IO_MUX_GPIO36_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO36_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO36_FUN_IE_M  (IO_MUX_GPIO36_FUN_IE_V << IO_MUX_GPIO36_FUN_IE_S)
-#define IO_MUX_GPIO36_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO36_FUN_IE_S  9
-/** IO_MUX_GPIO36_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO36_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO36_FUN_DRV_M  (IO_MUX_GPIO36_FUN_DRV_V << IO_MUX_GPIO36_FUN_DRV_S)
-#define IO_MUX_GPIO36_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO36_FUN_DRV_S  10
-/** IO_MUX_GPIO36_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO36_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO36_MCU_SEL_M  (IO_MUX_GPIO36_MCU_SEL_V << IO_MUX_GPIO36_MCU_SEL_S)
-#define IO_MUX_GPIO36_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO36_MCU_SEL_S  12
-/** IO_MUX_GPIO36_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO36_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO36_FILTER_EN_M  (IO_MUX_GPIO36_FILTER_EN_V << IO_MUX_GPIO36_FILTER_EN_S)
-#define IO_MUX_GPIO36_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO36_FILTER_EN_S  15
-
-/** IO_MUX_gpio37_REG register
- *  iomux control register for gpio37
- */
-#define IO_MUX_GPIO37_REG (DR_REG_IO_MUX_BASE + 0x98)
-/** IO_MUX_GPIO37_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO37_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO37_MCU_OE_M  (IO_MUX_GPIO37_MCU_OE_V << IO_MUX_GPIO37_MCU_OE_S)
-#define IO_MUX_GPIO37_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO37_MCU_OE_S  0
-/** IO_MUX_GPIO37_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO37_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO37_SLP_SEL_M  (IO_MUX_GPIO37_SLP_SEL_V << IO_MUX_GPIO37_SLP_SEL_S)
-#define IO_MUX_GPIO37_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO37_SLP_SEL_S  1
-/** IO_MUX_GPIO37_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO37_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO37_MCU_WPD_M  (IO_MUX_GPIO37_MCU_WPD_V << IO_MUX_GPIO37_MCU_WPD_S)
-#define IO_MUX_GPIO37_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO37_MCU_WPD_S  2
-/** IO_MUX_GPIO37_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO37_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO37_MCU_WPU_M  (IO_MUX_GPIO37_MCU_WPU_V << IO_MUX_GPIO37_MCU_WPU_S)
-#define IO_MUX_GPIO37_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO37_MCU_WPU_S  3
-/** IO_MUX_GPIO37_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO37_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO37_MCU_IE_M  (IO_MUX_GPIO37_MCU_IE_V << IO_MUX_GPIO37_MCU_IE_S)
-#define IO_MUX_GPIO37_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO37_MCU_IE_S  4
-/** IO_MUX_GPIO37_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO37_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO37_MCU_DRV_M  (IO_MUX_GPIO37_MCU_DRV_V << IO_MUX_GPIO37_MCU_DRV_S)
-#define IO_MUX_GPIO37_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO37_MCU_DRV_S  5
-/** IO_MUX_GPIO37_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO37_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO37_FUN_WPD_M  (IO_MUX_GPIO37_FUN_WPD_V << IO_MUX_GPIO37_FUN_WPD_S)
-#define IO_MUX_GPIO37_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO37_FUN_WPD_S  7
-/** IO_MUX_GPIO37_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO37_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO37_FUN_WPU_M  (IO_MUX_GPIO37_FUN_WPU_V << IO_MUX_GPIO37_FUN_WPU_S)
-#define IO_MUX_GPIO37_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO37_FUN_WPU_S  8
-/** IO_MUX_GPIO37_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO37_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO37_FUN_IE_M  (IO_MUX_GPIO37_FUN_IE_V << IO_MUX_GPIO37_FUN_IE_S)
-#define IO_MUX_GPIO37_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO37_FUN_IE_S  9
-/** IO_MUX_GPIO37_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO37_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO37_FUN_DRV_M  (IO_MUX_GPIO37_FUN_DRV_V << IO_MUX_GPIO37_FUN_DRV_S)
-#define IO_MUX_GPIO37_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO37_FUN_DRV_S  10
-/** IO_MUX_GPIO37_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO37_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO37_MCU_SEL_M  (IO_MUX_GPIO37_MCU_SEL_V << IO_MUX_GPIO37_MCU_SEL_S)
-#define IO_MUX_GPIO37_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO37_MCU_SEL_S  12
-/** IO_MUX_GPIO37_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO37_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO37_FILTER_EN_M  (IO_MUX_GPIO37_FILTER_EN_V << IO_MUX_GPIO37_FILTER_EN_S)
-#define IO_MUX_GPIO37_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO37_FILTER_EN_S  15
-
-/** IO_MUX_gpio38_REG register
- *  iomux control register for gpio38
- */
-#define IO_MUX_GPIO38_REG (DR_REG_IO_MUX_BASE + 0x9c)
-/** IO_MUX_GPIO38_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO38_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO38_MCU_OE_M  (IO_MUX_GPIO38_MCU_OE_V << IO_MUX_GPIO38_MCU_OE_S)
-#define IO_MUX_GPIO38_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO38_MCU_OE_S  0
-/** IO_MUX_GPIO38_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO38_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO38_SLP_SEL_M  (IO_MUX_GPIO38_SLP_SEL_V << IO_MUX_GPIO38_SLP_SEL_S)
-#define IO_MUX_GPIO38_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO38_SLP_SEL_S  1
-/** IO_MUX_GPIO38_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO38_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO38_MCU_WPD_M  (IO_MUX_GPIO38_MCU_WPD_V << IO_MUX_GPIO38_MCU_WPD_S)
-#define IO_MUX_GPIO38_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO38_MCU_WPD_S  2
-/** IO_MUX_GPIO38_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO38_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO38_MCU_WPU_M  (IO_MUX_GPIO38_MCU_WPU_V << IO_MUX_GPIO38_MCU_WPU_S)
-#define IO_MUX_GPIO38_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO38_MCU_WPU_S  3
-/** IO_MUX_GPIO38_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO38_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO38_MCU_IE_M  (IO_MUX_GPIO38_MCU_IE_V << IO_MUX_GPIO38_MCU_IE_S)
-#define IO_MUX_GPIO38_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO38_MCU_IE_S  4
-/** IO_MUX_GPIO38_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO38_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO38_MCU_DRV_M  (IO_MUX_GPIO38_MCU_DRV_V << IO_MUX_GPIO38_MCU_DRV_S)
-#define IO_MUX_GPIO38_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO38_MCU_DRV_S  5
-/** IO_MUX_GPIO38_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO38_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO38_FUN_WPD_M  (IO_MUX_GPIO38_FUN_WPD_V << IO_MUX_GPIO38_FUN_WPD_S)
-#define IO_MUX_GPIO38_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO38_FUN_WPD_S  7
-/** IO_MUX_GPIO38_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO38_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO38_FUN_WPU_M  (IO_MUX_GPIO38_FUN_WPU_V << IO_MUX_GPIO38_FUN_WPU_S)
-#define IO_MUX_GPIO38_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO38_FUN_WPU_S  8
-/** IO_MUX_GPIO38_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO38_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO38_FUN_IE_M  (IO_MUX_GPIO38_FUN_IE_V << IO_MUX_GPIO38_FUN_IE_S)
-#define IO_MUX_GPIO38_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO38_FUN_IE_S  9
-/** IO_MUX_GPIO38_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO38_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO38_FUN_DRV_M  (IO_MUX_GPIO38_FUN_DRV_V << IO_MUX_GPIO38_FUN_DRV_S)
-#define IO_MUX_GPIO38_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO38_FUN_DRV_S  10
-/** IO_MUX_GPIO38_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO38_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO38_MCU_SEL_M  (IO_MUX_GPIO38_MCU_SEL_V << IO_MUX_GPIO38_MCU_SEL_S)
-#define IO_MUX_GPIO38_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO38_MCU_SEL_S  12
-/** IO_MUX_GPIO38_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO38_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO38_FILTER_EN_M  (IO_MUX_GPIO38_FILTER_EN_V << IO_MUX_GPIO38_FILTER_EN_S)
-#define IO_MUX_GPIO38_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO38_FILTER_EN_S  15
-
-/** IO_MUX_gpio39_REG register
- *  iomux control register for gpio39
- */
-#define IO_MUX_GPIO39_REG (DR_REG_IO_MUX_BASE + 0xa0)
-/** IO_MUX_GPIO39_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO39_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO39_MCU_OE_M  (IO_MUX_GPIO39_MCU_OE_V << IO_MUX_GPIO39_MCU_OE_S)
-#define IO_MUX_GPIO39_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO39_MCU_OE_S  0
-/** IO_MUX_GPIO39_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO39_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO39_SLP_SEL_M  (IO_MUX_GPIO39_SLP_SEL_V << IO_MUX_GPIO39_SLP_SEL_S)
-#define IO_MUX_GPIO39_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO39_SLP_SEL_S  1
-/** IO_MUX_GPIO39_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO39_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO39_MCU_WPD_M  (IO_MUX_GPIO39_MCU_WPD_V << IO_MUX_GPIO39_MCU_WPD_S)
-#define IO_MUX_GPIO39_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO39_MCU_WPD_S  2
-/** IO_MUX_GPIO39_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO39_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO39_MCU_WPU_M  (IO_MUX_GPIO39_MCU_WPU_V << IO_MUX_GPIO39_MCU_WPU_S)
-#define IO_MUX_GPIO39_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO39_MCU_WPU_S  3
-/** IO_MUX_GPIO39_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO39_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO39_MCU_IE_M  (IO_MUX_GPIO39_MCU_IE_V << IO_MUX_GPIO39_MCU_IE_S)
-#define IO_MUX_GPIO39_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO39_MCU_IE_S  4
-/** IO_MUX_GPIO39_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO39_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO39_MCU_DRV_M  (IO_MUX_GPIO39_MCU_DRV_V << IO_MUX_GPIO39_MCU_DRV_S)
-#define IO_MUX_GPIO39_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO39_MCU_DRV_S  5
-/** IO_MUX_GPIO39_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO39_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO39_FUN_WPD_M  (IO_MUX_GPIO39_FUN_WPD_V << IO_MUX_GPIO39_FUN_WPD_S)
-#define IO_MUX_GPIO39_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO39_FUN_WPD_S  7
-/** IO_MUX_GPIO39_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO39_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO39_FUN_WPU_M  (IO_MUX_GPIO39_FUN_WPU_V << IO_MUX_GPIO39_FUN_WPU_S)
-#define IO_MUX_GPIO39_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO39_FUN_WPU_S  8
-/** IO_MUX_GPIO39_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO39_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO39_FUN_IE_M  (IO_MUX_GPIO39_FUN_IE_V << IO_MUX_GPIO39_FUN_IE_S)
-#define IO_MUX_GPIO39_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO39_FUN_IE_S  9
-/** IO_MUX_GPIO39_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO39_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO39_FUN_DRV_M  (IO_MUX_GPIO39_FUN_DRV_V << IO_MUX_GPIO39_FUN_DRV_S)
-#define IO_MUX_GPIO39_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO39_FUN_DRV_S  10
-/** IO_MUX_GPIO39_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO39_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO39_MCU_SEL_M  (IO_MUX_GPIO39_MCU_SEL_V << IO_MUX_GPIO39_MCU_SEL_S)
-#define IO_MUX_GPIO39_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO39_MCU_SEL_S  12
-/** IO_MUX_GPIO39_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO39_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO39_FILTER_EN_M  (IO_MUX_GPIO39_FILTER_EN_V << IO_MUX_GPIO39_FILTER_EN_S)
-#define IO_MUX_GPIO39_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO39_FILTER_EN_S  15
-
-/** IO_MUX_gpio40_REG register
- *  iomux control register for gpio40
- */
-#define IO_MUX_GPIO40_REG (DR_REG_IO_MUX_BASE + 0xa4)
-/** IO_MUX_GPIO40_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO40_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO40_MCU_OE_M  (IO_MUX_GPIO40_MCU_OE_V << IO_MUX_GPIO40_MCU_OE_S)
-#define IO_MUX_GPIO40_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO40_MCU_OE_S  0
-/** IO_MUX_GPIO40_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO40_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO40_SLP_SEL_M  (IO_MUX_GPIO40_SLP_SEL_V << IO_MUX_GPIO40_SLP_SEL_S)
-#define IO_MUX_GPIO40_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO40_SLP_SEL_S  1
-/** IO_MUX_GPIO40_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO40_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO40_MCU_WPD_M  (IO_MUX_GPIO40_MCU_WPD_V << IO_MUX_GPIO40_MCU_WPD_S)
-#define IO_MUX_GPIO40_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO40_MCU_WPD_S  2
-/** IO_MUX_GPIO40_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO40_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO40_MCU_WPU_M  (IO_MUX_GPIO40_MCU_WPU_V << IO_MUX_GPIO40_MCU_WPU_S)
-#define IO_MUX_GPIO40_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO40_MCU_WPU_S  3
-/** IO_MUX_GPIO40_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO40_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO40_MCU_IE_M  (IO_MUX_GPIO40_MCU_IE_V << IO_MUX_GPIO40_MCU_IE_S)
-#define IO_MUX_GPIO40_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO40_MCU_IE_S  4
-/** IO_MUX_GPIO40_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO40_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO40_MCU_DRV_M  (IO_MUX_GPIO40_MCU_DRV_V << IO_MUX_GPIO40_MCU_DRV_S)
-#define IO_MUX_GPIO40_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO40_MCU_DRV_S  5
-/** IO_MUX_GPIO40_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO40_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO40_FUN_WPD_M  (IO_MUX_GPIO40_FUN_WPD_V << IO_MUX_GPIO40_FUN_WPD_S)
-#define IO_MUX_GPIO40_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO40_FUN_WPD_S  7
-/** IO_MUX_GPIO40_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO40_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO40_FUN_WPU_M  (IO_MUX_GPIO40_FUN_WPU_V << IO_MUX_GPIO40_FUN_WPU_S)
-#define IO_MUX_GPIO40_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO40_FUN_WPU_S  8
-/** IO_MUX_GPIO40_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO40_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO40_FUN_IE_M  (IO_MUX_GPIO40_FUN_IE_V << IO_MUX_GPIO40_FUN_IE_S)
-#define IO_MUX_GPIO40_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO40_FUN_IE_S  9
-/** IO_MUX_GPIO40_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO40_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO40_FUN_DRV_M  (IO_MUX_GPIO40_FUN_DRV_V << IO_MUX_GPIO40_FUN_DRV_S)
-#define IO_MUX_GPIO40_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO40_FUN_DRV_S  10
-/** IO_MUX_GPIO40_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO40_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO40_MCU_SEL_M  (IO_MUX_GPIO40_MCU_SEL_V << IO_MUX_GPIO40_MCU_SEL_S)
-#define IO_MUX_GPIO40_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO40_MCU_SEL_S  12
-/** IO_MUX_GPIO40_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO40_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO40_FILTER_EN_M  (IO_MUX_GPIO40_FILTER_EN_V << IO_MUX_GPIO40_FILTER_EN_S)
-#define IO_MUX_GPIO40_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO40_FILTER_EN_S  15
-
-/** IO_MUX_gpio41_REG register
- *  iomux control register for gpio41
- */
-#define IO_MUX_GPIO41_REG (DR_REG_IO_MUX_BASE + 0xa8)
-/** IO_MUX_GPIO41_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO41_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO41_MCU_OE_M  (IO_MUX_GPIO41_MCU_OE_V << IO_MUX_GPIO41_MCU_OE_S)
-#define IO_MUX_GPIO41_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO41_MCU_OE_S  0
-/** IO_MUX_GPIO41_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO41_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO41_SLP_SEL_M  (IO_MUX_GPIO41_SLP_SEL_V << IO_MUX_GPIO41_SLP_SEL_S)
-#define IO_MUX_GPIO41_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO41_SLP_SEL_S  1
-/** IO_MUX_GPIO41_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO41_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO41_MCU_WPD_M  (IO_MUX_GPIO41_MCU_WPD_V << IO_MUX_GPIO41_MCU_WPD_S)
-#define IO_MUX_GPIO41_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO41_MCU_WPD_S  2
-/** IO_MUX_GPIO41_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO41_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO41_MCU_WPU_M  (IO_MUX_GPIO41_MCU_WPU_V << IO_MUX_GPIO41_MCU_WPU_S)
-#define IO_MUX_GPIO41_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO41_MCU_WPU_S  3
-/** IO_MUX_GPIO41_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO41_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO41_MCU_IE_M  (IO_MUX_GPIO41_MCU_IE_V << IO_MUX_GPIO41_MCU_IE_S)
-#define IO_MUX_GPIO41_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO41_MCU_IE_S  4
-/** IO_MUX_GPIO41_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO41_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO41_MCU_DRV_M  (IO_MUX_GPIO41_MCU_DRV_V << IO_MUX_GPIO41_MCU_DRV_S)
-#define IO_MUX_GPIO41_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO41_MCU_DRV_S  5
-/** IO_MUX_GPIO41_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO41_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO41_FUN_WPD_M  (IO_MUX_GPIO41_FUN_WPD_V << IO_MUX_GPIO41_FUN_WPD_S)
-#define IO_MUX_GPIO41_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO41_FUN_WPD_S  7
-/** IO_MUX_GPIO41_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO41_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO41_FUN_WPU_M  (IO_MUX_GPIO41_FUN_WPU_V << IO_MUX_GPIO41_FUN_WPU_S)
-#define IO_MUX_GPIO41_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO41_FUN_WPU_S  8
-/** IO_MUX_GPIO41_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO41_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO41_FUN_IE_M  (IO_MUX_GPIO41_FUN_IE_V << IO_MUX_GPIO41_FUN_IE_S)
-#define IO_MUX_GPIO41_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO41_FUN_IE_S  9
-/** IO_MUX_GPIO41_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO41_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO41_FUN_DRV_M  (IO_MUX_GPIO41_FUN_DRV_V << IO_MUX_GPIO41_FUN_DRV_S)
-#define IO_MUX_GPIO41_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO41_FUN_DRV_S  10
-/** IO_MUX_GPIO41_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO41_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO41_MCU_SEL_M  (IO_MUX_GPIO41_MCU_SEL_V << IO_MUX_GPIO41_MCU_SEL_S)
-#define IO_MUX_GPIO41_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO41_MCU_SEL_S  12
-/** IO_MUX_GPIO41_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO41_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO41_FILTER_EN_M  (IO_MUX_GPIO41_FILTER_EN_V << IO_MUX_GPIO41_FILTER_EN_S)
-#define IO_MUX_GPIO41_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO41_FILTER_EN_S  15
-
-/** IO_MUX_gpio42_REG register
- *  iomux control register for gpio42
- */
-#define IO_MUX_GPIO42_REG (DR_REG_IO_MUX_BASE + 0xac)
-/** IO_MUX_GPIO42_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO42_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO42_MCU_OE_M  (IO_MUX_GPIO42_MCU_OE_V << IO_MUX_GPIO42_MCU_OE_S)
-#define IO_MUX_GPIO42_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO42_MCU_OE_S  0
-/** IO_MUX_GPIO42_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO42_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO42_SLP_SEL_M  (IO_MUX_GPIO42_SLP_SEL_V << IO_MUX_GPIO42_SLP_SEL_S)
-#define IO_MUX_GPIO42_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO42_SLP_SEL_S  1
-/** IO_MUX_GPIO42_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO42_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO42_MCU_WPD_M  (IO_MUX_GPIO42_MCU_WPD_V << IO_MUX_GPIO42_MCU_WPD_S)
-#define IO_MUX_GPIO42_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO42_MCU_WPD_S  2
-/** IO_MUX_GPIO42_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO42_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO42_MCU_WPU_M  (IO_MUX_GPIO42_MCU_WPU_V << IO_MUX_GPIO42_MCU_WPU_S)
-#define IO_MUX_GPIO42_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO42_MCU_WPU_S  3
-/** IO_MUX_GPIO42_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO42_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO42_MCU_IE_M  (IO_MUX_GPIO42_MCU_IE_V << IO_MUX_GPIO42_MCU_IE_S)
-#define IO_MUX_GPIO42_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO42_MCU_IE_S  4
-/** IO_MUX_GPIO42_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO42_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO42_MCU_DRV_M  (IO_MUX_GPIO42_MCU_DRV_V << IO_MUX_GPIO42_MCU_DRV_S)
-#define IO_MUX_GPIO42_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO42_MCU_DRV_S  5
-/** IO_MUX_GPIO42_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO42_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO42_FUN_WPD_M  (IO_MUX_GPIO42_FUN_WPD_V << IO_MUX_GPIO42_FUN_WPD_S)
-#define IO_MUX_GPIO42_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO42_FUN_WPD_S  7
-/** IO_MUX_GPIO42_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO42_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO42_FUN_WPU_M  (IO_MUX_GPIO42_FUN_WPU_V << IO_MUX_GPIO42_FUN_WPU_S)
-#define IO_MUX_GPIO42_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO42_FUN_WPU_S  8
-/** IO_MUX_GPIO42_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO42_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO42_FUN_IE_M  (IO_MUX_GPIO42_FUN_IE_V << IO_MUX_GPIO42_FUN_IE_S)
-#define IO_MUX_GPIO42_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO42_FUN_IE_S  9
-/** IO_MUX_GPIO42_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO42_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO42_FUN_DRV_M  (IO_MUX_GPIO42_FUN_DRV_V << IO_MUX_GPIO42_FUN_DRV_S)
-#define IO_MUX_GPIO42_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO42_FUN_DRV_S  10
-/** IO_MUX_GPIO42_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO42_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO42_MCU_SEL_M  (IO_MUX_GPIO42_MCU_SEL_V << IO_MUX_GPIO42_MCU_SEL_S)
-#define IO_MUX_GPIO42_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO42_MCU_SEL_S  12
-/** IO_MUX_GPIO42_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO42_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO42_FILTER_EN_M  (IO_MUX_GPIO42_FILTER_EN_V << IO_MUX_GPIO42_FILTER_EN_S)
-#define IO_MUX_GPIO42_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO42_FILTER_EN_S  15
-
-/** IO_MUX_gpio43_REG register
- *  iomux control register for gpio43
- */
-#define IO_MUX_GPIO43_REG (DR_REG_IO_MUX_BASE + 0xb0)
-/** IO_MUX_GPIO43_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO43_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO43_MCU_OE_M  (IO_MUX_GPIO43_MCU_OE_V << IO_MUX_GPIO43_MCU_OE_S)
-#define IO_MUX_GPIO43_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO43_MCU_OE_S  0
-/** IO_MUX_GPIO43_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO43_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO43_SLP_SEL_M  (IO_MUX_GPIO43_SLP_SEL_V << IO_MUX_GPIO43_SLP_SEL_S)
-#define IO_MUX_GPIO43_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO43_SLP_SEL_S  1
-/** IO_MUX_GPIO43_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO43_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO43_MCU_WPD_M  (IO_MUX_GPIO43_MCU_WPD_V << IO_MUX_GPIO43_MCU_WPD_S)
-#define IO_MUX_GPIO43_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO43_MCU_WPD_S  2
-/** IO_MUX_GPIO43_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO43_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO43_MCU_WPU_M  (IO_MUX_GPIO43_MCU_WPU_V << IO_MUX_GPIO43_MCU_WPU_S)
-#define IO_MUX_GPIO43_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO43_MCU_WPU_S  3
-/** IO_MUX_GPIO43_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO43_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO43_MCU_IE_M  (IO_MUX_GPIO43_MCU_IE_V << IO_MUX_GPIO43_MCU_IE_S)
-#define IO_MUX_GPIO43_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO43_MCU_IE_S  4
-/** IO_MUX_GPIO43_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO43_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO43_MCU_DRV_M  (IO_MUX_GPIO43_MCU_DRV_V << IO_MUX_GPIO43_MCU_DRV_S)
-#define IO_MUX_GPIO43_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO43_MCU_DRV_S  5
-/** IO_MUX_GPIO43_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO43_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO43_FUN_WPD_M  (IO_MUX_GPIO43_FUN_WPD_V << IO_MUX_GPIO43_FUN_WPD_S)
-#define IO_MUX_GPIO43_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO43_FUN_WPD_S  7
-/** IO_MUX_GPIO43_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO43_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO43_FUN_WPU_M  (IO_MUX_GPIO43_FUN_WPU_V << IO_MUX_GPIO43_FUN_WPU_S)
-#define IO_MUX_GPIO43_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO43_FUN_WPU_S  8
-/** IO_MUX_GPIO43_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO43_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO43_FUN_IE_M  (IO_MUX_GPIO43_FUN_IE_V << IO_MUX_GPIO43_FUN_IE_S)
-#define IO_MUX_GPIO43_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO43_FUN_IE_S  9
-/** IO_MUX_GPIO43_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO43_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO43_FUN_DRV_M  (IO_MUX_GPIO43_FUN_DRV_V << IO_MUX_GPIO43_FUN_DRV_S)
-#define IO_MUX_GPIO43_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO43_FUN_DRV_S  10
-/** IO_MUX_GPIO43_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO43_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO43_MCU_SEL_M  (IO_MUX_GPIO43_MCU_SEL_V << IO_MUX_GPIO43_MCU_SEL_S)
-#define IO_MUX_GPIO43_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO43_MCU_SEL_S  12
-/** IO_MUX_GPIO43_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO43_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO43_FILTER_EN_M  (IO_MUX_GPIO43_FILTER_EN_V << IO_MUX_GPIO43_FILTER_EN_S)
-#define IO_MUX_GPIO43_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO43_FILTER_EN_S  15
-
-/** IO_MUX_gpio44_REG register
- *  iomux control register for gpio44
- */
-#define IO_MUX_GPIO44_REG (DR_REG_IO_MUX_BASE + 0xb4)
-/** IO_MUX_GPIO44_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO44_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO44_MCU_OE_M  (IO_MUX_GPIO44_MCU_OE_V << IO_MUX_GPIO44_MCU_OE_S)
-#define IO_MUX_GPIO44_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO44_MCU_OE_S  0
-/** IO_MUX_GPIO44_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO44_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO44_SLP_SEL_M  (IO_MUX_GPIO44_SLP_SEL_V << IO_MUX_GPIO44_SLP_SEL_S)
-#define IO_MUX_GPIO44_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO44_SLP_SEL_S  1
-/** IO_MUX_GPIO44_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO44_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO44_MCU_WPD_M  (IO_MUX_GPIO44_MCU_WPD_V << IO_MUX_GPIO44_MCU_WPD_S)
-#define IO_MUX_GPIO44_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO44_MCU_WPD_S  2
-/** IO_MUX_GPIO44_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO44_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO44_MCU_WPU_M  (IO_MUX_GPIO44_MCU_WPU_V << IO_MUX_GPIO44_MCU_WPU_S)
-#define IO_MUX_GPIO44_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO44_MCU_WPU_S  3
-/** IO_MUX_GPIO44_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO44_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO44_MCU_IE_M  (IO_MUX_GPIO44_MCU_IE_V << IO_MUX_GPIO44_MCU_IE_S)
-#define IO_MUX_GPIO44_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO44_MCU_IE_S  4
-/** IO_MUX_GPIO44_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO44_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO44_MCU_DRV_M  (IO_MUX_GPIO44_MCU_DRV_V << IO_MUX_GPIO44_MCU_DRV_S)
-#define IO_MUX_GPIO44_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO44_MCU_DRV_S  5
-/** IO_MUX_GPIO44_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO44_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO44_FUN_WPD_M  (IO_MUX_GPIO44_FUN_WPD_V << IO_MUX_GPIO44_FUN_WPD_S)
-#define IO_MUX_GPIO44_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO44_FUN_WPD_S  7
-/** IO_MUX_GPIO44_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO44_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO44_FUN_WPU_M  (IO_MUX_GPIO44_FUN_WPU_V << IO_MUX_GPIO44_FUN_WPU_S)
-#define IO_MUX_GPIO44_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO44_FUN_WPU_S  8
-/** IO_MUX_GPIO44_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO44_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO44_FUN_IE_M  (IO_MUX_GPIO44_FUN_IE_V << IO_MUX_GPIO44_FUN_IE_S)
-#define IO_MUX_GPIO44_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO44_FUN_IE_S  9
-/** IO_MUX_GPIO44_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO44_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO44_FUN_DRV_M  (IO_MUX_GPIO44_FUN_DRV_V << IO_MUX_GPIO44_FUN_DRV_S)
-#define IO_MUX_GPIO44_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO44_FUN_DRV_S  10
-/** IO_MUX_GPIO44_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO44_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO44_MCU_SEL_M  (IO_MUX_GPIO44_MCU_SEL_V << IO_MUX_GPIO44_MCU_SEL_S)
-#define IO_MUX_GPIO44_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO44_MCU_SEL_S  12
-/** IO_MUX_GPIO44_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO44_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO44_FILTER_EN_M  (IO_MUX_GPIO44_FILTER_EN_V << IO_MUX_GPIO44_FILTER_EN_S)
-#define IO_MUX_GPIO44_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO44_FILTER_EN_S  15
-
-/** IO_MUX_gpio45_REG register
- *  iomux control register for gpio45
- */
-#define IO_MUX_GPIO45_REG (DR_REG_IO_MUX_BASE + 0xb8)
-/** IO_MUX_GPIO45_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO45_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO45_MCU_OE_M  (IO_MUX_GPIO45_MCU_OE_V << IO_MUX_GPIO45_MCU_OE_S)
-#define IO_MUX_GPIO45_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO45_MCU_OE_S  0
-/** IO_MUX_GPIO45_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO45_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO45_SLP_SEL_M  (IO_MUX_GPIO45_SLP_SEL_V << IO_MUX_GPIO45_SLP_SEL_S)
-#define IO_MUX_GPIO45_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO45_SLP_SEL_S  1
-/** IO_MUX_GPIO45_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO45_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO45_MCU_WPD_M  (IO_MUX_GPIO45_MCU_WPD_V << IO_MUX_GPIO45_MCU_WPD_S)
-#define IO_MUX_GPIO45_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO45_MCU_WPD_S  2
-/** IO_MUX_GPIO45_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO45_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO45_MCU_WPU_M  (IO_MUX_GPIO45_MCU_WPU_V << IO_MUX_GPIO45_MCU_WPU_S)
-#define IO_MUX_GPIO45_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO45_MCU_WPU_S  3
-/** IO_MUX_GPIO45_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO45_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO45_MCU_IE_M  (IO_MUX_GPIO45_MCU_IE_V << IO_MUX_GPIO45_MCU_IE_S)
-#define IO_MUX_GPIO45_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO45_MCU_IE_S  4
-/** IO_MUX_GPIO45_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO45_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO45_MCU_DRV_M  (IO_MUX_GPIO45_MCU_DRV_V << IO_MUX_GPIO45_MCU_DRV_S)
-#define IO_MUX_GPIO45_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO45_MCU_DRV_S  5
-/** IO_MUX_GPIO45_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO45_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO45_FUN_WPD_M  (IO_MUX_GPIO45_FUN_WPD_V << IO_MUX_GPIO45_FUN_WPD_S)
-#define IO_MUX_GPIO45_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO45_FUN_WPD_S  7
-/** IO_MUX_GPIO45_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO45_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO45_FUN_WPU_M  (IO_MUX_GPIO45_FUN_WPU_V << IO_MUX_GPIO45_FUN_WPU_S)
-#define IO_MUX_GPIO45_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO45_FUN_WPU_S  8
-/** IO_MUX_GPIO45_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO45_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO45_FUN_IE_M  (IO_MUX_GPIO45_FUN_IE_V << IO_MUX_GPIO45_FUN_IE_S)
-#define IO_MUX_GPIO45_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO45_FUN_IE_S  9
-/** IO_MUX_GPIO45_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO45_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO45_FUN_DRV_M  (IO_MUX_GPIO45_FUN_DRV_V << IO_MUX_GPIO45_FUN_DRV_S)
-#define IO_MUX_GPIO45_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO45_FUN_DRV_S  10
-/** IO_MUX_GPIO45_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO45_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO45_MCU_SEL_M  (IO_MUX_GPIO45_MCU_SEL_V << IO_MUX_GPIO45_MCU_SEL_S)
-#define IO_MUX_GPIO45_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO45_MCU_SEL_S  12
-/** IO_MUX_GPIO45_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO45_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO45_FILTER_EN_M  (IO_MUX_GPIO45_FILTER_EN_V << IO_MUX_GPIO45_FILTER_EN_S)
-#define IO_MUX_GPIO45_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO45_FILTER_EN_S  15
-
-/** IO_MUX_gpio46_REG register
- *  iomux control register for gpio46
- */
-#define IO_MUX_GPIO46_REG (DR_REG_IO_MUX_BASE + 0xbc)
-/** IO_MUX_GPIO46_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO46_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO46_MCU_OE_M  (IO_MUX_GPIO46_MCU_OE_V << IO_MUX_GPIO46_MCU_OE_S)
-#define IO_MUX_GPIO46_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO46_MCU_OE_S  0
-/** IO_MUX_GPIO46_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO46_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO46_SLP_SEL_M  (IO_MUX_GPIO46_SLP_SEL_V << IO_MUX_GPIO46_SLP_SEL_S)
-#define IO_MUX_GPIO46_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO46_SLP_SEL_S  1
-/** IO_MUX_GPIO46_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO46_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO46_MCU_WPD_M  (IO_MUX_GPIO46_MCU_WPD_V << IO_MUX_GPIO46_MCU_WPD_S)
-#define IO_MUX_GPIO46_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO46_MCU_WPD_S  2
-/** IO_MUX_GPIO46_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO46_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO46_MCU_WPU_M  (IO_MUX_GPIO46_MCU_WPU_V << IO_MUX_GPIO46_MCU_WPU_S)
-#define IO_MUX_GPIO46_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO46_MCU_WPU_S  3
-/** IO_MUX_GPIO46_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO46_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO46_MCU_IE_M  (IO_MUX_GPIO46_MCU_IE_V << IO_MUX_GPIO46_MCU_IE_S)
-#define IO_MUX_GPIO46_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO46_MCU_IE_S  4
-/** IO_MUX_GPIO46_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO46_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO46_MCU_DRV_M  (IO_MUX_GPIO46_MCU_DRV_V << IO_MUX_GPIO46_MCU_DRV_S)
-#define IO_MUX_GPIO46_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO46_MCU_DRV_S  5
-/** IO_MUX_GPIO46_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO46_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO46_FUN_WPD_M  (IO_MUX_GPIO46_FUN_WPD_V << IO_MUX_GPIO46_FUN_WPD_S)
-#define IO_MUX_GPIO46_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO46_FUN_WPD_S  7
-/** IO_MUX_GPIO46_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO46_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO46_FUN_WPU_M  (IO_MUX_GPIO46_FUN_WPU_V << IO_MUX_GPIO46_FUN_WPU_S)
-#define IO_MUX_GPIO46_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO46_FUN_WPU_S  8
-/** IO_MUX_GPIO46_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO46_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO46_FUN_IE_M  (IO_MUX_GPIO46_FUN_IE_V << IO_MUX_GPIO46_FUN_IE_S)
-#define IO_MUX_GPIO46_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO46_FUN_IE_S  9
-/** IO_MUX_GPIO46_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO46_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO46_FUN_DRV_M  (IO_MUX_GPIO46_FUN_DRV_V << IO_MUX_GPIO46_FUN_DRV_S)
-#define IO_MUX_GPIO46_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO46_FUN_DRV_S  10
-/** IO_MUX_GPIO46_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO46_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO46_MCU_SEL_M  (IO_MUX_GPIO46_MCU_SEL_V << IO_MUX_GPIO46_MCU_SEL_S)
-#define IO_MUX_GPIO46_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO46_MCU_SEL_S  12
-/** IO_MUX_GPIO46_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO46_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO46_FILTER_EN_M  (IO_MUX_GPIO46_FILTER_EN_V << IO_MUX_GPIO46_FILTER_EN_S)
-#define IO_MUX_GPIO46_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO46_FILTER_EN_S  15
-
-/** IO_MUX_gpio47_REG register
- *  iomux control register for gpio47
- */
-#define IO_MUX_GPIO47_REG (DR_REG_IO_MUX_BASE + 0xc0)
-/** IO_MUX_GPIO47_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO47_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO47_MCU_OE_M  (IO_MUX_GPIO47_MCU_OE_V << IO_MUX_GPIO47_MCU_OE_S)
-#define IO_MUX_GPIO47_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO47_MCU_OE_S  0
-/** IO_MUX_GPIO47_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO47_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO47_SLP_SEL_M  (IO_MUX_GPIO47_SLP_SEL_V << IO_MUX_GPIO47_SLP_SEL_S)
-#define IO_MUX_GPIO47_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO47_SLP_SEL_S  1
-/** IO_MUX_GPIO47_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO47_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO47_MCU_WPD_M  (IO_MUX_GPIO47_MCU_WPD_V << IO_MUX_GPIO47_MCU_WPD_S)
-#define IO_MUX_GPIO47_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO47_MCU_WPD_S  2
-/** IO_MUX_GPIO47_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO47_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO47_MCU_WPU_M  (IO_MUX_GPIO47_MCU_WPU_V << IO_MUX_GPIO47_MCU_WPU_S)
-#define IO_MUX_GPIO47_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO47_MCU_WPU_S  3
-/** IO_MUX_GPIO47_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO47_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO47_MCU_IE_M  (IO_MUX_GPIO47_MCU_IE_V << IO_MUX_GPIO47_MCU_IE_S)
-#define IO_MUX_GPIO47_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO47_MCU_IE_S  4
-/** IO_MUX_GPIO47_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO47_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO47_MCU_DRV_M  (IO_MUX_GPIO47_MCU_DRV_V << IO_MUX_GPIO47_MCU_DRV_S)
-#define IO_MUX_GPIO47_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO47_MCU_DRV_S  5
-/** IO_MUX_GPIO47_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO47_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO47_FUN_WPD_M  (IO_MUX_GPIO47_FUN_WPD_V << IO_MUX_GPIO47_FUN_WPD_S)
-#define IO_MUX_GPIO47_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO47_FUN_WPD_S  7
-/** IO_MUX_GPIO47_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO47_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO47_FUN_WPU_M  (IO_MUX_GPIO47_FUN_WPU_V << IO_MUX_GPIO47_FUN_WPU_S)
-#define IO_MUX_GPIO47_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO47_FUN_WPU_S  8
-/** IO_MUX_GPIO47_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO47_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO47_FUN_IE_M  (IO_MUX_GPIO47_FUN_IE_V << IO_MUX_GPIO47_FUN_IE_S)
-#define IO_MUX_GPIO47_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO47_FUN_IE_S  9
-/** IO_MUX_GPIO47_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO47_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO47_FUN_DRV_M  (IO_MUX_GPIO47_FUN_DRV_V << IO_MUX_GPIO47_FUN_DRV_S)
-#define IO_MUX_GPIO47_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO47_FUN_DRV_S  10
-/** IO_MUX_GPIO47_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO47_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO47_MCU_SEL_M  (IO_MUX_GPIO47_MCU_SEL_V << IO_MUX_GPIO47_MCU_SEL_S)
-#define IO_MUX_GPIO47_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO47_MCU_SEL_S  12
-/** IO_MUX_GPIO47_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO47_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO47_FILTER_EN_M  (IO_MUX_GPIO47_FILTER_EN_V << IO_MUX_GPIO47_FILTER_EN_S)
-#define IO_MUX_GPIO47_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO47_FILTER_EN_S  15
-
-/** IO_MUX_gpio48_REG register
- *  iomux control register for gpio48
- */
-#define IO_MUX_GPIO48_REG (DR_REG_IO_MUX_BASE + 0xc4)
-/** IO_MUX_GPIO48_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO48_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO48_MCU_OE_M  (IO_MUX_GPIO48_MCU_OE_V << IO_MUX_GPIO48_MCU_OE_S)
-#define IO_MUX_GPIO48_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO48_MCU_OE_S  0
-/** IO_MUX_GPIO48_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO48_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO48_SLP_SEL_M  (IO_MUX_GPIO48_SLP_SEL_V << IO_MUX_GPIO48_SLP_SEL_S)
-#define IO_MUX_GPIO48_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO48_SLP_SEL_S  1
-/** IO_MUX_GPIO48_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO48_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO48_MCU_WPD_M  (IO_MUX_GPIO48_MCU_WPD_V << IO_MUX_GPIO48_MCU_WPD_S)
-#define IO_MUX_GPIO48_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO48_MCU_WPD_S  2
-/** IO_MUX_GPIO48_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO48_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO48_MCU_WPU_M  (IO_MUX_GPIO48_MCU_WPU_V << IO_MUX_GPIO48_MCU_WPU_S)
-#define IO_MUX_GPIO48_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO48_MCU_WPU_S  3
-/** IO_MUX_GPIO48_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO48_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO48_MCU_IE_M  (IO_MUX_GPIO48_MCU_IE_V << IO_MUX_GPIO48_MCU_IE_S)
-#define IO_MUX_GPIO48_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO48_MCU_IE_S  4
-/** IO_MUX_GPIO48_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO48_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO48_MCU_DRV_M  (IO_MUX_GPIO48_MCU_DRV_V << IO_MUX_GPIO48_MCU_DRV_S)
-#define IO_MUX_GPIO48_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO48_MCU_DRV_S  5
-/** IO_MUX_GPIO48_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO48_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO48_FUN_WPD_M  (IO_MUX_GPIO48_FUN_WPD_V << IO_MUX_GPIO48_FUN_WPD_S)
-#define IO_MUX_GPIO48_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO48_FUN_WPD_S  7
-/** IO_MUX_GPIO48_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO48_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO48_FUN_WPU_M  (IO_MUX_GPIO48_FUN_WPU_V << IO_MUX_GPIO48_FUN_WPU_S)
-#define IO_MUX_GPIO48_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO48_FUN_WPU_S  8
-/** IO_MUX_GPIO48_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO48_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO48_FUN_IE_M  (IO_MUX_GPIO48_FUN_IE_V << IO_MUX_GPIO48_FUN_IE_S)
-#define IO_MUX_GPIO48_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO48_FUN_IE_S  9
-/** IO_MUX_GPIO48_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO48_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO48_FUN_DRV_M  (IO_MUX_GPIO48_FUN_DRV_V << IO_MUX_GPIO48_FUN_DRV_S)
-#define IO_MUX_GPIO48_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO48_FUN_DRV_S  10
-/** IO_MUX_GPIO48_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO48_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO48_MCU_SEL_M  (IO_MUX_GPIO48_MCU_SEL_V << IO_MUX_GPIO48_MCU_SEL_S)
-#define IO_MUX_GPIO48_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO48_MCU_SEL_S  12
-/** IO_MUX_GPIO48_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO48_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO48_FILTER_EN_M  (IO_MUX_GPIO48_FILTER_EN_V << IO_MUX_GPIO48_FILTER_EN_S)
-#define IO_MUX_GPIO48_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO48_FILTER_EN_S  15
-
-/** IO_MUX_gpio49_REG register
- *  iomux control register for gpio49
- */
-#define IO_MUX_GPIO49_REG (DR_REG_IO_MUX_BASE + 0xc8)
-/** IO_MUX_GPIO49_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO49_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO49_MCU_OE_M  (IO_MUX_GPIO49_MCU_OE_V << IO_MUX_GPIO49_MCU_OE_S)
-#define IO_MUX_GPIO49_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO49_MCU_OE_S  0
-/** IO_MUX_GPIO49_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO49_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO49_SLP_SEL_M  (IO_MUX_GPIO49_SLP_SEL_V << IO_MUX_GPIO49_SLP_SEL_S)
-#define IO_MUX_GPIO49_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO49_SLP_SEL_S  1
-/** IO_MUX_GPIO49_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO49_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO49_MCU_WPD_M  (IO_MUX_GPIO49_MCU_WPD_V << IO_MUX_GPIO49_MCU_WPD_S)
-#define IO_MUX_GPIO49_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO49_MCU_WPD_S  2
-/** IO_MUX_GPIO49_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO49_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO49_MCU_WPU_M  (IO_MUX_GPIO49_MCU_WPU_V << IO_MUX_GPIO49_MCU_WPU_S)
-#define IO_MUX_GPIO49_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO49_MCU_WPU_S  3
-/** IO_MUX_GPIO49_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO49_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO49_MCU_IE_M  (IO_MUX_GPIO49_MCU_IE_V << IO_MUX_GPIO49_MCU_IE_S)
-#define IO_MUX_GPIO49_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO49_MCU_IE_S  4
-/** IO_MUX_GPIO49_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO49_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO49_MCU_DRV_M  (IO_MUX_GPIO49_MCU_DRV_V << IO_MUX_GPIO49_MCU_DRV_S)
-#define IO_MUX_GPIO49_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO49_MCU_DRV_S  5
-/** IO_MUX_GPIO49_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO49_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO49_FUN_WPD_M  (IO_MUX_GPIO49_FUN_WPD_V << IO_MUX_GPIO49_FUN_WPD_S)
-#define IO_MUX_GPIO49_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO49_FUN_WPD_S  7
-/** IO_MUX_GPIO49_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO49_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO49_FUN_WPU_M  (IO_MUX_GPIO49_FUN_WPU_V << IO_MUX_GPIO49_FUN_WPU_S)
-#define IO_MUX_GPIO49_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO49_FUN_WPU_S  8
-/** IO_MUX_GPIO49_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO49_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO49_FUN_IE_M  (IO_MUX_GPIO49_FUN_IE_V << IO_MUX_GPIO49_FUN_IE_S)
-#define IO_MUX_GPIO49_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO49_FUN_IE_S  9
-/** IO_MUX_GPIO49_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO49_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO49_FUN_DRV_M  (IO_MUX_GPIO49_FUN_DRV_V << IO_MUX_GPIO49_FUN_DRV_S)
-#define IO_MUX_GPIO49_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO49_FUN_DRV_S  10
-/** IO_MUX_GPIO49_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO49_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO49_MCU_SEL_M  (IO_MUX_GPIO49_MCU_SEL_V << IO_MUX_GPIO49_MCU_SEL_S)
-#define IO_MUX_GPIO49_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO49_MCU_SEL_S  12
-/** IO_MUX_GPIO49_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO49_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO49_FILTER_EN_M  (IO_MUX_GPIO49_FILTER_EN_V << IO_MUX_GPIO49_FILTER_EN_S)
-#define IO_MUX_GPIO49_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO49_FILTER_EN_S  15
-
-/** IO_MUX_gpio50_REG register
- *  iomux control register for gpio50
- */
-#define IO_MUX_GPIO50_REG (DR_REG_IO_MUX_BASE + 0xcc)
-/** IO_MUX_GPIO50_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO50_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO50_MCU_OE_M  (IO_MUX_GPIO50_MCU_OE_V << IO_MUX_GPIO50_MCU_OE_S)
-#define IO_MUX_GPIO50_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO50_MCU_OE_S  0
-/** IO_MUX_GPIO50_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO50_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO50_SLP_SEL_M  (IO_MUX_GPIO50_SLP_SEL_V << IO_MUX_GPIO50_SLP_SEL_S)
-#define IO_MUX_GPIO50_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO50_SLP_SEL_S  1
-/** IO_MUX_GPIO50_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO50_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO50_MCU_WPD_M  (IO_MUX_GPIO50_MCU_WPD_V << IO_MUX_GPIO50_MCU_WPD_S)
-#define IO_MUX_GPIO50_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO50_MCU_WPD_S  2
-/** IO_MUX_GPIO50_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO50_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO50_MCU_WPU_M  (IO_MUX_GPIO50_MCU_WPU_V << IO_MUX_GPIO50_MCU_WPU_S)
-#define IO_MUX_GPIO50_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO50_MCU_WPU_S  3
-/** IO_MUX_GPIO50_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO50_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO50_MCU_IE_M  (IO_MUX_GPIO50_MCU_IE_V << IO_MUX_GPIO50_MCU_IE_S)
-#define IO_MUX_GPIO50_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO50_MCU_IE_S  4
-/** IO_MUX_GPIO50_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO50_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO50_MCU_DRV_M  (IO_MUX_GPIO50_MCU_DRV_V << IO_MUX_GPIO50_MCU_DRV_S)
-#define IO_MUX_GPIO50_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO50_MCU_DRV_S  5
-/** IO_MUX_GPIO50_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO50_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO50_FUN_WPD_M  (IO_MUX_GPIO50_FUN_WPD_V << IO_MUX_GPIO50_FUN_WPD_S)
-#define IO_MUX_GPIO50_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO50_FUN_WPD_S  7
-/** IO_MUX_GPIO50_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO50_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO50_FUN_WPU_M  (IO_MUX_GPIO50_FUN_WPU_V << IO_MUX_GPIO50_FUN_WPU_S)
-#define IO_MUX_GPIO50_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO50_FUN_WPU_S  8
-/** IO_MUX_GPIO50_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO50_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO50_FUN_IE_M  (IO_MUX_GPIO50_FUN_IE_V << IO_MUX_GPIO50_FUN_IE_S)
-#define IO_MUX_GPIO50_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO50_FUN_IE_S  9
-/** IO_MUX_GPIO50_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO50_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO50_FUN_DRV_M  (IO_MUX_GPIO50_FUN_DRV_V << IO_MUX_GPIO50_FUN_DRV_S)
-#define IO_MUX_GPIO50_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO50_FUN_DRV_S  10
-/** IO_MUX_GPIO50_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO50_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO50_MCU_SEL_M  (IO_MUX_GPIO50_MCU_SEL_V << IO_MUX_GPIO50_MCU_SEL_S)
-#define IO_MUX_GPIO50_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO50_MCU_SEL_S  12
-/** IO_MUX_GPIO50_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO50_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO50_FILTER_EN_M  (IO_MUX_GPIO50_FILTER_EN_V << IO_MUX_GPIO50_FILTER_EN_S)
-#define IO_MUX_GPIO50_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO50_FILTER_EN_S  15
-
-/** IO_MUX_gpio51_REG register
- *  iomux control register for gpio51
- */
-#define IO_MUX_GPIO51_REG (DR_REG_IO_MUX_BASE + 0xd0)
-/** IO_MUX_GPIO51_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO51_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO51_MCU_OE_M  (IO_MUX_GPIO51_MCU_OE_V << IO_MUX_GPIO51_MCU_OE_S)
-#define IO_MUX_GPIO51_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO51_MCU_OE_S  0
-/** IO_MUX_GPIO51_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO51_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO51_SLP_SEL_M  (IO_MUX_GPIO51_SLP_SEL_V << IO_MUX_GPIO51_SLP_SEL_S)
-#define IO_MUX_GPIO51_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO51_SLP_SEL_S  1
-/** IO_MUX_GPIO51_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO51_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO51_MCU_WPD_M  (IO_MUX_GPIO51_MCU_WPD_V << IO_MUX_GPIO51_MCU_WPD_S)
-#define IO_MUX_GPIO51_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO51_MCU_WPD_S  2
-/** IO_MUX_GPIO51_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO51_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO51_MCU_WPU_M  (IO_MUX_GPIO51_MCU_WPU_V << IO_MUX_GPIO51_MCU_WPU_S)
-#define IO_MUX_GPIO51_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO51_MCU_WPU_S  3
-/** IO_MUX_GPIO51_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO51_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO51_MCU_IE_M  (IO_MUX_GPIO51_MCU_IE_V << IO_MUX_GPIO51_MCU_IE_S)
-#define IO_MUX_GPIO51_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO51_MCU_IE_S  4
-/** IO_MUX_GPIO51_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO51_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO51_MCU_DRV_M  (IO_MUX_GPIO51_MCU_DRV_V << IO_MUX_GPIO51_MCU_DRV_S)
-#define IO_MUX_GPIO51_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO51_MCU_DRV_S  5
-/** IO_MUX_GPIO51_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO51_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO51_FUN_WPD_M  (IO_MUX_GPIO51_FUN_WPD_V << IO_MUX_GPIO51_FUN_WPD_S)
-#define IO_MUX_GPIO51_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO51_FUN_WPD_S  7
-/** IO_MUX_GPIO51_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO51_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO51_FUN_WPU_M  (IO_MUX_GPIO51_FUN_WPU_V << IO_MUX_GPIO51_FUN_WPU_S)
-#define IO_MUX_GPIO51_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO51_FUN_WPU_S  8
-/** IO_MUX_GPIO51_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO51_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO51_FUN_IE_M  (IO_MUX_GPIO51_FUN_IE_V << IO_MUX_GPIO51_FUN_IE_S)
-#define IO_MUX_GPIO51_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO51_FUN_IE_S  9
-/** IO_MUX_GPIO51_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO51_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO51_FUN_DRV_M  (IO_MUX_GPIO51_FUN_DRV_V << IO_MUX_GPIO51_FUN_DRV_S)
-#define IO_MUX_GPIO51_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO51_FUN_DRV_S  10
-/** IO_MUX_GPIO51_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO51_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO51_MCU_SEL_M  (IO_MUX_GPIO51_MCU_SEL_V << IO_MUX_GPIO51_MCU_SEL_S)
-#define IO_MUX_GPIO51_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO51_MCU_SEL_S  12
-/** IO_MUX_GPIO51_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO51_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO51_FILTER_EN_M  (IO_MUX_GPIO51_FILTER_EN_V << IO_MUX_GPIO51_FILTER_EN_S)
-#define IO_MUX_GPIO51_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO51_FILTER_EN_S  15
-
-/** IO_MUX_gpio52_REG register
- *  iomux control register for gpio52
- */
-#define IO_MUX_GPIO52_REG (DR_REG_IO_MUX_BASE + 0xd4)
-/** IO_MUX_GPIO52_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO52_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO52_MCU_OE_M  (IO_MUX_GPIO52_MCU_OE_V << IO_MUX_GPIO52_MCU_OE_S)
-#define IO_MUX_GPIO52_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO52_MCU_OE_S  0
-/** IO_MUX_GPIO52_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO52_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO52_SLP_SEL_M  (IO_MUX_GPIO52_SLP_SEL_V << IO_MUX_GPIO52_SLP_SEL_S)
-#define IO_MUX_GPIO52_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO52_SLP_SEL_S  1
-/** IO_MUX_GPIO52_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO52_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO52_MCU_WPD_M  (IO_MUX_GPIO52_MCU_WPD_V << IO_MUX_GPIO52_MCU_WPD_S)
-#define IO_MUX_GPIO52_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO52_MCU_WPD_S  2
-/** IO_MUX_GPIO52_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO52_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO52_MCU_WPU_M  (IO_MUX_GPIO52_MCU_WPU_V << IO_MUX_GPIO52_MCU_WPU_S)
-#define IO_MUX_GPIO52_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO52_MCU_WPU_S  3
-/** IO_MUX_GPIO52_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO52_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO52_MCU_IE_M  (IO_MUX_GPIO52_MCU_IE_V << IO_MUX_GPIO52_MCU_IE_S)
-#define IO_MUX_GPIO52_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO52_MCU_IE_S  4
-/** IO_MUX_GPIO52_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO52_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO52_MCU_DRV_M  (IO_MUX_GPIO52_MCU_DRV_V << IO_MUX_GPIO52_MCU_DRV_S)
-#define IO_MUX_GPIO52_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO52_MCU_DRV_S  5
-/** IO_MUX_GPIO52_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO52_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO52_FUN_WPD_M  (IO_MUX_GPIO52_FUN_WPD_V << IO_MUX_GPIO52_FUN_WPD_S)
-#define IO_MUX_GPIO52_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO52_FUN_WPD_S  7
-/** IO_MUX_GPIO52_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO52_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO52_FUN_WPU_M  (IO_MUX_GPIO52_FUN_WPU_V << IO_MUX_GPIO52_FUN_WPU_S)
-#define IO_MUX_GPIO52_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO52_FUN_WPU_S  8
-/** IO_MUX_GPIO52_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO52_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO52_FUN_IE_M  (IO_MUX_GPIO52_FUN_IE_V << IO_MUX_GPIO52_FUN_IE_S)
-#define IO_MUX_GPIO52_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO52_FUN_IE_S  9
-/** IO_MUX_GPIO52_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO52_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO52_FUN_DRV_M  (IO_MUX_GPIO52_FUN_DRV_V << IO_MUX_GPIO52_FUN_DRV_S)
-#define IO_MUX_GPIO52_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO52_FUN_DRV_S  10
-/** IO_MUX_GPIO52_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO52_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO52_MCU_SEL_M  (IO_MUX_GPIO52_MCU_SEL_V << IO_MUX_GPIO52_MCU_SEL_S)
-#define IO_MUX_GPIO52_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO52_MCU_SEL_S  12
-/** IO_MUX_GPIO52_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO52_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO52_FILTER_EN_M  (IO_MUX_GPIO52_FILTER_EN_V << IO_MUX_GPIO52_FILTER_EN_S)
-#define IO_MUX_GPIO52_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO52_FILTER_EN_S  15
-
-/** IO_MUX_gpio53_REG register
- *  iomux control register for gpio53
- */
-#define IO_MUX_GPIO53_REG (DR_REG_IO_MUX_BASE + 0xd8)
-/** IO_MUX_GPIO53_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO53_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO53_MCU_OE_M  (IO_MUX_GPIO53_MCU_OE_V << IO_MUX_GPIO53_MCU_OE_S)
-#define IO_MUX_GPIO53_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO53_MCU_OE_S  0
-/** IO_MUX_GPIO53_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO53_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO53_SLP_SEL_M  (IO_MUX_GPIO53_SLP_SEL_V << IO_MUX_GPIO53_SLP_SEL_S)
-#define IO_MUX_GPIO53_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO53_SLP_SEL_S  1
-/** IO_MUX_GPIO53_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO53_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO53_MCU_WPD_M  (IO_MUX_GPIO53_MCU_WPD_V << IO_MUX_GPIO53_MCU_WPD_S)
-#define IO_MUX_GPIO53_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO53_MCU_WPD_S  2
-/** IO_MUX_GPIO53_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO53_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO53_MCU_WPU_M  (IO_MUX_GPIO53_MCU_WPU_V << IO_MUX_GPIO53_MCU_WPU_S)
-#define IO_MUX_GPIO53_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO53_MCU_WPU_S  3
-/** IO_MUX_GPIO53_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO53_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO53_MCU_IE_M  (IO_MUX_GPIO53_MCU_IE_V << IO_MUX_GPIO53_MCU_IE_S)
-#define IO_MUX_GPIO53_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO53_MCU_IE_S  4
-/** IO_MUX_GPIO53_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO53_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO53_MCU_DRV_M  (IO_MUX_GPIO53_MCU_DRV_V << IO_MUX_GPIO53_MCU_DRV_S)
-#define IO_MUX_GPIO53_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO53_MCU_DRV_S  5
-/** IO_MUX_GPIO53_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO53_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO53_FUN_WPD_M  (IO_MUX_GPIO53_FUN_WPD_V << IO_MUX_GPIO53_FUN_WPD_S)
-#define IO_MUX_GPIO53_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO53_FUN_WPD_S  7
-/** IO_MUX_GPIO53_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO53_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO53_FUN_WPU_M  (IO_MUX_GPIO53_FUN_WPU_V << IO_MUX_GPIO53_FUN_WPU_S)
-#define IO_MUX_GPIO53_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO53_FUN_WPU_S  8
-/** IO_MUX_GPIO53_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO53_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO53_FUN_IE_M  (IO_MUX_GPIO53_FUN_IE_V << IO_MUX_GPIO53_FUN_IE_S)
-#define IO_MUX_GPIO53_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO53_FUN_IE_S  9
-/** IO_MUX_GPIO53_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO53_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO53_FUN_DRV_M  (IO_MUX_GPIO53_FUN_DRV_V << IO_MUX_GPIO53_FUN_DRV_S)
-#define IO_MUX_GPIO53_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO53_FUN_DRV_S  10
-/** IO_MUX_GPIO53_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO53_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO53_MCU_SEL_M  (IO_MUX_GPIO53_MCU_SEL_V << IO_MUX_GPIO53_MCU_SEL_S)
-#define IO_MUX_GPIO53_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO53_MCU_SEL_S  12
-/** IO_MUX_GPIO53_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO53_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO53_FILTER_EN_M  (IO_MUX_GPIO53_FILTER_EN_V << IO_MUX_GPIO53_FILTER_EN_S)
-#define IO_MUX_GPIO53_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO53_FILTER_EN_S  15
-
-/** IO_MUX_gpio54_REG register
- *  iomux control register for gpio54
- */
-#define IO_MUX_GPIO54_REG (DR_REG_IO_MUX_BASE + 0xdc)
-/** IO_MUX_GPIO54_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO54_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO54_MCU_OE_M  (IO_MUX_GPIO54_MCU_OE_V << IO_MUX_GPIO54_MCU_OE_S)
-#define IO_MUX_GPIO54_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO54_MCU_OE_S  0
-/** IO_MUX_GPIO54_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO54_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO54_SLP_SEL_M  (IO_MUX_GPIO54_SLP_SEL_V << IO_MUX_GPIO54_SLP_SEL_S)
-#define IO_MUX_GPIO54_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO54_SLP_SEL_S  1
-/** IO_MUX_GPIO54_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO54_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO54_MCU_WPD_M  (IO_MUX_GPIO54_MCU_WPD_V << IO_MUX_GPIO54_MCU_WPD_S)
-#define IO_MUX_GPIO54_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO54_MCU_WPD_S  2
-/** IO_MUX_GPIO54_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO54_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO54_MCU_WPU_M  (IO_MUX_GPIO54_MCU_WPU_V << IO_MUX_GPIO54_MCU_WPU_S)
-#define IO_MUX_GPIO54_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO54_MCU_WPU_S  3
-/** IO_MUX_GPIO54_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO54_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO54_MCU_IE_M  (IO_MUX_GPIO54_MCU_IE_V << IO_MUX_GPIO54_MCU_IE_S)
-#define IO_MUX_GPIO54_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO54_MCU_IE_S  4
-/** IO_MUX_GPIO54_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO54_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO54_MCU_DRV_M  (IO_MUX_GPIO54_MCU_DRV_V << IO_MUX_GPIO54_MCU_DRV_S)
-#define IO_MUX_GPIO54_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO54_MCU_DRV_S  5
-/** IO_MUX_GPIO54_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO54_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO54_FUN_WPD_M  (IO_MUX_GPIO54_FUN_WPD_V << IO_MUX_GPIO54_FUN_WPD_S)
-#define IO_MUX_GPIO54_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO54_FUN_WPD_S  7
-/** IO_MUX_GPIO54_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO54_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO54_FUN_WPU_M  (IO_MUX_GPIO54_FUN_WPU_V << IO_MUX_GPIO54_FUN_WPU_S)
-#define IO_MUX_GPIO54_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO54_FUN_WPU_S  8
-/** IO_MUX_GPIO54_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO54_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO54_FUN_IE_M  (IO_MUX_GPIO54_FUN_IE_V << IO_MUX_GPIO54_FUN_IE_S)
-#define IO_MUX_GPIO54_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO54_FUN_IE_S  9
-/** IO_MUX_GPIO54_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO54_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO54_FUN_DRV_M  (IO_MUX_GPIO54_FUN_DRV_V << IO_MUX_GPIO54_FUN_DRV_S)
-#define IO_MUX_GPIO54_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO54_FUN_DRV_S  10
-/** IO_MUX_GPIO54_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO54_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO54_MCU_SEL_M  (IO_MUX_GPIO54_MCU_SEL_V << IO_MUX_GPIO54_MCU_SEL_S)
-#define IO_MUX_GPIO54_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO54_MCU_SEL_S  12
-/** IO_MUX_GPIO54_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO54_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO54_FILTER_EN_M  (IO_MUX_GPIO54_FILTER_EN_V << IO_MUX_GPIO54_FILTER_EN_S)
-#define IO_MUX_GPIO54_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO54_FILTER_EN_S  15
-
-/** IO_MUX_gpio55_REG register
- *  iomux control register for gpio55
- */
-#define IO_MUX_GPIO55_REG (DR_REG_IO_MUX_BASE + 0xe0)
-/** IO_MUX_GPIO55_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO55_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO55_MCU_OE_M  (IO_MUX_GPIO55_MCU_OE_V << IO_MUX_GPIO55_MCU_OE_S)
-#define IO_MUX_GPIO55_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO55_MCU_OE_S  0
-/** IO_MUX_GPIO55_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO55_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO55_SLP_SEL_M  (IO_MUX_GPIO55_SLP_SEL_V << IO_MUX_GPIO55_SLP_SEL_S)
-#define IO_MUX_GPIO55_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO55_SLP_SEL_S  1
-/** IO_MUX_GPIO55_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO55_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO55_MCU_WPD_M  (IO_MUX_GPIO55_MCU_WPD_V << IO_MUX_GPIO55_MCU_WPD_S)
-#define IO_MUX_GPIO55_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO55_MCU_WPD_S  2
-/** IO_MUX_GPIO55_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO55_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO55_MCU_WPU_M  (IO_MUX_GPIO55_MCU_WPU_V << IO_MUX_GPIO55_MCU_WPU_S)
-#define IO_MUX_GPIO55_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO55_MCU_WPU_S  3
-/** IO_MUX_GPIO55_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO55_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO55_MCU_IE_M  (IO_MUX_GPIO55_MCU_IE_V << IO_MUX_GPIO55_MCU_IE_S)
-#define IO_MUX_GPIO55_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO55_MCU_IE_S  4
-/** IO_MUX_GPIO55_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO55_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO55_MCU_DRV_M  (IO_MUX_GPIO55_MCU_DRV_V << IO_MUX_GPIO55_MCU_DRV_S)
-#define IO_MUX_GPIO55_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO55_MCU_DRV_S  5
-/** IO_MUX_GPIO55_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO55_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO55_FUN_WPD_M  (IO_MUX_GPIO55_FUN_WPD_V << IO_MUX_GPIO55_FUN_WPD_S)
-#define IO_MUX_GPIO55_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO55_FUN_WPD_S  7
-/** IO_MUX_GPIO55_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO55_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO55_FUN_WPU_M  (IO_MUX_GPIO55_FUN_WPU_V << IO_MUX_GPIO55_FUN_WPU_S)
-#define IO_MUX_GPIO55_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO55_FUN_WPU_S  8
-/** IO_MUX_GPIO55_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO55_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO55_FUN_IE_M  (IO_MUX_GPIO55_FUN_IE_V << IO_MUX_GPIO55_FUN_IE_S)
-#define IO_MUX_GPIO55_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO55_FUN_IE_S  9
-/** IO_MUX_GPIO55_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO55_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO55_FUN_DRV_M  (IO_MUX_GPIO55_FUN_DRV_V << IO_MUX_GPIO55_FUN_DRV_S)
-#define IO_MUX_GPIO55_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO55_FUN_DRV_S  10
-/** IO_MUX_GPIO55_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO55_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO55_MCU_SEL_M  (IO_MUX_GPIO55_MCU_SEL_V << IO_MUX_GPIO55_MCU_SEL_S)
-#define IO_MUX_GPIO55_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO55_MCU_SEL_S  12
-/** IO_MUX_GPIO55_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO55_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO55_FILTER_EN_M  (IO_MUX_GPIO55_FILTER_EN_V << IO_MUX_GPIO55_FILTER_EN_S)
-#define IO_MUX_GPIO55_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO55_FILTER_EN_S  15
-
-/** IO_MUX_gpio56_REG register
- *  iomux control register for gpio56
- */
-#define IO_MUX_GPIO56_REG (DR_REG_IO_MUX_BASE + 0xe4)
-/** IO_MUX_GPIO56_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  output enable on sleep mode
- */
-#define IO_MUX_GPIO56_MCU_OE    (BIT(0))
-#define IO_MUX_GPIO56_MCU_OE_M  (IO_MUX_GPIO56_MCU_OE_V << IO_MUX_GPIO56_MCU_OE_S)
-#define IO_MUX_GPIO56_MCU_OE_V  0x00000001U
-#define IO_MUX_GPIO56_MCU_OE_S  0
-/** IO_MUX_GPIO56_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  io sleep mode enable. set 1 to enable sleep mode.
- */
-#define IO_MUX_GPIO56_SLP_SEL    (BIT(1))
-#define IO_MUX_GPIO56_SLP_SEL_M  (IO_MUX_GPIO56_SLP_SEL_V << IO_MUX_GPIO56_SLP_SEL_S)
-#define IO_MUX_GPIO56_SLP_SEL_V  0x00000001U
-#define IO_MUX_GPIO56_SLP_SEL_S  1
-/** IO_MUX_GPIO56_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  pull-down enable on sleep mode
- */
-#define IO_MUX_GPIO56_MCU_WPD    (BIT(2))
-#define IO_MUX_GPIO56_MCU_WPD_M  (IO_MUX_GPIO56_MCU_WPD_V << IO_MUX_GPIO56_MCU_WPD_S)
-#define IO_MUX_GPIO56_MCU_WPD_V  0x00000001U
-#define IO_MUX_GPIO56_MCU_WPD_S  2
-/** IO_MUX_GPIO56_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  pull-up enable on sleep mode
- */
-#define IO_MUX_GPIO56_MCU_WPU    (BIT(3))
-#define IO_MUX_GPIO56_MCU_WPU_M  (IO_MUX_GPIO56_MCU_WPU_V << IO_MUX_GPIO56_MCU_WPU_S)
-#define IO_MUX_GPIO56_MCU_WPU_V  0x00000001U
-#define IO_MUX_GPIO56_MCU_WPU_S  3
-/** IO_MUX_GPIO56_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  input enable on sleep mode
- */
-#define IO_MUX_GPIO56_MCU_IE    (BIT(4))
-#define IO_MUX_GPIO56_MCU_IE_M  (IO_MUX_GPIO56_MCU_IE_V << IO_MUX_GPIO56_MCU_IE_S)
-#define IO_MUX_GPIO56_MCU_IE_V  0x00000001U
-#define IO_MUX_GPIO56_MCU_IE_S  4
-/** IO_MUX_GPIO56_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  select drive strength on sleep mode
- */
-#define IO_MUX_GPIO56_MCU_DRV    0x00000003U
-#define IO_MUX_GPIO56_MCU_DRV_M  (IO_MUX_GPIO56_MCU_DRV_V << IO_MUX_GPIO56_MCU_DRV_S)
-#define IO_MUX_GPIO56_MCU_DRV_V  0x00000003U
-#define IO_MUX_GPIO56_MCU_DRV_S  5
-/** IO_MUX_GPIO56_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  pull-down enable
- */
-#define IO_MUX_GPIO56_FUN_WPD    (BIT(7))
-#define IO_MUX_GPIO56_FUN_WPD_M  (IO_MUX_GPIO56_FUN_WPD_V << IO_MUX_GPIO56_FUN_WPD_S)
-#define IO_MUX_GPIO56_FUN_WPD_V  0x00000001U
-#define IO_MUX_GPIO56_FUN_WPD_S  7
-/** IO_MUX_GPIO56_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  pull-up enable
- */
-#define IO_MUX_GPIO56_FUN_WPU    (BIT(8))
-#define IO_MUX_GPIO56_FUN_WPU_M  (IO_MUX_GPIO56_FUN_WPU_V << IO_MUX_GPIO56_FUN_WPU_S)
-#define IO_MUX_GPIO56_FUN_WPU_V  0x00000001U
-#define IO_MUX_GPIO56_FUN_WPU_S  8
-/** IO_MUX_GPIO56_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  input enable
- */
-#define IO_MUX_GPIO56_FUN_IE    (BIT(9))
-#define IO_MUX_GPIO56_FUN_IE_M  (IO_MUX_GPIO56_FUN_IE_V << IO_MUX_GPIO56_FUN_IE_S)
-#define IO_MUX_GPIO56_FUN_IE_V  0x00000001U
-#define IO_MUX_GPIO56_FUN_IE_S  9
-/** IO_MUX_GPIO56_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
- *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
- */
-#define IO_MUX_GPIO56_FUN_DRV    0x00000003U
-#define IO_MUX_GPIO56_FUN_DRV_M  (IO_MUX_GPIO56_FUN_DRV_V << IO_MUX_GPIO56_FUN_DRV_S)
-#define IO_MUX_GPIO56_FUN_DRV_V  0x00000003U
-#define IO_MUX_GPIO56_FUN_DRV_S  10
-/** IO_MUX_GPIO56_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  0:select function0, 1:select function1 ...
- */
-#define IO_MUX_GPIO56_MCU_SEL    0x00000007U
-#define IO_MUX_GPIO56_MCU_SEL_M  (IO_MUX_GPIO56_MCU_SEL_V << IO_MUX_GPIO56_MCU_SEL_S)
-#define IO_MUX_GPIO56_MCU_SEL_V  0x00000007U
-#define IO_MUX_GPIO56_MCU_SEL_S  12
-/** IO_MUX_GPIO56_FILTER_EN : R/W; bitpos: [15]; default: 0;
- *  input filter enable
- */
-#define IO_MUX_GPIO56_FILTER_EN    (BIT(15))
-#define IO_MUX_GPIO56_FILTER_EN_M  (IO_MUX_GPIO56_FILTER_EN_V << IO_MUX_GPIO56_FILTER_EN_S)
-#define IO_MUX_GPIO56_FILTER_EN_V  0x00000001U
-#define IO_MUX_GPIO56_FILTER_EN_S  15
-
-/** IO_MUX_DATE_REG register
- *  iomux version
- */
-#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0x104)
-/** IO_MUX_DATE : R/W; bitpos: [27:0]; default: 2101794;
- *  csv date
- */
-#define IO_MUX_DATE    0x0FFFFFFFU
-#define IO_MUX_DATE_M  (IO_MUX_DATE_V << IO_MUX_DATE_S)
-#define IO_MUX_DATE_V  0x0FFFFFFFU
-#define IO_MUX_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_struct.h
deleted file mode 100644
index 0ebee78c3498..000000000000
--- a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_struct.h
+++ /dev/null
@@ -1,3430 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: IOMUX Register */
-/** Type of gpio0 register
- *  iomux control register for gpio0
- */
-typedef union {
-    struct {
-        /** gpio0_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio0_mcu_oe:1;
-        /** gpio0_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio0_slp_sel:1;
-        /** gpio0_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio0_mcu_wpd:1;
-        /** gpio0_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio0_mcu_wpu:1;
-        /** gpio0_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio0_mcu_ie:1;
-        /** gpio0_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio0_mcu_drv:2;
-        /** gpio0_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio0_fun_wpd:1;
-        /** gpio0_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio0_fun_wpu:1;
-        /** gpio0_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio0_fun_ie:1;
-        /** gpio0_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio0_fun_drv:2;
-        /** gpio0_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio0_mcu_sel:3;
-        /** gpio0_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio0_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio0_reg_t;
-
-/** Type of gpio1 register
- *  iomux control register for gpio1
- */
-typedef union {
-    struct {
-        /** gpio1_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio1_mcu_oe:1;
-        /** gpio1_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio1_slp_sel:1;
-        /** gpio1_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio1_mcu_wpd:1;
-        /** gpio1_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio1_mcu_wpu:1;
-        /** gpio1_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio1_mcu_ie:1;
-        /** gpio1_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio1_mcu_drv:2;
-        /** gpio1_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio1_fun_wpd:1;
-        /** gpio1_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio1_fun_wpu:1;
-        /** gpio1_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio1_fun_ie:1;
-        /** gpio1_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio1_fun_drv:2;
-        /** gpio1_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio1_mcu_sel:3;
-        /** gpio1_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio1_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio1_reg_t;
-
-/** Type of gpio2 register
- *  iomux control register for gpio2
- */
-typedef union {
-    struct {
-        /** gpio2_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio2_mcu_oe:1;
-        /** gpio2_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio2_slp_sel:1;
-        /** gpio2_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio2_mcu_wpd:1;
-        /** gpio2_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio2_mcu_wpu:1;
-        /** gpio2_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio2_mcu_ie:1;
-        /** gpio2_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio2_mcu_drv:2;
-        /** gpio2_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio2_fun_wpd:1;
-        /** gpio2_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio2_fun_wpu:1;
-        /** gpio2_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio2_fun_ie:1;
-        /** gpio2_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio2_fun_drv:2;
-        /** gpio2_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio2_mcu_sel:3;
-        /** gpio2_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio2_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio2_reg_t;
-
-/** Type of gpio3 register
- *  iomux control register for gpio3
- */
-typedef union {
-    struct {
-        /** gpio3_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio3_mcu_oe:1;
-        /** gpio3_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio3_slp_sel:1;
-        /** gpio3_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio3_mcu_wpd:1;
-        /** gpio3_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio3_mcu_wpu:1;
-        /** gpio3_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio3_mcu_ie:1;
-        /** gpio3_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio3_mcu_drv:2;
-        /** gpio3_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio3_fun_wpd:1;
-        /** gpio3_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio3_fun_wpu:1;
-        /** gpio3_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio3_fun_ie:1;
-        /** gpio3_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio3_fun_drv:2;
-        /** gpio3_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio3_mcu_sel:3;
-        /** gpio3_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio3_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio3_reg_t;
-
-/** Type of gpio4 register
- *  iomux control register for gpio4
- */
-typedef union {
-    struct {
-        /** gpio4_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio4_mcu_oe:1;
-        /** gpio4_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio4_slp_sel:1;
-        /** gpio4_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio4_mcu_wpd:1;
-        /** gpio4_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio4_mcu_wpu:1;
-        /** gpio4_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio4_mcu_ie:1;
-        /** gpio4_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio4_mcu_drv:2;
-        /** gpio4_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio4_fun_wpd:1;
-        /** gpio4_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio4_fun_wpu:1;
-        /** gpio4_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio4_fun_ie:1;
-        /** gpio4_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio4_fun_drv:2;
-        /** gpio4_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio4_mcu_sel:3;
-        /** gpio4_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio4_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio4_reg_t;
-
-/** Type of gpio5 register
- *  iomux control register for gpio5
- */
-typedef union {
-    struct {
-        /** gpio5_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio5_mcu_oe:1;
-        /** gpio5_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio5_slp_sel:1;
-        /** gpio5_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio5_mcu_wpd:1;
-        /** gpio5_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio5_mcu_wpu:1;
-        /** gpio5_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio5_mcu_ie:1;
-        /** gpio5_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio5_mcu_drv:2;
-        /** gpio5_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio5_fun_wpd:1;
-        /** gpio5_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio5_fun_wpu:1;
-        /** gpio5_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio5_fun_ie:1;
-        /** gpio5_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio5_fun_drv:2;
-        /** gpio5_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio5_mcu_sel:3;
-        /** gpio5_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio5_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio5_reg_t;
-
-/** Type of gpio6 register
- *  iomux control register for gpio6
- */
-typedef union {
-    struct {
-        /** gpio6_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio6_mcu_oe:1;
-        /** gpio6_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio6_slp_sel:1;
-        /** gpio6_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio6_mcu_wpd:1;
-        /** gpio6_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio6_mcu_wpu:1;
-        /** gpio6_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio6_mcu_ie:1;
-        /** gpio6_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio6_mcu_drv:2;
-        /** gpio6_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio6_fun_wpd:1;
-        /** gpio6_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio6_fun_wpu:1;
-        /** gpio6_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio6_fun_ie:1;
-        /** gpio6_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio6_fun_drv:2;
-        /** gpio6_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio6_mcu_sel:3;
-        /** gpio6_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio6_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio6_reg_t;
-
-/** Type of gpio7 register
- *  iomux control register for gpio7
- */
-typedef union {
-    struct {
-        /** gpio7_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio7_mcu_oe:1;
-        /** gpio7_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio7_slp_sel:1;
-        /** gpio7_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio7_mcu_wpd:1;
-        /** gpio7_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio7_mcu_wpu:1;
-        /** gpio7_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio7_mcu_ie:1;
-        /** gpio7_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio7_mcu_drv:2;
-        /** gpio7_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio7_fun_wpd:1;
-        /** gpio7_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio7_fun_wpu:1;
-        /** gpio7_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio7_fun_ie:1;
-        /** gpio7_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio7_fun_drv:2;
-        /** gpio7_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio7_mcu_sel:3;
-        /** gpio7_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio7_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio7_reg_t;
-
-/** Type of gpio8 register
- *  iomux control register for gpio8
- */
-typedef union {
-    struct {
-        /** gpio8_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio8_mcu_oe:1;
-        /** gpio8_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio8_slp_sel:1;
-        /** gpio8_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio8_mcu_wpd:1;
-        /** gpio8_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio8_mcu_wpu:1;
-        /** gpio8_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio8_mcu_ie:1;
-        /** gpio8_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio8_mcu_drv:2;
-        /** gpio8_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio8_fun_wpd:1;
-        /** gpio8_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio8_fun_wpu:1;
-        /** gpio8_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio8_fun_ie:1;
-        /** gpio8_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio8_fun_drv:2;
-        /** gpio8_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio8_mcu_sel:3;
-        /** gpio8_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio8_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio8_reg_t;
-
-/** Type of gpio9 register
- *  iomux control register for gpio9
- */
-typedef union {
-    struct {
-        /** gpio9_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio9_mcu_oe:1;
-        /** gpio9_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio9_slp_sel:1;
-        /** gpio9_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio9_mcu_wpd:1;
-        /** gpio9_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio9_mcu_wpu:1;
-        /** gpio9_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio9_mcu_ie:1;
-        /** gpio9_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio9_mcu_drv:2;
-        /** gpio9_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio9_fun_wpd:1;
-        /** gpio9_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio9_fun_wpu:1;
-        /** gpio9_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio9_fun_ie:1;
-        /** gpio9_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio9_fun_drv:2;
-        /** gpio9_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio9_mcu_sel:3;
-        /** gpio9_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio9_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio9_reg_t;
-
-/** Type of gpio10 register
- *  iomux control register for gpio10
- */
-typedef union {
-    struct {
-        /** gpio10_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio10_mcu_oe:1;
-        /** gpio10_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio10_slp_sel:1;
-        /** gpio10_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio10_mcu_wpd:1;
-        /** gpio10_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio10_mcu_wpu:1;
-        /** gpio10_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio10_mcu_ie:1;
-        /** gpio10_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio10_mcu_drv:2;
-        /** gpio10_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio10_fun_wpd:1;
-        /** gpio10_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio10_fun_wpu:1;
-        /** gpio10_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio10_fun_ie:1;
-        /** gpio10_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio10_fun_drv:2;
-        /** gpio10_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio10_mcu_sel:3;
-        /** gpio10_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio10_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio10_reg_t;
-
-/** Type of gpio11 register
- *  iomux control register for gpio11
- */
-typedef union {
-    struct {
-        /** gpio11_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio11_mcu_oe:1;
-        /** gpio11_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio11_slp_sel:1;
-        /** gpio11_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio11_mcu_wpd:1;
-        /** gpio11_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio11_mcu_wpu:1;
-        /** gpio11_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio11_mcu_ie:1;
-        /** gpio11_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio11_mcu_drv:2;
-        /** gpio11_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio11_fun_wpd:1;
-        /** gpio11_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio11_fun_wpu:1;
-        /** gpio11_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio11_fun_ie:1;
-        /** gpio11_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio11_fun_drv:2;
-        /** gpio11_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio11_mcu_sel:3;
-        /** gpio11_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio11_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio11_reg_t;
-
-/** Type of gpio12 register
- *  iomux control register for gpio12
- */
-typedef union {
-    struct {
-        /** gpio12_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio12_mcu_oe:1;
-        /** gpio12_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio12_slp_sel:1;
-        /** gpio12_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio12_mcu_wpd:1;
-        /** gpio12_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio12_mcu_wpu:1;
-        /** gpio12_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio12_mcu_ie:1;
-        /** gpio12_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio12_mcu_drv:2;
-        /** gpio12_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio12_fun_wpd:1;
-        /** gpio12_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio12_fun_wpu:1;
-        /** gpio12_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio12_fun_ie:1;
-        /** gpio12_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio12_fun_drv:2;
-        /** gpio12_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio12_mcu_sel:3;
-        /** gpio12_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio12_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio12_reg_t;
-
-/** Type of gpio13 register
- *  iomux control register for gpio13
- */
-typedef union {
-    struct {
-        /** gpio13_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio13_mcu_oe:1;
-        /** gpio13_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio13_slp_sel:1;
-        /** gpio13_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio13_mcu_wpd:1;
-        /** gpio13_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio13_mcu_wpu:1;
-        /** gpio13_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio13_mcu_ie:1;
-        /** gpio13_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio13_mcu_drv:2;
-        /** gpio13_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio13_fun_wpd:1;
-        /** gpio13_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio13_fun_wpu:1;
-        /** gpio13_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio13_fun_ie:1;
-        /** gpio13_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio13_fun_drv:2;
-        /** gpio13_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio13_mcu_sel:3;
-        /** gpio13_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio13_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio13_reg_t;
-
-/** Type of gpio14 register
- *  iomux control register for gpio14
- */
-typedef union {
-    struct {
-        /** gpio14_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio14_mcu_oe:1;
-        /** gpio14_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio14_slp_sel:1;
-        /** gpio14_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio14_mcu_wpd:1;
-        /** gpio14_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio14_mcu_wpu:1;
-        /** gpio14_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio14_mcu_ie:1;
-        /** gpio14_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio14_mcu_drv:2;
-        /** gpio14_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio14_fun_wpd:1;
-        /** gpio14_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio14_fun_wpu:1;
-        /** gpio14_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio14_fun_ie:1;
-        /** gpio14_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio14_fun_drv:2;
-        /** gpio14_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio14_mcu_sel:3;
-        /** gpio14_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio14_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio14_reg_t;
-
-/** Type of gpio15 register
- *  iomux control register for gpio15
- */
-typedef union {
-    struct {
-        /** gpio15_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio15_mcu_oe:1;
-        /** gpio15_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio15_slp_sel:1;
-        /** gpio15_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio15_mcu_wpd:1;
-        /** gpio15_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio15_mcu_wpu:1;
-        /** gpio15_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio15_mcu_ie:1;
-        /** gpio15_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio15_mcu_drv:2;
-        /** gpio15_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio15_fun_wpd:1;
-        /** gpio15_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio15_fun_wpu:1;
-        /** gpio15_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio15_fun_ie:1;
-        /** gpio15_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio15_fun_drv:2;
-        /** gpio15_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio15_mcu_sel:3;
-        /** gpio15_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio15_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio15_reg_t;
-
-/** Type of gpio16 register
- *  iomux control register for gpio16
- */
-typedef union {
-    struct {
-        /** gpio16_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio16_mcu_oe:1;
-        /** gpio16_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio16_slp_sel:1;
-        /** gpio16_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio16_mcu_wpd:1;
-        /** gpio16_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio16_mcu_wpu:1;
-        /** gpio16_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio16_mcu_ie:1;
-        /** gpio16_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio16_mcu_drv:2;
-        /** gpio16_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio16_fun_wpd:1;
-        /** gpio16_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio16_fun_wpu:1;
-        /** gpio16_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio16_fun_ie:1;
-        /** gpio16_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio16_fun_drv:2;
-        /** gpio16_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio16_mcu_sel:3;
-        /** gpio16_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio16_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio16_reg_t;
-
-/** Type of gpio17 register
- *  iomux control register for gpio17
- */
-typedef union {
-    struct {
-        /** gpio17_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio17_mcu_oe:1;
-        /** gpio17_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio17_slp_sel:1;
-        /** gpio17_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio17_mcu_wpd:1;
-        /** gpio17_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio17_mcu_wpu:1;
-        /** gpio17_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio17_mcu_ie:1;
-        /** gpio17_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio17_mcu_drv:2;
-        /** gpio17_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio17_fun_wpd:1;
-        /** gpio17_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio17_fun_wpu:1;
-        /** gpio17_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio17_fun_ie:1;
-        /** gpio17_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio17_fun_drv:2;
-        /** gpio17_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio17_mcu_sel:3;
-        /** gpio17_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio17_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio17_reg_t;
-
-/** Type of gpio18 register
- *  iomux control register for gpio18
- */
-typedef union {
-    struct {
-        /** gpio18_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio18_mcu_oe:1;
-        /** gpio18_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio18_slp_sel:1;
-        /** gpio18_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio18_mcu_wpd:1;
-        /** gpio18_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio18_mcu_wpu:1;
-        /** gpio18_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio18_mcu_ie:1;
-        /** gpio18_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio18_mcu_drv:2;
-        /** gpio18_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio18_fun_wpd:1;
-        /** gpio18_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio18_fun_wpu:1;
-        /** gpio18_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio18_fun_ie:1;
-        /** gpio18_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio18_fun_drv:2;
-        /** gpio18_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio18_mcu_sel:3;
-        /** gpio18_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio18_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio18_reg_t;
-
-/** Type of gpio19 register
- *  iomux control register for gpio19
- */
-typedef union {
-    struct {
-        /** gpio19_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio19_mcu_oe:1;
-        /** gpio19_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio19_slp_sel:1;
-        /** gpio19_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio19_mcu_wpd:1;
-        /** gpio19_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio19_mcu_wpu:1;
-        /** gpio19_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio19_mcu_ie:1;
-        /** gpio19_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio19_mcu_drv:2;
-        /** gpio19_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio19_fun_wpd:1;
-        /** gpio19_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio19_fun_wpu:1;
-        /** gpio19_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio19_fun_ie:1;
-        /** gpio19_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio19_fun_drv:2;
-        /** gpio19_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio19_mcu_sel:3;
-        /** gpio19_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio19_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio19_reg_t;
-
-/** Type of gpio20 register
- *  iomux control register for gpio20
- */
-typedef union {
-    struct {
-        /** gpio20_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio20_mcu_oe:1;
-        /** gpio20_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio20_slp_sel:1;
-        /** gpio20_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio20_mcu_wpd:1;
-        /** gpio20_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio20_mcu_wpu:1;
-        /** gpio20_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio20_mcu_ie:1;
-        /** gpio20_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio20_mcu_drv:2;
-        /** gpio20_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio20_fun_wpd:1;
-        /** gpio20_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio20_fun_wpu:1;
-        /** gpio20_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio20_fun_ie:1;
-        /** gpio20_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio20_fun_drv:2;
-        /** gpio20_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio20_mcu_sel:3;
-        /** gpio20_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio20_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio20_reg_t;
-
-/** Type of gpio21 register
- *  iomux control register for gpio21
- */
-typedef union {
-    struct {
-        /** gpio21_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio21_mcu_oe:1;
-        /** gpio21_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio21_slp_sel:1;
-        /** gpio21_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio21_mcu_wpd:1;
-        /** gpio21_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio21_mcu_wpu:1;
-        /** gpio21_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio21_mcu_ie:1;
-        /** gpio21_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio21_mcu_drv:2;
-        /** gpio21_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio21_fun_wpd:1;
-        /** gpio21_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio21_fun_wpu:1;
-        /** gpio21_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio21_fun_ie:1;
-        /** gpio21_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio21_fun_drv:2;
-        /** gpio21_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio21_mcu_sel:3;
-        /** gpio21_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio21_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio21_reg_t;
-
-/** Type of gpio22 register
- *  iomux control register for gpio22
- */
-typedef union {
-    struct {
-        /** gpio22_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio22_mcu_oe:1;
-        /** gpio22_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio22_slp_sel:1;
-        /** gpio22_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio22_mcu_wpd:1;
-        /** gpio22_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio22_mcu_wpu:1;
-        /** gpio22_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio22_mcu_ie:1;
-        /** gpio22_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio22_mcu_drv:2;
-        /** gpio22_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio22_fun_wpd:1;
-        /** gpio22_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio22_fun_wpu:1;
-        /** gpio22_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio22_fun_ie:1;
-        /** gpio22_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio22_fun_drv:2;
-        /** gpio22_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio22_mcu_sel:3;
-        /** gpio22_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio22_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio22_reg_t;
-
-/** Type of gpio23 register
- *  iomux control register for gpio23
- */
-typedef union {
-    struct {
-        /** gpio23_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio23_mcu_oe:1;
-        /** gpio23_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio23_slp_sel:1;
-        /** gpio23_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio23_mcu_wpd:1;
-        /** gpio23_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio23_mcu_wpu:1;
-        /** gpio23_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio23_mcu_ie:1;
-        /** gpio23_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio23_mcu_drv:2;
-        /** gpio23_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio23_fun_wpd:1;
-        /** gpio23_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio23_fun_wpu:1;
-        /** gpio23_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio23_fun_ie:1;
-        /** gpio23_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio23_fun_drv:2;
-        /** gpio23_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio23_mcu_sel:3;
-        /** gpio23_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio23_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio23_reg_t;
-
-/** Type of gpio24 register
- *  iomux control register for gpio24
- */
-typedef union {
-    struct {
-        /** gpio24_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio24_mcu_oe:1;
-        /** gpio24_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio24_slp_sel:1;
-        /** gpio24_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio24_mcu_wpd:1;
-        /** gpio24_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio24_mcu_wpu:1;
-        /** gpio24_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio24_mcu_ie:1;
-        /** gpio24_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio24_mcu_drv:2;
-        /** gpio24_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio24_fun_wpd:1;
-        /** gpio24_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio24_fun_wpu:1;
-        /** gpio24_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio24_fun_ie:1;
-        /** gpio24_fun_drv : R/W; bitpos: [11:10]; default: 3;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio24_fun_drv:2;
-        /** gpio24_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio24_mcu_sel:3;
-        /** gpio24_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio24_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio24_reg_t;
-
-/** Type of gpio25 register
- *  iomux control register for gpio25
- */
-typedef union {
-    struct {
-        /** gpio25_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio25_mcu_oe:1;
-        /** gpio25_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio25_slp_sel:1;
-        /** gpio25_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio25_mcu_wpd:1;
-        /** gpio25_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio25_mcu_wpu:1;
-        /** gpio25_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio25_mcu_ie:1;
-        /** gpio25_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio25_mcu_drv:2;
-        /** gpio25_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio25_fun_wpd:1;
-        /** gpio25_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio25_fun_wpu:1;
-        /** gpio25_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio25_fun_ie:1;
-        /** gpio25_fun_drv : R/W; bitpos: [11:10]; default: 3;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio25_fun_drv:2;
-        /** gpio25_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio25_mcu_sel:3;
-        /** gpio25_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio25_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio25_reg_t;
-
-/** Type of gpio26 register
- *  iomux control register for gpio26
- */
-typedef union {
-    struct {
-        /** gpio26_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio26_mcu_oe:1;
-        /** gpio26_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio26_slp_sel:1;
-        /** gpio26_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio26_mcu_wpd:1;
-        /** gpio26_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio26_mcu_wpu:1;
-        /** gpio26_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio26_mcu_ie:1;
-        /** gpio26_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio26_mcu_drv:2;
-        /** gpio26_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio26_fun_wpd:1;
-        /** gpio26_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio26_fun_wpu:1;
-        /** gpio26_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio26_fun_ie:1;
-        /** gpio26_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio26_fun_drv:2;
-        /** gpio26_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio26_mcu_sel:3;
-        /** gpio26_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio26_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio26_reg_t;
-
-/** Type of gpio27 register
- *  iomux control register for gpio27
- */
-typedef union {
-    struct {
-        /** gpio27_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio27_mcu_oe:1;
-        /** gpio27_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio27_slp_sel:1;
-        /** gpio27_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio27_mcu_wpd:1;
-        /** gpio27_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio27_mcu_wpu:1;
-        /** gpio27_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio27_mcu_ie:1;
-        /** gpio27_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio27_mcu_drv:2;
-        /** gpio27_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio27_fun_wpd:1;
-        /** gpio27_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio27_fun_wpu:1;
-        /** gpio27_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio27_fun_ie:1;
-        /** gpio27_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio27_fun_drv:2;
-        /** gpio27_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio27_mcu_sel:3;
-        /** gpio27_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio27_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio27_reg_t;
-
-/** Type of gpio28 register
- *  iomux control register for gpio28
- */
-typedef union {
-    struct {
-        /** gpio28_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio28_mcu_oe:1;
-        /** gpio28_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio28_slp_sel:1;
-        /** gpio28_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio28_mcu_wpd:1;
-        /** gpio28_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio28_mcu_wpu:1;
-        /** gpio28_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio28_mcu_ie:1;
-        /** gpio28_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio28_mcu_drv:2;
-        /** gpio28_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio28_fun_wpd:1;
-        /** gpio28_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio28_fun_wpu:1;
-        /** gpio28_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio28_fun_ie:1;
-        /** gpio28_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio28_fun_drv:2;
-        /** gpio28_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio28_mcu_sel:3;
-        /** gpio28_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio28_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio28_reg_t;
-
-/** Type of gpio29 register
- *  iomux control register for gpio29
- */
-typedef union {
-    struct {
-        /** gpio29_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio29_mcu_oe:1;
-        /** gpio29_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio29_slp_sel:1;
-        /** gpio29_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio29_mcu_wpd:1;
-        /** gpio29_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio29_mcu_wpu:1;
-        /** gpio29_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio29_mcu_ie:1;
-        /** gpio29_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio29_mcu_drv:2;
-        /** gpio29_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio29_fun_wpd:1;
-        /** gpio29_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio29_fun_wpu:1;
-        /** gpio29_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio29_fun_ie:1;
-        /** gpio29_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio29_fun_drv:2;
-        /** gpio29_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio29_mcu_sel:3;
-        /** gpio29_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio29_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio29_reg_t;
-
-/** Type of gpio30 register
- *  iomux control register for gpio30
- */
-typedef union {
-    struct {
-        /** gpio30_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio30_mcu_oe:1;
-        /** gpio30_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio30_slp_sel:1;
-        /** gpio30_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio30_mcu_wpd:1;
-        /** gpio30_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio30_mcu_wpu:1;
-        /** gpio30_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio30_mcu_ie:1;
-        /** gpio30_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio30_mcu_drv:2;
-        /** gpio30_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio30_fun_wpd:1;
-        /** gpio30_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio30_fun_wpu:1;
-        /** gpio30_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio30_fun_ie:1;
-        /** gpio30_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio30_fun_drv:2;
-        /** gpio30_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio30_mcu_sel:3;
-        /** gpio30_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio30_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio30_reg_t;
-
-/** Type of gpio31 register
- *  iomux control register for gpio31
- */
-typedef union {
-    struct {
-        /** gpio31_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio31_mcu_oe:1;
-        /** gpio31_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio31_slp_sel:1;
-        /** gpio31_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio31_mcu_wpd:1;
-        /** gpio31_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio31_mcu_wpu:1;
-        /** gpio31_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio31_mcu_ie:1;
-        /** gpio31_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio31_mcu_drv:2;
-        /** gpio31_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio31_fun_wpd:1;
-        /** gpio31_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio31_fun_wpu:1;
-        /** gpio31_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio31_fun_ie:1;
-        /** gpio31_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio31_fun_drv:2;
-        /** gpio31_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio31_mcu_sel:3;
-        /** gpio31_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio31_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio31_reg_t;
-
-/** Type of gpio32 register
- *  iomux control register for gpio32
- */
-typedef union {
-    struct {
-        /** gpio32_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio32_mcu_oe:1;
-        /** gpio32_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio32_slp_sel:1;
-        /** gpio32_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio32_mcu_wpd:1;
-        /** gpio32_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio32_mcu_wpu:1;
-        /** gpio32_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio32_mcu_ie:1;
-        /** gpio32_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio32_mcu_drv:2;
-        /** gpio32_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio32_fun_wpd:1;
-        /** gpio32_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio32_fun_wpu:1;
-        /** gpio32_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio32_fun_ie:1;
-        /** gpio32_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio32_fun_drv:2;
-        /** gpio32_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio32_mcu_sel:3;
-        /** gpio32_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio32_filter_en:1;
-        /** gpio32_rue_i3c : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t gpio32_rue_i3c:1;
-        /** gpio32_ru_i3c : R/W; bitpos: [18:17]; default: 0;
-         *  NA
-         */
-        uint32_t gpio32_ru_i3c:2;
-        /** gpio32_rue_sel_i3c : R/W; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t gpio32_rue_sel_i3c:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} io_mux_gpio32_reg_t;
-
-/** Type of gpio33 register
- *  iomux control register for gpio33
- */
-typedef union {
-    struct {
-        /** gpio33_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio33_mcu_oe:1;
-        /** gpio33_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio33_slp_sel:1;
-        /** gpio33_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio33_mcu_wpd:1;
-        /** gpio33_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio33_mcu_wpu:1;
-        /** gpio33_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio33_mcu_ie:1;
-        /** gpio33_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio33_mcu_drv:2;
-        /** gpio33_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio33_fun_wpd:1;
-        /** gpio33_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio33_fun_wpu:1;
-        /** gpio33_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio33_fun_ie:1;
-        /** gpio33_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio33_fun_drv:2;
-        /** gpio33_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio33_mcu_sel:3;
-        /** gpio33_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio33_filter_en:1;
-        /** gpio33_rue_i3c : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t gpio33_rue_i3c:1;
-        /** gpio33_ru_i3c : R/W; bitpos: [18:17]; default: 0;
-         *  NA
-         */
-        uint32_t gpio33_ru_i3c:2;
-        /** gpio33_rue_sel_i3c : R/W; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t gpio33_rue_sel_i3c:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} io_mux_gpio33_reg_t;
-
-/** Type of gpio34 register
- *  iomux control register for gpio34
- */
-typedef union {
-    struct {
-        /** gpio34_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio34_mcu_oe:1;
-        /** gpio34_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio34_slp_sel:1;
-        /** gpio34_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio34_mcu_wpd:1;
-        /** gpio34_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio34_mcu_wpu:1;
-        /** gpio34_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio34_mcu_ie:1;
-        /** gpio34_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio34_mcu_drv:2;
-        /** gpio34_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio34_fun_wpd:1;
-        /** gpio34_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio34_fun_wpu:1;
-        /** gpio34_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio34_fun_ie:1;
-        /** gpio34_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio34_fun_drv:2;
-        /** gpio34_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio34_mcu_sel:3;
-        /** gpio34_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio34_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio34_reg_t;
-
-/** Type of gpio35 register
- *  iomux control register for gpio35
- */
-typedef union {
-    struct {
-        /** gpio35_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio35_mcu_oe:1;
-        /** gpio35_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio35_slp_sel:1;
-        /** gpio35_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio35_mcu_wpd:1;
-        /** gpio35_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio35_mcu_wpu:1;
-        /** gpio35_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio35_mcu_ie:1;
-        /** gpio35_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio35_mcu_drv:2;
-        /** gpio35_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio35_fun_wpd:1;
-        /** gpio35_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio35_fun_wpu:1;
-        /** gpio35_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio35_fun_ie:1;
-        /** gpio35_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio35_fun_drv:2;
-        /** gpio35_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio35_mcu_sel:3;
-        /** gpio35_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio35_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio35_reg_t;
-
-/** Type of gpio36 register
- *  iomux control register for gpio36
- */
-typedef union {
-    struct {
-        /** gpio36_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio36_mcu_oe:1;
-        /** gpio36_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio36_slp_sel:1;
-        /** gpio36_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio36_mcu_wpd:1;
-        /** gpio36_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio36_mcu_wpu:1;
-        /** gpio36_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio36_mcu_ie:1;
-        /** gpio36_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio36_mcu_drv:2;
-        /** gpio36_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio36_fun_wpd:1;
-        /** gpio36_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio36_fun_wpu:1;
-        /** gpio36_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio36_fun_ie:1;
-        /** gpio36_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio36_fun_drv:2;
-        /** gpio36_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio36_mcu_sel:3;
-        /** gpio36_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio36_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio36_reg_t;
-
-/** Type of gpio37 register
- *  iomux control register for gpio37
- */
-typedef union {
-    struct {
-        /** gpio37_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio37_mcu_oe:1;
-        /** gpio37_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio37_slp_sel:1;
-        /** gpio37_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio37_mcu_wpd:1;
-        /** gpio37_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio37_mcu_wpu:1;
-        /** gpio37_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio37_mcu_ie:1;
-        /** gpio37_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio37_mcu_drv:2;
-        /** gpio37_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio37_fun_wpd:1;
-        /** gpio37_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio37_fun_wpu:1;
-        /** gpio37_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio37_fun_ie:1;
-        /** gpio37_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio37_fun_drv:2;
-        /** gpio37_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio37_mcu_sel:3;
-        /** gpio37_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio37_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio37_reg_t;
-
-/** Type of gpio38 register
- *  iomux control register for gpio38
- */
-typedef union {
-    struct {
-        /** gpio38_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio38_mcu_oe:1;
-        /** gpio38_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio38_slp_sel:1;
-        /** gpio38_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio38_mcu_wpd:1;
-        /** gpio38_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio38_mcu_wpu:1;
-        /** gpio38_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio38_mcu_ie:1;
-        /** gpio38_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio38_mcu_drv:2;
-        /** gpio38_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio38_fun_wpd:1;
-        /** gpio38_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio38_fun_wpu:1;
-        /** gpio38_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio38_fun_ie:1;
-        /** gpio38_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio38_fun_drv:2;
-        /** gpio38_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio38_mcu_sel:3;
-        /** gpio38_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio38_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio38_reg_t;
-
-/** Type of gpio39 register
- *  iomux control register for gpio39
- */
-typedef union {
-    struct {
-        /** gpio39_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio39_mcu_oe:1;
-        /** gpio39_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio39_slp_sel:1;
-        /** gpio39_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio39_mcu_wpd:1;
-        /** gpio39_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio39_mcu_wpu:1;
-        /** gpio39_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio39_mcu_ie:1;
-        /** gpio39_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio39_mcu_drv:2;
-        /** gpio39_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio39_fun_wpd:1;
-        /** gpio39_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio39_fun_wpu:1;
-        /** gpio39_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio39_fun_ie:1;
-        /** gpio39_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio39_fun_drv:2;
-        /** gpio39_mcu_sel : R/W; bitpos: [14:12]; default: 1;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio39_mcu_sel:3;
-        /** gpio39_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio39_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio39_reg_t;
-
-/** Type of gpio40 register
- *  iomux control register for gpio40
- */
-typedef union {
-    struct {
-        /** gpio40_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio40_mcu_oe:1;
-        /** gpio40_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio40_slp_sel:1;
-        /** gpio40_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio40_mcu_wpd:1;
-        /** gpio40_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio40_mcu_wpu:1;
-        /** gpio40_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio40_mcu_ie:1;
-        /** gpio40_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio40_mcu_drv:2;
-        /** gpio40_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio40_fun_wpd:1;
-        /** gpio40_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio40_fun_wpu:1;
-        /** gpio40_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio40_fun_ie:1;
-        /** gpio40_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio40_fun_drv:2;
-        /** gpio40_mcu_sel : R/W; bitpos: [14:12]; default: 1;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio40_mcu_sel:3;
-        /** gpio40_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio40_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio40_reg_t;
-
-/** Type of gpio41 register
- *  iomux control register for gpio41
- */
-typedef union {
-    struct {
-        /** gpio41_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio41_mcu_oe:1;
-        /** gpio41_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio41_slp_sel:1;
-        /** gpio41_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio41_mcu_wpd:1;
-        /** gpio41_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio41_mcu_wpu:1;
-        /** gpio41_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio41_mcu_ie:1;
-        /** gpio41_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio41_mcu_drv:2;
-        /** gpio41_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio41_fun_wpd:1;
-        /** gpio41_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio41_fun_wpu:1;
-        /** gpio41_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio41_fun_ie:1;
-        /** gpio41_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio41_fun_drv:2;
-        /** gpio41_mcu_sel : R/W; bitpos: [14:12]; default: 1;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio41_mcu_sel:3;
-        /** gpio41_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio41_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio41_reg_t;
-
-/** Type of gpio42 register
- *  iomux control register for gpio42
- */
-typedef union {
-    struct {
-        /** gpio42_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio42_mcu_oe:1;
-        /** gpio42_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio42_slp_sel:1;
-        /** gpio42_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio42_mcu_wpd:1;
-        /** gpio42_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio42_mcu_wpu:1;
-        /** gpio42_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio42_mcu_ie:1;
-        /** gpio42_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio42_mcu_drv:2;
-        /** gpio42_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio42_fun_wpd:1;
-        /** gpio42_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio42_fun_wpu:1;
-        /** gpio42_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio42_fun_ie:1;
-        /** gpio42_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio42_fun_drv:2;
-        /** gpio42_mcu_sel : R/W; bitpos: [14:12]; default: 1;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio42_mcu_sel:3;
-        /** gpio42_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio42_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio42_reg_t;
-
-/** Type of gpio43 register
- *  iomux control register for gpio43
- */
-typedef union {
-    struct {
-        /** gpio43_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio43_mcu_oe:1;
-        /** gpio43_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio43_slp_sel:1;
-        /** gpio43_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio43_mcu_wpd:1;
-        /** gpio43_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio43_mcu_wpu:1;
-        /** gpio43_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio43_mcu_ie:1;
-        /** gpio43_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio43_mcu_drv:2;
-        /** gpio43_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio43_fun_wpd:1;
-        /** gpio43_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio43_fun_wpu:1;
-        /** gpio43_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio43_fun_ie:1;
-        /** gpio43_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio43_fun_drv:2;
-        /** gpio43_mcu_sel : R/W; bitpos: [14:12]; default: 1;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio43_mcu_sel:3;
-        /** gpio43_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio43_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio43_reg_t;
-
-/** Type of gpio44 register
- *  iomux control register for gpio44
- */
-typedef union {
-    struct {
-        /** gpio44_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio44_mcu_oe:1;
-        /** gpio44_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio44_slp_sel:1;
-        /** gpio44_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio44_mcu_wpd:1;
-        /** gpio44_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio44_mcu_wpu:1;
-        /** gpio44_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio44_mcu_ie:1;
-        /** gpio44_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio44_mcu_drv:2;
-        /** gpio44_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio44_fun_wpd:1;
-        /** gpio44_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio44_fun_wpu:1;
-        /** gpio44_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio44_fun_ie:1;
-        /** gpio44_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio44_fun_drv:2;
-        /** gpio44_mcu_sel : R/W; bitpos: [14:12]; default: 1;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio44_mcu_sel:3;
-        /** gpio44_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio44_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio44_reg_t;
-
-/** Type of gpio45 register
- *  iomux control register for gpio45
- */
-typedef union {
-    struct {
-        /** gpio45_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio45_mcu_oe:1;
-        /** gpio45_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio45_slp_sel:1;
-        /** gpio45_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio45_mcu_wpd:1;
-        /** gpio45_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio45_mcu_wpu:1;
-        /** gpio45_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio45_mcu_ie:1;
-        /** gpio45_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio45_mcu_drv:2;
-        /** gpio45_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio45_fun_wpd:1;
-        /** gpio45_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio45_fun_wpu:1;
-        /** gpio45_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio45_fun_ie:1;
-        /** gpio45_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio45_fun_drv:2;
-        /** gpio45_mcu_sel : R/W; bitpos: [14:12]; default: 1;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio45_mcu_sel:3;
-        /** gpio45_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio45_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio45_reg_t;
-
-/** Type of gpio46 register
- *  iomux control register for gpio46
- */
-typedef union {
-    struct {
-        /** gpio46_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio46_mcu_oe:1;
-        /** gpio46_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio46_slp_sel:1;
-        /** gpio46_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio46_mcu_wpd:1;
-        /** gpio46_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio46_mcu_wpu:1;
-        /** gpio46_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio46_mcu_ie:1;
-        /** gpio46_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio46_mcu_drv:2;
-        /** gpio46_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio46_fun_wpd:1;
-        /** gpio46_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio46_fun_wpu:1;
-        /** gpio46_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio46_fun_ie:1;
-        /** gpio46_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio46_fun_drv:2;
-        /** gpio46_mcu_sel : R/W; bitpos: [14:12]; default: 1;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio46_mcu_sel:3;
-        /** gpio46_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio46_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio46_reg_t;
-
-/** Type of gpio47 register
- *  iomux control register for gpio47
- */
-typedef union {
-    struct {
-        /** gpio47_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio47_mcu_oe:1;
-        /** gpio47_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio47_slp_sel:1;
-        /** gpio47_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio47_mcu_wpd:1;
-        /** gpio47_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio47_mcu_wpu:1;
-        /** gpio47_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio47_mcu_ie:1;
-        /** gpio47_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio47_mcu_drv:2;
-        /** gpio47_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio47_fun_wpd:1;
-        /** gpio47_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio47_fun_wpu:1;
-        /** gpio47_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio47_fun_ie:1;
-        /** gpio47_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio47_fun_drv:2;
-        /** gpio47_mcu_sel : R/W; bitpos: [14:12]; default: 1;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio47_mcu_sel:3;
-        /** gpio47_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio47_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio47_reg_t;
-
-/** Type of gpio48 register
- *  iomux control register for gpio48
- */
-typedef union {
-    struct {
-        /** gpio48_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio48_mcu_oe:1;
-        /** gpio48_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio48_slp_sel:1;
-        /** gpio48_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio48_mcu_wpd:1;
-        /** gpio48_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio48_mcu_wpu:1;
-        /** gpio48_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio48_mcu_ie:1;
-        /** gpio48_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio48_mcu_drv:2;
-        /** gpio48_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio48_fun_wpd:1;
-        /** gpio48_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio48_fun_wpu:1;
-        /** gpio48_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio48_fun_ie:1;
-        /** gpio48_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio48_fun_drv:2;
-        /** gpio48_mcu_sel : R/W; bitpos: [14:12]; default: 1;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio48_mcu_sel:3;
-        /** gpio48_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio48_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio48_reg_t;
-
-/** Type of gpio49 register
- *  iomux control register for gpio49
- */
-typedef union {
-    struct {
-        /** gpio49_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio49_mcu_oe:1;
-        /** gpio49_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio49_slp_sel:1;
-        /** gpio49_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio49_mcu_wpd:1;
-        /** gpio49_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio49_mcu_wpu:1;
-        /** gpio49_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio49_mcu_ie:1;
-        /** gpio49_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio49_mcu_drv:2;
-        /** gpio49_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio49_fun_wpd:1;
-        /** gpio49_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio49_fun_wpu:1;
-        /** gpio49_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio49_fun_ie:1;
-        /** gpio49_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio49_fun_drv:2;
-        /** gpio49_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio49_mcu_sel:3;
-        /** gpio49_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio49_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio49_reg_t;
-
-/** Type of gpio50 register
- *  iomux control register for gpio50
- */
-typedef union {
-    struct {
-        /** gpio50_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio50_mcu_oe:1;
-        /** gpio50_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio50_slp_sel:1;
-        /** gpio50_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio50_mcu_wpd:1;
-        /** gpio50_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio50_mcu_wpu:1;
-        /** gpio50_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio50_mcu_ie:1;
-        /** gpio50_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio50_mcu_drv:2;
-        /** gpio50_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio50_fun_wpd:1;
-        /** gpio50_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio50_fun_wpu:1;
-        /** gpio50_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio50_fun_ie:1;
-        /** gpio50_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio50_fun_drv:2;
-        /** gpio50_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio50_mcu_sel:3;
-        /** gpio50_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio50_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio50_reg_t;
-
-/** Type of gpio51 register
- *  iomux control register for gpio51
- */
-typedef union {
-    struct {
-        /** gpio51_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio51_mcu_oe:1;
-        /** gpio51_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio51_slp_sel:1;
-        /** gpio51_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio51_mcu_wpd:1;
-        /** gpio51_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio51_mcu_wpu:1;
-        /** gpio51_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio51_mcu_ie:1;
-        /** gpio51_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio51_mcu_drv:2;
-        /** gpio51_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio51_fun_wpd:1;
-        /** gpio51_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio51_fun_wpu:1;
-        /** gpio51_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio51_fun_ie:1;
-        /** gpio51_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio51_fun_drv:2;
-        /** gpio51_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio51_mcu_sel:3;
-        /** gpio51_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio51_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio51_reg_t;
-
-/** Type of gpio52 register
- *  iomux control register for gpio52
- */
-typedef union {
-    struct {
-        /** gpio52_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio52_mcu_oe:1;
-        /** gpio52_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio52_slp_sel:1;
-        /** gpio52_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio52_mcu_wpd:1;
-        /** gpio52_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio52_mcu_wpu:1;
-        /** gpio52_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio52_mcu_ie:1;
-        /** gpio52_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio52_mcu_drv:2;
-        /** gpio52_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio52_fun_wpd:1;
-        /** gpio52_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio52_fun_wpu:1;
-        /** gpio52_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio52_fun_ie:1;
-        /** gpio52_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio52_fun_drv:2;
-        /** gpio52_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio52_mcu_sel:3;
-        /** gpio52_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio52_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio52_reg_t;
-
-/** Type of gpio53 register
- *  iomux control register for gpio53
- */
-typedef union {
-    struct {
-        /** gpio53_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio53_mcu_oe:1;
-        /** gpio53_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio53_slp_sel:1;
-        /** gpio53_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio53_mcu_wpd:1;
-        /** gpio53_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio53_mcu_wpu:1;
-        /** gpio53_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio53_mcu_ie:1;
-        /** gpio53_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio53_mcu_drv:2;
-        /** gpio53_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio53_fun_wpd:1;
-        /** gpio53_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio53_fun_wpu:1;
-        /** gpio53_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio53_fun_ie:1;
-        /** gpio53_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio53_fun_drv:2;
-        /** gpio53_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio53_mcu_sel:3;
-        /** gpio53_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio53_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio53_reg_t;
-
-/** Type of gpio54 register
- *  iomux control register for gpio54
- */
-typedef union {
-    struct {
-        /** gpio54_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio54_mcu_oe:1;
-        /** gpio54_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio54_slp_sel:1;
-        /** gpio54_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio54_mcu_wpd:1;
-        /** gpio54_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio54_mcu_wpu:1;
-        /** gpio54_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio54_mcu_ie:1;
-        /** gpio54_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio54_mcu_drv:2;
-        /** gpio54_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio54_fun_wpd:1;
-        /** gpio54_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio54_fun_wpu:1;
-        /** gpio54_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio54_fun_ie:1;
-        /** gpio54_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio54_fun_drv:2;
-        /** gpio54_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio54_mcu_sel:3;
-        /** gpio54_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio54_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio54_reg_t;
-
-/** Type of gpio55 register
- *  iomux control register for gpio55
- */
-typedef union {
-    struct {
-        /** gpio55_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio55_mcu_oe:1;
-        /** gpio55_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio55_slp_sel:1;
-        /** gpio55_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio55_mcu_wpd:1;
-        /** gpio55_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio55_mcu_wpu:1;
-        /** gpio55_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio55_mcu_ie:1;
-        /** gpio55_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio55_mcu_drv:2;
-        /** gpio55_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio55_fun_wpd:1;
-        /** gpio55_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio55_fun_wpu:1;
-        /** gpio55_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio55_fun_ie:1;
-        /** gpio55_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio55_fun_drv:2;
-        /** gpio55_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio55_mcu_sel:3;
-        /** gpio55_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio55_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio55_reg_t;
-
-/** Type of gpio56 register
- *  iomux control register for gpio56
- */
-typedef union {
-    struct {
-        /** gpio56_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  output enable on sleep mode
-         */
-        uint32_t gpio56_mcu_oe:1;
-        /** gpio56_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  io sleep mode enable. set 1 to enable sleep mode.
-         */
-        uint32_t gpio56_slp_sel:1;
-        /** gpio56_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  pull-down enable on sleep mode
-         */
-        uint32_t gpio56_mcu_wpd:1;
-        /** gpio56_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  pull-up enable on sleep mode
-         */
-        uint32_t gpio56_mcu_wpu:1;
-        /** gpio56_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  input enable on sleep mode
-         */
-        uint32_t gpio56_mcu_ie:1;
-        /** gpio56_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  select drive strength on sleep mode
-         */
-        uint32_t gpio56_mcu_drv:2;
-        /** gpio56_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  pull-down enable
-         */
-        uint32_t gpio56_fun_wpd:1;
-        /** gpio56_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  pull-up enable
-         */
-        uint32_t gpio56_fun_wpu:1;
-        /** gpio56_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  input enable
-         */
-        uint32_t gpio56_fun_ie:1;
-        /** gpio56_fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
-         */
-        uint32_t gpio56_fun_drv:2;
-        /** gpio56_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  0:select function0, 1:select function1 ...
-         */
-        uint32_t gpio56_mcu_sel:3;
-        /** gpio56_filter_en : R/W; bitpos: [15]; default: 0;
-         *  input filter enable
-         */
-        uint32_t gpio56_filter_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} io_mux_gpio56_reg_t;
-
-/** Type of date register
- *  iomux version
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 2101794;
-         *  csv date
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} io_mux_date_reg_t;
-
-
-typedef struct {
-    uint32_t reserved_000;
-    volatile io_mux_gpio0_reg_t gpio0;
-    volatile io_mux_gpio1_reg_t gpio1;
-    volatile io_mux_gpio2_reg_t gpio2;
-    volatile io_mux_gpio3_reg_t gpio3;
-    volatile io_mux_gpio4_reg_t gpio4;
-    volatile io_mux_gpio5_reg_t gpio5;
-    volatile io_mux_gpio6_reg_t gpio6;
-    volatile io_mux_gpio7_reg_t gpio7;
-    volatile io_mux_gpio8_reg_t gpio8;
-    volatile io_mux_gpio9_reg_t gpio9;
-    volatile io_mux_gpio10_reg_t gpio10;
-    volatile io_mux_gpio11_reg_t gpio11;
-    volatile io_mux_gpio12_reg_t gpio12;
-    volatile io_mux_gpio13_reg_t gpio13;
-    volatile io_mux_gpio14_reg_t gpio14;
-    volatile io_mux_gpio15_reg_t gpio15;
-    volatile io_mux_gpio16_reg_t gpio16;
-    volatile io_mux_gpio17_reg_t gpio17;
-    volatile io_mux_gpio18_reg_t gpio18;
-    volatile io_mux_gpio19_reg_t gpio19;
-    volatile io_mux_gpio20_reg_t gpio20;
-    volatile io_mux_gpio21_reg_t gpio21;
-    volatile io_mux_gpio22_reg_t gpio22;
-    volatile io_mux_gpio23_reg_t gpio23;
-    volatile io_mux_gpio24_reg_t gpio24;
-    volatile io_mux_gpio25_reg_t gpio25;
-    volatile io_mux_gpio26_reg_t gpio26;
-    volatile io_mux_gpio27_reg_t gpio27;
-    volatile io_mux_gpio28_reg_t gpio28;
-    volatile io_mux_gpio29_reg_t gpio29;
-    volatile io_mux_gpio30_reg_t gpio30;
-    volatile io_mux_gpio31_reg_t gpio31;
-    volatile io_mux_gpio32_reg_t gpio32;
-    volatile io_mux_gpio33_reg_t gpio33;
-    volatile io_mux_gpio34_reg_t gpio34;
-    volatile io_mux_gpio35_reg_t gpio35;
-    volatile io_mux_gpio36_reg_t gpio36;
-    volatile io_mux_gpio37_reg_t gpio37;
-    volatile io_mux_gpio38_reg_t gpio38;
-    volatile io_mux_gpio39_reg_t gpio39;
-    volatile io_mux_gpio40_reg_t gpio40;
-    volatile io_mux_gpio41_reg_t gpio41;
-    volatile io_mux_gpio42_reg_t gpio42;
-    volatile io_mux_gpio43_reg_t gpio43;
-    volatile io_mux_gpio44_reg_t gpio44;
-    volatile io_mux_gpio45_reg_t gpio45;
-    volatile io_mux_gpio46_reg_t gpio46;
-    volatile io_mux_gpio47_reg_t gpio47;
-    volatile io_mux_gpio48_reg_t gpio48;
-    volatile io_mux_gpio49_reg_t gpio49;
-    volatile io_mux_gpio50_reg_t gpio50;
-    volatile io_mux_gpio51_reg_t gpio51;
-    volatile io_mux_gpio52_reg_t gpio52;
-    volatile io_mux_gpio53_reg_t gpio53;
-    volatile io_mux_gpio54_reg_t gpio54;
-    volatile io_mux_gpio55_reg_t gpio55;
-    volatile io_mux_gpio56_reg_t gpio56;
-    uint32_t reserved_0e8[7];
-    volatile io_mux_date_reg_t date;
-} io_mux_dev_t;
-
-extern io_mux_dev_t IO_MUX;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(io_mux_dev_t) == 0x108, "Invalid size of io_mux_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h
index b8eac91be1c7..8e9cbb504092 100644
--- a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h
+++ b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h
@@ -7,8 +7,6 @@
 #pragma once
 #include "soc/soc.h"
 
-//TODO: IDF-13419
-
 /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
 /* Output enable in sleep mode */
 #define SLP_OE (BIT(0))
@@ -357,6 +355,7 @@
 #define FUNC_GPIO31_GPIO31                                               1
 #define FUNC_GPIO31_GPIO31_0                                             0
 
+// Strapping: Diag Group Sel1
 #define PERIPHS_IO_MUX_U_PAD_GPIO32               (REG_IO_MUX_BASE + 0x84)
 #define FUNC_GPIO32_DBG_PSRAM_DQ4_PAD                                    4
 #define FUNC_GPIO32_EMAC_RMII_CLK_PAD                                    3
@@ -364,6 +363,7 @@
 #define FUNC_GPIO32_GPIO32                                               1
 #define FUNC_GPIO32_GPIO32_0                                             0
 
+// Strapping: Diag Group Sel0
 #define PERIPHS_IO_MUX_U_PAD_GPIO33               (REG_IO_MUX_BASE + 0x88)
 #define FUNC_GPIO33_DBG_PSRAM_DQ5_PAD                                    4
 #define FUNC_GPIO33_EMAC_PHY_TXEN_PAD                                    3
@@ -371,6 +371,7 @@
 #define FUNC_GPIO33_GPIO33                                               1
 #define FUNC_GPIO33_GPIO33_0                                             0
 
+// Strapping: USB2JTAG select: 1->usb2jtag 0-> pad_jtag
 #define PERIPHS_IO_MUX_U_PAD_GPIO34               (REG_IO_MUX_BASE + 0x8C)
 #define FUNC_GPIO34_DBG_PSRAM_DQ6_PAD                                    4
 #define FUNC_GPIO34_EMAC_PHY_TXD0_PAD                                    3
@@ -378,6 +379,7 @@
 #define FUNC_GPIO34_GPIO34                                               1
 #define FUNC_GPIO34_GPIO34_0                                             0
 
+// Strapping: Boot Mode select 3
 #define PERIPHS_IO_MUX_U_PAD_GPIO35               (REG_IO_MUX_BASE + 0x90)
 #define FUNC_GPIO35_DBG_PSRAM_DQ7_PAD                                    4
 #define FUNC_GPIO35_EMAC_PHY_TXD1_PAD                                    3
@@ -385,6 +387,7 @@
 #define FUNC_GPIO35_GPIO35                                               1
 #define FUNC_GPIO35_GPIO35_0                                             0
 
+// Strapping: Boot Mode select 2
 #define PERIPHS_IO_MUX_U_PAD_GPIO36               (REG_IO_MUX_BASE + 0x94)
 #define FUNC_GPIO36_DBG_PSRAM_DQS_0_PAD                                  4
 #define FUNC_GPIO36_EMAC_PHY_TXER_PAD                                    3
@@ -392,11 +395,13 @@
 #define FUNC_GPIO36_GPIO36                                               1
 #define FUNC_GPIO36_GPIO36_0                                             0
 
+// Strapping: Boot Mode select 1
 #define PERIPHS_IO_MUX_U_PAD_GPIO37               (REG_IO_MUX_BASE + 0x98)
 #define FUNC_GPIO37_SPI2_IO7_PAD                                         2
 #define FUNC_GPIO37_GPIO37                                               1
 #define FUNC_GPIO37_UART0_TXD_PAD                                        0
 
+// Strapping: Boot Mode select 0
 #define PERIPHS_IO_MUX_U_PAD_GPIO38               (REG_IO_MUX_BASE + 0x9C)
 #define FUNC_GPIO38_SPI2_DQS_PAD                                         2
 #define FUNC_GPIO38_GPIO38                                               1
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h
index b2b0e6630623..e187ba74596c 100644
--- a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h
+++ b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h
@@ -10,7 +10,6 @@
 extern "C" {
 #endif
 
-//TODO: IDF-13419
 /** Type of GPIO register
  *  IO MUX gpio configuration register
  */
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h
index 740839aecdcd..c445ffbd1661 100644
--- a/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h
@@ -114,22 +114,6 @@ typedef union {
 } lp_iomux_ext_wakeup0_sel_reg_t;
 
 
-/** Group: lp_pad_hold */
-/** Type of lp_pad_hold register
- *  Reserved
- */
-typedef union {
-    struct {
-        /** reg_lp_gpio_hold : R/W; bitpos: [15:0]; default: 0;
-         *  Reserved
-         */
-        uint32_t reg_lp_gpio_hold:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_iomux_lp_pad_hold_reg_t;
-
-
 /** Group: lp_pad_hys */
 /** Type of lp_pad_hys register
  *  Reserved
@@ -151,7 +135,7 @@ typedef struct lp_iomux_dev_t {
     volatile lp_iomux_ver_date_reg_t ver_date;
     volatile lp_iomux_pad_reg_t pad[16];
     volatile lp_iomux_ext_wakeup0_sel_reg_t ext_wakeup0_sel;
-    volatile lp_iomux_lp_pad_hold_reg_t lp_pad_hold;
+    uint32_t reserved_04c;
     volatile lp_iomux_lp_pad_hys_reg_t lp_pad_hys;
 } lp_iomux_dev_t;
 
diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
index 5b1219fa7926..10f4f203b5ce 100644
--- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
@@ -407,10 +407,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
     int
     default 3
 
-config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
-    bool
-    default y
-
 config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
     int
     default 8
diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h
index 8cc946cda988..2dbf4f8d5c7c 100644
--- a/components/soc/esp32s2/include/soc/soc_caps.h
+++ b/components/soc/esp32s2/include/soc/soc_caps.h
@@ -182,9 +182,6 @@
 #define SOC_GPIO_CLOCKOUT_BY_IO_MUX    (1)
 #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM  (3)
 
-// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
-#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
-
 /*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
index 697cb9fd6f07..7c92228f8b98 100644
--- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
@@ -491,10 +491,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
     int
     default 3
 
-config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
-    bool
-    default y
-
 config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
     int
     default 8
diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h
index 26e89ba34c68..689435d105c3 100644
--- a/components/soc/esp32s3/include/soc/soc_caps.h
+++ b/components/soc/esp32s3/include/soc/soc_caps.h
@@ -198,9 +198,6 @@
 #define SOC_GPIO_CLOCKOUT_BY_IO_MUX    (1)
 #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM  (3)
 
-// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
-#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
-
 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
diff --git a/components/ulp/test_apps/ulp_fsm/main/test_ulp.c b/components/ulp/test_apps/ulp_fsm/main/test_ulp.c
index ee4ae12f88bd..faa44964f6d0 100644
--- a/components/ulp/test_apps/ulp_fsm/main/test_ulp.c
+++ b/components/ulp/test_apps/ulp_fsm/main/test_ulp.c
@@ -362,7 +362,7 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]")
         TEST_ESP_OK(ulp_run(0));
 
         /* Wait for the ULP co-processor to finish up */
-        vTaskDelay(10 / portTICK_PERIOD_MS);
+        vTaskDelay(50 / portTICK_PERIOD_MS);
 
         /* Verify the test results */
         uint32_t clear = REG_READ(RTC_CNTL_STORE0_REG);
diff --git a/docs/en/api-reference/peripherals/isp.rst b/docs/en/api-reference/peripherals/isp.rst
index be0197bb0d14..52a829c66c30 100644
--- a/docs/en/api-reference/peripherals/isp.rst
+++ b/docs/en/api-reference/peripherals/isp.rst
@@ -723,7 +723,7 @@ Calling :cpp:func:`esp_isp_demosaic_configure` to configure Demosaic function, y
         ...
     };
 
-    ESP_ERROR_CHECK(esp_isp_demosaic_configure(isp_proc, &sharpen_config));
+    ESP_ERROR_CHECK(esp_isp_demosaic_configure(isp_proc, &demosaic_config));
     ESP_ERROR_CHECK(esp_isp_demosaic_enable(isp_proc));
 
 After calling :cpp:func:`esp_isp_demosaic_configure`, you need to enable the ISP Demosaic controller, by calling :cpp:func:`esp_isp_demosaic_enable`. This function:
diff --git a/docs/zh_CN/api-reference/peripherals/isp.rst b/docs/zh_CN/api-reference/peripherals/isp.rst
index e43900f0c536..09cbdbbc7805 100644
--- a/docs/zh_CN/api-reference/peripherals/isp.rst
+++ b/docs/zh_CN/api-reference/peripherals/isp.rst
@@ -724,7 +724,7 @@ ISP 去马赛克控制器
         ...
     };
 
-    ESP_ERROR_CHECK(esp_isp_demosaic_configure(isp_proc, &sharpen_config));
+    ESP_ERROR_CHECK(esp_isp_demosaic_configure(isp_proc, &demosaic_config));
     ESP_ERROR_CHECK(esp_isp_demosaic_enable(isp_proc));
 
 调用 :cpp:func:`esp_isp_demosaic_configure` 后，需要通过调用 :cpp:func:`esp_isp_demosaic_enable` 来启用 ISP 去马赛克控制器。此函数：
diff --git a/tools/test_apps/system/g0_components/CMakeLists.txt b/tools/test_apps/system/g0_components/CMakeLists.txt
index 4751f860e995..ed83187265ce 100644
--- a/tools/test_apps/system/g0_components/CMakeLists.txt
+++ b/tools/test_apps/system/g0_components/CMakeLists.txt
@@ -26,6 +26,10 @@ idf_build_set_property(__BUILD_COMPONENT_DEPGRAPH_ENABLED 1)
 
 project(g0_components)
 
+if(CONFIG_IDF_TARGET_ESP32P4)
+    idf_build_set_property(C_COMPILE_OPTIONS "-DCONFIG_ESP_REV_MIN_FULL=300" APPEND)
+endif()
+
 if(CONFIG_IDF_TARGET_ESP32C2)
     # clk_tree hal-driver needs CONFIG_XTAL_FREQ
     idf_build_set_property(C_COMPILE_OPTIONS "-DCONFIG_XTAL_FREQ=26" APPEND)