diff --git a/components/app_update/test_apps/test_app_update/.build-test-rules.yml b/components/app_update/test_apps/test_app_update/.build-test-rules.yml index b0fce9257604..ce361079ee5b 100644 --- a/components/app_update/test_apps/test_app_update/.build-test-rules.yml +++ b/components/app_update/test_apps/test_app_update/.build-test-rules.yml @@ -15,6 +15,9 @@ components/app_update/test_apps: - if: IDF_TARGET == "esp32c61" and CONFIG_NAME == "xip_psram_with_rom_impl" temporary: true reason: not supported yet # TODO: [ESP32C61] IDF-12784 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14401 disable_test: - if: CONFIG_NAME == "recovery_bootloader" and SOC_RECOVERY_BOOTLOADER_SUPPORTED == 1 and IDF_TARGET == "esp32c61" temporary: true diff --git a/components/app_update/test_apps/test_app_update/README.md b/components/app_update/test_apps/test_app_update/README.md index 7b96141437ec..3c34983dd59f 100644 --- a/components/app_update/test_apps/test_app_update/README.md +++ b/components/app_update/test_apps/test_app_update/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c index eb83ae8b1359..e5769d712013 100644 --- a/components/bootloader_support/src/bootloader_console.c +++ b/components/bootloader_support/src/bootloader_console.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,6 @@ #include "soc/uart_periph.h" #include "soc/uart_channel.h" #include "soc/io_mux_reg.h" -#include "soc/gpio_periph.h" #include "soc/gpio_sig_map.h" #include "soc/rtc.h" #include "hal/gpio_ll.h" @@ -26,9 +25,21 @@ #include "esp_rom_sys.h" #include "esp_rom_caps.h" +static void __attribute__((unused)) release_default_console_io(void) +{ + // Default console is UART0 with TX and RX on their IOMUX pins + gpio_ll_output_disable(&GPIO, UART_NUM_0_TXD_DIRECT_GPIO_NUM); + gpio_ll_func_sel(&GPIO, U0TXD_GPIO_NUM, PIN_FUNC_GPIO); // Set TX pin to GPIO function to truly disable output + esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(UART_NUM_0, SOC_UART_RX_PIN_IDX), 0); +} + #ifdef CONFIG_ESP_CONSOLE_NONE void bootloader_console_init(void) { + // Wait for UART FIFO to be empty. + esp_rom_output_tx_wait_idle(0); + release_default_console_io(); + esp_rom_install_channel_putc(1, NULL); esp_rom_install_channel_putc(2, NULL); } @@ -59,9 +70,7 @@ void bootloader_console_init(void) if (uart_num != 0 || uart_tx_gpio != UART_NUM_0_TXD_DIRECT_GPIO_NUM || uart_rx_gpio != UART_NUM_0_RXD_DIRECT_GPIO_NUM) { - // Change default UART pins back to GPIOs - gpio_ll_func_sel(&GPIO, UART_NUM_0_RXD_DIRECT_GPIO_NUM, PIN_FUNC_GPIO); - gpio_ll_func_sel(&GPIO, UART_NUM_0_TXD_DIRECT_GPIO_NUM, PIN_FUNC_GPIO); + release_default_console_io(); // Route GPIO signals to/from pins const uint32_t tx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX); const uint32_t rx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX); @@ -101,6 +110,10 @@ static char s_usb_cdc_buf[ESP_ROM_CDC_ACM_WORK_BUF_MIN]; void bootloader_console_init(void) { + // Wait for UART FIFO to be empty. + esp_rom_output_tx_wait_idle(0); + release_default_console_io(); + #ifdef CONFIG_IDF_TARGET_ESP32S2 /* ESP32-S2 specific patch to set the correct serial number in the descriptor. * Later chips don't need this. @@ -120,6 +133,10 @@ void bootloader_console_init(void) #ifdef CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG void bootloader_console_init(void) { + // Wait for UART FIFO to be empty. + esp_rom_output_tx_wait_idle(0); + release_default_console_io(); + esp_rom_output_switch_buffer(ESP_ROM_USB_SERIAL_DEVICE_NUM); /* Switch console channel to avoid output on UART and allow */ diff --git a/components/bt/host/nimble/Kconfig.in b/components/bt/host/nimble/Kconfig.in index 214c2408f81f..d816de184089 100644 --- a/components/bt/host/nimble/Kconfig.in +++ b/components/bt/host/nimble/Kconfig.in @@ -485,6 +485,26 @@ menu "Memory Settings" default 1 help This is the service data unit buffer count for l2cap coc. + + config BT_NIMBLE_MEMPOOL_RUNTIME_ALLOC + bool "Support on-demand runtime memory allocation for mempool" + depends on BT_NIMBLE_ENABLED && !SOC_ESP_NIMBLE_CONTROLLER + default n + help + When this option is enabled, mempool does not require pre-allocating memory. + Instead, memory for each block will be dynamically allocated and released + during mempool usage. This can significantly reduce memory consumption + after mempool initialization, but may have some impact on performance. + + config BT_NIMBLE_MEMPOOL_BLOCK_REUSED + bool "Support block reuse for mempool runtime memory allocation" + depends on BT_NIMBLE_MEMPOOL_RUNTIME_ALLOC + default n + help + When this option is enabled, dynamically allocated blocks will not be freed + but will be reused instead. This ensures virtually no impact on performance + while reducing the memory consumption of the mempool. + endmenu #Memory menu "BLE 5.x Features" @@ -581,7 +601,7 @@ menu "BLE 5.x Features" config BT_NIMBLE_EXT_SCAN bool "Enable extended scanning" - depends on BT_NIMBLE_50_FEATURE_SUPPORT && BT_NIMBLE_ROLE_OBSERVER + depends on BT_NIMBLE_50_FEATURE_SUPPORT default y help Enable this option to do extended scanning. diff --git a/components/bt/host/nimble/esp-hci/src/esp_nimble_hci.c b/components/bt/host/nimble/esp-hci/src/esp_nimble_hci.c index 04778593cafb..bffd7ee14039 100644 --- a/components/bt/host/nimble/esp-hci/src/esp_nimble_hci.c +++ b/components/bt/host/nimble/esp-hci/src/esp_nimble_hci.c @@ -96,7 +96,11 @@ int ble_hci_trans_hs_cmd_tx(uint8_t *cmd) rc = BLE_HS_ETIMEOUT_HCI; } +#if MYNEWT_VAL(MP_RUNTIME_ALLOC) + ble_transport_free(BLE_HCI_CMD, cmd); +#else ble_transport_free(cmd); +#endif return rc; } diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble index 45387330100a..6f9ff29d2619 160000 --- a/components/bt/host/nimble/nimble +++ b/components/bt/host/nimble/nimble @@ -1 +1 @@ -Subproject commit 45387330100ab0709a0d9e0510e764fdc91cfb83 +Subproject commit 6f9ff29d261939945c4f2fa74c01763009cb2cd0 diff --git a/components/bt/host/nimble/port/include/ble_svc_gap_stub.h b/components/bt/host/nimble/port/include/ble_svc_gap_stub.h new file mode 100644 index 000000000000..1fb456f2194d --- /dev/null +++ b/components/bt/host/nimble/port/include/ble_svc_gap_stub.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_log.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define BLE_SVC_GAP_TAG "ble_svc_gap" + +/** + * Stub implementations for GAP service APIs. + * These are compiled when CONFIG_BT_NIMBLE_GAP_SERVICE is disabled. + */ + +static inline void ble_svc_gap_init(void) +{ + ESP_LOGE(BLE_SVC_GAP_TAG, "GAP service not enabled. Enable CONFIG_BT_NIMBLE_GAP_SERVICE to use this API."); +} + +static inline int ble_svc_gap_device_name_set(const char *name) +{ + (void)name; + ESP_LOGE(BLE_SVC_GAP_TAG, "GAP service not enabled. Enable CONFIG_BT_NIMBLE_GAP_SERVICE to use this API."); + return -1; +} + +static inline const char *ble_svc_gap_device_name(void) +{ + ESP_LOGE(BLE_SVC_GAP_TAG, "GAP service not enabled. Enable CONFIG_BT_NIMBLE_GAP_SERVICE to use this API."); + return NULL; +} + +static inline int ble_svc_gap_device_appearance_set(uint16_t appearance) +{ + ESP_LOGE(BLE_SVC_GAP_TAG, "GAP service not enabled. Enable CONFIG_BT_NIMBLE_GAP_SERVICE to use this API."); + return -1; +} + +static inline int ble_svc_gap_device_key_material_set(uint8_t *session_key, uint8_t *iv) +{ + ESP_LOGE(BLE_SVC_GAP_TAG, "GAP service not enabled. Enable CONFIG_BT_NIMBLE_GAP_SERVICE to use this API."); + return -1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/bt/host/nimble/port/include/esp_nimble_cfg.h b/components/bt/host/nimble/port/include/esp_nimble_cfg.h index db2a4a1990b1..445c0e295725 100644 --- a/components/bt/host/nimble/port/include/esp_nimble_cfg.h +++ b/components/bt/host/nimble/port/include/esp_nimble_cfg.h @@ -1804,9 +1804,11 @@ #endif /*** @apache-mynewt-nimble/nimble/host/services/gap */ +#ifdef CONFIG_BT_NIMBLE_GAP_SERVICE #ifndef MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE #define MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE CONFIG_BT_NIMBLE_SVC_GAP_APPEARANCE #endif +#endif #ifndef MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE_WRITE_PERM #if CONFIG_BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM @@ -1819,10 +1821,12 @@ #endif //CONFIG_BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM #endif //MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE_WRITE_PERM +#ifdef CONFIG_BT_NIMBLE_GAP_SERVICE #ifndef MYNEWT_VAL_BLE_SVC_GAP_CENTRAL_ADDRESS_RESOLUTION #define MYNEWT_VAL_BLE_SVC_GAP_CENTRAL_ADDRESS_RESOLUTION \ CONFIG_BT_NIMBLE_SVC_GAP_CENT_ADDR_RESOLUTION #endif +#endif #ifndef CONFIG_BT_NIMBLE_SVC_GAP_DEVICE_NAME #define MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME "nimble" @@ -1830,9 +1834,11 @@ #define MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME CONFIG_BT_NIMBLE_SVC_GAP_DEVICE_NAME #endif +#ifdef CONFIG_BT_NIMBLE_GAP_SERVICE #ifndef MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME_MAX_LENGTH #define MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME_MAX_LENGTH CONFIG_BT_NIMBLE_GAP_DEVICE_NAME_MAX_LEN // According to the specification, the maximum length should be 248 #endif +#endif #ifndef MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME_WRITE_PERM #if CONFIG_BT_NIMBLE_SVC_GAP_NAME_WRITE_PERM @@ -2208,4 +2214,20 @@ #endif #endif +#ifndef MYNEWT_VAL_MP_RUNTIME_ALLOC +#ifdef CONFIG_BT_NIMBLE_MEMPOOL_RUNTIME_ALLOC +#define MYNEWT_VAL_MP_RUNTIME_ALLOC (1) +#else +#define MYNEWT_VAL_MP_RUNTIME_ALLOC (0) +#endif +#endif + +#ifndef MYNEWT_VAL_MP_BLOCK_REUSED +#ifdef CONFIG_BT_NIMBLE_MEMPOOL_BLOCK_REUSED +#define MYNEWT_VAL_MP_BLOCK_REUSED (1) +#else +#define MYNEWT_VAL_MP_BLOCK_REUSED (0) +#endif +#endif + #endif diff --git a/components/cxx/test_apps/.build-test-rules.yml b/components/cxx/test_apps/.build-test-rules.yml index 3b8ff55552b6..d21ee93145d5 100644 --- a/components/cxx/test_apps/.build-test-rules.yml +++ b/components/cxx/test_apps/.build-test-rules.yml @@ -5,3 +5,7 @@ components/cxx/test_apps: - if: IDF_TARGET in ["esp32", "esp32c3"] temporary: true reason: the other targets are not tested yet + disable: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14402 diff --git a/components/driver/test_apps/.build-test-rules.yml b/components/driver/test_apps/.build-test-rules.yml index 9d87486d629a..c721e4a2b395 100644 --- a/components/driver/test_apps/.build-test-rules.yml +++ b/components/driver/test_apps/.build-test-rules.yml @@ -21,6 +21,9 @@ components/driver/test_apps/legacy_adc_driver: - if: IDF_TARGET == "esp32c61" temporary: true reason: lack of runners + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14357 depends_components: - efuse - esp_driver_i2s @@ -57,6 +60,10 @@ components/driver/test_apps/legacy_rmt_driver: components/driver/test_apps/legacy_rtc_temp_driver: disable: - if: SOC_TEMP_SENSOR_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14834 components/driver/test_apps/legacy_sigma_delta_driver: disable: @@ -76,6 +83,9 @@ components/driver/test_apps/legacy_twai: disable: - if: SOC_TWAI_SUPPORTED != 1 or SOC_TWAI_SUPPORT_FD == 1 reason: legacy driver doesn't support FD + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14393 depends_filepatterns: - components/driver/twai/**/* depends_components: diff --git a/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py b/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py index a7acc58b252d..cdff7ee2067c 100644 --- a/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py +++ b/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py @@ -18,6 +18,7 @@ ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c5', 'esp32p4'], indirect=['target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14357') def test_legacy_adc(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/driver/test_apps/legacy_rtc_temp_driver/pytest_legacy_temp_sensor_driver.py b/components/driver/test_apps/legacy_rtc_temp_driver/pytest_legacy_temp_sensor_driver.py index 47646ffe489f..3d27a10b4346 100644 --- a/components/driver/test_apps/legacy_rtc_temp_driver/pytest_legacy_temp_sensor_driver.py +++ b/components/driver/test_apps/legacy_rtc_temp_driver/pytest_legacy_temp_sensor_driver.py @@ -18,5 +18,6 @@ ['esp32s2', 'esp32c3', 'esp32s3', 'esp32c2', 'esp32c6', 'esp32h2', 'esp32p4', 'esp32c5', 'esp32c61'], indirect=['target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14834') def test_legacy_temp_sensor_driver(dut: Dut) -> None: dut.run_all_single_board_cases(timeout=120) diff --git a/components/driver/test_apps/legacy_twai/README.md b/components/driver/test_apps/legacy_twai/README.md index bf6a3f380d30..2eccd3e551ac 100644 --- a/components/driver/test_apps/legacy_twai/README.md +++ b/components/driver/test_apps/legacy_twai/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # Enable Socket CAN Device with bitrate 250Kbps diff --git a/components/driver/test_apps/legacy_twai/pytest_twai.py b/components/driver/test_apps/legacy_twai/pytest_twai.py index ae59da978665..dd3a5d24e80f 100644 --- a/components/driver/test_apps/legacy_twai/pytest_twai.py +++ b/components/driver/test_apps/legacy_twai/pytest_twai.py @@ -19,9 +19,7 @@ ], indirect=True, ) -@idf_parametrize( - 'target', ['esp32', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32s2', 'esp32s3', 'esp32p4'], indirect=['target'] -) +@idf_parametrize('target', ['esp32', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32s2', 'esp32s3'], indirect=['target']) def test_legacy_twai_self(dut: Dut) -> None: dut.run_all_single_board_cases(group='twai-loop-back') @@ -46,9 +44,7 @@ def fixture_create_socket_can() -> Bus: ], indirect=True, ) -@idf_parametrize( - 'target', ['esp32', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32s2', 'esp32s3', 'esp32p4'], indirect=['target'] -) +@idf_parametrize('target', ['esp32', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32s2', 'esp32s3'], indirect=['target']) def test_legacy_twai_listen_only(dut: Dut, socket_can: Bus) -> None: dut.serial.hard_reset() dut.expect_exact('Press ENTER to see the list of tests') @@ -76,9 +72,7 @@ def test_legacy_twai_listen_only(dut: Dut, socket_can: Bus) -> None: ], indirect=True, ) -@idf_parametrize( - 'target', ['esp32', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32s2', 'esp32s3', 'esp32p4'], indirect=['target'] -) +@idf_parametrize('target', ['esp32', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32s2', 'esp32s3'], indirect=['target']) def test_legacy_twai_remote_request(dut: Dut, socket_can: Bus) -> None: dut.serial.hard_reset() dut.expect_exact('Press ENTER to see the list of tests') diff --git a/components/efuse/test_apps/.build-test-rules.yml b/components/efuse/test_apps/.build-test-rules.yml index 22eeea2060ea..b3c80820a007 100644 --- a/components/efuse/test_apps/.build-test-rules.yml +++ b/components/efuse/test_apps/.build-test-rules.yml @@ -3,6 +3,10 @@ components/efuse/test_apps: enable: - if: (INCLUDE_DEFAULT == 1 and SOC_EFUSE_SUPPORTED == 1) or IDF_TARGET == "linux") + disable: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14403 disable_test: - if: IDF_TARGET in ["esp32s2", "esp32s3"] reason: eFuse for S2 and S3 is similar to the C3 chip, so we only test for C3. diff --git a/components/efuse/test_apps/README.md b/components/efuse/test_apps/README.md index 8b53053b4359..c694e797c7d6 100644 --- a/components/efuse/test_apps/README.md +++ b/components/efuse/test_apps/README.md @@ -1,3 +1,3 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | ----- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | Linux | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | ----- | diff --git a/components/efuse/test_apps/pytest_efuse.py b/components/efuse/test_apps/pytest_efuse.py index 6d823e62cb08..0826ecb9c590 100644 --- a/components/efuse/test_apps/pytest_efuse.py +++ b/components/efuse/test_apps/pytest_efuse.py @@ -6,7 +6,8 @@ @pytest.mark.temp_skip_ci( - targets=['esp32s2', 'esp32s3'], reason='eFuse for S2 and S3 is similar to the C3 chip, so testing on C3 is enough' + targets=['esp32s2', 'esp32s3', 'esp32p4'], + reason='eFuse for S2 and S3 is similar to the C3 chip, so testing on C3 is enough', ) @pytest.mark.generic @idf_parametrize('target', ['supported_targets'], indirect=['target']) diff --git a/components/esp_adc/test_apps/.build-test-rules.yml b/components/esp_adc/test_apps/.build-test-rules.yml index aa97546c7d49..3a0b9ebae5b5 100644 --- a/components/esp_adc/test_apps/.build-test-rules.yml +++ b/components/esp_adc/test_apps/.build-test-rules.yml @@ -4,6 +4,10 @@ components/esp_adc/test_apps/adc: disable: - if: SOC_ADC_SUPPORTED != 1 - if: CONFIG_NAME == "gdma_iram_safe" and IDF_TARGET in ["esp32", "esp32s2", "esp32c2"] + disable_test: + - if: IDF_TARGET == "esp32p4" and CONFIG_NAME != "esp32p4_eco4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14357 depends_components: - esp_adc - esp_driver_gpio diff --git a/components/esp_adc/test_apps/adc/pytest_adc.py b/components/esp_adc/test_apps/adc/pytest_adc.py index d44ee01691ec..9013a33780bd 100644 --- a/components/esp_adc/test_apps/adc/pytest_adc.py +++ b/components/esp_adc/test_apps/adc/pytest_adc.py @@ -12,6 +12,7 @@ ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c5', 'esp32p4', 'esp32c61'], indirect=['target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14357') def test_adc(dut: Dut) -> None: dut.run_all_single_board_cases(timeout=120, reset=True) @@ -30,3 +31,17 @@ def test_adc(dut: Dut) -> None: @idf_parametrize('target', ['esp32c2'], indirect=['target']) def test_adc_esp32c2_xtal_26mhz(dut: Dut) -> None: dut.run_all_single_board_cases(timeout=120, reset=True) + + +# P4 REV2 adc +@pytest.mark.adc +@pytest.mark.esp32p4_eco4 +@pytest.mark.parametrize('config', ['esp32p4_eco4'], indirect=True) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14357') +@idf_parametrize( + 'target', + ['esp32p4'], + indirect=['target'], +) +def test_adc_p4_rev2(dut: Dut) -> None: + dut.run_all_single_board_cases(timeout=120, reset=True) diff --git a/components/esp_adc/test_apps/adc/sdkconfig.ci.esp32p4_eco4 b/components/esp_adc/test_apps/adc/sdkconfig.ci.esp32p4_eco4 new file mode 100644 index 000000000000..2c6c907fab6e --- /dev/null +++ b/components/esp_adc/test_apps/adc/sdkconfig.ci.esp32p4_eco4 @@ -0,0 +1,2 @@ +CONFIG_IDF_TARGET="esp32p4" +CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y diff --git a/components/esp_common/test_apps/.build-test-rules.yml b/components/esp_common/test_apps/.build-test-rules.yml index c52d810e1520..efe89f68860c 100644 --- a/components/esp_common/test_apps/.build-test-rules.yml +++ b/components/esp_common/test_apps/.build-test-rules.yml @@ -4,3 +4,6 @@ components/esp_common/test_apps/esp_common: disable: - if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1 - if: CONFIG_NAME == "psram_noinit" and SOC_SPIRAM_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14404 diff --git a/components/esp_common/test_apps/esp_common/README.md b/components/esp_common/test_apps/esp_common/README.md index 44f3780f1d6a..7f28f609e612 100644 --- a/components/esp_common/test_apps/esp_common/README.md +++ b/components/esp_common/test_apps/esp_common/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | diff --git a/components/esp_common/test_apps/esp_common/pytest_esp_common.py b/components/esp_common/test_apps/esp_common/pytest_esp_common.py index 726657be4211..e2bca929f25d 100644 --- a/components/esp_common/test_apps/esp_common/pytest_esp_common.py +++ b/components/esp_common/test_apps/esp_common/pytest_esp_common.py @@ -8,6 +8,7 @@ @pytest.mark.generic +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14404') @pytest.mark.parametrize( 'config', ['default'], @@ -28,6 +29,7 @@ def test_esp_common(dut: Dut) -> None: indirect=True, ) @idf_parametrize('target', ['esp32', 'esp32s2', 'esp32s3', 'esp32p4', 'esp32c5'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14404') def test_esp_attr_psram_noinit(dut: Dut) -> None: dut.run_all_single_board_cases() @@ -40,6 +42,7 @@ def test_esp_attr_psram_noinit(dut: Dut) -> None: indirect=True, ) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14404') def test_esp_attr_psram_noinit_multiple_stages(case_tester: Any) -> None: case_tester.run_all_multi_stage_cases() @@ -54,6 +57,7 @@ def test_esp_attr_psram_noinit_multiple_stages(case_tester: Any) -> None: indirect=True, ) @idf_parametrize('target', ['esp32', 'esp32s2', 'esp32s3', 'esp32p4', 'esp32c5'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14404') def test_esp_attr_psram(dut: Dut) -> None: dut.run_all_single_board_cases() @@ -90,5 +94,6 @@ def test_esp_attr_xip_psram_esp32s3(dut: Dut) -> None: indirect=True, ) @idf_parametrize('target', ['esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14404') def test_esp_attr_xip_psram_esp32p4(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_driver_cam/test_apps/.build-test-rules.yml b/components/esp_driver_cam/test_apps/.build-test-rules.yml index 0d419e7609c7..6be395b4ec8b 100644 --- a/components/esp_driver_cam/test_apps/.build-test-rules.yml +++ b/components/esp_driver_cam/test_apps/.build-test-rules.yml @@ -1,6 +1,9 @@ components/esp_driver_cam/test_apps/csi: disable: - if: SOC_MIPI_CSI_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" # TODO: IDF-14358 + temporary: true + reason: p4 rev3 migration depends_components: - esp_driver_cam diff --git a/components/esp_driver_gpio/src/gpio.c b/components/esp_driver_gpio/src/gpio.c index eaf7909edb25..08e8b102afc1 100644 --- a/components/esp_driver_gpio/src/gpio.c +++ b/components/esp_driver_gpio/src/gpio.c @@ -207,7 +207,8 @@ esp_err_t gpio_output_disable(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); gpio_hal_output_disable(gpio_context.gpio_hal, gpio_num); - gpio_hal_set_output_enable_ctrl(gpio_context.gpio_hal, gpio_num, false, false); // so that output disable could take effect + gpio_hal_set_output_enable_ctrl(gpio_context.gpio_hal, gpio_num, false, false); // so that output disable could always take effect when func sel is GPIO + gpio_hal_func_sel(gpio_context.gpio_hal, gpio_num, PIN_FUNC_GPIO); // otherwise the oe can only be controlled by peripheral return ESP_OK; } @@ -216,6 +217,7 @@ esp_err_t gpio_output_enable(gpio_num_t gpio_num) GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO output gpio_num error", ESP_ERR_INVALID_ARG); gpio_hal_matrix_out_default(gpio_context.gpio_hal, gpio_num); // No peripheral output signal routed to the pin, just as a simple GPIO output gpio_hal_output_enable(gpio_context.gpio_hal, gpio_num); + gpio_hal_func_sel(gpio_context.gpio_hal, gpio_num, PIN_FUNC_GPIO); // otherwise the oe can only be controlled by peripheral return ESP_OK; } @@ -1096,9 +1098,10 @@ esp_err_t gpio_dump_io_configuration(FILE *out_stream, uint64_t io_bit_mask) gpio_get_io_config(gpio_num, &io_config); // When the IO is used as a simple GPIO output, oe signal can only be controlled by the oe register - // When the IO is not used as a simple GPIO output, oe signal could be controlled by the peripheral + // When the IO connects to a peripheral signal through GPIO Matrix, oe signal can be controlled by the peripheral or the oe register (switch by oe_ctrl_by_periph) + // When the IO connects to a peripheral signal through IOMUX, oe signal can only be controlled by the peripheral const char *oe_str = io_config.oe ? "1" : "0"; - if (io_config.sig_out != SIG_GPIO_OUT_IDX && io_config.oe_ctrl_by_periph) { + if (io_config.fun_sel != PIN_FUNC_GPIO || io_config.oe_ctrl_by_periph) { oe_str = "[periph_sig_ctrl]"; } diff --git a/components/esp_driver_i2c/test_apps/.build-test-rules.yml b/components/esp_driver_i2c/test_apps/.build-test-rules.yml index 5436c0467eaf..4df5bbf7725e 100644 --- a/components/esp_driver_i2c/test_apps/.build-test-rules.yml +++ b/components/esp_driver_i2c/test_apps/.build-test-rules.yml @@ -3,5 +3,9 @@ components/esp_driver_i2c/test_apps/i2c_test_apps: disable: - if: SOC_I2C_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET in ["esp32h21", "esp32p4"] + temporary: true + reason: p4 rev3 migration # TODO: IDF-14395 depends_components: - esp_driver_i2c diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py b/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py index 501d7a47e665..fbfa3c756a32 100644 --- a/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py +++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py @@ -15,12 +15,14 @@ ], indirect=True, ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14395') @idf_parametrize('target', ['supported_targets'], indirect=['target']) def test_i2c(dut: Dut) -> None: dut.run_all_single_board_cases() @pytest.mark.generic_multi_device +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14395') @pytest.mark.parametrize( 'count, config', [ diff --git a/components/esp_driver_i2s/test_apps/.build-test-rules.yml b/components/esp_driver_i2s/test_apps/.build-test-rules.yml index 12a74125b1f1..07fa39b90759 100644 --- a/components/esp_driver_i2s/test_apps/.build-test-rules.yml +++ b/components/esp_driver_i2s/test_apps/.build-test-rules.yml @@ -11,6 +11,10 @@ components/esp_driver_i2s/test_apps/i2s_multi_dev: disable: - if: SOC_I2S_SUPPORTED != 1 - if: SOC_I2S_HW_VERSION_2 != 1 + disable_test: + - if: IDF_TARGET in ["esp32p4"] # TODO: IDF-14396 + temporary: true + reason: lack of runners depends_components: - esp_driver_i2s diff --git a/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py b/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py index d07ece199c09..d0d94ae389ec 100644 --- a/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py +++ b/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py @@ -6,6 +6,7 @@ @pytest.mark.generic_multi_device +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14396') @pytest.mark.parametrize('count', [2], indirect=True) @idf_parametrize('target', soc_filtered_targets('SOC_I2S_SUPPORTS_TDM == 1'), indirect=['target']) def test_i2s_multi_dev(case_tester) -> None: # type: ignore diff --git a/components/esp_driver_ledc/test_apps/.build-test-rules.yml b/components/esp_driver_ledc/test_apps/.build-test-rules.yml index 50e40b72c0a7..c9446e000a9c 100644 --- a/components/esp_driver_ledc/test_apps/.build-test-rules.yml +++ b/components/esp_driver_ledc/test_apps/.build-test-rules.yml @@ -3,5 +3,9 @@ components/esp_driver_ledc/test_apps/ledc: disable: - if: SOC_LEDC_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14398 depends_components: - esp_driver_ledc diff --git a/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py b/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py index 70d71e08267a..42f19403bfe6 100644 --- a/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py +++ b/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py @@ -16,6 +16,7 @@ indirect=True, ) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14398') def test_ledc(dut: IdfDut) -> None: dut.run_all_single_board_cases(reset=True) @@ -35,6 +36,7 @@ def test_ledc_psram(dut: IdfDut) -> None: @pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='s3 multi device runner has no psram') +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14398') @pytest.mark.generic_multi_device @pytest.mark.parametrize( 'count, config', diff --git a/components/esp_driver_mcpwm/test_apps/.build-test-rules.yml b/components/esp_driver_mcpwm/test_apps/.build-test-rules.yml index cbc941233cd2..85658d61ffc7 100644 --- a/components/esp_driver_mcpwm/test_apps/.build-test-rules.yml +++ b/components/esp_driver_mcpwm/test_apps/.build-test-rules.yml @@ -3,5 +3,9 @@ components/esp_driver_mcpwm/test_apps/mcpwm: disable: - if: SOC_MCPWM_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14412 depends_components: - esp_driver_mcpwm diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/pytest_mcpwm.py b/components/esp_driver_mcpwm/test_apps/mcpwm/pytest_mcpwm.py index 8d910fffa8fd..fc6313a7e243 100644 --- a/components/esp_driver_mcpwm/test_apps/mcpwm/pytest_mcpwm.py +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/pytest_mcpwm.py @@ -15,5 +15,6 @@ indirect=True, ) @idf_parametrize('target', ['esp32', 'esp32s3', 'esp32c5', 'esp32c6', 'esp32h2', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14412') def test_mcpwm(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_driver_parlio/test_apps/.build-test-rules.yml b/components/esp_driver_parlio/test_apps/.build-test-rules.yml index efce473ee7f9..f748dc7351ad 100644 --- a/components/esp_driver_parlio/test_apps/.build-test-rules.yml +++ b/components/esp_driver_parlio/test_apps/.build-test-rules.yml @@ -3,5 +3,9 @@ components/esp_driver_parlio/test_apps/parlio: disable: - if: SOC_PARLIO_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14413 depends_components: - esp_driver_parlio diff --git a/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py b/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py index b275afc55c57..55b9dbb6c9db 100644 --- a/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py +++ b/components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py @@ -15,5 +15,6 @@ indirect=True, ) @idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32h2', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14413') def test_parlio(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_driver_ppa/include/driver/ppa.h b/components/esp_driver_ppa/include/driver/ppa.h index 9f019a45576b..5a3917d88d0c 100644 --- a/components/esp_driver_ppa/include/driver/ppa.h +++ b/components/esp_driver_ppa/include/driver/ppa.h @@ -127,7 +127,6 @@ typedef struct { }; ppa_color_range_t yuv_range; /*!< When the color mode is any YUV color space, this field is to describe its color range */ ppa_color_conv_std_rgb_yuv_t yuv_std; /*!< When the color mode is any YUV color space, this field is to describe its YUV<->RGB conversion standard */ - color_yuv422_pack_order_t yuv422_pack_order; /*!< When the color mode is YUV422, this field is to describe its data pack order */ } ppa_in_pic_blk_config_t; /** diff --git a/components/esp_driver_ppa/src/ppa_blend.c b/components/esp_driver_ppa/src/ppa_blend.c index 7a44dce2df92..e5cdb5ceb280 100644 --- a/components/esp_driver_ppa/src/ppa_blend.c +++ b/components/esp_driver_ppa/src/ppa_blend.c @@ -144,9 +144,6 @@ bool ppa_blend_transaction_on_picked(uint32_t num_chans, const dma2d_trans_chann ppa_ll_blend_set_rx_bg_yuv_range(platform->hal.dev, blend_trans_desc->in_bg.yuv_range); ppa_ll_blend_set_rx_bg_yuv2rgb_std(platform->hal.dev, blend_trans_desc->in_bg.yuv_std); } - if ((uint32_t)blend_trans_desc->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_YUV422) { - ppa_ll_blend_set_rx_bg_yuv422_pack_order(platform->hal.dev, blend_trans_desc->in_bg.yuv422_pack_order); - } ppa_ll_blend_enable_rx_bg_byte_swap(platform->hal.dev, blend_trans_desc->bg_byte_swap); ppa_ll_blend_enable_rx_bg_rgb_swap(platform->hal.dev, blend_trans_desc->bg_rgb_swap); ppa_ll_blend_configure_rx_bg_alpha(platform->hal.dev, blend_trans_desc->bg_alpha_update_mode, blend_trans_desc->bg_alpha_value); @@ -201,7 +198,7 @@ esp_err_t ppa_do_blend(ppa_client_handle_t ppa_client, const ppa_blend_oper_conf config->in_bg.block_h % 2 == 0 && config->in_bg.block_w % 2 == 0 && config->in_bg.block_offset_x % 2 == 0 && config->in_bg.block_offset_y % 2 == 0, ESP_ERR_INVALID_ARG, TAG, "YUV420 input does not support odd h/w/offset_x/offset_y"); - } else if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_YUV422) { + } else if (PPA_IS_CM_YUV422(config->in_bg.blend_cm)) { ESP_RETURN_ON_FALSE(config->in_bg.pic_w % 2 == 0 && config->in_bg.block_w % 2 == 0 && config->in_bg.block_offset_x % 2 == 0, ESP_ERR_INVALID_ARG, TAG, "YUV422 input does not support odd w/offset_x"); } @@ -218,7 +215,7 @@ esp_err_t ppa_do_blend(ppa_client_handle_t ppa_client, const ppa_blend_oper_conf ESP_RETURN_ON_FALSE(config->out.pic_h % 2 == 0 && config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0, ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y"); - } else if (config->out.blend_cm == PPA_BLEND_COLOR_MODE_YUV422) { + } else if (PPA_IS_CM_YUV422(config->out.blend_cm)) { ESP_RETURN_ON_FALSE(config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0, ESP_ERR_INVALID_ARG, TAG, "YUV422 output does not support odd w/offset_x"); } diff --git a/components/esp_driver_ppa/src/ppa_fill.c b/components/esp_driver_ppa/src/ppa_fill.c index 9ec997649bab..6b923e24bf88 100644 --- a/components/esp_driver_ppa/src/ppa_fill.c +++ b/components/esp_driver_ppa/src/ppa_fill.c @@ -104,7 +104,7 @@ esp_err_t ppa_do_fill(ppa_client_handle_t ppa_client, const ppa_fill_oper_config // config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0, // ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y"); // } else - if (config->out.fill_cm == PPA_FILL_COLOR_MODE_YUV422) { + if (config->out.fill_cm == PPA_FILL_COLOR_MODE_YUV422_UYVY) { ESP_RETURN_ON_FALSE(config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0, ESP_ERR_INVALID_ARG, TAG, "YUV422 output does not support odd w/offset_x"); } diff --git a/components/esp_driver_ppa/src/ppa_priv.h b/components/esp_driver_ppa/src/ppa_priv.h index d335145a45e0..e1810be07a51 100644 --- a/components/esp_driver_ppa/src/ppa_priv.h +++ b/components/esp_driver_ppa/src/ppa_priv.h @@ -35,6 +35,10 @@ extern "C" { ESP_RETURN_ON_FALSE(COLOR_SPACE_TYPE(color_type_id) == COLOR_SPACE_ARGB || COLOR_SPACE_TYPE(color_type_id) == COLOR_SPACE_RGB, \ ESP_ERR_INVALID_ARG, TAG, str "_cm does not support rgb_swap"); +#define PPA_IS_CM_YUV422(color_type_id) \ + (color_type_id == COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_UYVY422) || color_type_id == COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_VYUY422) || \ + color_type_id == COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUYV422) || color_type_id == COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YVYU422)) + #define PPA_ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) #define PPA_ALIGN_DOWN(num, align) ((num) & ~((align) - 1)) diff --git a/components/esp_driver_ppa/src/ppa_srm.c b/components/esp_driver_ppa/src/ppa_srm.c index 9e488682381a..fd30be80e73b 100644 --- a/components/esp_driver_ppa/src/ppa_srm.c +++ b/components/esp_driver_ppa/src/ppa_srm.c @@ -147,9 +147,6 @@ bool ppa_srm_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel ppa_ll_srm_set_rx_yuv_range(platform->hal.dev, srm_trans_desc->in.yuv_range); ppa_ll_srm_set_rx_yuv2rgb_std(platform->hal.dev, srm_trans_desc->in.yuv_std); } - if ((uint32_t)ppa_in_color_mode == COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422)) { - ppa_ll_srm_set_rx_yuv422_pack_order(platform->hal.dev, srm_trans_desc->in.yuv422_pack_order); - } ppa_ll_srm_enable_rx_byte_swap(platform->hal.dev, srm_trans_desc->byte_swap); ppa_ll_srm_enable_rx_rgb_swap(platform->hal.dev, srm_trans_desc->rgb_swap); ppa_ll_srm_configure_rx_alpha(platform->hal.dev, srm_trans_desc->alpha_update_mode, srm_trans_desc->alpha_value); @@ -190,7 +187,7 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s config->in.block_h % 2 == 0 && config->in.block_w % 2 == 0 && config->in.block_offset_x % 2 == 0 && config->in.block_offset_y % 2 == 0, ESP_ERR_INVALID_ARG, TAG, "YUV420 input does not support odd h/w/offset_x/offset_y"); - } else if (config->in.srm_cm == PPA_SRM_COLOR_MODE_YUV422) { + } else if (PPA_IS_CM_YUV422(config->in.srm_cm)) { ESP_RETURN_ON_FALSE(config->in.pic_w % 2 == 0 && config->in.block_w % 2 == 0 && config->in.block_offset_x % 2 == 0, ESP_ERR_INVALID_ARG, TAG, "YUV422 input does not support odd w/offset_x"); } @@ -198,7 +195,7 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s ESP_RETURN_ON_FALSE(config->out.pic_h % 2 == 0 && config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0, ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y"); - } else if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV422) { + } else if (PPA_IS_CM_YUV422(config->out.srm_cm)) { ESP_RETURN_ON_FALSE(config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0, ESP_ERR_INVALID_ARG, TAG, "YUV422 output does not support odd w/offset_x"); } @@ -278,7 +275,7 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV420) { srm_trans_desc->scale_x_frag = srm_trans_desc->scale_x_frag & ~1; srm_trans_desc->scale_y_frag = srm_trans_desc->scale_y_frag & ~1; - } else if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV422) { + } else if (PPA_IS_CM_YUV422(config->out.srm_cm)) { srm_trans_desc->scale_x_frag = srm_trans_desc->scale_x_frag & ~1; } srm_trans_desc->alpha_value = new_alpha_value; diff --git a/components/esp_driver_ppa/test_apps/main/test_ppa.c b/components/esp_driver_ppa/test_apps/main/test_ppa.c index 5b8dce8b5f3e..011add8c2e97 100644 --- a/components/esp_driver_ppa/test_apps/main/test_ppa.c +++ b/components/esp_driver_ppa/test_apps/main/test_ppa.c @@ -562,10 +562,10 @@ TEST_CASE("ppa_fill_basic_data_correctness_check", "[PPA]") #if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3) // Test a yuv color fill - oper_config.out.fill_cm = PPA_FILL_COLOR_MODE_YUV422; // output YUV422 is with YVYU packed order + oper_config.out.fill_cm = PPA_FILL_COLOR_MODE_YUV422_UYVY; // output YUV422 is with UYVY packed order const color_macroblock_yuv_data_t fill_yuv_color = {.y = 0xFF, .u = 0x55, .v = 0xAA}; oper_config.fill_yuv_color = fill_yuv_color; - out_pixel_format.color_type_id = PPA_FILL_COLOR_MODE_YUV422; + out_pixel_format.color_type_id = PPA_FILL_COLOR_MODE_YUV422_UYVY; out_pixel_depth = color_hal_pixel_format_get_bit_depth(out_pixel_format); // bits TEST_ESP_OK(ppa_do_fill(ppa_client_handle, &oper_config)); diff --git a/components/esp_driver_rmt/test_apps/.build-test-rules.yml b/components/esp_driver_rmt/test_apps/.build-test-rules.yml index 2a97c6cdec19..b737b52f8f77 100644 --- a/components/esp_driver_rmt/test_apps/.build-test-rules.yml +++ b/components/esp_driver_rmt/test_apps/.build-test-rules.yml @@ -3,5 +3,9 @@ components/esp_driver_rmt/test_apps/rmt: disable: - if: SOC_RMT_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14414 depends_components: - esp_driver_rmt diff --git a/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py b/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py index 4a9612aa79fd..1ef07f27e3b6 100644 --- a/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py +++ b/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py @@ -17,6 +17,7 @@ @idf_parametrize( 'target', ['esp32', 'esp32s2', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32h2', 'esp32p4'], indirect=['target'] ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14414') def test_rmt(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_driver_sdio/test_apps/.build-test-rules.yml b/components/esp_driver_sdio/test_apps/.build-test-rules.yml index 4b34b4542944..7c2d3e4321ae 100644 --- a/components/esp_driver_sdio/test_apps/.build-test-rules.yml +++ b/components/esp_driver_sdio/test_apps/.build-test-rules.yml @@ -2,6 +2,10 @@ components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc: enable: - if: IDF_TARGET in ["esp32", "esp32p4"] reason: runners use ESP32 / ESP32P4 SDMMC as host + disable: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14359 depends_components: - sdmmc - esp_driver_sdmmc diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/README.md b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/README.md index cbe7d02b0755..abb7f3c223cf 100644 --- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/README.md +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-P4 | -| ----------------- | ----- | -------- | +| Supported Targets | ESP32 | +| ----------------- | ----- | # SDIO Cross Chips Test Apps: SDMMC Host App diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/pytest_sdio.py b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/pytest_sdio.py index e6621bb44eb7..6ec9dac8093f 100644 --- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/pytest_sdio.py +++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/pytest_sdio.py @@ -99,6 +99,7 @@ def test_sdio_esp32_esp32(dut: Tuple[IdfDut, IdfDut]) -> None: indirect=True, ) @pytest.mark.parametrize('app_path, target, config', c5_param_default, indirect=True) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14359') def test_sdio_esp32p4_esp32c5(dut: Tuple[IdfDut, IdfDut]) -> None: test_sdio_flow(dut) @@ -171,6 +172,7 @@ def test_sdio_speed_frhost_esp32_esp32(dut: Tuple[IdfDut, IdfDut]) -> None: indirect=True, ) @pytest.mark.parametrize('app_path, target, config', c5_param_default, indirect=True) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14359') def test_sdio_speed_frhost_esp32p4_esp32c5(dut: Tuple[IdfDut, IdfDut]) -> None: test_sdio_speed_frhost_flow(dut, 10000, 4000) @@ -243,6 +245,7 @@ def test_sdio_speed_tohost_esp32_esp32(dut: Tuple[IdfDut, IdfDut]) -> None: indirect=True, ) @pytest.mark.parametrize('app_path, target, config', c5_param_default, indirect=True) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14359') def test_sdio_speed_tohost_esp32p4_esp32c5(dut: Tuple[IdfDut, IdfDut]) -> None: test_sdio_speed_tohost_flow(dut, 9000, 4000) diff --git a/components/esp_driver_sdspi/test_apps/.build-test-rules.yml b/components/esp_driver_sdspi/test_apps/.build-test-rules.yml index 57fdd2e11cba..fdfaa7e1073c 100644 --- a/components/esp_driver_sdspi/test_apps/.build-test-rules.yml +++ b/components/esp_driver_sdspi/test_apps/.build-test-rules.yml @@ -1,6 +1,9 @@ components/esp_driver_sdspi/test_apps/sdspi: disable: - if: SOC_GPSPI_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14363 disable_test: - if: IDF_TARGET not in ["esp32", "esp32s3", "esp32c3", "esp32c5", "esp32p4"] reason: needs special runner, select few typical targets for testing diff --git a/components/esp_driver_sdspi/test_apps/sdspi/README.md b/components/esp_driver_sdspi/test_apps/sdspi/README.md index 15bfc62bf3a4..20b7a36ebc1e 100644 --- a/components/esp_driver_sdspi/test_apps/sdspi/README.md +++ b/components/esp_driver_sdspi/test_apps/sdspi/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | diff --git a/components/esp_driver_sdspi/test_apps/sdspi/pytest_sdspi.py b/components/esp_driver_sdspi/test_apps/sdspi/pytest_sdspi.py index 4c187b2d12ee..a56856d50106 100644 --- a/components/esp_driver_sdspi/test_apps/sdspi/pytest_sdspi.py +++ b/components/esp_driver_sdspi/test_apps/sdspi/pytest_sdspi.py @@ -6,6 +6,7 @@ @pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='C5 C61 GPSPI same, so testing on C5 is enough') +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14393') @pytest.mark.sdcard_spimode @idf_parametrize('target', ['esp32', 'esp32s3', 'esp32c3', 'esp32p4', 'esp32c5'], indirect=['target']) def test_sdspi(dut: IdfDut) -> None: diff --git a/components/esp_driver_spi/test_apps/.build-test-rules.yml b/components/esp_driver_spi/test_apps/.build-test-rules.yml index 9b605ff85528..b269fe750238 100644 --- a/components/esp_driver_spi/test_apps/.build-test-rules.yml +++ b/components/esp_driver_spi/test_apps/.build-test-rules.yml @@ -9,20 +9,36 @@ components/esp_driver_spi/test_apps/master: disable: - if: SOC_GPSPI_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14399 <<: *spi_depends_default components/esp_driver_spi/test_apps/param: disable: - if: SOC_GPSPI_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET in ["esp32h21", "esp32p4"] + temporary: true + reason: p4 rev3 migration # TODO: IDF-14399 <<: *spi_depends_default components/esp_driver_spi/test_apps/slave: disable: - if: SOC_GPSPI_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET in ["esp32h21", "esp32p4"] + temporary: true + reason: p4 rev3 migration # TODO: IDF-14399 <<: *spi_depends_default components/esp_driver_spi/test_apps/slave_hd: disable: - if: SOC_GPSPI_SUPPORTED != 1 - if: SOC_SPI_SUPPORT_SLAVE_HD_VER2 != 1 + disable_test: + - if: IDF_TARGET in ["esp32h21", "esp32p4", "esp32c61"] + temporary: true + reason: p4 rev3 migration # TODO: IDF-14399 <<: *spi_depends_default diff --git a/components/esp_driver_spi/test_apps/master/pytest_spi_master.py b/components/esp_driver_spi/test_apps/master/pytest_spi_master.py index a141e2190071..24b40d0dd9f8 100644 --- a/components/esp_driver_spi/test_apps/master/pytest_spi_master.py +++ b/components/esp_driver_spi/test_apps/master/pytest_spi_master.py @@ -14,6 +14,7 @@ indirect=True, ) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14399') def test_master_single_dev(case_tester) -> None: # type: ignore for case in case_tester.test_menu: if 'test_env' in case.attributes: @@ -39,6 +40,7 @@ def test_master_esp_flash(case_tester) -> None: # type: ignore @pytest.mark.generic_multi_device +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14399') @pytest.mark.parametrize( 'count, config', [ diff --git a/components/esp_driver_spi/test_apps/param/pytest_spi_param.py b/components/esp_driver_spi/test_apps/param/pytest_spi_param.py index bd55a0ab782c..0178177384bc 100644 --- a/components/esp_driver_spi/test_apps/param/pytest_spi_param.py +++ b/components/esp_driver_spi/test_apps/param/pytest_spi_param.py @@ -5,6 +5,7 @@ @pytest.mark.generic +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14399') @idf_parametrize('target', ['supported_targets'], indirect=['target']) def test_param_single_dev(case_tester) -> None: # type: ignore case_tester.run_all_normal_cases(reset=True) @@ -13,5 +14,6 @@ def test_param_single_dev(case_tester) -> None: # type: ignore @pytest.mark.generic_multi_device @pytest.mark.parametrize('count', [2], indirect=True) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14399') def test_param_multi_dev(case_tester) -> None: # type: ignore case_tester.run_all_multi_dev_cases(reset=True) diff --git a/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py b/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py index 0b0adc8cbb97..90c6c1757519 100644 --- a/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py +++ b/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py @@ -6,6 +6,7 @@ @pytest.mark.generic @pytest.mark.parametrize('config', ['release', 'iram_safe'], indirect=True) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14399') @idf_parametrize('target', ['supported_targets'], indirect=['target']) def test_slave_single_dev(case_tester) -> None: # type: ignore case_tester.run_all_normal_cases(reset=True) @@ -13,6 +14,7 @@ def test_slave_single_dev(case_tester) -> None: # type: ignore @pytest.mark.generic_multi_device @pytest.mark.parametrize('count, config', [(2, 'release'), (2, 'iram_safe')], indirect=True) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14399') @idf_parametrize('target', ['supported_targets'], indirect=['target']) def test_slave_multi_dev(case_tester) -> None: # type: ignore case_tester.run_all_multi_dev_cases(reset=True) diff --git a/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py b/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py index ba138ca0a5c8..b19a86ab8aaf 100644 --- a/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py +++ b/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py @@ -8,6 +8,7 @@ @pytest.mark.generic @pytest.mark.parametrize('config', ['release'], indirect=True) +@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c61'], reason='p4 rev3 migration # TODO: IDF-14399') @idf_parametrize( 'target', ['esp32s2', 'esp32s3', 'esp32c2', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32c61', 'esp32h2', 'esp32p4'], @@ -20,6 +21,7 @@ def test_slave_hd_single_dev(case_tester) -> None: # type: ignore # if `test_env` not defined, will run on `generic_multi_device` by default @pytest.mark.generic_multi_device @pytest.mark.parametrize('count, config', [(2, 'release')], indirect=True) +@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c61'], reason='p4 rev3 migration # TODO: IDF-14399') @idf_parametrize( 'target', ['esp32s2', 'esp32s3', 'esp32c2', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32h2', 'esp32p4'], diff --git a/components/esp_driver_tsens/test_apps/.build-test-rules.yml b/components/esp_driver_tsens/test_apps/.build-test-rules.yml index 0117f07d13f6..ee0011111241 100644 --- a/components/esp_driver_tsens/test_apps/.build-test-rules.yml +++ b/components/esp_driver_tsens/test_apps/.build-test-rules.yml @@ -6,6 +6,10 @@ components/esp_driver_tsens/test_apps/temperature_sensor: - if: IDF_TARGET == "esp32c5" and CONFIG_NAME == "iram_safe" temporary: false reason: Use test_temperature_sensor_cbs_esp32c5 instead, iram_safe need to use single app large partition table on c5 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14834 depends_components: - esp_driver_tsens - esp_phy diff --git a/components/esp_driver_tsens/test_apps/temperature_sensor/pytest_temperature_sensor.py b/components/esp_driver_tsens/test_apps/temperature_sensor/pytest_temperature_sensor.py index 987e0db89ff5..ee39b9a29a0d 100644 --- a/components/esp_driver_tsens/test_apps/temperature_sensor/pytest_temperature_sensor.py +++ b/components/esp_driver_tsens/test_apps/temperature_sensor/pytest_temperature_sensor.py @@ -19,6 +19,7 @@ ['esp32s2', 'esp32c3', 'esp32s3', 'esp32c2', 'esp32c6', 'esp32h2', 'esp32p4', 'esp32c5', 'esp32c61'], indirect=['target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14834') def test_temperature_sensor_driver(dut: Dut) -> None: dut.run_all_single_board_cases() @@ -32,6 +33,7 @@ def test_temperature_sensor_driver(dut: Dut) -> None: indirect=True, ) @idf_parametrize('target', ['esp32c6', 'esp32h2', 'esp32p4', 'esp32c61'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14834') def test_temperature_sensor_cbs(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_driver_twai/test_apps/.build-test-rules.yml b/components/esp_driver_twai/test_apps/.build-test-rules.yml index 3cae20b47dcf..96a4646be017 100644 --- a/components/esp_driver_twai/test_apps/.build-test-rules.yml +++ b/components/esp_driver_twai/test_apps/.build-test-rules.yml @@ -1,5 +1,8 @@ components/esp_driver_twai/test_apps/test_twai: disable: - if: SOC_TWAI_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14393 depends_components: - esp_driver_twai diff --git a/components/esp_driver_twai/test_apps/test_twai/README.md b/components/esp_driver_twai/test_apps/test_twai/README.md index 46d16c788ce9..b5f247a643dd 100644 --- a/components/esp_driver_twai/test_apps/test_twai/README.md +++ b/components/esp_driver_twai/test_apps/test_twai/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_driver_twai/test_apps/test_twai/pytest_driver_twai.py b/components/esp_driver_twai/test_apps/test_twai/pytest_driver_twai.py index a08017531b59..846b2bf8dcec 100644 --- a/components/esp_driver_twai/test_apps/test_twai/pytest_driver_twai.py +++ b/components/esp_driver_twai/test_apps/test_twai/pytest_driver_twai.py @@ -13,6 +13,7 @@ @pytest.mark.generic +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14393') @pytest.mark.parametrize('config', ['release', 'cache_safe'], indirect=True) @idf_parametrize('target', soc_filtered_targets('SOC_TWAI_SUPPORTED == 1'), indirect=['target']) def test_driver_twai_loopbk(dut: Dut) -> None: @@ -36,6 +37,7 @@ def fixture_create_socket_can() -> Bus: @pytest.mark.twai_std +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14393') @pytest.mark.parametrize('config', ['release'], indirect=True) @idf_parametrize('target', soc_filtered_targets('SOC_TWAI_SUPPORTED == 1'), indirect=['target']) def test_driver_twai_listen_only(dut: Dut, socket_can: Bus) -> None: @@ -58,6 +60,7 @@ def test_driver_twai_listen_only(dut: Dut, socket_can: Bus) -> None: @pytest.mark.twai_std +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14393') @pytest.mark.parametrize('config', ['release'], indirect=True) @idf_parametrize('target', soc_filtered_targets('SOC_TWAI_SUPPORTED == 1'), indirect=['target']) def test_driver_twai_remote_request(dut: Dut, socket_can: Bus) -> None: diff --git a/components/esp_driver_uart/include/driver/uart.h b/components/esp_driver_uart/include/driver/uart.h index 8946ce126025..ca668019ca78 100644 --- a/components/esp_driver_uart/include/driver/uart.h +++ b/components/esp_driver_uart/include/driver/uart.h @@ -605,7 +605,9 @@ esp_err_t uart_flush_input(uart_port_t uart_num); esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t* size); /** - * @brief UART get TX ring buffer free space size + * @brief UART get TX ring buffer free space size for the next data to be enqueued + * + * It returns the tight conservative bound for NOSPLIT ring buffer overall enqueueable payload across up to two chunks. * * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). * @param size Pointer of size_t to accept the free space size diff --git a/components/esp_driver_uart/src/uart.c b/components/esp_driver_uart/src/uart.c index 8eb9caa1eb15..d8eaa6ba0b4d 100644 --- a/components/esp_driver_uart/src/uart.c +++ b/components/esp_driver_uart/src/uart.c @@ -143,7 +143,6 @@ typedef struct { bool coll_det_flg; /*!< UART collision detection flag */ bool rx_always_timeout_flg; /*!< UART always detect rx timeout flag */ int rx_buffered_len; /*!< UART cached data length */ - int rx_buf_size; /*!< RX ring buffer size */ bool rx_buffer_full_flg; /*!< RX ring buffer full flag. */ uint8_t *rx_data_buf; /*!< Data buffer to stash FIFO data*/ uint8_t rx_stash_len; /*!< stashed data length.(When using flow control, after reading out FIFO data, if we fail to push to buffer, we can just stash them.) */ @@ -153,8 +152,8 @@ typedef struct { bool tx_waiting_fifo; /*!< this flag indicates that some task is waiting for FIFO empty interrupt, used to send all data without any data buffer*/ uint8_t *tx_ptr; /*!< TX data pointer to push to FIFO in TX buffer mode*/ uart_tx_data_t *tx_head; /*!< TX data pointer to head of the current buffer in TX ring buffer*/ - uint32_t tx_len_tot; /*!< Total length of current item in ring buffer*/ - uint32_t tx_len_cur; + uint32_t trans_total_remaining_len; /*!< Remaining data length of the current processing transaction in TX ring buffer*/ + uint32_t trans_chunk_remaining_len; /*!< Remaining data length of the current processing chunk of the transaction in TX ring buffer*/ uint8_t tx_brk_flg; /*!< Flag to indicate to send a break signal in the end of the item sending procedure */ uint8_t tx_brk_len; /*!< TX break signal cycle length/number */ uint8_t tx_waiting_brk; /*!< Flag to indicate that TX FIFO is ready to send break signal after FIFO is empty, do not push data into TX FIFO right now.*/ @@ -221,6 +220,10 @@ static bool uart_module_enable(uart_port_t uart_num) uart_ll_enable_bus_clock(uart_num, true); } if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) { + // Workaround: Set RX signal to high to avoid false RX BRK_DET interrupt raised after register reset + if (uart_context[uart_num].rx_io_num == -1) { + esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), false); + } HP_UART_BUS_CLK_ATOMIC() { uart_ll_reset_register(uart_num); } @@ -251,6 +254,16 @@ static bool uart_module_enable(uart_port_t uart_num) } #if (SOC_UART_LP_NUM >= 1) else { + // Workaround: Set RX signal to high to avoid false RX BRK_DET interrupt raised after register reset + if (uart_context[uart_num].rx_io_num == -1) { // if RX pin is already configured, then workaround not needed, skip +#if SOC_LP_GPIO_MATRIX_SUPPORTED + lp_gpio_connect_in_signal(LP_GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), false); +#else + // the signal is directly connected to its LP IO pin, the only way is to enable its pullup + uint32_t io_num = uart_periph_signal[uart_num].pins[SOC_UART_RX_PIN_IDX].default_gpio; + gpio_pullup_en(io_num); +#endif + } LP_UART_BUS_CLK_ATOMIC() { lp_uart_ll_enable_bus_clock(TO_LP_UART_NUM(uart_num), true); lp_uart_ll_reset_register(TO_LP_UART_NUM(uart_num)); @@ -716,18 +729,26 @@ static bool uart_try_set_iomux_pin(uart_port_t uart_num, int io_num, uint32_t id } rtc_gpio_init(io_num); rtc_gpio_iomux_func_sel(io_num, upin->iomux_func); + // undo the workaround done in uart_module_enable for RX pin +#if !SOC_LP_GPIO_MATRIX_SUPPORTED + if (upin->input) { + gpio_pullup_dis(io_num); + } +#endif } #endif return true; } -static void uart_release_pin(uart_port_t uart_num) +static void uart_release_pin(uart_port_t uart_num, bool release_tx, bool release_rx, bool release_rts, bool release_cts) { if (uart_num >= UART_NUM_MAX) { return; } - if (uart_context[uart_num].tx_io_num >= 0) { + + uint32_t released_io_mask = 0; + if (release_tx && uart_context[uart_num].tx_io_num >= 0) { gpio_output_disable(uart_context[uart_num].tx_io_num); #if (SOC_UART_LP_NUM >= 1) if (!(uart_num < SOC_UART_HP_NUM)) { @@ -737,9 +758,12 @@ static void uart_release_pin(uart_port_t uart_num) #if CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND || CONFIG_PM_SLP_DISABLE_GPIO gpio_sleep_sel_en(uart_context[uart_num].tx_io_num); // re-enable the switch to the sleep configuration to save power consumption #endif + + released_io_mask |= BIT64(uart_context[uart_num].tx_io_num); + uart_context[uart_num].tx_io_num = -1; } - if (uart_context[uart_num].rx_io_num >= 0) { + if (release_rx && uart_context[uart_num].rx_io_num >= 0) { if (uart_num < SOC_UART_HP_NUM) { esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), false); } @@ -754,18 +778,24 @@ static void uart_release_pin(uart_port_t uart_num) #if CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND || CONFIG_PM_SLP_DISABLE_GPIO gpio_sleep_sel_en(uart_context[uart_num].rx_io_num); // re-enable the switch to the sleep configuration to save power consumption #endif + + released_io_mask |= BIT64(uart_context[uart_num].rx_io_num); + uart_context[uart_num].rx_io_num = -1; } - if (uart_context[uart_num].rts_io_num >= 0) { + if (release_rts && uart_context[uart_num].rts_io_num >= 0) { gpio_output_disable(uart_context[uart_num].rts_io_num); #if (SOC_UART_LP_NUM >= 1) if (!(uart_num < SOC_UART_HP_NUM)) { rtc_gpio_deinit(uart_context[uart_num].rts_io_num); } #endif + + released_io_mask |= BIT64(uart_context[uart_num].rts_io_num); + uart_context[uart_num].rts_io_num = -1; } - if (uart_context[uart_num].cts_io_num >= 0) { + if (release_cts && uart_context[uart_num].cts_io_num >= 0) { if (uart_num < SOC_UART_HP_NUM) { esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), false); } @@ -777,15 +807,13 @@ static void uart_release_pin(uart_port_t uart_num) rtc_gpio_deinit(uart_context[uart_num].cts_io_num); } #endif - } - esp_gpio_revoke(uart_context[uart_num].io_reserved_mask); + released_io_mask |= BIT64(uart_context[uart_num].cts_io_num); + uart_context[uart_num].cts_io_num = -1; + } - uart_context[uart_num].tx_io_num = -1; - uart_context[uart_num].rx_io_num = -1; - uart_context[uart_num].rts_io_num = -1; - uart_context[uart_num].cts_io_num = -1; - uart_context[uart_num].io_reserved_mask = 0; + esp_gpio_revoke(uart_context[uart_num].io_reserved_mask & released_io_mask); + uart_context[uart_num].io_reserved_mask &= ~released_io_mask; } esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int rts_io_num, int cts_io_num) @@ -820,7 +848,7 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r #endif // First, release previously configured IOs if there is - uart_release_pin(uart_num); + uart_release_pin(uart_num, (tx_io_num >= 0), (rx_io_num >= 0), (rts_io_num >= 0), (cts_io_num >= 0)); // Potential IO reserved mask uint64_t io_reserve_mask = 0; @@ -987,8 +1015,8 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf uint32_t sclk_freq; ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(uart_sclk_sel, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "invalid src_clk"); - // Enable the newly selected clock source. - ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(uart_sclk_sel, true), UART_TAG, "clock source enable failed"); + // Enable the newly selected clock source + esp_clk_tree_enable_src(uart_sclk_sel, true); #if SOC_UART_SUPPORT_RTC_CLK if (uart_sclk_sel == (soc_module_clk_t)UART_SCLK_RTC) { periph_rtc_dig_clk8m_enable(); @@ -997,8 +1025,6 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf bool success = false; UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); - soc_module_clk_t uart_old_sclk_sel = uart_context[uart_num].sclk_sel; - uart_context[uart_num].sclk_sel = uart_sclk_sel; uart_hal_init(&(uart_context[uart_num].hal), uart_num); if (uart_num < SOC_UART_HP_NUM) { HP_UART_SRC_CLK_ATOMIC() { @@ -1014,7 +1040,6 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf success = lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, uart_config->baud_rate, sclk_freq); } #endif - // Disable the previously selected clock source uart_hal_set_parity(&(uart_context[uart_num].hal), uart_config->parity); uart_hal_set_data_bit_num(&(uart_context[uart_num].hal), uart_config->data_bits); uart_hal_set_stop_bits(&(uart_context[uart_num].hal), uart_config->stop_bits); @@ -1023,8 +1048,18 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); uart_hal_rxfifo_rst(&(uart_context[uart_num].hal)); uart_hal_txfifo_rst(&(uart_context[uart_num].hal)); - ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(uart_old_sclk_sel, false), UART_TAG, "clock source disable failed"); - ESP_RETURN_ON_FALSE(success, ESP_FAIL, UART_TAG, "baud rate unachievable"); + // Disable the previously selected clock source, and update the new source in context + soc_module_clk_t uart_old_sclk_sel = uart_context[uart_num].sclk_sel; + esp_clk_tree_enable_src(uart_old_sclk_sel, false); + if (success) { + uart_context[uart_num].sclk_sel = uart_sclk_sel; + } else { + uart_context[uart_num].sclk_sel = -1; + esp_clk_tree_enable_src(uart_sclk_sel, false); + ESP_LOGE(UART_TAG, "baud rate unachievable"); + return ESP_FAIL; + } + #if SOC_UART_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP // Create sleep retention link if desired if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM && uart_num < SOC_UART_HP_NUM) { @@ -1152,15 +1187,15 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param) //That would cause a watch_dog reset because empty interrupt happens so often. //Although this is a loop in ISR, this loop will execute at most 128 turns. while (tx_fifo_rem) { - if (p_uart->tx_len_tot == 0 || p_uart->tx_ptr == NULL || p_uart->tx_len_cur == 0) { + if (p_uart->trans_total_remaining_len == 0 || p_uart->tx_ptr == NULL || p_uart->trans_chunk_remaining_len == 0) { size_t size; p_uart->tx_head = (uart_tx_data_t *) xRingbufferReceiveFromISR(p_uart->tx_ring_buf, &size); if (p_uart->tx_head) { //The first item is the data description //Get the first item to get the data information - if (p_uart->tx_len_tot == 0) { + if (p_uart->trans_total_remaining_len == 0) { p_uart->tx_ptr = NULL; - p_uart->tx_len_tot = p_uart->tx_head->tx_data.size; + p_uart->trans_total_remaining_len = p_uart->tx_head->tx_data.size; if (p_uart->tx_head->type == UART_DATA_BREAK) { p_uart->tx_brk_flg = 1; p_uart->tx_brk_len = p_uart->tx_head->tx_data.brk_len; @@ -1172,22 +1207,22 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param) //Update the TX item pointer, we will need this to return item to buffer. p_uart->tx_ptr = (uint8_t *)p_uart->tx_head; en_tx_flg = true; - p_uart->tx_len_cur = size; + p_uart->trans_chunk_remaining_len = size; } } else { //Can not get data from ring buffer, return; break; } } - if (p_uart->tx_len_tot > 0 && p_uart->tx_ptr && p_uart->tx_len_cur > 0) { + if (p_uart->trans_total_remaining_len > 0 && p_uart->tx_ptr && p_uart->trans_chunk_remaining_len > 0) { // To fill the TX FIFO. uint32_t send_len = uart_enable_tx_write_fifo(uart_num, (const uint8_t *) p_uart->tx_ptr, - MIN(p_uart->tx_len_cur, tx_fifo_rem)); + MIN(p_uart->trans_chunk_remaining_len, tx_fifo_rem)); p_uart->tx_ptr += send_len; - p_uart->tx_len_tot -= send_len; - p_uart->tx_len_cur -= send_len; + p_uart->trans_total_remaining_len -= send_len; + p_uart->trans_chunk_remaining_len -= send_len; tx_fifo_rem -= send_len; - if (p_uart->tx_len_cur == 0) { + if (p_uart->trans_chunk_remaining_len == 0) { //Return item to ring buffer. vRingbufferReturnItemFromISR(p_uart->tx_ring_buf, p_uart->tx_head, &HPTaskAwoken); need_yield |= (HPTaskAwoken == pdTRUE); @@ -1195,7 +1230,7 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param) p_uart->tx_ptr = NULL; //Sending item done, now we need to send break if there is a record. //Set TX break signal after FIFO is empty - if (p_uart->tx_len_tot == 0 && p_uart->tx_brk_flg == 1) { + if (p_uart->trans_total_remaining_len == 0 && p_uart->tx_brk_flg == 1) { uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE); UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); uart_hal_tx_break(&(uart_context[uart_num].hal), p_uart->tx_brk_len); @@ -1522,6 +1557,8 @@ int uart_tx_chars(uart_port_t uart_num, const char *buffer, uint32_t len) return tx_len; } +// Per transaction in the ring buffer: +// A data description item, followed by one or more data chunk items static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool brk_en, int brk_len) { if (size == 0) { @@ -1536,7 +1573,6 @@ static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool #endif p_uart_obj[uart_num]->coll_det_flg = false; if (p_uart_obj[uart_num]->tx_buf_size > 0) { - size_t max_size = xRingbufferGetMaxItemSize(p_uart_obj[uart_num]->tx_ring_buf); int offset = 0; uart_tx_data_t evt; evt.tx_data.size = size; @@ -1548,11 +1584,14 @@ static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool } xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *) &evt, sizeof(uart_tx_data_t), portMAX_DELAY); while (size > 0) { - size_t send_size = size > max_size / 2 ? max_size / 2 : size; - xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *)(src + offset), send_size, portMAX_DELAY); - size -= send_size; - offset += send_size; - uart_enable_tx_intr(uart_num, 1, UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT)); + size_t free_size = xRingbufferGetCurFreeSize(p_uart_obj[uart_num]->tx_ring_buf); + size_t send_size = MIN(size, free_size); + if (send_size > 0) { + xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *)(src + offset), send_size, portMAX_DELAY); + size -= send_size; + offset += send_size; + uart_enable_tx_intr(uart_num, 1, UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT)); + } } } else { while (size) { @@ -1676,7 +1715,79 @@ esp_err_t uart_get_tx_buffer_free_size(uart_port_t uart_num, size_t *size) ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error"); ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), ESP_ERR_INVALID_ARG, UART_TAG, "uart driver error"); ESP_RETURN_ON_FALSE((size != NULL), ESP_ERR_INVALID_ARG, UART_TAG, "arg pointer is NULL"); - *size = p_uart_obj[uart_num]->tx_buf_size - p_uart_obj[uart_num]->tx_len_tot; + + // If tx buffer is disabled or ring buffer is full, overall enqueueable payload is 0 + if (p_uart_obj[uart_num]->tx_buf_size == 0 || xRingbufferGetCurFreeSize(p_uart_obj[uart_num]->tx_ring_buf) == 0) { + *size = 0; + return ESP_OK; + } + + // Tight conservative bound for NOSPLIT ring buffer overall enqueueable payload across up to two segments + const size_t RINGBUF_ITEM_HDR_SIZE = 8; // per public ringbuf API docs + + // Per-item cap in current state and basis to infer minimal buffer size + size_t max_item = xRingbufferGetMaxItemSize(p_uart_obj[uart_num]->tx_ring_buf); + + // Get current ring buffer pointer offsets and items waiting to detect empty + UBaseType_t off_free = 0; + UBaseType_t off_acq = 0; + UBaseType_t items_waiting = 0; + vRingbufferGetInfo(p_uart_obj[uart_num]->tx_ring_buf, &off_free, NULL, NULL, &off_acq, &items_waiting); + + // Minimal possible total buffer size for NOSPLIT: see ringbuf initialization logic + // xMaxItemSize = ALIGN4(xSize/2) - header => xSize_min = 2 * (xMaxItemSize + header - up_to_3_alignment) + size_t buf_size_min = 2 * (max_item + RINGBUF_ITEM_HDR_SIZE - 3); + buf_size_min &= ~((size_t)3); // align down to 4 bytes + + size_t total_payload = 0; + if (off_acq == off_free && items_waiting == 0) { + // Empty buffer: conservatively treat as a single large contiguous segment + total_payload = p_uart_obj[uart_num]->tx_buf_size - RINGBUF_ITEM_HDR_SIZE; + } else if (off_acq <= off_free) { + // Single contiguous free segment + size_t seg = (size_t)off_free - (size_t)off_acq; + if (seg > RINGBUF_ITEM_HDR_SIZE) { + size_t usable = seg - RINGBUF_ITEM_HDR_SIZE; + usable &= ~((size_t)3); + if (usable > max_item) { + usable = max_item; + } + total_payload = usable; + } + } else { + // Free space wraps: two segments [acq..tail) and [head..free) + size_t seg1 = buf_size_min - (size_t)off_acq; + size_t seg2 = (size_t)off_free; // from head (offset 0) to free + size_t payload1 = 0; + if (seg1 > RINGBUF_ITEM_HDR_SIZE) { + size_t usable1 = seg1 - RINGBUF_ITEM_HDR_SIZE; + usable1 &= ~((size_t)3); + if (usable1 > max_item) { + usable1 = max_item; + } + payload1 = usable1; + } + size_t payload2 = 0; + if (seg2 > RINGBUF_ITEM_HDR_SIZE) { + size_t usable2 = seg2 - RINGBUF_ITEM_HDR_SIZE; + usable2 &= ~((size_t)3); + if (usable2 > max_item) { + usable2 = max_item; + } + payload2 = usable2; + } + total_payload = payload1 + payload2; + } + + // Subtract the cost of the transaction's data description item (header + aligned struct) + size_t desc_cost = RINGBUF_ITEM_HDR_SIZE + (((sizeof(uart_tx_data_t)) + 3) & ~((size_t)3)); + if (total_payload > desc_cost) { + total_payload -= desc_cost; + } else { + total_payload = 0; + } + + *size = total_payload; return ESP_OK; } @@ -1852,7 +1963,8 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b p_uart_obj[uart_num]->event_queue_size = event_queue_size; p_uart_obj[uart_num]->tx_ptr = NULL; p_uart_obj[uart_num]->tx_head = NULL; - p_uart_obj[uart_num]->tx_len_tot = 0; + p_uart_obj[uart_num]->trans_total_remaining_len = 0; + p_uart_obj[uart_num]->trans_chunk_remaining_len = 0; p_uart_obj[uart_num]->tx_brk_flg = 0; p_uart_obj[uart_num]->tx_brk_len = 0; p_uart_obj[uart_num]->tx_waiting_brk = 0; @@ -1873,12 +1985,6 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b return ESP_FAIL; } - uart_intr_config_t uart_intr = { - .intr_enable_mask = UART_INTR_CONFIG_FLAG, - .rxfifo_full_thresh = UART_THRESHOLD_NUM(uart_num, UART_FULL_THRESH_DEFAULT), - .rx_timeout_thresh = UART_TOUT_THRESH_DEFAULT, - .txfifo_empty_intr_thresh = UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT), - }; uart_module_enable(uart_num); uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK); uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK); @@ -1888,6 +1994,42 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b &p_uart_obj[uart_num]->intr_handle); ESP_GOTO_ON_ERROR(ret, err, UART_TAG, "Could not allocate an interrupt for UART"); + // Make sure uart sclk at least exist first (following code touchs hardware, and requires sclk to be enabled) + if (uart_context[uart_num].sclk_sel == -1 && uart_num != CONFIG_ESP_CONSOLE_UART_NUM) { + // set to a default clock source + soc_module_clk_t default_sclk = -1; + if (uart_num < SOC_UART_HP_NUM) { + default_sclk = UART_SCLK_DEFAULT; + } +#if (SOC_UART_LP_NUM >= 1) + else { + default_sclk = LP_UART_SCLK_DEFAULT; + } +#endif + esp_clk_tree_enable_src(default_sclk, true); + UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); + if (uart_num < SOC_UART_HP_NUM) { + HP_UART_SRC_CLK_ATOMIC() { + uart_hal_set_sclk(&(uart_context[uart_num].hal), default_sclk); + } + } +#if (SOC_UART_LP_NUM >= 1) + else { + LP_UART_SRC_CLK_ATOMIC() { + lp_uart_ll_set_source_clk(uart_context[uart_num].hal.dev, (soc_periph_lp_uart_clk_src_t)default_sclk); + } + } +#endif + uart_context[uart_num].sclk_sel = default_sclk; + UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); + } + + uart_intr_config_t uart_intr = { + .intr_enable_mask = UART_INTR_CONFIG_FLAG, + .rxfifo_full_thresh = UART_THRESHOLD_NUM(uart_num, UART_FULL_THRESH_DEFAULT), + .rx_timeout_thresh = UART_TOUT_THRESH_DEFAULT, + .txfifo_empty_intr_thresh = UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT), + }; ret = uart_intr_config(uart_num, &uart_intr); ESP_GOTO_ON_ERROR(ret, err, UART_TAG, "Could not configure the interrupt for UART"); @@ -1907,7 +2049,7 @@ esp_err_t uart_driver_delete(uart_port_t uart_num) return ESP_OK; } - uart_release_pin(uart_num); + uart_release_pin(uart_num, true, true, true, true); esp_intr_free(p_uart_obj[uart_num]->intr_handle); uart_disable_rx_intr(uart_num); @@ -1916,14 +2058,15 @@ esp_err_t uart_driver_delete(uart_port_t uart_num) uart_free_driver_obj(p_uart_obj[uart_num]); p_uart_obj[uart_num] = NULL; - ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(uart_context[uart_num].sclk_sel, false), UART_TAG, "clock source disable failed"); + if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) { + esp_clk_tree_enable_src(uart_context[uart_num].sclk_sel, false); #if SOC_UART_SUPPORT_RTC_CLK - soc_module_clk_t sclk = 0; - uart_hal_get_sclk(&(uart_context[uart_num].hal), &sclk); - if (sclk == (soc_module_clk_t)UART_SCLK_RTC) { - periph_rtc_dig_clk8m_disable(); - } + if (uart_context[uart_num].sclk_sel == (soc_module_clk_t)UART_SCLK_RTC) { + periph_rtc_dig_clk8m_disable(); + } #endif + uart_context[uart_num].sclk_sel = -1; + } #if SOC_UART_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP // Free sleep retention link for HP UART @@ -2125,7 +2268,7 @@ esp_err_t uart_detect_bitrate_start(uart_port_t uart_num, const uart_bitrate_det uart_sclk_sel = (soc_module_clk_t)((config->source_clk) ? config->source_clk : UART_SCLK_DEFAULT); // if no specifying the clock source (soc_module_clk_t starts from 1), then just use the default clock uint32_t sclk_freq = 0; ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz(uart_sclk_sel, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), err, UART_TAG, "invalid source_clk"); - ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src(uart_sclk_sel, true), err, UART_TAG, "clock source enable failed"); + esp_clk_tree_enable_src(uart_sclk_sel, true); #if SOC_UART_SUPPORT_RTC_CLK if (uart_sclk_sel == (soc_module_clk_t)UART_SCLK_RTC) { periph_rtc_dig_clk8m_enable(); @@ -2135,6 +2278,7 @@ esp_err_t uart_detect_bitrate_start(uart_port_t uart_num, const uart_bitrate_det uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel); uart_hal_set_baudrate(&(uart_context[uart_num].hal), 57600, sclk_freq); // set to any baudrate } + uart_context[uart_num].sclk_sel = uart_sclk_sel; uart_set_pin(uart_num, UART_PIN_NO_CHANGE, config->rx_io_num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); } else if (config != NULL) { ESP_LOGW(UART_TAG, "unable to re-configure for an acquired port, ignoring the new config"); @@ -2186,13 +2330,16 @@ esp_err_t uart_detect_bitrate_stop(uart_port_t uart_num, bool deinit, uart_bitra } if (deinit) { // release the port - uart_release_pin(uart_num); - ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(uart_context[uart_num].sclk_sel, false), UART_TAG, "clock source disable failed"); + uart_release_pin(uart_num, true, true, true, true); + if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) { + esp_clk_tree_enable_src(uart_context[uart_num].sclk_sel, false); #if SOC_UART_SUPPORT_RTC_CLK - if (src_clk == (soc_module_clk_t)UART_SCLK_RTC) { - periph_rtc_dig_clk8m_disable(); - } + if (src_clk == (soc_module_clk_t)UART_SCLK_RTC) { + periph_rtc_dig_clk8m_disable(); + } #endif + uart_context[uart_num].sclk_sel = -1; + } uart_module_disable(uart_num); } return ret; diff --git a/components/esp_driver_uart/test_apps/rs485/main/test_app_main.c b/components/esp_driver_uart/test_apps/rs485/main/test_app_main.c index cfdd58655af4..ad7c76757443 100644 --- a/components/esp_driver_uart/test_apps/rs485/main/test_app_main.c +++ b/components/esp_driver_uart/test_apps/rs485/main/test_app_main.c @@ -10,7 +10,7 @@ #include "esp_heap_caps.h" #include "esp_newlib.h" -#define TEST_MEMORY_LEAK_THRESHOLD (200) +#define TEST_MEMORY_LEAK_THRESHOLD (250) void setUp(void) { diff --git a/components/esp_driver_uart/test_apps/uart/main/test_uart.c b/components/esp_driver_uart/test_apps/uart/main/test_uart.c index 06b85f3b5e64..59ee006bfbad 100644 --- a/components/esp_driver_uart/test_apps/uart/main/test_uart.c +++ b/components/esp_driver_uart/test_apps/uart/main/test_uart.c @@ -419,23 +419,73 @@ TEST_CASE("uart tx with ringbuffer test", "[uart]") rd_data[i] = 0; } - size_t tx_buffer_free_space; - uart_get_tx_buffer_free_size(uart_num, &tx_buffer_free_space); - TEST_ASSERT_EQUAL_INT(2048, tx_buffer_free_space); // full tx buffer space is free uart_write_bytes(uart_num, (const char *)wr_data, 1024); - uart_get_tx_buffer_free_size(uart_num, &tx_buffer_free_space); - TEST_ASSERT_LESS_THAN(2048, tx_buffer_free_space); // tx transmit in progress: tx buffer has content - TEST_ASSERT_GREATER_OR_EQUAL(1024, tx_buffer_free_space); uart_wait_tx_done(uart_num, portMAX_DELAY); - uart_get_tx_buffer_free_size(uart_num, &tx_buffer_free_space); - TEST_ASSERT_EQUAL_INT(2048, tx_buffer_free_space); // tx done: tx buffer back to empty + uart_read_bytes(uart_num, rd_data, 1024, pdMS_TO_TICKS(1000)); TEST_ASSERT_EQUAL_HEX8_ARRAY(wr_data, rd_data, 1024); + TEST_ESP_OK(uart_driver_delete(uart_num)); free(rd_data); free(wr_data); } +TEST_CASE("uart tx ring buffer free space test", "[uart]") +{ + uart_port_param_t port_param = {}; + TEST_ASSERT(port_select(&port_param)); + // This is a test on the driver API, no need to test for both HP/LP uart port, call port_select() to be compatible with pytest + // Let's only test on HP UART + if (port_param.port_num < SOC_UART_HP_NUM) { + uart_port_t uart_num = port_param.port_num; + uint8_t *rd_data = (uint8_t *)malloc(1024); + TEST_ASSERT_NOT_NULL(rd_data); + uint8_t *wr_data = (uint8_t *)malloc(2048); + TEST_ASSERT_NOT_NULL(wr_data); + uart_config_t uart_config = { + .baud_rate = 2000000, + .data_bits = UART_DATA_8_BITS, + .parity = UART_PARITY_DISABLE, + .stop_bits = UART_STOP_BITS_1, + .flow_ctrl = UART_HW_FLOWCTRL_CTS_RTS, + .rx_flow_ctrl_thresh = port_param.rx_flow_ctrl_thresh, + .source_clk = port_param.default_src_clk, + }; + uart_wait_tx_idle_polling(uart_num); + TEST_ESP_OK(uart_param_config(uart_num, &uart_config)); + TEST_ESP_OK(uart_driver_install(uart_num, 256, 1024 * 2, 20, NULL, 0)); + // Let CTS be high, so that transmission is blocked + esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, uart_periph_signal[uart_num].pins[SOC_UART_CTS_PIN_IDX].signal, false); + + // When nothing pushed to the TX ring buffer, the free space should be the full capacity + size_t tx_buffer_free_space; + uart_get_tx_buffer_free_size(uart_num, &tx_buffer_free_space); + TEST_ASSERT_EQUAL_INT(2020, tx_buffer_free_space); // no-split ring buffer: 2048 - 20 (data description item) - 8 (header) + + // Push 1024 bytes to the TX ring buffer + uart_write_bytes(uart_num, (const char *)wr_data, 1024); // two chunks + vTaskDelay(pdMS_TO_TICKS(500)); + uart_get_tx_buffer_free_size(uart_num, &tx_buffer_free_space); + TEST_ASSERT_LESS_THAN(2020, tx_buffer_free_space); // tx buffer has content + TEST_ASSERT_GREATER_OR_EQUAL(952, tx_buffer_free_space); + + // Fill the remaining space in the TX ring buffer + uart_write_bytes(uart_num, (const char *)wr_data, tx_buffer_free_space); + uart_get_tx_buffer_free_size(uart_num, &tx_buffer_free_space); + TEST_ASSERT_EQUAL_INT(0, tx_buffer_free_space); // tx buffer is full + + // Let CTS be low, so that transmission is unblocked + esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, uart_periph_signal[uart_num].pins[SOC_UART_CTS_PIN_IDX].signal, false); + uart_wait_tx_done(uart_num, portMAX_DELAY); + uart_get_tx_buffer_free_size(uart_num, &tx_buffer_free_space); + TEST_ASSERT_EQUAL_INT(2020, tx_buffer_free_space); // tx buffer is back to full capacity + + TEST_ESP_OK(uart_driver_delete(uart_num)); + free(rd_data); + free(wr_data); + } +} + TEST_CASE("uart int state restored after flush", "[uart]") { uart_port_param_t port_param = {}; diff --git a/components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml b/components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml index 88ae1369439d..6a34e96a2072 100644 --- a/components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml +++ b/components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml @@ -3,6 +3,9 @@ components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag: disable: - if: SOC_USB_SERIAL_JTAG_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14364 disable_test: - if: IDF_TARGET in ["esp32p4", "esp32c5", "esp32c61"] temporary: true @@ -15,6 +18,9 @@ components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag: components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag_vfs: disable: - if: SOC_USB_SERIAL_JTAG_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14364 disable_test: - if: IDF_TARGET in ["esp32p4", "esp32c5", "esp32c61"] temporary: true diff --git a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/README.md b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/README.md index c1d7d543d389..e3a01dc27f42 100644 --- a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/README.md +++ b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | diff --git a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag_vfs/README.md b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag_vfs/README.md index c1d7d543d389..e3a01dc27f42 100644 --- a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag_vfs/README.md +++ b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag_vfs/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | diff --git a/components/esp_eth/test_apps/.build-test-rules.yml b/components/esp_eth/test_apps/.build-test-rules.yml index dc4d00c17b3e..3d07cc18a3c0 100644 --- a/components/esp_eth/test_apps/.build-test-rules.yml +++ b/components/esp_eth/test_apps/.build-test-rules.yml @@ -2,7 +2,7 @@ components/esp_eth/test_apps: enable: - - if: IDF_TARGET in ["esp32", "esp32p4"] + - if: IDF_TARGET in ["esp32"] # TODO: IDF-14365 reason: ESP32 and ESP32P4 have internal EMAC. SPI Ethernet runners are based on ESP32. depends_components: - esp_eth diff --git a/components/esp_eth/test_apps/README.md b/components/esp_eth/test_apps/README.md index 9747c000db1c..0e2cf8cb135a 100644 --- a/components/esp_eth/test_apps/README.md +++ b/components/esp_eth/test_apps/README.md @@ -1,6 +1,6 @@ # EMAC Test -| Supported Targets | ESP32 | ESP32-P4 | -| ----------------- | ----- | -------- | +| Supported Targets | ESP32 | +| ----------------- | ----- | This test app is used to test Ethernet MAC behavior with different chips. diff --git a/components/esp_eth/test_apps/pytest_esp_eth.py b/components/esp_eth/test_apps/pytest_esp_eth.py index b151a1f1f35a..4a2b4003cc6c 100644 --- a/components/esp_eth/test_apps/pytest_esp_eth.py +++ b/components/esp_eth/test_apps/pytest_esp_eth.py @@ -49,7 +49,7 @@ def find_target_if(self, my_if: str = '') -> None: def configure_eth_if(self, eth_type: int = 0) -> Iterator[socket.socket]: if eth_type == 0: eth_type = self.eth_type - so = socket.socket(socket.AF_PACKET, socket.SOCK_RAW, socket.htons(eth_type)) + so = socket.socket(socket.AF_PACKET, socket.SOCK_RAW, socket.htons(eth_type)) # type: ignore[attr-defined] so.bind((self.target_if, 0)) try: yield so @@ -288,6 +288,7 @@ def test_esp_eth_ip101(dut: IdfDut) -> None: # ----------- IP101 ESP32P4 ----------- @pytest.mark.eth_ip101 +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14365') @pytest.mark.parametrize( 'config', [ @@ -303,6 +304,7 @@ def test_esp32p4_ethernet(dut: IdfDut) -> None: @pytest.mark.eth_ip101 +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14365') @pytest.mark.parametrize( 'config', [ @@ -318,6 +320,7 @@ def test_esp32p4_emac(dut: IdfDut) -> None: @pytest.mark.eth_ip101 +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14365') @pytest.mark.parametrize( 'config', [ diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig index d10906be9303..d10007399d7d 100644 --- a/components/esp_hw_support/Kconfig +++ b/components/esp_hw_support/Kconfig @@ -133,12 +133,11 @@ menu "Hardware Settings" config ESP_SLEEP_GPIO_RESET_WORKAROUND bool "light sleep GPIO reset workaround" - default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || \ - IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32C5 + default y if !(IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2) select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE help - esp32c2, esp32c3, esp32s3, esp32c5, esp32c6 and esp32h2 will reset at wake-up if GPIO is received - a small electrostatic pulse during light sleep, with specific condition + All existing chips except esp32 and esp32s2 will reset on wake-up if a GPIO receives + a small electrostatic pulse during light sleep, with specific conditions. - GPIO needs to be configured as input-mode only - The pin receives a small electrostatic pulse, and reset occurs when the pulse diff --git a/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c b/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c index 33387c0c7204..99ff4f03297d 100644 --- a/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c +++ b/components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c @@ -509,6 +509,7 @@ static TCM_IRAM_ATTR void smp_core_do_retention(void) // Wait another core start to do retention bool smp_skip_retention = false; smp_retention_state_t another_core_state; + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-infinite-loop") while (1) { another_core_state = atomic_load(&s_smp_retention_state[!core_id]); if (another_core_state == SMP_SKIP_RETENTION) { @@ -519,6 +520,7 @@ static TCM_IRAM_ATTR void smp_core_do_retention(void) break; } } + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-infinite-loop") if (!smp_skip_retention) { atomic_store(&s_smp_retention_state[core_id], SMP_BACKUP_START); @@ -580,9 +582,11 @@ void sleep_smp_cpu_wakeup_prepare(void) #if ESP_SLEEP_POWER_DOWN_CPU uint8_t core_id = esp_cpu_get_core_id(); if (atomic_load(&s_smp_retention_state[core_id]) == SMP_RESTORE_DONE) { + ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-infinite-loop") while (atomic_load(&s_smp_retention_state[!core_id]) != SMP_RESTORE_DONE) { ; } + ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-infinite-loop") } atomic_store(&s_smp_retention_state[core_id], SMP_IDLE); #else diff --git a/components/esp_hw_support/port/esp32c5/esp_clk_tree.c b/components/esp_hw_support/port/esp32c5/esp_clk_tree.c index c3dfa3494770..b2bf766c51b7 100644 --- a/components/esp_hw_support/port/esp32c5/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32c5/esp_clk_tree.c @@ -76,10 +76,9 @@ static bool esp_clk_tree_initialized = false; void esp_clk_tree_initialize(void) { soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); - if (((rst_reason == RESET_REASON_CPU0_MWDT0) || (rst_reason == RESET_REASON_CPU0_MWDT1) \ + if ((rst_reason == RESET_REASON_CPU0_MWDT0) || (rst_reason == RESET_REASON_CPU0_MWDT1) \ || (rst_reason == RESET_REASON_CPU0_SW) || (rst_reason == RESET_REASON_CPU0_RTC_WDT) \ - || (rst_reason == RESET_REASON_CPU0_JTAG) || (rst_reason == RESET_REASON_CPU0_LOCKUP)) \ - && (REG_READ(RTC_CLK_SRC_REF_CNT_ARRAY_REG) == (uint32_t)s_pll_src_cg_ref_cnt)) { + || (rst_reason == RESET_REASON_CPU0_JTAG) || (rst_reason == RESET_REASON_CPU0_LOCKUP)) { esp_clk_tree_initialized = true; return; } diff --git a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support index f1d582651d78..7699334a4af2 100644 --- a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support +++ b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support @@ -3,6 +3,7 @@ comment "Read the help text of the option below for explanation" config ESP32P4_SELECTS_REV_LESS_V3 bool "Select ESP32-P4 revisions <3.0 (No >=3.x Support)" + default n if IDF_CI_BUILD default y help Select this option to support ESP32-P4 revisions 0.x and 1.x. diff --git a/components/esp_hw_support/test_apps/.build-test-rules.yml b/components/esp_hw_support/test_apps/.build-test-rules.yml index 46d53f32424f..5412abcfd692 100644 --- a/components/esp_hw_support/test_apps/.build-test-rules.yml +++ b/components/esp_hw_support/test_apps/.build-test-rules.yml @@ -11,6 +11,10 @@ components/esp_hw_support/test_apps/dma: components/esp_hw_support/test_apps/dma2d: disable: - if: SOC_DMA2D_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14471 depends_filepatterns: - components/esp_hw_support/dma/**/* @@ -21,6 +25,9 @@ components/esp_hw_support/test_apps/host_test_linux: components/esp_hw_support/test_apps/mspi: disable: - if: IDF_TARGET not in ["esp32c5", "esp32c61", "esp32s3", "esp32p4"] + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14366 components/esp_hw_support/test_apps/mspi_psram_with_dfs: disable: @@ -33,6 +40,10 @@ components/esp_hw_support/test_apps/rtc_8md256: components/esp_hw_support/test_apps/rtc_clk: disable: - if: SOC_CLK_TREE_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14441 components/esp_hw_support/test_apps/rtc_power_modes: enable: @@ -48,11 +59,14 @@ components/esp_hw_support/test_apps/sleep_retention: components/esp_hw_support/test_apps/vad_wakeup: disable: - if: SOC_LP_VAD_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14368 components/esp_hw_support/test_apps/wakeup_tests: enable: - if: SOC_DEEP_SLEEP_SUPPORTED == 1 and SOC_LIGHT_SLEEP_SUPPORTED == 1 disable_test: - - if: IDF_TARGET in ["esp32h21", "esp32h4"] + - if: IDF_TARGET in ["esp32h21", "esp32h4", "esp32p4"] temporary: true - reason: lack of runners + reason: lack of runners # TODO: IDF-14400 diff --git a/components/esp_hw_support/test_apps/dma2d/pytest_dma2d.py b/components/esp_hw_support/test_apps/dma2d/pytest_dma2d.py index 314949f22247..3a55fff306ba 100644 --- a/components/esp_hw_support/test_apps/dma2d/pytest_dma2d.py +++ b/components/esp_hw_support/test_apps/dma2d/pytest_dma2d.py @@ -14,5 +14,6 @@ indirect=True, ) @idf_parametrize('target', ['esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14471') def test_dma2d(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_hw_support/test_apps/mspi/README.md b/components/esp_hw_support/test_apps/mspi/README.md index fbd388ce7036..9603da7376dc 100644 --- a/components/esp_hw_support/test_apps/mspi/README.md +++ b/components/esp_hw_support/test_apps/mspi/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C61 | ESP32-P4 | ESP32-S3 | -| ----------------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C61 | ESP32-S3 | +| ----------------- | -------- | --------- | -------- | This project tests if Flash and PSRAM can work under different configurations. To add new configuration, create one more sdkconfig.ci.NAME file in this directory. diff --git a/components/esp_hw_support/test_apps/mspi/pytest_flash_psram.py b/components/esp_hw_support/test_apps/mspi/pytest_flash_psram.py index 4925c8c0a9fd..27b826b1f55c 100644 --- a/components/esp_hw_support/test_apps/mspi/pytest_flash_psram.py +++ b/components/esp_hw_support/test_apps/mspi/pytest_flash_psram.py @@ -49,6 +49,7 @@ def test_flash4_psram4(dut: IdfDut) -> None: @pytest.mark.flash_120m +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14366') @pytest.mark.parametrize( 'config', [ diff --git a/components/esp_hw_support/test_apps/rtc_clk/pytest_rtc_clk.py b/components/esp_hw_support/test_apps/rtc_clk/pytest_rtc_clk.py index bd3bb67f9191..b9cd310362c7 100644 --- a/components/esp_hw_support/test_apps/rtc_clk/pytest_rtc_clk.py +++ b/components/esp_hw_support/test_apps/rtc_clk/pytest_rtc_clk.py @@ -10,6 +10,7 @@ @pytest.mark.generic @idf_parametrize('target', soc_filtered_targets('SOC_CLK_TREE_SUPPORTED == 1'), indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14441') def test_rtc_clk(case_tester: CaseTester) -> None: for case in case_tester.test_menu: if 'test_env' in case.attributes: @@ -30,6 +31,7 @@ def test_rtc_no_xtal32k(dut: IdfDut) -> None: @pytest.mark.generic +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14441') @idf_parametrize('target', soc_filtered_targets('SOC_CLK_TREE_SUPPORTED == 1'), indirect=['target']) def test_rtc_calib_compensation_across_dslp(case_tester: CaseTester) -> None: case_tester.run_all_multi_stage_cases() diff --git a/components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py b/components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py index 3560100cc7a1..da1feb33398c 100644 --- a/components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py +++ b/components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py @@ -40,6 +40,7 @@ @pytest.mark.generic_multi_device +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14400') @pytest.mark.parametrize('count', [2], indirect=True) @pytest.mark.parametrize('config', TEST_CONFIGS, indirect=True) @idf_parametrize( @@ -97,6 +98,7 @@ def test_ext1_deepsleep(dut: Tuple[IdfDut, IdfDut]) -> None: @pytest.mark.generic_multi_device @pytest.mark.parametrize('count', [2], indirect=True) @pytest.mark.parametrize('config', TEST_CONFIGS, indirect=True) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14400') @idf_parametrize('target', ['esp32c2', 'esp32c3', 'esp32c6', 'esp32p4', 'esp32c5'], indirect=['target']) def test_rtcio_deepsleep(dut: Tuple[IdfDut, IdfDut]) -> None: wakee = dut[0] @@ -142,6 +144,7 @@ def test_rtcio_deepsleep(dut: Tuple[IdfDut, IdfDut]) -> None: @pytest.mark.generic_multi_device @pytest.mark.parametrize('count', [2], indirect=True) @pytest.mark.parametrize('config', TEST_CONFIGS, indirect=True) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14400') @idf_parametrize('target', ['supported_targets'], indirect=['target']) def test_gpio_wakeup_enable_lightsleep(dut: Tuple[IdfDut, IdfDut]) -> None: wakee = dut[0] diff --git a/components/esp_mm/test_apps/.build-test-rules.yml b/components/esp_mm/test_apps/.build-test-rules.yml new file mode 100644 index 000000000000..a879b36b546e --- /dev/null +++ b/components/esp_mm/test_apps/.build-test-rules.yml @@ -0,0 +1,7 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +components/esp_mm/test_apps/mm: + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14470 diff --git a/components/esp_mm/test_apps/mm/pytest_mmap.py b/components/esp_mm/test_apps/mm/pytest_mmap.py index d696bee32daf..182a2807fda1 100644 --- a/components/esp_mm/test_apps/mm/pytest_mmap.py +++ b/components/esp_mm/test_apps/mm/pytest_mmap.py @@ -3,10 +3,12 @@ import pytest from pytest_embedded import Dut from pytest_embedded_idf.utils import idf_parametrize + # normal mmu tests @pytest.mark.generic +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14470') @pytest.mark.parametrize( 'config', [ @@ -29,6 +31,7 @@ def test_mmap(dut: Dut) -> None: @pytest.mark.generic +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14470') @idf_parametrize( 'config,target', [ @@ -60,6 +63,7 @@ def test_mmap_xip_psram(dut: Dut) -> None: # normal cache tests @pytest.mark.generic +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14470') @pytest.mark.parametrize( 'config', [ @@ -84,6 +88,7 @@ def test_cache(dut: Dut) -> None: ], indirect=['config', 'target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='h4 rev3 migration # TODO: IDF-14470') def test_cache_psram(dut: Dut) -> None: dut.run_all_single_board_cases(group='cache') diff --git a/components/esp_netif/test_apps/.build-test-rules.yml b/components/esp_netif/test_apps/.build-test-rules.yml index 7baad8830160..9e37eaeb543c 100644 --- a/components/esp_netif/test_apps/.build-test-rules.yml +++ b/components/esp_netif/test_apps/.build-test-rules.yml @@ -13,7 +13,7 @@ components/esp_netif/test_apps/test_app_esp_netif: components/esp_netif/test_apps/test_app_vfs_l2tap: disable: - - if: IDF_TARGET not in ["esp32", "esp32p4"] + - if: IDF_TARGET not in ["esp32"] # TODO: IDF-14365 temporary: true reason: Not needed to test on all targets (chosen two, one for each architecture plus P4 tests time stamping) depends_components: diff --git a/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md b/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md index 4873c15b15b5..f708a1985a36 100644 --- a/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md +++ b/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-P4 | -| ----------------- | ----- | -------- | +| Supported Targets | ESP32 | +| ----------------- | ----- | diff --git a/components/esp_netif/test_apps/test_app_vfs_l2tap/pytest_esp_vfs_l2tap.py b/components/esp_netif/test_apps/test_app_vfs_l2tap/pytest_esp_vfs_l2tap.py index 1a9f547da81a..fb14d5ce5905 100644 --- a/components/esp_netif/test_apps/test_app_vfs_l2tap/pytest_esp_vfs_l2tap.py +++ b/components/esp_netif/test_apps/test_app_vfs_l2tap/pytest_esp_vfs_l2tap.py @@ -19,6 +19,7 @@ def test_esp_netif_vfs_l2tp(dut: Dut) -> None: @pytest.mark.eth_ip101 +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14365') @pytest.mark.parametrize( 'config', [ diff --git a/components/esp_pm/test_apps/.build-test-rules.yml b/components/esp_pm/test_apps/.build-test-rules.yml index 22379b93284a..6a59d41af7d1 100644 --- a/components/esp_pm/test_apps/.build-test-rules.yml +++ b/components/esp_pm/test_apps/.build-test-rules.yml @@ -8,5 +8,9 @@ components/esp_pm/test_apps: - if: IDF_TARGET in ["esp32c61", "esp32h21", "esp32h4"] temporary: true reason: not support yet # TODO: [ESP32C61] IDF-9250, [ESP32H21] IDF-11522, [ESP32H4] IDF-12286 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14416 depends_components: - esp_pm diff --git a/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py b/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py index 2cd49b588483..881da90fcc2e 100644 --- a/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py +++ b/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py @@ -18,6 +18,7 @@ indirect=True, ) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c61'], reason='p4 rev3 migration # TODO: IDF-14416') def test_esp_pm(dut: Dut) -> None: dut.run_all_single_board_cases() @@ -53,5 +54,6 @@ def test_esp_attr_xip_psram_esp32s3(dut: Dut) -> None: ['pm_pd_top_sleep'], ) @idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32h2', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14416') def test_esp_pd_top_and_cpu_sleep(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h b/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h index b0faf3605221..3c5d3750b81c 100644 --- a/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h +++ b/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h @@ -58,7 +58,6 @@ extern "C" { #define RTC_SLOW_CLK_CAL_REG LP_AON_STORE1_REG #define RTC_BOOT_TIME_LOW_REG LP_AON_STORE2_REG #define RTC_BOOT_TIME_HIGH_REG LP_AON_STORE3_REG -#define RTC_CLK_SRC_REF_CNT_ARRAY_REG LP_AON_STORE4_REG #define RTC_ENTRY_LENGTH_REG LP_AON_STORE5_REG #define RTC_ENTRY_ADDR_REG LP_AON_STORE6_REG #define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG diff --git a/components/esp_rom/test_apps/.build-test-rules.yml b/components/esp_rom/test_apps/.build-test-rules.yml index 7d6745313d3c..8365d0634071 100644 --- a/components/esp_rom/test_apps/.build-test-rules.yml +++ b/components/esp_rom/test_apps/.build-test-rules.yml @@ -10,6 +10,10 @@ components/esp_rom/test_apps/rom_impl_components: - if: CONFIG_NAME == "rom_impl_components" and ((ESP_ROM_HAS_HAL_WDT != 1 and ESP_ROM_HAS_HAL_SYSTIMER != 1) and (ESP_ROM_HAS_HEAP_TLSF != 1 and ESP_ROM_HAS_SPI_FLASH != 1)) - if: CONFIG_NAME == "no_rom_impl_components" and ((ESP_ROM_HAS_HAL_WDT != 1 and ESP_ROM_HAS_HAL_SYSTIMER != 1) and (ESP_ROM_HAS_HEAP_TLSF != 1 and ESP_ROM_HAS_SPI_FLASH != 1)) - if: SOC_WDT_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14417 components/esp_rom/test_apps/rom_tests: disable_test: diff --git a/components/esp_rom/test_apps/rom_impl_components/pytest_esp_rom_impl_components.py b/components/esp_rom/test_apps/rom_impl_components/pytest_esp_rom_impl_components.py index 4efbe677c09b..be167655ba3f 100644 --- a/components/esp_rom/test_apps/rom_impl_components/pytest_esp_rom_impl_components.py +++ b/components/esp_rom/test_apps/rom_impl_components/pytest_esp_rom_impl_components.py @@ -15,5 +15,6 @@ indirect=True, ) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14417') def test_esp_rom_impl_components(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_security/test_apps/.build-test-rules.yml b/components/esp_security/test_apps/.build-test-rules.yml index 6802faf7539e..5a6cdf0da0e0 100644 --- a/components/esp_security/test_apps/.build-test-rules.yml +++ b/components/esp_security/test_apps/.build-test-rules.yml @@ -3,5 +3,9 @@ components/esp_security/test_apps/crypto_drivers: enable: - if: ((SOC_HMAC_SUPPORTED == 1) or (SOC_DIG_SIGN_SUPPORTED == 1)) or (SOC_KEY_MANAGER_SUPPORTED == 1) + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14418 depends_components: - esp_security diff --git a/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py b/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py index 8e697da9af44..59dc1fdf66d6 100644 --- a/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py +++ b/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py @@ -9,5 +9,6 @@ @idf_parametrize( 'target', ['esp32s2', 'esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32p4', 'esp32c5'], indirect=['target'] ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14418') def test_crypto_drivers(dut: Dut) -> None: dut.run_all_single_board_cases(timeout=180) diff --git a/components/esp_system/ld/esp32p4/memory.ld.in b/components/esp_system/ld/esp32p4/memory.ld.in index 107b00d98b70..4154b9369a65 100644 --- a/components/esp_system/ld/esp32p4/memory.ld.in +++ b/components/esp_system/ld/esp32p4/memory.ld.in @@ -142,15 +142,22 @@ REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg ); #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS REGION_ALIAS("text_seg_low", irom_seg); #else +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 REGION_ALIAS("text_seg_low", sram_low); - REGION_ALIAS("text_seg_high", sram_high); +#else + REGION_ALIAS("text_seg_low", sram_seg); +#endif //CONFIG_ESP32P4_SELECTS_REV_LESS_V3 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS REGION_ALIAS("rodata_seg_low", drom_seg); #else +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 REGION_ALIAS("rodata_seg_low", sram_low); REGION_ALIAS("rodata_seg_high", sram_high); +#else + REGION_ALIAS("rodata_seg_low", sram_seg); +#endif //CONFIG_ESP32P4_SELECTS_REV_LESS_V3 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS #if CONFIG_SPIRAM_XIP_FROM_PSRAM diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index ea59796c4441..cbd5dafa3c83 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -97,6 +97,7 @@ #include "hal/cache_hal.h" #include "hal/cache_ll.h" #include "hal/efuse_ll.h" +#include "soc/uart_pins.h" #include "hal/cpu_utility_ll.h" #include "soc/periph_defs.h" #include "esp_cpu.h" @@ -773,8 +774,15 @@ NOINLINE_ATTR static void system_early_init(const soc_reset_reason_t *rst_reas) // In a single thread mode, the freertos is not started yet. So don't have to use a critical section. int __DECLARE_RCC_ATOMIC_ENV __attribute__((unused)); // To avoid build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE); -#endif -#endif + int console_uart_tx_pin = U0TXD_GPIO_NUM; + int console_uart_rx_pin = U0RXD_GPIO_NUM; +#if CONFIG_ESP_CONSOLE_UART_CUSTOM + console_uart_tx_pin = (CONFIG_ESP_CONSOLE_UART_TX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_TX_GPIO : U0TXD_GPIO_NUM; + console_uart_rx_pin = (CONFIG_ESP_CONSOLE_UART_RX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_RX_GPIO : U0RXD_GPIO_NUM; +#endif + ESP_EARLY_LOGI(TAG, "GPIO %d and %d are used as console UART I/O pins", console_uart_rx_pin, console_uart_tx_pin); +#endif // CONFIG_ESP_CONSOLE_UART +#endif // !CONFIG_IDF_ENV_FPGA #if SOC_DEEP_SLEEP_SUPPORTED // Need to unhold the IOs that were hold right before entering deep sleep, which are used as wakeup pins diff --git a/components/esp_system/port/soc/esp32c5/system_internal.c b/components/esp_system/port/soc/esp32c5/system_internal.c index f9b8c95bd25c..c5608e4a376c 100644 --- a/components/esp_system/port/soc/esp32c5/system_internal.c +++ b/components/esp_system/port/soc/esp32c5/system_internal.c @@ -36,8 +36,11 @@ void esp_system_reset_modules_on_exit(void) { // Flush any data left in UART FIFOs before reset the UART peripheral - esp_rom_output_tx_wait_idle(0); - esp_rom_output_tx_wait_idle(1); + for (int i = 0; i < SOC_UART_HP_NUM; ++i) { + if (uart_ll_is_enabled(i)) { + esp_rom_output_tx_wait_idle(i); + } + } // TODO: IDF-8845 #if SOC_MODEM_CLOCK_SUPPORTED diff --git a/components/esp_system/test_apps/.build-test-rules.yml b/components/esp_system/test_apps/.build-test-rules.yml index d68503725d63..5afed0496a3d 100644 --- a/components/esp_system/test_apps/.build-test-rules.yml +++ b/components/esp_system/test_apps/.build-test-rules.yml @@ -16,6 +16,10 @@ components/esp_system/test_apps/esp_system_unity_tests: disable: - if: (CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1) - if: (CONFIG_NAME == "psram_with_pd_top" and (SOC_SPIRAM_SUPPORTED != 1 or SOC_PM_SUPPORT_TOP_PD != 1)) + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14419 components/esp_system/test_apps/linux_apis: enable: diff --git a/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py b/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py index 3d0d92f2272e..f9520f834aac 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py +++ b/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py @@ -20,6 +20,7 @@ ], indirect=['config', 'target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14419') def test_esp_system(dut: Dut) -> None: # esp32p4 32MB PSRAM initialize in startup takes more than 30 sec dut.run_all_single_board_cases(timeout=60) @@ -28,6 +29,7 @@ def test_esp_system(dut: Dut) -> None: @pytest.mark.generic @idf_parametrize('config', ['default'], indirect=['config']) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14419') def test_stack_smash_protection(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') dut.write('"stack smashing protection"') diff --git a/components/esp_timer/test_apps/.build-test-rules.yml b/components/esp_timer/test_apps/.build-test-rules.yml index b62f794ee43b..027881f6be28 100644 --- a/components/esp_timer/test_apps/.build-test-rules.yml +++ b/components/esp_timer/test_apps/.build-test-rules.yml @@ -4,3 +4,7 @@ components/esp_timer/test_apps: disable: - if: CONFIG_NAME == "dfs" and SOC_CLK_XTAL32K_SUPPORTED != 1 reason: The test requires the XTAL32K clock to measure the esp_timer timing accuracy + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14420 diff --git a/components/esp_timer/test_apps/pytest_esp_timer_ut.py b/components/esp_timer/test_apps/pytest_esp_timer_ut.py index 1c3c991fbe03..2ab8928b1989 100644 --- a/components/esp_timer/test_apps/pytest_esp_timer_ut.py +++ b/components/esp_timer/test_apps/pytest_esp_timer_ut.py @@ -22,6 +22,7 @@ ], indirect=['config', 'target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14420') def test_esp_timer(dut: Dut) -> None: dut.run_all_single_board_cases(timeout=120) @@ -36,6 +37,7 @@ def test_esp_timer(dut: Dut) -> None: indirect=True, ) @idf_parametrize('target', ['esp32'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14420') def test_esp_timer_psram(dut: Dut) -> None: dut.run_all_single_board_cases(timeout=120) diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index b21d04b63e76..962017b26aa0 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit b21d04b63e76d001ec5546fc336e7f5c091120fd +Subproject commit 962017b26aa0b9d7ee1d2457d28bdd7131e29986 diff --git a/components/freertos/test_apps/freertos/pytest_freertos.py b/components/freertos/test_apps/freertos/pytest_freertos.py index c1e8ea7bdc15..ce86a54cf8e4 100644 --- a/components/freertos/test_apps/freertos/pytest_freertos.py +++ b/components/freertos/test_apps/freertos/pytest_freertos.py @@ -33,9 +33,21 @@ @idf_parametrize( 'config,target,markers', [ - ('default', 'supported_targets'), - ('freertos_options', 'supported_targets'), - ('tickless_idle', 'supported_targets'), + ( + 'default', + 'supported_targets', + (pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421'),), + ), + ( + 'freertos_options', + 'supported_targets', + (pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421'),), + ), + ( + 'tickless_idle', + 'supported_targets', + (pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421'),), + ), ('psram', 'esp32'), ('psram', 'esp32c5'), ('psram', 'esp32p4'), @@ -74,6 +86,7 @@ def test_freertos_flash_auto_suspend(dut: Dut) -> None: @pytest.mark.generic @pytest.mark.parametrize('config', ['freertos_options'], indirect=True) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421') def test_task_notify_too_high_index_fails(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests.') dut.write('"Notify too high index fails"') @@ -85,6 +98,7 @@ def test_task_notify_too_high_index_fails(dut: Dut) -> None: @pytest.mark.generic @pytest.mark.parametrize('config', ['freertos_options'], indirect=True) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421') def test_task_notify_wait_too_high_index_fails(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests.') dut.write('"Notify Wait too high index fails"') @@ -96,6 +110,7 @@ def test_task_notify_wait_too_high_index_fails(dut: Dut) -> None: @pytest.mark.generic @pytest.mark.parametrize('config', ['default'], indirect=True) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421') def test_port_must_assert_in_isr(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests.') dut.write('"port must assert if in ISR context"') diff --git a/components/hal/color_hal.c b/components/hal/color_hal.c index c26b3db6a659..632785999487 100644 --- a/components/hal/color_hal.c +++ b/components/hal/color_hal.c @@ -28,6 +28,10 @@ uint32_t color_hal_pixel_format_get_bit_depth(color_space_pixel_format_t format) return 12; case COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565): case COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422): + case COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_UYVY422): + case COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_VYUY422): + case COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUYV422): + case COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YVYU422): return 16; case COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB666): return 18; diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/hal/esp32/include/hal/gpio_ll.h index 7ed1a2c93b64..42fb4c0550fe 100644 --- a/components/hal/esp32/include/hal/gpio_ll.h +++ b/components/hal/esp32/include/hal/gpio_ll.h @@ -688,7 +688,7 @@ static inline void gpio_ll_set_input_signal_from(gpio_dev_t *hw, uint32_t signal } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32c2/include/hal/gpio_ll.h b/components/hal/esp32c2/include/hal/gpio_ll.h index b5b915f50599..f7a27b880b85 100644 --- a/components/hal/esp32c2/include/hal/gpio_ll.h +++ b/components/hal/esp32c2/include/hal/gpio_ll.h @@ -490,7 +490,7 @@ static inline void gpio_ll_set_input_signal_from(gpio_dev_t *hw, uint32_t signal } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/hal/esp32c3/include/hal/gpio_ll.h index 834f994fb32a..21ba6d1599fb 100644 --- a/components/hal/esp32c3/include/hal/gpio_ll.h +++ b/components/hal/esp32c3/include/hal/gpio_ll.h @@ -488,7 +488,7 @@ static inline void gpio_ll_set_input_signal_from(gpio_dev_t *hw, uint32_t signal } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32c5/include/hal/gpio_ll.h b/components/hal/esp32c5/include/hal/gpio_ll.h index 5153b64a8500..fbc13550b0eb 100644 --- a/components/hal/esp32c5/include/hal/gpio_ll.h +++ b/components/hal/esp32c5/include/hal/gpio_ll.h @@ -479,7 +479,7 @@ static inline void gpio_ll_set_input_signal_from(gpio_dev_t *hw, uint32_t signal } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32c6/include/hal/gpio_ll.h b/components/hal/esp32c6/include/hal/gpio_ll.h index 54d39baa3b59..084ac9274682 100644 --- a/components/hal/esp32c6/include/hal/gpio_ll.h +++ b/components/hal/esp32c6/include/hal/gpio_ll.h @@ -449,7 +449,7 @@ static inline void gpio_ll_set_input_signal_from(gpio_dev_t *hw, uint32_t signal } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32c61/include/hal/gpio_ll.h b/components/hal/esp32c61/include/hal/gpio_ll.h index 61ca1be3a4b9..1360533a5d56 100644 --- a/components/hal/esp32c61/include/hal/gpio_ll.h +++ b/components/hal/esp32c61/include/hal/gpio_ll.h @@ -479,7 +479,7 @@ static inline void gpio_ll_set_input_signal_from(gpio_dev_t *hw, uint32_t signal } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32h2/include/hal/gpio_ll.h b/components/hal/esp32h2/include/hal/gpio_ll.h index ed12ec6299b4..ce89097939c5 100644 --- a/components/hal/esp32h2/include/hal/gpio_ll.h +++ b/components/hal/esp32h2/include/hal/gpio_ll.h @@ -495,7 +495,7 @@ static inline void gpio_ll_set_input_signal_from(gpio_dev_t *hw, uint32_t signal } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32h21/include/hal/gpio_ll.h b/components/hal/esp32h21/include/hal/gpio_ll.h index e988be80992e..25549bc420ee 100644 --- a/components/hal/esp32h21/include/hal/gpio_ll.h +++ b/components/hal/esp32h21/include/hal/gpio_ll.h @@ -479,7 +479,7 @@ static inline void gpio_ll_set_input_signal_from(gpio_dev_t *hw, uint32_t signal } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32h4/include/hal/gpio_ll.h b/components/hal/esp32h4/include/hal/gpio_ll.h index 6add0f6d4bfa..39d3517537f4 100644 --- a/components/hal/esp32h4/include/hal/gpio_ll.h +++ b/components/hal/esp32h4/include/hal/gpio_ll.h @@ -491,7 +491,7 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f } /** - * @brief Set peripheral output to an GPIO pad through the IOMUX. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32p4/include/hal/gpio_ll.h b/components/hal/esp32p4/include/hal/gpio_ll.h index 1ef00742681a..ed77bf14e5bb 100644 --- a/components/hal/esp32p4/include/hal/gpio_ll.h +++ b/components/hal/esp32p4/include/hal/gpio_ll.h @@ -607,7 +607,7 @@ static inline void gpio_ll_set_input_signal_from(gpio_dev_t *hw, uint32_t signal } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32p4/include/hal/ppa_ll.h b/components/hal/esp32p4/include/hal/ppa_ll.h index d20cf73ad428..a0e7323397fc 100644 --- a/components/hal/esp32p4/include/hal/ppa_ll.h +++ b/components/hal/esp32p4/include/hal/ppa_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -199,6 +199,38 @@ static inline void ppa_ll_srm_start(ppa_dev_t *dev) dev->sr_scal_rotate.scal_rotate_start = 1; } +/** + * @brief Set PPA SRM input side YUV422 data format packing order + * + * @param dev Peripheral instance address + * @param color_mode One of the values in ppa_srm_color_mode_t + */ +static inline void ppa_ll_srm_set_rx_yuv422_pack_order(ppa_dev_t *dev, ppa_srm_color_mode_t color_mode) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (color_mode) { + case PPA_SRM_COLOR_MODE_YUV422_YVYU: + dev->sr_color_mode.yuv422_rx_byte_order = 3; + break; + case PPA_SRM_COLOR_MODE_YUV422_YUYV: + dev->sr_color_mode.yuv422_rx_byte_order = 2; + break; + case PPA_SRM_COLOR_MODE_YUV422_VYUY: + dev->sr_color_mode.yuv422_rx_byte_order = 1; + break; + case PPA_SRM_COLOR_MODE_YUV422_UYVY: + dev->sr_color_mode.yuv422_rx_byte_order = 0; + break; + default: + // Unsupported YUV422 pack order + abort(); + } +#else + // YUV422 not supported by PPA SRM hardware before P4 ECO5 + abort(); +#endif +} + /** * @brief Check if the given color mode is supported by PPA SRM engine * @@ -214,7 +246,10 @@ static inline bool ppa_ll_srm_is_color_mode_supported(ppa_srm_color_mode_t color case PPA_SRM_COLOR_MODE_YUV420: case PPA_SRM_COLOR_MODE_YUV444: // YUV444 not supported by PPA hardware, but can be converted by 2D-DMA before/after PPA #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 - case PPA_SRM_COLOR_MODE_YUV422: + case PPA_SRM_COLOR_MODE_YUV422_UYVY: + case PPA_SRM_COLOR_MODE_YUV422_VYUY: + case PPA_SRM_COLOR_MODE_YUV422_YUYV: + case PPA_SRM_COLOR_MODE_YUV422_YVYU: case PPA_SRM_COLOR_MODE_GRAY8: #endif return true; @@ -232,6 +267,7 @@ static inline bool ppa_ll_srm_is_color_mode_supported(ppa_srm_color_mode_t color static inline void ppa_ll_srm_set_rx_color_mode(ppa_dev_t *dev, ppa_srm_color_mode_t color_mode) { uint32_t val = 0; + bool is_yuv422 __attribute__ ((unused)) = false; switch (color_mode) { case PPA_SRM_COLOR_MODE_ARGB8888: val = 0; @@ -246,8 +282,12 @@ static inline void ppa_ll_srm_set_rx_color_mode(ppa_dev_t *dev, ppa_srm_color_mo val = 8; break; #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 - case PPA_SRM_COLOR_MODE_YUV422: + case PPA_SRM_COLOR_MODE_YUV422_UYVY: + case PPA_SRM_COLOR_MODE_YUV422_VYUY: + case PPA_SRM_COLOR_MODE_YUV422_YUYV: + case PPA_SRM_COLOR_MODE_YUV422_YVYU: val = 9; + is_yuv422 = true; break; case PPA_SRM_COLOR_MODE_GRAY8: val = 12; @@ -258,6 +298,13 @@ static inline void ppa_ll_srm_set_rx_color_mode(ppa_dev_t *dev, ppa_srm_color_mo abort(); } dev->sr_color_mode.sr_rx_cm = val; + +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + // set YUV422 packing order + if (is_yuv422) { + ppa_ll_srm_set_rx_yuv422_pack_order(dev, color_mode); + } +#endif } /** @@ -283,7 +330,7 @@ static inline void ppa_ll_srm_set_tx_color_mode(ppa_dev_t *dev, ppa_srm_color_mo val = 8; break; #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 - case PPA_SRM_COLOR_MODE_YUV422: + case PPA_SRM_COLOR_MODE_YUV422_UYVY: val = 9; break; case PPA_SRM_COLOR_MODE_GRAY8: @@ -381,38 +428,6 @@ static inline void ppa_ll_srm_set_tx_yuv_range(ppa_dev_t *dev, ppa_color_range_t } } -/** - * @brief Set PPA SRM input side YUV422 data format packing order - * - * @param dev Peripheral instance address - * @param pack_order One of the pack order options in color_yuv422_pack_order_t - */ -static inline void ppa_ll_srm_set_rx_yuv422_pack_order(ppa_dev_t *dev, color_yuv422_pack_order_t pack_order) -{ -#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 - switch (pack_order) { - case COLOR_YUV422_PACK_ORDER_YVYU: - dev->sr_color_mode.yuv422_rx_byte_order = 0; - break; - case COLOR_YUV422_PACK_ORDER_YUYV: - dev->sr_color_mode.yuv422_rx_byte_order = 1; - break; - case COLOR_YUV422_PACK_ORDER_VYUY: - dev->sr_color_mode.yuv422_rx_byte_order = 2; - break; - case COLOR_YUV422_PACK_ORDER_UYVY: - dev->sr_color_mode.yuv422_rx_byte_order = 3; - break; - default: - // Unsupported YUV422 pack order - abort(); - } -#else - // YUV422 not supported by PPA SRM hardware before P4 ECO5 - abort(); -#endif -} - /** * @brief Enable PPA SRM input data swap in RGB (e.g. ARGB becomes BGRA, RGB becomes BGR) * @@ -537,7 +552,10 @@ static inline void ppa_ll_srm_get_dma_dscr_port_mode_block_size(ppa_dev_t *dev, *block_h = 20; *block_v = 18; break; - case PPA_SRM_COLOR_MODE_YUV422: + case PPA_SRM_COLOR_MODE_YUV422_UYVY: + case PPA_SRM_COLOR_MODE_YUV422_VYUY: + case PPA_SRM_COLOR_MODE_YUV422_YUYV: + case PPA_SRM_COLOR_MODE_YUV422_YVYU: *block_h = 20; *block_v = 20; break; @@ -561,7 +579,10 @@ static inline void ppa_ll_srm_get_dma_dscr_port_mode_block_size(ppa_dev_t *dev, *block_h = 36; *block_v = 34; break; - case PPA_SRM_COLOR_MODE_YUV422: + case PPA_SRM_COLOR_MODE_YUV422_UYVY: + case PPA_SRM_COLOR_MODE_YUV422_VYUY: + case PPA_SRM_COLOR_MODE_YUV422_YUYV: + case PPA_SRM_COLOR_MODE_YUV422_YVYU: *block_h = 36; *block_v = 36; break; @@ -628,6 +649,38 @@ static inline void ppa_ll_blend_start(ppa_dev_t *dev, ppa_ll_blend_trans_mode_t dev->blend_trans_mode.blend_trans_mode_update = 1; } +/** + * @brief Set PPA blending source image background YUV422 data format packing order + * + * @param dev Peripheral instance address + * @param color_mode One of the values in ppa_blend_color_mode_t + */ +static inline void ppa_ll_blend_set_rx_bg_yuv422_pack_order(ppa_dev_t *dev, ppa_blend_color_mode_t color_mode) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (color_mode) { + case PPA_BLEND_COLOR_MODE_YUV422_YVYU: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 3; + break; + case PPA_BLEND_COLOR_MODE_YUV422_YUYV: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 2; + break; + case PPA_BLEND_COLOR_MODE_YUV422_VYUY: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 1; + break; + case PPA_BLEND_COLOR_MODE_YUV422_UYVY: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 0; + break; + default: + // Unsupported YUV422 pack order + abort(); + } +#else + // YUV422 not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + /** * @brief Check if the given color mode is supported by PPA blending engine * @@ -646,7 +699,10 @@ static inline bool ppa_ll_blend_is_color_mode_supported(ppa_blend_color_mode_t c // case PPA_BLEND_COLOR_MODE_L4: #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 case PPA_BLEND_COLOR_MODE_YUV420: - case PPA_BLEND_COLOR_MODE_YUV422: + case PPA_BLEND_COLOR_MODE_YUV422_UYVY: + case PPA_BLEND_COLOR_MODE_YUV422_VYUY: + case PPA_BLEND_COLOR_MODE_YUV422_YUYV: + case PPA_BLEND_COLOR_MODE_YUV422_YVYU: case PPA_BLEND_COLOR_MODE_GRAY8: #endif return true; @@ -664,6 +720,7 @@ static inline bool ppa_ll_blend_is_color_mode_supported(ppa_blend_color_mode_t c static inline void ppa_ll_blend_set_rx_bg_color_mode(ppa_dev_t *dev, ppa_blend_color_mode_t color_mode) { uint32_t val = 0; + bool is_yuv422 __attribute__ ((unused)) = false; switch (color_mode) { case PPA_BLEND_COLOR_MODE_ARGB8888: val = 0; @@ -684,8 +741,12 @@ static inline void ppa_ll_blend_set_rx_bg_color_mode(ppa_dev_t *dev, ppa_blend_c case PPA_BLEND_COLOR_MODE_YUV420: val = 8; break; - case PPA_BLEND_COLOR_MODE_YUV422: + case PPA_BLEND_COLOR_MODE_YUV422_UYVY: + case PPA_BLEND_COLOR_MODE_YUV422_VYUY: + case PPA_BLEND_COLOR_MODE_YUV422_YUYV: + case PPA_BLEND_COLOR_MODE_YUV422_YVYU: val = 9; + is_yuv422 = true; break; case PPA_BLEND_COLOR_MODE_GRAY8: val = 12; @@ -696,6 +757,13 @@ static inline void ppa_ll_blend_set_rx_bg_color_mode(ppa_dev_t *dev, ppa_blend_c abort(); } dev->blend_color_mode.blend0_rx_cm = val; + +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + // set YUV422 packing order + if (is_yuv422) { + ppa_ll_blend_set_rx_bg_yuv422_pack_order(dev, color_mode); + } +#endif } /** @@ -759,7 +827,7 @@ static inline void ppa_ll_blend_set_tx_color_mode(ppa_dev_t *dev, ppa_blend_colo case PPA_BLEND_COLOR_MODE_YUV420: val = 8; break; - case PPA_BLEND_COLOR_MODE_YUV422: + case PPA_BLEND_COLOR_MODE_YUV422_UYVY: val = 9; break; case PPA_BLEND_COLOR_MODE_GRAY8: @@ -877,38 +945,6 @@ static inline void ppa_ll_blend_set_tx_yuv_range(ppa_dev_t *dev, ppa_color_range #endif } -/** - * @brief Set PPA blending source image background YUV422 data format packing order - * - * @param dev Peripheral instance address - * @param pack_order One of the pack order options in color_yuv422_pack_order_t - */ -static inline void ppa_ll_blend_set_rx_bg_yuv422_pack_order(ppa_dev_t *dev, color_yuv422_pack_order_t pack_order) -{ -#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 - switch (pack_order) { - case COLOR_YUV422_PACK_ORDER_YVYU: - dev->blend_color_mode.blend0_rx_yuv422_byte_order = 0; - break; - case COLOR_YUV422_PACK_ORDER_YUYV: - dev->blend_color_mode.blend0_rx_yuv422_byte_order = 1; - break; - case COLOR_YUV422_PACK_ORDER_VYUY: - dev->blend_color_mode.blend0_rx_yuv422_byte_order = 2; - break; - case COLOR_YUV422_PACK_ORDER_UYVY: - dev->blend_color_mode.blend0_rx_yuv422_byte_order = 3; - break; - default: - // Unsupported YUV422 pack order - abort(); - } -#else - // YUV422 not supported by PPA blending hardware before P4 ECO5 - abort(); -#endif -} - /** * @brief Enable PPA blending input background data wrap in RGB (e.g. ARGB becomes BGRA, RGB becomes BGR) * @@ -1052,7 +1088,7 @@ static inline void ppa_ll_blend_configure_filling_block(ppa_dev_t *dev, ppa_fill case PPA_FILL_COLOR_MODE_GRAY8: fill_color_data = *(uint32_t *)data; break; - case PPA_FILL_COLOR_MODE_YUV422: { + case PPA_FILL_COLOR_MODE_YUV422_UYVY: { color_macroblock_yuv_data_t *yuv_data = (color_macroblock_yuv_data_t *)data; fill_color_data = ((yuv_data->y) << 24) | ((yuv_data->v) << 16) | ((yuv_data->y) << 8) | (yuv_data->u); break; diff --git a/components/hal/esp32p4/include/hal/usb_dwc_ll.h b/components/hal/esp32p4/include/hal/usb_dwc_ll.h index 1ee7334a749a..c1b1a44e080a 100644 --- a/components/hal/esp32p4/include/hal/usb_dwc_ll.h +++ b/components/hal/esp32p4/include/hal/usb_dwc_ll.h @@ -1061,6 +1061,21 @@ FORCE_INLINE_ATTR bool usb_dwc_ll_get_stoppclk_st(usb_dwc_dev_t *hw) return hw->pcgcctl_reg.stoppclk; } +FORCE_INLINE_ATTR void usb_dwc_ll_set_gatehclk(usb_dwc_dev_t *hw, bool gate) +{ + hw->pcgcctl_reg.gatehclk = gate; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_gatehclk_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.gatehclk; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_physleep_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.physleep; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/gpio_ll.h b/components/hal/esp32s2/include/hal/gpio_ll.h index 872fc55c8256..98a7e0ce2f1e 100644 --- a/components/hal/esp32s2/include/hal/gpio_ll.h +++ b/components/hal/esp32s2/include/hal/gpio_ll.h @@ -502,7 +502,7 @@ static inline void gpio_ll_set_input_signal_from(gpio_dev_t *hw, uint32_t signal } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32s2/include/hal/usb_dwc_ll.h b/components/hal/esp32s2/include/hal/usb_dwc_ll.h index d3eef71367be..90ad414aeb2a 100644 --- a/components/hal/esp32s2/include/hal/usb_dwc_ll.h +++ b/components/hal/esp32s2/include/hal/usb_dwc_ll.h @@ -8,6 +8,7 @@ #include #include +#include "esp_attr.h" #include "soc/usb_dwc_struct.h" #include "soc/usb_dwc_cfg.h" #include "hal/usb_dwc_types.h" @@ -976,6 +977,32 @@ static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem qtd->buffer_status_val = 0; } +// ---------------------------- Power and Clock Gating Register -------------------------------- +FORCE_INLINE_ATTR void usb_dwc_ll_set_stoppclk(usb_dwc_dev_t *hw, bool stop) +{ + hw->pcgcctl_reg.stoppclk = stop; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_stoppclk_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.stoppclk; +} + +FORCE_INLINE_ATTR void usb_dwc_ll_set_gatehclk(usb_dwc_dev_t *hw, bool gate) +{ + hw->pcgcctl_reg.gatehclk = gate; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_gatehclk_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.gatehclk; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_physleep_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.physleep; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/gpio_ll.h b/components/hal/esp32s3/include/hal/gpio_ll.h index ddebea0479aa..ddb42de7f7b6 100644 --- a/components/hal/esp32s3/include/hal/gpio_ll.h +++ b/components/hal/esp32s3/include/hal/gpio_ll.h @@ -503,7 +503,7 @@ static inline void gpio_ll_set_input_signal_from(gpio_dev_t *hw, uint32_t signal } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32s3/include/hal/usb_dwc_ll.h b/components/hal/esp32s3/include/hal/usb_dwc_ll.h index 32f7469a3e35..aaab0c9417ee 100644 --- a/components/hal/esp32s3/include/hal/usb_dwc_ll.h +++ b/components/hal/esp32s3/include/hal/usb_dwc_ll.h @@ -8,6 +8,7 @@ #include #include +#include "esp_attr.h" #include "soc/usb_dwc_struct.h" #include "soc/usb_dwc_cfg.h" #include "hal/usb_dwc_types.h" @@ -976,6 +977,32 @@ static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem qtd->buffer_status_val = 0; } +// ---------------------------- Power and Clock Gating Register -------------------------------- +FORCE_INLINE_ATTR void usb_dwc_ll_set_stoppclk(usb_dwc_dev_t *hw, bool stop) +{ + hw->pcgcctl_reg.stoppclk = stop; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_stoppclk_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.stoppclk; +} + +FORCE_INLINE_ATTR void usb_dwc_ll_set_gatehclk(usb_dwc_dev_t *hw, bool gate) +{ + hw->pcgcctl_reg.gatehclk = gate; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_gatehclk_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.gatehclk; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_physleep_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.physleep; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/gpio_hal.c b/components/hal/gpio_hal.c index 7bba273a2edc..f59598a92227 100644 --- a/components/hal/gpio_hal.c +++ b/components/hal/gpio_hal.c @@ -40,8 +40,8 @@ void gpio_hal_iomux_in(gpio_hal_context_t *hal, uint32_t gpio_num, int func, uin void gpio_hal_iomux_out(gpio_hal_context_t *hal, uint32_t gpio_num, int func) { - gpio_ll_set_output_enable_ctrl(hal->dev, gpio_num, true, false); gpio_ll_func_sel(hal->dev, gpio_num, func); + // as long as the func sel is not GPIO, the oe can only be controlled by the peripheral } #if SOC_GPIO_SUPPORT_PIN_HYS_FILTER diff --git a/components/hal/include/hal/color_types.h b/components/hal/include/hal/color_types.h index b222db3abf28..cb8cef6786b5 100644 --- a/components/hal/include/hal/color_types.h +++ b/components/hal/include/hal/color_types.h @@ -59,6 +59,11 @@ typedef enum { COLOR_PIXEL_YUV422, ///< 16 bits, 8-bit Y per pixel, 8-bit U and V per two pixels COLOR_PIXEL_YUV420, ///< 12 bits, 8-bit Y per pixel, 8-bit U and V per four pixels COLOR_PIXEL_YUV411, ///< 12 bits, 8-bit Y per pixel, 8-bit U and V per four pixels + + COLOR_PIXEL_UYVY422, ///< 16 bits, 8-bit Y per pixel, 8-bit U and V per two pixels w/ (lowest byte) U0-Y0-V0-Y1 (highest byte) pack order + COLOR_PIXEL_VYUY422, ///< 16 bits, 8-bit Y per pixel, 8-bit U and V per two pixels w/ (lowest byte) V0-Y0-U0-Y1 (highest byte) pack order + COLOR_PIXEL_YUYV422, ///< 16 bits, 8-bit Y per pixel, 8-bit U and V per two pixels w/ (lowest byte) Y0-U0-Y1-V0 (highest byte) pack order + COLOR_PIXEL_YVYU422, ///< 16 bits, 8-bit Y per pixel, 8-bit U and V per two pixels w/ (lowest byte) Y0-V0-Y1-U0 (highest byte) pack order } color_pixel_yuv_format_t; /** diff --git a/components/hal/include/hal/gpio_hal.h b/components/hal/include/hal/gpio_hal.h index ebc0090d946f..f57ee4c4c995 100644 --- a/components/hal/include/hal/gpio_hal.h +++ b/components/hal/include/hal/gpio_hal.h @@ -161,7 +161,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num); #define gpio_hal_output_enable(hal, gpio_num) gpio_ll_output_enable((hal)->dev, gpio_num) /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hal Context of the HAL layer * @param gpio_num GPIO number diff --git a/components/hal/include/hal/ppa_types.h b/components/hal/include/hal/ppa_types.h index dd967e42180a..6f9932225506 100644 --- a/components/hal/include/hal/ppa_types.h +++ b/components/hal/include/hal/ppa_types.h @@ -44,7 +44,10 @@ typedef enum { // YUV444 not supported by PPA hardware, but we can use 2D-DMA to do conversion before sending into and after coming out from the PPA module // If in_pic is YUV444, then TX DMA channel could do DMA2D_CSC_TX_YUV444_TO_RGB888_601/709, so PPA in_color_mode is RGB888 // If out_pic is YUV444, then RX DMA channel could do DMA2D_CSC_RX_YUV420_TO_YUV444, so PPA out_color_mode is YUV420 - PPA_SRM_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA SRM color mode: YUV422 (input data pack order all supported, but output data format is fixed to YVYU) */ + PPA_SRM_COLOR_MODE_YUV422_UYVY = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_UYVY422), /*!< PPA SRM color mode: YUV422 */ + PPA_SRM_COLOR_MODE_YUV422_VYUY = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_VYUY422), /*!< PPA SRM color mode: YUV422, only available on input */ + PPA_SRM_COLOR_MODE_YUV422_YUYV = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUYV422), /*!< PPA SRM color mode: YUV422, only available on input */ + PPA_SRM_COLOR_MODE_YUV422_YVYU = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YVYU422), /*!< PPA SRM color mode: YUV422, only available on input */ PPA_SRM_COLOR_MODE_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< PPA SRM color mode: GRAY8 */ } ppa_srm_color_mode_t; @@ -58,7 +61,10 @@ typedef enum { PPA_BLEND_COLOR_MODE_A8 = COLOR_TYPE_ID(COLOR_SPACE_ALPHA, COLOR_PIXEL_A8), /*!< PPA blend color mode: A8, only available on blend foreground input */ PPA_BLEND_COLOR_MODE_A4 = COLOR_TYPE_ID(COLOR_SPACE_ALPHA, COLOR_PIXEL_A4), /*!< PPA blend color mode: A4, only available on blend foreground input */ PPA_BLEND_COLOR_MODE_YUV420 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV420), /*!< PPA blend color mode: YUV420, only available on blend background input or on output */ - PPA_BLEND_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA blend color mode: YUV422, only available on blend background input (all pack order supported) or on output (fixed to YVYU) */ + PPA_BLEND_COLOR_MODE_YUV422_UYVY = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_UYVY422), /*!< PPA blend color mode: YUV422, only available on blend background input or on output */ + PPA_BLEND_COLOR_MODE_YUV422_VYUY = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_VYUY422), /*!< PPA blend color mode: YUV422, only available on blend background input */ + PPA_BLEND_COLOR_MODE_YUV422_YUYV = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUYV422), /*!< PPA blend color mode: YUV422, only available on blend background input */ + PPA_BLEND_COLOR_MODE_YUV422_YVYU = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YVYU422), /*!< PPA blend color mode: YUV422, only available on blend background input */ PPA_BLEND_COLOR_MODE_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< PPA blend color mode: GRAY8, only available on blend background input or on output */ // TODO: Support CLUT to support L4/L8 color mode // PPA_BLEND_COLOR_MODE_L8 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L8), /*!< PPA blend color mode: L8, only available on blend input */ @@ -73,7 +79,7 @@ typedef enum { PPA_FILL_COLOR_MODE_RGB888 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB888), /*!< PPA fill color mode: RGB888 */ PPA_FILL_COLOR_MODE_RGB565 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565), /*!< PPA fill color mode: RGB565 */ // PPA_FILL_COLOR_MODE_YUV420 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV420), /*!< PPA fill color mode: YUV420 */ // Non-typical YUV420, U and V components have to be the same value - PPA_FILL_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA fill color mode: YUV422 (w/ YVYU pack order) */ + PPA_FILL_COLOR_MODE_YUV422_UYVY = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_UYVY422), /*!< PPA fill color mode: YUV422 (w/ UYVY pack order) */ PPA_FILL_COLOR_MODE_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< PPA fill color mode: GRAY8 */ } ppa_fill_color_mode_t; diff --git a/components/hal/include/hal/usb_dwc_hal.h b/components/hal/include/hal/usb_dwc_hal.h index d6eab592221b..6178c1d4b885 100644 --- a/components/hal/include/hal/usb_dwc_hal.h +++ b/components/hal/include/hal/usb_dwc_hal.h @@ -553,6 +553,66 @@ static inline bool usb_dwc_hal_port_check_if_suspended(usb_dwc_hal_context_t *ha return usb_dwc_ll_hprt_get_port_suspend(hal->dev); } +// ----------------------------------------------------- Power and Clock gating ---------------------------------------- + +/** + * @brief Gate internal clock of the DWC_OTG core + * + * This function gates the internal clock of the DWC_OTG core to reduce power consumption + * + * Internal clock gating: + * - stop PHY clock (PCLK) + * - gate HCLK to modules other than the AHB slave, AHB master and wakeup logic + * Internal clock un-gating: + * - un-stop PHY clock (PCLK) + * - un-gate HCLK + * + * @note This is a part of a sequence from the DWC Programming guide, chapter 14.2.2.1 + * @param hal Context of the HAL layer + * @param enable Enable or disable internal clock gating + */ +static inline void usb_dwc_hal_pwr_clk_internal_clock_gate(usb_dwc_hal_context_t *hal, bool enable) +{ + usb_dwc_ll_set_stoppclk(hal->dev, enable); // Enable/disable PHY clock stop + usb_dwc_ll_set_gatehclk(hal->dev, enable); // Gate/ungate HCLK +} + +/** + * @brief Check if the PHY clock (PCLK) stop is enabled or disabled + * + * @param hal Context of the HAL layer + * @return true The PCLK stop is enabled + * @return false The PCLK stop is not enabled + */ +static inline bool usb_dwc_hal_pwr_clk_check_phy_clk_stopped(usb_dwc_hal_context_t *hal) +{ + return usb_dwc_ll_get_stoppclk_st(hal->dev); +} + +/** + * @brief Check if the HCLK is gated or ungated + * + * @param hal Context of the HAL layer + * @return true The HCLK is gated + * @return false The HCLK is not gated + */ +static inline bool usb_dwc_hal_pwr_clk_check_hclk_gated(usb_dwc_hal_context_t *hal) +{ + return usb_dwc_ll_get_gatehclk_st(hal->dev); +} + +/** + * @brief Check if PHY is in sleep state + * + * @param hal Context of the HAL layer + * @return true The USB PHY is in sleep state + * @return false The USB PHY is not in sleep state + */ +static inline bool usb_dwc_hal_pwr_clk_check_phy_sleep(usb_dwc_hal_context_t *hal) +{ + return usb_dwc_ll_get_physleep_st(hal->dev); +} + // ----------------------------------------------------- Channel ------------------------------------------------------- // ----------------- Channel Allocation -------------------- diff --git a/components/mbedtls/test_apps/.build-test-rules.yml b/components/mbedtls/test_apps/.build-test-rules.yml index 0e72c8d3dc48..52531a92dcc7 100644 --- a/components/mbedtls/test_apps/.build-test-rules.yml +++ b/components/mbedtls/test_apps/.build-test-rules.yml @@ -5,6 +5,9 @@ components/mbedtls/test_apps: - if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1 - if: CONFIG_NAME == "psram_all_ext" and SOC_SPIRAM_SUPPORTED != 1 - if: CONFIG_NAME == "ecdsa_sign" and SOC_ECDSA_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14367 depends_components: - efuse - mbedtls diff --git a/components/mbedtls/test_apps/README.md b/components/mbedtls/test_apps/README.md index 44f3780f1d6a..7f28f609e612 100644 --- a/components/mbedtls/test_apps/README.md +++ b/components/mbedtls/test_apps/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | diff --git a/components/mbedtls/test_apps/pytest_mbedtls_ut.py b/components/mbedtls/test_apps/pytest_mbedtls_ut.py index 00d9582bf042..743f5c8c6e6b 100644 --- a/components/mbedtls/test_apps/pytest_mbedtls_ut.py +++ b/components/mbedtls/test_apps/pytest_mbedtls_ut.py @@ -7,6 +7,7 @@ @pytest.mark.generic @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14367') def test_mbedtls(dut: Dut) -> None: dut.run_all_single_board_cases() @@ -58,6 +59,7 @@ def test_mbedtls_psram(dut: Dut) -> None: indirect=True, ) @idf_parametrize('target', ['esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14367') def test_mbedtls_psram_esp32p4(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/newlib/test_apps/.build-test-rules.yml b/components/newlib/test_apps/.build-test-rules.yml index 8383b02ebced..7e5c31fd38eb 100644 --- a/components/newlib/test_apps/.build-test-rules.yml +++ b/components/newlib/test_apps/.build-test-rules.yml @@ -1,3 +1,7 @@ # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps components/newlib/test_apps/newlib: + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14415 diff --git a/components/newlib/test_apps/newlib/pytest_newlib.py b/components/newlib/test_apps/newlib/pytest_newlib.py index 96d5e4ac1ce2..de750e938bb5 100644 --- a/components/newlib/test_apps/newlib/pytest_newlib.py +++ b/components/newlib/test_apps/newlib/pytest_newlib.py @@ -20,5 +20,6 @@ ], indirect=['config', 'target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14415') def test_newlib(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/protocomm/src/transports/protocomm_nimble.c b/components/protocomm/src/transports/protocomm_nimble.c index 51f5c6332735..fea2516a5aca 100644 --- a/components/protocomm/src/transports/protocomm_nimble.c +++ b/components/protocomm/src/transports/protocomm_nimble.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -547,6 +547,7 @@ static int simple_ble_start(const simple_ble_cfg_t *cfg) ble_hs_cfg.sm_our_key_dist = BLE_SM_PAIR_KEY_DIST_ENC | BLE_SM_PAIR_KEY_DIST_ID; ble_hs_cfg.sm_their_key_dist = BLE_SM_PAIR_KEY_DIST_ENC | BLE_SM_PAIR_KEY_DIST_ID; +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(cfg); if (rc != 0) { ESP_LOGE(TAG, "Error initializing GATT server"); @@ -565,6 +566,7 @@ static int simple_ble_start(const simple_ble_cfg_t *cfg) resp_data.name_len = strlen(ble_svc_gap_device_name()); resp_data.name_is_complete = 1; } +#endif /* Set manufacturer data if protocomm_ble_mfg_data points to valid data */ if (protocomm_ble_mfg_data != NULL) { diff --git a/components/pthread/test_apps/pthread_unity_tests/pytest_pthread_unity_tests.py b/components/pthread/test_apps/pthread_unity_tests/pytest_pthread_unity_tests.py index 5e6aba09c9f5..2cf9732abdb0 100644 --- a/components/pthread/test_apps/pthread_unity_tests/pytest_pthread_unity_tests.py +++ b/components/pthread/test_apps/pthread_unity_tests/pytest_pthread_unity_tests.py @@ -14,6 +14,7 @@ indirect=True, ) @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421') def test_pthread(dut: Dut) -> None: dut.run_all_single_board_cases(group='!thread-specific', timeout=300) diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_reg.h index e7b75d50a4b5..6545f51a1fa8 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_reg.h @@ -11,1183 +11,1183 @@ extern "C" { #endif -/** I2C_SCL_LOW_PERIOD_REG register +/** LP_I2C_SCL_LOW_PERIOD_REG register * Configures the low level width of the SCL * Clock */ -#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0) -/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SCL_LOW_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x0) +/** LP_I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; * This register is used to configure for how long SCL remains low in master mode, in * I2C module clock cycles. */ -#define I2C_SCL_LOW_PERIOD 0x000001FFU -#define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) -#define I2C_SCL_LOW_PERIOD_V 0x000001FFU -#define I2C_SCL_LOW_PERIOD_S 0 +#define LP_I2C_SCL_LOW_PERIOD 0x000001FFU +#define LP_I2C_SCL_LOW_PERIOD_M (LP_I2C_SCL_LOW_PERIOD_V << LP_I2C_SCL_LOW_PERIOD_S) +#define LP_I2C_SCL_LOW_PERIOD_V 0x000001FFU +#define LP_I2C_SCL_LOW_PERIOD_S 0 -/** I2C_CTR_REG register +/** LP_I2C_CTR_REG register * Transmission setting */ -#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4) -/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; +#define LP_I2C_CTR_REG (DR_REG_LP_I2C_BASE + 0x4) +/** LP_I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; * This register is used to select the sample mode.1: sample SDA data on the SCL low * level.0: sample SDA data on the SCL high level. */ -#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) -#define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) -#define I2C_SAMPLE_SCL_LEVEL_V 0x00000001U -#define I2C_SAMPLE_SCL_LEVEL_S 2 -/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; +#define LP_I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define LP_I2C_SAMPLE_SCL_LEVEL_M (LP_I2C_SAMPLE_SCL_LEVEL_V << LP_I2C_SAMPLE_SCL_LEVEL_S) +#define LP_I2C_SAMPLE_SCL_LEVEL_V 0x00000001U +#define LP_I2C_SAMPLE_SCL_LEVEL_S 2 +/** LP_I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; * This register is used to configure the ACK value that need to sent by master when * the rx_fifo_cnt has reached the threshold. */ -#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) -#define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) -#define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U -#define I2C_RX_FULL_ACK_LEVEL_S 3 -/** I2C_TRANS_START : WT; bitpos: [5]; default: 0; +#define LP_I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define LP_I2C_RX_FULL_ACK_LEVEL_M (LP_I2C_RX_FULL_ACK_LEVEL_V << LP_I2C_RX_FULL_ACK_LEVEL_S) +#define LP_I2C_RX_FULL_ACK_LEVEL_V 0x00000001U +#define LP_I2C_RX_FULL_ACK_LEVEL_S 3 +/** LP_I2C_TRANS_START : WT; bitpos: [5]; default: 0; * Set this bit to start sending the data in txfifo. */ -#define I2C_TRANS_START (BIT(5)) -#define I2C_TRANS_START_M (I2C_TRANS_START_V << I2C_TRANS_START_S) -#define I2C_TRANS_START_V 0x00000001U -#define I2C_TRANS_START_S 5 -/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; +#define LP_I2C_TRANS_START (BIT(5)) +#define LP_I2C_TRANS_START_M (LP_I2C_TRANS_START_V << LP_I2C_TRANS_START_S) +#define LP_I2C_TRANS_START_V 0x00000001U +#define LP_I2C_TRANS_START_S 5 +/** LP_I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; * This bit is used to control the sending mode for data needing to be sent. 1: send * data from the least significant bit,0: send data from the most significant bit. */ -#define I2C_TX_LSB_FIRST (BIT(6)) -#define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) -#define I2C_TX_LSB_FIRST_V 0x00000001U -#define I2C_TX_LSB_FIRST_S 6 -/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; +#define LP_I2C_TX_LSB_FIRST (BIT(6)) +#define LP_I2C_TX_LSB_FIRST_M (LP_I2C_TX_LSB_FIRST_V << LP_I2C_TX_LSB_FIRST_S) +#define LP_I2C_TX_LSB_FIRST_V 0x00000001U +#define LP_I2C_TX_LSB_FIRST_S 6 +/** LP_I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; * This bit is used to control the storage mode for received data.1: receive data from * the least significant bit,0: receive data from the most significant bit. */ -#define I2C_RX_LSB_FIRST (BIT(7)) -#define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) -#define I2C_RX_LSB_FIRST_V 0x00000001U -#define I2C_RX_LSB_FIRST_S 7 -/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; +#define LP_I2C_RX_LSB_FIRST (BIT(7)) +#define LP_I2C_RX_LSB_FIRST_M (LP_I2C_RX_LSB_FIRST_V << LP_I2C_RX_LSB_FIRST_S) +#define LP_I2C_RX_LSB_FIRST_V 0x00000001U +#define LP_I2C_RX_LSB_FIRST_S 7 +/** LP_I2C_CLK_EN : R/W; bitpos: [8]; default: 0; * Reserved */ -#define I2C_CLK_EN (BIT(8)) -#define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) -#define I2C_CLK_EN_V 0x00000001U -#define I2C_CLK_EN_S 8 -/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; +#define LP_I2C_CLK_EN (BIT(8)) +#define LP_I2C_CLK_EN_M (LP_I2C_CLK_EN_V << LP_I2C_CLK_EN_S) +#define LP_I2C_CLK_EN_V 0x00000001U +#define LP_I2C_CLK_EN_S 8 +/** LP_I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; * This is the enable bit for arbitration_lost. */ -#define I2C_ARBITRATION_EN (BIT(9)) -#define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) -#define I2C_ARBITRATION_EN_V 0x00000001U -#define I2C_ARBITRATION_EN_S 9 -/** I2C_FSM_RST : WT; bitpos: [10]; default: 0; +#define LP_I2C_ARBITRATION_EN (BIT(9)) +#define LP_I2C_ARBITRATION_EN_M (LP_I2C_ARBITRATION_EN_V << LP_I2C_ARBITRATION_EN_S) +#define LP_I2C_ARBITRATION_EN_V 0x00000001U +#define LP_I2C_ARBITRATION_EN_S 9 +/** LP_I2C_FSM_RST : WT; bitpos: [10]; default: 0; * This register is used to reset the scl FMS. */ -#define I2C_FSM_RST (BIT(10)) -#define I2C_FSM_RST_M (I2C_FSM_RST_V << I2C_FSM_RST_S) -#define I2C_FSM_RST_V 0x00000001U -#define I2C_FSM_RST_S 10 -/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; +#define LP_I2C_FSM_RST (BIT(10)) +#define LP_I2C_FSM_RST_M (LP_I2C_FSM_RST_V << LP_I2C_FSM_RST_S) +#define LP_I2C_FSM_RST_V 0x00000001U +#define LP_I2C_FSM_RST_S 10 +/** LP_I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; * synchronization bit */ -#define I2C_CONF_UPGATE (BIT(11)) -#define I2C_CONF_UPGATE_M (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S) -#define I2C_CONF_UPGATE_V 0x00000001U -#define I2C_CONF_UPGATE_S 11 +#define LP_I2C_CONF_UPGATE (BIT(11)) +#define LP_I2C_CONF_UPGATE_M (LP_I2C_CONF_UPGATE_V << LP_I2C_CONF_UPGATE_S) +#define LP_I2C_CONF_UPGATE_V 0x00000001U +#define LP_I2C_CONF_UPGATE_S 11 -/** I2C_SR_REG register +/** LP_I2C_SR_REG register * Describe I2C work status. */ -#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8) -/** I2C_RESP_REC : RO; bitpos: [0]; default: 0; +#define LP_I2C_SR_REG (DR_REG_LP_I2C_BASE + 0x8) +/** LP_I2C_RESP_REC : RO; bitpos: [0]; default: 0; * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. */ -#define I2C_RESP_REC (BIT(0)) -#define I2C_RESP_REC_M (I2C_RESP_REC_V << I2C_RESP_REC_S) -#define I2C_RESP_REC_V 0x00000001U -#define I2C_RESP_REC_S 0 -/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; +#define LP_I2C_RESP_REC (BIT(0)) +#define LP_I2C_RESP_REC_M (LP_I2C_RESP_REC_V << LP_I2C_RESP_REC_S) +#define LP_I2C_RESP_REC_V 0x00000001U +#define LP_I2C_RESP_REC_S 0 +/** LP_I2C_ARB_LOST : RO; bitpos: [3]; default: 0; * When the I2C controller loses control of SCL line, this register changes to 1. */ -#define I2C_ARB_LOST (BIT(3)) -#define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) -#define I2C_ARB_LOST_V 0x00000001U -#define I2C_ARB_LOST_S 3 -/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; +#define LP_I2C_ARB_LOST (BIT(3)) +#define LP_I2C_ARB_LOST_M (LP_I2C_ARB_LOST_V << LP_I2C_ARB_LOST_S) +#define LP_I2C_ARB_LOST_V 0x00000001U +#define LP_I2C_ARB_LOST_S 3 +/** LP_I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. */ -#define I2C_BUS_BUSY (BIT(4)) -#define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) -#define I2C_BUS_BUSY_V 0x00000001U -#define I2C_BUS_BUSY_S 4 -/** I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0; +#define LP_I2C_BUS_BUSY (BIT(4)) +#define LP_I2C_BUS_BUSY_M (LP_I2C_BUS_BUSY_V << LP_I2C_BUS_BUSY_S) +#define LP_I2C_BUS_BUSY_V 0x00000001U +#define LP_I2C_BUS_BUSY_S 4 +/** LP_I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0; * This field represents the amount of data needed to be sent. */ -#define I2C_RXFIFO_CNT 0x0000001FU -#define I2C_RXFIFO_CNT_M (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S) -#define I2C_RXFIFO_CNT_V 0x0000001FU -#define I2C_RXFIFO_CNT_S 8 -/** I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0; +#define LP_I2C_RXFIFO_CNT 0x0000001FU +#define LP_I2C_RXFIFO_CNT_M (LP_I2C_RXFIFO_CNT_V << LP_I2C_RXFIFO_CNT_S) +#define LP_I2C_RXFIFO_CNT_V 0x0000001FU +#define LP_I2C_RXFIFO_CNT_S 8 +/** LP_I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0; * This field stores the amount of received data in RAM. */ -#define I2C_TXFIFO_CNT 0x0000001FU -#define I2C_TXFIFO_CNT_M (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S) -#define I2C_TXFIFO_CNT_V 0x0000001FU -#define I2C_TXFIFO_CNT_S 18 -/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; +#define LP_I2C_TXFIFO_CNT 0x0000001FU +#define LP_I2C_TXFIFO_CNT_M (LP_I2C_TXFIFO_CNT_V << LP_I2C_TXFIFO_CNT_S) +#define LP_I2C_TXFIFO_CNT_V 0x0000001FU +#define LP_I2C_TXFIFO_CNT_S 18 +/** LP_I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; * This field indicates the states of the I2C module state machine. 0: Idle, 1: * Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK */ -#define I2C_SCL_MAIN_STATE_LAST 0x00000007U -#define I2C_SCL_MAIN_STATE_LAST_M (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S) -#define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U -#define I2C_SCL_MAIN_STATE_LAST_S 24 -/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; +#define LP_I2C_SCL_MAIN_STATE_LAST 0x00000007U +#define LP_I2C_SCL_MAIN_STATE_LAST_M (LP_I2C_SCL_MAIN_STATE_LAST_V << LP_I2C_SCL_MAIN_STATE_LAST_S) +#define LP_I2C_SCL_MAIN_STATE_LAST_V 0x00000007U +#define LP_I2C_SCL_MAIN_STATE_LAST_S 24 +/** LP_I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; * This field indicates the states of the state machine used to produce SCL.0: Idle, * 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop */ -#define I2C_SCL_STATE_LAST 0x00000007U -#define I2C_SCL_STATE_LAST_M (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S) -#define I2C_SCL_STATE_LAST_V 0x00000007U -#define I2C_SCL_STATE_LAST_S 28 +#define LP_I2C_SCL_STATE_LAST 0x00000007U +#define LP_I2C_SCL_STATE_LAST_M (LP_I2C_SCL_STATE_LAST_V << LP_I2C_SCL_STATE_LAST_S) +#define LP_I2C_SCL_STATE_LAST_V 0x00000007U +#define LP_I2C_SCL_STATE_LAST_S 28 -/** I2C_TO_REG register +/** LP_I2C_TO_REG register * Setting time out control for receiving data. */ -#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc) -/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; +#define LP_I2C_TO_REG (DR_REG_LP_I2C_BASE + 0xc) +/** LP_I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; * This register is used to configure the timeout for receiving a data bit in APBclock * cycles. */ -#define I2C_TIME_OUT_VALUE 0x0000001FU -#define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) -#define I2C_TIME_OUT_VALUE_V 0x0000001FU -#define I2C_TIME_OUT_VALUE_S 0 -/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; +#define LP_I2C_TIME_OUT_VALUE 0x0000001FU +#define LP_I2C_TIME_OUT_VALUE_M (LP_I2C_TIME_OUT_VALUE_V << LP_I2C_TIME_OUT_VALUE_S) +#define LP_I2C_TIME_OUT_VALUE_V 0x0000001FU +#define LP_I2C_TIME_OUT_VALUE_S 0 +/** LP_I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; * This is the enable bit for time out control. */ -#define I2C_TIME_OUT_EN (BIT(5)) -#define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) -#define I2C_TIME_OUT_EN_V 0x00000001U -#define I2C_TIME_OUT_EN_S 5 +#define LP_I2C_TIME_OUT_EN (BIT(5)) +#define LP_I2C_TIME_OUT_EN_M (LP_I2C_TIME_OUT_EN_V << LP_I2C_TIME_OUT_EN_S) +#define LP_I2C_TIME_OUT_EN_V 0x00000001U +#define LP_I2C_TIME_OUT_EN_S 5 -/** I2C_FIFO_ST_REG register +/** LP_I2C_FIFO_ST_REG register * FIFO status register. */ -#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14) -/** I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0; +#define LP_I2C_FIFO_ST_REG (DR_REG_LP_I2C_BASE + 0x14) +/** LP_I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0; * This is the offset address of the APB reading from rxfifo */ -#define I2C_RXFIFO_RADDR 0x0000000FU -#define I2C_RXFIFO_RADDR_M (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S) -#define I2C_RXFIFO_RADDR_V 0x0000000FU -#define I2C_RXFIFO_RADDR_S 0 -/** I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0; +#define LP_I2C_RXFIFO_RADDR 0x0000000FU +#define LP_I2C_RXFIFO_RADDR_M (LP_I2C_RXFIFO_RADDR_V << LP_I2C_RXFIFO_RADDR_S) +#define LP_I2C_RXFIFO_RADDR_V 0x0000000FU +#define LP_I2C_RXFIFO_RADDR_S 0 +/** LP_I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0; * This is the offset address of i2c module receiving data and writing to rxfifo. */ -#define I2C_RXFIFO_WADDR 0x0000000FU -#define I2C_RXFIFO_WADDR_M (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S) -#define I2C_RXFIFO_WADDR_V 0x0000000FU -#define I2C_RXFIFO_WADDR_S 5 -/** I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0; +#define LP_I2C_RXFIFO_WADDR 0x0000000FU +#define LP_I2C_RXFIFO_WADDR_M (LP_I2C_RXFIFO_WADDR_V << LP_I2C_RXFIFO_WADDR_S) +#define LP_I2C_RXFIFO_WADDR_V 0x0000000FU +#define LP_I2C_RXFIFO_WADDR_S 5 +/** LP_I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0; * This is the offset address of i2c module reading from txfifo. */ -#define I2C_TXFIFO_RADDR 0x0000000FU -#define I2C_TXFIFO_RADDR_M (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S) -#define I2C_TXFIFO_RADDR_V 0x0000000FU -#define I2C_TXFIFO_RADDR_S 10 -/** I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0; +#define LP_I2C_TXFIFO_RADDR 0x0000000FU +#define LP_I2C_TXFIFO_RADDR_M (LP_I2C_TXFIFO_RADDR_V << LP_I2C_TXFIFO_RADDR_S) +#define LP_I2C_TXFIFO_RADDR_V 0x0000000FU +#define LP_I2C_TXFIFO_RADDR_S 10 +/** LP_I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0; * This is the offset address of APB bus writing to txfifo. */ -#define I2C_TXFIFO_WADDR 0x0000000FU -#define I2C_TXFIFO_WADDR_M (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S) -#define I2C_TXFIFO_WADDR_V 0x0000000FU -#define I2C_TXFIFO_WADDR_S 15 +#define LP_I2C_TXFIFO_WADDR 0x0000000FU +#define LP_I2C_TXFIFO_WADDR_M (LP_I2C_TXFIFO_WADDR_V << LP_I2C_TXFIFO_WADDR_S) +#define LP_I2C_TXFIFO_WADDR_V 0x0000000FU +#define LP_I2C_TXFIFO_WADDR_S 15 -/** I2C_FIFO_CONF_REG register +/** LP_I2C_FIFO_CONF_REG register * FIFO configuration register. */ -#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18) -/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6; +#define LP_I2C_FIFO_CONF_REG (DR_REG_LP_I2C_BASE + 0x18) +/** LP_I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6; * The water mark threshold of rx FIFO in nonfifo access mode. When * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than * reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. */ -#define I2C_RXFIFO_WM_THRHD 0x0000000FU -#define I2C_RXFIFO_WM_THRHD_M (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S) -#define I2C_RXFIFO_WM_THRHD_V 0x0000000FU -#define I2C_RXFIFO_WM_THRHD_S 0 -/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2; +#define LP_I2C_RXFIFO_WM_THRHD 0x0000000FU +#define LP_I2C_RXFIFO_WM_THRHD_M (LP_I2C_RXFIFO_WM_THRHD_V << LP_I2C_RXFIFO_WM_THRHD_S) +#define LP_I2C_RXFIFO_WM_THRHD_V 0x0000000FU +#define LP_I2C_RXFIFO_WM_THRHD_S 0 +/** LP_I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2; * The water mark threshold of tx FIFO in nonfifo access mode. When * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than * reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. */ -#define I2C_TXFIFO_WM_THRHD 0x0000000FU -#define I2C_TXFIFO_WM_THRHD_M (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S) -#define I2C_TXFIFO_WM_THRHD_V 0x0000000FU -#define I2C_TXFIFO_WM_THRHD_S 5 -/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; +#define LP_I2C_TXFIFO_WM_THRHD 0x0000000FU +#define LP_I2C_TXFIFO_WM_THRHD_M (LP_I2C_TXFIFO_WM_THRHD_V << LP_I2C_TXFIFO_WM_THRHD_S) +#define LP_I2C_TXFIFO_WM_THRHD_V 0x0000000FU +#define LP_I2C_TXFIFO_WM_THRHD_S 5 +/** LP_I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; * Set this bit to enable APB nonfifo access. */ -#define I2C_NONFIFO_EN (BIT(10)) -#define I2C_NONFIFO_EN_M (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S) -#define I2C_NONFIFO_EN_V 0x00000001U -#define I2C_NONFIFO_EN_S 10 -/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; +#define LP_I2C_NONFIFO_EN (BIT(10)) +#define LP_I2C_NONFIFO_EN_M (LP_I2C_NONFIFO_EN_V << LP_I2C_NONFIFO_EN_S) +#define LP_I2C_NONFIFO_EN_V 0x00000001U +#define LP_I2C_NONFIFO_EN_S 10 +/** LP_I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; * Set this bit to reset rx-fifo. */ -#define I2C_RX_FIFO_RST (BIT(12)) -#define I2C_RX_FIFO_RST_M (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S) -#define I2C_RX_FIFO_RST_V 0x00000001U -#define I2C_RX_FIFO_RST_S 12 -/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; +#define LP_I2C_RX_FIFO_RST (BIT(12)) +#define LP_I2C_RX_FIFO_RST_M (LP_I2C_RX_FIFO_RST_V << LP_I2C_RX_FIFO_RST_S) +#define LP_I2C_RX_FIFO_RST_V 0x00000001U +#define LP_I2C_RX_FIFO_RST_S 12 +/** LP_I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; * Set this bit to reset tx-fifo. */ -#define I2C_TX_FIFO_RST (BIT(13)) -#define I2C_TX_FIFO_RST_M (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S) -#define I2C_TX_FIFO_RST_V 0x00000001U -#define I2C_TX_FIFO_RST_S 13 -/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; +#define LP_I2C_TX_FIFO_RST (BIT(13)) +#define LP_I2C_TX_FIFO_RST_M (LP_I2C_TX_FIFO_RST_V << LP_I2C_TX_FIFO_RST_S) +#define LP_I2C_TX_FIFO_RST_V 0x00000001U +#define LP_I2C_TX_FIFO_RST_S 13 +/** LP_I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. */ -#define I2C_FIFO_PRT_EN (BIT(14)) -#define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) -#define I2C_FIFO_PRT_EN_V 0x00000001U -#define I2C_FIFO_PRT_EN_S 14 +#define LP_I2C_FIFO_PRT_EN (BIT(14)) +#define LP_I2C_FIFO_PRT_EN_M (LP_I2C_FIFO_PRT_EN_V << LP_I2C_FIFO_PRT_EN_S) +#define LP_I2C_FIFO_PRT_EN_V 0x00000001U +#define LP_I2C_FIFO_PRT_EN_S 14 -/** I2C_DATA_REG register +/** LP_I2C_DATA_REG register * Rx FIFO read data. */ -#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c) -/** I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; +#define LP_I2C_DATA_REG (DR_REG_LP_I2C_BASE + 0x1c) +/** LP_I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; * The value of rx FIFO read data. */ -#define I2C_FIFO_RDATA 0x000000FFU -#define I2C_FIFO_RDATA_M (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S) -#define I2C_FIFO_RDATA_V 0x000000FFU -#define I2C_FIFO_RDATA_S 0 +#define LP_I2C_FIFO_RDATA 0x000000FFU +#define LP_I2C_FIFO_RDATA_M (LP_I2C_FIFO_RDATA_V << LP_I2C_FIFO_RDATA_S) +#define LP_I2C_FIFO_RDATA_V 0x000000FFU +#define LP_I2C_FIFO_RDATA_S 0 -/** I2C_INT_RAW_REG register +/** LP_I2C_INT_RAW_REG register * Raw interrupt status */ -#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20) -/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. - */ -#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) -#define I2C_RXFIFO_WM_INT_RAW_M (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S) -#define I2C_RXFIFO_WM_INT_RAW_V 0x00000001U -#define I2C_RXFIFO_WM_INT_RAW_S 0 -/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; - * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. - */ -#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) -#define I2C_TXFIFO_WM_INT_RAW_M (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S) -#define I2C_TXFIFO_WM_INT_RAW_V 0x00000001U -#define I2C_TXFIFO_WM_INT_RAW_S 1 -/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. - */ -#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) -#define I2C_RXFIFO_OVF_INT_RAW_M (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S) -#define I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_RAW_S 2 -/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; - * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. - */ -#define I2C_END_DETECT_INT_RAW (BIT(3)) -#define I2C_END_DETECT_INT_RAW_M (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S) -#define I2C_END_DETECT_INT_RAW_V 0x00000001U -#define I2C_END_DETECT_INT_RAW_S 3 -/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; - * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. - */ -#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_RAW_M (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S) -#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 -/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; - * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. - */ -#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_RAW_M (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S) -#define I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_RAW_S 5 -/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; - * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_RAW_M (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S) -#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 -/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; - * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_RAW_M (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S) -#define I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_RAW_S 7 -/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; - * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. - */ -#define I2C_TIME_OUT_INT_RAW (BIT(8)) -#define I2C_TIME_OUT_INT_RAW_M (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S) -#define I2C_TIME_OUT_INT_RAW_V 0x00000001U -#define I2C_TIME_OUT_INT_RAW_S 8 -/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; - * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. - */ -#define I2C_TRANS_START_INT_RAW (BIT(9)) -#define I2C_TRANS_START_INT_RAW_M (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S) -#define I2C_TRANS_START_INT_RAW_V 0x00000001U -#define I2C_TRANS_START_INT_RAW_S 9 -/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; - * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_NACK_INT_RAW (BIT(10)) -#define I2C_NACK_INT_RAW_M (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S) -#define I2C_NACK_INT_RAW_V 0x00000001U -#define I2C_NACK_INT_RAW_S 10 -/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; - * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. - */ -#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) -#define I2C_TXFIFO_OVF_INT_RAW_M (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S) -#define I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_RAW_S 11 -/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. - */ -#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) -#define I2C_RXFIFO_UDF_INT_RAW_M (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S) -#define I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_RAW_S 12 -/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; - * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. - */ -#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) -#define I2C_SCL_ST_TO_INT_RAW_M (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S) -#define I2C_SCL_ST_TO_INT_RAW_V 0x00000001U -#define I2C_SCL_ST_TO_INT_RAW_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; - * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. - */ -#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 -/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; - * The raw interrupt bit for I2C_DET_START_INT interrupt. - */ -#define I2C_DET_START_INT_RAW (BIT(15)) -#define I2C_DET_START_INT_RAW_M (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S) -#define I2C_DET_START_INT_RAW_V 0x00000001U -#define I2C_DET_START_INT_RAW_S 15 +#define LP_I2C_INT_RAW_REG (DR_REG_LP_I2C_BASE + 0x20) +/** LP_I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt bit for LP_I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_RAW_M (LP_I2C_RXFIFO_WM_INT_RAW_V << LP_I2C_RXFIFO_WM_INT_RAW_S) +#define LP_I2C_RXFIFO_WM_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_RAW_S 0 +/** LP_I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt bit for LP_I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_RAW_M (LP_I2C_TXFIFO_WM_INT_RAW_V << LP_I2C_TXFIFO_WM_INT_RAW_S) +#define LP_I2C_TXFIFO_WM_INT_RAW_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_RAW_S 1 +/** LP_I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt bit for LP_I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_RAW_M (LP_I2C_RXFIFO_OVF_INT_RAW_V << LP_I2C_RXFIFO_OVF_INT_RAW_S) +#define LP_I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_RAW_S 2 +/** LP_I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_RAW (BIT(3)) +#define LP_I2C_END_DETECT_INT_RAW_M (LP_I2C_END_DETECT_INT_RAW_V << LP_I2C_END_DETECT_INT_RAW_S) +#define LP_I2C_END_DETECT_INT_RAW_V 0x00000001U +#define LP_I2C_END_DETECT_INT_RAW_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_M (LP_I2C_BYTE_TRANS_DONE_INT_RAW_V << LP_I2C_BYTE_TRANS_DONE_INT_RAW_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_RAW_M (LP_I2C_ARBITRATION_LOST_INT_RAW_V << LP_I2C_ARBITRATION_LOST_INT_RAW_S) +#define LP_I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_RAW_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt bit for LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_M (LP_I2C_MST_TXFIFO_UDF_INT_RAW_V << LP_I2C_MST_TXFIFO_UDF_INT_RAW_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_RAW_M (LP_I2C_TRANS_COMPLETE_INT_RAW_V << LP_I2C_TRANS_COMPLETE_INT_RAW_S) +#define LP_I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_RAW_S 7 +/** LP_I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt bit for the LP_I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_RAW (BIT(8)) +#define LP_I2C_TIME_OUT_INT_RAW_M (LP_I2C_TIME_OUT_INT_RAW_V << LP_I2C_TIME_OUT_INT_RAW_S) +#define LP_I2C_TIME_OUT_INT_RAW_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_RAW_S 8 +/** LP_I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt bit for the LP_I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_RAW (BIT(9)) +#define LP_I2C_TRANS_START_INT_RAW_M (LP_I2C_TRANS_START_INT_RAW_V << LP_I2C_TRANS_START_INT_RAW_S) +#define LP_I2C_TRANS_START_INT_RAW_V 0x00000001U +#define LP_I2C_TRANS_START_INT_RAW_S 9 +/** LP_I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt bit for LP_I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_RAW (BIT(10)) +#define LP_I2C_NACK_INT_RAW_M (LP_I2C_NACK_INT_RAW_V << LP_I2C_NACK_INT_RAW_S) +#define LP_I2C_NACK_INT_RAW_V 0x00000001U +#define LP_I2C_NACK_INT_RAW_S 10 +/** LP_I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt bit for LP_I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_RAW_M (LP_I2C_TXFIFO_OVF_INT_RAW_V << LP_I2C_TXFIFO_OVF_INT_RAW_S) +#define LP_I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_RAW_S 11 +/** LP_I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt bit for LP_I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_RAW_M (LP_I2C_RXFIFO_UDF_INT_RAW_V << LP_I2C_RXFIFO_UDF_INT_RAW_S) +#define LP_I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_RAW_S 12 +/** LP_I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt bit for LP_I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_RAW_M (LP_I2C_SCL_ST_TO_INT_RAW_V << LP_I2C_SCL_ST_TO_INT_RAW_S) +#define LP_I2C_SCL_ST_TO_INT_RAW_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_RAW_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_M (LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V << LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/** LP_I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt bit for LP_I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_RAW (BIT(15)) +#define LP_I2C_DET_START_INT_RAW_M (LP_I2C_DET_START_INT_RAW_V << LP_I2C_DET_START_INT_RAW_S) +#define LP_I2C_DET_START_INT_RAW_V 0x00000001U +#define LP_I2C_DET_START_INT_RAW_S 15 -/** I2C_INT_CLR_REG register +/** LP_I2C_INT_CLR_REG register * Interrupt clear bits */ -#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24) -/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. - */ -#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) -#define I2C_RXFIFO_WM_INT_CLR_M (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S) -#define I2C_RXFIFO_WM_INT_CLR_V 0x00000001U -#define I2C_RXFIFO_WM_INT_CLR_S 0 -/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. - */ -#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) -#define I2C_TXFIFO_WM_INT_CLR_M (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S) -#define I2C_TXFIFO_WM_INT_CLR_V 0x00000001U -#define I2C_TXFIFO_WM_INT_CLR_S 1 -/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. - */ -#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) -#define I2C_RXFIFO_OVF_INT_CLR_M (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S) -#define I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_CLR_S 2 -/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the I2C_END_DETECT_INT interrupt. - */ -#define I2C_END_DETECT_INT_CLR (BIT(3)) -#define I2C_END_DETECT_INT_CLR_M (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S) -#define I2C_END_DETECT_INT_CLR_V 0x00000001U -#define I2C_END_DETECT_INT_CLR_S 3 -/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the I2C_END_DETECT_INT interrupt. - */ -#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_CLR_M (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S) -#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 -/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. - */ -#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_CLR_M (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S) -#define I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_CLR_S 5 -/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_CLR_M (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S) -#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 -/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_CLR_M (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S) -#define I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_CLR_S 7 -/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the I2C_TIME_OUT_INT interrupt. - */ -#define I2C_TIME_OUT_INT_CLR (BIT(8)) -#define I2C_TIME_OUT_INT_CLR_M (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S) -#define I2C_TIME_OUT_INT_CLR_V 0x00000001U -#define I2C_TIME_OUT_INT_CLR_S 8 -/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the I2C_TRANS_START_INT interrupt. - */ -#define I2C_TRANS_START_INT_CLR (BIT(9)) -#define I2C_TRANS_START_INT_CLR_M (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S) -#define I2C_TRANS_START_INT_CLR_V 0x00000001U -#define I2C_TRANS_START_INT_CLR_S 9 -/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_NACK_INT_CLR (BIT(10)) -#define I2C_NACK_INT_CLR_M (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S) -#define I2C_NACK_INT_CLR_V 0x00000001U -#define I2C_NACK_INT_CLR_S 10 -/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. - */ -#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) -#define I2C_TXFIFO_OVF_INT_CLR_M (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S) -#define I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_CLR_S 11 -/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. - */ -#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) -#define I2C_RXFIFO_UDF_INT_CLR_M (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S) -#define I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_CLR_S 12 -/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. - */ -#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) -#define I2C_SCL_ST_TO_INT_CLR_M (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S) -#define I2C_SCL_ST_TO_INT_CLR_V 0x00000001U -#define I2C_SCL_ST_TO_INT_CLR_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; - * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. - */ -#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 -/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; - * Set this bit to clear I2C_DET_START_INT interrupt. - */ -#define I2C_DET_START_INT_CLR (BIT(15)) -#define I2C_DET_START_INT_CLR_M (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S) -#define I2C_DET_START_INT_CLR_V 0x00000001U -#define I2C_DET_START_INT_CLR_S 15 +#define LP_I2C_INT_CLR_REG (DR_REG_LP_I2C_BASE + 0x24) +/** LP_I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear LP_I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_CLR_M (LP_I2C_RXFIFO_WM_INT_CLR_V << LP_I2C_RXFIFO_WM_INT_CLR_S) +#define LP_I2C_RXFIFO_WM_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_CLR_S 0 +/** LP_I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear LP_I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_CLR_M (LP_I2C_TXFIFO_WM_INT_CLR_V << LP_I2C_TXFIFO_WM_INT_CLR_S) +#define LP_I2C_TXFIFO_WM_INT_CLR_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_CLR_S 1 +/** LP_I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear LP_I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_CLR_M (LP_I2C_RXFIFO_OVF_INT_CLR_V << LP_I2C_RXFIFO_OVF_INT_CLR_S) +#define LP_I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_CLR_S 2 +/** LP_I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_CLR (BIT(3)) +#define LP_I2C_END_DETECT_INT_CLR_M (LP_I2C_END_DETECT_INT_CLR_V << LP_I2C_END_DETECT_INT_CLR_S) +#define LP_I2C_END_DETECT_INT_CLR_V 0x00000001U +#define LP_I2C_END_DETECT_INT_CLR_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_M (LP_I2C_BYTE_TRANS_DONE_INT_CLR_V << LP_I2C_BYTE_TRANS_DONE_INT_CLR_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the LP_I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_CLR_M (LP_I2C_ARBITRATION_LOST_INT_CLR_V << LP_I2C_ARBITRATION_LOST_INT_CLR_S) +#define LP_I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_CLR_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_M (LP_I2C_MST_TXFIFO_UDF_INT_CLR_V << LP_I2C_MST_TXFIFO_UDF_INT_CLR_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_CLR_M (LP_I2C_TRANS_COMPLETE_INT_CLR_V << LP_I2C_TRANS_COMPLETE_INT_CLR_S) +#define LP_I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_CLR_S 7 +/** LP_I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the LP_I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_CLR (BIT(8)) +#define LP_I2C_TIME_OUT_INT_CLR_M (LP_I2C_TIME_OUT_INT_CLR_V << LP_I2C_TIME_OUT_INT_CLR_S) +#define LP_I2C_TIME_OUT_INT_CLR_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_CLR_S 8 +/** LP_I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the LP_I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_CLR (BIT(9)) +#define LP_I2C_TRANS_START_INT_CLR_M (LP_I2C_TRANS_START_INT_CLR_V << LP_I2C_TRANS_START_INT_CLR_S) +#define LP_I2C_TRANS_START_INT_CLR_V 0x00000001U +#define LP_I2C_TRANS_START_INT_CLR_S 9 +/** LP_I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear LP_I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_CLR (BIT(10)) +#define LP_I2C_NACK_INT_CLR_M (LP_I2C_NACK_INT_CLR_V << LP_I2C_NACK_INT_CLR_S) +#define LP_I2C_NACK_INT_CLR_V 0x00000001U +#define LP_I2C_NACK_INT_CLR_S 10 +/** LP_I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear LP_I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_CLR_M (LP_I2C_TXFIFO_OVF_INT_CLR_V << LP_I2C_TXFIFO_OVF_INT_CLR_S) +#define LP_I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_CLR_S 11 +/** LP_I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear LP_I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_CLR_M (LP_I2C_RXFIFO_UDF_INT_CLR_V << LP_I2C_RXFIFO_UDF_INT_CLR_S) +#define LP_I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_CLR_S 12 +/** LP_I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear LP_I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_CLR_M (LP_I2C_SCL_ST_TO_INT_CLR_V << LP_I2C_SCL_ST_TO_INT_CLR_S) +#define LP_I2C_SCL_ST_TO_INT_CLR_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_CLR_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear LP_I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_M (LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V << LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/** LP_I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear LP_I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_CLR (BIT(15)) +#define LP_I2C_DET_START_INT_CLR_M (LP_I2C_DET_START_INT_CLR_V << LP_I2C_DET_START_INT_CLR_S) +#define LP_I2C_DET_START_INT_CLR_V 0x00000001U +#define LP_I2C_DET_START_INT_CLR_S 15 -/** I2C_INT_ENA_REG register +/** LP_I2C_INT_ENA_REG register * Interrupt enable bits */ -#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28) -/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. - */ -#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) -#define I2C_RXFIFO_WM_INT_ENA_M (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S) -#define I2C_RXFIFO_WM_INT_ENA_V 0x00000001U -#define I2C_RXFIFO_WM_INT_ENA_S 0 -/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. - */ -#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) -#define I2C_TXFIFO_WM_INT_ENA_M (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S) -#define I2C_TXFIFO_WM_INT_ENA_V 0x00000001U -#define I2C_TXFIFO_WM_INT_ENA_S 1 -/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. - */ -#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ENA_M (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S) -#define I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_ENA_S 2 -/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. - */ -#define I2C_END_DETECT_INT_ENA (BIT(3)) -#define I2C_END_DETECT_INT_ENA_M (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S) -#define I2C_END_DETECT_INT_ENA_V 0x00000001U -#define I2C_END_DETECT_INT_ENA_S 3 -/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. - */ -#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ENA_M (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S) -#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 -/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. - */ -#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ENA_M (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S) -#define I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_ENA_S 5 -/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ENA_M (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S) -#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 -/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ENA_M (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S) -#define I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_ENA_S 7 -/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. - */ -#define I2C_TIME_OUT_INT_ENA (BIT(8)) -#define I2C_TIME_OUT_INT_ENA_M (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S) -#define I2C_TIME_OUT_INT_ENA_V 0x00000001U -#define I2C_TIME_OUT_INT_ENA_S 8 -/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. - */ -#define I2C_TRANS_START_INT_ENA (BIT(9)) -#define I2C_TRANS_START_INT_ENA_M (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S) -#define I2C_TRANS_START_INT_ENA_V 0x00000001U -#define I2C_TRANS_START_INT_ENA_S 9 -/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_NACK_INT_ENA (BIT(10)) -#define I2C_NACK_INT_ENA_M (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S) -#define I2C_NACK_INT_ENA_V 0x00000001U -#define I2C_NACK_INT_ENA_S 10 -/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. - */ -#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ENA_M (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S) -#define I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_ENA_S 11 -/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. - */ -#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ENA_M (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S) -#define I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_ENA_S 12 -/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. - */ -#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) -#define I2C_SCL_ST_TO_INT_ENA_M (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S) -#define I2C_SCL_ST_TO_INT_ENA_V 0x00000001U -#define I2C_SCL_ST_TO_INT_ENA_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; - * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. - */ -#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 -/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; - * The interrupt enable bit for I2C_DET_START_INT interrupt. - */ -#define I2C_DET_START_INT_ENA (BIT(15)) -#define I2C_DET_START_INT_ENA_M (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S) -#define I2C_DET_START_INT_ENA_V 0x00000001U -#define I2C_DET_START_INT_ENA_S 15 +#define LP_I2C_INT_ENA_REG (DR_REG_LP_I2C_BASE + 0x28) +/** LP_I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for LP_I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_ENA_M (LP_I2C_RXFIFO_WM_INT_ENA_V << LP_I2C_RXFIFO_WM_INT_ENA_S) +#define LP_I2C_RXFIFO_WM_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_ENA_S 0 +/** LP_I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for LP_I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_ENA_M (LP_I2C_TXFIFO_WM_INT_ENA_V << LP_I2C_TXFIFO_WM_INT_ENA_S) +#define LP_I2C_TXFIFO_WM_INT_ENA_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_ENA_S 1 +/** LP_I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for LP_I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_ENA_M (LP_I2C_RXFIFO_OVF_INT_ENA_V << LP_I2C_RXFIFO_OVF_INT_ENA_S) +#define LP_I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_ENA_S 2 +/** LP_I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_ENA (BIT(3)) +#define LP_I2C_END_DETECT_INT_ENA_M (LP_I2C_END_DETECT_INT_ENA_V << LP_I2C_END_DETECT_INT_ENA_S) +#define LP_I2C_END_DETECT_INT_ENA_V 0x00000001U +#define LP_I2C_END_DETECT_INT_ENA_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_M (LP_I2C_BYTE_TRANS_DONE_INT_ENA_V << LP_I2C_BYTE_TRANS_DONE_INT_ENA_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_ENA_M (LP_I2C_ARBITRATION_LOST_INT_ENA_V << LP_I2C_ARBITRATION_LOST_INT_ENA_S) +#define LP_I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_ENA_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_M (LP_I2C_MST_TXFIFO_UDF_INT_ENA_V << LP_I2C_MST_TXFIFO_UDF_INT_ENA_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_ENA_M (LP_I2C_TRANS_COMPLETE_INT_ENA_V << LP_I2C_TRANS_COMPLETE_INT_ENA_S) +#define LP_I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_ENA_S 7 +/** LP_I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the LP_I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_ENA (BIT(8)) +#define LP_I2C_TIME_OUT_INT_ENA_M (LP_I2C_TIME_OUT_INT_ENA_V << LP_I2C_TIME_OUT_INT_ENA_S) +#define LP_I2C_TIME_OUT_INT_ENA_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_ENA_S 8 +/** LP_I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the LP_I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_ENA (BIT(9)) +#define LP_I2C_TRANS_START_INT_ENA_M (LP_I2C_TRANS_START_INT_ENA_V << LP_I2C_TRANS_START_INT_ENA_S) +#define LP_I2C_TRANS_START_INT_ENA_V 0x00000001U +#define LP_I2C_TRANS_START_INT_ENA_S 9 +/** LP_I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for LP_I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_ENA (BIT(10)) +#define LP_I2C_NACK_INT_ENA_M (LP_I2C_NACK_INT_ENA_V << LP_I2C_NACK_INT_ENA_S) +#define LP_I2C_NACK_INT_ENA_V 0x00000001U +#define LP_I2C_NACK_INT_ENA_S 10 +/** LP_I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for LP_I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_ENA_M (LP_I2C_TXFIFO_OVF_INT_ENA_V << LP_I2C_TXFIFO_OVF_INT_ENA_S) +#define LP_I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_ENA_S 11 +/** LP_I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for LP_I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_ENA_M (LP_I2C_RXFIFO_UDF_INT_ENA_V << LP_I2C_RXFIFO_UDF_INT_ENA_S) +#define LP_I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_ENA_S 12 +/** LP_I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for LP_I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_ENA_M (LP_I2C_SCL_ST_TO_INT_ENA_V << LP_I2C_SCL_ST_TO_INT_ENA_S) +#define LP_I2C_SCL_ST_TO_INT_ENA_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_ENA_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_M (LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V << LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/** LP_I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for LP_I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_ENA (BIT(15)) +#define LP_I2C_DET_START_INT_ENA_M (LP_I2C_DET_START_INT_ENA_V << LP_I2C_DET_START_INT_ENA_S) +#define LP_I2C_DET_START_INT_ENA_V 0x00000001U +#define LP_I2C_DET_START_INT_ENA_S 15 -/** I2C_INT_STATUS_REG register +/** LP_I2C_INT_STATUS_REG register * Status of captured I2C communication events */ -#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c) -/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. - */ -#define I2C_RXFIFO_WM_INT_ST (BIT(0)) -#define I2C_RXFIFO_WM_INT_ST_M (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S) -#define I2C_RXFIFO_WM_INT_ST_V 0x00000001U -#define I2C_RXFIFO_WM_INT_ST_S 0 -/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. - */ -#define I2C_TXFIFO_WM_INT_ST (BIT(1)) -#define I2C_TXFIFO_WM_INT_ST_M (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S) -#define I2C_TXFIFO_WM_INT_ST_V 0x00000001U -#define I2C_TXFIFO_WM_INT_ST_S 1 -/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. - */ -#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ST_M (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S) -#define I2C_RXFIFO_OVF_INT_ST_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_ST_S 2 -/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. - */ -#define I2C_END_DETECT_INT_ST (BIT(3)) -#define I2C_END_DETECT_INT_ST_M (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S) -#define I2C_END_DETECT_INT_ST_V 0x00000001U -#define I2C_END_DETECT_INT_ST_S 3 -/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. - */ -#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ST_M (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S) -#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 -/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. - */ -#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ST_M (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S) -#define I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_ST_S 5 -/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ST_M (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S) -#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 -/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; - * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. - */ -#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ST_M (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S) -#define I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_ST_S 7 -/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; - * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. - */ -#define I2C_TIME_OUT_INT_ST (BIT(8)) -#define I2C_TIME_OUT_INT_ST_M (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S) -#define I2C_TIME_OUT_INT_ST_V 0x00000001U -#define I2C_TIME_OUT_INT_ST_S 8 -/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; - * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. - */ -#define I2C_TRANS_START_INT_ST (BIT(9)) -#define I2C_TRANS_START_INT_ST_M (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S) -#define I2C_TRANS_START_INT_ST_V 0x00000001U -#define I2C_TRANS_START_INT_ST_S 9 -/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; - * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. - */ -#define I2C_NACK_INT_ST (BIT(10)) -#define I2C_NACK_INT_ST_M (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S) -#define I2C_NACK_INT_ST_V 0x00000001U -#define I2C_NACK_INT_ST_S 10 -/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; - * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. - */ -#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ST_M (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S) -#define I2C_TXFIFO_OVF_INT_ST_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_ST_S 11 -/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. - */ -#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ST_M (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S) -#define I2C_RXFIFO_UDF_INT_ST_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_ST_S 12 -/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; - * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. - */ -#define I2C_SCL_ST_TO_INT_ST (BIT(13)) -#define I2C_SCL_ST_TO_INT_ST_M (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S) -#define I2C_SCL_ST_TO_INT_ST_V 0x00000001U -#define I2C_SCL_ST_TO_INT_ST_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; - * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. - */ -#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ST_M (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S) -#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 -/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; - * The masked interrupt status bit for I2C_DET_START_INT interrupt. - */ -#define I2C_DET_START_INT_ST (BIT(15)) -#define I2C_DET_START_INT_ST_M (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S) -#define I2C_DET_START_INT_ST_V 0x00000001U -#define I2C_DET_START_INT_ST_S 15 +#define LP_I2C_INT_STATUS_REG (DR_REG_LP_I2C_BASE + 0x2c) +/** LP_I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for LP_I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_ST_M (LP_I2C_RXFIFO_WM_INT_ST_V << LP_I2C_RXFIFO_WM_INT_ST_S) +#define LP_I2C_RXFIFO_WM_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_ST_S 0 +/** LP_I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for LP_I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_ST_M (LP_I2C_TXFIFO_WM_INT_ST_V << LP_I2C_TXFIFO_WM_INT_ST_S) +#define LP_I2C_TXFIFO_WM_INT_ST_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_ST_S 1 +/** LP_I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for LP_I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_ST_M (LP_I2C_RXFIFO_OVF_INT_ST_V << LP_I2C_RXFIFO_OVF_INT_ST_S) +#define LP_I2C_RXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_ST_S 2 +/** LP_I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_ST (BIT(3)) +#define LP_I2C_END_DETECT_INT_ST_M (LP_I2C_END_DETECT_INT_ST_V << LP_I2C_END_DETECT_INT_ST_S) +#define LP_I2C_END_DETECT_INT_ST_V 0x00000001U +#define LP_I2C_END_DETECT_INT_ST_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_M (LP_I2C_BYTE_TRANS_DONE_INT_ST_V << LP_I2C_BYTE_TRANS_DONE_INT_ST_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_ST_M (LP_I2C_ARBITRATION_LOST_INT_ST_V << LP_I2C_ARBITRATION_LOST_INT_ST_S) +#define LP_I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_ST_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_M (LP_I2C_MST_TXFIFO_UDF_INT_ST_V << LP_I2C_MST_TXFIFO_UDF_INT_ST_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_ST_M (LP_I2C_TRANS_COMPLETE_INT_ST_V << LP_I2C_TRANS_COMPLETE_INT_ST_S) +#define LP_I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_ST_S 7 +/** LP_I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the LP_I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_ST (BIT(8)) +#define LP_I2C_TIME_OUT_INT_ST_M (LP_I2C_TIME_OUT_INT_ST_V << LP_I2C_TIME_OUT_INT_ST_S) +#define LP_I2C_TIME_OUT_INT_ST_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_ST_S 8 +/** LP_I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the LP_I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_ST (BIT(9)) +#define LP_I2C_TRANS_START_INT_ST_M (LP_I2C_TRANS_START_INT_ST_V << LP_I2C_TRANS_START_INT_ST_S) +#define LP_I2C_TRANS_START_INT_ST_V 0x00000001U +#define LP_I2C_TRANS_START_INT_ST_S 9 +/** LP_I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for LP_I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_ST (BIT(10)) +#define LP_I2C_NACK_INT_ST_M (LP_I2C_NACK_INT_ST_V << LP_I2C_NACK_INT_ST_S) +#define LP_I2C_NACK_INT_ST_V 0x00000001U +#define LP_I2C_NACK_INT_ST_S 10 +/** LP_I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for LP_I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_ST_M (LP_I2C_TXFIFO_OVF_INT_ST_V << LP_I2C_TXFIFO_OVF_INT_ST_S) +#define LP_I2C_TXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_ST_S 11 +/** LP_I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for LP_I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_ST_M (LP_I2C_RXFIFO_UDF_INT_ST_V << LP_I2C_RXFIFO_UDF_INT_ST_S) +#define LP_I2C_RXFIFO_UDF_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_ST_S 12 +/** LP_I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for LP_I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_ST_M (LP_I2C_SCL_ST_TO_INT_ST_V << LP_I2C_SCL_ST_TO_INT_ST_S) +#define LP_I2C_SCL_ST_TO_INT_ST_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_ST_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_M (LP_I2C_SCL_MAIN_ST_TO_INT_ST_V << LP_I2C_SCL_MAIN_ST_TO_INT_ST_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/** LP_I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for LP_I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_ST (BIT(15)) +#define LP_I2C_DET_START_INT_ST_M (LP_I2C_DET_START_INT_ST_V << LP_I2C_DET_START_INT_ST_S) +#define LP_I2C_DET_START_INT_ST_V 0x00000001U +#define LP_I2C_DET_START_INT_ST_S 15 -/** I2C_SDA_HOLD_REG register +/** LP_I2C_SDA_HOLD_REG register * Configures the hold time after a negative SCL edge. */ -#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30) -/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SDA_HOLD_REG (DR_REG_LP_I2C_BASE + 0x30) +/** LP_I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; * This register is used to configure the time to hold the data after the negativeedge * of SCL, in I2C module clock cycles. */ -#define I2C_SDA_HOLD_TIME 0x000001FFU -#define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) -#define I2C_SDA_HOLD_TIME_V 0x000001FFU -#define I2C_SDA_HOLD_TIME_S 0 +#define LP_I2C_SDA_HOLD_TIME 0x000001FFU +#define LP_I2C_SDA_HOLD_TIME_M (LP_I2C_SDA_HOLD_TIME_V << LP_I2C_SDA_HOLD_TIME_S) +#define LP_I2C_SDA_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SDA_HOLD_TIME_S 0 -/** I2C_SDA_SAMPLE_REG register +/** LP_I2C_SDA_SAMPLE_REG register * Configures the sample time after a positive SCL edge. */ -#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34) -/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SDA_SAMPLE_REG (DR_REG_LP_I2C_BASE + 0x34) +/** LP_I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; * This register is used to configure for how long SDA is sampled, in I2C module clock * cycles. */ -#define I2C_SDA_SAMPLE_TIME 0x000001FFU -#define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) -#define I2C_SDA_SAMPLE_TIME_V 0x000001FFU -#define I2C_SDA_SAMPLE_TIME_S 0 +#define LP_I2C_SDA_SAMPLE_TIME 0x000001FFU +#define LP_I2C_SDA_SAMPLE_TIME_M (LP_I2C_SDA_SAMPLE_TIME_V << LP_I2C_SDA_SAMPLE_TIME_S) +#define LP_I2C_SDA_SAMPLE_TIME_V 0x000001FFU +#define LP_I2C_SDA_SAMPLE_TIME_S 0 -/** I2C_SCL_HIGH_PERIOD_REG register +/** LP_I2C_SCL_HIGH_PERIOD_REG register * Configures the high level width of SCL */ -#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38) -/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SCL_HIGH_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x38) +/** LP_I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; * This register is used to configure for how long SCL setup to high level and remains * high in master mode, in I2C module clock cycles. */ -#define I2C_SCL_HIGH_PERIOD 0x000001FFU -#define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) -#define I2C_SCL_HIGH_PERIOD_V 0x000001FFU -#define I2C_SCL_HIGH_PERIOD_S 0 -/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; +#define LP_I2C_SCL_HIGH_PERIOD 0x000001FFU +#define LP_I2C_SCL_HIGH_PERIOD_M (LP_I2C_SCL_HIGH_PERIOD_V << LP_I2C_SCL_HIGH_PERIOD_S) +#define LP_I2C_SCL_HIGH_PERIOD_V 0x000001FFU +#define LP_I2C_SCL_HIGH_PERIOD_S 0 +/** LP_I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; * This register is used to configure for the SCL_FSM's waiting period for SCL high * level in master mode, in I2C module clock cycles. */ -#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU -#define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) -#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU -#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 +#define LP_I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_M (LP_I2C_SCL_WAIT_HIGH_PERIOD_V << LP_I2C_SCL_WAIT_HIGH_PERIOD_S) +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_S 9 -/** I2C_SCL_START_HOLD_REG register +/** LP_I2C_SCL_START_HOLD_REG register * Configures the delay between the SDA and SCL negative edge for a start condition */ -#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40) -/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_START_HOLD_REG (DR_REG_LP_I2C_BASE + 0x40) +/** LP_I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the time between the negative edgeof SDA and the * negative edge of SCL for a START condition, in I2C module clock cycles. */ -#define I2C_SCL_START_HOLD_TIME 0x000001FFU -#define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) -#define I2C_SCL_START_HOLD_TIME_V 0x000001FFU -#define I2C_SCL_START_HOLD_TIME_S 0 +#define LP_I2C_SCL_START_HOLD_TIME 0x000001FFU +#define LP_I2C_SCL_START_HOLD_TIME_M (LP_I2C_SCL_START_HOLD_TIME_V << LP_I2C_SCL_START_HOLD_TIME_S) +#define LP_I2C_SCL_START_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SCL_START_HOLD_TIME_S 0 -/** I2C_SCL_RSTART_SETUP_REG register +/** LP_I2C_SCL_RSTART_SETUP_REG register * Configures the delay between the positive * edge of SCL and the negative edge of SDA */ -#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44) -/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_RSTART_SETUP_REG (DR_REG_LP_I2C_BASE + 0x44) +/** LP_I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the time between the positiveedge of SCL and the * negative edge of SDA for a RESTART condition, in I2C module clock cycles. */ -#define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU -#define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) -#define I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU -#define I2C_SCL_RSTART_SETUP_TIME_S 0 +#define LP_I2C_SCL_RSTART_SETUP_TIME 0x000001FFU +#define LP_I2C_SCL_RSTART_SETUP_TIME_M (LP_I2C_SCL_RSTART_SETUP_TIME_V << LP_I2C_SCL_RSTART_SETUP_TIME_S) +#define LP_I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU +#define LP_I2C_SCL_RSTART_SETUP_TIME_S 0 -/** I2C_SCL_STOP_HOLD_REG register +/** LP_I2C_SCL_STOP_HOLD_REG register * Configures the delay after the SCL clock * edge for a stop condition */ -#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48) -/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_STOP_HOLD_REG (DR_REG_LP_I2C_BASE + 0x48) +/** LP_I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the delay after the STOP condition,in I2C module * clock cycles. */ -#define I2C_SCL_STOP_HOLD_TIME 0x000001FFU -#define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) -#define I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU -#define I2C_SCL_STOP_HOLD_TIME_S 0 +#define LP_I2C_SCL_STOP_HOLD_TIME 0x000001FFU +#define LP_I2C_SCL_STOP_HOLD_TIME_M (LP_I2C_SCL_STOP_HOLD_TIME_V << LP_I2C_SCL_STOP_HOLD_TIME_S) +#define LP_I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SCL_STOP_HOLD_TIME_S 0 -/** I2C_SCL_STOP_SETUP_REG register +/** LP_I2C_SCL_STOP_SETUP_REG register * Configures the delay between the SDA and * SCL positive edge for a stop condition */ -#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c) -/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_STOP_SETUP_REG (DR_REG_LP_I2C_BASE + 0x4c) +/** LP_I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the time between the positive edgeof SCL and the * positive edge of SDA, in I2C module clock cycles. */ -#define I2C_SCL_STOP_SETUP_TIME 0x000001FFU -#define I2C_SCL_STOP_SETUP_TIME_M (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S) -#define I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU -#define I2C_SCL_STOP_SETUP_TIME_S 0 +#define LP_I2C_SCL_STOP_SETUP_TIME 0x000001FFU +#define LP_I2C_SCL_STOP_SETUP_TIME_M (LP_I2C_SCL_STOP_SETUP_TIME_V << LP_I2C_SCL_STOP_SETUP_TIME_S) +#define LP_I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU +#define LP_I2C_SCL_STOP_SETUP_TIME_S 0 -/** I2C_FILTER_CFG_REG register +/** LP_I2C_FILTER_CFG_REG register * SCL and SDA filter configuration register */ -#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50) -/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; +#define LP_I2C_FILTER_CFG_REG (DR_REG_LP_I2C_BASE + 0x50) +/** LP_I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; * When a pulse on the SCL input has smaller width than this register valuein I2C * module clock cycles, the I2C controller will ignore that pulse. */ -#define I2C_SCL_FILTER_THRES 0x0000000FU -#define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) -#define I2C_SCL_FILTER_THRES_V 0x0000000FU -#define I2C_SCL_FILTER_THRES_S 0 -/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; +#define LP_I2C_SCL_FILTER_THRES 0x0000000FU +#define LP_I2C_SCL_FILTER_THRES_M (LP_I2C_SCL_FILTER_THRES_V << LP_I2C_SCL_FILTER_THRES_S) +#define LP_I2C_SCL_FILTER_THRES_V 0x0000000FU +#define LP_I2C_SCL_FILTER_THRES_S 0 +/** LP_I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; * When a pulse on the SDA input has smaller width than this register valuein I2C * module clock cycles, the I2C controller will ignore that pulse. */ -#define I2C_SDA_FILTER_THRES 0x0000000FU -#define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) -#define I2C_SDA_FILTER_THRES_V 0x0000000FU -#define I2C_SDA_FILTER_THRES_S 4 -/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; +#define LP_I2C_SDA_FILTER_THRES 0x0000000FU +#define LP_I2C_SDA_FILTER_THRES_M (LP_I2C_SDA_FILTER_THRES_V << LP_I2C_SDA_FILTER_THRES_S) +#define LP_I2C_SDA_FILTER_THRES_V 0x0000000FU +#define LP_I2C_SDA_FILTER_THRES_S 4 +/** LP_I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; * This is the filter enable bit for SCL. */ -#define I2C_SCL_FILTER_EN (BIT(8)) -#define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) -#define I2C_SCL_FILTER_EN_V 0x00000001U -#define I2C_SCL_FILTER_EN_S 8 -/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; +#define LP_I2C_SCL_FILTER_EN (BIT(8)) +#define LP_I2C_SCL_FILTER_EN_M (LP_I2C_SCL_FILTER_EN_V << LP_I2C_SCL_FILTER_EN_S) +#define LP_I2C_SCL_FILTER_EN_V 0x00000001U +#define LP_I2C_SCL_FILTER_EN_S 8 +/** LP_I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; * This is the filter enable bit for SDA. */ -#define I2C_SDA_FILTER_EN (BIT(9)) -#define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) -#define I2C_SDA_FILTER_EN_V 0x00000001U -#define I2C_SDA_FILTER_EN_S 9 +#define LP_I2C_SDA_FILTER_EN (BIT(9)) +#define LP_I2C_SDA_FILTER_EN_M (LP_I2C_SDA_FILTER_EN_V << LP_I2C_SDA_FILTER_EN_S) +#define LP_I2C_SDA_FILTER_EN_V 0x00000001U +#define LP_I2C_SDA_FILTER_EN_S 9 -/** I2C_CLK_CONF_REG register +/** LP_I2C_CLK_CONF_REG register * I2C CLK configuration register */ -#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54) -/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; +#define LP_I2C_CLK_CONF_REG (DR_REG_LP_I2C_BASE + 0x54) +/** LP_I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; * the integral part of the fractional divisor for i2c module */ -#define I2C_SCLK_DIV_NUM 0x000000FFU -#define I2C_SCLK_DIV_NUM_M (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S) -#define I2C_SCLK_DIV_NUM_V 0x000000FFU -#define I2C_SCLK_DIV_NUM_S 0 -/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; +#define LP_I2C_SCLK_DIV_NUM 0x000000FFU +#define LP_I2C_SCLK_DIV_NUM_M (LP_I2C_SCLK_DIV_NUM_V << LP_I2C_SCLK_DIV_NUM_S) +#define LP_I2C_SCLK_DIV_NUM_V 0x000000FFU +#define LP_I2C_SCLK_DIV_NUM_S 0 +/** LP_I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; * the numerator of the fractional part of the fractional divisor for i2c module */ -#define I2C_SCLK_DIV_A 0x0000003FU -#define I2C_SCLK_DIV_A_M (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S) -#define I2C_SCLK_DIV_A_V 0x0000003FU -#define I2C_SCLK_DIV_A_S 8 -/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; +#define LP_I2C_SCLK_DIV_A 0x0000003FU +#define LP_I2C_SCLK_DIV_A_M (LP_I2C_SCLK_DIV_A_V << LP_I2C_SCLK_DIV_A_S) +#define LP_I2C_SCLK_DIV_A_V 0x0000003FU +#define LP_I2C_SCLK_DIV_A_S 8 +/** LP_I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; * the denominator of the fractional part of the fractional divisor for i2c module */ -#define I2C_SCLK_DIV_B 0x0000003FU -#define I2C_SCLK_DIV_B_M (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S) -#define I2C_SCLK_DIV_B_V 0x0000003FU -#define I2C_SCLK_DIV_B_S 14 -/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; +#define LP_I2C_SCLK_DIV_B 0x0000003FU +#define LP_I2C_SCLK_DIV_B_M (LP_I2C_SCLK_DIV_B_V << LP_I2C_SCLK_DIV_B_S) +#define LP_I2C_SCLK_DIV_B_V 0x0000003FU +#define LP_I2C_SCLK_DIV_B_S 14 +/** LP_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. */ -#define I2C_SCLK_SEL (BIT(20)) -#define I2C_SCLK_SEL_M (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S) -#define I2C_SCLK_SEL_V 0x00000001U -#define I2C_SCLK_SEL_S 20 -/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; +#define LP_I2C_SCLK_SEL (BIT(20)) +#define LP_I2C_SCLK_SEL_M (LP_I2C_SCLK_SEL_V << LP_I2C_SCLK_SEL_S) +#define LP_I2C_SCLK_SEL_V 0x00000001U +#define LP_I2C_SCLK_SEL_S 20 +/** LP_I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; * The clock switch for i2c module */ -#define I2C_SCLK_ACTIVE (BIT(21)) -#define I2C_SCLK_ACTIVE_M (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S) -#define I2C_SCLK_ACTIVE_V 0x00000001U -#define I2C_SCLK_ACTIVE_S 21 +#define LP_I2C_SCLK_ACTIVE (BIT(21)) +#define LP_I2C_SCLK_ACTIVE_M (LP_I2C_SCLK_ACTIVE_V << LP_I2C_SCLK_ACTIVE_S) +#define LP_I2C_SCLK_ACTIVE_V 0x00000001U +#define LP_I2C_SCLK_ACTIVE_S 21 -/** I2C_COMD0_REG register +/** LP_I2C_COMD0_REG register * I2C command register 0 */ -#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58) -/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD0_REG (DR_REG_LP_I2C_BASE + 0x58) +/** LP_I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 0. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND0 0x00003FFFU -#define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) -#define I2C_COMMAND0_V 0x00003FFFU -#define I2C_COMMAND0_S 0 -/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND0 0x00003FFFU +#define LP_I2C_COMMAND0_M (LP_I2C_COMMAND0_V << LP_I2C_COMMAND0_S) +#define LP_I2C_COMMAND0_V 0x00003FFFU +#define LP_I2C_COMMAND0_S 0 +/** LP_I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 0 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND0_DONE (BIT(31)) -#define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) -#define I2C_COMMAND0_DONE_V 0x00000001U -#define I2C_COMMAND0_DONE_S 31 +#define LP_I2C_COMMAND0_DONE (BIT(31)) +#define LP_I2C_COMMAND0_DONE_M (LP_I2C_COMMAND0_DONE_V << LP_I2C_COMMAND0_DONE_S) +#define LP_I2C_COMMAND0_DONE_V 0x00000001U +#define LP_I2C_COMMAND0_DONE_S 31 -/** I2C_COMD1_REG register +/** LP_I2C_COMD1_REG register * I2C command register 1 */ -#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c) -/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD1_REG (DR_REG_LP_I2C_BASE + 0x5c) +/** LP_I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 1. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND1 0x00003FFFU -#define I2C_COMMAND1_M (I2C_COMMAND1_V << I2C_COMMAND1_S) -#define I2C_COMMAND1_V 0x00003FFFU -#define I2C_COMMAND1_S 0 -/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND1 0x00003FFFU +#define LP_I2C_COMMAND1_M (LP_I2C_COMMAND1_V << LP_I2C_COMMAND1_S) +#define LP_I2C_COMMAND1_V 0x00003FFFU +#define LP_I2C_COMMAND1_S 0 +/** LP_I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 1 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND1_DONE (BIT(31)) -#define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) -#define I2C_COMMAND1_DONE_V 0x00000001U -#define I2C_COMMAND1_DONE_S 31 +#define LP_I2C_COMMAND1_DONE (BIT(31)) +#define LP_I2C_COMMAND1_DONE_M (LP_I2C_COMMAND1_DONE_V << LP_I2C_COMMAND1_DONE_S) +#define LP_I2C_COMMAND1_DONE_V 0x00000001U +#define LP_I2C_COMMAND1_DONE_S 31 -/** I2C_COMD2_REG register +/** LP_I2C_COMD2_REG register * I2C command register 2 */ -#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60) -/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD2_REG (DR_REG_LP_I2C_BASE + 0x60) +/** LP_I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 2. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND2 0x00003FFFU -#define I2C_COMMAND2_M (I2C_COMMAND2_V << I2C_COMMAND2_S) -#define I2C_COMMAND2_V 0x00003FFFU -#define I2C_COMMAND2_S 0 -/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND2 0x00003FFFU +#define LP_I2C_COMMAND2_M (LP_I2C_COMMAND2_V << LP_I2C_COMMAND2_S) +#define LP_I2C_COMMAND2_V 0x00003FFFU +#define LP_I2C_COMMAND2_S 0 +/** LP_I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 2 is done in I2C Master mode, this bit changes to highLevel. */ -#define I2C_COMMAND2_DONE (BIT(31)) -#define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) -#define I2C_COMMAND2_DONE_V 0x00000001U -#define I2C_COMMAND2_DONE_S 31 +#define LP_I2C_COMMAND2_DONE (BIT(31)) +#define LP_I2C_COMMAND2_DONE_M (LP_I2C_COMMAND2_DONE_V << LP_I2C_COMMAND2_DONE_S) +#define LP_I2C_COMMAND2_DONE_V 0x00000001U +#define LP_I2C_COMMAND2_DONE_S 31 -/** I2C_COMD3_REG register +/** LP_I2C_COMD3_REG register * I2C command register 3 */ -#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64) -/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD3_REG (DR_REG_LP_I2C_BASE + 0x64) +/** LP_I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 3. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND3 0x00003FFFU -#define I2C_COMMAND3_M (I2C_COMMAND3_V << I2C_COMMAND3_S) -#define I2C_COMMAND3_V 0x00003FFFU -#define I2C_COMMAND3_S 0 -/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND3 0x00003FFFU +#define LP_I2C_COMMAND3_M (LP_I2C_COMMAND3_V << LP_I2C_COMMAND3_S) +#define LP_I2C_COMMAND3_V 0x00003FFFU +#define LP_I2C_COMMAND3_S 0 +/** LP_I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 3 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND3_DONE (BIT(31)) -#define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) -#define I2C_COMMAND3_DONE_V 0x00000001U -#define I2C_COMMAND3_DONE_S 31 +#define LP_I2C_COMMAND3_DONE (BIT(31)) +#define LP_I2C_COMMAND3_DONE_M (LP_I2C_COMMAND3_DONE_V << LP_I2C_COMMAND3_DONE_S) +#define LP_I2C_COMMAND3_DONE_V 0x00000001U +#define LP_I2C_COMMAND3_DONE_S 31 -/** I2C_COMD4_REG register +/** LP_I2C_COMD4_REG register * I2C command register 4 */ -#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68) -/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD4_REG (DR_REG_LP_I2C_BASE + 0x68) +/** LP_I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 4. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND4 0x00003FFFU -#define I2C_COMMAND4_M (I2C_COMMAND4_V << I2C_COMMAND4_S) -#define I2C_COMMAND4_V 0x00003FFFU -#define I2C_COMMAND4_S 0 -/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND4 0x00003FFFU +#define LP_I2C_COMMAND4_M (LP_I2C_COMMAND4_V << LP_I2C_COMMAND4_S) +#define LP_I2C_COMMAND4_V 0x00003FFFU +#define LP_I2C_COMMAND4_S 0 +/** LP_I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 4 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND4_DONE (BIT(31)) -#define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) -#define I2C_COMMAND4_DONE_V 0x00000001U -#define I2C_COMMAND4_DONE_S 31 +#define LP_I2C_COMMAND4_DONE (BIT(31)) +#define LP_I2C_COMMAND4_DONE_M (LP_I2C_COMMAND4_DONE_V << LP_I2C_COMMAND4_DONE_S) +#define LP_I2C_COMMAND4_DONE_V 0x00000001U +#define LP_I2C_COMMAND4_DONE_S 31 -/** I2C_COMD5_REG register +/** LP_I2C_COMD5_REG register * I2C command register 5 */ -#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c) -/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD5_REG (DR_REG_LP_I2C_BASE + 0x6c) +/** LP_I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 5. It consists of three parts:op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND5 0x00003FFFU -#define I2C_COMMAND5_M (I2C_COMMAND5_V << I2C_COMMAND5_S) -#define I2C_COMMAND5_V 0x00003FFFU -#define I2C_COMMAND5_S 0 -/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND5 0x00003FFFU +#define LP_I2C_COMMAND5_M (LP_I2C_COMMAND5_V << LP_I2C_COMMAND5_S) +#define LP_I2C_COMMAND5_V 0x00003FFFU +#define LP_I2C_COMMAND5_S 0 +/** LP_I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 5 is done in I2C Master mode, this bit changes to high level. */ -#define I2C_COMMAND5_DONE (BIT(31)) -#define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) -#define I2C_COMMAND5_DONE_V 0x00000001U -#define I2C_COMMAND5_DONE_S 31 +#define LP_I2C_COMMAND5_DONE (BIT(31)) +#define LP_I2C_COMMAND5_DONE_M (LP_I2C_COMMAND5_DONE_V << LP_I2C_COMMAND5_DONE_S) +#define LP_I2C_COMMAND5_DONE_V 0x00000001U +#define LP_I2C_COMMAND5_DONE_S 31 -/** I2C_COMD6_REG register +/** LP_I2C_COMD6_REG register * I2C command register 6 */ -#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70) -/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD6_REG (DR_REG_LP_I2C_BASE + 0x70) +/** LP_I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 6. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND6 0x00003FFFU -#define I2C_COMMAND6_M (I2C_COMMAND6_V << I2C_COMMAND6_S) -#define I2C_COMMAND6_V 0x00003FFFU -#define I2C_COMMAND6_S 0 -/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND6 0x00003FFFU +#define LP_I2C_COMMAND6_M (LP_I2C_COMMAND6_V << LP_I2C_COMMAND6_S) +#define LP_I2C_COMMAND6_V 0x00003FFFU +#define LP_I2C_COMMAND6_S 0 +/** LP_I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 6 is done in I2C Master mode, this bit changes to high level. */ -#define I2C_COMMAND6_DONE (BIT(31)) -#define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) -#define I2C_COMMAND6_DONE_V 0x00000001U -#define I2C_COMMAND6_DONE_S 31 +#define LP_I2C_COMMAND6_DONE (BIT(31)) +#define LP_I2C_COMMAND6_DONE_M (LP_I2C_COMMAND6_DONE_V << LP_I2C_COMMAND6_DONE_S) +#define LP_I2C_COMMAND6_DONE_V 0x00000001U +#define LP_I2C_COMMAND6_DONE_S 31 -/** I2C_COMD7_REG register +/** LP_I2C_COMD7_REG register * I2C command register 7 */ -#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74) -/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD7_REG (DR_REG_LP_I2C_BASE + 0x74) +/** LP_I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 7. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND7 0x00003FFFU -#define I2C_COMMAND7_M (I2C_COMMAND7_V << I2C_COMMAND7_S) -#define I2C_COMMAND7_V 0x00003FFFU -#define I2C_COMMAND7_S 0 -/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND7 0x00003FFFU +#define LP_I2C_COMMAND7_M (LP_I2C_COMMAND7_V << LP_I2C_COMMAND7_S) +#define LP_I2C_COMMAND7_V 0x00003FFFU +#define LP_I2C_COMMAND7_S 0 +/** LP_I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 7 is done in I2C Master mode, this bit changes to high level. */ -#define I2C_COMMAND7_DONE (BIT(31)) -#define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) -#define I2C_COMMAND7_DONE_V 0x00000001U -#define I2C_COMMAND7_DONE_S 31 +#define LP_I2C_COMMAND7_DONE (BIT(31)) +#define LP_I2C_COMMAND7_DONE_M (LP_I2C_COMMAND7_DONE_V << LP_I2C_COMMAND7_DONE_S) +#define LP_I2C_COMMAND7_DONE_V 0x00000001U +#define LP_I2C_COMMAND7_DONE_S 31 -/** I2C_SCL_ST_TIME_OUT_REG register +/** LP_I2C_SCL_ST_TIME_OUT_REG register * SCL status time out register */ -#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78) -/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; +#define LP_I2C_SCL_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x78) +/** LP_I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 */ -#define I2C_SCL_ST_TO_I2C 0x0000001FU -#define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) -#define I2C_SCL_ST_TO_I2C_V 0x0000001FU -#define I2C_SCL_ST_TO_I2C_S 0 +#define LP_I2C_SCL_ST_TO_I2C 0x0000001FU +#define LP_I2C_SCL_ST_TO_LP_I2C_M (LP_I2C_SCL_ST_TO_LP_I2C_V << LP_I2C_SCL_ST_TO_LP_I2C_S) +#define LP_I2C_SCL_ST_TO_LP_I2C_V 0x0000001FU +#define LP_I2C_SCL_ST_TO_LP_I2C_S 0 -/** I2C_SCL_MAIN_ST_TIME_OUT_REG register +/** LP_I2C_SCL_MAIN_ST_TIME_OUT_REG register * SCL main status time out register */ -#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c) -/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; +#define LP_I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x7c) +/** LP_I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more * than 23 */ -#define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU -#define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) -#define I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001FU -#define I2C_SCL_MAIN_ST_TO_I2C_S 0 +#define LP_I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU +#define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_M (LP_I2C_SCL_MAIN_ST_TO_LP_I2C_V << LP_I2C_SCL_MAIN_ST_TO_LP_I2C_S) +#define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_V 0x0000001FU +#define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_S 0 -/** I2C_SCL_SP_CONF_REG register +/** LP_I2C_SCL_SP_CONF_REG register * Power configuration register */ -#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80) -/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; +#define LP_I2C_SCL_SP_CONF_REG (DR_REG_LP_I2C_BASE + 0x80) +/** LP_I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses * equals to reg_scl_rst_slv_num[4:0]. */ -#define I2C_SCL_RST_SLV_EN (BIT(0)) -#define I2C_SCL_RST_SLV_EN_M (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S) -#define I2C_SCL_RST_SLV_EN_V 0x00000001U -#define I2C_SCL_RST_SLV_EN_S 0 -/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; +#define LP_I2C_SCL_RST_SLV_EN (BIT(0)) +#define LP_I2C_SCL_RST_SLV_EN_M (LP_I2C_SCL_RST_SLV_EN_V << LP_I2C_SCL_RST_SLV_EN_S) +#define LP_I2C_SCL_RST_SLV_EN_V 0x00000001U +#define LP_I2C_SCL_RST_SLV_EN_S 0 +/** LP_I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; * Configure the pulses of SCL generated in I2C master mode. Valid when * reg_scl_rst_slv_en is 1. */ -#define I2C_SCL_RST_SLV_NUM 0x0000001FU -#define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) -#define I2C_SCL_RST_SLV_NUM_V 0x0000001FU -#define I2C_SCL_RST_SLV_NUM_S 1 -/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; +#define LP_I2C_SCL_RST_SLV_NUM 0x0000001FU +#define LP_I2C_SCL_RST_SLV_NUM_M (LP_I2C_SCL_RST_SLV_NUM_V << LP_I2C_SCL_RST_SLV_NUM_S) +#define LP_I2C_SCL_RST_SLV_NUM_V 0x0000001FU +#define LP_I2C_SCL_RST_SLV_NUM_S 1 +/** LP_I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. */ -#define I2C_SCL_PD_EN (BIT(6)) -#define I2C_SCL_PD_EN_M (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S) -#define I2C_SCL_PD_EN_V 0x00000001U -#define I2C_SCL_PD_EN_S 6 -/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; +#define LP_I2C_SCL_PD_EN (BIT(6)) +#define LP_I2C_SCL_PD_EN_M (LP_I2C_SCL_PD_EN_V << LP_I2C_SCL_PD_EN_S) +#define LP_I2C_SCL_PD_EN_V 0x00000001U +#define LP_I2C_SCL_PD_EN_S 6 +/** LP_I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. */ -#define I2C_SDA_PD_EN (BIT(7)) -#define I2C_SDA_PD_EN_M (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S) -#define I2C_SDA_PD_EN_V 0x00000001U -#define I2C_SDA_PD_EN_S 7 +#define LP_I2C_SDA_PD_EN (BIT(7)) +#define LP_I2C_SDA_PD_EN_M (LP_I2C_SDA_PD_EN_V << LP_I2C_SDA_PD_EN_S) +#define LP_I2C_SDA_PD_EN_V 0x00000001U +#define LP_I2C_SDA_PD_EN_S 7 -/** I2C_DATE_REG register +/** LP_I2C_DATE_REG register * Version register */ -#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8) -/** I2C_DATE : R/W; bitpos: [31:0]; default: 37765408; +#define LP_I2C_DATE_REG (DR_REG_LP_I2C_BASE + 0xf8) +/** LP_I2C_DATE : R/W; bitpos: [31:0]; default: 37765408; * This is the the version register. */ -#define I2C_DATE 0xFFFFFFFFU -#define I2C_DATE_M (I2C_DATE_V << I2C_DATE_S) -#define I2C_DATE_V 0xFFFFFFFFU -#define I2C_DATE_S 0 +#define LP_I2C_DATE 0xFFFFFFFFU +#define LP_I2C_DATE_M (LP_I2C_DATE_V << LP_I2C_DATE_S) +#define LP_I2C_DATE_V 0xFFFFFFFFU +#define LP_I2C_DATE_S 0 -/** I2C_TXFIFO_START_ADDR_REG register +/** LP_I2C_TXFIFO_START_ADDR_REG register * I2C TXFIFO base address register */ -#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100) -/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; +#define LP_I2C_TXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x100) +/** LP_I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; * This is the I2C txfifo first address. */ -#define I2C_TXFIFO_START_ADDR 0xFFFFFFFFU -#define I2C_TXFIFO_START_ADDR_M (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S) -#define I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU -#define I2C_TXFIFO_START_ADDR_S 0 +#define LP_I2C_TXFIFO_START_ADDR 0xFFFFFFFFU +#define LP_I2C_TXFIFO_START_ADDR_M (LP_I2C_TXFIFO_START_ADDR_V << LP_I2C_TXFIFO_START_ADDR_S) +#define LP_I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU +#define LP_I2C_TXFIFO_START_ADDR_S 0 -/** I2C_RXFIFO_START_ADDR_REG register +/** LP_I2C_RXFIFO_START_ADDR_REG register * I2C RXFIFO base address register */ -#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180) -/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; +#define LP_I2C_RXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x180) +/** LP_I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; * This is the I2C rxfifo first address. */ -#define I2C_RXFIFO_START_ADDR 0xFFFFFFFFU -#define I2C_RXFIFO_START_ADDR_M (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S) -#define I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU -#define I2C_RXFIFO_START_ADDR_S 0 +#define LP_I2C_RXFIFO_START_ADDR 0xFFFFFFFFU +#define LP_I2C_RXFIFO_START_ADDR_M (LP_I2C_RXFIFO_START_ADDR_V << LP_I2C_RXFIFO_START_ADDR_S) +#define LP_I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU +#define LP_I2C_RXFIFO_START_ADDR_S 0 #ifdef __cplusplus } diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h index 0735efd6bed2..db7e40838dab 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h @@ -813,245 +813,19 @@ typedef union { } lp_spi_sleep_conf1_reg_t; -/** Group: LP SPI W0 REG */ -/** Type of spi_w0 register +/** Group: LP SPI Wn REG */ +/** Type of spi_wn register * SPI CPU-controlled buffer0 */ typedef union { struct { - /** reg_buf0 : R/W/SS; bitpos: [31:0]; default: 0; + /** reg_buf : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ - uint32_t reg_buf0:32; + uint32_t reg_buf:32; }; uint32_t val; -} lp_spi_w0_reg_t; - - -/** Group: LP SPI W1 REG */ -/** Type of spi_w1 register - * SPI CPU-controlled buffer1 - */ -typedef union { - struct { - /** reg_buf1 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf1:32; - }; - uint32_t val; -} lp_spi_w1_reg_t; - - -/** Group: LP SPI W2 REG */ -/** Type of spi_w2 register - * SPI CPU-controlled buffer2 - */ -typedef union { - struct { - /** reg_buf2 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf2:32; - }; - uint32_t val; -} lp_spi_w2_reg_t; - - -/** Group: LP SPI W3 REG */ -/** Type of spi_w3 register - * SPI CPU-controlled buffer3 - */ -typedef union { - struct { - /** reg_buf3 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf3:32; - }; - uint32_t val; -} lp_spi_w3_reg_t; - - -/** Group: LP SPI W4 REG */ -/** Type of spi_w4 register - * SPI CPU-controlled buffer4 - */ -typedef union { - struct { - /** reg_buf4 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf4:32; - }; - uint32_t val; -} lp_spi_w4_reg_t; - - -/** Group: LP SPI W5 REG */ -/** Type of spi_w5 register - * SPI CPU-controlled buffer5 - */ -typedef union { - struct { - /** reg_buf5 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf5:32; - }; - uint32_t val; -} lp_spi_w5_reg_t; - - -/** Group: LP SPI W6 REG */ -/** Type of spi_w6 register - * SPI CPU-controlled buffer6 - */ -typedef union { - struct { - /** reg_buf6 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf6:32; - }; - uint32_t val; -} lp_spi_w6_reg_t; - - -/** Group: LP SPI W7 REG */ -/** Type of spi_w7 register - * SPI CPU-controlled buffer7 - */ -typedef union { - struct { - /** reg_buf7 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf7:32; - }; - uint32_t val; -} lp_spi_w7_reg_t; - - -/** Group: LP SPI W8 REG */ -/** Type of spi_w8 register - * SPI CPU-controlled buffer8 - */ -typedef union { - struct { - /** reg_buf8 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf8:32; - }; - uint32_t val; -} lp_spi_w8_reg_t; - - -/** Group: LP SPI W9 REG */ -/** Type of spi_w9 register - * SPI CPU-controlled buffer9 - */ -typedef union { - struct { - /** reg_buf9 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf9:32; - }; - uint32_t val; -} lp_spi_w9_reg_t; - - -/** Group: LP SPI W10 REG */ -/** Type of spi_w10 register - * SPI CPU-controlled buffer10 - */ -typedef union { - struct { - /** reg_buf10 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf10:32; - }; - uint32_t val; -} lp_spi_w10_reg_t; - - -/** Group: LP SPI W11 REG */ -/** Type of spi_w11 register - * SPI CPU-controlled buffer11 - */ -typedef union { - struct { - /** reg_buf11 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf11:32; - }; - uint32_t val; -} lp_spi_w11_reg_t; - - -/** Group: LP SPI W12 REG */ -/** Type of spi_w12 register - * SPI CPU-controlled buffer12 - */ -typedef union { - struct { - /** reg_buf12 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf12:32; - }; - uint32_t val; -} lp_spi_w12_reg_t; - - -/** Group: LP SPI W13 REG */ -/** Type of spi_w13 register - * SPI CPU-controlled buffer13 - */ -typedef union { - struct { - /** reg_buf13 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf13:32; - }; - uint32_t val; -} lp_spi_w13_reg_t; - - -/** Group: LP SPI W14 REG */ -/** Type of spi_w14 register - * SPI CPU-controlled buffer14 - */ -typedef union { - struct { - /** reg_buf14 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf14:32; - }; - uint32_t val; -} lp_spi_w14_reg_t; - - -/** Group: LP SPI W15 REG */ -/** Type of spi_w15 register - * SPI CPU-controlled buffer15 - */ -typedef union { - struct { - /** reg_buf15 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf15:32; - }; - uint32_t val; -} lp_spi_w15_reg_t; - +} lp_spi_wn_reg_t; /** Group: LP SPI SLAVE REG */ /** Type of spi_slave register @@ -1238,22 +1012,7 @@ typedef struct { volatile lp_spi_sleep_conf1_reg_t spi_sleep_conf1; volatile lp_spi_dma_int_set_reg_t spi_dma_int_set; uint32_t reserved_050[18]; - volatile lp_spi_w0_reg_t spi_w0; - volatile lp_spi_w1_reg_t spi_w1; - volatile lp_spi_w2_reg_t spi_w2; - volatile lp_spi_w3_reg_t spi_w3; - volatile lp_spi_w4_reg_t spi_w4; - volatile lp_spi_w5_reg_t spi_w5; - volatile lp_spi_w6_reg_t spi_w6; - volatile lp_spi_w7_reg_t spi_w7; - volatile lp_spi_w8_reg_t spi_w8; - volatile lp_spi_w9_reg_t spi_w9; - volatile lp_spi_w10_reg_t spi_w10; - volatile lp_spi_w11_reg_t spi_w11; - volatile lp_spi_w12_reg_t spi_w12; - volatile lp_spi_w13_reg_t spi_w13; - volatile lp_spi_w14_reg_t spi_w14; - volatile lp_spi_w15_reg_t spi_w15; + volatile lp_spi_wn_reg_t data_buf[16]; uint32_t reserved_0d8[2]; volatile lp_spi_slave_reg_t spi_slave; volatile lp_spi_slave1_reg_t spi_slave1; @@ -1263,12 +1022,12 @@ typedef struct { volatile lp_rnd_eco_cs_reg_t rnd_eco_cs; volatile lp_rnd_eco_low_reg_t rnd_eco_low; volatile lp_rnd_eco_high_reg_t rnd_eco_high; -} lp_dev_t; +} lp_spi_dev_t; -extern lp_dev_t LP_SPI; +extern lp_spi_dev_t LP_SPI; #ifndef __cplusplus -_Static_assert(sizeof(lp_dev_t) == 0x100, "Invalid size of lp_dev_t structure"); +_Static_assert(sizeof(lp_spi_dev_t) == 0x100, "Invalid size of lp_spi_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_reg.h index 683e3596ac03..68abe42e330c 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_reg.h @@ -11,331 +11,331 @@ extern "C" { #endif -/** RTC_TIMER_TAR0_LOW_REG register +/** LP_TIMER_TAR0_LOW_REG register * need_des */ -#define RTC_TIMER_TAR0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x0) -/** RTC_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; +#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0) +/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_M (RTC_TIMER_MAIN_TIMER_TAR_LOW0_V << RTC_TIMER_MAIN_TIMER_TAR_LOW0_S) -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_S 0 +#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0 -/** RTC_TIMER_TAR0_HIGH_REG register +/** LP_TIMER_TAR0_HIGH_REG register * need_des */ -#define RTC_TIMER_TAR0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x4) -/** RTC_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; +#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_M (RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S) -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 -/** RTC_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_TAR_EN0_M (RTC_TIMER_MAIN_TIMER_TAR_EN0_V << RTC_TIMER_MAIN_TIMER_TAR_EN0_S) -#define RTC_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_TAR_EN0_S 31 +#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31 -/** RTC_TIMER_TAR1_LOW_REG register +/** LP_TIMER_TAR1_LOW_REG register * need_des */ -#define RTC_TIMER_TAR1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x8) -/** RTC_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0; +#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8) +/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_M (RTC_TIMER_MAIN_TIMER_TAR_LOW1_V << RTC_TIMER_MAIN_TIMER_TAR_LOW1_S) -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_S 0 +#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0 -/** RTC_TIMER_TAR1_HIGH_REG register +/** LP_TIMER_TAR1_HIGH_REG register * need_des */ -#define RTC_TIMER_TAR1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0xc) -/** RTC_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0; +#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_M (RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S) -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S 0 -/** RTC_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_TAR_EN1_M (RTC_TIMER_MAIN_TIMER_TAR_EN1_V << RTC_TIMER_MAIN_TIMER_TAR_EN1_S) -#define RTC_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_TAR_EN1_S 31 +#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31 -/** RTC_TIMER_UPDATE_REG register +/** LP_TIMER_UPDATE_REG register * need_des */ -#define RTC_TIMER_UPDATE_REG (DR_REG_RTC_TIMER_BASE + 0x10) -/** RTC_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0; +#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10) +/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_UPDATE (BIT(28)) -#define RTC_TIMER_MAIN_TIMER_UPDATE_M (RTC_TIMER_MAIN_TIMER_UPDATE_V << RTC_TIMER_MAIN_TIMER_UPDATE_S) -#define RTC_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_UPDATE_S 28 -/** RTC_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; +#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(28)) +#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S) +#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_UPDATE_S 28 +/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_M (RTC_TIMER_MAIN_TIMER_XTAL_OFF_V << RTC_TIMER_MAIN_TIMER_XTAL_OFF_S) -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_S 29 -/** RTC_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; +#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29 +/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_SYS_STALL_M (RTC_TIMER_MAIN_TIMER_SYS_STALL_V << RTC_TIMER_MAIN_TIMER_SYS_STALL_S) -#define RTC_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_SYS_STALL_S 30 -/** RTC_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30 +/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_SYS_RST_M (RTC_TIMER_MAIN_TIMER_SYS_RST_V << RTC_TIMER_MAIN_TIMER_SYS_RST_S) -#define RTC_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_SYS_RST_S 31 +#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S) +#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31 -/** RTC_TIMER_MAIN_BUF0_LOW_REG register +/** LP_TIMER_MAIN_BUF0_LOW_REG register * need_des */ -#define RTC_TIMER_MAIN_BUF0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x14) -/** RTC_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; +#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14) +/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_M (RTC_TIMER_MAIN_TIMER_BUF0_LOW_V << RTC_TIMER_MAIN_TIMER_BUF0_LOW_S) -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_S 0 +#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0 -/** RTC_TIMER_MAIN_BUF0_HIGH_REG register +/** LP_TIMER_MAIN_BUF0_HIGH_REG register * need_des */ -#define RTC_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x18) -/** RTC_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; +#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18) +/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_M (RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S) -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 -/** RTC_TIMER_MAIN_BUF1_LOW_REG register +/** LP_TIMER_MAIN_BUF1_LOW_REG register * need_des */ -#define RTC_TIMER_MAIN_BUF1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x1c) -/** RTC_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; +#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c) +/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_M (RTC_TIMER_MAIN_TIMER_BUF1_LOW_V << RTC_TIMER_MAIN_TIMER_BUF1_LOW_S) -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_S 0 +#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0 -/** RTC_TIMER_MAIN_BUF1_HIGH_REG register +/** LP_TIMER_MAIN_BUF1_HIGH_REG register * need_des */ -#define RTC_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x20) -/** RTC_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; +#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20) +/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_M (RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S) -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 -/** RTC_TIMER_MAIN_OVERFLOW_REG register +/** LP_TIMER_MAIN_OVERFLOW_REG register * need_des */ -#define RTC_TIMER_MAIN_OVERFLOW_REG (DR_REG_RTC_TIMER_BASE + 0x24) -/** RTC_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24) +/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_M (RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V << RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S) -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 -/** RTC_TIMER_INT_RAW_REG register +/** LP_TIMER_INT_RAW_REG register * need_des */ -#define RTC_TIMER_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x28) -/** RTC_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; +#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28) +/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_OVERFLOW_RAW (BIT(30)) -#define RTC_TIMER_OVERFLOW_RAW_M (RTC_TIMER_OVERFLOW_RAW_V << RTC_TIMER_OVERFLOW_RAW_S) -#define RTC_TIMER_OVERFLOW_RAW_V 0x00000001U -#define RTC_TIMER_OVERFLOW_RAW_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; +#define LP_TIMER_OVERFLOW_RAW (BIT(30)) +#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S) +#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U +#define LP_TIMER_OVERFLOW_RAW_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_RAW_M (RTC_TIMER_SOC_WAKEUP_INT_RAW_V << RTC_TIMER_SOC_WAKEUP_INT_RAW_S) -#define RTC_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_RAW_S 31 +#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31 -/** RTC_TIMER_INT_ST_REG register +/** LP_TIMER_INT_ST_REG register * need_des */ -#define RTC_TIMER_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x2c) -/** RTC_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; +#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c) +/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_OVERFLOW_ST (BIT(30)) -#define RTC_TIMER_OVERFLOW_ST_M (RTC_TIMER_OVERFLOW_ST_V << RTC_TIMER_OVERFLOW_ST_S) -#define RTC_TIMER_OVERFLOW_ST_V 0x00000001U -#define RTC_TIMER_OVERFLOW_ST_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; +#define LP_TIMER_OVERFLOW_ST (BIT(30)) +#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S) +#define LP_TIMER_OVERFLOW_ST_V 0x00000001U +#define LP_TIMER_OVERFLOW_ST_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_ST_M (RTC_TIMER_SOC_WAKEUP_INT_ST_V << RTC_TIMER_SOC_WAKEUP_INT_ST_S) -#define RTC_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_ST_S 31 +#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S) +#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31 -/** RTC_TIMER_INT_ENA_REG register +/** LP_TIMER_INT_ENA_REG register * need_des */ -#define RTC_TIMER_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x30) -/** RTC_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; +#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30) +/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_OVERFLOW_ENA (BIT(30)) -#define RTC_TIMER_OVERFLOW_ENA_M (RTC_TIMER_OVERFLOW_ENA_V << RTC_TIMER_OVERFLOW_ENA_S) -#define RTC_TIMER_OVERFLOW_ENA_V 0x00000001U -#define RTC_TIMER_OVERFLOW_ENA_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; +#define LP_TIMER_OVERFLOW_ENA (BIT(30)) +#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S) +#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U +#define LP_TIMER_OVERFLOW_ENA_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_ENA_M (RTC_TIMER_SOC_WAKEUP_INT_ENA_V << RTC_TIMER_SOC_WAKEUP_INT_ENA_S) -#define RTC_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_ENA_S 31 +#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31 -/** RTC_TIMER_INT_CLR_REG register +/** LP_TIMER_INT_CLR_REG register * need_des */ -#define RTC_TIMER_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x34) -/** RTC_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; +#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34) +/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_OVERFLOW_CLR (BIT(30)) -#define RTC_TIMER_OVERFLOW_CLR_M (RTC_TIMER_OVERFLOW_CLR_V << RTC_TIMER_OVERFLOW_CLR_S) -#define RTC_TIMER_OVERFLOW_CLR_V 0x00000001U -#define RTC_TIMER_OVERFLOW_CLR_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; +#define LP_TIMER_OVERFLOW_CLR (BIT(30)) +#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S) +#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U +#define LP_TIMER_OVERFLOW_CLR_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_CLR_M (RTC_TIMER_SOC_WAKEUP_INT_CLR_V << RTC_TIMER_SOC_WAKEUP_INT_CLR_S) -#define RTC_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_CLR_S 31 +#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31 -/** RTC_TIMER_LP_INT_RAW_REG register +/** LP_TIMER_LP_INT_RAW_REG register * need_des */ -#define RTC_TIMER_LP_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x38) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; +#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_M (RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S 31 +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31 -/** RTC_TIMER_LP_INT_ST_REG register +/** LP_TIMER_LP_INT_ST_REG register * need_des */ -#define RTC_TIMER_LP_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x3c) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0; +#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_M (RTC_TIMER_MAIN_TIMER_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_LP_INT_ST_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_S 31 +#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31 -/** RTC_TIMER_LP_INT_ENA_REG register +/** LP_TIMER_LP_INT_ENA_REG register * need_des */ -#define RTC_TIMER_LP_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x40) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0; +#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_M (RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S 31 +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31 -/** RTC_TIMER_LP_INT_CLR_REG register +/** LP_TIMER_LP_INT_CLR_REG register * need_des */ -#define RTC_TIMER_LP_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x44) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0; +#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_M (RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S 31 +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31 -/** RTC_TIMER_DATE_REG register +/** LP_TIMER_DATE_REG register * need_des */ -#define RTC_TIMER_DATE_REG (DR_REG_RTC_TIMER_BASE + 0x3fc) -/** RTC_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976; +#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc) +/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976; * need_des */ -#define RTC_TIMER_DATE 0x7FFFFFFFU -#define RTC_TIMER_DATE_M (RTC_TIMER_DATE_V << RTC_TIMER_DATE_S) -#define RTC_TIMER_DATE_V 0x7FFFFFFFU -#define RTC_TIMER_DATE_S 0 -/** RTC_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; +#define LP_TIMER_DATE 0x7FFFFFFFU +#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S) +#define LP_TIMER_DATE_V 0x7FFFFFFFU +#define LP_TIMER_DATE_S 0 +/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_CLK_EN (BIT(31)) -#define RTC_TIMER_CLK_EN_M (RTC_TIMER_CLK_EN_V << RTC_TIMER_CLK_EN_S) -#define RTC_TIMER_CLK_EN_V 0x00000001U -#define RTC_TIMER_CLK_EN_S 31 +#define LP_TIMER_CLK_EN (BIT(31)) +#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S) +#define LP_TIMER_CLK_EN_V 0x00000001U +#define LP_TIMER_CLK_EN_S 31 #ifdef __cplusplus } diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h index 32b477ef1085..676f27357a6a 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h @@ -5,6 +5,7 @@ */ #pragma once +#include #include #include "pmu_reg.h" #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h index baa0dbb88d16..a1ae216013e8 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h @@ -287,7 +287,7 @@ extern "C" { #define PPA_RGB2YUV_PROTOCOL_V 0x00000001U #define PPA_RGB2YUV_PROTOCOL_S 11 /** PPA_YUV422_RX_BYTE_ORDER : R/W; bitpos: [13:12]; default: 0; - * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr) */ #define PPA_YUV422_RX_BYTE_ORDER 0x00000003U #define PPA_YUV422_RX_BYTE_ORDER_M (PPA_YUV422_RX_BYTE_ORDER_V << PPA_YUV422_RX_BYTE_ORDER_S) @@ -351,7 +351,7 @@ extern "C" { #define PPA_BLEND_TX_RGB2YUV_PROTOCOL_V 0x00000001U #define PPA_BLEND_TX_RGB2YUV_PROTOCOL_S 15 /** PPA_BLEND0_RX_YUV422_BYTE_ORDER : R/W; bitpos: [17:16]; default: 0; - * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr) */ #define PPA_BLEND0_RX_YUV422_BYTE_ORDER 0x00000003U #define PPA_BLEND0_RX_YUV422_BYTE_ORDER_M (PPA_BLEND0_RX_YUV422_BYTE_ORDER_V << PPA_BLEND0_RX_YUV422_BYTE_ORDER_S) diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h index 855a9df1e9a8..b65bff4e4b99 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h @@ -116,7 +116,7 @@ typedef union { */ uint32_t rgb2yuv_protocol:1; /** yuv422_rx_byte_order : R/W; bitpos: [13:12]; default: 0; - * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr) */ uint32_t yuv422_rx_byte_order:2; uint32_t reserved_14:18; @@ -161,7 +161,7 @@ typedef union { */ uint32_t blend_tx_rgb2yuv_protocol:1; /** blend0_rx_yuv422_byte_order : R/W; bitpos: [17:16]; default: 0; - * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr) */ uint32_t blend0_rx_yuv422_byte_order:2; uint32_t reserved_18:14; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h index 95ce3b2fe2e3..c8978c0f5455 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h @@ -14,1272 +14,1272 @@ extern "C" { /** USB_DEVICE_EP1_REG register * FIFO access for the CDC-ACM data IN and OUT endpoints. */ -#define USB_DEVICE_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0) -/** USB_DEVICE_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0; +#define USB_DEVICE_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) +/** USB_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0; * Write and read byte data to/from UART Tx/Rx FIFO through this field. When * USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) * into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check * USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is * received, then read data from UART Rx FIFO. */ -#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_M (USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_V << USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_S) -#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_S 0 +#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S) +#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_S 0 /** USB_DEVICE_EP1_CONF_REG register * Configuration and control registers for the CDC-ACM FIFOs. */ -#define USB_DEVICE_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4) -/** USB_DEVICE_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; +#define USB_DEVICE_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) +/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; * Set this bit to indicate writing byte data to UART Tx FIFO is done. */ -#define USB_DEVICE_SERIAL_JTAG_WR_DONE (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_WR_DONE_M (USB_DEVICE_SERIAL_JTAG_WR_DONE_V << USB_DEVICE_SERIAL_JTAG_WR_DONE_S) -#define USB_DEVICE_SERIAL_JTAG_WR_DONE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_WR_DONE_S 0 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; +#define USB_SERIAL_JTAG_WR_DONE (BIT(0)) +#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S) +#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001U +#define USB_SERIAL_JTAG_WR_DONE_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing * USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB * Host. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; * 1'b1: Indicate there is data in UART Rx FIFO. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 /** USB_DEVICE_INT_RAW_REG register * Interrupt raw status register. */ -#define USB_DEVICE_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8) -/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; +#define USB_DEVICE_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when flush cmd is received for IN * endpoint 2 of JTAG. */ -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 -/** USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 +/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt bit turns to high level when SOF frame is received. */ -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; +#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S) +#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; * default: 0; * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received * one packet. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 -/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; * The raw interrupt bit turns to high level when pid error is detected. */ -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 -/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; * The raw interrupt bit turns to high level when CRC5 error is detected. */ -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 -/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; * The raw interrupt bit turns to high level when CRC16 error is detected. */ -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 -/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; * The raw interrupt bit turns to high level when stuff error is detected. */ -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 -/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; * default: 0; * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is * received. */ -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 -/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; * The raw interrupt bit turns to high level when usb bus reset is detected. */ -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; * default: 0; * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with * zero palyload. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; * default: 0; * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with * zero palyload. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 -/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; * The raw interrupt bit turns to high level when level of RTS from usb serial channel * is changed. */ -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW (BIT(12)) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_S 12 -/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; * The raw interrupt bit turns to high level when level of DTR from usb serial channel * is changed. */ -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW (BIT(13)) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_S 13 -/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; * The raw interrupt bit turns to high level when level of GET LINE CODING request is * received. */ -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW (BIT(14)) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S 14 -/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; * The raw interrupt bit turns to high level when level of SET LINE CODING request is * received. */ -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW (BIT(15)) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 /** USB_DEVICE_INT_ST_REG register * Interrupt status register. */ -#define USB_DEVICE_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xc) -/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; +#define USB_DEVICE_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; * The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 -/** USB_DEVICE_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; * The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) +#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ST_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; * The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; * The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 -/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; * The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_S 4 -/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; +#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; * The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 -/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; * The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 -/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; * The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 -/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; * The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 -/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; * The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; * The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; * The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 -/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; * The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 -/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; * The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 -/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; * The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 -/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; * The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 /** USB_DEVICE_INT_ENA_REG register * Interrupt enable status register. */ -#define USB_DEVICE_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10) -/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; +#define USB_DEVICE_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 -/** USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; * The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) +#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; * The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; * The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 -/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; * The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 -/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; * The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 -/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; * The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 -/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; * The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 -/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; * The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 -/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; * The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; * The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; * The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 -/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; * The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 -/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; * The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 -/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; * The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 -/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; * The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 /** USB_DEVICE_INT_CLR_REG register * Interrupt clear status register. */ -#define USB_DEVICE_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14) -/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; +#define USB_DEVICE_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; * Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 -/** USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 +/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; * Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) +#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; * Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; * Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 -/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; * Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 -/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; * Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 -/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; * Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 -/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; * Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 -/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; * Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 -/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; * Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; * Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; * Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 -/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; * Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 -/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; * Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 -/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; * Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 -/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; * Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 /** USB_DEVICE_CONF0_REG register * PHY hardware configuration. */ -#define USB_DEVICE_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18) -/** USB_DEVICE_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; +#define USB_DEVICE_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) +/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; * Select internal/external PHY */ -#define USB_DEVICE_SERIAL_JTAG_PHY_SEL (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_PHY_SEL_M (USB_DEVICE_SERIAL_JTAG_PHY_SEL_V << USB_DEVICE_SERIAL_JTAG_PHY_SEL_S) -#define USB_DEVICE_SERIAL_JTAG_PHY_SEL_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PHY_SEL_S 0 -/** USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_PHY_SEL (BIT(0)) +#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S) +#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001U +#define USB_SERIAL_JTAG_PHY_SEL_S 0 +/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; * Enable software control USB D+ D- exchange */ -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 -/** USB_DEVICE_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 +/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; * USB D+ D- exchange */ -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_M (USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_V << USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_S) -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_S 2 -/** USB_DEVICE_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; +#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2)) +#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_S 2 +/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; * Control single-end input high threshold,1.76V to 2V, step 80mV */ -#define USB_DEVICE_SERIAL_JTAG_VREFH 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_VREFH_M (USB_DEVICE_SERIAL_JTAG_VREFH_V << USB_DEVICE_SERIAL_JTAG_VREFH_S) -#define USB_DEVICE_SERIAL_JTAG_VREFH_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_VREFH_S 3 -/** USB_DEVICE_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; +#define USB_SERIAL_JTAG_VREFH 0x00000003U +#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S) +#define USB_SERIAL_JTAG_VREFH_V 0x00000003U +#define USB_SERIAL_JTAG_VREFH_S 3 +/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; * Control single-end input low threshold,0.8V to 1.04V, step 80mV */ -#define USB_DEVICE_SERIAL_JTAG_VREFL 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_VREFL_M (USB_DEVICE_SERIAL_JTAG_VREFL_V << USB_DEVICE_SERIAL_JTAG_VREFL_S) -#define USB_DEVICE_SERIAL_JTAG_VREFL_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_VREFL_S 5 -/** USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_VREFL 0x00000003U +#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S) +#define USB_SERIAL_JTAG_VREFL_V 0x00000003U +#define USB_SERIAL_JTAG_VREFL_S 5 +/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; * Enable software control input threshold */ -#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_M (USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_V << USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_S) -#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_S 7 -/** USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; +#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7 +/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; * Enable software control USB D+ D- pullup pulldown */ -#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) -#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 -/** USB_DEVICE_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 +/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; * Control USB D+ pull up. */ -#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP_M (USB_DEVICE_SERIAL_JTAG_DP_PULLUP_V << USB_DEVICE_SERIAL_JTAG_DP_PULLUP_S) -#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP_S 9 -/** USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; +#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9)) +#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S) +#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLUP_S 9 +/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; * Control USB D+ pull down. */ -#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) -#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_M (USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_V << USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_S) -#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_S 10 -/** USB_DEVICE_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; +#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) +#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S) +#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10 +/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; * Control USB D- pull up. */ -#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP (BIT(11)) -#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP_M (USB_DEVICE_SERIAL_JTAG_DM_PULLUP_V << USB_DEVICE_SERIAL_JTAG_DM_PULLUP_S) -#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP_S 11 -/** USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; +#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11)) +#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S) +#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLUP_S 11 +/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; * Control USB D- pull down. */ -#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) -#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_M (USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_V << USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_S) -#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_S 12 -/** USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; +#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) +#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S) +#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12 +/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; * Control pull up value. */ -#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) -#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_M (USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_V << USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_S) -#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_S 13 -/** USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; +#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) +#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S) +#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U +#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13 +/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; * Enable USB pad function. */ -#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) -#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_S) -#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_S 14 -/** USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0; +#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14 +/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0; * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input * through GPIO Matrix. */ -#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(15)) -#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) -#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(15)) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 /** USB_DEVICE_TEST_REG register * Registers used for debugging the PHY. */ -#define USB_DEVICE_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1c) -/** USB_DEVICE_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; +#define USB_DEVICE_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) +/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; * Enable test of the USB pad */ -#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_M (USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_V << USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_S 0 -/** USB_DEVICE_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0)) +#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S) +#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_ENABLE_S 0 +/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; * USB pad oen in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_M (USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_V << USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_S 1 -/** USB_DEVICE_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) +#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S) +#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_USB_OE_S 1 +/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; * USB D+ tx value in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_M (USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_V << USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_S 2 -/** USB_DEVICE_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2)) +#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S) +#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DP_S 2 +/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; * USB D- tx value in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_M (USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_V << USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_S 3 -/** USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1; +#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3)) +#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S) +#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DM_S 3 +/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1; * USB RCV value in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_M (USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_V << USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_S 4 -/** USB_DEVICE_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1; +#define USB_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) +#define USB_SERIAL_JTAG_TEST_RX_RCV_M (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S) +#define USB_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_RCV_S 4 +/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1; * USB D+ rx value in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_M (USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_V << USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_S 5 -/** USB_DEVICE_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; +#define USB_SERIAL_JTAG_TEST_RX_DP (BIT(5)) +#define USB_SERIAL_JTAG_TEST_RX_DP_M (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S) +#define USB_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DP_S 5 +/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; * USB D- rx value in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_M (USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_V << USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_S 6 +#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6)) +#define USB_SERIAL_JTAG_TEST_RX_DM_M (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S) +#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DM_S 6 /** USB_DEVICE_JFIFO_ST_REG register * JTAG FIFO status and control registers. */ -#define USB_DEVICE_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20) -/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; +#define USB_DEVICE_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) +/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; * JTAT in fifo counter. */ -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_S) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_S 0 -/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; +#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S) +#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0 +/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; * 1: JTAG in fifo is empty. */ -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_S) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 -/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 +/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; * 1: JTAG in fifo is full. */ -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_S) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_S 3 -/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; +#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3 +/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; * JTAT out fifo counter. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_S 4 -/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; +#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S) +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4 +/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; * 1: JTAG out fifo is empty. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 -/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 +/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; * 1: JTAG out fifo is full. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_S 7 -/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; +#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7 +/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; * Write 1 to reset JTAG in fifo. */ -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_S) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_S 8 -/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; +#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8 +/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; * Write 1 to reset JTAG out fifo. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_S 9 +#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9 /** USB_DEVICE_FRAM_NUM_REG register * Last received SOF frame index register. */ -#define USB_DEVICE_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24) -/** USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; +#define USB_DEVICE_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) +/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; * Frame index of received SOF frame. */ -#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU -#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_S) -#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU -#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S) +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 /** USB_DEVICE_IN_EP0_ST_REG register * Control IN endpoint status information. */ -#define USB_DEVICE_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28) -/** USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; +#define USB_DEVICE_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) +/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 0. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S) +#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of IN endpoint 0. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of IN endpoint 0. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 /** USB_DEVICE_IN_EP1_ST_REG register * CDC-ACM IN endpoint status information. */ -#define USB_DEVICE_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2c) -/** USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; +#define USB_DEVICE_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) +/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 1. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S) +#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of IN endpoint 1. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of IN endpoint 1. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 /** USB_DEVICE_IN_EP2_ST_REG register * CDC-ACM interrupt IN endpoint status information. */ -#define USB_DEVICE_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30) -/** USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; +#define USB_DEVICE_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) +/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 2. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S) +#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of IN endpoint 2. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of IN endpoint 2. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 /** USB_DEVICE_IN_EP3_ST_REG register * JTAG IN endpoint status information. */ -#define USB_DEVICE_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34) -/** USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; +#define USB_DEVICE_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) +/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 3. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S) +#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of IN endpoint 3. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of IN endpoint 3. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 /** USB_DEVICE_OUT_EP0_ST_REG register * Control OUT endpoint status information. */ -#define USB_DEVICE_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38) -/** USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; +#define USB_DEVICE_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) +/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; * State of OUT Endpoint 0. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_M (USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_V << USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is * detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of OUT endpoint 0. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 /** USB_DEVICE_OUT_EP1_ST_REG register * CDC-ACM OUT endpoint status information. */ -#define USB_DEVICE_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3c) -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; +#define USB_DEVICE_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) +/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; * State of OUT Endpoint 1. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is * detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of OUT endpoint 1. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; * Data count in OUT endpoint 1 when one packet is received. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 /** USB_DEVICE_OUT_EP2_ST_REG register * JTAG OUT endpoint status information. */ -#define USB_DEVICE_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40) -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; +#define USB_DEVICE_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) +/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; * State of OUT Endpoint 2. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is * detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of OUT endpoint 2. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 /** USB_DEVICE_MISC_CONF_REG register * Clock enable control */ -#define USB_DEVICE_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44) -/** USB_DEVICE_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; +#define USB_DEVICE_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) +/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes * registers. */ -#define USB_DEVICE_SERIAL_JTAG_CLK_EN (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_CLK_EN_M (USB_DEVICE_SERIAL_JTAG_CLK_EN_V << USB_DEVICE_SERIAL_JTAG_CLK_EN_S) -#define USB_DEVICE_SERIAL_JTAG_CLK_EN_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CLK_EN_S 0 +#define USB_SERIAL_JTAG_CLK_EN (BIT(0)) +#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S) +#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_CLK_EN_S 0 -/** USB_DEVICE_MEM_CONF_REG register +/** USB_SERIAL_JTAG_MEM_CONF_REG register * Memory power control */ -#define USB_DEVICE_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48) -/** USB_DEVICE_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; +#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) +/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; * 1: power down usb memory. */ -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_M (USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_V << USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_S) -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_S 0 -/** USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; +#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0)) +#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S) +#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_PD_S 0 +/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; * 1: Force clock on for usb memory. */ -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_S) -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 /** USB_DEVICE_CHIP_RST_REG register * CDC-ACM chip reset control. */ -#define USB_DEVICE_CHIP_RST_REG (DR_REG_USB_DEVICE_BASE + 0x4c) -/** USB_DEVICE_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; +#define USB_DEVICE_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c) +/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. */ -#define USB_DEVICE_SERIAL_JTAG_RTS (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_RTS_M (USB_DEVICE_SERIAL_JTAG_RTS_V << USB_DEVICE_SERIAL_JTAG_RTS_S) -#define USB_DEVICE_SERIAL_JTAG_RTS_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RTS_S 0 -/** USB_DEVICE_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_RTS (BIT(0)) +#define USB_SERIAL_JTAG_RTS_M (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S) +#define USB_SERIAL_JTAG_RTS_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_S 0 +/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0; * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. */ -#define USB_DEVICE_SERIAL_JTAG_DTR (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_DTR_M (USB_DEVICE_SERIAL_JTAG_DTR_V << USB_DEVICE_SERIAL_JTAG_DTR_S) -#define USB_DEVICE_SERIAL_JTAG_DTR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DTR_S 1 -/** USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_DTR (BIT(1)) +#define USB_SERIAL_JTAG_DTR_M (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S) +#define USB_SERIAL_JTAG_DTR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_S 1 +/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0; * Set this bit to disable chip reset from usb serial channel to reset chip. */ -#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M (USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S) -#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS (BIT(2)) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 /** USB_DEVICE_SET_LINE_CODE_W0_REG register * W0 of SET_LINE_CODING command. */ -#define USB_DEVICE_SET_LINE_CODE_W0_REG (DR_REG_USB_DEVICE_BASE + 0x50) -/** USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; +#define USB_DEVICE_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50) +/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; * The value of dwDTERate set by host through SET_LINE_CODING command. */ -#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_M (USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_V << USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_S) -#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_S 0 +#define USB_SERIAL_JTAG_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_M (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_S 0 /** USB_DEVICE_SET_LINE_CODE_W1_REG register * W1 of SET_LINE_CODING command. */ -#define USB_DEVICE_SET_LINE_CODE_W1_REG (DR_REG_USB_DEVICE_BASE + 0x54) -/** USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; +#define USB_DEVICE_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54) +/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; * The value of bCharFormat set by host through SET_LINE_CODING command. */ -#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_M (USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_V << USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_S) -#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_S 0 -/** USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0; +#define USB_SERIAL_JTAG_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_M (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_S 0 +/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0; * The value of bParityTpye set by host through SET_LINE_CODING command. */ -#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_M (USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_V << USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_S) -#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_S 8 -/** USB_DEVICE_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0; +#define USB_SERIAL_JTAG_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_M (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0; * The value of bDataBits set by host through SET_LINE_CODING command. */ -#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS_M (USB_DEVICE_SERIAL_JTAG_BDATA_BITS_V << USB_DEVICE_SERIAL_JTAG_BDATA_BITS_S) -#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS_S 16 +#define USB_SERIAL_JTAG_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_M (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S) +#define USB_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_S 16 /** USB_DEVICE_GET_LINE_CODE_W0_REG register * W0 of GET_LINE_CODING command. */ -#define USB_DEVICE_GET_LINE_CODE_W0_REG (DR_REG_USB_DEVICE_BASE + 0x58) -/** USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; +#define USB_DEVICE_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58) +/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; * The value of dwDTERate set by software which is requested by GET_LINE_CODING * command. */ -#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_M (USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_S) -#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 /** USB_DEVICE_GET_LINE_CODE_W1_REG register * W1 of GET_LINE_CODING command. */ -#define USB_DEVICE_GET_LINE_CODE_W1_REG (DR_REG_USB_DEVICE_BASE + 0x5c) -/** USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; +#define USB_DEVICE_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c) +/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; * The value of bCharFormat set by software which is requested by GET_LINE_CODING * command. */ -#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_M (USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_V << USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_S) -#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_S 0 -/** USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0; +#define USB_SERIAL_JTAG_GET_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_M (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S) +#define USB_SERIAL_JTAG_GET_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_S 0 +/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0; * The value of bParityTpye set by software which is requested by GET_LINE_CODING * command. */ -#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_M (USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_S) -#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_S 8 -/** USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0; +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0; * The value of bDataBits set by software which is requested by GET_LINE_CODING * command. */ -#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_M (USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_S) -#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 /** USB_DEVICE_CONFIG_UPDATE_REG register * Configuration registers' value update */ -#define USB_DEVICE_CONFIG_UPDATE_REG (DR_REG_USB_DEVICE_BASE + 0x60) -/** USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; +#define USB_DEVICE_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60) +/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; * Write 1 to this register would update the value of configure registers from APB * clock domain to 48MHz clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_M (USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_V << USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_S) -#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_S 0 +#define USB_SERIAL_JTAG_CONFIG_UPDATE (BIT(0)) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_M (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U +#define USB_SERIAL_JTAG_CONFIG_UPDATE_S 0 /** USB_DEVICE_SER_AFIFO_CONFIG_REG register * Serial AFIFO configure register */ -#define USB_DEVICE_SER_AFIFO_CONFIG_REG (DR_REG_USB_DEVICE_BASE + 0x64) -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; +#define USB_DEVICE_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64) +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; * Write 1 to reset CDC_ACM IN async FIFO write clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S 0 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR (BIT(0)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0; * Write 1 to reset CDC_ACM IN async FIFO read clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0; * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S 2 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S 2 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0; * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; * CDC_ACM OUTPUT async FIFO empty signal in read clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S 4 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S 4 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0; * CDC_ACM OUT IN async FIFO empty signal in write clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL (BIT(5)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 /** USB_DEVICE_BUS_RESET_ST_REG register * USB Bus reset status register */ -#define USB_DEVICE_BUS_RESET_ST_REG (DR_REG_USB_DEVICE_BASE + 0x68) -/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; +#define USB_DEVICE_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68) +/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus * reset is released. */ -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_S) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST (BIT(0)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 /** USB_DEVICE_ECO_LOW_48_REG register * Reserved. */ -#define USB_DEVICE_ECO_LOW_48_REG (DR_REG_USB_DEVICE_BASE + 0x6c) -/** USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0; +#define USB_DEVICE_ECO_LOW_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c) +/** USB_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_S) -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_S 0 +#define USB_SERIAL_JTAG_RND_ECO_LOW_48 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_48_M (USB_SERIAL_JTAG_RND_ECO_LOW_48_V << USB_SERIAL_JTAG_RND_ECO_LOW_48_S) +#define USB_SERIAL_JTAG_RND_ECO_LOW_48_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_48_S 0 /** USB_DEVICE_ECO_HIGH_48_REG register * Reserved. */ -#define USB_DEVICE_ECO_HIGH_48_REG (DR_REG_USB_DEVICE_BASE + 0x70) -/** USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295; +#define USB_DEVICE_ECO_HIGH_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70) +/** USB_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_S) -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_S 0 +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_M (USB_SERIAL_JTAG_RND_ECO_HIGH_48_V << USB_SERIAL_JTAG_RND_ECO_HIGH_48_S) +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_S 0 /** USB_DEVICE_ECO_CELL_CTRL_48_REG register * Reserved. */ -#define USB_DEVICE_ECO_CELL_CTRL_48_REG (DR_REG_USB_DEVICE_BASE + 0x74) -/** USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0; +#define USB_DEVICE_ECO_CELL_CTRL_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x74) +/** USB_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48 (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_M (USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_V << USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_S) -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_S 0 -/** USB_DEVICE_SERIAL_JTAG_RDN_ENA_48 : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_RDN_RESULT_48 (BIT(0)) +#define USB_SERIAL_JTAG_RDN_RESULT_48_M (USB_SERIAL_JTAG_RDN_RESULT_48_V << USB_SERIAL_JTAG_RDN_RESULT_48_S) +#define USB_SERIAL_JTAG_RDN_RESULT_48_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_RESULT_48_S 0 +/** USB_SERIAL_JTAG_RDN_ENA_48 : R/W; bitpos: [1]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48 (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_M (USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_V << USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_S) -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_S 1 +#define USB_SERIAL_JTAG_RDN_ENA_48 (BIT(1)) +#define USB_SERIAL_JTAG_RDN_ENA_48_M (USB_SERIAL_JTAG_RDN_ENA_48_V << USB_SERIAL_JTAG_RDN_ENA_48_S) +#define USB_SERIAL_JTAG_RDN_ENA_48_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_ENA_48_S 1 /** USB_DEVICE_ECO_LOW_APB_REG register * Reserved. */ -#define USB_DEVICE_ECO_LOW_APB_REG (DR_REG_USB_DEVICE_BASE + 0x78) -/** USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0; +#define USB_DEVICE_ECO_LOW_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x78) +/** USB_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_S) -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_S 0 +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_M (USB_SERIAL_JTAG_RND_ECO_LOW_APB_V << USB_SERIAL_JTAG_RND_ECO_LOW_APB_S) +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_S 0 /** USB_DEVICE_ECO_HIGH_APB_REG register * Reserved. */ -#define USB_DEVICE_ECO_HIGH_APB_REG (DR_REG_USB_DEVICE_BASE + 0x7c) -/** USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295; +#define USB_DEVICE_ECO_HIGH_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x7c) +/** USB_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_S) -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_S 0 +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_M (USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V << USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S) +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S 0 /** USB_DEVICE_ECO_CELL_CTRL_APB_REG register * Reserved. */ -#define USB_DEVICE_ECO_CELL_CTRL_APB_REG (DR_REG_USB_DEVICE_BASE + 0x80) -/** USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0; +#define USB_DEVICE_ECO_CELL_CTRL_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) +/** USB_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_M (USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_V << USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_S) -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_S 0 -/** USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_RDN_RESULT_APB (BIT(0)) +#define USB_SERIAL_JTAG_RDN_RESULT_APB_M (USB_SERIAL_JTAG_RDN_RESULT_APB_V << USB_SERIAL_JTAG_RDN_RESULT_APB_S) +#define USB_SERIAL_JTAG_RDN_RESULT_APB_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_RESULT_APB_S 0 +/** USB_SERIAL_JTAG_RDN_ENA_APB : R/W; bitpos: [1]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_M (USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_V << USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_S) -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_S 1 +#define USB_SERIAL_JTAG_RDN_ENA_APB (BIT(1)) +#define USB_SERIAL_JTAG_RDN_ENA_APB_M (USB_SERIAL_JTAG_RDN_ENA_APB_V << USB_SERIAL_JTAG_RDN_ENA_APB_S) +#define USB_SERIAL_JTAG_RDN_ENA_APB_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_ENA_APB_S 1 /** USB_DEVICE_SRAM_CTRL_REG register * PPA SRAM Control Register */ -#define USB_DEVICE_SRAM_CTRL_REG (DR_REG_USB_DEVICE_BASE + 0x84) -/** USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; +#define USB_DEVICE_SRAM_CTRL_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x84) +/** USB_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; * Control signals */ -#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL 0x00003FFFU -#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_M (USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_V << USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_S) -#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_V 0x00003FFFU -#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_S 0 +#define USB_SERIAL_JTAG_MEM_AUX_CTRL 0x00003FFFU +#define USB_SERIAL_JTAG_MEM_AUX_CTRL_M (USB_SERIAL_JTAG_MEM_AUX_CTRL_V << USB_SERIAL_JTAG_MEM_AUX_CTRL_S) +#define USB_SERIAL_JTAG_MEM_AUX_CTRL_V 0x00003FFFU +#define USB_SERIAL_JTAG_MEM_AUX_CTRL_S 0 /** USB_DEVICE_DATE_REG register * Date register */ -#define USB_DEVICE_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x88) -/** USB_DEVICE_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752; +#define USB_DEVICE_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x88) +/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752; * register version. */ -#define USB_DEVICE_SERIAL_JTAG_DATE 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_DATE_M (USB_DEVICE_SERIAL_JTAG_DATE_V << USB_DEVICE_SERIAL_JTAG_DATE_S) -#define USB_DEVICE_SERIAL_JTAG_DATE_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_DATE_S 0 +#define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S) +#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_S 0 #ifdef __cplusplus } diff --git a/components/ulp/test_apps/.build-test-rules.yml b/components/ulp/test_apps/.build-test-rules.yml index 8045f63c2e02..a8eeee9bd7bb 100644 --- a/components/ulp/test_apps/.build-test-rules.yml +++ b/components/ulp/test_apps/.build-test-rules.yml @@ -5,10 +5,17 @@ components/ulp/test_apps/lp_core/lp_core_basic_tests: - if: SOC_LP_CORE_SUPPORTED != 1 - if: CONFIG_NAME == "xtal" and SOC_CLK_LP_FAST_SUPPORT_XTAL != 1 - if: CONFIG_NAME == "lp_vad" and SOC_LP_VAD_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14368 components/ulp/test_apps/lp_core/lp_core_hp_uart: disable: - if: SOC_LP_CORE_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14422 components/ulp/test_apps/ulp_fsm: enable: diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/README.md b/components/ulp/test_apps/lp_core/lp_core_basic_tests/README.md index 59db987a228b..86c1aea12b07 100644 --- a/components/ulp/test_apps/lp_core/lp_core_basic_tests/README.md +++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/README.md @@ -1,3 +1,3 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | -| ----------------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | +| ----------------- | -------- | -------- | diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/pytest_lp_core_basic.py b/components/ulp/test_apps/lp_core/lp_core_basic_tests/pytest_lp_core_basic.py index 1961db15ae8f..054bd960c9a9 100644 --- a/components/ulp/test_apps/lp_core/lp_core_basic_tests/pytest_lp_core_basic.py +++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/pytest_lp_core_basic.py @@ -7,6 +7,7 @@ @pytest.mark.generic +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14368') @pytest.mark.parametrize( 'config', [ @@ -20,6 +21,7 @@ def test_lp_core(dut: Dut) -> None: @pytest.mark.generic +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14368') @pytest.mark.parametrize( 'config', [ @@ -33,6 +35,7 @@ def test_lp_core_xtal(dut: Dut) -> None: @pytest.mark.lp_i2s +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14368') @pytest.mark.parametrize( 'config', [ @@ -61,6 +64,7 @@ def test_lp_core_multi_device(case_tester) -> None: # type: ignore @pytest.mark.generic_multi_device +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14422') @pytest.mark.parametrize( 'target', [ diff --git a/components/ulp/test_apps/lp_core/lp_core_hp_uart/pytest_lp_core_hp_uart.py b/components/ulp/test_apps/lp_core/lp_core_hp_uart/pytest_lp_core_hp_uart.py index 72e91019cc7f..c574112a26ce 100644 --- a/components/ulp/test_apps/lp_core/lp_core_hp_uart/pytest_lp_core_hp_uart.py +++ b/components/ulp/test_apps/lp_core/lp_core_hp_uart/pytest_lp_core_hp_uart.py @@ -7,6 +7,7 @@ @pytest.mark.generic @idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_hp_uart_print(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') dut.write('"lp-print can output to hp-uart"') @@ -17,6 +18,7 @@ def test_lp_core_hp_uart_print(dut: Dut) -> None: @pytest.mark.generic @idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_panic(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') dut.write('"LP-Core panic"') @@ -28,6 +30,7 @@ def test_lp_core_panic(dut: Dut) -> None: @pytest.mark.generic @idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_shared_mem(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') dut.write('"LP-Core Shared-mem"') @@ -46,6 +49,7 @@ def test_lp_core_shared_mem(dut: Dut) -> None: @pytest.mark.generic @idf_parametrize('target', ['esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_lp_rom(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') dut.write('"LP-Core LP-ROM"') diff --git a/components/usb/test_apps/.build-test-rules.yml b/components/usb/test_apps/.build-test-rules.yml index 947b7394a3ca..2e7b467dc4b6 100644 --- a/components/usb/test_apps/.build-test-rules.yml +++ b/components/usb/test_apps/.build-test-rules.yml @@ -4,9 +4,9 @@ components/usb/test_apps: enable: - if: SOC_USB_OTG_SUPPORTED == 1 disable_test: - - if: IDF_TARGET not in ["esp32s3", "esp32p4"] + - if: IDF_TARGET not in ["esp32s3"] temporary: true - reason: lack of runners with usb_host_flash_disk tag + reason: lack of runners with usb_host_flash_disk tag, p4 rev3 migration, IDF-14832 depends_components: - usb depends_filepatterns: diff --git a/components/usb/test_apps/hcd/pytest_usb_hcd.py b/components/usb/test_apps/hcd/pytest_usb_hcd.py index 66c2c416bb39..65389b14008e 100644 --- a/components/usb/test_apps/hcd/pytest_usb_hcd.py +++ b/components/usb/test_apps/hcd/pytest_usb_hcd.py @@ -5,7 +5,9 @@ from pytest_embedded_idf.utils import idf_parametrize -@pytest.mark.temp_skip_ci(targets=['esp32s2'], reason='lack of runners with usb_host_flash_disk tag') +@pytest.mark.temp_skip_ci( + targets=['esp32s2', 'esp32p4'], reason='lack of runners with usb_host_flash_disk tag, p4 rev3 migration, IDF-14832' +) @pytest.mark.usb_host_flash_disk @idf_parametrize( 'config,target', diff --git a/components/usb/test_apps/usb_host/pytest_usb_host.py b/components/usb/test_apps/usb_host/pytest_usb_host.py index a797423bb3f3..c9c7607c08b3 100644 --- a/components/usb/test_apps/usb_host/pytest_usb_host.py +++ b/components/usb/test_apps/usb_host/pytest_usb_host.py @@ -5,7 +5,9 @@ from pytest_embedded_idf.utils import idf_parametrize -@pytest.mark.temp_skip_ci(targets=['esp32s2'], reason='lack of runners with usb_host_flash_disk tag') +@pytest.mark.temp_skip_ci( + targets=['esp32s2', 'esp32p4'], reason='lack of runners with usb_host_flash_disk tag, p4 rev3 migration, IDF-14832' +) @pytest.mark.usb_host_flash_disk @idf_parametrize('target', ['esp32s2', 'esp32s3', 'esp32p4'], indirect=['target']) def test_usb_host(dut: Dut) -> None: diff --git a/docs/en/api-reference/peripherals/gptimer.rst b/docs/en/api-reference/peripherals/gptimer.rst index f82e6426e8bc..5140abe02be3 100644 --- a/docs/en/api-reference/peripherals/gptimer.rst +++ b/docs/en/api-reference/peripherals/gptimer.rst @@ -1,3 +1,4 @@ +=============================== General Purpose Timer (GPTimer) =============================== @@ -11,7 +12,7 @@ This document introduces the features of the General Purpose Timer (GPTimer) dri :depth: 2 Overview --------- +======== GPTimer is a dedicated driver for the {IDF_TARGET_NAME} [`Timer Group peripheral <{IDF_TARGET_TRM_EN_URL}#timg>`__]. This timer can select different clock sources and prescalers to meet the requirements of nanosecond-level resolution. Additionally, it has flexible timeout alarm functions and allows automatic updating of the count value at the alarm moment, achieving very precise timing cycles. @@ -24,7 +25,7 @@ Based on the **high resolution, high count range, and high response** capabiliti - etc. Quick Start ------------ +=========== This section provides a concise overview of how to use the GPTimer driver. Through practical examples, it demonstrates how to initialize and start a timer, configure alarm events, and register callback functions. The typical usage flow is as follows: @@ -54,7 +55,7 @@ This section provides a concise overview of how to use the GPTimer driver. Throu } Creating and Starting a Timer -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +----------------------------- First, we need to create a timer instance. The following code shows how to create a timer with a resolution of 1 MHz: @@ -104,7 +105,7 @@ The :cpp:func:`gptimer_start` and :cpp:func:`gptimer_stop` functions follow the However, note that when the timer is in the **intermediate state** of starting (the start has begun but not yet completed), if another thread calls the :cpp:func:`gptimer_start` or :cpp:func:`gptimer_stop` function, it will return the :c:macro:`ESP_ERR_INVALID_STATE` error to avoid triggering uncertain behavior. Setting and Getting the Count Value -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +----------------------------------- When a timer is newly created, its internal counter value defaults to zero. You can set other count values using the :cpp:func:`gptimer_set_raw_count` function. The maximum count value depends on the bit width of the hardware timer (usually no less than ``54 bits``). @@ -126,7 +127,7 @@ The :cpp:func:`gptimer_get_raw_count` function is used to get the current count double time = (double)count / resolution_hz; Triggering Periodic Alarm Events -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +-------------------------------- In addition to the timestamp function, the general-purpose timer also supports alarm functions. The following code shows how to set a periodic alarm that triggers once per second: @@ -194,7 +195,7 @@ The supported event callback functions for GPTimer are as follows: Be sure to register the callback function before calling :cpp:func:`gptimer_enable`, otherwise the timer event will not correctly trigger the interrupt service. Triggering One-Shot Alarm Events -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +-------------------------------- Some application scenarios only require triggering a one-shot alarm interrupt. The following code shows how to set a one-shot alarm that triggers after 1 second: @@ -242,17 +243,17 @@ Some application scenarios only require triggering a one-shot alarm interrupt. T Unlike periodic alarms, the above code disables the auto-reload function when configuring the alarm behavior. This means that after the alarm event occurs, the timer will not automatically reload to the preset count value but will continue counting until it overflows. If you want the timer to stop immediately after the alarm, you can call :cpp:func:`gptimer_stop` in the callback function. Resource Recycling -^^^^^^^^^^^^^^^^^^ +------------------ When the timer is no longer needed, you should call the :cpp:func:`gptimer_delete_timer` function to release software and hardware resources. Before deleting, ensure that the timer is already stopped. Advanced Features ------------------ +================= After understanding the basic usage, we can further explore more features of the GPTimer driver. Dynamic Alarm Value Update -^^^^^^^^^^^^^^^^^^^^^^^^^^ +-------------------------- The GPTimer driver supports dynamically updating the alarm value in the interrupt callback function by calling the :cpp:func:`gptimer_set_alarm_action` function, thereby implementing a monotonic software timer list. The following code shows how to reset the next alarm trigger time when the alarm event occurs: @@ -300,7 +301,7 @@ The GPTimer driver supports dynamically updating the alarm value in the interrup .. _gptimer-etm-event-and-task: GPTimer's ETM Events and Tasks - ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + ------------------------------ GPTimer can generate various events that can be connected to the :doc:`ETM ` module. The event types are listed in :cpp:type:`gptimer_etm_event_type_t`. Users can create an ``ETM event`` handle by calling :cpp:func:`gptimer_new_etm_event`. GPTimer also supports some tasks that can be triggered by other events and executed automatically. The task types are listed in :cpp:type:`gptimer_etm_task_type_t`. Users can create an ``ETM task`` handle by calling :cpp:func:`gptimer_new_etm_task`. @@ -308,7 +309,7 @@ The GPTimer driver supports dynamically updating the alarm value in the interrup For how to connect the timer events and tasks to the ETM channel, please refer to the :doc:`ETM ` documentation. Power Management -^^^^^^^^^^^^^^^^ +---------------- When power management :ref:`CONFIG_PM_ENABLE` is enabled, the system may adjust or disable the clock source before entering sleep mode, causing the GPTimer to lose accuracy. @@ -319,7 +320,7 @@ To prevent this, the GPTimer driver creates a power management lock internally. Besides disabling the clock source, the system can also power down the GPTimer before entering sleep mode to further reduce power consumption. To achieve this, set :cpp:member:`gptimer_config_t::allow_pd` to ``true``. Before the system enters sleep mode, the GPTimer register context will be backed up to memory and restored after the system wakes up. Note that enabling this option reduces power consumption but increases memory usage. Therefore, you need to balance power consumption and memory usage when using this feature. Thread Safety -^^^^^^^^^^^^^ +------------- The driver uses critical sections to ensure atomic operations on registers. Key members in the driver handle are also protected by critical sections. The driver's internal state machine uses atomic instructions to ensure thread safety, with state checks preventing certain invalid concurrent operations (e.g., conflicts between `start` and `stop`). Therefore, GPTimer driver APIs can be used in a multi-threaded environment without extra locking. @@ -335,7 +336,7 @@ The following functions can also be used in an interrupt context: - :cpp:func:`gptimer_set_alarm_action` Cache Safety -^^^^^^^^^^^^ +------------ When the file system performs Flash read/write operations, the system temporarily disables the Cache function to avoid errors when loading instructions and data from Flash. This causes the GPTimer interrupt handler to be unresponsive during this period, preventing the user callback function from executing in time. If you want the interrupt handler to run normally when the Cache is disabled, you can enable the :ref:`CONFIG_GPTIMER_ISR_CACHE_SAFE` option. @@ -344,7 +345,7 @@ When the file system performs Flash read/write operations, the system temporaril Note that when this option is enabled, all interrupt callback functions and their context data **must be placed in internal storage**. This is because the system cannot load data and instructions from Flash when the Cache is disabled. Performance -^^^^^^^^^^^ +----------- To improve the real-time responsiveness of interrupt handling, the GPTimer driver provides the :ref:`CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM` option. Once enabled, the interrupt handler is placed in internal RAM, reducing delays caused by potential cache misses when loading instructions from Flash. @@ -355,12 +356,12 @@ To improve the real-time responsiveness of interrupt handling, the GPTimer drive As mentioned above, the GPTimer driver allows some functions to be called in an interrupt context. By enabling the :ref:`CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM` option, these functions can also be placed in IRAM, which helps avoid performance loss caused by cache misses and allows them to be used when the Cache is disabled. Other Kconfig Options -^^^^^^^^^^^^^^^^^^^^^ +--------------------- - The :ref:`CONFIG_GPTIMER_ENABLE_DEBUG_LOG` option forces the GPTimer driver to enable all debug logs, regardless of the global log level settings. Enabling this option helps developers obtain more detailed log information during debugging, making it easier to locate and solve problems. Resource Consumption -^^^^^^^^^^^^^^^^^^^^ +-------------------- Use the :doc:`/api-guides/tools/idf-size` tool to check the code and data consumption of the GPTimer driver. The following are the test conditions (using ESP32-C2 as an example): @@ -386,7 +387,7 @@ Use the :doc:`/api-guides/tools/idf-size` tool to check the code and data consum Additionally, each GPTimer handle dynamically allocates about ``100`` bytes of memory from the heap. If the :cpp:member:`gptimer_config_t::flags::allow_pd` option is enabled, each timer will also consume approximately ``30`` extra bytes of memory during sleep to store the register context. Application Examples --------------------- +==================== .. list:: @@ -395,12 +396,26 @@ Application Examples :SOC_TIMER_SUPPORT_ETM: - :example:`peripherals/timer_group/gptimer_capture_hc_sr04` demonstrates how to use the general-purpose timer and Event Task Matrix (ETM) to accurately capture timestamps of ultrasonic sensor events and convert them into distance information. API Reference -------------- +============= + +GPTimer Driver APIs +------------------- .. include-build-file:: inc/gptimer.inc + +GPTimer Driver Types +-------------------- + .. include-build-file:: inc/gptimer_types.inc + +GPTimer HAL Types +----------------- + .. include-build-file:: inc/timer_types.inc +GPTimer ETM APIs +---------------- + .. only:: SOC_TIMER_SUPPORT_ETM .. include-build-file:: inc/gptimer_etm.inc diff --git a/docs/en/api-reference/peripherals/twai.rst b/docs/en/api-reference/peripherals/twai.rst index 6d64c6c0304f..59e03f4f5f3d 100644 --- a/docs/en/api-reference/peripherals/twai.rst +++ b/docs/en/api-reference/peripherals/twai.rst @@ -1,3 +1,4 @@ +==================================== Two-Wire Automotive Interface (TWAI) ==================================== @@ -10,7 +11,7 @@ This document introduces the features of the Two-Wire Automotive Interface (TWAI :depth: 2 Overview --------- +======== TWAI is a highly reliable, multi-master, real-time, serial asynchronous communication protocol designed for automotive and industrial applications. It is compatible with the frame structure defined in the ISO 11898-1 standard and supports both standard frames with 11-bit identifiers and extended frames with 29-bit identifiers. The protocol supports message prioritization with lossless arbitration, automatic retransmission, and fault confinement mechanisms. The {IDF_TARGET_NAME} includes {IDF_TARGET_CONFIG_SOC_TWAI_CONTROLLER_NUM} TWAI controllers, allowing for the creation of {IDF_TARGET_CONFIG_SOC_TWAI_CONTROLLER_NUM} driver instances. @@ -30,7 +31,7 @@ Thanks to its hardware-based fault tolerance and multi-master architecture, the - Acting as a bridging node alongside other communication protocols Getting Started ---------------- +=============== This section provides a quick overview of how to use the TWAI driver. Through simple examples, it demonstrates how to create a TWAI node instance, transmit and receive messages on the bus, and safely stop and uninstall the driver. The general usage flow is as follows: @@ -38,7 +39,7 @@ This section provides a quick overview of how to use the TWAI driver. Through si :align: center Hardware Connection -^^^^^^^^^^^^^^^^^^^ +------------------- The {IDF_TARGET_NAME} does not integrate an internal TWAI transceiver. Therefore, an external transceiver is required to connect to a TWAI bus. The model of the external transceiver depends on the physical layer standard used in your specific application. For example, a TJA105x transceiver can be used to comply with the ISO 11898-2 standard. @@ -53,7 +54,7 @@ Specifically: - CLK_OUT (optional): Outputs the time quantum clock of the controller, which is a divided version of the source clock. Creating and Starting a TWAI Node -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +--------------------------------- First, we need to create a TWAI instance. The following code demonstrates how to create a TWAI node with a baud rate of 200 kHz: @@ -95,7 +96,7 @@ The :cpp:func:`twai_node_enable` function starts the TWAI controller. Once enabl The corresponding function, :cpp:func:`twai_node_disable`, immediately stops the node and disconnects it from the bus. Any ongoing transmissions will be aborted. When the node is re-enabled later, if there are pending transmissions in the queue, the driver will immediately initiate a new transmission attempt. Transmitting Messages -^^^^^^^^^^^^^^^^^^^^^ +--------------------- TWAI messages come in various types, which are specified by their headers. A typical data frame consists primarily of a header and data payload, with a structure similar to the following: @@ -130,7 +131,7 @@ The :cpp:type:`twai_frame_t` message structure also includes other configuration - :cpp:member:`twai_frame_t::header::esi`: For received frames, indicates the error state of the transmitting node. Receiving Messages -^^^^^^^^^^^^^^^^^^ +------------------ Receiving messages must be done within a receive event callback. Therefore, to receive messages, you need to register a receive event callback via :cpp:member:`twai_event_callbacks_t::on_rx_done` before starting the controller. This enables the controller to deliver received messages via the callback when events occur. The following code snippets demonstrate how to register the receive event callback and how to handle message reception inside the callback: @@ -163,12 +164,12 @@ Receiving messages inside the callback: Similarly, since the driver uses pointers for message passing, you must configure the pointer :cpp:member:`twai_frame_t::buffer` and its memory length :cpp:member:`twai_frame_t::buffer_len` before receiving. Stopping and Deleting the Node -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +------------------------------ When the TWAI node is no longer needed, you should call :cpp:func:`twai_node_delete` to release software and hardware resources. Make sure the TWAI controller is stopped before deleting the node. Advanced Features ------------------ +================= After understanding the basic usage, you can further explore more advanced capabilities of the TWAI driver. The driver supports more detailed controller configuration and error feedback features. The complete driver feature diagram is shown below: @@ -176,7 +177,7 @@ After understanding the basic usage, you can further explore more advanced capab :align: center Transmit from ISR -^^^^^^^^^^^^^^^^^ +----------------- The TWAI driver supports transmitting messages from an Interrupt Service Routine (ISR). This is particularly useful for applications requiring low-latency responses or periodic transmissions triggered by hardware timers. For example, you can trigger a new transmission from within the ``on_tx_done`` callback, which is executed in an ISR context. @@ -202,7 +203,7 @@ The TWAI driver supports transmitting messages from an Interrupt Service Routine When calling :cpp:func:`twai_node_transmit` from an ISR, the ``timeout`` parameter is ignored, and the function will not block. If the transmit queue is full, the function will return immediately with an error. It is the application's responsibility to handle cases where the queue is full. Bit Timing Customization -^^^^^^^^^^^^^^^^^^^^^^^^ +------------------------ Unlike other asynchronous communication protocols, the TWAI controller performs counting and sampling within one bit time in units of **Time Quanta (Tq)**. The number of time quanta per bit determines the final baud rate and the sample point position. When signal quality is poor, you can manually fine-tune these timing segments to meet specific requirements. The time quanta within a bit time are divided into different segments, as illustrated below: @@ -247,10 +248,10 @@ When manually configuring these timing segments, it is important to pay attentio Different combinations of ``brp``, ``prop_seg``, ``tseg_1``, ``tseg_2``, and ``sjw`` can achieve the same baud rate. Users should consider factors such as **propagation delay, node processing time, and phase errors**, and adjust the timing parameters based on the physical characteristics of the bus. Filter Configuration -^^^^^^^^^^^^^^^^^^^^^ +--------------------- Mask Filters -"""""""""""" +^^^^^^^^^^^^ The TWAI controller hardware can filter messages based on their ID to reduce software and hardware overhead, thereby improving node efficiency. Nodes that filter out certain messages will **not receive those messages, but will still send acknowledgments (ACKs)**. @@ -279,7 +280,7 @@ The following code demonstrates how to calculate the MASK and configure a filter .. only:: not SOC_TWAI_SUPPORT_FD Dual Filter Mode - """""""""""""""" + ^^^^^^^^^^^^^^^^ {IDF_TARGET_NAME} supports dual filter mode, which allows the hardware to be configured as two parallel independent 16-bit mask filters. By enabling this, more IDs can be received. Note that using dual filter mode to filter 29-bit extended IDs, each filter can only filter the upper 16 bits of the ID, while the remaining 13 bits are not filtered. The following code demonstrates how to configure dual filter mode using the function :cpp:func:`twai_make_dual_filter`: @@ -293,7 +294,7 @@ The following code demonstrates how to calculate the MASK and configure a filter .. only:: SOC_TWAI_SUPPORT_FD Range Filter - """""""""""" + ^^^^^^^^^^^^ {IDF_TARGET_NAME} also includes 1 range filter, which exists alongside the mask filters. You can configure the desired ID reception range directly using the function :cpp:func:`twai_node_config_range_filter`. The details are as follows: @@ -301,7 +302,7 @@ The following code demonstrates how to calculate the MASK and configure a filter - Configuring an invalid range means no messages will be received. Bus Errors and Recovery -^^^^^^^^^^^^^^^^^^^^^^^ +----------------------- The TWAI controller can detect errors caused by bus interference or corrupted frames that do not conform to the frame format. It implements a fault isolation mechanism using transmit and receive error counters (TEC and REC). The values of these counters determine the node's error state: Error Active, Error Warning, Error Passive, and Bus Off. This mechanism ensures that nodes with persistent errors eventually disconnect themselves from the bus. @@ -317,12 +318,12 @@ When the node’s error state changes, the :cpp:member:`twai_event_callbacks_t:: When recovery completes, the :cpp:member:`twai_event_callbacks_t::on_state_change` callback will be triggered again, the node changes its state from :cpp:enumerator:`TWAI_ERROR_BUS_OFF` to :cpp:enumerator:`TWAI_ERROR_ACTIVE`. A recovered node can immediately resume transmissions; if there are pending tasks in the transmit queue, the driver will start transmitting them right away. Power Management -^^^^^^^^^^^^^^^^ +---------------- When power management is enabled via :ref:`CONFIG_PM_ENABLE`, the system may adjust or disable clock sources before entering sleep mode, which could cause TWAI to malfunction. To prevent this, the driver manages a power management lock internally. This lock is acquired when calling :cpp:func:`twai_node_enable`, ensuring the system does not enter sleep mode and TWAI remains functional. To allow the system to enter a low-power state, call :cpp:func:`twai_node_disable` to release the lock. During sleep, the TWAI controller will also stop functioning. Cache Safety -^^^^^^^^^^^^ +------------ During Flash write operations, the system temporarily disables cache to prevent instruction and data fetch errors from Flash. This can cause interrupt handlers stored in Flash to become unresponsive. If you want interrupt routines to remain operational during cache-disabled periods, enable the :ref:`CONFIG_TWAI_ISR_CACHE_SAFE` option. @@ -331,12 +332,12 @@ During Flash write operations, the system temporarily disables cache to prevent When this option is enabled, **all interrupt callback functions and their context data must reside in internal memory**, because the system cannot fetch instructions or data from Flash while the cache is disabled. Thread Safety -^^^^^^^^^^^^^ +------------- The driver guarantees thread safety for all public TWAI APIs. You can safely call these APIs from different RTOS tasks without requiring additional synchronization or locking mechanisms. Performance -^^^^^^^^^^^ +----------- To improve the real-time performance of interrupt handling, the driver provides the :ref:`CONFIG_TWAI_ISR_IN_IRAM` option. When enabled, the TWAI ISR (Interrupt Service Routine) and receive operations are placed in internal RAM, reducing latency caused by instruction fetching from Flash. @@ -347,7 +348,7 @@ For applications that require high-performance transmit operations, the driver p However, user-defined callback functions and context data invoked by the ISR may still reside in Flash. To fully eliminate Flash latency, users must place these functions and data into internal RAM using macros such as :c:macro:`IRAM_ATTR` for functions and :c:macro:`DRAM_ATTR` for data. Resource Usage -^^^^^^^^^^^^^^ +-------------- You can inspect the Flash and memory usage of the TWAI driver using the :doc:`/api-guides/tools/idf-size` tool. Below are the test conditions (based on the ESP32-C6 as an example): @@ -385,12 +386,12 @@ Resource Usage with :ref:`CONFIG_TWAI_ISR_IN_IRAM` Enabled: Additionally, each TWAI handle dynamically allocates approximately ``168`` + 4 * :cpp:member:`twai_onchip_node_config_t::tx_queue_depth` bytes of memory from the heap. Other Kconfig Options -^^^^^^^^^^^^^^^^^^^^^ +--------------------- - :ref:`CONFIG_TWAI_ENABLE_DEBUG_LOG`: This option forces all debug logs of the TWAI driver to be enabled regardless of the global log level settings. Enabling this can help developers obtain more detailed log information during debugging, making it easier to locate and resolve issues. Application Examples --------------------- +==================== .. list:: @@ -398,9 +399,24 @@ Application Examples - :example:`peripherals/twai/twai_network` using 2 nodes with different roles: transmitting and listening, demonstrates how to use the driver for single and bulk data transmission, as well as configure filters to receive these data. API Reference -------------- +============= + +On-Chip TWAI APIs +----------------- .. include-build-file:: inc/esp_twai_onchip.inc + +TWAI Driver APIs +---------------- + .. include-build-file:: inc/esp_twai.inc + +TWAI Driver Types +----------------- + .. include-build-file:: inc/esp_twai_types.inc + +TWAI HAL Types +-------------- + .. include-build-file:: inc/twai_types.inc diff --git a/docs/zh_CN/api-reference/peripherals/gptimer.rst b/docs/zh_CN/api-reference/peripherals/gptimer.rst index 217340ec200f..0a75387258c3 100644 --- a/docs/zh_CN/api-reference/peripherals/gptimer.rst +++ b/docs/zh_CN/api-reference/peripherals/gptimer.rst @@ -1,3 +1,4 @@ +======================== 通用硬件定时器 (GPTimer) ======================== @@ -11,7 +12,7 @@ :depth: 2 概述 ----- +==== 通用定时器是 {IDF_TARGET_NAME} [`定时器组外设 <{IDF_TARGET_TRM_CN_URL}#timg>`__]的专用驱动程序。该定时器可以选择不同的时钟源和分频系数，能满足纳秒级的分辨率要求。此外，它还具有灵活的超时报警功能，并允许在报警时刻自动更新计数值，从而实现非常精准的定时周期。 @@ -24,7 +25,7 @@ - 其他 快速入门 --------- +======== 本节将带你快速了解如何使用 GPTimer 驱动。通过简单的示例，展示如何创建一个定时器并启动它，如何设置警报事件，以及如何注册事件回调函数。一般的使用流程如下： @@ -54,7 +55,7 @@ } 创建和启动定时器 -^^^^^^^^^^^^^^^^ +---------------- 首先，我们需要创建一个定时器实例。以下代码展示了如何创建一个分辨率为 1 MHz 的定时器： @@ -104,7 +105,7 @@ 但是请注意，当定时器处于启动的 **中间状态** 时（启动开始了，但还没有启动完毕），此时如果另外一个线程调用 :cpp:func:`gptimer_start` 或者 :cpp:func:`gptimer_stop` 函数，则会返回 :c:macro:`ESP_ERR_INVALID_STATE` 错误，避免触发不确定的行为。 设置和获取计数值 -^^^^^^^^^^^^^^^^ +---------------- 一个刚创建的定时器，其内部计数器值默认为 0。你可以通过 :cpp:func:`gptimer_set_raw_count` 设置其他的计数值。最大计数值取决于硬件定时器的位宽（通常不少于 ``54 bit``）。 @@ -126,7 +127,7 @@ double time = (double)count / resolution_hz; 触发周期性警报事件 -^^^^^^^^^^^^^^^^^^ +------------------ 除了时间戳功能以外，通用定时器还支持警报功能。以下代码展示了如何设置一个周期性警报，每秒触发一次： @@ -194,7 +195,7 @@ GPTimer 支持的事件回调函数有下面这些： 请务必在调用 :cpp:func:`gptimer_enable` 之前注册回调函数，否则定时器事件将无法正确触发中断服务。 触发一次性警报事件 -^^^^^^^^^^^^^^^^^^ +------------------ 还有一些应用场景只需要触发一次警报中断，以下代码展示了如何设置一个一次性警报，在 1 秒后触发： @@ -242,17 +243,17 @@ GPTimer 支持的事件回调函数有下面这些： 与周期性警报不同，上述代码在配置警报行为时关闭了自动重载功能。这意味着，当警报事件发生后，定时器将不会自动重载到预设的计数值，而是继续计数直到溢出。如果希望定时器在警报后立即停止，可以在回调函数中调用 :cpp:func:`gptimer_stop`。 资源回收 -^^^^^^^^ +-------- 当不再需要使用定时器时，应该调用 :cpp:func:`gptimer_delete_timer` 函数来释放软硬件资源。删除前请确保定时器已经处于停止状态。 进阶功能 --------- +======== 在了解了基本用法后，我们可以进一步探索 GPTimer 驱动的更多玩法。 动态更新警报值 -^^^^^^^^^^^^^^ +-------------- GPTimer 驱动支持在中断回调函数中调用 :cpp:func:`gptimer_set_alarm_action` 函数来动态更新警报值，从而实现单调型的软件定时器链表。以下代码展示了如何在警报事件发生时，重新设置下一次警报的触发时间： @@ -300,7 +301,7 @@ GPTimer 驱动支持在中断回调函数中调用 :cpp:func:`gptimer_set_alarm_ .. _gptimer-etm-event-and-task: GPTimer 的 ETM 事件与任务 - ^^^^^^^^^^^^^^^^^^^^^^^^^ + ------------------------- GPTimer 可以生成多种事件，这些事件可以连接到 :doc:`ETM ` 模块。事件类型列在 :cpp:type:`gptimer_etm_event_type_t` 中。用户可以通过调用 :cpp:func:`gptimer_new_etm_event` 来创建 ``ETM event`` 句柄。 GPTimer 还支持一些可由其他事件触发并自动执行的任务。任务类型列在 :cpp:type:`gptimer_etm_task_type_t` 中。用户可以通过调用 :cpp:func:`gptimer_new_etm_task` 来创建 ``ETM task`` 句柄。 @@ -308,7 +309,7 @@ GPTimer 驱动支持在中断回调函数中调用 :cpp:func:`gptimer_set_alarm_ 有关如何将定时器事件和任务连接到 ETM 通道，请参阅 :doc:`ETM ` 文档。 关于低功耗 -^^^^^^^^^^ +---------- 当启用电源管理 :ref:`CONFIG_PM_ENABLE` 时，系统在进入睡眠模式前可能会调整或禁用时钟源，从而导致 GPTimer 的计时出错。 @@ -319,7 +320,7 @@ GPTimer 驱动支持在中断回调函数中调用 :cpp:func:`gptimer_set_alarm_ 除了关闭时钟源外，系统在进入睡眠模式时还可以关闭 GPTimer 的电源以进一步降低功耗。要实现这一点，需要将 :cpp:member:`gptimer_config_t::allow_pd` 设置为 ``true``。在系统进入睡眠模式之前， GPTimer 的寄存器上下文会被备份到内存中，并在系统唤醒后恢复。请注意，启用此选项虽然可以降低功耗，但会增加内存的使用量。因此，在使用该功能时需要在功耗和内存消耗之间进行权衡。 关于线程安全 -^^^^^^^^^^^^ +------------ 驱动使用了临界区保证了对寄存器的原子操作。句柄内部的关键成员也受临界区保护。驱动内部的状态机使用了原子指令保证了线程安全，通过状态检查还能进一步防止一些不合法的并发操作（例如 `start` 和 `stop` 冲突）。因此， GPTimer 驱动的 API 可以在多线程环境下使用，无需自行加锁。 @@ -335,7 +336,7 @@ GPTimer 驱动支持在中断回调函数中调用 :cpp:func:`gptimer_set_alarm_ - :cpp:func:`gptimer_set_alarm_action` 关于 Cache 安全 -^^^^^^^^^^^^^^^ +--------------- 在文件系统进行 Flash 读写操作时，为了避免 Cache 从 Flash 加载指令和数据时出现错误，系统会暂时禁用 Cache 功能。这会导致 GPTimer 的中断处理程序在此期间无法响应，从而使用户的回调函数无法及时执行。如果希望在 Cache 被禁用期间，中断处理程序仍能正常运行，可以启用 :ref:`CONFIG_GPTIMER_ISR_CACHE_SAFE` 选项。 @@ -344,7 +345,7 @@ GPTimer 驱动支持在中断回调函数中调用 :cpp:func:`gptimer_set_alarm_ 请注意，在启用该选项后，所有的中断回调函数及其上下文数据 **必须存放在内部存储空间** 中。因为在 Cache 被禁用时，系统无法从 Flash 中加载数据和指令。 关于性能 -^^^^^^^^ +-------- 为了提升中断处理的实时响应能力， GPTimer 驱动提供了 :ref:`CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM` 选项。启用该选项后，中断处理程序将被放置在内部 RAM 中运行，从而减少了从 Flash 加载指令时可能出现的缓存丢失带来的延迟。 @@ -355,12 +356,12 @@ GPTimer 驱动支持在中断回调函数中调用 :cpp:func:`gptimer_set_alarm_ 前文还提到， GPTimer 驱动允许部分函数在中断上下文中使用。:ref:`CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM` 选项可以将这些函数放入 IRAM 中，一来，可以避免缓存缺失带来的性能损失，二来，这些函数在 Cache 关闭期间也能使用。 其他 Kconfig 选项 -^^^^^^^^^^^^^^^^^ +----------------- - :ref:`CONFIG_GPTIMER_ENABLE_DEBUG_LOG` 选项允许强制启用 GPTimer 驱动的所有调试日志，无论全局日志级别设置如何。启用此选项可以帮助开发人员在调试过程中获取更详细的日志信息，从而更容易定位和解决问题。 关于资源消耗 -^^^^^^^^^^^^ +------------ 使用 :doc:`/api-guides/tools/idf-size` 工具可以查看 GPTimer 驱动的代码和数据消耗。以下是测试前提条件（以 ESP32-C2 为例）： @@ -386,7 +387,7 @@ GPTimer 驱动支持在中断回调函数中调用 :cpp:func:`gptimer_set_alarm_ 此外，每一个 GPTimer 句柄会从 heap 中动态申请约 ``100`` 字节的内存。如果还使能了 :cpp:member:`gptimer_config_t::flags::allow_pd` 选项，那么每个定时器还会在睡眠期间额外消耗约 ``30`` 字节的内存用于保存寄存器上下文。 应用示例 --------- +======== .. list:: @@ -395,12 +396,26 @@ GPTimer 驱动支持在中断回调函数中调用 :cpp:func:`gptimer_set_alarm_ :SOC_TIMER_SUPPORT_ETM: - :example:`peripherals/timer_group/gptimer_capture_hc_sr04` 展示了如何使用通用定时器和事件任务矩阵(ETM)来精确捕获超声波传感器事件的时间戳，并据此换算成距离信息。 API 参考 --------- +======== + +GPTimer 驱动 API +----------------- .. include-build-file:: inc/gptimer.inc + +GPTimer 驱动类型 +---------------- + .. include-build-file:: inc/gptimer_types.inc + +GPTimer HAL 类型 +---------------- + .. include-build-file:: inc/timer_types.inc .. only:: SOC_TIMER_SUPPORT_ETM + GPTimer ETM API + --------------- + .. include-build-file:: inc/gptimer_etm.inc diff --git a/docs/zh_CN/api-reference/peripherals/isp.rst b/docs/zh_CN/api-reference/peripherals/isp.rst index 09cbdbbc7805..4b7e441f8a21 100644 --- a/docs/zh_CN/api-reference/peripherals/isp.rst +++ b/docs/zh_CN/api-reference/peripherals/isp.rst @@ -389,7 +389,7 @@ ISP AE 控制器 使用单次 AE 数据统计时，需要禁用连续 AE 模式，否则结果可能会被环境检测器覆盖。完成单次操作后，请重新启动连续模式。 -除了上述单次统计 API 外，ISP AE 驱动程序还可以连续获取 AE 统计信息。调用 :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_statistics_done` 可启动连续统计，调用 :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_change` 可停止统计。 +除了上述单次统计 API 外，ISP AE 驱动程序还可以连续获取 AE 统计信息。调用 :cpp:func:`esp_isp_ae_controller_start_continuous_statistics` 可启动连续统计，调用 :cpp:func:`esp_isp_ae_controller_stop_continuous_statistics` 可停止统计。 若想启用连续统计，需要先注册回调函数 :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_statistics_done` 或 :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_change` 以获取统计数据。有关如何注册回调函数，请参见 :ref:`isp-callback`。 diff --git a/docs/zh_CN/api-reference/peripherals/twai.rst b/docs/zh_CN/api-reference/peripherals/twai.rst index a39aa3a85baa..e01c2300639e 100644 --- a/docs/zh_CN/api-reference/peripherals/twai.rst +++ b/docs/zh_CN/api-reference/peripherals/twai.rst @@ -1,3 +1,4 @@ +=================== 双线汽车接口 (TWAI) =================== @@ -10,7 +11,7 @@ :depth: 2 概述 ----- +==== TWAI 是一种适用于汽车和工业应用的高可靠性的多主机实时串行异步通信协议。它兼容 ISO11898-1 标准定义的帧结构，可以支持 11 位 ID 的标准帧和 29 位 ID 的扩展帧。支持报文优先级和无损仲裁，支持自动重传和故障自动隔离机制。{IDF_TARGET_NAME} 包含 {IDF_TARGET_CONFIG_SOC_TWAI_CONTROLLER_NUM} 个 TWAI 控制器，可以创建 {IDF_TARGET_CONFIG_SOC_TWAI_CONTROLLER_NUM} 个驱动实例。 @@ -30,7 +31,7 @@ TWAI 是一种适用于汽车和工业应用的高可靠性的多主机实时串 - 配合其他通信协议作为桥接设备 快速入门 --------- +======== 本节将带你快速了解如何使用 TWAI 驱动。通过简单的示例，展示如何创建一个 TWAI 节点实例，如何发送和接收总线上的报文，以及如何安全停止和删除驱动。一般的使用流程如下： @@ -38,7 +39,7 @@ TWAI 是一种适用于汽车和工业应用的高可靠性的多主机实时串 :align: center 硬件连接 -^^^^^^^^ +-------- {IDF_TARGET_NAME} 内部没有集成 TWAI 收发器。因此你需要外接一个收发器才能加入 TWAI 总线。外部收发器的型号取决于具体应用遵循的物理层规范。例如，使用 TJA105x 收发器以兼容 ISO 11898-2 标准。 @@ -53,7 +54,7 @@ TWAI 是一种适用于汽车和工业应用的高可靠性的多主机实时串 - CLK_OUT （可选），输出控制器时间量子时钟，即源时钟的分频时钟。 创建和启动 TWAI 节点 -^^^^^^^^^^^^^^^^^^^^^ +--------------------- 首先，我们需要创建一个 TWAI 实例。以下代码展示了如何创建一个波特率为 200kHz 的 TWAI 节点： @@ -95,7 +96,7 @@ TWAI 是一种适用于汽车和工业应用的高可靠性的多主机实时串 与之对应的函数是 :cpp:func:`twai_node_disable`，该函数将立即停止节点工作并与总线断开，正在进行的传输将被中止。当下次重新启动时，如果发送队列中有未完成的任务，驱动将立即发起新的传输。 发送报文 -^^^^^^^^ +-------- TWAI 报文有多种类型，由报头指定。一个典型的数据帧报文主要包括报头和数据，大概结构如下： @@ -130,7 +131,7 @@ TWAI 报文有多种类型，由报头指定。一个典型的数据帧报文主 - :cpp:member:`twai_frame_t::header::esi` 对于收到的报文，指示发送节点的错误状态。 接收报文 -^^^^^^^^ +-------- 接收报文必须在接收事件回调中进行，因此，要接收报文需要在控制器启动前注册接收事件回调 :cpp:member:`twai_event_callbacks_t::on_rx_done` ，从而在事件发生时接收报文。以下代码分别展示了如何注册接收事件回调，以及如何在回调中接收报文： @@ -163,12 +164,12 @@ TWAI 报文有多种类型，由报头指定。一个典型的数据帧报文主 同样，驱动使用指针进行传递，因此需要在接收前配置 :cpp:member:`twai_frame_t::buffer` 的指针及其内存长度 :cpp:member:`twai_frame_t::buffer_len` 停止和删除节点 -^^^^^^^^^^^^^^ +-------------- 当不再需要使用 TWAI 时，应该调用 :cpp:func:`twai_node_delete` 函数来释放软硬件资源。删除前请确保 TWAI 已经处于停止状态。 进阶功能 --------- +======== 在了解了基本用法后，我们可以进一步探索 TWAI 驱动的更多玩法。驱动支持更详细的控制器配置和错误反馈功能，完整的驱动功能图如下： @@ -176,7 +177,7 @@ TWAI 报文有多种类型，由报头指定。一个典型的数据帧报文主 :align: center 在 ISR 中发送 -^^^^^^^^^^^^^ +------------- TWAI 驱动支持在中断服务程序 (ISR) 中发送报文。这对于需要低延迟响应或由硬件定时器触发的周期性传输的应用特别有用。例如，你可以在 ``on_tx_done`` 回调中触发一次新的传输，该回调在 ISR 上下文中执行。 @@ -202,7 +203,7 @@ TWAI 驱动支持在中断服务程序 (ISR) 中发送报文。这对于需要 在 ISR 中调用 :cpp:func:`twai_node_transmit` 时，``timeout`` 参数将被忽略，函数不会阻塞。如果发送队列已满，函数将立即返回错误。应用程序需要自行处理队列已满的情况。 位时序自定义 -^^^^^^^^^^^^^ +------------- 和其他异步通信不同的是，TWAI 控制器在一个位时间里实际上在进行以 **时间量子（Tq）** 为单位的计数 / 采样，一个位里的时间量子的数量决定了最终的波特率以及采样点位置。在信号质量较低时时，可以手动更加精准的配置这些时序段以满足要求。位时间里的时间量子分为不同的段，如图所示： @@ -247,10 +248,10 @@ TWAI 驱动支持在中断服务程序 (ISR) 中发送报文。这对于需要 ``brp``、``prop_seg``、``tseg_1``、``tseg_2`` 和 ``sjw`` 的不同组合可以实现相同波特率。用户应考虑 **传播延迟、节点信息处理时间和相位误差** 等因素，根据总线的物理特性进行调整。 过滤器配置 -^^^^^^^^^^ +---------- 掩码过滤器 -"""""""""" +^^^^^^^^^^ TWAI 控制器硬件可以根据 ID 对报文进行过滤，从而减少软硬件开销使节点更加高效。过滤掉报文的节点 **不会接收到该报文，但仍会应答**。 @@ -279,7 +280,7 @@ TWAI 控制器硬件可以根据 ID 对报文进行过滤，从而减少软硬 .. only:: not SOC_TWAI_SUPPORT_FD 双过滤器模式 - """""""""""" + ^^^^^^^^^^^^ {IDF_TARGET_NAME} 支持双过滤器模式，可将硬件配置为并列的两个独立的 16 位掩码过滤器，支持接收更多 ID。但注意，使用双过滤器模式过滤 29 位扩展ID时，每个过滤器只能过滤其ID的高 16 位，剩余13位不做过滤。以下代码展示了如何借助 :cpp:func:`twai_make_dual_filter` 配置双过滤器模式。 @@ -293,7 +294,7 @@ TWAI 控制器硬件可以根据 ID 对报文进行过滤，从而减少软硬 .. only:: SOC_TWAI_SUPPORT_FD 范围过滤器 - """""""""" + ^^^^^^^^^^ {IDF_TARGET_NAME} 还包含 1 个范围过滤器，与掩码过滤器属并列关系。可以通过 :cpp:func:`twai_node_config_range_filter` 函数直接配置希望接收的 ID 范围。其中： @@ -301,7 +302,7 @@ TWAI 控制器硬件可以根据 ID 对报文进行过滤，从而减少软硬 - 配置为无效区间则表示不接收任何报文。 总线错误和恢复 -^^^^^^^^^^^^^^ +-------------- TWAI控制器能够检测由于总线干扰产生的/损坏的不符合帧格式的错误，并规定了一套由发送/接收错误计数器(TEC/REC)实现的故障隔离机制。计数器值决定节点的错误状态，即主动错误、错误警告、被动错误和离线，它可以使持续存在错误的节点最终自行断开与总线的连接。 @@ -317,12 +318,12 @@ TWAI控制器能够检测由于总线干扰产生的/损坏的不符合帧格式 节点恢复完成时同样进入 :cpp:member:`twai_event_callbacks_t::on_state_change` 回调，状态由 :cpp:enumerator:`TWAI_ERROR_BUS_OFF` 变为 :cpp:enumerator:`TWAI_ERROR_ACTIVE`。恢复完成的节点可以立即进行传输，如果发送队列中有未完成的任务，驱动将立即发起新的传输。 关于低功耗 -^^^^^^^^^^ +---------- 当启用电源管理 :ref:`CONFIG_PM_ENABLE` 时，系统在进入睡眠模式前可能会调整或关闭时钟源，从而导致 TWAI 出错。为了防止这种情况发生，驱动内部使用电源锁管理。当调用 :cpp:func:`twai_node_enable` 函数后，该锁将被激活，确保系统不会进入睡眠模式，从而保持 TWAI 功能正常。如果需要降低功耗，可以调用 :cpp:func:`twai_node_disable` 函数来释放电源管理锁，使系统能够进入睡眠模式，睡眠期间 TWAI 控制器也将停止工作。 关于 Cache 安全 -^^^^^^^^^^^^^^^ +--------------- 在进行 Flash 写操作时，为了避免 Cache 从 Flash 加载指令和数据时出现错误，系统会暂时禁用 Cache 功能。这会导致存放在 Flash 上的中断处理程序在此期间无法响应。如果希望在 Cache 被禁用期间，中断处理程序仍能正常运行，可以启用 :ref:`CONFIG_TWAI_ISR_CACHE_SAFE` 选项。 @@ -331,12 +332,12 @@ TWAI控制器能够检测由于总线干扰产生的/损坏的不符合帧格式 请注意，在启用该选项后，所有的中断回调函数及其上下文数据 **必须存放在内部存储空间** 中。因为在 Cache 被禁用时，系统无法从 Flash 中加载数据和指令。 关于线程安全 -^^^^^^^^^^^^^ +------------- 驱动程序可保证所有公开的 TWAI API 的线程安全，使用时，可以直接从不同的 RTOS 任务中调用此类 API，无需额外锁保护。 关于性能 -^^^^^^^^ +-------- 为了提升中断处理的实时响应能力， 驱动提供了 :ref:`CONFIG_TWAI_ISR_IN_IRAM` 选项。启用该选项后，中断处理程序和接收操作将被放置在内部 RAM 中运行，从而减少了从 Flash 加载指令带来的延迟。 @@ -347,7 +348,7 @@ TWAI控制器能够检测由于总线干扰产生的/损坏的不符合帧格式 但是，中断处理程序调用的用户回调函数和用户上下文数据仍然可能位于 Flash 中，延迟问题还是会存在，这需要用户自己将回调函数和数据放入内部 RAM 中，比如使用 :c:macro:`IRAM_ATTR` 和 :c:macro:`DRAM_ATTR`。 关于资源消耗 -^^^^^^^^^^^^ +------------ 使用 :doc:`/api-guides/tools/idf-size` 工具可以查看 TWAI 驱动的 Flash 和内存空间消耗。以下是测试条件（以 ESP32-C6 为例）： @@ -385,12 +386,12 @@ TWAI控制器能够检测由于总线干扰产生的/损坏的不符合帧格式 此外，每一个 TWAI 句柄会从 heap 中动态申请约 ``168`` + 4 * :cpp:member:`twai_onchip_node_config_t::tx_queue_depth` 字节的内存。 其他 Kconfig 选项 -^^^^^^^^^^^^^^^^^ +----------------- - :ref:`CONFIG_TWAI_ENABLE_DEBUG_LOG` 选项允许强制启用 TWAI 驱动的所有调试日志，无论全局日志级别设置如何。启用此选项可以帮助开发人员在调试过程中获取更详细的日志信息，从而更容易定位和解决问题。 应用示例 --------- +======== .. list:: @@ -398,9 +399,24 @@ TWAI控制器能够检测由于总线干扰产生的/损坏的不符合帧格式 - :example:`peripherals/twai/twai_network` 通过发送、监听， 2 个不同角色的节点，演示了如何使用驱动程序进行单次的和大量的数据发送，以及配置过滤器以接收这些数据。 API 参考 --------- +======== + +片上 TWAI API +------------- .. include-build-file:: inc/esp_twai_onchip.inc + +TWAI 驱动 API +------------- + .. include-build-file:: inc/esp_twai.inc + +TWAI 驱动类型 +------------- + .. include-build-file:: inc/esp_twai_types.inc + +TWAI HAL 类型 +-------------- + .. include-build-file:: inc/twai_types.inc diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/main.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/main.c index 2903a67c02fc..d4c871e96492 100644 --- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/main.c +++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/main/main.c @@ -78,12 +78,14 @@ void app_main(void) { return; } +#if CONFIG_BT_NIMBLE_GAP_SERVICE /* GAP service initialization */ rc = gap_init(); if (rc != 0) { ESP_LOGE(TAG, "failed to initialize GAP service, error code: %d", rc); return; } +#endif /* NimBLE host configuration initialization */ nimble_host_config_init(); diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/main.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/main.c index b3fa8a9012e5..6fc6c414a015 100644 --- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/main.c +++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/main.c @@ -82,12 +82,14 @@ void app_main(void) { return; } +#if CONFIG_BT_NIMBLE_GAP_SERVICE /* GAP service initialization */ rc = gap_init(); if (rc != 0) { ESP_LOGE(TAG, "failed to initialize GAP service, error code: %d", rc); return; } +#endif /* NimBLE host configuration initialization */ nimble_host_config_init(); diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c index 68fffcaafba5..d4d220d9fc17 100644 --- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c +++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/main/src/gap.c @@ -251,6 +251,7 @@ int gap_init(void) { /* Local variables */ int rc = 0; + /* Initialize GAP service */ ble_svc_gap_init(); diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/main.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/main.c index aa804b209951..5283e2e7856e 100644 --- a/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/main.c +++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/main/main.c @@ -109,12 +109,14 @@ void app_main(void) { return; } +#if CONFIG_BT_NIMBLE_GAP_SERVICE /* GAP service initialization */ rc = gap_init(); if (rc != 0) { ESP_LOGE(TAG, "failed to initialize GAP service, error code: %d", rc); return; } +#endif /* GATT server initialization */ rc = gatt_svc_init(); diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/main.c b/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/main.c index 26541056a6c7..dfe997eb080c 100644 --- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/main.c +++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/main/main.c @@ -118,12 +118,14 @@ void app_main(void) { return; } +#if CONFIG_BT_NIMBLE_GAP_SERVICE /* GAP service initialization */ rc = gap_init(); if (rc != 0) { ESP_LOGE(TAG, "failed to initialize GAP service, error code: %d", rc); return; } +#endif /* GATT server initialization */ rc = gatt_svc_init(); diff --git a/examples/bluetooth/nimble/ble_cts/cts_cent/main/main.c b/examples/bluetooth/nimble/ble_cts/cts_cent/main/main.c index 0a99776f2cba..128b6afd3ac8 100644 --- a/examples/bluetooth/nimble/ble_cts/cts_cent/main/main.c +++ b/examples/bluetooth/nimble/ble_cts/cts_cent/main/main.c @@ -44,6 +44,7 @@ void printtime(struct ble_svc_cts_curr_time ctime) { ESP_LOGI(tag, "fractions : %d\n", ctime.et_256.fractions_256); } +#if MYNEWT_VAL(BLE_GATTC) /** * Application callback. Called when the read of the cts current time * characteristic has completed. @@ -137,6 +138,7 @@ ble_cts_cent_on_disc_complete(const struct peer *peer, int status, void *arg) */ ble_cts_cent_read_time(peer); } +#endif /** * Initiates the GAP general discovery procedure. @@ -434,6 +436,7 @@ ble_cts_cent_gap_event(struct ble_gap_event *event, void *arg) return 0; } #else +#if MYNEWT_VAL(BLE_GATTC) /* Perform service discovery */ rc = peer_disc_all(event->connect.conn_handle, ble_cts_cent_on_disc_complete, NULL); @@ -441,6 +444,7 @@ ble_cts_cent_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif #endif // BLE_GATT_CACHING_ASSOC_ENABLE #endif } else { @@ -485,6 +489,7 @@ ble_cts_cent_gap_event(struct ble_gap_event *event, void *arg) return 0; } #else +#if MYNEWT_VAL(BLE_GATTC) /*** Go for service discovery after encryption has been successfully enabled ***/ rc = peer_disc_all(event->connect.conn_handle, ble_cts_cent_on_disc_complete, NULL); @@ -492,6 +497,7 @@ ble_cts_cent_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif #endif // BLE_GATT_CACHING_ASSOC_ENABLE #endif return 0; diff --git a/examples/bluetooth/nimble/ble_cts/cts_prph/main/main.c b/examples/bluetooth/nimble/ble_cts/cts_prph/main/main.c index 2da3a66ad69f..04ee0c3eadd2 100644 --- a/examples/bluetooth/nimble/ble_cts/cts_prph/main/main.c +++ b/examples/bluetooth/nimble/ble_cts/cts_prph/main/main.c @@ -28,7 +28,6 @@ static uint8_t ext_adv_pattern_1[] = { static const char *tag = "NimBLE_CTS_PRPH"; static const char *device_name = "ble_cts_prph"; - static int ble_cts_prph_gap_event(struct ble_gap_event *event, void *arg); static uint8_t ble_cts_prph_addr_type; @@ -274,8 +273,6 @@ void ble_cts_prph_host_task(void *param) void app_main(void) { - int rc; - /* Initialize NVS — it is used to store PHY calibration data */ esp_err_t ret = nvs_flash_init(); if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { @@ -302,12 +299,15 @@ void app_main(void) ble_hs_cfg.sm_sc = 1; ble_hs_cfg.sm_mitm = 1; +#if MYNEWT_VAL(BLE_GATTS) + int rc; rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name */ rc = ble_svc_gap_device_name_set(device_name); assert(rc == 0); +#endif /* Start the task */ nimble_port_freertos_init(ble_cts_prph_host_task); diff --git a/examples/bluetooth/nimble/ble_dynamic_service/main/main.c b/examples/bluetooth/nimble/ble_dynamic_service/main/main.c index d99326f81d3e..02a7ed07271e 100644 --- a/examples/bluetooth/nimble/ble_dynamic_service/main/main.c +++ b/examples/bluetooth/nimble/ble_dynamic_service/main/main.c @@ -280,12 +280,14 @@ app_main(void) ble_hs_cfg.gatts_register_cb = gatt_svr_register_cb; ble_hs_cfg.store_status_cb = ble_store_util_status_rr; +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name. */ rc = ble_svc_gap_device_name_set("ble-dynamic-service"); assert(rc == 0); +#endif nimble_port_freertos_init(dynamic_service_host_task); diff --git a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/main/main.c b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/main/main.c index 1b3e77574d69..a141d0f2e0fd 100644 --- a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/main/main.c +++ b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/main/main.c @@ -22,7 +22,10 @@ static struct km_peer kmp[CONFIG_BT_NIMBLE_MAX_CONNECTIONS + 1] = {0}; static const char *tag = "ENC_ADV_DATA_CENT"; static int enc_adv_data_cent_gap_event(struct ble_gap_event *event, void *arg); + +#if MYNEWT_VAL(BLE_GATTC) static int mtu_def = 512; +#endif void ble_store_config_init(void); @@ -37,6 +40,7 @@ enc_adv_data_find_peer(const uint8_t *peer_addr) return -1; } +#if MYNEWT_VAL(BLE_GATTC) static int enc_adv_data_set_km_exist(const uint8_t *peer_addr) { @@ -47,6 +51,7 @@ enc_adv_data_set_km_exist(const uint8_t *peer_addr) kmp[ind].key_material_exist = true; return 0; } +#endif static bool enc_adv_data_check_km_exist(const uint8_t *peer_addr) @@ -60,6 +65,7 @@ enc_adv_data_check_km_exist(const uint8_t *peer_addr) return kmp[ind].key_material_exist; } +#if MYNEWT_VAL(BLE_GATTC) /** * Application callback. Called when the read has completed. */ @@ -175,6 +181,7 @@ enc_adv_data_cent_on_disc_complete(const struct peer *peer, int status, void *ar enc_adv_data_cent_read(peer); } } +#endif /** * Initiates the GAP general discovery procedure. @@ -444,6 +451,7 @@ enc_adv_data_cent_gap_event(struct ble_gap_event *event, void *arg) print_conn_desc(&desc); MODLOG_DFLT(INFO, ""); +#if MYNEWT_VAL(BLE_GATTC) rc = ble_att_set_preferred_mtu(mtu_def); if (rc != 0) { ESP_LOGE(tag, "Failed to set preferred MTU; rc = %d", rc); @@ -453,6 +461,7 @@ enc_adv_data_cent_gap_event(struct ble_gap_event *event, void *arg) if (rc != 0) { ESP_LOGE(tag, "Failed to negotiate MTU; rc = %d", rc); } +#endif /* Remember peer. */ rc = peer_add(event->connect.conn_handle); @@ -511,12 +520,14 @@ enc_adv_data_cent_gap_event(struct ble_gap_event *event, void *arg) assert(rc == 0); print_conn_desc(&desc); +#if MYNEWT_VAL(BLE_GATTC) /* Perform service discovery */ rc = peer_disc_all(event->enc_change.conn_handle, enc_adv_data_cent_on_disc_complete, NULL); if (rc != 0) { MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); } +#endif return 0; case BLE_GAP_EVENT_NOTIFY_RX: diff --git a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/main/main.c b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/main/main.c index e0c87902583b..78a3159eb40e 100644 --- a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/main/main.c +++ b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/main/main.c @@ -413,15 +413,16 @@ app_main(void) ble_hs_cfg.sm_their_key_dist |= BLE_SM_PAIR_KEY_DIST_ID; #endif +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name. */ rc = ble_svc_gap_device_name_set("enc_adv_data_prph"); assert(rc == 0); +#endif /* Set the session key and initialization vector */ - rc = ble_svc_gap_device_key_material_set(km.session_key, km.iv); assert(rc == 0); diff --git a/examples/bluetooth/nimble/ble_htp/htp_cent/main/main.c b/examples/bluetooth/nimble/ble_htp/htp_cent/main/main.c index 2e47880916b8..281dadc61030 100644 --- a/examples/bluetooth/nimble/ble_htp/htp_cent/main/main.c +++ b/examples/bluetooth/nimble/ble_htp/htp_cent/main/main.c @@ -20,6 +20,8 @@ static int ble_htp_cent_gap_event(struct ble_gap_event *event, void *arg); void ble_store_config_init(void); static void ble_htp_cent_scan(void); + +#if MYNEWT_VAL(BLE_GATTC) /** * Application callback. Called when the attempt to subscribe to notifications * for the HTP intermediate temperature characteristic has completed. @@ -255,7 +257,7 @@ ble_htp_cent_on_disc_complete(const struct peer *peer, int status, void *arg) */ ble_htp_cent_read_write_subscribe(peer); } - +#endif /** * Initiates the GAP general discovery procedure. */ @@ -548,6 +550,7 @@ ble_htp_cent_gap_event(struct ble_gap_event *event, void *arg) return 0; } #else +#if MYNEWT_VAL(BLE_GATTC) /* Perform service discovery */ rc = peer_disc_all(event->connect.conn_handle, ble_htp_cent_on_disc_complete, NULL); @@ -555,6 +558,7 @@ ble_htp_cent_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif #endif // BLE_GATT_CACHING_ASSOC_ENABLE #endif } else { @@ -599,6 +603,7 @@ ble_htp_cent_gap_event(struct ble_gap_event *event, void *arg) return 0; } #else +#if MYNEWT_VAL(BLE_GATTC) /*** Go for service discovery after encryption has been successfully enabled ***/ rc = peer_disc_all(event->connect.conn_handle, ble_htp_cent_on_disc_complete, NULL); @@ -606,6 +611,7 @@ ble_htp_cent_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif #endif // BLE_GATT_CACHING_ASSOC_ENABLE #endif return 0; diff --git a/examples/bluetooth/nimble/ble_htp/htp_prph/main/main.c b/examples/bluetooth/nimble/ble_htp/htp_prph/main/main.c index 01bece43a40e..896c1d6fd4e2 100644 --- a/examples/bluetooth/nimble/ble_htp/htp_prph/main/main.c +++ b/examples/bluetooth/nimble/ble_htp/htp_prph/main/main.c @@ -201,6 +201,8 @@ ble_htp_prph_tx_htp_reset(void) static void ble_htp_prph_tx(TimerHandle_t ev) { + +#if CONFIG_BT_NIMBLE_HTP_SERVICE int rc; float temp; @@ -222,6 +224,7 @@ ble_htp_prph_tx(TimerHandle_t ev) } else { MODLOG_DFLT(INFO, "Error in sending notification"); } +#endif ble_htp_prph_tx_htp_reset(); } @@ -259,7 +262,9 @@ ble_htp_prph_gap_event(struct ble_gap_event *event, void *arg) #endif ble_htp_prph_tx_htp_stop(); +#if CONFIG_BT_NIMBLE_HTP_SERVICE ble_svc_htp_on_disconnect(event->disconnect.conn.conn_handle); +#endif break; case BLE_GAP_EVENT_ADV_COMPLETE: @@ -276,7 +281,9 @@ ble_htp_prph_gap_event(struct ble_gap_event *event, void *arg) "val_handle=%d\n", event->subscribe.cur_notify, event->subscribe.attr_handle); +#if CONFIG_BT_NIMBLE_HTP_SERVICE ble_svc_htp_subscribe(event->subscribe.conn_handle, event->subscribe.attr_handle); +#endif if (event->subscribe.cur_notify) { ble_htp_prph_tx_htp_reset(); @@ -336,8 +343,6 @@ void ble_htp_prph_host_task(void *param) void app_main(void) { - int rc; - /* Initialize NVS — it is used to store PHY calibration data */ esp_err_t ret = nvs_flash_init(); if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { @@ -368,12 +373,15 @@ void app_main(void) ble_htp_prph_tx_timer = xTimerCreate("ble_htp_prph_tx_timer", pdMS_TO_TICKS(1000), pdTRUE, (void *)0, ble_htp_prph_tx); +#if MYNEWT_VAL(BLE_GATTS) + int rc; rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name */ rc = ble_svc_gap_device_name_set(device_name); assert(rc == 0); +#endif /* Start the task */ nimble_port_freertos_init(ble_htp_prph_host_task); diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/main.c b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/main.c index 010ea85a1541..641a2f43bc21 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/main.c +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/main.c @@ -133,7 +133,6 @@ bleprph_advertise(void) { struct ble_gap_adv_params adv_params; struct ble_hs_adv_fields fields; - const char *name; int rc; /** @@ -160,6 +159,7 @@ bleprph_advertise(void) fields.tx_pwr_lvl_is_present = 1; fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO; + const char *name; name = ble_svc_gap_device_name(); fields.name = (uint8_t *)name; fields.name_len = strlen(name); diff --git a/examples/bluetooth/nimble/ble_multi_adv/main/main.c b/examples/bluetooth/nimble/ble_multi_adv/main/main.c index b8393aa806f2..03f93210fd9d 100644 --- a/examples/bluetooth/nimble/ble_multi_adv/main/main.c +++ b/examples/bluetooth/nimble/ble_multi_adv/main/main.c @@ -459,8 +459,6 @@ void ble_multi_adv_host_task(void *param) void app_main(void) { - int rc; - /* Initialize NVS — it is used to store PHY calibration data */ esp_err_t ret = nvs_flash_init(); if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { @@ -495,6 +493,8 @@ app_main(void) ble_instance_cb[i].cb = NULL; } +#if MYNEWT_VAL(BLE_GATTS) + int rc; rc = gatt_svr_init(); assert(rc == 0); @@ -502,6 +502,7 @@ app_main(void) /* Set the default device name. */ rc = ble_svc_gap_device_name_set("nimble-multi-adv"); assert(rc == 0); +#endif #endif /* XXX Need to have template for store */ diff --git a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/main/main.c b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/main/main.c index 6acd00750c52..c324092aee35 100644 --- a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/main/main.c +++ b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/main/main.c @@ -461,13 +461,17 @@ app_main(void) rc = peer_init(BLE_PEER_MAX_NUM, BLE_PEER_MAX_NUM, BLE_PEER_MAX_NUM, BLE_PEER_MAX_NUM); assert(rc == 0); #endif - /* Set the default device name. We will act as both central and peripheral. */ - rc = ble_svc_gap_device_name_set("esp-ble-role-coex"); - assert(rc == 0); + +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); + /* Set the default device name. We will act as both central and peripheral. */ + rc = ble_svc_gap_device_name_set("esp-ble-role-coex"); + assert(rc == 0); +#endif + /* XXX Need to have template for store */ ble_store_config_init(); diff --git a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/main/main.c b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/main/main.c index 47f6461572ae..e4b0f4686ae1 100644 --- a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/main/main.c +++ b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/main/main.c @@ -287,12 +287,14 @@ app_main(void) ble_hs_cfg.gatts_register_cb = gatt_svr_register_cb; ble_hs_cfg.store_status_cb = ble_store_util_status_rr; +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name. */ rc = ble_svc_gap_device_name_set("esp-multi-conn"); assert(rc == 0); +#endif /* XXX Need to have template for store */ ble_store_config_init(); diff --git a/examples/bluetooth/nimble/ble_phy/phy_cent/main/main.c b/examples/bluetooth/nimble/ble_phy/phy_cent/main/main.c index 09eb5f6cc615..cec4bcaa3a77 100644 --- a/examples/bluetooth/nimble/ble_phy/phy_cent/main/main.c +++ b/examples/bluetooth/nimble/ble_phy/phy_cent/main/main.c @@ -24,6 +24,7 @@ static void blecent_scan(void); static uint8_t s_current_phy; void ble_store_config_init(void); +#if MYNEWT_VAL(BLE_GATTC) /** * Performs GATT operation against the specified peer: * 1. Reads the Supported LE PHY characteristic. @@ -167,6 +168,7 @@ blecent_on_disc_complete(const struct peer *peer, int status, void *arg) blecent_read(peer); } +#endif /* Set default LE PHY before establishing connection */ void set_default_le_phy(uint8_t tx_phys_mask, uint8_t rx_phys_mask) @@ -388,6 +390,7 @@ blecent_gap_event(struct ble_gap_event *event, void *arg) return 0; } +#if MYNEWT_VAL(BLE_GATTC) /* Perform service discovery. */ rc = peer_disc_all(event->connect.conn_handle, blecent_on_disc_complete, NULL); @@ -395,6 +398,7 @@ blecent_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif } else { /* Connection attempt failed; resume scanning. */ MODLOG_DFLT(ERROR, "Error: Connection failed; status=%d\n", diff --git a/examples/bluetooth/nimble/ble_phy/phy_prph/main/main.c b/examples/bluetooth/nimble/ble_phy/phy_prph/main/main.c index b43e8f649fd6..4fce3bedb36f 100644 --- a/examples/bluetooth/nimble/ble_phy/phy_prph/main/main.c +++ b/examples/bluetooth/nimble/ble_phy/phy_prph/main/main.c @@ -342,8 +342,10 @@ app_main(void) ble_hs_cfg.sm_their_key_dist = 1; #endif +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init_le_phy(); assert(rc == 0); +#endif /* Set the default device name. */ rc = ble_svc_gap_device_name_set("bleprph-phy"); diff --git a/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_cent/main/main.c b/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_cent/main/main.c index 0f6f9b309d58..108988328003 100644 --- a/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_cent/main/main.c +++ b/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_cent/main/main.c @@ -33,6 +33,7 @@ void ble_store_config_init(void); static void ble_prox_cent_scan(void); static int ble_prox_cent_gap_event(struct ble_gap_event *event, void *arg); +#if MYNEWT_VAL(BLE_GATTC) static int ble_prox_cent_on_read(uint16_t conn_handle, const struct ble_gatt_error *error, @@ -172,6 +173,7 @@ ble_prox_cent_on_disc_complete(const struct peer *peer, int status, void *arg) */ ble_prox_cent_read_write_subscribe(peer); } +#endif /** * Initiates the GAP general discovery procedure. @@ -480,6 +482,7 @@ ble_prox_cent_gap_event(struct ble_gap_event *event, void *arg) return 0; } #else +#if MYNEWT_VAL(BLE_GATTC) /* Perform service discovery */ rc = peer_disc_all(event->connect.conn_handle, ble_prox_cent_on_disc_complete, NULL); @@ -487,6 +490,7 @@ ble_prox_cent_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif #endif // BLE_GATT_CACHING_ASSOC_ENABLE #endif } else { @@ -547,6 +551,7 @@ ble_prox_cent_gap_event(struct ble_gap_event *event, void *arg) return 0; } #else +#if MYNEWT_VAL(BLE_GATTC) /*** Go for service discovery after encryption has been successfully enabled ***/ rc = peer_disc_all(event->connect.conn_handle, ble_prox_cent_on_disc_complete, NULL); @@ -554,6 +559,7 @@ ble_prox_cent_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif #endif // BLE_GATT_CACHING_ASSOC_ENABLE #endif return 0; @@ -656,6 +662,7 @@ ble_prox_cent_path_loss_task(void *pvParameters) path_loss = 0; } +#if MYNEWT_VAL(BLE_GATTC) rc = ble_gattc_write_no_rsp_flat(i, conn_peer[i].val_handle, &path_loss, sizeof(path_loss)); if (rc != 0) { @@ -664,6 +671,7 @@ ble_prox_cent_path_loss_task(void *pvParameters) } else { MODLOG_DFLT(INFO, "Write to alert level characteristis done"); } +#endif } } } @@ -743,7 +751,6 @@ app_main(void) /* Initialize a task to keep checking path loss of the link */ ble_prox_cent_init(); - for (int i = 0; i <= MYNEWT_VAL(BLE_MAX_CONNECTIONS); i++) { disconn_peer[i].addr = NULL; disconn_peer[i].link_lost = true; diff --git a/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/main/main.c b/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/main/main.c index 7eb301cdb25d..336f80c72297 100644 --- a/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/main/main.c +++ b/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/main/main.c @@ -270,8 +270,6 @@ void ble_prox_prph_host_task(void *param) void app_main(void) { - int rc; - /* Initialize NVS — it is used to store PHY calibration data */ esp_err_t ret = nvs_flash_init(); if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { @@ -286,9 +284,10 @@ void app_main(void) return; } +#if CONFIG_BT_NIMBLE_PROX_SERVICE /* Initialize a task to keep checking path loss of the link */ ble_svc_prox_init(); - +#endif /* Initialize the NimBLE host configuration */ ble_hs_cfg.sync_cb = ble_prox_prph_on_sync; ble_hs_cfg.reset_cb = ble_prox_prph_on_reset; @@ -301,6 +300,7 @@ void app_main(void) ble_hs_cfg.sm_sc = 1; ble_hs_cfg.sm_mitm = 1; + int rc; /* Set the default device name */ rc = ble_svc_gap_device_name_set(device_name); assert(rc == 0); diff --git a/examples/bluetooth/nimble/ble_spp/spp_client/main/main.c b/examples/bluetooth/nimble/ble_spp/spp_client/main/main.c index 4b479214c394..5b5fb206e5f2 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_client/main/main.c +++ b/examples/bluetooth/nimble/ble_spp/spp_client/main/main.c @@ -26,6 +26,7 @@ uint16_t attribute_handle[CONFIG_BT_NIMBLE_MAX_CONNECTIONS + 1]; static void ble_spp_client_scan(void); static ble_addr_t connected_addr[CONFIG_BT_NIMBLE_MAX_CONNECTIONS + 1]; +#if MYNEWT_VAL(BLE_GATTC) static void ble_spp_client_write_subscribe(const struct peer *peer) { uint8_t value[2]; @@ -90,7 +91,6 @@ ble_spp_client_set_handle(const struct peer *peer) value, sizeof(value), NULL, NULL); } - /** * Called when service discovery of the specified peer has completed. */ @@ -119,6 +119,7 @@ ble_spp_client_on_disc_complete(const struct peer *peer, int status, void *arg) ble_spp_client_scan(); #endif } +#endif /** * Initiates the GAP general discovery procedure. @@ -306,6 +307,7 @@ ble_spp_client_gap_event(struct ble_gap_event *event, void *arg) return 0; } +#if MYNEWT_VAL(BLE_GATTC) /* Perform service discovery. */ rc = peer_disc_all(event->connect.conn_handle, ble_spp_client_on_disc_complete, NULL); @@ -313,6 +315,7 @@ ble_spp_client_gap_event(struct ble_gap_event *event, void *arg) MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); return 0; } +#endif } else { /* Connection attempt failed; resume scanning. */ MODLOG_DFLT(ERROR, "Error: Connection failed; status=%d\n", @@ -421,12 +424,14 @@ void ble_client_uart_task(void *pvParameters) uart_read_bytes(UART_NUM_0, temp, event.size, portMAX_DELAY); for ( i = 0; i <= CONFIG_BT_NIMBLE_MAX_CONNECTIONS; i++) { if (attribute_handle[i] != 0) { +#if MYNEWT_VAL(BLE_GATTC) rc = ble_gattc_write_flat(i, attribute_handle[i], temp, event.size, NULL, NULL); if (rc == 0) { ESP_LOGI(tag, "Write in uart task success!"); } else { ESP_LOGI(tag, "Error in writing characteristic rc=%d", rc); } +#endif vTaskDelay(10); } } diff --git a/examples/bluetooth/nimble/ble_spp/spp_server/main/main.c b/examples/bluetooth/nimble/ble_spp/spp_server/main/main.c index b61cc2247d90..b79521be6956 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_server/main/main.c +++ b/examples/bluetooth/nimble/ble_spp/spp_server/main/main.c @@ -63,7 +63,6 @@ ble_spp_server_advertise(void) { struct ble_gap_adv_params adv_params; struct ble_hs_adv_fields fields; - const char *name; int rc; /** @@ -90,6 +89,7 @@ ble_spp_server_advertise(void) fields.tx_pwr_lvl_is_present = 1; fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO; + const char *name; name = ble_svc_gap_device_name(); fields.name = (uint8_t *)name; fields.name_len = strlen(name); @@ -412,8 +412,6 @@ static void ble_spp_uart_init(void) void app_main(void) { - int rc; - /* Initialize NVS — it is used to store PHY calibration data */ esp_err_t ret = nvs_flash_init(); if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { @@ -459,6 +457,8 @@ app_main(void) ble_hs_cfg.sm_their_key_dist = 1; #endif +#if MYNEWT_VAL(BLE_GATTS) + int rc; /* Register custom service */ rc = gatt_svr_init(); assert(rc == 0); @@ -466,6 +466,7 @@ app_main(void) /* Set the default device name. */ rc = ble_svc_gap_device_name_set("nimble-ble-spp-svr"); assert(rc == 0); +#endif /* XXX Need to have template for store */ ble_store_config_init(); diff --git a/examples/bluetooth/nimble/blecsc/main/main.c b/examples/bluetooth/nimble/blecsc/main/main.c index 3b69a930dc17..73c30906d96c 100644 --- a/examples/bluetooth/nimble/blecsc/main/main.c +++ b/examples/bluetooth/nimble/blecsc/main/main.c @@ -324,12 +324,14 @@ app_main(void) rc = ble_npl_callout_reset(&blecsc_measure_timer, portTICK_PERIOD_MS * 100); assert(rc == 0); +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(&csc_measurement_state); assert(rc == 0); /* Set the default device name */ rc = ble_svc_gap_device_name_set(device_name); assert(rc == 0); +#endif nimble_port_freertos_init(blecsc_host_task); diff --git a/examples/bluetooth/nimble/blehr/main/main.c b/examples/bluetooth/nimble/blehr/main/main.c index b9c7ea991f91..94b7b495fd52 100644 --- a/examples/bluetooth/nimble/blehr/main/main.c +++ b/examples/bluetooth/nimble/blehr/main/main.c @@ -293,12 +293,14 @@ void app_main(void) /* name, period/time, auto reload, timer ID, callback */ blehr_tx_timer = xTimerCreate("blehr_tx_timer", pdMS_TO_TICKS(1000), pdTRUE, (void *)0, blehr_tx_hrate); +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name */ rc = ble_svc_gap_device_name_set(device_name); assert(rc == 0); +#endif /* Start the task */ nimble_port_freertos_init(blehr_host_task); diff --git a/examples/bluetooth/nimble/bleprph_host_only/main/main.c b/examples/bluetooth/nimble/bleprph_host_only/main/main.c index 756863565a90..a03b3157ead7 100644 --- a/examples/bluetooth/nimble/bleprph_host_only/main/main.c +++ b/examples/bluetooth/nimble/bleprph_host_only/main/main.c @@ -131,7 +131,6 @@ bleprph_advertise(void) { struct ble_gap_adv_params adv_params; struct ble_hs_adv_fields fields; - const char *name; int rc; /** @@ -158,6 +157,7 @@ bleprph_advertise(void) fields.tx_pwr_lvl_is_present = 1; fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO; + const char *name; name = ble_svc_gap_device_name(); fields.name = (uint8_t *)name; fields.name_len = strlen(name); @@ -528,12 +528,14 @@ app_main(void) ble_hs_cfg.sm_their_key_dist |= BLE_SM_PAIR_KEY_DIST_ID; #endif +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name. */ rc = ble_svc_gap_device_name_set("nimble-bleprph"); assert(rc == 0); +#endif /* XXX Need to have template for store */ ble_store_config_init(); diff --git a/examples/bluetooth/nimble/bleprph_wifi_coex/main/main.c b/examples/bluetooth/nimble/bleprph_wifi_coex/main/main.c index bd2af71daa53..4d31b9d3086b 100644 --- a/examples/bluetooth/nimble/bleprph_wifi_coex/main/main.c +++ b/examples/bluetooth/nimble/bleprph_wifi_coex/main/main.c @@ -311,7 +311,6 @@ bleprph_advertise(void) { struct ble_gap_adv_params adv_params; struct ble_hs_adv_fields fields; - const char *name; int rc; /** @@ -338,6 +337,7 @@ bleprph_advertise(void) fields.tx_pwr_lvl_is_present = 1; fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO; + const char *name; name = ble_svc_gap_device_name(); fields.name = (uint8_t *)name; fields.name_len = strlen(name); @@ -525,8 +525,6 @@ void bleprph_host_task(void *param) void app_main(void) { - int rc; - /* Initialize NVS — it is used to store PHY calibration data */ esp_err_t ret = nvs_flash_init(); if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { @@ -550,12 +548,15 @@ app_main(void) ble_hs_cfg.gatts_register_cb = gatt_svr_register_cb; ble_hs_cfg.store_status_cb = ble_store_util_status_rr; +#if MYNEWT_VAL(BLE_GATTS) + int rc; rc = gatt_svr_init(); assert(rc == 0); /* Set the default device name. */ rc = ble_svc_gap_device_name_set("nimble-bleprph"); assert(rc == 0); +#endif /* XXX Need to have template for store */ ble_store_config_init(); diff --git a/examples/bluetooth/nimble/power_save/main/main.c b/examples/bluetooth/nimble/power_save/main/main.c index 166d83de37f4..0e7e9bcf5b6a 100644 --- a/examples/bluetooth/nimble/power_save/main/main.c +++ b/examples/bluetooth/nimble/power_save/main/main.c @@ -169,7 +169,6 @@ bleprph_advertise(void) { struct ble_gap_adv_params adv_params; struct ble_hs_adv_fields fields; - const char *name; int rc; /** @@ -196,6 +195,7 @@ bleprph_advertise(void) fields.tx_pwr_lvl_is_present = 1; fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO; + const char *name; name = ble_svc_gap_device_name(); fields.name = (uint8_t *)name; fields.name_len = strlen(name); @@ -622,6 +622,7 @@ app_main(void) ble_hs_cfg.sm_their_key_dist |= BLE_SM_PAIR_KEY_DIST_ID; #endif +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); @@ -629,6 +630,7 @@ app_main(void) /* Set the default device name. */ rc = ble_svc_gap_device_name_set("nimble-bleprph"); assert(rc == 0); +#endif #endif /* XXX Need to have template for store */ diff --git a/examples/bluetooth/nimble/throughput_app/blecent_throughput/main/main.c b/examples/bluetooth/nimble/throughput_app/blecent_throughput/main/main.c index 49d1007a94a8..1177a9fb0ea9 100644 --- a/examples/bluetooth/nimble/throughput_app/blecent_throughput/main/main.c +++ b/examples/bluetooth/nimble/throughput_app/blecent_throughput/main/main.c @@ -945,6 +945,7 @@ app_main(void) rc = peer_init(MYNEWT_VAL(BLE_MAX_CONNECTIONS), 64, 64, 64); assert(rc == 0); #endif + /* Set the default device name. */ rc = ble_svc_gap_device_name_set("gattc-throughput"); assert(rc == 0); diff --git a/examples/bluetooth/nimble/throughput_app/bleprph_throughput/main/main.c b/examples/bluetooth/nimble/throughput_app/bleprph_throughput/main/main.c index 5ccfd6291459..e15042207fe3 100644 --- a/examples/bluetooth/nimble/throughput_app/bleprph_throughput/main/main.c +++ b/examples/bluetooth/nimble/throughput_app/bleprph_throughput/main/main.c @@ -26,10 +26,10 @@ static uint8_t ext_adv_pattern[] = { }; static uint8_t s_current_phy; -#else -static const char *device_name = "nimble_prph"; #endif +static const char *device_name = "nimble_prph"; + #define NOTIFY_THROUGHPUT_PAYLOAD 495 #define MIN_REQUIRED_MBUF 2 /* Assuming payload of 500Bytes and each mbuf can take 292Bytes. */ #define PREFERRED_MTU_VALUE 512 @@ -509,10 +509,10 @@ void app_main(void) /* Initialize Notify Task */ xTaskCreate(notify_task, "notify_task", 4096, NULL, 10, NULL); +#if MYNEWT_VAL(BLE_GATTS) rc = gatt_svr_init(); assert(rc == 0); -#if !(CONFIG_EXAMPLE_EXTENDED_ADV) /* Set the default device name */ rc = ble_svc_gap_device_name_set(device_name); assert(rc == 0); diff --git a/examples/cxx/.build-test-rules.yml b/examples/cxx/.build-test-rules.yml new file mode 100644 index 000000000000..9d21130a1c7a --- /dev/null +++ b/examples/cxx/.build-test-rules.yml @@ -0,0 +1,13 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +examples/cxx/exceptions: + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14402 + +examples/cxx/rtti: + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14402 diff --git a/examples/cxx/exceptions/pytest_examples_cxx_exceptions.py b/examples/cxx/exceptions/pytest_examples_cxx_exceptions.py index f62a8ae866ec..b2df9354f113 100644 --- a/examples/cxx/exceptions/pytest_examples_cxx_exceptions.py +++ b/examples/cxx/exceptions/pytest_examples_cxx_exceptions.py @@ -7,6 +7,7 @@ @pytest.mark.generic @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14402') def test_examples_cpp_exceptions(dut: IdfDut) -> None: lines = [ 'app_main starting', diff --git a/examples/cxx/rtti/pytest_examples_cxx_rtti.py b/examples/cxx/rtti/pytest_examples_cxx_rtti.py index e6d81bd99bfa..705acc6249b2 100644 --- a/examples/cxx/rtti/pytest_examples_cxx_rtti.py +++ b/examples/cxx/rtti/pytest_examples_cxx_rtti.py @@ -7,6 +7,7 @@ @pytest.mark.generic @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14402') def test_cpp_rtti_example(dut: IdfDut) -> None: dut.expect_exact('Type name of std::cout is: std::ostream') dut.expect_exact('Type name of std::cin is: std::istream') diff --git a/examples/ethernet/.build-test-rules.yml b/examples/ethernet/.build-test-rules.yml index 9d33a571b4b5..c73718e096fc 100644 --- a/examples/ethernet/.build-test-rules.yml +++ b/examples/ethernet/.build-test-rules.yml @@ -4,9 +4,9 @@ examples/ethernet/basic: enable: - if: INCLUDE_DEFAULT == 1 disable: - - if: IDF_TARGET in ["esp32h21", "esp32h4"] + - if: IDF_TARGET in ["esp32h21", "esp32h4", "esp32p4"] temporary: true - reason: not supported yet # TODO: [ESP32H21] IDF-11581 [ESP32H4] IDF-12360 + reason: not supported yet # TODO: [ESP32H21] IDF-11581 [ESP32H4] IDF-12360, IDF-14365 disable_test: - if: IDF_TARGET not in ["esp32"] temporary: true @@ -21,9 +21,9 @@ examples/ethernet/basic: examples/ethernet/iperf: disable: - - if: IDF_TARGET in ["esp32h21", "esp32h4"] + - if: IDF_TARGET in ["esp32h21", "esp32h4", "esp32p4"] temporary: true - reason: not supported yet # TODO: [ESP32H21] IDF-11581 [ESP32H4] IDF-12360 + reason: not supported yet # TODO: [ESP32H21] IDF-11581 [ESP32H4] IDF-12360, IDF-14365 disable_test: - if: IDF_TARGET not in ["esp32", "esp32p4"] temporary: true diff --git a/examples/ethernet/basic/README.md b/examples/ethernet/basic/README.md index 76ef20af002e..2a25d912c212 100644 --- a/examples/ethernet/basic/README.md +++ b/examples/ethernet/basic/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | # Ethernet Example (See the README.md file in the upper level 'examples' directory for more information about examples.) diff --git a/examples/ethernet/iperf/README.md b/examples/ethernet/iperf/README.md index 4f609030b2dd..806c86337d49 100644 --- a/examples/ethernet/iperf/README.md +++ b/examples/ethernet/iperf/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | # Ethernet iperf Example diff --git a/examples/ethernet/iperf/pytest_eth_iperf.py b/examples/ethernet/iperf/pytest_eth_iperf.py index 25a47182753f..0d5b758be6db 100644 --- a/examples/ethernet/iperf/pytest_eth_iperf.py +++ b/examples/ethernet/iperf/pytest_eth_iperf.py @@ -1,5 +1,12 @@ # SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Unlicense OR CC0-1.0 +import os +import subprocess + +import pytest +from common_test_methods import get_host_ip4_by_dest_ip +from idf_iperf_test_util import IperfUtility +from pytest_embedded import Dut from pytest_embedded_idf.utils import idf_parametrize """ @@ -10,16 +17,12 @@ - use `sudo killall iperf` to force kill iperf, didn't implement windows version """ -import os -import subprocess - -import pytest -from common_test_methods import get_host_ip4_by_dest_ip -from idf_iperf_test_util import IperfUtility -from pytest_embedded import Dut try: - from typing import Any, Callable, Tuple, Optional + from typing import Any + from typing import Callable + from typing import Optional + from typing import Tuple except ImportError: # Only used for type annotations pass @@ -132,6 +135,7 @@ def test_esp_eth_iperf_ip101( @pytest.mark.eth_ip101 +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14365') @pytest.mark.parametrize( 'config', [ diff --git a/examples/peripherals/.build-test-rules.yml b/examples/peripherals/.build-test-rules.yml index 11706d46d28b..42ad6d38508e 100644 --- a/examples/peripherals/.build-test-rules.yml +++ b/examples/peripherals/.build-test-rules.yml @@ -10,11 +10,19 @@ examples/peripherals/adc/continuous_read: disable: - if: SOC_ADC_DMA_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14357 <<: *adc_dependencies examples/peripherals/adc/oneshot_read: disable: - if: SOC_ADC_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14357 <<: *adc_dependencies examples/peripherals/analog_comparator: @@ -442,12 +450,20 @@ examples/peripherals/spi_slave_hd/segment_mode/seg_slave: examples/peripherals/temperature_sensor/temp_sensor: disable: - if: SOC_TEMP_SENSOR_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14834 depends_components: - esp_driver_tsens examples/peripherals/temperature_sensor/temp_sensor_monitor: disable: - if: SOC_TEMPERATURE_SENSOR_INTR_SUPPORT != 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14834 depends_components: - esp_driver_tsens @@ -496,9 +512,25 @@ examples/peripherals/twai/twai_error_recovery: depends_components: - esp_driver_twai -examples/peripherals/twai/twai_network: +examples/peripherals/twai/twai_network/twai_listen_only: disable: - if: SOC_TWAI_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET in ["esp32p4", "esp32h2"] + temporary: true + reason: p4 rev3 migration # TODO: IDF-14393 + depends_components: + - esp_driver_twai + + + +examples/peripherals/twai/twai_network/twai_sender: + disable: + - if: SOC_TWAI_SUPPORTED != 1 + disable_test: + - if: IDF_TARGET in ["esp32p4", "esp32c5"] + temporary: true + reason: p4 rev3 migration # TODO: IDF-14393 depends_components: - esp_driver_twai @@ -524,6 +556,7 @@ examples/peripherals/usb/device: depends_components: - usb - fatfs + - esp_hw_support # for usb_phy depends_filepatterns: - examples/peripherals/usb/device/**/* @@ -544,12 +577,13 @@ examples/peripherals/usb/host: disable: - if: SOC_USB_OTG_SUPPORTED != 1 disable_test: - - if: IDF_TARGET not in ["esp32s3", "esp32p4"] + - if: IDF_TARGET not in ["esp32s3"] temporary: true - reason: lack of runners with usb_host_flash_disk tag + reason: lack of runners with usb_host_flash_disk tag, p4 rev3 migration, IDF-14832 depends_components: - usb - fatfs + - esp_hw_support # for usb_phy depends_filepatterns: - components/hal/usb*.c - components/hal/include/hal/usb*.h diff --git a/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py b/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py index c7793c69a529..dbc532175196 100644 --- a/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py +++ b/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py @@ -11,6 +11,7 @@ ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c5', 'esp32p4', 'esp32c61'], indirect=['target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14357') def test_adc_continuous(dut: Dut) -> None: res = dut.expect(r'TASK: ret is 0, ret_num is (\d+) bytes') num = res.group(1).decode('utf8') diff --git a/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py b/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py index 17e15ba72777..5b8ecc80bccc 100644 --- a/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py +++ b/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py @@ -11,6 +11,7 @@ ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c5', 'esp32p4', 'esp32c61'], indirect=['target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14357') def test_adc_oneshot(dut: Dut) -> None: dut.expect(r'EXAMPLE: ADC1 Channel\[(\d+)\] Raw Data: (\d+)', timeout=5) diff --git a/examples/peripherals/temperature_sensor/temp_sensor/pytest_temp_sensor_example.py b/examples/peripherals/temperature_sensor/temp_sensor/pytest_temp_sensor_example.py index df1727e3f46c..97dcf3aba1ac 100644 --- a/examples/peripherals/temperature_sensor/temp_sensor/pytest_temp_sensor_example.py +++ b/examples/peripherals/temperature_sensor/temp_sensor/pytest_temp_sensor_example.py @@ -11,6 +11,7 @@ ['esp32s2', 'esp32c3', 'esp32s3', 'esp32c2', 'esp32c6', 'esp32h2', 'esp32p4', 'esp32c5', 'esp32c61'], indirect=['target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14834') def test_temp_sensor_example(dut: Dut) -> None: dut.expect_exact('Install temperature sensor') dut.expect_exact('Enable temperature sensor') diff --git a/examples/peripherals/temperature_sensor/temp_sensor_monitor/pytest_temp_sensor_monitor_example.py b/examples/peripherals/temperature_sensor/temp_sensor_monitor/pytest_temp_sensor_monitor_example.py index f5cccf04ac3e..a1fc48b1a0a7 100644 --- a/examples/peripherals/temperature_sensor/temp_sensor_monitor/pytest_temp_sensor_monitor_example.py +++ b/examples/peripherals/temperature_sensor/temp_sensor_monitor/pytest_temp_sensor_monitor_example.py @@ -7,6 +7,7 @@ @pytest.mark.generic @idf_parametrize('target', ['esp32c6', 'esp32h2', 'esp32p4', 'esp32c5', 'esp32c61'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14834') def test_temp_sensor_monitor_example(dut: Dut) -> None: dut.expect_exact('Install temperature sensor') dut.expect_exact('Enable temperature sensor') diff --git a/examples/peripherals/twai/twai_network/pytest_twai_network.py b/examples/peripherals/twai/twai_network/pytest_twai_network.py index d1bfc7c6f54f..962920194da6 100644 --- a/examples/peripherals/twai/twai_network/pytest_twai_network.py +++ b/examples/peripherals/twai/twai_network/pytest_twai_network.py @@ -54,6 +54,7 @@ def generate_target_combinations(target_list: list, count: int = 2) -> list: ], indirect=True, ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14393') def test_twai_network_multi(dut: Tuple[IdfDut, IdfDut], socket_can: Bus) -> None: # type: ignore """ Test TWAI network communication between two nodes: diff --git a/examples/peripherals/usb/device/tusb_composite_msc_serialdevice/pytest_usb_device_composite.py b/examples/peripherals/usb/device/tusb_composite_msc_serialdevice/pytest_usb_device_composite.py index 2c42a9235aeb..475519082953 100644 --- a/examples/peripherals/usb/device/tusb_composite_msc_serialdevice/pytest_usb_device_composite.py +++ b/examples/peripherals/usb/device/tusb_composite_msc_serialdevice/pytest_usb_device_composite.py @@ -23,7 +23,7 @@ def test_usb_composite_device_serial_example(dut: Dut) -> None: for port, _, hwid in ports: if '303A:4001' in hwid: with Serial(port) as s: - s.write('text\r\n'.encode()) # Write dummy text to COM port + s.write(b'text\r\n') # Write dummy text to COM port dut.expect_exact('Data from channel 0:') # Check ESP log dut.expect_exact('|text..|') res = s.readline() # Check COM echo diff --git a/examples/peripherals/usb/device/tusb_serial_device/pytest_usb_device_serial.py b/examples/peripherals/usb/device/tusb_serial_device/pytest_usb_device_serial.py index f1dd71ef11fd..0f54f382b12e 100644 --- a/examples/peripherals/usb/device/tusb_serial_device/pytest_usb_device_serial.py +++ b/examples/peripherals/usb/device/tusb_serial_device/pytest_usb_device_serial.py @@ -21,7 +21,7 @@ def test_usb_device_serial_example(dut: Dut) -> None: for port, _, hwid in ports: if '303A:4001' in hwid: with Serial(port) as s: - s.write('text\r\n'.encode()) # Write dummy text to COM port + s.write(b'text\r\n') # Write dummy text to COM port dut.expect_exact('Data from channel 0:') # Check ESP log dut.expect_exact('|text..|') res = s.readline() # Check COM echo diff --git a/examples/peripherals/usb/host/msc/pytest_usb_host_msc.py b/examples/peripherals/usb/host/msc/pytest_usb_host_msc.py index 5a4fda394a01..76bbdc0a62bd 100644 --- a/examples/peripherals/usb/host/msc/pytest_usb_host_msc.py +++ b/examples/peripherals/usb/host/msc/pytest_usb_host_msc.py @@ -5,7 +5,9 @@ from pytest_embedded_idf.utils import idf_parametrize -@pytest.mark.temp_skip_ci(targets=['esp32s2'], reason='lack of runners with usb_host_flash_disk tag') +@pytest.mark.temp_skip_ci( + targets=['esp32s2', 'esp32p4'], reason='lack of runners with usb_host_flash_disk tag,p4 rev3 migration, IDF-14832' +) @pytest.mark.usb_host_flash_disk @idf_parametrize( 'config,target', diff --git a/examples/peripherals/usb/host/usb_host_lib/pytest_usb_host_lib.py b/examples/peripherals/usb/host/usb_host_lib/pytest_usb_host_lib.py index b3907df7af32..965bd498b4c6 100644 --- a/examples/peripherals/usb/host/usb_host_lib/pytest_usb_host_lib.py +++ b/examples/peripherals/usb/host/usb_host_lib/pytest_usb_host_lib.py @@ -5,7 +5,9 @@ from pytest_embedded_idf.utils import idf_parametrize -@pytest.mark.temp_skip_ci(targets=['esp32s2'], reason='lack of runners with usb_host_flash_disk tag') +@pytest.mark.temp_skip_ci( + targets=['esp32s2', 'esp32p4'], reason='lack of runners with usb_host_flash_disk tag,p4 rev3 migration, IDF-14832' +) @pytest.mark.usb_host_flash_disk @idf_parametrize('target', ['esp32s2', 'esp32s3', 'esp32p4'], indirect=['target']) def test_usb_host_lib_example(dut: Dut) -> None: diff --git a/examples/security/.build-test-rules.yml b/examples/security/.build-test-rules.yml index 792158ea99eb..5d8d1ae3ae4a 100644 --- a/examples/security/.build-test-rules.yml +++ b/examples/security/.build-test-rules.yml @@ -1,6 +1,10 @@ # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps examples/security/flash_encryption: + disable: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14367 disable_test: - if: IDF_TARGET in ["esp32s2", "esp32s3", "esp32c6", "esp32h2", "esp32c2", "esp32p4", "esp32c5", "esp32c61"] temporary: true diff --git a/examples/security/flash_encryption/README.md b/examples/security/flash_encryption/README.md index 7b7e05f2ab60..4d822a092bfd 100644 --- a/examples/security/flash_encryption/README.md +++ b/examples/security/flash_encryption/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | # Flash Encryption diff --git a/examples/storage/.build-test-rules.yml b/examples/storage/.build-test-rules.yml index ae865e617720..7775365d8dbd 100644 --- a/examples/storage/.build-test-rules.yml +++ b/examples/storage/.build-test-rules.yml @@ -87,6 +87,9 @@ examples/storage/sd_card/sdspi: - esp_driver_sdspi disable: - if: SOC_GPSPI_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14363 disable_test: - if: IDF_TARGET not in ["esp32", "esp32s3", "esp32c3", "esp32c5", "esp32p4"] reason: needs special runner, select few typical targets for testing diff --git a/examples/storage/sd_card/sdspi/README.md b/examples/storage/sd_card/sdspi/README.md index bb5ba7dcb887..284d922aa594 100644 --- a/examples/storage/sd_card/sdspi/README.md +++ b/examples/storage/sd_card/sdspi/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | # SD Card example (SDSPI) diff --git a/examples/storage/sd_card/sdspi/pytest_sdspi_card_example.py b/examples/storage/sd_card/sdspi/pytest_sdspi_card_example.py index 086b6c70b74b..fb2b43d31d7a 100644 --- a/examples/storage/sd_card/sdspi/pytest_sdspi_card_example.py +++ b/examples/storage/sd_card/sdspi/pytest_sdspi_card_example.py @@ -9,6 +9,7 @@ @pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='C5 C61 GPSPI same, so testing on C5 is enough') +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14363') @pytest.mark.sdcard_spimode @idf_parametrize('target', ['esp32', 'esp32s3', 'esp32c3', 'esp32p4', 'esp32c5'], indirect=['target']) def test_examples_sd_card_sdspi(dut: Dut) -> None: diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml index 1a8b5a2507af..26eb93764bde 100644 --- a/examples/system/.build-test-rules.yml +++ b/examples/system/.build-test-rules.yml @@ -2,6 +2,9 @@ examples/system/app_trace_basic: disable: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14364 - if: IDF_TARGET == "esp32h21" temporary: true reason: not supported yet #TODO: OCD-1081 @@ -107,6 +110,9 @@ examples/system/gcov: - if: IDF_TARGET == "esp32c61" temporary: true reason: lack of runners + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14440 examples/system/gdbstub: disable: @@ -268,6 +274,9 @@ examples/system/select: examples/system/sysview_tracing: disable: - if: SOC_GPTIMER_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14364 disable_test: - if: IDF_TARGET == "esp32h21" temporary: true @@ -282,6 +291,9 @@ examples/system/sysview_tracing: examples/system/sysview_tracing_heap_log: disable: - if: SOC_GPTIMER_SUPPORTED != 1 + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14364 disable_test: - if: IDF_TARGET == "esp32h21" temporary: true @@ -303,6 +315,10 @@ examples/system/task_watchdog: examples/system/ulp/lp_core/build_system: enable: - if: SOC_LP_CORE_SUPPORTED == 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14422 depends_components: - ulp @@ -323,6 +339,10 @@ examples/system/ulp/lp_core/gpio: examples/system/ulp/lp_core/gpio_intr_pulse_counter: enable: - if: (SOC_LP_CORE_SUPPORTED == 1) and (SOC_ULP_LP_UART_SUPPORTED == 1 and SOC_DEEP_SLEEP_SUPPORTED == 1) + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14422 depends_components: - ulp @@ -335,12 +355,20 @@ examples/system/ulp/lp_core/gpio_wakeup: examples/system/ulp/lp_core/inter_cpu_critical_section/: enable: - if: SOC_LP_CORE_SUPPORTED == 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14422 depends_components: - ulp examples/system/ulp/lp_core/interrupt: enable: - if: SOC_LP_CORE_SUPPORTED == 1 + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14422 depends_components: - ulp diff --git a/examples/system/app_trace_basic/README.md b/examples/system/app_trace_basic/README.md index 151e992d1a40..72abab1b8da9 100644 --- a/examples/system/app_trace_basic/README.md +++ b/examples/system/app_trace_basic/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | # Application Level Tracing Example (Basic) diff --git a/examples/system/app_trace_basic/pytest_app_trace_basic.py b/examples/system/app_trace_basic/pytest_app_trace_basic.py index 319636b8d81a..a794148b2d88 100644 --- a/examples/system/app_trace_basic/pytest_app_trace_basic.py +++ b/examples/system/app_trace_basic/pytest_app_trace_basic.py @@ -54,5 +54,6 @@ def test_examples_app_trace_basic(openocd_dut: 'OpenOCD', dut: IdfDut) -> None: @pytest.mark.usb_serial_jtag @idf_parametrize('target', ['esp32s3', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32h2', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14364') def test_examples_app_trace_basic_usj(openocd_dut: 'OpenOCD', dut: IdfDut) -> None: _test_examples_app_trace_basic(openocd_dut, dut) diff --git a/examples/system/gcov/pytest_gcov.py b/examples/system/gcov/pytest_gcov.py index 7c15e45744ab..024b062c5611 100644 --- a/examples/system/gcov/pytest_gcov.py +++ b/examples/system/gcov/pytest_gcov.py @@ -80,5 +80,6 @@ def test_gcov(openocd_dut: 'OpenOCD', dut: IdfDut) -> None: @pytest.mark.usb_serial_jtag @idf_parametrize('target', ['esp32s3', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32h2', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14440') def test_gcov_usj(openocd_dut: 'OpenOCD', dut: IdfDut) -> None: _test_gcov(openocd_dut, dut) diff --git a/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py b/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py index 4128c2c89638..81d9f50a797f 100644 --- a/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py +++ b/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py @@ -7,6 +7,7 @@ @pytest.mark.generic @idf_parametrize('target', ['esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14423') def test_ipc_isr_riscv(dut: Dut) -> None: dut.expect_exact('example: Start') dut.expect_exact('example: MSTATUS = 0x11880') diff --git a/examples/system/light_sleep/main/uart_wakeup.c b/examples/system/light_sleep/main/uart_wakeup.c index d5f8d7bf1b98..79279e0a33cd 100644 --- a/examples/system/light_sleep/main/uart_wakeup.c +++ b/examples/system/light_sleep/main/uart_wakeup.c @@ -14,12 +14,18 @@ #include "driver/uart_wakeup.h" #include "sdkconfig.h" -#define EXAMPLE_UART_NUM 0 +#define EXAMPLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM /* Notice that ESP32 has to use the iomux input to configure uart as wakeup source * Please use 'UxRXD_GPIO_NUM' as uart rx pin. No limitation to the other target */ #define EXAMPLE_UART_TX_IO_NUM U0TXD_GPIO_NUM #define EXAMPLE_UART_RX_IO_NUM U0RXD_GPIO_NUM +#if CONFIG_ESP_CONSOLE_UART +#define EXAMPLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE +#else +#define EXAMPLE_UART_BAUDRATE 115200 +#endif + #define EXAMPLE_UART_WAKEUP_EDGE_THRESHOLD 3 #define EXAMPLE_UART_WAKEUP_FIFO_THRESHOLD 8 #define EXAMPLE_UART_WAKEUP_CHARS_SEQ "ok" @@ -103,7 +109,7 @@ static void uart_wakeup_task(void *arg) static void uart_initialization(void) { uart_config_t uart_cfg = { - .baud_rate = CONFIG_ESP_CONSOLE_UART_BAUDRATE, + .baud_rate = EXAMPLE_UART_BAUDRATE, .data_bits = UART_DATA_8_BITS, .parity = UART_PARITY_DISABLE, .stop_bits = UART_STOP_BITS_1, diff --git a/examples/system/sysview_tracing/README.md b/examples/system/sysview_tracing/README.md index 22a208cab68b..f675c0eaf1ba 100644 --- a/examples/system/sysview_tracing/README.md +++ b/examples/system/sysview_tracing/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | # Example: Application Level Tracing - SystemView Tracing (sysview_tracing) This test code shows how to perform system-wide behavioral analysis of the program using [SEGGER SystemView tool](https://www.segger.com/products/development-tools/systemview/). diff --git a/examples/system/sysview_tracing/pytest_sysview_tracing.py b/examples/system/sysview_tracing/pytest_sysview_tracing.py index fa273f41e974..57e342c50fdd 100644 --- a/examples/system/sysview_tracing/pytest_sysview_tracing.py +++ b/examples/system/sysview_tracing/pytest_sysview_tracing.py @@ -62,5 +62,6 @@ def test_examples_sysview_tracing(openocd_dut: 'OpenOCD', dut: IdfDut) -> None: @pytest.mark.usb_serial_jtag @idf_parametrize('target', ['esp32s3', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32h2', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14364') def test_examples_sysview_tracing_usj(openocd_dut: 'OpenOCD', dut: IdfDut) -> None: _test_examples_sysview_tracing(openocd_dut, dut) diff --git a/examples/system/sysview_tracing_heap_log/README.md b/examples/system/sysview_tracing_heap_log/README.md index 050a5f5fbb18..22d00657d02a 100644 --- a/examples/system/sysview_tracing_heap_log/README.md +++ b/examples/system/sysview_tracing_heap_log/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | # SystemView Heap and Log Tracing Example diff --git a/examples/system/sysview_tracing_heap_log/pytest_sysview_tracing_heap_log.py b/examples/system/sysview_tracing_heap_log/pytest_sysview_tracing_heap_log.py index 546bb97908d8..4cffbea5b3b7 100644 --- a/examples/system/sysview_tracing_heap_log/pytest_sysview_tracing_heap_log.py +++ b/examples/system/sysview_tracing_heap_log/pytest_sysview_tracing_heap_log.py @@ -67,5 +67,6 @@ def test_examples_sysview_tracing_heap_log(openocd_dut: 'OpenOCD', idf_path: str @pytest.mark.parametrize('config', ['app_trace_jtag'], indirect=True) @pytest.mark.usb_serial_jtag @idf_parametrize('target', ['esp32s3', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32h2', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14364') def test_examples_sysview_tracing_heap_log_usj(openocd_dut: 'OpenOCD', idf_path: str, dut: IdfDut) -> None: _test_examples_sysview_tracing_heap_log(openocd_dut, idf_path, dut) diff --git a/examples/system/ulp/lp_core/build_system/pytest_lp_core_build_sys.py b/examples/system/ulp/lp_core/build_system/pytest_lp_core_build_sys.py index b9089f97eb46..498d68c6b58c 100644 --- a/examples/system/ulp/lp_core/build_system/pytest_lp_core_build_sys.py +++ b/examples/system/ulp/lp_core/build_system/pytest_lp_core_build_sys.py @@ -7,5 +7,6 @@ @pytest.mark.generic @idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_build_sys(dut: IdfDut) -> None: dut.expect('Sum calculated by ULP using external library func: 11') diff --git a/examples/system/ulp/lp_core/gpio_intr_pulse_counter/pytest_lp_core_pcnt.py b/examples/system/ulp/lp_core/gpio_intr_pulse_counter/pytest_lp_core_pcnt.py index 8b3e00f60f4c..2885f81958ff 100644 --- a/examples/system/ulp/lp_core/gpio_intr_pulse_counter/pytest_lp_core_pcnt.py +++ b/examples/system/ulp/lp_core/gpio_intr_pulse_counter/pytest_lp_core_pcnt.py @@ -9,6 +9,7 @@ @pytest.mark.generic @idf_parametrize('target', ['esp32c6', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_pcnt(dut: Dut) -> None: res = dut.expect(r'ULP will wake up processor after every (\d+) pulses') wakeup_limit = res.group(1).decode('utf-8') diff --git a/examples/system/ulp/lp_core/inter_cpu_critical_section/pytest_lp_core_critical_section.py b/examples/system/ulp/lp_core/inter_cpu_critical_section/pytest_lp_core_critical_section.py index 8fabae0eb9d3..0562a97061cb 100644 --- a/examples/system/ulp/lp_core/inter_cpu_critical_section/pytest_lp_core_critical_section.py +++ b/examples/system/ulp/lp_core/inter_cpu_critical_section/pytest_lp_core_critical_section.py @@ -16,6 +16,7 @@ def test_lp_core_critical_section_main_1_task(dut: Dut) -> None: @pytest.mark.generic @idf_parametrize('target', ['esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_critical_section_main_2_tasks(dut: Dut) -> None: dut.expect("LP CPU's increment starts, shared counter = 0") dut.expect(r'core 0 started, cnt = \d+') diff --git a/examples/system/ulp/lp_core/interrupt/pytest_lp_core_intr.py b/examples/system/ulp/lp_core/interrupt/pytest_lp_core_intr.py index 622198c941cd..a3c971dffd58 100644 --- a/examples/system/ulp/lp_core/interrupt/pytest_lp_core_intr.py +++ b/examples/system/ulp/lp_core/interrupt/pytest_lp_core_intr.py @@ -7,5 +7,6 @@ @pytest.mark.generic @idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_lp_core_intr(dut: Dut) -> None: dut.expect('Triggered 10 interrupts on the LP-Core, LP-Core received 10 interrupts') diff --git a/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml b/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml index 83dc426fa5c8..0baec0864184 100644 --- a/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml +++ b/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml @@ -19,7 +19,5 @@ no_runner_tags: - esp32c61,jtag - esp32c61,usb_serial_jtag - esp32h2,jtag - - esp32p4,* - esp32p4,jtag - - esp32p4_2,* - esp32s2,usb_host_flash_disk diff --git a/tools/ci/idf_pytest/constants.py b/tools/ci/idf_pytest/constants.py index 68ab0df6d0c3..c6c042b40ee1 100644 --- a/tools/ci/idf_pytest/constants.py +++ b/tools/ci/idf_pytest/constants.py @@ -149,6 +149,7 @@ 'esp32c3eco7': 'esp32c3 major version(v1.1) chips', 'esp32c2eco4': 'esp32c2 major version(v2.0) chips', 'recovery_bootloader': 'Runner with recovery bootloader offset set in eFuse', + 'esp32p4_eco4': 'Runner with esp32p4 eco4 connected', } # by default the timeout is 1h, for some special cases we need to extend it diff --git a/tools/ci/idf_pytest/plugin.py b/tools/ci/idf_pytest/plugin.py index cfbeca5e4d97..77a14526cc05 100644 --- a/tools/ci/idf_pytest/plugin.py +++ b/tools/ci/idf_pytest/plugin.py @@ -25,12 +25,12 @@ from pytest_ignore_test_results.ignore_results import ChildCase from pytest_ignore_test_results.ignore_results import ChildCasesStashKey -from .constants import CollectMode from .constants import DEFAULT_SDKCONFIG from .constants import PREVIEW_TARGETS +from .constants import SUPPORTED_TARGETS +from .constants import CollectMode from .constants import PytestApp from .constants import PytestCase -from .constants import SUPPORTED_TARGETS from .utils import comma_sep_str_to_list from .utils import format_case_id from .utils import merge_junit_files @@ -82,7 +82,11 @@ def __init__( self._single_target_duplicate_mode = single_target_duplicate_mode self.apps_list = ( - [os.path.join(idf_relpath(app.app_dir), app.build_dir) for app in apps if app.build_status == BuildStatus.SUCCESS] + [ + os.path.join(idf_relpath(app.app_dir), app.build_dir) + for app in apps + if app.build_status == BuildStatus.SUCCESS + ] if apps is not None else None ) @@ -137,7 +141,7 @@ def item_to_pytest_case(self, item: Function) -> t.Optional[PytestCase]: return PytestCase( apps=[PytestApp(app_paths[i], targets[i], configs[i]) for i in range(count)], item=item, - multi_dut_without_param=multi_dut_without_param + multi_dut_without_param=multi_dut_without_param, ) def pytest_collectstart(self) -> None: @@ -270,9 +274,10 @@ def pytest_collection_modifyitems(self, items: t.List[Function]) -> None: case = item_to_case_dict[item] target = self.get_param(item, 'target', None) if ( - not case.is_single_dut_test_case and - target is not None and - target not in case.skip_targets + not case.is_single_dut_test_case + and target is not None + and target not in case.skip_targets + and not any([_t in target for _t in case.skip_targets if '|' not in _t]) ): filtered_items.append(item) items[:] = filtered_items diff --git a/tools/test_apps/system/.build-test-rules.yml b/tools/test_apps/system/.build-test-rules.yml index b28e22b837c0..2770141fb73a 100644 --- a/tools/test_apps/system/.build-test-rules.yml +++ b/tools/test_apps/system/.build-test-rules.yml @@ -13,9 +13,9 @@ tools/test_apps/system/build_test: tools/test_apps/system/clang_build_test: enable: - - if: IDF_TARGET in ["esp32", "esp32s2", "esp32s3", "esp32c2", "esp32c3", "esp32c5", "esp32c6", "esp32h2", "esp32p4"] + - if: IDF_TARGET in ["esp32", "esp32s2", "esp32s3", "esp32c2", "esp32c3", "esp32c5", "esp32c6", "esp32h2"] temporary: true - reason: the other targets are not supported yet + reason: the other targets are not supported yet, esp32p4 # TODO: IDF-14355 tools/test_apps/system/cxx_no_except: enable: @@ -27,6 +27,10 @@ tools/test_apps/system/eh_frame: disable: - if: IDF_TARGET in ["esp32", "esp32s2", "esp32s3", "linux"] reason: Only relevant for riscv targets + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14424 tools/test_apps/system/esp_intr_dump: @@ -61,6 +65,12 @@ tools/test_apps/system/gdb_loadable_elf: temporary: true reason: target esp32c6, esp32h2 is not supported yet +tools/test_apps/system/gdbstub_runtime: + disable_test: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-13142 + tools/test_apps/system/log: disable_test: - if: IDF_TARGET not in ["esp32", "esp32c3"] @@ -95,7 +105,15 @@ tools/test_apps/system/no_embedded_paths: tools/test_apps/system/panic: enable: - - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32p4", "esp32c61", "esp32h21"] # preview targets + - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32p4"] # preview targets + disable: + - if: IDF_TARGET == "esp32p4" # TODO: IDF-14348 + +tools/test_apps/system/ram_loadable_app: + disable: + - if: IDF_TARGET == "esp32p4" + temporary: true + reason: p4 rev3 migration # TODO: IDF-14370 tools/test_apps/system/rtc_mem_reserve: enable: diff --git a/tools/test_apps/system/clang_build_test/README.md b/tools/test_apps/system/clang_build_test/README.md index c410436a3a4c..99461edd6069 100644 --- a/tools/test_apps/system/clang_build_test/README.md +++ b/tools/test_apps/system/clang_build_test/README.md @@ -1,4 +1,4 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | This project is for testing if the application can be built with Clang toolchain. diff --git a/tools/test_apps/system/eh_frame/pytest_eh_frame.py b/tools/test_apps/system/eh_frame/pytest_eh_frame.py index f70b715e3556..92de8630dc5f 100644 --- a/tools/test_apps/system/eh_frame/pytest_eh_frame.py +++ b/tools/test_apps/system/eh_frame/pytest_eh_frame.py @@ -9,9 +9,10 @@ @idf_parametrize( 'target', ['esp32c2', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32c61', 'esp32h2', 'esp32p4'], indirect=['target'] ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14424') def test_eh_frame_wdt(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') - dut.confirm_write('"Test task wdt can print backtrace with eh-frame"', expect_str=f'Running') + dut.confirm_write('"Test task wdt can print backtrace with eh-frame"', expect_str='Running') # Expect a backtrace which is at least 3 PC-SP pairs deep dut.expect(r'Backtrace: (0x[a-fA-F0-9]+:0x[a-fA-F0-9]+\s*){3,}') @@ -21,9 +22,10 @@ def test_eh_frame_wdt(dut: Dut) -> None: @idf_parametrize( 'target', ['esp32c2', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32c61', 'esp32h2', 'esp32p4'], indirect=['target'] ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14424') def test_eh_frame_panic(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') - dut.confirm_write('"Test panic can print backtrace with eh-frame"', expect_str=f'Running') + dut.confirm_write('"Test panic can print backtrace with eh-frame"', expect_str='Running') # Expect a backtrace which is at least 3 PC-SP pairs deep dut.expect(r'Backtrace: (0x[a-fA-F0-9]+:0x[a-fA-F0-9]+\s*){3,}') diff --git a/tools/test_apps/system/gdbstub_runtime/pytest_gdbstub_runtime.py b/tools/test_apps/system/gdbstub_runtime/pytest_gdbstub_runtime.py index afa68d1b5399..34747df52de2 100644 --- a/tools/test_apps/system/gdbstub_runtime/pytest_gdbstub_runtime.py +++ b/tools/test_apps/system/gdbstub_runtime/pytest_gdbstub_runtime.py @@ -41,6 +41,7 @@ def run_and_break(dut: PanicTestDut, cmd: str) -> Dict[Any, Any]: @pytest.mark.generic @idf_parametrize('target', ['esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-13142') def test_hwloop_jump(dut: PanicTestDut) -> None: start_gdb(dut) @@ -100,6 +101,7 @@ def test_hwloop_jump(dut: PanicTestDut) -> None: @pytest.mark.generic @idf_parametrize('target', ['supported_targets'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-13142') def test_gdbstub_runtime(dut: PanicTestDut) -> None: start_gdb(dut) @@ -202,7 +204,9 @@ def test_gdbstub_runtime(dut: PanicTestDut) -> None: @pytest.mark.generic -@pytest.mark.temp_skip_ci(targets=['esp32', 'esp32s2', 'esp32s3'], reason='fix IDF-7927') +@pytest.mark.temp_skip_ci( + targets=['esp32', 'esp32s2', 'esp32s3', 'esp32p4'], reason='fix IDF-7927, p4 rev3 migration, IDF-13142' +) @idf_parametrize('target', ['esp32', 'esp32s2', 'esp32s3'], indirect=['target']) def test_gdbstub_runtime_xtensa_stepping_bug(dut: PanicTestDut) -> None: start_gdb(dut) diff --git a/tools/test_apps/system/panic/README.md b/tools/test_apps/system/panic/README.md index abc7746d75ce..574b9f3fc159 100644 --- a/tools/test_apps/system/panic/README.md +++ b/tools/test_apps/system/panic/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | # Introduction diff --git a/tools/test_apps/system/panic/pytest_panic.py b/tools/test_apps/system/panic/pytest_panic.py index 6720f13963bd..51d4d0067757 100644 --- a/tools/test_apps/system/panic/pytest_panic.py +++ b/tools/test_apps/system/panic/pytest_panic.py @@ -185,6 +185,7 @@ def common_test( @pytest.mark.generic @idf_parametrize('config, target', CONFIGS, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_task_wdt_cpu0(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) dut.expect_exact('Task watchdog got triggered. The following tasks/users did not reset the watchdog in time:') @@ -217,6 +218,7 @@ def test_task_wdt_cpu0(dut: PanicTestDut, config: str, test_func_name: str) -> N @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_DUAL_CORE, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_task_wdt_cpu1(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) dut.expect_exact('Task watchdog got triggered. The following tasks/users did not reset the watchdog in time:') @@ -254,6 +256,7 @@ def test_task_wdt_cpu1(dut: PanicTestDut, config: str, test_func_name: str) -> N ], indirect=['config', 'target'], ) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_panic_extram_stack(dut: PanicTestDut, config: str) -> None: if 'heap' in config: dut.run_test_func('test_panic_extram_stack_heap') @@ -281,6 +284,7 @@ def test_panic_extram_stack(dut: PanicTestDut, config: str) -> None: @pytest.mark.generic @idf_parametrize('config, target', CONFIGS, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_int_wdt(dut: PanicTestDut, target: str, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) dut.expect_gme('Interrupt wdt timeout on CPU0') @@ -303,6 +307,7 @@ def test_int_wdt(dut: PanicTestDut, target: str, config: str, test_func_name: st @pytest.mark.generic @idf_parametrize('config, target', CONFIGS, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_int_wdt_cache_disabled(dut: PanicTestDut, target: str, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) dut.expect_gme('Interrupt wdt timeout on CPU0') @@ -325,6 +330,7 @@ def test_int_wdt_cache_disabled(dut: PanicTestDut, target: str, config: str, tes @pytest.mark.generic @idf_parametrize('config, target', CONFIGS, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_cache_error(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) if dut.target in ['esp32c3', 'esp32c2']: @@ -356,6 +362,7 @@ def test_cache_error(dut: PanicTestDut, config: str, test_func_name: str) -> Non @pytest.mark.generic @idf_parametrize('config, target', CONFIGS, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_stack_overflow(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) if dut.is_xtensa: @@ -377,6 +384,7 @@ def test_stack_overflow(dut: PanicTestDut, config: str, test_func_name: str) -> @pytest.mark.generic @idf_parametrize('config, target', CONFIGS, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_instr_fetch_prohibited(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) if dut.is_xtensa: @@ -404,6 +412,7 @@ def test_instr_fetch_prohibited(dut: PanicTestDut, config: str, test_func_name: @pytest.mark.generic @idf_parametrize('config, target', CONFIGS, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_illegal_instruction(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) if dut.is_xtensa: @@ -440,18 +449,21 @@ def check_x_prohibited(dut: PanicTestDut, config: str, test_func_name: str, oper @pytest.mark.generic @idf_parametrize('config, target', CONFIGS, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_storeprohibited(dut: PanicTestDut, config: str, test_func_name: str) -> None: check_x_prohibited(dut, config, test_func_name, 'Store') @pytest.mark.generic @idf_parametrize('config, target', CONFIGS, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_loadprohibited(dut: PanicTestDut, config: str, test_func_name: str) -> None: check_x_prohibited(dut, config, test_func_name, 'Load') @pytest.mark.generic @idf_parametrize('config, target', CONFIGS, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_abort(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) regex_pattern = rb'abort\(\) was called at PC [0-9xa-f]+ on core 0' @@ -474,6 +486,7 @@ def test_abort(dut: PanicTestDut, config: str, test_func_name: str) -> None: @pytest.mark.generic @idf_parametrize('config, target', CONFIGS, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_ub(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) regex_pattern = rb'Undefined behavior of type out_of_bounds' @@ -502,6 +515,7 @@ def test_ub(dut: PanicTestDut, config: str, test_func_name: str) -> None: @pytest.mark.generic @idf_parametrize('config, target', CONFIGS, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_abort_cache_disabled(dut: PanicTestDut, config: str, test_func_name: str) -> None: if dut.target == 'esp32s2': pytest.xfail(reason='Crashes in itoa which is not in ROM, IDF-3572') @@ -526,6 +540,7 @@ def test_abort_cache_disabled(dut: PanicTestDut, config: str, test_func_name: st @pytest.mark.generic @idf_parametrize('config, target', CONFIGS, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_assert(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) regex_pattern = rb'assert failed:[\s\w()]*?\s[.\w/]*\.(?:c|cpp|h|hpp):\d.*$' @@ -548,6 +563,7 @@ def test_assert(dut: PanicTestDut, config: str, test_func_name: str) -> None: @pytest.mark.generic @idf_parametrize('config, target', CONFIGS, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_assert_cache_disabled(dut: PanicTestDut, config: str, test_func_name: str) -> None: if dut.target == 'esp32s2': pytest.xfail(reason='Crashes in itoa which is not in ROM, IDF-3572') @@ -585,6 +601,7 @@ def cache_error_log_check(dut: PanicTestDut) -> None: @pytest.mark.generic @idf_parametrize('config, target', CONFIG_PANIC, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_assert_cache_write_back_error_can_print_backtrace(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) cache_error_log_check(dut) @@ -593,6 +610,7 @@ def test_assert_cache_write_back_error_can_print_backtrace(dut: PanicTestDut, co @pytest.mark.generic @pytest.mark.parametrize('config', ['panic_delay'], indirect=True) @idf_parametrize('target', ['esp32'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_panic_delay(dut: PanicTestDut) -> None: dut.run_test_func('test_storeprohibited') try: @@ -610,6 +628,7 @@ def test_panic_delay(dut: PanicTestDut) -> None: @pytest.mark.generic @idf_parametrize('config, target', CONFIG_PANIC, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_panic_handler_stuck0(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) @@ -622,6 +641,7 @@ def test_panic_handler_stuck0(dut: PanicTestDut, config: str, test_func_name: st @pytest.mark.generic @idf_parametrize('config, target', CONFIG_PANIC_DUAL_CORE, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_panic_handler_stuck1(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) @@ -634,6 +654,7 @@ def test_panic_handler_stuck1(dut: PanicTestDut, config: str, test_func_name: st @pytest.mark.generic @idf_parametrize('config, target', CONFIG_PANIC, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_panic_handler_crash0(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) @@ -652,6 +673,7 @@ def test_panic_handler_crash0(dut: PanicTestDut, config: str, test_func_name: st @pytest.mark.generic @idf_parametrize('config, target', CONFIG_PANIC_DUAL_CORE, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_panic_handler_crash1(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) @@ -756,6 +778,7 @@ def test_panic_handler_crash1(dut: PanicTestDut, config: str, test_func_name: st @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_MEMPROT_DCACHE, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_dcache_read_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) dut.expect_exact(r'Test error: Test function has returned') @@ -766,6 +789,7 @@ def test_dcache_read_violation(dut: PanicTestDut, test_func_name: str) -> None: @pytest.mark.generic @pytest.mark.xfail('config.getvalue("target") == "esp32s2"', reason='Incorrect panic reason may be observed', run=False) @idf_parametrize('config, target', CONFIGS_MEMPROT_DCACHE, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_dcache_write_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) dut.expect_gme('Memory protection fault') @@ -777,6 +801,7 @@ def test_dcache_write_violation(dut: PanicTestDut, test_func_name: str) -> None: @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_MEMPROT_IDRAM, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_iram_reg1_write_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) @@ -797,6 +822,7 @@ def test_iram_reg1_write_violation(dut: PanicTestDut, test_func_name: str) -> No @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_MEMPROT_IDRAM, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_iram_reg2_write_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) @@ -822,6 +848,7 @@ def test_iram_reg2_write_violation(dut: PanicTestDut, test_func_name: str) -> No @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_MEMPROT_IDRAM, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_iram_reg3_write_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) @@ -849,6 +876,7 @@ def test_iram_reg3_write_violation(dut: PanicTestDut, test_func_name: str) -> No @pytest.mark.generic @pytest.mark.xfail('config.getvalue("target") == "esp32s2"', reason='Incorrect panic reason may be observed', run=False) @idf_parametrize('config, target', CONFIGS_MEMPROT_IDRAM, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_iram_reg4_write_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) @@ -878,6 +906,7 @@ def test_iram_reg4_write_violation(dut: PanicTestDut, test_func_name: str) -> No 'config.getvalue("target") == "esp32s2"', reason='Multiple panic reasons for the same test may surface', run=False ) @idf_parametrize('config, target', CONFIGS_MEMPROT_IDRAM, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_dram_reg1_execute_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) @@ -900,6 +929,7 @@ def test_dram_reg1_execute_violation(dut: PanicTestDut, test_func_name: str) -> 'config.getvalue("target") == "esp32s2"', reason='Multiple panic reasons for the same test may surface', run=False ) @idf_parametrize('config, target', CONFIGS_MEMPROT_IDRAM, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_dram_reg2_execute_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) @@ -917,6 +947,7 @@ def test_dram_reg2_execute_violation(dut: PanicTestDut, test_func_name: str) -> @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_MEMPROT_RTC_FAST_MEM, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_rtc_fast_reg1_execute_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) dut.expect_exact(r'Test error: Test function has returned') @@ -929,6 +960,7 @@ def test_rtc_fast_reg1_execute_violation(dut: PanicTestDut, test_func_name: str) reason='Not a violation condition, no PMS peripheral case', ) @idf_parametrize('config, target', CONFIGS_MEMPROT_RTC_FAST_MEM, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_rtc_fast_reg2_execute_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) dut.expect_gme('Memory protection fault') @@ -953,6 +985,7 @@ def test_rtc_fast_reg2_execute_violation(dut: PanicTestDut, test_func_name: str) 'config.getvalue("target") == "esp32s2"', reason='Multiple panic reasons for the same test may surface', run=False ) @idf_parametrize('config, target', CONFIGS_MEMPROT_RTC_FAST_MEM, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_rtc_fast_reg3_execute_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) @@ -978,6 +1011,7 @@ def test_rtc_fast_reg3_execute_violation(dut: PanicTestDut, test_func_name: str) @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_MEMPROT_RTC_SLOW_MEM, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_rtc_slow_reg1_execute_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) dut.expect_gme('Memory protection fault') @@ -989,6 +1023,7 @@ def test_rtc_slow_reg1_execute_violation(dut: PanicTestDut, test_func_name: str) @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_MEMPROT_RTC_SLOW_MEM, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_rtc_slow_reg2_execute_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) dut.expect_gme('Memory protection fault') @@ -1000,6 +1035,7 @@ def test_rtc_slow_reg2_execute_violation(dut: PanicTestDut, test_func_name: str) @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_MEMPROT_FLASH_IDROM, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_irom_reg_write_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) dut.expect_gme('Store access fault') @@ -1009,6 +1045,7 @@ def test_irom_reg_write_violation(dut: PanicTestDut, test_func_name: str) -> Non @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_MEMPROT_FLASH_IDROM, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_drom_reg_write_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) dut.expect_gme('Store access fault') @@ -1018,6 +1055,7 @@ def test_drom_reg_write_violation(dut: PanicTestDut, test_func_name: str) -> Non @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_MEMPROT_FLASH_IDROM, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_drom_reg_execute_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) dut.expect_gme('Instruction access fault') @@ -1027,6 +1065,7 @@ def test_drom_reg_execute_violation(dut: PanicTestDut, test_func_name: str) -> N @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_MEMPROT_SPIRAM_XIP_IROM_ALIGNMENT_HEAP, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_spiram_xip_irom_alignment_reg_execute_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) try: @@ -1039,6 +1078,7 @@ def test_spiram_xip_irom_alignment_reg_execute_violation(dut: PanicTestDut, test @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_MEMPROT_SPIRAM_XIP_DROM_ALIGNMENT_HEAP, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_spiram_xip_drom_alignment_reg_execute_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) try: @@ -1054,6 +1094,7 @@ def test_spiram_xip_drom_alignment_reg_execute_violation(dut: PanicTestDut, test @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_MEMPROT_INVALID_REGION_PROTECTION_USING_PMA, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_invalid_memory_region_write_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) dut.expect_gme('Store access fault') @@ -1063,6 +1104,7 @@ def test_invalid_memory_region_write_violation(dut: PanicTestDut, test_func_name @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_MEMPROT_INVALID_REGION_PROTECTION_USING_PMA, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_invalid_memory_region_execute_violation(dut: PanicTestDut, test_func_name: str) -> None: dut.run_test_func(test_func_name) dut.expect_gme('Instruction access fault') @@ -1079,6 +1121,7 @@ def test_gdbstub_coredump(dut: PanicTestDut) -> None: common_test(dut, 'gdbstub_coredump', get_default_backtrace(test_func_name)) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_hw_stack_guard_cpu(dut: PanicTestDut, cpu: int) -> None: dut.expect_exact(f"Guru Meditation Error: Core {cpu} panic'ed (Stack protection fault).") dut.expect_none('ASSIST_DEBUG is not triggered BUT interrupt occurred!') @@ -1098,6 +1141,7 @@ def test_hw_stack_guard_cpu(dut: PanicTestDut, cpu: int) -> None: @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_HW_STACK_GUARD, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_hw_stack_guard_cpu0(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) test_hw_stack_guard_cpu(dut, 0) @@ -1106,6 +1150,7 @@ def test_hw_stack_guard_cpu0(dut: PanicTestDut, config: str, test_func_name: str @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_HW_STACK_GUARD_DUAL_CORE, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_hw_stack_guard_cpu1(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) test_hw_stack_guard_cpu(dut, 1) @@ -1128,6 +1173,7 @@ def test_illegal_access(dut: PanicTestDut, config: str, test_func_name: str) -> @pytest.mark.generic @idf_parametrize('config, target', CONFIG_CAPTURE_DRAM, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_capture_dram(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) regex_pattern = rb'assert failed:[\s\w()]*?\s[.\w/]*\.(?:c|cpp|h|hpp):\d.*$' @@ -1181,12 +1227,14 @@ def _test_coredump_summary(dut: PanicTestDut, flash_encrypted: bool, coredump_en @pytest.mark.generic @idf_parametrize('config, target', CONFIG_COREDUMP_SUMMARY, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_coredump_summary(dut: PanicTestDut) -> None: _test_coredump_summary(dut, False, False) @pytest.mark.flash_encryption @idf_parametrize('config, target', CONFIG_COREDUMP_SUMMARY_FLASH_ENCRYPTED, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_coredump_summary_flash_encrypted(dut: PanicTestDut, config: str) -> None: _test_coredump_summary(dut, True, config == 'coredump_flash_encrypted') @@ -1194,6 +1242,7 @@ def test_coredump_summary_flash_encrypted(dut: PanicTestDut, config: str) -> Non @pytest.mark.generic @idf_parametrize('config', ['coredump_flash_elf_sha'], indirect=['config']) @idf_parametrize('target', TARGETS_ALL, indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_tcb_corrupted(dut: PanicTestDut, target: str, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) if dut.is_xtensa: @@ -1226,6 +1275,7 @@ def test_tcb_corrupted(dut: PanicTestDut, target: str, config: str, test_func_na @pytest.mark.generic @idf_parametrize('config, target', CONFIGS_BACKTRACE, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_panic_print_backtrace(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut.run_test_func(test_func_name) regex_pattern = rb'abort\(\) was called at PC [0-9xa-f]+ on core 0' @@ -1240,6 +1290,7 @@ def test_panic_print_backtrace(dut: PanicTestDut, config: str, test_func_name: s @pytest.mark.generic @idf_parametrize('config, target', CONFIG_PANIC_HALT, indirect=['config', 'target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14348') def test_panic_halt(dut: PanicTestDut) -> None: dut.run_test_func('test_panic_halt') dut.expect_exact('CPU halted.', timeout=30) diff --git a/tools/test_apps/system/ram_loadable_app/README.md b/tools/test_apps/system/ram_loadable_app/README.md index 84892aa9baeb..3e8ac4cc0aca 100644 --- a/tools/test_apps/system/ram_loadable_app/README.md +++ b/tools/test_apps/system/ram_loadable_app/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | # RAM loadable app Example diff --git a/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py b/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py index c01afe1777b2..ba8935c726dd 100644 --- a/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py +++ b/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py @@ -43,6 +43,7 @@ def test_ram_loadable_app(dut: IdfDut) -> None: # Tests with ram_app runners @pytest.mark.ram_app +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14370') @pytest.mark.parametrize( 'config', [ @@ -57,6 +58,7 @@ def test_ram_loadable_app_with_ram_app_runner(dut: IdfDut) -> None: @pytest.mark.ram_app +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration, IDF-14370') @pytest.mark.parametrize( 'config', [ diff --git a/tools/test_apps/system/rtc_mem_reserve/pytest_rtc_mem_reserve.py b/tools/test_apps/system/rtc_mem_reserve/pytest_rtc_mem_reserve.py index a03a14f070cc..409d252794ee 100644 --- a/tools/test_apps/system/rtc_mem_reserve/pytest_rtc_mem_reserve.py +++ b/tools/test_apps/system/rtc_mem_reserve/pytest_rtc_mem_reserve.py @@ -7,5 +7,6 @@ @pytest.mark.generic @idf_parametrize('target', ['esp32p4'], indirect=['target']) +@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14422') def test_rtc_mem_reserve(dut: Dut) -> None: dut.run_all_single_board_cases()