diff --git a/components/bootloader_support/src/bootloader_random_esp32c5.c b/components/bootloader_support/src/bootloader_random_esp32c5.c
index e51923562a36..15c2314413ad 100644
--- a/components/bootloader_support/src/bootloader_random_esp32c5.c
+++ b/components/bootloader_support/src/bootloader_random_esp32c5.c
@@ -11,6 +11,8 @@
 #include "esp_private/regi2c_ctrl.h"
 #include "soc/lpperi_reg.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -30,8 +32,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.unit = ADC_UNIT_1;
diff --git a/components/bootloader_support/src/bootloader_random_esp32c6.c b/components/bootloader_support/src/bootloader_random_esp32c6.c
index efd6ab384a2f..de45f07c327a 100644
--- a/components/bootloader_support/src/bootloader_random_esp32c6.c
+++ b/components/bootloader_support/src/bootloader_random_esp32c6.c
@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.unit = ADC_UNIT_2;
diff --git a/components/bootloader_support/src/bootloader_random_esp32c61.c b/components/bootloader_support/src/bootloader_random_esp32c61.c
index 7bc9322c9433..1f1e2ad9ffad 100644
--- a/components/bootloader_support/src/bootloader_random_esp32c61.c
+++ b/components/bootloader_support/src/bootloader_random_esp32c61.c
@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.unit = ADC_UNIT_1;
diff --git a/components/bootloader_support/src/bootloader_random_esp32h2.c b/components/bootloader_support/src/bootloader_random_esp32h2.c
index 3c6ba78987e4..4c4f5155a70f 100644
--- a/components/bootloader_support/src/bootloader_random_esp32h2.c
+++ b/components/bootloader_support/src/bootloader_random_esp32h2.c
@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.atten = ADC_ATTEN_DB_2_5;
diff --git a/components/bootloader_support/src/bootloader_random_esp32p4.c b/components/bootloader_support/src/bootloader_random_esp32p4.c
index 5fdcb42bcbac..0a9f90ac9dff 100644
--- a/components/bootloader_support/src/bootloader_random_esp32p4.c
+++ b/components/bootloader_support/src/bootloader_random_esp32p4.c
@@ -1,108 +1,88 @@
 /*
  * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
+*
+* SPDX-License-Identifier: Apache-2.0
+*/
+#include "sdkconfig.h"
 #include "bootloader_random.h"
-#include "soc/soc.h"
-#include "soc/adc_reg.h"
-#include "soc/pmu_reg.h"
-#include "soc/regi2c_saradc.h"
-#include "soc/hp_sys_clkrst_reg.h"
-#include "soc/lp_adc_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "esp_rom_regi2c.h"
+#include "hal/regi2c_ctrl_ll.h"
+#include "hal/adc_ll.h"
+#include "hal/adc_types.h"
+#include "hal/config.h"
 
-// TODO IDF-6497: once ADC API is supported, use the API instead of defining functions and constants here
+#include "esp_private/periph_ctrl.h"
+#include "esp_private/adc_share_hw_ctrl.h"
 
-#define I2C_SAR_ADC_INIT_CODE_VAL 2166
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+#include "hal/trng_ll.h"
+#endif
 
-typedef struct {
-    int atten;
-    int channel;
-} pattern_item;
-
-typedef struct {
-    pattern_item item[4];
-} pattern_table;
-
-static void adc1_fix_initcode_set(uint32_t initcode_value)
-{
-    uint32_t msb = initcode_value >> 8;
-    uint32_t lsb = initcode_value & 0xff;
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
-}
-
-//total 4 tables
-static void hpadc_sar1_pattern_table_cfg(unsigned int table_idx, pattern_table table)
-{
-    uint32_t wdata = 0;
-    wdata = (table.item[0].channel << 20 | table.item[0].atten << 18 |
-            table.item[1].channel << 14|table.item[1].atten << 12 |
-            table.item[2].channel << 8 |table.item[2].atten << 6 |
-            table.item[3].channel << 2 |table.item[3].atten);
-    WRITE_PERI_REG(ADC_SAR1_PATT_TAB1_REG + table_idx * 4, wdata);
-}
+#define I2C_SAR_ADC_INIT_CODE_VAL       2166
+#define ADC_RNG_CLKM_DIV_NUM            0
+#define ADC_RNG_CLKM_DIV_B              0
+#define ADC_RNG_CLKM_DIV_A              0
 
 void bootloader_random_enable(void)
 {
-    pattern_table sar1_table[4] = {};
-    uint32_t pattern_len = 0;
-
-    SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_ADC_APB_CLK_EN);
-    SET_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL23_REG, HP_SYS_CLKRST_REG_ADC_CLK_EN);
+    _adc_ll_reset_register();
+    _adc_ll_enable_bus_clock(true);
 
-    SET_PERI_REG_MASK(RTCADC_MEAS1_MUX_REG, RTCADC_SAR1_DIG_FORCE);
-    SET_PERI_REG_MASK(PMU_RF_PWC_REG,PMU_XPD_PERIF_I2C);
+    adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
+    adc_ll_digi_controller_clk_div(0, 0, 0);
 
-    uint32_t sar1_clk_div_num = GET_PERI_REG_BITS2((HP_SYS_CLKRST_PERI_CLK_CTRL24_REG),
-            (HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_M),
-            (HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_S));
-
-    SET_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE); //start force 1
+    // some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
+#ifndef BOOTLOADER_BUILD
+    regi2c_saradc_enable();
+#else
+    regi2c_ctrl_ll_i2c_sar_periph_enable();
+#endif
 
     // enable analog i2c master clock for RNG runtime
     ANALOG_CLOCK_ENABLE();
 
-    adc1_fix_initcode_set(I2C_SAR_ADC_INIT_CODE_VAL);
-
-    //  cfg pattern table
-    sar1_table[0].item[0].channel = 10; //rand() % 6;
-    sar1_table[0].item[0].atten = 3;
-    sar1_table[0].item[1].channel = 10;
-    sar1_table[0].item[1].atten = 3;
-    sar1_table[0].item[2].channel = 10;
-    sar1_table[0].item[2].atten = 3;
-    sar1_table[0].item[3].channel = 10;
-    sar1_table[0].item[3].atten = 3;
-
-    hpadc_sar1_pattern_table_cfg(0, sar1_table[0]);
-    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_SAR1_PATT_LEN, pattern_len, ADC_SAR1_PATT_LEN_S);
-
-    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR1_FORCE, 3, ADC_XPD_SAR1_FORCE_S);
-    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR2_FORCE, 3, ADC_XPD_SAR2_FORCE_S);
-
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, 1);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, 0);
-
-    CLEAR_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE);
-    SET_PERI_REG_MASK(ADC_CTRL2_REG, ADC_TIMER_EN);
-    SET_PERI_REG_BITS(ADC_CTRL2_REG, ADC_TIMER_TARGET, sar1_clk_div_num * 25, ADC_TIMER_TARGET_S);
-
-    while (GET_PERI_REG_MASK(ADC_INT_RAW_REG, ADC_SAR1_DONE_INT_RAW) == 0) { }
-
-    SET_PERI_REG_MASK(ADC_INT_CLR_REG, ADC_APB_SARADC1_DONE_INT_CLR);
+    adc_ll_regi2c_init();
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+
+    adc_digi_pattern_config_t pattern_config = {};
+    pattern_config.unit = ADC_UNIT_1;
+    pattern_config.atten = ADC_ATTEN_DB_12;
+    pattern_config.channel = ADC_CHANNEL_10;
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 1, pattern_config);
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 2, pattern_config);
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 3, pattern_config);
+    adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, 1);
+
+    adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_DIG);
+    adc_ll_digi_set_power_manage(ADC_UNIT_1, ADC_LL_POWER_SW_ON);
+
+    adc_ll_digi_set_clk_div(15);
+    adc_ll_digi_set_trigger_interval(100);
+    adc_ll_digi_trigger_enable();
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    trng_ll_enable();
+#endif
 }
 
 void bootloader_random_disable(void)
 {
+    adc_ll_digi_trigger_disable();
+    adc_ll_digi_reset_pattern_table();
+    adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);
+    adc_ll_set_calibration_param(ADC_UNIT_2, 0x0);
+    adc_ll_regi2c_adc_deinit();
+
+#ifndef BOOTLOADER_BUILD
+    regi2c_saradc_disable();
+#endif
+
     // disable analog i2c master clock
     ANALOG_CLOCK_DISABLE();
+    adc_ll_digi_controller_clk_div(4, 0, 0);
+    adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
+    adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_ULP);
 
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0);
-
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, 0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, 0);
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    trng_ll_disable();
+#endif
 }
diff --git a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
index 163dadd20761..bd7511fa91a4 100644
--- a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
+++ b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
@@ -43,6 +43,7 @@
 #include "hal/lpwdt_ll.h"
 #include "hal/regi2c_ctrl_ll.h"
 #include "hal/brownout_ll.h"
+#include "hal/axi_icm_ll.h"
 
 static const char *TAG = "boot.esp32c5";
 
@@ -85,6 +86,9 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
+    // Clear bit reset_event_bypass to ensure that the system bus is also reset during a core reset (WDT),
+    // preventing bus freezing caused by an incorrect MSPI core reset in ROM.
+    axi_icm_ll_reset_with_core_reset(true);
     _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
     regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-8667 Remove this?
     regi2c_ctrl_ll_master_configure_clock();
diff --git a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
index 449649b71458..55137ac2e65f 100644
--- a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
+++ b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
@@ -44,6 +44,7 @@
 #include "hal/lpwdt_ll.h"
 #include "hal/regi2c_ctrl_ll.h"
 #include "hal/brownout_ll.h"
+#include "hal/axi_icm_ll.h"
 
 static const char *TAG = "boot.esp32c61";
 
@@ -86,6 +87,9 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
+    // Clear bit reset_event_bypass to ensure that the system bus is also reset during a core reset (WDT),
+    // preventing bus freezing caused by an incorrect MSPI core reset in ROM.
+    axi_icm_ll_reset_with_core_reset(true);
     _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
     regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
     regi2c_ctrl_ll_master_configure_clock();
diff --git a/components/bt/common/include/bt_common.h b/components/bt/common/include/bt_common.h
index 300bbc6d8513..d8fb107878ea 100644
--- a/components/bt/common/include/bt_common.h
+++ b/components/bt/common/include/bt_common.h
@@ -238,6 +238,7 @@ typedef uint64_t UINT64;
 typedef bool BOOLEAN;
 /* Maximum UUID size - 16 bytes, and structure to hold any type of UUID. */
 #define MAX_UUID_SIZE              16
+#define MAX_UUID_NUM               32
 
 typedef struct {
 #define LEN_UUID_16     2
diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_act.c b/components/bt/host/bluedroid/bta/dm/bta_dm_act.c
index 3ec7ae2aff5a..c0383286a206 100644
--- a/components/bt/host/bluedroid/bta/dm/bta_dm_act.c
+++ b/components/bt/host/bluedroid/bta/dm/bta_dm_act.c
@@ -2056,7 +2056,7 @@ void bta_dm_sdp_result (tBTA_DM_MSG *p_data)
 #endif
 
     UINT32 num_uuids = 0;
-    UINT8  uuid_list[32][MAX_UUID_SIZE]; // assuming a max of 32 services
+    UINT8  uuid_list[MAX_UUID_NUM][MAX_UUID_SIZE]; // assuming a max of MAX_UUID_NUM services
 
     if ((p_data->sdp_event.sdp_result == SDP_SUCCESS)
             || (p_data->sdp_event.sdp_result == SDP_NO_RECS_MATCH)
@@ -2119,8 +2119,12 @@ void bta_dm_sdp_result (tBTA_DM_MSG *p_data)
                             (tBTA_SERVICE_MASK)(BTA_SERVICE_ID_TO_SERVICE_MASK(bta_dm_search_cb.service_index - 1));
                         tmp_svc = bta_service_id_to_uuid_lkup_tbl[bta_dm_search_cb.service_index - 1];
                         /* Add to the list of UUIDs */
-                        sdpu_uuid16_to_uuid128(tmp_svc, uuid_list[num_uuids]);
-                        num_uuids++;
+                        if (num_uuids < MAX_UUID_NUM) {
+                            sdpu_uuid16_to_uuid128(tmp_svc, uuid_list[num_uuids]);
+                            num_uuids++;
+                        } else {
+                            APPL_TRACE_WARNING("only process the first %d records\n", MAX_UUID_NUM);
+                        }
                     }
                 }
             }
@@ -2154,8 +2158,13 @@ void bta_dm_sdp_result (tBTA_DM_MSG *p_data)
                 p_sdp_rec = SDP_FindServiceInDb_128bit(bta_dm_search_cb.p_sdp_db, p_sdp_rec);
                 if (p_sdp_rec) {
                     if (SDP_FindServiceUUIDInRec_128bit(p_sdp_rec, &temp_uuid)) {
-                        memcpy(uuid_list[num_uuids], temp_uuid.uu.uuid128, MAX_UUID_SIZE);
-                        num_uuids++;
+                        if (num_uuids < MAX_UUID_NUM) {
+                            memcpy(uuid_list[num_uuids], temp_uuid.uu.uuid128, MAX_UUID_SIZE);
+                            num_uuids++;
+                        } else {
+                            APPL_TRACE_WARNING("only process the first %d records\n", MAX_UUID_NUM);
+                            break;
+                        }
                     }
                 }
             } while (p_sdp_rec);
diff --git a/components/cxx/test_apps/.build-test-rules.yml b/components/cxx/test_apps/.build-test-rules.yml
index d21ee93145d5..fb9b59cba276 100644
--- a/components/cxx/test_apps/.build-test-rules.yml
+++ b/components/cxx/test_apps/.build-test-rules.yml
@@ -2,10 +2,6 @@
 
 components/cxx/test_apps:
   enable:
-    - if: IDF_TARGET in ["esp32", "esp32c3"]
+    - if: IDF_TARGET in ["esp32", "esp32c3", "esp32p4"]
       temporary: true
       reason: the other targets are not tested yet
-  disable:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: p4 rev3 migration # TODO: IDF-14402
diff --git a/components/cxx/test_apps/exception/README.md b/components/cxx/test_apps/exception/README.md
index 1fb88efd154b..4a9124336874 100644
--- a/components/cxx/test_apps/exception/README.md
+++ b/components/cxx/test_apps/exception/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C3 |
-| ----------------- | ----- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-P4 |
+| ----------------- | ----- | -------- | -------- |
diff --git a/components/cxx/test_apps/exception/main/test_exception.cpp b/components/cxx/test_apps/exception/main/test_exception.cpp
index d0ef7166c706..6e353ce67350 100644
--- a/components/cxx/test_apps/exception/main/test_exception.cpp
+++ b/components/cxx/test_apps/exception/main/test_exception.cpp
@@ -13,7 +13,7 @@
    - 88 bytes are allocated by pthread_setspecific() to init internal lock
    - some more memory...
    */
-#if CONFIG_IDF_TARGET_ESP32
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32P4
 #define LEAKS (300)
 #elif CONFIG_IDF_TARGET_ESP32S2
 #define LEAKS (800)
diff --git a/components/cxx/test_apps/exception/pytest_cxx_exception.py b/components/cxx/test_apps/exception/pytest_cxx_exception.py
index e89f3c561a93..2e49b119811c 100644
--- a/components/cxx/test_apps/exception/pytest_cxx_exception.py
+++ b/components/cxx/test_apps/exception/pytest_cxx_exception.py
@@ -6,6 +6,6 @@
 
 
 @pytest.mark.generic
-@idf_parametrize('target', ['esp32', 'esp32c3'], indirect=['target'])
+@idf_parametrize('target', ['esp32', 'esp32c3', 'esp32p4'], indirect=['target'])
 def test_cxx_exception(dut: Dut) -> None:
     dut.run_all_single_board_cases()
diff --git a/components/cxx/test_apps/exception_no_except/README.md b/components/cxx/test_apps/exception_no_except/README.md
index 1fb88efd154b..4a9124336874 100644
--- a/components/cxx/test_apps/exception_no_except/README.md
+++ b/components/cxx/test_apps/exception_no_except/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C3 |
-| ----------------- | ----- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-P4 |
+| ----------------- | ----- | -------- | -------- |
diff --git a/components/cxx/test_apps/exception_no_except/pytest_cxx_exception_no_except.py b/components/cxx/test_apps/exception_no_except/pytest_cxx_exception_no_except.py
index ba8849827b2f..9fde60c34eee 100644
--- a/components/cxx/test_apps/exception_no_except/pytest_cxx_exception_no_except.py
+++ b/components/cxx/test_apps/exception_no_except/pytest_cxx_exception_no_except.py
@@ -6,7 +6,7 @@
 
 
 @pytest.mark.generic
-@idf_parametrize('target', ['esp32', 'esp32c3'], indirect=['target'])
+@idf_parametrize('target', ['esp32', 'esp32c3', 'esp32p4'], indirect=['target'])
 def test_cxx_noexcept_out_of_range(dut: Dut) -> None:
     dut.expect_exact('Press ENTER to see the list of tests')
     dut.write('1')
@@ -15,7 +15,7 @@ def test_cxx_noexcept_out_of_range(dut: Dut) -> None:
 
 
 @pytest.mark.generic
-@idf_parametrize('target', ['esp32', 'esp32c3'], indirect=['target'])
+@idf_parametrize('target', ['esp32', 'esp32c3', 'esp32p4'], indirect=['target'])
 def test_cxx_noexcept_bad_alloc(dut: Dut) -> None:
     dut.expect_exact('Press ENTER to see the list of tests')
     dut.write('2')
diff --git a/components/cxx/test_apps/general/README.md b/components/cxx/test_apps/general/README.md
index 1fb88efd154b..4a9124336874 100644
--- a/components/cxx/test_apps/general/README.md
+++ b/components/cxx/test_apps/general/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C3 |
-| ----------------- | ----- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-P4 |
+| ----------------- | ----- | -------- | -------- |
diff --git a/components/cxx/test_apps/general/main/test_cxx_general.cpp b/components/cxx/test_apps/general/main/test_cxx_general.cpp
index 9d099e6f25e5..882815743624 100644
--- a/components/cxx/test_apps/general/main/test_cxx_general.cpp
+++ b/components/cxx/test_apps/general/main/test_cxx_general.cpp
@@ -108,18 +108,16 @@ TEST_CASE("static initialization guards work as expected", "[misc]")
     TEST_ASSERT_NOT_NULL(s_slow_init_sem);
     int task_count = 0;
     // four tasks competing for static initialization of one object
-    task_count += start_slow_init_task<1>(0, PRO_CPU_NUM);
-#if CONFIG_FREERTOS_NUMBER_OF_CORES == 2
-    task_count += start_slow_init_task<1>(1, APP_CPU_NUM);
-#endif
+    for (int i = 0; i < CONFIG_FREERTOS_NUMBER_OF_CORES; i++) {
+        task_count += start_slow_init_task<1>(i, i);
+    }
     task_count += start_slow_init_task<1>(2, PRO_CPU_NUM);
     task_count += start_slow_init_task<1>(3, tskNO_AFFINITY);
 
     // four tasks competing for static initialization of another object
-    task_count += start_slow_init_task<2>(0, PRO_CPU_NUM);
-#if CONFIG_FREERTOS_NUMBER_OF_CORES == 2
-    task_count += start_slow_init_task<2>(1, APP_CPU_NUM);
-#endif
+    for (int i = 0; i < CONFIG_FREERTOS_NUMBER_OF_CORES; i++) {
+        task_count += start_slow_init_task<2>(i, i);
+    }
     task_count += start_slow_init_task<2>(2, PRO_CPU_NUM);
     task_count += start_slow_init_task<2>(3, tskNO_AFFINITY);
 
diff --git a/components/cxx/test_apps/general/pytest_cxx_general.py b/components/cxx/test_apps/general/pytest_cxx_general.py
index f480ed673cf9..25028e58da9e 100644
--- a/components/cxx/test_apps/general/pytest_cxx_general.py
+++ b/components/cxx/test_apps/general/pytest_cxx_general.py
@@ -9,21 +9,21 @@
 
 @pytest.mark.generic
 @pytest.mark.parametrize('config', configurations, indirect=True)
-@idf_parametrize('target', ['esp32', 'esp32c3'], indirect=['target'])
+@idf_parametrize('target', ['esp32', 'esp32c3', 'esp32p4'], indirect=['target'])
 def test_cxx_static_init_non_pod(dut: Dut) -> None:
     dut.run_all_single_board_cases(name=['can use static initializers for non-POD types'])
 
 
 @pytest.mark.generic
 @pytest.mark.parametrize('config', configurations, indirect=True)
-@idf_parametrize('target', ['esp32', 'esp32c3'], indirect=['target'])
+@idf_parametrize('target', ['esp32', 'esp32c3', 'esp32p4'], indirect=['target'])
 def test_cxx_misc(dut: Dut) -> None:
     dut.run_all_single_board_cases(group='misc')
 
 
 @pytest.mark.generic
 @pytest.mark.parametrize('config', configurations, indirect=True)
-@idf_parametrize('target', ['esp32', 'esp32c3'], indirect=['target'])
+@idf_parametrize('target', ['esp32', 'esp32c3', 'esp32p4'], indirect=['target'])
 def test_cxx_stack_smash(dut: Dut) -> None:
     dut.expect_exact('Press ENTER to see the list of tests')
     dut.write('"stack smashing protection CXX"')
diff --git a/components/cxx/test_apps/rtti/README.md b/components/cxx/test_apps/rtti/README.md
index 1fb88efd154b..4a9124336874 100644
--- a/components/cxx/test_apps/rtti/README.md
+++ b/components/cxx/test_apps/rtti/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C3 |
-| ----------------- | ----- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-P4 |
+| ----------------- | ----- | -------- | -------- |
diff --git a/components/cxx/test_apps/rtti/main/test_rtti.cpp b/components/cxx/test_apps/rtti/main/test_rtti.cpp
index 71d0c3b94947..322d9d9628e4 100644
--- a/components/cxx/test_apps/rtti/main/test_rtti.cpp
+++ b/components/cxx/test_apps/rtti/main/test_rtti.cpp
@@ -14,7 +14,7 @@
    - 88 bytes are allocated by pthread_setspecific() to init internal lock
    - some more memory...
    */
-#if CONFIG_IDF_TARGET_ESP32
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32P4
 #define LEAKS (300)
 #elif CONFIG_IDF_TARGET_ESP32S2
 #define LEAKS (800)
diff --git a/components/cxx/test_apps/rtti/pytest_cxx_rtti.py b/components/cxx/test_apps/rtti/pytest_cxx_rtti.py
index 40ec38cbd027..2672322c9ae8 100644
--- a/components/cxx/test_apps/rtti/pytest_cxx_rtti.py
+++ b/components/cxx/test_apps/rtti/pytest_cxx_rtti.py
@@ -6,6 +6,6 @@
 
 
 @pytest.mark.generic
-@idf_parametrize('target', ['esp32', 'esp32c3'], indirect=['target'])
+@idf_parametrize('target', ['esp32', 'esp32c3', 'esp32p4'], indirect=['target'])
 def test_cxx_rtti(dut: Dut) -> None:
     dut.run_all_single_board_cases()
diff --git a/components/efuse/esp32p4/esp_efuse_rtc_calib.c b/components/efuse/esp32p4/esp_efuse_rtc_calib.c
index 74a6687c375d..2867168c8ac9 100644
--- a/components/efuse/esp32p4/esp_efuse_rtc_calib.c
+++ b/components/efuse/esp32p4/esp_efuse_rtc_calib.c
@@ -22,7 +22,7 @@ int esp_efuse_rtc_calib_get_ver(void)
 {
     uint32_t cali_version = 0;
     uint32_t blk_ver = efuse_hal_blk_version();
-    if (blk_ver >= 1 && blk_ver < 100) {
+    if (blk_ver >= 1) {
         cali_version = ESP_EFUSE_ADC_CALIB_VER1;
     } else {
         ESP_LOGW("eFuse", "calibration efuse version does not match, set default version to 0");
diff --git a/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c b/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c
index 292ac0436425..cc62ad90e152 100644
--- a/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c
+++ b/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c
@@ -308,17 +308,17 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo
 #if SOC_EFUSE_ECDSA_KEY
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
 #endif
-#if SOC_EFUSE_ECDSA_KEY_P192
+#if SOC_EFUSE_ECDSA_KEY_P192 || EFUSE_LL_HAS_ECDSA_KEY_P192
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 ||
 #endif
-#if SOC_EFUSE_ECDSA_KEY_P384
+#if SOC_EFUSE_ECDSA_KEY_P384 || EFUSE_LL_HAS_ECDSA_KEY_P384
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L ||
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H ||
 #endif
-#if SOC_PSRAM_ENCRYPTION_XTS_AES_128
+#if SOC_PSRAM_ENCRYPTION_XTS_AES_128 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_128
             purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY ||
 #endif
-#if SOC_PSRAM_ENCRYPTION_XTS_AES_256
+#if SOC_PSRAM_ENCRYPTION_XTS_AES_256 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_256
             purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 ||
             purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 ||
 #endif
diff --git a/components/efuse/test_apps/.build-test-rules.yml b/components/efuse/test_apps/.build-test-rules.yml
index b3c80820a007..22eeea2060ea 100644
--- a/components/efuse/test_apps/.build-test-rules.yml
+++ b/components/efuse/test_apps/.build-test-rules.yml
@@ -3,10 +3,6 @@
 components/efuse/test_apps:
   enable:
     - if: (INCLUDE_DEFAULT == 1 and SOC_EFUSE_SUPPORTED == 1) or IDF_TARGET == "linux")
-  disable:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: p4 rev3 migration # TODO: IDF-14403
   disable_test:
     - if: IDF_TARGET in ["esp32s2", "esp32s3"]
       reason: eFuse for S2 and S3 is similar to the C3 chip, so we only test for C3.
diff --git a/components/efuse/test_apps/README.md b/components/efuse/test_apps/README.md
index c694e797c7d6..8b53053b4359 100644
--- a/components/efuse/test_apps/README.md
+++ b/components/efuse/test_apps/README.md
@@ -1,3 +1,3 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | Linux |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | ----- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | ----- |
 
diff --git a/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c b/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c
index c27d3d59b74d..074be58411c8 100644
--- a/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c
+++ b/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c
@@ -14,6 +14,7 @@
 #include "esp_efuse.h"
 #include "esp_efuse_table.h"
 #include "esp_efuse_utility.h"
+#include "hal/efuse_ll.h"
 #include "sdkconfig.h"
 
 __attribute__((unused)) static const char* TAG = "efuse_key_test";
@@ -93,17 +94,17 @@ static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key)
 #if SOC_EFUSE_ECDSA_KEY
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
 #endif
-#if SOC_EFUSE_ECDSA_KEY_P192
+#if SOC_EFUSE_ECDSA_KEY_P192 || EFUSE_LL_HAS_ECDSA_KEY_P192
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 ||
 #endif
-#if SOC_EFUSE_ECDSA_KEY_P384
+#if SOC_EFUSE_ECDSA_KEY_P384 || EFUSE_LL_HAS_ECDSA_KEY_P384
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L ||
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H ||
 #endif
-#if SOC_PSRAM_ENCRYPTION_XTS_AES_128
+#if SOC_PSRAM_ENCRYPTION_XTS_AES_128 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_128
             purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY ||
 #endif
-#if SOC_PSRAM_ENCRYPTION_XTS_AES_256
+#if SOC_PSRAM_ENCRYPTION_XTS_AES_256 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_256
             purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 ||
             purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 ||
 #endif
@@ -126,7 +127,7 @@ static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key)
     TEST_ASSERT_EQUAL(purpose, esp_efuse_get_key_purpose(num_key));
     esp_efuse_purpose_t purpose2 = 0;
     const esp_efuse_desc_t** key_purpose = esp_efuse_get_purpose_field(num_key);
-    TEST_ESP_OK(esp_efuse_read_field_blob(key_purpose, &purpose2, key_purpose[0]->bit_count));
+    TEST_ESP_OK(esp_efuse_read_field_blob(key_purpose, &purpose2, esp_efuse_get_field_size(key_purpose)));
     TEST_ASSERT_EQUAL(purpose, purpose2);
     TEST_ASSERT_TRUE(esp_efuse_get_keypurpose_dis_write(num_key));
     return ESP_OK;
diff --git a/components/efuse/test_apps/pytest_efuse.py b/components/efuse/test_apps/pytest_efuse.py
index 0826ecb9c590..7d9c53673598 100644
--- a/components/efuse/test_apps/pytest_efuse.py
+++ b/components/efuse/test_apps/pytest_efuse.py
@@ -6,7 +6,7 @@
 
 
 @pytest.mark.temp_skip_ci(
-    targets=['esp32s2', 'esp32s3', 'esp32p4'],
+    targets=['esp32s2', 'esp32s3'],
     reason='eFuse for S2 and S3 is similar to the C3 chip, so testing on C3 is enough',
 )
 @pytest.mark.generic
diff --git a/components/esp_adc/test_apps/.build-test-rules.yml b/components/esp_adc/test_apps/.build-test-rules.yml
index 3a0b9ebae5b5..aa97546c7d49 100644
--- a/components/esp_adc/test_apps/.build-test-rules.yml
+++ b/components/esp_adc/test_apps/.build-test-rules.yml
@@ -4,10 +4,6 @@ components/esp_adc/test_apps/adc:
   disable:
     - if: SOC_ADC_SUPPORTED != 1
     - if: CONFIG_NAME == "gdma_iram_safe" and IDF_TARGET in ["esp32", "esp32s2", "esp32c2"]
-  disable_test:
-    - if: IDF_TARGET == "esp32p4" and CONFIG_NAME != "esp32p4_eco4"
-      temporary: true
-      reason: p4 rev3 migration # TODO: IDF-14357
   depends_components:
     - esp_adc
     - esp_driver_gpio
diff --git a/components/esp_adc/test_apps/adc/main/test_adc_tsens.c b/components/esp_adc/test_apps/adc/main/test_adc_tsens.c
index ce33491f3ecf..ab2369282d0e 100644
--- a/components/esp_adc/test_apps/adc/main/test_adc_tsens.c
+++ b/components/esp_adc/test_apps/adc/main/test_adc_tsens.c
@@ -29,7 +29,7 @@ static const char *TAG = "adc_tsens";
 
 static int adc_raw[2][10];
 
-TEST_CASE("Test temperature sensor cannot be influenced by ADC", "[adc]")
+TEST_CASE("Test temperature sensor cannot be influenced by ADC", "[adc][ignore]")
 {
     ESP_LOGI(TAG, "Install temperature sensor, expected temp ranger range: 10~50 ℃");
     temperature_sensor_handle_t temp_sensor = NULL;
diff --git a/components/esp_adc/test_apps/adc/pytest_adc.py b/components/esp_adc/test_apps/adc/pytest_adc.py
index 9013a33780bd..3cc1661ac2b3 100644
--- a/components/esp_adc/test_apps/adc/pytest_adc.py
+++ b/components/esp_adc/test_apps/adc/pytest_adc.py
@@ -12,7 +12,6 @@
     ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c5', 'esp32p4', 'esp32c61'],
     indirect=['target'],
 )
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14357')
 def test_adc(dut: Dut) -> None:
     dut.run_all_single_board_cases(timeout=120, reset=True)
 
diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index 768ef06a1f8d..391a7d4063d0 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -183,7 +183,7 @@
 #define DEFAULT_SLEEP_OUT_OVERHEAD_US       (318)
 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (56)
 #elif CONFIG_IDF_TARGET_ESP32C61
-#define DEFAULT_SLEEP_OUT_OVERHEAD_US       (65)
+#define DEFAULT_SLEEP_OUT_OVERHEAD_US       (230)
 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (70)
 #elif CONFIG_IDF_TARGET_ESP32H2
 #define DEFAULT_SLEEP_OUT_OVERHEAD_US       (118)
diff --git a/components/esp_hw_support/test_apps/.build-test-rules.yml b/components/esp_hw_support/test_apps/.build-test-rules.yml
index 5412abcfd692..112e747363f4 100644
--- a/components/esp_hw_support/test_apps/.build-test-rules.yml
+++ b/components/esp_hw_support/test_apps/.build-test-rules.yml
@@ -67,6 +67,6 @@ components/esp_hw_support/test_apps/wakeup_tests:
   enable:
     - if: SOC_DEEP_SLEEP_SUPPORTED == 1 and SOC_LIGHT_SLEEP_SUPPORTED == 1
   disable_test:
-    - if: IDF_TARGET in ["esp32h21", "esp32h4", "esp32p4"]
+    - if: IDF_TARGET in ["esp32h21", "esp32h4"]
       temporary: true
-      reason: lack of runners # TODO: IDF-14400
+      reason: lack of runners
diff --git a/components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py b/components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py
index da1feb33398c..3560100cc7a1 100644
--- a/components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py
+++ b/components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py
@@ -40,7 +40,6 @@
 
 
 @pytest.mark.generic_multi_device
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14400')
 @pytest.mark.parametrize('count', [2], indirect=True)
 @pytest.mark.parametrize('config', TEST_CONFIGS, indirect=True)
 @idf_parametrize(
@@ -98,7 +97,6 @@ def test_ext1_deepsleep(dut: Tuple[IdfDut, IdfDut]) -> None:
 @pytest.mark.generic_multi_device
 @pytest.mark.parametrize('count', [2], indirect=True)
 @pytest.mark.parametrize('config', TEST_CONFIGS, indirect=True)
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14400')
 @idf_parametrize('target', ['esp32c2', 'esp32c3', 'esp32c6', 'esp32p4', 'esp32c5'], indirect=['target'])
 def test_rtcio_deepsleep(dut: Tuple[IdfDut, IdfDut]) -> None:
     wakee = dut[0]
@@ -144,7 +142,6 @@ def test_rtcio_deepsleep(dut: Tuple[IdfDut, IdfDut]) -> None:
 @pytest.mark.generic_multi_device
 @pytest.mark.parametrize('count', [2], indirect=True)
 @pytest.mark.parametrize('config', TEST_CONFIGS, indirect=True)
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14400')
 @idf_parametrize('target', ['supported_targets'], indirect=['target'])
 def test_gpio_wakeup_enable_lightsleep(dut: Tuple[IdfDut, IdfDut]) -> None:
     wakee = dut[0]
diff --git a/components/esp_phy/lib b/components/esp_phy/lib
index fbc304747bc5..cb9f62b42096 160000
--- a/components/esp_phy/lib
+++ b/components/esp_phy/lib
@@ -1 +1 @@
-Subproject commit fbc304747bc55b40ef7225130fcf87f43b981482
+Subproject commit cb9f62b42096ec1e20c05f2aa57fdd0d04df4d33
diff --git a/components/esp_pm/test_apps/.build-test-rules.yml b/components/esp_pm/test_apps/.build-test-rules.yml
index 6a59d41af7d1..22379b93284a 100644
--- a/components/esp_pm/test_apps/.build-test-rules.yml
+++ b/components/esp_pm/test_apps/.build-test-rules.yml
@@ -8,9 +8,5 @@ components/esp_pm/test_apps:
     - if: IDF_TARGET in ["esp32c61", "esp32h21", "esp32h4"]
       temporary: true
       reason: not support yet # TODO: [ESP32C61] IDF-9250, [ESP32H21] IDF-11522, [ESP32H4] IDF-12286
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: p4 rev3 migration # TODO: IDF-14416
   depends_components:
     - esp_pm
diff --git a/components/esp_pm/test_apps/esp_pm/main/test_pm.c b/components/esp_pm/test_apps/esp_pm/main/test_pm.c
index 8d62c3cee66b..193ffc398aa3 100644
--- a/components/esp_pm/test_apps/esp_pm/main/test_pm.c
+++ b/components/esp_pm/test_apps/esp_pm/main/test_pm.c
@@ -69,8 +69,12 @@ static const int test_freqs[] = {32, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 64, 48, 32
 static const int test_freqs[] = {CONFIG_XTAL_FREQ, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 80, CONFIG_XTAL_FREQ, 80,
                                  CONFIG_XTAL_FREQ / 2, CONFIG_XTAL_FREQ}; // C2 xtal has 40/26MHz option
 #elif CONFIG_IDF_TARGET_ESP32P4
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 static const int test_freqs[] = {40, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 90, 40, 90, 10, 90, 20, 40, 360, 90, 180, 90, 40};
 #else
+static const int test_freqs[] = {40, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 100, 40, 100, 10, 100, 20, 40, 400, 100, 200, 100, 40};
+#endif
+#else
 static const int test_freqs[] = {240, 40, 160, 240, 80, 40, 240, 40, 80, 10, 80, 20, 40};
 #endif
 
diff --git a/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py b/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py
index 881da90fcc2e..a5c78fbddfed 100644
--- a/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py
+++ b/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py
@@ -18,7 +18,7 @@
     indirect=True,
 )
 @idf_parametrize('target', ['supported_targets'], indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c61'], reason='p4 rev3 migration # TODO: IDF-14416')
+@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='not supported yet')  # TODO: [ESP32C61] IDF-9250 IDF-10985
 def test_esp_pm(dut: Dut) -> None:
     dut.run_all_single_board_cases()
 
@@ -54,6 +54,5 @@ def test_esp_attr_xip_psram_esp32s3(dut: Dut) -> None:
     ['pm_pd_top_sleep'],
 )
 @idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32h2', 'esp32p4'], indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14416')
 def test_esp_pd_top_and_cpu_sleep(dut: Dut) -> None:
     dut.run_all_single_board_cases()
diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.net80211.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.net80211.ld
index 56761322bdc2..ef8d8dac6f76 100644
--- a/components/esp_rom/esp32c6/ld/esp32c6.rom.net80211.ld
+++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.net80211.ld
@@ -64,4 +64,3 @@ s_netstack_free = 0x4087ff94;
 mesh_rxcb = 0x4087ff90;
 sta_rxcb = 0x4087ff8c;
 g_itwt_fid = 0x4087ff88;
-esp_test_tx_addba_request = 0x4087ff84;
diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.pp.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.pp.ld
index 105d01a0f111..60646765e00a 100644
--- a/components/esp_rom/esp32c6/ld/esp32c6.rom.pp.ld
+++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.pp.ld
@@ -299,7 +299,7 @@ tsf_hal_unmap_tbtt_target_to_rx_frame = 0x40001024;
 //ppHEAMPDU2Normal = 0x40001030;
 //ppCalTxHEAMPDULength = 0x40001034;
 //ppCalTxHESMPDULength = 0x40001038;
-rcGetRate = 0x4000103c;
+//rcGetRate = 0x4000103c;
 rcGetDCMMaxRate = 0x40001040;
 //rcGetSMPDURate = 0x40001044;
 ppDirectRecycleAmpdu = 0x40001048;
diff --git a/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.systimer.ld b/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.systimer.ld
new file mode 100644
index 000000000000..9b884abe8a87
--- /dev/null
+++ b/components/esp_rom/esp32h4/ld/esp32h4.rom.beta5.systimer.ld
@@ -0,0 +1,28 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/***************************************
+ Group hal_systimer
+ ***************************************/
+
+/* Functions */
+/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
+/* systimer_hal_init = 0x4000039c; */
+/* systimer_hal_deinit = 0x400003a0; */
+
+systimer_hal_set_tick_rate_ops = 0x400003a4;
+systimer_hal_get_counter_value = 0x400003a8;
+systimer_hal_get_time = 0x400003ac;
+systimer_hal_set_alarm_target = 0x400003b0;
+systimer_hal_set_alarm_period = 0x400003b4;
+systimer_hal_get_alarm_value = 0x400003b8;
+systimer_hal_enable_alarm_int = 0x400003bc;
+systimer_hal_on_apb_freq_update = 0x400003c0;
+systimer_hal_counter_value_advance = 0x400003c4;
+systimer_hal_enable_counter = 0x400003c8;
+systimer_hal_select_alarm_mode = 0x400003cc;
+systimer_hal_connect_alarm_counter = 0x400003d0;
+systimer_hal_counter_can_stall_by_cpu = 0x400003d4;
diff --git a/components/esp_rom/esp32h4/ld/esp32h4.rom.systimer.ld b/components/esp_rom/esp32h4/ld/esp32h4.rom.systimer.ld
index 56bb8115cafd..225f53de7850 100644
--- a/components/esp_rom/esp32h4/ld/esp32h4.rom.systimer.ld
+++ b/components/esp_rom/esp32h4/ld/esp32h4.rom.systimer.ld
@@ -9,18 +9,20 @@
  ***************************************/
 
 /* Functions */
-systimer_hal_init = 0x4000039c;
-systimer_hal_deinit = 0x400003a0;
-systimer_hal_set_tick_rate_ops = 0x400003a4;
-systimer_hal_get_counter_value = 0x400003a8;
-systimer_hal_get_time = 0x400003ac;
-systimer_hal_set_alarm_target = 0x400003b0;
-systimer_hal_set_alarm_period = 0x400003b4;
-systimer_hal_get_alarm_value = 0x400003b8;
-systimer_hal_enable_alarm_int = 0x400003bc;
-systimer_hal_on_apb_freq_update = 0x400003c0;
-systimer_hal_counter_value_advance = 0x400003c4;
-systimer_hal_enable_counter = 0x400003c8;
-systimer_hal_select_alarm_mode = 0x400003cc;
-systimer_hal_connect_alarm_counter = 0x400003d0;
-systimer_hal_counter_can_stall_by_cpu = 0x400003d4;
+/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
+/* systimer_hal_init = 0x4000036c; */
+/* systimer_hal_deinit = 0x40000370; */
+
+systimer_hal_set_tick_rate_ops = 0x40000374;
+systimer_hal_get_counter_value = 0x40000378;
+systimer_hal_get_time = 0x4000037c;
+systimer_hal_set_alarm_target = 0x40000380;
+systimer_hal_set_alarm_period = 0x40000384;
+systimer_hal_get_alarm_value = 0x40000388;
+systimer_hal_enable_alarm_int = 0x4000038c;
+systimer_hal_on_apb_freq_update = 0x40000390;
+systimer_hal_counter_value_advance = 0x40000394;
+systimer_hal_enable_counter = 0x40000398;
+systimer_hal_select_alarm_mode = 0x4000039c;
+systimer_hal_connect_alarm_counter = 0x400003a0;
+systimer_hal_counter_can_stall_by_cpu = 0x400003a4;
diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.ld
index a60e9d0b0774..0df2f533eb23 100644
--- a/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.ld
+++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.ld
@@ -170,28 +170,6 @@ rom_spiflash_legacy_data = 0x4ffbffe8;
 g_flash_guard_ops = 0x4ffbfff0;
 
 
-/***************************************
- Group hal_systimer
- ***************************************/
-
-/* Functions */
-systimer_hal_init = 0x4fc00228;
-systimer_hal_deinit = 0x4fc0022c;
-systimer_hal_set_tick_rate_ops = 0x4fc00230;
-systimer_hal_get_counter_value = 0x4fc00234;
-systimer_hal_get_time = 0x4fc00238;
-systimer_hal_set_alarm_target = 0x4fc0023c;
-systimer_hal_set_alarm_period = 0x4fc00240;
-systimer_hal_get_alarm_value = 0x4fc00244;
-systimer_hal_enable_alarm_int = 0x4fc00248;
-systimer_hal_on_apb_freq_update = 0x4fc0024c;
-systimer_hal_counter_value_advance = 0x4fc00250;
-systimer_hal_enable_counter = 0x4fc00254;
-systimer_hal_select_alarm_mode = 0x4fc00258;
-systimer_hal_connect_alarm_counter = 0x4fc0025c;
-systimer_hal_counter_can_stall_by_cpu = 0x4fc00260;
-
-
 /***************************************
  Group cache
  ***************************************/
diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.newlib.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.newlib.ld
index 0498c23bf16d..827507e6e4ba 100644
--- a/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.newlib.ld
+++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.eco5.newlib.ld
@@ -10,7 +10,9 @@
  *
  * Compatible with ROM where ECO version equal or greater to 5.
  *
- * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ * THIS FILE WAS AUTOMATICALLY GENERATED. !!! BUT EDITED !!!
+ * The file was originally generated for use with newlib, but it was split into
+ * multiple files to make it compatible with picolibc.
  */
 
 /***************************************
@@ -18,69 +20,12 @@
  ***************************************/
 
 /* Functions */
-esp_rom_newlib_init_common_mutexes = 0x4fc00264;
-memset = 0x4fc00268;
-memcpy = 0x4fc0026c;
-memmove = 0x4fc00270;
-memcmp = 0x4fc00274;
-strcpy = 0x4fc00278;
-strncpy = 0x4fc0027c;
-strcmp = 0x4fc00280;
-strncmp = 0x4fc00284;
-strlen = 0x4fc00288;
-strstr = 0x4fc0028c;
-bzero = 0x4fc00290;
 _isatty_r = 0x4fc00294;
-sbrk = 0x4fc00298;
-isalnum = 0x4fc0029c;
-isalpha = 0x4fc002a0;
-isascii = 0x4fc002a4;
-isblank = 0x4fc002a8;
-iscntrl = 0x4fc002ac;
-isdigit = 0x4fc002b0;
-islower = 0x4fc002b4;
-isgraph = 0x4fc002b8;
-isprint = 0x4fc002bc;
-ispunct = 0x4fc002c0;
-isspace = 0x4fc002c4;
-isupper = 0x4fc002c8;
-toupper = 0x4fc002cc;
-tolower = 0x4fc002d0;
-toascii = 0x4fc002d4;
-memccpy = 0x4fc002d8;
-memchr = 0x4fc002dc;
-memrchr = 0x4fc002e0;
-strcasecmp = 0x4fc002e4;
-strcasestr = 0x4fc002e8;
-strcat = 0x4fc002ec;
 strdup = 0x4fc002f0;
-strchr = 0x4fc002f4;
-strcspn = 0x4fc002f8;
-strcoll = 0x4fc002fc;
-strlcat = 0x4fc00300;
-strlcpy = 0x4fc00304;
-strlwr = 0x4fc00308;
-strncasecmp = 0x4fc0030c;
-strncat = 0x4fc00310;
 strndup = 0x4fc00314;
-strnlen = 0x4fc00318;
-strrchr = 0x4fc0031c;
-strsep = 0x4fc00320;
-strspn = 0x4fc00324;
-strtok_r = 0x4fc00328;
-strupr = 0x4fc0032c;
-longjmp = 0x4fc00330;
-setjmp = 0x4fc00334;
-abs = 0x4fc00338;
-div = 0x4fc0033c;
-labs = 0x4fc00340;
-ldiv = 0x4fc00344;
-qsort = 0x4fc00348;
 rand_r = 0x4fc0034c;
 rand = 0x4fc00350;
 srand = 0x4fc00354;
-utoa = 0x4fc00358;
-itoa = 0x4fc0035c;
 atoi = 0x4fc00360;
 atol = 0x4fc00364;
 strtol = 0x4fc00368;
@@ -94,6 +39,3 @@ __swhatbuf_r = 0x4fc00384;
 __swbuf_r = 0x4fc00388;
 __swbuf = 0x4fc0038c;
 __swsetup_r = 0x4fc00390;
-/* Data (.data, .bss, .rodata) */
-syscall_table_ptr = 0x4ffbffe4;
-_global_impure_ptr = 0x4ffbffe0;
diff --git a/components/esp_system/ld/esp32p4/memory.ld.in b/components/esp_system/ld/esp32p4/memory.ld.in
index 4154b9369a65..37b5f0f8f1fa 100644
--- a/components/esp_system/ld/esp32p4/memory.ld.in
+++ b/components/esp_system/ld/esp32p4/memory.ld.in
@@ -32,12 +32,6 @@
 #define SRAM_HIGH_END      SRAM_HIGH_START + SRAM_HIGH_SIZE
 #endif
 
-#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
-#define MSPI_WORKAROUND_SIZE   CONFIG_P4_REV3_MSPI_WORKAROUND_SIZE
-#else
-#define MSPI_WORKAROUND_SIZE   0x0
-#endif
-
 #define IDROM_SEG_SIZE   (CONFIG_MMU_PAGE_SIZE << 10)
 
 #define LP_ROM_DRAM_START 0x5010fa80 // Value taken from ROM elf, includes LP ROM stack
diff --git a/components/esp_system/ld/esp32p4/sections.rev3.ld.in b/components/esp_system/ld/esp32p4/sections.rev3.ld.in
index e370942abf49..d8cbd2572946 100644
--- a/components/esp_system/ld/esp32p4/sections.rev3.ld.in
+++ b/components/esp_system/ld/esp32p4/sections.rev3.ld.in
@@ -403,18 +403,16 @@ SECTIONS
      * C++ constructor tables.
      *
      * Excluding crtbegin.o/crtend.o since IDF doesn't use the toolchain crt.
-     *
-     * RISC-V gcc is configured with --enable-initfini-array so it emits
-     * .init_array section instead. But the init_priority sections will be
-     * sorted for iteration in ascending order during startup.
-     * The rest of the init_array sections is sorted for iteration in descending
-     * order during startup, however. Hence a different section is generated for
-     * the init_priority functions which is iterated in ascending order during
-     * startup. The corresponding code can be found in startup.c.
      */
-    ALIGNED_SYMBOL(4, __init_priority_array_start)
-    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))
-    __init_priority_array_end = ABSOLUTE(.);
+    ALIGNED_SYMBOL(4, __preinit_array_start)
+    KEEP (*(.preinit_array))
+    __preinit_array_end = ABSOLUTE(.);
+
+    . = ALIGN(4);
+    PROVIDE(__init_priority_array_start = ABSOLUTE(.));
+    KEEP (*(SORT_BY_INIT_PRIORITY(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)))
+    . = ALIGN(4);
+    PROVIDE(__init_priority_array_end = ABSOLUTE(.));
 
     ALIGNED_SYMBOL(4, __init_array_start)
     KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))
diff --git a/components/esp_system/ld/ld.common b/components/esp_system/ld/ld.common
index 04401fd24ba9..dfe698e4dfdc 100644
--- a/components/esp_system/ld/ld.common
+++ b/components/esp_system/ld/ld.common
@@ -74,6 +74,12 @@
         #define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC)
     #endif
 
+    #if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
+        #define MSPI_WORKAROUND_SIZE   CONFIG_P4_REV3_MSPI_WORKAROUND_SIZE
+    #else
+        #define MSPI_WORKAROUND_SIZE   0x0
+    #endif
+
 #endif // SOC_RTC_MEM_SUPPORTED
 
 #define QUOTED_STRING(STRING) #STRING
diff --git a/components/esp_system/port/soc/esp32c5/system_internal.c b/components/esp_system/port/soc/esp32c5/system_internal.c
index c5608e4a376c..b62820da4a83 100644
--- a/components/esp_system/port/soc/esp32c5/system_internal.c
+++ b/components/esp_system/port/soc/esp32c5/system_internal.c
@@ -48,6 +48,7 @@ void esp_system_reset_modules_on_exit(void)
     modem_lpcon_ll_reset_all(&MODEM_LPCON);
 #endif
     // Set Peripheral clk rst
+    SET_PERI_REG_MASK(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN); // Must reset mspi AXI before reset mspi core.
     SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
     SET_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
     SET_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
@@ -59,9 +60,11 @@ void esp_system_reset_modules_on_exit(void)
     SET_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
     //ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control.
     SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
+    SET_PERI_REG_MASK(PCR_REGDMA_CONF_REG, PCR_REGDMA_RST_EN);
 
     // Clear Peripheral clk rst
     CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
+    CLEAR_PERI_REG_MASK(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN); // Must release mspi core reset before mspi AXI.
     CLEAR_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
@@ -70,6 +73,7 @@ void esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
+    CLEAR_PERI_REG_MASK(PCR_REGDMA_CONF_REG, PCR_REGDMA_RST_EN);
 
     // Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
     // and hence avoiding any possibility with crypto failure in ROM security workflows.
diff --git a/components/esp_system/port/soc/esp32c6/system_internal.c b/components/esp_system/port/soc/esp32c6/system_internal.c
index 98536cfae97e..a811b0cb1244 100644
--- a/components/esp_system/port/soc/esp32c6/system_internal.c
+++ b/components/esp_system/port/soc/esp32c6/system_internal.c
@@ -53,6 +53,7 @@ void esp_system_reset_modules_on_exit(void)
     SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
     //ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control.
     SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
+    SET_PERI_REG_MASK(PCR_REGDMA_CONF_REG, PCR_REGDMA_RST_EN);
 
     // Clear Peripheral clk rst
     CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
@@ -79,6 +80,7 @@ void esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
+    CLEAR_PERI_REG_MASK(PCR_REGDMA_CONF_REG, PCR_REGDMA_RST_EN);
 
     // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
     // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
diff --git a/components/esp_system/port/soc/esp32c61/system_internal.c b/components/esp_system/port/soc/esp32c61/system_internal.c
index 60d38fdd3eaf..896dc34e3c70 100644
--- a/components/esp_system/port/soc/esp32c61/system_internal.c
+++ b/components/esp_system/port/soc/esp32c61/system_internal.c
@@ -48,6 +48,7 @@ void esp_system_reset_modules_on_exit(void)
 #endif
 
     // Set Peripheral clk rst
+    SET_PERI_REG_MASK(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN); // Must reset mspi AXI before reset mspi core.
     SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
     SET_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
     SET_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
@@ -58,8 +59,10 @@ void esp_system_reset_modules_on_exit(void)
     SET_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
     //ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control.
     SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
+    SET_PERI_REG_MASK(PCR_REGDMA_CONF_REG, PCR_REGDMA_RST_EN);
 
     // Clear Peripheral clk rst
+    CLEAR_PERI_REG_MASK(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN); // Must release mspi core reset before mspi AXI.
     CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
@@ -68,6 +71,7 @@ void esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
+    CLEAR_PERI_REG_MASK(PCR_REGDMA_CONF_REG, PCR_REGDMA_RST_EN);
 
     // Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
     // and hence avoiding any possibility with crypto failure in ROM security workflows.
diff --git a/components/esp_system/port/soc/esp32h2/system_internal.c b/components/esp_system/port/soc/esp32h2/system_internal.c
index afd0384c70a5..88c6e8511e3d 100644
--- a/components/esp_system/port/soc/esp32h2/system_internal.c
+++ b/components/esp_system/port/soc/esp32h2/system_internal.c
@@ -50,6 +50,7 @@ void esp_system_reset_modules_on_exit(void)
     SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
     //ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control.
     SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
+    SET_PERI_REG_MASK(PCR_REGDMA_CONF_REG, PCR_REGDMA_RST_EN);
 
     // Clear Peripheral clk rst
     CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
@@ -60,6 +61,7 @@ void esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
+    CLEAR_PERI_REG_MASK(PCR_REGDMA_CONF_REG, PCR_REGDMA_RST_EN);
 
     // Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
     // and hence avoiding any possibility with crypto failure in ROM security workflows.
diff --git a/components/esp_system/port/soc/esp32h21/system_internal.c b/components/esp_system/port/soc/esp32h21/system_internal.c
index 9ce076894cb9..4f64427debd9 100644
--- a/components/esp_system/port/soc/esp32h21/system_internal.c
+++ b/components/esp_system/port/soc/esp32h21/system_internal.c
@@ -50,6 +50,7 @@ void esp_system_reset_modules_on_exit(void)
     SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
     //ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control.
     SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
+    SET_PERI_REG_MASK(PCR_REGDMA_CONF_REG, PCR_REGDMA_RST_EN);
 
     // Clear Peripheral clk rst
     CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
@@ -60,6 +61,7 @@ void esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
+    CLEAR_PERI_REG_MASK(PCR_REGDMA_CONF_REG, PCR_REGDMA_RST_EN);
 
     // Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
     // and hence avoiding any possibility with crypto failure in ROM security workflows.
diff --git a/components/esp_system/port/soc/esp32h4/system_internal.c b/components/esp_system/port/soc/esp32h4/system_internal.c
index 2c8dd1a8c927..a29680fa3458 100644
--- a/components/esp_system/port/soc/esp32h4/system_internal.c
+++ b/components/esp_system/port/soc/esp32h4/system_internal.c
@@ -35,6 +35,7 @@ void esp_system_reset_modules_on_exit(void)
     }
 
     // Set Peripheral clk rst
+    SET_PERI_REG_MASK(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN); // Must reset mspi AXI before reset mspi core.
     SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
     SET_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
     SET_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
@@ -45,9 +46,11 @@ void esp_system_reset_modules_on_exit(void)
     SET_PERI_REG_MASK(PCR_PWM1_CONF_REG, PCR_PWM1_RST_EN);
     //ETM may directly control the GPIO or other peripherals even after CPU reset. Reset to stop these control.
     SET_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
+    SET_PERI_REG_MASK(PCR_REGDMA_CONF_REG, PCR_REGDMA_RST_EN);
 
     // Clear Peripheral clk rst
     CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
+    CLEAR_PERI_REG_MASK(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN); // Must release mspi core reset before mspi AXI.
     CLEAR_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
@@ -56,6 +59,7 @@ void esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_PWM0_CONF_REG, PCR_PWM0_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_PWM1_CONF_REG, PCR_PWM1_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_ETM_CONF_REG, PCR_ETM_RST_EN);
+    CLEAR_PERI_REG_MASK(PCR_REGDMA_CONF_REG, PCR_REGDMA_RST_EN);
 
     // Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
     // and hence avoiding any possibility with crypto failure in ROM security workflows.
diff --git a/components/esp_system/test_apps/.build-test-rules.yml b/components/esp_system/test_apps/.build-test-rules.yml
index 5afed0496a3d..d68503725d63 100644
--- a/components/esp_system/test_apps/.build-test-rules.yml
+++ b/components/esp_system/test_apps/.build-test-rules.yml
@@ -16,10 +16,6 @@ components/esp_system/test_apps/esp_system_unity_tests:
   disable:
     - if: (CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1)
     - if: (CONFIG_NAME == "psram_with_pd_top" and (SOC_SPIRAM_SUPPORTED != 1 or SOC_PM_SUPPORT_TOP_PD != 1))
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: p4 rev3 migration # TODO: IDF-14419
 
 components/esp_system/test_apps/linux_apis:
   enable:
diff --git a/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py b/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py
index f9520f834aac..3d0d92f2272e 100644
--- a/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py
+++ b/components/esp_system/test_apps/esp_system_unity_tests/pytest_esp_system_unity_tests.py
@@ -20,7 +20,6 @@
     ],
     indirect=['config', 'target'],
 )
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14419')
 def test_esp_system(dut: Dut) -> None:
     # esp32p4 32MB PSRAM initialize in startup takes more than 30 sec
     dut.run_all_single_board_cases(timeout=60)
@@ -29,7 +28,6 @@ def test_esp_system(dut: Dut) -> None:
 @pytest.mark.generic
 @idf_parametrize('config', ['default'], indirect=['config'])
 @idf_parametrize('target', ['supported_targets'], indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14419')
 def test_stack_smash_protection(dut: Dut) -> None:
     dut.expect_exact('Press ENTER to see the list of tests')
     dut.write('"stack smashing protection"')
diff --git a/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.framepointer b/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.framepointer
index 464cba0ee4a2..c504d304a3f5 100644
--- a/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.framepointer
+++ b/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.framepointer
@@ -1 +1,3 @@
 CONFIG_ESP_SYSTEM_USE_FRAME_POINTER=y
+# Increase size of bootloader due to frame pointer
+CONFIG_PARTITION_TABLE_OFFSET=0x10000
diff --git a/components/esp_timer/test_apps/.build-test-rules.yml b/components/esp_timer/test_apps/.build-test-rules.yml
index 027881f6be28..b62f794ee43b 100644
--- a/components/esp_timer/test_apps/.build-test-rules.yml
+++ b/components/esp_timer/test_apps/.build-test-rules.yml
@@ -4,7 +4,3 @@ components/esp_timer/test_apps:
   disable:
     - if: CONFIG_NAME == "dfs" and SOC_CLK_XTAL32K_SUPPORTED != 1
       reason: The test requires the XTAL32K clock to measure the esp_timer timing accuracy
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: p4 rev3 migration # TODO: IDF-14420
diff --git a/components/esp_timer/test_apps/pytest_esp_timer_ut.py b/components/esp_timer/test_apps/pytest_esp_timer_ut.py
index 2ab8928b1989..1c3c991fbe03 100644
--- a/components/esp_timer/test_apps/pytest_esp_timer_ut.py
+++ b/components/esp_timer/test_apps/pytest_esp_timer_ut.py
@@ -22,7 +22,6 @@
     ],
     indirect=['config', 'target'],
 )
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14420')
 def test_esp_timer(dut: Dut) -> None:
     dut.run_all_single_board_cases(timeout=120)
 
@@ -37,7 +36,6 @@ def test_esp_timer(dut: Dut) -> None:
     indirect=True,
 )
 @idf_parametrize('target', ['esp32'], indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14420')
 def test_esp_timer_psram(dut: Dut) -> None:
     dut.run_all_single_board_cases(timeout=120)
 
diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib
index 962017b26aa0..10bed0821c16 160000
--- a/components/esp_wifi/lib
+++ b/components/esp_wifi/lib
@@ -1 +1 @@
-Subproject commit 962017b26aa0b9d7ee1d2457d28bdd7131e29986
+Subproject commit 10bed0821c16e428211a3c5de9375dbc510c7544
diff --git a/components/freertos/test_apps/freertos/pytest_freertos.py b/components/freertos/test_apps/freertos/pytest_freertos.py
index ce86a54cf8e4..c1e8ea7bdc15 100644
--- a/components/freertos/test_apps/freertos/pytest_freertos.py
+++ b/components/freertos/test_apps/freertos/pytest_freertos.py
@@ -33,21 +33,9 @@
 @idf_parametrize(
     'config,target,markers',
     [
-        (
-            'default',
-            'supported_targets',
-            (pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421'),),
-        ),
-        (
-            'freertos_options',
-            'supported_targets',
-            (pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421'),),
-        ),
-        (
-            'tickless_idle',
-            'supported_targets',
-            (pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421'),),
-        ),
+        ('default', 'supported_targets'),
+        ('freertos_options', 'supported_targets'),
+        ('tickless_idle', 'supported_targets'),
         ('psram', 'esp32'),
         ('psram', 'esp32c5'),
         ('psram', 'esp32p4'),
@@ -86,7 +74,6 @@ def test_freertos_flash_auto_suspend(dut: Dut) -> None:
 @pytest.mark.generic
 @pytest.mark.parametrize('config', ['freertos_options'], indirect=True)
 @idf_parametrize('target', ['supported_targets'], indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421')
 def test_task_notify_too_high_index_fails(dut: Dut) -> None:
     dut.expect_exact('Press ENTER to see the list of tests.')
     dut.write('"Notify too high index fails"')
@@ -98,7 +85,6 @@ def test_task_notify_too_high_index_fails(dut: Dut) -> None:
 @pytest.mark.generic
 @pytest.mark.parametrize('config', ['freertos_options'], indirect=True)
 @idf_parametrize('target', ['supported_targets'], indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421')
 def test_task_notify_wait_too_high_index_fails(dut: Dut) -> None:
     dut.expect_exact('Press ENTER to see the list of tests.')
     dut.write('"Notify Wait too high index fails"')
@@ -110,7 +96,6 @@ def test_task_notify_wait_too_high_index_fails(dut: Dut) -> None:
 @pytest.mark.generic
 @pytest.mark.parametrize('config', ['default'], indirect=True)
 @idf_parametrize('target', ['supported_targets'], indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14421')
 def test_port_must_assert_in_isr(dut: Dut) -> None:
     dut.expect_exact('Press ENTER to see the list of tests.')
     dut.write('"port must assert if in ISR context"')
diff --git a/components/hal/esp32c5/include/hal/adc_ll.h b/components/hal/esp32c5/include/hal/adc_ll.h
index aebb2557cff1..0483dc9d8b2b 100644
--- a/components/hal/esp32c5/include/hal/adc_ll.h
+++ b/components/hal/esp32c5/include/hal/adc_ll.h
@@ -142,6 +142,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -191,6 +192,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1;
@@ -206,6 +208,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -278,6 +281,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle;
@@ -286,6 +290,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1;
@@ -294,6 +299,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0;
@@ -307,6 +313,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -319,6 +326,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -573,6 +581,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC APB clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -582,6 +591,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -590,6 +600,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;
diff --git a/components/hal/esp32c5/include/hal/axi_icm_ll.h b/components/hal/esp32c5/include/hal/axi_icm_ll.h
index 903a49490d41..fd975954bbdf 100644
--- a/components/hal/esp32c5/include/hal/axi_icm_ll.h
+++ b/components/hal/esp32c5/include/hal/axi_icm_ll.h
@@ -7,8 +7,10 @@
 
 #include <stddef.h>
 #include <stdint.h>
+#include <stdbool.h>
 #include "hal/assert.h"
 #include "soc/hp_system_struct.h"
+#include "soc/pcr_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -36,6 +38,15 @@ static inline void axi_icm_ll_set_cache_arbiter_prio(uint8_t priority)
     HP_SYSTEM.axi_mst_pri.cache_priority = priority;
 }
 
+/**
+ * @brief Reset system bus with soc core reset.
+ * @param reset_with_core_reset True to reset system bus with soc core reset.
+ */
+static inline void axi_icm_ll_reset_with_core_reset(bool reset_with_core_reset)
+{
+    PCR.reset_event_bypass.reset_event_bypass = !reset_with_core_reset;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32c6/include/hal/adc_ll.h b/components/hal/esp32c6/include/hal/adc_ll.h
index 185fe69af493..7fe369d11f7a 100644
--- a/components/hal/esp32c6/include/hal/adc_ll.h
+++ b/components/hal/esp32c6/include/hal/adc_ll.h
@@ -141,6 +141,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -190,6 +191,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1;
@@ -205,6 +207,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -277,6 +280,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle;
@@ -285,6 +289,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1;
@@ -293,6 +298,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0;
@@ -306,6 +312,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -318,6 +325,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -572,6 +580,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -581,6 +590,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -589,6 +599,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;
diff --git a/components/hal/esp32c61/include/hal/adc_ll.h b/components/hal/esp32c61/include/hal/adc_ll.h
index 9e14aaf3a897..4b1b1addc9b7 100644
--- a/components/hal/esp32c61/include/hal/adc_ll.h
+++ b/components/hal/esp32c61/include/hal/adc_ll.h
@@ -142,6 +142,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -191,6 +192,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     ADC.saradc_ctrl.saradc_sar_patt_len = patt_len - 1;
@@ -206,6 +208,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -280,6 +283,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     ADC.saradc_ctrl2.saradc_timer_target = cycle;
@@ -288,6 +292,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     ADC.saradc_ctrl2.saradc_timer_en = 1;
@@ -296,6 +301,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     ADC.saradc_ctrl2.saradc_timer_en = 0;
@@ -309,6 +315,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -321,6 +328,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -575,6 +583,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC APB clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -584,6 +593,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -592,6 +602,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;
diff --git a/components/hal/esp32c61/include/hal/axi_icm_ll.h b/components/hal/esp32c61/include/hal/axi_icm_ll.h
index 1742a9933c17..4cf121d6d712 100644
--- a/components/hal/esp32c61/include/hal/axi_icm_ll.h
+++ b/components/hal/esp32c61/include/hal/axi_icm_ll.h
@@ -7,8 +7,10 @@
 
 #include <stddef.h>
 #include <stdint.h>
+#include <stdbool.h>
 #include "hal/assert.h"
 #include "soc/hp_system_struct.h"
+#include "soc/pcr_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -36,6 +38,15 @@ static inline void axi_icm_ll_set_cache_arbiter_prio(uint8_t priority)
     HP_SYSTEM.system_axi_mst_pri.system_cache_priority = priority;
 }
 
+/**
+ * @brief Reset system bus with soc core reset.
+ * @param reset_with_core_reset True to reset system bus with soc core reset.
+ */
+static inline void axi_icm_ll_reset_with_core_reset(bool reset_with_core_reset)
+{
+    PCR.reset_event_bypass.reset_event_bypass = !reset_with_core_reset;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h
index b0b47b913f57..3e2baaa7abe8 100644
--- a/components/hal/esp32h2/include/hal/adc_ll.h
+++ b/components/hal/esp32h2/include/hal/adc_ll.h
@@ -142,6 +142,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -191,6 +192,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1;
@@ -206,6 +208,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -278,6 +281,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle;
@@ -286,6 +290,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1;
@@ -294,6 +299,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0;
@@ -307,6 +313,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -319,6 +326,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -573,6 +581,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -582,6 +591,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -590,6 +600,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;
diff --git a/components/hal/esp32p4/include/hal/adc_ll.h b/components/hal/esp32p4/include/hal/adc_ll.h
index b52394bfc0dc..f3c7487c1d8c 100644
--- a/components/hal/esp32p4/include/hal/adc_ll.h
+++ b/components/hal/esp32p4/include/hal/adc_ll.h
@@ -150,6 +150,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -207,6 +208,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl23, reg_adc_clk_div_num, div_num);
@@ -219,6 +221,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -331,6 +334,7 @@ static inline void adc_ll_digi_filter_enable(adc_digi_iir_filter_t idx, adc_unit
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 16.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     if (adc_n == ADC_UNIT_1) {
@@ -350,6 +354,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 11.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -372,6 +377,18 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
     }
 }
 
+
+/**
+ * Rest pattern table to default value
+ */
+static inline void adc_ll_digi_reset_pattern_table(void)
+{
+    for(int i = 0; i < 4; i++) {
+        ADC.sar1_patt_tab[i].sar1_patt_tab = 0xffffff;
+        ADC.sar2_patt_tab[i].sar2_patt_tab = 0xffffff;
+    }
+}
+
 /**
  * Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
  *
@@ -410,6 +427,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     ADC.ctrl2.timer_target = cycle;
@@ -454,6 +472,7 @@ static inline void adc_ll_digi_reset(void)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     ADC.ctrl2.timer_sel = 1;
@@ -463,6 +482,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     ADC.ctrl2.timer_en = 0;
@@ -520,24 +540,26 @@ static inline void _adc_ll_sar2_clock_force_en(bool enable)
  * @brief Enable the ADC clock
  * @param enable true to enable, false to disable
  */
-static inline void adc_ll_enable_bus_clock(bool enable)
+__attribute__((always_inline))
+static inline void _adc_ll_enable_bus_clock(bool enable)
 {
     HP_SYS_CLKRST.soc_clk_ctrl2.reg_adc_apb_clk_en = enable;
     HP_SYS_CLKRST.peri_clk_ctrl23.reg_adc_clk_en = enable;
 }
 // HP_SYS_CLKRST.soc_clk_ctrl2 are shared registers, so this function must be used in an atomic way
-#define adc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; adc_ll_enable_bus_clock(__VA_ARGS__)
+#define adc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _adc_ll_enable_bus_clock(__VA_ARGS__)
 
 /**
  * @brief Reset ADC module
  */
-static inline void adc_ll_reset_register(void)
+__attribute__((always_inline))
+static inline void _adc_ll_reset_register(void)
 {
     HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_adc = 1;
     HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_adc = 0;
 }
 //  HP_SYS_CLKRST.hp_rst_en2 is a shared register, so this function must be used in an atomic way
-#define adc_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; adc_ll_reset_register(__VA_ARGS__)
+#define adc_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _adc_ll_reset_register(__VA_ARGS__)
 
 
 
@@ -547,6 +569,7 @@ static inline void adc_ll_reset_register(void)
  * @param adc_n ADC unit.
  * @param manage Set ADC power status.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_power_manage(adc_unit_t adc_n, adc_ll_power_t manage)
 {
     if (adc_n == ADC_UNIT_1) {
@@ -753,6 +776,48 @@ static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param
     }
 }
 
+/**
+ * Set the SAR DTEST param
+ *
+ * @param param DTEST value
+ */
+__attribute__((always_inline))
+static inline void adc_ll_set_dtest_param(uint32_t param)
+{
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, param);
+}
+
+/**
+ * Set the SAR ENT param
+ *
+ * @param param ENT value
+ */
+__attribute__((always_inline))
+static inline void adc_ll_set_ent_param(uint32_t param)
+{
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, param);
+}
+
+/**
+ * Init regi2c SARADC registers
+ */
+__attribute__((always_inline))
+static inline void adc_ll_regi2c_init(void)
+{
+    adc_ll_set_dtest_param(0);
+    adc_ll_set_ent_param(1);
+}
+
+/**
+ * Deinit regi2c SARADC registers
+ */
+__attribute__((always_inline))
+static inline void adc_ll_regi2c_adc_deinit(void)
+{
+    adc_ll_set_dtest_param(0);
+    adc_ll_set_ent_param(0);
+}
+
 /*---------------------------------------------------------------
                     Oneshot Read
 ---------------------------------------------------------------*/
diff --git a/components/hal/esp32p4/include/hal/cpu_utility_ll.h b/components/hal/esp32p4/include/hal/cpu_utility_ll.h
index 3c8b235d8155..e4110a7e6458 100644
--- a/components/hal/esp32p4/include/hal/cpu_utility_ll.h
+++ b/components/hal/esp32p4/include/hal/cpu_utility_ll.h
@@ -33,11 +33,13 @@ FORCE_INLINE_ATTR void cpu_utility_ll_stall_cpu(uint32_t cpu_no)
 {
     if (cpu_no == 0) {
         HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore0_stall_code, 0x86);
-        while(!REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE0_CORESTALLED_ST));
     } else {
         HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore1_stall_code, 0x86);
-        while(!REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE1_CORESTALLED_ST));
     }
+    // We do not check stalled status here because
+    // it will not be set if the stalled core was in WFI when the stall happens, thus any check
+    // is unreliable.
+    // TODO: when ECO6 fixes this we can add back a check here
 }
 
 FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no)
diff --git a/components/hal/esp32p4/include/hal/efuse_ll.h b/components/hal/esp32p4/include/hal/efuse_ll.h
index b2d6223ff47f..fe250fa555dc 100644
--- a/components/hal/esp32p4/include/hal/efuse_ll.h
+++ b/components/hal/esp32p4/include/hal/efuse_ll.h
@@ -13,6 +13,7 @@
 #include "rom/efuse.h"
 #include "hal/ecdsa_types.h"
 #include "hal/ecdsa_ll.h"
+#include "hal/config.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -27,6 +28,25 @@ typedef enum {
     EFUSE_CONTROLLER_STATE_READ_RS_BLK      = 5,    ///< efuse_controllerid is on reading RS block state.
 } efuse_controller_state_t;
 
+/* Revision-aware eFuse feature macros
+ *
+ * These macros indicate whether an eFuse feature is available given the
+ * configured minimum supported chip revision (HAL_CONFIG(CHIP_SUPPORT_MIN_REV)).
+ * Use them when a feature's presence depends on the chosen minimum revision.
+ *
+ * Note: SOC_* capability macros describe silicon capabilities; these
+ * EFUSE_LL_HAS_* macros reflect availability relative to the configured min revision.
+ * If a feature is present in silicon and does not depend on the chip revision,
+ * then add SOC_* macro in soc_caps.h instead.
+ */
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+// Rev 3.00+: key_purpose fields expanded from 4 to 5 bits, enabling additional key types.
+#define EFUSE_LL_HAS_ECDSA_KEY_P192    (1)
+#define EFUSE_LL_HAS_ECDSA_KEY_P384    (1)
+#define EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_128  (1)
+#define EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_256  (1)
+#endif
+
 // Always inline these functions even no gcc optimization is applied.
 
 /******************* eFuse fields *************************/
diff --git a/components/hal/esp32p4/include/hal/trng_ll.h b/components/hal/esp32p4/include/hal/trng_ll.h
new file mode 100644
index 000000000000..1626f58e7053
--- /dev/null
+++ b/components/hal/esp32p4/include/hal/trng_ll.h
@@ -0,0 +1,116 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/trng_struct.h"
+#include "hal/config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Enable or disable TRNG clock
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void trng_ll_enable_clock(bool enable)
+{
+    LP_TRNG.date.clk_en = enable;
+}
+
+/**
+ * @brief Reset TRNG module
+ */
+static inline void trng_ll_reset(void)
+{
+    LP_TRNG.rstn.rstn = 0;
+    LP_TRNG.rstn.rstn = 1;
+}
+
+/**
+ * @brief Enable or disable TRNG sampling
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void trng_ll_enable_sample(bool enable)
+{
+    LP_TRNG.cfg.sample_enable = enable;
+}
+
+/**
+ * @brief Set TRNG timer prescaler
+ *
+ * @param prescaler Timer prescaler value (0-255)
+ */
+static inline void trng_ll_set_timer_prescaler(uint8_t prescaler)
+{
+    LP_TRNG.cfg.timer_pscale = prescaler;
+}
+
+/**
+ * @brief Enable or disable TRNG timer XOR
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void trng_ll_enable_timer(bool enable)
+{
+    LP_TRNG.cfg.timer_en = enable;
+}
+
+/**
+ * @brief Get TRNG sample count
+ *
+ * @return Current sample count (0-255)
+ */
+static inline uint8_t trng_ll_get_sample_count(void)
+{
+    return (uint8_t)LP_TRNG.cfg.sample_cnt;
+}
+
+/**
+ * @brief Read random data from TRNG
+ *
+ * @return 32-bit random data
+ */
+static inline uint32_t trng_ll_read_data(void)
+{
+    return LP_TRNG.data.data;
+}
+
+/**
+ * @brief Enable TRNG module
+ *
+ * TODO: unify in trng_hal.c
+ */
+static inline void trng_ll_enable(void)
+{
+    trng_ll_enable_clock(true);
+    trng_ll_reset();
+    trng_ll_enable_timer(true);
+    trng_ll_enable_sample(true);
+}
+
+/**
+ * @brief Disable TRNG module
+ *
+ * TODO: unify in trng_hal.c
+ */
+static inline void trng_ll_disable(void)
+{
+    trng_ll_enable_sample(false);
+    trng_ll_enable_timer(false);
+    trng_ll_enable_clock(false);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/include/hal/adc_types.h b/components/hal/include/hal/adc_types.h
index 833aa1ceab1b..56f673fa0431 100644
--- a/components/hal/include/hal/adc_types.h
+++ b/components/hal/include/hal/adc_types.h
@@ -38,6 +38,7 @@ typedef enum {
     ADC_CHANNEL_7,     ///< ADC channel
     ADC_CHANNEL_8,     ///< ADC channel
     ADC_CHANNEL_9,     ///< ADC channel
+    ADC_CHANNEL_10,    ///< ADC channel
 } adc_channel_t;
 
 /**
diff --git a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c
index 4cb5cd4429c5..05f70e2cd195 100644
--- a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c
+++ b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c
@@ -217,13 +217,20 @@ static inline size_t get_cache_line_size(const void *addr)
     return (size_t)cache_hal_get_cache_line_size(cache_level, CACHE_TYPE_DATA);
 }
 
-/* Output buffers in external ram needs to be 16-byte aligned and DMA can't access input in the iCache mem range,
-   reallocate them into internal memory and encrypt in chunks to avoid
-   having to malloc too big of a buffer
-
-  The function esp_aes_process_dma_ext_ram zeroises the output buffer in the case of memory allocation failure.
-*/
-
+/**
+ * @brief Output buffers located in external RAM must be aligned to dcache_line_size, and DMA cannot access input data residing in the iCache memory range.
+ * To accommodate this issues, we reallocate them into internal memory and process the AES operation in chunks, avoiding large single-block allocations.
+ *
+ * In the case of ESP32-P4, internal memory is also cacheable, so using internal RAM does not bypass the buffer-alignment requirement; the cache still enforces aligned
+ * memory-to-cache (M2C) operations. Therefore, to safely perform an M2C sync on an unaligned buffer, we must ALIGN_UP the output buffer to the nearest cache line
+ * regardless of whether the output buffer resides in internal or external memory.
+ * (The ESP32-P4 AES driver already performs cache-to-memory (C2M) operations on the output buffer using the aligned-up length, which prevents the corruption that could
+ * otherwise occur when extra cache-line bytes need to be included during an aligned-up M2C operation.).
+ *
+ * Thus, for ESP32-P4, we reallocate the buffers into cache-line-size aligned external memory addresses itself, and use the above strategy to perform the AES operation in chunks.
+ *
+ * @note The function esp_aes_process_dma_ext_ram zeroises the output buffer in the case of memory allocation failure.
+ */
 static int esp_aes_process_dma_ext_ram(esp_aes_context *ctx, const unsigned char *input, unsigned char *output, size_t len, uint8_t *stream_out, bool realloc_input, bool realloc_output)
 {
     size_t chunk_len;
@@ -240,8 +247,9 @@ static int esp_aes_process_dma_ext_ram(esp_aes_context *ctx, const unsigned char
     size_t output_alignment = 1;
 
 /* When AES-DMA operations are carried out using external memory with external memory encryption enabled,
-   we need to make sure that the addresses and the sizes of the buffers on which the DMA operates are 16 byte-aligned. */
-#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
+   we need to make sure that the addresses and the sizes of the buffers on which the DMA operates are 16 byte-aligned.
+   This is only applicable for ESP32-P4, as other targets use internal memory for DMA operations. */
+#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
     if (efuse_hal_flash_encryption_enabled()) {
         if (esp_ptr_external_ram(input) || esp_ptr_external_ram(output) || esp_ptr_in_drom(input) || esp_ptr_in_drom(output)) {
             input_alignment = MAX(get_cache_line_size(input), SOC_GDMA_EXT_MEM_ENC_ALIGNMENT);
@@ -251,7 +259,7 @@ static int esp_aes_process_dma_ext_ram(esp_aes_context *ctx, const unsigned char
             output_heap_caps = MALLOC_CAP_8BIT | (esp_ptr_external_ram(output) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
         }
     }
-#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
+#endif /* SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE */
 
     if (realloc_input) {
         input_buf = heap_caps_aligned_alloc(input_alignment, chunk_len, input_heap_caps);
@@ -356,6 +364,8 @@ static inline esp_err_t dma_desc_link(crypto_dma_desc_t *dmadesc, size_t crypto_
         dmadesc[i].next = ((i == crypto_dma_desc_num - 1) ? NULL : &dmadesc[i+1]);
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
         /* Write back both input buffers and output buffers to clear any cache dirty bit if set */
+        // Even output buffers are C2M synced here, because, while performing an aligned up M2C operation,
+        // extra bytes in the cache (len - ALIGN_UP(len)) might get corrupted if not C2M synced before.
         ret = esp_cache_msync(dmadesc[i].buffer, ALIGN_UP(dmadesc[i].dw0.length, buffer_cache_line_size), ESP_CACHE_MSYNC_FLAG_DIR_C2M);
         if (ret != ESP_OK) {
             return ret;
@@ -644,6 +654,12 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
         goto cleanup;
     }
     for (int i = 0; i < output_dma_desc_num; i++) {
+        // Align the output buffer to the cache line size before performing the M2C sync, because M2C sync cannot be performed on buffers with unaligned lengths.
+        // Note: This does not corrupt the extra bytes in the cache (len - ALIGN_UP(len)) because the ESP32-P4 AES driver already performs cache-to-memory (C2M)
+        // operations on the output buffer using the aligned-up length.
+        // But what if those extra bytes get updated (say by a different process) during the AES operation? Would the updated value be lost/corrupted?
+        // No, because the heap allocator would have already allocated a ALIGNED_UP buffer for the output buffer according to the alignment requirements,
+        // while allocating the output buffer (see esp_heap_adjust_alignment_to_hw()).
         if (esp_cache_msync(output_desc[i].buffer, ALIGN_UP(output_desc[i].dw0.length, output_cache_line_size), ESP_CACHE_MSYNC_FLAG_DIR_M2C) != ESP_OK) {
             ESP_LOGE(TAG, "Output DMA descriptor buffers cache sync M2C failed");
             ret = -1;
diff --git a/components/soc/esp32c61/register/soc/pcr_struct.h b/components/soc/esp32c61/register/soc/pcr_struct.h
index 9e36f9e79079..97b48ecdb5e9 100644
--- a/components/soc/esp32c61/register/soc/pcr_struct.h
+++ b/components/soc/esp32c61/register/soc/pcr_struct.h
@@ -1774,6 +1774,30 @@ typedef union {
     uint32_t val;
 } pcr_timergroup_xtal_conf_reg_t;
 
+/** Type of reset_event_bypass register
+ *  reset event bypass backdoor configuration register
+ */
+typedef union {
+    struct {
+        /** reset_event_bypass_apm : R/W; bitpos: [0]; default: 0;
+         *  This field is used to control reset event relationship for
+         *  tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset
+         *  by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg
+         *  will not only be reset by power-reset, but also some reset event.
+         */
+        uint32_t reset_event_bypass_apm:1;
+        /** reset_event_bypass : R/W; bitpos: [1]; default: 1;
+         *  This field is used to control reset event relationship for system-bus. 1: system
+         *  bus (including arbiter/router) will only be reset by power-reset. some reset event
+         *  will be bypass. 0: system bus (including arbiter/router) will not only be reset by
+         *  power-reset, but also some reset event.
+         */
+        uint32_t reset_event_bypass:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_reset_event_bypass_reg_t;
+
 /** Type of regdma_conf register
  *  REGDMA configuration register
  */
@@ -1966,7 +1990,7 @@ typedef struct {
     uint32_t reserved_128;
     volatile pcr_timergroup_wdt_conf_reg_t timergroup_wdt_conf;
     volatile pcr_timergroup_xtal_conf_reg_t timergroup_xtal_conf;
-    uint32_t reserved_134;
+    volatile pcr_reset_event_bypass_reg_t reset_event_bypass;
     volatile pcr_regdma_conf_reg_t regdma_conf;
     volatile pcr_etm_conf_reg_t etm_conf;
     uint32_t reserved_140[6];
diff --git a/components/soc/esp32p4/include/soc/wdev_reg.h b/components/soc/esp32p4/include/soc/wdev_reg.h
deleted file mode 100644
index 50e082d2f724..000000000000
--- a/components/soc/esp32p4/include/soc/wdev_reg.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "soc.h"
-#include "soc/lpperi_reg.h"
-
-/* Hardware random number generator register */
-#define WDEV_RND_REG    0x501101a4
diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld
index d25499b74e0f..8110e9f02feb 100644
--- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld
+++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld
@@ -82,6 +82,7 @@ PROVIDE ( LP_I2C        = 0x50122000 );
 PROVIDE ( LP_SPI        = 0x50123000 );
 PROVIDE ( LP_WDT        = 0x50116000 );
 PROVIDE ( LP_I2S        = 0x50125000 );
+PROVIDE ( LP_TRNG       = 0x50126000 );
 PROVIDE ( LP_ADC        = 0x50127000 );
 PROVIDE ( LP_TOUCH      = 0x50128000 );
 PROVIDE ( LP_GPIO         = 0x5012A000 );
diff --git a/components/soc/esp32p4/register/hw_ver1/soc/wdev_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/wdev_reg.h
new file mode 100644
index 000000000000..f837dbcded1c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver1/soc/wdev_reg.h
@@ -0,0 +1,20 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/lp_system_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Hardware random number generator register */
+#define WDEV_RND_REG    LP_SYSTEM_REG_RNG_DATA_REG
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/reg_base.h b/components/soc/esp32p4/register/hw_ver3/soc/reg_base.h
index 12e537ee3aa5..cd7caa0765bc 100644
--- a/components/soc/esp32p4/register/hw_ver3/soc/reg_base.h
+++ b/components/soc/esp32p4/register/hw_ver3/soc/reg_base.h
@@ -151,6 +151,7 @@
 #define DR_REG_LP_SPI_BASE            (DR_REG_LPPERIPH_BASE + 0x3000)
 #define DR_REG_I2C_ANA_MST_BASE       (DR_REG_LPPERIPH_BASE + 0x4000)
 #define DR_REG_LP_I2S_BASE            (DR_REG_LPPERIPH_BASE + 0x5000)
+#define DR_REG_LP_TRNG_BASE           (DR_REG_LPPERIPH_BASE + 0x6000)
 #define DR_REG_LP_ADC_BASE            (DR_REG_LPPERIPH_BASE + 0x7000)
 #define DR_REG_LP_TOUCH_BASE          (DR_REG_LPPERIPH_BASE + 0x8000)
 #define DR_REG_LP_GPIO_BASE           (DR_REG_LPPERIPH_BASE + 0xA000)
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/trng_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/trng_reg.h
index cbdd7e2bd182..46a82394aaf6 100644
--- a/components/soc/esp32p4/register/hw_ver3/soc/trng_reg.h
+++ b/components/soc/esp32p4/register/hw_ver3/soc/trng_reg.h
@@ -14,7 +14,7 @@ extern "C" {
 /** RNG_CFG_REG register
  *  configure rng register
  */
-#define RNG_CFG_REG (DR_REG_RNG_BASE + 0x0)
+#define RNG_CFG_REG (DR_REG_LP_TRNG_BASE + 0x0)
 /** RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0;
  *  enable rng RO
  *  1: enable RO
@@ -49,7 +49,7 @@ extern "C" {
 /** RNG_DATA_REG register
  *  RNG result register
  */
-#define RNG_DATA_REG (DR_REG_RNG_BASE + 0x4)
+#define RNG_DATA_REG (DR_REG_LP_TRNG_BASE + 0x4)
 /** RNG_DATA : RO; bitpos: [31:0]; default: 0;
  *  get rng data
  */
@@ -61,7 +61,7 @@ extern "C" {
 /** RNG_RSTN_REG register
  *  rng rstn register
  */
-#define RNG_RSTN_REG (DR_REG_RNG_BASE + 0x8)
+#define RNG_RSTN_REG (DR_REG_LP_TRNG_BASE + 0x8)
 /** RNG_RSTN : R/W; bitpos: [0]; default: 1;
  *  enable rng system reset: 1: not reset, 0: reset
  */
@@ -73,7 +73,7 @@ extern "C" {
 /** RNG_DATE_REG register
  *  need_des
  */
-#define RNG_DATE_REG (DR_REG_RNG_BASE + 0xc)
+#define RNG_DATE_REG (DR_REG_LP_TRNG_BASE + 0xc)
 /** RNG_DATE : R/W; bitpos: [30:0]; default: 2425091;
  *  need_des
  */
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/wdev_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/wdev_reg.h
new file mode 100644
index 000000000000..36ef570e2b48
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver3/soc/wdev_reg.h
@@ -0,0 +1,20 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/trng_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Hardware random number generator register */
+#define WDEV_RND_REG    RNG_DATA_REG
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/ulp/ld/lp_core_riscv.ld b/components/ulp/ld/lp_core_riscv.ld
index 0f2da81c3ec4..05d84951b686 100644
--- a/components/ulp/ld/lp_core_riscv.ld
+++ b/components/ulp/ld/lp_core_riscv.ld
@@ -9,11 +9,13 @@
 
 #if CONFIG_ESP_ROM_HAS_LP_ROM
 /* With LP-ROM memory layout is different due to LP ROM stack/data */
-#define ULP_MEM_START_ADDRESS SOC_RTC_DRAM_LOW + RESERVE_RTC_MEM
+/* For P4 ECO5 we also reserve some RTC MEM at the first for MSPI workaround */
+#define ULP_MEM_START_ADDRESS SOC_RTC_DRAM_LOW + RESERVE_RTC_MEM + MSPI_WORKAROUND_SIZE
 #else
 #define ULP_MEM_START_ADDRESS (SOC_RTC_DRAM_LOW)
 #endif
 
+
 #define ALIGN_DOWN(SIZE, AL)   (SIZE & ~(AL - 1))
 /* Ensure the end where the shared memory starts is aligned to 8 bytes
    if updating this also update the same in ulp_lp_core_memory_shared.c
diff --git a/examples/cxx/.build-test-rules.yml b/examples/cxx/.build-test-rules.yml
deleted file mode 100644
index 9d21130a1c7a..000000000000
--- a/examples/cxx/.build-test-rules.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
-
-examples/cxx/exceptions:
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: p4 rev3 migration # TODO: IDF-14402
-
-examples/cxx/rtti:
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: p4 rev3 migration # TODO: IDF-14402
diff --git a/examples/cxx/exceptions/pytest_examples_cxx_exceptions.py b/examples/cxx/exceptions/pytest_examples_cxx_exceptions.py
index b2df9354f113..f62a8ae866ec 100644
--- a/examples/cxx/exceptions/pytest_examples_cxx_exceptions.py
+++ b/examples/cxx/exceptions/pytest_examples_cxx_exceptions.py
@@ -7,7 +7,6 @@
 
 @pytest.mark.generic
 @idf_parametrize('target', ['supported_targets'], indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14402')
 def test_examples_cpp_exceptions(dut: IdfDut) -> None:
     lines = [
         'app_main starting',
diff --git a/examples/cxx/rtti/pytest_examples_cxx_rtti.py b/examples/cxx/rtti/pytest_examples_cxx_rtti.py
index 705acc6249b2..e6d81bd99bfa 100644
--- a/examples/cxx/rtti/pytest_examples_cxx_rtti.py
+++ b/examples/cxx/rtti/pytest_examples_cxx_rtti.py
@@ -7,7 +7,6 @@
 
 @pytest.mark.generic
 @idf_parametrize('target', ['supported_targets'], indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14402')
 def test_cpp_rtti_example(dut: IdfDut) -> None:
     dut.expect_exact('Type name of std::cout is: std::ostream')
     dut.expect_exact('Type name of std::cin is: std::istream')
diff --git a/examples/peripherals/.build-test-rules.yml b/examples/peripherals/.build-test-rules.yml
index 42ad6d38508e..20dfad0ee99b 100644
--- a/examples/peripherals/.build-test-rules.yml
+++ b/examples/peripherals/.build-test-rules.yml
@@ -10,19 +10,11 @@
 examples/peripherals/adc/continuous_read:
   disable:
     - if: SOC_ADC_DMA_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: p4 rev3 migration # TODO: IDF-14357
   <<: *adc_dependencies
 
 examples/peripherals/adc/oneshot_read:
   disable:
     - if: SOC_ADC_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: p4 rev3 migration # TODO: IDF-14357
   <<: *adc_dependencies
 
 examples/peripherals/analog_comparator:
diff --git a/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py b/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py
index dbc532175196..c7793c69a529 100644
--- a/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py
+++ b/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py
@@ -11,7 +11,6 @@
     ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c5', 'esp32p4', 'esp32c61'],
     indirect=['target'],
 )
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14357')
 def test_adc_continuous(dut: Dut) -> None:
     res = dut.expect(r'TASK: ret is 0, ret_num is (\d+) bytes')
     num = res.group(1).decode('utf8')
diff --git a/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py b/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py
index 5b8ecc80bccc..17e15ba72777 100644
--- a/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py
+++ b/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py
@@ -11,7 +11,6 @@
     ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c5', 'esp32p4', 'esp32c61'],
     indirect=['target'],
 )
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14357')
 def test_adc_oneshot(dut: Dut) -> None:
     dut.expect(r'EXAMPLE: ADC1 Channel\[(\d+)\] Raw Data: (\d+)', timeout=5)
 
diff --git a/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py b/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py
index 81d9f50a797f..29c7211cfcee 100644
--- a/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py
+++ b/examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py
@@ -10,12 +10,9 @@
 @pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14423')
 def test_ipc_isr_riscv(dut: Dut) -> None:
     dut.expect_exact('example: Start')
-    dut.expect_exact('example: MSTATUS = 0x11880')
     dut.expect_exact('example: in[0] = 0x1')
     dut.expect_exact('example: in[1] = 0x2')
     dut.expect_exact('example: in[2] = 0x3')
     dut.expect_exact('example: out[0] = (in[0] | in[1] | in[2]) = 0x3')
     dut.expect_exact('example: out[1] = (in[0] + in[1] + in[2]) = 0x6')
-    dut.expect_exact('example: out[2] = MCAUSE of other cpu = 0xb800002c')
-    dut.expect_exact('example: out[3] = MSTATUS of other cpu = 0x11880')
     dut.expect_exact('example: End')
diff --git a/examples/system/sysview_tracing_heap_log/sdkconfig.defaults.esp32p4 b/examples/system/sysview_tracing_heap_log/sdkconfig.defaults.esp32p4
new file mode 100644
index 000000000000..8b07012800d3
--- /dev/null
+++ b/examples/system/sysview_tracing_heap_log/sdkconfig.defaults.esp32p4
@@ -0,0 +1,2 @@
+# Increase size of bootloader due to frame pointer. Only overflowed on P4.
+CONFIG_PARTITION_TABLE_OFFSET=0x10000
diff --git a/tools/test_apps/system/.build-test-rules.yml b/tools/test_apps/system/.build-test-rules.yml
index 2770141fb73a..76d0f5f3802f 100644
--- a/tools/test_apps/system/.build-test-rules.yml
+++ b/tools/test_apps/system/.build-test-rules.yml
@@ -27,10 +27,6 @@ tools/test_apps/system/eh_frame:
   disable:
     - if: IDF_TARGET in ["esp32", "esp32s2", "esp32s3", "linux"]
       reason: Only relevant for riscv targets
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: p4 rev3 migration # TODO: IDF-14424
 
 tools/test_apps/system/esp_intr_dump:
 
diff --git a/tools/test_apps/system/eh_frame/pytest_eh_frame.py b/tools/test_apps/system/eh_frame/pytest_eh_frame.py
index 92de8630dc5f..ca6de919f424 100644
--- a/tools/test_apps/system/eh_frame/pytest_eh_frame.py
+++ b/tools/test_apps/system/eh_frame/pytest_eh_frame.py
@@ -9,7 +9,6 @@
 @idf_parametrize(
     'target', ['esp32c2', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32c61', 'esp32h2', 'esp32p4'], indirect=['target']
 )
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14424')
 def test_eh_frame_wdt(dut: Dut) -> None:
     dut.expect_exact('Press ENTER to see the list of tests')
     dut.confirm_write('"Test task wdt can print backtrace with eh-frame"', expect_str='Running')
@@ -22,7 +21,6 @@ def test_eh_frame_wdt(dut: Dut) -> None:
 @idf_parametrize(
     'target', ['esp32c2', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32c61', 'esp32h2', 'esp32p4'], indirect=['target']
 )
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14424')
 def test_eh_frame_panic(dut: Dut) -> None:
     dut.expect_exact('Press ENTER to see the list of tests')
     dut.confirm_write('"Test panic can print backtrace with eh-frame"', expect_str='Running')