diff --git a/components/app_trace/port/port_uart.c b/components/app_trace/port/port_uart.c index 053f235cdbf8..43dd60c8a7f5 100644 --- a/components/app_trace/port/port_uart.c +++ b/components/app_trace/port/port_uart.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -288,10 +288,9 @@ static esp_err_t esp_apptrace_uart_up_buffer_put(esp_apptrace_uart_data_t *hw_da static void esp_apptrace_uart_down_buffer_config(esp_apptrace_uart_data_t *hw_data, uint8_t *buf, uint32_t size) { - hw_data->down_buffer = (uint8_t *)malloc(size); - if (hw_data->down_buffer == NULL){ - assert(false && "Failed to allocate apptrace uart down buffer!"); - } + assert(buf != NULL && "Down buffer cannot be NULL"); + + hw_data->down_buffer = buf; hw_data->down_buffer_size = size; } diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c index eb83ae8b1359..e5769d712013 100644 --- a/components/bootloader_support/src/bootloader_console.c +++ b/components/bootloader_support/src/bootloader_console.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,6 @@ #include "soc/uart_periph.h" #include "soc/uart_channel.h" #include "soc/io_mux_reg.h" -#include "soc/gpio_periph.h" #include "soc/gpio_sig_map.h" #include "soc/rtc.h" #include "hal/gpio_ll.h" @@ -26,9 +25,21 @@ #include "esp_rom_sys.h" #include "esp_rom_caps.h" +static void __attribute__((unused)) release_default_console_io(void) +{ + // Default console is UART0 with TX and RX on their IOMUX pins + gpio_ll_output_disable(&GPIO, UART_NUM_0_TXD_DIRECT_GPIO_NUM); + gpio_ll_func_sel(&GPIO, U0TXD_GPIO_NUM, PIN_FUNC_GPIO); // Set TX pin to GPIO function to truly disable output + esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(UART_NUM_0, SOC_UART_RX_PIN_IDX), 0); +} + #ifdef CONFIG_ESP_CONSOLE_NONE void bootloader_console_init(void) { + // Wait for UART FIFO to be empty. + esp_rom_output_tx_wait_idle(0); + release_default_console_io(); + esp_rom_install_channel_putc(1, NULL); esp_rom_install_channel_putc(2, NULL); } @@ -59,9 +70,7 @@ void bootloader_console_init(void) if (uart_num != 0 || uart_tx_gpio != UART_NUM_0_TXD_DIRECT_GPIO_NUM || uart_rx_gpio != UART_NUM_0_RXD_DIRECT_GPIO_NUM) { - // Change default UART pins back to GPIOs - gpio_ll_func_sel(&GPIO, UART_NUM_0_RXD_DIRECT_GPIO_NUM, PIN_FUNC_GPIO); - gpio_ll_func_sel(&GPIO, UART_NUM_0_TXD_DIRECT_GPIO_NUM, PIN_FUNC_GPIO); + release_default_console_io(); // Route GPIO signals to/from pins const uint32_t tx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX); const uint32_t rx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX); @@ -101,6 +110,10 @@ static char s_usb_cdc_buf[ESP_ROM_CDC_ACM_WORK_BUF_MIN]; void bootloader_console_init(void) { + // Wait for UART FIFO to be empty. + esp_rom_output_tx_wait_idle(0); + release_default_console_io(); + #ifdef CONFIG_IDF_TARGET_ESP32S2 /* ESP32-S2 specific patch to set the correct serial number in the descriptor. * Later chips don't need this. @@ -120,6 +133,10 @@ void bootloader_console_init(void) #ifdef CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG void bootloader_console_init(void) { + // Wait for UART FIFO to be empty. + esp_rom_output_tx_wait_idle(0); + release_default_console_io(); + esp_rom_output_switch_buffer(ESP_ROM_USB_SERIAL_DEVICE_NUM); /* Switch console channel to avoid output on UART and allow */ diff --git a/components/bt/CMakeLists.txt b/components/bt/CMakeLists.txt index 170fba3a9d74..84f65b94fd59 100644 --- a/components/bt/CMakeLists.txt +++ b/components/bt/CMakeLists.txt @@ -616,19 +616,17 @@ if(CONFIG_BT_ENABLED) "esp_ble_mesh/v1.1/btc/btc_ble_mesh_sar_model.c" "esp_ble_mesh/v1.1/btc/btc_ble_mesh_srpl_model.c" "esp_ble_mesh/lib/ext.c") + if(CONFIG_BLE_MESH_SAR_ENHANCEMENT) list(APPEND srcs "esp_ble_mesh/core/transport.enh.c") else() list(APPEND srcs "esp_ble_mesh/core/transport.c") endif() else() - list(APPEND srcs - "esp_ble_mesh/core/transport.c") + list(APPEND srcs "esp_ble_mesh/core/transport.c") endif() endif() - - if(CONFIG_BT_LE_CONTROLLER_NPL_OS_PORTING_SUPPORT) list(APPEND srcs "porting/npl/freertos/src/npl_os_freertos.c" @@ -935,7 +933,7 @@ set(bt_priv_requires ) if(CONFIG_BLE_COMPRESSED_LOG_ENABLE) - set(BT_ROOT_PATH "${CMAKE_CURRENT_SOURCE_DIR}") + set(CODE_BASE_PATH "${CMAKE_CURRENT_SOURCE_DIR}") # When log compression is enabled, selected logs are replaced # by auto-generated macros that emit pre-encoded data. # This eliminates the original format strings, reducing firmware size and diff --git a/components/bt/common/ble_log/Kconfig.in b/components/bt/common/ble_log/Kconfig.in index f3a5e5348a72..2bb05ede5af5 100644 --- a/components/bt/common/ble_log/Kconfig.in +++ b/components/bt/common/ble_log/Kconfig.in @@ -7,6 +7,8 @@ config BLE_LOG_ENABLED if BLE_LOG_ENABLED config BLE_LOG_TASK_STACK_SIZE int "Stack size for BLE Log Task" + default 1024 if IDF_TARGET_ARCH_RISCV + default 2048 if IDF_TARGET_ARCH_XTENSA default 1024 help Stack size for BLE Log Task diff --git a/components/bt/common/ble_log/ble_log_spi_out.c b/components/bt/common/ble_log/ble_log_spi_out.c index 79c0087226a8..bff68af46bb7 100644 --- a/components/bt/common/ble_log/ble_log_spi_out.c +++ b/components/bt/common/ble_log/ble_log_spi_out.c @@ -41,7 +41,14 @@ #define SPI_OUT_LOG_STR_BUF_SIZE (100) #define SPI_OUT_MALLOC(size) heap_caps_malloc(size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) #define SPI_OUT_TASK_PRIORITY (ESP_TASK_PRIO_MAX - 1) + +#if CONFIG_IDF_TARGET_ARCH_RISCV #define SPI_OUT_TASK_STACK_SIZE (1024) +#elif CONFIG_IDF_TARGET_ARCH_XTENSA +#define SPI_OUT_TASK_STACK_SIZE (2048) +#else +static_assert(false, "BLE Log SPI Out: Unsupported target architecture"); +#endif /* CONFIG_IDF_TARGET_ARCH_RISCV */ #if SPI_OUT_TS_SYNC_ENABLED #define SPI_OUT_TS_SYNC_TIMEOUT_MS (1000) diff --git a/components/bt/common/ble_log/extension/log_compression/CMakeLists.txt b/components/bt/common/ble_log/extension/log_compression/CMakeLists.txt index 967b0e9b8eca..15ae73550ace 100644 --- a/components/bt/common/ble_log/extension/log_compression/CMakeLists.txt +++ b/components/bt/common/ble_log/extension/log_compression/CMakeLists.txt @@ -1,6 +1,6 @@ - set(LOG_COMPRESSED_MODULE "") set(LOG_COMPRESSED_MODULE_CODE_PATH "") +set(BT_ROOT_PATH $ENV{IDF_PATH}/components/bt) set(LOG_COMPRESSED_SRCS_DIR "${CMAKE_BINARY_DIR}/ble_log/.compressed_srcs") # default config value for ble mesh module @@ -17,32 +17,62 @@ set(BLE_HOST_TAGS_PRESERVE "") if(CONFIG_BLE_MESH_COMPRESSED_LOG_ENABLE) list(APPEND LOG_COMPRESSED_MODULE "BLE_MESH") - if(NOT EXISTS "${CMAKE_BINARY_DIR}/ble_log/include/mesh_log_index.h") - file(WRITE "${CMAKE_BINARY_DIR}/ble_log/include/mesh_log_index.h" "") - endif() - list(APPEND LOG_COMPRESSED_MODULE_CODE_PATH "esp_ble_mesh") # update config file set(BLE_MESH_CODE_PATH "esp_ble_mesh") set(BLE_MESH_LOG_INDEX_HEADER "mesh_log_index.h") + set(BLE_MESH_LOG_SCRIPT_PATH + "${CMAKE_CURRENT_LIST_DIR}/scripts/module_scripts/ble_mesh/make_mesh_log_macro.py") # update BLE_MESH_TAGS and BLE_MESH_TAGS_PRESERVE include(${CMAKE_CURRENT_LIST_DIR}/cmake/ble_mesh_log_tags.cmake) - + if(NOT EXISTS "${CMAKE_BINARY_DIR}/ble_log/include/${BLE_MESH_LOG_INDEX_HEADER}") + file(WRITE "${CMAKE_BINARY_DIR}/ble_log/include/${BLE_MESH_LOG_INDEX_HEADER}" "") + endif() + list(APPEND LOG_COMPRESSED_MODULE_CODE_PATH ${BLE_MESH_CODE_PATH}) endif() + if(CONFIG_BLE_HOST_COMPRESSED_LOG_ENABLE AND CONFIG_BT_BLUEDROID_ENABLED) list(APPEND LOG_COMPRESSED_MODULE "BLE_HOST") - list(APPEND LOG_COMPRESSED_MODULE_CODE_PATH "host/bluedroid/stack") - if(NOT EXISTS "${CMAKE_BINARY_DIR}/ble_log/include/host_log_index.h") - file(WRITE "${CMAKE_BINARY_DIR}/ble_log/include/host_log_index.h" "") - endif() + # update config file set(HOST_CODE_PATH "host/bluedroid/stack") set(HOST_LOG_INDEX_HEADER "host_log_index.h") + set(BLE_HOST_LOG_SCRIPT_PATH + "${CMAKE_CURRENT_LIST_DIR}/scripts/module_scripts/bluedroid/make_bluedroid_log_macro.py") + include(${CMAKE_CURRENT_LIST_DIR}/cmake/ble_host_bluedroid_tags.cmake) + if(NOT EXISTS "${CMAKE_BINARY_DIR}/ble_log/include/${HOST_LOG_INDEX_HEADER}") + file(WRITE "${CMAKE_BINARY_DIR}/ble_log/include/${HOST_LOG_INDEX_HEADER}" "") + endif() + list(APPEND LOG_COMPRESSED_MODULE_CODE_PATH ${HOST_CODE_PATH}) +endif() + +if(BLE_COMPRESSED_LIB_LOG_BUILD) + if(NOT (BLE_COMPRESSED_LIB_NAME AND BLE_COMPRESSED_LIB_CODE_DIR AND BLE_COMPRESSED_LIB_LOG_TAGS)) + message(FATAL_ERROR "Invalid settings") + else() + message("Building compressed log for ${BLE_COMPRESSED_LIB_NAME}") + endif() + list(APPEND LOG_COMPRESSED_MODULE ${BLE_COMPRESSED_LIB_NAME}) + if(NOT EXISTS "${CMAKE_BINARY_DIR}/ble_log/include/${BLE_COMPRESSED_LIB_LOG_INDEX_HEADER}") + file(WRITE "${CMAKE_BINARY_DIR}/ble_log/include/${BLE_COMPRESSED_LIB_LOG_INDEX_HEADER}" "") + endif() + list(APPEND LOG_COMPRESSED_MODULE_CODE_PATH ${BLE_COMPRESSED_LIB_CODE_DIR}) + + string(REPLACE ";" "," BLE_COMPRESSED_LIB_CODE_DIR "${BLE_COMPRESSED_LIB_CODE_DIR}") + string(REPLACE ";" "," BLE_COMPRESSED_LIB_LOG_TAGS "${BLE_COMPRESSED_LIB_LOG_TAGS}") + string(REPLACE ";" "," BLE_COMPRESSED_LIB_LOG_TAGS_PRESERVE "${BLE_COMPRESSED_LIB_LOG_TAGS_PRESERVE}") +else() + set(BLE_COMPRESSED_LIB_NAME "placeholder") endif() + + if(LOG_COMPRESSED_MODULE) - list(APPEND srcs "common/ble_log/extension/log_compression/ble_log_compression.c") - list(APPEND include_dirs "${CMAKE_BINARY_DIR}/ble_log/include") + # When building the library, ble_log_compression.c and its dependencies are not needed + if(NOT BLE_COMPRESSED_LIB_LOG_BUILD) + list(APPEND srcs "common/ble_log/extension/log_compression/ble_log_compression.c") + list(APPEND include_dirs "${CMAKE_BINARY_DIR}/ble_log/include") + endif() if(NOT CMAKE_VERSION VERSION_LESS 3.15.0) set(Python3_FIND_STRATEGY LOCATION) find_package(Python3 COMPONENTS Interpreter) @@ -111,19 +141,39 @@ if(LOG_COMPRESSED_MODULE) "host/nimble/nimble/nimble/host/store/config/src") endif() - add_custom_target(ble_log_compression ALL - COMMAND ${BLE_PYTHON_EXECUTABLE} ${PYTHON_SCRIPT} - compress - --compressed_srcs_path "${LOG_COMPRESSED_SRCS_DIR}" - --build_path "${CMAKE_BINARY_DIR}" - --module "'${LOG_COMPRESSED_MODULE}'" - --bt_path "${BT_ROOT_PATH}" - --srcs "'${compressed_srcs}'" - DEPENDS ${compressed_srcs_with_abs_path} ${PYTHON_SCRIPT} - COMMENT "Log compression is being performed, please wait..." - WORKING_DIRECTORY ${BT_ROOT_PATH} - USES_TERMINAL - ) + if(BLE_COMPRESSED_LIB_LOG_BUILD) + execute_process(COMMAND ${BLE_PYTHON_EXECUTABLE} ${PYTHON_SCRIPT} + compress + --compressed_srcs_path "${LOG_COMPRESSED_SRCS_DIR}" + --build_path "${CMAKE_BINARY_DIR}" + --module "${LOG_COMPRESSED_MODULE}" + --code_base_path "${CODE_BASE_PATH}" + --srcs "${compressed_srcs}" + RESULT_VARIABLE result + OUTPUT_VARIABLE out + ERROR_VARIABLE err) + if(NOT ${result} EQUAL 0) + message(WARNING "${err}") + message(WARNING "Exit this log compression due to failure of compression") + set(LOG_COMPRESS_INCLUDE_DIRS ${include_dirs} PARENT_SCOPE) + set(LOG_COMPRESSION_TARGET "" PARENT_SCOPE) + return() + endif() + else() + add_custom_target(ble_log_compression ALL + COMMAND ${BLE_PYTHON_EXECUTABLE} ${PYTHON_SCRIPT} + compress + --compressed_srcs_path "${LOG_COMPRESSED_SRCS_DIR}" + --build_path "${CMAKE_BINARY_DIR}" + --module "'${LOG_COMPRESSED_MODULE}'" + --code_base_path "${CODE_BASE_PATH}" + --srcs "'${compressed_srcs}'" + DEPENDS ${compressed_srcs_with_abs_path} ${PYTHON_SCRIPT} + COMMENT "Log compression is being performed, please wait..." + WORKING_DIRECTORY ${BT_ROOT_PATH} + USES_TERMINAL + ) + endif() function(add_flags_if_in_list file file_list compile_flags) set(PROCESSED OFF PARENT_SCOPE) @@ -190,7 +240,10 @@ if(LOG_COMPRESSED_MODULE) set(LOG_COMPRESSION_TARGET ble_log_compression PARENT_SCOPE) # set(LOG_COMPRESSION_TARGET "" PARENT_SCOPE) set(LOG_COMPRESS_SRCS "${compressed_srcs_with_abs_path};${uncompressed_srcs}" PARENT_SCOPE) - list(APPEND include_dirs "common/ble_log/extension/log_compression/include") + if(NOT BLE_COMPRESSED_LIB_LOG_BUILD) + list(APPEND include_dirs "common/ble_log/extension/log_compression/include") + endif() + list(APPEND include_dirs "${CMAKE_BINARY_DIR}/ble_log/include") set(LOG_COMPRESS_INCLUDE_DIRS ${include_dirs} PARENT_SCOPE) else() set(LOG_COMPRESSION_TARGET "" PARENT_SCOPE) diff --git a/components/bt/common/ble_log/extension/log_compression/scripts/ble_log_compress.py b/components/bt/common/ble_log/extension/log_compression/scripts/ble_log_compress.py index da1f4493b68d..c48e067db836 100644 --- a/components/bt/common/ble_log/extension/log_compression/scripts/ble_log_compress.py +++ b/components/bt/common/ble_log/extension/log_compression/scripts/ble_log_compress.py @@ -15,6 +15,7 @@ """ import argparse import enum +import importlib.util import logging import os import re @@ -25,6 +26,7 @@ from datetime import datetime from pathlib import Path from typing import Any +from typing import cast from typing import Dict from typing import List from typing import Tuple @@ -68,10 +70,16 @@ SOURCE_ENUM_MAP = { 'BLE_HOST': 0, 'BLE_MESH': 1, + 'BLE_MESH_LIB': 2, } # Functions that require hex formatting -HEX_FUNCTIONS = ['bt_hex'] # Used in Mesh and Audio modules +HEX_FUNCTIONS = { + # func_name: (arg_cnt, buf_idx, buf_len) + # Negative buf_len indicates constant buffer size + 'bt_hex': (2, 0, 1), # Used in Mesh and Audio modules + 'MAC2STR': (1, 0, -6), # Used in Bluedroid Host +} # C keywords to exclude from function names C_KEYWORDS = { @@ -115,15 +123,6 @@ '__LINE__', } -BLUEDROID_LOG_MODE_LEVEL_GET = { - 'BTM': 'btm_cb.trace_level', - 'L2CAP': 'l2cb.l2cap_trace_level', - 'GAP': 'gap_cb.trace_level', - 'GATT': 'gatt_cb.trace_level', - 'SMP': 'smp_cb.trace_level', - 'APPL': 'appl_trace_level', -} - class ARG_SIZE_TYPE(enum.IntEnum): U32 = 0 @@ -170,11 +169,12 @@ class LogCompressor: """Main class for BLE log compression.""" def __init__(self) -> None: - self.bt_component_path = Path() + self.code_base_path = Path() self.build_dir = Path() self.bt_compressed_srcs_path = Path() self.config: dict[str, Any] = {} self.module_info: dict[str, Any] = {} + self.module_mod: dict[str, Any] = {} def init_parser(self) -> Parser: """Initialize tree-sitter parser for C.""" @@ -367,15 +367,20 @@ def _process_log_node(self, node: Node, function_boundaries: list[tuple[str, int if ( arg_node.type == 'call_expression' and arg_node.child_by_field_name('function') - and arg_node.child_by_field_name('function').text.decode('utf-8') in HEX_FUNCTIONS + and arg_node.child_by_field_name('function').text.decode('utf-8') in HEX_FUNCTIONS.keys() ): # Extract arguments of the hex function + hex_func_name = arg_node.child_by_field_name('function').text.decode('utf-8') hex_args = arg_node.child_by_field_name('arguments') - if hex_args and hex_args.named_child_count >= 2: - buf_node = hex_args.named_children[0] - len_node = hex_args.named_children[1] + hex_func_info = HEX_FUNCTIONS[hex_func_name] + if hex_args and hex_args.named_child_count == hex_func_info[0]: + buf_node = hex_args.named_children[hex_func_info[1]].text.decode('utf-8') + if hex_func_info[2] < 0: + len_node = abs(hex_func_info[2]) + else: + len_node = hex_args.named_children[hex_func_info[2]].text.decode('utf-8') token_list = list(token) - token_list[6] = f'@hex_func@{buf_node.text.decode("utf-8")}@{len_node.text.decode("utf-8")}' + token_list[6] = f'@hex_func@{buf_node}@{len_node}' tokens[tokens_tuple_map[i]] = tuple(token_list) log_info['argu_tokens'] = tokens @@ -415,7 +420,7 @@ def _can_be_hexified(self, token: tuple[int, int, str, str, str, str, str], node if ( node.type == 'call_expression' and node.child_by_field_name('function') - and node.child_by_field_name('function').text.decode('utf-8') in HEX_FUNCTIONS + and node.child_by_field_name('function').text.decode('utf-8') in HEX_FUNCTIONS.keys() ): return True @@ -458,53 +463,6 @@ def generate_compressed_macro( if not log_idx: return '' - def generate_mesh_log_prefix(source: str, tag: str, print_statm: str) -> str: - level = tag.split('_')[-1] - mod = tag.split('_')[0] - if level == 'ERR': - level = 'ERROR' - log_level = 'BLE_MESH_LOG_LEVEL_ERROR' - elif level == 'WARN': - level = 'WARN' - log_level = 'BLE_MESH_LOG_LEVEL_WARN' - elif level == 'INFO': - level = 'INFO' - log_level = 'BLE_MESH_LOG_LEVEL_INFO' - elif level == 'DBG': - level = 'DEBUG' - log_level = 'BLE_MESH_LOG_LEVEL_DEBUG' - else: - LOGGER.error(f'Invalid log level {level}') - return '' - if mod == 'NET': - used_log_levl = 'BLE_MESH_NET_BUF_LOG_LEVEL' - used_log_mod = 'BLE_MESH_NET_BUF' - else: - used_log_levl = 'BLE_MESH_LOG_LEVEL' - used_log_mod = 'BLE_MESH' - return ( - f'{{do {{ if (({used_log_levl} >= {log_level}) &&' - f' BLE_MESH_LOG_LEVEL_CHECK({used_log_mod}, {level})) {print_statm};}} while (0);}}\\\n' - ) - - def generate_bluedroid_log_prefix(source: str, tag: str, print_statm: str) -> str: - tag_info = tag.split('_') - mod = tag_info[0] - - return ( - f'{{if ({BLUEDROID_LOG_MODE_LEVEL_GET[mod]} >= BT_TRACE_LEVEL_{tag_info[-1]} &&' - f' BT_LOG_LEVEL_CHECK({mod}, {tag_info[-1]})) {print_statm};}}\\\n' - ) - - def generate_log_lvl_prefix(source: str, tag: str, print_statm: str) -> str: - if source == 'BLE_MESH': - return ' ' + generate_mesh_log_prefix(source, tag, print_statm) - elif source == 'BLE_HOST': # only bluedroid host supported for now - return ' ' + generate_bluedroid_log_prefix(source, tag, print_statm) - else: - LOGGER.error(f'Unknown source {source}') - return '' - source_value = SOURCE_ENUM_MAP.get(source.upper()) if source_value is None: raise ValueError(f'Invalid source: {source}') @@ -547,41 +505,22 @@ def generate_log_lvl_prefix(source: str, tag: str, print_statm: str) -> str: else: sizes.append(f'{int(ARG_SIZE_TYPE.U32)}') - if arg_count > 0: - size_str = ', '.join(sizes) - arg_str = ', '.join(arguments).replace('\n', '') - macro += generate_log_lvl_prefix( - source, - tag, - (f'BLE_LOG_COMPRESSED_HEX_PRINT({source_value}, {log_idx}, {arg_count}, {size_str}, {arg_str})'), - ) + stmt = self.module_mod[source].gen_compressed_stmt( + log_idx, + source_value, + tag, + log_info['arguments'][0], + [{'name': arg, 'size_type': size_type} for arg, size_type in zip(arguments, sizes)], + [ + { + 'buffer': hex_str.split('@')[2], + 'length': hex_str.split('@')[3], + } + for hex_str in hex_func + ], + ) + macro += cast(str, stmt) - for idx, item in enumerate(hex_func): - # hex_func format: @hex_func@buf@len - parts = item.split('@') - if len(parts) >= 4: - buf = parts[2] - buf_len = parts[3] - macro += generate_log_lvl_prefix( - source, - tag, - (f'BLE_LOG_COMPRESSED_HEX_PRINT_BUF({source_value}, {log_idx}, {idx}, {buf}, {buf_len})'), - ) - else: - macro += generate_log_lvl_prefix( - source, tag, f'BLE_LOG_COMPRESSED_HEX_PRINT_WITH_ZERO_ARGUMENTS({source_value}, {log_idx})' - ) - for idx, item in enumerate(hex_func): - # hex_func format: @hex_func@buf@len - parts = item.split('@') - if len(parts) >= 4: - buf = parts[2] - buf_len = parts[3] - macro += generate_log_lvl_prefix( - source, - tag, - (f'BLE_LOG_COMPRESSED_HEX_PRINT_BUF({source_value}, {log_idx}, {idx}, {buf}, {buf_len})'), - ) if ( 'tags_with_preserve' in self.module_info[source] and tag in self.module_info[source]['tags_with_preserve'] @@ -589,8 +528,7 @@ def generate_log_lvl_prefix(source: str, tag: str, print_statm: str) -> str: macro += f' {tag}(fmt, ##__VA_ARGS__);\\\n' else: # Non-hexified log - print_fmt = print_fmt or 'NULL' - macro += f' BLE_LOG_COMPRESSED_PRINT({source_value}, {log_idx}, "{print_fmt}", ##__VA_ARGS__); \\\n' + raise ValueError('Hexify convert failed') macro += '}\n' return macro @@ -712,7 +650,7 @@ def prepare_source_files(self, srcs: list[str]) -> None: total_cnt = 0 for src in srcs: if pattern.match(src): - src_path = self.bt_component_path / src + src_path = self.code_base_path / src dest_path = self.bt_compressed_srcs_path / src temp_path = f'{dest_path}.tmp' total_cnt += 1 @@ -750,7 +688,7 @@ def generate_log_index_header(self, module: str, macros: list[tuple[int, str]]) module: Module name macros: List of (log_id, macro_definition) """ - # header_path = self.bt_component_path / self.module_info[module]['log_index_path'] + # header_path = self.code_base_path / self.module_info[module]['log_index_path'] header_path = self.build_dir / Path('ble_log') / Path('include') / self.module_info[module]['log_index_file'] # Create directory if needed header_path.parent.mkdir(parents=True, exist_ok=True) @@ -760,8 +698,7 @@ def generate_log_index_header(self, module: str, macros: list[tuple[int, str]]) return elif update_state == self.db_manager.SOURCE_LOG_UPDATE_FULL: # Header template - header_content = ( - textwrap.dedent(f""" + header_content = textwrap.dedent(f""" /* * SPDX-FileCopyrightText: {datetime.now().year} Espressif Systems (Shanghai) CO LTD * @@ -774,22 +711,11 @@ def generate_log_index_header(self, module: str, macros: list[tuple[int, str]]) #include #include - // Compression function declarations - extern int ble_log_compressed_hex_print - (uint32_t source, uint32_t log_index, size_t args_size_cnt, ...); - extern int ble_log_compressed_hex_print_buf - (uint8_t source, uint32_t log_index, uint8_t buf_idx, const uint8_t *buf, size_t len); - - // Compression macros - #define BLE_LOG_COMPRESSED_HEX_PRINT(source, log_index, args_cnt, ...) \\ - ble_log_compressed_hex_print(source, log_index, args_cnt, ##__VA_ARGS__) - #define BLE_LOG_COMPRESSED_HEX_PRINT_BUF(source, log_index, buf_idx, buf, len) \\ - ble_log_compressed_hex_print_buf(source, log_index, buf_idx, (const uint8_t *)buf, len) - #define BLE_LOG_COMPRESSED_HEX_PRINT_WITH_ZERO_ARGUMENTS(source, log_index) \\ - ble_log_compressed_hex_print(source, log_index, 0) """).strip() - + '\n\n' - ) + + header_content += self.module_mod[module].gen_header_head() + header_content += '\n\n' + # Add sorted macros for log_id, macro_def in sorted(macros, key=lambda x: x[0]): header_content += macro_def + '\n' @@ -848,6 +774,14 @@ def load_config(self, config_path: str, module_names: list[str]) -> None: for module in module_names: if module in modules: self.module_info[module] = modules[module] + module_script_path = self.module_info[module]['script'] + spec = self.module_mod[module] = importlib.util.spec_from_file_location(module, module_script_path) + if spec and spec.loader: + self.module_mod[module] = importlib.util.module_from_spec(spec) + spec.loader.exec_module(self.module_mod[module]) + else: + LOGGER.error(f"Failed to load module '{module}' script") + raise ImportError(' Failed to load module script') print(f'Found module {module} for compression\n', flush=True, end='', file=sys.stdout) else: LOGGER.warning(f"Skipping module '{module}' - config not found") @@ -859,7 +793,7 @@ def main(self) -> int: compress_parser = subparsers.add_parser('compress') compress_parser.add_argument('--srcs', required=True, help='Semicolon-separated source file paths') - compress_parser.add_argument('--bt_path', required=True, help='Bluetooth component root path') + compress_parser.add_argument('--code_base_path', required=True, help='Component base path') compress_parser.add_argument('--module', required=True, help='Semicolon-separated module names') compress_parser.add_argument('--build_path', required=True, help='Build output directory') compress_parser.add_argument('--compressed_srcs_path', required=True, help='Directory for processed sources') @@ -867,7 +801,7 @@ def main(self) -> int: args = parser.parse_args() # Setup paths - self.bt_component_path = Path(args.bt_path) + self.code_base_path = Path(args.code_base_path) self.build_dir = Path(args.build_path) self.bt_compressed_srcs_path = Path(args.compressed_srcs_path) @@ -943,7 +877,7 @@ def main(self) -> int: # Mark files as processed for module, info in self.module_info.items(): for temp_path in info['files_to_process']: - src_path = self.bt_component_path / os.path.relpath(temp_path[:-4], self.bt_compressed_srcs_path) + src_path = self.code_base_path / os.path.relpath(temp_path[:-4], self.bt_compressed_srcs_path) db_manager.mark_file_processed(module, src_path, temp_path) for root, _, files in os.walk(self.bt_compressed_srcs_path): for name in files: diff --git a/components/bt/common/ble_log/extension/log_compression/scripts/configs/module_info.yml.in b/components/bt/common/ble_log/extension/log_compression/scripts/configs/module_info.yml.in index 853dcd474865..5201f57503a9 100644 --- a/components/bt/common/ble_log/extension/log_compression/scripts/configs/module_info.yml.in +++ b/components/bt/common/ble_log/extension/log_compression/scripts/configs/module_info.yml.in @@ -6,6 +6,7 @@ log_config: description: "BLE Mesh" code_path: [@BLE_MESH_CODE_PATH@] log_index_file: @BLE_MESH_LOG_INDEX_HEADER@ + script: @BLE_MESH_LOG_SCRIPT_PATH@ tags: [@BLE_MESH_TAGS@] tags_with_preserve: [@BLE_MESH_TAGS_PRESERVE@] @@ -13,5 +14,14 @@ log_config: description: "BLE Host" code_path: [@HOST_CODE_PATH@] log_index_file: @HOST_LOG_INDEX_HEADER@ + script: @BLE_HOST_LOG_SCRIPT_PATH@ tags: [@BLE_HOST_TAGS@] tags_with_preserve: [@BLE_HOST_TAGS_PRESERVE@] + + @BLE_COMPRESSED_LIB_NAME@: + description: "@BLE_COMPRESSED_LIB_DESC@" + code_path: [@BLE_COMPRESSED_LIB_CODE_DIR@] + log_index_file: @BLE_COMPRESSED_LIB_LOG_INDEX_HEADER@ + script: @BLE_COMPRESSED_LIB_LOG_SCRIPT_PATH@ + tags: [@BLE_COMPRESSED_LIB_LOG_TAGS@] + tags_with_preserve: [@BLE_COMPRESSED_LIB_LOG_TAGS_PRESERVE@] diff --git a/components/bt/common/ble_log/extension/log_compression/scripts/inttypes_map.py b/components/bt/common/ble_log/extension/log_compression/scripts/inttypes_map.py index 9e95a18cffef..44f193ac226f 100644 --- a/components/bt/common/ble_log/extension/log_compression/scripts/inttypes_map.py +++ b/components/bt/common/ble_log/extension/log_compression/scripts/inttypes_map.py @@ -163,4 +163,5 @@ 'SCNoPTR': __PRIPTR_PREFIX + 'o', 'SCNuPTR': __PRIPTR_PREFIX + 'u', 'SCNxPTR': __PRIPTR_PREFIX + 'x', + 'MACSTR': '%s', } diff --git a/components/bt/common/ble_log/extension/log_compression/scripts/module_scripts/ble_mesh/make_mesh_log_macro.py b/components/bt/common/ble_log/extension/log_compression/scripts/module_scripts/ble_mesh/make_mesh_log_macro.py new file mode 100644 index 000000000000..791de5f8abb7 --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/scripts/module_scripts/ble_mesh/make_mesh_log_macro.py @@ -0,0 +1,71 @@ +# SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import textwrap + + +def generate_mesh_log_prefix(tag: str, print_statm: str) -> str: + level = tag.split('_')[-1] + mod = tag.split('_')[0] + if level == 'ERR': + level = 'ERROR' + log_level = 'BLE_MESH_LOG_LEVEL_ERROR' + elif level == 'WARN': + level = 'WARN' + log_level = 'BLE_MESH_LOG_LEVEL_WARN' + elif level == 'INFO': + level = 'INFO' + log_level = 'BLE_MESH_LOG_LEVEL_INFO' + elif level == 'DBG': + level = 'DEBUG' + log_level = 'BLE_MESH_LOG_LEVEL_DEBUG' + else: + return '' + if mod == 'NET': + used_log_levl = 'BLE_MESH_NET_BUF_LOG_LEVEL' + used_log_mod = 'BLE_MESH_NET_BUF' + else: + used_log_levl = 'BLE_MESH_LOG_LEVEL' + used_log_mod = 'BLE_MESH' + return ( + f'{{do {{ if (({used_log_levl} >= {log_level}) &&' + f' BLE_MESH_LOG_LEVEL_CHECK({used_log_mod}, {level})) {print_statm};}} while (0);}}\\\n' + ) + + +def gen_header_head() -> str: + head = textwrap.dedent(""" + // Compression function declarations + extern int ble_log_compressed_hex_print + (uint8_t source, uint32_t log_index, size_t args_size_cnt, ...); + extern int ble_log_compressed_hex_print_buf + (uint8_t source, uint32_t log_index, uint8_t buf_idx, const uint8_t *buf, size_t len); + """) + return head + + +def gen_compressed_stmt( + log_index: int, module_id: int, func_name: str, fmt: str, args: list[dict], buffer_args: list[dict] +) -> str: + if len(args) == 0: + stmt = f' ble_log_compressed_hex_print({module_id}, {log_index}, 0);' + for idx, buffer_arg in enumerate(buffer_args): + stmt += '\\\n' + stmt += ( + f' ble_log_compressed_hex_print_buf(' + f'{module_id}, {log_index}, {idx}, ' + f'(const uint8_t *){buffer_arg["buffer"]}, {buffer_arg["length"]});' + ) + stmt += '\\\n' + return ' ' + generate_mesh_log_prefix(func_name, stmt) + size_str = ', '.join([arg['size_type'] for arg in args]) + args_str = ', '.join([arg['name'] for arg in args]).replace('\n', '') + stmt = f' ble_log_compressed_hex_print({module_id}, {log_index}, {len(args)}, {size_str}, {args_str});' + for idx, buffer_arg in enumerate(buffer_args): + stmt += '\\\n' + stmt += ( + f' ble_log_compressed_hex_print_buf(' + f'{module_id}, {log_index}, {idx}, ' + f'(const uint8_t *){buffer_arg["buffer"]}, {buffer_arg["length"]});' + ) + stmt += '\\\n' + return ' ' + generate_mesh_log_prefix(func_name, stmt) diff --git a/components/bt/common/ble_log/extension/log_compression/scripts/module_scripts/bluedroid/make_bluedroid_log_macro.py b/components/bt/common/ble_log/extension/log_compression/scripts/module_scripts/bluedroid/make_bluedroid_log_macro.py new file mode 100644 index 000000000000..72be38c081af --- /dev/null +++ b/components/bt/common/ble_log/extension/log_compression/scripts/module_scripts/bluedroid/make_bluedroid_log_macro.py @@ -0,0 +1,61 @@ +# SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import textwrap + +BLUEDROID_LOG_MODE_LEVEL_GET = { + 'BTM': 'btm_cb.trace_level', + 'L2CAP': 'l2cb.l2cap_trace_level', + 'GAP': 'gap_cb.trace_level', + 'GATT': 'gatt_cb.trace_level', + 'SMP': 'smp_cb.trace_level', + 'APPL': 'appl_trace_level', +} + + +def generate_bluedroid_log_prefix(tag: str, print_statm: str) -> str: + tag_info = tag.split('_') + mod = tag_info[0] + + return ( + f'{{if ({BLUEDROID_LOG_MODE_LEVEL_GET[mod]} >= BT_TRACE_LEVEL_{tag_info[-1]} &&' + f' BT_LOG_LEVEL_CHECK({mod}, {tag_info[-1]})) {print_statm};}}\\\n' + ) + + +def gen_header_head() -> str: + head = textwrap.dedent(""" + // Compression function declarations + extern int ble_log_compressed_hex_print + (uint8_t source, uint32_t log_index, size_t args_size_cnt, ...); + extern int ble_log_compressed_hex_print_buf + (uint8_t source, uint32_t log_index, uint8_t buf_idx, const uint8_t *buf, size_t len); + """) + return head + + +def gen_compressed_stmt( + log_index: int, module_id: int, func_name: str, fmt: str, args: list[dict], buffer_args: list[dict] +) -> str: + if len(args) == 0: + stmt = f' ble_log_compressed_hex_print({module_id},{log_index}, 0);' + for idx, buffer_arg in enumerate(buffer_args): + stmt += '\\\n' + stmt += ( + f' ble_log_compressed_hex_print_buf(' + f'{module_id}, {log_index}, {idx}, ' + f'(const uint8_t *){buffer_arg["buffer"]}, {buffer_arg["length"]});' + ) + stmt += '\\\n' + return ' ' + generate_bluedroid_log_prefix(func_name, stmt) + size_str = ', '.join([arg['size_type'] for arg in args]) + args_str = ', '.join([arg['name'] for arg in args]).replace('\n', '') + stmt = f' ble_log_compressed_hex_print({module_id},{log_index}, {len(args)}, {size_str}, {args_str});' + for idx, buffer_arg in enumerate(buffer_args): + stmt += '\\\n' + stmt += ( + f' ble_log_compressed_hex_print_buf(' + f'{module_id}, {log_index}, {idx}, ' + f'(const uint8_t *){buffer_arg["buffer"]}, {buffer_arg["length"]});' + ) + stmt += '\\\n' + return ' ' + generate_bluedroid_log_prefix(func_name, stmt) diff --git a/components/bt/common/ble_log/src/ble_log_lbm.c b/components/bt/common/ble_log/src/ble_log_lbm.c index 5078f2bad7dc..9b8626d1ad77 100644 --- a/components/bt/common/ble_log/src/ble_log_lbm.c +++ b/components/bt/common/ble_log/src/ble_log_lbm.c @@ -421,6 +421,7 @@ void ble_log_flush(void) BLE_LOG_REF_COUNT_RELEASE(&lbm_ref_count); } +BLE_LOG_IRAM_ATTR bool ble_log_write_hex(ble_log_src_t src_code, const uint8_t *addr, size_t len) { BLE_LOG_REF_COUNT_ACQUIRE(&lbm_ref_count); diff --git a/components/bt/common/ble_log/src/internal_include/ble_log_ts.h b/components/bt/common/ble_log/src/internal_include/ble_log_ts.h index 11e74e1508e5..5e0864b25874 100644 --- a/components/bt/common/ble_log/src/internal_include/ble_log_ts.h +++ b/components/bt/common/ble_log/src/internal_include/ble_log_ts.h @@ -29,10 +29,10 @@ extern uint32_t r_ble_lll_timer_current_tick_get(void); #elif defined(CONFIG_IDF_TARGET_ESP32C2) extern uint32_t r_os_cputime_get32(void); #define BLE_LOG_GET_LC_TS r_os_cputime_get32() -/* Legacy BLE Controller (Wait for support) */ -// #elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) -// extern uint32_t lld_read_clock_us(void); -// #define BLE_LOG_GET_LC_TS lld_read_clock_us() +/* Legacy BLE Controller */ +#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) +extern uint32_t lld_read_clock_us(void); +#define BLE_LOG_GET_LC_TS lld_read_clock_us() #else /* Other targets */ #define BLE_LOG_GET_LC_TS 0 #endif /* BLE targets */ diff --git a/components/bt/common/btc/core/btc_alarm.c b/components/bt/common/btc/core/btc_alarm.c index 6c6177f7a351..67604332c13e 100644 --- a/components/bt/common/btc/core/btc_alarm.c +++ b/components/bt/common/btc/core/btc_alarm.c @@ -12,7 +12,7 @@ void btc_alarm_handler(btc_msg_t *msg) { btc_alarm_args_t *arg = (btc_alarm_args_t *)msg->arg; - BTC_TRACE_DEBUG("%s act %d\n", __FUNCTION__, msg->act); + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); if (arg->cb) { arg->cb(arg->cb_data); diff --git a/components/bt/common/include/bt_common.h b/components/bt/common/include/bt_common.h index 300bbc6d8513..dd57f6f957e1 100644 --- a/components/bt/common/include/bt_common.h +++ b/components/bt/common/include/bt_common.h @@ -61,6 +61,16 @@ #define HEAP_MEMORY_DEBUG FALSE #endif +#if UC_BT_BLUEDROID_THREAD_DEBUG +#define OSI_THREAD_DEBUG TRUE +#else +#define OSI_THREAD_DEBUG FALSE +#endif + +#define OSI_THREAD_BLOCK_TIME UC_BT_BLUEDROID_THREAD_BLOCK_TIME + +#define OSI_THREAD_BLOCK_MSG UC_BT_BLUEDROID_THREAD_BLOCK_MSG + #ifndef BT_BLE_DYNAMIC_ENV_MEMORY #define BT_BLE_DYNAMIC_ENV_MEMORY FALSE #endif @@ -238,6 +248,7 @@ typedef uint64_t UINT64; typedef bool BOOLEAN; /* Maximum UUID size - 16 bytes, and structure to hold any type of UUID. */ #define MAX_UUID_SIZE 16 +#define MAX_UUID_NUM 32 typedef struct { #define LEN_UUID_16 2 diff --git a/components/bt/common/include/bt_user_config.h b/components/bt/common/include/bt_user_config.h index 5632b5fe22ae..2d695fa1c338 100644 --- a/components/bt/common/include/bt_user_config.h +++ b/components/bt/common/include/bt_user_config.h @@ -107,6 +107,24 @@ #define UC_BT_BLUEDROID_MEM_DEBUG FALSE #endif +#ifdef CONFIG_BT_BLUEDROID_THREAD_DEBUG +#define UC_BT_BLUEDROID_THREAD_DEBUG TRUE +#else +#define UC_BT_BLUEDROID_THREAD_DEBUG FALSE +#endif + +#ifdef CONFIG_BT_BLUEDROID_THREAD_BLOCK_TIME +#define UC_BT_BLUEDROID_THREAD_BLOCK_TIME CONFIG_BT_BLUEDROID_THREAD_BLOCK_TIME +#else +#define UC_BT_BLUEDROID_THREAD_BLOCK_TIME 1000 +#endif + +#ifdef CONFIG_BT_BLUEDROID_THREAD_BLOCK_MSG +#define UC_BT_BLUEDROID_THREAD_BLOCK_MSG CONFIG_BT_BLUEDROID_THREAD_BLOCK_MSG +#else +#define UC_BT_BLUEDROID_THREAD_BLOCK_MSG 50 +#endif + #ifdef CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST #define UC_HEAP_ALLOCATION_FROM_SPIRAM_FIRST CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST #else diff --git a/components/bt/common/osi/allocator.c b/components/bt/common/osi/allocator.c index 86fb705b071d..91ec942eb57c 100644 --- a/components/bt/common/osi/allocator.c +++ b/components/bt/common/osi/allocator.c @@ -216,7 +216,9 @@ void *osi_malloc_func(size_t size) void *p = osi_malloc_base(size); if (size != 0 && p == NULL) { - OSI_TRACE_ERROR("malloc failed (caller=%p size=%u)\n", __builtin_return_address(0), size); + OSI_TRACE_ERROR("malloc failed (caller=%p size=%u)", __builtin_return_address(0), size); + OSI_TRACE_ERROR("heap info: free=%d, largest_block=%d", + heap_caps_get_free_size(MALLOC_CAP_DEFAULT), heap_caps_get_largest_free_block(MALLOC_CAP_DEFAULT)); #if HEAP_ALLOCATION_FAILS_ABORT assert(0); #endif @@ -230,7 +232,9 @@ void *osi_calloc_func(size_t size) void *p = osi_calloc_base(size); if (size != 0 && p == NULL) { - OSI_TRACE_ERROR("calloc failed (caller=%p size=%u)\n", __builtin_return_address(0), size); + OSI_TRACE_ERROR("calloc failed (caller=%p size=%u)", __builtin_return_address(0), size); + OSI_TRACE_ERROR("heap info: free=%d, largest_block=%d", + heap_caps_get_free_size(MALLOC_CAP_DEFAULT), heap_caps_get_largest_free_block(MALLOC_CAP_DEFAULT)); #if HEAP_ALLOCATION_FAILS_ABORT assert(0); #endif @@ -241,8 +245,5 @@ void *osi_calloc_func(size_t size) void osi_free_func(void *ptr) { -#if HEAP_MEMORY_DEBUG - osi_mem_dbg_clean(ptr, __func__, __LINE__); -#endif - free(ptr); + osi_free(ptr); } diff --git a/components/bt/common/osi/include/osi/allocator.h b/components/bt/common/osi/include/osi/allocator.h index d95040538d86..071892ffafea 100644 --- a/components/bt/common/osi/include/osi/allocator.h +++ b/components/bt/common/osi/include/osi/allocator.h @@ -21,6 +21,7 @@ #include #include +#include "bt_common.h" #include "esp_heap_caps.h" char *osi_strdup(const char *str); diff --git a/components/bt/common/osi/thread.c b/components/bt/common/osi/thread.c index 91bc7906ceab..95475670be52 100644 --- a/components/bt/common/osi/thread.c +++ b/components/bt/common/osi/thread.c @@ -61,6 +61,10 @@ struct osi_event { static const size_t DEFAULT_WORK_QUEUE_CAPACITY = 100; +#if OSI_THREAD_DEBUG +static void osi_thread_run_item(osi_thread_t *thread, int wq_idx, struct work_item *item); +#endif + static struct work_queue *osi_work_queue_create(size_t capacity) { if (capacity == 0) { @@ -162,7 +166,11 @@ static void osi_thread_run(void *arg) struct work_item item; while (!thread->stop && idx < thread->work_queue_num) { if (osi_thead_work_queue_get(thread->work_queues[idx], &item) == true) { + #if OSI_THREAD_DEBUG + osi_thread_run_item(thread, idx, &item); + #else item.func(item.context); + #endif idx = 0; continue; } else { @@ -451,3 +459,45 @@ bool osi_thread_post_event(struct osi_event *event, uint32_t timeout) return ret; } + +#if OSI_THREAD_DEBUG +static void osi_thread_run_item(osi_thread_t *thread, int wq_idx, struct work_item *item) +{ + uint32_t pre_time; + uint32_t pre_msg_cnt; + uint32_t cur_time; + uint32_t cur_msg_cnt; + + pre_time = esp_log_timestamp(); + pre_msg_cnt = uxQueueMessagesWaiting(thread->work_queues[wq_idx]->queue); + item->func(item->context); + cur_time = esp_log_timestamp(); + cur_msg_cnt = uxQueueMessagesWaiting(thread->work_queues[wq_idx]->queue); + if ((cur_time - pre_time) >= OSI_THREAD_BLOCK_TIME || + (cur_msg_cnt > pre_msg_cnt && (cur_msg_cnt - pre_msg_cnt) >= OSI_THREAD_BLOCK_MSG)) { + OSI_TRACE_ERROR("%s was blocked while running item: %p exec_time=[%u %u] msg_inc=[%u %u]", + pcTaskGetName(thread->thread_handle), item->func, cur_time, pre_time, cur_msg_cnt, pre_msg_cnt); + assert(0); + } +} + +void osi_thread_workqueue_dump(osi_thread_t *thread) +{ + int idx = 0; + struct work_item item; + + vTaskSuspendAll(); + + while (idx < thread->work_queue_num) { + if (osi_thead_work_queue_get(thread->work_queues[idx], &item) == true) { + esp_rom_printf("[%u] %p %p\n", idx, item.func, item.context); + idx = 0; + continue; + } else { + idx++; + } + } + + xTaskResumeAll(); +} +#endif // OSI_THREAD_DEBUG diff --git a/components/bt/controller/esp32c6/Kconfig.in b/components/bt/controller/esp32c6/Kconfig.in index 93ba37845426..a2f5ec997b10 100644 --- a/components/bt/controller/esp32c6/Kconfig.in +++ b/components/bt/controller/esp32c6/Kconfig.in @@ -977,3 +977,11 @@ menu "Scheduling Priority Level Config" default 2 if BT_LE_SYNC_SCHED_PRIO_HIGH_LEVEL default 1 endmenu + +config BT_LE_CTRL_SLV_FAST_RX_CONN_DATA_EN + bool "Enable Peripheral fast PDU reception during latency" + default n + help + When this option is enabled, the Controller continues receiving PDUs + In the next connection event instead of entering latency + After a data packet is received. diff --git a/components/bt/controller/esp32c6/bt.c b/components/bt/controller/esp32c6/bt.c index 0b7825de344a..a442f8d85c83 100644 --- a/components/bt/controller/esp32c6/bt.c +++ b/components/bt/controller/esp32c6/bt.c @@ -167,7 +167,7 @@ extern void esp_unregister_npl_funcs (void); extern void npl_freertos_mempool_deinit(void); extern uint32_t r_os_cputime_get32(void); extern uint32_t r_os_cputime_ticks_to_usecs(uint32_t ticks); -extern void r_ble_lll_rfmgmt_set_sleep_cb(void *s_cb, void *w_cb, void *s_arg, +extern void r_ble_lll_sleep_set_sleep_cb(void *s_cb, void *w_cb, void *s_arg, void *w_arg, uint32_t us_to_enabled); extern void r_ble_rtc_wake_up_state_clr(void); extern int os_msys_init(void); @@ -848,10 +848,10 @@ esp_err_t controller_sleep_init(void) #ifdef CONFIG_BT_LE_SLEEP_ENABLE ESP_LOGW(NIMBLE_PORT_LOG_TAG, "BLE modem sleep is enabled"); #if CONFIG_FREERTOS_USE_TICKLESS_IDLE - r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, + r_ble_lll_sleep_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, BLE_RTC_DELAY_US_LIGHT_SLEEP); #else - r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, + r_ble_lll_sleep_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, BLE_RTC_DELAY_US_MODEM_SLEEP); #endif /* FREERTOS_USE_TICKLESS_IDLE */ #endif // CONFIG_BT_LE_SLEEP_ENABLE diff --git a/components/bt/controller/esp32c6/esp_bt_cfg.h b/components/bt/controller/esp32c6/esp_bt_cfg.h index 2586976c90d5..71f7f9d19404 100644 --- a/components/bt/controller/esp32c6/esp_bt_cfg.h +++ b/components/bt/controller/esp32c6/esp_bt_cfg.h @@ -212,6 +212,12 @@ extern "C" { #define DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN (0) #endif +#if defined(CONFIG_BT_LE_CTRL_SLV_FAST_RX_CONN_DATA_EN) +#define DEFAULT_BT_LE_CTRL_SLV_FAST_RX_CONN_DATA_EN (CONFIG_BT_LE_CTRL_SLV_FAST_RX_CONN_DATA_EN) +#else +#define DEFAULT_BT_LE_CTRL_SLV_FAST_RX_CONN_DATA_EN (0) +#endif + #ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART #define HCI_UART_EN CONFIG_BT_LE_HCI_INTERFACE_USE_UART #else diff --git a/components/bt/controller/esp32h2/Kconfig.in b/components/bt/controller/esp32h2/Kconfig.in index 17a1d9abf2ce..00ae776c2d78 100644 --- a/components/bt/controller/esp32h2/Kconfig.in +++ b/components/bt/controller/esp32h2/Kconfig.in @@ -981,3 +981,11 @@ menu "Scheduling Priority Level Config" default 2 if BT_LE_SYNC_SCHED_PRIO_HIGH_LEVEL default 1 endmenu + +config BT_LE_CTRL_SLV_FAST_RX_CONN_DATA_EN + bool "Enable Peripheral fast PDU reception during latency" + default n + help + When this option is enabled, the Controller continues receiving PDUs + In the next connection event instead of entering latency + After a data packet is received. diff --git a/components/bt/controller/esp32h2/bt.c b/components/bt/controller/esp32h2/bt.c index 4daa9d3fbeba..6ea4185a2712 100644 --- a/components/bt/controller/esp32h2/bt.c +++ b/components/bt/controller/esp32h2/bt.c @@ -159,7 +159,7 @@ extern void esp_unregister_npl_funcs (void); extern void npl_freertos_mempool_deinit(void); extern uint32_t r_os_cputime_get32(void); extern uint32_t r_os_cputime_ticks_to_usecs(uint32_t ticks); -extern void r_ble_lll_rfmgmt_set_sleep_cb(void *s_cb, void *w_cb, void *s_arg, +extern void r_ble_lll_sleep_set_sleep_cb(void *s_cb, void *w_cb, void *s_arg, void *w_arg, uint32_t us_to_enabled); extern void r_ble_rtc_wake_up_state_clr(void); extern int os_msys_init(void); @@ -816,10 +816,10 @@ esp_err_t controller_sleep_init(void) #ifdef CONFIG_BT_LE_SLEEP_ENABLE ESP_LOGW(NIMBLE_PORT_LOG_TAG, "BLE modem sleep is enabled"); #if CONFIG_FREERTOS_USE_TICKLESS_IDLE - r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, + r_ble_lll_sleep_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, BLE_RTC_DELAY_US_LIGHT_SLEEP); #else - r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, + r_ble_lll_sleep_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, BLE_RTC_DELAY_US_MODEM_SLEEP); #endif /* FREERTOS_USE_TICKLESS_IDLE */ #endif // CONFIG_BT_LE_SLEEP_ENABLE diff --git a/components/bt/controller/esp32h2/esp_bt_cfg.h b/components/bt/controller/esp32h2/esp_bt_cfg.h index e79eb742e2dd..4dbe2f2fe89b 100644 --- a/components/bt/controller/esp32h2/esp_bt_cfg.h +++ b/components/bt/controller/esp32h2/esp_bt_cfg.h @@ -209,6 +209,12 @@ extern "C" { #define DEFAULT_BT_LE_CTRL_FAST_CONN_DATA_TX_EN (0) #endif +#if defined(CONFIG_BT_LE_CTRL_SLV_FAST_RX_CONN_DATA_EN) +#define DEFAULT_BT_LE_CTRL_SLV_FAST_RX_CONN_DATA_EN (CONFIG_BT_LE_CTRL_SLV_FAST_RX_CONN_DATA_EN) +#else +#define DEFAULT_BT_LE_CTRL_SLV_FAST_RX_CONN_DATA_EN (0) +#endif + #ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART #define HCI_UART_EN CONFIG_BT_LE_HCI_INTERFACE_USE_UART #else diff --git a/components/bt/controller/lib_esp32 b/components/bt/controller/lib_esp32 index 45910ee1e502..05e9c75b8977 160000 --- a/components/bt/controller/lib_esp32 +++ b/components/bt/controller/lib_esp32 @@ -1 +1 @@ -Subproject commit 45910ee1e50236e9d7219429666d7be7965427aa +Subproject commit 05e9c75b8977a3767c5cf5afedcd4c7f8c0f5f62 diff --git a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib index c82c623de457..7c104a8d09e3 160000 --- a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib +++ b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib @@ -1 +1 @@ -Subproject commit c82c623de457e1b06cf0dad5c963d023dbb6fe76 +Subproject commit 7c104a8d09e35f3244636fcf01004d5c767f12c2 diff --git a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib index 1495595b82f5..cf7c287226c2 160000 --- a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib +++ b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib @@ -1 +1 @@ -Subproject commit 1495595b82f5423d12b325960ae89bc604ebdcd4 +Subproject commit cf7c287226c2c8575dc1cb9896d54a14a18d1dd4 diff --git a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib index 9cfbeb5f1637..a568fa5a0354 160000 --- a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib +++ b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib @@ -1 +1 @@ -Subproject commit 9cfbeb5f163788174073da19b3cd09c4d00cc860 +Subproject commit a568fa5a03545dd133a301ccdbae99afa3692923 diff --git a/components/bt/esp_ble_mesh/core/access.c b/components/bt/esp_ble_mesh/core/access.c index 3791add9e34f..a616928b0d97 100644 --- a/components/bt/esp_ble_mesh/core/access.c +++ b/components/bt/esp_ble_mesh/core/access.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -25,7 +25,7 @@ #if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" -#endif +#endif /* CONFIG_BLE_MESH_V11_SUPPORT */ #define BLE_MESH_SDU_MAX_LEN 384 @@ -45,6 +45,8 @@ void bt_mesh_model_foreach(void (*func)(struct bt_mesh_model *mod, { int i, j; + BT_DBG("ModelForeach"); + if (comp_0 == NULL) { BT_ERR("Invalid device composition"); return; @@ -53,15 +55,21 @@ void bt_mesh_model_foreach(void (*func)(struct bt_mesh_model *mod, for (i = 0; i < comp_0->elem_count; i++) { struct bt_mesh_elem *elem = &comp_0->elem[i]; + BT_DBG("Element %u", i); + for (j = 0; j < elem->model_count; j++) { struct bt_mesh_model *model = &elem->models[j]; + BT_DBG("ID 0x%04x", model->id); + func(model, elem, false, i == 0, user_data); } for (j = 0; j < elem->vnd_model_count; j++) { struct bt_mesh_model *model = &elem->vnd_models[j]; + BT_DBG("ID 0x%04x CID 0x%04x", model->vnd.id, model->vnd.company); + func(model, elem, true, i == 0, user_data); } } @@ -71,6 +79,8 @@ int32_t bt_mesh_model_pub_period_get(struct bt_mesh_model *mod) { int period = 0; + BT_DBG("ModelPubPeriodGet"); + if (!mod->pub) { BT_ERR("Model has no publication support"); return 0; @@ -98,6 +108,9 @@ int32_t bt_mesh_model_pub_period_get(struct bt_mesh_model *mod) return 0; } + BT_DBG("Period %ld FastPeriod %u PeriodDiv %u", + period, mod->pub->fast_period, mod->pub->period_div); + if (mod->pub->fast_period) { return period >> mod->pub->period_div; } @@ -110,19 +123,22 @@ static int32_t next_period(struct bt_mesh_model *mod) struct bt_mesh_model_pub *pub = mod->pub; uint32_t elapsed = 0U, period = 0U; + BT_DBG("NextPeriod"); + if (!pub) { BT_ERR("Model has no publication support"); - return -ENOTSUP; + return 0; } period = bt_mesh_model_pub_period_get(mod); if (!period) { + BT_DBG("PeriodZero"); return 0; } elapsed = k_uptime_get_32() - pub->period_start; - BT_INFO("Publishing took %ums", elapsed); + BT_INFO("Elapsed %u Period %u", elapsed, period); if (elapsed >= period) { BT_WARN("Publication sending took longer than the period"); @@ -138,7 +154,7 @@ static void publish_sent(int err, void *user_data) struct bt_mesh_model *mod = user_data; int32_t delay = 0; - BT_DBG("err %d", err); + BT_DBG("PublishSent, Err %d", err); if (!mod->pub) { BT_ERR("Model has no publication support"); @@ -151,8 +167,9 @@ static void publish_sent(int err, void *user_data) delay = next_period(mod); } + BT_DBG("PubCount %u PubDelay %ld", mod->pub->count, delay); + if (delay) { - BT_INFO("Publishing next time in %dms", delay); k_delayed_work_submit(&mod->pub->timer, delay); } } @@ -162,6 +179,8 @@ static void publish_start(uint16_t duration, int err, void *user_data) struct bt_mesh_model *mod = user_data; struct bt_mesh_model_pub *pub = mod->pub; + BT_DBG("PublishStart, Err %d", err); + if (err) { BT_ERR("Failed to publish: err %d", err); return; @@ -191,6 +210,8 @@ static int publish_retransmit(struct bt_mesh_model *mod) }; int err = 0; + BT_DBG("PublishRetransmit"); + if (!pub || !pub->msg) { BT_ERR("Model has no publication support"); return -ENOTSUP; @@ -219,9 +240,14 @@ static int publish_retransmit(struct bt_mesh_model *mod) ctx.send_tag |= BLE_MESH_TAG_SEND_SEGMENTED; } + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Dst 0x%04x", + ctx.net_idx, ctx.app_idx, ctx.addr); + BT_DBG("TTL %u SendCred %u SendRel %u PubCount %u", + ctx.send_ttl, ctx.send_cred, pub->send_rel, pub->count); + #if CONFIG_BLE_MESH_DF_SRV bt_mesh_model_pub_use_directed(&tx, pub->directed_pub_policy); -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ sdu = bt_mesh_alloc_buf(pub->msg->len + BLE_MESH_MIC_LONG); if (!sdu) { @@ -241,8 +267,11 @@ static int publish_retransmit(struct bt_mesh_model *mod) static void publish_retransmit_end(int err, struct bt_mesh_model_pub *pub) { + BT_DBG("PublishRetransmitEnd, Err %d", err); + /* Cancel all retransmits for this publish attempt */ pub->count = 0U; + /* Make sure the publish timer gets reset */ publish_sent(err, pub->mod); } @@ -256,7 +285,8 @@ static void mod_publish(struct k_work *work) int err = 0; period_ms = bt_mesh_model_pub_period_get(pub->mod); - BT_INFO("Publish period %u ms", period_ms); + + BT_INFO("ModPublish, Period %u", period_ms); if (pub->count) { err = publish_retransmit(pub->mod); @@ -284,6 +314,7 @@ static void mod_publish(struct k_work *work) if (pub->update && pub->update(pub->mod)) { /* Cancel this publish attempt. */ BT_ERR("Update failed, skipping publish (err %d)", err); + pub->period_start = k_uptime_get_32(); publish_retransmit_end(err, pub); return; @@ -297,6 +328,8 @@ static void mod_publish(struct k_work *work) struct bt_mesh_elem *bt_mesh_model_elem(struct bt_mesh_model *mod) { + BT_DBG("ModelElem, ElemIdx %u", mod->elem_idx); + return &comp_0->elem[mod->elem_idx]; } @@ -304,6 +337,8 @@ struct bt_mesh_model *bt_mesh_model_get(bool vnd, uint8_t elem_idx, uint8_t mod_ { struct bt_mesh_elem *elem = NULL; + BT_DBG("ModelGet, ElemIdx %u ModIdx %u Vnd %u", elem_idx, mod_idx, vnd); + if (!comp_0) { BT_ERR("comp_0 not initialized"); return NULL; @@ -339,6 +374,8 @@ static void mod_init(struct bt_mesh_model *mod, struct bt_mesh_elem *elem, int *err = user_data; int i; + BT_DBG("ModInit, Vnd %u Primary %u", vnd, primary); + if (!user_data) { BT_ERR("Invalid model init user data"); return; @@ -368,6 +405,8 @@ static void mod_init(struct bt_mesh_model *mod, struct bt_mesh_elem *elem, mod->model_idx = mod - elem->models; } + BT_DBG("ElemIdx %u ModelIdx %u", mod->elem_idx, mod->model_idx); + if (vnd) { return; } @@ -381,6 +420,8 @@ int bt_mesh_comp_register(const struct bt_mesh_comp *comp) { int err = 0; + BT_DBG("CompRegister, ElemCount %u", comp->elem_count); + /* There must be at least one element */ if (!comp->elem_count) { return -EINVAL; @@ -400,6 +441,8 @@ static void mod_deinit(struct bt_mesh_model *mod, struct bt_mesh_elem *elem, int *err = user_data; int i; + BT_DBG("ModDeinit, Vnd %u Primary %u", vnd, primary); + if (!user_data) { BT_ERR("Invalid model deinit user data"); return; @@ -438,6 +481,8 @@ int bt_mesh_comp_deregister(void) { int err = 0; + BT_DBG("CompDeregister"); + if (comp_0 == NULL) { return -EINVAL; } @@ -456,25 +501,29 @@ void bt_mesh_comp_provision(uint16_t addr) dev_primary_addr = addr; - BT_INFO("Primary address 0x%04x, element count %u", addr, comp_0->elem_count); + BT_INFO("CompProvision, PrimaryAddr 0x%04x ElemCount %u", addr, comp_0->elem_count); for (i = 0; i < comp_0->elem_count; i++) { struct bt_mesh_elem *elem = &comp_0->elem[i]; elem->addr = addr++; - BT_DBG("addr 0x%04x mod_count %u vnd_mod_count %u", + BT_DBG("ElemAddr 0x%04x ModCount %u VndModCount %u", elem->addr, elem->model_count, elem->vnd_model_count); } } void bt_mesh_comp_unprovision(void) { + BT_DBG("CompUnprovision"); + dev_primary_addr = BLE_MESH_ADDR_UNASSIGNED; } uint16_t bt_mesh_primary_addr(void) { + BT_DBG("PrimaryAddr 0x%04x", dev_primary_addr); + return dev_primary_addr; } @@ -482,12 +531,16 @@ uint16_t *bt_mesh_model_find_group(struct bt_mesh_model *mod, uint16_t addr) { int i; + BT_DBG("ModelFindGroup, Addr 0x%04x", addr); + for (i = 0; i < ARRAY_SIZE(mod->groups); i++) { if (mod->groups[i] == addr) { + BT_DBG("ModGroupFound"); return &mod->groups[i]; } } + BT_DBG("ModGroupNotFound"); return NULL; } @@ -498,6 +551,8 @@ static struct bt_mesh_model *bt_mesh_elem_find_group(struct bt_mesh_elem *elem, uint16_t *match = NULL; int i; + BT_DBG("ElemFindGroup, Addr 0x%04x", group_addr); + for (i = 0; i < elem->model_count; i++) { model = &elem->models[i]; @@ -523,6 +578,8 @@ struct bt_mesh_elem *bt_mesh_elem_find(uint16_t addr) { uint16_t index = 0U; + BT_DBG("ElemFind, Addr 0x%04x", addr); + if (BLE_MESH_ADDR_IS_UNICAST(addr)) { index = (addr - comp_0->elem[0].addr); if (index < comp_0->elem_count) { @@ -545,6 +602,8 @@ struct bt_mesh_elem *bt_mesh_elem_find(uint16_t addr) uint8_t bt_mesh_elem_count(void) { + BT_DBG("ElemCount %u", comp_0->elem_count); + return comp_0->elem_count; } @@ -552,6 +611,8 @@ static bool model_has_key(struct bt_mesh_model *mod, uint16_t key) { int i; + BT_DBG("ModelHasKey, AppIdx 0x%04x", key); + for (i = 0; i < ARRAY_SIZE(mod->keys); i++) { if (mod->keys[i] == key) { return true; @@ -565,6 +626,8 @@ static bool model_has_dst(struct bt_mesh_model *model, struct bt_mesh_subnet *sub, uint16_t dst) { + BT_DBG("ModelHasDst, Dst 0x%04x", dst); + if (BLE_MESH_ADDR_IS_UNICAST(dst)) { return (comp_0->elem[model->elem_idx].addr == dst); } @@ -583,6 +646,8 @@ static const struct bt_mesh_model_op *find_op(struct bt_mesh_model *models, { int i; + BT_DBG("FindOp, ModelCount %u Opcode 0x%08lx", model_count, opcode); + for (i = 0; i < model_count; i++) { const struct bt_mesh_model_op *op; @@ -601,6 +666,8 @@ static const struct bt_mesh_model_op *find_op(struct bt_mesh_model *models, static int get_opcode(struct net_buf_simple *buf, uint32_t *opcode, bool pull_buf) { + BT_DBG("GetOpCode, PullBuf %u", pull_buf); + switch (buf->data[0] >> 6) { case 0x00: case 0x01: @@ -646,6 +713,8 @@ static int get_opcode(struct net_buf_simple *buf, uint32_t *opcode, bool pull_bu int bt_mesh_get_opcode(struct net_buf_simple *buf, uint32_t *opcode, bool pull_buf) { + BT_DBG("GetOpCode"); + if (buf == NULL || buf->len == 0 || opcode == NULL) { BT_ERR("%s, Invalid parameter", __func__); return -EINVAL; @@ -656,6 +725,8 @@ int bt_mesh_get_opcode(struct net_buf_simple *buf, bool bt_mesh_fixed_group_match(uint16_t addr) { + BT_DBG("FixedGroupMatch, Addr 0x%04x", addr); + /* Check for fixed group addresses */ switch (addr) { case BLE_MESH_ADDR_ALL_NODES: @@ -677,12 +748,14 @@ bool bt_mesh_fixed_direct_match(struct bt_mesh_subnet *sub, uint16_t addr) * shall be processed by the primary element of all nodes that * have directed forwarding functionality enabled. */ + BT_DBG("FixedDirectMatch, Addr 0x%04x", addr); + #if CONFIG_BLE_MESH_DF_SRV if (addr == BLE_MESH_ADDR_DIRECTS && sub && sub->directed_forwarding == BLE_MESH_DIRECTED_FORWARDING_ENABLED) { return true; } -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ return false; } @@ -695,16 +768,17 @@ void bt_mesh_model_recv(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) uint8_t count = 0U; int i; - BT_INFO("recv, app_idx 0x%04x src 0x%04x dst 0x%04x", rx->ctx.app_idx, - rx->ctx.addr, rx->ctx.recv_dst); - BT_INFO("recv, len %u: %s", buf->len, bt_hex(buf->data, buf->len)); + BT_INFO("ModelRecv"); + BT_INFO("AppIdx 0x%04x Src 0x%04x Dst 0x%04x", + rx->ctx.app_idx, rx->ctx.addr, rx->ctx.recv_dst); + BT_INFO("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); if (get_opcode(buf, &opcode, true) < 0) { BT_WARN("Unable to decode OpCode"); return; } - BT_DBG("OpCode 0x%08x", opcode); + BT_DBG("OpCode 0x%08lx RecvCred %u", opcode, rx->ctx.recv_cred); for (i = 0; i < comp_0->elem_count; i++) { struct bt_mesh_elem *elem = &comp_0->elem[i]; @@ -729,10 +803,12 @@ void bt_mesh_model_recv(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) } if (!model_has_key(model, rx->ctx.app_idx)) { + BT_DBG("ModelNotHasKey"); continue; } if (!model_has_dst(model, rx->sub, rx->ctx.recv_dst)) { + BT_DBG("ModelNotHasDst"); continue; } @@ -776,6 +852,8 @@ void bt_mesh_model_recv(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) void bt_mesh_model_msg_init(struct net_buf_simple *msg, uint32_t opcode) { + BT_DBG("ModelMsgInit, OpCode 0x%08lx", opcode); + net_buf_simple_init(msg, 0); switch (BLE_MESH_MODEL_OP_LEN(opcode)) { @@ -801,6 +879,8 @@ void bt_mesh_model_msg_init(struct net_buf_simple *msg, uint32_t opcode) static bool ready_to_send(uint16_t dst) { + BT_DBG("IsReadyToSend, Dst 0x%04x", dst); + if (IS_ENABLED(CONFIG_BLE_MESH_NODE) && bt_mesh_is_provisioned()) { return true; } @@ -808,7 +888,7 @@ static bool ready_to_send(uint16_t dst) if (IS_ENABLED(CONFIG_BLE_MESH_PROVISIONER) && bt_mesh_is_provisioner_en()) { if (bt_mesh_provisioner_check_msg_dst(dst) == false && bt_mesh_elem_find(dst) == false) { - BT_ERR("Failed to find DST 0x%04x", dst); + BT_ERR("Failed to find Dst 0x%04x", dst); return false; } return true; @@ -820,15 +900,19 @@ static bool ready_to_send(uint16_t dst) #if !CONFIG_BLE_MESH_V11_SUPPORT static bool use_friend_cred(uint16_t net_idx, uint16_t dst) { + BT_DBG("IsFrndCredUsed, NetIdx 0x%04x Dst 0x%04x", net_idx, dst); + /* Currently LPN only supports using NetKey in bt_mesh.sub[0] */ if (IS_ENABLED(CONFIG_BLE_MESH_LOW_POWER) && net_idx == 0 && bt_mesh_lpn_match(dst)) { + BT_DBG("LPNMatch"); return true; } if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND) && bt_mesh_friend_match(net_idx, dst)) { + BT_DBG("FrndMatch"); return true; } @@ -843,6 +927,9 @@ bool bt_mesh_valid_security_cred(struct bt_mesh_net_tx *tx) * If not, later a better security credentials could be * chosen for the message. */ + BT_DBG("IsValidSecCred, NetIdx 0x%04x Tag 0x%02x Cred %u", + tx->ctx->net_idx, tx->ctx->send_tag, tx->ctx->send_cred); + if (!bt_mesh_tag_immutable_cred(tx->ctx->send_tag)) { return true; } @@ -871,22 +958,27 @@ void bt_mesh_choose_better_security_cred(struct bt_mesh_net_tx *tx) net_idx = tx->ctx->net_idx; addr = tx->ctx->addr; + BT_DBG("ChooseBetterSecCred"); + BT_DBG("NetIdx 0x%04x Dst 0x%04x Tag 0x%02x Cred %u", + net_idx, addr, send_tag, send_cred); + /* If the message is tagged with immutable-credentials, * then the security credentials shall not be changed. */ if (bt_mesh_tag_immutable_cred(send_tag)) { + BT_DBG("ImmutableCred"); return; } if (send_cred > BLE_MESH_FRIENDSHIP_CRED) { - BT_INFO("Use managed flooding security credentials"); + BT_INFO("UseFloodingSecCred"); tx->ctx->send_cred = BLE_MESH_FLOODING_CRED; return; } if (send_cred == BLE_MESH_FRIENDSHIP_CRED) { if (!use_friend_cred(net_idx, addr)) { - BT_INFO("Use managed flooding security credentials"); + BT_INFO("UseFloodingSecCred"); tx->ctx->send_cred = BLE_MESH_FLOODING_CRED; tx->ctx->send_tag = send_tag | BLE_MESH_TAG_IMMUTABLE_CRED; } else { @@ -911,14 +1003,13 @@ void bt_mesh_choose_better_security_cred(struct bt_mesh_net_tx *tx) if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND) && BLE_MESH_ADDR_IS_UNICAST(addr) && bt_mesh_friend_match(net_idx, addr)) { - BT_INFO("Use friendship security credentials"); + BT_INFO("UseFrndSecCred"); tx->ctx->send_cred = BLE_MESH_FRIENDSHIP_CRED; tx->ctx->send_tag = send_tag | BLE_MESH_TAG_IMMUTABLE_CRED; return; } - /** - * Spec 3.7.3.1 + /* Spec 3.7.3.1 * The Low power node in friendship should use friendship security * material. * @@ -938,11 +1029,12 @@ void bt_mesh_choose_better_security_cred(struct bt_mesh_net_tx *tx) if (BLE_MESH_ADDR_IS_UNICAST(addr) && bt_mesh.lpn.frnd == addr && !bt_mesh_tag_immutable_cred(send_tag)) { + BT_INFO("UseFrndSecCred"); tx->ctx->send_cred = BLE_MESH_FRIENDSHIP_CRED; tx->ctx->send_tag = send_tag | BLE_MESH_TAG_IMMUTABLE_CRED; return; } -#endif +#endif /* CONFIG_BLE_MESH_LOW_POWER */ } #endif /* !CONFIG_BLE_MESH_V11_SUPPORT */ @@ -953,9 +1045,10 @@ static int model_send(struct bt_mesh_model *model, { int err = 0; - BT_INFO("send, app_idx 0x%04x src 0x%04x dst 0x%04x", - tx->ctx->app_idx, tx->src, tx->ctx->addr); - BT_INFO("send, len %u: %s", msg->len, bt_hex(msg->data, msg->len)); + BT_INFO("ModelSend"); + BT_INFO("AppIdx 0x%04x Src 0x%04x Dst 0x%04x TTL %u", + tx->ctx->app_idx, tx->src, tx->ctx->addr, tx->ctx->send_ttl); + BT_INFO("Len %u: %s", msg->len, bt_hex(msg->data, msg->len)); if (ready_to_send(tx->ctx->addr) == false) { BT_ERR("Not ready to send"); @@ -994,7 +1087,7 @@ static int model_send(struct bt_mesh_model *model, #if CONFIG_BLE_MESH_DF_SRV bt_mesh_is_directed_path_needed(tx); -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ return err; } @@ -1006,9 +1099,11 @@ int bt_mesh_model_send_implicit(struct bt_mesh_model *model, { struct bt_mesh_subnet *sub = NULL; + BT_DBG("ModelSendImplicit"); + sub = bt_mesh_subnet_get(ctx->net_idx); if (!sub) { - BT_ERR("Send, NetKey 0x%04x not found", ctx->net_idx); + BT_ERR("NetIdx 0x%04x not found", ctx->net_idx); return -EADDRNOTAVAIL; } @@ -1029,9 +1124,11 @@ int bt_mesh_model_send(struct bt_mesh_model *model, { struct bt_mesh_subnet *sub = NULL; + BT_DBG("ModelSend, NetIdx 0x%04x", ctx->net_idx); + sub = bt_mesh_subnet_get(ctx->net_idx); if (!sub) { - BT_ERR("Send, NetKey 0x%04x not found", ctx->net_idx); + BT_ERR("NetIdx 0x%04x not found", ctx->net_idx); return -EADDRNOTAVAIL; } @@ -1058,6 +1155,8 @@ int bt_mesh_model_publish(struct bt_mesh_model *model) }; int err = 0; + BT_DBG("ModelPublish"); + if (!pub || !pub->msg) { BT_ERR("Model has no publication support"); return -ENOTSUP; @@ -1106,12 +1205,12 @@ int bt_mesh_model_publish(struct bt_mesh_model *model) #if CONFIG_BLE_MESH_DF_SRV bt_mesh_model_pub_use_directed(&tx, pub->directed_pub_policy); -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ pub->count = BLE_MESH_PUB_TRANSMIT_COUNT(pub->retransmit); - BT_INFO("Publish Retransmit Count %u Interval %ums", pub->count, - BLE_MESH_PUB_TRANSMIT_INT(pub->retransmit)); + BT_INFO("PubCount %u PubInterval %u", + pub->count, BLE_MESH_PUB_TRANSMIT_INT(pub->retransmit)); sdu = bt_mesh_alloc_buf(pub->msg->len + BLE_MESH_MIC_LONG); if (!sdu) { @@ -1135,6 +1234,8 @@ struct bt_mesh_model *bt_mesh_model_find_vnd(struct bt_mesh_elem *elem, { int i; + BT_DBG("ModelFindVnd, ID 0x%04x CID 0x%04x", id, company); + for (i = 0; i < elem->vnd_model_count; i++) { if (elem->vnd_models[i].vnd.company == company && elem->vnd_models[i].vnd.id == id) { @@ -1149,6 +1250,8 @@ struct bt_mesh_model *bt_mesh_model_find(struct bt_mesh_elem *elem, uint16_t id) { int i; + BT_DBG("ModelFind, ID 0x%04x", id); + for (i = 0; i < elem->model_count; i++) { if (elem->models[i].id == id) { return &elem->models[i]; @@ -1160,6 +1263,8 @@ struct bt_mesh_model *bt_mesh_model_find(struct bt_mesh_elem *elem, uint16_t id) const struct bt_mesh_comp *bt_mesh_comp_get(void) { + BT_DBG("CompGet %p", comp_0); + return comp_0; } @@ -1177,6 +1282,8 @@ const uint8_t *bt_mesh_dev_key_get(uint16_t dst) key = bt_mesh_provisioner_dev_key_get(dst); } + BT_DBG("Dst 0x%04x DevKey %s", dst, key ? bt_hex(key, 16) : ""); + return key; } @@ -1188,20 +1295,22 @@ size_t bt_mesh_rx_netkey_size(void) if (bt_mesh_is_provisioned()) { size = ARRAY_SIZE(bt_mesh.sub); } -#endif +#endif /* CONFIG_BLE_MESH_NODE && !CONFIG_BLE_MESH_PROVISIONER */ #if !CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER if (bt_mesh_is_provisioner_en()) { size = ARRAY_SIZE(bt_mesh.p_sub); } -#endif +#endif /* !CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER */ #if CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER size = ARRAY_SIZE(bt_mesh.sub); if (bt_mesh_is_provisioner_en()) { size += ARRAY_SIZE(bt_mesh.p_sub); } -#endif +#endif /* CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER */ + + BT_DBG("RxNetKeySize %u", size); return size; } @@ -1214,13 +1323,13 @@ struct bt_mesh_subnet *bt_mesh_rx_netkey_get(size_t index) if (bt_mesh_is_provisioned()) { sub = &bt_mesh.sub[index]; } -#endif +#endif /* CONFIG_BLE_MESH_NODE && !CONFIG_BLE_MESH_PROVISIONER */ #if !CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER if (bt_mesh_is_provisioner_en()) { sub = bt_mesh.p_sub[index]; } -#endif +#endif /* !CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER */ #if CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER if (index < ARRAY_SIZE(bt_mesh.sub)) { @@ -1228,7 +1337,10 @@ struct bt_mesh_subnet *bt_mesh_rx_netkey_get(size_t index) } else { sub = bt_mesh.p_sub[index - ARRAY_SIZE(bt_mesh.sub)]; } -#endif +#endif /* CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER */ + + BT_DBG("RxNetKeyGet, Index %u NetIdx 0x%04x", + index, sub ? sub->net_idx : BLE_MESH_KEY_ANY); return sub; } @@ -1252,7 +1364,7 @@ size_t bt_mesh_rx_devkey_size(void) if (bt_mesh_is_provisioner_en()) { size = 1; } -#endif +#endif /* !CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER */ #if CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER size = 1; @@ -1264,7 +1376,9 @@ size_t bt_mesh_rx_devkey_size(void) if (bt_mesh_is_provisioner_en()) { size += 1; } -#endif +#endif /* CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER */ + + BT_DBG("RxDevKeySize %u", size); return size; } @@ -1281,13 +1395,13 @@ const uint8_t *bt_mesh_rx_devkey_get(size_t index, uint16_t src) key = bt_mesh.dev_key_ca; } } -#endif +#endif /* CONFIG_BLE_MESH_NODE && !CONFIG_BLE_MESH_PROVISIONER */ #if !CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER if (bt_mesh_is_provisioner_en()) { key = bt_mesh_provisioner_dev_key_get(src); } -#endif +#endif /* !CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER */ #if CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER if (index == 0) { @@ -1305,11 +1419,13 @@ const uint8_t *bt_mesh_rx_devkey_get(size_t index, uint16_t src) */ key = bt_mesh.dev_key_ca; } else -#endif +#endif /* CONFIG_BLE_MESH_RPR_SRV */ { key = bt_mesh_provisioner_dev_key_get(src); } -#endif +#endif /* CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER */ + + BT_DBG("RxDevKeyGet, Index %u Src 0x%04x", index, src); return key; } @@ -1322,20 +1438,22 @@ size_t bt_mesh_rx_appkey_size(void) if (bt_mesh_is_provisioned()) { size = ARRAY_SIZE(bt_mesh.app_keys); } -#endif +#endif /* CONFIG_BLE_MESH_NODE && !CONFIG_BLE_MESH_PROVISIONER */ #if !CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER if (bt_mesh_is_provisioner_en()) { size = ARRAY_SIZE(bt_mesh.p_app_keys); } -#endif +#endif /* !CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER */ #if CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER size = ARRAY_SIZE(bt_mesh.app_keys); if (bt_mesh_is_provisioner_en()) { size += ARRAY_SIZE(bt_mesh.p_app_keys); } -#endif +#endif /* CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER */ + + BT_DBG("RxAppKeySize %u", size); return size; } @@ -1348,13 +1466,13 @@ struct bt_mesh_app_key *bt_mesh_rx_appkey_get(size_t index) if (bt_mesh_is_provisioned()) { key = &bt_mesh.app_keys[index]; } -#endif +#endif /* CONFIG_BLE_MESH_NODE && !CONFIG_BLE_MESH_PROVISIONER */ #if !CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER if (bt_mesh_is_provisioner_en()) { key = bt_mesh.p_app_keys[index]; } -#endif +#endif /* !CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER */ #if CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER if (index < ARRAY_SIZE(bt_mesh.app_keys)) { @@ -1362,7 +1480,87 @@ struct bt_mesh_app_key *bt_mesh_rx_appkey_get(size_t index) } else { key = bt_mesh.p_app_keys[index - ARRAY_SIZE(bt_mesh.app_keys)]; } -#endif +#endif /* CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER */ + + BT_DBG("RxAppKeyGet, Index %u AppIdx 0x%04x", + index, key ? key->app_idx : BLE_MESH_KEY_ANY); return key; } + +struct bt_mesh_app_key *bt_mesh_app_key_get(uint16_t app_idx) +{ + BT_DBG("AppKeyGet, AppIdx 0x%04x", app_idx); + + if (bt_mesh_is_provisioned()) { +#if CONFIG_BLE_MESH_NODE + if (!IS_ENABLED(CONFIG_BLE_MESH_FAST_PROV)) { + for (int i = 0; i < ARRAY_SIZE(bt_mesh.app_keys); i++) { + if (bt_mesh.app_keys[i].net_idx != BLE_MESH_KEY_UNUSED && + bt_mesh.app_keys[i].app_idx == app_idx) { + BT_DBG("NodeAppKey"); + return &bt_mesh.app_keys[i]; + } + } + } else { + BT_DBG("FastProvAppKey"); + return bt_mesh_fast_prov_app_key_find(app_idx); + } +#endif /* CONFIG_BLE_MESH_NODE */ + } else if (bt_mesh_is_provisioner_en()) { +#if CONFIG_BLE_MESH_PROVISIONER + for (int i = 0; i < ARRAY_SIZE(bt_mesh.p_app_keys); i++) { + if (bt_mesh.p_app_keys[i] && + bt_mesh.p_app_keys[i]->net_idx != BLE_MESH_KEY_UNUSED && + bt_mesh.p_app_keys[i]->app_idx == app_idx) { + BT_DBG("PvnrAppKey"); + return bt_mesh.p_app_keys[i]; + } + } +#endif /* CONFIG_BLE_MESH_PROVISIONER */ + } + + return NULL; +} + +int bt_mesh_upper_key_get(const struct bt_mesh_subnet *subnet, uint16_t app_idx, + const uint8_t **key, uint8_t *aid, uint16_t dst) +{ + struct bt_mesh_app_key *app_key = NULL; + + BT_DBG("UpperKeyGet, AppIdx 0x%04x Dst 0x%04x", app_idx, dst); + + if (app_idx == BLE_MESH_KEY_DEV) { + *key = bt_mesh_dev_key_get(dst); + if (!*key) { + BT_ERR("DevKeyNotFound 0x%04x", dst); + return -EINVAL; + } + + *aid = 0U; + return 0; + } + + if (!subnet) { + BT_ERR("InvalidSubnet"); + return -EINVAL; + } + + app_key = bt_mesh_app_key_get(app_idx); + if (!app_key) { + BT_ERR("AppKeyNotFound 0x%04x", app_idx); + return -ENOENT; + } + + if (subnet->kr_phase == BLE_MESH_KR_PHASE_2 && app_key->updated) { + BT_DBG("NewAppKey"); + *key = app_key->keys[1].val; + *aid = app_key->keys[1].id; + } else { + BT_DBG("OldAppKey"); + *key = app_key->keys[0].val; + *aid = app_key->keys[0].id; + } + + return 0; +} diff --git a/components/bt/esp_ble_mesh/core/adv.c b/components/bt/esp_ble_mesh/core/adv.c index 22323ca3404e..5f58c2058b33 100644 --- a/components/bt/esp_ble_mesh/core/adv.c +++ b/components/bt/esp_ble_mesh/core/adv.c @@ -166,8 +166,8 @@ static inline int adv_send(struct net_buf *buf) struct bt_mesh_adv_data ad = {0}; int err = 0; - BT_DBG("type %u len %u: %s", BLE_MESH_ADV(buf)->type, - buf->len, bt_hex(buf->data, buf->len)); + BT_DBG("LegacyAdvSend, Type %u", BLE_MESH_ADV(buf)->type); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); #if CONFIG_BLE_MESH_SUPPORT_BLE_ADV if (BLE_MESH_ADV(buf)->type != BLE_MESH_ADV_BLE) { @@ -192,13 +192,14 @@ static inline int adv_send(struct net_buf *buf) #if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX if (BLE_MESH_ADV(buf)->type == BLE_MESH_ADV_PROXY_SOLIC) { bt_mesh_adv_buf_ref_debug(__func__, buf, 3U, BLE_MESH_BUF_REF_SMALL); + struct bt_mesh_adv_data solic_ad[2] = { BLE_MESH_ADV_DATA_BYTES(BLE_MESH_DATA_UUID16_ALL, 0x59, 0x18), BLE_MESH_ADV_DATA(BLE_MESH_DATA_SVC_DATA16, buf->data, buf->len), }; err = bt_le_adv_start(¶m, solic_ad, ARRAY_SIZE(solic_ad), NULL, 0); } else -#endif +#endif /* CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX */ { bt_mesh_adv_buf_ref_debug(__func__, buf, 4U, BLE_MESH_BUF_REF_SMALL); err = bt_le_adv_start(¶m, &ad, 1, NULL, 0); @@ -215,8 +216,8 @@ static inline int adv_send(struct net_buf *buf) } BT_DBG("interval %dms, duration %dms, period %dms, count %d", - ADV_SCAN_INT(tx->param.interval), tx->param.duration, - tx->param.period, tx->param.count); + ADV_SCAN_INT(tx->param.interval), tx->param.duration, + tx->param.period, tx->param.count); data.adv_data_len = tx->buf->data[0]; if (data.adv_data_len) { @@ -235,6 +236,7 @@ static inline int adv_send(struct net_buf *buf) #endif /* CONFIG_BLE_MESH_SUPPORT_BLE_ADV */ net_buf_unref(buf); + adv_send_start(duration, err, cb, cb_data); if (err) { BT_ERR("Start advertising failed: err %d", err); @@ -264,24 +266,33 @@ static inline TickType_t K_WAIT(int32_t val) static void adv_thread(void *p) { #if CONFIG_BLE_MESH_RELAY_ADV_BUF + QueueHandle_t relay_adv_handle = NULL; QueueSetMemberHandle_t handle = NULL; -#endif - bt_mesh_msg_t msg = {0}; +#endif /* CONFIG_BLE_MESH_RELAY_ADV_BUF */ struct net_buf **buf = NULL; + bt_mesh_msg_t msg = {0}; + +#if CONFIG_BLE_MESH_RELAY_ADV_BUF + relay_adv_handle = relay_adv_handle_get(); + assert(relay_adv_handle); +#endif /* CONFIG_BLE_MESH_RELAY_ADV_BUF */ buf = (struct net_buf **)(&msg.arg); - BT_DBG("%s, starts", __func__); + BT_DBG("LegacyAdvThread"); while (1) { *buf = NULL; + #if !CONFIG_BLE_MESH_RELAY_ADV_BUF #if (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || \ CONFIG_BLE_MESH_GATT_PROXY_SERVER xQueueReceive(adv_queue.handle, &msg, K_NO_WAIT); while (!(*buf)) { int32_t timeout = 0; + BT_DBG("Mesh Proxy Advertising start"); + timeout = bt_mesh_proxy_server_adv_start(); BT_DBG("Mesh Proxy Advertising up to %d ms", timeout); xQueueReceive(adv_queue.handle, &msg, K_WAIT(timeout)); @@ -304,12 +315,17 @@ static void adv_thread(void *p) } else { while (!(*buf)) { int32_t timeout = 0; + BT_DBG("Mesh Proxy Advertising start"); + timeout = bt_mesh_proxy_server_adv_start(); BT_DBG("Mesh Proxy Advertising up to %d ms", timeout); + handle = xQueueSelectFromSet(mesh_queue_set, K_WAIT(timeout)); + BT_DBG("Mesh Proxy Advertising stop"); bt_mesh_proxy_server_adv_stop(); + if (handle) { if (uxQueueMessagesWaiting(adv_queue.handle)) { xQueueReceive(adv_queue.handle, &msg, K_NO_WAIT); @@ -319,7 +335,7 @@ static void adv_thread(void *p) } } } -#else +#else /* (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || CONFIG_BLE_MESH_GATT_PROXY_SERVER */ handle = xQueueSelectFromSet(mesh_queue_set, portMAX_DELAY); if (handle) { if (uxQueueMessagesWaiting(adv_queue.handle)) { @@ -347,6 +363,7 @@ static void adv_thread(void *p) * BLE_MESH_RELAY_TIME_INTERVAL, this relay packet will not be sent. */ BT_INFO("Ignore relay packet"); + net_buf_unref(*buf); } else { if (adv_send(*buf)) { @@ -359,6 +376,8 @@ static void adv_thread(void *p) net_buf_unref(*buf); } + BT_DBG("Yield"); + /* Give other threads a chance to run */ taskYIELD(); } @@ -509,6 +528,8 @@ void bt_mesh_adv_update(void) .arg = NULL, }; + BT_DBG("LegacyAdvUpdate"); + bt_mesh_task_post(&msg, K_NO_WAIT, false); } diff --git a/components/bt/esp_ble_mesh/core/adv.h b/components/bt/esp_ble_mesh/core/adv.h index 369d3cef3d0e..e249eed1b179 100644 --- a/components/bt/esp_ble_mesh/core/adv.h +++ b/components/bt/esp_ble_mesh/core/adv.h @@ -94,6 +94,7 @@ uint16_t bt_mesh_get_stored_relay_count(void); void bt_mesh_adv_update(void); void bt_mesh_adv_init(void); + void bt_mesh_adv_deinit(void); #if CONFIG_BLE_MESH_SUPPORT_BLE_ADV diff --git a/components/bt/esp_ble_mesh/core/adv_common.c b/components/bt/esp_ble_mesh/core/adv_common.c new file mode 100644 index 000000000000..ff4e50ac1c8d --- /dev/null +++ b/components/bt/esp_ble_mesh/core/adv_common.c @@ -0,0 +1,951 @@ +/* Bluetooth Mesh */ + +/* + * SPDX-FileCopyrightText: 2017 Intel Corporation + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include "adv_common.h" +#include "net.h" +#include "ble_adv.h" + +NET_BUF_POOL_DEFINE(adv_buf_pool, CONFIG_BLE_MESH_ADV_BUF_COUNT, + BLE_MESH_ADV_DATA_SIZE, BLE_MESH_ADV_USER_DATA_SIZE, NULL); + +static struct bt_mesh_adv adv_pool[CONFIG_BLE_MESH_ADV_BUF_COUNT]; + +static struct bt_mesh_adv_queue adv_queue; + +#if CONFIG_BLE_MESH_RELAY_ADV_BUF +NET_BUF_POOL_DEFINE(relay_adv_buf_pool, CONFIG_BLE_MESH_RELAY_ADV_BUF_COUNT, + BLE_MESH_ADV_DATA_SIZE, BLE_MESH_ADV_USER_DATA_SIZE, NULL); + +static struct bt_mesh_adv relay_adv_pool[CONFIG_BLE_MESH_RELAY_ADV_BUF_COUNT]; +struct bt_mesh_adv_queue relay_adv_queue; + +#define BLE_MESH_RELAY_TIME_INTERVAL K_SECONDS(6) +#define BLE_MESH_MAX_TIME_INTERVAL 0xFFFFFFFF +#endif /* CONFIG_BLE_MESH_RELAY_ADV_BUF */ + +static bt_mesh_mutex_t adv_buf_alloc_lock; +#if CONFIG_BLE_MESH_EXT_ADV +NET_BUF_POOL_DEFINE(ext_adv_buf_pool, CONFIG_BLE_MESH_EXT_ADV_BUF_COUNT, + BLE_MESH_ADV_DATA_SIZE, BLE_MESH_ADV_USER_DATA_SIZE, NULL); +static bt_mesh_ext_adv_t ext_adv_pool[CONFIG_BLE_MESH_EXT_ADV_BUF_COUNT]; +#if CONFIG_BLE_MESH_EXT_RELAY_ADV_BUF_COUNT +NET_BUF_POOL_DEFINE(ext_relay_adv_buf_pool, CONFIG_BLE_MESH_EXT_RELAY_ADV_BUF_COUNT, + BLE_MESH_ADV_DATA_SIZE, BLE_MESH_ADV_USER_DATA_SIZE, NULL); +static bt_mesh_ext_adv_t ext_relay_adv_pool[CONFIG_BLE_MESH_EXT_RELAY_ADV_BUF_COUNT]; +#endif /* CONFIG_BLE_MESH_EXT_RELAY_ADV_BUF_COUNT */ +#if CONFIG_BLE_MESH_LONG_PACKET +NET_BUF_POOL_DEFINE(ext_long_adv_buf_pool, CONFIG_BLE_MESH_LONG_PACKET_TX_SEG_CNT, + CONFIG_BLE_MESH_LONG_PACKET_ADV_LEN, BLE_MESH_ADV_USER_DATA_SIZE, NULL); +static bt_mesh_ext_adv_t ext_long_adv_pool[CONFIG_BLE_MESH_LONG_PACKET_TX_SEG_CNT]; +#if CONFIG_BLE_MESH_LONG_PACKET_RELAY_ADV_BUF_COUNT +NET_BUF_POOL_DEFINE(ext_long_relay_adv_buf_pool, CONFIG_BLE_MESH_LONG_PACKET_RELAY_ADV_BUF_COUNT, + CONFIG_BLE_MESH_LONG_PACKET_ADV_LEN, BLE_MESH_ADV_USER_DATA_SIZE, NULL); +static bt_mesh_ext_adv_t ext_long_relay_adv_pool[CONFIG_BLE_MESH_LONG_PACKET_RELAY_ADV_BUF_COUNT]; +#endif /* CONFIG_BLE_MESH_LONG_PACKET_RELAY_ADV_BUF_COUNT */ +#endif /* CONFIG_BLE_MESH_LONG_PACKET */ +#endif /* CONFIG_BLE_MESH_EXT_ADV */ + +static inline void init_adv_with_defaults(struct bt_mesh_adv *adv, + enum bt_mesh_adv_type type) +{ + memset(adv, 0, sizeof(struct bt_mesh_adv)); + adv->type = type; + adv->adv_itvl = BLE_MESH_ADV_ITVL_DEFAULT; + adv->adv_cnt = BLE_MESH_ADV_CNT_DEFAULT; + adv->channel_map = BLE_MESH_ADV_CHAN_DEFAULT; +} + +#if CONFIG_BLE_MESH_FRIEND +/* We reserve one extra buffer for each friendship, since we need to be able + * to resend the last sent PDU, which sits separately outside of the queue. + */ +#define FRIEND_BUF_COUNT ((CONFIG_BLE_MESH_FRIEND_QUEUE_SIZE + 1) * \ + CONFIG_BLE_MESH_FRIEND_LPN_COUNT) + +NET_BUF_POOL_FIXED_DEFINE(friend_buf_pool, FRIEND_BUF_COUNT, + BLE_MESH_ADV_DATA_SIZE, NULL); + +static bt_mesh_friend_adv_t frnd_adv_pool[FRIEND_BUF_COUNT]; +#endif /* CONFIG_BLE_MESH_FRIEND */ + +struct bt_mesh_adv_task { + TaskHandle_t handle; +#if (CONFIG_BLE_MESH_FREERTOS_STATIC_ALLOC_EXTERNAL && \ + (CONFIG_SPIRAM_CACHE_WORKAROUND || !CONFIG_IDF_TARGET_ESP32) && \ + CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY) + StaticTask_t *task; + StackType_t *stack; +#endif +}; + +static struct bt_mesh_adv_task adv_task; + +static struct bt_mesh_adv_type_manager adv_types[BLE_MESH_ADV_TYPES_NUM]; + +#if CONFIG_BLE_MESH_USE_BLE_50 +static struct bt_mesh_adv_inst adv_insts[] = { + [BLE_MESH_ADV_INST] = { + .id = CONFIG_BLE_MESH_ADV_INST_ID, +#if CONFIG_BLE_MESH_SUPPORT_MULTI_ADV + .busy = false, +#endif /* CONFIG_BLE_MESH_SUPPORT_MULTI_ADV */ + }, +#if CONFIG_BLE_MESH_SUPPORT_MULTI_ADV +#if (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || \ + CONFIG_BLE_MESH_GATT_PROXY_SERVER + [BLE_MESH_ADV_PROXY_INST] = { + .id = CONFIG_BLE_MESH_PROXY_ADV_INST_ID, + .busy = false, + }, +#endif +#if CONFIG_BLE_MESH_SEPARATE_RELAY_ADV_INSTANCE + [BLE_MESH_RELAY_ADV_INST] = { + .id = CONFIG_BLE_MESH_RELAY_ADV_INST_ID, + .busy = false, + }, +#endif /* CONFIG_BLE_MESH_SEPARATE_RELAY_ADV_INSTANCE */ +#if CONFIG_BLE_MESH_SEPARATE_BLE_ADV_INSTANCE + [BLE_MESH_BLE_ADV_INST] = { + .id = CONFIG_BLE_MESH_BLE_ADV_INST_ID, + .busy = false, + }, +#endif /* CONFIG_BLE_MESH_SEPARATE_BLE_ADV_INSTANCE */ +#endif /* CONFIG_BLE_MESH_SUPPORT_MULTI_ADV */ +}; + +static struct bt_mesh_adv_inst *find_adv_inst_with_inst_id(uint8_t id) +{ + BT_DBG("FindAdvInstWithID, InstID %u", id); + + for (int i = 0; i < ARRAY_SIZE(adv_insts); i++) { + if (adv_insts[i].id == id) { + return &adv_insts[i]; + } + } + + BT_WARN("NotFoundAdvInst, InstID %u", id); + return NULL; +} + +struct bt_mesh_adv_inst *bt_mesh_get_adv_insts_set(void) +{ + return adv_insts; +} + +bool bt_mesh_is_adv_inst_used(uint8_t inst_id) +{ + BT_DBG("IsAdvInstUsed, InstID %u", inst_id); + + return (find_adv_inst_with_inst_id(inst_id) != NULL); +} + +int bt_mesh_adv_inst_init(enum bt_mesh_adv_inst_type inst_type, uint8_t inst_id) +{ + BT_DBG("AdvInstInit, InstType %u InstID %u", inst_type, inst_id); + + if (inst_type >= BLE_MESH_ADV_INST_TYPES_NUM) { + BT_ERR("InvalidAdvInstType %u", inst_type); + return -EINVAL; + } + + if (inst_id == BLE_MESH_ADV_INST_UNUSED) { + BT_ERR("UnusedAdvInstID"); + return -EINVAL; + } + + adv_insts[inst_type].id = inst_id; + + return 0; +} + +int bt_mesh_adv_inst_deinit(enum bt_mesh_adv_inst_type inst_type) +{ + BT_DBG("AdvInstDeinit, InstType %u", inst_type); + + if (inst_type >= BLE_MESH_ADV_INST_TYPES_NUM) { + BT_ERR("Invalid adv inst type %d", inst_type); + return -EINVAL; + } + + BT_DBG("InstID %u", adv_insts[inst_type].id); + + bt_le_ext_adv_stop(adv_insts[inst_type].id); + + adv_insts[inst_type].id = BLE_MESH_ADV_INST_UNUSED; +#if CONFIG_BLE_MESH_SUPPORT_MULTI_ADV + adv_insts[inst_type].spt_mask = 0; +#endif /* CONFIG_BLE_MESH_SUPPORT_MULTI_ADV */ + + return 0; +} +#endif /* CONFIG_BLE_MESH_USE_BLE_50 */ + +static struct bt_mesh_adv *adv_alloc(int id, enum bt_mesh_adv_type type) +{ + BT_DBG("AdvAlloc, ID %d", id); + init_adv_with_defaults(&adv_pool[id], type); + return &adv_pool[id]; +} + +#if CONFIG_BLE_MESH_EXT_ADV +struct bt_mesh_adv *ext_adv_alloc(int id, enum bt_mesh_adv_type type) +{ + init_adv_with_defaults(&ext_adv_pool[id].adv, type); + ext_adv_pool[id].primary_phy = BLE_MESH_ADV_PRI_PHY_DEFAULT; + ext_adv_pool[id].secondary_phy = BLE_MESH_ADV_SEC_PHY_DEFAULT; + ext_adv_pool[id].include_tx_power = BLE_MESH_TX_POWER_INCLUDE_DEFAULT; + ext_adv_pool[id].tx_power = BLE_MESH_TX_POWER_DEFAULT; + return &ext_adv_pool[id].adv; +} +#if CONFIG_BLE_MESH_EXT_RELAY_ADV_BUF_COUNT +struct bt_mesh_adv *ext_relay_adv_alloc(int id, enum bt_mesh_adv_type type) +{ + init_adv_with_defaults(&ext_relay_adv_pool[id].adv, type); + ext_relay_adv_pool[id].primary_phy = BLE_MESH_ADV_PRI_PHY_DEFAULT; + ext_relay_adv_pool[id].secondary_phy = BLE_MESH_ADV_SEC_PHY_DEFAULT; + ext_relay_adv_pool[id].include_tx_power = BLE_MESH_TX_POWER_INCLUDE_DEFAULT; + ext_relay_adv_pool[id].tx_power = BLE_MESH_TX_POWER_DEFAULT; + return &ext_relay_adv_pool[id].adv; +} +#endif /* CONFIG_BLE_MESH_EXT_RELAY_ADV_BUF_COUNT */ +#endif /* CONFIG_BLE_MESH_EXT_ADV */ + +#if CONFIG_BLE_MESH_LONG_PACKET +struct bt_mesh_adv *ext_long_adv_alloc(int id, enum bt_mesh_adv_type type) +{ + init_adv_with_defaults(&ext_long_adv_pool[id].adv, type); + ext_long_adv_pool[id].primary_phy = BLE_MESH_ADV_PRI_PHY_DEFAULT; + ext_long_adv_pool[id].secondary_phy = BLE_MESH_ADV_SEC_PHY_DEFAULT; + ext_long_adv_pool[id].include_tx_power = BLE_MESH_TX_POWER_INCLUDE_DEFAULT; + ext_long_adv_pool[id].tx_power = BLE_MESH_TX_POWER_DEFAULT; + return &ext_long_adv_pool[id].adv; +} +#if CONFIG_BLE_MESH_LONG_PACKET_RELAY_ADV_BUF_COUNT +struct bt_mesh_adv *ext_long_relay_adv_alloc(int id, enum bt_mesh_adv_type type) +{ + init_adv_with_defaults(&ext_long_relay_adv_pool[id].adv, type); + ext_long_relay_adv_pool[id].primary_phy = BLE_MESH_ADV_PRI_PHY_DEFAULT; + ext_long_relay_adv_pool[id].secondary_phy = BLE_MESH_ADV_SEC_PHY_DEFAULT; + ext_long_relay_adv_pool[id].include_tx_power = BLE_MESH_TX_POWER_INCLUDE_DEFAULT; + ext_long_relay_adv_pool[id].tx_power = BLE_MESH_TX_POWER_DEFAULT; + return &ext_long_relay_adv_pool[id].adv; +} +#endif /* CONFIG_BLE_MESH_LONG_PACKET_RELAY_ADV_BUF_COUNT */ +#endif /* CONFIG_BLE_MESH_LONG_PACKET */ + +struct bt_mesh_adv_type_manager *bt_mesh_adv_types_mgmt_get(enum bt_mesh_adv_type adv_type) +{ + BT_DBG("AdvTypeMgmtGet, AdvType %u", adv_type); + + return &adv_types[adv_type]; +} + +void bt_mesh_adv_buf_ref_debug(const char *func, struct net_buf *buf, + uint8_t ref_cmp, bt_mesh_buf_ref_flag_t flag) +{ + if (buf == NULL || func == NULL || flag >= BLE_MESH_BUF_REF_MAX) { + BT_ERR("%s, Invalid parameter", __func__); + return; + } + + BT_DBG("AdvBufRefDebug, BufRef %u RefCmp %u", buf->ref, ref_cmp); + + switch (flag) { + case BLE_MESH_BUF_REF_EQUAL: + if (buf->ref != ref_cmp) { + BT_ERR("Unexpected ref %d in %s, expect to equal to %d", buf->ref, func, ref_cmp); + } + break; + case BLE_MESH_BUF_REF_SMALL: + if (buf->ref >= ref_cmp) { + BT_ERR("Unexpected ref %d in %s, expect to smaller than %d", buf->ref, func, ref_cmp); + } + break; + default: + break; + } +} + +#if CONFIG_BLE_MESH_SUPPORT_MULTI_ADV +void bt_mesh_adv_inst_type_add(enum bt_mesh_adv_inst_type inst_type, + enum bt_mesh_adv_type adv_type) +{ + BT_DBG("AdvInstTypeAdd, InstType %u AdvType %u", inst_type, adv_type); + + if (inst_type >= BLE_MESH_ADV_INST_TYPES_NUM) { + BT_ERR("Invalid adv inst type %d", inst_type); + return; + } + + if (adv_type >= BLE_MESH_ADV_TYPES_NUM) { + BT_ERR("Invalid adv type %d", adv_type); + return; + } + + adv_insts[inst_type].spt_mask |= BIT(adv_type); +} + +void bt_mesh_adv_inst_type_rem(enum bt_mesh_adv_inst_type inst_type, + enum bt_mesh_adv_type adv_type) +{ + BT_DBG("AdvInstTypeRem, InstType %u AdvType %u", inst_type, adv_type); + + if (inst_type >= BLE_MESH_ADV_INST_TYPES_NUM) { + BT_ERR("Invalid adv inst type %d", inst_type); + return; + } + + if (adv_type >= BLE_MESH_ADV_TYPES_NUM) { + BT_ERR("Invalid adv type %d", adv_type); + return; + } + + adv_insts[inst_type].spt_mask &= ~BIT(adv_type); +} + +void bt_mesh_adv_inst_type_clear(enum bt_mesh_adv_inst_type inst_type, + enum bt_mesh_adv_type adv_type) +{ + BT_DBG("AdvInstTypeClear, InstType %u AdvType %u", inst_type, adv_type); + + if (inst_type >= BLE_MESH_ADV_INST_TYPES_NUM) { + BT_ERR("Invalid adv inst type %d", inst_type); + return; + } + + if (adv_type >= BLE_MESH_ADV_TYPES_NUM) { + BT_ERR("Invalid adv type %d", adv_type); + return; + } + + adv_insts[inst_type].spt_mask = 0; +} +#endif /* CONFIG_BLE_MESH_SUPPORT_MULTI_ADV */ + +int bt_mesh_adv_queue_init(struct bt_mesh_adv_queue *adv_queue, uint16_t queue_size, + bt_mesh_adv_queue_send_cb_t cb) +{ + BT_DBG("AdvQueueInit, QueueSize %u", queue_size); + + if (!adv_queue || !queue_size || !cb) { + BT_ERR("%s, Invalid parameter", __func__); + return -EINVAL; + } + + bt_mesh_queue_init(&adv_queue->q, queue_size, sizeof(bt_mesh_msg_t)); + adv_queue->send = cb; + + return 0; +} + +int bt_mesh_adv_queue_deinit(struct bt_mesh_adv_queue *adv_queue) +{ + BT_DBG("AdvQueueDeinit"); + + if (!adv_queue) { + BT_ERR("%s, Invalid parameter", __func__); + return -EINVAL; + } + + bt_mesh_queue_deinit(&adv_queue->q); + adv_queue->send = NULL; + + return 0; +} + +void bt_mesh_adv_type_init(enum bt_mesh_adv_type adv_type, + struct bt_mesh_adv_queue *adv_queue, + struct net_buf_pool *buf_pool, + bt_mesh_pool_allocator_t adv_alloc) +{ + BT_DBG("AdvTypeInit, AdvType %u", adv_type); + + if (adv_type >= BLE_MESH_ADV_TYPES_NUM) { + BT_ERR("%s, Invalid adv type %d", __func__, adv_type); + return; + } + + if (!adv_queue || !buf_pool || !adv_alloc) { + BT_ERR("%s, Invalid parameter", __func__); + return; + } + + adv_types[adv_type].adv_q = adv_queue; + adv_types[adv_type].pool = buf_pool; + adv_types[adv_type].pool_allocator = adv_alloc; +} + +void bt_mesh_adv_type_deinit(enum bt_mesh_adv_type adv_type) +{ + BT_DBG("AdvTypeDeinit, AdvType %u", adv_type); + + if (adv_type >= BLE_MESH_ADV_TYPES_NUM) { + BT_ERR("%s, Invalid adv type %d", __func__, adv_type); + return; + } + + adv_types[adv_type].adv_q = NULL; + adv_types[adv_type].pool = NULL; + adv_types[adv_type].pool_allocator = NULL; +} + +#if CONFIG_BLE_MESH_USE_BLE_50 +int bt_mesh_adv_task_wakeup(uint32_t evt) +{ + BT_DBG("AdvTypeWakeup, Evt 0x%08lx", evt); + + xTaskNotify(adv_task.handle, evt, eSetBits); + return 0; +} + +bool bt_mesh_adv_task_wait(uint32_t wait_bits, uint32_t timeout, uint32_t *notify) +{ + BT_DBG("AdvTypeWait, WaitBits 0x%08lx Timeout %lu", wait_bits, timeout); + + return (xTaskNotifyWait(wait_bits, UINT32_MAX, notify, K_WAIT(timeout)) == pdTRUE); +} +#else /* CONFIG_BLE_MESH_USE_BLE_50 */ +bool bt_mesh_adv_task_wait(uint32_t timeout) +{ + BT_DBG("AdvTypeWait, Timeout %lu", timeout); + + vTaskDelay(K_WAIT(timeout)); + return true; +} +#endif /* CONFIG_BLE_MESH_USE_BLE_50 */ + +uint16_t bt_mesh_pdu_duration(uint8_t xmit) +{ + uint16_t duration = 0U; + uint16_t adv_int = 0U; + + adv_int = MAX(ADV_ITVL_MIN, BLE_MESH_TRANSMIT_INT(xmit)); + duration = (BLE_MESH_TRANSMIT_COUNT(xmit) + 1) * (adv_int + 10); + + BT_DBG("PDUDuration %u", duration); + + return duration; +} + +struct net_buf *bt_mesh_adv_create_from_pool(enum bt_mesh_adv_type type, int32_t timeout) +{ + struct bt_mesh_adv *adv = NULL; + struct net_buf *buf = NULL; + + BT_DBG("AdvCreateFromPool, Type %u", type); + + if (bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_SUSPENDED)) { + BT_WARN("Refusing to allocate buffer while suspended"); + return NULL; + } + + if (type >= BLE_MESH_ADV_TYPES_NUM) { + BT_ERR("%s, Invalid adv type %u", __func__, type); + return NULL; + } + + if (adv_types[type].pool == NULL || adv_types[type].pool_allocator == NULL) { + BT_ERR("Uninitialized adv type %d", type); + return NULL; + } + + bt_mesh_r_mutex_lock(&adv_buf_alloc_lock); + + buf = net_buf_alloc(adv_types[type].pool, timeout); + if (!buf) { + BT_WARN("net buf alloc failed"); + bt_mesh_r_mutex_unlock(&adv_buf_alloc_lock); + return NULL; + } + + BT_DBG("Pool %p BufCount %u UinitCount %u BufID %d Ref %u", + adv_types[type].pool, adv_types[type].pool->buf_count, + adv_types[type].pool->uninit_count, net_buf_id(buf), + buf->ref); + + adv = adv_types[type].pool_allocator(net_buf_id(buf), type); + BLE_MESH_ADV(buf) = adv; + bt_mesh_r_mutex_unlock(&adv_buf_alloc_lock); + + return buf; +} + +void bt_mesh_unref_buf_from_pool(struct net_buf_pool *pool) +{ + BT_DBG("UnrefBufFromPool"); + + if (pool == NULL) { + BT_ERR("%s, Invalid parameter", __func__); + return; + } + + for (int i = 0; i < pool->buf_count; i++) { + struct net_buf *buf = &pool->__bufs[i]; + + BT_DBG("%u: Buf %p Ref %u", i, buf, buf->ref); + + if (buf->ref > 1U) { + buf->ref = 1U; + } + net_buf_unref(buf); + } +} + +void bt_mesh_unref_buf(bt_mesh_msg_t *msg) +{ + struct net_buf *buf = msg->arg; + + BT_DBG("UnRefBuf %p", buf); + + if (buf) { + BT_DBG("Ref %u", buf->ref); + + bt_mesh_atomic_set(&BLE_MESH_ADV_BUSY(buf), 0); + + if (buf->ref > 1U) { + buf->ref = 1U; + } + net_buf_unref(buf); + } +} + +void bt_mesh_generic_adv_send(struct net_buf *buf, uint8_t xmit, + const struct bt_mesh_send_cb *cb, + void *cb_data, uint16_t src, + uint16_t dst, bool front) +{ + bt_mesh_msg_t msg = { + .relay = false, /* useless flag in multi-instance mode */ + }; + + BT_DBG("GenericAdvSend"); + BT_DBG("Src 0x%04x Dst 0x%04x Type 0x%02x", + src, dst, BLE_MESH_ADV(buf)->type); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); + + BLE_MESH_ADV(buf)->cb = cb; + BLE_MESH_ADV(buf)->cb_data = cb_data; + bt_mesh_atomic_set(&BLE_MESH_ADV_BUSY(buf), 1); + BLE_MESH_ADV(buf)->xmit = xmit; + + bt_mesh_adv_buf_ref_debug(__func__, buf, 3U, BLE_MESH_BUF_REF_SMALL); + + msg.arg = (void *)net_buf_ref(buf); + +#if CONFIG_BLE_MESH_RELAY_ADV_BUF + if (BLE_MESH_ADV(buf)->type == BLE_MESH_ADV_RELAY_DATA) { + msg.relay = true; + msg.src = src; + msg.dst = dst; + msg.timestamp = k_uptime_get_32(); + + BT_DBG("RelayAdvData, Timestamp %lu", msg.timestamp); + } +#endif /* CONFIG_BLE_MESH_RELAY_ADV_BUF */ + + assert(adv_types[BLE_MESH_ADV(buf)->type].adv_q); + assert(adv_types[BLE_MESH_ADV(buf)->type].adv_q->send); + + adv_types[BLE_MESH_ADV(buf)->type].adv_q->send(&msg, portMAX_DELAY, front); + +#if CONFIG_BLE_MESH_SUPPORT_MULTI_ADV + bt_mesh_adv_task_wakeup(ADV_TASK_PKT_SEND_EVT); +#endif /* CONFIG_BLE_MESH_SUPPORT_MULTI_ADV */ +} + +struct bt_mesh_adv_queue *bt_mesh_adv_queue_get(void) +{ + return &adv_queue; +} + +void bt_mesh_task_post(bt_mesh_msg_t *msg, uint32_t timeout, bool front) +{ + BT_DBG("TaskPost, Front %u", front); + + if (adv_queue.q.handle == NULL) { + BT_ERR("Invalid adv queue"); + return; + } + + if (front) { + if (xQueueSendToFront(adv_queue.q.handle, msg, timeout) != pdTRUE) { + BT_ERR("Failed to send item to adv queue front"); + bt_mesh_unref_buf(msg); + } + } else { + if (xQueueSend(adv_queue.q.handle, msg, timeout) != pdTRUE) { + BT_ERR("Failed to send item to adv queue back"); + bt_mesh_unref_buf(msg); + } + } +} + +#if CONFIG_BLE_MESH_RELAY_ADV_BUF +bool bt_mesh_ignore_relay_packet(uint32_t timestamp) +{ + uint32_t now = k_uptime_get_32(); + uint32_t interval = 0U; + + if (now >= timestamp) { + interval = now - timestamp; + } else { + interval = BLE_MESH_MAX_TIME_INTERVAL - (timestamp - now) + 1; + } + + BT_DBG("IgnoreRelayPacket"); + BT_DBG("Now %lu Timestamp %lu Interval %lu", now, timestamp, interval); + + return ((interval >= BLE_MESH_RELAY_TIME_INTERVAL) ? true : false); +} + +static struct bt_mesh_adv *relay_adv_alloc(int id, enum bt_mesh_adv_type type) +{ + BT_DBG("RelayAdvAlloc, ID %d", id); + memset(&relay_adv_pool[id], 0, sizeof(struct bt_mesh_adv)); + init_adv_with_defaults(&relay_adv_pool[id], type); + return &relay_adv_pool[id]; +} + +static void bt_mesh_relay_task_post(bt_mesh_msg_t *msg, uint32_t timeout, bool front) +{ + bt_mesh_msg_t old_msg = {0}; + + BT_DBG("RelayTaskPost, Front %u", front); + + if (relay_adv_queue.q.handle == NULL) { + BT_ERR("Invalid relay queue"); + return; + } + + if (xQueueSend(relay_adv_queue.q.handle, msg, timeout) == pdTRUE) { + return; + } + + /* If failed to send packet to the relay queue(queue is full), we will + * remove the oldest packet in the queue and put the new one into it. + */ + if (uxQueueMessagesWaiting(relay_adv_queue.q.handle)) { + BT_INFO("Full queue, remove the oldest relay packet"); + + /* Remove the oldest relay packet from queue */ + if (xQueueReceive(relay_adv_queue.q.handle, &old_msg, K_NO_WAIT) != pdTRUE) { + BT_ERR("Failed to remove item from relay queue"); + bt_mesh_unref_buf(msg); + return; + } + + /* Unref buf used for the oldest relay packet */ + bt_mesh_unref_buf(&old_msg); + + /* Send the latest relay packet to queue */ + if (xQueueSend(relay_adv_queue.q.handle, msg, K_NO_WAIT) != pdTRUE) { + BT_ERR("Failed to send item to relay queue"); + bt_mesh_unref_buf(msg); + return; + } + } else { + BT_WARN("Empty queue, but failed to send the relay packet"); + bt_mesh_unref_buf(msg); + } +} + +uint16_t bt_mesh_get_stored_relay_count(void) +{ + uint16_t count = (uint16_t)uxQueueMessagesWaiting(relay_adv_queue.q.handle); + + BT_DBG("StoredRelayCount %u", count); + + return count; +} + +void bt_mesh_relay_adv_init(void) +{ + BT_DBG("RelayAdvInit"); + bt_mesh_adv_queue_init(&relay_adv_queue, bt_mesh_relay_adv_buf_count_get(), + bt_mesh_relay_task_post); + bt_mesh_adv_type_init(BLE_MESH_ADV_RELAY_DATA, &relay_adv_queue, + &relay_adv_buf_pool, &relay_adv_alloc); +#if CONFIG_BLE_MESH_EXT_ADV + bt_mesh_adv_type_init(BLE_MESH_ADV_EXT_RELAY_DATA, &relay_adv_queue, + &ext_adv_buf_pool, &ext_relay_adv_alloc); +#if CONFIG_BLE_MESH_LONG_PACKET && CONFIG_BLE_MESH_LONG_PACKET_RELAY_ADV_BUF_COUNT + bt_mesh_adv_type_init(BLE_MESH_ADV_EXT_LONG_RELAY_DATA, &relay_adv_queue, + &ext_long_relay_adv_buf_pool, ext_long_relay_adv_alloc); +#endif /* CONFIG_BLE_MESH_LONG_PACKET && CONFIG_BLE_MESH_LONG_PACKET_RELAY_ADV_BUF_COUNT */ +#endif /* CONFIG_BLE_MESH_EXT_ADV */ + +#if CONFIG_BLE_MESH_USE_BLE_50 +#if CONFIG_BLE_MESH_SEPARATE_RELAY_ADV_INSTANCE + bt_mesh_adv_inst_init(BLE_MESH_RELAY_ADV_INST, + CONFIG_BLE_MESH_RELAY_ADV_INST_ID); + bt_mesh_adv_inst_type_add(BLE_MESH_RELAY_ADV_INST, BLE_MESH_ADV_RELAY_DATA); + +#if CONFIG_BLE_MESH_EXT_ADV + bt_mesh_adv_inst_type_add(BLE_MESH_RELAY_ADV_INST, BLE_MESH_ADV_EXT_RELAY_DATA); +#if CONFIG_BLE_MESH_LONG_PACKET + bt_mesh_adv_inst_type_add(BLE_MESH_RELAY_ADV_INST, BLE_MESH_ADV_EXT_LONG_RELAY_DATA); +#endif /* CONFIG_BLE_MESH_LONG_PACKET */ +#endif /* CONFIG_BLE_MESH_EXT_ADV */ +#else /* CONFIG_BLE_MESH_SEPARATE_RELAY_ADV_INSTANCE */ +#if CONFIG_BLE_MESH_SUPPORT_MULTI_ADV + bt_mesh_adv_inst_type_add(BLE_MESH_ADV_INST, BLE_MESH_ADV_RELAY_DATA); +#if CONFIG_BLE_MESH_EXT_ADV + bt_mesh_adv_inst_type_add(BLE_MESH_ADV_INST, BLE_MESH_ADV_EXT_RELAY_DATA); +#if CONFIG_BLE_MESH_LONG_PACKET + bt_mesh_adv_inst_type_add(BLE_MESH_ADV_INST, BLE_MESH_ADV_EXT_LONG_RELAY_DATA); +#endif /* CONFIG_BLE_MESH_LONG_PACKET */ +#endif /* CONFIG_BLE_MESH_EXT_ADV */ +#endif /* CONFIG_BLE_MESH_SUPPORT_MULTI_ADV */ +#endif /* CONFIG_BLE_MESH_SEPARATE_RELAY_ADV_INSTANCE */ +#endif /* CONFIG_BLE_MESH_USE_BLE_50 */ +} + +#if CONFIG_BLE_MESH_DEINIT +void bt_mesh_relay_adv_deinit(void) +{ + BT_DBG("RelayAdvDeinit"); + + bt_mesh_adv_queue_deinit(&relay_adv_queue); + + bt_mesh_adv_type_deinit(BLE_MESH_ADV_RELAY_DATA); +#if CONFIG_BLE_MESH_EXT_ADV + bt_mesh_adv_type_deinit(BLE_MESH_ADV_EXT_RELAY_DATA); +#if CONFIG_BLE_MESH_LONG_PACKET + bt_mesh_adv_type_deinit(BLE_MESH_ADV_EXT_LONG_RELAY_DATA); +#endif /* CONFIG_BLE_MESH_LONG_PACKET */ +#endif /* CONFIG_BLE_MESH_EXT_ADV */ + +#if CONFIG_BLE_MESH_USE_BLE_50 +#if CONFIG_BLE_MESH_SEPARATE_RELAY_ADV_INSTANCE + bt_mesh_adv_inst_type_rem(BLE_MESH_RELAY_ADV_INST, BLE_MESH_ADV_RELAY_DATA); +#if CONFIG_BLE_MESH_EXT_ADV + bt_mesh_adv_inst_type_rem(BLE_MESH_RELAY_ADV_INST, BLE_MESH_ADV_EXT_RELAY_DATA); +#if CONFIG_BLE_MESH_LONG_PACKET + bt_mesh_adv_inst_type_rem(BLE_MESH_RELAY_ADV_INST, BLE_MESH_ADV_EXT_LONG_RELAY_DATA); +#endif /* CONFIG_BLE_MESH_LONG_PACKET */ +#endif /* CONFIG_BLE_MESH_EXT_ADV */ + bt_mesh_adv_inst_deinit(BLE_MESH_RELAY_ADV_INST); +#else /* CONFIG_BLE_MESH_SEPARATE_RELAY_ADV_INSTANCE */ +#if CONFIG_BLE_MESH_SUPPORT_MULTI_ADV + bt_mesh_adv_inst_type_rem(BLE_MESH_ADV_INST, BLE_MESH_ADV_RELAY_DATA); +#if CONFIG_BLE_MESH_EXT_ADV + bt_mesh_adv_inst_type_rem(BLE_MESH_ADV_INST, BLE_MESH_ADV_EXT_RELAY_DATA); +#if CONFIG_BLE_MESH_LONG_PACKET + bt_mesh_adv_inst_type_rem(BLE_MESH_ADV_INST, BLE_MESH_ADV_EXT_LONG_RELAY_DATA); +#endif /* CONFIG_BLE_MESH_LONG_PACKET */ +#endif /* CONFIG_BLE_MESH_EXT_ADV */ +#endif /* CONFIG_BLE_MESH_SUPPORT_MULTI_ADV */ +#endif /* CONFIG_BLE_MESH_SEPARATE_RELAY_ADV_INSTANCE */ +#endif /* CONFIG_BLE_MESH_USE_BLE_50 */ + + bt_mesh_unref_buf_from_pool(&relay_adv_buf_pool); + memset(relay_adv_pool, 0, sizeof(relay_adv_pool)); +} +#endif /* CONFIG_BLE_MESH_DEINIT */ +#endif /* CONFIG_BLE_MESH_RELAY_ADV_BUF */ + +#if CONFIG_BLE_MESH_FRIEND +static struct bt_mesh_adv *bt_mesh_frnd_adv_buf_get(int idx, enum bt_mesh_adv_type type) +{ + BT_DBG("FrndAdvBufGet, Idx %d", idx); + + memset(&frnd_adv_pool[idx].adv, 0, sizeof(struct bt_mesh_adv)); + init_adv_with_defaults(&frnd_adv_pool[idx].adv, type); + frnd_adv_pool[idx].app_idx = BLE_MESH_KEY_UNUSED; + return &frnd_adv_pool[idx].adv; +} + +void bt_mesh_frnd_adv_init(void) +{ + BT_DBG("FrndAdvInit"); + + bt_mesh_adv_type_init(BLE_MESH_ADV_FRIEND, &adv_queue, &friend_buf_pool, bt_mesh_frnd_adv_buf_get); + +#if CONFIG_BLE_MESH_SUPPORT_MULTI_ADV + bt_mesh_adv_inst_type_add(BLE_MESH_ADV_INST, BLE_MESH_ADV_FRIEND); +#endif /* CONFIG_BLE_MESH_SUPPORT_MULTI_ADV */ +} + +void bt_mesh_frnd_adv_deinit(void) +{ + BT_DBG("FrndAdvDeinit"); + + bt_mesh_adv_type_deinit(BLE_MESH_ADV_FRIEND); + +#if CONFIG_BLE_MESH_FRIEND && CONFIG_BLE_MESH_SUPPORT_MULTI_ADV + bt_mesh_adv_inst_type_rem(BLE_MESH_ADV_INST, BLE_MESH_ADV_FRIEND); +#endif /* CONFIG_BLE_MESH_FRIEND */ + + bt_mesh_unref_buf_from_pool(&friend_buf_pool); + memset(frnd_adv_pool, 0, sizeof(frnd_adv_pool)); +} +#endif /* CONFIG_BLE_MESH_FRIEND */ + +void bt_mesh_adv_task_init(void adv_thread(void *p)) +{ + BT_DBG("AdvTaskInit"); + + if (!adv_thread) { + BT_ERR("%s, Invalid parameter", __func__); + return; + } + +#if (CONFIG_BLE_MESH_FREERTOS_STATIC_ALLOC_EXTERNAL && \ + (CONFIG_SPIRAM_CACHE_WORKAROUND || !CONFIG_IDF_TARGET_ESP32) && \ + CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY) + adv_task.task = heap_caps_calloc(1, sizeof(StaticTask_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT); + assert(adv_task.task); + + adv_task.stack = heap_caps_calloc_prefer(1, BLE_MESH_ADV_TASK_STACK_SIZE * sizeof(StackType_t), + 2, MALLOC_CAP_SPIRAM|MALLOC_CAP_8BIT, + MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT); + assert(adv_task.stack); + + adv_task.handle = xTaskCreateStaticPinnedToCore(adv_thread, BLE_MESH_ADV_TASK_NAME, + BLE_MESH_ADV_TASK_STACK_SIZE, NULL, + BLE_MESH_ADV_TASK_PRIO, adv_task.stack, + adv_task.task, BLE_MESH_ADV_TASK_CORE); + assert(adv_task.handle); +#else /* CONFIG_BLE_MESH_FREERTOS_STATIC_ALLOC_EXTERNAL && (CONFIG_SPIRAM_CACHE_WORKAROUND || !CONFIG_IDF_TARGET_ESP32) && CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY */ + int ret = xTaskCreatePinnedToCore(adv_thread, BLE_MESH_ADV_TASK_NAME, BLE_MESH_ADV_TASK_STACK_SIZE, NULL, + BLE_MESH_ADV_TASK_PRIO, &adv_task.handle, BLE_MESH_ADV_TASK_CORE); +#if CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE + if (ret != pdTRUE) { + BT_ERR("xTaskCreatePinnedToCore failed, ret %d", ret); + return; + } +#else + assert(ret == pdTRUE); +#endif /* CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE */ +#endif /* CONFIG_BLE_MESH_FREERTOS_STATIC_ALLOC_EXTERNAL && (CONFIG_SPIRAM_CACHE_WORKAROUND || !CONFIG_IDF_TARGET_ESP32) && CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY */ +} + +void bt_mesh_adv_common_init(void) +{ + BT_DBG("AdvCommonInit"); + + bt_mesh_r_mutex_create(&adv_buf_alloc_lock); + bt_mesh_adv_queue_init(&adv_queue, bt_mesh_adv_buf_count_get(), bt_mesh_task_post); + bt_mesh_adv_type_init(BLE_MESH_ADV_PROV, &adv_queue, &adv_buf_pool, adv_alloc); + bt_mesh_adv_type_init(BLE_MESH_ADV_DATA, &adv_queue, &adv_buf_pool, adv_alloc); + bt_mesh_adv_type_init(BLE_MESH_ADV_BEACON, &adv_queue, &adv_buf_pool, adv_alloc); + bt_mesh_adv_type_init(BLE_MESH_ADV_URI, &adv_queue, &adv_buf_pool, adv_alloc); +#if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX + bt_mesh_adv_type_init(BLE_MESH_ADV_PROXY_SOLIC, &adv_queue, &adv_buf_pool, adv_alloc); +#endif /* CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX */ + +#if CONFIG_BLE_MESH_USE_BLE_50 + bt_mesh_adv_inst_init(BLE_MESH_ADV_INST, CONFIG_BLE_MESH_ADV_INST_ID); +#if CONFIG_BLE_MESH_EXT_ADV + bt_mesh_adv_type_init(BLE_MESH_ADV_EXT_PROV, &adv_queue, &ext_adv_buf_pool, ext_adv_alloc); + bt_mesh_adv_type_init(BLE_MESH_ADV_EXT_DATA, &adv_queue, &ext_adv_buf_pool, ext_adv_alloc); +#if !CONFIG_BLE_MESH_RELAY_ADV_BUF && CONFIG_BLE_MESH_EXT_RELAY_ADV_BUF_COUNT + bt_mesh_adv_type_init(BLE_MESH_ADV_EXT_RELAY_DATA, &adv_queue, &ext_relay_adv_buf_pool, ext_relay_adv_alloc); +#endif +#if CONFIG_BLE_MESH_LONG_PACKET + bt_mesh_adv_type_init(BLE_MESH_ADV_EXT_LONG_PROV, &adv_queue, &ext_long_adv_buf_pool, ext_long_adv_alloc); + bt_mesh_adv_type_init(BLE_MESH_ADV_EXT_LONG_DATA, &adv_queue, &ext_long_adv_buf_pool, ext_long_adv_alloc); +#if !CONFIG_BLE_MESH_RELAY_ADV_BUF && CONFIG_BLE_MESH_LONG_PACKET_RELAY_ADV_BUF_COUNT + bt_mesh_adv_type_init(BLE_MESH_ADV_EXT_LONG_RELAY_DATA, &adv_queue, &ext_long_relay_adv_buf_pool, ext_long_relay_adv_alloc); +#endif /* !CONFIG_BLE_MESH_RELAY_ADV_BUF && CONFIG_BLE_MESH_LONG_PACKET_RELAY_ADV_BUF_COUNT */ +#endif /* CONFIG_BLE_MESH_LONG_PACKET */ +#endif /* CONFIG_BLE_MESH_EXT_ADV */ +#endif /* CONFIG_BLE_MESH_USE_BLE_50 */ + +#if CONFIG_BLE_MESH_SUPPORT_MULTI_ADV + /* Due to the limitation of the sequence number in the network layer, + * it is not possible to use multiple advertising instances to process + * data from the same message queue when sending mesh packets. + * + * Therefore, shall to check whether there are duplicates in the queue + * buffer corresponding to each advertising instance. + */ + bt_mesh_adv_inst_type_add(BLE_MESH_ADV_INST, BLE_MESH_ADV_PROV); + bt_mesh_adv_inst_type_add(BLE_MESH_ADV_INST, BLE_MESH_ADV_DATA); + bt_mesh_adv_inst_type_add(BLE_MESH_ADV_INST, BLE_MESH_ADV_BEACON); + bt_mesh_adv_inst_type_add(BLE_MESH_ADV_INST, BLE_MESH_ADV_URI); +#if CONFIG_BLE_MESH_EXT_ADV + bt_mesh_adv_inst_type_add(BLE_MESH_ADV_INST, BLE_MESH_ADV_EXT_PROV); + bt_mesh_adv_inst_type_add(BLE_MESH_ADV_INST, BLE_MESH_ADV_EXT_DATA); +#if CONFIG_BLE_MESH_RELAY && !CONFIG_BLE_MESH_RELAY_ADV_BUF + bt_mesh_adv_inst_type_add(BLE_MESH_ADV_INST, BLE_MESH_ADV_EXT_RELAY_DATA); +#endif +#if CONFIG_BLE_MESH_LONG_PACKET + bt_mesh_adv_inst_type_add(BLE_MESH_ADV_INST, BLE_MESH_ADV_EXT_LONG_PROV); + bt_mesh_adv_inst_type_add(BLE_MESH_ADV_INST, BLE_MESH_ADV_EXT_LONG_DATA); +#if CONFIG_BLE_MESH_RELAY && !CONFIG_BLE_MESH_RELAY_ADV_BUF + bt_mesh_adv_inst_type_add(BLE_MESH_ADV_INST, BLE_MESH_ADV_EXT_LONG_RELAY_DATA); +#endif /* !CONFIG_BLE_MESH_RELAY_ADV_BUF */ +#endif /* CONFIG_BLE_MESH_LONG_PACKET */ +#endif /* CONFIG_BLE_MESH_EXT_ADV */ +#endif /* CONFIG_BLE_MESH_SUPPORT_MULTI_ADV */ +} + +#if CONFIG_BLE_MESH_DEINIT +void bt_mesh_adv_task_deinit(void) +{ + BT_DBG("AdvTaskDeinit"); + + vTaskDelete(adv_task.handle); + adv_task.handle = NULL; + +#if (CONFIG_BLE_MESH_FREERTOS_STATIC_ALLOC_EXTERNAL && \ + (CONFIG_SPIRAM_CACHE_WORKAROUND || !CONFIG_IDF_TARGET_ESP32) && \ + CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY) + heap_caps_free(adv_task.stack); + adv_task.stack = NULL; + heap_caps_free(adv_task.task); + adv_task.task = NULL; +#endif +} + +void bt_mesh_adv_common_deinit(void) +{ + BT_DBG("AdvCommonDeinit"); + + bt_mesh_adv_type_deinit(BLE_MESH_ADV_PROV); + bt_mesh_adv_type_deinit(BLE_MESH_ADV_DATA); + bt_mesh_adv_type_deinit(BLE_MESH_ADV_BEACON); + bt_mesh_adv_type_deinit(BLE_MESH_ADV_URI); + +#if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX + bt_mesh_adv_type_deinit(BLE_MESH_ADV_PROXY_SOLIC); +#endif + +#if CONFIG_BLE_MESH_EXT_ADV + bt_mesh_adv_type_deinit(BLE_MESH_ADV_EXT_PROV); + bt_mesh_adv_type_deinit(BLE_MESH_ADV_EXT_DATA); +#if !CONFIG_BLE_MESH_RELAY_ADV_BUF + bt_mesh_adv_type_deinit(BLE_MESH_ADV_EXT_RELAY_DATA); +#endif +#if CONFIG_BLE_MESH_LONG_PACKET + bt_mesh_adv_type_deinit(BLE_MESH_ADV_EXT_LONG_PROV); + bt_mesh_adv_type_deinit(BLE_MESH_ADV_EXT_LONG_DATA); +#if !CONFIG_BLE_MESH_RELAY_ADV_BUF + bt_mesh_adv_type_deinit(BLE_MESH_ADV_EXT_LONG_RELAY_DATA); +#endif +#endif /* CONFIG_BLE_MESH_LONG_PACKET */ +#endif /* CONFIG_BLE_MESH_EXT_ADV */ + + bt_mesh_adv_queue_deinit(&adv_queue); + +#if CONFIG_BLE_MESH_USE_BLE_50 + bt_mesh_adv_inst_deinit(BLE_MESH_ADV_INST); +#endif /* CONFIG_BLE_MESH_USE_BLE_50 */ + + bt_mesh_unref_buf_from_pool(&adv_buf_pool); + memset(adv_pool, 0, sizeof(adv_pool)); + + bt_mesh_r_mutex_free(&adv_buf_alloc_lock); +} +#endif /* CONFIG_BLE_MESH_DEINIT */ diff --git a/components/bt/esp_ble_mesh/core/adv_common.h b/components/bt/esp_ble_mesh/core/adv_common.h new file mode 100644 index 000000000000..54267ee5222d --- /dev/null +++ b/components/bt/esp_ble_mesh/core/adv_common.h @@ -0,0 +1,405 @@ +/* Bluetooth Mesh */ + +/* + * SPDX-FileCopyrightText: 2017 Intel Corporation + * SPDX-FileContributor: 2024-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ADV_COMMON_H_ +#define _ADV_COMMON_H_ + +#include "mesh/common.h" +#include "mesh/atomic.h" +#include "mesh/access.h" +#include "mesh/adapter.h" +#include "mesh/queue.h" +#include "mesh/timer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Pre-5.0 controllers enforce a minimum interval of 100ms + * whereas 5.0+ controllers can go down to 20ms. + */ +#if CONFIG_BLE_MESH_HCI_5_0 +#define ADV_ITVL_MIN 20 +#else +#define ADV_ITVL_MIN 100 +#endif + +/* Convert from ms to 0.625ms units */ +#define ADV_SCAN_UNIT(_ms) ((_ms) * 8 / 5) +/* Convert from 0.625ms units to interval(ms) */ +#define ADV_SCAN_INT(val) ((val) * 5 / 8) + +/* Maximum advertising data payload for a single data type */ +#define BLE_MESH_ADV_DATA_SIZE 29 + +/* The user data is a pointer (4 bytes) to struct bt_mesh_adv */ +#define BLE_MESH_ADV_USER_DATA_SIZE 4 + +#define BLE_MESH_ADV(buf) (*(struct bt_mesh_adv **)net_buf_user_data(buf)) +#define BLE_MESH_ADV_BUSY(buf) (BLE_MESH_ADV(buf)->busy) + +#define BLE_MESH_MSG_NET_BUF(msg) ((struct net_buf *)(msg->arg)) + +#define BLE_MESH_ADV_INST_UNUSED 0xFF + +struct bt_mesh_adv { + const struct bt_mesh_send_cb *cb; + void *cb_data; + + uint8_t type; + + bt_mesh_atomic_t busy; + + uint8_t xmit; + + uint32_t adv_itvl; + uint8_t adv_cnt; + uint8_t channel_map; +}; + +#if CONFIG_BLE_MESH_USE_BLE_50 +#define EXT_ADV(buf) CONTAINER_OF(BLE_MESH_ADV(buf), bt_mesh_ext_adv_t, adv) +typedef struct { + struct bt_mesh_adv adv; + uint8_t primary_phy; + uint8_t secondary_phy; + uint8_t include_tx_power:1; + int8_t tx_power; +} bt_mesh_ext_adv_t; +#endif + +#if CONFIG_BLE_MESH_FRIEND +#define FRIEND_ADV(buf) CONTAINER_OF(BLE_MESH_ADV(buf), bt_mesh_friend_adv_t, adv) + +typedef struct { + struct bt_mesh_adv adv; + uint16_t app_idx; +} bt_mesh_friend_adv_t; +#endif /* CONFIG_BLE_MESH_FRIEND */ + +enum { +#if CONFIG_BLE_MESH_USE_BLE_50 + ADV_TASK_MESH_ADV_INST_EVT = BIT(CONFIG_BLE_MESH_ADV_INST_ID), + +#if CONFIG_BLE_MESH_SUPPORT_MULTI_ADV +#if (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || \ + CONFIG_BLE_MESH_GATT_PROXY_SERVER + ADV_TASK_PROX_ADV_INST_EVT = BIT(CONFIG_BLE_MESH_PROXY_ADV_INST_ID), +#endif + +#if CONFIG_BLE_MESH_SEPARATE_RELAY_ADV_INSTANCE + ADV_TASK_RELAY_ADV_INST_EVT = BIT(CONFIG_BLE_MESH_RELAY_ADV_INST_ID), +#endif + +#if CONFIG_BLE_MESH_SEPARATE_BLE_ADV_INSTANCE + ADV_TASK_BLE_ADV_INST_EVT = BIT(CONFIG_BLE_MESH_BLE_ADV_INST_ID), +#endif +#endif /* CONFIG_BLE_MESH_SUPPORT_MULTI_ADV */ + +#if (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || \ + CONFIG_BLE_MESH_GATT_PROXY_SERVER + ADV_TASK_PROXY_ADV_UPD_EVT = BIT(30), +#endif +#endif /* CONFIG_BLE_MESH_USE_BLE_50 */ + + ADV_TASK_PKT_SEND_EVT = BIT(31), + + ADV_TASK_EVT_MAX, +}; + +uint16_t bt_mesh_pdu_duration(uint8_t xmit); + +typedef struct bt_mesh_msg { + bool relay; /* Flag indicates if the packet is a relayed one */ + void *arg; /* Pointer to the struct net_buf */ + uint16_t src; /* Source address for relay packets */ + uint16_t dst; /* Destination address for relay packets */ + uint32_t timestamp; /* Timestamp recorded when the relay packet is posted to queue */ +} bt_mesh_msg_t; + +struct bt_mesh_adv_inst { + uint8_t id; + +#if CONFIG_BLE_MESH_SUPPORT_MULTI_ADV + bool busy; + struct net_buf *sending_buf; + + /* Indicate which adv_type is supported by this instance */ + uint32_t spt_mask; +#endif /* CONFIG_BLE_MESH_SUPPORT_MULTI_ADV */ +}; + +enum bt_mesh_adv_type { + BLE_MESH_ADV_PROV, + BLE_MESH_ADV_DATA, +#if CONFIG_BLE_MESH_EXT_ADV + BLE_MESH_ADV_EXT_PROV, + BLE_MESH_ADV_EXT_DATA, + BLE_MESH_ADV_EXT_RELAY_DATA, +#if CONFIG_BLE_MESH_LONG_PACKET + BLE_MESH_ADV_EXT_LONG_PROV, + BLE_MESH_ADV_EXT_LONG_DATA, + BLE_MESH_ADV_EXT_LONG_RELAY_DATA, +#endif /* CONFIG_BLE_MESH_LONG_PACKET */ +#endif /* CONFIG_BLE_MESH_EXT_ADV */ +#if CONFIG_BLE_MESH_FRIEND + BLE_MESH_ADV_FRIEND, +#endif +#if CONFIG_BLE_MESH_RELAY_ADV_BUF + BLE_MESH_ADV_RELAY_DATA, +#endif + BLE_MESH_ADV_BEACON, + BLE_MESH_ADV_URI, +#if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX + BLE_MESH_ADV_PROXY_SOLIC, +#endif +#if CONFIG_BLE_MESH_SUPPORT_BLE_ADV + BLE_MESH_ADV_BLE, +#endif + BLE_MESH_ADV_TYPES_NUM, +}; + +typedef enum { + BLE_MESH_BUF_REF_EQUAL, + BLE_MESH_BUF_REF_SMALL, + BLE_MESH_BUF_REF_MAX, +} bt_mesh_buf_ref_flag_t; + + +static const uint8_t adv_type[] = { + [BLE_MESH_ADV_PROV] = BLE_MESH_DATA_MESH_PROV, + [BLE_MESH_ADV_DATA] = BLE_MESH_DATA_MESH_MESSAGE, +#if CONFIG_BLE_MESH_EXT_ADV + [BLE_MESH_ADV_EXT_PROV] = BLE_MESH_DATA_MESH_PROV, + [BLE_MESH_ADV_EXT_RELAY_DATA] = BLE_MESH_DATA_MESH_MESSAGE, + [BLE_MESH_ADV_EXT_DATA] = BLE_MESH_DATA_MESH_MESSAGE, +#if CONFIG_BLE_MESH_LONG_PACKET + [BLE_MESH_ADV_EXT_LONG_PROV] = BLE_MESH_DATA_MESH_PROV, + [BLE_MESH_ADV_EXT_LONG_RELAY_DATA] = BLE_MESH_DATA_MESH_MESSAGE, + [BLE_MESH_ADV_EXT_LONG_DATA] = BLE_MESH_DATA_MESH_MESSAGE, +#endif /* CONFIG_BLE_MESH_LONG_PACKET */ +#endif /* CONFIG_BLE_MESH_EXT_ADV */ +#if CONFIG_BLE_MESH_FRIEND + [BLE_MESH_ADV_FRIEND] = BLE_MESH_DATA_MESH_MESSAGE, +#endif +#if CONFIG_BLE_MESH_RELAY_ADV_BUF + [BLE_MESH_ADV_RELAY_DATA] = BLE_MESH_DATA_MESH_MESSAGE, +#endif + [BLE_MESH_ADV_BEACON] = BLE_MESH_DATA_MESH_BEACON, + [BLE_MESH_ADV_URI] = BLE_MESH_DATA_URI, +}; + +typedef struct bt_mesh_adv *(*bt_mesh_pool_allocator_t)(int id, enum bt_mesh_adv_type type); +typedef void (*bt_mesh_adv_queue_send_cb_t)(bt_mesh_msg_t *msg, uint32_t timeout, bool front); + +struct bt_mesh_adv_type_manager { + struct bt_mesh_adv_queue *adv_q; + struct net_buf_pool *pool; + bt_mesh_pool_allocator_t pool_allocator; +}; + +struct bt_mesh_adv_queue { + bt_mesh_queue_t q; + bt_mesh_adv_queue_send_cb_t send; +}; + +static inline TickType_t K_WAIT(int32_t val) +{ + return (val == K_FOREVER) ? portMAX_DELAY : (val / portTICK_PERIOD_MS); +} + +static inline void adv_send_start(uint16_t duration, int err, + const struct bt_mesh_send_cb *cb, + void *cb_data) +{ + if (cb && cb->start) { + cb->start(duration, err, cb_data); + } +} + +static inline void adv_send_end(int err, const struct bt_mesh_send_cb *cb, + void *cb_data) +{ + if (cb && cb->end) { + cb->end(err, cb_data); + } +} + +struct bt_mesh_adv_queue *bt_mesh_adv_queue_get(void); + +struct net_buf *bt_mesh_adv_create_from_pool(enum bt_mesh_adv_type type, int32_t timeout); + +static inline struct net_buf *bt_mesh_adv_create(enum bt_mesh_adv_type type, int32_t timeout) +{ + return bt_mesh_adv_create_from_pool(type, timeout); +} + +void bt_mesh_adv_buf_ref_debug(const char *func, struct net_buf *buf, + uint8_t ref_cmp, bt_mesh_buf_ref_flag_t flag); + +struct bt_mesh_adv_type_manager *bt_mesh_adv_types_mgmt_get(enum bt_mesh_adv_type adv_type); + +void bt_mesh_generic_adv_send(struct net_buf *buf, uint8_t xmit, + const struct bt_mesh_send_cb *cb, + void *cb_data, uint16_t src, + uint16_t dst, bool front); + +static inline void bt_mesh_adv_send(struct net_buf *buf, uint8_t xmit, + const struct bt_mesh_send_cb *cb, + void *cb_data) +{ + bt_mesh_generic_adv_send(buf, xmit, cb, cb_data, BLE_MESH_ADDR_UNASSIGNED, BLE_MESH_ADDR_UNASSIGNED, false); +} + +void bt_mesh_unref_buf_from_pool(struct net_buf_pool *pool); + +void bt_mesh_unref_buf(bt_mesh_msg_t *msg); + +int bt_mesh_adv_queue_init(struct bt_mesh_adv_queue *adv_queue, + uint16_t queue_size, + bt_mesh_adv_queue_send_cb_t cb); + +int bt_mesh_adv_queue_deinit(struct bt_mesh_adv_queue *adv_queue); + +void bt_mesh_adv_type_init(enum bt_mesh_adv_type adv_type, + struct bt_mesh_adv_queue *adv_queue, + struct net_buf_pool *buf_pool, + bt_mesh_pool_allocator_t adv_alloc); + +void bt_mesh_adv_type_deinit(enum bt_mesh_adv_type adv_type); + +void bt_mesh_task_post(bt_mesh_msg_t *msg, uint32_t timeout, bool front); + +#if CONFIG_BLE_MESH_USE_BLE_50 +struct bt_mesh_adv_inst *bt_mesh_get_adv_insts_set(void); + +bool bt_mesh_is_adv_inst_used(uint8_t inst_id); + +int bt_mesh_adv_inst_init(enum bt_mesh_adv_inst_type inst_type, uint8_t inst_id); + +int bt_mesh_adv_inst_deinit(enum bt_mesh_adv_inst_type inst_type); +#endif /* CONFIG_BLE_MESH_USE_BLE_50 */ + +#if CONFIG_BLE_MESH_SUPPORT_MULTI_ADV +void bt_mesh_adv_inst_type_add(enum bt_mesh_adv_inst_type inst_type, + enum bt_mesh_adv_type adv_type); + +void bt_mesh_adv_inst_type_rem(enum bt_mesh_adv_inst_type inst_type, + enum bt_mesh_adv_type adv_type); + +void bt_mesh_adv_inst_type_clear(enum bt_mesh_adv_inst_type inst_type, + enum bt_mesh_adv_type adv_type); +#endif /* CONFIG_BLE_MESH_SUPPORT_MULTI_ADV */ + +#if CONFIG_BLE_MESH_RELAY_ADV_BUF +static ALWAYS_INLINE +uint16_t bt_mesh_relay_adv_buf_count_get(void) +{ + uint16_t relay_adv_count = 2 + CONFIG_BLE_MESH_RELAY_ADV_BUF_COUNT; + +#if CONFIG_BLE_MESH_EXT_ADV && CONFIG_BLE_MESH_RELAY + relay_adv_count += CONFIG_BLE_MESH_EXT_RELAY_ADV_BUF_COUNT; +#endif + +#if CONFIG_BLE_MESH_LONG_PACKET && CONFIG_BLE_MESH_RELAY + relay_adv_count += CONFIG_BLE_MESH_LONG_PACKET_RELAY_ADV_BUF_COUNT; +#endif + return relay_adv_count; +} + +void bt_mesh_relay_adv_init(void); + +bool bt_mesh_ignore_relay_packet(uint32_t timestamp); + +static inline void bt_mesh_relay_adv_send(struct net_buf *buf, uint8_t xmit, + uint16_t src, uint16_t dst, + const struct bt_mesh_send_cb *cb, + void *cb_data) +{ + bt_mesh_generic_adv_send(buf, xmit, cb, cb_data, src, dst, false); +}; + +uint16_t bt_mesh_get_stored_relay_count(void); + +#if CONFIG_BLE_MESH_DEINIT +void bt_mesh_relay_adv_deinit(void); +#endif +#endif /* CONFIG_BLE_MESH_RELAY_ADV_BUF */ + +#if CONFIG_BLE_MESH_FRIEND +void bt_mesh_frnd_adv_init(void); + +#if CONFIG_BLE_MESH_DEINIT +void bt_mesh_frnd_adv_deinit(void); +#endif /* CONFIG_BLE_MESH_DEINIT */ +#endif /* CONFIG_BLE_MESH_FRIEND */ + +static ALWAYS_INLINE +uint16_t bt_mesh_adv_buf_count_get(void) +{ + uint16_t adv_count = 2 + CONFIG_BLE_MESH_ADV_BUF_COUNT; + +#if CONFIG_BLE_MESH_EXT_ADV + adv_count += CONFIG_BLE_MESH_EXT_ADV_BUF_COUNT; +#if !CONFIG_BLE_MESH_RELAY_ADV_BUF && CONFIG_BLE_MESH_RELAY + adv_count += CONFIG_BLE_MESH_EXT_RELAY_ADV_BUF_COUNT; +#endif /* !CONFIG_BLE_MESH_RELAY_ADV_BUF && CONFIG_BLE_MESH_RELAY */ +#endif /* CONFIG_BLE_MESH_EXT_ADV */ + +#if CONFIG_BLE_MESH_LONG_PACKET + adv_count += CONFIG_BLE_MESH_LONG_PACKET_ADV_BUF_COUNT; +#if !CONFIG_BLE_MESH_RELAY_ADV_BUF && CONFIG_BLE_MESH_RELAY + adv_count += CONFIG_BLE_MESH_LONG_PACKET_RELAY_ADV_BUF_COUNT; +#endif /* !CONFIG_BLE_MESH_RELAY_ADV_BUF && CONFIG_BLE_MESH_RELAY */ +#endif /* CONFIG_BLE_MESH_LONG_PACKET */ + +#if (CONFIG_BLE_MESH_SUPPORT_BLE_ADV && \ + !(CONFIG_BLE_MESH_USE_BLE_50 && CONFIG_BLE_MESH_SEPARATE_BLE_ADV_INSTANCE)) + adv_count += CONFIG_BLE_MESH_BLE_ADV_BUF_COUNT; +#endif /* CONFIG_BLE_MESH_SUPPORT_BLE_ADV */ + + return adv_count; +} + +void bt_mesh_adv_task_init(void adv_thread(void *p)); + +void bt_mesh_adv_common_init(void); + +#if CONFIG_BLE_MESH_DEINIT +void bt_mesh_adv_task_deinit(void); + +void bt_mesh_adv_common_deinit(void); +#endif + +#if CONFIG_BLE_MESH_USE_BLE_50 +int bt_mesh_adv_task_wakeup(uint32_t evt); + +bool bt_mesh_adv_task_wait(uint32_t wait_bits, TickType_t timeout, uint32_t *notify); +#else /* CONFIG_BLE_MESH_USE_BLE_50 */ +bool bt_mesh_adv_task_wait(uint32_t timeout); +#endif /* CONFIG_BLE_MESH_USE_BLE_50 */ + +#if CONFIG_BLE_MESH_SUPPORT_BLE_ADV +static inline void bt_mesh_ble_adv_send(struct net_buf *buf, const struct bt_mesh_send_cb *cb, + void *cb_data, bool front) +{ + bt_mesh_generic_adv_send(buf, 0, cb, cb_data, BLE_MESH_ADDR_UNASSIGNED, BLE_MESH_ADDR_UNASSIGNED, front); +} + +int bt_mesh_start_ble_advertising(const struct bt_mesh_ble_adv_param *param, + const struct bt_mesh_ble_adv_data *data, uint8_t *index); + +int bt_mesh_stop_ble_advertising(uint8_t index); +#endif /* CONFIG_BLE_MESH_SUPPORT_BLE_ADV */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ADV_COMMON_H_ */ diff --git a/components/bt/esp_ble_mesh/core/beacon.c b/components/bt/esp_ble_mesh/core/beacon.c index 97ec6ebd8231..e58214c0c3aa 100644 --- a/components/bt/esp_ble_mesh/core/beacon.c +++ b/components/bt/esp_ble_mesh/core/beacon.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -27,19 +27,19 @@ #if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" -#endif +#endif /* CONFIG_BLE_MESH_V11_SUPPORT */ -#if defined(CONFIG_BLE_MESH_UNPROVISIONED_BEACON_INTERVAL) +#if CONFIG_BLE_MESH_UNPROVISIONED_BEACON_INTERVAL #define UNPROV_BEACON_INTERVAL K_SECONDS(CONFIG_BLE_MESH_UNPROVISIONED_BEACON_INTERVAL) -#else +#else /* CONFIG_BLE_MESH_UNPROVISIONED_BEACON_INTERVAL */ #define UNPROV_BEACON_INTERVAL K_SECONDS(5) -#endif +#endif /* CONFIG_BLE_MESH_UNPROVISIONED_BEACON_INTERVAL */ #if CONFIG_BLE_MESH_BQB_TEST #define SECURE_BEACON_INTERVAL K_SECONDS(3) -#else +#else /* CONFIG_BLE_MESH_BQB_TEST */ #define SECURE_BEACON_INTERVAL K_SECONDS(10) -#endif +#endif /* CONFIG_BLE_MESH_BQB_TEST */ /* 3 transmissions, 20ms interval */ #define UNPROV_XMIT BLE_MESH_TRANSMIT(2, 20) @@ -58,6 +58,8 @@ struct bt_mesh_subnet *cache_check(uint8_t data[21], bool private_beacon) uint8_t *cache = NULL; int i = 0; + BT_DBG("CacheCheck, PrivateBeacon %u", private_beacon); + subnet_size = bt_mesh_rx_netkey_size(); for (i = 0; i < subnet_size; i++) { @@ -69,11 +71,12 @@ struct bt_mesh_subnet *cache_check(uint8_t data[21], bool private_beacon) #if CONFIG_BLE_MESH_PRIVATE_BEACON cache = private_beacon ? sub->mpb_cache : sub->snb_cache; -#else +#else /* CONFIG_BLE_MESH_PRIVATE_BEACON */ cache = sub->snb_cache; -#endif +#endif /* CONFIG_BLE_MESH_PRIVATE_BEACON */ if (!memcmp(cache, data, 21)) { + BT_DBG("BeaconSubFound, NetIdx 0x%04x", sub->net_idx); return sub; } } @@ -83,11 +86,13 @@ struct bt_mesh_subnet *cache_check(uint8_t data[21], bool private_beacon) void cache_add(uint8_t data[21], struct bt_mesh_subnet *sub, bool private_beacon) { + BT_DBG("CacheAdd, NetIdx 0x%04x PrivateBeacon %u", sub->net_idx, private_beacon); + #if CONFIG_BLE_MESH_PRIVATE_BEACON if (private_beacon) { memcpy(sub->mpb_cache, data, 21); } else -#endif +#endif /* CONFIG_BLE_MESH_PRIVATE_BEACON */ { memcpy(sub->snb_cache, data, 21); } @@ -98,10 +103,10 @@ static void secure_beacon_complete(int err, void *user_data) struct bt_mesh_subnet *sub = NULL; uint16_t net_idx = BLE_MESH_KEY_UNUSED; - BT_DBG("err %d", err); - net_idx = (uint16_t)NET_IDX_GET(user_data); + BT_DBG("SecureBeaconComplete, NetIdx 0x%04x Err %d", net_idx, err); + /* For node, directly updating the "beacon_sent" timestamp is fine, * since the subnet is pre-allocated. * For Provisioner, before updating the "beacon_sent" timestamp, we @@ -112,6 +117,8 @@ static void secure_beacon_complete(int err, void *user_data) sub = bt_mesh_subnet_get(net_idx); if (sub) { sub->snb_sent = k_uptime_get_32(); + + BT_DBG("SnbSent %lu", sub->snb_sent); } } @@ -121,6 +128,8 @@ void bt_mesh_secure_beacon_create(struct bt_mesh_subnet *sub, uint8_t flags = bt_mesh_net_flags(sub); struct bt_mesh_subnet_keys *keys = NULL; + BT_DBG("SecureBeaconCreate"); + net_buf_simple_add_u8(buf, BEACON_TYPE_SECURE); if (sub->kr_flag) { @@ -139,10 +148,10 @@ void bt_mesh_secure_beacon_create(struct bt_mesh_subnet *sub, net_buf_simple_add_mem(buf, sub->auth, 8); - BT_DBG("SNB: net_idx 0x%03x iv_index 0x%08x flags 0x%02x", - sub->net_idx, bt_mesh.iv_index, flags); - BT_DBG("SNB: NetID %s Auth %s", bt_hex(keys->net_id, 8), - bt_hex(sub->auth, 8)); + BT_DBG("NetIdx 0x%04x IVIndex 0x%08x Flags 0x%02x", + sub->net_idx, bt_mesh.iv_index, flags); + BT_DBG("NetID %s Auth %s", bt_hex(keys->net_id, 8), + bt_hex(sub->auth, 8)); } static int secure_beacon_send(void) @@ -154,6 +163,8 @@ static int secure_beacon_send(void) size_t subnet_size = 0U; int i = 0; + BT_DBG("SecureBeaconSend"); + subnet_size = bt_mesh_rx_netkey_size(); for (i = 0; i < subnet_size; i++) { @@ -165,6 +176,8 @@ static int secure_beacon_send(void) continue; } + BT_DBG("Now %lu SnbSent %lu SnbLast %u", now, sub->snb_sent, sub->snb_last); + time_diff = now - sub->snb_sent; if (time_diff < K_SECONDS(600) && time_diff < BEACON_THRESHOLD(sub->snb_last)) { @@ -178,9 +191,10 @@ static int secure_beacon_send(void) */ #if CONFIG_BLE_MESH_GATT_PROXY_CLIENT if (bt_mesh_proxy_client_beacon_send(sub, false)) { + BT_DBG("ProxyClientBeaconSend"); continue; } -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_CLIENT */ buf = bt_mesh_adv_create(BLE_MESH_ADV_BEACON, K_NO_WAIT); if (!buf) { @@ -201,6 +215,7 @@ static int secure_beacon_send(void) * updating its "snb_sent" timestamp. */ bt_mesh_adv_send(buf, SNB_XMIT, &send_cb, NET_IDX_SET(sub->net_idx)); + net_buf_unref(buf); } @@ -214,6 +229,8 @@ static int unprovisioned_beacon_send(void) struct net_buf *buf = NULL; uint16_t oob_info = 0U; + BT_DBG("UnprovisionedBeaconSend"); + if (bt_mesh_prov_get() == NULL) { BT_ERR("No provisioning context provided"); return -EINVAL; @@ -252,6 +269,8 @@ static int unprovisioned_beacon_send(void) len = strlen(bt_mesh_prov_get()->uri); + BT_DBG("URI %u: %s", len, bt_mesh_prov_get()->uri); + if (net_buf_tailroom(buf) < len) { BT_WARN("Too long URI to fit advertising data"); } else { @@ -277,6 +296,8 @@ void update_beacon_observation(bool private_beacon) size_t subnet_size = 0U; int i = 0; + BT_DBG("UpdateBeaconObservation, PrivateBeacon %u", private_beacon); + /* Observation period is 20 seconds, whereas the beacon timer * runs every 10 seconds. We process what's happened during * the window only after the second half. @@ -287,13 +308,15 @@ void update_beacon_observation(bool private_beacon) if (private_beacon) { mpb_first_half = !mpb_first_half; if (mpb_first_half) { + BT_DBG("MpbFirstHalf"); return; } } else -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ { snb_first_half = !snb_first_half; if (snb_first_half) { + BT_DBG("SnbFirstHalf"); return; } } @@ -309,11 +332,15 @@ void update_beacon_observation(bool private_beacon) #if CONFIG_BLE_MESH_PRB_SRV if (private_beacon) { + BT_DBG("NetIdx 0x%04x MpbCur %u", sub->net_idx, sub->mpb_cur); + sub->mpb_last = sub->mpb_cur; sub->mpb_cur = 0U; } else -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ { + BT_DBG("NetIdx 0x%04x SnbCur %u", sub->net_idx, sub->snb_cur); + sub->snb_last = sub->snb_cur; sub->snb_cur = 0U; } @@ -330,9 +357,12 @@ static bool ready_to_send(void) static void secure_beacon_send_timeout(struct k_work *work) { + BT_DBG("SecureBeaconSendTimeout"); + /* Don't send anything if we have an active provisioning link */ if (IS_ENABLED(CONFIG_BLE_MESH_NODE) && bt_mesh_is_node() && IS_ENABLED(CONFIG_BLE_MESH_PROV) && bt_mesh_prov_active()) { + BT_DBG("ProvActive"); k_delayed_work_submit(&snb_timer, UNPROV_BEACON_INTERVAL); return; } @@ -345,11 +375,14 @@ static void secure_beacon_send_timeout(struct k_work *work) /* Only resubmit if beaconing is still enabled */ if (bt_mesh_secure_beacon_get() == BLE_MESH_SECURE_BEACON_ENABLED || bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_IVU_INITIATOR)) { + BT_DBG("Resubmit, SecureBeacon %u", bt_mesh_secure_beacon_get()); + k_delayed_work_submit(&snb_timer, SECURE_BEACON_INTERVAL); } } else { if (IS_ENABLED(CONFIG_BLE_MESH_NODE) && bt_mesh_is_node()) { unprovisioned_beacon_send(); + k_delayed_work_submit(&snb_timer, UNPROV_BEACON_INTERVAL); } } @@ -365,6 +398,8 @@ static void secure_beacon_recv(struct net_buf_simple *buf) bool new_key = false; uint8_t flags = 0U; + BT_DBG("SecureBeaconRecv"); + if (buf->len != 21) { BT_ERR("Malformed secure beacon (len %u)", buf->len); return; @@ -384,7 +419,7 @@ static void secure_beacon_recv(struct net_buf_simple *buf) iv_index = net_buf_simple_pull_be32(buf); auth = buf->data; - BT_DBG("flags 0x%02x id %s iv_index 0x%08x", + BT_DBG("Flags 0x%02x NetID %s IVIndex 0x%08x", flags, bt_hex(net_id, 8), iv_index); sub = bt_mesh_subnet_find_with_snb(net_id, flags, iv_index, auth, &new_key); @@ -393,6 +428,9 @@ static void secure_beacon_recv(struct net_buf_simple *buf) return; } + BT_DBG("NetIdx 0x%04x KrPhase %u NewKey %u", + sub->net_idx, sub->kr_phase, new_key); + if (sub->kr_phase == BLE_MESH_KR_PHASE_2 && !new_key) { BT_WARN("Ignoring Phase 2 KR Update secured using old key"); return; @@ -417,8 +455,7 @@ static void secure_beacon_recv(struct net_buf_simple *buf) goto update_stats; } - BT_DBG("SNB: net_idx 0x%03x iv_index 0x%08x current iv_index 0x%08x", - sub->net_idx, iv_index, bt_mesh.iv_index); + BT_DBG("IVIndex 0x%08lx CurIVIndex 0x%08lx", iv_index, bt_mesh.iv_index); if (bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_IVU_INITIATOR) && (bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_IVU_IN_PROGRESS) == @@ -452,6 +489,7 @@ static void secure_beacon_recv(struct net_buf_simple *buf) update_stats: if (bt_mesh_secure_beacon_get() == BLE_MESH_SECURE_BEACON_ENABLED && sub->snb_cur < 0xff) { + BT_DBG("SnbCurInc %u", sub->snb_cur); sub->snb_cur++; } } @@ -460,7 +498,8 @@ void bt_mesh_beacon_recv(struct net_buf_simple *buf, int8_t rssi) { uint8_t type = 0U; - BT_DBG("%u bytes: %s", buf->len, bt_hex(buf->data, buf->len)); + BT_DBG("BeaconRecv"); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); if (buf->len < 1) { BT_ERR("Too short beacon"); @@ -470,7 +509,7 @@ void bt_mesh_beacon_recv(struct net_buf_simple *buf, int8_t rssi) type = net_buf_simple_pull_u8(buf); switch (type) { case BEACON_TYPE_UNPROVISIONED: - BT_DBG("Unprovisioned device beacon received"); + BT_DBG("UnprovDevBeaconRecv, Rssi %d", rssi); if (IS_ENABLED(CONFIG_BLE_MESH_PROVISIONER) && IS_ENABLED(CONFIG_BLE_MESH_PB_ADV) && @@ -480,11 +519,16 @@ void bt_mesh_beacon_recv(struct net_buf_simple *buf, int8_t rssi) #if CONFIG_BLE_MESH_RPR_SRV if (bt_mesh_is_provisioned()) { - const bt_mesh_addr_t *addr = bt_mesh_get_unprov_dev_addr(); + const bt_mesh_addr_t *addr = NULL; + + addr = bt_mesh_get_unprov_dev_addr(); + assert(addr); + bt_mesh_unprov_dev_fifo_enqueue(buf->data, addr->val, bt_mesh_get_adv_type()); + bt_mesh_rpr_srv_unprov_beacon_recv(buf, bt_mesh_get_adv_type(), addr, rssi); } -#endif +#endif /* CONFIG_BLE_MESH_RPR_SRV */ break; case BEACON_TYPE_SECURE: secure_beacon_recv(buf); @@ -493,7 +537,7 @@ void bt_mesh_beacon_recv(struct net_buf_simple *buf, int8_t rssi) case BEACON_TYPE_PRIVATE: bt_mesh_private_beacon_recv(buf); break; -#endif +#endif /* CONFIG_BLE_MESH_PRIVATE_BEACON */ default: BT_DBG("Unknown beacon type 0x%02x", type); break; @@ -514,7 +558,7 @@ void bt_mesh_beacon_init(void) BT_ERR("Failed to create a mpb_timer"); return; } -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ } #if CONFIG_BLE_MESH_DEINIT @@ -532,24 +576,28 @@ void bt_mesh_beacon_deinit(void) void bt_mesh_beacon_ivu_initiator(bool enable) { + BT_DBG("BeaconIVUInitiator, IVUInitiator %u", enable); + bt_mesh_atomic_set_bit_to(bt_mesh.flags, BLE_MESH_IVU_INITIATOR, enable); if (enable) { k_delayed_work_submit(&snb_timer, K_NO_WAIT); + #if CONFIG_BLE_MESH_PRB_SRV if (bt_mesh_private_beacon_state_get() == BLE_MESH_PRIVATE_BEACON_ENABLED) { bt_mesh_private_beacon_timer_submit(K_NO_WAIT); } -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ } else { if (bt_mesh_secure_beacon_get() == BLE_MESH_SECURE_BEACON_DISABLED) { k_delayed_work_cancel(&snb_timer); } + #if CONFIG_BLE_MESH_PRB_SRV if (bt_mesh_private_beacon_state_get() == BLE_MESH_PRIVATE_BEACON_DISABLED) { bt_mesh_private_beacon_timer_cancel(); } -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ } } @@ -558,8 +606,12 @@ void bt_mesh_secure_beacon_enable(void) size_t subnet_size = 0U; int i = 0; + BT_DBG("SecureBeaconEnable"); + if (IS_ENABLED(CONFIG_BLE_MESH_NODE) && bt_mesh_is_node() && !bt_mesh_is_provisioned()) { + BT_DBG("NodeNotProvisioned"); + k_delayed_work_submit(&snb_timer, K_NO_WAIT); return; } @@ -584,6 +636,9 @@ void bt_mesh_secure_beacon_enable(void) void bt_mesh_secure_beacon_disable(void) { + BT_DBG("SecureBeaconDisable, IVUInitiator %u", + bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_IVU_INITIATOR)); + if (!bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_IVU_INITIATOR)) { k_delayed_work_cancel(&snb_timer); } diff --git a/components/bt/esp_ble_mesh/core/ble_adv.c b/components/bt/esp_ble_mesh/core/ble_adv.c new file mode 100644 index 000000000000..aaaa4b429060 --- /dev/null +++ b/components/bt/esp_ble_mesh/core/ble_adv.c @@ -0,0 +1,371 @@ +/* Bluetooth Mesh */ + +/* + * SPDX-FileCopyrightText: 2017 Intel Corporation + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include "ble_adv.h" +#include "mesh/common.h" +#include "mesh/buf.h" + +#if CONFIG_BLE_MESH_USE_BLE_50 && CONFIG_BLE_MESH_SEPARATE_BLE_ADV_INSTANCE +/* Use independent ble adv queue only if multi adv instance is used */ +static struct bt_mesh_adv_queue ble_adv_queue; +static void bt_mesh_ble_task_post(bt_mesh_msg_t *msg, uint32_t timeout, bool front); +#endif + +static struct bt_mesh_adv_queue *p_ble_adv_queue; + +/* length + advertising data + length + scan response data */ +NET_BUF_POOL_DEFINE(ble_adv_buf_pool, CONFIG_BLE_MESH_BLE_ADV_BUF_COUNT, + ((BLE_MESH_ADV_DATA_SIZE + 3) << 1), BLE_MESH_ADV_USER_DATA_SIZE, NULL); + +static struct bt_mesh_adv ble_adv_pool[CONFIG_BLE_MESH_BLE_ADV_BUF_COUNT]; + +static struct bt_mesh_ble_adv_tx ble_adv_tx[CONFIG_BLE_MESH_BLE_ADV_BUF_COUNT]; + +#define SEND_BLE_ADV_INFINITE 0xFFFF + +static struct bt_mesh_adv *ble_adv_alloc(int id, enum bt_mesh_adv_type type) +{ + BT_DBG("BLEAdvAlloc, ID %d", id); + memset(&ble_adv_pool[id], 0, sizeof(struct bt_mesh_adv)); + ble_adv_pool[id].type = type; + return &ble_adv_pool[id]; +} + +#if CONFIG_BLE_MESH_USE_BLE_50 && CONFIG_BLE_MESH_SEPARATE_BLE_ADV_INSTANCE +/* A separate post function is required only when using a separate queue */ +static void bt_mesh_ble_task_post(bt_mesh_msg_t *msg, uint32_t timeout, bool front) +{ + BT_DBG("BLETaskPost, Front %u", front); + + if (p_ble_adv_queue->q.handle == NULL) { + BT_ERR("Invalid adv queue"); + return; + } + + if (front) { + if (xQueueSendToFront(p_ble_adv_queue->q.handle, msg, timeout) != pdTRUE) { + BT_ERR("Failed to send item to adv queue front"); + bt_mesh_unref_buf(msg); + } + } else { + if (xQueueSend(p_ble_adv_queue->q.handle, msg, timeout) != pdTRUE) { + BT_ERR("Failed to send item to adv queue back"); + bt_mesh_unref_buf(msg); + } + } +} +#endif + +static void ble_adv_tx_reset(struct bt_mesh_ble_adv_tx *tx, bool unref) +{ + BT_DBG("BLEAdvTxReset, Unref %u", unref); + + if (tx->buf == NULL) { + BT_DBG("NullTxBuf"); + return; + } + + if (bt_mesh_atomic_test_bit(tx->flags, TIMER_INIT)) { + k_delayed_work_free(&tx->resend); + } + bt_mesh_atomic_set(tx->flags, 0); + + memset(&tx->param, 0, sizeof(tx->param)); + + BT_DBG("Buf %p Ref %u Busy %u", + tx->buf, tx->buf->ref, + !!bt_mesh_atomic_get(&BLE_MESH_ADV_BUSY(tx->buf))); + + bt_mesh_atomic_set(&BLE_MESH_ADV_BUSY(tx->buf), 0); + if (unref) { + net_buf_unref(tx->buf); + } + tx->buf = NULL; +} + +static void ble_adv_send_start(uint16_t duration, int err, void *cb_data) +{ + struct bt_mesh_ble_adv_tx *tx = cb_data; + + BT_DBG("BLEAdvSendStart, Duration %u Err %d", duration, err); + + /* If failed to send BLE adv packet, and param->count is not 0 + * which means the timer has been initialized, here we need to + * free the timer. + */ + if (err) { + ble_adv_tx_reset(tx, true); + } +} + +static void ble_adv_send_end(int err, void *cb_data) +{ + struct bt_mesh_ble_adv_tx *tx = cb_data; + + BT_DBG("BLEAdvSendEnd, Err %d", err); + + if (err) { + ble_adv_tx_reset(tx, true); + return; + } + + BT_DBG("Count %u Period %u", tx->param.count, tx->param.period); + + if (tx->param.count) { + if (tx->param.period) { + k_delayed_work_submit(&tx->resend, tx->param.period); + } else { + k_work_submit(&tx->resend.work); + } + } else { + ble_adv_tx_reset(tx, true); + } +} + +static struct bt_mesh_send_cb ble_adv_send_cb = { + .start = ble_adv_send_start, + .end = ble_adv_send_end, +}; + +static void ble_adv_resend(struct k_work *work) +{ + struct bt_mesh_ble_adv_tx *tx = CONTAINER_OF(work, struct bt_mesh_ble_adv_tx, resend.work); + bool front = false; + + BT_DBG("BLEAdvResend"); + + if (tx->buf == NULL) { + /* The advertising has been cancelled */ + BT_INFO("%s, cancelled", __func__); + return; + } + + BT_DBG("Priority %u Count %u Buf %p", tx->param.priority, tx->param.count, tx->buf); + + front = (tx->param.priority == BLE_MESH_BLE_ADV_PRIO_HIGH) ? true : false; + + bt_mesh_ble_adv_send(tx->buf, &ble_adv_send_cb, tx, front); + + if (tx->param.count == SEND_BLE_ADV_INFINITE) { + /* Send the BLE advertising packet infinitely */ + return; + } + + if (tx->param.count > 0U) { + tx->param.count--; + } +} + +int bt_mesh_start_ble_advertising(const struct bt_mesh_ble_adv_param *param, + const struct bt_mesh_ble_adv_data *data, uint8_t *index) +{ + struct bt_mesh_ble_adv_tx *tx = NULL; + struct net_buf *buf = NULL; + bool front = false; + + BT_DBG("StartBLEAdv"); + + if (param == NULL || index == NULL) { + BT_ERR("%s, Invalid parameter", __func__); + return -EINVAL; + } + + if (param->adv_type != BLE_MESH_ADV_DIRECT_IND && + (param->interval < 0x20 || param->interval > 0x4000)) { + BT_ERR("Invalid adv interval 0x%04x", param->interval); + return -EINVAL; + } + + if (param->adv_type > BLE_MESH_ADV_DIRECT_IND_LOW_DUTY) { + BT_ERR("Invalid adv type 0x%02x", param->adv_type); + return -EINVAL; + } + + if (param->own_addr_type > BLE_MESH_ADDR_RANDOM_ID) { + BT_ERR("Invalid own addr type 0x%02x", param->own_addr_type); + return -EINVAL; + } + + if ((param->own_addr_type == BLE_MESH_ADDR_PUBLIC_ID || + param->own_addr_type == BLE_MESH_ADDR_RANDOM_ID || + param->adv_type == BLE_MESH_ADV_DIRECT_IND || + param->adv_type == BLE_MESH_ADV_DIRECT_IND_LOW_DUTY) && + param->peer_addr_type > BLE_MESH_ADDR_RANDOM) { + BT_ERR("Invalid peer addr type 0x%02x", param->peer_addr_type); + return -EINVAL; + } + + if (data && (data->adv_data_len > 31 || data->scan_rsp_data_len > 31)) { + BT_ERR("Invalid adv data length (adv %d, scan rsp %d)", + data->adv_data_len, data->scan_rsp_data_len); + return -EINVAL; + } + + if (param->priority > BLE_MESH_BLE_ADV_PRIO_HIGH) { + BT_ERR("Invalid adv priority %d", param->priority); + return -EINVAL; + } + + if (param->duration < ADV_SCAN_INT(param->interval)) { + BT_ERR("Too small duration %dms", param->duration); + return -EINVAL; + } + + buf = bt_mesh_adv_create(BLE_MESH_ADV_BLE, K_NO_WAIT); + if (!buf) { + BT_ERR("No empty ble adv buffer"); + return -ENOBUFS; + } + + BT_DBG("AdvType 0x%02x Interval 0x%04x AddrType 0x%02x/0x%02x", + param->adv_type, param->interval, param->own_addr_type, param->peer_addr_type); + BT_DBG("DataLen %u/%u Priority %u Count %u Duration %u", + (data ? data->adv_data_len : 0), (data ? data->scan_rsp_data_len : 0), + param->priority, param->count, param->duration); + + /* Set advertising data and scan response data */ + memset(buf->data, 0, buf->size); + if (data) { + net_buf_add_u8(buf, data->adv_data_len); + if (data->adv_data_len) { + net_buf_add_mem(buf, data->adv_data, data->adv_data_len); + } + net_buf_add_u8(buf, data->scan_rsp_data_len); + if (data->scan_rsp_data_len) { + net_buf_add_mem(buf, data->scan_rsp_data, data->scan_rsp_data_len); + } + } + + *index = net_buf_id(buf); + tx = &ble_adv_tx[*index]; + tx->buf = buf; + memcpy(&tx->param, param, sizeof(tx->param)); + + front = (tx->param.priority == BLE_MESH_BLE_ADV_PRIO_HIGH) ? true : false; + bt_mesh_ble_adv_send(buf, &ble_adv_send_cb, tx, front); + + if (param->count) { + if (k_delayed_work_init(&tx->resend, ble_adv_resend)) { + /* If failed to create a timer, the BLE adv packet will be + * sent only once. Just give a warning here, and since the + * BLE adv packet can be sent, return 0 here. + */ + BT_WARN("Send BLE adv packet only once"); + + tx->param.count = 0; + net_buf_unref(buf); + return 0; + } + + bt_mesh_atomic_set_bit(tx->flags, TIMER_INIT); + } else { + /* Send the BLE advertising packet only once */ + net_buf_unref(buf); + } + + return 0; +} + +int bt_mesh_stop_ble_advertising(uint8_t index) +{ + struct bt_mesh_ble_adv_tx *tx = NULL; + bool unref = true; + + BT_DBG("StopBLEAdv, Index %u", index); + + if (index >= ARRAY_SIZE(ble_adv_tx)) { + BT_ERR("Invalid adv index %d", index); + return -EINVAL; + } + + tx = &ble_adv_tx[index]; + + if (tx->buf == NULL) { + BT_WARN("Already stopped, index %d", index); + return 0; + } + + BT_DBG("Busy %u Ref %u", + !!bt_mesh_atomic_get(&BLE_MESH_ADV_BUSY(tx->buf)), + tx->buf->ref); + + /* busy 1, ref 1; busy 1, ref 2; + * busy 0, ref 0; busy 0, ref 1; + */ + + if (bt_mesh_atomic_get(&BLE_MESH_ADV_BUSY(tx->buf)) && + tx->buf->ref == 1U) { + unref = false; + } + ble_adv_tx_reset(tx, unref); + + return 0; +} + +struct bt_mesh_adv_queue *bt_mesh_ble_adv_queue_get(void) +{ +#if CONFIG_BLE_MESH_USE_BLE_50 && CONFIG_BLE_MESH_SEPARATE_BLE_ADV_INSTANCE + bt_mesh_adv_queue_init(&ble_adv_queue, CONFIG_BLE_MESH_BLE_ADV_BUF_COUNT, bt_mesh_ble_task_post); + return &ble_adv_queue; +#else + return bt_mesh_adv_queue_get(); +#endif +} + +void bt_mesh_ble_adv_init(void) +{ + BT_DBG("BLEAdvInit"); + p_ble_adv_queue = bt_mesh_ble_adv_queue_get(); + bt_mesh_adv_type_init(BLE_MESH_ADV_BLE, p_ble_adv_queue, &ble_adv_buf_pool, ble_adv_alloc); +#if CONFIG_BLE_MESH_USE_BLE_50 +#if CONFIG_BLE_MESH_SEPARATE_BLE_ADV_INSTANCE + bt_mesh_adv_inst_init(BLE_MESH_BLE_ADV_INST, CONFIG_BLE_MESH_BLE_ADV_INST_ID); + bt_mesh_adv_inst_type_add(BLE_MESH_BLE_ADV_INST, BLE_MESH_ADV_BLE); +#else /* CONFIG_BLE_MESH_SEPARATE_BLE_ADV_INSTANCE */ +#if CONFIG_BLE_MESH_SUPPORT_MULTI_ADV + bt_mesh_adv_inst_type_add(BLE_MESH_ADV_INST, BLE_MESH_ADV_BLE); +#endif /* CONFIG_BLE_MESH_SUPPORT_MULTI_ADV */ +#endif /* CONFIG_BLE_MESH_SEPARATE_BLE_ADV_INSTANCE */ +#endif /* CONFIG_BLE_MESH_USE_BLE_50 */ +} + +#if CONFIG_BLE_MESH_DEINIT +void bt_mesh_ble_adv_deinit(void) +{ + BT_DBG("BLEAdvDeinit"); + + for (int i = 0; i < ARRAY_SIZE(ble_adv_tx); i++) { + ble_adv_tx_reset(&ble_adv_tx[i], false); + } + + bt_mesh_unref_buf_from_pool(&ble_adv_buf_pool); + memset(ble_adv_pool, 0, sizeof(ble_adv_pool)); + +#if CONFIG_BLE_MESH_USE_BLE_50 && CONFIG_BLE_MESH_SEPARATE_BLE_ADV_INSTANCE + /* In other cases, ble_adv queue is an adv queue, + * so ble does not need to deinit separately */ + bt_mesh_adv_queue_deinit(p_ble_adv_queue); +#endif + bt_mesh_adv_type_deinit(BLE_MESH_ADV_BLE); + +#if CONFIG_BLE_MESH_USE_BLE_50 +#if CONFIG_BLE_MESH_SEPARATE_BLE_ADV_INSTANCE + bt_mesh_adv_inst_deinit(BLE_MESH_BLE_ADV_INST); + bt_mesh_adv_inst_type_rem(BLE_MESH_BLE_ADV_INST, BLE_MESH_ADV_BLE); +#else +#if CONFIG_BLE_MESH_SUPPORT_MULTI_ADV + bt_mesh_adv_inst_type_rem(BLE_MESH_ADV_INST, BLE_MESH_ADV_BLE); +#endif +#endif /* CONFIG_BLE_MESH_SEPARATE_BLE_ADV_INSTANCE */ +#endif /* CONFIG_BLE_MESH_USE_BLE_50 */ +} +#endif /* CONFIG_BLE_MESH_DEINIT */ diff --git a/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c b/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c index 2f3b3d351b86..6ae6b0fc23db 100644 --- a/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c +++ b/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c @@ -1010,7 +1010,7 @@ int bt_mesh_gatts_service_register(struct bt_mesh_gatt_service *svc) svc->attrs[i].handle = char_handle - 1; svc->attrs[i + 1].handle = char_handle; BT_DBG("Add characteristic, uuid 0x%04x, handle %d, perm %d, properties %d", - BLE_MESH_UUID_16(gatts_chrc->uuid)->val, char_handle, svc->attrs[i + 1].perm, gatts_chrc->properties); + BLE_MESH_UUID_16(gatts_chrc->uuid)->val, char_handle, svc->attrs[i + 1].perm, gatts_chrc->properties); break; } case BLE_MESH_UUID_GATT_CEP_VAL: @@ -1198,7 +1198,7 @@ uint16_t bt_mesh_gattc_get_service_uuid(struct bt_mesh_conn *conn) int bt_mesh_gattc_conn_create(const bt_mesh_addr_t *addr, uint16_t service_uuid) { - tBTA_BLE_CONN_PARAMS conn_1m_param = {0}; + tBTA_BLE_CONN_PARAMS conn_1m_param = {0}; uint8_t zero[6] = {0}; int i; diff --git a/components/bt/esp_ble_mesh/core/cfg_cli.c b/components/bt/esp_ble_mesh/core/cfg_cli.c index 3aedd3644b8a..c0968428d2df 100644 --- a/components/bt/esp_ble_mesh/core/cfg_cli.c +++ b/components/bt/esp_ble_mesh/core/cfg_cli.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -110,6 +110,8 @@ static void cfg_client_recv_status(struct bt_mesh_model *model, struct net_buf_simple buf = {0}; uint8_t evt_type = 0xFF; + BT_DBG("CfgClientRecvStatus"); + if (!model || !ctx) { BT_ERR("%s, Invalid parameter", __func__); return; @@ -125,6 +127,8 @@ static void cfg_client_recv_status(struct bt_mesh_model *model, if (!node) { BT_DBG("Unexpected Config Status 0x%04x", ctx->recv_op); } else { + BT_DBG("OpCode 0x%08lx RecvOp 0x%08lx", node->opcode, ctx->recv_op); + switch (node->opcode) { case OP_BEACON_GET: case OP_COMP_DATA_GET: @@ -230,9 +234,10 @@ static void comp_data_status(struct bt_mesh_model *model, { struct bt_mesh_cfg_comp_data_status status = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("CompDataStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status.page = net_buf_simple_pull_u8(buf); status.comp_data = bt_mesh_alloc_buf(buf->len); @@ -252,9 +257,10 @@ static void state_status_u8(struct bt_mesh_model *model, { uint8_t status = 0U; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("StateStatusU8"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status = net_buf_simple_pull_u8(buf); @@ -265,6 +271,8 @@ static void beacon_status(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { + BT_DBG("BeaconStatus"); + state_status_u8(model, ctx, buf); } @@ -272,6 +280,8 @@ static void ttl_status(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { + BT_DBG("TTLStatus"); + state_status_u8(model, ctx, buf); } @@ -279,6 +289,8 @@ static void friend_status(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { + BT_DBG("FrndStatus"); + state_status_u8(model, ctx, buf); } @@ -286,6 +298,8 @@ static void gatt_proxy_status(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { + BT_DBG("GattProxyStatus"); + state_status_u8(model, ctx, buf); } @@ -295,9 +309,10 @@ static void relay_status(struct bt_mesh_model *model, { struct bt_mesh_cfg_relay_status status = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("RelayStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status.relay = net_buf_simple_pull_u8(buf); status.retransmit = net_buf_simple_pull_u8(buf); @@ -311,9 +326,10 @@ static void net_key_status(struct bt_mesh_model *model, { struct bt_mesh_cfg_netkey_status status = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("NetKeyStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status.status = net_buf_simple_pull_u8(buf); status.net_idx = net_buf_simple_pull_le16(buf) & 0xfff; @@ -327,9 +343,10 @@ static void app_key_status(struct bt_mesh_model *model, { struct bt_mesh_cfg_appkey_status status = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("AppKeyStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status.status = net_buf_simple_pull_u8(buf); key_idx_unpack(buf, &status.net_idx, &status.app_idx); @@ -343,9 +360,10 @@ static void mod_app_status(struct bt_mesh_model *model, { struct bt_mesh_cfg_mod_app_status status = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("ModAppStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status.status = net_buf_simple_pull_u8(buf); status.elem_addr = net_buf_simple_pull_le16(buf); @@ -366,9 +384,10 @@ static void mod_pub_status(struct bt_mesh_model *model, { struct bt_mesh_cfg_mod_pub_status status = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("ModPubStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status.status = net_buf_simple_pull_u8(buf); status.elem_addr = net_buf_simple_pull_le16(buf); @@ -395,9 +414,10 @@ static void mod_sub_status(struct bt_mesh_model *model, { struct bt_mesh_cfg_mod_sub_status status = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("ModSubStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status.status = net_buf_simple_pull_u8(buf); status.elem_addr = net_buf_simple_pull_le16(buf); @@ -418,9 +438,10 @@ static void hb_sub_status(struct bt_mesh_model *model, { struct bt_mesh_cfg_hb_sub_status status = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("HbSubStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status.status = net_buf_simple_pull_u8(buf); status.src = net_buf_simple_pull_le16(buf); @@ -439,9 +460,10 @@ static void hb_pub_status(struct bt_mesh_model *model, { struct bt_mesh_cfg_hb_pub_status status = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("HbPubStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status.status = net_buf_simple_pull_u8(buf); status.dst = net_buf_simple_pull_le16(buf); @@ -458,9 +480,10 @@ static void node_reset_status(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("NodeResetStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); cfg_client_recv_status(model, ctx, NULL, 0); } @@ -471,9 +494,10 @@ static void mod_sub_list(struct bt_mesh_model *model, { struct bt_mesh_cfg_mod_sub_list list = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("ModSubList"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); list.status = net_buf_simple_pull_u8(buf); list.elem_addr = net_buf_simple_pull_le16(buf); @@ -500,9 +524,10 @@ static void net_key_list(struct bt_mesh_model *model, { struct bt_mesh_cfg_net_key_list list = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("NetKeyList"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); list.net_idx = bt_mesh_alloc_buf(buf->len); if (!list.net_idx) { @@ -520,9 +545,10 @@ static void app_key_list(struct bt_mesh_model *model, { struct bt_mesh_cfg_app_key_list list = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("AppKeyList"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); list.status = net_buf_simple_pull_u8(buf); list.net_idx = net_buf_simple_pull_le16(buf); @@ -542,9 +568,10 @@ static void node_id_status(struct bt_mesh_model *model, { struct bt_mesh_cfg_node_id_status status = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("NodeIDStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status.status = net_buf_simple_pull_u8(buf); status.net_idx = net_buf_simple_pull_le16(buf); @@ -559,9 +586,10 @@ static void mod_app_list(struct bt_mesh_model *model, { struct bt_mesh_cfg_mod_app_list list = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("ModAppList"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); list.status = net_buf_simple_pull_u8(buf); list.elem_addr = net_buf_simple_pull_le16(buf); @@ -588,9 +616,10 @@ static void kr_phase_status(struct bt_mesh_model *model, { struct bt_mesh_cfg_key_refresh_status status = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("KrPhaseStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status.status = net_buf_simple_pull_u8(buf); status.net_idx = net_buf_simple_pull_le16(buf); @@ -605,9 +634,10 @@ static void lpn_pollto_status(struct bt_mesh_model *model, { struct bt_mesh_cfg_lpn_pollto_status status = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("LPNPollToStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status.lpn_addr = net_buf_simple_pull_le16(buf); status.timeout = net_buf_simple_pull_u8(buf); @@ -621,6 +651,8 @@ static void net_trans_status(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { + BT_DBG("NetTransStatus"); + state_status_u8(model, ctx, buf); } @@ -656,6 +688,9 @@ static int send_msg_with_none(bt_mesh_client_common_param_t *param, uint32_t op) { BLE_MESH_MODEL_BUF_DEFINE(msg, op, 0); + BT_DBG("SendMsgWithNone"); + BT_DBG("Dst 0x%04x Op 0x%08lx", param->ctx.addr, op); + bt_mesh_model_msg_init(&msg, op); return bt_mesh_client_send_msg(param, &msg, true, timeout_handler); @@ -665,6 +700,9 @@ static int send_msg_with_u8(bt_mesh_client_common_param_t *param, uint32_t op, u { BLE_MESH_MODEL_BUF_DEFINE(msg, op, 1); + BT_DBG("SendMsgWithU8"); + BT_DBG("Dst 0x%04x Op 0x%08lx Val 0x%02x", param->ctx.addr, op, val); + bt_mesh_model_msg_init(&msg, op); net_buf_simple_add_u8(&msg, val); @@ -675,6 +713,9 @@ static int send_msg_with_le16(bt_mesh_client_common_param_t *param, uint32_t op, { BLE_MESH_MODEL_BUF_DEFINE(msg, op, 2); + BT_DBG("SendMsgWithLE16"); + BT_DBG("Dst 0x%04x Op 0x%08lx Val 0x%04x", param->ctx.addr, op, val); + bt_mesh_model_msg_init(&msg, op); net_buf_simple_add_le16(&msg, val); @@ -683,55 +724,76 @@ static int send_msg_with_le16(bt_mesh_client_common_param_t *param, uint32_t op, int bt_mesh_cfg_comp_data_get(bt_mesh_client_common_param_t *param, uint8_t page) { + BT_DBG("CompDataGet, Page %u", page); + return send_msg_with_u8(param, OP_COMP_DATA_GET, page); } int bt_mesh_cfg_beacon_get(bt_mesh_client_common_param_t *param) { + BT_DBG("BeaconGet"); + return send_msg_with_none(param, OP_BEACON_GET); } int bt_mesh_cfg_beacon_set(bt_mesh_client_common_param_t *param, uint8_t val) { + BT_DBG("BeaconSet, Val 0x%02x", val); + if (val > 0x01) { BT_ERR("Invalid beacon state 0x%02x", val); return -EINVAL; } + return send_msg_with_u8(param, OP_BEACON_SET, val); } int bt_mesh_cfg_ttl_get(bt_mesh_client_common_param_t *param) { + BT_DBG("TTLGet"); + return send_msg_with_none(param, OP_DEFAULT_TTL_GET); } int bt_mesh_cfg_ttl_set(bt_mesh_client_common_param_t *param, uint8_t val) { + BT_DBG("TTLSet, Val 0x%02x", val); + return send_msg_with_u8(param, OP_DEFAULT_TTL_SET, val); } int bt_mesh_cfg_friend_get(bt_mesh_client_common_param_t *param) { + BT_DBG("FrndGet"); + return send_msg_with_none(param, OP_FRIEND_GET); } int bt_mesh_cfg_friend_set(bt_mesh_client_common_param_t *param, uint8_t val) { + BT_DBG("FrndSet, Val 0x%02x", val); + return send_msg_with_u8(param, OP_FRIEND_SET, val); } int bt_mesh_cfg_gatt_proxy_get(bt_mesh_client_common_param_t *param) { + BT_DBG("GattProxyGet"); + return send_msg_with_none(param, OP_GATT_PROXY_GET); } int bt_mesh_cfg_gatt_proxy_set(bt_mesh_client_common_param_t *param, uint8_t val) { + BT_DBG("GattProxySet, Val 0x%02x", val); + return send_msg_with_u8(param, OP_GATT_PROXY_SET, val); } int bt_mesh_cfg_relay_get(bt_mesh_client_common_param_t *param) { + BT_DBG("RelayGet"); + return send_msg_with_none(param, OP_RELAY_GET); } @@ -740,6 +802,8 @@ int bt_mesh_cfg_relay_set(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_RELAY_SET, 2); + BT_DBG("RelaySet, Relay 0x%02x Retransmit 0x%02x", relay, retransmit); + bt_mesh_model_msg_init(&msg, OP_RELAY_SET); net_buf_simple_add_u8(&msg, relay); net_buf_simple_add_u8(&msg, retransmit); @@ -752,11 +816,15 @@ int bt_mesh_cfg_net_key_add(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_NET_KEY_ADD, 18); + BT_DBG("NetKeyAdd"); + if (!net_key) { BT_ERR("Invalid NetKey"); return -EINVAL; } + BT_DBG("NetIdx 0x%04x NetKey %s", net_idx, bt_hex(net_key, 16)); + bt_mesh_model_msg_init(&msg, OP_NET_KEY_ADD); net_buf_simple_add_le16(&msg, net_idx); net_buf_simple_add_mem(&msg, net_key, 16); @@ -770,11 +838,16 @@ int bt_mesh_cfg_app_key_add(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_APP_KEY_ADD, 19); + BT_DBG("AppKeyAdd"); + if (!app_key) { BT_ERR("Invalid AppKey"); return -EINVAL; } + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x AppKey %s", + net_idx, app_idx, bt_hex(app_key, 16)); + bt_mesh_model_msg_init(&msg, OP_APP_KEY_ADD); key_idx_pack(&msg, net_idx, app_idx); net_buf_simple_add_mem(&msg, app_key, 16); @@ -788,6 +861,10 @@ int bt_mesh_cfg_mod_app_bind(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_MOD_APP_BIND, 8); + BT_DBG("ModAppBind"); + BT_DBG("ElemAddr 0x%04x AppIdx 0x%04x ModID 0x%04x CID 0x%04x", + elem_addr, app_idx, mod_id, cid); + bt_mesh_model_msg_init(&msg, OP_MOD_APP_BIND); net_buf_simple_add_le16(&msg, elem_addr); net_buf_simple_add_le16(&msg, app_idx); @@ -805,6 +882,10 @@ static int mod_sub(bt_mesh_client_common_param_t *param, uint32_t op, { BLE_MESH_MODEL_BUF_DEFINE(msg, op, 8); + BT_DBG("ModSub"); + BT_DBG("ElemAddr 0x%04x SubAddr 0x%04x ModID 0x%04x CID 0x%04x", + elem_addr, sub_addr, mod_id, cid); + bt_mesh_model_msg_init(&msg, op); net_buf_simple_add_le16(&msg, elem_addr); net_buf_simple_add_le16(&msg, sub_addr); @@ -820,6 +901,8 @@ int bt_mesh_cfg_mod_sub_add(bt_mesh_client_common_param_t *param, uint16_t elem_addr, uint16_t sub_addr, uint16_t mod_id, uint16_t cid) { + BT_DBG("ModSubAdd"); + return mod_sub(param, OP_MOD_SUB_ADD, elem_addr, sub_addr, mod_id, cid); } @@ -827,6 +910,8 @@ int bt_mesh_cfg_mod_sub_del(bt_mesh_client_common_param_t *param, uint16_t elem_addr, uint16_t sub_addr, uint16_t mod_id, uint16_t cid) { + BT_DBG("ModSubDel"); + return mod_sub(param, OP_MOD_SUB_DEL, elem_addr, sub_addr, mod_id, cid); } @@ -834,6 +919,8 @@ int bt_mesh_cfg_mod_sub_overwrite(bt_mesh_client_common_param_t *param, uint16_t elem_addr, uint16_t sub_addr, uint16_t mod_id, uint16_t cid) { + BT_DBG("ModSubOverwrite"); + return mod_sub(param, OP_MOD_SUB_OVERWRITE, elem_addr, sub_addr, mod_id, cid); } @@ -843,13 +930,15 @@ static int mod_sub_va(bt_mesh_client_common_param_t *param, uint32_t op, { BLE_MESH_MODEL_BUF_DEFINE(msg, op, 22); + BT_DBG("ModSubVa"); + if (!label) { BT_ERR("Invalid label uuid"); return -EINVAL; } - BT_DBG("elem_addr 0x%04x label %s", elem_addr, bt_hex(label, 16)); - BT_DBG("mod_id 0x%04x cid 0x%04x", mod_id, cid); + BT_DBG("ElemAddr 0x%04x ModID 0x%04x CID 0x%04x", elem_addr, mod_id, cid); + BT_DBG("Label %s", bt_hex(label, 16)); bt_mesh_model_msg_init(&msg, op); net_buf_simple_add_le16(&msg, elem_addr); @@ -866,6 +955,8 @@ int bt_mesh_cfg_mod_sub_va_add(bt_mesh_client_common_param_t *param, uint16_t elem_addr, const uint8_t label[16], uint16_t mod_id, uint16_t cid) { + BT_DBG("ModSubVaAdd"); + return mod_sub_va(param, OP_MOD_SUB_VA_ADD, elem_addr, label, mod_id, cid); } @@ -873,6 +964,8 @@ int bt_mesh_cfg_mod_sub_va_del(bt_mesh_client_common_param_t *param, uint16_t elem_addr, const uint8_t label[16], uint16_t mod_id, uint16_t cid) { + BT_DBG("ModSubVaDel"); + return mod_sub_va(param, OP_MOD_SUB_VA_DEL, elem_addr, label, mod_id, cid); } @@ -880,6 +973,8 @@ int bt_mesh_cfg_mod_sub_va_overwrite(bt_mesh_client_common_param_t *param, uint16_t elem_addr, const uint8_t label[16], uint16_t mod_id, uint16_t cid) { + BT_DBG("ModSubVaOverwrite"); + return mod_sub_va(param, OP_MOD_SUB_VA_OVERWRITE, elem_addr, label, mod_id, cid); } @@ -888,6 +983,9 @@ int bt_mesh_cfg_mod_pub_get(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_MOD_PUB_GET, 6); + BT_DBG("ModPubGet"); + BT_DBG("ElemAddr 0x%04x ModID 0x%04x CID 0x%04x", elem_addr, mod_id, cid); + bt_mesh_model_msg_init(&msg, OP_MOD_PUB_GET); net_buf_simple_add_le16(&msg, elem_addr); if (cid != BLE_MESH_CID_NVAL) { @@ -904,11 +1002,17 @@ int bt_mesh_cfg_mod_pub_set(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_MOD_PUB_SET, 13); + BT_DBG("ModPubSet"); + BT_DBG("ElemAddr 0x%04x ModID 0x%04x CID 0x%04x", elem_addr, mod_id, cid); + if (!pub) { BT_ERR("Invalid model pub set"); return -EINVAL; } + BT_DBG("Addr 0x%04x AppIdx 0x%04x TTL %u Period 0x%02x Transmit 0x%02x", + pub->addr, pub->app_idx, pub->ttl, pub->period, pub->transmit); + bt_mesh_model_msg_init(&msg, OP_MOD_PUB_SET); net_buf_simple_add_le16(&msg, elem_addr); net_buf_simple_add_le16(&msg, pub->addr); @@ -929,11 +1033,15 @@ int bt_mesh_cfg_hb_sub_set(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_HEARTBEAT_SUB_SET, 5); + BT_DBG("HbSubSet"); + if (!sub) { BT_ERR("Invalid heartbeat sub set"); return -EINVAL; } + BT_DBG("Src 0x%04x Dst 0x%04x Period 0x%02x", sub->src, sub->dst, sub->period); + bt_mesh_model_msg_init(&msg, OP_HEARTBEAT_SUB_SET); net_buf_simple_add_le16(&msg, sub->src); net_buf_simple_add_le16(&msg, sub->dst); @@ -944,6 +1052,8 @@ int bt_mesh_cfg_hb_sub_set(bt_mesh_client_common_param_t *param, int bt_mesh_cfg_hb_sub_get(bt_mesh_client_common_param_t *param) { + BT_DBG("HbSubGet"); + return send_msg_with_none(param, OP_HEARTBEAT_SUB_GET); } @@ -952,11 +1062,16 @@ int bt_mesh_cfg_hb_pub_set(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_HEARTBEAT_PUB_SET, 9); + BT_DBG("HbPubSet"); + if (!pub) { BT_ERR("Invalid heartbeat pub set"); return -EINVAL; } + BT_DBG("Dst 0x%04x Count 0x%02x Period 0x%02x TTL %u Feat 0x%04x NetIdx 0x%04x", + pub->dst, pub->count, pub->period, pub->ttl, pub->feat, pub->net_idx); + bt_mesh_model_msg_init(&msg, OP_HEARTBEAT_PUB_SET); net_buf_simple_add_le16(&msg, pub->dst); net_buf_simple_add_u8(&msg, pub->count); @@ -970,11 +1085,15 @@ int bt_mesh_cfg_hb_pub_set(bt_mesh_client_common_param_t *param, int bt_mesh_cfg_hb_pub_get(bt_mesh_client_common_param_t *param) { + BT_DBG("HbPubGet"); + return send_msg_with_none(param, OP_HEARTBEAT_PUB_GET); } int bt_mesh_cfg_node_reset(bt_mesh_client_common_param_t *param) { + BT_DBG("NodeReset"); + return send_msg_with_none(param, OP_NODE_RESET); } @@ -985,11 +1104,18 @@ int bt_mesh_cfg_mod_pub_va_set(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_MOD_PUB_VA_SET, 27); + BT_DBG("ModPubVaSet"); + BT_DBG("ElemAddr 0x%04x ModID 0x%04x CID 0x%04x", elem_addr, mod_id, cid); + if (!label || !pub) { BT_ERR("%s, Invalid parameter", __func__); return -EINVAL; } + BT_DBG("Label %s", bt_hex(label, 16)); + BT_DBG("AppIdx 0x%04x TTL %u Period 0x%02x Transmit 0x%02x", + pub->app_idx, pub->ttl, pub->period, pub->transmit); + bt_mesh_model_msg_init(&msg, OP_MOD_PUB_VA_SET); net_buf_simple_add_le16(&msg, elem_addr); net_buf_simple_add_mem(&msg, label, 16); @@ -1010,6 +1136,9 @@ int bt_mesh_cfg_mod_sub_del_all(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_MOD_SUB_DEL_ALL, 6); + BT_DBG("ModSubDelAll"); + BT_DBG("ElemAddr 0x%04x ModID 0x%04x CID 0x%04x", elem_addr, mod_id, cid); + bt_mesh_model_msg_init(&msg, OP_MOD_SUB_DEL_ALL); net_buf_simple_add_le16(&msg, elem_addr); if (cid != BLE_MESH_CID_NVAL) { @@ -1038,12 +1167,18 @@ static int mod_sub_get(bt_mesh_client_common_param_t *param, uint32_t op, int bt_mesh_cfg_mod_sub_get(bt_mesh_client_common_param_t *param, uint16_t elem_addr, uint16_t mod_id) { + BT_DBG("ModSubGet"); + BT_DBG("ElemAddr 0x%04x ModID 0x%04x", elem_addr, mod_id); + return mod_sub_get(param, OP_MOD_SUB_GET, elem_addr, mod_id, BLE_MESH_CID_NVAL); } int bt_mesh_cfg_mod_sub_get_vnd(bt_mesh_client_common_param_t *param, uint16_t elem_addr, uint16_t mod_id, uint16_t cid) { + BT_DBG("ModSubGetVnd"); + BT_DBG("ElemAddr 0x%04x ModID 0x%04x CID 0x%04x", elem_addr, mod_id, cid); + if (cid == BLE_MESH_CID_NVAL) { BT_ERR("Invalid company id"); return -EINVAL; @@ -1056,11 +1191,15 @@ int bt_mesh_cfg_net_key_update(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_NET_KEY_UPDATE, 18); + BT_DBG("NetKeyUpdate"); + if (!net_key) { BT_ERR("Invalid NetKey"); return -EINVAL; } + BT_DBG("NetIdx 0x%04x NetKey %s", net_idx, bt_hex(net_key, 16)); + bt_mesh_model_msg_init(&msg, OP_NET_KEY_UPDATE); net_buf_simple_add_le16(&msg, net_idx); net_buf_simple_add_mem(&msg, net_key, 16); @@ -1070,11 +1209,15 @@ int bt_mesh_cfg_net_key_update(bt_mesh_client_common_param_t *param, int bt_mesh_cfg_net_key_delete(bt_mesh_client_common_param_t *param, uint16_t net_idx) { + BT_DBG("NetKeyDelete, NetIdx 0x%04x", net_idx); + return send_msg_with_le16(param, OP_NET_KEY_DEL, net_idx); } int bt_mesh_cfg_net_key_get(bt_mesh_client_common_param_t *param) { + BT_DBG("NetKeyGet"); + return send_msg_with_none(param, OP_NET_KEY_GET); } @@ -1084,11 +1227,16 @@ int bt_mesh_cfg_app_key_update(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_APP_KEY_UPDATE, 19); + BT_DBG("AppKeyUpdate"); + if (!app_key) { BT_ERR("Invalid AppKey"); return -EINVAL; } + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x AppKey %s", + net_idx, app_idx, bt_hex(app_key, 16)); + bt_mesh_model_msg_init(&msg, OP_APP_KEY_UPDATE); key_idx_pack(&msg, net_idx, app_idx); net_buf_simple_add_mem(&msg, app_key, 16); @@ -1101,6 +1249,8 @@ int bt_mesh_cfg_app_key_delete(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_APP_KEY_DEL, 3); + BT_DBG("AppKeyDelete, NetIdx 0x%04x AppIdx 0x%04x", net_idx, app_idx); + bt_mesh_model_msg_init(&msg, OP_APP_KEY_DEL); key_idx_pack(&msg, net_idx, app_idx); @@ -1109,11 +1259,15 @@ int bt_mesh_cfg_app_key_delete(bt_mesh_client_common_param_t *param, int bt_mesh_cfg_app_key_get(bt_mesh_client_common_param_t *param, uint16_t net_idx) { + BT_DBG("AppKeyGet, NetIdx 0x%04x", net_idx); + return send_msg_with_le16(param, OP_APP_KEY_GET, net_idx); } int bt_mesh_cfg_node_identity_get(bt_mesh_client_common_param_t *param, uint16_t net_idx) { + BT_DBG("NodeIdentityGet, NetIdx 0x%04x", net_idx); + return send_msg_with_le16(param, OP_NODE_IDENTITY_GET, net_idx); } @@ -1122,6 +1276,8 @@ int bt_mesh_cfg_node_identity_set(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_NODE_IDENTITY_SET, 3); + BT_DBG("NodeIdentitySet, NetIdx 0x%04x Identity 0x%02x", net_idx, identity); + if (identity > 0x02) { BT_ERR("Invalid node identity 0x%02x", identity); return -EINVAL; @@ -1140,6 +1296,10 @@ int bt_mesh_cfg_mod_app_unbind(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_MOD_APP_UNBIND, 8); + BT_DBG("ModAppUnbind"); + BT_DBG("ElemAddr 0x%04x AppIdx 0x%04x ModID 0x%04x CID 0x%04x", + elem_addr, app_idx, mod_id, cid); + bt_mesh_model_msg_init(&msg, OP_MOD_APP_UNBIND); net_buf_simple_add_le16(&msg, elem_addr); net_buf_simple_add_le16(&msg, app_idx); @@ -1169,21 +1329,29 @@ static int mod_app_get(bt_mesh_client_common_param_t *param, uint32_t op, int bt_mesh_cfg_mod_app_get(bt_mesh_client_common_param_t *param, uint16_t elem_addr, uint16_t mod_id) { + BT_DBG("ModAppGet, ElemAddr 0x%04x ModID 0x%04x", elem_addr, mod_id); + return mod_app_get(param, OP_SIG_MOD_APP_GET, elem_addr, mod_id, BLE_MESH_CID_NVAL); } int bt_mesh_cfg_mod_app_get_vnd(bt_mesh_client_common_param_t *param, uint16_t elem_addr, uint16_t mod_id, uint16_t cid) { + BT_DBG("ModAppGetVnd"); + BT_DBG("ElemAddr 0x%04x ModID 0x%04x CID 0x%04x", elem_addr, mod_id, cid); + if (cid == BLE_MESH_CID_NVAL) { BT_ERR("Invalid company id"); return -EINVAL; } + return mod_app_get(param, OP_VND_MOD_APP_GET, elem_addr, mod_id, cid); } int bt_mesh_cfg_kr_phase_get(bt_mesh_client_common_param_t *param, uint16_t net_idx) { + BT_DBG("KrPhaseGet, NetIdx 0x%04x", net_idx); + return send_msg_with_le16(param, OP_KRP_GET, net_idx); } @@ -1192,6 +1360,8 @@ int bt_mesh_cfg_kr_phase_set(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_KRP_SET, 3); + BT_DBG("KrPhaseSet, NetIdx 0x%04x Transition 0x%02x", net_idx, transition); + if (transition > 0x03) { BT_ERR("Invalid kr phase transition 0x%02x", transition); return -EINVAL; @@ -1206,16 +1376,22 @@ int bt_mesh_cfg_kr_phase_set(bt_mesh_client_common_param_t *param, int bt_mesh_cfg_lpn_timeout_get(bt_mesh_client_common_param_t *param, uint16_t lpn_addr) { + BT_DBG("LPNTimeoutGet, LPN 0x%04x", lpn_addr); + return send_msg_with_le16(param, OP_LPN_TIMEOUT_GET, lpn_addr); } int bt_mesh_cfg_net_transmit_get(bt_mesh_client_common_param_t *param) { + BT_DBG("NetTransmitGet"); + return send_msg_with_none(param, OP_NET_TRANSMIT_GET); } int bt_mesh_cfg_net_transmit_set(bt_mesh_client_common_param_t *param, uint8_t transmit) { + BT_DBG("NetTransmitSet, Transmit 0x%02x", transmit); + return send_msg_with_u8(param, OP_NET_TRANSMIT_SET, transmit); } @@ -1224,6 +1400,8 @@ static int cfg_cli_init(struct bt_mesh_model *model) config_internal_data_t *internal = NULL; bt_mesh_config_client_t *client = NULL; + BT_DBG("CfgCliInit"); + if (!model) { BT_ERR("Invalid Configuration Client model"); return -EINVAL; @@ -1271,6 +1449,8 @@ static int cfg_cli_deinit(struct bt_mesh_model *model) { bt_mesh_config_client_t *client = NULL; + BT_DBG("CfgCliDeinit"); + if (!model) { BT_ERR("Invalid Configuration Client model"); return -EINVAL; diff --git a/components/bt/esp_ble_mesh/core/cfg_srv.c b/components/bt/esp_ble_mesh/core/cfg_srv.c index fe605939a549..d8be5f042465 100644 --- a/components/bt/esp_ble_mesh/core/cfg_srv.c +++ b/components/bt/esp_ble_mesh/core/cfg_srv.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -32,7 +32,7 @@ #if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" -#endif +#endif /* CONFIG_BLE_MESH_V11_SUPPORT */ #define DEFAULT_TTL 7 @@ -66,6 +66,9 @@ static uint8_t bt_mesh_comp_page_check(uint8_t page, bool largest) static inline uint16_t get_comp_elem_size(struct bt_mesh_elem *elem) { + BT_DBG("GetCompElemSize, ModelCount %u VndModelCount %u", + elem->model_count, elem->vnd_model_count); + return (4 + elem->model_count * 2 + elem->vnd_model_count * 4); } @@ -77,6 +80,8 @@ static uint16_t get_comp_data_size(const struct bt_mesh_comp *comp) size += get_comp_elem_size(&(comp->elem[i])); } + BT_DBG("GetCompDataSize, Size %u", size); + return size; } @@ -119,6 +124,7 @@ static void get_comp_data(struct net_buf_simple *buf, */ if (full_element && net_buf_simple_tailroom(buf) < get_comp_elem_size(elem)) { + BT_WARN("NoRoomForElementModelList"); return; } @@ -137,6 +143,8 @@ static void get_comp_data(struct net_buf_simple *buf, net_buf_simple_add_le16(buf, model->vnd.id); } } + + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); } static int fetch_comp_data(struct net_buf_simple *buf, @@ -155,7 +163,7 @@ static int fetch_comp_data(struct net_buf_simple *buf, if (net_buf_simple_tailroom(buf) < 10 || size - offset > net_buf_simple_tailroom(buf)) { BT_ERR("Too small buffer for comp data %d, %d, expected %d", - page, buf->size, size - offset); + page, buf->size, size - offset); return -EINVAL; } @@ -183,6 +191,9 @@ static int bt_mesh_get_comp_data(struct net_buf_simple *buf, uint8_t page, uint16_t offset, bool full_element) { + BT_DBG("FetchCompData, Page %u Offset %u FullElement %u", + page, offset, full_element); + if (page == 0) { return fetch_comp_data(buf, comp_0, page, offset, full_element); } @@ -199,9 +210,10 @@ static void comp_data_get(struct bt_mesh_model *model, struct net_buf_simple *sdu = NULL; uint8_t page = 0U; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("CompDataGet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); /* TODO: * @@ -268,14 +280,17 @@ static void comp_data_get(struct bt_mesh_model *model, } static struct bt_mesh_model *get_model(struct bt_mesh_elem *elem, - struct net_buf_simple *buf, bool *vnd) + struct net_buf_simple *buf, + bool *vnd) { uint16_t company = 0U, id = 0U; + BT_DBG("GetModel, Len %u", buf->len); + if (buf->len < 4) { id = net_buf_simple_pull_le16(buf); - BT_DBG("ID 0x%04x addr 0x%04x", id, elem->addr); + BT_DBG("ID 0x%04x ElemAddr 0x%04x", id, elem->addr); *vnd = false; @@ -285,42 +300,49 @@ static struct bt_mesh_model *get_model(struct bt_mesh_elem *elem, company = net_buf_simple_pull_le16(buf); id = net_buf_simple_pull_le16(buf); - BT_DBG("Company 0x%04x ID 0x%04x addr 0x%04x", company, id, - elem->addr); + BT_DBG("CID 0x%04x ID 0x%04x Addr 0x%04x", company, id, elem->addr); *vnd = true; return bt_mesh_model_find_vnd(elem, company, id); } -static bool mod_pub_app_key_bound(struct bt_mesh_model *model, - uint16_t app_idx) +static bool mod_pub_app_key_bound(struct bt_mesh_model *model, uint16_t app_idx) { int i; + BT_DBG("ModPubAppKeyBound, AppIdx 0x%04x", app_idx); + for (i = 0; i < ARRAY_SIZE(model->keys); i++) { if (model->keys[i] == app_idx) { return true; } } - BT_ERR("AppKey(0x%02x) not bound to this model", app_idx); + BT_ERR("AppKeyNotBound, AppIdx 0x%04x", app_idx); return false; } static uint8_t _mod_pub_set(struct bt_mesh_model *model, uint16_t pub_addr, - uint16_t app_idx, uint8_t cred_flag, uint8_t ttl, uint8_t period, - uint8_t retransmit, bool store) + uint16_t app_idx, uint8_t cred_flag, uint8_t ttl, + uint8_t period, uint8_t retransmit, bool store) { + BT_DBG("_ModPubSet"); + BT_DBG("Addr 0x%04x AppIdx 0x%04x TTL %u Period 0x%02x Retransmit 0x%02x Store %u", + pub_addr, app_idx, ttl, period, retransmit, store); + if (!model->pub) { + BT_DBG("StatusNvalPubParam"); return STATUS_NVAL_PUB_PARAM; } if (!IS_ENABLED(CONFIG_BLE_MESH_LOW_POWER) && cred_flag) { + BT_DBG("StatusFeatNotSupp"); return STATUS_FEAT_NOT_SUPP; } if (!model->pub->update && period) { + BT_DBG("StatusNvalPubParam"); return STATUS_NVAL_PUB_PARAM; } @@ -353,6 +375,7 @@ static uint8_t _mod_pub_set(struct bt_mesh_model *model, uint16_t pub_addr, */ if (!bt_mesh_app_key_get(app_idx) || !mod_pub_app_key_bound(model, app_idx)) { + BT_DBG("StatusInvalidAppKey"); return STATUS_INVALID_APPKEY; } @@ -367,7 +390,8 @@ static uint8_t _mod_pub_set(struct bt_mesh_model *model, uint16_t pub_addr, int32_t period_ms; period_ms = bt_mesh_model_pub_period_get(model); - BT_DBG("period %u ms", period_ms); + + BT_DBG("PubPeriod %ld", period_ms); if (period_ms) { k_delayed_work_submit(&model->pub->timer, period_ms); @@ -387,9 +411,10 @@ static uint8_t mod_bind(struct bt_mesh_model *model, uint16_t key_idx) { int i; - BT_DBG("model %p key_idx 0x%03x", model, key_idx); + BT_DBG("ModBind, KeyIdx 0x%04x", key_idx); if (!bt_mesh_app_key_get(key_idx)) { + BT_DBG("StatusInvalidAppKey"); return STATUS_INVALID_APPKEY; } @@ -412,6 +437,7 @@ static uint8_t mod_bind(struct bt_mesh_model *model, uint16_t key_idx) } } + BT_DBG("StatusInsuffResources"); return STATUS_INSUFF_RESOURCES; } @@ -419,9 +445,10 @@ static uint8_t mod_unbind(struct bt_mesh_model *model, uint16_t key_idx, bool st { int i; - BT_DBG("model %p key_idx 0x%03x store %u", model, key_idx, store); + BT_DBG("ModUnbind, KeyIdx 0x%04x Store %u", key_idx, store); if (!bt_mesh_app_key_get(key_idx)) { + BT_DBG("StatusInvalidAppKey"); return STATUS_INVALID_APPKEY; } @@ -449,6 +476,8 @@ struct bt_mesh_app_key *bt_mesh_app_key_alloc(uint16_t app_idx) { int i; + BT_DBG("AppKeyAlloc, AppIdx 0x%04x", app_idx); + for (i = 0; i < ARRAY_SIZE(bt_mesh.app_keys); i++) { struct bt_mesh_app_key *key = &bt_mesh.app_keys[i]; @@ -457,31 +486,36 @@ struct bt_mesh_app_key *bt_mesh_app_key_alloc(uint16_t app_idx) } } + BT_ERR("AppKeyFull"); return NULL; } -static uint8_t app_key_set(uint16_t net_idx, uint16_t app_idx, const uint8_t val[16], - bool update) +static uint8_t app_key_set(uint16_t net_idx, uint16_t app_idx, + const uint8_t val[16], bool update) { struct bt_mesh_app_keys *keys = NULL; struct bt_mesh_app_key *key = NULL; struct bt_mesh_subnet *sub = NULL; - BT_DBG("net_idx 0x%04x app_idx %04x update %u val %s", + BT_DBG("AppKeySet"); + BT_DBG("NetIdx 0x%04x AppIdx %04x Update %u Val %s", net_idx, app_idx, update, bt_hex(val, 16)); sub = bt_mesh_subnet_get(net_idx); if (!sub) { + BT_DBG("StatusInvalidNetKey"); return STATUS_INVALID_NETKEY; } key = bt_mesh_app_key_get(app_idx); if (update) { if (!key) { + BT_DBG("StatusInvalidAppKey"); return STATUS_INVALID_APPKEY; } if (key->net_idx != net_idx) { + BT_DBG("StatusInvalidBinding"); return STATUS_INVALID_BINDING; } @@ -493,11 +527,13 @@ static uint8_t app_key_set(uint16_t net_idx, uint16_t app_idx, const uint8_t val * the AppKey value is different. */ if (sub->kr_phase != BLE_MESH_KR_PHASE_1) { + BT_DBG("StatusCannotUpdate"); return STATUS_CANNOT_UPDATE; } if (key->updated) { if (memcmp(keys->val, val, 16)) { + BT_DBG("StatusCannotUpdate"); return STATUS_CANNOT_UPDATE; } @@ -513,14 +549,17 @@ static uint8_t app_key_set(uint16_t net_idx, uint16_t app_idx, const uint8_t val } if (key->net_idx == net_idx) { + BT_DBG("StatusIdxAlreadyStored"); return STATUS_IDX_ALREADY_STORED; } + BT_DBG("StatusInvalidNetKey"); return STATUS_INVALID_NETKEY; } key = bt_mesh_app_key_alloc(app_idx); if (!key) { + BT_DBG("StatusInsuffResources"); return STATUS_INSUFF_RESOURCES; } @@ -532,17 +571,15 @@ static uint8_t app_key_set(uint16_t net_idx, uint16_t app_idx, const uint8_t val key->updated = false; } + BT_DBG("StatusStorageFail"); return STATUS_STORAGE_FAIL; } - BT_DBG("app_idx 0x%04x AID 0x%02x", app_idx, keys->id); - key->net_idx = net_idx; key->app_idx = app_idx; memcpy(keys->val, val, 16); if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { - BT_DBG("Storing AppKey persistently"); bt_mesh_store_app_key(key); } @@ -559,14 +596,13 @@ static void app_key_add(struct bt_mesh_model *model, key_idx_unpack(buf, &key_net_idx, &key_app_idx); - BT_DBG("AppIdx 0x%04x NetIdx 0x%04x", key_app_idx, key_net_idx); + BT_DBG("AppKeyAdd, NetIdx 0x%04x AppIdx 0x%04x", key_net_idx, key_app_idx); bt_mesh_model_msg_init(&msg, OP_APP_KEY_STATUS); status = app_key_set(key_net_idx, key_app_idx, buf->data, false); - BT_DBG("status 0x%02x", status); - net_buf_simple_add_u8(&msg, status); + net_buf_simple_add_u8(&msg, status); key_idx_pack(&msg, key_net_idx, key_app_idx); if (bt_mesh_model_send(model, ctx, &msg, NULL, NULL)) { @@ -594,14 +630,13 @@ static void app_key_update(struct bt_mesh_model *model, key_idx_unpack(buf, &key_net_idx, &key_app_idx); - BT_DBG("AppIdx 0x%04x NetIdx 0x%04x", key_app_idx, key_net_idx); + BT_DBG("AppKeyUpdate, NetIdx 0x%04x AppIdx 0x%04x", key_net_idx, key_app_idx); bt_mesh_model_msg_init(&msg, OP_APP_KEY_STATUS); status = app_key_set(key_net_idx, key_app_idx, buf->data, true); - BT_DBG("status 0x%02x", status); - net_buf_simple_add_u8(&msg, status); + net_buf_simple_add_u8(&msg, status); key_idx_pack(&msg, key_net_idx, key_app_idx); if (bt_mesh_model_send(model, ctx, &msg, NULL, NULL)) { @@ -628,6 +663,8 @@ static void _mod_unbind(struct bt_mesh_model *mod, struct bt_mesh_elem *elem, { struct unbind_data *data = user_data; + BT_DBG("_ModUnbind, Vnd %u Primary %u", vnd, primary); + mod_unbind(mod, data->app_idx, data->store); } @@ -635,7 +672,7 @@ void bt_mesh_app_key_del(struct bt_mesh_app_key *key, bool store) { struct unbind_data data = { .app_idx = key->app_idx, .store = store }; - BT_DBG("AppIdx 0x%03x store %u", key->app_idx, store); + BT_DBG("AppKeyDel, AppIdx 0x%04x Store %u", key->app_idx, store); bt_mesh_model_foreach(_mod_unbind, &data); @@ -658,9 +695,10 @@ static void app_key_del(struct bt_mesh_model *model, key_idx_unpack(buf, &key_net_idx, &key_app_idx); - BT_DBG("AppIdx 0x%04x NetIdx 0x%04x", key_app_idx, key_net_idx); + BT_DBG("AppkeyDel, NetIdx 0x%04x AppIdx 0x%04x", key_net_idx, key_app_idx); if (!bt_mesh_subnet_get(key_net_idx)) { + BT_DBG("StatusInvalidNetKey"); status = STATUS_INVALID_NETKEY; goto send_status; } @@ -675,11 +713,13 @@ static void app_key_del(struct bt_mesh_model *model, } if (key->net_idx != key_net_idx) { + BT_DBG("StatusInvalidBinding"); status = STATUS_INVALID_BINDING; goto send_status; } bt_mesh_app_key_del(key, true); + status = STATUS_SUCCESS; send_status: @@ -703,7 +743,7 @@ static void app_key_del(struct bt_mesh_model *model, } /* Index list length: 3 bytes for every pair and 2 bytes for an odd idx */ -#define IDX_LEN(num) (((num) / 2) * 3 + ((num) % 2) * 2) +#define IDX_LEN(num) (((num) / 2) * 3 + ((num) % 2) * 2) static void app_key_get(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, @@ -714,17 +754,20 @@ static void app_key_get(struct bt_mesh_model *model, uint16_t get_idx = 0U, i = 0U, prev = 0U; uint8_t status = 0U; + BT_DBG("AppkeyGet"); + get_idx = net_buf_simple_pull_le16(buf); if (get_idx > 0xfff) { BT_ERR("Invalid NetKeyIndex 0x%04x", get_idx); return; } - BT_DBG("idx 0x%04x", get_idx); + BT_DBG("GetIdx 0x%04x", get_idx); bt_mesh_model_msg_init(&msg, OP_APP_KEY_LIST); if (!bt_mesh_subnet_get(get_idx)) { + BT_DBG("StatusInvalidNetKey"); status = STATUS_INVALID_NETKEY; } else { status = STATUS_SUCCESS; @@ -738,6 +781,7 @@ static void app_key_get(struct bt_mesh_model *model, } prev = BLE_MESH_KEY_UNUSED; + for (i = 0U; i < ARRAY_SIZE(bt_mesh.app_keys); i++) { struct bt_mesh_app_key *key = &bt_mesh.app_keys[i]; @@ -770,9 +814,10 @@ static void beacon_get(struct bt_mesh_model *model, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_BEACON_STATUS, 1); - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("BeaconGet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); bt_mesh_model_msg_init(&msg, OP_BEACON_STATUS); net_buf_simple_add_u8(&msg, bt_mesh_secure_beacon_get()); @@ -789,9 +834,10 @@ static void beacon_set(struct bt_mesh_model *model, BLE_MESH_MODEL_BUF_DEFINE(msg, OP_BEACON_STATUS, 1); struct bt_mesh_cfg_srv *cfg = model->user_data; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("BeaconSet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); if (!cfg) { BT_WARN("No Configuration Server context available"); @@ -828,9 +874,10 @@ static void default_ttl_get(struct bt_mesh_model *model, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_DEFAULT_TTL_STATUS, 1); - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("DefaultTTLGet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); bt_mesh_model_msg_init(&msg, OP_DEFAULT_TTL_STATUS); net_buf_simple_add_u8(&msg, bt_mesh_default_ttl_get()); @@ -847,9 +894,10 @@ static void default_ttl_set(struct bt_mesh_model *model, BLE_MESH_MODEL_BUF_DEFINE(msg, OP_DEFAULT_TTL_STATUS, 1); struct bt_mesh_cfg_srv *cfg = model->user_data; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("DefaultTTLSet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); if (!cfg) { BT_WARN("No Configuration Server context available"); @@ -879,6 +927,8 @@ static void send_gatt_proxy_status(struct bt_mesh_model *model, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_GATT_PROXY_STATUS, 1); + BT_DBG("SendGattProxyStatus"); + bt_mesh_model_msg_init(&msg, OP_GATT_PROXY_STATUS); net_buf_simple_add_u8(&msg, bt_mesh_gatt_proxy_get()); @@ -891,9 +941,10 @@ static void gatt_proxy_get(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("GattProxyGet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); send_gatt_proxy_status(model, ctx); } @@ -904,9 +955,10 @@ static void gatt_proxy_set(struct bt_mesh_model *model, { struct bt_mesh_cfg_srv *cfg = model->user_data; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("GattProxySet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); if (buf->data[0] != 0x00 && buf->data[0] != 0x01) { BT_WARN("Invalid GATT Proxy value 0x%02x", buf->data[0]); @@ -923,7 +975,7 @@ static void gatt_proxy_set(struct bt_mesh_model *model, goto send_status; } - BT_DBG("GATT Proxy 0x%02x -> 0x%02x", cfg->gatt_proxy, buf->data[0]); + BT_DBG("GattProxy 0x%02x -> 0x%02x", cfg->gatt_proxy, buf->data[0]); if (cfg->gatt_proxy == buf->data[0]) { goto send_status; @@ -934,11 +986,11 @@ static void gatt_proxy_set(struct bt_mesh_model *model, #if CONFIG_BLE_MESH_PRB_SRV /* If the value of the GATT Proxy state of the node is 0x01 (see Table 4.21), * then the value of the Private GATT Proxy state shall be Disable (0x00). - */ + */ if (buf->data[0] == BLE_MESH_GATT_PROXY_ENABLED) { bt_mesh_disable_private_gatt_proxy(); } -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ #if CONFIG_BLE_MESH_DF_SRV /* If the value of the GATT Proxy state of the node is 0x00, @@ -946,7 +998,7 @@ static void gatt_proxy_set(struct bt_mesh_model *model, * directed proxy use directed default shall be 0x02. */ bt_mesh_disable_directed_proxy_state(ctx->net_idx); -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { bt_mesh_store_cfg(); @@ -966,9 +1018,10 @@ static void net_transmit_get(struct bt_mesh_model *model, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_NET_TRANSMIT_STATUS, 1); - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("NetTransmitGet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); bt_mesh_model_msg_init(&msg, OP_NET_TRANSMIT_STATUS); net_buf_simple_add_u8(&msg, bt_mesh_net_transmit_get()); @@ -985,11 +1038,13 @@ static void net_transmit_set(struct bt_mesh_model *model, BLE_MESH_MODEL_BUF_DEFINE(msg, OP_NET_TRANSMIT_STATUS, 1); struct bt_mesh_cfg_srv *cfg = model->user_data; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("NetTransmitSet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); - BT_DBG("Transmit 0x%02x (count %u interval %ums)", buf->data[0], + BT_DBG("Transmit 0x%02x Count %u Interval %u", + buf->data[0], BLE_MESH_TRANSMIT_COUNT(buf->data[0]), BLE_MESH_TRANSMIT_INT(buf->data[0])); @@ -1017,9 +1072,10 @@ static void relay_get(struct bt_mesh_model *model, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_RELAY_STATUS, 2); - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("RelayGet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); bt_mesh_model_msg_init(&msg, OP_RELAY_STATUS); net_buf_simple_add_u8(&msg, bt_mesh_relay_get()); @@ -1037,9 +1093,10 @@ static void relay_set(struct bt_mesh_model *model, BLE_MESH_MODEL_BUF_DEFINE(msg, OP_RELAY_STATUS, 2); struct bt_mesh_cfg_srv *cfg = model->user_data; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("RelaySet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); if (!cfg) { BT_WARN("No Configuration Server context available"); @@ -1050,6 +1107,7 @@ static void relay_set(struct bt_mesh_model *model, change = false; } else { change = (cfg->relay != buf->data[0]); + cfg->relay = buf->data[0]; cfg->relay_retransmit = buf->data[1]; @@ -1058,9 +1116,8 @@ static void relay_set(struct bt_mesh_model *model, } } - BT_DBG("Relay 0x%02x (%s) xmit 0x%02x (count %u interval %u)", - cfg->relay, change ? "changed" : "not changed", - cfg->relay_retransmit, + BT_DBG("Relay 0x%02x Change %u Xmit 0x%02x Count %u Interval %u", + cfg->relay, change, cfg->relay_retransmit, BLE_MESH_TRANSMIT_COUNT(cfg->relay_retransmit), BLE_MESH_TRANSMIT_INT(cfg->relay_retransmit)); @@ -1089,6 +1146,10 @@ static void send_mod_pub_status(struct bt_mesh_model *cfg_mod, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_MOD_PUB_STATUS, 14); + BT_DBG("SendModPubStatus"); + BT_DBG("ElemAddr 0x%04x PubAddr 0x%04x Vnd %u Status 0x%02x", + elem_addr, pub_addr, vnd, status); + bt_mesh_model_msg_init(&msg, OP_MOD_PUB_STATUS); net_buf_simple_add_u8(&msg, status); @@ -1129,6 +1190,8 @@ static void mod_pub_get(struct bt_mesh_model *model, uint8_t *mod_id = NULL, status = 0U; bool vnd = false; + BT_DBG("ModPubGet"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -1137,10 +1200,11 @@ static void mod_pub_get(struct bt_mesh_model *model, mod_id = buf->data; - BT_DBG("elem_addr 0x%04x", elem_addr); + BT_DBG("ElemAddr 0x%04x", elem_addr); elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); mod = NULL; vnd = (buf->len == 4U); status = STATUS_INVALID_ADDRESS; @@ -1149,11 +1213,13 @@ static void mod_pub_get(struct bt_mesh_model *model, mod = get_model(elem, buf, &vnd); if (!mod) { + BT_DBG("StatusInvalidModel"); status = STATUS_INVALID_MODEL; goto send_status; } if (!mod->pub) { + BT_DBG("StatusNvalPubParam"); status = STATUS_NVAL_PUB_PARAM; goto send_status; } @@ -1162,8 +1228,7 @@ static void mod_pub_get(struct bt_mesh_model *model, status = STATUS_SUCCESS; send_status: - send_mod_pub_status(model, ctx, elem_addr, pub_addr, vnd, mod, - status, mod_id); + send_mod_pub_status(model, ctx, elem_addr, pub_addr, vnd, mod, status, mod_id); } static void mod_pub_set(struct bt_mesh_model *model, @@ -1177,6 +1242,8 @@ static void mod_pub_set(struct bt_mesh_model *model, uint8_t *mod_id = NULL; bool vnd = false; + BT_DBG("ModPubSet"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -1198,16 +1265,18 @@ static void mod_pub_set(struct bt_mesh_model *model, retransmit = net_buf_simple_pull_u8(buf); mod_id = buf->data; - BT_DBG("elem_addr 0x%04x pub_addr 0x%04x cred_flag %u", + BT_DBG("ElemAddr 0x%04x PubAddr 0x%04x CredFlag %u", elem_addr, pub_addr, cred_flag); - BT_DBG("pub_app_idx 0x%03x, pub_ttl %u pub_period 0x%02x", + BT_DBG("PubAppIdx 0x%04x PubTTL %u PubPeriod 0x%02x", pub_app_idx, pub_ttl, pub_period); - BT_DBG("retransmit 0x%02x (count %u interval %ums)", retransmit, + BT_DBG("Retransmit 0x%02x Count %u Interval %u", + retransmit, BLE_MESH_PUB_TRANSMIT_COUNT(retransmit), BLE_MESH_PUB_TRANSMIT_INT(retransmit)); elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); mod = NULL; vnd = (buf->len == 4U); status = STATUS_INVALID_ADDRESS; @@ -1216,6 +1285,7 @@ static void mod_pub_set(struct bt_mesh_model *model, mod = get_model(elem, buf, &vnd); if (!mod) { + BT_DBG("StatusInvalidModel"); status = STATUS_INVALID_MODEL; goto send_status; } @@ -1224,8 +1294,7 @@ static void mod_pub_set(struct bt_mesh_model *model, pub_period, retransmit, true); send_status: - send_mod_pub_status(model, ctx, elem_addr, pub_addr, vnd, mod, - status, mod_id); + send_mod_pub_status(model, ctx, elem_addr, pub_addr, vnd, mod, status, mod_id); if (status == STATUS_SUCCESS && mod->pub) { bt_mesh_cfg_server_state_change_t change = {0}; @@ -1245,6 +1314,8 @@ static void mod_pub_set(struct bt_mesh_model *model, struct label *get_label(uint16_t index) { + BT_DBG("GetLabel, Index %u", index); + if (index >= ARRAY_SIZE(labels)) { return NULL; } @@ -1255,7 +1326,10 @@ struct label *get_label(uint16_t index) #if CONFIG_BLE_MESH_LABEL_COUNT > 0 static inline void va_store(struct label *store) { + BT_DBG("VaStore"); + bt_mesh_atomic_set_bit(store->flags, BLE_MESH_VA_CHANGED); + if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { bt_mesh_store_label(); } @@ -1267,6 +1341,8 @@ static struct label *va_find(const uint8_t *label_uuid, struct label *match = NULL; int i; + BT_DBG("VaFind"); + if (free_slot != NULL) { *free_slot = NULL; } @@ -1291,10 +1367,14 @@ uint8_t va_add(uint8_t *label_uuid, uint16_t *addr) { struct label *update = NULL, *free_slot = NULL; + BT_DBG("VaAdd"); + update = va_find(label_uuid, &free_slot); if (update) { update->ref++; + va_store(update); + if (addr) { *addr = update->addr; } @@ -1302,10 +1382,12 @@ uint8_t va_add(uint8_t *label_uuid, uint16_t *addr) } if (!free_slot) { + BT_DBG("StatusInsuffResources"); return STATUS_INSUFF_RESOURCES; } if (bt_mesh_virtual_addr(label_uuid, addr) < 0) { + BT_DBG("StatusUnspecified"); return STATUS_UNSPECIFIED; } @@ -1321,6 +1403,8 @@ uint8_t va_del(uint8_t *label_uuid, uint16_t *addr) { struct label *update = NULL; + BT_DBG("VaDel"); + update = va_find(label_uuid, NULL); if (update) { update->ref--; @@ -1337,6 +1421,7 @@ uint8_t va_del(uint8_t *label_uuid, uint16_t *addr) *addr = BLE_MESH_ADDR_UNASSIGNED; } + BT_DBG("StatusCannotRemove"); return STATUS_CANNOT_REMOVE; } @@ -1346,6 +1431,8 @@ static size_t mod_sub_list_clear(struct bt_mesh_model *mod) size_t clear_count = 0U; int i; + BT_DBG("ModSubListClear"); + /* Unref stored labels related to this model */ for (i = 0, clear_count = 0; i < ARRAY_SIZE(mod->groups); i++) { if (!BLE_MESH_ADDR_IS_VIRTUAL(mod->groups[i])) { @@ -1365,10 +1452,12 @@ static size_t mod_sub_list_clear(struct bt_mesh_model *mod) if (label_uuid) { va_del(label_uuid, NULL); } else { - BT_ERR("Label UUID not found"); + BT_ERR("LabelUUIDNotFound"); } } + BT_DBG("ClearCount %u", clear_count); + return clear_count; } @@ -1384,6 +1473,8 @@ static void mod_pub_va_set(struct bt_mesh_model *model, uint8_t *mod_id = NULL; bool vnd = false; + BT_DBG("ModPubVaSet"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -1404,15 +1495,17 @@ static void mod_pub_va_set(struct bt_mesh_model *model, retransmit = net_buf_simple_pull_u8(buf); mod_id = buf->data; - BT_DBG("elem_addr 0x%04x cred_flag %u", elem_addr, cred_flag); - BT_DBG("pub_app_idx 0x%03x, pub_ttl %u pub_period 0x%02x", + BT_DBG("ElemAddr 0x%04x CredFlag %u", elem_addr, cred_flag); + BT_DBG("PubAppIdx 0x%04x PubTTL %u PubPeriod 0x%02x", pub_app_idx, pub_ttl, pub_period); - BT_DBG("retransmit 0x%02x (count %u interval %ums)", retransmit, + BT_DBG("Retransmit 0x%02x Count %u Interval %u", + retransmit, BLE_MESH_PUB_TRANSMIT_COUNT(retransmit), BLE_MESH_PUB_TRANSMIT_INT(retransmit)); elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); mod = NULL; vnd = (buf->len == 4U); pub_addr = 0U; @@ -1422,6 +1515,7 @@ static void mod_pub_va_set(struct bt_mesh_model *model, mod = get_model(elem, buf, &vnd); if (!mod) { + BT_DBG("StatusInvalidModel"); pub_addr = 0U; status = STATUS_INVALID_MODEL; goto send_status; @@ -1434,15 +1528,16 @@ static void mod_pub_va_set(struct bt_mesh_model *model, } send_status: - send_mod_pub_status(model, ctx, elem_addr, pub_addr, vnd, mod, - status, mod_id); + send_mod_pub_status(model, ctx, elem_addr, pub_addr, vnd, mod, status, mod_id); } -#else +#else /* CONFIG_BLE_MESH_LABEL_COUNT > 0 */ static size_t mod_sub_list_clear(struct bt_mesh_model *mod) { size_t clear_count = 0U; int i; + BT_DBG("ModSubListClear"); + /* Unref stored labels related to this model */ for (i = 0, clear_count = 0; i < ARRAY_SIZE(mod->groups); i++) { if (mod->groups[i] != BLE_MESH_ADDR_UNASSIGNED) { @@ -1451,6 +1546,8 @@ static size_t mod_sub_list_clear(struct bt_mesh_model *mod) } } + BT_DBG("ClearCount %u", clear_count); + return clear_count; } @@ -1458,12 +1555,14 @@ static void mod_pub_va_set(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { + uint16_t elem_addr = 0U, pub_addr = 0U; uint8_t *mod_id = NULL, status = 0U; struct bt_mesh_model *mod = NULL; struct bt_mesh_elem *elem = NULL; - uint16_t elem_addr = 0U, pub_addr = 0U; bool vnd = false; + BT_DBG("ModPubVaSet"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -1473,10 +1572,11 @@ static void mod_pub_va_set(struct bt_mesh_model *model, net_buf_simple_pull(buf, 16); mod_id = net_buf_simple_pull(buf, 4); - BT_DBG("elem_addr 0x%04x", elem_addr); + BT_DBG("ElemAddr 0x%04x", elem_addr); elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); mod = NULL; vnd = (buf->len == 4U); status = STATUS_INVALID_ADDRESS; @@ -1485,33 +1585,37 @@ static void mod_pub_va_set(struct bt_mesh_model *model, mod = get_model(elem, buf, &vnd); if (!mod) { + BT_DBG("StatusInvalidModel"); status = STATUS_INVALID_MODEL; goto send_status; } if (!mod->pub) { + BT_DBG("StatusNvalPubParam"); status = STATUS_NVAL_PUB_PARAM; goto send_status; } pub_addr = mod->pub->addr; + + BT_DBG("StatusInsuffResources"); status = STATUS_INSUFF_RESOURCES; send_status: - send_mod_pub_status(model, ctx, elem_addr, pub_addr, vnd, mod, - status, mod_id); + send_mod_pub_status(model, ctx, elem_addr, pub_addr, vnd, mod, status, mod_id); } #endif /* CONFIG_BLE_MESH_LABEL_COUNT > 0 */ static void send_mod_sub_status(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, uint8_t status, - uint16_t elem_addr, uint16_t sub_addr, uint8_t *mod_id, - bool vnd) + uint16_t elem_addr, uint16_t sub_addr, + uint8_t *mod_id, bool vnd) { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_MOD_SUB_STATUS, 9); - BT_DBG("status 0x%02x elem_addr 0x%04x sub_addr 0x%04x", status, - elem_addr, sub_addr); + BT_DBG("SendModSubStatus"); + BT_DBG("Status 0x%02x ElemAddr 0x%04x SubAddr 0x%04x Vnd %u", + status, elem_addr, sub_addr, vnd); bt_mesh_model_msg_init(&msg, OP_MOD_SUB_STATUS); @@ -1542,6 +1646,8 @@ static void mod_sub_add(struct bt_mesh_model *model, bool vnd = false; int i; + BT_DBG("ModSubAdd"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -1550,12 +1656,13 @@ static void mod_sub_add(struct bt_mesh_model *model, sub_addr = net_buf_simple_pull_le16(buf); - BT_DBG("elem_addr 0x%04x, sub_addr 0x%04x", elem_addr, sub_addr); + BT_DBG("ElemAddr 0x%04x SubAddr 0x%04x", elem_addr, sub_addr); mod_id = buf->data; elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); mod = NULL; vnd = (buf->len == 4U); status = STATUS_INVALID_ADDRESS; @@ -1564,18 +1671,19 @@ static void mod_sub_add(struct bt_mesh_model *model, mod = get_model(elem, buf, &vnd); if (!mod) { + BT_DBG("StatusInvalidModel"); status = STATUS_INVALID_MODEL; goto send_status; } if (!BLE_MESH_ADDR_IS_GROUP(sub_addr)) { + BT_DBG("StatusInvalidAddress"); status = STATUS_INVALID_ADDRESS; goto send_status; } if (bt_mesh_model_find_group(mod, sub_addr)) { /* Tried to add existing subscription */ - BT_DBG("found existing subscription"); status = STATUS_SUCCESS; goto send_status; } @@ -1592,6 +1700,7 @@ static void mod_sub_add(struct bt_mesh_model *model, } if (i == ARRAY_SIZE(mod->groups)) { + BT_DBG("StatusInsuffResources"); status = STATUS_INSUFF_RESOURCES; } else { status = STATUS_SUCCESS; @@ -1606,12 +1715,11 @@ static void mod_sub_add(struct bt_mesh_model *model, } send_status: - send_mod_sub_status(model, ctx, status, elem_addr, sub_addr, - mod_id, vnd); + send_mod_sub_status(model, ctx, status, elem_addr, sub_addr, mod_id, vnd); #if CONFIG_BLE_MESH_DF_SRV bt_mesh_directed_forwarding_node_solicitation(mod, bt_mesh_subnet_get(ctx->net_idx)); -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ if (status == STATUS_SUCCESS) { bt_mesh_cfg_server_state_change_t change = {0}; @@ -1636,6 +1744,8 @@ static void mod_sub_del(struct bt_mesh_model *model, uint8_t status = 0U; bool vnd = false; + BT_DBG("ModSubDel"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -1644,12 +1754,13 @@ static void mod_sub_del(struct bt_mesh_model *model, sub_addr = net_buf_simple_pull_le16(buf); - BT_DBG("elem_addr 0x%04x sub_addr 0x%04x", elem_addr, sub_addr); + BT_DBG("ElemAddr 0x%04x SubAddr 0x%04x", elem_addr, sub_addr); mod_id = buf->data; elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); mod = NULL; vnd = (buf->len == 4U); status = STATUS_INVALID_ADDRESS; @@ -1658,11 +1769,13 @@ static void mod_sub_del(struct bt_mesh_model *model, mod = get_model(elem, buf, &vnd); if (!mod) { + BT_DBG("StatusInvalidModel"); status = STATUS_INVALID_MODEL; goto send_status; } if (!BLE_MESH_ADDR_IS_GROUP(sub_addr)) { + BT_DBG("StatusInvalidAddress"); status = STATUS_INVALID_ADDRESS; goto send_status; } @@ -1686,8 +1799,7 @@ static void mod_sub_del(struct bt_mesh_model *model, } send_status: - send_mod_sub_status(model, ctx, status, elem_addr, sub_addr, - mod_id, vnd); + send_mod_sub_status(model, ctx, status, elem_addr, sub_addr, mod_id, vnd); if (status == STATUS_SUCCESS) { bt_mesh_cfg_server_state_change_t change = {0}; @@ -1711,6 +1823,8 @@ static void mod_sub_overwrite(struct bt_mesh_model *model, uint8_t status = 0U; bool vnd = false; + BT_DBG("ModSubOverwrite"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -1719,12 +1833,13 @@ static void mod_sub_overwrite(struct bt_mesh_model *model, sub_addr = net_buf_simple_pull_le16(buf); - BT_DBG("elem_addr 0x%04x sub_addr 0x%04x", elem_addr, sub_addr); + BT_DBG("ElemAddr 0x%04x SubAddr 0x%04x", elem_addr, sub_addr); mod_id = buf->data; elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); mod = NULL; vnd = (buf->len == 4U); status = STATUS_INVALID_ADDRESS; @@ -1733,11 +1848,13 @@ static void mod_sub_overwrite(struct bt_mesh_model *model, mod = get_model(elem, buf, &vnd); if (!mod) { + BT_DBG("StatusInvalidModel"); status = STATUS_INVALID_MODEL; goto send_status; } if (!BLE_MESH_ADDR_IS_GROUP(sub_addr)) { + BT_DBG("StatusInvalidAddress"); status = STATUS_INVALID_ADDRESS; goto send_status; } @@ -1760,13 +1877,13 @@ static void mod_sub_overwrite(struct bt_mesh_model *model, bt_mesh_lpn_group_add(sub_addr); } } else { + BT_DBG("StatusInsuffResources"); status = STATUS_INSUFF_RESOURCES; } send_status: - send_mod_sub_status(model, ctx, status, elem_addr, sub_addr, - mod_id, vnd); + send_mod_sub_status(model, ctx, status, elem_addr, sub_addr, mod_id, vnd); } static void mod_sub_del_all(struct bt_mesh_model *model, @@ -1780,18 +1897,21 @@ static void mod_sub_del_all(struct bt_mesh_model *model, uint8_t status = 0U; bool vnd = false; + BT_DBG("ModSubDelAll"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); return; } - BT_DBG("elem_addr 0x%04x", elem_addr); + BT_DBG("ElemAddr 0x%04x", elem_addr); mod_id = buf->data; elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); mod = NULL; vnd = (buf->len == 4U); status = STATUS_INVALID_ADDRESS; @@ -1800,6 +1920,7 @@ static void mod_sub_del_all(struct bt_mesh_model *model, mod = get_model(elem, buf, &vnd); if (!mod) { + BT_DBG("StatusInvalidModel"); status = STATUS_INVALID_MODEL; goto send_status; } @@ -1832,6 +1953,8 @@ static void mod_sub_get(struct bt_mesh_model *model, uint16_t addr = 0U, id = 0U; int i; + BT_DBG("ModSubGet"); + addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(addr)) { BT_ERR("Prohibited element address 0x%04x", addr); @@ -1840,12 +1963,13 @@ static void mod_sub_get(struct bt_mesh_model *model, id = net_buf_simple_pull_le16(buf); - BT_DBG("addr 0x%04x id 0x%04x", addr, id); + BT_DBG("ElemAddr 0x%04x ID 0x%04x", addr, id); bt_mesh_model_msg_init(&msg, OP_MOD_SUB_LIST); elem = bt_mesh_elem_find(addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); net_buf_simple_add_u8(&msg, STATUS_INVALID_ADDRESS); net_buf_simple_add_le16(&msg, addr); net_buf_simple_add_le16(&msg, id); @@ -1854,6 +1978,7 @@ static void mod_sub_get(struct bt_mesh_model *model, mod = bt_mesh_model_find(elem, id); if (!mod) { + BT_DBG("StatusInvalidModel"); net_buf_simple_add_u8(&msg, STATUS_INVALID_MODEL); net_buf_simple_add_le16(&msg, addr); net_buf_simple_add_le16(&msg, id); @@ -1888,6 +2013,8 @@ static void mod_sub_get_vnd(struct bt_mesh_model *model, uint16_t company = 0U, addr = 0U, id = 0U; int i; + BT_DBG("ModSubGetVnd"); + addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(addr)) { BT_ERR("Prohibited element address 0x%04x", addr); @@ -1897,12 +2024,13 @@ static void mod_sub_get_vnd(struct bt_mesh_model *model, company = net_buf_simple_pull_le16(buf); id = net_buf_simple_pull_le16(buf); - BT_DBG("addr 0x%04x company 0x%04x id 0x%04x", addr, company, id); + BT_DBG("ElemAddr 0x%04x CID 0x%04x ID 0x%04x", addr, company, id); bt_mesh_model_msg_init(&msg, OP_MOD_SUB_LIST_VND); elem = bt_mesh_elem_find(addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); net_buf_simple_add_u8(&msg, STATUS_INVALID_ADDRESS); net_buf_simple_add_le16(&msg, addr); net_buf_simple_add_le16(&msg, company); @@ -1912,6 +2040,7 @@ static void mod_sub_get_vnd(struct bt_mesh_model *model, mod = bt_mesh_model_find_vnd(elem, company, id); if (!mod) { + BT_DBG("StatusInvalidModel"); net_buf_simple_add_u8(&msg, STATUS_INVALID_MODEL); net_buf_simple_add_le16(&msg, addr); net_buf_simple_add_le16(&msg, company); @@ -1951,6 +2080,8 @@ static void mod_sub_va_add(struct bt_mesh_model *model, bool vnd = false; int i; + BT_DBG("ModSubVaAdd"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -1959,11 +2090,12 @@ static void mod_sub_va_add(struct bt_mesh_model *model, label_uuid = net_buf_simple_pull_mem(buf, 16); - BT_DBG("elem_addr 0x%04x", elem_addr); + BT_DBG("ElemAddr 0x%04x", elem_addr); mod_id = buf->data; elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); mod = NULL; vnd = (buf->len == 4U); sub_addr = BLE_MESH_ADDR_UNASSIGNED; @@ -1973,6 +2105,7 @@ static void mod_sub_va_add(struct bt_mesh_model *model, mod = get_model(elem, buf, &vnd); if (!mod) { + BT_DBG("StatusInvalidModel"); sub_addr = BLE_MESH_ADDR_UNASSIGNED; status = STATUS_INVALID_MODEL; goto send_status; @@ -2001,6 +2134,7 @@ static void mod_sub_va_add(struct bt_mesh_model *model, } if (i == ARRAY_SIZE(mod->groups)) { + BT_DBG("StatusInsuffResources"); status = STATUS_INSUFF_RESOURCES; } else { if (IS_ENABLED(CONFIG_BLE_MESH_LOW_POWER)) { @@ -2015,8 +2149,7 @@ static void mod_sub_va_add(struct bt_mesh_model *model, } send_status: - send_mod_sub_status(model, ctx, status, elem_addr, sub_addr, - mod_id, vnd); + send_mod_sub_status(model, ctx, status, elem_addr, sub_addr, mod_id, vnd); } static void mod_sub_va_del(struct bt_mesh_model *model, @@ -2032,6 +2165,8 @@ static void mod_sub_va_del(struct bt_mesh_model *model, uint8_t status = 0U; bool vnd = false; + BT_DBG("ModSubVaDel"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -2040,12 +2175,13 @@ static void mod_sub_va_del(struct bt_mesh_model *model, label_uuid = net_buf_simple_pull_mem(buf, 16); - BT_DBG("elem_addr 0x%04x", elem_addr); + BT_DBG("ElemAddr 0x%04x", elem_addr); mod_id = buf->data; elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); mod = NULL; vnd = (buf->len == 4U); sub_addr = BLE_MESH_ADDR_UNASSIGNED; @@ -2055,6 +2191,7 @@ static void mod_sub_va_del(struct bt_mesh_model *model, mod = get_model(elem, buf, &vnd); if (!mod) { + BT_DBG("StatusInvalidModel"); sub_addr = BLE_MESH_ADDR_UNASSIGNED; status = STATUS_INVALID_MODEL; goto send_status; @@ -2079,12 +2216,12 @@ static void mod_sub_va_del(struct bt_mesh_model *model, status = STATUS_SUCCESS; } else { + BT_DBG("StatusCannotRemove"); status = STATUS_CANNOT_REMOVE; } send_status: - send_mod_sub_status(model, ctx, status, elem_addr, sub_addr, - mod_id, vnd); + send_mod_sub_status(model, ctx, status, elem_addr, sub_addr, mod_id, vnd); } static void mod_sub_va_overwrite(struct bt_mesh_model *model, @@ -2099,6 +2236,8 @@ static void mod_sub_va_overwrite(struct bt_mesh_model *model, uint8_t status = 0U; bool vnd = false; + BT_DBG("ModSubVaOverwrite"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -2107,12 +2246,13 @@ static void mod_sub_va_overwrite(struct bt_mesh_model *model, label_uuid = net_buf_simple_pull_mem(buf, 16); - BT_DBG("elem_addr 0x%04x", elem_addr); + BT_DBG("ElemAddr 0x%04x", elem_addr); mod_id = buf->data; elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); mod = NULL; vnd = (buf->len == 4U); status = STATUS_INVALID_ADDRESS; @@ -2121,6 +2261,7 @@ static void mod_sub_va_overwrite(struct bt_mesh_model *model, mod = get_model(elem, buf, &vnd); if (!mod) { + BT_DBG("StatusInvalidModel"); status = STATUS_INVALID_MODEL; goto send_status; } @@ -2145,14 +2286,14 @@ static void mod_sub_va_overwrite(struct bt_mesh_model *model, } } } else { + BT_DBG("StatusInsuffResources"); status = STATUS_INSUFF_RESOURCES; } send_status: - send_mod_sub_status(model, ctx, status, elem_addr, sub_addr, - mod_id, vnd); + send_mod_sub_status(model, ctx, status, elem_addr, sub_addr, mod_id, vnd); } -#else +#else /* CONFIG_BLE_MESH_LABEL_COUNT > 0 */ static void mod_sub_va_add(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) @@ -2164,6 +2305,8 @@ static void mod_sub_va_add(struct bt_mesh_model *model, uint8_t status = 0U; bool vnd = false; + BT_DBG("ModSubVaAdd"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -2176,6 +2319,7 @@ static void mod_sub_va_add(struct bt_mesh_model *model, elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); mod = NULL; vnd = (buf->len == 4U); status = STATUS_INVALID_ADDRESS; @@ -2184,10 +2328,12 @@ static void mod_sub_va_add(struct bt_mesh_model *model, mod = get_model(elem, buf, &vnd); if (!mod) { + BT_DBG("StatusInvalidModel"); status = STATUS_INVALID_MODEL; goto send_status; } + BT_DBG("StatusInsuffResources"); status = STATUS_INSUFF_RESOURCES; send_status: @@ -2205,6 +2351,8 @@ static void mod_sub_va_del(struct bt_mesh_model *model, uint8_t status = 0U; bool vnd = false; + BT_DBG("ModSubVaDel"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -2217,16 +2365,19 @@ static void mod_sub_va_del(struct bt_mesh_model *model, elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); vnd = (buf->len == 4U); status = STATUS_INVALID_ADDRESS; goto send_status; } if (!get_model(elem, buf, &vnd)) { + BT_DBG("StatusInvalidModel"); status = STATUS_INVALID_MODEL; goto send_status; } + BT_DBG("StatusInsuffResources"); status = STATUS_INSUFF_RESOURCES; send_status: @@ -2244,6 +2395,8 @@ static void mod_sub_va_overwrite(struct bt_mesh_model *model, uint8_t status = 0U; bool vnd = false; + BT_DBG("ModSubVaOverwrite"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -2256,16 +2409,19 @@ static void mod_sub_va_overwrite(struct bt_mesh_model *model, elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); vnd = (buf->len == 4U); status = STATUS_INVALID_ADDRESS; goto send_status; } if (!get_model(elem, buf, &vnd)) { + BT_DBG("StatusInvalidModel"); status = STATUS_INVALID_MODEL; goto send_status; } + BT_DBG("StatusInsuffResources"); status = STATUS_INSUFF_RESOURCES; send_status: @@ -2280,6 +2436,8 @@ static void send_net_key_status(struct bt_mesh_model *model, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_NET_KEY_STATUS, 3); + BT_DBG("SendNetKeyStatus"); + bt_mesh_model_msg_init(&msg, OP_NET_KEY_STATUS); net_buf_simple_add_u8(&msg, status); @@ -2298,13 +2456,15 @@ static void net_key_add(struct bt_mesh_model *model, uint16_t idx = 0U; int err = 0; + BT_DBG("NetKeyAdd"); + idx = net_buf_simple_pull_le16(buf); if (idx > 0xfff) { BT_ERR("Invalid NetKeyIndex 0x%04x", idx); return; } - BT_DBG("idx 0x%04x", idx); + BT_DBG("NetIdx 0x%04x", idx); sub = bt_mesh_subnet_get(idx); if (!sub) { @@ -2318,8 +2478,8 @@ static void net_key_add(struct bt_mesh_model *model, } if (!sub) { - send_net_key_status(model, ctx, idx, - STATUS_INSUFF_RESOURCES); + BT_DBG("StatusInsuffResources"); + send_net_key_status(model, ctx, idx, STATUS_INSUFF_RESOURCES); return; } } @@ -2329,6 +2489,7 @@ static void net_key_add(struct bt_mesh_model *model, uint8_t status = 0U; if (memcmp(buf->data, sub->keys[0].net, 16)) { + BT_DBG("StatusIdxAlreadyStored"); status = STATUS_IDX_ALREADY_STORED; } else { status = STATUS_SUCCESS; @@ -2340,6 +2501,7 @@ static void net_key_add(struct bt_mesh_model *model, err = bt_mesh_net_keys_create(&sub->keys[0], buf->data); if (err) { + BT_DBG("StatusUnspecified"); send_net_key_status(model, ctx, idx, STATUS_UNSPECIFIED); return; } @@ -2347,7 +2509,6 @@ static void net_key_add(struct bt_mesh_model *model, sub->net_idx = idx; if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { - BT_DBG("Storing NetKey persistently"); bt_mesh_store_subnet(sub); } @@ -2368,7 +2529,7 @@ static void net_key_add(struct bt_mesh_model *model, if (sub->directed_proxy != BLE_MESH_DIRECTED_PROXY_NOT_SUPPORTED) { bt_mesh_directed_proxy_server_directed_proxy_caps_send(sub, false); } -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV && CONFIG_BLE_MESH_SUPPORT_DIRECTED_PROXY */ bt_mesh_adv_update(); } else { @@ -2381,7 +2542,7 @@ static void net_key_add(struct bt_mesh_model *model, if (bt_mesh_directed_forwarding_sub_init(sub)) { BT_ERR("Failed to init subnet for directed forward"); } -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ bt_mesh_cfg_server_state_change_t change = {0}; change.cfg_netkey_add.net_idx = sub->net_idx; @@ -2398,16 +2559,19 @@ static void net_key_update(struct bt_mesh_model *model, uint16_t idx = 0U; int err = 0; + BT_DBG("NetKeyUpdate"); + idx = net_buf_simple_pull_le16(buf); if (idx > 0xfff) { BT_ERR("Invalid NetKeyIndex 0x%04x", idx); return; } - BT_DBG("idx 0x%04x", idx); + BT_DBG("NetIdx 0x%04x", idx); sub = bt_mesh_subnet_get(idx); if (!sub) { + BT_DBG("StatusInvalidNetKey"); send_net_key_status(model, ctx, idx, STATUS_INVALID_NETKEY); return; } @@ -2432,6 +2596,7 @@ static void net_key_update(struct bt_mesh_model *model, /* fall through */ case BLE_MESH_KR_PHASE_2: case BLE_MESH_KR_PHASE_3: + BT_DBG("StatusCannotUpdate"); send_net_key_status(model, ctx, idx, STATUS_CANNOT_UPDATE); return; } @@ -2443,6 +2608,7 @@ static void net_key_update(struct bt_mesh_model *model, } if (err) { + BT_DBG("StatusUnspecified"); send_net_key_status(model, ctx, idx, STATUS_UNSPECIFIED); return; } @@ -2450,7 +2616,6 @@ static void net_key_update(struct bt_mesh_model *model, sub->kr_phase = BLE_MESH_KR_PHASE_1; if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { - BT_DBG("Storing NetKey persistently"); bt_mesh_store_subnet(sub); } @@ -2467,6 +2632,8 @@ static void net_key_update(struct bt_mesh_model *model, static void hb_pub_disable(struct bt_mesh_cfg_srv *cfg) { + BT_DBG("HbPubDisable"); + cfg->hb_pub.dst = BLE_MESH_ADDR_UNASSIGNED; cfg->hb_pub.count = 0U; cfg->hb_pub.ttl = 0U; @@ -2483,13 +2650,15 @@ static void net_key_del(struct bt_mesh_model *model, uint16_t del_idx = 0U; uint8_t status = 0U; + BT_DBG("NetKeyDel"); + del_idx = net_buf_simple_pull_le16(buf); if (del_idx > 0xfff) { BT_ERR("Invalid NetKeyIndex 0x%04x", del_idx); return; } - BT_DBG("idx 0x%04x", del_idx); + BT_DBG("NetIdx 0x%04x", del_idx); sub = bt_mesh_subnet_get(del_idx); if (!sub) { @@ -2504,6 +2673,7 @@ static void net_key_del(struct bt_mesh_model *model, * The NetKey List must contain a minimum of one NetKey. */ if (ctx->net_idx == del_idx) { + BT_DBG("StatusCannotRemove"); status = STATUS_CANNOT_REMOVE; goto send_status; } @@ -2525,8 +2695,8 @@ static void net_key_del(struct bt_mesh_model *model, #if CONFIG_BLE_MESH_SETTINGS bt_mesh_clear_directed_forwarding_table_data(del_idx); -#endif -#endif +#endif /* CONFIG_BLE_MESH_SETTINGS */ +#endif /* CONFIG_BLE_MESH_DF_SRV && CONFIG_BLE_MESH_SUPPORT_DIRECTED_PROXY */ bt_mesh_subnet_del(sub, true); status = STATUS_SUCCESS; @@ -2540,11 +2710,11 @@ static void net_key_del(struct bt_mesh_model *model, * Index of the deleted NetKey are removed. */ bt_mesh_delete_netkey_in_bridge_table(del_idx); -#endif /* CONFIG_BLE_MESH_BRC_SRV */ +#endif /* CONFIG_BLE_MESH_BRC_SRV */ #if CONFIG_BLE_MESH_RPR_SRV bt_mesh_rpr_srv_netkey_del(del_idx); -#endif +#endif /* CONFIG_BLE_MESH_RPR_SRV */ send_status: send_net_key_status(model, ctx, del_idx, status); @@ -2565,6 +2735,8 @@ static void net_key_get(struct bt_mesh_model *model, IDX_LEN(CONFIG_BLE_MESH_SUBNET_COUNT)); uint16_t prev = 0U, i = 0U; + BT_DBG("NetKeyGet"); + bt_mesh_model_msg_init(&msg, OP_NET_KEY_LIST); prev = BLE_MESH_KEY_UNUSED; @@ -2602,9 +2774,10 @@ static void node_identity_get(struct bt_mesh_model *model, uint8_t node_id = 0U; uint16_t idx = 0U; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("NodeIdentityGet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); idx = net_buf_simple_pull_le16(buf); if (idx > 0xfff) { @@ -2616,6 +2789,7 @@ static void node_identity_get(struct bt_mesh_model *model, sub = bt_mesh_subnet_get(idx); if (!sub) { + BT_DBG("StatusInvalidNetKey"); net_buf_simple_add_u8(&msg, STATUS_INVALID_NETKEY); node_id = 0x00; } else { @@ -2640,9 +2814,10 @@ static void node_identity_set(struct bt_mesh_model *model, uint8_t node_id = 0U; uint16_t idx = 0U; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("NodeIdentitySet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); idx = net_buf_simple_pull_le16(buf); if (idx > 0xfff) { @@ -2660,6 +2835,7 @@ static void node_identity_set(struct bt_mesh_model *model, sub = bt_mesh_subnet_get(idx); if (!sub) { + BT_DBG("StatusInvalidNetKey"); net_buf_simple_add_u8(&msg, STATUS_INVALID_NETKEY); net_buf_simple_add_le16(&msg, idx); net_buf_simple_add_u8(&msg, node_id); @@ -2672,7 +2848,8 @@ static void node_identity_set(struct bt_mesh_model *model, * Identity state shall be Disable (0x00). */ bt_mesh_proxy_private_identity_disable(); -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ + bt_mesh_proxy_server_identity_start(sub); } else { bt_mesh_proxy_server_identity_stop(sub); @@ -2697,6 +2874,10 @@ static void create_mod_app_status(struct net_buf_simple *msg, { bt_mesh_model_msg_init(msg, OP_MOD_APP_STATUS); + BT_DBG("CreateModAppStatus"); + BT_DBG("ElemAddr 0x%04x AppIdx 0x%04x Status 0x%02x Vnd %u", + elem_addr, app_idx, status, vnd); + net_buf_simple_add_u8(msg, status); net_buf_simple_add_le16(msg, elem_addr); net_buf_simple_add_le16(msg, app_idx); @@ -2719,6 +2900,8 @@ static void mod_app_bind(struct bt_mesh_model *model, uint8_t *mod_id = NULL, status = 0U; bool vnd = false; + BT_DBG("ModAppBind"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -2730,6 +2913,7 @@ static void mod_app_bind(struct bt_mesh_model *model, elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); mod = NULL; vnd = (buf->len == 4U); status = STATUS_INVALID_ADDRESS; @@ -2738,24 +2922,24 @@ static void mod_app_bind(struct bt_mesh_model *model, mod = get_model(elem, buf, &vnd); if (!mod) { + BT_DBG("StatusInvalidModel"); status = STATUS_INVALID_MODEL; goto send_status; } /* Configuration Server only allows device key based access */ if (model == mod) { - BT_ERR("Client tried to bind AppKey to Configuration Model"); + BT_ERR("StatusCannotBind"); status = STATUS_CANNOT_BIND; goto send_status; } status = mod_bind(mod, key_app_idx); - BT_INFO("bind app key %#x on mode %#x", key_app_idx, mod->id); + BT_INFO("AppIdx 0x%04x ID 0x%04x", key_app_idx, mod->id); + send_status: - BT_DBG("status 0x%02x", status); - create_mod_app_status(&msg, mod, vnd, elem_addr, key_app_idx, status, - mod_id); + create_mod_app_status(&msg, mod, vnd, elem_addr, key_app_idx, status, mod_id); if (bt_mesh_model_send(model, ctx, &msg, NULL, NULL)) { BT_ERR("Unable to send Config Model App Bind Status"); @@ -2783,6 +2967,8 @@ static void mod_app_unbind(struct bt_mesh_model *model, uint8_t *mod_id = NULL, status = 0U; bool vnd = false; + BT_DBG("ModAppUnbind"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -2794,6 +2980,7 @@ static void mod_app_unbind(struct bt_mesh_model *model, elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); mod = NULL; vnd = (buf->len == 4U); status = STATUS_INVALID_ADDRESS; @@ -2802,6 +2989,7 @@ static void mod_app_unbind(struct bt_mesh_model *model, mod = get_model(elem, buf, &vnd); if (!mod) { + BT_DBG("StatusInvalidModel"); status = STATUS_INVALID_MODEL; goto send_status; } @@ -2809,9 +2997,7 @@ static void mod_app_unbind(struct bt_mesh_model *model, status = mod_unbind(mod, key_app_idx, true); send_status: - BT_DBG("status 0x%02x", status); - create_mod_app_status(&msg, mod, vnd, elem_addr, key_app_idx, status, - mod_id); + create_mod_app_status(&msg, mod, vnd, elem_addr, key_app_idx, status, mod_id); if (bt_mesh_model_send(model, ctx, &msg, NULL, NULL)) { BT_ERR("Unable to send Config Model App Unbind Status"); @@ -2828,23 +3014,22 @@ static void mod_app_unbind(struct bt_mesh_model *model, } } -#define KEY_LIST_LEN (CONFIG_BLE_MESH_MODEL_KEY_COUNT * 2) +#define KEY_LIST_LEN (CONFIG_BLE_MESH_MODEL_KEY_COUNT * 2) static void mod_app_get(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { - NET_BUF_SIMPLE_DEFINE(msg, - MAX(BLE_MESH_MODEL_BUF_LEN(OP_VND_MOD_APP_LIST, - 9 + KEY_LIST_LEN), - BLE_MESH_MODEL_BUF_LEN(OP_SIG_MOD_APP_LIST, - 9 + KEY_LIST_LEN))); + NET_BUF_SIMPLE_DEFINE(msg, MAX(BLE_MESH_MODEL_BUF_LEN(OP_VND_MOD_APP_LIST, 9 + KEY_LIST_LEN), + BLE_MESH_MODEL_BUF_LEN(OP_SIG_MOD_APP_LIST, 9 + KEY_LIST_LEN))); struct bt_mesh_model *mod = NULL; struct bt_mesh_elem *elem = NULL; uint8_t *mod_id = NULL, status = 0U; uint16_t elem_addr = 0U; bool vnd = false; + BT_DBG("ModAppGet"); + elem_addr = net_buf_simple_pull_le16(buf); if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { BT_ERR("Prohibited element address 0x%04x", elem_addr); @@ -2853,10 +3038,11 @@ static void mod_app_get(struct bt_mesh_model *model, mod_id = buf->data; - BT_DBG("elem_addr 0x%04x", elem_addr); + BT_DBG("ElemAddr 0x%04x", elem_addr); elem = bt_mesh_elem_find(elem_addr); if (!elem) { + BT_DBG("StatusInvalidAddress"); mod = NULL; vnd = (buf->len == 4U); status = STATUS_INVALID_ADDRESS; @@ -2865,6 +3051,7 @@ static void mod_app_get(struct bt_mesh_model *model, mod = get_model(elem, buf, &vnd); if (!mod) { + BT_DBG("StatusInvalidModel"); status = STATUS_INVALID_MODEL; goto send_list; } @@ -2908,15 +3095,15 @@ static void node_reset(struct bt_mesh_model *model, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_NODE_RESET_STATUS, 0); - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); - + BT_DBG("NodeReset"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); bt_mesh_model_msg_init(&msg, OP_NODE_RESET_STATUS); - /* Send the response first since we won't have any keys left to - * send it later. + /* Send the response first since we won't have any keys + * left to send it later. */ if (bt_mesh_model_send(model, ctx, &msg, NULL, NULL)) { BT_ERR("Unable to send Config Node Reset Status"); @@ -2933,6 +3120,8 @@ static void send_friend_status(struct bt_mesh_model *model, BLE_MESH_MODEL_BUF_DEFINE(msg, OP_FRIEND_STATUS, 1); struct bt_mesh_cfg_srv *cfg = model->user_data; + BT_DBG("SendFrndStatus"); + bt_mesh_model_msg_init(&msg, OP_FRIEND_STATUS); net_buf_simple_add_u8(&msg, cfg->frnd); @@ -2945,9 +3134,10 @@ static void friend_get(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("FrndGet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); send_friend_status(model, ctx); } @@ -2958,9 +3148,10 @@ static void friend_set(struct bt_mesh_model *model, { struct bt_mesh_cfg_srv *cfg = model->user_data; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("FrndSet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); if (buf->data[0] != 0x00 && buf->data[0] != 0x01) { BT_WARN("Invalid Friend value 0x%02x", buf->data[0]); @@ -2972,7 +3163,7 @@ static void friend_set(struct bt_mesh_model *model, goto send_status; } - BT_DBG("Friend 0x%02x -> 0x%02x", cfg->frnd, buf->data[0]); + BT_DBG("Frnd 0x%02x -> 0x%02x", cfg->frnd, buf->data[0]); if (cfg->frnd == buf->data[0]) { goto send_status; @@ -2993,7 +3184,7 @@ static void friend_set(struct bt_mesh_model *model, * then the value of the directed friend state shall be 0x00. */ bt_mesh_disable_directed_friend_state(ctx->net_idx); -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV && CONFIG_BLE_MESH_FRIEND */ } } @@ -3016,7 +3207,8 @@ static void lpn_timeout_get(struct bt_mesh_model *model, lpn_addr = net_buf_simple_pull_le16(buf); - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x lpn_addr 0x%02x", + BT_DBG("LPNTimeoutGet"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x LPN 0x%04x", ctx->net_idx, ctx->app_idx, ctx->addr, lpn_addr); if (!BLE_MESH_ADDR_IS_UNICAST(lpn_addr)) { @@ -3054,6 +3246,8 @@ static void send_krp_status(struct bt_mesh_model *model, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_KRP_STATUS, 4); + BT_DBG("SendKrpStatus"); + bt_mesh_model_msg_init(&msg, OP_KRP_STATUS); net_buf_simple_add_u8(&msg, status); @@ -3071,20 +3265,22 @@ static void krp_get(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct bt_mesh_subnet *sub = NULL; uint16_t idx = 0U; + BT_DBG("KrpGet"); + idx = net_buf_simple_pull_le16(buf); if (idx > 0xfff) { BT_ERR("Invalid NetKeyIndex 0x%04x", idx); return; } - BT_DBG("idx 0x%04x", idx); + BT_DBG("NetIdx 0x%04x", idx); sub = bt_mesh_subnet_get(idx); if (!sub) { + BT_DBG("StatusInvalidNetKey"); send_krp_status(model, ctx, idx, 0x00, STATUS_INVALID_NETKEY); } else { - send_krp_status(model, ctx, idx, sub->kr_phase, - STATUS_SUCCESS); + send_krp_status(model, ctx, idx, sub->kr_phase, STATUS_SUCCESS); } } @@ -3095,6 +3291,8 @@ static void krp_set(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, uint8_t phase = 0U; uint16_t idx = 0U; + BT_DBG("KrpSet"); + idx = net_buf_simple_pull_le16(buf); phase = net_buf_simple_pull_u8(buf); @@ -3103,15 +3301,16 @@ static void krp_set(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, return; } - BT_DBG("idx 0x%04x transition 0x%02x", idx, phase); + BT_DBG("NetIdx 0x%04x Phase 0x%02x", idx, phase); sub = bt_mesh_subnet_get(idx); if (!sub) { + BT_DBG("StatusInvalidNetKey"); send_krp_status(model, ctx, idx, 0x00, STATUS_INVALID_NETKEY); return; } - BT_DBG("%u -> %u", sub->kr_phase, phase); + BT_DBG("KrPhase %u -> %u", sub->kr_phase, phase); if (phase < BLE_MESH_KR_PHASE_2 || phase > BLE_MESH_KR_PHASE_3 || (sub->kr_phase == BLE_MESH_KR_NORMAL && @@ -3126,7 +3325,6 @@ static void krp_set(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, sub->kr_flag = 1; if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { - BT_DBG("Storing kr phase persistently"); bt_mesh_store_subnet(sub); } @@ -3157,6 +3355,8 @@ static void krp_set(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, static uint8_t hb_log(uint16_t val) { + BT_DBG("HbLog, Val 0x%04x", val); + switch (val) { case 0x0000: return 0x00; @@ -3169,6 +3369,8 @@ static uint8_t hb_log(uint16_t val) static uint8_t hb_pub_count_log(uint16_t val) { + BT_DBG("HbPubCountLog, Val 0x%04x", val); + switch (val) { case 0x0000: return 0x00; @@ -3183,6 +3385,8 @@ static uint8_t hb_pub_count_log(uint16_t val) static uint16_t hb_pwr2(uint8_t val, uint8_t sub) { + BT_DBG("HbPwr2, Val 0x%02x Sub 0x%02x", val, sub); + switch (val) { case 0x00: return 0x0000; @@ -3210,7 +3414,7 @@ static void hb_pub_send_status(struct bt_mesh_model *model, BLE_MESH_MODEL_BUF_DEFINE(msg, OP_HEARTBEAT_PUB_STATUS, 10); struct bt_mesh_cfg_srv *cfg = model->user_data; - BT_DBG("src 0x%04x status 0x%02x", ctx->addr, status); + BT_DBG("HbPubSendStatus, Src 0x%04x Status 0x%02x", ctx->addr, status); bt_mesh_model_msg_init(&msg, OP_HEARTBEAT_PUB_STATUS); @@ -3239,7 +3443,7 @@ static void heartbeat_pub_get(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { - BT_DBG("src 0x%04x", ctx->addr); + BT_DBG("HeartbeatPubGet, Src 0x%04x", ctx->addr); hb_pub_send_status(model, ctx, STATUS_SUCCESS, NULL); } @@ -3253,27 +3457,30 @@ static void heartbeat_pub_set(struct bt_mesh_model *model, uint16_t dst = 0U, feat = 0U, idx = 0U; uint8_t status = 0U; - BT_DBG("src 0x%04x", ctx->addr); + BT_DBG("HeartbeatPubSet, Src 0x%04x", ctx->addr); dst = sys_le16_to_cpu(param->dst); /* All other address types but virtual are valid */ if (BLE_MESH_ADDR_IS_VIRTUAL(dst)) { + BT_DBG("StatusInvalidAddress"); status = STATUS_INVALID_ADDRESS; goto failed; } if (param->count_log > 0x11 && param->count_log != 0xff) { + BT_DBG("StatusCannotSet"); status = STATUS_CANNOT_SET; goto failed; } if (param->period_log > 0x11) { + BT_DBG("StatusCannotSet"); status = STATUS_CANNOT_SET; goto failed; } if (param->ttl > BLE_MESH_TTL_MAX && param->ttl != BLE_MESH_TTL_DEFAULT) { - BT_ERR("Invalid TTL value 0x%02x", param->ttl); + BT_ERR("InvalidTTL %u", param->ttl); return; } @@ -3281,11 +3488,12 @@ static void heartbeat_pub_set(struct bt_mesh_model *model, idx = sys_le16_to_cpu(param->net_idx); if (idx > 0xfff) { - BT_ERR("Invalid NetKeyIndex 0x%04x", idx); + BT_ERR("InvalidNetIdx 0x%04x", idx); return; } if (!bt_mesh_subnet_get(idx)) { + BT_DBG("StatusInvalidNetKey"); status = STATUS_INVALID_NETKEY; goto failed; } @@ -3302,7 +3510,7 @@ static void heartbeat_pub_set(struct bt_mesh_model *model, cfg->hb_pub.count = hb_pwr2(param->count_log, 1); cfg->hb_pub.ttl = param->ttl; - BT_DBG("period %u ms", hb_pwr2(param->period_log, 1) * 1000U); + BT_DBG("Period %u", hb_pwr2(param->period_log, 1) * 1000U); /* Note: Send heartbeat message here will cause wrong heartbeat status message */ #if 0 @@ -3343,14 +3551,15 @@ static void heartbeat_pub_set(struct bt_mesh_model *model, } static void hb_sub_send_status(struct bt_mesh_model *model, - struct bt_mesh_msg_ctx *ctx, uint8_t status) + struct bt_mesh_msg_ctx *ctx, + uint8_t status) { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_HEARTBEAT_SUB_STATUS, 9); struct bt_mesh_cfg_srv *cfg = model->user_data; uint16_t period = 0U; int64_t uptime = 0; - BT_DBG("src 0x%04x status 0x%02x", ctx->addr, status); + BT_DBG("HbSubSendStatus, Src 0x%04x Status 0x%02x", ctx->addr, status); uptime = k_uptime_get(); if (uptime > cfg->hb_sub.expiry) { @@ -3378,7 +3587,7 @@ static void heartbeat_sub_get(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { - BT_DBG("src 0x%04x", ctx->addr); + BT_DBG("HeartbeatSubGet, Src 0x%04x", ctx->addr); hb_sub_send_status(model, ctx, STATUS_SUCCESS); } @@ -3392,13 +3601,13 @@ static void heartbeat_sub_set(struct bt_mesh_model *model, uint8_t sub_period = 0U; int32_t period_ms = 0; - BT_DBG("src 0x%04x", ctx->addr); + BT_DBG("HeartbeatSubSet, Src 0x%04x", ctx->addr); sub_src = net_buf_simple_pull_le16(buf); sub_dst = net_buf_simple_pull_le16(buf); sub_period = net_buf_simple_pull_u8(buf); - BT_DBG("sub_src 0x%04x sub_dst 0x%04x period 0x%02x", + BT_DBG("SubSrc 0x%04x SubDst 0x%04x SubPeriod 0x%02x", sub_src, sub_dst, sub_period); if (sub_src != BLE_MESH_ADDR_UNASSIGNED && @@ -3447,7 +3656,7 @@ static void heartbeat_sub_set(struct bt_mesh_model *model, /* Let the transport layer know it needs to handle this address */ bt_mesh_set_hb_sub_dst(cfg->hb_sub.dst); - BT_DBG("period_ms %u", period_ms); + BT_DBG("Period %ld", period_ms); if (period_ms) { cfg->hb_sub.expiry = k_uptime_get() + period_ms; @@ -3529,7 +3738,8 @@ static void hb_publish(struct k_work *work) struct bt_mesh_subnet *sub = NULL; uint16_t period_ms = 0U; - BT_DBG("hb_pub.count: %u", cfg->hb_pub.count); + BT_DBG("HbPublish, NetIdx 0x%04x Count %u", + cfg->hb_pub.net_idx, cfg->hb_pub.count); sub = bt_mesh_subnet_get(cfg->hb_pub.net_idx); if (!sub) { @@ -3557,15 +3767,20 @@ static void hb_publish(struct k_work *work) static bool conf_is_valid(struct bt_mesh_cfg_srv *cfg) { + BT_DBG("ConfIsValid"); + if (cfg->relay > 0x02) { + BT_ERR("InvalidRelay 0x%02x", cfg->relay); return false; } if (cfg->beacon > 0x01) { + BT_ERR("InvalidBeacon 0x%02x", cfg->beacon); return false; } if (cfg->default_ttl > BLE_MESH_TTL_MAX) { + BT_ERR("InvalidDefaultTTL 0x%02x", cfg->default_ttl); return false; } @@ -3591,6 +3806,8 @@ static int cfg_srv_init(struct bt_mesh_model *model) { struct bt_mesh_cfg_srv *cfg = model->user_data; + BT_DBG("CfgSrvInit"); + if (!bt_mesh_model_in_primary(model)) { BT_ERR("Configuration Server only allowed in primary element"); return -EINVAL; @@ -3602,7 +3819,6 @@ static int cfg_srv_init(struct bt_mesh_model *model) } if (!conf_is_valid(cfg)) { - BT_ERR("Invalid values in configuration"); return -EINVAL; } @@ -3637,6 +3853,8 @@ static int cfg_srv_deinit(struct bt_mesh_model *model) { struct bt_mesh_cfg_srv *cfg = model->user_data; + BT_DBG("CfgSrvDeinit"); + if (!bt_mesh_model_in_primary(model)) { BT_ERR("Configuration Server only allowed in primary element"); return -EINVAL; @@ -3682,6 +3900,9 @@ static void mod_reset(struct bt_mesh_model *mod, struct bt_mesh_elem *elem, clear_count = mod_sub_list_clear(mod); + BT_DBG("ModReset, ClearCount %lu Vnd %u Primary %u", + clear_count, vnd, primary); + if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS) && clear_count && store) { bt_mesh_store_mod_sub(mod); } @@ -3689,6 +3910,8 @@ static void mod_reset(struct bt_mesh_model *mod, struct bt_mesh_elem *elem, void bt_mesh_mod_sub_reset(bool store) { + BT_DBG("ModSubReset, Store %u", store); + bt_mesh_model_foreach(mod_reset, &store); } @@ -3697,6 +3920,8 @@ void bt_mesh_cfg_reset(bool store) struct bt_mesh_cfg_srv *cfg = conf; int i; + BT_DBG("CfgReset, Store %u", store); + if (!cfg) { return; } @@ -3725,7 +3950,11 @@ void bt_mesh_cfg_reset(bool store) uint8_t bt_mesh_net_transmit_get(void) { + BT_DBG("NetTransmitGet"); + if (conf) { + BT_DBG("Val 0x%02x", conf->net_transmit); + return conf->net_transmit; } @@ -3734,6 +3963,8 @@ uint8_t bt_mesh_net_transmit_get(void) void bt_mesh_relay_local_set(bool enable) { + BT_DBG("RelayLocalSet, Enable %u", enable); + if (conf && conf->relay != BLE_MESH_RELAY_NOT_SUPPORTED) { if (enable) { conf->relay = BLE_MESH_RELAY_ENABLED; @@ -3745,7 +3976,11 @@ void bt_mesh_relay_local_set(bool enable) uint8_t bt_mesh_relay_get(void) { + BT_DBG("RelayGet"); + if (conf) { + BT_DBG("Val 0x%02x", conf->relay); + return conf->relay; } @@ -3754,8 +3989,11 @@ uint8_t bt_mesh_relay_get(void) uint8_t bt_mesh_friend_get(void) { + BT_DBG("FrndGet"); + if (conf) { - BT_DBG("conf %p conf->frnd 0x%02x", conf, conf->frnd); + BT_DBG("Val 0x%02x", conf->frnd); + return conf->frnd; } @@ -3764,7 +4002,11 @@ uint8_t bt_mesh_friend_get(void) uint8_t bt_mesh_relay_retransmit_get(void) { + BT_DBG("RelayRetransmitGet"); + if (conf) { + BT_DBG("Val 0x%02x", conf->relay_retransmit); + return conf->relay_retransmit; } @@ -3773,7 +4015,11 @@ uint8_t bt_mesh_relay_retransmit_get(void) uint8_t bt_mesh_secure_beacon_get(void) { + BT_DBG("SecureBeaconGet"); + if (conf) { + BT_DBG("Val 0x%02x", conf->beacon); + return conf->beacon; } @@ -3782,7 +4028,11 @@ uint8_t bt_mesh_secure_beacon_get(void) uint8_t bt_mesh_gatt_proxy_get(void) { + BT_DBG("GattProxyGet"); + if (conf) { + BT_DBG("Val 0x%02x", conf->gatt_proxy); + return conf->gatt_proxy; } @@ -3791,7 +4041,11 @@ uint8_t bt_mesh_gatt_proxy_get(void) uint8_t bt_mesh_default_ttl_get(void) { + BT_DBG("DefaultTTLGet"); + if (conf) { + BT_DBG("Val 0x%02x", conf->default_ttl); + return conf->default_ttl; } @@ -3802,7 +4056,7 @@ uint8_t *bt_mesh_label_uuid_get(uint16_t addr) { int i; - BT_DBG("addr 0x%04x", addr); + BT_DBG("LabelUUIDGet, Addr 0x%04x", addr); for (i = 0; i < ARRAY_SIZE(labels); i++) { if (labels[i].addr == addr) { @@ -3819,6 +4073,8 @@ uint8_t *bt_mesh_label_uuid_get(uint16_t addr) struct bt_mesh_hb_pub *bt_mesh_hb_pub_get(void) { + BT_DBG("HbPubGet"); + if (!conf) { return NULL; } @@ -3828,6 +4084,8 @@ struct bt_mesh_hb_pub *bt_mesh_hb_pub_get(void) void bt_mesh_hb_pub_disable(void) { + BT_DBG("HbPubDisable"); + if (conf) { hb_pub_disable(conf); } @@ -3835,6 +4093,8 @@ void bt_mesh_hb_pub_disable(void) struct bt_mesh_cfg_srv *bt_mesh_cfg_get(void) { + BT_DBG("CfgGet, Conf %p", conf); + return conf; } @@ -3842,7 +4102,7 @@ void bt_mesh_subnet_del(struct bt_mesh_subnet *sub, bool store) { int i; - BT_DBG("NetIdx 0x%03x store %u", sub->net_idx, store); + BT_DBG("SubnetDel, NetIdx 0x%04x Store %u", sub->net_idx, store); if (conf && conf->hb_pub.net_idx == sub->net_idx) { hb_pub_disable(conf); diff --git a/components/bt/esp_ble_mesh/core/crypto.c b/components/bt/esp_ble_mesh/core/crypto.c index 2577c65efba2..a9991e324b36 100644 --- a/components/bt/esp_ble_mesh/core/crypto.c +++ b/components/bt/esp_ble_mesh/core/crypto.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -24,9 +24,9 @@ #if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" -#endif +#endif /* CONFIG_BLE_MESH_V11_SUPPORT */ -#define NET_MIC_LEN(pdu) (((pdu)[1] & 0x80) ? 8 : 4) +#define NET_MIC_LEN(pdu) (((pdu)[1] & 0x80) ? 8 : 4) #define APP_MIC_LEN(aszmic) ((aszmic) ? 8 : 4) int bt_mesh_aes_cmac(const uint8_t key[16], struct bt_mesh_sg *sg, @@ -369,10 +369,11 @@ static int bt_mesh_ccm_encrypt(const uint8_t key[16], uint8_t nonce[13], size_t i = 0U, j = 0U; int err = 0; - BT_DBG("key %s", bt_hex(key, 16)); - BT_DBG("nonce %s", bt_hex(nonce, 13)); - BT_DBG("msg (len %u) %s", msg_len, bt_hex(msg, msg_len)); - BT_DBG("aad_len %u mic_size %u", aad_len, mic_size); + BT_DBG("CCMEncrypt"); + BT_DBG("Key %s", bt_hex(key, 16)); + BT_DBG("Nonce %s", bt_hex(nonce, 13)); + BT_DBG("Len %u: %s", msg_len, bt_hex(msg, msg_len)); + BT_DBG("AADLen %u MicSize %u", aad_len, mic_size); /* Unsupported AAD size */ if (aad_len >= 0xff00) { @@ -580,7 +581,7 @@ int bt_mesh_net_obfuscate(uint8_t *pdu, uint32_t iv_index, uint8_t tmp[16] = {0}; int err = 0, i; - BT_DBG("IVIndex %u, PrivacyKey %s", iv_index, bt_hex(privacy_key, 16)); + BT_DBG("IVIndex %lu PrivacyKey %s", iv_index, bt_hex(privacy_key, 16)); sys_put_be32(iv_index, &priv_rand[5]); memcpy(&priv_rand[9], &pdu[7], 7); @@ -589,6 +590,7 @@ int bt_mesh_net_obfuscate(uint8_t *pdu, uint32_t iv_index, err = bt_mesh_encrypt_be(privacy_key, priv_rand, tmp); if (err) { + BT_ERR("NetObfuscateFailed (%d)", err); return err; } @@ -606,9 +608,9 @@ int bt_mesh_net_encrypt(const uint8_t key[16], struct net_buf_simple *buf, uint8_t nonce[13] = {0}; int err = 0; - BT_DBG("IVIndex %u EncKey %s mic_len %u", iv_index, bt_hex(key, 16), - mic_len); - BT_DBG("PDU (len %u) %s", buf->len, bt_hex(buf->data, buf->len)); + BT_DBG("IVIndex %u EncKey %s MicLen %u proxy %u/%u", + iv_index, bt_hex(key, 16), mic_len, proxy, proxy_solic); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); #if CONFIG_BLE_MESH_PROXY if (proxy) { @@ -633,6 +635,8 @@ int bt_mesh_net_encrypt(const uint8_t key[16], struct net_buf_simple *buf, NULL, 0, &buf->data[7], mic_len); if (!err) { net_buf_simple_add(buf, mic_len); + } else { + BT_ERR("NetEncryptFailed (%d)", err); } return err; @@ -643,10 +647,11 @@ int bt_mesh_net_decrypt(const uint8_t key[16], struct net_buf_simple *buf, { uint8_t mic_len = NET_MIC_LEN(buf->data); uint8_t nonce[13] = {0}; + int err; - BT_DBG("PDU (%u bytes) %s", buf->len, bt_hex(buf->data, buf->len)); - BT_DBG("iv_index %u, key %s mic_len %u", iv_index, bt_hex(key, 16), - mic_len); + BT_DBG("IVIndex %u EncKey %s MicLen %u proxy %u/%u", + iv_index, bt_hex(key, 16), mic_len, proxy, proxy_solic); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); #if CONFIG_BLE_MESH_PROXY if (proxy) { @@ -669,8 +674,13 @@ int bt_mesh_net_decrypt(const uint8_t key[16], struct net_buf_simple *buf, buf->len -= mic_len; - return bt_mesh_ccm_decrypt(key, nonce, &buf->data[7], buf->len - 7, - NULL, 0, &buf->data[7], mic_len); + err = bt_mesh_ccm_decrypt(key, nonce, &buf->data[7], buf->len - 7, + NULL, 0, &buf->data[7], mic_len); + if (err) { + BT_ERR("NetDecrypt failed (%d)", err); + } + + return err; } static void create_app_nonce(uint8_t nonce[13], bool dev_key, uint8_t aszmic, @@ -698,14 +708,15 @@ int bt_mesh_app_encrypt(const uint8_t key[16], bool dev_key, uint8_t aszmic, uint8_t nonce[13] = {0}; int err = 0; + BT_DBG("AppEncrypt"); BT_DBG("AppKey %s", bt_hex(key, 16)); - BT_DBG("dev_key %u src 0x%04x dst 0x%04x", dev_key, src, dst); - BT_DBG("seq_num 0x%08x iv_index 0x%08x", seq_num, iv_index); - BT_DBG("Clear: %s", bt_hex(buf->data, buf->len)); + BT_DBG("DevKey %u Src 0x%04x Dst 0x%04x", dev_key, src, dst); + BT_DBG("SeqNum 0x%08lx IVIndex 0x%08lx", seq_num, iv_index); + BT_DBG("Data %u %s", buf->len, bt_hex(buf->data, buf->len)); create_app_nonce(nonce, dev_key, aszmic, src, dst, seq_num, iv_index); - BT_DBG("Nonce %s", bt_hex(nonce, 13)); + BT_DBG("Nonce %s", bt_hex(nonce, 13)); err = bt_mesh_ccm_encrypt(key, nonce, buf->data, buf->len, ad, ad ? 16 : 0, buf->data, APP_MIC_LEN(aszmic)); @@ -725,12 +736,12 @@ int bt_mesh_app_decrypt(const uint8_t key[16], bool dev_key, uint8_t aszmic, uint8_t nonce[13] = {0}; int err = 0; - BT_DBG("EncData (len %u) %s", buf->len, bt_hex(buf->data, buf->len)); + BT_DBG("EncData %u %s", buf->len, bt_hex(buf->data, buf->len)); create_app_nonce(nonce, dev_key, aszmic, src, dst, seq_num, iv_index); BT_DBG("AppKey %s", bt_hex(key, 16)); - BT_DBG("Nonce %s", bt_hex(nonce, 13)); + BT_DBG("Nonce %s", bt_hex(nonce, 13)); err = bt_mesh_ccm_decrypt(key, nonce, buf->data, buf->len, ad, ad ? 16 : 0, out->data, APP_MIC_LEN(aszmic)); diff --git a/components/bt/esp_ble_mesh/core/ext_adv.c b/components/bt/esp_ble_mesh/core/ext_adv.c new file mode 100644 index 000000000000..8b85076aedbe --- /dev/null +++ b/components/bt/esp_ble_mesh/core/ext_adv.c @@ -0,0 +1,502 @@ +/* Bluetooth Mesh */ + +/* + * SPDX-FileCopyrightText: 2017 Intel Corporation + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include "mesh/kernel.h" +#include "mesh.h" +#include "mesh/hci.h" +#include "mesh/common.h" +#include "mesh/ffs.h" +#include "ext_adv.h" +#include "beacon.h" +#include "prov_common.h" +#include "foundation.h" +#include "proxy_server.h" +#include "proxy_client.h" +#include "prov_pvnr.h" +#include "mesh/adapter.h" + +#include "adv_common.h" +#include "ble_adv.h" + +static struct bt_mesh_adv_inst *adv_insts; + +static int adv_send(struct bt_mesh_adv_inst *inst, uint16_t *adv_duration) +{ + struct net_buf *buf = inst->sending_buf; + const struct bt_mesh_send_cb *cb = BLE_MESH_ADV(buf)->cb; + void *cb_data = BLE_MESH_ADV(buf)->cb_data; + struct bt_mesh_adv_param param = {0}; + uint16_t duration = 0U, adv_int = 0U; + uint8_t adv_cnt = 0; + struct bt_mesh_adv_data ad = {0}; + int err = 0; +#if CONFIG_BLE_MESH_EXT_ADV + uint8_t is_ext_adv = false; +#endif + + BT_DBG("ExtAdvSend, Type %u", BLE_MESH_ADV(buf)->type); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); + + switch (BLE_MESH_ADV(buf)->type) { +#if CONFIG_BLE_MESH_EXT_ADV + case BLE_MESH_ADV_EXT_PROV: + case BLE_MESH_ADV_EXT_DATA: + case BLE_MESH_ADV_EXT_RELAY_DATA: +#if CONFIG_BLE_MESH_LONG_PACKET + case BLE_MESH_ADV_EXT_LONG_PROV: + case BLE_MESH_ADV_EXT_LONG_DATA: + case BLE_MESH_ADV_EXT_LONG_RELAY_DATA: +#endif /* CONFIG_BLE_MESH_LONG_PACKET */ + { + is_ext_adv = true; + } +#endif /* CONFIG_BLE_MESH_EXT_ADV */ + case BLE_MESH_ADV_PROV: + case BLE_MESH_ADV_DATA: +#if CONFIG_BLE_MESH_FRIEND + case BLE_MESH_ADV_FRIEND: +#endif /* CONFIG_BLE_MESH_FRIEND */ +#if CONFIG_BLE_MESH_RELAY_ADV_BUF + case BLE_MESH_ADV_RELAY_DATA: +#endif /* CONFIG_BLE_MESH_RELAY_ADV_BUF */ +#if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX + case BLE_MESH_ADV_PROXY_SOLIC: +#endif /* CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX */ + case BLE_MESH_ADV_BEACON: + case BLE_MESH_ADV_URI: { +#if CONFIG_BLE_MESH_EXT_ADV + if (is_ext_adv) { + param.primary_phy = EXT_ADV(buf)->primary_phy; + param.secondary_phy = EXT_ADV(buf)->secondary_phy; + param.include_tx_power = EXT_ADV(buf)->include_tx_power; + param.tx_power = EXT_ADV(buf)->tx_power; + } else +#endif + { + param.primary_phy = BLE_MESH_ADV_PRI_PHY_DEFAULT; + param.secondary_phy = BLE_MESH_ADV_SEC_PHY_DEFAULT; + param.include_tx_power = BLE_MESH_TX_POWER_INCLUDE_DEFAULT; + param.tx_power = BLE_MESH_TX_POWER_DEFAULT; + } + + if (BLE_MESH_ADV(buf)->adv_itvl != BLE_MESH_ADV_ITVL_DEFAULT) { + adv_int = MAX(ADV_ITVL_MIN, BLE_MESH_ADV(buf)->adv_itvl); + } else { + adv_int = MAX(ADV_ITVL_MIN, + BLE_MESH_TRANSMIT_INT(BLE_MESH_ADV(buf)->xmit)); + } + + if (BLE_MESH_ADV(buf)->adv_cnt != BLE_MESH_ADV_CNT_DEFAULT) { + adv_cnt = BLE_MESH_ADV(buf)->adv_cnt; + } else { + adv_cnt = BLE_MESH_TRANSMIT_COUNT(BLE_MESH_ADV(buf)->xmit) + 1; + } + + duration = adv_cnt * (adv_int + 10); + + BT_DBG("count %u interval %ums duration %ums", + adv_cnt, adv_int, duration); + + ad.type = adv_type[BLE_MESH_ADV(buf)->type]; + ad.data_len = buf->len; + ad.data = buf->data; + + param.options = 0U; + param.interval_min = ADV_SCAN_UNIT(adv_int); + param.interval_max = param.interval_min; + + param.adv_duration = duration; + param.adv_count = adv_cnt; + + if (BLE_MESH_ADV(buf)->channel_map) { + param.channel_map = BLE_MESH_ADV(buf)->channel_map; + } else { + param.channel_map = BLE_MESH_ADV_CHAN_DEFAULT; + } + +#if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX + if (BLE_MESH_ADV(buf)->type == BLE_MESH_ADV_PROXY_SOLIC) { + bt_mesh_adv_buf_ref_debug(__func__, buf, 3U, BLE_MESH_BUF_REF_SMALL); + + struct bt_mesh_adv_data solic_ad[2] = { + BLE_MESH_ADV_DATA_BYTES(BLE_MESH_DATA_UUID16_ALL, 0x59, 0x18), + BLE_MESH_ADV_DATA(BLE_MESH_DATA_SVC_DATA16, buf->data, buf->len), + }; + + err = bt_le_ext_adv_start(CONFIG_BLE_MESH_ADV_INST_ID, ¶m, + solic_ad, ARRAY_SIZE(solic_ad), NULL, 0); + } else +#endif /* CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX */ + { + bt_mesh_adv_buf_ref_debug(__func__, buf, 4U, BLE_MESH_BUF_REF_SMALL); + + err = bt_le_ext_adv_start(inst->id, ¶m, &ad, 1, NULL, 0); + } + } + break; + +#if CONFIG_BLE_MESH_SUPPORT_BLE_ADV + case BLE_MESH_ADV_BLE: + struct bt_mesh_ble_adv_data data = {0}; + struct bt_mesh_ble_adv_tx *tx = cb_data; + + if (tx == NULL) { + BT_ERR("Invalid adv user data"); + net_buf_unref(buf); + return -EINVAL; + } + + BT_DBG("interval %dms, duration %dms, period %dms, count %d", + ADV_SCAN_INT(tx->param.interval), tx->param.duration, + tx->param.period, tx->param.count); + + data.adv_data_len = tx->buf->data[0]; + if (data.adv_data_len) { + memcpy(data.adv_data, tx->buf->data + 1, data.adv_data_len); + } + data.scan_rsp_data_len = tx->buf->data[data.adv_data_len + 1]; + if (data.scan_rsp_data_len) { + memcpy(data.scan_rsp_data, tx->buf->data + data.adv_data_len + 2, data.scan_rsp_data_len); + } + duration = tx->param.duration; + + bt_mesh_adv_buf_ref_debug(__func__, buf, 3U, BLE_MESH_BUF_REF_SMALL); + + err = bt_mesh_ble_ext_adv_start(inst->id, &tx->param, &data); + break; +#endif /* CONFIG_BLE_MESH_SUPPORT_BLE_ADV */ + + default: + BT_ERR("InvalidAdvType %u", BLE_MESH_ADV(buf)->type); + break; + } + + adv_send_start(duration, err, cb, cb_data); + if (err) { + BT_ERR("Start advertising failed: err %d", err); + return err; + } + + *adv_duration = duration; + + BT_DBG("Advertising started. %u ms", duration); + return 0; +} + +static int find_valid_msg_from_queue(bt_mesh_queue_t *msg_queue, bt_mesh_msg_t *msg) +{ + BT_DBG("FindValidMsgFromQueue"); + + while(uxQueueMessagesWaiting(msg_queue->handle)) { + xQueueReceive(msg_queue->handle, msg, K_WAIT(K_FOREVER)); + + /* In the previous adv task design, only the *buf of messages pushed to the queue + * by adv_update would be empty, but in the new design, there is a new processing + * method for adv_update's messages, so *buf here cannot be empty. + */ + assert(msg->arg); + + BT_DBG("Buf %p Relay %u Busy %u", + BLE_MESH_MSG_NET_BUF(msg), msg->relay, + !!bt_mesh_atomic_get(&BLE_MESH_ADV_BUSY(BLE_MESH_MSG_NET_BUF(msg)))); + + /* If the message is cancelled for advertising, then continue to retrieve the next + * message from that queue. + */ + if (!bt_mesh_atomic_cas(&BLE_MESH_ADV_BUSY(BLE_MESH_MSG_NET_BUF(msg)), 1, 0)) { + bt_mesh_adv_buf_ref_debug(__func__, BLE_MESH_MSG_NET_BUF(msg), 1U, BLE_MESH_BUF_REF_EQUAL); + + /* Cancel the adv task's reference to this data packet. + * Tips: + * The reference of buffer by adv_task occurs when the buffer is pushed into + * the queue. + */ + net_buf_unref(BLE_MESH_MSG_NET_BUF(msg)); + + /* Avoid reading the last message in the queue, which could lead to pointing + * to an invalid buffer due to the absence of other messages in the queue. + */ + msg->arg = NULL; + continue; + } + +#if CONFIG_BLE_MESH_RELAY_ADV_BUF + /* If the relay message should be ignored, then continue to retrieve the next message + * from that queue. + */ + if (msg->relay && bt_mesh_ignore_relay_packet(msg->timestamp)) { + /* If the interval between "current time - msg.timestamp" is bigger than + * BLE_MESH_RELAY_TIME_INTERVAL, this relay packet will not be sent. + */ + BT_DBG("Ignore relay packet"); + + net_buf_unref(BLE_MESH_MSG_NET_BUF(msg)); + msg->arg = NULL; + continue; + } +#endif /* CONFIG_BLE_MESH_RELAY_ADV_BUF */ + + break; + } + + if (msg->arg == NULL) { + return -EINVAL; + } + + return 0; +} + +static int activate_idle_adv_instance(uint32_t *update_evts, uint16_t *min_duration) +{ + uint16_t cur_min_duration = K_FOREVER; + enum bt_mesh_adv_type adv_type = 0; + bt_mesh_queue_t *msg_queue = NULL; + uint16_t duration = K_FOREVER; + bt_mesh_msg_t msg = {0}; + uint32_t spt_mask = 0; + uint32_t evts = 0; + + BT_DBG("ActivateIdleAdvInst"); + +#if (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || \ + CONFIG_BLE_MESH_GATT_PROXY_SERVER + if (!adv_insts[BLE_MESH_ADV_PROXY_INST].busy) { + BT_DBG("Mesh Proxy Advertising start"); + + duration = bt_mesh_proxy_server_adv_start(); + if (duration < cur_min_duration) { + cur_min_duration = duration; + } + + adv_insts[BLE_MESH_ADV_PROXY_INST].busy = true; + evts |= ADV_TASK_ADV_INST_EVT(adv_insts[BLE_MESH_ADV_PROXY_INST].id); + } +#endif + + for (int i = BLE_MESH_ADV_INST; i < BLE_MESH_ADV_INST_TYPES_NUM; i++) { + struct bt_mesh_adv_inst *instance = &adv_insts[i]; + + if (instance->busy +#if (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || \ + CONFIG_BLE_MESH_GATT_PROXY_SERVER + || unlikely(instance->id == CONFIG_BLE_MESH_PROXY_ADV_INST_ID) +#endif + ) { + BT_DBG("AdvInstSkipped, InstID %u Busy %u", instance->id, instance->busy); + continue; + } + + spt_mask = instance->spt_mask; + adv_type = 0; + + while(spt_mask) { + adv_type = find_lsb_set(spt_mask) - 1; + spt_mask &= ~BIT(adv_type); + msg_queue = &(bt_mesh_adv_types_mgmt_get(adv_type)->adv_q->q); + + /* If no new message in the queue, the *buf (aka: msg.arg) will be empty */ + if (find_valid_msg_from_queue(msg_queue, &msg)) { + BT_DBG("NoMsgForAdvInst, InstID %u", instance->id); + continue; + } + + instance->sending_buf = (struct net_buf *)msg.arg; + + if (adv_send(instance, &duration)) { + /* When this adv instance fails to broadcast, it could be due to some + * persistent issues, such as incorrect adv parameter settings, or it + * could be due to some temporary issues, such as memory allocation + * failure. + * + * Therefore, it is advisable to skip subsequent queue reads for this + * instance and attempt to broadcast subsequent data again next time, + * rather than disabling the adv instance. + */ + BT_ERR("AdvSendFailed, InstID %u AdvType %u SptMask %08lx Buf %p", + instance->id, adv_type, instance->spt_mask, instance->sending_buf); + + net_buf_unref(instance->sending_buf); + instance->sending_buf = NULL; + break; + } + + BT_DBG("Activate, InstID %u AdvType %u SptMask %08lx Buf %p Duration %u/%u", + instance->id, adv_type, instance->spt_mask, + instance->sending_buf, duration, cur_min_duration); + + if (duration < cur_min_duration) { + cur_min_duration = duration; + } + + instance->busy = true; + evts |= ADV_TASK_ADV_INST_EVT(adv_insts[i].id); + + /* Must be nullified to avoid affecting the next adv instance's judgment + * on whether the message queue is empty. + */ + msg.arg = NULL; + break; + } + } + + BT_DBG("ActivateEnd, Duration %u UpdateEvts %08lx Evts%08lx", + cur_min_duration, *update_evts, evts); + + *min_duration = cur_min_duration; + *update_evts |= evts; + + return 0; +} + +static uint32_t received_adv_evts_handle(uint32_t recv_evts) +{ + BT_DBG("RecvAdvEvtsHandle, RecvEvts 0x%08lx", recv_evts); + + if (!recv_evts) { + return 0; + } + + for (int i = 0; recv_evts && i < BLE_MESH_ADV_INST_TYPES_NUM; i++) { + uint32_t evt = ADV_TASK_ADV_INST_EVT(adv_insts[i].id); + + if (recv_evts & evt) { + recv_evts &= ~evt; + +#if (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || \ + CONFIG_BLE_MESH_GATT_PROXY_SERVER + if (unlikely(i == BLE_MESH_ADV_PROXY_INST)) { + BT_DBG("Mesh Proxy Advertising auto stop"); + + bt_mesh_proxy_server_adv_flag_set(false); + } else +#endif + { + adv_send_end(0, BLE_MESH_ADV(adv_insts[i].sending_buf)->cb, + BLE_MESH_ADV(adv_insts[i].sending_buf)->cb_data); + + bt_mesh_adv_buf_ref_debug(__func__, adv_insts[i].sending_buf, 4U, BLE_MESH_BUF_REF_SMALL); + + net_buf_unref(adv_insts[i].sending_buf); + adv_insts[i].sending_buf = NULL; + } + + adv_insts[i].busy = false; + } + } + + return recv_evts; +} + +static void adv_thread(void *p) +{ + uint16_t adv_duration = K_FOREVER; + uint32_t recv_evts = 0; + uint32_t wait_evts = 0; + + BT_DBG("ExtAdvThread"); + + while (1) { + adv_duration = K_FOREVER; + wait_evts |= ADV_TASK_PKT_SEND_EVT; + + activate_idle_adv_instance(&wait_evts, &adv_duration); + + bt_mesh_adv_task_wait(wait_evts, adv_duration, &recv_evts); + + BT_DBG("WaitEvts %08lx RecvEvts %08lx", wait_evts, recv_evts); + + wait_evts &= ~recv_evts; + +#if (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || \ + CONFIG_BLE_MESH_GATT_PROXY_SERVER + if (recv_evts & ADV_TASK_PROXY_ADV_UPD_EVT) { + adv_insts[BLE_MESH_ADV_PROXY_INST].busy = false; + recv_evts &= ~ADV_TASK_PROXY_ADV_UPD_EVT; + } +#endif + + /* The `recv_evts == ADV_TASK_PKT_SEND_EVT` indicates that new packets + * have been put into the queue, and the advertising instances started + * previously have not yet been stopped. + */ + if (recv_evts == ADV_TASK_PKT_SEND_EVT) { + continue; + } + + if (recv_evts & ADV_TASK_PKT_SEND_EVT) { + recv_evts &= ~ADV_TASK_PKT_SEND_EVT; + } + + recv_evts = received_adv_evts_handle(recv_evts); + + if (recv_evts) { + BT_ERR("RecvEvts %08lx", recv_evts); + } + } +} + +void bt_mesh_adv_update(void) +{ + BT_DBG("ExtAdvUpdate"); + +#if (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || \ + CONFIG_BLE_MESH_GATT_PROXY_SERVER + BT_DBG("Mesh Proxy Advertising stopped manually"); + + bt_mesh_proxy_server_adv_stop(); + + if (adv_insts[BLE_MESH_ADV_PROXY_INST].busy) { + bt_mesh_adv_task_wakeup(ADV_TASK_PROXY_ADV_UPD_EVT); + } +#endif +} + +void bt_mesh_adv_init(void) +{ + BT_DBG("ExtAdvInit"); + + bt_mesh_adv_common_init(); + + adv_insts = bt_mesh_get_adv_insts_set(); + +#if CONFIG_BLE_MESH_RELAY_ADV_BUF + bt_mesh_relay_adv_init(); +#endif /* CONFIG_BLE_MESH_RELAY_ADV_BUF */ + +#if CONFIG_BLE_MESH_SUPPORT_BLE_ADV + bt_mesh_ble_adv_init(); +#endif /* CONFIG_BLE_MESH_SUPPORT_BLE_ADV */ + + bt_mesh_adv_task_init(adv_thread); +} + +#if CONFIG_BLE_MESH_DEINIT +void bt_mesh_adv_deinit(void) +{ + BT_DBG("ExtAdvDeinit"); + + bt_mesh_adv_task_deinit(); + + bt_mesh_adv_common_deinit(); + + adv_insts = NULL; + +#if CONFIG_BLE_MESH_RELAY_ADV_BUF + bt_mesh_relay_adv_deinit(); +#endif /* CONFIG_BLE_MESH_RELAY_ADV_BUF */ + +#if CONFIG_BLE_MESH_SUPPORT_BLE_ADV + bt_mesh_ble_adv_deinit(); +#endif /* CONFIG_BLE_MESH_SUPPORT_BLE_ADV */ +} +#endif /* CONFIG_BLE_MESH_DEINIT */ diff --git a/components/bt/esp_ble_mesh/core/ext_adv.h b/components/bt/esp_ble_mesh/core/ext_adv.h new file mode 100644 index 000000000000..eaa9c4f81973 --- /dev/null +++ b/components/bt/esp_ble_mesh/core/ext_adv.h @@ -0,0 +1,33 @@ +/* Bluetooth Mesh */ + +/* + * SPDX-FileCopyrightText: 2017 Intel Corporation + * SPDX-FileContributor: 2024-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EXT_ADV_H_ +#define _EXT_ADV_H_ + +#include "mesh/atomic.h" +#include "mesh/access.h" +#include "mesh/adapter.h" +#include "mesh/queue.h" +#include "adv_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void bt_mesh_adv_update(void); + +void bt_mesh_adv_init(void); + +void bt_mesh_adv_deinit(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _EXT_ADV_H_ */ diff --git a/components/bt/esp_ble_mesh/core/fast_prov.c b/components/bt/esp_ble_mesh/core/fast_prov.c index 049a12bb438c..3fe9b742483d 100644 --- a/components/bt/esp_ble_mesh/core/fast_prov.c +++ b/components/bt/esp_ble_mesh/core/fast_prov.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -27,12 +27,15 @@ const uint8_t *bt_mesh_fast_prov_dev_key_get(uint16_t dst) { const uint8_t *key = NULL; + BT_DBG("FastProvDevKeyGet, Dst 0x%04x", dst); + if (!BLE_MESH_ADDR_IS_UNICAST(dst)) { BT_ERR("Invalid unicast address 0x%04x", dst); return NULL; } if (bt_mesh_is_provisioner_en() == false) { + BT_DBG("NodeDevKey"); return bt_mesh.dev_key; } @@ -42,9 +45,11 @@ const uint8_t *bt_mesh_fast_prov_dev_key_get(uint16_t dst) */ key = bt_mesh_provisioner_dev_key_get(dst); if (key) { + BT_DBG("PvnrDevKey"); return key; } + BT_DBG("NodeDevKeyFinal"); return bt_mesh.dev_key; } @@ -53,9 +58,12 @@ struct bt_mesh_subnet *bt_mesh_fast_prov_subnet_get(uint16_t net_idx) struct bt_mesh_subnet *sub = NULL; int i; + BT_DBG("FastProvSubnetGet, NetIdx 0x%04x", net_idx); + for (i = 0; i < ARRAY_SIZE(bt_mesh.sub); i++) { sub = &bt_mesh.sub[i]; if (sub->net_idx == net_idx) { + BT_DBG("NodeSub"); return sub; } } @@ -63,10 +71,12 @@ struct bt_mesh_subnet *bt_mesh_fast_prov_subnet_get(uint16_t net_idx) for (i = 0; i < ARRAY_SIZE(bt_mesh.p_sub); i++) { sub = bt_mesh.p_sub[i]; if (sub && sub->net_idx == net_idx) { + BT_DBG("PvnrSub"); return sub; } } + BT_DBG("NoSub"); return NULL; } @@ -75,10 +85,13 @@ struct bt_mesh_app_key *bt_mesh_fast_prov_app_key_find(uint16_t app_idx) struct bt_mesh_app_key *key = NULL; int i; + BT_DBG("FastProvAppKeyFind, AppIdx 0x%04x", app_idx); + for (i = 0; i < ARRAY_SIZE(bt_mesh.app_keys); i++) { key = &bt_mesh.app_keys[i]; if (key->net_idx != BLE_MESH_KEY_UNUSED && key->app_idx == app_idx) { + BT_DBG("NodeAppKey"); return key; } } @@ -87,15 +100,19 @@ struct bt_mesh_app_key *bt_mesh_fast_prov_app_key_find(uint16_t app_idx) key = bt_mesh.p_app_keys[i]; if (key && key->net_idx != BLE_MESH_KEY_UNUSED && key->app_idx == app_idx) { + BT_DBG("PvnrAppKey"); return key; } } + BT_DBG("NoAppKey"); return NULL; } uint8_t bt_mesh_set_fast_prov_net_idx(uint16_t net_idx) { + BT_DBG("SetFastProvNetIdx, NetIdx 0x%04x", net_idx); + /* Set net_idx for fast provisioning */ bt_mesh_provisioner_set_fast_prov_net_idx(net_idx); @@ -116,6 +133,8 @@ uint8_t bt_mesh_fast_prov_net_key_add(const uint8_t net_key[16]) net_idx = bt_mesh_provisioner_get_fast_prov_net_idx(); bt_mesh.p_net_idx_next = net_idx; + BT_DBG("FastProvNetKeyAdd, NetIdx 0x%04x", net_idx); + err = bt_mesh_provisioner_local_net_key_add(net_key, &net_idx); if (err) { BT_ERR("Invalid NetKeyIndex 0x%04x", net_idx); @@ -130,12 +149,16 @@ const uint8_t *bt_mesh_fast_prov_net_key_get(uint16_t net_idx) { struct bt_mesh_subnet *sub = NULL; + BT_DBG("FastProvNetKeyGet, NetIdx 0x%04x", net_idx); + sub = bt_mesh_fast_prov_subnet_get(net_idx); if (!sub) { BT_ERR("Invalid NetKeyIndex 0x%04x", net_idx); return NULL; } + BT_DBG("KrFlag %u", sub->kr_flag); + return (sub->kr_flag ? sub->keys[1].net : sub->keys[0].net); } @@ -143,17 +166,23 @@ const uint8_t *bt_mesh_get_fast_prov_app_key(uint16_t net_idx, uint16_t app_idx) { struct bt_mesh_app_key *key = NULL; + BT_DBG("GetFastProvAppKey, NetIdx 0x%04x AppIdx 0x%04x", net_idx, app_idx); + key = bt_mesh_fast_prov_app_key_find(app_idx); if (!key) { BT_ERR("Invalid AppKeyIndex 0x%04x", app_idx); return NULL; } + BT_DBG("KeyUpdated %u", key->updated); + return (key->updated ? key->keys[1].val : key->keys[0].val); } uint8_t bt_mesh_set_fast_prov_action(uint8_t action) { + BT_DBG("SetFastProvAction, Action %u", action); + if (!action || action > ACTION_EXIT) { return 0x01; } @@ -168,9 +197,11 @@ uint8_t bt_mesh_set_fast_prov_action(uint8_t action) if (bt_mesh_secure_beacon_get() == BLE_MESH_SECURE_BEACON_ENABLED) { bt_mesh_secure_beacon_disable(); } + if (IS_ENABLED(CONFIG_BLE_MESH_PB_GATT)) { bt_mesh_proxy_client_prov_enable(); } + bt_mesh_provisioner_set_primary_elem_addr(bt_mesh_primary_addr()); bt_mesh_provisioner_set_prov_bearer(BLE_MESH_PROV_ADV, false); bt_mesh_provisioner_fast_prov_enable(true); @@ -179,11 +210,15 @@ uint8_t bt_mesh_set_fast_prov_action(uint8_t action) if (IS_ENABLED(CONFIG_BLE_MESH_PB_GATT)) { bt_mesh_proxy_client_prov_disable(); } + if (bt_mesh_secure_beacon_get() == BLE_MESH_SECURE_BEACON_ENABLED) { bt_mesh_secure_beacon_enable(); } + bt_mesh_atomic_and(bt_mesh.flags, ~(BIT(BLE_MESH_PROVISIONER) | BIT(BLE_MESH_VALID_PROV))); + bt_mesh_provisioner_fast_prov_enable(false); + if (action == ACTION_EXIT) { bt_mesh_provisioner_remove_node(NULL); } @@ -191,4 +226,5 @@ uint8_t bt_mesh_set_fast_prov_action(uint8_t action) return 0x0; } + #endif /* CONFIG_BLE_MESH_FAST_PROV */ diff --git a/components/bt/esp_ble_mesh/core/foundation.h b/components/bt/esp_ble_mesh/core/foundation.h index 4f3aa79ad11a..66f8c5ea2b8c 100644 --- a/components/bt/esp_ble_mesh/core/foundation.h +++ b/components/bt/esp_ble_mesh/core/foundation.h @@ -287,6 +287,7 @@ uint8_t bt_mesh_default_ttl_get(void); void bt_mesh_subnet_del(struct bt_mesh_subnet *sub, bool store); struct bt_mesh_app_key *bt_mesh_app_key_alloc(uint16_t app_idx); + void bt_mesh_app_key_del(struct bt_mesh_app_key *key, bool store); static inline void key_idx_pack(struct net_buf_simple *buf, diff --git a/components/bt/esp_ble_mesh/core/friend.c b/components/bt/esp_ble_mesh/core/friend.c index aa9607492b22..e31810e26326 100644 --- a/components/bt/esp_ble_mesh/core/friend.c +++ b/components/bt/esp_ble_mesh/core/friend.c @@ -91,6 +91,9 @@ static struct bt_mesh_adv *adv_alloc(int id) static bool is_lpn_unicast(struct bt_mesh_friend *frnd, uint16_t addr) { + BT_INFO("IsLPNUnicast, LPN 0x%04x NumElem %u Addr 0x%04x", + frnd->lpn, frnd->num_elem, addr); + if (frnd->lpn == BLE_MESH_ADDR_UNASSIGNED) { return false; } @@ -103,11 +106,16 @@ struct bt_mesh_friend *bt_mesh_friend_find(uint16_t net_idx, uint16_t lpn_addr, { int i; - BT_DBG("net_idx 0x%04x lpn_addr 0x%04x", net_idx, lpn_addr); + BT_DBG("FrndFind"); + BT_DBG("NetIdx 0x%04x LPN 0x%04x Valid %u Established %u", + net_idx, lpn_addr, valid, established); for (i = 0; i < ARRAY_SIZE(bt_mesh.frnd); i++) { struct bt_mesh_friend *frnd = &bt_mesh.frnd[i]; + BT_DBG("%u: LPN 0x%04x NetIdx 0x%04x Valid %u Established %u", + i, frnd->lpn, frnd->net_idx, frnd->valid, frnd->established); + if (valid && !frnd->valid) { continue; } @@ -130,11 +138,15 @@ struct bt_mesh_friend *bt_mesh_friend_find(uint16_t net_idx, uint16_t lpn_addr, static void purge_buffers(sys_slist_t *list) { + BT_DBG("PurgeBuffers"); + while (!sys_slist_is_empty(list)) { struct net_buf *buf = NULL; buf = (void *)sys_slist_get_not_empty(list); + BT_DBG("Buf %p Ref %u", buf, buf->ref); + buf->frags = NULL; buf->flags &= ~NET_BUF_FRAGS; @@ -149,18 +161,21 @@ static void purge_buffers(sys_slist_t *list) */ static int32_t recv_delay(struct bt_mesh_friend *frnd) { + BT_DBG("RecvDelay, LPN 0x%04x RecvWin %u RecvDelay %u", + frnd->lpn, CONFIG_BLE_MESH_FRIEND_RECV_WIN, frnd->recv_delay); + #if CONFIG_BLE_MESH_FRIEND_RECV_WIN > 50 return (int32_t)frnd->recv_delay + (CONFIG_BLE_MESH_FRIEND_RECV_WIN / 5); -#else +#else /* CONFIG_BLE_MESH_FRIEND_RECV_WIN > 50 */ return frnd->recv_delay; -#endif +#endif /* CONFIG_BLE_MESH_FRIEND_RECV_WIN > 50 */ } static void friend_clear(struct bt_mesh_friend *frnd, uint8_t reason) { int i; - BT_DBG("LPN 0x%04x", frnd->lpn); + BT_DBG("FrndClear, LPN 0x%04x Reason 0x%02x", frnd->lpn, reason); k_delayed_work_cancel(&frnd->timer); @@ -182,9 +197,13 @@ static void friend_clear(struct bt_mesh_friend *frnd, uint8_t reason) friend_cred_del(frnd->net_idx, frnd->lpn); if (frnd->last) { + BT_DBG("FrndLast, Buf %p Ref %u PendingBuf %u", + frnd->last, frnd->last->ref, frnd->pending_buf); + /* Cancel the sending if necessary */ if (frnd->pending_buf) { bt_mesh_adv_buf_ref_debug(__func__, frnd->last, 2U, BLE_MESH_BUF_REF_EQUAL); + bt_mesh_atomic_set(&BLE_MESH_ADV_BUSY(frnd->last), 0); } else { bt_mesh_adv_buf_ref_debug(__func__, frnd->last, 1U, BLE_MESH_BUF_REF_EQUAL); @@ -199,6 +218,8 @@ static void friend_clear(struct bt_mesh_friend *frnd, uint8_t reason) for (i = 0; i < ARRAY_SIZE(frnd->seg); i++) { struct bt_mesh_friend_seg *seg = &frnd->seg[i]; + BT_DBG("%u: SegCount %u", i, seg->seg_count); + purge_buffers(&seg->queue); seg->seg_count = 0U; } @@ -216,11 +237,13 @@ void bt_mesh_friend_clear_net_idx(uint16_t net_idx) { int i; - BT_DBG("net_idx 0x%04x", net_idx); + BT_DBG("FrndClearNetIdx, NetIdx 0x%04x", net_idx); for (i = 0; i < ARRAY_SIZE(bt_mesh.frnd); i++) { struct bt_mesh_friend *frnd = &bt_mesh.frnd[i]; + BT_DBG("%u: LPN 0x%04x NetIdx 0x%04x", i, frnd->lpn, frnd->net_idx); + if (frnd->net_idx == BLE_MESH_KEY_UNUSED) { continue; } @@ -235,11 +258,13 @@ void bt_mesh_friend_sec_update(uint16_t net_idx) { int i; - BT_DBG("net_idx 0x%04x", net_idx); + BT_DBG("FrndSecUpdate, NetIdx 0x%04x", net_idx); for (i = 0; i < ARRAY_SIZE(bt_mesh.frnd); i++) { struct bt_mesh_friend *frnd = &bt_mesh.frnd[i]; + BT_DBG("%u: NetIdx 0x%04x", i, frnd->net_idx); + if (frnd->net_idx == BLE_MESH_KEY_UNUSED) { continue; } @@ -279,19 +304,21 @@ int bt_mesh_friend_clear(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) }; struct bt_mesh_ctl_friend_clear_confirm cfm = {0}; + BT_DBG("FrndClear, NetIdx 0x%04x", rx->sub->net_idx); + if (buf->len < sizeof(*msg)) { - BT_WARN("Too short Friend Clear (len %d)", buf->len); + BT_WARN("Too short FriendClear (len %d)", buf->len); return -EINVAL; } lpn_addr = sys_be16_to_cpu(msg->lpn_addr); lpn_counter = sys_be16_to_cpu(msg->lpn_counter); - BT_DBG("LPN addr 0x%04x counter 0x%04x", lpn_addr, lpn_counter); + BT_DBG("LPN 0x%04x Counter %u", lpn_addr, lpn_counter); frnd = bt_mesh_friend_find(rx->sub->net_idx, lpn_addr, false, false); if (!frnd) { - BT_WARN("No matching LPN addr 0x%04x", lpn_addr); + BT_WARN("NoMatchLPN, Addr 0x%04x", lpn_addr); return 0; } @@ -327,6 +354,8 @@ static bool friend_sub_exist(struct bt_mesh_friend *frnd, uint16_t addr) { int i; + BT_DBG("IsFrndSubExist, Addr 0x%04x", addr); + for (i = 0; i < ARRAY_SIZE(frnd->sub_list); i++) { if (frnd->sub_list[i] == addr) { return true; @@ -340,6 +369,8 @@ static void friend_sub_add(struct bt_mesh_friend *frnd, uint16_t addr) { int i; + BT_DBG("FrndSubAdd, Addr 0x%04x", addr); + for (i = 0; i < ARRAY_SIZE(frnd->sub_list); i++) { if (frnd->sub_list[i] == BLE_MESH_ADDR_UNASSIGNED) { frnd->sub_list[i] = addr; @@ -354,6 +385,8 @@ static void friend_sub_rem(struct bt_mesh_friend *frnd, uint16_t addr) { int i; + BT_DBG("FrndSubRem, Addr 0x%04x", addr); + for (i = 0; i < ARRAY_SIZE(frnd->sub_list); i++) { if (frnd->sub_list[i] == addr) { frnd->sub_list[i] = BLE_MESH_ADDR_UNASSIGNED; @@ -408,6 +441,10 @@ static int unseg_app_sdu_unpack(struct bt_mesh_friend *frnd, uint16_t app_idx = FRIEND_ADV(buf)->app_idx; int err = 0; + BT_DBG("UnsegAppSduUnpack"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x RecvDst 0x%04x", + frnd->net_idx, app_idx, meta->net.ctx.recv_dst); + meta->subnet = friend_subnet_get(frnd->net_idx); if (!meta->subnet) { BT_ERR("Invalid subnet for unseg app sdu"); @@ -416,6 +453,7 @@ static int unseg_app_sdu_unpack(struct bt_mesh_friend *frnd, meta->is_dev_key = (app_idx == BLE_MESH_KEY_DEV); bt_mesh_net_header_parse(&buf->b, &meta->net); + err = bt_mesh_upper_key_get(meta->subnet, app_idx, &meta->key, &meta->aid, meta->net.ctx.addr); if (err) { @@ -446,6 +484,8 @@ static int unseg_app_sdu_decrypt(struct bt_mesh_friend *frnd, net_buf_simple_pull(&sdu, 10); sdu.len -= 4; + BT_DBG("UnsegAppSduDecrypt, SduLen %u", sdu.len); + return bt_mesh_app_decrypt(meta->key, meta->is_dev_key, 0, &sdu, &sdu, meta->ad, meta->net.ctx.addr, meta->net.ctx.recv_dst, meta->net.seq, @@ -462,6 +502,8 @@ static int unseg_app_sdu_encrypt(struct bt_mesh_friend *frnd, net_buf_simple_pull(&sdu, 10); sdu.len -= 4; + BT_DBG("UnsegAppSduEncrypt, SduLen %u", sdu.len); + return bt_mesh_app_encrypt(meta->key, meta->is_dev_key, 0, &sdu, meta->ad, meta->net.ctx.addr, meta->net.ctx.recv_dst, bt_mesh.seq, @@ -474,6 +516,10 @@ static int unseg_app_sdu_prepare(struct bt_mesh_friend *frnd, struct unseg_app_sdu_meta meta = {0}; int err = 0; + BT_DBG("UnsegAppSduPrepare"); + BT_DBG("LPN 0x%04x AppIdx 0x%04x Buf %p", + frnd->lpn, FRIEND_ADV(buf)->app_idx, buf); + if (FRIEND_ADV(buf)->app_idx == BLE_MESH_KEY_UNUSED) { return 0; } @@ -487,6 +533,7 @@ static int unseg_app_sdu_prepare(struct bt_mesh_friend *frnd, * unchanged. */ if (meta.net.seq == bt_mesh.seq) { + BT_DBG("Seq 0x%06x", bt_mesh.seq); return 0; } @@ -514,8 +561,11 @@ static int encrypt_friend_pdu(struct bt_mesh_friend *frnd, struct net_buf *buf, uint8_t nid = 0U; int err = 0; + BT_DBG("EncryptFrndPDU, LPN 0x%04x NetIdx 0x%04x Cred %u", + frnd->lpn, frnd->net_idx, master_cred); + if (!sub) { - BT_ERR("Invalid subnet to encrypt friend pdu"); + BT_ERR("NoSubToEncryptFrndPDU"); return -EINVAL; } @@ -525,7 +575,7 @@ static int encrypt_friend_pdu(struct bt_mesh_friend *frnd, struct net_buf *buf, nid = sub->keys[sub->kr_flag].nid; } else { if (friend_cred_get(sub, frnd->lpn, &nid, &enc, &priv)) { - BT_ERR("friend_cred_get failed"); + BT_ERR("FrndCredNotFound"); return -ENOENT; } } @@ -538,6 +588,7 @@ static int encrypt_friend_pdu(struct bt_mesh_friend *frnd, struct net_buf *buf, if (FRIEND_ADV(buf)->app_idx != BLE_MESH_KEY_UNUSED) { err = unseg_app_sdu_prepare(frnd, buf); if (err) { + BT_DBG("UnsegAppSduPrepareFailed, Err %d", err); return err; } } @@ -552,15 +603,15 @@ static int encrypt_friend_pdu(struct bt_mesh_friend *frnd, struct net_buf *buf, iv_index = (bt_mesh.iv_index - ((bt_mesh.iv_index & 1) != ivi)); } + BT_DBG("Src 0x%04x NID 0x%02x IVIndex 0x%08lx", src, nid, iv_index); + buf->data[0] = (nid | (iv_index & 1) << 7); if (bt_mesh_net_encrypt(enc, &buf->b, iv_index, false, false)) { - BT_ERR("Encrypting failed"); return -EINVAL; } if (bt_mesh_net_obfuscate(buf->data, iv_index, priv)) { - BT_ERR("Obfuscating failed"); return -EINVAL; } @@ -573,7 +624,7 @@ static struct net_buf *encode_friend_ctl(struct bt_mesh_friend *frnd, { struct friend_pdu_info info = {0}; - BT_DBG("LPN 0x%04x", frnd->lpn); + BT_DBG("EncodeFrndCTL"); net_buf_simple_push_u8(sdu, TRANS_CTL_HDR(ctl_op, 0)); @@ -587,21 +638,25 @@ static struct net_buf *encode_friend_ctl(struct bt_mesh_friend *frnd, info.iv_index = BLE_MESH_NET_IVI_TX; + BT_DBG("CTLOp 0x%02x IVIndex 0x%08lx", ctl_op, info.iv_index); + return create_friend_pdu(frnd, &info, sdu); } static struct net_buf *encode_update(struct bt_mesh_friend *frnd, uint8_t md) { + struct bt_mesh_subnet *sub = friend_subnet_get(frnd->net_idx); struct bt_mesh_ctl_friend_update *upd = NULL; NET_BUF_SIMPLE_DEFINE(sdu, 1 + sizeof(*upd)); - struct bt_mesh_subnet *sub = friend_subnet_get(frnd->net_idx); + + BT_DBG("EncodeUpdate, NetIdx 0x%04x", frnd->net_idx); if (!sub) { BT_ERR("Friend subnet 0x%04x not found", frnd->net_idx); return NULL; } - BT_DBG("lpn 0x%04x md 0x%02x", frnd->lpn, md); + BT_DBG("LPN 0x%04x MD %u", frnd->lpn, md); net_buf_simple_reserve(&sdu, 1); @@ -619,7 +674,7 @@ static void enqueue_sub_cfm(struct bt_mesh_friend *frnd, uint8_t xact) NET_BUF_SIMPLE_DEFINE(sdu, 1 + sizeof(*cfm)); struct net_buf *buf = NULL; - BT_DBG("lpn 0x%04x xact 0x%02x", frnd->lpn, xact); + BT_DBG("EnqueueSubCFM, LPN 0x%04x Xact 0x%02x", frnd->lpn, xact); net_buf_simple_reserve(&sdu, 1); @@ -637,7 +692,7 @@ static void enqueue_sub_cfm(struct bt_mesh_friend *frnd, uint8_t xact) } if (frnd->last) { - BT_DBG("Discarding last PDU"); + BT_DBG("DiscardFrndLast, Buf %p Ref %u", frnd->last, frnd->last->ref); net_buf_unref(frnd->last); } @@ -647,9 +702,12 @@ static void enqueue_sub_cfm(struct bt_mesh_friend *frnd, uint8_t xact) static void friend_recv_delay(struct bt_mesh_friend *frnd) { + int32_t delay = recv_delay(frnd); + + BT_INFO("FrndRecvDelay, Delay %ld", delay); + frnd->pending_req = 1U; - k_delayed_work_submit(&frnd->timer, recv_delay(frnd)); - BT_INFO("Waiting RecvDelay of %d ms", recv_delay(frnd)); + k_delayed_work_submit(&frnd->timer, delay); } int bt_mesh_friend_sub_add(struct bt_mesh_net_rx *rx, @@ -658,6 +716,8 @@ int bt_mesh_friend_sub_add(struct bt_mesh_net_rx *rx, struct bt_mesh_friend *frnd = NULL; uint8_t xact = 0U; + BT_DBG("FrndSubAdd"); + if (buf->len < BLE_MESH_FRIEND_SUB_MIN_LEN) { BT_WARN("Too short Friend Subscription Add (len %d)", buf->len); return -EINVAL; @@ -665,7 +725,7 @@ int bt_mesh_friend_sub_add(struct bt_mesh_net_rx *rx, frnd = bt_mesh_friend_find(rx->sub->net_idx, rx->ctx.addr, true, true); if (!frnd) { - BT_WARN("No matching LPN addr 0x%04x", rx->ctx.addr); + BT_WARN("NoMatchLPN, Addr 0x%04x", rx->ctx.addr); return 0; } @@ -689,6 +749,7 @@ int bt_mesh_friend_sub_add(struct bt_mesh_net_rx *rx, } if (friend_sub_exist(frnd, addr)) { + BT_DBG("FrndSubExist, Addr 0x%04x", addr); continue; } @@ -699,9 +760,9 @@ int bt_mesh_friend_sub_add(struct bt_mesh_net_rx *rx, #if CONFIG_BLE_MESH_DF_SRV return bt_mesh_directed_friend_solicitation(frnd, rx->sub); -#else +#else /* CONFIG_BLE_MESH_DF_SRV */ return 0; -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ } int bt_mesh_friend_sub_rem(struct bt_mesh_net_rx *rx, @@ -710,6 +771,8 @@ int bt_mesh_friend_sub_rem(struct bt_mesh_net_rx *rx, struct bt_mesh_friend *frnd = NULL; uint8_t xact = 0U; + BT_DBG("FrndSubRem"); + if (buf->len < BLE_MESH_FRIEND_SUB_MIN_LEN) { BT_WARN("Too short Friend Subscription Remove (len %d)", buf->len); return -EINVAL; @@ -717,7 +780,7 @@ int bt_mesh_friend_sub_rem(struct bt_mesh_net_rx *rx, frnd = bt_mesh_friend_find(rx->sub->net_idx, rx->ctx.addr, true, true); if (!frnd) { - BT_WARN("No matching LPN addr 0x%04x", rx->ctx.addr); + BT_WARN("NoMatchLPN, Addr 0x%04x", rx->ctx.addr); return 0; } @@ -736,7 +799,7 @@ int bt_mesh_friend_sub_rem(struct bt_mesh_net_rx *rx, if (!BLE_MESH_ADDR_IS_GROUP(addr) && !BLE_MESH_ADDR_IS_VIRTUAL(addr) && !BLE_MESH_ADDR_IS_FIXED_GROUP(addr)) { - BT_WARN("Invalid friend sub addr 0x%04x to remove", addr); + BT_WARN("InvalidFrndSub, Addr 0x%04x", addr); continue; } @@ -750,6 +813,8 @@ int bt_mesh_friend_sub_rem(struct bt_mesh_net_rx *rx, static void enqueue_buf(struct bt_mesh_friend *frnd, struct net_buf *buf) { + BT_DBG("EnqueueBuf, Buf %p QueueSize %u", buf, frnd->queue_size); + net_buf_slist_put(&frnd->queue, buf); frnd->queue_size++; } @@ -758,6 +823,8 @@ static void enqueue_update(struct bt_mesh_friend *frnd, uint8_t md) { struct net_buf *buf = NULL; + BT_DBG("EnqueueUpdate, LPN 0x%04x MD %u", frnd->lpn, md); + buf = encode_update(frnd, md); if (!buf) { BT_ERR("Unable to encode Friend Update"); @@ -772,6 +839,8 @@ int bt_mesh_friend_poll(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) struct bt_mesh_ctl_friend_poll *msg = (void *)buf->data; struct bt_mesh_friend *frnd = NULL; + BT_DBG("FrndPoll"); + if (buf->len < sizeof(*msg)) { BT_WARN("Too short Friend Poll (len %d)", buf->len); return -EINVAL; @@ -779,7 +848,7 @@ int bt_mesh_friend_poll(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) frnd = bt_mesh_friend_find(rx->sub->net_idx, rx->ctx.addr, true, false); if (!frnd) { - BT_WARN("No matching LPN addr 0x%04x", rx->ctx.addr); + BT_WARN("NoMatchLPN, Addr 0x%04x", rx->ctx.addr); return 0; } @@ -793,12 +862,13 @@ int bt_mesh_friend_poll(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) return 0; } - BT_DBG("msg->fsn %u frnd->fsn %u", (msg->fsn & 1), frnd->fsn); + BT_DBG("MsgFSN %u FrndFSN %u", (msg->fsn & 1), frnd->fsn); friend_recv_delay(frnd); if (!frnd->established) { - BT_INFO("Friendship established with 0x%04x", frnd->lpn); + BT_INFO("Friendship established with LPN 0x%04x", frnd->lpn); + frnd->established = 1U; if (friend_cb) { friend_cb(true, frnd->lpn, 0); @@ -806,7 +876,8 @@ int bt_mesh_friend_poll(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) } if (msg->fsn == frnd->fsn && frnd->last) { - BT_DBG("Re-sending last PDU"); + BT_DBG("ResendFrndLast"); + frnd->send_last = 1U; } else { if (frnd->last) { @@ -817,8 +888,8 @@ int bt_mesh_friend_poll(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) frnd->fsn = msg->fsn; if (sys_slist_is_empty(&frnd->queue)) { + BT_DBG("EnqueueFrndUpdate"); enqueue_update(frnd, 0); - BT_DBG("Enqueued Friend Update to empty queue"); } } @@ -829,6 +900,8 @@ static struct bt_mesh_friend *find_clear(uint16_t prev_friend) { int i; + BT_DBG("FindClear, PrevFrnd 0x%04x", prev_friend); + for (i = 0; i < ARRAY_SIZE(bt_mesh.frnd); i++) { struct bt_mesh_friend *frnd = &bt_mesh.frnd[i]; @@ -844,6 +917,8 @@ static void friend_clear_sent(int err, void *user_data) { struct bt_mesh_friend *frnd = user_data; + BT_DBG("FrndClearSent, RepeatSec %u Err %d", frnd->clear.repeat_sec, err); + k_delayed_work_submit(&frnd->clear.timer, K_SECONDS(frnd->clear.repeat_sec)); frnd->clear.repeat_sec *= 2U; @@ -875,6 +950,8 @@ static void send_friend_clear(struct bt_mesh_friend *frnd) .lpn_counter = sys_cpu_to_be16(frnd->lpn_counter), }; + BT_DBG("SendFrndClear, Addr 0x%04x", frnd->clear.frnd); + if (!tx.sub) { BT_ERR("Invalid subnet for Friend Clear"); return; @@ -886,13 +963,15 @@ static void send_friend_clear(struct bt_mesh_friend *frnd) static void clear_timeout(struct k_work *work) { - struct bt_mesh_friend *frnd = CONTAINER_OF(work, struct bt_mesh_friend, - clear.timer.work); + struct bt_mesh_friend *frnd = CONTAINER_OF(work, struct bt_mesh_friend, clear.timer.work); uint32_t duration = 0U; - BT_DBG("LPN 0x%04x (old) Friend 0x%04x", frnd->lpn, frnd->clear.frnd); - duration = k_uptime_get_32() - frnd->clear.start; + + BT_DBG("ClearTimeout"); + BT_DBG("LPN 0x%04x Frnd 0x%04x Duration %lu PollTo %ld", + frnd->lpn, frnd->clear.frnd, duration, frnd->poll_to); + if (duration > 2 * frnd->poll_to) { BT_DBG("Clear Procedure timer expired"); frnd->clear.frnd = BLE_MESH_ADDR_UNASSIGNED; @@ -904,11 +983,13 @@ static void clear_timeout(struct k_work *work) static void clear_procedure_start(struct bt_mesh_friend *frnd) { - BT_DBG("LPN 0x%04x (old) Friend 0x%04x", frnd->lpn, frnd->clear.frnd); - frnd->clear.start = k_uptime_get_32(); frnd->clear.repeat_sec = 1U; + BT_DBG("ClearProcedureStart"); + BT_DBG("LPN 0x%04x Frnd 0x%04x ClearStart %lu", + frnd->lpn, frnd->clear.frnd, frnd->clear.start); + send_friend_clear(frnd); } @@ -919,6 +1000,8 @@ int bt_mesh_friend_clear_cfm(struct bt_mesh_net_rx *rx, struct bt_mesh_friend *frnd = NULL; uint16_t lpn_addr = 0U, lpn_counter = 0U; + BT_DBG("FrndClearCFM"); + if (buf->len < sizeof(*msg)) { BT_WARN("Too short Friend Clear Confirm (len %d)", buf->len); return -EINVAL; @@ -956,6 +1039,9 @@ static void enqueue_offer(struct bt_mesh_friend *frnd, int8_t rssi) NET_BUF_SIMPLE_DEFINE(sdu, 1 + sizeof(*off)); struct net_buf *buf = NULL; + BT_DBG("EnqueueOffset"); + BT_DBG("LPN 0x%04x Counter %u Rssi %d", frnd->lpn, frnd->counter, rssi); + net_buf_simple_reserve(&sdu, 1); off = net_buf_simple_add(&sdu, sizeof(*off)); @@ -1000,7 +1086,7 @@ static int32_t offer_delay(struct bt_mesh_friend *frnd, int8_t rssi, uint8_t cri static const uint8_t fact[] = { 10, 15, 20, 25 }; int32_t delay = 0; - BT_INFO("ReceiveWindowFactor %u ReceiveWindow %u RSSIFactor %u RSSI %d", + BT_INFO("RecvWinFactor %u RecvWin %u RssiFactor %u Rssi %d", fact[RECV_WIN_FACT(crit)], RECV_WIN, fact[RSSI_FACT(crit)], rssi); @@ -1009,7 +1095,7 @@ static int32_t offer_delay(struct bt_mesh_friend *frnd, int8_t rssi, uint8_t cri delay -= (int32_t)fact[RSSI_FACT(crit)] * rssi; delay /= 10; - BT_DBG("Local Delay calculated as %d ms", delay); + BT_DBG("OfferDelay %d", delay); if (delay < 100) { return K_MSEC(100); @@ -1025,13 +1111,15 @@ int bt_mesh_friend_req(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) uint32_t poll_to = 0U; int i; + BT_DBG("FrndReq"); + if (buf->len < sizeof(*msg)) { BT_WARN("Too short Friend Request (len %d)", buf->len); return -EINVAL; } if (msg->recv_delay <= 0x09) { - BT_WARN("Prohibited ReceiveDelay (0x%02x)", msg->recv_delay); + BT_WARN("Prohibited RecvDelay (0x%02x)", msg->recv_delay); return -EINVAL; } @@ -1058,7 +1146,7 @@ int bt_mesh_friend_req(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) } if (CONFIG_BLE_MESH_FRIEND_QUEUE_SIZE < MIN_QUEUE_SIZE(msg->criteria)) { - BT_WARN("We have a too small Friend Queue size (%u < %u)", + BT_WARN("Too small Friend Queue size (%u < %u)", CONFIG_BLE_MESH_FRIEND_QUEUE_SIZE, MIN_QUEUE_SIZE(msg->criteria)); return 0; @@ -1093,11 +1181,10 @@ int bt_mesh_friend_req(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) frnd->lpn_counter = sys_be16_to_cpu(msg->lpn_counter); frnd->clear.frnd = sys_be16_to_cpu(msg->prev_addr); - BT_INFO("LPN 0x%04x rssi %d recv_delay %u poll_to %ums", - frnd->lpn, rx->ctx.recv_rssi, frnd->recv_delay, frnd->poll_to); + BT_INFO("LPN 0x%04x Rssi %d RecvDelay %u PollTo %u", + frnd->lpn, rx->ctx.recv_rssi, frnd->recv_delay, frnd->poll_to); - /** - * Spec says: + /* Spec says: * After a friendship has been established, if the PreviousAddress field * of the Friend Request message contains a valid unicast address that is * not the Friend node’s own unicast address, then the Friend node shall @@ -1109,11 +1196,9 @@ int bt_mesh_friend_req(struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) } k_delayed_work_submit(&frnd->timer, - offer_delay(frnd, rx->ctx.recv_rssi, - msg->criteria)); + offer_delay(frnd, rx->ctx.recv_rssi, msg->criteria)); - friend_cred_create(rx->sub, frnd->lpn, frnd->lpn_counter, - frnd->counter); + friend_cred_create(rx->sub, frnd->lpn, frnd->lpn_counter, frnd->counter); enqueue_offer(frnd, rx->ctx.recv_rssi); @@ -1127,6 +1212,8 @@ static bool is_seg(struct bt_mesh_friend_seg *seg, uint16_t src, uint16_t seq_ze uint16_t buf_seq_zero = 0U; uint16_t buf_src = 0U; + BT_DBG("IsSeg, Buf %p", buf); + if (!buf) { return false; } @@ -1148,6 +1235,9 @@ static struct bt_mesh_friend_seg *get_seg(struct bt_mesh_friend *frnd, struct bt_mesh_friend_seg *unassigned = NULL; int i; + BT_DBG("GetSeg, Src 0x%04x SeqZero 0x%04x SegCount %u", + src, seq_zero, seg_count); + for (i = 0; i < ARRAY_SIZE(frnd->seg); i++) { struct bt_mesh_friend_seg *seg = &frnd->seg[i]; @@ -1173,15 +1263,18 @@ static void enqueue_friend_pdu(struct bt_mesh_friend *frnd, struct net_buf *buf) { struct bt_mesh_friend_seg *seg = NULL; + uint16_t seq_zero = 0; - BT_DBG("type %u", type); + BT_DBG("EnqueueFrndPDU, Type %u", type); if (type == BLE_MESH_FRIEND_PDU_SINGLE) { enqueue_buf(frnd, buf); return; } - uint16_t seq_zero = (((buf->data[10] << 8 | buf->data[11]) >> 2) & TRANS_SEQ_ZERO_MASK); + seq_zero = (((buf->data[10] << 8 | buf->data[11]) >> 2) & TRANS_SEQ_ZERO_MASK); + + BT_DBG("Src 0x%04x SegCount %u SegZero 0x%04x", src, seg_count, seq_zero); seg = get_seg(frnd, src, seq_zero, seg_count); if (!seg) { @@ -1207,7 +1300,7 @@ static void buf_send_start(uint16_t duration, int err, void *user_data) { struct bt_mesh_friend *frnd = user_data; - BT_DBG("err %d", err); + BT_DBG("BufSendStart, Err %d", err); frnd->pending_buf = 0U; @@ -1222,7 +1315,7 @@ static void buf_send_end(int err, void *user_data) { struct bt_mesh_friend *frnd = user_data; - BT_DBG("err %d", err); + BT_DBG("BufSendEnd, Err %d", err); if (frnd->pending_req) { BT_WARN("Another request before previous completed sending"); @@ -1230,47 +1323,48 @@ static void buf_send_end(int err, void *user_data) } if (frnd->established) { + BT_DBG("WaitForNextPoll %u", frnd->poll_to); + k_delayed_work_submit(&frnd->timer, frnd->poll_to); - BT_DBG("Waiting %u ms for next poll", frnd->poll_to); } else { /* Friend offer timeout is 1 second */ + BT_DBG("WaitForFirstPoll"); + k_delayed_work_submit(&frnd->timer, K_SECONDS(1)); - BT_DBG("Waiting for first poll"); } } static void friend_timeout(struct k_work *work) { - struct bt_mesh_friend *frnd = CONTAINER_OF(work, struct bt_mesh_friend, - timer.work); + struct bt_mesh_friend *frnd = CONTAINER_OF(work, struct bt_mesh_friend, timer.work); static const struct bt_mesh_send_cb buf_sent_cb = { .start = buf_send_start, .end = buf_send_end, }; + BT_DBG("FrndTimeout"); + if (frnd->pending_buf != 0U) { BT_ERR("Previous buffer not yet sent!"); return; } - BT_DBG("lpn 0x%04x send_last %u last %p", frnd->lpn, - frnd->send_last, frnd->last); + BT_DBG("LPN 0x%04x SendLast %u FrndLast %p", frnd->lpn, frnd->send_last, frnd->last); if (frnd->send_last && frnd->last) { - BT_DBG("Sending frnd->last %p", frnd->last); frnd->send_last = 0U; goto send_last; } if (frnd->established && !frnd->pending_req) { - BT_WARN("Friendship lost with 0x%04x", frnd->lpn); + BT_WARN("FriendshipLost, LPN 0x%04x", frnd->lpn); friend_clear(frnd, BLE_MESH_FRIENDSHIP_TERMINATE_POLL_TIMEOUT); return; } frnd->last = (void *)sys_slist_get(&frnd->queue); if (!frnd->last) { - BT_WARN("Friendship not established with 0x%04x", frnd->lpn); + BT_WARN("FriendshipNotEstablished, LPN 0x%04x", frnd->lpn); friend_clear(frnd, BLE_MESH_FRIENDSHIP_TERMINATE_ESTABLISH_FAIL); return; } @@ -1283,8 +1377,9 @@ static void friend_timeout(struct k_work *work) frnd->last->flags &= ~NET_BUF_FRAGS; frnd->last->frags = NULL; - BT_DBG("Sending buf %p from Friend Queue of LPN 0x%04x", - frnd->last, frnd->lpn); + BT_DBG("SendBufFromFrndQueue, Last %p QueueSize %u LPN 0x%04x", + frnd->last, frnd->queue_size, frnd->lpn); + frnd->queue_size--; send_last: @@ -1302,6 +1397,8 @@ int bt_mesh_friend_init(void) { int i; + BT_DBG("FrndInit"); + if (friend_init == true) { BT_WARN("%s, Already", __func__); return -EALREADY; @@ -1333,6 +1430,8 @@ int bt_mesh_friend_deinit(void) { int i; + BT_DBG("FrndDeinit"); + if (friend_init == false) { BT_WARN("%s, Already", __func__); return -EALREADY; @@ -1363,6 +1462,8 @@ static bool is_segack(struct net_buf *buf, const uint64_t *seqauth, uint16_t src struct net_buf_simple_state state = {0}; bool found = false; + BT_DBG("IsSegAck, Len %u", buf->len); + if (buf->len != 16) { return false; } @@ -1372,23 +1473,27 @@ static bool is_segack(struct net_buf *buf, const uint64_t *seqauth, uint16_t src net_buf_skip(buf, 1); /* skip IVI, NID */ if (!(net_buf_pull_u8(buf) >> 7)) { + BT_DBG("Not SegAck"); goto end; } net_buf_pull(buf, 3); /* skip SEQNUM */ if (src != net_buf_pull_be16(buf)) { + BT_DBG("SrcNotSegAck"); goto end; } net_buf_skip(buf, 2); /* skip dst */ - if (TRANS_CTL_OP((uint8_t *) net_buf_pull_mem(buf, 1)) != TRANS_CTL_OP_ACK) { + if (TRANS_CTL_OP((uint8_t *)net_buf_pull_mem(buf, 1)) != TRANS_CTL_OP_ACK) { + BT_DBG("OpNotSegAck"); goto end; } - found = ((net_buf_pull_be16(buf) >> 2) & TRANS_SEQ_ZERO_MASK) == - (*seqauth & TRANS_SEQ_ZERO_MASK); + found = (((net_buf_pull_be16(buf) >> 2) & TRANS_SEQ_ZERO_MASK) == + (*seqauth & TRANS_SEQ_ZERO_MASK)); + end: net_buf_simple_restore(&buf->b, &state); return found; @@ -1399,17 +1504,18 @@ static void friend_purge_old_ack(struct bt_mesh_friend *frnd, { sys_snode_t *cur = NULL, *prev = NULL; - BT_DBG("SeqAuth %llx src 0x%04x", *seq_auth, src); + BT_DBG("FrndPurgeOldAck, SeqAuth %llx Src 0x%04x", *seq_auth, src); for (cur = sys_slist_peek_head(&frnd->queue); - cur != NULL; prev = cur, cur = sys_slist_peek_next(cur)) { + cur != NULL; prev = cur, cur = sys_slist_peek_next(cur)) { struct net_buf *buf = (void *)cur; if (is_segack(buf, seq_auth, src)) { - BT_DBG("Removing old ack from Friend Queue"); + BT_DBG("RemoveOldAckFromFrndQueue, QueueSize %u", frnd->queue_size); sys_slist_remove(&frnd->queue, prev, cur); frnd->queue_size--; + /* Make sure old slist entry state doesn't remain */ buf->frags = NULL; @@ -1428,6 +1534,9 @@ static void friend_lpn_enqueue_rx(struct bt_mesh_friend *frnd, struct friend_pdu_info info = {0}; struct net_buf *buf = NULL; + BT_DBG("FrndLPNEnqueueRx, LPN 0x%04x QueueSize %u Type 0x%02x", + frnd->lpn, frnd->queue_size, type); + /* Because of network loopback, tx packets will also be passed into * this rx function. These packets have already been added to the * queue, and should be ignored. @@ -1436,8 +1545,6 @@ static void friend_lpn_enqueue_rx(struct bt_mesh_friend *frnd, return; } - BT_DBG("LPN 0x%04x queue_size %u", frnd->lpn, frnd->queue_size); - if (type == BLE_MESH_FRIEND_PDU_SINGLE && seq_auth) { friend_purge_old_ack(frnd, seq_auth, rx->ctx.addr); } @@ -1465,7 +1572,7 @@ static void friend_lpn_enqueue_rx(struct bt_mesh_friend *frnd, enqueue_friend_pdu(frnd, type, info.src, seg_count, buf); - BT_DBG("Queued message for LPN 0x%04x, queue_size %u", + BT_DBG("QueuedMsg, LPN 0x%04x QueueSize %u", frnd->lpn, frnd->queue_size); } @@ -1478,7 +1585,7 @@ static void friend_lpn_enqueue_tx(struct bt_mesh_friend *frnd, struct friend_pdu_info info = {0}; struct net_buf *buf = NULL; - BT_DBG("LPN 0x%04x", frnd->lpn); + BT_DBG("FrndLPNEnqueueTx, LPN 0x%04x Type 0x%02x", frnd->lpn, type); if (type == BLE_MESH_FRIEND_PDU_SINGLE && seq_auth) { friend_purge_old_ack(frnd, seq_auth, tx->src); @@ -1510,7 +1617,7 @@ static void friend_lpn_enqueue_tx(struct bt_mesh_friend *frnd, enqueue_friend_pdu(frnd, type, info.src, seg_count, buf); - BT_DBG("Queued message for LPN 0x%04x", frnd->lpn); + BT_DBG("QueuedMsg, LPN 0x%04x", frnd->lpn); } static bool friend_lpn_matches(struct bt_mesh_friend *frnd, uint16_t net_idx, @@ -1518,6 +1625,10 @@ static bool friend_lpn_matches(struct bt_mesh_friend *frnd, uint16_t net_idx, { int i; + BT_DBG("IsFrndLPNMatch"); + BT_DBG("LPN 0x%04x NetIdx 0x%04x/0x%04x Addr 0x%04x Established %u", + frnd->lpn, net_idx, frnd->net_idx, addr, frnd->established); + if (!frnd->established) { return false; } @@ -1543,12 +1654,13 @@ bool bt_mesh_friend_match(uint16_t net_idx, uint16_t addr) { int i; + BT_DBG("FrndMatch, NetIdx 0x%04x Addr 0x%04x", net_idx, addr); + for (i = 0; i < ARRAY_SIZE(bt_mesh.frnd); i++) { struct bt_mesh_friend *frnd = &bt_mesh.frnd[i]; if (friend_lpn_matches(frnd, net_idx, addr)) { - BT_DBG("LPN 0x%04x matched address 0x%04x", - frnd->lpn, addr); + BT_DBG("LPNMatch, LPN 0x%04x Addr 0x%04x", frnd->lpn, addr); return true; } } @@ -1562,6 +1674,8 @@ bool bt_mesh_friend_unicast_match(uint16_t net_idx, uint16_t addr, uint8_t *sele { int i; + BT_DBG("FrndUnicastMatch, NetIdx 0x%04x addr 0x%04x", net_idx, addr); + if (!BLE_MESH_ADDR_IS_UNICAST(addr) || selem == NULL) { BT_ERR("%s, Invalid parameter", __func__); return false; @@ -1587,6 +1701,10 @@ static bool friend_queue_has_space(struct bt_mesh_friend *frnd, uint16_t addr, uint32_t total = 0U; int i; + BT_DBG("IsFrndQueueHasSpace"); + BT_DBG("LPN 0x%04x SegCount %u QueueSize %u Addr 0x%04x", + frnd->lpn, seg_count, CONFIG_BLE_MESH_FRIEND_QUEUE_SIZE, addr); + if (seg_count > CONFIG_BLE_MESH_FRIEND_QUEUE_SIZE) { return false; } @@ -1595,8 +1713,8 @@ static bool friend_queue_has_space(struct bt_mesh_friend *frnd, uint16_t addr, struct bt_mesh_friend_seg *seg = &frnd->seg[i]; if (seq_auth && is_seg(seg, addr, *seq_auth & TRANS_SEQ_ZERO_MASK)) { - /* If there's a segment queue for this message then the - * space verification has already happened. + /* If there's a segment queue for this message then the space + * verification has already happened. */ return true; } @@ -1604,6 +1722,8 @@ static bool friend_queue_has_space(struct bt_mesh_friend *frnd, uint16_t addr, total += seg->seg_count; } + BT_DBG("TotalCount %u", total); + /* If currently pending segments combined with this segmented message * are more than the Friend Queue Size, then there's no space. This * is because we don't have a mechanism of aborting already pending @@ -1618,6 +1738,10 @@ bool bt_mesh_friend_queue_has_space(uint16_t net_idx, uint16_t src, uint16_t dst bool someone_has_space = false, friend_match = false; int i; + BT_DBG("FrndQueueHasSpace"); + BT_DBG("NetIdx 0x%04x Src 0x%04x Dst 0x%04x SegCount %u", + net_idx, src, dst, seg_count); + for (i = 0; i < ARRAY_SIZE(bt_mesh.frnd); i++) { struct bt_mesh_friend *frnd = &bt_mesh.frnd[i]; @@ -1636,6 +1760,7 @@ bool bt_mesh_friend_queue_has_space(uint16_t net_idx, uint16_t src, uint16_t dst * transport layer can continue its work. */ if (!friend_match) { + BT_DBG("NoMatchLPN"); return true; } @@ -1653,6 +1778,9 @@ static bool friend_queue_prepare_space(struct bt_mesh_friend *frnd, uint16_t add bool pending_segments = false; uint8_t avail_space = 0U; + BT_DBG("FrndQueuePrepareSpace"); + BT_DBG("LPN 0x%04x Addr 0x%04x SegCount %u", frnd->lpn, addr, seg_count); + if (!friend_queue_has_space(frnd, addr, seq_auth, seg_count)) { return false; } @@ -1668,6 +1796,9 @@ static bool friend_queue_prepare_space(struct bt_mesh_friend *frnd, uint16_t add return false; } + BT_DBG("PendingSeg %u AvailSpace %u QueueSize %u", + pending_segments, avail_space, frnd->queue_size); + frnd->queue_size--; avail_space++; @@ -1690,15 +1821,19 @@ void bt_mesh_friend_enqueue_rx(struct bt_mesh_net_rx *rx, { int i; + BT_DBG("FrndEnqueueRx"); + BT_DBG("FrndMatch %u RecvTTL %u NetIf %u FrndGet %u", + rx->friend_match, rx->ctx.recv_ttl, rx->net_if, + bt_mesh_friend_get()); + if (!rx->friend_match || (rx->ctx.recv_ttl <= 1U && rx->net_if != BLE_MESH_NET_IF_LOCAL) || bt_mesh_friend_get() != BLE_MESH_FRIEND_ENABLED) { return; } - BT_DBG("recv_ttl %u net_idx 0x%04x src 0x%04x dst 0x%04x", - rx->ctx.recv_ttl, rx->sub->net_idx, rx->ctx.addr, - rx->ctx.recv_dst); + BT_DBG("NetIdx 0x%04x Src 0x%04x Dst 0x%04x", + rx->sub->net_idx, rx->ctx.addr, rx->ctx.recv_dst); for (i = 0; i < ARRAY_SIZE(bt_mesh.frnd); i++) { struct bt_mesh_friend *frnd = &bt_mesh.frnd[i]; @@ -1713,8 +1848,7 @@ void bt_mesh_friend_enqueue_rx(struct bt_mesh_net_rx *rx, continue; } - friend_lpn_enqueue_rx(frnd, rx, type, seq_auth, seg_count, - sbuf); + friend_lpn_enqueue_rx(frnd, rx, type, seq_auth, seg_count, sbuf); } } @@ -1726,14 +1860,15 @@ bool bt_mesh_friend_enqueue_tx(struct bt_mesh_net_tx *tx, bool matched = false; int i; + BT_DBG("FrndEnqueueTx"); + BT_DBG("NetIdx 0x%04x Dst 0x%04x Src 0x%04x FrndState %u", + tx->sub->net_idx, tx->ctx->addr, tx->src, bt_mesh_friend_get()); + if (!bt_mesh_friend_match(tx->sub->net_idx, tx->ctx->addr) || bt_mesh_friend_get() != BLE_MESH_FRIEND_ENABLED) { return matched; } - BT_DBG("net_idx 0x%04x dst 0x%04x src 0x%04x", tx->sub->net_idx, - tx->ctx->addr, tx->src); - for (i = 0; i < ARRAY_SIZE(bt_mesh.frnd); i++) { struct bt_mesh_friend *frnd = &bt_mesh.frnd[i]; @@ -1760,6 +1895,9 @@ void bt_mesh_friend_clear_incomplete(struct bt_mesh_subnet *sub, uint16_t src, { int i; + BT_DBG("FrndClearComplete"); + BT_DBG("NetIdx 0x%04x Src 0x%04x Dst 0x%04x", sub->net_idx, src, dst); + for (i = 0; i < ARRAY_SIZE(bt_mesh.frnd); i++) { struct bt_mesh_friend *frnd = &bt_mesh.frnd[i]; int j; @@ -1788,6 +1926,8 @@ void bt_mesh_friend_remove_lpn(uint16_t lpn_addr) { struct bt_mesh_friend *frnd = NULL; + BT_DBG("FrndRemoveLPN, Addr 0x%04x", lpn_addr); + frnd = bt_mesh_friend_find(BLE_MESH_KEY_ANY, lpn_addr, false, false); if (frnd) { friend_clear(frnd, BLE_MESH_FRIENDSHIP_TERMINATE_DISABLE); diff --git a/components/bt/esp_ble_mesh/core/health_cli.c b/components/bt/esp_ble_mesh/core/health_cli.c index 1e03d93513c4..df9685e45fe3 100644 --- a/components/bt/esp_ble_mesh/core/health_cli.c +++ b/components/bt/esp_ble_mesh/core/health_cli.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -68,6 +68,8 @@ static void health_client_recv_status(struct bt_mesh_model *model, struct net_buf_simple buf = {0}; uint8_t evt_type = 0xFF; + BT_DBG("HealthClientRecvStatus"); + if (!model || !ctx || !status || !len) { BT_ERR("%s, Invalid parameter", __func__); return; @@ -83,6 +85,8 @@ static void health_client_recv_status(struct bt_mesh_model *model, if (!node) { BT_DBG("Unexpected Health Status 0x%04x", ctx->recv_op); } else { + BT_DBG("OpCode 0x%08lx RecvOp 0x%08lx", node->opcode, ctx->recv_op); + switch (node->opcode) { case OP_HEALTH_FAULT_GET: case OP_HEALTH_PERIOD_GET: @@ -131,9 +135,10 @@ static void health_fault_status(struct bt_mesh_model *model, { struct bt_mesh_health_fault_status status = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("HealthFaultStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status.test_id = net_buf_simple_pull_u8(buf); status.cid = net_buf_simple_pull_le16(buf); @@ -154,9 +159,10 @@ static void health_current_status(struct bt_mesh_model *model, { struct bt_mesh_health_current_status status = {0}; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("HealthCurrentStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status.test_id = net_buf_simple_pull_u8(buf); status.cid = net_buf_simple_pull_le16(buf); @@ -177,9 +183,10 @@ static void health_period_status(struct bt_mesh_model *model, { uint8_t status = 0U; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("HealthPeriodStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status = net_buf_simple_pull_u8(buf); @@ -192,9 +199,10 @@ static void health_attention_status(struct bt_mesh_model *model, { uint8_t status = 0U; - BT_DBG("net_idx 0x%04x app_idx 0x%04x src 0x%04x len %u: %s", - ctx->net_idx, ctx->app_idx, ctx->addr, buf->len, - bt_hex(buf->data, buf->len)); + BT_DBG("HealthAttentionStatus"); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Src 0x%04x", + ctx->net_idx, ctx->app_idx, ctx->addr); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); status = net_buf_simple_pull_u8(buf); @@ -213,6 +221,8 @@ int bt_mesh_health_attention_get(bt_mesh_client_common_param_t *param) { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_ATTENTION_GET, 0); + BT_DBG("HealthAttentionGet"); + bt_mesh_model_msg_init(&msg, OP_ATTENTION_GET); return bt_mesh_client_send_msg(param, &msg, true, timeout_handler); @@ -223,6 +233,8 @@ int bt_mesh_health_attention_set(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_ATTENTION_SET, 1); + BT_DBG("HealthAttentionSet, Attention 0x%02x NeedAck %u", attention, need_ack); + bt_mesh_model_msg_init(&msg, need_ack ? OP_ATTENTION_SET : OP_ATTENTION_SET_UNREL); net_buf_simple_add_u8(&msg, attention); @@ -233,6 +245,8 @@ int bt_mesh_health_period_get(bt_mesh_client_common_param_t *param) { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_HEALTH_PERIOD_GET, 0); + BT_DBG("HealthPeriodGet"); + bt_mesh_model_msg_init(&msg, OP_HEALTH_PERIOD_GET); return bt_mesh_client_send_msg(param, &msg, true, timeout_handler); @@ -243,6 +257,8 @@ int bt_mesh_health_period_set(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_HEALTH_PERIOD_SET, 1); + BT_DBG("HealthPeriodSet, Divisor 0x%02x NeedAck %u", divisor, need_ack); + bt_mesh_model_msg_init(&msg, need_ack ? OP_HEALTH_PERIOD_SET : OP_HEALTH_PERIOD_SET_UNREL); net_buf_simple_add_u8(&msg, divisor); @@ -254,6 +270,8 @@ int bt_mesh_health_fault_test(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_HEALTH_FAULT_TEST, 3); + BT_DBG("HealthFaultTest, CID 0x%04x TestID 0x%04x NeedAck %u", cid, test_id, need_ack); + bt_mesh_model_msg_init(&msg, need_ack ? OP_HEALTH_FAULT_TEST : OP_HEALTH_FAULT_TEST_UNREL); net_buf_simple_add_u8(&msg, test_id); net_buf_simple_add_le16(&msg, cid); @@ -266,6 +284,8 @@ int bt_mesh_health_fault_clear(bt_mesh_client_common_param_t *param, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_HEALTH_FAULT_CLEAR, 2); + BT_DBG("HealthFaultClear, CID 0x%04x NeedAck %u", cid, need_ack); + bt_mesh_model_msg_init(&msg, need_ack ? OP_HEALTH_FAULT_CLEAR : OP_HEALTH_FAULT_CLEAR_UNREL); net_buf_simple_add_le16(&msg, cid); @@ -276,6 +296,8 @@ int bt_mesh_health_fault_get(bt_mesh_client_common_param_t *param, uint16_t cid) { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_HEALTH_FAULT_GET, 2); + BT_DBG("HealthFaultGet, CID 0x%04x", cid); + bt_mesh_model_msg_init(&msg, OP_HEALTH_FAULT_GET); net_buf_simple_add_le16(&msg, cid); @@ -287,6 +309,8 @@ static int health_cli_init(struct bt_mesh_model *model) health_internal_data_t *internal = NULL; bt_mesh_health_client_t *client = NULL; + BT_DBG("HealthCliInit"); + if (!model) { BT_ERR("Invalid Health Client model"); return -EINVAL; @@ -328,6 +352,8 @@ static int health_cli_deinit(struct bt_mesh_model *model) { bt_mesh_health_client_t *client = NULL; + BT_DBG("HealthCliDeinit"); + if (!model) { BT_ERR("Invalid Health Client model"); return -EINVAL; diff --git a/components/bt/esp_ble_mesh/core/health_srv.c b/components/bt/esp_ble_mesh/core/health_srv.c index a27e4547b211..98656586e7b9 100644 --- a/components/bt/esp_ble_mesh/core/health_srv.c +++ b/components/bt/esp_ble_mesh/core/health_srv.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -26,8 +26,7 @@ /* Health Server context of the primary element */ struct bt_mesh_health_srv *health_srv; -/** - * When an Element receives a Health Fault Get, or a Health Fault Test, or +/* When an Element receives a Health Fault Get, or a Health Fault Test, or * a Health Fault Test Unacknowledged, or a Health Fault Clear, or a Health * Fault Clear Unacknowledged message that is not successfully processed * (i.e. the Company ID field that does not identify any Health Fault state @@ -48,6 +47,8 @@ static uint8_t health_get_curr_fault_count(struct bt_mesh_model *model) } } + BT_DBG("HealthGetCurrFaultCount, Count %u", count); + return count; } @@ -61,6 +62,8 @@ static void health_get_fault_value(struct bt_mesh_model *model, array_size = current ? ARRAY_SIZE(srv->test.curr_faults) : ARRAY_SIZE(srv->test.reg_faults); + BT_DBG("HealthGetFaultValue, Current %u Size %lu", current, array_size); + for (i = 0U; i < array_size; i++) { if (net_buf_simple_tailroom(msg) == 0) { return; @@ -70,6 +73,8 @@ static void health_get_fault_value(struct bt_mesh_model *model, if (fault != HEALTH_NO_FAULT) { net_buf_simple_add_u8(msg, fault); } + + BT_DBG("%u: Fault 0x%02x", i, fault); } } @@ -78,12 +83,16 @@ static bool health_is_test_id_exist(struct bt_mesh_model *model, uint8_t test_id struct bt_mesh_health_srv *srv = model->user_data; int i; + BT_DBG("HealthIsTestIDExist, TestID 0x%02x", test_id); + for (i = 0; i < srv->test.id_count; i++) { if (srv->test.test_ids[i] == test_id) { + BT_DBG("TestIDExist"); return true; } } + BT_DBG("TestIDNotExist"); return false; } @@ -94,19 +103,23 @@ static int health_send_fault_status(struct bt_mesh_model *model, struct net_buf_simple *msg = NULL; int err = 0; + BT_DBG("HealthSendFaultStatus"); + msg = bt_mesh_alloc_buf(4 + ARRAY_SIZE(srv->test.reg_faults) + 4); if (!msg) { BT_ERR("%s, Out of memory", __func__); return -ENOMEM; } + BT_DBG("TestID 0x%02x CID 0x%04x", + srv->test.prev_test_id, srv->test.company_id); + bt_mesh_model_msg_init(msg, OP_HEALTH_FAULT_STATUS); net_buf_simple_add_u8(msg, srv->test.prev_test_id); net_buf_simple_add_le16(msg, srv->test.company_id); if (ctx->recv_op != OP_HEALTH_FAULT_CLEAR) { - /** - * For Health Fault Clear, the FaultArray field in Health Fault Status - * shall be empty. + /* For Health Fault Clear, the FaultArray field + * in Health Fault Status shall be empty. */ health_get_fault_value(model, msg, false); } @@ -127,6 +140,8 @@ static void health_fault_get(struct bt_mesh_model *model, struct bt_mesh_health_srv *srv = model->user_data; uint16_t company_id = 0U; + BT_DBG("HealthFaultGet"); + if (!srv) { BT_ERR("No Health Server context provided"); return; @@ -138,7 +153,7 @@ static void health_fault_get(struct bt_mesh_model *model, return; } - BT_DBG("company_id 0x%04x", company_id); + BT_DBG("CID 0x%04x", company_id); health_send_fault_status(model, ctx); } @@ -150,6 +165,8 @@ static void health_fault_clear(struct bt_mesh_model *model, struct bt_mesh_health_srv *srv = model->user_data; uint16_t company_id = 0U; + BT_DBG("HealthFaultClear"); + if (!srv) { BT_ERR("No Health Server context provided"); return; @@ -161,7 +178,7 @@ static void health_fault_clear(struct bt_mesh_model *model, return; } - BT_DBG("company_id 0x%04x", company_id); + BT_DBG("CID 0x%04x", company_id); memset(srv->test.reg_faults, HEALTH_NO_FAULT, ARRAY_SIZE(srv->test.reg_faults)); @@ -182,6 +199,8 @@ static void health_fault_test(struct bt_mesh_model *model, uint16_t company_id = 0U; uint8_t test_id = 0U; + BT_DBG("HealthFaultTest"); + if (!srv) { BT_ERR("No Health Server context provided"); return; @@ -199,7 +218,7 @@ static void health_fault_test(struct bt_mesh_model *model, return; } - BT_DBG("test 0x%02x company 0x%04x", test_id, company_id); + BT_DBG("TestID 0x%02x CID 0x%04x", test_id, company_id); srv->test.prev_test_id = test_id; @@ -219,13 +238,16 @@ static void send_attention_status(struct bt_mesh_model *model, struct bt_mesh_health_srv *srv = model->user_data; uint8_t time = 0U; + BT_DBG("SendAttentionStatus"); + if (!srv) { BT_ERR("No Health Server context provided"); return; } time = k_delayed_work_remaining_get(&srv->attn_timer) / 1000; - BT_DBG("%u second%s", time, (time == 1U) ? "" : "s"); + + BT_DBG("Time %u", time); bt_mesh_model_msg_init(&msg, OP_ATTENTION_STATUS); net_buf_simple_add_u8(&msg, time); @@ -239,6 +261,8 @@ static void attention_get(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { + BT_DBG("AttentionGet"); + send_attention_status(model, ctx); } @@ -250,7 +274,7 @@ static void health_set_attention(struct bt_mesh_model *model, time = net_buf_simple_pull_u8(buf); - BT_DBG("%u second%s", time, (time == 1U) ? "" : "s"); + BT_DBG("HealthSetAttention, Time %u", time); bt_mesh_attention(model, time); } @@ -259,6 +283,8 @@ static void attention_set(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { + BT_DBG("AttentionSet"); + health_set_attention(model, ctx, buf); if (ctx->recv_op == OP_ATTENTION_SET) { @@ -271,6 +297,8 @@ static void send_health_period_status(struct bt_mesh_model *model, { BLE_MESH_MODEL_BUF_DEFINE(msg, OP_HEALTH_PERIOD_STATUS, 1); + BT_DBG("SendHealthPeriodStatus"); + bt_mesh_model_msg_init(&msg, OP_HEALTH_PERIOD_STATUS); net_buf_simple_add_u8(&msg, model->pub->period_div); @@ -283,6 +311,8 @@ static void health_period_get(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { + BT_DBG("HealthPeriodGet"); + send_health_period_status(model, ctx); } @@ -292,13 +322,15 @@ static void health_set_period(struct bt_mesh_model *model, { uint8_t period = 0U; + BT_DBG("HealthSetPeriod"); + period = net_buf_simple_pull_u8(buf); if (period > 15) { BT_WARN("Prohibited period value %u", period); return; } - BT_DBG("period %u", period); + BT_DBG("Period %u", period); model->pub->period_div = period; } @@ -307,6 +339,8 @@ static void health_period_set(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) { + BT_DBG("HealthPeriodSet"); + health_set_period(model, ctx, buf); if (ctx->recv_op == OP_HEALTH_PERIOD_SET) { @@ -334,6 +368,8 @@ static size_t health_get_current(struct bt_mesh_model *model, { struct bt_mesh_health_srv *srv = model->user_data; + BT_DBG("HealthGetCurrent"); + if (!srv) { BT_ERR("No Health Server context provided"); return 0; @@ -344,6 +380,9 @@ static size_t health_get_current(struct bt_mesh_model *model, return 0; } + BT_DBG("TestID 0x%02x CID 0x%04x", + srv->test.prev_test_id, srv->test.company_id); + bt_mesh_model_msg_init(msg, OP_HEALTH_CURRENT_STATUS); net_buf_simple_add_u8(msg, srv->test.prev_test_id); net_buf_simple_add_le16(msg, srv->test.company_id); @@ -357,6 +396,8 @@ static int health_pub_update(struct bt_mesh_model *model) struct bt_mesh_model_pub *pub = model->pub; size_t count = 0U; + BT_DBG("HealthPubUpdate"); + if (!pub || !pub->msg) { BT_ERR("Invalid health publication context"); return -EINVAL; @@ -369,6 +410,8 @@ static int health_pub_update(struct bt_mesh_model *model) pub->fast_period = 0U; } + BT_DBG("Count %lu", count); + return 0; } @@ -376,6 +419,8 @@ int bt_mesh_fault_update(struct bt_mesh_elem *elem) { struct bt_mesh_model *model = NULL; + BT_DBG("FaultUpdate"); + model = bt_mesh_model_find(elem, BLE_MESH_MODEL_ID_HEALTH_SRV); if (!model) { BT_ERR("Health Server not exists"); @@ -409,6 +454,8 @@ static void attention_off(struct k_work *work) return; } + BT_DBG("AttentionOff"); + if (srv->cb.attn_off) { srv->cb.attn_off(srv->model); } @@ -423,6 +470,8 @@ static int health_srv_init(struct bt_mesh_model *model) * supported by any secondary elements. */ + BT_DBG("HealthSrvInit"); + if (!srv) { BT_ERR("No Health Server context provided"); return -EINVAL; @@ -433,6 +482,8 @@ static int health_srv_init(struct bt_mesh_model *model) return -EINVAL; } + BT_DBG("TestIDCount %u", srv->test.id_count); + if (!model->pub) { BT_ERR("Health Server has no publication support"); return -EINVAL; @@ -460,6 +511,8 @@ static int health_srv_deinit(struct bt_mesh_model *model) { struct bt_mesh_health_srv *srv = model->user_data; + BT_DBG("HealthSrvDeinit"); + if (!srv) { BT_ERR("No Health Server context provided"); return -EINVAL; @@ -499,6 +552,8 @@ void bt_mesh_attention(struct bt_mesh_model *model, uint8_t time) { struct bt_mesh_health_srv *srv = NULL; + BT_DBG("Attention, Time %u", time); + if (!model) { srv = health_srv; if (!srv) { diff --git a/components/bt/esp_ble_mesh/core/heartbeat.c b/components/bt/esp_ble_mesh/core/heartbeat.c index 4ff63a13abe0..444ea285decc 100644 --- a/components/bt/esp_ble_mesh/core/heartbeat.c +++ b/components/bt/esp_ble_mesh/core/heartbeat.c @@ -1,6 +1,6 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -21,11 +21,15 @@ static uint16_t hb_sub_dst = BLE_MESH_ADDR_UNASSIGNED; void bt_mesh_set_hb_sub_dst(uint16_t addr) { + BT_DBG("SetHbSubDst 0x%04x", addr); + hb_sub_dst = addr; } uint16_t bt_mesh_get_hb_sub_dst(void) { + BT_DBG("GetHbSubDst 0x%04x", hb_sub_dst); + return hb_sub_dst; } @@ -33,6 +37,9 @@ void bt_mesh_heartbeat_recv(uint16_t src, uint16_t dst, uint8_t hops, uint16_t f { struct bt_mesh_cfg_srv *cfg = bt_mesh_cfg_get(); + BT_DBG("HeartbeatRecv"); + BT_DBG("Src 0x%04x Dst 0x%04x Hops %u Feat 0x%04x", src, dst, hops, feat); + if (cfg == NULL) { BT_WARN("No configuration server context available"); return; @@ -55,9 +62,8 @@ void bt_mesh_heartbeat_recv(uint16_t src, uint16_t dst, uint8_t hops, uint16_t f cfg->hb_sub.count++; } - BT_DBG("src 0x%04x dst 0x%04x hops %u min %u max %u count %u", src, - dst, hops, cfg->hb_sub.min_hops, cfg->hb_sub.max_hops, - cfg->hb_sub.count); + BT_DBG("MinHops %u MaxHops %u Count %u", + cfg->hb_sub.min_hops, cfg->hb_sub.max_hops, cfg->hb_sub.count); if (cfg->hb_sub.func) { cfg->hb_sub.func(hops, feat); @@ -67,7 +73,6 @@ void bt_mesh_heartbeat_recv(uint16_t src, uint16_t dst, uint8_t hops, uint16_t f void bt_mesh_heartbeat_send(void) { struct bt_mesh_cfg_srv *cfg = bt_mesh_cfg_get(); - uint16_t feat = 0U; struct __attribute__((packed)) { uint8_t init_ttl; uint16_t feat; @@ -85,6 +90,9 @@ void bt_mesh_heartbeat_send(void) .src = bt_mesh_model_elem(cfg->model)->addr, .xmit = bt_mesh_net_transmit_get(), }; + uint16_t feat = 0U; + + BT_DBG("HeartbeatSend, Dst 0x%04x", cfg->hb_pub.dst); /* Do nothing if heartbeat publication is not enabled */ if (cfg->hb_pub.dst == BLE_MESH_ADDR_UNASSIGNED) { @@ -111,7 +119,7 @@ void bt_mesh_heartbeat_send(void) hb.feat = sys_cpu_to_be16(feat); - BT_INFO("InitTTL %u feat 0x%04x", cfg->hb_pub.ttl, feat); + BT_INFO("InitTTL %u Feat 0x%04x", cfg->hb_pub.ttl, feat); bt_mesh_ctl_send(&tx, TRANS_CTL_OP_HEARTBEAT, &hb, sizeof(hb), NULL, NULL); @@ -149,6 +157,8 @@ int bt_mesh_pvnr_register_hb_recv_cb(bt_mesh_pvnr_hb_recv_cb_t cb) int bt_mesh_pvnr_set_hb_recv_filter_type(uint8_t type) { + BT_DBG("PvnrSetHbRecvFilterType"); + if (type > HEARTBEAT_FILTER_REJECTLIST) { BT_ERR("Invalid heartbeat filter type 0x%02x", type); return -EINVAL; @@ -158,6 +168,8 @@ int bt_mesh_pvnr_set_hb_recv_filter_type(uint8_t type) * clear the existing filter entries. */ if (hb_rx.type != type) { + BT_DBG("OldType %u NewType %u", hb_rx.type, type); + memset(&hb_rx, 0, offsetof(struct heartbeat_recv, cb)); hb_rx.type = type; } @@ -169,6 +181,8 @@ static int hb_filter_alloc(uint16_t src, uint16_t dst) { int i; + BT_DBG("HbFilterAlloc, Src 0x%04x Dst 0x%04x", src, dst); + for (i = 0; i < ARRAY_SIZE(hb_rx.filter); i++) { struct heartbeat_filter *filter = &hb_rx.filter[i]; @@ -180,7 +194,7 @@ static int hb_filter_alloc(uint16_t src, uint16_t dst) } } - BT_ERR("Heartbeat filter is full!"); + BT_ERR("HbFilterFull"); return -ENOMEM; } @@ -188,6 +202,8 @@ static int hb_filter_add(uint16_t src, uint16_t dst) { int i; + BT_DBG("HbFilterAdd, Src 0x%04x Dst 0x%04x", src, dst); + if (!(BLE_MESH_ADDR_IS_UNICAST(src) && (BLE_MESH_ADDR_IS_UNICAST(dst) || BLE_MESH_ADDR_IS_GROUP(dst)))) { BT_ERR("Invalid filter address, src 0x%04x, dst 0x%04x", src, dst); @@ -199,7 +215,7 @@ static int hb_filter_add(uint16_t src, uint16_t dst) struct heartbeat_filter *filter = &hb_rx.filter[i]; if (filter->src == src && filter->dst == dst) { - BT_WARN("Filter already exists, src 0x%04x dst 0x%04x", filter->src, filter->dst); + BT_DBG("FilterIndex %u", i); return 0; } } @@ -211,6 +227,8 @@ static int hb_filter_remove(uint16_t src, uint16_t dst) { int i; + BT_DBG("HbFilterRemove, Src 0x%04x Dst 0x%04x", src, dst); + if (!(BLE_MESH_ADDR_IS_UNICAST(src) && (BLE_MESH_ADDR_IS_UNICAST(dst) || BLE_MESH_ADDR_IS_GROUP(dst)))) { BT_ERR("Invalid filter address, src 0x%04x, dst 0x%04x", src, dst); @@ -221,6 +239,7 @@ static int hb_filter_remove(uint16_t src, uint16_t dst) struct heartbeat_filter *filter = &hb_rx.filter[i]; if (filter->src == src && filter->dst == dst) { + BT_DBG("FilterIndex %u", i); memset(filter, 0, sizeof(struct heartbeat_filter)); } } @@ -236,7 +255,7 @@ int bt_mesh_pvnr_set_hb_recv_filter_info(uint8_t op, uint16_t src, uint16_t dst) case HEARTBEAT_FILTER_REMOVE: return hb_filter_remove(src, dst); default: - BT_ERR("Invalid heartbeat filter opcode 0x%02x", op); + BT_ERR("Invalid HbFilterOpCode 0x%02x", op); return -EINVAL; } } @@ -248,6 +267,7 @@ static bool filter_with_rejectlist(uint16_t hb_src, uint16_t hb_dst) for (i = 0; i < ARRAY_SIZE(hb_rx.filter); i++) { struct heartbeat_filter *filter = &hb_rx.filter[i]; if (hb_src == filter->src && hb_dst == filter->dst) { + BT_DBG("InRejectList, Src 0x%04x Dst 0x%04x", hb_src, hb_dst); return true; } } @@ -262,6 +282,7 @@ static bool filter_with_acceptlist(uint16_t hb_src, uint16_t hb_dst) for (i = 0; i < ARRAY_SIZE(hb_rx.filter); i++) { struct heartbeat_filter *filter = &hb_rx.filter[i]; if (hb_src == filter->src && hb_dst == filter->dst) { + BT_DBG("InAcceptList, Src 0x%04x Dst 0x%04x", hb_src, hb_dst); return false; } } @@ -273,6 +294,8 @@ void bt_mesh_pvnr_heartbeat_recv(uint16_t hb_src, uint16_t hb_dst, uint8_t init_ttl, uint8_t rx_ttl, uint8_t hops, uint16_t feat, int8_t rssi) { + BT_DBG("PvnrHeartbeatRecv"); + if (hb_rx.cb == NULL) { BT_DBG("Receiving heartbeat is not enabled"); return; @@ -280,16 +303,17 @@ void bt_mesh_pvnr_heartbeat_recv(uint16_t hb_src, uint16_t hb_dst, if (hb_rx.type == HEARTBEAT_FILTER_REJECTLIST) { if (filter_with_rejectlist(hb_src, hb_dst)) { - BT_INFO("Filtered by rejectlist, src 0x%04x, dst 0x%04x", hb_src, hb_dst); return; } } else { if (filter_with_acceptlist(hb_src, hb_dst)) { - BT_INFO("Filtered by acceptlist, src 0x%04x, dst 0x%04x", hb_src, hb_dst); return; } } + BT_DBG("Src 0x%04x Dst 0x%04x InitTTL %u RxTTL %u Hops %u Feat 0x%04x Rssi %d", + hb_src, hb_dst, init_ttl, rx_ttl, hops, feat, rssi); + if (hb_rx.cb) { hb_rx.cb(hb_src, hb_dst, init_ttl, rx_ttl, hops, feat, rssi); } diff --git a/components/bt/esp_ble_mesh/core/include/mesh/adapter.h b/components/bt/esp_ble_mesh/core/include/mesh/adapter.h index 1cb239a3caca..5a1e4326a926 100644 --- a/components/bt/esp_ble_mesh/core/include/mesh/adapter.h +++ b/components/bt/esp_ble_mesh/core/include/mesh/adapter.h @@ -1,7 +1,7 @@ /* * SPDX-FileCopyrightText: 2017 Nordic Semiconductor ASA * SPDX-FileCopyrightText: 2015-2017 Intel Corporation - * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -553,7 +553,7 @@ struct bt_mesh_gatt_attr { * @param len Length of data to read * @param offset Offset to start reading from * - * @return Number fo bytes read, or in case of an error + * @return Number of bytes read, or in case of an error * BLE_MESH_GATT_ERR() with a specific ATT error code. */ ssize_t (*read)(struct bt_mesh_conn *conn, diff --git a/components/bt/esp_ble_mesh/core/local.c b/components/bt/esp_ble_mesh/core/local.c index 4451e0d7b263..c0fc5b3f453e 100644 --- a/components/bt/esp_ble_mesh/core/local.c +++ b/components/bt/esp_ble_mesh/core/local.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,14 +22,17 @@ static struct bt_mesh_model *find_model(uint16_t elem_addr, uint16_t cid, uint16 { struct bt_mesh_elem *elem = NULL; + BT_DBG("FindModelLocal"); + BT_DBG("ElemAddr 0x%04x CID 0x%04x ID 0x%04x", elem_addr, cid, mod_id); + if (!BLE_MESH_ADDR_IS_UNICAST(elem_addr)) { - BT_ERR("Invalid unicast address 0x%04x", elem_addr); + BT_ERR("InvalidUnicastAddr 0x%04x", elem_addr); return NULL; } elem = bt_mesh_elem_find(elem_addr); if (elem == NULL) { - BT_ERR("No element found, addr 0x%04x", elem_addr); + BT_ERR("NoElemFound 0x%04x", elem_addr); return NULL; } @@ -46,19 +49,23 @@ int bt_mesh_model_subscribe_group_addr(uint16_t elem_addr, uint16_t cid, struct bt_mesh_model *model = NULL; int i; + BT_DBG("ModelSubGroupAddrLocal"); + BT_DBG("ElemAddr 0x%04x CID 0x%04x ID 0x%04x GroupAddr 0x%04x", + elem_addr, cid, mod_id, group_addr); + model = find_model(elem_addr, cid, mod_id); if (model == NULL) { - BT_ERR("Subscribe, model not found, cid 0x%04x, mod_id 0x%04x", cid, mod_id); + BT_ERR("ModelNotFound, CID 0x%04x ID 0x%04x", cid, mod_id); return -ENODEV; } if (!BLE_MESH_ADDR_IS_GROUP(group_addr)) { - BT_ERR("Subscribe, not a group address 0x%04x", group_addr); + BT_ERR("NotGroupAddr 0x%04x", group_addr); return -EINVAL; } if (bt_mesh_model_find_group(model, group_addr)) { - BT_INFO("Group address 0x%04x already exists", group_addr); + BT_INFO("GroupAddrExist 0x%04x", group_addr); return 0; } @@ -74,12 +81,11 @@ int bt_mesh_model_subscribe_group_addr(uint16_t elem_addr, uint16_t cid, bt_mesh_lpn_group_add(group_addr); } - BT_INFO("Subscribe group address 0x%04x", group_addr); return 0; } } - BT_ERR("Subscribe, model sub is full!"); + BT_ERR("ModelSubFull"); return -ENOMEM; } @@ -89,20 +95,24 @@ int bt_mesh_model_unsubscribe_group_addr(uint16_t elem_addr, uint16_t cid, struct bt_mesh_model *model = NULL; uint16_t *match = NULL; + BT_DBG("ModelUnsubGroupAddrLocal"); + BT_DBG("ElemAddr 0x%04x CID 0x%04x ID 0x%04x GroupAddr 0x%04x", + elem_addr, cid, mod_id, group_addr); + model = find_model(elem_addr, cid, mod_id); if (model == NULL) { - BT_ERR("Unsubscribe, model not found, cid 0x%04x, mod_id 0x%04x", cid, mod_id); + BT_ERR("ModelNotFound, CID 0x%04x ID 0x%04x", cid, mod_id); return -ENODEV; } if (!BLE_MESH_ADDR_IS_GROUP(group_addr)) { - BT_ERR("Unsubscribe, not a group address 0x%04x", group_addr); + BT_ERR("NotGroupAddr 0x%04x", group_addr); return -EINVAL; } match = bt_mesh_model_find_group(model, group_addr); if (match == NULL) { - BT_WARN("Group address 0x%04x not exists", group_addr); + BT_WARN("GroupAddrExist 0x%04x", group_addr); return -EEXIST; } @@ -116,7 +126,6 @@ int bt_mesh_model_unsubscribe_group_addr(uint16_t elem_addr, uint16_t cid, bt_mesh_lpn_group_del(&group_addr, 1); } - BT_INFO("Unsubscribe group address 0x%04x", group_addr); return 0; } @@ -126,20 +135,24 @@ int bt_mesh_enable_directed_forwarding(uint16_t net_idx, bool directed_forwardin { struct bt_mesh_subnet *sub = NULL; + BT_DBG("EnableDFLocal, NetIdx 0x%04x DF %u DFRelay %u", + net_idx, directed_forwarding, directed_forwarding_relay); + if (net_idx > 0xFFF) { - BT_ERR("Invalid NetKeyIndex 0x%04x", net_idx); + BT_ERR("InvalidNetIdx 0x%04x", net_idx); return -EINVAL; } sub = bt_mesh_subnet_get(net_idx); if (!sub) { - BT_ERR("NetKey 0x%04x not exists", net_idx); + BT_ERR("NetIdxNotExist 0x%04x", net_idx); return -EINVAL; } if (directed_forwarding == BLE_MESH_DIRECTED_FORWARDING_DISABLED && directed_forwarding_relay == BLE_MESH_DIRECTED_RELAY_ENABLED) { - BT_ERR("Invalid Config directed forwarding: %d, directed forwarding relay: %d", directed_forwarding, directed_forwarding_relay); + BT_ERR("InvalidDFConfig %u/%u", + directed_forwarding, directed_forwarding_relay); return -EINVAL; } @@ -155,14 +168,16 @@ const uint8_t *bt_mesh_node_get_local_net_key(uint16_t net_idx) { struct bt_mesh_subnet *sub = NULL; + BT_DBG("NodeGetNetKeyLocal, NetIdx 0x%04x", net_idx); + if (net_idx > 0xFFF) { - BT_ERR("Invalid NetKeyIndex 0x%04x", net_idx); + BT_ERR("InvalidNetIdx 0x%04x", net_idx); return NULL; } sub = bt_mesh_subnet_get(net_idx); if (!sub) { - BT_ERR("NetKey 0x%04x not exists", net_idx); + BT_ERR("NetIdxNotExist 0x%04x", net_idx); return NULL; } @@ -173,14 +188,16 @@ const uint8_t *bt_mesh_node_get_local_app_key(uint16_t app_idx) { struct bt_mesh_app_key *key = NULL; + BT_DBG("NodeGetAppKeyLocal, AppIdx 0x%04x", app_idx); + if (app_idx > 0xFFF) { - BT_ERR("Invalid AppKeyIndex 0x%04x", app_idx); + BT_ERR("InvalidAppIdx 0x%04x", app_idx); return NULL; } key = bt_mesh_app_key_get(app_idx); if (!key) { - BT_ERR("AppKey 0x%04x not exists", app_idx); + BT_ERR("AppIdxNotExist 0x%04x", app_idx); return NULL; } @@ -193,19 +210,21 @@ int bt_mesh_node_local_net_key_add(uint16_t net_idx, const uint8_t net_key[16]) int err = 0; int i; + BT_DBG("NodeAddNetKeyLocal, NetIdx 0x%04x", net_idx); + if (net_idx > 0xFFF || net_key == NULL) { BT_ERR("%s, Invalid parameter", __func__); return -EINVAL; } if (!bt_mesh_is_provisioned()) { - BT_ERR("Not provisioned, failed to add NetKey"); + BT_ERR("NotProvisioned"); return -EIO; } sub = bt_mesh_subnet_get(net_idx); if (sub) { - BT_WARN("NetKey 0x%04x already exists", net_idx); + BT_WARN("NetIdxExist 0x%04x", net_idx); return -EEXIST; } @@ -215,7 +234,7 @@ int bt_mesh_node_local_net_key_add(uint16_t net_idx, const uint8_t net_key[16]) memcmp(bt_mesh.sub[i].keys[0].net, net_key, 16) == 0) || (bt_mesh.sub[i].kr_flag == true && memcmp(bt_mesh.sub[i].keys[1].net, net_key, 16) == 0)) { - BT_WARN("Key value %s already exists", bt_hex(net_key, 16)); + BT_WARN("NetKeyValExist %s", bt_hex(net_key, 16)); return -EEXIST; } } @@ -229,13 +248,13 @@ int bt_mesh_node_local_net_key_add(uint16_t net_idx, const uint8_t net_key[16]) } if (sub == NULL) { - BT_ERR("NetKey is full!"); + BT_ERR("NetKeyFull"); return -ENOMEM; } err = bt_mesh_net_keys_create(&sub->keys[0], net_key); if (err) { - BT_ERR("Failed to create keys for NetKey 0x%04x", net_idx); + BT_ERR("NetKeyCreateFail 0x%04x", net_idx); return -EIO; } @@ -249,7 +268,6 @@ int bt_mesh_node_local_net_key_add(uint16_t net_idx, const uint8_t net_key[16]) } if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { - BT_DBG("Storing NetKey persistently"); bt_mesh_store_subnet(sub); } @@ -264,24 +282,26 @@ int bt_mesh_node_local_app_key_add(uint16_t net_idx, uint16_t app_idx, { struct bt_mesh_app_key *key = NULL; + BT_DBG("NodeAddAppKeyLocal, NetIdx 0x%04x AppIdx 0x%04x", net_idx, app_idx); + if (net_idx > 0xFFF || app_idx > 0xFFF || app_key == NULL) { BT_ERR("%s, Invalid parameter", __func__); return -EINVAL; } if (!bt_mesh_is_provisioned()) { - BT_ERR("Not provisioned, failed to add AppKey"); + BT_ERR("NotProvisioned"); return -EIO; } if (bt_mesh_subnet_get(net_idx) == NULL) { - BT_ERR("Subnet 0x%04x not exists", net_idx); + BT_ERR("NetIdxNotExist 0x%04x", net_idx); return -EIO; } key = bt_mesh_app_key_get(app_idx); if (key) { - BT_WARN("AppKey 0x%04x already exists", app_idx); + BT_WARN("AppIdxExist 0x%04x", app_idx); return -EEXIST; } @@ -291,7 +311,7 @@ int bt_mesh_node_local_app_key_add(uint16_t net_idx, uint16_t app_idx, memcmp(bt_mesh.app_keys[i].keys[0].val, app_key, 16) == 0) || (bt_mesh.app_keys[i].updated == true && memcmp(bt_mesh.app_keys[i].keys[1].val, app_key, 16) == 0)) { - BT_WARN("Key value %s already exists", bt_hex(app_key, 16)); + BT_WARN("AppKeyValExist %s", bt_hex(app_key, 16)); return -EEXIST; } } @@ -302,7 +322,7 @@ int bt_mesh_node_local_app_key_add(uint16_t net_idx, uint16_t app_idx, struct bt_mesh_app_keys *keys = &key->keys[0]; if (bt_mesh_app_id(app_key, &keys->id)) { - BT_ERR("Failed to generate AID"); + BT_ERR("GenAIDFail"); return -EIO; } @@ -312,15 +332,12 @@ int bt_mesh_node_local_app_key_add(uint16_t net_idx, uint16_t app_idx, memcpy(keys->val, app_key, 16); if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { - BT_DBG("Storing AppKey persistently"); bt_mesh_store_app_key(key); } - BT_INFO("Add AppKey 0x%04x, NetKeyIndex 0x%04x", app_idx, net_idx); return 0; } - BT_ERR("AppKey is full!"); return -ENOMEM; } @@ -330,25 +347,29 @@ int bt_mesh_node_bind_app_key_to_model(uint16_t elem_addr, uint16_t mod_id, struct bt_mesh_model *model = NULL; int i; + BT_DBG("NodeBindAppKeyLocal"); + BT_DBG("ElemAddr 0x%04x CID 0x%04x ID 0x%04x AppIdx 0x%04x", + elem_addr, cid, mod_id, app_idx); + if (!bt_mesh_is_provisioned()) { - BT_ERR("Not provisioned, failed to bind AppKey"); + BT_ERR("NotProvisioned"); return -EIO; } model = find_model(elem_addr, cid, mod_id); if (model == NULL) { - BT_ERR("Bind, model(id 0x%04x, cid 0x%04x) not found", mod_id, cid); + BT_ERR("ModelNotFound, ID 0x%04x CID 0x%04x", mod_id, cid); return -ENODEV; } if (bt_mesh_app_key_get(app_idx) == NULL) { - BT_ERR("Bind, AppKey 0x%03x not exists", app_idx); + BT_ERR("AppIdxNotExist 0x%04x", app_idx); return -ENODEV; } for (i = 0; i < ARRAY_SIZE(model->keys); i++) { if (model->keys[i] == app_idx) { - BT_WARN("Already bound to AppKey 0x%04x", app_idx); + BT_WARN("AppIdxBound 0x%04x", app_idx); return -EALREADY; } } @@ -356,16 +377,16 @@ int bt_mesh_node_bind_app_key_to_model(uint16_t elem_addr, uint16_t mod_id, for (i = 0; i < ARRAY_SIZE(model->keys); i++) { if (model->keys[i] == BLE_MESH_KEY_UNUSED) { model->keys[i] = app_idx; + if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { bt_mesh_store_mod_bind(model); } - BT_INFO("Model(id 0x%04x, cid 0x%04x) bound to AppKey 0x%04x", mod_id, cid, app_idx); return 0; } } - BT_ERR("Model bound is full!"); + BT_ERR("ModelBindFull"); return -ENOMEM; } #endif /* CONFIG_BLE_MESH_NODE */ diff --git a/components/bt/esp_ble_mesh/core/lpn.c b/components/bt/esp_ble_mesh/core/lpn.c index 80f5b4321afc..a38b0944e4de 100644 --- a/components/bt/esp_ble_mesh/core/lpn.c +++ b/components/bt/esp_ble_mesh/core/lpn.c @@ -81,30 +81,30 @@ static const char *state2str(int state) { switch (state) { case BLE_MESH_LPN_DISABLED: - return "disabled"; + return "Disabled"; case BLE_MESH_LPN_CLEAR: - return "clear"; + return "Clear"; case BLE_MESH_LPN_TIMER: - return "timer"; + return "Timer"; case BLE_MESH_LPN_ENABLED: - return "enabled"; + return "Enabled"; case BLE_MESH_LPN_REQ_WAIT: - return "req wait"; + return "ReqWait"; case BLE_MESH_LPN_WAIT_OFFER: - return "wait offer"; + return "WaitOffer"; case BLE_MESH_LPN_ESTABLISHED: - return "established"; + return "Established"; case BLE_MESH_LPN_RECV_DELAY: - return "recv delay"; + return "RecvDelay"; case BLE_MESH_LPN_WAIT_UPDATE: - return "wait update"; + return "WaitUpdate"; case BLE_MESH_LPN_OFFER_RECV: - return "offer recv"; + return "OfferRecv"; default: - return "(unknown)"; + return "(Unknown)"; } } -#endif +#endif /* !CONFIG_BLE_MESH_NO_LOG */ static inline void lpn_set_state(int state) { @@ -120,9 +120,9 @@ static inline void group_zero(bt_mesh_atomic_t *target) for (i = 0; i < ARRAY_SIZE(bt_mesh.lpn.added); i++) { bt_mesh_atomic_set(&target[i], 0); } -#else +#else /* CONFIG_BLE_MESH_LPN_GROUPS > 32 */ bt_mesh_atomic_set(target, 0); -#endif +#endif /* CONFIG_BLE_MESH_LPN_GROUPS > 32 */ } static inline void group_set(bt_mesh_atomic_t *target, bt_mesh_atomic_t *source) @@ -133,9 +133,9 @@ static inline void group_set(bt_mesh_atomic_t *target, bt_mesh_atomic_t *source) for (i = 0; i < ARRAY_SIZE(bt_mesh.lpn.added); i++) { (void)bt_mesh_atomic_or(&target[i], bt_mesh_atomic_get(&source[i])); } -#else +#else /* CONFIG_BLE_MESH_LPN_GROUPS > 32 */ (void)bt_mesh_atomic_or(target, bt_mesh_atomic_get(source)); -#endif +#endif /* CONFIG_BLE_MESH_LPN_GROUPS > 32 */ } static inline void group_clear(bt_mesh_atomic_t *target, bt_mesh_atomic_t *source) @@ -146,9 +146,9 @@ static inline void group_clear(bt_mesh_atomic_t *target, bt_mesh_atomic_t *sourc for (i = 0; i < ARRAY_SIZE(bt_mesh.lpn.added); i++) { (void)bt_mesh_atomic_and(&target[i], ~bt_mesh_atomic_get(&source[i])); } -#else +#else /* CONFIG_BLE_MESH_LPN_GROUPS > 32 */ (void)bt_mesh_atomic_and(target, ~bt_mesh_atomic_get(source)); -#endif +#endif /* CONFIG_BLE_MESH_LPN_GROUPS > 32 */ } static void clear_friendship(bool force, bool disable); @@ -159,6 +159,8 @@ static void friend_clear_sent(int err, void *user_data) { struct bt_mesh_lpn *lpn = &bt_mesh.lpn; + BT_DBG("FrndClearSent, Err %d", err); + /* We're switching away from Low Power behavior, so permanently * enable scanning. */ @@ -169,6 +171,8 @@ static void friend_clear_sent(int err, void *user_data) lpn->req_attempts++; + BT_DBG("ReqAttempts %u", lpn->req_attempts); + if (err) { BT_ERR("Sending Friend Clear failed (err %d)", err); lpn_set_state(BLE_MESH_LPN_ENABLED); @@ -206,6 +210,8 @@ static int send_friend_clear(void) .lpn_counter = sys_cpu_to_be16(bt_mesh.lpn.counter), }; + BT_DBG("SendFrndClear"); + return bt_mesh_ctl_send(&tx, TRANS_CTL_OP_FRIEND_CLEAR, &req, sizeof(req), &clear_sent_cb, NULL); } @@ -215,10 +221,12 @@ static void clear_friendship(bool force, bool disable) struct bt_mesh_cfg_srv *cfg = bt_mesh_cfg_get(); struct bt_mesh_lpn *lpn = &bt_mesh.lpn; - BT_DBG("force %u disable %u", force, disable); + BT_DBG("ClearFriendship, Force %u Disable %u", force, disable); if (!force && lpn->established && !lpn->clear_success && lpn->req_attempts < CLEAR_ATTEMPTS) { + BT_DBG("SendFrndClear, ReqAttempts %u", lpn->req_attempts); + send_friend_clear(); lpn->disable = disable; return; @@ -253,7 +261,7 @@ static void clear_friendship(bool force, bool disable) bt_mesh_restore_directed_forwarding_state(bt_mesh.sub[0].net_idx, lpn->old_directed_forwarding); } -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ lpn->frnd = BLE_MESH_ADDR_UNASSIGNED; lpn->fsn = 0U; @@ -306,6 +314,8 @@ static void friend_req_sent(uint16_t duration, int err, void *user_data) return; } + BT_DBG("FrndReqSent, duration %u", duration); + lpn->adv_duration = duration; if (IS_ENABLED(CONFIG_BLE_MESH_LPN_ESTABLISHMENT)) { @@ -349,6 +359,8 @@ static int send_friend_req(struct bt_mesh_lpn *lpn) .lpn_counter = sys_cpu_to_be16(lpn->counter), }; + BT_DBG("SendFrndReq, NetIdx 0x%04x", ctx.net_idx); + return bt_mesh_ctl_send(&tx, TRANS_CTL_OP_FRIEND_REQ, &req, sizeof(req), &friend_req_sent_cb, NULL); } @@ -357,7 +369,7 @@ static void req_sent(uint16_t duration, int err, void *user_data) { struct bt_mesh_lpn *lpn = &bt_mesh.lpn; - BT_DBG("req 0x%02x duration %u err %d state %s", + BT_DBG("ReqSent, Req 0x%02x Duration %u Err %d State %s", lpn->sent_req, duration, err, state2str(lpn->state)); if (err) { @@ -372,6 +384,9 @@ static void req_sent(uint16_t duration, int err, void *user_data) if (lpn->established || IS_ENABLED(CONFIG_BLE_MESH_LPN_ESTABLISHMENT)) { lpn_set_state(BLE_MESH_LPN_RECV_DELAY); + + BT_DBG("RecvDelay %u ScanLatency %u", LPN_RECV_DELAY, SCAN_LATENCY); + /* We start scanning a bit early to eliminate risk of missing * response data due to HCI and other latencies. */ @@ -379,6 +394,9 @@ static void req_sent(uint16_t duration, int err, void *user_data) LPN_RECV_DELAY - SCAN_LATENCY); } else { lpn_set_state(BLE_MESH_LPN_OFFER_RECV); + + BT_DBG("RecvDelay %u RecvWin %u", LPN_RECV_DELAY, lpn->recv_win); + /** * Friend Update is replied by Friend Node with TTL set to 0 and Network * Transmit set to 30ms which will cause the packet easy to be missed. @@ -416,7 +434,7 @@ static int send_friend_poll(void) uint8_t fsn = lpn->fsn; int err = 0; - BT_DBG("lpn->sent_req 0x%02x", lpn->sent_req); + BT_DBG("SendFrndPoll, Req 0x%02x ", lpn->sent_req); if (lpn->sent_req) { if (lpn->sent_req != TRANS_CTL_OP_FRIEND_POLL) { @@ -438,6 +456,8 @@ static int send_friend_poll(void) void bt_mesh_lpn_disable(bool force) { + BT_DBG("LPNDisable, Force %u State 0x%02x", force, bt_mesh.lpn.state); + if (bt_mesh.lpn.state == BLE_MESH_LPN_DISABLED) { return; } @@ -449,6 +469,8 @@ int bt_mesh_lpn_set(bool enable, bool force) { struct bt_mesh_lpn *lpn = &bt_mesh.lpn; + BT_DBG("LPNSet, Enable %u Force %u State 0x%02x", enable, force, lpn->state); + if (enable) { if (lpn->state != BLE_MESH_LPN_DISABLED) { return 0; @@ -479,7 +501,7 @@ int bt_mesh_lpn_set(bool enable, bool force) send_friend_req(lpn); } else { if (IS_ENABLED(CONFIG_BLE_MESH_LPN_AUTO) && - lpn->state == BLE_MESH_LPN_TIMER) { + lpn->state == BLE_MESH_LPN_TIMER) { k_delayed_work_cancel(&lpn->timer); lpn_set_state(BLE_MESH_LPN_DISABLED); } else { @@ -492,7 +514,7 @@ int bt_mesh_lpn_set(bool enable, bool force) static void friend_response_received(struct bt_mesh_lpn *lpn) { - BT_DBG("lpn->sent_req 0x%02x", lpn->sent_req); + BT_DBG("FrndRspRecv, Req 0x%02x Fsn %u", lpn->sent_req, lpn->fsn); if (lpn->sent_req == TRANS_CTL_OP_FRIEND_POLL) { lpn->fsn++; @@ -509,6 +531,8 @@ void bt_mesh_lpn_msg_received(struct bt_mesh_net_rx *rx) { struct bt_mesh_lpn *lpn = &bt_mesh.lpn; + BT_DBG("LPNMsgRecv, Req 0x%02x State 0x%02x", lpn->sent_req, lpn->state); + if (lpn->state == BLE_MESH_LPN_TIMER) { BT_DBG("Restarting establishment timer"); k_delayed_work_submit(&lpn->timer, LPN_AUTO_TIMEOUT); @@ -522,8 +546,6 @@ void bt_mesh_lpn_msg_received(struct bt_mesh_net_rx *rx) friend_response_received(lpn); - BT_DBG("Requesting more messages from Friend"); - send_friend_poll(); } @@ -537,6 +559,8 @@ int bt_mesh_lpn_friend_offer(struct bt_mesh_net_rx *rx, uint16_t frnd_counter = 0U; int err = 0; + BT_DBG("LPNFrndOffer"); + if (buf->len < sizeof(*msg)) { BT_WARN("Too short Friend Offer"); return -EINVAL; @@ -554,9 +578,9 @@ int bt_mesh_lpn_friend_offer(struct bt_mesh_net_rx *rx, frnd_counter = sys_be16_to_cpu(msg->frnd_counter); - BT_INFO("recv_win %u queue_size %u sub_list_size %u rssi %d counter %u", - msg->recv_win, msg->queue_size, msg->sub_list_size, msg->rssi, - frnd_counter); + BT_INFO("Frnd 0x%04x RecvWin %u QueueSize %u SubListSize %u FrndCounter %u Rssi %d", + rx->ctx.addr, msg->recv_win, msg->queue_size, + msg->sub_list_size, frnd_counter, msg->rssi); lpn->frnd = rx->ctx.addr; @@ -575,6 +599,8 @@ int bt_mesh_lpn_friend_offer(struct bt_mesh_net_rx *rx, err = send_friend_poll(); if (err) { + BT_ERR("SendFrndPollFailed, Err %d", err); + friend_cred_clear(cred); lpn->frnd = BLE_MESH_ADDR_UNASSIGNED; lpn->recv_win = 0U; @@ -598,6 +624,8 @@ int bt_mesh_lpn_friend_clear_cfm(struct bt_mesh_net_rx *rx, struct bt_mesh_lpn *lpn = &bt_mesh.lpn; uint16_t addr = 0U, counter = 0U; + BT_DBG("LPNFrndClearCFM"); + if (buf->len < sizeof(*msg)) { BT_WARN("Too short Friend Clear Confirm"); return -EINVAL; @@ -611,7 +639,7 @@ int bt_mesh_lpn_friend_clear_cfm(struct bt_mesh_net_rx *rx, addr = sys_be16_to_cpu(msg->lpn_addr); counter = sys_be16_to_cpu(msg->lpn_counter); - BT_DBG("LPNAddress 0x%04x LPNCounter 0x%04x", addr, counter); + BT_DBG("LPN 0x%04x Counter 0x%04x", addr, counter); if (addr != bt_mesh_primary_addr() || counter != lpn->counter) { BT_WARN("Invalid parameters in Friend Clear Confirm"); @@ -630,8 +658,11 @@ static void lpn_group_add(uint16_t group) uint16_t *free_slot = NULL; int i; + BT_DBG("LPNGroupAdd, Addr 0x%04x", group); + for (i = 0; i < ARRAY_SIZE(lpn->groups); i++) { if (lpn->groups[i] == group) { + BT_DBG("ClearLPNToRemove"); bt_mesh_atomic_clear_bit(lpn->to_remove, i); return; } @@ -655,10 +686,13 @@ static void lpn_group_del(uint16_t group) struct bt_mesh_lpn *lpn = &bt_mesh.lpn; int i; + BT_DBG("LPNGroupDel, Addr 0x%04x", group); + for (i = 0; i < ARRAY_SIZE(lpn->groups); i++) { if (lpn->groups[i] == group) { if (bt_mesh_atomic_test_bit(lpn->added, i) || bt_mesh_atomic_test_bit(lpn->pending, i)) { + BT_DBG("Set LPNToRemove"); bt_mesh_atomic_set_bit(lpn->to_remove, i); lpn->groups_changed = 1U; } else { @@ -676,9 +710,9 @@ static inline int group_popcount(bt_mesh_atomic_t *target) for (i = 0; i < ARRAY_SIZE(bt_mesh.lpn.added); i++) { count += popcount(bt_mesh_atomic_get(&target[i])); } -#else +#else /* CONFIG_BLE_MESH_LPN_GROUPS > 32 */ return popcount(bt_mesh_atomic_get(target)); -#endif +#endif /* CONFIG_BLE_MESH_LPN_GROUPS > 32 */ } static bool sub_update(uint8_t op) @@ -703,7 +737,7 @@ static bool sub_update(uint8_t op) struct bt_mesh_ctl_friend_sub req = {0}; size_t i = 0U, g = 0U; - BT_DBG("op 0x%02x sent_req 0x%02x", op, lpn->sent_req); + BT_DBG("SubUpdate, OP 0x%02x Req 0x%02x ", op, lpn->sent_req); if (lpn->sent_req) { return false; @@ -725,7 +759,8 @@ static bool sub_update(uint8_t op) } if (added_count + g >= lpn->queue_size) { - BT_WARN("Friend Queue Size exceeded"); + BT_WARN("FrndQueueExceeded, Added %u G %u Size %u", + added_count, g, lpn->queue_size); break; } @@ -744,6 +779,8 @@ static bool sub_update(uint8_t op) req.xact = lpn->xact_next++; + BT_DBG("Xact %u G %u", req.xact, g); + if (bt_mesh_ctl_send(&tx, op, &req, 1 + g * 2, &req_sent_cb, NULL) < 0) { group_zero(lpn->pending); @@ -752,14 +789,19 @@ static bool sub_update(uint8_t op) lpn->xact_pending = req.xact; lpn->sent_req = op; + return true; } static void update_timeout(struct bt_mesh_lpn *lpn) { + BT_DBG("UpdateTimeout"); + if (lpn->established) { BT_WARN("No response from Friend during ReceiveWindow"); + bt_mesh_scan_disable(); + lpn_set_state(BLE_MESH_LPN_ESTABLISHED); k_delayed_work_submit(&lpn->timer, POLL_RETRY_TIMEOUT); } else { @@ -767,6 +809,8 @@ static void update_timeout(struct bt_mesh_lpn *lpn) bt_mesh_scan_disable(); } + BT_DBG("ReqAttempts %u", lpn->req_attempts); + if (lpn->req_attempts < FIRST_POLL_ATTEMPTS) { BT_WARN("Retrying first Friend Poll"); lpn->sent_req = 0U; @@ -784,7 +828,7 @@ static void lpn_timeout(struct k_work *work) { struct bt_mesh_lpn *lpn = &bt_mesh.lpn; - BT_DBG("state: %s", state2str(lpn->state)); + BT_DBG("LPNTimeout, State: %s", state2str(lpn->state)); switch (lpn->state) { case BLE_MESH_LPN_DISABLED: @@ -830,6 +874,8 @@ static void lpn_timeout(struct k_work *work) clear_friendship(true, false); break; case BLE_MESH_LPN_ESTABLISHED: + BT_DBG("ReqAttempts %u vs. %u", lpn->req_attempts, REQ_ATTEMPTS(lpn)); + if (lpn->req_attempts < REQ_ATTEMPTS(lpn)) { uint8_t req = lpn->sent_req; @@ -867,11 +913,13 @@ static void lpn_timeout(struct k_work *work) void bt_mesh_lpn_group_add(uint16_t group) { - BT_DBG("group 0x%04x", group); + BT_DBG("LPNGroupAdd, Addr 0x%04x", group); lpn_group_add(group); if (!bt_mesh_lpn_established() || bt_mesh.lpn.sent_req) { + BT_INFO("Established %u Req 0x%02x", + bt_mesh_lpn_established(), bt_mesh.lpn.sent_req); return; } @@ -882,6 +930,8 @@ void bt_mesh_lpn_group_del(uint16_t *groups, size_t group_count) { int i; + BT_DBG("LPNGroupDel, GroupCount %u", group_count); + for (i = 0; i < group_count; i++) { if (groups[i] != BLE_MESH_ADDR_UNASSIGNED) { BT_DBG("group 0x%04x", groups[i]); @@ -890,6 +940,8 @@ void bt_mesh_lpn_group_del(uint16_t *groups, size_t group_count) } if (!bt_mesh_lpn_established() || bt_mesh.lpn.sent_req) { + BT_INFO("Established %u Req 0x%02x", + bt_mesh_lpn_established(), bt_mesh.lpn.sent_req); return; } @@ -900,6 +952,7 @@ static int32_t poll_timeout(struct bt_mesh_lpn *lpn) { /* If we're waiting for segment acks keep polling at high freq */ if (bt_mesh_tx_in_progress()) { + BT_DBG("PollTimeout, Max %u", POLL_TIMEOUT_MAX(lpn)); return MIN(POLL_TIMEOUT_MAX(lpn), K_SECONDS(1)); } @@ -909,7 +962,7 @@ static int32_t poll_timeout(struct bt_mesh_lpn *lpn) POLL_TIMEOUT_MAX(lpn)); } - BT_DBG("Poll Timeout is %ums", lpn->poll_timeout); + BT_DBG("PollTimeout %u", lpn->poll_timeout); return lpn->poll_timeout; } @@ -920,12 +973,15 @@ int bt_mesh_lpn_friend_sub_cfm(struct bt_mesh_net_rx *rx, struct bt_mesh_ctl_friend_sub_confirm *msg = (void *)buf->data; struct bt_mesh_lpn *lpn = &bt_mesh.lpn; + BT_DBG("LPNFrndSubCFM"); + if (buf->len < sizeof(*msg)) { BT_WARN("Too short Friend Subscription Confirm"); return -EINVAL; } - BT_DBG("xact 0x%02x", msg->xact); + BT_DBG("Xact %u Req 0x%02x GroupsChanged %u PendingPoll %u", + msg->xact, lpn->sent_req, lpn->groups_changed, lpn->pending_poll); if (!lpn->sent_req) { BT_WARN("No pending subscription list message"); @@ -987,11 +1043,16 @@ int bt_mesh_lpn_friend_update(struct bt_mesh_net_rx *rx, struct bt_mesh_subnet *sub = rx->sub; uint32_t iv_index = 0U; + BT_DBG("LPNFrndUpdate"); + if (buf->len < sizeof(*msg)) { BT_WARN("Too short Friend Update"); return -EINVAL; } + BT_DBG("Req 0x%02x KrPhase %u Established %u", + lpn->sent_req, sub->kr_phase, lpn->established); + if (lpn->sent_req != TRANS_CTL_OP_FRIEND_POLL) { BT_WARN("Unexpected friend update"); return 0; @@ -1034,8 +1095,7 @@ int bt_mesh_lpn_friend_update(struct bt_mesh_net_rx *rx, } /* Set initial poll timeout */ - lpn->poll_timeout = MIN(POLL_TIMEOUT_MAX(lpn), - POLL_TIMEOUT_INIT); + lpn->poll_timeout = MIN(POLL_TIMEOUT_MAX(lpn), POLL_TIMEOUT_INIT); /* If the Low Power node supports directed forwarding functionality when * the friendship is established in a subnet, the Low Power node shall @@ -1046,18 +1106,16 @@ int bt_mesh_lpn_friend_update(struct bt_mesh_net_rx *rx, */ #if CONFIG_BLE_MESH_DF_SRV lpn->old_directed_forwarding = bt_mesh_get_and_disable_directed_forwarding_state(sub); -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ } friend_response_received(lpn); iv_index = sys_be32_to_cpu(msg->iv_index); - BT_INFO("flags 0x%02x iv_index 0x%08x md %u", msg->flags, iv_index, - msg->md); + BT_INFO("Flags 0x%02x IVIndex 0x%08lx MD %u", msg->flags, iv_index, msg->md); - if (bt_mesh_kr_update(sub, BLE_MESH_KEY_REFRESH(msg->flags), - rx->new_key)) { + if (bt_mesh_kr_update(sub, BLE_MESH_KEY_REFRESH(msg->flags), rx->new_key)) { bt_mesh_net_secure_beacon_update(sub); } @@ -1086,12 +1144,12 @@ int bt_mesh_lpn_friend_update(struct bt_mesh_net_rx *rx, int bt_mesh_lpn_poll(void) { + BT_DBG("LPNPoll, Established %u", bt_mesh.lpn.established); + if (!bt_mesh.lpn.established) { return -EAGAIN; } - BT_DBG("Requesting more messages"); - return send_friend_poll(); } @@ -1104,6 +1162,8 @@ int bt_mesh_lpn_init(void) { struct bt_mesh_lpn *lpn = &bt_mesh.lpn; + BT_DBG("LPNInit"); + k_delayed_work_init(&lpn->timer, lpn_timeout); if (lpn->state == BLE_MESH_LPN_ENABLED) { @@ -1130,6 +1190,8 @@ int bt_mesh_lpn_deinit(void) { struct bt_mesh_lpn *lpn = &bt_mesh.lpn; + BT_DBG("LPNDeinit"); + bt_mesh_lpn_disable(true); k_delayed_work_free(&lpn->timer); diff --git a/components/bt/esp_ble_mesh/core/main.c b/components/bt/esp_ble_mesh/core/main.c index 957234e312e3..cc5543697e9a 100644 --- a/components/bt/esp_ble_mesh/core/main.c +++ b/components/bt/esp_ble_mesh/core/main.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -32,12 +32,14 @@ #if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" -#endif +#endif /* CONFIG_BLE_MESH_V11_SUPPORT */ static bool mesh_init = false; bool bt_mesh_is_initialized(void) { + BT_DBG("IsInitialized %u", mesh_init); + return mesh_init; } @@ -48,9 +50,10 @@ int bt_mesh_provision(const uint8_t net_key[16], uint16_t net_idx, bool pb_gatt_enabled = false; int err = 0; - BT_INFO("Primary Element: 0x%04x", addr); - BT_INFO("net_idx 0x%04x flags 0x%02x iv_index 0x%04x", - net_idx, flags, iv_index); + BT_INFO("NodeProvisioned"); + BT_INFO("PrimaryAddr 0x%04x", addr); + BT_INFO("NetIdx 0x%04x Flags 0x%02x IVIndex 0x%08lx", + net_idx, flags, iv_index); BT_INFO("DevKey %s", bt_hex(dev_key, 16)); BT_INFO("NetKey %s", bt_hex(net_key, 16)); @@ -69,9 +72,12 @@ int bt_mesh_provision(const uint8_t net_key[16], uint16_t net_idx, pb_gatt_enabled = false; } + BT_DBG("PbGattEnabled %u", pb_gatt_enabled); + err = bt_mesh_net_create(net_idx, flags, net_key, iv_index); if (err) { BT_ERR("Create network for node failed"); + bt_mesh_atomic_clear_bit(bt_mesh.flags, BLE_MESH_VALID); if (IS_ENABLED(CONFIG_BLE_MESH_PB_GATT) && pb_gatt_enabled) { @@ -89,11 +95,11 @@ int bt_mesh_provision(const uint8_t net_key[16], uint16_t net_idx, if (IS_ENABLED(CONFIG_BLE_MESH_LOW_POWER) && IS_ENABLED(CONFIG_BLE_MESH_LPN_SUB_ALL_NODES_ADDR)) { + BT_DBG("LPNAllNodesAdded"); bt_mesh_lpn_group_add(BLE_MESH_ADDR_ALL_NODES); } if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { - BT_DBG("Storing network information persistently"); bt_mesh_store_net(); bt_mesh_store_subnet(&bt_mesh.sub[0]); bt_mesh_store_iv(false); @@ -106,6 +112,8 @@ int bt_mesh_provision(const uint8_t net_key[16], uint16_t net_idx, void bt_mesh_node_reset(void) { + BT_DBG("NodeLocalReset"); + if (!bt_mesh_is_provisioned()) { BT_WARN("%s, Not provisioned", __func__); return; @@ -154,7 +162,7 @@ void bt_mesh_node_reset(void) #if CONFIG_BLE_MESH_PRB_SRV bt_mesh_private_beacon_disable(); -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ bt_mesh_comp_unprovision(); @@ -165,7 +173,7 @@ void bt_mesh_node_reset(void) bt_mesh_clear_role(); #if CONFIG_BLE_MESH_DF_SRV bt_mesh_clear_all_directed_forwarding_table_data(); -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ } memset(bt_mesh.flags, 0, sizeof(bt_mesh.flags)); @@ -177,34 +185,52 @@ void bt_mesh_node_reset(void) bool bt_mesh_is_node(void) { - return bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_NODE); + bool is_node = bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_NODE); + + BT_DBG("IsNode %u", is_node); + + return is_node; } bool bt_mesh_is_provisioned(void) { + bool is_provisioned = false; + if (bt_mesh_is_node()) { - return bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_VALID); - } else { - return false; + is_provisioned = bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_VALID); } + + BT_DBG("IsProvisioned %u", is_provisioned); + + return is_provisioned; } bool bt_mesh_is_provisioner(void) { - return bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_PROVISIONER); + bool is_pvnr = bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_PROVISIONER); + + BT_DBG("IsPvnr %u", is_pvnr); + + return is_pvnr; } bool bt_mesh_is_provisioner_en(void) { + bool is_pvnr_en = false; + if (bt_mesh_is_provisioner()) { - return bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_VALID_PROV); + is_pvnr_en = bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_VALID_PROV); } - return false; + BT_DBG("IsPvnrEn %u", is_pvnr_en); + + return is_pvnr_en; } static bool prov_bearers_valid(bt_mesh_prov_bearer_t bearers) { + BT_DBG("ProvBearersValid, Bearers 0x%02x", bearers); + if ((!(bearers & (BLE_MESH_PROV_ADV | BLE_MESH_PROV_GATT))) || (IS_ENABLED(CONFIG_BLE_MESH_PB_ADV) && !IS_ENABLED(CONFIG_BLE_MESH_PB_GATT) && @@ -215,6 +241,7 @@ static bool prov_bearers_valid(bt_mesh_prov_bearer_t bearers) BT_ERR("Invalid bearers 0x%02x", bearers); return false; } + return true; } @@ -222,6 +249,8 @@ int bt_mesh_prov_enable(bt_mesh_prov_bearer_t bearers) { int err = 0; + BT_DBG("ProvEnable, Bearers 0x%02x", bearers); + if (bt_mesh_is_provisioned()) { BT_WARN("%s, Already", __func__); return -EALREADY; @@ -247,6 +276,7 @@ int bt_mesh_prov_enable(bt_mesh_prov_bearer_t bearers) if (role == BLE_MESH_SETTINGS_ROLE_NONE) { bt_mesh_atomic_set_bit(bt_mesh.flags, BLE_MESH_NODE); } + if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS_BACKWARD_COMPATIBILITY) || role == BLE_MESH_SETTINGS_ROLE_NONE) { if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { @@ -277,6 +307,8 @@ int bt_mesh_prov_enable(bt_mesh_prov_bearer_t bearers) int bt_mesh_prov_disable(bt_mesh_prov_bearer_t bearers) { + BT_DBG("ProvDisable, Bearers 0x%02x", bearers); + if (bt_mesh_is_provisioned()) { BT_WARN("%s, Already provisioned", __func__); return -EALREADY; @@ -309,6 +341,8 @@ int bt_mesh_prov_disable(bt_mesh_prov_bearer_t bearers) static void model_suspend(struct bt_mesh_model *mod, struct bt_mesh_elem *elem, bool vnd, bool primary, void *user_data) { + BT_DBG("ModelSuspend, Vnd %u Primary %u", vnd, primary); + if (mod->pub && mod->pub->update) { mod->pub->count = 0U; k_delayed_work_cancel(&mod->pub->timer); @@ -319,6 +353,8 @@ int bt_mesh_suspend(void) { int err = 0; + BT_DBG("Suspend"); + if (!bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_VALID)) { return -EINVAL; } @@ -344,7 +380,7 @@ int bt_mesh_suspend(void) if (bt_mesh_private_beacon_state_get() == BLE_MESH_PRIVATE_BEACON_ENABLED) { bt_mesh_private_beacon_disable(); } -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ bt_mesh_model_foreach(model_suspend, NULL); @@ -354,6 +390,8 @@ int bt_mesh_suspend(void) static void model_resume(struct bt_mesh_model *mod, struct bt_mesh_elem *elem, bool vnd, bool primary, void *user_data) { + BT_DBG("ModelResume, Vnd %u Primary %u", vnd, primary); + if (mod->pub && mod->pub->update) { int32_t period_ms = bt_mesh_model_pub_period_get(mod); @@ -367,6 +405,8 @@ int bt_mesh_resume(void) { int err = 0; + BT_DBG("Resume"); + if (!bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_VALID)) { return -EINVAL; } @@ -390,7 +430,7 @@ int bt_mesh_resume(void) if (bt_mesh_private_beacon_state_get() == BLE_MESH_PRIVATE_BEACON_ENABLED) { bt_mesh_private_beacon_enable(); } -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ bt_mesh_model_foreach(model_resume, NULL); @@ -402,6 +442,8 @@ int bt_mesh_init(const struct bt_mesh_prov *prov, { int err = 0; + BT_DBG("Init"); + if (mesh_init == true) { BT_WARN("%s, Already", __func__); return -EALREADY; @@ -414,7 +456,7 @@ int bt_mesh_init(const struct bt_mesh_prov *prov, BT_ERR("Bluetooth Mesh v1.1 init failed"); return err; } -#endif +#endif /* CONFIG_BLE_MESH_V11_SUPPORT */ bt_mesh_mutex_init(); @@ -452,7 +494,7 @@ int bt_mesh_init(const struct bt_mesh_prov *prov, if (err) { return err; } -#endif +#endif /* CONFIG_BLE_MESH_PROXY_SOLIC */ if (IS_ENABLED(CONFIG_BLE_MESH_PROV)) { err = bt_mesh_prov_set(prov); @@ -507,6 +549,8 @@ int bt_mesh_deinit(struct bt_mesh_deinit_param *param) { int err = 0; + BT_DBG("Deinit"); + if (param == NULL) { BT_ERR("%s, Invalid parameter", __func__); return -EINVAL; @@ -522,7 +566,7 @@ int bt_mesh_deinit(struct bt_mesh_deinit_param *param) #if CONFIG_BLE_MESH_PRB_SRV bt_mesh_private_beacon_disable(); -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ if (IS_ENABLED(CONFIG_BLE_MESH_NODE) && bt_mesh_is_node()) { if (IS_ENABLED(CONFIG_BLE_MESH_PB_GATT) && @@ -583,7 +627,7 @@ int bt_mesh_deinit(struct bt_mesh_deinit_param *param) #if CONFIG_BLE_MESH_PROXY_SOLIC bt_mesh_proxy_solic_deinit(); -#endif +#endif /* CONFIG_BLE_MESH_PROXY_SOLIC */ if ((IS_ENABLED(CONFIG_BLE_MESH_NODE) && IS_ENABLED(CONFIG_BLE_MESH_PB_GATT)) || @@ -638,6 +682,8 @@ int bt_mesh_provisioner_enable(bt_mesh_prov_bearer_t bearers) { int err = 0; + BT_DBG("PvnrEnable, Bearers 0x%02x", bearers); + if (bt_mesh_is_provisioner_en()) { BT_WARN("%s, Already", __func__); return -EALREADY; @@ -703,7 +749,7 @@ int bt_mesh_provisioner_enable(bt_mesh_prov_bearer_t bearers) BLE_MESH_EXCEP_LIST_TYPE_MESH_PROV_ADV, NULL); } -#endif +#endif /* CONFIG_BLE_MESH_USE_DUPLICATE_SCAN */ if (IS_ENABLED(CONFIG_BLE_MESH_PB_GATT) && (bearers & BLE_MESH_PROV_GATT)) { @@ -722,7 +768,7 @@ int bt_mesh_provisioner_enable(bt_mesh_prov_bearer_t bearers) if (bt_mesh_private_beacon_state_get() == BLE_MESH_PRIVATE_BEACON_ENABLED) { bt_mesh_private_beacon_enable(); } -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ err = bt_mesh_scan_enable(); if (err) { @@ -736,6 +782,8 @@ int bt_mesh_provisioner_disable(bt_mesh_prov_bearer_t bearers) { bt_mesh_prov_bearer_t enable = 0U; + BT_DBG("PvnrDisable, Bearers 0x%02x", bearers); + if (!bt_mesh_is_provisioner_en()) { BT_WARN("%s, Already", __func__); return -EALREADY; @@ -762,7 +810,7 @@ int bt_mesh_provisioner_disable(bt_mesh_prov_bearer_t bearers) bt_mesh_update_exceptional_list(BLE_MESH_EXCEP_LIST_SUB_CODE_REMOVE, BLE_MESH_EXCEP_LIST_TYPE_MESH_PROV_ADV, NULL); -#endif +#endif /* CONFIG_BLE_MESH_USE_DUPLICATE_SCAN */ } if (!(enable & (~bearers))) { @@ -776,7 +824,7 @@ int bt_mesh_provisioner_disable(bt_mesh_prov_bearer_t bearers) BLE_MESH_EXCEP_LIST_TYPE_MESH_BEACON, NULL); } -#endif +#endif /* CONFIG_BLE_MESH_USE_DUPLICATE_SCAN */ /* Clear corresponding flags */ bt_mesh_atomic_and(bt_mesh.flags, ~(BIT(BLE_MESH_PROVISIONER) | BIT(BLE_MESH_VALID_PROV))); @@ -794,7 +842,7 @@ int bt_mesh_provisioner_disable(bt_mesh_prov_bearer_t bearers) if (bt_mesh_private_beacon_state_get() == BLE_MESH_PRIVATE_BEACON_ENABLED) { bt_mesh_private_beacon_disable(); } -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND)) { bt_mesh_friend_clear_net_idx(BLE_MESH_KEY_ANY); diff --git a/components/bt/esp_ble_mesh/core/net.c b/components/bt/esp_ble_mesh/core/net.c index 15d099cc5cd3..209b0fdabd50 100644 --- a/components/bt/esp_ble_mesh/core/net.c +++ b/components/bt/esp_ble_mesh/core/net.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -33,7 +33,7 @@ #if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" -#endif +#endif /* CONFIG_BLE_MESH_V11_SUPPORT */ /* Minimum valid Mesh Network PDU length. The Network headers * themselves take up 9 bytes. After that there is a minimum of 1 byte @@ -41,23 +41,27 @@ * PDUs must use a 64-bit (8 byte) NetMIC, whereas CTL=0 PDUs have at least * a 32-bit (4 byte) NetMIC and AppMIC giving again a total of 8 bytes. */ -#define BLE_MESH_NET_MIN_PDU_LEN (BLE_MESH_NET_HDR_LEN + 1 + 8) +#define BLE_MESH_NET_MIN_PDU_LEN (BLE_MESH_NET_HDR_LEN + 1 + 8) /* Seq limit after IV Update is triggered */ -#define IV_UPDATE_SEQ_LIMIT 8000000 +#define IV_UPDATE_SEQ_LIMIT 8000000 /* Determine how many friendship credentials we need */ #if CONFIG_BLE_MESH_FRIEND -#define FRIEND_CRED_COUNT CONFIG_BLE_MESH_FRIEND_LPN_COUNT +#define FRIEND_CRED_COUNT CONFIG_BLE_MESH_FRIEND_LPN_COUNT #elif CONFIG_BLE_MESH_LOW_POWER -#define FRIEND_CRED_COUNT CONFIG_BLE_MESH_SUBNET_COUNT +#define FRIEND_CRED_COUNT CONFIG_BLE_MESH_SUBNET_COUNT #else -#define FRIEND_CRED_COUNT 0 +#define FRIEND_CRED_COUNT 0 #endif +#if CONFIG_BLE_MESH_RELAY_ADV_BUF +#define MAX_STORED_RELAY_COUNT (CONFIG_BLE_MESH_RELAY_ADV_BUF_COUNT / 2) +#endif /* CONFIG_BLE_MESH_RELAY_ADV_BUF */ + #if FRIEND_CRED_COUNT > 0 static struct friend_cred friend_cred[FRIEND_CRED_COUNT]; -#endif +#endif /* FRIEND_CRED_COUNT > 0 */ static struct { uint32_t src:15, /* MSB of source address is always 0 */ @@ -83,10 +87,6 @@ struct bt_mesh_net bt_mesh = { static uint32_t dup_cache[4]; static int dup_cache_next; -#if CONFIG_BLE_MESH_RELAY_ADV_BUF -#define BLE_MESH_MAX_STORED_RELAY_COUNT (CONFIG_BLE_MESH_RELAY_ADV_BUF_COUNT / 2) -#endif - static bool check_dup(struct net_buf_simple *data) { const uint8_t *tail = net_buf_simple_tail(data); @@ -95,12 +95,17 @@ static bool check_dup(struct net_buf_simple *data) val = sys_get_be32(tail - 4) ^ sys_get_be32(tail - 8); + BT_DBG("CheckDup, Val 0x%08lx", val); + for (i = 0; i < ARRAY_SIZE(dup_cache); i++) { if (dup_cache[i] == val) { + BT_DBG("DupCacheFound"); return true; } } + BT_DBG("DupCacheAdd, CacheNext %ld %d", val, dup_cache_next); + dup_cache[dup_cache_next++] = val; dup_cache_next %= ARRAY_SIZE(dup_cache); @@ -112,9 +117,13 @@ static bool msg_cache_match(struct bt_mesh_net_rx *rx, { int i; + BT_DBG("MsgCacheMatch"); + for (i = 0; i < ARRAY_SIZE(msg_cache); i++) { if (msg_cache[i].src == BLE_MESH_NET_HDR_SRC(pdu->data) && msg_cache[i].seq == (BLE_MESH_NET_HDR_SEQ(pdu->data) & BIT_MASK(17))) { + BT_DBG("CacheFound, Src 0x%04x Seq 0x%06x", + msg_cache[i].src, msg_cache[i].seq); return true; } } @@ -124,6 +133,9 @@ static bool msg_cache_match(struct bt_mesh_net_rx *rx, static void msg_cache_add(struct bt_mesh_net_rx *rx) { + BT_DBG("MsgCacheAdd, Src 0x%04x Seq 0x%06x CacheNext %u", + rx->ctx.addr, rx->seq, msg_cache_next); + rx->msg_cache_idx = msg_cache_next++; msg_cache[rx->msg_cache_idx].src = rx->ctx.addr; msg_cache[rx->msg_cache_idx].seq = rx->seq; @@ -135,6 +147,8 @@ void bt_mesh_msg_cache_clear(uint16_t unicast_addr, uint8_t elem_num) { int i; + BT_DBG("MsgCacheClear, Addr 0x%04x ElemNum %u", unicast_addr, elem_num); + for (i = 0; i < ARRAY_SIZE(msg_cache); i++) { if (msg_cache[i].src >= unicast_addr && msg_cache[i].src < unicast_addr + elem_num) { @@ -146,6 +160,8 @@ void bt_mesh_msg_cache_clear(uint16_t unicast_addr, uint8_t elem_num) struct bt_mesh_subnet *bt_mesh_subnet_get(uint16_t net_idx) { + BT_DBG("SubnetGet, NetIdx 0x%04x", net_idx); + if (bt_mesh_is_provisioned()) { #if CONFIG_BLE_MESH_NODE if (!IS_ENABLED(CONFIG_BLE_MESH_FAST_PROV)) { @@ -161,7 +177,7 @@ struct bt_mesh_subnet *bt_mesh_subnet_get(uint16_t net_idx) } else { return bt_mesh_fast_prov_subnet_get(net_idx); } -#endif +#endif /* CONFIG_BLE_MESH_NODE */ } else if (bt_mesh_is_provisioner_en()) { #if CONFIG_BLE_MESH_PROVISIONER if (net_idx == BLE_MESH_KEY_ANY) { @@ -174,7 +190,7 @@ struct bt_mesh_subnet *bt_mesh_subnet_get(uint16_t net_idx) return bt_mesh.p_sub[i]; } } -#endif +#endif /* CONFIG_BLE_MESH_PROVISIONER */ } return NULL; @@ -187,6 +203,8 @@ int bt_mesh_net_keys_create(struct bt_mesh_subnet_keys *keys, uint8_t nid = 0U; int err = 0; + BT_DBG("NetKeysCreate"); + err = bt_mesh_k2(key, p, sizeof(p), &nid, keys->enc, keys->privacy); if (err) { BT_ERR("Unable to generate NID, EncKey & PrivacyKey"); @@ -258,6 +276,9 @@ int friend_cred_set(struct friend_cred *cred, uint8_t idx, const uint8_t net_key uint8_t p[9] = {0}; int err = 0; + BT_DBG("FrndCredSet, NetIdx 0x%04x Addr 0x%04x Idx %u", + cred->net_idx, cred->addr, idx); + #if CONFIG_BLE_MESH_LOW_POWER if (cred->addr == bt_mesh.lpn.frnd) { lpn_addr = bt_mesh_primary_addr(); @@ -266,14 +287,13 @@ int friend_cred_set(struct friend_cred *cred, uint8_t idx, const uint8_t net_key lpn_addr = cred->addr; frnd_addr = bt_mesh_primary_addr(); } -#else +#else /* CONFIG_BLE_MESH_LOW_POWER */ lpn_addr = cred->addr; frnd_addr = bt_mesh_primary_addr(); -#endif +#endif /* CONFIG_BLE_MESH_LOW_POWER */ - BT_DBG("LPNAddress 0x%04x FriendAddress 0x%04x", lpn_addr, frnd_addr); - BT_DBG("LPNCounter 0x%04x FriendCounter 0x%04x", cred->lpn_counter, - cred->frnd_counter); + BT_DBG("LPN 0x%04x Frnd 0x%04x LPNCounter %u FrndCounter %u", + lpn_addr, frnd_addr, cred->lpn_counter, cred->frnd_counter); p[0] = 0x01; sys_put_be16(lpn_addr, p + 1); @@ -288,9 +308,9 @@ int friend_cred_set(struct friend_cred *cred, uint8_t idx, const uint8_t net_key return err; } - BT_DBG("Friend NID 0x%02x EncKey %s", cred->cred[idx].nid, - bt_hex(cred->cred[idx].enc, 16)); - BT_DBG("Friend PrivacyKey %s", bt_hex(cred->cred[idx].privacy, 16)); + BT_DBG("FrndNID 0x%02x EncKey %s", + cred->cred[idx].nid, bt_hex(cred->cred[idx].enc, 16)); + BT_DBG("FrndPrivacyKey %s", bt_hex(cred->cred[idx].privacy, 16)); return 0; } @@ -299,11 +319,14 @@ void friend_cred_refresh(uint16_t net_idx) { int i; + BT_DBG("FrndCredRefresh, NetIdx 0x%04x", net_idx); + for (i = 0; i < ARRAY_SIZE(friend_cred); i++) { struct friend_cred *cred = &friend_cred[i]; if (cred->addr != BLE_MESH_ADDR_UNASSIGNED && cred->net_idx == net_idx) { + BT_DBG("Refreshed, Addr 0x%04x", cred->addr); memcpy(&cred->cred[0], &cred->cred[1], sizeof(cred->cred[0])); } @@ -314,7 +337,7 @@ int friend_cred_update(struct bt_mesh_subnet *sub) { int err = 0, i; - BT_DBG("net_idx 0x%04x", sub->net_idx); + BT_DBG("FrndCredUpdate, NetIdx 0x%04x", sub->net_idx); for (i = 0; i < ARRAY_SIZE(friend_cred); i++) { struct friend_cred *cred = &friend_cred[i]; @@ -324,6 +347,8 @@ int friend_cred_update(struct bt_mesh_subnet *sub) continue; } + BT_DBG("UpdateFound, Addr 0x%04x", cred->addr); + err = friend_cred_set(cred, 1, sub->keys[1].net); if (err) { return err; @@ -339,7 +364,8 @@ struct friend_cred *friend_cred_create(struct bt_mesh_subnet *sub, uint16_t addr struct friend_cred *cred = NULL; int i, err = 0; - BT_DBG("net_idx 0x%04x addr 0x%04x", sub->net_idx, addr); + BT_DBG("FrndCredCreate, NetIdx 0x%04x KrFlag %u Addr 0x%04x", + sub->net_idx, sub->kr_flag, addr); for (cred = NULL, i = 0; i < ARRAY_SIZE(friend_cred); i++) { if ((friend_cred[i].addr == BLE_MESH_ADDR_UNASSIGNED) || @@ -379,6 +405,8 @@ struct friend_cred *friend_cred_create(struct bt_mesh_subnet *sub, uint16_t addr void friend_cred_clear(struct friend_cred *cred) { + BT_DBG("FrndCredClear, NetIdx 0x%04x Addr 0x%04x", cred->net_idx, cred->addr); + cred->net_idx = BLE_MESH_KEY_UNUSED; cred->addr = BLE_MESH_ADDR_UNASSIGNED; cred->lpn_counter = 0U; @@ -390,9 +418,13 @@ int friend_cred_del(uint16_t net_idx, uint16_t addr) { int i; + BT_DBG("FrndCredDel, NetIdx 0x%04x Addr 0x%04x", net_idx, addr); + for (i = 0; i < ARRAY_SIZE(friend_cred); i++) { struct friend_cred *cred = &friend_cred[i]; + BT_DBG("%u: NetIdx 0x%04x Addr 0x%04x", i, cred->net_idx, cred->addr); + if (cred->addr == addr && cred->net_idx == net_idx) { friend_cred_clear(cred); return 0; @@ -407,7 +439,8 @@ int friend_cred_get(struct bt_mesh_subnet *sub, uint16_t addr, uint8_t *nid, { int i; - BT_DBG("net_idx 0x%04x addr 0x%04x", sub->net_idx, addr); + BT_DBG("FrndCredGet, NetIdx 0x%04x KrFlag %u Addr 0x%04x", + sub->net_idx, sub->kr_flag, addr); for (i = 0; i < ARRAY_SIZE(friend_cred); i++) { struct friend_cred *cred = &friend_cred[i]; @@ -437,13 +470,15 @@ int friend_cred_get(struct bt_mesh_subnet *sub, uint16_t addr, uint8_t *nid, return -ENOENT; } -#else +#else /* (CONFIG_BLE_MESH_LOW_POWER || CONFIG_BLE_MESH_FRIEND) */ int friend_cred_get(struct bt_mesh_subnet *sub, uint16_t addr, uint8_t *nid, const uint8_t **enc, const uint8_t **priv) { + BT_DBG("FrndCredGetNoEnt"); + return -ENOENT; } -#endif /* FRIEND || LOW_POWER */ +#endif /* (CONFIG_BLE_MESH_LOW_POWER || CONFIG_BLE_MESH_FRIEND) */ uint8_t bt_mesh_net_flags(struct bt_mesh_subnet *sub) { @@ -457,36 +492,40 @@ uint8_t bt_mesh_net_flags(struct bt_mesh_subnet *sub) flags |= BLE_MESH_NET_FLAG_IVU; } + BT_DBG("NetFlags 0x%02x", flags); + return flags; } int bt_mesh_net_secure_beacon_update(struct bt_mesh_subnet *sub) { - uint8_t flags = bt_mesh_net_flags(sub); struct bt_mesh_subnet_keys *keys = NULL; + uint8_t flags = 0; + + BT_DBG("SecureBeaconUpdate, NetIdx 0x%04x KrFlag %u IVIndex %lu", + sub->net_idx, sub->kr_flag, bt_mesh.iv_index); if (sub->kr_flag) { - BT_DBG("NetIndex %u Using new key", sub->net_idx); keys = &sub->keys[1]; } else { - BT_DBG("NetIndex %u Using current key", sub->net_idx); keys = &sub->keys[0]; } - BT_DBG("flags 0x%02x, IVI 0x%08x", flags, bt_mesh.iv_index); + flags = bt_mesh_net_flags(sub); return bt_mesh_secure_beacon_auth(keys->beacon, flags, keys->net_id, bt_mesh.iv_index, sub->auth); } -int bt_mesh_net_create(uint16_t idx, uint8_t flags, const uint8_t key[16], +int bt_mesh_net_create(uint16_t net_idx, uint8_t flags, const uint8_t key[16], uint32_t iv_index) { struct bt_mesh_subnet *sub = NULL; int err = 0; - BT_DBG("idx %u flags 0x%02x iv_index %u", idx, flags, iv_index); - + BT_DBG("NetCreate"); + BT_DBG("NetIdx 0x%04x Flags 0x%02x IVIndex %lu Hours %u", + net_idx, flags, iv_index, BLE_MESH_IVU_HOURS); BT_DBG("NetKey %s", bt_hex(key, 16)); (void)memset(msg_cache, 0, sizeof(msg_cache)); @@ -509,7 +548,7 @@ int bt_mesh_net_create(uint16_t idx, uint8_t flags, const uint8_t key[16], } } - sub->net_idx = idx; + sub->net_idx = net_idx; if (IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_SERVER)) { sub->node_id = BLE_MESH_NODE_IDENTITY_STOPPED; @@ -517,7 +556,7 @@ int bt_mesh_net_create(uint16_t idx, uint8_t flags, const uint8_t key[16], sub->node_id = BLE_MESH_NODE_IDENTITY_NOT_SUPPORTED; #if CONFIG_BLE_MESH_PRB_SRV sub->private_node_id = BLE_MESH_PRIVATE_NODE_IDENTITY_NOT_SUPPORTED; -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ } bt_mesh.iv_index = iv_index; @@ -535,27 +574,29 @@ int bt_mesh_net_create(uint16_t idx, uint8_t flags, const uint8_t key[16], #if CONFIG_BLE_MESH_DF_SRV return bt_mesh_directed_forwarding_sub_init(sub); -#endif - +#else /* CONFIG_BLE_MESH_DF_SRV */ return 0; +#endif /* CONFIG_BLE_MESH_DF_SRV */ } void bt_mesh_net_revoke_keys(struct bt_mesh_subnet *sub) { int i; - BT_DBG("idx 0x%04x", sub->net_idx); + BT_DBG("RevokeKeys, NetIdx 0x%04x", sub->net_idx); memcpy(&sub->keys[0], &sub->keys[1], sizeof(sub->keys[0])); if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { - BT_DBG("Store updated NetKey persistently"); bt_mesh_store_subnet(sub); } for (i = 0; i < ARRAY_SIZE(bt_mesh.app_keys); i++) { struct bt_mesh_app_key *key = &bt_mesh.app_keys[i]; + BT_DBG("Revoke, NetIdx 0x%04x AppIdx 0x%04x KeyUpdated %u", + key->net_idx, key->app_idx, key->updated); + if (key->net_idx != sub->net_idx || !key->updated) { continue; } @@ -564,7 +605,6 @@ void bt_mesh_net_revoke_keys(struct bt_mesh_subnet *sub) key->updated = false; if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { - BT_DBG("Store updated AppKey persistently"); bt_mesh_store_app_key(key); } } @@ -572,6 +612,9 @@ void bt_mesh_net_revoke_keys(struct bt_mesh_subnet *sub) bool bt_mesh_kr_update(struct bt_mesh_subnet *sub, uint8_t new_kr, bool new_key) { + BT_DBG("KrUpdate, NewKr %u NewKey %u KrFlag %u KrPhase %u", + new_kr, new_key, sub->kr_flag, sub->kr_phase); + if (new_kr != sub->kr_flag && sub->kr_phase == BLE_MESH_KR_NORMAL) { BT_WARN("KR change in normal operation. Are we blacklisted?"); return false; @@ -582,10 +625,10 @@ bool bt_mesh_kr_update(struct bt_mesh_subnet *sub, uint8_t new_kr, bool new_key) if (sub->kr_flag) { if (sub->kr_phase == BLE_MESH_KR_PHASE_1) { BT_INFO("Phase 1 -> Phase 2"); + sub->kr_phase = BLE_MESH_KR_PHASE_2; if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { - BT_DBG("Storing kr phase persistently"); bt_mesh_store_subnet(sub); } @@ -606,14 +649,14 @@ bool bt_mesh_kr_update(struct bt_mesh_subnet *sub, uint8_t new_kr, bool new_key) * Intentional fall-through. */ case BLE_MESH_KR_PHASE_2: - BT_INFO("KR Phase 0x%02x -> Normal", sub->kr_phase); + BT_INFO("KrPhase 0x%02x -> Normal", sub->kr_phase); #if CONFIG_BLE_MESH_PRB_SRV /* In this case, consider that kr_flag has changed, so * need to modify the content of the random field. */ bt_mesh_private_beacon_update_random(sub); -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ sub->kr_phase = BLE_MESH_KR_NORMAL; bt_mesh_net_revoke_keys(sub); @@ -633,15 +676,21 @@ bool bt_mesh_kr_update(struct bt_mesh_subnet *sub, uint8_t new_kr, bool new_key) #if CONFIG_BLE_MESH_IV_UPDATE_TEST void bt_mesh_iv_update_test(bool enable) { + BT_DBG("IVUpdateTest, Enable %u", enable); + bt_mesh_atomic_set_bit_to(bt_mesh.flags, BLE_MESH_IVU_TEST, enable); + /* Reset the duration variable - needed for some PTS tests */ bt_mesh.ivu_duration = 0U; } bool bt_mesh_iv_update(void) { + BT_DBG("IVUpdate, IVIndex %lu InProgress %u", bt_mesh.iv_index, + bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_IVU_IN_PROGRESS)); + if (!bt_mesh_is_provisioned()) { - BT_ERR("Not yet provisioned"); + BT_ERR("NotProvisioned"); return false; } @@ -660,6 +709,8 @@ bool bt_mesh_iv_update(void) /* Used for sending immediate beacons to Friend queues and GATT clients */ void bt_mesh_net_sec_update(struct bt_mesh_subnet *sub) { + BT_DBG("NetSecUpdate, NetIdx 0x%04x", sub ? sub->net_idx : BLE_MESH_KEY_ANY); + if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND)) { bt_mesh_friend_sec_update(sub ? sub->net_idx : BLE_MESH_KEY_ANY); } @@ -667,8 +718,8 @@ void bt_mesh_net_sec_update(struct bt_mesh_subnet *sub) if (IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_SERVER) && (bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED #if CONFIG_BLE_MESH_PRB_SRV - || bt_mesh_private_gatt_proxy_state_get() == BLE_MESH_PRIVATE_GATT_PROXY_ENABLED -#endif + || bt_mesh_private_gatt_proxy_state_get() == BLE_MESH_PRIVATE_GATT_PROXY_ENABLED +#endif /* CONFIG_BLE_MESH_PRB_SRV */ )) { bt_mesh_proxy_server_beacon_send(sub); } @@ -678,6 +729,11 @@ bool bt_mesh_net_iv_update(uint32_t iv_index, bool iv_update) { int i; + BT_DBG("NetIVUpdate"); + BT_DBG("IVIndex %lu/%lu IVU %u InProgress %u", + iv_index, bt_mesh.iv_index, iv_update, + bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_IVU_IN_PROGRESS)); + /* If a node in Normal Operation receives a Secure Network beacon or * a Mesh Private beacon with an IV index less than the last known * IV Index or greater than the last known IV Index + 42, the Secure @@ -685,7 +741,7 @@ bool bt_mesh_net_iv_update(uint32_t iv_index, bool iv_update) */ if (iv_index < bt_mesh.iv_index || iv_index > bt_mesh.iv_index + 42) { - BT_ERR("IV Index out of sync: 0x%08x != 0x%08x", + BT_ERR("IVIndex out of sync: 0x%08x != 0x%08x", iv_index, bt_mesh.iv_index); return false; } @@ -721,7 +777,7 @@ bool bt_mesh_net_iv_update(uint32_t iv_index, bool iv_update) if ((iv_index > bt_mesh.iv_index + 1) #if CONFIG_BLE_MESH_IVU_RECOVERY_IVI || (iv_index == bt_mesh.iv_index + 1 && !iv_update) -#endif +#endif /* CONFIG_BLE_MESH_IVU_RECOVERY_IVI */ ) { BT_WARN("Performing IV Index Recovery"); (void)memset(bt_mesh.rpl, 0, sizeof(bt_mesh.rpl)); @@ -742,7 +798,7 @@ bool bt_mesh_net_iv_update(uint32_t iv_index, bool iv_update) BT_WARN("Ignoring new index in normal mode"); return false; } -#endif +#endif /* !CONFIG_BLE_MESH_IVU_RECOVERY_IVI */ if (!iv_update) { /* Nothing to do */ @@ -802,9 +858,11 @@ bool bt_mesh_net_iv_update(uint32_t iv_index, bool iv_update) bool bt_mesh_primary_subnet_exist(void) { if (bt_mesh_subnet_get(BLE_MESH_KEY_PRIMARY)) { + BT_DBG("PrimarySubnetExist"); return true; } + BT_DBG("PrimarySubnetNotExist"); return false; } @@ -812,6 +870,8 @@ uint32_t bt_mesh_next_seq(void) { uint32_t seq = bt_mesh.seq++; + BT_DBG("NextSeq %lu", seq); + if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { bt_mesh_store_seq(); } @@ -836,8 +896,9 @@ int bt_mesh_net_resend(struct bt_mesh_subnet *sub, struct net_buf *buf, uint16_t dst = 0U; int err = 0; - BT_DBG("net_idx 0x%04x new_key %u len %u", sub->net_idx, new_key, - buf->len); + BT_DBG("NetResend"); + BT_DBG("NetIdx 0x%04x NewKey %u Len %u Tag 0x%02x", + sub->net_idx, new_key, buf->len, tx_tag); /* Previously when resending the segments, only managed flooding * security credentials will be used. @@ -884,13 +945,11 @@ int bt_mesh_net_resend(struct bt_mesh_subnet *sub, struct net_buf *buf, err = bt_mesh_net_obfuscate(buf->data, BLE_MESH_NET_IVI_TX, priv); if (err) { - BT_ERR("De-obfuscate failed (err %d)", err); return err; } err = bt_mesh_net_decrypt(enc, &buf->b, BLE_MESH_NET_IVI_TX, false, false); if (err) { - BT_ERR("Decrypt failed (err %d)", err); return err; } @@ -903,13 +962,11 @@ int bt_mesh_net_resend(struct bt_mesh_subnet *sub, struct net_buf *buf, err = bt_mesh_net_encrypt(enc, &buf->b, BLE_MESH_NET_IVI_TX, false, false); if (err) { - BT_ERR("Encrypt failed (err %d)", err); return err; } err = bt_mesh_net_obfuscate(buf->data, BLE_MESH_NET_IVI_TX, priv); if (err) { - BT_ERR("Obfuscate failed (err %d)", err); return err; } @@ -927,6 +984,7 @@ int bt_mesh_net_resend(struct bt_mesh_subnet *sub, struct net_buf *buf, } bt_mesh_adv_send(buf, BLE_MESH_ADV(buf)->xmit, cb, cb_data); + return 0; } @@ -934,8 +992,10 @@ static void bt_mesh_net_local(void) { struct net_buf *buf = NULL; + BT_DBG("NetLocal"); + while ((buf = net_buf_slist_get(&bt_mesh.local_queue))) { - BT_DBG("len %u: %s", buf->len, bt_hex(buf->data, buf->len)); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); bt_mesh_net_recv(&buf->b, 0, BLE_MESH_NET_IF_LOCAL); net_buf_unref(buf); } @@ -949,6 +1009,10 @@ int bt_mesh_net_encode(struct bt_mesh_net_tx *tx, struct net_buf_simple *buf, uint8_t nid = 0U; int err = 0; + BT_DBG("NetEncode"); + BT_DBG("Src 0x%04x Dst 0x%04x Cred 0x%02x CTL %u Proxy %u", + tx->src, tx->ctx->addr, tx->ctx->send_cred, ctl, proxy); + if (ctl && net_buf_simple_tailroom(buf) < BLE_MESH_MIC_LONG) { BT_ERR("Insufficient MIC space for CTL PDU"); return -EINVAL; @@ -959,9 +1023,6 @@ int bt_mesh_net_encode(struct bt_mesh_net_tx *tx, struct net_buf_simple *buf, return -EINVAL; } - BT_DBG("src 0x%04x dst 0x%04x ctl %u seq 0x%06x", - tx->src, tx->ctx->addr, ctl, bt_mesh.seq); - net_buf_simple_push_be16(buf, tx->ctx->addr); net_buf_simple_push_be16(buf, tx->src); @@ -973,8 +1034,6 @@ int bt_mesh_net_encode(struct bt_mesh_net_tx *tx, struct net_buf_simple *buf, net_buf_simple_push_u8(buf, tx->ctx->send_ttl); } - BT_INFO("Use security credentials 0x%02x, proxy %d", tx->ctx->send_cred, proxy); - if (IS_ENABLED(CONFIG_BLE_MESH_LOW_POWER) && tx->ctx->send_cred == BLE_MESH_FRIENDSHIP_CRED) { err = friend_cred_get(tx->sub, BLE_MESH_ADDR_UNASSIGNED, @@ -1035,16 +1094,13 @@ static void bt_mesh_net_adv_xmit_update(struct bt_mesh_net_tx *tx) */ if (bt_mesh_tag_friendship(tx->ctx->send_tag)) { tx->xmit = BLE_MESH_TRANSMIT(0, BLE_MESH_TRANSMIT_INT(bt_mesh_net_transmit_get())); - return; - } - - if (bt_mesh_tag_relay(tx->ctx->send_tag)) { + } else if (bt_mesh_tag_relay(tx->ctx->send_tag)) { tx->xmit = bt_mesh_relay_retransmit_get(); } else { tx->xmit = bt_mesh_net_transmit_get(); } - return; + BT_INFO("NetAdvXmitUpdate, Tag 0x%02x Xmit 0x%02x", tx->ctx->send_tag, tx->xmit); } #endif /* !CONFIG_BLE_MESH_V11_SUPPORT */ @@ -1054,11 +1110,11 @@ int bt_mesh_net_send(struct bt_mesh_net_tx *tx, struct net_buf *buf, uint8_t bearer = BLE_MESH_ALL_BEARERS; int err = 0; - BT_DBG("src 0x%04x dst 0x%04x len %u headroom %u tailroom %u", - tx->src, tx->ctx->addr, buf->len, net_buf_headroom(buf), - net_buf_tailroom(buf)); - BT_DBG("Payload len %u: %s", buf->len, bt_hex(buf->data, buf->len)); - BT_DBG("Seq 0x%06x", bt_mesh.seq); + BT_DBG("NetSend"); + BT_DBG("Src 0x%04x Dst 0x%04x TTL %u Cred %u Tag 0x%02x Seq 0x%06x Room %u/%u", + tx->src, tx->ctx->addr, tx->ctx->send_ttl, tx->ctx->send_cred, + tx->ctx->send_tag, bt_mesh.seq, net_buf_headroom(buf), net_buf_tailroom(buf)); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); if (tx->ctx->send_ttl == BLE_MESH_TTL_DEFAULT) { tx->ctx->send_ttl = bt_mesh_default_ttl_get(); @@ -1092,6 +1148,8 @@ int bt_mesh_net_send(struct bt_mesh_net_tx *tx, struct net_buf *buf, #if CONFIG_BLE_MESH_DF_SRV bt_mesh_update_net_send_cred(tx, &bearer); + + BT_DBG("TxBearer 0x%02x", bearer); #endif /* CONFIG_BLE_MESH_DF_SRV */ err = bt_mesh_net_encode(tx, &buf->b, false); @@ -1142,6 +1200,8 @@ int bt_mesh_net_send(struct bt_mesh_net_tx *tx, struct net_buf *buf, bt_mesh_tag_relay(tx->ctx->send_tag)) && tx->ctx->send_cred != BLE_MESH_FRIENDSHIP_CRED) { if (bt_mesh_proxy_client_relay(&buf->b, tx->ctx->addr)) { + BT_DBG("ProxyClientRelay"); + /* If Proxy Client succeeds to send messages with GATT bearer, * we can directly finish here. And if not, which means no * connection has been created with Proxy Client, here we will @@ -1203,17 +1263,14 @@ int bt_mesh_net_send(struct bt_mesh_net_tx *tx, struct net_buf *buf, */ bt_mesh_net_adv_xmit_update(tx); - BT_INFO("Network PDU, count %d, interval %d", - BLE_MESH_TRANSMIT_COUNT(tx->xmit), BLE_MESH_TRANSMIT_INT(tx->xmit)); bt_mesh_adv_send(buf, tx->xmit, cb, cb_data); err = 0; goto done; } - BT_WARN("Not sent, src 0x%04x, dst 0x%04x, ttl %d, cred 0x%02x, tag 0x%02x", - tx->src, tx->ctx->addr, tx->ctx->send_ttl, tx->ctx->send_cred, - tx->ctx->send_tag); + BT_WARN("NetNotSend"); + err = -EIO; done: @@ -1227,7 +1284,10 @@ static bool auth_match(struct bt_mesh_subnet_keys *keys, { uint8_t net_auth[8] = {0}; + BT_DBG("AuthMatch"); + if (memcmp(net_id, keys->net_id, 8)) { + BT_DBG("NetID %s != %s", bt_hex(net_id, 8), bt_hex(keys->net_id, 8)); return false; } @@ -1235,8 +1295,7 @@ static bool auth_match(struct bt_mesh_subnet_keys *keys, net_auth); if (memcmp(auth, net_auth, 8)) { - BT_WARN("Authentication Value %s != %s", - bt_hex(auth, 8), bt_hex(net_auth, 8)); + BT_WARN("NetAuth %s != %s", bt_hex(auth, 8), bt_hex(net_auth, 8)); return false; } @@ -1252,6 +1311,8 @@ struct bt_mesh_subnet *bt_mesh_subnet_find_with_snb(const uint8_t net_id[8], uin subnet_size = bt_mesh_rx_netkey_size(); + BT_DBG("SubnetFindWithSnb, Size %lu", subnet_size); + for (i = 0; i < subnet_size; i++) { struct bt_mesh_subnet *sub = bt_mesh_rx_netkey_get(i); @@ -1282,8 +1343,10 @@ int net_decrypt(struct bt_mesh_subnet *sub, const uint8_t *enc, size_t data_len, struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) { - BT_DBG("NID 0x%02x net_idx 0x%04x", BLE_MESH_NET_HDR_NID(data), sub->net_idx); - BT_DBG("IVI %u net->iv_index 0x%08x", BLE_MESH_NET_HDR_IVI(data), bt_mesh.iv_index); + BT_DBG("NetDecrypt"); + BT_DBG("IVI %u NID 0x%02x NetIdx 0x%04x IVIndex %lu NetIf %u", + BLE_MESH_NET_HDR_IVI(data), BLE_MESH_NET_HDR_NID(data), + sub->net_idx, bt_mesh.iv_index, rx->net_if); rx->old_iv = (BLE_MESH_NET_HDR_IVI(data) != (bt_mesh.iv_index & 0x01)); @@ -1305,12 +1368,11 @@ int net_decrypt(struct bt_mesh_subnet *sub, const uint8_t *enc, return -EALREADY; } - BT_DBG("src 0x%04x", rx->ctx.addr); + BT_DBG("Src 0x%04x", rx->ctx.addr); if (IS_ENABLED(CONFIG_BLE_MESH_PROXY) && rx->net_if == BLE_MESH_NET_IF_PROXY_CFG) { - return bt_mesh_net_decrypt(enc, buf, BLE_MESH_NET_IVI_RX(rx), - true, false); + return bt_mesh_net_decrypt(enc, buf, BLE_MESH_NET_IVI_RX(rx), true, false); } return bt_mesh_net_decrypt(enc, buf, BLE_MESH_NET_IVI_RX(rx), false, false); @@ -1323,7 +1385,9 @@ static int friend_decrypt(struct bt_mesh_subnet *sub, const uint8_t *data, { int i; - BT_DBG("NID 0x%02x net_idx 0x%04x", BLE_MESH_NET_HDR_NID(data), sub->net_idx); + BT_DBG("FrndDecrypt"); + BT_DBG("NID 0x%02x NetIdx 0x%04x KrPhase %u", + BLE_MESH_NET_HDR_NID(data), sub->net_idx, sub->kr_phase); for (i = 0; i < ARRAY_SIZE(friend_cred); i++) { struct friend_cred *cred = &friend_cred[i]; @@ -1335,6 +1399,7 @@ static int friend_decrypt(struct bt_mesh_subnet *sub, const uint8_t *data, if (BLE_MESH_NET_HDR_NID(data) == cred->cred[0].nid && !net_decrypt(sub, cred->cred[0].enc, cred->cred[0].privacy, data, data_len, rx, buf)) { + BT_DBG("UseOldKey"); return 0; } @@ -1345,6 +1410,7 @@ static int friend_decrypt(struct bt_mesh_subnet *sub, const uint8_t *data, if (BLE_MESH_NET_HDR_NID(data) == cred->cred[1].nid && !net_decrypt(sub, cred->cred[1].enc, cred->cred[1].privacy, data, data_len, rx, buf)) { + BT_DBG("UseNewKey"); rx->new_key = 1U; return 0; } @@ -1358,11 +1424,14 @@ static int flooding_decrypt(struct bt_mesh_subnet *sub, const uint8_t *data, size_t data_len, struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) { - BT_DBG("NID 0x%02x net_idx 0x%04x", BLE_MESH_NET_HDR_NID(data), sub->net_idx); + BT_DBG("FloodingDecrypt"); + BT_DBG("NID 0x%02x NetIdx 0x%04x KrPhase %u", + BLE_MESH_NET_HDR_NID(data), sub->net_idx, sub->kr_phase); if (BLE_MESH_NET_HDR_NID(data) == sub->keys[0].nid && !net_decrypt(sub, sub->keys[0].enc, sub->keys[0].privacy, data, data_len, rx, buf)) { + BT_DBG("UseOldKey"); return 0; } @@ -1373,6 +1442,7 @@ static int flooding_decrypt(struct bt_mesh_subnet *sub, const uint8_t *data, if (BLE_MESH_NET_HDR_NID(data) == sub->keys[1].nid && !net_decrypt(sub, sub->keys[1].enc, sub->keys[1].privacy, data, data_len, rx, buf)) { + BT_DBG("UseNewKey"); rx->new_key = 1U; return 0; } @@ -1390,10 +1460,12 @@ static bool net_find_and_decrypt(const uint8_t *data, size_t data_len, array_size = bt_mesh_rx_netkey_size(); + BT_DBG("NetFindAndDecrypt, Size %u", array_size); + for (i = 0; i < array_size; i++) { sub = bt_mesh_rx_netkey_get(i); if (!sub) { - BT_DBG("Subnet not found"); + BT_DBG("SubNotFound"); continue; } @@ -1403,7 +1475,7 @@ static bool net_find_and_decrypt(const uint8_t *data, size_t data_len, #if CONFIG_BLE_MESH_BRC_SRV sub->sbr_net_idx = BLE_MESH_KEY_UNUSED; -#endif +#endif /* CONFIG_BLE_MESH_BRC_SRV */ #if (CONFIG_BLE_MESH_LOW_POWER || CONFIG_BLE_MESH_FRIEND) if (!friend_decrypt(sub, data, data_len, rx, buf)) { @@ -1412,7 +1484,7 @@ static bool net_find_and_decrypt(const uint8_t *data, size_t data_len, rx->sub = sub; return true; } -#endif +#endif /* (CONFIG_BLE_MESH_LOW_POWER || CONFIG_BLE_MESH_FRIEND) */ #if CONFIG_BLE_MESH_DF_SRV if (!bt_mesh_directed_decrypt(sub, data, data_len, rx, buf)) { @@ -1441,6 +1513,8 @@ static bool net_find_and_decrypt(const uint8_t *data, size_t data_len, */ static bool relay_to_adv(enum bt_mesh_net_if net_if) { + BT_DBG("RelayToAdv, NetIf %u", net_if); + switch (net_if) { case BLE_MESH_NET_IF_LOCAL: return true; @@ -1450,7 +1524,7 @@ static bool relay_to_adv(enum bt_mesh_net_if net_if) return (bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED #if CONFIG_BLE_MESH_PRB_SRV || bt_mesh_private_gatt_proxy_state_get() == BLE_MESH_PRIVATE_GATT_PROXY_ENABLED -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ ); default: return false; @@ -1461,6 +1535,8 @@ static bool relay_to_adv(enum bt_mesh_net_if net_if) static uint8_t net_retransmission_adv(struct bt_mesh_net_rx *rx, uint8_t *cred, uint8_t *tag) { + BT_DBG("NetRetransmissionAdv"); + if (rx->ctx.recv_cred == BLE_MESH_FLOODING_CRED) { uint8_t bearer = BLE_MESH_NONE_BEARER; @@ -1484,6 +1560,8 @@ static uint8_t net_retransmission_adv(struct bt_mesh_net_rx *rx, *cred = BLE_MESH_FLOODING_CRED; } + BT_DBG("FloodingBearer 0x%02x", bearer); + return bearer; } @@ -1493,6 +1571,9 @@ static uint8_t net_retransmission_adv(struct bt_mesh_net_rx *rx, /* Condition: Directed friend is disabled. */ *cred = BLE_MESH_FLOODING_CRED; + + BT_DBG("FrndBearerAll"); + return BLE_MESH_ALL_BEARERS; } @@ -1502,6 +1583,8 @@ static uint8_t net_retransmission_adv(struct bt_mesh_net_rx *rx, static uint8_t net_retransmission_gatt(struct bt_mesh_net_rx *rx, uint8_t *cred, uint8_t *tag) { + BT_DBG("NetRetransmissionGatt"); + if (rx->ctx.recv_cred == BLE_MESH_FLOODING_CRED) { /* Inbound bearer: GATT; * Inbound Security Material: managed flooding; @@ -1511,6 +1594,9 @@ static uint8_t net_retransmission_gatt(struct bt_mesh_net_rx *rx, bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED) { /* Condition: Directed proxy is disabled. */ *cred = BLE_MESH_FLOODING_CRED; + + BT_DBG("FloodingBearerAll"); + return BLE_MESH_ALL_BEARERS; } @@ -1539,14 +1625,19 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, struct bt_mesh_net_rx *rx) { const uint8_t *enc = NULL, *priv = NULL; + bool netkey_changed = false; struct net_buf *buf = NULL; uint8_t bearer = 0; uint8_t xmit = 0U; uint8_t cred = 0; uint8_t nid = 0U; - bool netkey_changed = false; uint8_t tag = 0; + BT_DBG("NetRelay"); + BT_DBG("TTL %u CTL %u Dst 0x%04x RecvCred %u NetIf %u", + rx->ctx.recv_ttl, rx->ctl, rx->ctx.recv_dst, + rx->ctx.recv_cred, rx->net_if); + if (rx->net_if == BLE_MESH_NET_IF_LOCAL) { /* Locally originated PDUs with TTL=1 will only be delivered * to local elements as per Mesh Profile 1.0 section 3.4.5.2: @@ -1602,12 +1693,12 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, BT_ERR("Bridge RPL attack"); goto done; } -#endif +#endif /* CONFIG_BLE_MESH_BRC_SRV */ if (cred != BLE_MESH_FLOODING_CRED #if CONFIG_BLE_MESH_DF_SRV - && cred != BLE_MESH_DIRECTED_CRED -#endif + && cred != BLE_MESH_DIRECTED_CRED +#endif /* CONFIG_BLE_MESH_DF_SRV */ ) { BT_WARN("No outbound security cred found, inbound cred %d", rx->ctx.recv_cred); return; @@ -1623,8 +1714,6 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, return; } - BT_DBG("TTL %u CTL %u dst 0x%04x", rx->ctx.recv_ttl, rx->ctl, rx->ctx.recv_dst); - /* The Relay Retransmit state is only applied to adv-adv relaying. * Anything else (like GATT to adv, or locally originated packets) * use the Network Transmit state. @@ -1656,7 +1745,7 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, /* Check if the number of relay packets in queue is too large, if so * use minimum relay retransmit value for later relay packets. */ - if (bt_mesh_get_stored_relay_count() >= BLE_MESH_MAX_STORED_RELAY_COUNT) { + if (bt_mesh_get_stored_relay_count() >= MAX_STORED_RELAY_COUNT) { xmit = BLE_MESH_TRANSMIT(0, 20); } buf = bt_mesh_relay_adv_create(BLE_MESH_ADV_DATA, K_NO_WAIT); @@ -1692,10 +1781,12 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, /* Check if subnet bridge is supported & decide which NetKey is used */ if (bt_mesh_subnet_bridge_state_get() == BLE_MESH_SUBNET_BRIDGE_ENABLED) { netkey_changed = bt_mesh_bridge_change_net_key(rx, &enc, &priv, &nid, cred); + + BT_DBG("NetKeyChanged %u", netkey_changed); } -#endif +#endif /* CONFIG_BLE_MESH_BRC_SRV */ - BT_DBG("Relaying packet. TTL is now %u", BLE_MESH_NET_HDR_TTL(buf->data)); + BT_DBG("Relaying, NewTTL %u", BLE_MESH_NET_HDR_TTL(buf->data)); /* 1. Update NID if RX or RX was with friend credentials(included by case 3). * 2. Update NID if the net_key has changed. @@ -1711,12 +1802,10 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, * layer nonce includes the IVI. */ if (bt_mesh_net_encrypt(enc, &buf->b, BLE_MESH_NET_IVI_RX(rx), false, false)) { - BT_ERR("Re-encrypting failed"); goto done; } if (bt_mesh_net_obfuscate(buf->data, BLE_MESH_NET_IVI_RX(rx), priv)) { - BT_ERR("Re-obfuscating failed"); goto done; } @@ -1733,7 +1822,7 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, cred != BLE_MESH_FRIENDSHIP_CRED) || #if CONFIG_BLE_MESH_PRB_SRV bt_mesh_private_gatt_proxy_state_get() == BLE_MESH_PRIVATE_GATT_PROXY_ENABLED || -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ rx->net_if == BLE_MESH_NET_IF_LOCAL || rx->ctx.recv_cred == BLE_MESH_FRIENDSHIP_CRED)) { if (bt_mesh_proxy_server_relay(&buf->b, rx->ctx.recv_dst) && @@ -1749,9 +1838,9 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, rx->ctx.recv_cred == BLE_MESH_FRIENDSHIP_CRED) { #if !CONFIG_BLE_MESH_RELAY_ADV_BUF bt_mesh_adv_send(buf, xmit, NULL, NULL); -#else +#else /* !CONFIG_BLE_MESH_RELAY_ADV_BUF */ bt_mesh_relay_adv_send(buf, xmit, rx->ctx.addr, rx->ctx.recv_dst, NULL, NULL); -#endif +#endif /* !CONFIG_BLE_MESH_RELAY_ADV_BUF */ } done: @@ -1761,6 +1850,8 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, void bt_mesh_net_header_parse(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx) { + BT_DBG("NetHeaderParse"); + rx->old_iv = (BLE_MESH_NET_HDR_IVI(buf->data) != (bt_mesh.iv_index & 0x01)); rx->ctl = BLE_MESH_NET_HDR_CTL(buf->data); rx->ctx.recv_ttl = BLE_MESH_NET_HDR_TTL(buf->data); @@ -1772,9 +1863,10 @@ void bt_mesh_net_header_parse(struct net_buf_simple *buf, int bt_mesh_net_decode(struct net_buf_simple *data, enum bt_mesh_net_if net_if, struct bt_mesh_net_rx *rx, struct net_buf_simple *buf) { + BT_DBG("NetDecode, NetIf %u", net_if); + if (data->len < BLE_MESH_NET_MIN_PDU_LEN) { BT_WARN("Dropping too short mesh packet (len %u)", data->len); - BT_WARN("%s", bt_hex(data->data, data->len)); return -EINVAL; } @@ -1782,7 +1874,7 @@ int bt_mesh_net_decode(struct net_buf_simple *data, enum bt_mesh_net_if net_if, return -EINVAL; } - BT_DBG("%u bytes: %s", data->len, bt_hex(data->data, data->len)); + BT_DBG("Len %u: %s", data->len, bt_hex(data->data, data->len)); rx->net_if = net_if; @@ -1818,8 +1910,6 @@ int bt_mesh_net_decode(struct net_buf_simple *data, enum bt_mesh_net_if net_if, rx->seq = BLE_MESH_NET_HDR_SEQ(buf->data); rx->ctx.recv_dst = BLE_MESH_NET_HDR_DST(buf->data); - BT_DBG("Decryption successful. Payload len %u", buf->len); - if (net_if != BLE_MESH_NET_IF_PROXY_CFG && rx->ctx.recv_dst == BLE_MESH_ADDR_UNASSIGNED) { BT_ERR("Destination address is unassigned; dropping packet"); @@ -1832,16 +1922,15 @@ int bt_mesh_net_decode(struct net_buf_simple *data, enum bt_mesh_net_if net_if, BT_ERR("Destination address is RFU; dropping packet 0x%02x", rx->ctx.recv_dst); return -EBADMSG; } -#endif +#endif /* !CONFIG_BLE_MESH_BQB_TEST */ if (net_if != BLE_MESH_NET_IF_LOCAL && bt_mesh_elem_find(rx->ctx.addr)) { BT_DBG("Dropping locally originated packet"); return -EBADMSG; } - BT_DBG("src 0x%04x dst 0x%04x ttl %u", rx->ctx.addr, rx->ctx.recv_dst, - rx->ctx.recv_ttl); - BT_DBG("PDU: %s", bt_hex(buf->data, buf->len)); + BT_DBG("Src 0x%04x Dst 0x%04x TTL %u", rx->ctx.addr, rx->ctx.recv_dst, rx->ctx.recv_ttl); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); msg_cache_add(rx); @@ -1851,25 +1940,31 @@ int bt_mesh_net_decode(struct net_buf_simple *data, enum bt_mesh_net_if net_if, static bool ready_to_recv(void) { if (IS_ENABLED(CONFIG_BLE_MESH_NODE) && bt_mesh_is_provisioned()) { + BT_DBG("NodeReadyToRecv"); return true; } if (IS_ENABLED(CONFIG_BLE_MESH_PROVISIONER) && bt_mesh_is_provisioner_en()) { if (bt_mesh_provisioner_get_node_count()) { + BT_DBG("PvnrReadyToRecv"); return true; } } + BT_DBG("NotReadyToRecv"); return false; } static bool ignore_net_msg(uint16_t src, uint16_t dst) { + BT_DBG("IgnoreNetMsg, Src 0x%04x Dst 0x%04x", src, dst); + if (IS_ENABLED(CONFIG_BLE_MESH_FAST_PROV)) { /* When fast provisioning is enabled, the node addr * message will be sent to the Primary Provisioner, * which shall not be ignored here. */ + BT_DBG("FastProvNotIgnoreNetMsg"); return false; } @@ -1884,11 +1979,12 @@ static bool ignore_net_msg(uint16_t src, uint16_t dst) */ if (!bt_mesh_provisioner_get_node_with_addr(src) && !bt_mesh_elem_find(src)) { - BT_INFO("Not found node address 0x%04x", src); + BT_INFO("PvnrIgnoreNetMsg"); return true; } } + BT_DBG("NotIgnoreNetMsg"); return false; } @@ -1916,6 +2012,9 @@ void bt_mesh_net_recv(struct net_buf_simple *data, int8_t rssi, /* Save the state so the buffer can later be relayed */ net_buf_simple_save(&buf, &state); + BT_DBG("NetRecv, Src 0x%04x Dst 0x%04x Rssi %d NetIf %u", + rx.ctx.addr, rx.ctx.recv_dst, rx.ctx.recv_rssi, net_if); + BT_BQB(BLE_MESH_BQB_TEST_LOG_LEVEL_PRIMARY_ID_NODE | \ BLE_MESH_BQB_TEST_LOG_LEVEL_SUB_ID_NET, "\nNetRecv: ctl: %d, src: %d, dst: %d, ttl: %d, data: 0x%s", @@ -1933,10 +2032,12 @@ void bt_mesh_net_recv(struct net_buf_simple *data, int8_t rssi, if (IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_SERVER) && #if CONFIG_BLE_MESH_PRB_SRV bt_mesh_private_gatt_proxy_state_get() != BLE_MESH_PRIVATE_GATT_PROXY_ENABLED && -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ net_if == BLE_MESH_NET_IF_PROXY) { bt_mesh_proxy_server_addr_add(data, rx.ctx.addr); + BT_DBG("ProxyServerAddrAdd"); + if (bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_DISABLED && !rx.local_match) { BT_INFO("Proxy is disabled; ignoring message"); @@ -1956,6 +2057,7 @@ void bt_mesh_net_recv(struct net_buf_simple *data, int8_t rssi, !bt_mesh_addr_in_uar(&rx.sub->proxy_client_uar, rx.ctx.addr) && !bt_mesh_proxy_server_find_client_by_addr(rx.ctx.addr)) { rx.ctx.recv_tag |= BLE_MESH_TAG_IMMUTABLE_CRED; + BT_DBG("ImmutableCredTag"); } #endif /* CONFIG_BLE_MESH_DF_SRV */ } @@ -1992,7 +2094,7 @@ static void ivu_refresh(struct k_work *work) { bt_mesh.ivu_duration += BLE_MESH_IVU_HOURS; - BT_INFO("%s for %u hour%s", + BT_INFO("IVURefresh, %s for %u hour%s", bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_IVU_IN_PROGRESS) ? "IVU in Progress" : "IVU Normal mode", bt_mesh.ivu_duration, bt_mesh.ivu_duration == 1U ? "" : "s"); @@ -2016,6 +2118,8 @@ static void ivu_refresh(struct k_work *work) void bt_mesh_net_start(void) { + BT_DBG("NetStart"); + if (bt_mesh_secure_beacon_get() == BLE_MESH_SECURE_BEACON_ENABLED) { bt_mesh_secure_beacon_enable(); } else { @@ -2028,7 +2132,7 @@ void bt_mesh_net_start(void) } else { bt_mesh_private_beacon_disable(); } -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ if (IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_SERVER) && bt_mesh_gatt_proxy_get() != BLE_MESH_GATT_PROXY_NOT_SUPPORTED) { @@ -2041,7 +2145,7 @@ void bt_mesh_net_start(void) bt_mesh_update_exceptional_list(BLE_MESH_EXCEP_LIST_SUB_CODE_ADD, BLE_MESH_EXCEP_LIST_TYPE_MESH_BEACON, NULL); -#endif +#endif /* CONFIG_BLE_MESH_USE_DUPLICATE_SCAN */ if (IS_ENABLED(CONFIG_BLE_MESH_LOW_POWER)) { /* TODO: Enable duplicate scan in Low Power Mode */ @@ -2060,6 +2164,7 @@ void bt_mesh_net_start(void) uint32_t iv_index = bt_mesh.iv_index; uint8_t flags = (uint8_t)bt_mesh.sub[0].kr_flag; const uint8_t *net_key = bt_mesh.sub[0].keys[flags].net; + if (bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_IVU_IN_PROGRESS)) { flags |= BLE_MESH_NET_FLAG_IVU; } @@ -2070,16 +2175,20 @@ void bt_mesh_net_start(void) void bt_mesh_net_init(void) { + BT_DBG("NetInit"); + k_delayed_work_init(&bt_mesh.ivu_timer, ivu_refresh); } void bt_mesh_net_reset(void) { + BT_DBG("NetReset"); + k_delayed_work_cancel(&bt_mesh.ivu_timer); #if FRIEND_CRED_COUNT > 0 memset(friend_cred, 0, sizeof(friend_cred)); -#endif +#endif /* FRIEND_CRED_COUNT > 0 */ memset(msg_cache, 0, sizeof(msg_cache)); msg_cache_next = 0U; @@ -2094,6 +2203,8 @@ void bt_mesh_net_reset(void) #if CONFIG_BLE_MESH_DEINIT void bt_mesh_net_deinit(void) { + BT_DBG("NetDeinit"); + bt_mesh_net_reset(); k_delayed_work_free(&bt_mesh.ivu_timer); diff --git a/components/bt/esp_ble_mesh/core/net.h b/components/bt/esp_ble_mesh/core/net.h index 7da8c4a07824..493954178fdd 100644 --- a/components/bt/esp_ble_mesh/core/net.h +++ b/components/bt/esp_ble_mesh/core/net.h @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -66,7 +66,7 @@ struct bt_mesh_subnet { #if CONFIG_BLE_MESH_BRC_SRV uint16_t sbr_net_idx; /* NetKeyIndex of bridged subnet */ -#endif +#endif /* CONFIG_BLE_MESH_BRC_SRV */ bool kr_flag; /* Key Refresh Flag */ uint8_t kr_phase; /* Key Refresh Phase */ @@ -163,17 +163,17 @@ struct bt_mesh_rpl { bool old_iv; #if CONFIG_BLE_MESH_SETTINGS bool store; -#endif +#endif /* CONFIG_BLE_MESH_SETTINGS */ uint32_t seq; }; #if CONFIG_BLE_MESH_FRIEND #define FRIEND_SEG_RX CONFIG_BLE_MESH_FRIEND_SEG_RX #define FRIEND_SUB_LIST_SIZE CONFIG_BLE_MESH_FRIEND_SUB_LIST_SIZE -#else +#else /* CONFIG_BLE_MESH_FRIEND */ #define FRIEND_SEG_RX 0 #define FRIEND_SUB_LIST_SIZE 0 -#endif +#endif /* CONFIG_BLE_MESH_FRIEND */ struct bt_mesh_friend { uint16_t lpn; @@ -220,10 +220,10 @@ struct bt_mesh_friend { }; #if CONFIG_BLE_MESH_LOW_POWER -#define LPN_GROUPS CONFIG_BLE_MESH_LPN_GROUPS -#else -#define LPN_GROUPS 0 -#endif +#define LPN_GROUPS CONFIG_BLE_MESH_LPN_GROUPS +#else /* CONFIG_BLE_MESH_LOW_POWER */ +#define LPN_GROUPS 0 +#endif /* CONFIG_BLE_MESH_LOW_POWER */ /* Low Power Node state */ struct bt_mesh_lpn { @@ -275,7 +275,7 @@ struct bt_mesh_lpn { #if CONFIG_BLE_MESH_DF_SRV uint8_t old_directed_forwarding; -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ /* Duration reported for last advertising packet */ uint16_t adv_duration; @@ -331,11 +331,11 @@ struct bt_mesh_net { #if CONFIG_BLE_MESH_FRIEND /* Friend state, unique for each LPN that we're Friends for */ struct bt_mesh_friend frnd[CONFIG_BLE_MESH_FRIEND_LPN_COUNT]; -#endif +#endif /* CONFIG_BLE_MESH_FRIEND */ #if CONFIG_BLE_MESH_LOW_POWER struct bt_mesh_lpn lpn; /* Low Power Node state */ -#endif +#endif /* CONFIG_BLE_MESH_LOW_POWER */ /* Number of hours in current IV Update state */ uint8_t ivu_duration; @@ -362,7 +362,7 @@ struct bt_mesh_net { struct bt_mesh_subnet *p_sub[CONFIG_BLE_MESH_PROVISIONER_SUBNET_COUNT]; /* Next net_idx can be assigned */ uint16_t p_net_idx_next; -#endif +#endif /* CONFIG_BLE_MESH_PROVISIONER */ }; /* Network interface */ @@ -393,7 +393,7 @@ struct bt_mesh_net_rx { friend_match:1, /* Matched an LPN we're friends for */ #if CONFIG_BLE_MESH_NOT_RELAY_REPLAY_MSG replay_msg:1, /* Replayed messages */ -#endif +#endif /* CONFIG_BLE_MESH_NOT_RELAY_REPLAY_MSG */ sbr_rpl:1; /* Bridge RPL attacker */ uint16_t msg_cache_idx; /* Index of entry in message cache */ }; @@ -431,7 +431,7 @@ void bt_mesh_msg_cache_clear(uint16_t unicast_addr, uint8_t elem_num); int bt_mesh_net_keys_create(struct bt_mesh_subnet_keys *keys, const uint8_t key[16]); -int bt_mesh_net_create(uint16_t idx, uint8_t flags, const uint8_t key[16], +int bt_mesh_net_create(uint16_t net_idx, uint8_t flags, const uint8_t key[16], uint32_t iv_index); uint8_t bt_mesh_net_flags(struct bt_mesh_subnet *sub); diff --git a/components/bt/esp_ble_mesh/core/nimble_host/adapter.c b/components/bt/esp_ble_mesh/core/nimble_host/adapter.c index 1a1632117189..42cbec6a5495 100644 --- a/components/bt/esp_ble_mesh/core/nimble_host/adapter.c +++ b/components/bt/esp_ble_mesh/core/nimble_host/adapter.c @@ -698,8 +698,7 @@ static int gap_event_cb(struct ble_gap_event *event, void *arg) return 0; case BLE_GAP_EVENT_ADV_COMPLETE: - MODLOG_DFLT(INFO, "advertise complete; reason=%d", - event->adv_complete.reason); + BT_DBG("advertise complete; reason=%d", event->adv_complete.reason); return 0; case BLE_GAP_EVENT_ENC_CHANGE: diff --git a/components/bt/esp_ble_mesh/core/prov_common.c b/components/bt/esp_ble_mesh/core/prov_common.c index 6f9e1dfa417c..bf5657852b87 100644 --- a/components/bt/esp_ble_mesh/core/prov_common.c +++ b/components/bt/esp_ble_mesh/core/prov_common.c @@ -48,6 +48,7 @@ void bt_mesh_prov_buf_init(struct net_buf_simple *buf, uint8_t type) bt_mesh_output_action_t bt_mesh_prov_output_action(uint8_t action) { + BT_DBG("ProvOutputAction:%d", action); switch (action) { case OUTPUT_OOB_BLINK: return BLE_MESH_BLINK; @@ -66,6 +67,7 @@ bt_mesh_output_action_t bt_mesh_prov_output_action(uint8_t action) bt_mesh_input_action_t bt_mesh_prov_input_action(uint8_t action) { + BT_DBG("ProvInputAction:%d", action); switch (action) { case INPUT_OOB_PUSH: return BLE_MESH_PUSH; @@ -151,20 +153,27 @@ static uint8_t bt_mesh_prov_buf_type_get(struct net_buf_simple *buf) uint8_t node_next_xact_id(struct bt_mesh_prov_link *link) { + uint8_t nxt_xact_id = 0; if (link->tx.id != 0 && link->tx.id != 0xFF) { - return ++link->tx.id; + nxt_xact_id = ++link->tx.id; + } else { + link->tx.id = 0x80; + nxt_xact_id = 0x80; } - link->tx.id = 0x80; - return link->tx.id; + BT_DBG("NodeNextXActId:%d", nxt_xact_id); + return nxt_xact_id; } uint8_t pvnr_next_xact_id(struct bt_mesh_prov_link *link) { + uint8_t nxt_xact_id = 0; if (link->tx.id > 0x7F) { link->tx.id = 0; } - return link->tx.id++; + nxt_xact_id = link->tx.id++; + BT_DBG("PvnrNextXActId:%d", nxt_xact_id); + return nxt_xact_id; } bool bt_mesh_gen_prov_start(struct bt_mesh_prov_link *link, @@ -186,7 +195,7 @@ bool bt_mesh_gen_prov_start(struct bt_mesh_prov_link *link, link->rx.id = rx->xact_id; link->rx.fcs = net_buf_simple_pull_u8(buf); - BT_DBG("len %u last_seg %u total_len %u fcs 0x%02x", buf->len, + BT_DBG("LinkId:%08x,len %u last_seg %u total_len %u fcs 0x%02x", link->link_id, buf->len, START_LAST_SEG(rx->gpc), link->rx.buf->len, link->rx.fcs); /* At least one-octet pdu type is needed */ @@ -227,9 +236,10 @@ bool bt_mesh_gen_prov_start(struct bt_mesh_prov_link *link, link->rx.last_seg = START_LAST_SEG(rx->gpc); memcpy(link->rx.buf->data, buf->data, buf->len); XACT_SEG_RECV(link, 0); - + BT_DBG("Seg: %04x, lastSeg: %04x, Data: %s", link->rx.seg, link->rx.last_seg, bt_hex(buf->data, buf->len)); /* Still have some segments to receive */ if (link->rx.seg) { + BT_DBG("Still have some segments to receive: %02x", link->rx.seg); return false; } @@ -242,7 +252,7 @@ bool bt_mesh_gen_prov_cont(struct bt_mesh_prov_link *link, { uint8_t seg = CONT_SEG_INDEX(rx->gpc); - BT_DBG("len %u, seg_index %u", buf->len, seg); + BT_DBG("LinkId:%08x,len %u,seg_index %u", link->link_id, buf->len, seg); if (link->rx.seg == 0 && link->rx.prev_id == rx->xact_id) { BT_INFO("Resending ack"); @@ -287,6 +297,7 @@ bool bt_mesh_gen_prov_cont(struct bt_mesh_prov_link *link, /* Still have some segments to receive */ if (link->rx.seg) { + BT_DBG("Still have some segments to receive: %02x", link->rx.seg); return false; } @@ -346,12 +357,14 @@ void bt_mesh_gen_prov_ack_send(struct bt_mesh_prov_link *link, uint8_t xact_id) net_buf_add_u8(buf, xact_id); net_buf_add_u8(buf, GPC_ACK); + BT_DBG("GenericProvAckSend,LinkId:%08x,XActId:%02x", link->link_id, xact_id); bt_mesh_adv_send(buf, PROV_XMIT, complete, link); net_buf_unref(buf); } static void free_segments(struct bt_mesh_prov_link *link) { + BT_DBG("FreeSegments:%08x", link->link_id); for (size_t i = 0; i < ARRAY_SIZE(link->tx.buf); i++) { struct net_buf *buf = link->tx.buf[i]; @@ -386,6 +399,7 @@ static void buf_sent(int err, void *user_data) int32_t timeout = RETRANSMIT_TIMEOUT; if (!link->tx.buf[0]) { + BT_DBG("LinkId:%08x,NoTxBuf", link->link_id); return; } @@ -412,6 +426,8 @@ static void prov_retransmit(struct k_work *work) struct bt_mesh_prov_link *link = work->user_data; int64_t timeout = TRANSACTION_TIMEOUT; + BT_DBG("LinkRetransmit:%08x,flag:%s", link->link_id, bt_hex(link->flags, sizeof(link->flags))); + if (!bt_mesh_atomic_test_bit(link->flags, LINK_ACTIVE) && !bt_mesh_atomic_test_bit(link->flags, LINK_CLOSING)) { BT_WARN("Link not active"); @@ -419,6 +435,9 @@ static void prov_retransmit(struct k_work *work) } #if CONFIG_BLE_MESH_FAST_PROV + BT_DBG("FastProv, TxPDUType %u LastTxPDU %u", + link->tx_pdu_type, link->last_tx_pdu); + if (link->tx_pdu_type >= link->last_tx_pdu) { timeout = K_SECONDS(30); } @@ -490,7 +509,7 @@ static void prov_retransmit(struct k_work *work) BT_DBG("%u bytes: %s", buf->len, bt_hex(buf->data, buf->len)); - if (i + 1 < ARRAY_SIZE(link->tx.buf) && link->tx.buf[i + 1]) { + if (likely(i + 1 < ARRAY_SIZE(link->tx.buf) && link->tx.buf[i + 1])) { bt_mesh_adv_send(buf, PROV_XMIT, NULL, NULL); } else { bt_mesh_adv_send(buf, PROV_XMIT, &buf_sent_cb, link); @@ -518,7 +537,7 @@ static void send_reliable(struct bt_mesh_prov_link *link, uint8_t xmit) break; } - if (i + 1 < ARRAY_SIZE(link->tx.buf) && link->tx.buf[i + 1]) { + if (likely(i + 1 < ARRAY_SIZE(link->tx.buf) && link->tx.buf[i + 1])) { bt_mesh_adv_send(buf, xmit, NULL, NULL); } else { bt_mesh_adv_send(buf, xmit, &buf_sent_cb, link); @@ -651,6 +670,9 @@ int bt_mesh_prov_send_adv(struct bt_mesh_prov_link *link, struct net_buf_simple send_reliable(link, PROV_XMIT); #if CONFIG_BLE_MESH_FAST_PROV + BT_DBG("FastProv, TxPDUType %u LastTxPDU %u", + link->tx_pdu_type, link->last_tx_pdu); + if (link->tx_pdu_type >= link->last_tx_pdu) { timeout = K_SECONDS(60); } diff --git a/components/bt/esp_ble_mesh/core/prov_node.c b/components/bt/esp_ble_mesh/core/prov_node.c index 77f015d9897a..0805c1ddb962 100644 --- a/components/bt/esp_ble_mesh/core/prov_node.c +++ b/components/bt/esp_ble_mesh/core/prov_node.c @@ -52,6 +52,7 @@ struct bt_mesh_prov_link *bt_mesh_prov_node_get_link(void) static void close_link(uint8_t reason) { + BT_DBG("LinkClose(Rpr:%d),Reason:%d", bt_mesh_atomic_test_bit(prov_link.flags, PB_REMOTE), reason); if (bt_mesh_atomic_test_bit(prov_link.flags, PB_REMOTE)) { if (prov_link.pb_remote_close) { prov_link.pb_remote_close(&prov_link, reason); @@ -69,6 +70,7 @@ void bt_mesh_prov_node_close_link(uint8_t reason) static void reset_state(void) { + BT_INFO("ProvLinkStateReset"); k_delayed_work_cancel(&prov_link.prot_timer); /* Disable Attention Timer if it was set */ @@ -122,6 +124,7 @@ static void reset_adv_link(struct bt_mesh_prov_link *link, uint8_t reason) { ARG_UNUSED(link); + BT_INFO("ResetAdvLink:%08x", link->link_id); bt_mesh_prov_clear_tx(&prov_link, true); if (bt_mesh_prov_get()->link_close) { @@ -267,6 +270,7 @@ static int prov_auth(uint8_t method, uint8_t action, uint8_t size) auth_size = PROV_AUTH_SIZE(&prov_link); + BT_INFO("ProvAuth:method:%d,action:%d,size:%d", method, action, size); switch (method) { case AUTH_METHOD_NO_OOB: if (action || size) { @@ -411,6 +415,7 @@ static void prov_start(const uint8_t *data) if ((bt_mesh_prov_get()->oob_type & BIT(PROV_ONLY_OOB_AUTH_SUPPORT)) && ((data[0] == PROV_ALG_P256_HMAC_SHA256 && data[2] == AUTH_METHOD_NO_OOB) || data[0] == PROV_ALG_P256_CMAC_AES128)) { + BT_WARN("InvalidCapabilities,Alg:%d,Method:%d", data[0], data[2]); close_link(PROV_ERR_NVAL_FMT); return; } @@ -561,9 +566,10 @@ int bt_mesh_input_number(uint32_t num) auth_size = PROV_AUTH_SIZE(&prov_link); - BT_INFO("%u", num); + BT_INFO("ProvInputNumber:%u", num); if (!bt_mesh_atomic_test_and_clear_bit(prov_link.flags, WAIT_NUMBER)) { + BT_WARN("InvalidFlag:WAIT_NUMBER"); return -EINVAL; } @@ -572,6 +578,7 @@ int bt_mesh_input_number(uint32_t num) send_input_complete(); if (!bt_mesh_atomic_test_bit(prov_link.flags, HAVE_DHKEY)) { + BT_INFO("DHKeyExists"); return 0; } @@ -587,6 +594,7 @@ int bt_mesh_input_string(const char *str) BT_INFO("%s", str); if (!bt_mesh_atomic_test_and_clear_bit(prov_link.flags, WAIT_STRING)) { + BT_WARN("InvalidFlag:WAIT_STRING"); return -EINVAL; } @@ -595,6 +603,7 @@ int bt_mesh_input_string(const char *str) send_input_complete(); if (!bt_mesh_atomic_test_bit(prov_link.flags, HAVE_DHKEY)) { + BT_INFO("DHKeyExists"); return 0; } @@ -712,6 +721,7 @@ int bt_mesh_set_oob_pub_key(const uint8_t pub_key_x[32], /* If remote public key is not got, just return */ if (!bt_mesh_atomic_test_bit(prov_link.flags, REMOTE_PUB_KEY)) { + BT_WARN("RemotePubKeyNotSet"); return 0; } @@ -902,6 +912,7 @@ static void prov_data(const uint8_t *data) uint8_t reason = 0; if (bt_mesh_rpr_srv_nppi_check(prov_link.pb_remote_nppi, pdu, net_idx, iv_index, addr, &reason) == false) { + BT_WARN("RprNppiCheckFail:%d", reason); close_link(reason); return; } @@ -924,6 +935,7 @@ static void prov_data(const uint8_t *data) pdu, net_idx, flags, iv_index, addr, dev_key); if (err) { + BT_WARN("RprNppiStoreFail:%d", err); close_link(PROV_ERR_UNEXP_ERR); return; } @@ -964,6 +976,7 @@ static void prov_data(const uint8_t *data) * using Node Identity. */ if (IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_SERVER) && identity_enable) { + BT_DBG("EnableProxyIdentity"); bt_mesh_proxy_identity_enable(); } } @@ -973,7 +986,7 @@ static void prov_complete(const uint8_t *data) static void prov_failed(const uint8_t *data) { - BT_WARN("Error: 0x%02x", data[0]); + BT_WARN("ProvError: 0x%02x", data[0]); #if CONFIG_BLE_MESH_RPR_SRV if (bt_mesh_atomic_test_bit(prov_link.flags, PB_REMOTE)) { @@ -1011,7 +1024,7 @@ static const struct { #if CONFIG_BLE_MESH_PB_ADV static void link_open(struct prov_rx *rx, struct net_buf_simple *buf) { - BT_DBG("len %u", buf->len); + BT_DBG("LinkOpenLen:%u", buf->len); if (buf->len < 16) { BT_ERR("Too short bearer open message (len %u)", buf->len); @@ -1065,7 +1078,7 @@ static void link_open(struct prov_rx *rx, struct net_buf_simple *buf) static void link_ack(struct prov_rx *rx, struct net_buf_simple *buf) { - BT_DBG("len %u", buf->len); + BT_DBG("LinkAckLen:%u",buf->len); #if CONFIG_BLE_MESH_RPR_SRV if (bt_mesh_atomic_test_bit(prov_link.flags, PB_REMOTE)) { @@ -1094,7 +1107,7 @@ static void link_close(struct prov_rx *rx, struct net_buf_simple *buf) { uint8_t reason = 0; - BT_DBG("len %u", buf->len); + BT_DBG("LinkCloseLen %u", buf->len); if (buf->len != 1) { BT_ERR("Invalid Link Close length %d", buf->len); @@ -1258,12 +1271,14 @@ static void gen_prov_ack(struct prov_rx *rx, struct net_buf_simple *buf) BT_DBG("len %u", buf->len); if (!prov_link.tx.buf[0]) { + BT_DBG("AlreadyReceived"); return; } #if CONFIG_BLE_MESH_RPR_SRV if (bt_mesh_atomic_test_bit(prov_link.flags, PB_REMOTE)) { if (prov_link.tx.id == 0) { + BT_DBG("ZeroTxId"); return; } @@ -1278,6 +1293,7 @@ static void gen_prov_ack(struct prov_rx *rx, struct net_buf_simple *buf) #endif /* CONFIG_BLE_MESH_RPR_SRV */ if (rx->xact_id == prov_link.tx.id) { + BT_DBG("XActId:%04x,ReceivedAck", rx->xact_id); bt_mesh_prov_clear_tx(&prov_link, true); } } @@ -1342,7 +1358,7 @@ void bt_mesh_pb_adv_recv(struct net_buf_simple *buf) rx.xact_id = net_buf_simple_pull_u8(buf); rx.gpc = net_buf_simple_pull_u8(buf); - BT_DBG("link_id 0x%08x xact_id %u", rx.link_id, rx.xact_id); + BT_DBG("link_id 0x%08x xact_id %u gpc %u", rx.link_id, rx.xact_id, rx.gpc); if (bt_mesh_atomic_test_bit(prov_link.flags, LINK_ACTIVE) && prov_link.link_id != rx.link_id) { @@ -1441,7 +1457,7 @@ int bt_mesh_pb_gatt_recv(struct bt_mesh_conn *conn, struct net_buf_simple *buf) int bt_mesh_pb_gatt_open(struct bt_mesh_conn *conn) { - BT_DBG("conn %p", conn); + BT_DBG("ProvConnOpen %p", conn); /** * It's necessary to determine if it is PB_REMOTE because when the @@ -1482,7 +1498,7 @@ int bt_mesh_pb_gatt_open(struct bt_mesh_conn *conn) int bt_mesh_pb_gatt_close(struct bt_mesh_conn *conn, uint8_t reason) { - BT_DBG("conn %p", conn); + BT_DBG("ProvConnClose %p", conn); if (prov_link.conn != conn) { BT_ERR("Not connected"); diff --git a/components/bt/esp_ble_mesh/core/prov_pvnr.c b/components/bt/esp_ble_mesh/core/prov_pvnr.c index a0435587a98d..d1df4a69e11b 100644 --- a/components/bt/esp_ble_mesh/core/prov_pvnr.c +++ b/components/bt/esp_ble_mesh/core/prov_pvnr.c @@ -202,6 +202,7 @@ static inline void bt_mesh_pb_gatt_unlock(void) void bt_mesh_provisioner_pbg_count_dec(void) { + BT_DBG("PbgCntDec:%d", prov_ctx.pbg_count); if (prov_ctx.pbg_count) { prov_ctx.pbg_count--; } @@ -210,6 +211,7 @@ void bt_mesh_provisioner_pbg_count_dec(void) static inline void provisioner_pbg_count_inc(void) { prov_ctx.pbg_count++; + BT_DBG("PbgCntInc:%d", prov_ctx.pbg_count); } void bt_mesh_provisioner_clear_link_info(const uint8_t addr[6]) @@ -436,8 +438,8 @@ static int provisioner_start_prov_pb_gatt(const uint8_t uuid[16], const bt_mesh_ */ if (assign_addr == BLE_MESH_ADDR_UNASSIGNED && prov_ctx.alloc_addr == BLE_MESH_ADDR_UNASSIGNED) { - BT_ERR("No available unicast address to assign"); bt_mesh_pb_gatt_unlock(); + BT_ERR("No available unicast address to assign"); return -EIO; } @@ -451,6 +453,7 @@ static int provisioner_start_prov_pb_gatt(const uint8_t uuid[16], const bt_mesh_ !bt_mesh_atomic_test_bit(prov_links[i].flags, LINK_ACTIVE)) { if (bt_mesh_gattc_conn_create(addr, BLE_MESH_UUID_MESH_PROV_VAL)) { bt_mesh_pb_gatt_unlock(); + BT_ERR("ProvGattCreateFailed:%s", bt_hex(addr->val, 6)); return -EIO; } @@ -598,6 +601,7 @@ int bt_mesh_provisioner_add_unprov_dev(struct bt_mesh_unprov_dev_add *add_dev, u start: /* If not provisioning immediately, directly return here */ if (!(flags & START_PROV_NOW)) { + BT_DBG("StartProvNotSet"); return 0; } @@ -617,6 +621,9 @@ int bt_mesh_provisioner_add_unprov_dev(struct bt_mesh_unprov_dev_add *add_dev, u } if ((err = provisioner_check_unprov_dev_info(add_dev->uuid, add_dev->bearer))) { + if (err == -EALREADY) { + BT_INFO("The device is being provisioning"); + } return err; } @@ -710,6 +717,9 @@ int bt_mesh_provisioner_prov_device_with_addr(const uint8_t uuid[16], const uint } if ((err = provisioner_check_unprov_dev_info(uuid, bearer))) { + if (err == -EALREADY) { + BT_INFO("The device is being provisioning"); + } return err; } @@ -749,10 +759,12 @@ int bt_mesh_provisioner_delete_device(struct bt_mesh_device_delete *del_dev) return -EINVAL; } + BT_INFO("ProvisionerDeleteDevice:%s", bt_hex(del_dev->uuid, 16)); /* Find if the device is in the device queue */ for (i = 0; i < ARRAY_SIZE(unprov_dev); i++) { if (!memcmp(unprov_dev[i].uuid, del_dev->uuid, 16)) { memset(&unprov_dev[i], 0, sizeof(struct unprov_dev_queue)); + BT_INFO("Device is in the queue"); break; } } @@ -761,6 +773,7 @@ int bt_mesh_provisioner_delete_device(struct bt_mesh_device_delete *del_dev) for (i = 0; i < ARRAY_SIZE(prov_links); i++) { if (!memcmp(prov_links[i].uuid, del_dev->uuid, 16)) { close_link(&prov_links[i], CLOSE_REASON_FAILED); + BT_INFO("Device is being provisioned"); break; } } @@ -776,6 +789,7 @@ int bt_mesh_provisioner_set_dev_uuid_match(uint8_t offset, uint8_t length, return -EINVAL; } + BT_INFO("SetUUIDMatch,offset:%d,value:%s,flag:%d", offset, bt_hex(match, length), prov_flag); (void)memset(prov_ctx.match_value, 0, 16); prov_ctx.match_offset = offset; @@ -795,6 +809,7 @@ int bt_mesh_provisioner_adv_pkt_cb_register(unprov_adv_pkt_cb_t cb) return -EINVAL; } + BT_INFO("RegisterAdvCB:%p", notify_unprov_adv_pkt_cb); notify_unprov_adv_pkt_cb = cb; return 0; } @@ -815,6 +830,7 @@ int bt_mesh_provisioner_set_prov_data_info(struct bt_mesh_prov_data_info *info) } prov_ctx.net_idx = info->net_idx; + BT_INFO("SetProvCtx,NetIndex:%d", info->net_idx); } return 0; @@ -881,6 +897,7 @@ void bt_mesh_provisioner_set_prov_bearer(bt_mesh_prov_bearer_t bearers, bool cle } else { prov_ctx.bearers &= ~bearers; } + BT_INFO("ProvCtxBearer:%04x,clear:%d", prov_ctx.bearers, clear); } bt_mesh_prov_bearer_t bt_mesh_provisioner_get_prov_bearer(void) @@ -909,7 +926,7 @@ int bt_mesh_provisioner_set_static_oob_value(const uint8_t *value, uint8_t lengt prov_ctx.static_oob_len = MIN(BLE_MESH_PROV_STATIC_OOB_MAX_LEN, length); memcpy(prov_ctx.static_oob_val, value, prov_ctx.static_oob_len); - + BT_INFO("SetStaticOob:%s", bt_hex(value, prov_ctx.static_oob_len)); return 0; } @@ -984,11 +1001,13 @@ int bt_mesh_test_provisioner_update_alloc_addr(uint16_t unicast_addr, uint16_t e void bt_mesh_provisioner_fast_prov_enable(bool enable) { prov_ctx.fast_prov.enable = enable; + BT_INFO("FastProvEnable:%d", enable); } void bt_mesh_provisioner_set_fast_prov_net_idx(uint16_t net_idx) { prov_ctx.fast_prov.net_idx = net_idx; + BT_INFO("FastProvNetIdx:%d", net_idx); } uint16_t bt_mesh_provisioner_get_fast_prov_net_idx(void) @@ -1017,7 +1036,7 @@ uint8_t bt_mesh_set_fast_prov_unicast_addr_range(uint16_t min, uint16_t max) prov_ctx.fast_prov.unicast_addr_max = max; prov_ctx.alloc_addr = prov_ctx.fast_prov.unicast_addr_min; - + BT_INFO("FastProv,AddrMin:%04x,Max:%04x,allocAddr:%04x", min, max, prov_ctx.alloc_addr); return 0x0; /* status: success */ } @@ -1038,6 +1057,7 @@ static struct net_buf_simple *get_rx_buf(const uint8_t idx) static void reset_adv_link(struct bt_mesh_prov_link *link, uint8_t reason) { + BT_INFO("ResetAdvLink:%08x", link->link_id); bt_mesh_prov_clear_tx(link, true); if (bt_mesh_prov_get()->prov_link_close) { @@ -1106,6 +1126,7 @@ static void send_link_open(struct bt_mesh_prov_link *link) if (bt_mesh_atomic_test_bit(prov_links[i].flags, LINK_ACTIVE) && prov_links[i].link_id == link->link_id) { bt_mesh_rand(&link->link_id, sizeof(link->link_id)); + BT_DBG("ProvLinkIdx:%d,LinkId:%08x", i, link->link_id); break; } } @@ -1280,6 +1301,7 @@ static void prov_capabilities(struct bt_mesh_prov_link *link, if ((algorithms & BIT(PROV_ALG_P256_CMAC_AES128)) || (!((oob_type & BIT(PROV_STATIC_OOB_AVAILABLE)) == 0x00 || output_size == 0x00 || input_size == 0x00))) { + BT_INFO("InvalidOobTypeSet:%02x,Alg:%02x", oob_type, algorithms); goto fail; } } @@ -1358,6 +1380,7 @@ static void prov_capabilities(struct bt_mesh_prov_link *link, * send Remote Provisioning PDU Send with Public Key. */ if (bt_mesh_atomic_test_bit(link->flags, PB_REMOTE)) { + BT_DBG("WaitForRprClientCmd"); return; } @@ -1387,6 +1410,7 @@ static int prov_auth(struct bt_mesh_prov_link *link, bt_mesh_input_action_t input = 0U; uint8_t auth_size = PROV_AUTH_SIZE(link); + BT_INFO("ProvAuth:method:%d,action:%d,size:%d", method, action, size); switch (method) { case AUTH_METHOD_NO_OOB: if (action || size) { @@ -1778,6 +1802,7 @@ static void prov_gen_dh_key(struct bt_mesh_prov_link *link) */ if (link->auth_method == AUTH_METHOD_OUTPUT || link->auth_method == AUTH_METHOD_INPUT) { + BT_INFO("WaitForNextAction:%d", link->auth_method); return; } @@ -1814,6 +1839,7 @@ static void prov_gen_dh_key(struct bt_mesh_prov_link *link) * Input Complete, because if the authentication method is * Output OOB or Input OOB, it will directly return above. */ + BT_DBG("LinkExpect:%d", link->expect); if (link->expect != PROV_INPUT_COMPLETE) { send_confirm(link); } @@ -2094,6 +2120,7 @@ static void send_prov_data(struct bt_mesh_prov_link *link) link->unicast_addr = alloc_addr; } + BT_DBG("ProvAllocAddr:%04x", link->unicast_addr); bt_mesh_prov_buf_init(&buf, PROV_DATA); err = bt_mesh_prov_encrypt(session_key, nonce, pdu, net_buf_simple_add(&buf, 33)); @@ -2310,7 +2337,7 @@ static void prov_complete(struct bt_mesh_prov_link *link, static void prov_failed(struct bt_mesh_prov_link *link, struct net_buf_simple *buf) { - BT_WARN("Error 0x%02x", buf->data[0]); + BT_WARN("ProvError 0x%02x", buf->data[0]); close_link(link, CLOSE_REASON_FAILED); } @@ -2360,7 +2387,7 @@ static void close_link(struct bt_mesh_prov_link *link, uint8_t reason) #if CONFIG_BLE_MESH_PB_ADV static void link_ack(struct bt_mesh_prov_link *link, struct prov_rx *rx, struct net_buf_simple *buf) { - BT_DBG("len %u", buf->len); + BT_DBG("LinkAckLen %u", buf->len); if (buf->len) { BT_ERR("Invalid Link ACK length %d", buf->len); @@ -2388,7 +2415,7 @@ static void link_ack(struct bt_mesh_prov_link *link, struct prov_rx *rx, struct static void link_close(struct bt_mesh_prov_link *link, struct prov_rx *rx, struct net_buf_simple *buf) { - BT_DBG("len %u", buf->len); + BT_DBG("LinkCloseLen %u", buf->len); if (buf->len != 1) { BT_ERR("Invalid Link Close length %d", buf->len); @@ -2511,10 +2538,12 @@ static void gen_prov_ack(struct bt_mesh_prov_link *link, BT_DBG("len %u", buf->len); if (!link->tx.buf[0]) { + BT_DBG("NullTxbuf"); return; } if (!link->tx.id) { + BT_DBG("ZeroTxId"); return; } @@ -2620,7 +2649,7 @@ void bt_mesh_provisioner_pb_adv_recv(struct net_buf_simple *buf) rx.xact_id = net_buf_simple_pull_u8(buf); rx.gpc = net_buf_simple_pull_u8(buf); - BT_DBG("link_id 0x%08x xact_id %u", rx.link_id, rx.xact_id); + BT_DBG("link_id 0x%08x xact_id %u gpc %u", rx.link_id, rx.xact_id, rx.gpc); link = find_pba_link(rx.link_id); if (link == NULL) { @@ -2783,7 +2812,7 @@ static void protocol_timeout(struct k_work *work) { struct bt_mesh_prov_link *link = work->user_data; - BT_WARN("Protocol timeout"); + BT_WARN("Protocol timeout,RmtAddr:%s", bt_hex(link->addr.val, 6)); close_link(link, CLOSE_REASON_TIMEOUT); } @@ -3112,6 +3141,7 @@ int bt_mesh_rpr_cli_pdu_recv(struct bt_mesh_prov_link *link, uint8_t type, return -EINVAL; } + BT_INFO("RprCliProvType:%d", type); prov_handlers[type].func(link, buf); return 0; } diff --git a/components/bt/esp_ble_mesh/core/proxy_client.c b/components/bt/esp_ble_mesh/core/proxy_client.c index d89c5ff1fdfe..d8d68c934701 100644 --- a/components/bt/esp_ble_mesh/core/proxy_client.c +++ b/components/bt/esp_ble_mesh/core/proxy_client.c @@ -23,11 +23,11 @@ #if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" -#endif +#endif /* CONFIG_BLE_MESH_V11_SUPPORT */ #if (CONFIG_BLE_MESH_PROVISIONER && CONFIG_BLE_MESH_PB_GATT) || \ CONFIG_BLE_MESH_GATT_PROXY_CLIENT || \ - (CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_PB_GATT) + (CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_PB_GATT) static struct bt_mesh_proxy_server { struct bt_mesh_conn *conn; @@ -40,7 +40,8 @@ static struct bt_mesh_proxy_server { #if CONFIG_BLE_MESH_GATT_PROXY_CLIENT uint16_t net_idx; -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_CLIENT */ + uint8_t msg_type; struct k_delayed_work sar_timer; @@ -53,7 +54,7 @@ static struct { struct bt_mesh_prov_link *link; bt_mesh_addr_t addr; } waiting_conn_link[BLE_MESH_MAX_CONN]; -#endif +#endif /* CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_PB_GATT */ static uint8_t server_buf_data[BLE_MESH_PROXY_BUF_SIZE * BLE_MESH_MAX_CONN]; @@ -61,6 +62,8 @@ static struct bt_mesh_proxy_server *find_server(struct bt_mesh_conn *conn) { int i; + BT_DBG("FindServer, ConnHandle 0x%04x", conn->handle); + for (i = 0; i < ARRAY_SIZE(servers); i++) { if (servers[i].conn == conn) { return &servers[i]; @@ -74,15 +77,16 @@ static void proxy_sar_timeout(struct k_work *work) { struct bt_mesh_proxy_server *server = NULL; - BT_WARN("%s", __func__); + BT_WARN("ProxySARTimeout"); server = CONTAINER_OF(work, struct bt_mesh_proxy_server, sar_timer.work); if (!server || !server->conn) { - BT_ERR("Invalid proxy server parameter"); + BT_ERR("InvalidProxyServerParam"); return; } net_buf_simple_reset(&server->buf); + bt_mesh_gattc_disconnect(server->conn); } @@ -90,6 +94,8 @@ static void proxy_sar_timeout(struct k_work *work) int bt_mesh_rpr_srv_set_waiting_prov_link(struct bt_mesh_prov_link *link, bt_mesh_addr_t *addr) { + BT_DBG("RPRSrvSetWaitingProvLink"); + for (size_t i = 0; i < ARRAY_SIZE(waiting_conn_link);i++) { if (waiting_conn_link[i].link == NULL) { waiting_conn_link[i].link = link; @@ -103,8 +109,7 @@ int bt_mesh_rpr_srv_set_waiting_prov_link(struct bt_mesh_prov_link *link, #endif /* CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_PB_GATT */ #if CONFIG_BLE_MESH_GATT_PROXY_CLIENT -/** - * The following callbacks are used to notify proper information +/* The following callbacks are used to notify proper information * to the application layer. */ static proxy_client_recv_adv_cb_t proxy_client_adv_recv_cb; @@ -139,6 +144,8 @@ static void filter_status(struct bt_mesh_proxy_server *server, uint8_t filter_type = 0U; uint16_t list_size = 0U; + BT_DBG("FilterStatus"); + if (buf->len != 3) { BT_ERR("Invalid Proxy Filter Status length %d", buf->len); return; @@ -152,10 +159,11 @@ static void filter_status(struct bt_mesh_proxy_server *server, list_size = net_buf_simple_pull_be16(buf); - BT_INFO("filter_type 0x%02x, list_size %d", filter_type, list_size); + BT_INFO("FilterType %u ListSize %u", filter_type, list_size); if (proxy_client_filter_status_recv_cb) { - proxy_client_filter_status_recv_cb(server - servers, rx->ctx.addr, server->net_idx, filter_type, list_size); + proxy_client_filter_status_recv_cb(server - servers, rx->ctx.addr, + server->net_idx, filter_type, list_size); } } @@ -167,7 +175,7 @@ static void recv_directed_proxy_caps_status(struct bt_mesh_proxy_server *server, uint8_t directed_proxy = net_buf_simple_pull_u8(buf); uint8_t use_directed = net_buf_simple_pull_u8(buf); - BT_INFO("Directed Proxy 0x%02x, Use Directed 0x%02x", directed_proxy, use_directed); + BT_INFO("DirectedProxy %u UseDirected %u", directed_proxy, use_directed); ARG_UNUSED(directed_proxy); ARG_UNUSED(use_directed); @@ -181,13 +189,14 @@ static void proxy_cfg(struct bt_mesh_proxy_server *server) uint8_t opcode = 0U; int err = 0; + BT_DBG("ProxyCfg"); + if (server->buf.len > 29) { BT_ERR("Too large proxy cfg pdu (len %d)", server->buf.len); return; } - err = bt_mesh_net_decode(&server->buf, BLE_MESH_NET_IF_PROXY_CFG, - &rx, &buf); + err = bt_mesh_net_decode(&server->buf, BLE_MESH_NET_IF_PROXY_CFG, &rx, &buf); if (err) { BT_ERR("Failed to decode Proxy Configuration (err %d)", err); return; @@ -201,7 +210,7 @@ static void proxy_cfg(struct bt_mesh_proxy_server *server) rx.local_match = 1U; if (bt_mesh_rpl_check(&rx, NULL)) { - BT_WARN("Replay: src 0x%04x dst 0x%04x seq 0x%06x", + BT_WARN("Replay, Src 0x%04x Dst 0x%04x Seq 0x%06x", rx.ctx.addr, rx.ctx.recv_dst, rx.seq); return; } @@ -209,7 +218,7 @@ static void proxy_cfg(struct bt_mesh_proxy_server *server) /* Remove network headers */ net_buf_simple_pull(&buf, BLE_MESH_NET_HDR_LEN); - BT_DBG("%u bytes: %s", buf.len, bt_hex(buf.data, buf.len)); + BT_DBG("Len %u: %s", buf.len, bt_hex(buf.data, buf.len)); if (buf.len < 3) { BT_WARN("Too short proxy configuration PDU"); @@ -243,6 +252,8 @@ static void proxy_cfg(struct bt_mesh_proxy_server *server) static void proxy_complete_pdu(struct bt_mesh_proxy_server *server) { + BT_DBG("ProxyCompletePDU"); + switch (server->msg_type) { #if CONFIG_BLE_MESH_GATT_PROXY_CLIENT case BLE_MESH_PROXY_NET_PDU: @@ -265,14 +276,14 @@ static void proxy_complete_pdu(struct bt_mesh_proxy_server *server) if (server->conn == bt_mesh_prov_node_get_link()->conn) { bt_mesh_pb_gatt_recv(server->conn, &server->buf); } else -#endif +#endif /* CONFIG_BLE_MESH_RPR_SRV */ { #if CONFIG_BLE_MESH_PROVISIONER bt_mesh_provisioner_pb_gatt_recv(server->conn, &server->buf); -#endif +#endif /* CONFIG_BLE_MESH_PROVISIONER */ } break; -#endif +#endif /* CONFIG_BLE_MESH_PB_GATT && (CONFIG_BLE_MESH_PROVISIONER || CONFIG_BLE_MESH_RPR_SRV) */ default: BT_WARN("Unhandled Message Type 0x%02x", server->msg_type); break; @@ -291,6 +302,8 @@ static ssize_t proxy_recv(struct bt_mesh_conn *conn, const uint8_t *data = buf; uint16_t srvc_uuid = 0U; + BT_DBG("ProxyRecv, ConnHandle 0x%04x", conn->handle); + if (!server) { BT_ERR("No Proxy Server object found"); return -ENOTCONN; @@ -377,7 +390,8 @@ static ssize_t proxy_recv(struct bt_mesh_conn *conn, static int proxy_send(struct bt_mesh_conn *conn, const void *data, uint16_t len) { - BT_DBG("%u bytes: %s", len, bt_hex(data, len)); + BT_DBG("ProxySend"); + BT_DBG("Len %u: %s", len, bt_hex(data, len)); return bt_mesh_gattc_write_no_rsp(conn, NULL, data, len); } @@ -388,13 +402,15 @@ int bt_mesh_proxy_client_segment_send(struct bt_mesh_conn *conn, uint8_t type, uint16_t mtu = 0U; int err = 0; + BT_DBG("ProxyClientSegSend"); + if (conn == NULL) { BT_ERR("%s, Invalid parameter", __func__); return -EINVAL; } - BT_DBG("conn %p type 0x%02x len %u: %s", conn, type, msg->len, - bt_hex(msg->data, msg->len)); + BT_DBG("ConnHandle 0x%04x Type %u", conn->handle, type); + BT_DBG("Len %u: %s", msg->len, bt_hex(msg->data, msg->len)); mtu = bt_mesh_gattc_get_mtu_info(conn); if (!mtu) { @@ -402,6 +418,8 @@ int bt_mesh_proxy_client_segment_send(struct bt_mesh_conn *conn, uint8_t type, return -ENOTCONN; } + BT_DBG("MTU %u", mtu); + /* ATT_MTU - OpCode (1 byte) - Handle (2 bytes) */ mtu -= 3; if (mtu > msg->len) { @@ -433,6 +451,8 @@ int bt_mesh_proxy_client_send(struct bt_mesh_conn *conn, uint8_t type, { struct bt_mesh_proxy_server *server = find_server(conn); + BT_DBG("ProxyClientSend, ConnHandle 0x%04x Type %u", conn->handle, type); + if (!server) { BT_ERR("No Proxy Server object found"); return -ENOTCONN; @@ -450,6 +470,8 @@ static void proxy_connected(bt_mesh_addr_t *addr, struct bt_mesh_conn *conn, int { struct bt_mesh_proxy_server *server = NULL; + BT_DBG("ProxyConnected, ConnHandle 0x%04x ID %d", conn->handle, id); + if (!servers[id].conn) { server = &servers[id]; } @@ -475,7 +497,7 @@ static void proxy_connected(bt_mesh_addr_t *addr, struct bt_mesh_conn *conn, int break; } } -#endif +#endif /* CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_PB_GATT */ bt_mesh_gattc_exchange_mtu(id); } @@ -484,7 +506,7 @@ static void proxy_disconnected(bt_mesh_addr_t *addr, struct bt_mesh_conn *conn, { struct bt_mesh_proxy_server *server = find_server(conn); - BT_DBG("conn %p, handle is %d, reason 0x%02x", conn, conn->handle, reason); + BT_DBG("ProxyDisconnected, ConnHandle 0x%04x Reason 0x%02x", conn->handle, reason); if (!server) { BT_ERR("No Proxy Server object found"); @@ -521,14 +543,15 @@ static void proxy_disconnected(bt_mesh_addr_t *addr, struct bt_mesh_conn *conn, proxy_client_disconnect_cb(addr, server - servers, server->net_idx, reason); } } -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_CLIENT */ k_delayed_work_cancel(&server->sar_timer); + server->conn = NULL; server->conn_type = CLI_NONE; #if CONFIG_BLE_MESH_GATT_PROXY_CLIENT server->net_idx = BLE_MESH_KEY_UNUSED; -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_CLIENT */ } #if CONFIG_BLE_MESH_PB_GATT && \ @@ -537,6 +560,8 @@ static ssize_t prov_write_ccc(bt_mesh_addr_t *addr, struct bt_mesh_conn *conn) { struct bt_mesh_proxy_server *server = find_server(conn); + BT_DBG("ProvWriteCCC, ConnHandle 0x%04x", conn->handle); + if (!server) { BT_ERR("No Proxy Server object found"); return -ENOTCONN; @@ -555,11 +580,11 @@ static ssize_t prov_write_ccc(bt_mesh_addr_t *addr, struct bt_mesh_conn *conn) return bt_mesh_rpr_srv_recv_link_ack(addr->val, false); } -#endif +#endif /* CONFIG_BLE_MESH_RPR_SRV */ #if CONFIG_BLE_MESH_PROVISIONER return bt_mesh_provisioner_pb_gatt_open(conn, addr->val); -#endif +#endif /* CONFIG_BLE_MESH_PROVISIONER */ } return -ENOMEM; @@ -569,6 +594,8 @@ static ssize_t prov_recv_ntf(struct bt_mesh_conn *conn, uint8_t *data, uint16_t { struct bt_mesh_proxy_server *server = find_server(conn); + BT_DBG("ProvRecvNtf, ConnHandle 0x%04x", conn->handle); + if (!server) { BT_ERR("No Proxy Server object found"); return -ENOTCONN; @@ -585,6 +612,8 @@ int bt_mesh_proxy_client_prov_enable(void) { int i; + BT_DBG("ProxyClientProvEnable"); + for (i = 0; i < ARRAY_SIZE(servers); i++) { if (servers[i].conn) { servers[i].conn_type = CLI_PROV; @@ -598,6 +627,8 @@ int bt_mesh_proxy_client_prov_disable(void) { int i; + BT_DBG("ProxyClientProvDisable"); + for (i = 0; i < ARRAY_SIZE(servers); i++) { struct bt_mesh_proxy_server *server = &servers[i]; @@ -616,6 +647,8 @@ static ssize_t proxy_write_ccc(bt_mesh_addr_t *addr, struct bt_mesh_conn *conn) { struct bt_mesh_proxy_server *server = find_server(conn); + BT_DBG("ProxyWriteCCC, ConnHandle 0x%04x", conn->handle); + if (!server) { BT_ERR("No Proxy Server object found"); return -ENOTCONN; @@ -631,11 +664,12 @@ static ssize_t proxy_write_ccc(bt_mesh_addr_t *addr, struct bt_mesh_conn *conn) } #if CONFIG_BLE_MESH_BQB_TEST - /* notify maybe received first */ + /* Notification maybe received firstly */ if (server->conn_type == CLI_PROXY) { return 0; } -#endif +#endif /* CONFIG_BLE_MESH_BQB_TEST */ + return -EINVAL; } @@ -643,20 +677,23 @@ static ssize_t proxy_recv_ntf(struct bt_mesh_conn *conn, uint8_t *data, uint16_t { struct bt_mesh_proxy_server *server = find_server(conn); + BT_DBG("ProxyRecvNtf, ConnHandle 0x%04x", conn->handle); + if (!server) { BT_ERR("No Proxy Server object found"); return -ENOTCONN; } #if CONFIG_BLE_MESH_BQB_TEST - /* update conn type if notify received before write ccc */ + /* Update conn type if notification received before writing ccc */ if (server->conn_type == CLI_NONE) { server->conn_type = CLI_PROXY; + if (proxy_client_connect_cb) { proxy_client_connect_cb(&server->addr, server - servers, server->net_idx); } } -#endif +#endif /* CONFIG_BLE_MESH_BQB_TEST */ if (server->conn_type == CLI_PROXY) { return proxy_recv(conn, NULL, data, len, 0, 0); @@ -665,8 +702,7 @@ static ssize_t proxy_recv_ntf(struct bt_mesh_conn *conn, uint8_t *data, uint16_t return -EINVAL; } -/** - * Currently proxy client doesn't need bt_mesh_proxy_client_gatt_enable() +/* Currently proxy client doesn't need bt_mesh_proxy_client_gatt_enable() * and bt_mesh_proxy_client_gatt_disable() functions, and once they are * used, proxy client can be enabled to parse node_id_adv and net_id_adv * in order to support proxy client role. @@ -677,6 +713,8 @@ int bt_mesh_proxy_client_gatt_enable(void) { int i; + BT_DBG("ProxyClientGattEnable"); + for (i = 0; i < ARRAY_SIZE(servers); i++) { if (servers[i].conn) { servers[i].conn_type = CLI_PROXY; @@ -696,8 +734,9 @@ int bt_mesh_proxy_client_gatt_disable(void) { int i; - /** - * TODO: + BT_DBG("ProxyClientGattDisable"); + + /* TODO: * Once this function is invoked, proxy client shall stop handling * node_id & net_id adv packets, and if proxy connection exists, * it should be disconnected. @@ -739,6 +778,8 @@ static struct bt_mesh_subnet *bt_mesh_is_net_id_exist(const uint8_t net_id[8]) size = bt_mesh_rx_netkey_size(); + BT_DBG("IsNetIDExist, Size %u", size); + for (i = 0U; i < size; i++) { sub = bt_mesh_rx_netkey_get(i); if (sub && !memcmp(sub->keys[sub->kr_flag].net_id, net_id, 8)) { @@ -753,8 +794,11 @@ void bt_mesh_proxy_client_gatt_adv_recv(struct net_buf_simple *buf, const bt_mesh_addr_t *addr, int8_t rssi) { bt_mesh_proxy_adv_ctx_t ctx = {0}; + struct bt_mesh_subnet *sub = NULL; uint8_t type = 0U; + BT_DBG("ProxyClientGattAdvRecv, Rssi %d", rssi); + /* Check if connection reaches the maximum limitation */ if (bt_mesh_gattc_get_free_conn_count() == 0) { BT_INFO("BLE connections for mesh reach max limit"); @@ -763,14 +807,15 @@ void bt_mesh_proxy_client_gatt_adv_recv(struct net_buf_simple *buf, type = net_buf_simple_pull_u8(buf); + BT_DBG("Type %u", type); + switch (type) { - case BLE_MESH_PROXY_ADV_NET_ID: { + case BLE_MESH_PROXY_ADV_NET_ID: if (buf->len != sizeof(ctx.net_id.net_id)) { BT_WARN("Malformed Network ID"); return; } - struct bt_mesh_subnet *sub = NULL; sub = bt_mesh_is_net_id_exist(buf->data); if (!sub) { return; @@ -779,7 +824,6 @@ void bt_mesh_proxy_client_gatt_adv_recv(struct net_buf_simple *buf, memcpy(ctx.net_id.net_id, buf->data, buf->len); ctx.net_id.net_idx = sub->net_idx; break; - } case BLE_MESH_PROXY_ADV_NODE_ID: /* Gets node identity information. * hash = aes-ecb(identity key, 16 octets(padding + random + src)) mod 2^64, @@ -808,6 +852,8 @@ int bt_mesh_proxy_client_connect(const uint8_t addr[6], uint8_t addr_type, uint1 bt_mesh_addr_t remote_addr = {0}; int result = 0; + BT_DBG("ProxyClientConnect, NetIdx 0x%04x", net_idx); + if (!addr || addr_type > BLE_MESH_ADDR_RANDOM) { BT_ERR("%s, Invalid parameter", __func__); return -EINVAL; @@ -830,13 +876,13 @@ int bt_mesh_proxy_client_disconnect(uint8_t conn_handle) { struct bt_mesh_conn *conn = NULL; + BT_DBG("ProxyClientDisconnect, ConnHandle 0x%04x", conn_handle); + if (conn_handle >= BLE_MESH_MAX_CONN) { BT_ERR("%s, Invalid parameter", __func__); return -EINVAL; } - BT_DBG("conn_handle %d", conn_handle); - conn = servers[conn_handle].conn; if (!conn) { BT_ERR("Not connected, conn handle %d", conn_handle); @@ -853,6 +899,8 @@ bool bt_mesh_proxy_client_relay(struct net_buf_simple *buf, uint16_t dst) int err = 0; int i; + BT_DBG("ProxyClientRelay, Dst 0x%04x", dst); + for (i = 0; i < ARRAY_SIZE(servers); i++) { struct bt_mesh_proxy_server *server = &servers[i]; NET_BUF_SIMPLE_DEFINE(msg, 32); @@ -883,12 +931,15 @@ static int beacon_send(struct bt_mesh_conn *conn, struct bt_mesh_subnet *sub, bo { NET_BUF_SIMPLE_DEFINE(buf, 28); + BT_DBG("BeaconSend, ConnHandle 0x%04x Private %u", conn->handle, private); + net_buf_simple_reserve(&buf, 1); + #if CONFIG_BLE_MESH_PRB_SRV if (private) { bt_mesh_private_beacon_create(sub, &buf); } else -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ { bt_mesh_secure_beacon_create(sub, &buf); } @@ -902,6 +953,8 @@ bool bt_mesh_proxy_client_beacon_send(struct bt_mesh_subnet *sub, bool private) int err = 0; int i; + BT_DBG("ProxyClientBeaconSend, Private %u", private); + /* NULL means we send Secure Network Beacon or Mesh Private Beacon on all subnets */ if (!sub) { #if CONFIG_BLE_MESH_NODE @@ -958,6 +1011,8 @@ static int send_proxy_cfg(struct bt_mesh_conn *conn, uint16_t net_idx, struct bt uint16_t alloc_len = 0U; int err = 0; + BT_DBG("SendProxyCfg, ConnHandle 0x%04x NetIdx 0x%04x", conn->handle, net_idx); + tx.sub = bt_mesh_subnet_get(net_idx); if (!tx.sub) { BT_ERR("NetKey 0x%04x not found", net_idx); @@ -1021,6 +1076,7 @@ static int send_proxy_cfg(struct bt_mesh_conn *conn, uint16_t net_idx, struct bt */ buf = bt_mesh_alloc_buf(1 + BLE_MESH_NET_HDR_LEN + alloc_len + 8); if (!buf) { + BT_ERR("Out of memory"); return -ENOMEM; } @@ -1055,11 +1111,10 @@ static int send_proxy_cfg(struct bt_mesh_conn *conn, uint16_t net_idx, struct bt #endif /* CONFIG_BLE_MESH_DF_SRV */ } - BT_DBG("len %u bytes: %s", buf->len, bt_hex(buf->data, buf->len)); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); err = bt_mesh_net_encode(&tx, buf, true); if (err) { - BT_ERR("Encoding proxy cfg message failed (err %d)", err); goto end; } @@ -1078,13 +1133,14 @@ int bt_mesh_proxy_client_cfg_send(uint8_t conn_handle, uint16_t net_idx, { struct bt_mesh_conn *conn = NULL; - if (conn_handle >= BLE_MESH_MAX_CONN || !pdu || pdu->opcode > BLE_MESH_PROXY_CFG_DIRECTED_PROXY_CONTROL) { + BT_DBG("ProxyClientCfgSend, ConnHandle 0x%04x NetIdx 0x%04x", conn_handle, net_idx); + + if (conn_handle >= BLE_MESH_MAX_CONN || !pdu || + pdu->opcode > BLE_MESH_PROXY_CFG_DIRECTED_PROXY_CONTROL) { BT_ERR("%s, Invalid parameter", __func__); return -EINVAL; } - BT_DBG("conn_handle %d, net_idx 0x%04x", conn_handle, net_idx); - conn = servers[conn_handle].conn; if (!conn) { BT_ERR("Not connected, conn handle %d", conn_handle); @@ -1096,7 +1152,7 @@ int bt_mesh_proxy_client_cfg_send(uint8_t conn_handle, uint16_t net_idx, */ if (servers[conn_handle].net_idx != net_idx) { BT_ERR("NetKeyIndex 0x%04x mismatch, expect 0x%04x", - net_idx, servers[conn_handle].net_idx); + net_idx, servers[conn_handle].net_idx); return -EIO; } @@ -1108,16 +1164,19 @@ int bt_mesh_proxy_client_init(void) { int i; + BT_DBG("ProxyClientInit"); + /* Initialize the server receive buffers */ for (i = 0; i < ARRAY_SIZE(servers); i++) { struct bt_mesh_proxy_server *server = &servers[i]; k_delayed_work_init(&server->sar_timer, proxy_sar_timeout); + server->buf.size = BLE_MESH_PROXY_BUF_SIZE; server->buf.__buf = server_buf_data + (i * BLE_MESH_PROXY_BUF_SIZE); #if CONFIG_BLE_MESH_GATT_PROXY_CLIENT server->net_idx = BLE_MESH_KEY_UNUSED; -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_CLIENT */ } bt_mesh_gattc_conn_cb_register(&conn_callbacks); @@ -1126,7 +1185,7 @@ int bt_mesh_proxy_client_init(void) bt_mesh_update_exceptional_list(BLE_MESH_EXCEP_LIST_SUB_CODE_ADD, BLE_MESH_EXCEP_LIST_TYPE_MESH_PROXY_ADV, NULL); -#endif +#endif /* CONFIG_BLE_MESH_USE_DUPLICATE_SCAN && CONFIG_BLE_MESH_GATT_PROXY_CLIENT */ return 0; } @@ -1136,6 +1195,8 @@ int bt_mesh_proxy_client_deinit(void) { int i; + BT_DBG("ProxyClientDeinit"); + /* Initialize the server receive buffers */ for (i = 0; i < ARRAY_SIZE(servers); i++) { struct bt_mesh_proxy_server *server = &servers[i]; diff --git a/components/bt/esp_ble_mesh/core/proxy_server.c b/components/bt/esp_ble_mesh/core/proxy_server.c index cc98e03cdc4e..ed73f1144ac4 100644 --- a/components/bt/esp_ble_mesh/core/proxy_server.c +++ b/components/bt/esp_ble_mesh/core/proxy_server.c @@ -24,7 +24,7 @@ #if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" -#endif +#endif /* CONFIG_BLE_MESH_V11_SUPPORT */ #if (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || \ CONFIG_BLE_MESH_GATT_PROXY_SERVER @@ -65,19 +65,19 @@ static bool proxy_adv_enabled; #if CONFIG_BLE_MESH_GATT_PROXY_SERVER static void proxy_send_beacons(struct k_work *work); static uint16_t proxy_ccc_val; -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER */ #if CONFIG_BLE_MESH_PB_GATT static uint16_t prov_ccc_val; static bool prov_fast_adv; static uint32_t prov_start_time; -#endif +#endif /* CONFIG_BLE_MESH_PB_GATT */ static struct bt_mesh_proxy_client clients[BLE_MESH_MAX_CONN] = { [0 ... (BLE_MESH_MAX_CONN - 1)] = { #if CONFIG_BLE_MESH_PROXY_PRIVACY .proxy_privacy = BLE_MESH_PROXY_PRIVACY_DISABLED, -#endif +#endif /* CONFIG_BLE_MESH_PROXY_PRIVACY */ }, }; @@ -94,6 +94,8 @@ static char device_name[DEVICE_NAME_SIZE + 1]; struct bt_mesh_proxy_client *bt_mesh_proxy_server_get_client(uint8_t index) { + BT_DBG("ProxyServerGetClient, Index %u", index); + return &clients[0]; } @@ -104,11 +106,15 @@ uint8_t bt_mesh_proxy_server_get_client_count(void) int bt_mesh_set_device_name(const char *name) { + BT_DBG("SetDeviceName"); + if (!name) { BT_ERR("%s, Invalid parameter", __func__); return -EINVAL; } + BT_DBG("Name %s", name); + if (strlen(name) > DEVICE_NAME_SIZE) { BT_ERR("Too long device name (len %d)", strlen(name)); return -EINVAL; @@ -122,6 +128,8 @@ int bt_mesh_set_device_name(const char *name) const char *bt_mesh_get_device_name(void) { + BT_DBG("GetDeviceName %s", device_name); + return device_name; } @@ -129,6 +137,8 @@ static struct bt_mesh_proxy_client *find_client(struct bt_mesh_conn *conn) { int i; + BT_DBG("FindClient, ConnHandle 0x%04x", conn->handle); + for (i = 0; i < ARRAY_SIZE(clients); i++) { if (clients[i].conn == conn) { return &clients[i]; @@ -142,7 +152,7 @@ static void proxy_sar_timeout(struct k_work *work) { struct bt_mesh_proxy_client *client = NULL; - BT_WARN("Proxy SAR timeout"); + BT_WARN("ProxySARTimeout"); client = CONTAINER_OF(work, struct bt_mesh_proxy_client, sar_timer.work); if (!client || !client->conn) { @@ -155,8 +165,7 @@ static void proxy_sar_timeout(struct k_work *work) } #if CONFIG_BLE_MESH_GATT_PROXY_SERVER -/** - * The following callbacks are used to notify proper information +/* The following callbacks are used to notify proper information * to the application layer. */ static proxy_server_connect_cb_t proxy_server_connect_cb; @@ -177,6 +186,8 @@ static int next_idx; bool bt_mesh_proxy_server_find_client_by_addr(uint16_t addr) { + BT_DBG("ProxyServerFindClient, Addr 0x%04x", addr); + for (size_t i = 0; i < ARRAY_SIZE(clients); i++) { if (clients[i].conn) { for (size_t j = 0; j < ARRAY_SIZE(clients[i].filter); j++) { @@ -204,6 +215,8 @@ uint8_t bt_mesh_proxy_server_get_all_client_type(void) } } + BT_DBG("ProxyServerGetAllClientType, type 0x%02x", client_type); + return client_type; } @@ -212,13 +225,16 @@ static int filter_set(struct bt_mesh_proxy_client *client, { uint8_t type = 0U; + BT_INFO("FilterSet"); + if (buf->len < 1) { BT_WARN("Too short Filter Set message"); return -EINVAL; } type = net_buf_simple_pull_u8(buf); - BT_INFO("Set filter type 0x%02x", type); + + BT_INFO("Type 0x%02x", type); switch (type) { case 0x00: @@ -249,7 +265,7 @@ static void filter_add(struct bt_mesh_proxy_client *client, * is the element address of Proxy Client. */ - BT_DBG("addr 0x%04x", addr); + BT_DBG("FilterAdd, Addr 0x%04x ProxyClient %u", addr, proxy_client); if (addr == BLE_MESH_ADDR_UNASSIGNED) { return; @@ -279,14 +295,14 @@ static void filter_add(struct bt_mesh_proxy_client *client, } } - BT_WARN("Proxy filter is full!"); + BT_WARN("ProxyFilterFull"); } static void filter_remove(struct bt_mesh_proxy_client *client, uint16_t addr) { int i; - BT_DBG("addr 0x%04x", addr); + BT_DBG("FilterRemove, Addr 0x%04x", addr); if (addr == BLE_MESH_ADDR_UNASSIGNED) { return; @@ -314,6 +330,8 @@ static void send_filter_status(struct bt_mesh_proxy_client *client, uint16_t filter_size = 0U; int i, err = 0; + BT_DBG("SetFilterStatus"); + /* Configuration messages always have dst unassigned */ tx.ctx->addr = BLE_MESH_ADDR_UNASSIGNED; tx.ctx->send_cred = BLE_MESH_FLOODING_CRED, @@ -337,11 +355,10 @@ static void send_filter_status(struct bt_mesh_proxy_client *client, net_buf_simple_add_be16(buf, filter_size); - BT_DBG("%u bytes: %s", buf->len, bt_hex(buf->data, buf->len)); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); err = bt_mesh_net_encode(&tx, buf, true); if (err) { - BT_ERR("Encoding proxy filter status failed (err %d)", err); return; } @@ -358,13 +375,14 @@ static void proxy_cfg(struct bt_mesh_proxy_client *client) uint8_t opcode = 0U; int err = 0; + BT_DBG("ProxyCfg"); + if (client->buf.len > 29) { BT_ERR("Too large proxy cfg pdu (len %d)", client->buf.len); return; } - err = bt_mesh_net_decode(&client->buf, BLE_MESH_NET_IF_PROXY_CFG, - &rx, &buf); + err = bt_mesh_net_decode(&client->buf, BLE_MESH_NET_IF_PROXY_CFG, &rx, &buf); if (err) { BT_ERR("Failed to decode Proxy Configuration (err %d)", err); return; @@ -373,7 +391,7 @@ static void proxy_cfg(struct bt_mesh_proxy_client *client) rx.local_match = 1U; if (bt_mesh_rpl_check(&rx, NULL)) { - BT_WARN("Replay: src 0x%04x dst 0x%04x seq 0x%06x", + BT_WARN("Replay, Src 0x%04x Dst 0x%04x Seq 0x%06x", rx.ctx.addr, rx.ctx.recv_dst, rx.seq); return; } @@ -381,7 +399,7 @@ static void proxy_cfg(struct bt_mesh_proxy_client *client) /* Remove network headers */ net_buf_simple_pull(&buf, BLE_MESH_NET_HDR_LEN); - BT_DBG("%u bytes: %s", buf.len, bt_hex(buf.data, buf.len)); + BT_DBG("Len %u: %s", buf.len, bt_hex(buf.data, buf.len)); if (buf.len < 1) { BT_WARN("Too short proxy configuration PDU"); @@ -437,6 +455,8 @@ static int beacon_send(struct bt_mesh_proxy_client *client, struct bt_mesh_subne { NET_BUF_SIMPLE_DEFINE(buf, 28); + BT_DBG("BeaconSend"); + net_buf_simple_reserve(&buf, 1); #if CONFIG_BLE_MESH_PROXY_PRIVACY @@ -448,7 +468,7 @@ static int beacon_send(struct bt_mesh_proxy_client *client, struct bt_mesh_subne bt_mesh_private_beacon_create(sub, &buf); } else -#endif +#endif /* CONFIG_BLE_MESH_PROXY_PRIVACY */ { bt_mesh_secure_beacon_create(sub, &buf); } @@ -458,10 +478,12 @@ static int beacon_send(struct bt_mesh_proxy_client *client, struct bt_mesh_subne static void proxy_send_beacons(struct k_work *work) { - struct bt_mesh_proxy_client *client = NULL; + struct bt_mesh_proxy_client *client = CONTAINER_OF(work, + struct bt_mesh_proxy_client, + send_beacons);; int i; - client = CONTAINER_OF(work, struct bt_mesh_proxy_client, send_beacons); + BT_DBG("ProxySendBeacons"); /* Upon connection, the Proxy Server shall evaluate Proxy Privacy parameter * for the connection and the Proxy Server shall retain the value of the @@ -496,7 +518,7 @@ static void proxy_send_beacons(struct k_work *work) } else if (sub->proxy_privacy == BLE_MESH_PROXY_PRIVACY_ENABLED) { #if CONFIG_BLE_MESH_PRB_SRV /* TODO: Send Mesh Private Beacon */ -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ } } #endif @@ -507,6 +529,8 @@ void bt_mesh_proxy_server_beacon_send(struct bt_mesh_subnet *sub) { int i; + BT_DBG("ProxyServerBeaconSend, Sub %p", sub); + if (!sub) { /* NULL means we send on all subnets */ for (i = 0; i < ARRAY_SIZE(bt_mesh.sub); i++) { @@ -532,10 +556,14 @@ void bt_mesh_proxy_server_identity_start(struct bt_mesh_subnet *sub) /* Prioritize the recently enabled subnet */ next_idx = sub - bt_mesh.sub; + + BT_DBG("ProxyServerIdentityStart, NextIdx %d", next_idx); } void bt_mesh_proxy_server_identity_stop(struct bt_mesh_subnet *sub) { + BT_DBG("ProxyServerIdentityStop"); + sub->node_id = BLE_MESH_NODE_IDENTITY_STOPPED; sub->node_id_start = 0U; } @@ -544,7 +572,10 @@ int bt_mesh_proxy_identity_enable(void) { int i, count = 0; + BT_DBG("ProxyIdentityEnable"); + if (!bt_mesh_is_provisioned()) { + BT_DBG("NotProvisioned"); return -EAGAIN; } @@ -560,9 +591,12 @@ int bt_mesh_proxy_identity_enable(void) } bt_mesh_proxy_server_identity_start(sub); + count++; } + BT_DBG("SubCount %u", count); + if (count) { bt_mesh_adv_update(); } @@ -578,16 +612,22 @@ void bt_mesh_proxy_server_private_identity_start(struct bt_mesh_subnet *sub) /* Prioritize the recently enabled subnet */ next_idx = sub - bt_mesh.sub; + + BT_DBG("ProxyServerPrivateIdentityStart, NextIdx %d", next_idx); } void bt_mesh_proxy_server_private_identity_stop(struct bt_mesh_subnet *sub) { + BT_DBG("ProxyServerPrivateIdentityStop"); + sub->private_node_id = BLE_MESH_PRIVATE_NODE_IDENTITY_STOPPED; sub->node_id_start = 0U; } bool bt_mesh_proxy_server_is_node_id_enable(void) { + BT_DBG("ProxyServerIsNodeIDEnable"); + for (size_t i = 0; i < ARRAY_SIZE(bt_mesh.sub); i++) { /* If the Node Identity state of the node for any subnet * is 0x01 (i.e. running), return true. @@ -607,22 +647,27 @@ static bool is_exist_private_node_id_enable(void) { for (size_t i = 0; i < ARRAY_SIZE(bt_mesh.sub); i++) { /* If the value of the Node Identity state of the node - * for any subnet is 0x01,If exist return true. + * for any subnet is 0x01, if exist return true. */ struct bt_mesh_subnet *sub = &bt_mesh.sub[i]; if (sub->net_idx != BLE_MESH_KEY_UNUSED && sub->private_node_id == BLE_MESH_PRIVATE_NODE_IDENTITY_RUNNING) { + BT_DBG("PrivateNodeIDExist, NetIdx 0x%04x", sub->net_idx); return true; } } + BT_DBG("PrivateNodeIDNotExist"); return false; } int bt_mesh_proxy_private_identity_disable(void) { + BT_DBG("ProxyPrivateIdentityDisable"); + if (!bt_mesh_is_provisioned()) { + BT_DBG("NotProvisioned"); return -EAGAIN; } @@ -648,7 +693,10 @@ int bt_mesh_proxy_private_identity_enable(void) { int count = 0; + BT_DBG("ProxyPrivateIdentityEnable"); + if (!bt_mesh_is_provisioned()) { + BT_DBG("NotProvisioned"); return -EAGAIN; } @@ -664,9 +712,12 @@ int bt_mesh_proxy_private_identity_enable(void) } bt_mesh_proxy_server_private_identity_start(sub); + count++; } + BT_DBG("SubCount %u", count); + if (count) { bt_mesh_adv_update(); } @@ -674,10 +725,12 @@ int bt_mesh_proxy_private_identity_enable(void) return 0; } #endif /* CONFIG_BLE_MESH_PRB_SRV */ -#endif /* GATT_PROXY */ +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER */ static void proxy_complete_pdu(struct bt_mesh_proxy_client *client) { + BT_DBG("ProxyCompletePDU"); + switch (client->msg_type) { #if CONFIG_BLE_MESH_GATT_PROXY_SERVER case BLE_MESH_PROXY_NET_PDU: @@ -692,13 +745,13 @@ static void proxy_complete_pdu(struct bt_mesh_proxy_client *client) BT_DBG("Mesh Configuration PDU"); proxy_cfg(client); break; -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER */ #if CONFIG_BLE_MESH_PB_GATT case BLE_MESH_PROXY_PROV: BT_DBG("Mesh Provisioning PDU"); bt_mesh_pb_gatt_recv(client->conn, &client->buf); break; -#endif +#endif /* CONFIG_BLE_MESH_PB_GATT */ default: BT_WARN("Unhandled Message Type 0x%02x", client->msg_type); break; @@ -709,27 +762,35 @@ static void proxy_complete_pdu(struct bt_mesh_proxy_client *client) #if CONFIG_BLE_MESH_GATT_PROXY_SERVER if (client->msg_type < BLE_MESH_PROXY_PROV && client->proxy_msg_recv == false) { - client->proxy_msg_recv = true; - /** - * @Spec: P626 - * When a new connection is established between a Proxy Client and the Directed Proxy Server, and the - * first message received from the Proxy Client is a successfully processed DIRECTED_PROXY_CONTROL - * message, then the Directed Proxy Server shall set the Proxy_Client_Type parameter to Directed Proxy Client, - * shall set the Use_Directed parameter to Disable for all subnets known to the Directed Proxy Server - * except the subnet identified by the received message; - * otherwise, the Directed Proxy Server shall set the Proxy_Client_Type parameter to Proxy Client. + /* @Spec: P626 + * When a new connection is established between a Proxy Client and + * the Directed Proxy Server, and the first message received from + * the Proxy Client is a successfully processed DIRECTED_PROXY_CONTROL + * message, then the Directed Proxy Server shall set the Proxy_Client_Type + * parameter to Directed Proxy Client, shall set the Use_Directed + * parameter to Disable for all subnets known to the Directed Proxy + * Server except the subnet identified by the received message; + * otherwise, the Directed Proxy Server shall set the Proxy_Client_Type + * parameter to Proxy Client. * - * If the first message received is DIRECTED_PROXY_CONTROL, proxy_client_type will be set to Directed Proxy Client, - * But if device didn't receive DIRECTED_PROXY_CONTROL message and all received is normal proxy message, That - * client type will be always in UNSET state, because we set client type in handle function of DIRECTED_PROXY_CONTROL. + * If the first message received is DIRECTED_PROXY_CONTROL, proxy_client_type + * will be set to Directed Proxy Client. + * But if device didn't receive DIRECTED_PROXY_CONTROL message and all + * received is normal proxy message, That client type will be always in + * UNSET state, because we set client type in handle function of + * DIRECTED_PROXY_CONTROL. * * So the flowing code was used to avoid that situation. - */ + */ + client->proxy_msg_recv = true; + + BT_DBG("ProxyClientTypeUpdate"); + if (client->proxy_client_type == BLE_MESH_PROXY_CLI_TYPE_UNSET) { client->proxy_client_type = BLE_MESH_PROXY_CLI_TYPE_PROXY_CLIENT; } } -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER */ } #define ATTR_IS_PROV(attr) (attr->user_data != NULL) @@ -741,6 +802,8 @@ static ssize_t proxy_recv(struct bt_mesh_conn *conn, struct bt_mesh_proxy_client *client = find_client(conn); const uint8_t *data = buf; + BT_DBG("ProxyRecv"); + if (!client) { BT_ERR("No Proxy Client found"); return -ENOTCONN; @@ -826,7 +889,7 @@ static void proxy_connected(struct bt_mesh_conn *conn, uint8_t err) struct bt_mesh_proxy_client *client = NULL; int i; - BT_DBG("conn %p err 0x%02x", conn, err); + BT_DBG("ProxyConnected, ConnHandle 0x%04x Err 0x%02x", conn->handle, err); if (gatt_svc == MESH_GATT_PROV && conn_count == 1) { BT_WARN("Only one prov connection could exists"); @@ -845,7 +908,9 @@ static void proxy_connected(struct bt_mesh_conn *conn, uint8_t err) * Network Identity type. */ bt_mesh_proxy_server_stop_solic_adv_priv_net_id(); -#endif +#endif /* CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX */ + + BT_DBG("ConnCount %u vs. %u", conn_count, BLE_MESH_MAX_CONN); /* Try to re-enable advertising in case it's possible */ if (conn_count < BLE_MESH_MAX_CONN) { @@ -866,13 +931,15 @@ static void proxy_connected(struct bt_mesh_conn *conn, uint8_t err) client->conn = bt_mesh_conn_ref(conn); client->filter_type = SRV_NONE; + #if CONFIG_BLE_MESH_GATT_PROXY_SERVER (void)memset(client->filter, 0, sizeof(client->filter)); if (proxy_server_connect_cb) { proxy_server_connect_cb(conn->handle); } -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER */ + net_buf_simple_reset(&client->buf); } @@ -880,7 +947,8 @@ static void proxy_disconnected(struct bt_mesh_conn *conn, uint8_t reason) { int i; - BT_DBG("conn %p reason 0x%02x", conn, reason); + BT_DBG("ProxyDisconnected, ConnHandle 0x%04x Count %u Reason 0x%02x", + conn->handle, conn_count, reason); conn_count--; @@ -892,7 +960,8 @@ static void proxy_disconnected(struct bt_mesh_conn *conn, uint8_t reason) if (proxy_server_disconnect_cb) { proxy_server_disconnect_cb(conn->handle, reason); } -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER */ + if (IS_ENABLED(CONFIG_BLE_MESH_PB_GATT) && client->filter_type == SRV_PROV) { bt_mesh_pb_gatt_close(conn, reason); @@ -900,11 +969,11 @@ static void proxy_disconnected(struct bt_mesh_conn *conn, uint8_t reason) #if CONFIG_BLE_MESH_PROXY_PRIVACY client->proxy_privacy = BLE_MESH_PROXY_PRIVACY_DISABLED; -#endif +#endif /* CONFIG_BLE_MESH_PROXY_PRIVACY */ #if CONFIG_BLE_MESH_GATT_PROXY_SERVER && CONFIG_BLE_MESH_PRB_SRV k_delayed_work_cancel(&rand_upd_timer); -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER && CONFIG_BLE_MESH_PRB_SRV */ k_delayed_work_cancel(&client->sar_timer); bt_mesh_conn_unref(client->conn); @@ -924,13 +993,15 @@ static void proxy_disconnected(struct bt_mesh_conn *conn, uint8_t reason) if (bt_mesh_directed_proxy_server_update_dep_node(NULL, &clients[i], 0)) { BT_ERR("Proxy disconnected, failed to update dependent node"); } -#endif /* CONFIG_BLE_MESH_DF_SRV */ +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER && CONFIG_BLE_MESH_DF_SRV */ } struct net_buf_simple *bt_mesh_proxy_server_get_buf(void) { struct net_buf_simple *buf = &clients[0].buf; + BT_DBG("ProxyServerGetBuf"); + net_buf_simple_reset(buf); return buf; @@ -945,9 +1016,11 @@ static ssize_t prov_ccc_write(struct bt_mesh_conn *conn, struct bt_mesh_proxy_client *client = NULL; uint16_t *value = attr->user_data; - BT_DBG("len %u: %s", len, bt_hex(buf, len)); + BT_DBG("ProvCCCWrite"); + BT_DBG("Len %u: %s", len, bt_hex(buf, len)); if (len != sizeof(*value)) { + BT_WARN("MismatchLen %u != %u", len, sizeof(*value)); return BLE_MESH_GATT_ERR(BLE_MESH_ATT_ERR_INVALID_ATTRIBUTE_LEN); } @@ -978,6 +1051,8 @@ static ssize_t prov_ccc_read(struct bt_mesh_conn *conn, { uint16_t *value = attr->user_data; + BT_DBG("ProvCCCRead, Len %u", len); + return bt_mesh_gatts_attr_read(conn, attr, buf, len, offset, value, sizeof(*value)); } @@ -1007,6 +1082,8 @@ int bt_mesh_proxy_server_prov_enable(void) { int i; + BT_DBG("ProxyServerProvEnable"); + if (gatt_svc == MESH_GATT_PROV) { BT_WARN("%s, Already", __func__); return -EALREADY; @@ -1035,6 +1112,8 @@ int bt_mesh_proxy_server_prov_disable(bool disconnect) { int i; + BT_DBG("ProxyServerProvDisable, Disconnect %u", disconnect); + if (gatt_svc == MESH_GATT_NONE) { BT_WARN("%s, Already", __func__); return -EALREADY; @@ -1078,9 +1157,11 @@ static ssize_t proxy_ccc_write(struct bt_mesh_conn *conn, struct bt_mesh_proxy_client *client = NULL; uint16_t value = 0U; - BT_DBG("len %u: %s", len, bt_hex(buf, len)); + BT_DBG("ProxyCCCWrite"); + BT_DBG("Len %u: %s", len, bt_hex(buf, len)); if (len != sizeof(value)) { + BT_WARN("MismatchLen %u != %u", len, sizeof(value)); return BLE_MESH_GATT_ERR(BLE_MESH_ATT_ERR_INVALID_ATTRIBUTE_LEN); } @@ -1135,6 +1216,8 @@ static ssize_t proxy_ccc_read(struct bt_mesh_conn *conn, { uint16_t *value = attr->user_data; + BT_DBG("ProxyCCCRead, Len %u", len); + return bt_mesh_gatts_attr_read(conn, attr, buf, len, offset, value, sizeof(*value)); } @@ -1164,6 +1247,8 @@ int bt_mesh_proxy_server_gatt_enable(void) { int i; + BT_DBG("ProxyServerGattEnable"); + if (gatt_svc == MESH_GATT_PROXY) { BT_WARN("%s, Already", __func__); return -EALREADY; @@ -1190,6 +1275,8 @@ void bt_mesh_proxy_server_gatt_disconnect(void) { int i; + BT_DBG("ProxyServerGattDisconnect"); + for (i = 0; i < ARRAY_SIZE(clients); i++) { struct bt_mesh_proxy_client *client = &clients[i]; @@ -1203,6 +1290,8 @@ void bt_mesh_proxy_server_gatt_disconnect(void) int bt_mesh_proxy_server_gatt_disable(void) { + BT_DBG("ProxyServerGattDisable"); + if (gatt_svc == MESH_GATT_NONE) { BT_WARN("%s, Already", __func__); return -EALREADY; @@ -1227,7 +1316,7 @@ void bt_mesh_proxy_server_addr_add(struct net_buf_simple *buf, uint16_t addr) struct bt_mesh_proxy_client, buf); - BT_DBG("filter_type %u addr 0x%04x", client->filter_type, addr); + BT_DBG("ProxyServerAddrAdd, Type %u Addr 0x%04x", client->filter_type, addr); if (client->filter_type == SRV_WHITELIST) { filter_add(client, addr, true); @@ -1236,16 +1325,16 @@ void bt_mesh_proxy_server_addr_add(struct net_buf_simple *buf, uint16_t addr) } } -static bool client_filter_match(struct bt_mesh_proxy_client *client, - uint16_t addr) +static bool client_filter_match(struct bt_mesh_proxy_client *client, uint16_t addr) { int i; - BT_DBG("filter_type %u addr 0x%04x", client->filter_type, addr); + BT_DBG("ClientFilterMatch, Type %u Addr 0x%04x", client->filter_type, addr); if (client->filter_type == SRV_BLACKLIST) { for (i = 0; i < ARRAY_SIZE(client->filter); i++) { if (client->filter[i].addr == addr) { + BT_DBG("InBlackList"); return false; } } @@ -1254,12 +1343,14 @@ static bool client_filter_match(struct bt_mesh_proxy_client *client, } if (addr == BLE_MESH_ADDR_ALL_NODES) { + BT_DBG("AllNodes"); return true; } if (client->filter_type == SRV_WHITELIST) { for (i = 0; i < ARRAY_SIZE(client->filter); i++) { if (client->filter[i].addr == addr) { + BT_DBG("InWhiteList"); return true; } } @@ -1273,7 +1364,7 @@ bool bt_mesh_proxy_server_relay(struct net_buf_simple *buf, uint16_t dst) bool relayed = false; int i; - BT_DBG("%u bytes to dst 0x%04x", buf->len, dst); + BT_DBG("ProxyServerRelay, Len %u Dst 0x%04x", buf->len, dst); for (i = 0; i < ARRAY_SIZE(clients); i++) { struct bt_mesh_proxy_client *client = &clients[i]; @@ -1299,24 +1390,24 @@ bool bt_mesh_proxy_server_relay(struct net_buf_simple *buf, uint16_t dst) return relayed; } - #endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER */ static int proxy_send(struct bt_mesh_conn *conn, const void *data, uint16_t len) { - BT_DBG("%u bytes: %s", len, bt_hex(data, len)); + BT_DBG("ProxySend"); + BT_DBG("Len %u: %s", len, bt_hex(data, len)); #if CONFIG_BLE_MESH_GATT_PROXY_SERVER if (gatt_svc == MESH_GATT_PROXY) { return bt_mesh_gatts_notify(conn, &proxy_attrs[4], data, len); } -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER */ #if CONFIG_BLE_MESH_PB_GATT if (gatt_svc == MESH_GATT_PROV) { return bt_mesh_gatts_notify(conn, &prov_attrs[4], data, len); } -#endif +#endif /* CONFIG_BLE_MESH_PB_GATT */ return 0; } @@ -1326,11 +1417,15 @@ int bt_mesh_proxy_server_segment_send(struct bt_mesh_conn *conn, uint8_t type, { uint16_t mtu = 0U; - BT_DBG("conn %p type 0x%02x len %u: %s", conn, type, msg->len, - bt_hex(msg->data, msg->len)); + BT_DBG("ProxyServerSegSend"); + BT_DBG("ConnHandle 0x%04x Type %u", conn->handle, type); + BT_DBG("Len %u: %s", msg->len, bt_hex(msg->data, msg->len)); /* ATT_MTU - OpCode (1 byte) - Handle (2 bytes) */ mtu = bt_mesh_gatt_get_mtu(conn) - 3; + + BT_DBG("MTU %u", mtu); + if (mtu > msg->len) { net_buf_simple_push_u8(msg, BLE_MESH_PROXY_PDU_HDR(BLE_MESH_PROXY_SAR_COMP, type)); return proxy_send(conn, msg->data, msg->len); @@ -1360,6 +1455,8 @@ int bt_mesh_proxy_server_send(struct bt_mesh_conn *conn, uint8_t type, { struct bt_mesh_proxy_client *client = find_client(conn); + BT_DBG("ProxyServerSend, Type 0x%02x", type); + if (!client) { BT_ERR("No Proxy Client found"); return -ENOTCONN; @@ -1381,10 +1478,9 @@ static const struct bt_mesh_adv_data prov_ad[] = { BLE_MESH_ADV_DATA_BYTES(BLE_MESH_DATA_UUID16_ALL, 0x27, 0x18), BLE_MESH_ADV_DATA(BLE_MESH_DATA_SVC_DATA16, prov_svc_data, sizeof(prov_svc_data)), }; -#endif /* PB_GATT */ +#endif /* CONFIG_BLE_MESH_PB_GATT */ #if CONFIG_BLE_MESH_GATT_PROXY_SERVER - #define NET_ID_LEN 11 #define NODE_ID_LEN 19 #define PRIVATE_NET_ID_LEN 19 @@ -1432,6 +1528,9 @@ static size_t gatt_proxy_adv_create(struct bt_mesh_adv_data *proxy_sd) /* One octet for Length, and another octet for AD type */ size_t sd_space = 29; + BT_DBG("GattProxyAdvCreate"); + BT_DBG("Name %u: %s", name_len, name); + if (name_len > sd_space) { proxy_sd->type = BLE_MESH_DATA_NAME_SHORTENED; proxy_sd->data_len = sd_space; @@ -1452,6 +1551,8 @@ static int node_id_adv(struct bt_mesh_subnet *sub) uint8_t tmp[16] = {0}; int err = 0; + BT_DBG("NodeIDAdv, NetIdx 0x%04x", sub->net_idx); + proxy_svc_data[2] = BLE_MESH_PROXY_ADV_NODE_ID; err = bt_mesh_rand(proxy_svc_data + 11, 8); @@ -1489,10 +1590,10 @@ static int net_id_adv(struct bt_mesh_subnet *sub) size_t proxy_sd_len = 0U; int err = 0; - proxy_svc_data[2] = BLE_MESH_PROXY_ADV_NET_ID; + BT_DBG("NetIDAdv, NetIdx 0x%04x", sub->net_idx); + BT_DBG("NetId %s", bt_hex(sub->keys[sub->kr_flag].net_id, 8)); - BT_DBG("Advertising with NetId %s", - bt_hex(sub->keys[sub->kr_flag].net_id, 8)); + proxy_svc_data[2] = BLE_MESH_PROXY_ADV_NET_ID; memcpy(proxy_svc_data + 3, sub->keys[sub->kr_flag].net_id, 8); proxy_sd_len = gatt_proxy_adv_create(&proxy_sd); @@ -1512,11 +1613,15 @@ static int net_id_adv(struct bt_mesh_subnet *sub) #if CONFIG_BLE_MESH_PRB_SRV void bt_mesh_proxy_server_update_net_id_rand(void) { + BT_DBG("ProxyServerUpdateNetIDRand"); + k_delayed_work_submit(&rand_upd_timer, RAND_UPDATE_INTERVAL); } void bt_mesh_proxy_server_update_net_id_rand_stop(void) { + BT_DBG("ProxyServerUpdateNetIDRandStop"); + k_delayed_work_cancel(&rand_upd_timer); } @@ -1524,6 +1629,8 @@ static void random_update_timeout(struct k_work *work) { int err = 0; + BT_DBG("RandomUpdateTimeout"); + err = bt_mesh_rand(net_id_random, 8); if (err) { BT_ERR("Generate random value failed"); @@ -1540,6 +1647,8 @@ static int private_node_id_adv(struct bt_mesh_subnet *sub) uint8_t tmp[16] = {0}; int err = 0; + BT_DBG("PrivateNodeIDAdv, NetIdx 0x%04x", sub->net_idx); + proxy_svc_data[2] = BLE_MESH_PROXY_ADV_PRIVATE_NODE_ID; err = bt_mesh_rand(proxy_svc_data + 11, 8); @@ -1560,8 +1669,13 @@ static int private_node_id_adv(struct bt_mesh_subnet *sub) memcpy(proxy_svc_data + 3, tmp + 8, 8); proxy_sd_len = gatt_proxy_adv_create(&proxy_sd); +#if CONFIG_BLE_MESH_USE_BLE_50 + err = bt_le_ext_adv_start(proxy_adv_inst, &fast_adv_param, private_node_id_ad, + ARRAY_SIZE(private_node_id_ad), &proxy_sd, proxy_sd_len); +#else /* CONFIG_BLE_MESH_USE_BLE_50 */ err = bt_le_adv_start(&fast_adv_param, private_node_id_ad, ARRAY_SIZE(private_node_id_ad), &proxy_sd, proxy_sd_len); +#endif /* CONFIG_BLE_MESH_USE_BLE_50 */ if (err) { BT_WARN("Failed to advertise with Private Node ID (err %d)", err); return err; @@ -1573,8 +1687,7 @@ static int private_node_id_adv(struct bt_mesh_subnet *sub) } #endif /* CONFIG_BLE_MESH_PRB_SRV */ -#if (CONFIG_BLE_MESH_PRB_SRV || \ - CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX) +#if (CONFIG_BLE_MESH_PRB_SRV || CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX) static int private_net_id_adv(struct bt_mesh_subnet *sub) { struct bt_mesh_adv_data proxy_sd = {0}; @@ -1582,6 +1695,8 @@ static int private_net_id_adv(struct bt_mesh_subnet *sub) uint8_t tmp[16] = {0}; int err = 0; + BT_DBG("PrivateNetIDAdv, NetIdx 0x%04x", sub->net_idx); + proxy_svc_data[2] = BLE_MESH_PROXY_ADV_PRIVATE_NET_ID; /* TODO: @@ -1604,8 +1719,13 @@ static int private_net_id_adv(struct bt_mesh_subnet *sub) proxy_sd_len = gatt_proxy_adv_create(&proxy_sd); +#if CONFIG_BLE_MESH_USE_BLE_50 + err = bt_le_ext_adv_start(proxy_adv_inst, &fast_adv_param, private_net_id_ad, + ARRAY_SIZE(private_net_id_ad), &proxy_sd, proxy_sd_len); +#else /* CONFIG_BLE_MESH_USE_BLE_50 */ err = bt_le_adv_start(&fast_adv_param, private_net_id_ad, ARRAY_SIZE(private_net_id_ad), &proxy_sd, proxy_sd_len); +#endif /* CONFIG_BLE_MESH_USE_BLE_50 */ if (err) { BT_WARN("Failed to advertise with Private Net ID (err %d)", err); return err; @@ -1615,11 +1735,12 @@ static int private_net_id_adv(struct bt_mesh_subnet *sub) return 0; } -#endif /* (CONFIG_BLE_MESH_PRB_SRV || \ - CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX) */ +#endif /* (CONFIG_BLE_MESH_PRB_SRV || CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX) */ static bool advertise_subnet(struct bt_mesh_subnet *sub) { + BT_DBG("AdvSubnet, NetIdx 0x%04x", sub->net_idx); + if (sub->net_idx == BLE_MESH_KEY_UNUSED) { return false; } @@ -1629,7 +1750,7 @@ static bool advertise_subnet(struct bt_mesh_subnet *sub) #if CONFIG_BLE_MESH_PRB_SRV || sub->private_node_id == BLE_MESH_PRIVATE_NODE_IDENTITY_RUNNING || bt_mesh_private_gatt_proxy_state_get() == BLE_MESH_PRIVATE_GATT_PROXY_ENABLED -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ ); } @@ -1638,10 +1759,13 @@ static struct bt_mesh_subnet *next_sub(void) struct bt_mesh_subnet *sub = NULL; int i; + BT_DBG("NextSub"); + for (i = next_idx; i < ARRAY_SIZE(bt_mesh.sub); i++) { sub = &bt_mesh.sub[i]; if (advertise_subnet(sub)) { next_idx = (i + 1) % ARRAY_SIZE(bt_mesh.sub); + BT_DBG("NextIdx %d", next_idx); return sub; } } @@ -1653,6 +1777,7 @@ static struct bt_mesh_subnet *next_sub(void) sub = &bt_mesh.sub[i]; if (advertise_subnet(sub)) { next_idx = (i + 1) % ARRAY_SIZE(bt_mesh.sub); + BT_DBG("NextIdx %d", next_idx); return sub; } } @@ -1672,6 +1797,8 @@ static int sub_count(void) } } + BT_DBG("SubCount %ld", count); + return count; } @@ -1681,6 +1808,8 @@ static int32_t gatt_proxy_advertise(struct bt_mesh_subnet *sub) int subnet_count = 0; uint32_t active = 0U; + BT_DBG("GattProxyAdvertise"); + if (conn_count == BLE_MESH_MAX_CONN) { BT_WARN("Connectable advertising deferred (max connections %d)", conn_count); return remaining; @@ -1691,6 +1820,8 @@ static int32_t gatt_proxy_advertise(struct bt_mesh_subnet *sub) return remaining; } + BT_DBG("NetIdx 0x%04x NodeID %u", sub->net_idx, sub->node_id); + if (sub->node_id == BLE_MESH_NODE_IDENTITY_RUNNING) { active = k_uptime_get_32() - sub->node_id_start; @@ -1703,6 +1834,7 @@ static int32_t gatt_proxy_advertise(struct bt_mesh_subnet *sub) BT_DBG("Node ID stopped"); } } + #if CONFIG_BLE_MESH_PRB_SRV else if (sub->private_node_id == BLE_MESH_PRIVATE_NODE_IDENTITY_RUNNING) { active = k_uptime_get_32() - sub->node_id_start; @@ -1721,7 +1853,7 @@ static int32_t gatt_proxy_advertise(struct bt_mesh_subnet *sub) if (sub->node_id == BLE_MESH_NODE_IDENTITY_STOPPED #if CONFIG_BLE_MESH_PRB_SRV && sub->private_node_id == BLE_MESH_PRIVATE_NODE_IDENTITY_STOPPED -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ ) { if (bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED) { net_id_adv(sub); @@ -1730,11 +1862,10 @@ static int32_t gatt_proxy_advertise(struct bt_mesh_subnet *sub) else if (bt_mesh_private_gatt_proxy_state_get() == BLE_MESH_PRIVATE_GATT_PROXY_ENABLED) { private_net_id_adv(sub); } -#endif +#endif /* CONFIG_BLE_MESH_PRB_SRV */ } subnet_count = sub_count(); - BT_DBG("sub_count %u", subnet_count); if (subnet_count > 1) { int32_t max_timeout = 0; @@ -1747,16 +1878,18 @@ static int32_t gatt_proxy_advertise(struct bt_mesh_subnet *sub) max_timeout = NODE_ID_TIMEOUT / MAX(subnet_count, 6); max_timeout = MAX(max_timeout, K_SECONDS(1)); + BT_DBG("Remaining %d MaxTimeout %d", remaining, max_timeout); + if (remaining > max_timeout || remaining < 0) { remaining = max_timeout; } } - BT_DBG("Advertising %d ms for net_idx 0x%04x", remaining, sub->net_idx); + BT_DBG("Remaining %d NetIdx 0x%04x", remaining, sub->net_idx); return remaining; } -#endif /* GATT_PROXY */ +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER */ #if CONFIG_BLE_MESH_PB_GATT static size_t gatt_prov_adv_create(struct bt_mesh_adv_data prov_sd[2]) @@ -1766,6 +1899,8 @@ static size_t gatt_prov_adv_create(struct bt_mesh_adv_data prov_sd[2]) size_t prov_sd_len = 0U; size_t sd_space = 31U; + BT_DBG("GattProvAdvCreate"); + if (bt_mesh_prov_get() == NULL) { BT_ERR("No provisioning context provided"); return 0; @@ -1816,33 +1951,43 @@ static int32_t solic_adv_private_net_id(void) struct bt_mesh_subnet *sub = NULL; int32_t remaining = 0; + BT_DBG("SolicAdvPrivateNetID"); + remaining = bt_mesh_proxy_server_get_solic_adv_remaining(); if (remaining == 0) { + BT_DBG("RemainingZero"); return 0; } net_idx = bt_mesh_proxy_server_get_solic_adv_net_idx(); if (net_idx == BLE_MESH_KEY_UNUSED) { + BT_DBG("UnusedNetIdx"); return 0; } sub = bt_mesh_subnet_get(net_idx); if (sub == NULL) { + BT_DBG("NoSub"); return 0; } private_net_id_adv(sub); + return remaining; } #endif /* CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX */ int32_t bt_mesh_proxy_server_adv_start(void) { + BT_DBG("ProxyServerAdvStart"); if (gatt_svc == MESH_GATT_NONE) { + BT_DBG("GattSvcNone"); return K_FOREVER; } #if CONFIG_BLE_MESH_PB_GATT + BT_DBG("ProvFastAdv %u", prov_fast_adv); + if (prov_fast_adv) { prov_start_time = k_uptime_get_32(); } @@ -1852,6 +1997,8 @@ int32_t bt_mesh_proxy_server_adv_start(void) struct bt_mesh_adv_data prov_sd[2]; size_t prov_sd_len; + BT_DBG("NotProvisioned"); + if (k_uptime_get_32() - prov_start_time < K_SECONDS(60)) { param = &fast_adv_param; } else { @@ -1871,7 +2018,7 @@ int32_t bt_mesh_proxy_server_adv_start(void) } } } -#endif /* PB_GATT */ +#endif /* CONFIG_BLE_MESH_PB_GATT */ #if CONFIG_BLE_MESH_GATT_PROXY_SERVER if (bt_mesh_is_provisioned()) { @@ -1899,7 +2046,7 @@ void bt_mesh_proxy_server_adv_stop(void) { int err = 0; - BT_DBG("adv_enabled %u", proxy_adv_enabled); + BT_DBG("ProxyServerAdvStop, Enabled %u", proxy_adv_enabled); if (!proxy_adv_enabled) { return; @@ -1922,13 +2069,15 @@ int bt_mesh_proxy_server_init(void) { int i; + BT_DBG("ProxyServerInit"); + #if CONFIG_BLE_MESH_GATT_PROXY_SERVER bt_mesh_gatts_service_register(&proxy_svc); -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER */ #if CONFIG_BLE_MESH_PB_GATT bt_mesh_gatts_service_register(&prov_svc); -#endif +#endif /* CONFIG_BLE_MESH_PB_GATT */ /* Initialize the client receive buffers */ for (i = 0; i < ARRAY_SIZE(clients); i++) { @@ -1936,9 +2085,10 @@ int bt_mesh_proxy_server_init(void) client->buf.size = BLE_MESH_PROXY_BUF_SIZE; client->buf.__buf = client_buf_data + (i * BLE_MESH_PROXY_BUF_SIZE); -#if defined(CONFIG_BLE_MESH_GATT_PROXY_SERVER) + +#if CONFIG_BLE_MESH_GATT_PROXY_SERVER k_delayed_work_init(&client->send_beacons, proxy_send_beacons); -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER */ k_delayed_work_init(&client->sar_timer, proxy_sar_timeout); } @@ -1947,11 +2097,12 @@ int bt_mesh_proxy_server_init(void) BT_ERR("Failed to create a random update timer"); return -EIO; } -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER && CONFIG_BLE_MESH_PRB_SRV */ bt_mesh_gatts_conn_cb_register(&conn_callbacks); strncpy(device_name, "ESP-BLE-MESH", DEVICE_NAME_SIZE); + return bt_mesh_gatts_set_local_device_name(device_name); } @@ -1960,30 +2111,34 @@ int bt_mesh_proxy_server_deinit(void) { int i; + BT_DBG("ProxyServerDeinit"); + proxy_adv_enabled = false; gatt_svc = MESH_GATT_NONE; #if CONFIG_BLE_MESH_GATT_PROXY_SERVER bt_mesh_gatts_service_deregister(&proxy_svc); next_idx = 0; -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER */ #if CONFIG_BLE_MESH_PB_GATT bt_mesh_gatts_service_deregister(&prov_svc); -#endif +#endif /* CONFIG_BLE_MESH_PB_GATT */ for (i = 0; i < ARRAY_SIZE(clients); i++) { struct bt_mesh_proxy_client *client = &clients[i]; -#if defined(CONFIG_BLE_MESH_GATT_PROXY_SERVER) + +#if CONFIG_BLE_MESH_GATT_PROXY_SERVER k_delayed_work_free(&client->send_beacons); -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER */ k_delayed_work_free(&client->sar_timer); + memset(client, 0, sizeof(struct bt_mesh_proxy_client)); } #if CONFIG_BLE_MESH_GATT_PROXY_SERVER && CONFIG_BLE_MESH_PRB_SRV k_delayed_work_free(&rand_upd_timer); -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER && CONFIG_BLE_MESH_PRB_SRV */ memset(client_buf_data, 0, sizeof(client_buf_data)); memset(device_name, 0, sizeof(device_name)); diff --git a/components/bt/esp_ble_mesh/core/proxy_server.h b/components/bt/esp_ble_mesh/core/proxy_server.h index b98728910de1..c1994a56d420 100644 --- a/components/bt/esp_ble_mesh/core/proxy_server.h +++ b/components/bt/esp_ble_mesh/core/proxy_server.h @@ -57,7 +57,7 @@ struct bt_mesh_proxy_client { #if CONFIG_BLE_MESH_PROXY_PRIVACY uint8_t proxy_privacy; -#endif +#endif /* CONFIG_BLE_MESH_PROXY_PRIVACY */ #endif /* CONFIG_BLE_MESH_GATT_PROXY_SERVER */ struct k_delayed_work sar_timer; diff --git a/components/bt/esp_ble_mesh/core/rpl.c b/components/bt/esp_ble_mesh/core/rpl.c index 4e3e4c91cbce..c6ab282472d8 100644 --- a/components/bt/esp_ble_mesh/core/rpl.c +++ b/components/bt/esp_ble_mesh/core/rpl.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,6 +17,9 @@ void bt_mesh_update_rpl(struct bt_mesh_rpl *rpl, struct bt_mesh_net_rx *rx) { + BT_DBG("UpdateRPL, Src 0x%04x Seq 0x%06x OldIV %u", + rx->ctx.addr, rx->seq, rx->old_iv); + rpl->src = rx->ctx.addr; rpl->seq = rx->seq; rpl->old_iv = rx->old_iv; @@ -33,9 +36,16 @@ void bt_mesh_update_rpl(struct bt_mesh_rpl *rpl, struct bt_mesh_net_rx *rx) */ static bool rpl_check_and_store(struct bt_mesh_net_rx *rx, struct bt_mesh_rpl **match) { + BT_DBG("%s, Src 0x%04x Seq %lu OldIV %u", + match ? "RPLOnlyCheck" : "RPLCheckAndStore", + rx->ctx.addr, rx->seq, rx->old_iv); + for (size_t i = 0; i < ARRAY_SIZE(bt_mesh.rpl); i++) { struct bt_mesh_rpl *rpl = &bt_mesh.rpl[i]; + BT_DBG("RPL%u, Src 0x%04x Seq %lu OldIV %u", + i, rpl->src, rpl->seq, rpl->old_iv); + /* Empty slot */ if (rpl->src == BLE_MESH_ADDR_UNASSIGNED) { if (match) { @@ -50,6 +60,7 @@ static bool rpl_check_and_store(struct bt_mesh_net_rx *rx, struct bt_mesh_rpl ** /* Existing slot for given address */ if (rpl->src == rx->ctx.addr) { if (rx->old_iv && !rpl->old_iv) { + BT_DBG("DueToOldIV"); return true; } @@ -66,25 +77,30 @@ static bool rpl_check_and_store(struct bt_mesh_net_rx *rx, struct bt_mesh_rpl ** #if CONFIG_BLE_MESH_NOT_RELAY_REPLAY_MSG rx->replay_msg = 1; -#endif +#endif /* CONFIG_BLE_MESH_NOT_RELAY_REPLAY_MSG */ + BT_DBG("DueToSeq"); return true; } } - BT_ERR("RPL is full!"); + BT_ERR("RPLFull"); return true; } bool bt_mesh_rpl_check(struct bt_mesh_net_rx *rx, struct bt_mesh_rpl **match) { + BT_DBG("RPLCheck"); + /* Don't bother checking messages from ourselves */ if (rx->net_if == BLE_MESH_NET_IF_LOCAL) { + BT_DBG("LocalNetIf"); return false; } /* The RPL is used only for the local node */ if (!rx->local_match) { + BT_DBG("LocalNotMatch"); return false; } @@ -96,9 +112,14 @@ void bt_mesh_rpl_update(void) /* Discard "old old" IV Index entries from RPL and flag * any other ones (which are valid) as old. */ + BT_DBG("RPLUpdate"); + for (size_t i = 0; i < ARRAY_SIZE(bt_mesh.rpl); i++) { struct bt_mesh_rpl *rpl = &bt_mesh.rpl[i]; + BT_DBG("RPL%u, Src 0x%04x Seq %lu OldIV %u", + i, rpl->src, rpl->seq, rpl->old_iv); + if (rpl->src) { if (rpl->old_iv) { (void)memset(rpl, 0, sizeof(*rpl)); @@ -115,6 +136,8 @@ void bt_mesh_rpl_update(void) void bt_mesh_rpl_reset_single(uint16_t src, bool erase) { + BT_DBG("RPLResetSingle, Src 0x%04x Erase %u", src, erase); + if (!BLE_MESH_ADDR_IS_UNICAST(src)) { return; } @@ -132,6 +155,8 @@ void bt_mesh_rpl_reset_single(uint16_t src, bool erase) void bt_mesh_rpl_reset(bool erase) { + BT_DBG("RPLReset, Erase %u", erase); + (void)memset(bt_mesh.rpl, 0, sizeof(bt_mesh.rpl)); if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS) && erase) { diff --git a/components/bt/esp_ble_mesh/core/scan.c b/components/bt/esp_ble_mesh/core/scan.c index 4ddd2418d3cb..c709d9eaecd4 100644 --- a/components/bt/esp_ble_mesh/core/scan.c +++ b/components/bt/esp_ble_mesh/core/scan.c @@ -29,7 +29,7 @@ #if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" -#endif +#endif /* CONFIG_BLE_MESH_V11_SUPPORT */ /* Scan Window and Interval are equal for continuous scanning */ #define SCAN_INTERVAL 0x20 @@ -60,6 +60,11 @@ int bt_mesh_unprov_dev_fifo_dequeue(uint8_t *uuid, uint8_t *addr) { uint8_t idx = 0; + BT_DBG("UnprovDevFifoDequeue, PairNum %u StartIdx %u EndIdx %u", + unprov_dev_info_fifo.pair_num, + unprov_dev_info_fifo.start_idx, + unprov_dev_info_fifo.end_idx); + if (unprov_dev_info_fifo.pair_num == 0) { return 0; } @@ -84,9 +89,11 @@ int bt_mesh_unprov_dev_fifo_dequeue(uint8_t *uuid, uint8_t *addr) int bt_mesh_unprov_dev_info_query(uint8_t uuid[16], uint8_t addr[6], uint8_t *adv_type, uint8_t query_type) { + uint8_t pair_num = unprov_dev_info_fifo.pair_num; uint8_t idx = 0; uint8_t cnt = 0; - uint8_t pair_num = unprov_dev_info_fifo.pair_num; + + BT_DBG("UnprovDevInfoQuery, QueryType 0x%02x PairNum %u", query_type, pair_num); if (uuid == NULL && addr == NULL) { BT_WARN("No available information to query"); @@ -95,42 +102,49 @@ int bt_mesh_unprov_dev_info_query(uint8_t uuid[16], uint8_t addr[6], while (cnt < pair_num) { idx = (cnt + unprov_dev_info_fifo.start_idx) % BLE_MESH_STORE_UNPROV_INFO_MAX_NUM; + + BT_DBG("Count %u StartIdx %u Idx %u", cnt, unprov_dev_info_fifo.start_idx, idx); + if (query_type & BLE_MESH_STORE_UNPROV_INFO_QUERY_TYPE_UUID) { if (!memcmp(unprov_dev_info_fifo.info[idx].addr, addr, 6)) { if (query_type & BLE_MESH_STORE_UNPROV_INFO_QUERY_TYPE_EXISTS) { return 0; - } else { - memcpy(uuid, unprov_dev_info_fifo.info[idx].uuid, 16); - *adv_type = unprov_dev_info_fifo.info[idx].adv_type; - break; } + + memcpy(uuid, unprov_dev_info_fifo.info[idx].uuid, 16); + *adv_type = unprov_dev_info_fifo.info[idx].adv_type; + break; } } else { if (!memcmp(unprov_dev_info_fifo.info[idx].uuid, uuid, 16)) { if (query_type & BLE_MESH_STORE_UNPROV_INFO_QUERY_TYPE_EXISTS) { return 0; - } else { - memcpy(addr, unprov_dev_info_fifo.info[idx].addr, 6); - *adv_type = unprov_dev_info_fifo.info[idx].adv_type; - break; } + + memcpy(addr, unprov_dev_info_fifo.info[idx].addr, 6); + *adv_type = unprov_dev_info_fifo.info[idx].adv_type; + break; } } + cnt++; } if (cnt == pair_num) { + BT_DBG("Count == PairNum"); return -1; } return 0; - } int bt_mesh_unprov_dev_fifo_enqueue(uint8_t uuid[16], const uint8_t addr[6], uint8_t adv_type) { uint8_t idx = 0; + BT_DBG("UnprovDevFifoEnqueue, EndIdx %u PairNum %u", + unprov_dev_info_fifo.end_idx, unprov_dev_info_fifo.pair_num); + if (uuid == NULL || addr == NULL) { BT_ERR("Invalid argument %s", __func__); return -EINVAL; @@ -154,6 +168,9 @@ int bt_mesh_unprov_dev_fifo_enqueue(uint8_t uuid[16], const uint8_t addr[6], uin idx = (idx + 1) % BLE_MESH_STORE_UNPROV_INFO_MAX_NUM; unprov_dev_info_fifo.end_idx = idx; unprov_dev_info_fifo.pair_num++; + + BT_DBG("EndIdx %u PairNum %u", unprov_dev_info_fifo.end_idx, unprov_dev_info_fifo.pair_num); + return 0; } @@ -164,19 +181,22 @@ const bt_mesh_addr_t *bt_mesh_get_unprov_dev_addr(void) uint8_t bt_mesh_get_adv_type(void) { + BT_DBG("CurrentAdvType %u", current_adv_type); + return current_adv_type; } - #endif /* (CONFIG_BLE_MESH_PROVISIONER || CONFIG_BLE_MESH_RPR_SRV) */ #if (CONFIG_BLE_MESH_PROVISIONER && CONFIG_BLE_MESH_PB_GATT) || \ CONFIG_BLE_MESH_GATT_PROXY_CLIENT || \ CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX || \ - (CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_PB_GATT) + (CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_PB_GATT) static bool adv_flags_valid(struct net_buf_simple *buf) { uint8_t flags = 0U; + BT_DBG("IsAdvFlagsValid"); + if (buf->len != 1U) { BT_DBG("Unexpected adv flags length %d", buf->len); return false; @@ -184,7 +204,7 @@ static bool adv_flags_valid(struct net_buf_simple *buf) flags = net_buf_simple_pull_u8(buf); - BT_DBG("Received adv pkt with flags: 0x%02x", flags); + BT_DBG("Flags 0x%02x", flags); /* Flags context will not be checked currently */ ARG_UNUSED(flags); @@ -194,6 +214,8 @@ static bool adv_flags_valid(struct net_buf_simple *buf) static bool adv_service_uuid_valid(struct net_buf_simple *buf, uint16_t *uuid) { + BT_DBG("IsAdvServiceUUIDValid"); + if (buf->len != 2U) { BT_DBG("Length not match mesh service uuid"); return false; @@ -201,40 +223,42 @@ static bool adv_service_uuid_valid(struct net_buf_simple *buf, uint16_t *uuid) *uuid = net_buf_simple_pull_le16(buf); - BT_DBG("Received adv pkt with service UUID: %d", *uuid); + BT_DBG("UUID 0x%04x", *uuid); if (*uuid != BLE_MESH_UUID_MESH_PROV_VAL && *uuid != BLE_MESH_UUID_MESH_PROXY_VAL && *uuid != BLE_MESH_UUID_MESH_PROXY_SOLIC_VAL) { + BT_DBG("UnexpectMeshUUID"); return false; } - /** - * @brief In remote provisioning. - * A Node could handle the unprovisioned beacon. + /* In remote provisioning, Node could handle unprovisioned device beacon. * CASE: MESH/SR/RPR/SCN/BV-01-C - */ + */ #if CONFIG_BLE_MESH_RPR_SRV if (*uuid == BLE_MESH_UUID_MESH_PROV_VAL && !IS_ENABLED(CONFIG_BLE_MESH_PB_GATT)) { + BT_DBG("IgnorePBGattUUID"); return false; } -#else +#else /* CONFIG_BLE_MESH_RPR_SRV */ if (*uuid == BLE_MESH_UUID_MESH_PROV_VAL && (bt_mesh_is_provisioner_en() == false || !IS_ENABLED(CONFIG_BLE_MESH_PB_GATT))) { + BT_DBG("IgnorePBGattUUID"); return false; } -#endif - +#endif /* CONFIG_BLE_MESH_RPR_SRV */ if (*uuid == BLE_MESH_UUID_MESH_PROXY_VAL && !IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_CLIENT)) { + BT_DBG("IgnoreProxyUUID"); return false; } if (*uuid == BLE_MESH_UUID_MESH_PROXY_SOLIC_VAL && !IS_ENABLED(CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX)) { + BT_DBG("IgnoreProxySolicUUID"); return false; } @@ -247,6 +271,8 @@ static void handle_adv_service_data(struct net_buf_simple *buf, { uint16_t type = 0U; + BT_DBG("HandleAdvServiceData, UUID 0x%04x", uuid); + if (!buf || !addr) { BT_ERR("%s, Invalid parameter", __func__); return; @@ -254,7 +280,7 @@ static void handle_adv_service_data(struct net_buf_simple *buf, type = net_buf_simple_pull_le16(buf); if (type != uuid) { - BT_DBG("Invalid Mesh Service Data UUID 0x%04x", type); + BT_DBG("UnexpectMeshUUID 0x%04x", type); return; } @@ -276,8 +302,13 @@ static void handle_adv_service_data(struct net_buf_simple *buf, #if CONFIG_BLE_MESH_RPR_SRV if (bt_mesh_is_provisioned()) { - const bt_mesh_addr_t *addr = bt_mesh_get_unprov_dev_addr(); + const bt_mesh_addr_t *addr = NULL; + + addr = bt_mesh_get_unprov_dev_addr(); + assert(addr); + bt_mesh_unprov_dev_fifo_enqueue(buf->data, addr->val, bt_mesh_get_adv_type()); + bt_mesh_rpr_srv_unprov_beacon_recv(buf, bt_mesh_get_adv_type(), addr, rssi); } #endif /* CONFIG_BLE_MESH_RPR_SRV */ @@ -300,7 +331,8 @@ static void handle_adv_service_data(struct net_buf_simple *buf, BT_DBG("Start to handle Mesh Proxy Service Data"); bt_mesh_proxy_client_gatt_adv_recv(buf, addr, rssi); break; -#endif +#endif /* CONFIG_BLE_MESH_GATT_PROXY_CLIENT */ + #if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX case BLE_MESH_UUID_MESH_PROXY_SOLIC_VAL: if (buf->len != (1 + BLE_MESH_NET_HDR_LEN + 8)) { @@ -311,7 +343,8 @@ static void handle_adv_service_data(struct net_buf_simple *buf, BT_DBG("Start to handle Mesh Proxy Solic Service Data"); bt_mesh_proxy_server_solic_recv(buf, addr, rssi); break; -#endif +#endif /* CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX */ + default: break; } @@ -326,6 +359,8 @@ static bool ble_scan_en; int bt_mesh_start_ble_scan(struct bt_mesh_ble_scan_param *param) { + BT_DBG("StartBLEScan"); + if (ble_scan_en == true) { BT_WARN("%s, Already", __func__); return -EALREADY; @@ -338,6 +373,8 @@ int bt_mesh_start_ble_scan(struct bt_mesh_ble_scan_param *param) int bt_mesh_stop_ble_scan(void) { + BT_DBG("StopBLEScan"); + if (ble_scan_en == false) { BT_WARN("%s, Already", __func__); return -EALREADY; @@ -353,6 +390,7 @@ static void inline callback_ble_adv_pkt(const bt_mesh_addr_t *addr, uint16_t length, int8_t rssi) { if (ble_scan_en) { + BT_DBG("CallbackBLEAdvPkt, AdvType 0x%02x Len %u", adv_type, length); bt_mesh_ble_scan_cb_evt_to_btc(addr, adv_type, data, length, rssi); } } @@ -365,6 +403,8 @@ static bool rpr_ext_scan_handle_adv_pkt(const bt_mesh_addr_t *addr, struct net_buf_simple buf = {0}; bool rpr_adv = false; + BT_DBG("RPRExtScanHandleAdvPkt, Provisioned %u", bt_mesh_is_provisioned()); + if (bt_mesh_is_provisioned() == false) { return false; } @@ -382,15 +422,15 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr, uint8_t scan_rsp_len) { #if (CONFIG_BLE_MESH_PROVISIONER && CONFIG_BLE_MESH_PB_GATT) || \ - CONFIG_BLE_MESH_GATT_PROXY_CLIENT || \ + CONFIG_BLE_MESH_GATT_PROXY_CLIENT || \ CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX || \ - (CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_PB_GATT) + (CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_PB_GATT) uint16_t uuid = 0U; #endif #if (CONFIG_BLE_MESH_RPR_SRV || CONFIG_BLE_MESH_SUPPORT_BLE_SCAN) uint8_t *adv_data = buf->data; uint16_t adv_len = buf->len; -#endif +#endif /* (CONFIG_BLE_MESH_RPR_SRV || CONFIG_BLE_MESH_SUPPORT_BLE_SCAN) */ if (adv_type != BLE_MESH_ADV_NONCONN_IND && adv_type != BLE_MESH_ADV_IND) { #if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN @@ -399,7 +439,8 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr, return; } - BT_DBG("scan, len %u: %s", buf->len, bt_hex(buf->data, buf->len)); + BT_DBG("MeshScan"); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); #if (CONFIG_BLE_MESH_PROVISIONER || CONFIG_BLE_MESH_RPR_SRV) unprov_dev_addr = addr; @@ -411,6 +452,7 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr, uint8_t len, type; len = net_buf_simple_pull_u8(buf); + /* Check for early termination */ if (len == 0U) { #if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN @@ -420,7 +462,8 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr, } if (len > buf->len) { - BT_DBG("AD malformed"); + BT_DBG("MalformedAD"); + #if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN callback_ble_adv_pkt(addr, adv_type, adv_data, adv_len, rssi); #endif @@ -443,35 +486,42 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr, case BLE_MESH_DATA_MESH_MESSAGE: bt_mesh_net_recv(buf, rssi, BLE_MESH_NET_IF_ADV); break; + #if CONFIG_BLE_MESH_PB_ADV case BLE_MESH_DATA_MESH_PROV: if (IS_ENABLED(CONFIG_BLE_MESH_NODE) && bt_mesh_is_node()) { bt_mesh_pb_adv_recv(buf); } + if (IS_ENABLED(CONFIG_BLE_MESH_PROVISIONER) && bt_mesh_is_provisioner_en()) { bt_mesh_provisioner_pb_adv_recv(buf); } break; #endif /* CONFIG_BLE_MESH_PB_ADV */ + case BLE_MESH_DATA_MESH_BEACON: bt_mesh_beacon_recv(buf, rssi); break; + #if (CONFIG_BLE_MESH_PROVISIONER && CONFIG_BLE_MESH_PB_GATT) || \ CONFIG_BLE_MESH_GATT_PROXY_CLIENT || \ CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX || \ - (CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_PB_GATT) + (CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_PB_GATT) case BLE_MESH_DATA_FLAGS: if (!adv_flags_valid(buf)) { BT_DBG("Adv Flags mismatch, ignore this adv pkt"); + #if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN callback_ble_adv_pkt(addr, adv_type, adv_data, adv_len, rssi); #endif return; } break; + case BLE_MESH_DATA_UUID16_ALL: if (!adv_service_uuid_valid(buf, &uuid)) { BT_DBG("Adv Service UUID mismatch, ignore this adv pkt"); + #if CONFIG_BLE_MESH_RPR_SRV if (rpr_ext_scan_handle_adv_pkt(addr, adv_data, adv_len)) { /* If handled as extended scan report successfully, then not @@ -479,17 +529,23 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr, */ return; } -#endif +#endif /* CONFIG_BLE_MESH_RPR_SRV */ + #if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN callback_ble_adv_pkt(addr, adv_type, adv_data, adv_len, rssi); #endif return; } break; + case BLE_MESH_DATA_SVC_DATA16: handle_adv_service_data(buf, addr, uuid, rssi); break; -#endif +#endif /* (CONFIG_BLE_MESH_PROVISIONER && CONFIG_BLE_MESH_PB_GATT) || \ + CONFIG_BLE_MESH_GATT_PROXY_CLIENT || \ + CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX || \ + (CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_PB_GATT) */ + default: #if CONFIG_BLE_MESH_RPR_SRV if (rpr_ext_scan_handle_adv_pkt(addr, adv_data, adv_len)) { @@ -498,7 +554,8 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr, */ return; } -#endif +#endif /* CONFIG_BLE_MESH_RPR_SRV */ + #if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN callback_ble_adv_pkt(addr, adv_type, adv_data, adv_len, rssi); #endif @@ -538,9 +595,11 @@ int bt_mesh_scan_enable(void) .scan_fil_policy = BLE_MESH_SP_ADV_ALL, }; + BT_DBG("ScanEnable"); + err = bt_le_scan_start(&scan_param, bt_mesh_scan_cb); if (err && err != -EALREADY) { - BT_ERR("starting scan failed (err %d)", err); + BT_ERR("StartScanFailed, Err %d", err); return err; } @@ -551,9 +610,11 @@ int bt_mesh_scan_disable(void) { int err = 0; + BT_DBG("ScanDisable"); + err = bt_le_scan_stop(); if (err && err != -EALREADY) { - BT_ERR("stopping scan failed (err %d)", err); + BT_ERR("StopScanFailed, Err %d", err); return err; } @@ -563,23 +624,24 @@ int bt_mesh_scan_disable(void) #if CONFIG_BLE_MESH_TEST_USE_WHITE_LIST int bt_mesh_scan_with_wl_enable(void) { - int err = 0; - struct bt_mesh_scan_param scan_param = { .type = BLE_MESH_SCAN_PASSIVE, #if CONFIG_BLE_MESH_USE_DUPLICATE_SCAN .filter_dup = BLE_MESH_SCAN_FILTER_DUP_ENABLE, -#else +#else /* CONFIG_BLE_MESH_USE_DUPLICATE_SCAN */ .filter_dup = BLE_MESH_SCAN_FILTER_DUP_DISABLE, -#endif +#endif /* CONFIG_BLE_MESH_USE_DUPLICATE_SCAN */ .interval = SCAN_INTERVAL, .window = SCAN_WINDOW, .scan_fil_policy = BLE_MESH_SP_ADV_WL, }; + int err = 0; + + BT_DBG("ScanWithWLEnable"); err = bt_le_scan_start(&scan_param, bt_mesh_scan_cb); if (err && err != -EALREADY) { - BT_ERR("starting scan failed (err %d)", err); + BT_ERR("StartScanFailed, Err %d", err); return err; } diff --git a/components/bt/esp_ble_mesh/core/storage/settings.c b/components/bt/esp_ble_mesh/core/storage/settings.c index 40cf117f2e06..5aa4c3fee5c9 100644 --- a/components/bt/esp_ble_mesh/core/storage/settings.c +++ b/components/bt/esp_ble_mesh/core/storage/settings.c @@ -1,6 +1,6 @@ /* * SPDX-FileCopyrightText: 2018 Intel Corporation - * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -24,7 +24,7 @@ #if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" -#endif +#endif /* CONFIG_BLE_MESH_V11_SUPPORT */ /* BLE Mesh NVS Key and corresponding data struct. * Note: The length of nvs key must be <= 15. @@ -207,6 +207,8 @@ static int role_set(const char *name) bool exist = false; int err = 0; + BT_DBG("RoleSet, Name %s", name); + err = bt_mesh_load_core_settings(name, (uint8_t *)bt_mesh.flags, sizeof(bt_mesh.flags), &exist); if (err) { BT_ERR("Failed to load mesh device role"); @@ -219,9 +221,9 @@ static int role_set(const char *name) !IS_ENABLED(CONFIG_BLE_MESH_PROVISIONER)) { bt_mesh_atomic_set_bit(bt_mesh.flags, BLE_MESH_NODE); } -#else +#else /* CONFIG_BLE_MESH_SETTINGS_BACKWARD_COMPATIBILITY */ return 0; -#endif +#endif /* CONFIG_BLE_MESH_SETTINGS_BACKWARD_COMPATIBILITY */ } return 0; @@ -233,6 +235,8 @@ static int net_set(const char *name) bool exist = false; int err = 0; + BT_DBG("NetSet, Name %s", name); + err = bt_mesh_load_core_settings(name, (uint8_t *)&net, sizeof(net), &exist); if (err) { BT_ERR("Failed to load node net info"); @@ -259,6 +263,8 @@ static int dkca_set(const char *name) bool exist = false; int err = 0; + BT_DBG("DkcaSet, Name %s", name); + err = bt_mesh_load_core_settings(name, bt_mesh.dev_key_ca, sizeof(bt_mesh.dev_key_ca), &exist); if (err) { BT_ERR("Failed to load DevKey Candidate"); @@ -280,6 +286,8 @@ static int iv_set(const char *name) bool exist = false; int err = 0; + BT_DBG("IVSet, Name %s", name); + err = bt_mesh_load_core_settings(name, (uint8_t *)&iv, sizeof(iv), &exist); if (err) { BT_ERR("Failed to load iv_index"); @@ -297,7 +305,7 @@ static int iv_set(const char *name) bt_mesh.ivu_duration = iv.iv_duration; BT_INFO("Restored IV Index 0x%08x (IV Update Flag %u) duration %u hours", - iv.iv_index, iv.iv_update, iv.iv_duration); + iv.iv_index, iv.iv_update, iv.iv_duration); return 0; } @@ -308,6 +316,8 @@ static int seq_set(const char *name) bool exist = false; int err = 0; + BT_DBG("SeqSet, Name %s", name); + err = bt_mesh_load_core_settings(name, (uint8_t *)&seq, sizeof(seq), &exist); if (err) { BT_ERR("Failed to load sequence number"); @@ -329,7 +339,7 @@ static int seq_set(const char *name) bt_mesh.seq += (CONFIG_BLE_MESH_SEQ_STORE_RATE - (bt_mesh.seq % CONFIG_BLE_MESH_SEQ_STORE_RATE)); bt_mesh.seq--; -#endif +#endif /* CONFIG_BLE_MESH_SEQ_STORE_RATE > 0 */ BT_INFO("Restored Sequence Number 0x%06x", bt_mesh.seq); @@ -340,6 +350,8 @@ static struct bt_mesh_rpl *rpl_find(uint16_t src) { int i; + BT_DBG("RPLFind, Src 0x%04x", src); + for (i = 0; i < ARRAY_SIZE(bt_mesh.rpl); i++) { if (bt_mesh.rpl[i].src == src) { return &bt_mesh.rpl[i]; @@ -353,6 +365,8 @@ static struct bt_mesh_rpl *rpl_alloc(uint16_t src) { int i; + BT_DBG("RPLAlloc, Src 0x%04x", src); + for (i = 0; i < ARRAY_SIZE(bt_mesh.rpl); i++) { if (bt_mesh.rpl[i].src == BLE_MESH_ADDR_UNASSIGNED) { bt_mesh.rpl[i].src = src; @@ -374,6 +388,8 @@ static int rpl_set(const char *name) int err = 0; int i; + BT_DBG("RPLSet, Name %s", name); + buf = bt_mesh_get_core_settings_item(name); if (!buf) { return 0; @@ -427,6 +443,8 @@ static struct bt_mesh_subnet *subnet_exist(uint16_t net_idx) { int i; + BT_DBG("SubnetExist, NetIdx 0x%04x", net_idx); + for (i = 0; i < ARRAY_SIZE(bt_mesh.sub); i++) { if (bt_mesh.sub[i].net_idx == net_idx) { return &bt_mesh.sub[i]; @@ -440,6 +458,8 @@ static struct bt_mesh_subnet *subnet_alloc(uint16_t net_idx) { int i; + BT_DBG("SubnetAlloc, NetIdx 0x%04x", net_idx); + for (i = 0; i < ARRAY_SIZE(bt_mesh.sub); i++) { if (bt_mesh.sub[i].net_idx == BLE_MESH_KEY_UNUSED) { bt_mesh.sub[i].net_idx = net_idx; @@ -454,6 +474,8 @@ static struct bt_mesh_app_key *appkey_exist(uint16_t app_idx) { int i; + BT_DBG("AppKeyExist, AppIdx 0x%04x", app_idx); + for (i = 0; i < ARRAY_SIZE(bt_mesh.app_keys); i++) { if (bt_mesh.app_keys[i].net_idx != BLE_MESH_KEY_UNUSED && bt_mesh.app_keys[i].app_idx == app_idx) { @@ -475,6 +497,8 @@ static int net_key_set(const char *name) int err = 0; int i; + BT_DBG("NetKeySet, Name %s", name); + buf = bt_mesh_get_core_settings_item(name); if (!buf) { return 0; @@ -533,6 +557,8 @@ static int app_key_set(const char *name) int err = 0; int i; + BT_DBG("AppKeySet, Name %s", name); + buf = bt_mesh_get_core_settings_item(name); if (!buf) { return 0; @@ -564,7 +590,6 @@ static int app_key_set(const char *name) if (!app) { app = bt_mesh_app_key_alloc(app_idx); if (!app) { - BT_ERR("No space for a new appkey 0x%03x", app_idx); err = -ENOMEM; goto free; } @@ -579,7 +604,7 @@ static int app_key_set(const char *name) bt_mesh_app_id(app->keys[1].val, &app->keys[1].id); BT_INFO("Restored AppKeyIndex 0x%03x, NetKeyIndex 0x%03x", - app->app_idx, app->net_idx); + app->app_idx, app->net_idx); BT_INFO("Restored AppKey %s", bt_hex(app->keys[0].val, 16)); } @@ -595,6 +620,8 @@ static int hb_pub_set(const char *name) bool exist = false; int err = 0; + BT_DBG("HbPubSet, Name %s", name); + if (!hb_pub) { BT_ERR("Invalid heartbeat publication"); return -EINVAL; @@ -639,6 +666,8 @@ static int cfg_set(const char *name) bool exist = false; int err = 0; + BT_DBG("CfgSet, Name %s", name); + if (!cfg) { BT_ERR("Invalid configuration"); stored_cfg.valid = false; @@ -672,6 +701,8 @@ static int model_set_bind(bool vnd, struct bt_mesh_model *model, uint16_t model_ int err = 0; int i; + BT_DBG("ModelSetBind, Key 0x%04x Vnd %u", model_key, vnd); + /* Start with empty array regardless of cleared or set value */ for (i = 0; i < ARRAY_SIZE(model->keys); i++) { model->keys[i] = BLE_MESH_KEY_UNUSED; @@ -698,6 +729,8 @@ static int model_set_sub(bool vnd, struct bt_mesh_model *model, uint16_t model_k int err = 0; int i; + BT_DBG("ModelSetSub, Key 0x%04x Vnd %u", model_key, vnd); + /* Start with empty array regardless of cleared or set value */ for (i = 0; i < ARRAY_SIZE(model->groups); i++) { model->groups[i] = BLE_MESH_ADDR_UNASSIGNED; @@ -724,6 +757,8 @@ static int model_set_pub(bool vnd, struct bt_mesh_model *model, uint16_t model_k bool exist = false; int err = 0; + BT_DBG("ModelSetPub, Key 0x%04x Vnd %u", model_key, vnd); + if (!model->pub) { BT_INFO("Not support publication, model_id 0x%04x, cid 0x%04x", vnd ? model->vnd.id : model->id, vnd ? model->vnd.company : 0xFFFF); @@ -774,6 +809,8 @@ static int model_set(bool vnd, const char *name) size_t length = 0U; int i; + BT_DBG("ModelSet, Name %s Vnd %u", name, vnd); + buf = bt_mesh_get_core_settings_item(name); if (!buf) { return 0; @@ -790,7 +827,7 @@ static int model_set(bool vnd, const char *name) model = bt_mesh_model_get(vnd, elem_idx, model_idx); if (!model) { BT_ERR("%s model not found, elem_idx %u, model_idx %u", - vnd ? "vnd" : "sig", elem_idx, model_idx); + vnd ? "vnd" : "sig", elem_idx, model_idx); continue; } @@ -825,6 +862,8 @@ static int va_set(const char *name) int err = 0; int i; + BT_DBG("VaSet, Name %s", name); + buf = bt_mesh_get_core_settings_item(name); if (!buf) { return 0; @@ -869,7 +908,7 @@ static int va_set(const char *name) bt_mesh_free_buf(buf); return err; } -#endif +#endif /* CONFIG_BLE_MESH_LABEL_COUNT > 0 */ #if CONFIG_BLE_MESH_PROVISIONER static int p_prov_set(const char *name) @@ -878,6 +917,8 @@ static int p_prov_set(const char *name) bool exist = false; int err = 0; + BT_DBG("PvnrProvSet, Name %s", name); + err = bt_mesh_load_core_settings(name, (uint8_t *)&val, sizeof(val), &exist); if (err) { BT_ERR("Failed to load next address allocation"); @@ -891,7 +932,7 @@ static int p_prov_set(const char *name) bt_mesh_provisioner_restore_prov_info(val.primary_addr, val.alloc_addr); BT_INFO("Restored Primary Address 0x%04x, next address alloc 0x%04x", - val.primary_addr, val.alloc_addr); + val.primary_addr, val.alloc_addr); return 0; } @@ -902,6 +943,8 @@ static int p_net_idx_set(const char *name) bool exist = false; int err = 0; + BT_DBG("PvnrNetIdxSet, Name %s", name); + err = bt_mesh_load_core_settings(name, (uint8_t *)&net_idx, sizeof(net_idx), &exist); if (err) { BT_ERR("Failed to load next NetKeyIndex alloc"); @@ -925,6 +968,8 @@ static int p_app_idx_set(const char *name) bool exist = false; int err = 0; + BT_DBG("PvnrAppIdxSet, Name %s", name); + err = bt_mesh_load_core_settings(name, (uint8_t *)&app_idx, sizeof(app_idx), &exist); if (err) { BT_ERR("Failed to load next AppKeyIndex alloc"); @@ -946,6 +991,8 @@ static struct bt_mesh_subnet *p_subnet_exist(uint16_t net_idx) { int i; + BT_DBG("PvnrSubnetExist, NetIdx 0x%04x", net_idx); + for (i = 0; i < ARRAY_SIZE(bt_mesh.p_sub); i++) { if (bt_mesh.p_sub[i] && bt_mesh.p_sub[i]->net_idx == net_idx) { @@ -960,6 +1007,8 @@ static struct bt_mesh_subnet *p_subnet_alloc(void) { int i; + BT_DBG("PvnrSubnetAlloc"); + for (i = 0; i < ARRAY_SIZE(bt_mesh.p_sub); i++) { if (bt_mesh.p_sub[i] == NULL) { bt_mesh.p_sub[i] = bt_mesh_calloc(sizeof(struct bt_mesh_subnet)); @@ -979,6 +1028,8 @@ static struct bt_mesh_app_key *p_appkey_exist(uint16_t app_idx) { int i; + BT_DBG("PvnrAppKeyExist, AppIdx 0x%04x", app_idx); + for (i = 0; i < ARRAY_SIZE(bt_mesh.p_app_keys); i++) { if (bt_mesh.p_app_keys[i] && bt_mesh.p_app_keys[i]->net_idx != BLE_MESH_KEY_UNUSED && @@ -994,6 +1045,8 @@ static struct bt_mesh_app_key *p_appkey_alloc(void) { int i; + BT_DBG("PvnrAppKeyAlloc"); + for (i = 0; i < ARRAY_SIZE(bt_mesh.p_app_keys); i++) { if (bt_mesh.p_app_keys[i] == NULL) { bt_mesh.p_app_keys[i] = bt_mesh_calloc(sizeof(struct bt_mesh_app_key)); @@ -1020,6 +1073,8 @@ static int p_net_key_set(const char *name) int err = 0; int i; + BT_DBG("PvnrNetKeySet, Name %s", name); + buf = bt_mesh_get_core_settings_item(name); if (!buf) { return 0; @@ -1078,6 +1133,8 @@ static int p_app_key_set(const char *name) int err = 0; int i; + BT_DBG("PvnrAppKeySet, Name %s", name); + buf = bt_mesh_get_core_settings_item(name); if (!buf) { return 0; @@ -1124,7 +1181,7 @@ static int p_app_key_set(const char *name) bt_mesh_app_id(app->keys[1].val, &app->keys[1].id); BT_INFO("Restored AppKeyIndex 0x%03x, NetKeyIndex 0x%03x", - app->app_idx, app->net_idx); + app->app_idx, app->net_idx); BT_INFO("Restored AppKey %s", bt_hex(app->keys[0].val, 16)); } @@ -1140,6 +1197,8 @@ static int node_info_set(uint16_t addr, bool *exist) char get[16] = {'\0'}; int err = 0; + BT_DBG("NodeInfoSet, Addr 0x%04x", addr); + sprintf(get, "mesh/pn/%04x/i", addr); err = bt_mesh_load_core_settings(get, (uint8_t *)&info, sizeof(info), exist); if (err) { @@ -1180,6 +1239,8 @@ static int node_name_set(uint16_t addr) bool exist = false; int err = 0; + BT_DBG("NodeNameSet, Addr 0x%04x", addr); + sprintf(get, "mesh/pn/%04x/n", addr); err = bt_mesh_load_core_settings(get, (uint8_t *)name, BLE_MESH_NODE_NAME_SIZE, &exist); if (err) { @@ -1208,6 +1269,8 @@ static int node_comp_data_set(uint16_t addr) char get[16] = {'\0'}; int err = 0; + BT_DBG("NodeCompDataSet, Addr 0x%04x", addr); + sprintf(get, "mesh/pn/%04x/c", addr); buf = bt_mesh_get_core_settings_item(get); if (!buf) { @@ -1232,6 +1295,8 @@ static int p_node_set(const char *name) size_t length = 0U; int i; + BT_DBG("PvnrNodeSet, Name %s", name); + buf = bt_mesh_get_core_settings_item(name); if (!buf) { return 0; @@ -1286,7 +1351,7 @@ const struct bt_mesh_setting { { "mesh/vnd", vnd_mod_set }, /* For Node & Provisioner */ #if CONFIG_BLE_MESH_LABEL_COUNT > 0 { "mesh/vaddr", va_set }, /* For Node */ -#endif +#endif /* CONFIG_BLE_MESH_LABEL_COUNT > 0 */ #if CONFIG_BLE_MESH_PROVISIONER { "mesh/p_prov", p_prov_set }, /* For Provisioner */ { "mesh/p_netidx", p_net_idx_set }, /* For Provisioner */ @@ -1294,7 +1359,7 @@ const struct bt_mesh_setting { { "mesh/p_netkey", p_net_key_set }, /* For Provisioner */ { "mesh/p_appkey", p_app_key_set }, /* For Provisioner */ { "mesh/p_node", p_node_set }, /* For Provisioner */ -#endif +#endif /* CONFIG_BLE_MESH_PROVISIONER */ }; /** @@ -1316,6 +1381,8 @@ int settings_core_load(void) { int i; + BT_DBG("SettingsCoreLoad"); + for (i = 0; i < ARRAY_SIZE(settings); i++) { if ((!strcmp(settings[i].name, "mesh/net") || !strcmp(settings[i].name, "mesh/netkey") || @@ -1367,6 +1434,8 @@ static int subnet_init(struct bt_mesh_subnet *sub) { int err = 0; + BT_DBG("SubnetInit, NetIdx 0x%04x KrPhase %u", sub->net_idx, sub->kr_phase); + err = bt_mesh_net_keys_create(&sub->keys[0], sub->keys[0].net); if (err) { BT_ERR("Unable to generate keys for subnet"); @@ -1394,7 +1463,7 @@ static int subnet_init(struct bt_mesh_subnet *sub) #if CONFIG_BLE_MESH_DF_SRV bt_mesh_directed_forwarding_sub_init(sub); bt_mesh_recovery_directed_forwarding_table(sub); -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ return 0; } @@ -1402,8 +1471,10 @@ static int subnet_init(struct bt_mesh_subnet *sub) static void commit_model(struct bt_mesh_model *model, struct bt_mesh_elem *elem, bool vnd, bool primary, void *user_data) { + BT_DBG("CommitModel, Vnd %u Primary %u", vnd, primary); + if (model->pub && model->pub->update && - model->pub->addr != BLE_MESH_ADDR_UNASSIGNED) { + model->pub->addr != BLE_MESH_ADDR_UNASSIGNED) { int32_t ms = bt_mesh_model_pub_period_get(model); if (ms) { BT_DBG("Starting publish timer (period %u ms)", ms); @@ -1418,10 +1489,13 @@ int settings_core_commit(void) int err = 0; int i; + BT_DBG("SettingsCoreCommit"); + #if CONFIG_BLE_MESH_NODE if (bt_mesh_is_node()) { if (bt_mesh.sub[0].net_idx == BLE_MESH_KEY_UNUSED) { /* Nothing to do since we're not yet provisioned */ + BT_INFO("NodeNotYetProvisioned"); return 0; } @@ -1511,20 +1585,22 @@ int settings_core_commit(void) } /* Pending flags that use K_NO_WAIT as the storage timeout */ -#define NO_WAIT_PENDING_BITS (BIT(BLE_MESH_NET_PENDING) | \ - BIT(BLE_MESH_IV_PENDING) | \ - BIT(BLE_MESH_SEQ_PENDING)) +#define NO_WAIT_PENDING_BITS (BIT(BLE_MESH_NET_PENDING) | \ + BIT(BLE_MESH_IV_PENDING) | \ + BIT(BLE_MESH_SEQ_PENDING)) /* Pending flags that use CONFIG_BLE_MESH_STORE_TIMEOUT */ -#define GENERIC_PENDING_BITS (BIT(BLE_MESH_KEYS_PENDING) | \ - BIT(BLE_MESH_HB_PUB_PENDING) | \ - BIT(BLE_MESH_CFG_PENDING) | \ - BIT(BLE_MESH_MOD_PENDING)) +#define GENERIC_PENDING_BITS (BIT(BLE_MESH_KEYS_PENDING) | \ + BIT(BLE_MESH_HB_PUB_PENDING) | \ + BIT(BLE_MESH_CFG_PENDING) | \ + BIT(BLE_MESH_MOD_PENDING)) static void schedule_store(int flag) { int32_t timeout = 0, remaining = 0; + BT_DBG("ScheduleStore, Flag %ld", flag); + bt_mesh_atomic_set_bit(bt_mesh.flags, flag); /* When Node is not provisioned OR Provisioner is disabled, @@ -1562,7 +1638,8 @@ static void schedule_store(int flag) static void clear_net(void) { - BT_DBG("Clearing Network"); + BT_DBG("ClearNet"); + bt_mesh_erase_core_settings("mesh/net"); } @@ -1570,8 +1647,9 @@ static void store_pending_net(void) { struct net_val net = {0}; - BT_DBG("Primary address 0x%04x DevKey %s", bt_mesh_primary_addr(), - bt_hex(bt_mesh.dev_key, 16)); + BT_DBG("StorePendingNet"); + BT_DBG("PrimaryAddr 0x%04x DevKey %s", + bt_mesh_primary_addr(), bt_hex(bt_mesh.dev_key, 16)); net.primary_addr = bt_mesh_primary_addr(); memcpy(net.dev_key, bt_mesh.dev_key, 16); @@ -1581,13 +1659,15 @@ static void store_pending_net(void) void bt_mesh_store_role(void) { - BT_DBG("Store, device role %lu", bt_mesh_atomic_get(bt_mesh.flags) & BLE_MESH_SETTINGS_ROLE_BIT_MASK); + BT_DBG("StoreRole %lu", bt_mesh_atomic_get(bt_mesh.flags) & BLE_MESH_SETTINGS_ROLE_BIT_MASK); bt_mesh_save_core_settings("mesh/role", (const uint8_t *)bt_mesh.flags, sizeof(bt_mesh.flags)); } void bt_mesh_store_net(void) { + BT_DBG("StoreNetSchedule"); + schedule_store(BLE_MESH_NET_PENDING); } @@ -1595,6 +1675,8 @@ static void store_pending_iv(void) { struct iv_val iv = {0}; + BT_DBG("StorePendingIV"); + iv.iv_index = bt_mesh.iv_index; iv.iv_update = bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_IVU_IN_PROGRESS); iv.iv_duration = bt_mesh.ivu_duration; @@ -1604,6 +1686,8 @@ static void store_pending_iv(void) void bt_mesh_store_iv(bool only_duration) { + BT_DBG("StoreIVSchedule, OnlyDuration %u", only_duration); + schedule_store(BLE_MESH_IV_PENDING); if (!only_duration) { @@ -1614,7 +1698,8 @@ void bt_mesh_store_iv(bool only_duration) static void clear_iv(void) { - BT_DBG("Clearing IV"); + BT_DBG("ClearIV"); + bt_mesh_erase_core_settings("mesh/iv"); } @@ -1622,6 +1707,8 @@ static void store_pending_seq(void) { struct seq_val seq = {0}; + BT_DBG("StorePendingSeq, Seq 0x%06x", bt_mesh.seq); + sys_put_le24(bt_mesh.seq, seq.val); bt_mesh_save_core_settings("mesh/seq", (const uint8_t *)&seq, sizeof(seq)); @@ -1629,6 +1716,8 @@ static void store_pending_seq(void) void bt_mesh_store_seq(void) { + BT_DBG("StoreSeqSchedule, Seq 0x%06x", bt_mesh.seq); + if (CONFIG_BLE_MESH_SEQ_STORE_RATE && (bt_mesh.seq % CONFIG_BLE_MESH_SEQ_STORE_RATE)) { return; @@ -1639,7 +1728,8 @@ void bt_mesh_store_seq(void) void bt_mesh_clear_seq(void) { - BT_DBG("Clearing Seq"); + BT_DBG("ClearSeq"); + bt_mesh_erase_core_settings("mesh/seq"); } @@ -1649,7 +1739,8 @@ static void store_rpl(struct bt_mesh_rpl *entry) char name[16] = {'\0'}; int err = 0; - BT_DBG("src 0x%04x seq 0x%06x old_iv %u", entry->src, entry->seq, entry->old_iv); + BT_DBG("StoreRPL"); + BT_DBG("Src 0x%04x Seq 0x%06x OldIV %u", entry->src, entry->seq, entry->old_iv); rpl.seq = entry->seq; rpl.old_iv = entry->old_iv; @@ -1675,6 +1766,8 @@ static void clear_rpl(void) uint16_t src = 0U; int i; + BT_DBG("ClearRPL"); + buf = bt_mesh_get_core_settings_item("mesh/rpl"); if (!buf) { bt_mesh_erase_core_settings("mesh/rpl"); @@ -1704,9 +1797,14 @@ static void store_pending_rpl(void) { int i; + BT_DBG("StorePendingRPL"); + for (i = 0; i < ARRAY_SIZE(bt_mesh.rpl); i++) { struct bt_mesh_rpl *rpl = &bt_mesh.rpl[i]; + BT_DBG("%u: Src 0x%04x Seq 0x%06x OldIV %u Store %u", + i, rpl->src, rpl->seq, rpl->old_iv, rpl->store); + if (rpl->store) { rpl->store = false; store_rpl(rpl); @@ -1719,6 +1817,8 @@ static void store_pending_hb_pub(void) struct bt_mesh_hb_pub *hb_pub = bt_mesh_hb_pub_get(); struct hb_pub_val val = {0}; + BT_DBG("StorePendingHbPub"); + if (!hb_pub) { BT_ERR("Invalid heartbeat publication"); return; @@ -1736,7 +1836,8 @@ static void store_pending_hb_pub(void) static void clear_hb_pub(void) { - BT_DBG("Clear heartbeat publication"); + BT_DBG("ClearHbPub"); + bt_mesh_erase_core_settings("mesh/hb_pub"); } @@ -1745,6 +1846,8 @@ static void store_pending_cfg(void) struct bt_mesh_cfg_srv *cfg = bt_mesh_cfg_get(); struct cfg_val val = {0}; + BT_DBG("StorePendingCfg"); + if (!cfg) { BT_WARN("NULL configuration state"); return; @@ -1763,7 +1866,8 @@ static void store_pending_cfg(void) static void clear_cfg(void) { - BT_DBG("Clearing configuration"); + BT_DBG("ClearCfg"); + bt_mesh_erase_core_settings("mesh/cfg"); } @@ -1772,7 +1876,7 @@ static void clear_app_key(uint16_t app_idx) char name[16] = {'\0'}; int err = 0; - BT_DBG("AppKeyIndex 0x%03x", app_idx); + BT_DBG("ClearAppKey, AppIdx 0x%04x", app_idx); sprintf(name, "mesh/ak/%04x", app_idx); bt_mesh_erase_core_settings(name); @@ -1788,7 +1892,7 @@ static void clear_net_key(uint16_t net_idx) char name[16] = {'\0'}; int err = 0; - BT_DBG("NetKeyIndex 0x%03x", net_idx); + BT_DBG("ClearNetKey, NetIdx 0x%04x", net_idx); sprintf(name, "mesh/nk/%04x", net_idx); bt_mesh_erase_core_settings(name); @@ -1800,7 +1904,7 @@ static void clear_net_key(uint16_t net_idx) #if CONFIG_BLE_MESH_DF_SRV bt_mesh_clear_directed_forwarding_table_data(net_idx); -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ } static void store_net_key(struct bt_mesh_subnet *sub) @@ -1809,8 +1913,8 @@ static void store_net_key(struct bt_mesh_subnet *sub) char name[16] = {'\0'}; int err = 0; - BT_DBG("NetKeyIndex 0x%03x NetKey %s", sub->net_idx, - bt_hex(sub->keys[0].net, 16)); + BT_DBG("StoreNetKey, NetIdx 0x%04x KrFlag %u KrPhase %u", + sub->net_idx, sub->kr_flag, sub->kr_phase); memcpy(&key.val[0], sub->keys[0].net, 16); memcpy(&key.val[1], sub->keys[1].net, 16); @@ -1836,6 +1940,9 @@ static void store_app_key(struct bt_mesh_app_key *app) char name[16] = {'\0'}; int err = 0; + BT_DBG("StoreAppKey, NetIdx 0x%04x AppIdx 0x%04x Updated %u", + app->net_idx, app->app_idx, app->updated); + key.net_idx = app->net_idx; key.updated = app->updated; memcpy(key.val[0], app->keys[0].val, 16); @@ -1858,9 +1965,14 @@ static void store_pending_keys(void) { int i; + BT_DBG("StorePendingKeys"); + for (i = 0; i < ARRAY_SIZE(key_updates); i++) { struct key_update *update = &key_updates[i]; + BT_DBG("%u: KeyIdx 0x%04x Valid %u AppKey %u Clear %u", + i, update->key_idx, update->valid, update->app_key, update->clear); + if (!update->valid) { continue; } @@ -1874,6 +1986,7 @@ static void store_pending_keys(void) } else { if (update->app_key) { struct bt_mesh_app_key *key = NULL; + key = bt_mesh_app_key_get(update->key_idx); if (key) { store_app_key(key); @@ -1882,6 +1995,7 @@ static void store_pending_keys(void) } } else { struct bt_mesh_subnet *sub = NULL; + sub = bt_mesh_subnet_get(update->key_idx); if (sub) { store_net_key(sub); @@ -1901,6 +2015,8 @@ static void store_pending_mod_bind(struct bt_mesh_model *model, bool vnd) uint16_t model_key = 0U; int err = 0; + BT_DBG("StorePendingModBind, Vnd %u", vnd); + model_key = BLE_MESH_GET_MODEL_KEY(model->elem_idx, model->model_idx); sprintf(name, "mesh/%s/%04x/b", vnd ? "v" : "s", model_key); @@ -1913,7 +2029,7 @@ static void store_pending_mod_bind(struct bt_mesh_model *model, bool vnd) err = bt_mesh_add_core_settings_item(vnd ? "mesh/vnd" : "mesh/sig", model_key); if (err) { BT_ERR("Failed to add bound key to %s, model_key 0x%04x", - vnd ? "mesh/vnd" : "mesh/sig", model_key); + vnd ? "mesh/vnd" : "mesh/sig", model_key); } } @@ -1923,6 +2039,8 @@ static void store_pending_mod_sub(struct bt_mesh_model *model, bool vnd) uint16_t model_key = 0U; int err = 0; + BT_DBG("StorePendingModSub, Vnd %u", vnd); + model_key = BLE_MESH_GET_MODEL_KEY(model->elem_idx, model->model_idx); sprintf(name, "mesh/%s/%04x/s", vnd ? "v" : "s", model_key); @@ -1935,7 +2053,7 @@ static void store_pending_mod_sub(struct bt_mesh_model *model, bool vnd) err = bt_mesh_add_core_settings_item(vnd ? "mesh/vnd" : "mesh/sig", model_key); if (err) { BT_ERR("Failed to add subscription to %s, model_key 0x%04x", - vnd ? "mesh/vnd" : "mesh/sig", model_key); + vnd ? "mesh/vnd" : "mesh/sig", model_key); } } @@ -1946,6 +2064,8 @@ static void store_pending_mod_pub(struct bt_mesh_model *model, bool vnd) uint16_t model_key = 0U; int err = 0; + BT_DBG("StorePendingModPub, Vnd %u", vnd); + if (!model->pub) { BT_WARN("Model has no publication support"); return; @@ -1964,7 +2084,7 @@ static void store_pending_mod_pub(struct bt_mesh_model *model, bool vnd) #if CONFIG_BLE_MESH_DF_SRV pub.directed_pub_policy = model->pub->directed_pub_policy; /**< Directed publish policy */ -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ err = bt_mesh_save_core_settings(name, (const uint8_t *)&pub, sizeof(pub)); if (err) { @@ -1983,6 +2103,8 @@ static void store_pending_mod(struct bt_mesh_model *model, struct bt_mesh_elem *elem, bool vnd, bool primary, void *user_data) { + BT_DBG("StorePendingMod, Flags %u Vnd %u", model->flags, vnd); + if (!model->flags) { return; } @@ -2008,6 +2130,8 @@ static void clear_mod_bind(struct bt_mesh_model *model, bool vnd) char name[16] = {'\0'}; uint16_t model_key = 0U; + BT_DBG("ClearModBind, Vnd %u", vnd); + model_key = BLE_MESH_GET_MODEL_KEY(model->elem_idx, model->model_idx); sprintf(name, "mesh/%s/%04x/b", vnd ? "v" : "s", model_key); @@ -2020,6 +2144,8 @@ static void clear_mod_sub(struct bt_mesh_model *model, bool vnd) char name[16] = {'\0'}; uint16_t model_key = 0U; + BT_DBG("ClearModSub, Vnd %u", vnd); + model_key = BLE_MESH_GET_MODEL_KEY(model->elem_idx, model->model_idx); sprintf(name, "mesh/%s/%04x/s", vnd ? "v" : "s", model_key); @@ -2029,8 +2155,10 @@ static void clear_mod_sub(struct bt_mesh_model *model, bool vnd) static void clear_mod_pub(struct bt_mesh_model *model, bool vnd) { - char name[16] = {'\0'}; uint16_t model_key = 0U; + char name[16] = {'\0'}; + + BT_DBG("ClearModPub, Vnd %u", vnd); model_key = BLE_MESH_GET_MODEL_KEY(model->elem_idx, model->model_idx); sprintf(name, "mesh/%s/%04x/p", vnd ? "v" : "s", model_key); @@ -2043,6 +2171,8 @@ static void clear_pending_mod(struct bt_mesh_model *model, struct bt_mesh_elem *elem, bool vnd, bool primary, void *user_data) { + BT_DBG("ClearPendingMod, Flags 0x%04x Vnd %u", model->flags, vnd); + if (!model->flags) { return; } @@ -2066,12 +2196,14 @@ static void clear_pending_mod(struct bt_mesh_model *model, #define IS_VA_DEL(_label) ((_label)->ref == 0) static void store_pending_va(void) { + struct label *lab = NULL; struct va_val va = {0}; char name[16] = {'\0'}; - struct label *lab = NULL; uint16_t i = 0U; int err = 0; + BT_DBG("StorePendingVa"); + for (i = 0U; (lab = get_label(i)) != NULL; i++) { if (!bt_mesh_atomic_test_and_clear_bit(lab->flags, BLE_MESH_VA_CHANGED)) { @@ -2090,7 +2222,7 @@ static void store_pending_va(void) } if (err) { BT_ERR("Failed to %s virtual address %s", - IS_VA_DEL(lab) ? "delete" : "store", name); + IS_VA_DEL(lab) ? "delete" : "store", name); return; } @@ -2101,7 +2233,7 @@ static void store_pending_va(void) } if (err) { BT_ERR("Failed to %s 0x%04x in mesh/vaddr", - IS_VA_DEL(lab) ? "delete" : "store", i); + IS_VA_DEL(lab) ? "delete" : "store", i); return; } @@ -2111,6 +2243,8 @@ static void store_pending_va(void) static void store_pending(struct k_work *work) { + BT_DBG("StorePending"); + if (bt_mesh_atomic_test_and_clear_bit(bt_mesh.flags, BLE_MESH_RPL_PENDING)) { if (bt_mesh_is_provisioned() || bt_mesh_is_provisioner_en()) { store_pending_rpl(); @@ -2172,6 +2306,7 @@ static void store_pending(struct k_work *work) bt_mesh_model_foreach(store_pending_mod, NULL); } else { bt_mesh_model_foreach(clear_pending_mod, NULL); + bt_mesh_erase_core_settings("mesh/sig"); bt_mesh_erase_core_settings("mesh/vnd"); } @@ -2185,6 +2320,9 @@ static void store_pending(struct k_work *work) void bt_mesh_store_rpl(struct bt_mesh_rpl *entry) { + BT_DBG("StoreRPLSchedule"); + BT_DBG("Src 0x%04x Seq 0x%06x OldIV %u", entry->src, entry->seq, entry->old_iv); + entry->store = true; schedule_store(BLE_MESH_RPL_PENDING); } @@ -2197,6 +2335,8 @@ static struct key_update *key_update_find(bool app_key, uint16_t key_idx, *free_slot = NULL; + BT_DBG("KeyUpdateFind, KeyIdx 0x%04x AppKey %u", key_idx, app_key); + for (i = 0; i < ARRAY_SIZE(key_updates); i++) { struct key_update *update = &key_updates[i]; @@ -2222,7 +2362,7 @@ void bt_mesh_store_subnet(struct bt_mesh_subnet *sub) struct key_update *free_slot = NULL; struct key_update *update = NULL; - BT_DBG("NetKeyIndex 0x%03x", sub->net_idx); + BT_DBG("StoreSubnetSchedule, NetIdx 0x%04x", sub->net_idx); update = key_update_find(false, sub->net_idx, &free_slot); if (update) { @@ -2232,6 +2372,7 @@ void bt_mesh_store_subnet(struct bt_mesh_subnet *sub) } if (!free_slot) { + BT_DBG("NoFreeSlotForSubnet"); store_net_key(sub); return; } @@ -2249,7 +2390,7 @@ void bt_mesh_store_app_key(struct bt_mesh_app_key *key) struct key_update *free_slot = NULL; struct key_update *update = NULL; - BT_DBG("AppKeyIndex 0x%03x", key->app_idx); + BT_DBG("StoreAppKeySchedule, AppIdx 0x%04x", key->app_idx); update = key_update_find(true, key->app_idx, &free_slot); if (update) { @@ -2259,6 +2400,7 @@ void bt_mesh_store_app_key(struct bt_mesh_app_key *key) } if (!free_slot) { + BT_DBG("NoFreeSlotForAppKey"); store_app_key(key); return; } @@ -2273,22 +2415,29 @@ void bt_mesh_store_app_key(struct bt_mesh_app_key *key) void bt_mesh_store_hb_pub(void) { + BT_DBG("StoreHbPubSchedule"); + schedule_store(BLE_MESH_HB_PUB_PENDING); } void bt_mesh_store_cfg(void) { + BT_DBG("StoreCfgSchedule"); + schedule_store(BLE_MESH_CFG_PENDING); } void bt_mesh_clear_role(void) { - BT_DBG("Clear device role"); + BT_DBG("ClearRole"); + bt_mesh_erase_core_settings("mesh/role"); } void bt_mesh_clear_net(void) { + BT_DBG("ClearNetSchedule"); + schedule_store(BLE_MESH_NET_PENDING); schedule_store(BLE_MESH_IV_PENDING); schedule_store(BLE_MESH_CFG_PENDING); @@ -2299,7 +2448,7 @@ void bt_mesh_clear_subnet(struct bt_mesh_subnet *sub) struct key_update *free_slot = NULL; struct key_update *update = NULL; - BT_DBG("NetKeyIndex 0x%03x", sub->net_idx); + BT_DBG("ClearSubnetSchedule, NetIdx 0x%04x", sub->net_idx); update = key_update_find(false, sub->net_idx, &free_slot); if (update) { @@ -2326,7 +2475,7 @@ void bt_mesh_clear_app_key(struct bt_mesh_app_key *key) struct key_update *free_slot = NULL; struct key_update *update = NULL; - BT_DBG("AppKeyIndex 0x%03x", key->app_idx); + BT_DBG("ClearAppKeySchedule, AppIdx 0x%04x", key->app_idx); update = key_update_find(true, key->app_idx, &free_slot); if (update) { @@ -2353,6 +2502,8 @@ void bt_mesh_clear_rpl_single(uint16_t src) char name[16] = {'\0'}; int err = 0; + BT_DBG("ClearRPLSingle, Src 0x%04x", src); + if (!BLE_MESH_ADDR_IS_UNICAST(src)) { BT_ERR("Invalid src 0x%04x", src); return; @@ -2369,39 +2520,53 @@ void bt_mesh_clear_rpl_single(uint16_t src) void bt_mesh_clear_rpl(void) { + BT_DBG("ClearRPLSchedule"); + schedule_store(BLE_MESH_RPL_PENDING); } void bt_mesh_store_mod_bind(struct bt_mesh_model *model) { + BT_DBG("StoreModBindSchedule"); + model->flags |= BLE_MESH_MOD_BIND_PENDING; schedule_store(BLE_MESH_MOD_PENDING); } void bt_mesh_store_mod_sub(struct bt_mesh_model *model) { + BT_DBG("StoreModSubSchedule"); + model->flags |= BLE_MESH_MOD_SUB_PENDING; schedule_store(BLE_MESH_MOD_PENDING); } void bt_mesh_store_mod_pub(struct bt_mesh_model *model) { + BT_DBG("StoreModPubSchedule"); + model->flags |= BLE_MESH_MOD_PUB_PENDING; schedule_store(BLE_MESH_MOD_PENDING); } void bt_mesh_store_label(void) { + BT_DBG("StoreLabelSchedule"); + schedule_store(BLE_MESH_VA_PENDING); } void bt_mesh_store_dkca(void) { + BT_DBG("StoreDkca"); + bt_mesh_save_core_settings("mesh/dkca", bt_mesh.dev_key_ca, sizeof(bt_mesh.dev_key_ca)); } void bt_mesh_clear_dkca(void) { + BT_DBG("ClearDkca"); + bt_mesh_erase_core_settings("mesh/dkca"); } @@ -2423,7 +2588,7 @@ void bt_mesh_store_prov_info(uint16_t primary_addr, uint16_t alloc_addr) { struct prov_info val = {0}; - BT_DBG("Primary address 0x%04x, next address allocation 0x%04x", primary_addr, alloc_addr); + BT_DBG("StoreProvInfo, PrimaryAddr 0x%04x AllocAddr 0x%04x", primary_addr, alloc_addr); val.primary_addr = primary_addr; val.alloc_addr = alloc_addr; @@ -2433,7 +2598,8 @@ void bt_mesh_store_prov_info(uint16_t primary_addr, uint16_t alloc_addr) void bt_mesh_clear_prov_info(void) { - BT_DBG("Clearing prov info"); + BT_DBG("ClearProvInfo"); + bt_mesh_erase_core_settings("mesh/p_prov"); } @@ -2443,6 +2609,9 @@ static void store_p_net_key(struct bt_mesh_subnet *sub) char name[16] = {'\0'}; int err = 0; + BT_DBG("StorePvnrNetKey, NetIdx 0x%04x KrFlag %u KrPhase %u", + sub->net_idx, sub->kr_flag, sub->kr_phase); + memcpy(&key.val[0], sub->keys[0].net, 16); memcpy(&key.val[1], sub->keys[1].net, 16); key.kr_flag = sub->kr_flag; @@ -2467,6 +2636,9 @@ static void store_p_app_key(struct bt_mesh_app_key *app) char name[16] = {'\0'}; int err = 0; + BT_DBG("StorePvnrAppKey, NetIdx 0x%04x AppIdx 0x%04x Updated %u", + app->net_idx, app->app_idx, app->updated); + key.net_idx = app->net_idx; key.updated = app->updated; memcpy(key.val[0], app->keys[0].val, 16); @@ -2487,7 +2659,7 @@ static void store_p_app_key(struct bt_mesh_app_key *app) void bt_mesh_store_p_net_idx(void) { - BT_DBG("Store, p_net_idx_next 0x%03x", bt_mesh.p_net_idx_next); + BT_DBG("StorePvnrNetIdx, NetIdxNext 0x%04x", bt_mesh.p_net_idx_next); bt_mesh_save_core_settings("mesh/p_netidx", (const uint8_t *)&bt_mesh.p_net_idx_next, sizeof(bt_mesh.p_net_idx_next)); @@ -2495,13 +2667,14 @@ void bt_mesh_store_p_net_idx(void) void bt_mesh_clear_p_net_idx(void) { - BT_DBG("Clearing NetKey Index"); + BT_DBG("ClearPvnrNetIdx"); + bt_mesh_erase_core_settings("mesh/p_netidx"); } void bt_mesh_store_p_app_idx(void) { - BT_DBG("Store, p_app_idx_next 0x%03x", bt_mesh.p_app_idx_next); + BT_DBG("StorePvnrAppIdx, AppIdxNext 0x%04x", bt_mesh.p_app_idx_next); bt_mesh_save_core_settings("mesh/p_appidx", (const uint8_t *)&bt_mesh.p_app_idx_next, sizeof(bt_mesh.p_app_idx_next)); @@ -2509,32 +2682,37 @@ void bt_mesh_store_p_app_idx(void) void bt_mesh_clear_p_app_idx(void) { - BT_DBG("Clearing AppKey Index"); + BT_DBG("ClearPvnrAppIdx"); + bt_mesh_erase_core_settings("mesh/p_appidx"); } void bt_mesh_store_p_subnet(struct bt_mesh_subnet *sub) { + BT_DBG("StorePvnrSubnet"); + if (sub == NULL) { BT_ERR("Invalid subnet"); return; } - BT_DBG("NetKeyIndex 0x%03x NetKey %s", sub->net_idx, - bt_hex(sub->keys[0].net, 16)); + BT_DBG("NetIdx 0x%04x NetKey %s", + sub->net_idx, bt_hex(sub->keys[0].net, 16)); store_p_net_key(sub); } void bt_mesh_store_p_app_key(struct bt_mesh_app_key *key) { + BT_DBG("StorePvnrAppKey"); + if (key == NULL) { BT_ERR("Invalid AppKey"); return; } - BT_DBG("AppKeyIndex 0x%03x AppKey %s", key->app_idx, - bt_hex(key->keys[0].val, 16)); + BT_DBG("AppIdx 0x%03x AppKey %s", + key->app_idx, bt_hex(key->keys[0].val, 16)); store_p_app_key(key); } @@ -2544,7 +2722,7 @@ void bt_mesh_clear_p_subnet(uint16_t net_idx) char name[16] = {'\0'}; int err = 0; - BT_DBG("NetKeyIndex 0x%03x", net_idx); + BT_DBG("ClearPvnrSubnet, NetIdx 0x%04x", net_idx); sprintf(name, "mesh/pnk/%04x", net_idx); bt_mesh_erase_core_settings(name); @@ -2560,7 +2738,7 @@ void bt_mesh_clear_p_app_key(uint16_t app_idx) char name[16] = {'\0'}; int err = 0; - BT_DBG("AppKeyIndex 0x%03x", app_idx); + BT_DBG("ClearPvnrAppKey, AppIdx 0x%04x", app_idx); sprintf(name, "mesh/pak/%04x", app_idx); bt_mesh_erase_core_settings(name); @@ -2577,11 +2755,17 @@ void bt_mesh_store_node_info(struct bt_mesh_node *node) char name[16] = {'\0'}; int err = 0; + BT_DBG("StoreNodeInfo"); + if (node == NULL) { BT_ERR("Invalid node info"); return; } + BT_DBG("UnicastAddr 0x%04x ElemNum %u NetIdx 0x%04x Flags %u IVIndex %lu", + node->unicast_addr, node->element_num, + node->net_idx, node->flags, node->iv_index); + memcpy(val.addr, node->addr, BLE_MESH_ADDR_LEN); val.addr_type = node->addr_type; memcpy(val.dev_uuid, node->dev_uuid, 16); @@ -2611,6 +2795,8 @@ static void clear_node(uint16_t addr) char name[16] = {'\0'}; int err = 0; + BT_DBG("ClearNode, Addr 0x%04x", addr); + /* Clear node information */ sprintf(name, "mesh/pn/%04x/i", addr); bt_mesh_erase_core_settings(name); @@ -2631,13 +2817,13 @@ static void clear_node(uint16_t addr) void bt_mesh_clear_node_info(uint16_t unicast_addr) { + BT_DBG("ClearNodeInfo, Addr 0x%04x", unicast_addr); + if (!BLE_MESH_ADDR_IS_UNICAST(unicast_addr)) { BT_ERR("Invalid unicast address 0x%04x", unicast_addr); return; } - BT_DBG("Unicast address 0x%04x", unicast_addr); - clear_node(unicast_addr); } @@ -2647,11 +2833,15 @@ void bt_mesh_store_node_name(struct bt_mesh_node *node) char name[16] = {'\0'}; int err = 0; + BT_DBG("StoreNodeName"); + if (node == NULL) { BT_ERR("Invalid node info"); return; } + BT_DBG("UnicastAddr 0x%04x NodeName %s", node->unicast_addr, node->name); + strncpy(node_name, node->name, BLE_MESH_NODE_NAME_SIZE + 1); sprintf(name, "mesh/pn/%04x/n", node->unicast_addr); @@ -2666,11 +2856,15 @@ void bt_mesh_store_node_comp_data(struct bt_mesh_node *node) char name[16] = {'\0'}; int err = 0; + BT_DBG("StoreNodeCompData"); + if (!node || !node->comp_data || node->comp_length == 0U) { BT_ERR("Invalid node info"); return; } + BT_DBG("UnicastAddr 0x%04x CompLength %u", node->unicast_addr, node->comp_length); + sprintf(name, "mesh/pn/%04x/c", node->unicast_addr); err = bt_mesh_save_core_settings(name, (const uint8_t *)node->comp_data, node->comp_length); if (err) { @@ -2681,12 +2875,16 @@ void bt_mesh_store_node_comp_data(struct bt_mesh_node *node) int settings_core_init(void) { + BT_DBG("SettingsCoreInit"); + k_delayed_work_init(&pending_store, store_pending); return 0; } int bt_mesh_settings_init(void) { + BT_DBG("SettingsInit"); + bt_mesh_settings_mutex_new(); bt_mesh_settings_init_foreach(); return 0; @@ -2695,12 +2893,16 @@ int bt_mesh_settings_init(void) #if CONFIG_BLE_MESH_DEINIT int settings_core_deinit(void) { + BT_DBG("SettingsCoreDeinit"); + k_delayed_work_free(&pending_store); return 0; } int settings_core_erase(void) { + BT_DBG("SettingsCoreErase"); + /* Erase here must not use the pending_store timer. * This is used for erasing the information which * could not be erased during the previous deinit @@ -2714,6 +2916,8 @@ int settings_core_erase(void) int bt_mesh_settings_deinit(bool erase) { + BT_DBG("SettingsDeinit, Erase %u", erase); + bt_mesh_settings_deinit_foreach(erase); bt_mesh_settings_mutex_free(); return 0; @@ -2722,6 +2926,8 @@ int bt_mesh_settings_deinit(bool erase) void bt_mesh_settings_reset(bool erase) { + BT_DBG("SettingsReset, Erase %u", erase); + k_delayed_work_cancel(&pending_store); if (erase) { bt_mesh_clear_net(); diff --git a/components/bt/esp_ble_mesh/core/storage/settings_nvs.c b/components/bt/esp_ble_mesh/core/storage/settings_nvs.c index ca3ac144ef5d..e2f730d41aa1 100644 --- a/components/bt/esp_ble_mesh/core/storage/settings_nvs.c +++ b/components/bt/esp_ble_mesh/core/storage/settings_nvs.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,7 +17,7 @@ enum settings_type { SETTINGS_CORE, #if CONFIG_BLE_MESH_USE_MULTIPLE_NAMESPACE SETTINGS_UID, -#endif +#endif /* CONFIG_BLE_MESH_USE_MULTIPLE_NAMESPACE */ }; struct settings_context { @@ -62,15 +62,20 @@ static struct settings_context settings_ctx[] = { int bt_mesh_settings_nvs_open(const char* name, bt_mesh_nvs_handle_t *handle) { + assert(name); + BT_DBG("SettingsNVSOpen, Name %s", name); + #if CONFIG_BLE_MESH_SPECIFIC_PARTITION return nvs_open_from_partition(CONFIG_BLE_MESH_PARTITION_NAME, name, NVS_READWRITE, handle); -#else +#else /* CONFIG_BLE_MESH_SPECIFIC_PARTITION */ return nvs_open(name, NVS_READWRITE, handle); -#endif +#endif /* CONFIG_BLE_MESH_SPECIFIC_PARTITION */ } void bt_mesh_settings_nvs_close(bt_mesh_nvs_handle_t handle) { + BT_DBG("SettingsNVSClose, Handle %lu", handle); + nvs_close(handle); } @@ -79,6 +84,8 @@ void bt_mesh_settings_init_foreach(void) int err = 0; int i; + BT_DBG("SettingsInitForeach"); + #if CONFIG_BLE_MESH_SPECIFIC_PARTITION err = nvs_flash_init_partition(CONFIG_BLE_MESH_PARTITION_NAME); if (err != ESP_OK) { @@ -134,6 +141,8 @@ void bt_mesh_settings_deinit_foreach(bool erase) { int i; + BT_DBG("SettingsDeinitForeach, Erase %u", erase); + for (i = 0; i < ARRAY_SIZE(settings_ctx); i++) { struct settings_context *ctx = &settings_ctx[i]; @@ -152,7 +161,7 @@ void bt_mesh_settings_deinit_foreach(bool erase) #if CONFIG_BLE_MESH_SPECIFIC_PARTITION nvs_flash_deinit_partition(CONFIG_BLE_MESH_PARTITION_NAME); -#endif +#endif /* CONFIG_BLE_MESH_SPECIFIC_PARTITION */ } #endif /* CONFIG_BLE_MESH_DEINIT */ @@ -161,6 +170,8 @@ int bt_mesh_settings_direct_open(bt_mesh_nvs_handle_t *handle) int err = 0; int i; + BT_DBG("SettingsDirectOpen"); + #if CONFIG_BLE_MESH_SPECIFIC_PARTITION err = nvs_flash_init_partition(CONFIG_BLE_MESH_PARTITION_NAME); if (err != ESP_OK) { @@ -178,6 +189,8 @@ int bt_mesh_settings_direct_open(bt_mesh_nvs_handle_t *handle) return -EIO; } + BT_DBG("%u: NVSName %s Handle %lu", i, ctx->nvs_name, ctx->handle); + if (i == SETTINGS_CORE && handle) { *handle = ctx->handle; } @@ -190,25 +203,30 @@ void bt_mesh_settings_direct_close(void) { int i; + BT_DBG("SettingsDirectClose"); + for (i = 0; i < ARRAY_SIZE(settings_ctx); i++) { bt_mesh_settings_nvs_close(settings_ctx[i].handle); } #if CONFIG_BLE_MESH_SPECIFIC_PARTITION nvs_flash_deinit_partition(CONFIG_BLE_MESH_PARTITION_NAME); -#endif +#endif /* CONFIG_BLE_MESH_SPECIFIC_PARTITION */ } /* API used to get BLE Mesh related nvs handle */ static inline bt_mesh_nvs_handle_t settings_get_nvs_handle(enum settings_type type) { + BT_DBG("SettingsGetNVSHandle, Type %u", type); + #if CONFIG_BLE_MESH_USE_MULTIPLE_NAMESPACE if (type == SETTINGS_CORE) { extern bt_mesh_nvs_handle_t get_core_settings_handle(void); return get_core_settings_handle(); } -#endif +#endif /* CONFIG_BLE_MESH_USE_MULTIPLE_NAMESPACE */ + return settings_ctx[type].handle; } @@ -218,12 +236,8 @@ static int settings_save(bt_mesh_nvs_handle_t handle, const char *key, const uin { int err = 0; - if (key == NULL) { - BT_ERR("%s, Invalid parameter", __func__); - return -EINVAL; - } - - BT_DBG("nvs %s, key %s", val ? "set" : "erase", key); + BT_DBG("Settings%s, Handle %lu Len %lu Key %s", + val ? "Store" : "Erase", handle, len, key); if (val) { err = nvs_set_blob(handle, key, val, len); @@ -236,7 +250,7 @@ static int settings_save(bt_mesh_nvs_handle_t handle, const char *key, const uin } if (err != ESP_OK) { BT_ERR("Failed to %s %s data (err %d)", - val ? "set" : "erase", key, err); + val ? "set" : "erase", key, err); return -EIO; } @@ -262,6 +276,10 @@ int bt_mesh_save_settings(bt_mesh_nvs_handle_t handle, const char *key, int bt_mesh_save_core_settings(const char *key, const uint8_t *val, size_t len) { bt_mesh_nvs_handle_t handle = settings_get_nvs_handle(SETTINGS_CORE); + + assert(key); + BT_DBG("SaveCoreSettings, Handle %lu Len %lu Key %s", handle, len, key); + return bt_mesh_save_settings(handle, key, val, len); } @@ -269,26 +287,39 @@ int bt_mesh_save_core_settings(const char *key, const uint8_t *val, size_t len) int bt_mesh_save_uid_settings(const char *key, const uint8_t *val, size_t len) { bt_mesh_nvs_handle_t handle = settings_get_nvs_handle(SETTINGS_UID); + + assert(key); + BT_DBG("SaveUIDSettings, Handle %lu Len %lu Key %s", handle, len, key); + return bt_mesh_save_settings(handle, key, val, len); } -#endif +#endif /* CONFIG_BLE_MESH_USE_MULTIPLE_NAMESPACE */ int bt_mesh_erase_settings(bt_mesh_nvs_handle_t handle, const char *key) { + assert(key); + BT_DBG("EraseSettings, Handle %lu Key %s", handle, key); + return bt_mesh_save_settings(handle, key, NULL, 0); } int bt_mesh_erase_core_settings(const char *key) { + assert(key); + BT_DBG("EraseCoreSettings, Key %s", key); + return bt_mesh_save_core_settings(key, NULL, 0); } #if CONFIG_BLE_MESH_USE_MULTIPLE_NAMESPACE int bt_mesh_erase_uid_settings(const char *name) { + assert(name); + BT_DBG("EraseUIDSettings, Name %s", name); + return bt_mesh_save_uid_settings(name, NULL, 0); } -#endif +#endif /* CONFIG_BLE_MESH_USE_MULTIPLE_NAMESPACE */ /* API used to load BLE Mesh related settings */ @@ -297,10 +328,9 @@ static int settings_load(bt_mesh_nvs_handle_t handle, const char *key, { int err = 0; - if (key == NULL || buf == NULL || exist == NULL) { - BT_ERR("%s, Invalid parameter", __func__); - return -EINVAL; - } + BT_DBG("SettingsLoad, Handle %lu Key %s", handle, key); + + assert(buf && exist); err = nvs_get_blob(handle, key, buf, &buf_len); if (err != ESP_OK) { @@ -331,6 +361,10 @@ int bt_mesh_load_settings(bt_mesh_nvs_handle_t handle, const char *key, int bt_mesh_load_core_settings(const char *key, uint8_t *buf, size_t buf_len, bool *exist) { bt_mesh_nvs_handle_t handle = settings_get_nvs_handle(SETTINGS_CORE); + + assert(key); + BT_DBG("LoadCoreSettings, Handle %lu Key %s", handle, key); + return bt_mesh_load_settings(handle, key, buf, buf_len, exist); } @@ -338,9 +372,13 @@ int bt_mesh_load_core_settings(const char *key, uint8_t *buf, size_t buf_len, bo int bt_mesh_load_uid_settings(const char *key, uint8_t *buf, size_t buf_len, bool *exist) { bt_mesh_nvs_handle_t handle = settings_get_nvs_handle(SETTINGS_UID); + + assert(key); + BT_DBG("LoadUIDSettings, Handle %lu Key %s", handle, key); + return bt_mesh_load_settings(handle, key, buf, buf_len, exist); } -#endif +#endif /* CONFIG_BLE_MESH_USE_MULTIPLE_NAMESPACE */ /* API used to get length of BLE Mesh related settings */ @@ -349,10 +387,7 @@ static size_t settings_get_length(bt_mesh_nvs_handle_t handle, const char *key) size_t len = 0U; int err = 0; - if (key == NULL) { - BT_ERR("%s, Invalid parameter", __func__); - return 0; - } + BT_DBG("SettingsGetLength, Handle %lu Key %s", handle, key); err = nvs_get_blob(handle, key, NULL, &len); if (err != ESP_OK) { @@ -362,6 +397,8 @@ static size_t settings_get_length(bt_mesh_nvs_handle_t handle, const char *key) return 0; } + BT_DBG("Len %lu", len); + return len; } @@ -419,6 +456,10 @@ struct net_buf_simple *bt_mesh_get_settings_item(bt_mesh_nvs_handle_t handle, co struct net_buf_simple *bt_mesh_get_core_settings_item(const char *key) { bt_mesh_nvs_handle_t handle = settings_get_nvs_handle(SETTINGS_CORE); + + assert(key); + BT_DBG("GetCoreSettingsItem, Handle %lu Key %s", handle, key); + return bt_mesh_get_settings_item(handle, key); } @@ -426,9 +467,13 @@ struct net_buf_simple *bt_mesh_get_core_settings_item(const char *key) struct net_buf_simple *bt_mesh_get_uid_settings_item(const char *key) { bt_mesh_nvs_handle_t handle = settings_get_nvs_handle(SETTINGS_UID); + + assert(key); + BT_DBG("GetUIDSettingsItem, Handle %lu Key %s", handle, key); + return bt_mesh_get_settings_item(handle, key); } -#endif +#endif /* CONFIG_BLE_MESH_USE_MULTIPLE_NAMESPACE */ /* API used to check if the settings item exists */ @@ -438,6 +483,8 @@ bool bt_mesh_is_settings_item_exist(struct net_buf_simple *buf, const uint16_t v size_t length = 0U; int i; + BT_DBG("IsSettingsItemExist, Val 0x%04x", val); + if (!buf) { return false; } @@ -508,6 +555,10 @@ int bt_mesh_add_settings_item(bt_mesh_nvs_handle_t handle, const char *key, cons int bt_mesh_add_core_settings_item(const char *key, const uint16_t val) { bt_mesh_nvs_handle_t handle = settings_get_nvs_handle(SETTINGS_CORE); + + assert(key); + BT_DBG("AddCoreSettingsItem, Handle %lu Val 0x%04x Key %s", handle, val, key); + return bt_mesh_add_settings_item(handle, key, val); } @@ -515,9 +566,13 @@ int bt_mesh_add_core_settings_item(const char *key, const uint16_t val) int bt_mesh_add_uid_settings_item(const char *key, const uint16_t val) { bt_mesh_nvs_handle_t handle = settings_get_nvs_handle(SETTINGS_UID); + + assert(key); + BT_DBG("AddUIDSettingsItem, Handle %lu Val 0x%04x Key %s", handle, val, key); + return bt_mesh_add_settings_item(handle, key, val); } -#endif +#endif /* CONFIG_BLE_MESH_USE_MULTIPLE_NAMESPACE */ /* API used to remove the settings item */ @@ -580,6 +635,10 @@ int bt_mesh_remove_settings_item(bt_mesh_nvs_handle_t handle, const char *key, c int bt_mesh_remove_core_settings_item(const char *key, const uint16_t val) { bt_mesh_nvs_handle_t handle = settings_get_nvs_handle(SETTINGS_CORE); + + assert(key); + BT_DBG("RemoveCoreSettingsItem, Val 0x%04x Key %s", val, key); + return bt_mesh_remove_settings_item(handle, key, val); } @@ -587,14 +646,21 @@ int bt_mesh_remove_core_settings_item(const char *key, const uint16_t val) int bt_mesh_remove_uid_settings_item(const char *key, const uint16_t val) { bt_mesh_nvs_handle_t handle = settings_get_nvs_handle(SETTINGS_UID); + + assert(key); + BT_DBG("RemoveUIDSettingsItem, Val 0x%04x Key %s", val, key); + return bt_mesh_remove_settings_item(handle, key, val); } -#endif +#endif /* CONFIG_BLE_MESH_USE_MULTIPLE_NAMESPACE */ int bt_mesh_settings_erase_key(bt_mesh_nvs_handle_t handle, const char *key) { int err = 0; + assert(key); + BT_DBG("SettingsEraseKey, Handle %lu Key %s", handle, key); + err = nvs_erase_key(handle, key); if (err != ESP_OK) { if (err == ESP_ERR_NVS_NOT_FOUND) { @@ -618,6 +684,8 @@ int bt_mesh_settings_erase_all(bt_mesh_nvs_handle_t handle) { int err = 0; + BT_DBG("SettingsEraseAll, Handle %lu", handle); + err = nvs_erase_all(handle); if (err != ESP_OK) { BT_ERR("Failed to erase all (err %d)", err); @@ -632,4 +700,5 @@ int bt_mesh_settings_erase_all(bt_mesh_nvs_handle_t handle) return 0; } + #endif /* CONFIG_BLE_MESH_SETTINGS */ diff --git a/components/bt/esp_ble_mesh/core/storage/settings_uid.c b/components/bt/esp_ble_mesh/core/storage/settings_uid.c index 511709f1ecdc..e1de639722ea 100644 --- a/components/bt/esp_ble_mesh/core/storage/settings_uid.c +++ b/components/bt/esp_ble_mesh/core/storage/settings_uid.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -38,15 +38,22 @@ static int settings_direct_erase(uint8_t index); static inline bool settings_uid_empty(struct settings_uid *uid) { - return (uid->id[0] == '\0') ? true : false; + bool empty = (uid->id[0] == '\0') ? true : false; + + BT_DBG("SettingsUIDEmpty, Empty %u", empty); + + return empty; } bt_mesh_nvs_handle_t get_core_settings_handle(void) { int i; + BT_DBG("GetCoreSettingsHandle"); + for (i = 0; i < ARRAY_SIZE(user_ids); i++) { if (user_ids[i].open) { + BT_DBG("I %u Handle %lu", i, user_ids[i].handle); return user_ids[i].handle; } } @@ -59,6 +66,8 @@ int settings_uid_init(void) { int i; + BT_DBG("SettingsUIDInit"); + for (i = 0; i < ARRAY_SIZE(user_ids); i++) { memset(&user_ids[i], 0, sizeof(struct settings_uid)); user_ids[i].handle = INVALID_SETTINGS_HANDLE; @@ -76,6 +85,8 @@ int settings_uid_load(void) int err = 0; int i; + BT_DBG("SettingsUIDLoad"); + /* Before using user id to search settings, we need to * restore all the settings user_ids properly. */ @@ -114,6 +125,8 @@ int settings_uid_deinit(bool erase) { int i; + BT_DBG("SettingsUIDDeinit, Erase %u", erase); + for (i = 0; i < ARRAY_SIZE(user_ids); i++) { memset(&user_ids[i], 0, offsetof(struct settings_uid, handle)); /* Can not reset handle here, since it will be used @@ -128,6 +141,8 @@ int settings_uid_erase(void) { int i; + BT_DBG("SettingsUIDErase"); + for (i = 0; i < ARRAY_SIZE(user_ids); i++) { if (user_ids[i].open == true) { /* When a nvs namespace is open, which means it is @@ -158,6 +173,8 @@ static int settings_direct_erase(uint8_t index) char name[16] = {'\0'}; int err = 0; + BT_DBG("SettingsDirectErase, Index %u", index); + sprintf(name, "%s_%02x", "mesh_core", index); /* Get handle for core settings */ @@ -191,6 +208,8 @@ static uint8_t settings_index_get(const char *id, uint8_t *index) uint8_t idx = 0; int i; + BT_DBG("SettingsIndexGet"); + for (i = 0; i < ARRAY_SIZE(user_ids); i++) { if (strlen(user_ids[i].id) != strlen(id)) { continue; @@ -206,6 +225,8 @@ static uint8_t settings_index_get(const char *id, uint8_t *index) idx = INVALID_SETTINGS_INDEX; } + BT_DBG("Index %u", idx); + if (index) { *index = idx; } @@ -219,6 +240,8 @@ static int settings_open(uint8_t index) int err = 0; int i; + BT_DBG("SettingsOpen, Index %u UID %s", index, uid->id); + /* Check if the nvs namespace is already open */ if (uid->open == true) { BT_WARN("Settings already open, index %d", index); @@ -251,8 +274,6 @@ static int settings_open(uint8_t index) sprintf(uid->id, "%04x", index); } - BT_INFO("Open settings, index %d, uid %s", index, uid->id); - sprintf(name, "mesh/id/%04x", index); err = bt_mesh_save_uid_settings(name, (const uint8_t *)uid->id, SETTINGS_UID_SIZE); if (err) { @@ -288,6 +309,8 @@ static int settings_open(uint8_t index) int bt_mesh_provisioner_open_settings_with_index(uint8_t index) { + BT_DBG("PvnrOpenSettingsWithIndex, Index %u", index); + if (index >= ARRAY_SIZE(user_ids)) { BT_ERR("Invalid settings index %d", index); return -EINVAL; @@ -301,6 +324,8 @@ int bt_mesh_provisioner_open_settings_with_uid(const char *id, uint8_t *index) uint8_t idx = 0; int i; + BT_DBG("PvnrOpenSettingsWithUID"); + if (!id || strlen(id) > SETTINGS_UID_SIZE) { BT_ERR("Invalid settings uid"); return -EINVAL; @@ -328,6 +353,8 @@ int bt_mesh_provisioner_open_settings_with_uid(const char *id, uint8_t *index) idx = i; } + BT_DBG("Index %u", idx); + return settings_open(idx); } @@ -337,13 +364,14 @@ static int settings_close(uint8_t index, bool erase) char name[16] = {'\0'}; int err = 0; + BT_DBG("SettingsClose"); + BT_DBG("Index %u Erase %u UID %s", index, erase, uid->id); + if (uid->open == false) { BT_ERR("Settings not open, index %d", index); return -EIO; } - BT_INFO("Close settings, index %d, uid %s", index, uid->id); - /* Disable Provisioner firstly */ err = bt_mesh_provisioner_disable(BLE_MESH_PROV_ADV | BLE_MESH_PROV_GATT); if (err && err != -EALREADY) { @@ -378,6 +406,8 @@ static int settings_close(uint8_t index, bool erase) int bt_mesh_provisioner_close_settings_with_index(uint8_t index, bool erase) { + BT_DBG("PvnrCloseSettingsWithIndex, Index %u Erase %u", index, erase); + if (index >= ARRAY_SIZE(user_ids)) { BT_ERR("Invalid settings index %d", index); return -EINVAL; @@ -390,6 +420,8 @@ int bt_mesh_provisioner_close_settings_with_uid(const char *id, bool erase, uint { uint8_t idx = 0; + BT_DBG("PvnrCloseSettingsWithUID, Erase %u", erase); + if (!id || strlen(id) > SETTINGS_UID_SIZE) { BT_ERR("Invalid settings uid"); return -EINVAL; @@ -401,6 +433,8 @@ int bt_mesh_provisioner_close_settings_with_uid(const char *id, bool erase, uint return -ENODEV; } + BT_DBG("Index %u ID %s", idx, id); + return settings_close(idx, erase); } @@ -412,13 +446,13 @@ static int settings_delete(uint8_t index) */ struct settings_uid *uid = &user_ids[index]; + BT_DBG("SettingsDelete, Index %u UID %s", index, uid->id); + if (uid->open == true) { BT_ERR("Settings being used, index %d", index); return -EBUSY; } - BT_INFO("Delete settings, index %d, uid %s", index, uid->id); - settings_direct_erase(index); memset(uid, 0, sizeof(struct settings_uid)); @@ -429,6 +463,8 @@ static int settings_delete(uint8_t index) int bt_mesh_provisioner_delete_settings_with_index(uint8_t index) { + BT_DBG("PvnrDeleteSettingsWithIndex, Index %u", index); + if (index >= ARRAY_SIZE(user_ids)) { BT_ERR("Invalid settings index %d", index); return -EINVAL; @@ -441,6 +477,8 @@ int bt_mesh_provisioner_delete_settings_with_uid(const char *id, uint8_t *index) { uint8_t idx = 0; + BT_DBG("PvnrDeleteSettingsWithUID"); + if (!id || strlen(id) > SETTINGS_UID_SIZE) { BT_ERR("Invalid settings uid"); return -EINVAL; @@ -452,16 +490,22 @@ int bt_mesh_provisioner_delete_settings_with_uid(const char *id, uint8_t *index) return -ENODEV; } + BT_DBG("Index %u ID %s", idx, id); + return settings_delete(idx); } const char *bt_mesh_provisioner_get_settings_uid(uint8_t index) { + BT_DBG("PvnrGetSettingsUID, Index %u", index); + if (index >= ARRAY_SIZE(user_ids)) { BT_ERR("Invalid settings index %d", index); return NULL; } + BT_DBG("ID %s", user_ids[index].id); + return user_ids[index].id; } @@ -469,6 +513,8 @@ uint8_t bt_mesh_provisioner_get_settings_index(const char *id) { uint8_t idx = 0; + BT_DBG("PvnrGetSettingsIndex"); + if (!id || strlen(id) > SETTINGS_UID_SIZE) { BT_ERR("Invalid settings uid"); return INVALID_SETTINGS_INDEX; @@ -479,6 +525,8 @@ uint8_t bt_mesh_provisioner_get_settings_index(const char *id) BT_ERR("Settings uid %s not exists", id); } + BT_DBG("Index %u ID %s", idx, id); + return idx; } @@ -487,12 +535,16 @@ uint8_t bt_mesh_provisioner_get_free_settings_count(void) uint8_t count = 0; int i; + BT_DBG("PvnrGetFreeSettingsCount"); + for (i = 0; i < ARRAY_SIZE(user_ids); i++) { if (settings_uid_empty(&user_ids[i])) { count++; } } + BT_DBG("Count %u", count); + return count; } #endif /* CONFIG_BLE_MESH_USE_MULTIPLE_NAMESPACE */ @@ -503,6 +555,8 @@ int bt_mesh_provisioner_direct_erase_settings(void) bt_mesh_nvs_handle_t handle = 0; int err = 0; + BT_DBG("PvnrDirectEraseSettings"); + err = bt_mesh_settings_direct_open(&handle); if (err) { return err; @@ -514,9 +568,9 @@ int bt_mesh_provisioner_direct_erase_settings(void) } bt_mesh_erase_uid_settings("mesh/uid"); -#else +#else /* CONFIG_BLE_MESH_USE_MULTIPLE_NAMESPACE */ err = bt_mesh_settings_erase_all(handle); -#endif +#endif /* CONFIG_BLE_MESH_USE_MULTIPLE_NAMESPACE */ bt_mesh_settings_direct_close(); return err; diff --git a/components/bt/esp_ble_mesh/core/test.c b/components/bt/esp_ble_mesh/core/test.c index 3d3cc3bbd902..5b47258d5fab 100644 --- a/components/bt/esp_ble_mesh/core/test.c +++ b/components/bt/esp_ble_mesh/core/test.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -41,6 +41,8 @@ int bt_mesh_device_auto_enter_network(struct bt_mesh_device_network_info *info) int i, j, k; int err = 0; + BT_DBG("DeviceAutoEnterNetwork"); + if (info == NULL || !BLE_MESH_ADDR_IS_UNICAST(info->unicast_addr) || !BLE_MESH_ADDR_IS_GROUP(info->group_addr)) { return -EINVAL; @@ -139,6 +141,8 @@ int bt_mesh_test_update_white_list(struct bt_mesh_white_list *wl) { int err = 0; + BT_DBG("TestUpdateWhiteList"); + if (wl == NULL) { BT_ERR("%s, Invalid parameter", __func__); return -EINVAL; @@ -157,7 +161,7 @@ int bt_mesh_test_update_white_list(struct bt_mesh_white_list *wl) int bt_mesh_test_start_scanning(bool wl_en) { - BT_INFO("Scan with filter policy %s", wl_en ? "enabled" : "disabled"); + BT_DBG("TestStartScanning, wl_en %u", wl_en); if (wl_en) { return bt_mesh_scan_with_wl_enable(); @@ -168,6 +172,8 @@ int bt_mesh_test_start_scanning(bool wl_en) int bt_mesh_test_stop_scanning(void) { + BT_DBG("TestStopScanning"); + return bt_mesh_scan_disable(); } #endif /* CONFIG_BLE_MESH_TEST_USE_WHITE_LIST */ @@ -181,6 +187,8 @@ void bt_mesh_test_register_net_pdu_cb(bt_mesh_test_net_pdu_cb_t cb) void bt_mesh_test_set_seq(uint32_t seq) { + BT_DBG("TestSetSeq, Seq 0x%06x", seq); + if (seq > 0xFFFFFF) { BT_ERR("Invalid SEQ 0x%08x", seq); return; diff --git a/components/bt/esp_ble_mesh/core/transport.c b/components/bt/esp_ble_mesh/core/transport.c index 33054e847c93..b4855c4d87d0 100644 --- a/components/bt/esp_ble_mesh/core/transport.c +++ b/components/bt/esp_ble_mesh/core/transport.c @@ -29,7 +29,7 @@ #if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" -#endif +#endif /* CONFIG_BLE_MESH_V11_SUPPORT */ /* The transport layer needs at least three buffers for itself to avoid * deadlocks. Ensure that there are a sufficient number of advertising @@ -58,24 +58,24 @@ _Static_assert(CONFIG_BLE_MESH_ADV_BUF_COUNT >= (CONFIG_BLE_MESH_TX_SEG_MAX + 3) /* Number of retransmit attempts (after the initial transmit) per segment */ #define SEG_RETRANSMIT_ATTEMPTS 4 +/* How long to wait for available buffers before giving up */ +#define BUF_TIMEOUT K_NO_WAIT + /* "This timer shall be set to a minimum of 200 + 50 * TTL milliseconds.". * We use 400 since 300 is a common send duration for standard HCI, and we * need to have a timeout that's bigger than that. */ #define SEG_RETRANSMIT_TIMEOUT_UNICAST(tx) (K_MSEC(400) + 50 * (tx)->ttl) + /* When sending to a group, the messages are not acknowledged, and there's no * reason to delay the repetitions significantly. Delaying by more than 0 ms * to avoid flooding the network. */ #define SEG_RETRANSMIT_TIMEOUT_GROUP K_MSEC(50) -#define SEG_RETRANSMIT_TIMEOUT(tx) \ - (BLE_MESH_ADDR_IS_UNICAST((tx)->dst) ? \ - SEG_RETRANSMIT_TIMEOUT_UNICAST(tx) : \ - SEG_RETRANSMIT_TIMEOUT_GROUP) - -/* How long to wait for available buffers before giving up */ -#define BUF_TIMEOUT K_NO_WAIT +#define SEG_RETRANSMIT_TIMEOUT(tx) (BLE_MESH_ADDR_IS_UNICAST((tx)->dst) ? \ + SEG_RETRANSMIT_TIMEOUT_UNICAST(tx) : \ + SEG_RETRANSMIT_TIMEOUT_GROUP) static struct seg_tx { struct bt_mesh_subnet *sub; @@ -145,6 +145,8 @@ static inline void bt_mesh_seg_rx_unlock(void) uint8_t bt_mesh_get_seg_rtx_num(void) { + BT_DBG("SegRTXNum %u", SEG_RETRANSMIT_ATTEMPTS); + return SEG_RETRANSMIT_ATTEMPTS; } @@ -159,75 +161,10 @@ int32_t bt_mesh_get_seg_rtx_timeout(uint16_t dst, uint8_t ttl) struct seg_tx tx = { .ttl = ttl, }; - return SEG_RETRANSMIT_TIMEOUT_UNICAST(&tx); -} -struct bt_mesh_app_key *bt_mesh_app_key_get(uint16_t app_idx) -{ - if (bt_mesh_is_provisioned()) { -#if CONFIG_BLE_MESH_NODE - if (!IS_ENABLED(CONFIG_BLE_MESH_FAST_PROV)) { - for (int i = 0; i < ARRAY_SIZE(bt_mesh.app_keys); i++) { - if (bt_mesh.app_keys[i].net_idx != BLE_MESH_KEY_UNUSED && - bt_mesh.app_keys[i].app_idx == app_idx) { - return &bt_mesh.app_keys[i]; - } - } - } else { - return bt_mesh_fast_prov_app_key_find(app_idx); - } -#endif - } else if (bt_mesh_is_provisioner_en()) { -#if CONFIG_BLE_MESH_PROVISIONER - for (int i = 0; i < ARRAY_SIZE(bt_mesh.p_app_keys); i++) { - if (bt_mesh.p_app_keys[i] && - bt_mesh.p_app_keys[i]->net_idx != BLE_MESH_KEY_UNUSED && - bt_mesh.p_app_keys[i]->app_idx == app_idx) { - return bt_mesh.p_app_keys[i]; - } - } -#endif - } - - return NULL; -} - -int bt_mesh_upper_key_get(const struct bt_mesh_subnet *subnet, uint16_t app_idx, - const uint8_t **key, uint8_t *aid, uint16_t dst) -{ - struct bt_mesh_app_key *app_key = NULL; + BT_DBG("SegRTXTimeout, TTL %u", ttl); - if (app_idx == BLE_MESH_KEY_DEV) { - *key = bt_mesh_dev_key_get(dst); - if (!*key) { - BT_ERR("DevKey of 0x%04x not found", dst); - return -EINVAL; - } - - *aid = 0U; - return 0; - } - - if (!subnet) { - BT_ERR("Invalid subnet"); - return -EINVAL; - } - - app_key = bt_mesh_app_key_get(app_idx); - if (!app_key) { - BT_ERR("AppKey 0x%04x not found", app_idx); - return -ENOENT; - } - - if (subnet->kr_phase == BLE_MESH_KR_PHASE_2 && app_key->updated) { - *key = app_key->keys[1].val; - *aid = app_key->keys[1].id; - } else { - *key = app_key->keys[0].val; - *aid = app_key->keys[0].id; - } - - return 0; + return SEG_RETRANSMIT_TIMEOUT_UNICAST(&tx); } static int send_unseg(struct bt_mesh_net_tx *tx, struct net_buf_simple *sdu, @@ -236,8 +173,10 @@ static int send_unseg(struct bt_mesh_net_tx *tx, struct net_buf_simple *sdu, { struct net_buf *buf = NULL; - BT_DBG("src 0x%04x dst 0x%04x app_idx 0x%04x sdu_len %u", - tx->src, tx->ctx->addr, tx->ctx->app_idx, sdu->len); + BT_DBG("SendUnseg"); + BT_DBG("Src 0x%04x Dst 0x%04x AppIdx 0x%04x CtlOp 0x%02x SduLen %u", + tx->src, tx->ctx->addr, tx->ctx->app_idx, + ctl_op ? *ctl_op : 0xFF, sdu->len); buf = bt_mesh_adv_create(BLE_MESH_ADV_DATA, BUF_TIMEOUT); if (!buf) { @@ -261,13 +200,14 @@ static int send_unseg(struct bt_mesh_net_tx *tx, struct net_buf_simple *sdu, if (!bt_mesh_friend_queue_has_space(tx->sub->net_idx, tx->src, tx->ctx->addr, NULL, 1)) { + BT_WARN("NoSpaceInFrndQueue, SegCount 1"); + if (BLE_MESH_ADDR_IS_UNICAST(tx->ctx->addr)) { - BT_ERR("Not enough space in Friend Queue"); + BT_ERR("NotSentToUnicast"); net_buf_unref(buf); return -ENOBUFS; } - BT_WARN("No space in Friend Queue"); goto send; } @@ -277,6 +217,8 @@ static int send_unseg(struct bt_mesh_net_tx *tx, struct net_buf_simple *sdu, /* PDUs for a specific Friend should only go * out through the Friend Queue. */ + BT_DBG("FrndTxEnqueued, SegCount 1"); + net_buf_unref(buf); send_cb_finalize(cb, cb_data); return 0; @@ -289,6 +231,8 @@ static int send_unseg(struct bt_mesh_net_tx *tx, struct net_buf_simple *sdu, static inline uint8_t seg_len(bool ctl) { + BT_DBG("Ctl %u", ctl); + if (ctl) { return BLE_MESH_CTL_SEG_SDU_MAX; } @@ -302,26 +246,31 @@ bool bt_mesh_tx_in_progress(void) for (i = 0; i < ARRAY_SIZE(seg_tx); i++) { if (seg_tx[i].nack_count) { + BT_DBG("SegTxInProgress"); return true; } } + BT_DBG("SegTxNotInProgress"); return false; } static void seg_tx_done(struct seg_tx *tx, uint8_t seg_idx) { + BT_DBG("SegTxDone, SegIdx %u", seg_idx); bt_mesh_adv_buf_ref_debug(__func__, tx->seg[seg_idx], 3U, BLE_MESH_BUF_REF_SMALL); - /** - * When cancelling a segment that is still in the adv sending queue, `tx->seg_pending` - * must else be decremented by one. More detailed information - * can be found in BLEMESH24-26. + /* When cancelling a segment that is still in the adv sending queue, + * the `tx->seg_pending` must be decremented by one. + * More details could be found in BLEMESH24-26. */ if (bt_mesh_atomic_cas(&BLE_MESH_ADV_BUSY(tx->seg[seg_idx]), 1, 0)) { + BT_DBG("SegPendingDec %u", tx->seg_pending); tx->seg_pending--; } + BT_DBG("NackCountDec %u", tx->nack_count); + net_buf_unref(tx->seg[seg_idx]); tx->seg[seg_idx] = NULL; tx->nack_count--; @@ -331,6 +280,8 @@ static void seg_tx_reset(struct seg_tx *tx) { int i; + BT_DBG("SegTxReset"); + bt_mesh_seg_tx_lock(tx); k_delayed_work_cancel(&tx->rtx_timer); @@ -355,6 +306,7 @@ static void seg_tx_reset(struct seg_tx *tx) if (bt_mesh_atomic_test_and_clear_bit(bt_mesh.flags, BLE_MESH_IVU_PENDING)) { BT_DBG("Proceeding with pending IV Update"); + /* bt_mesh_net_iv_update() will re-enable the flag if this * wasn't the only transfer. */ @@ -369,6 +321,8 @@ static inline void seg_tx_complete(struct seg_tx *tx, int err) const struct bt_mesh_send_cb *cb = tx->cb; void *cb_data = tx->cb_data; + BT_DBG("SegTxComplete, Err %d", err); + seg_tx_reset(tx); /* TODO: notify the completion of sending segmented message */ @@ -380,35 +334,43 @@ static inline void seg_tx_complete(struct seg_tx *tx, int err) static void schedule_retransmit(struct seg_tx *tx) { - bt_mesh_seg_tx_lock(tx); - /* It's possible that a segment broadcast hasn't finished, - * but the tx are already released. Only the seg_pending - * of this segment remains unprocessed. So, here, we - * determine if the tx are released by checking if the - * destination (dst) is unassigned, and then process - * the seg_pending of this segment. + /* It's possible that a segment broadcast hasn't finished, but the tx + * has already been released. Only the seg_pending of this segment + * remains unprocessed. + * So, here we determine if the tx are released by checking if the + * destination (dst) is unassigned, and then process the seg_pending + * of this segment. * See BLEMESH25-92 for details */ + + BT_DBG("ScheduleRetransmit, Dst 0x%04x", tx->dst); + + bt_mesh_seg_tx_lock(tx); + if (tx->dst == BLE_MESH_ADDR_UNASSIGNED) { + BT_DBG("SegPending %u", tx->seg_pending); + if (tx->seg_pending) { tx->seg_pending--; } - bt_mesh_seg_tx_unlock(tx); - return; + goto end; } + BT_DBG("SegPending %u Attempts %u", tx->seg_pending, tx->attempts); + if (--tx->seg_pending) { - bt_mesh_seg_tx_unlock(tx); - return; + goto end; } if (!BLE_MESH_ADDR_IS_UNICAST(tx->dst) && !tx->attempts) { - BT_INFO("Complete tx sdu to group"); + BT_INFO("TxSduToGroupDone"); + seg_tx_complete(tx, 0); - bt_mesh_seg_tx_unlock(tx); - return; + goto end; } k_delayed_work_submit(&tx->rtx_timer, SEG_RETRANSMIT_TIMEOUT(tx)); + +end: bt_mesh_seg_tx_unlock(tx); } @@ -416,6 +378,8 @@ static void seg_first_send_start(uint16_t duration, int err, void *user_data) { struct seg_tx *tx = user_data; + BT_DBG("SegFirstSendStart, Err %d", err); + if (tx->cb && tx->cb->start) { tx->cb->start(duration, err, tx->cb_data); } @@ -425,6 +389,8 @@ static void seg_send_start(uint16_t duration, int err, void *user_data) { struct seg_tx *tx = user_data; + BT_DBG("SegSendStart, Err %d", err); + /* If there's an error in transmitting the 'sent' callback will never * be called. Make sure that we kick the retransmit timer also in this * case since otherwise we risk the transmission of becoming stale. @@ -438,6 +404,8 @@ static void seg_sent(int err, void *user_data) { struct seg_tx *tx = user_data; + BT_DBG("SegSent, Err %d", err); + schedule_retransmit(tx); } @@ -455,17 +423,19 @@ static void seg_tx_send_unacked(struct seg_tx *tx) { int i, err = 0; + BT_DBG("SegTxSendUnacked, Attempts %u", tx->attempts); + bt_mesh_seg_tx_lock(tx); if (!(tx->attempts--)) { BT_WARN("Ran out of retransmit attempts"); + bt_mesh_seg_tx_unlock(tx); + seg_tx_complete(tx, -ETIMEDOUT); return; } - BT_INFO("Attempts: %u", tx->attempts); - for (i = 0; i <= tx->seg_n; i++) { struct net_buf *seg = tx->seg[i]; @@ -478,9 +448,10 @@ static void seg_tx_send_unacked(struct seg_tx *tx) continue; } - tx->seg_pending++; + BT_INFO("SegPendingInc %u", tx->seg_pending); + BT_INFO("SegResend %u/%u Cred %u", i, tx->seg_n, tx->cred); - BT_INFO("Resending %u/%u, cred 0x%02x", i, tx->seg_n, tx->cred); + tx->seg_pending++; /* TODO: * tx->new_key should be replaced with sub->kr_flag, @@ -491,8 +462,10 @@ static void seg_tx_send_unacked(struct seg_tx *tx) &tx->cred, tx->tag, &seg_sent_cb, tx); if (err) { - BT_ERR("Sending segment failed"); + BT_ERR("ResendSegFailed, Err %d", err); + bt_mesh_seg_tx_unlock(tx); + seg_tx_complete(tx, -EIO); return; } @@ -505,6 +478,8 @@ static void seg_retransmit(struct k_work *work) { struct seg_tx *tx = CONTAINER_OF(work, struct seg_tx, rtx_timer); + BT_DBG("SegRetransmit"); + seg_tx_send_unacked(tx); } @@ -519,20 +494,24 @@ static int send_seg(struct bt_mesh_net_tx *net_tx, struct net_buf_simple *sdu, int err = 0; int i; - BT_DBG("src 0x%04x dst 0x%04x app_idx 0x%04x aszmic %u sdu_len %u", + BT_DBG("SendSeg"); + BT_DBG("Src 0x%04x Dst 0x%04x AppIdx 0x%04x Aszmic %u SduLen %u", net_tx->src, net_tx->ctx->addr, net_tx->ctx->app_idx, net_tx->aszmic, sdu->len); for (tx = NULL, i = 0; i < ARRAY_SIZE(seg_tx); i++) { - if (!seg_tx[i].nack_count && - /* In some critical conditions, the tx might be - * reset before a segment broadcast is finished. - * If this happens, the seg_pending of the segment - * hasn't been processed. To avoid assigning this - * uncleared tx to a new message, extra checks for - * seg_pending being 0 are added. See BLEMESH25-92 - * for details.*/ - !seg_tx[i].seg_pending) { + /* In some critical conditions, the tx might be reset before + * a segment transmission is finished. + * If this happens, the seg_pending of the segment will not + * be processed. + * And to avoid assigning this uncleared tx to a new message, + * extra checks for seg_pending being 0 are added. + * See BLEMESH25-92 for details. + */ + BT_DBG("Seg%u: NackCount %u SegPending %u", + i, seg_tx[i].nack_count, seg_tx[i].seg_pending); + + if (!seg_tx[i].nack_count && !seg_tx[i].seg_pending) { tx = &seg_tx[i]; break; } @@ -576,15 +555,16 @@ static int send_seg(struct bt_mesh_net_tx *net_tx, struct net_buf_simple *sdu, seq_zero = tx->seq_auth & TRANS_SEQ_ZERO_MASK; - BT_DBG("SeqZero 0x%04x", seq_zero); + BT_DBG("SegHdr 0x%02x SegN %u NackCount %u NewKey %u TTL %u SeqZero 0x%04x", + seg_hdr, tx->seg_n, tx->nack_count, tx->new_key, tx->ttl, seq_zero); if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND) && !bt_mesh_friend_queue_has_space(tx->sub->net_idx, net_tx->src, tx->dst, &tx->seq_auth, tx->seg_n + 1) && BLE_MESH_ADDR_IS_UNICAST(tx->dst)) { - BT_ERR("Not enough space in Friend Queue for %u segments", - tx->seg_n + 1); + BT_WARN("NoSpaceInFrndQueue, SegCount %u", tx->seg_n + 1); + seg_tx_reset(tx); return -ENOBUFS; } @@ -621,6 +601,8 @@ static int send_seg(struct bt_mesh_net_tx *net_tx, struct net_buf_simple *sdu, type = BLE_MESH_FRIEND_PDU_PARTIAL; } + BT_DBG("FrndPDUType %u", type); + if (bt_mesh_friend_enqueue_tx(net_tx, type, &tx->seq_auth, tx->seg_n + 1, @@ -629,6 +611,8 @@ static int send_seg(struct bt_mesh_net_tx *net_tx, struct net_buf_simple *sdu, /* PDUs for a specific Friend should only go * out through the Friend Queue. */ + BT_DBG("FrndTxEnqueued, SegCount %u", tx->seg_n + 1); + net_buf_unref(seg); continue; } @@ -636,14 +620,16 @@ static int send_seg(struct bt_mesh_net_tx *net_tx, struct net_buf_simple *sdu, tx->seg[seg_o] = net_buf_ref(seg); - BT_DBG("Sending %u/%u", seg_o, tx->seg_n); + BT_INFO("SegPendingInc %u", tx->seg_pending); + BT_INFO("SegSend %u/%u Cred %u", seg_o, tx->seg_n, tx->cred); + tx->seg_pending++; err = bt_mesh_net_send(net_tx, seg, seg_o ? &seg_sent_cb : &first_sent_cb, tx); if (err) { - BT_ERR("Sending segment failed (err %d)", err); + BT_ERR("SendSegFailed, Err %d", err); break; } @@ -652,6 +638,7 @@ static int send_seg(struct bt_mesh_net_tx *net_tx, struct net_buf_simple *sdu, * which will be used for retransmission later. */ if (tx->cred != net_tx->ctx->send_cred) { + BT_INFO("OldCred %u NewCred %u", tx->cred, net_tx->ctx->send_cred); tx->cred = net_tx->ctx->send_cred; } } @@ -665,7 +652,10 @@ static int send_seg(struct bt_mesh_net_tx *net_tx, struct net_buf_simple *sdu, /* This can happen if segments only went into the Friend Queue */ if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND) && !tx->seg[0]) { + BT_DBG("OnlyToFrndQueue"); + seg_tx_reset(tx); + /* If there was a callback notify sending immediately since * there's no other way to track this (at least currently) * with the Friend Queue. @@ -689,6 +679,8 @@ int bt_mesh_trans_send(struct bt_mesh_net_tx *tx, struct net_buf_simple *msg, uint8_t aid = 0U; int err = 0; + BT_DBG("transcend"); + if (msg->len < 1) { BT_ERR("Zero-length SDU not allowed"); return -EINVAL; @@ -698,9 +690,9 @@ int bt_mesh_trans_send(struct bt_mesh_net_tx *tx, struct net_buf_simple *msg, tx->ctx->send_tag |= BLE_MESH_TAG_SEND_SEGMENTED; } - BT_DBG("net_idx 0x%04x app_idx 0x%04x dst 0x%04x", tx->sub->net_idx, - tx->ctx->app_idx, tx->ctx->addr); - BT_DBG("len %u: %s", msg->len, bt_hex(msg->data, msg->len)); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Dst 0x%04x", + tx->sub->net_idx, tx->ctx->app_idx, tx->ctx->addr); + BT_DBG("Len %u: %s", msg->len, bt_hex(msg->data, msg->len)); err = bt_mesh_upper_key_get(tx->sub, tx->ctx->app_idx, &key, &aid, tx->ctx->addr); @@ -718,7 +710,7 @@ int bt_mesh_trans_send(struct bt_mesh_net_tx *tx, struct net_buf_simple *msg, tx->aszmic = 1U; } - BT_INFO("%s, send_tag 0x%02x, send_szmic %d, aszmic %d", + BT_INFO("%s, Tag 0x%02x Szmic %u Aszmic %u", bt_mesh_tag_send_segmented(tx->ctx->send_tag) ? "Seg" : "Unseg", tx->ctx->send_tag, tx->ctx->send_szmic, tx->aszmic); @@ -733,7 +725,7 @@ int bt_mesh_trans_send(struct bt_mesh_net_tx *tx, struct net_buf_simple *msg, tx->ctx->addr, bt_mesh.seq, BLE_MESH_NET_IVI_TX); if (err) { - BT_ERR("Encrypt failed (err %d)", err); + BT_ERR("AppEncryptFailed, Err %d", err); return err; } @@ -747,7 +739,7 @@ int bt_mesh_trans_send(struct bt_mesh_net_tx *tx, struct net_buf_simple *msg, static void revoke_dev_key(const uint8_t *dev_key) { if (!memcmp(dev_key, bt_mesh.dev_key_ca, 16)) { - BT_INFO("Revoke Device Key"); + BT_INFO("RevokeDevKey"); memcpy(bt_mesh.dev_key, bt_mesh.dev_key_ca, 16); memset(bt_mesh.dev_key_ca, 0, 16); @@ -768,8 +760,9 @@ static int sdu_recv(struct bt_mesh_net_rx *rx, uint32_t seq, uint8_t hdr, size_t i = 0U; int err = 0; - BT_DBG("ASZMIC %u AKF %u AID 0x%02x", aszmic, AKF(&hdr), AID(&hdr)); - BT_DBG("len %u: %s", buf->len, bt_hex(buf->data, buf->len)); + BT_DBG("SduRecv"); + BT_DBG("Aszmic %u AKF %u AID 0x%02x", aszmic, AKF(&hdr), AID(&hdr)); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); if (buf->len < 1 + APP_MIC_LEN(aszmic)) { BT_ERR("Too short SDU + MIC (len %u)", buf->len); @@ -808,7 +801,7 @@ static int sdu_recv(struct bt_mesh_net_rx *rx, uint32_t seq, uint8_t hdr, dev_key = bt_mesh_rx_devkey_get(i, rx->ctx.addr); if (!dev_key) { - BT_DBG("DevKey not found"); + BT_DBG("DevKeyNotFound"); continue; } @@ -819,6 +812,7 @@ static int sdu_recv(struct bt_mesh_net_rx *rx, uint32_t seq, uint8_t hdr, rx->ctx.recv_dst, seq, BLE_MESH_NET_IVI_RX(rx)); if (err) { + BT_DBG("DevKeyNotDecrypt"); continue; } @@ -844,6 +838,7 @@ static int sdu_recv(struct bt_mesh_net_rx *rx, uint32_t seq, uint8_t hdr, } BT_WARN("Unable to decrypt with DevKey"); + bt_mesh_free_buf(sdu); return -ENODEV; } @@ -856,7 +851,7 @@ static int sdu_recv(struct bt_mesh_net_rx *rx, uint32_t seq, uint8_t hdr, key = bt_mesh_rx_appkey_get(i); if (!key) { - BT_DBG("AppKey not found"); + BT_DBG("AppKeyNotFound"); continue; } @@ -890,8 +885,7 @@ static int sdu_recv(struct bt_mesh_net_rx *rx, uint32_t seq, uint8_t hdr, bt_hex(sdu->data, sdu->len)); if (err) { - BT_DBG("Unable to decrypt with AppKey 0x%03x", - key->app_idx); + BT_DBG("AppKeyNotDecrypt, AppIdx 0x%04x", key->app_idx); continue; } @@ -903,8 +897,9 @@ static int sdu_recv(struct bt_mesh_net_rx *rx, uint32_t seq, uint8_t hdr, } if (rx->local_match) { - BT_WARN("No matching AppKey"); + BT_WARN("NoMatchAppKey"); } + bt_mesh_free_buf(sdu); return 0; } @@ -914,6 +909,8 @@ static struct seg_tx *seg_tx_lookup(uint16_t seq_zero, uint8_t obo, uint16_t add struct seg_tx *tx = NULL; int i; + BT_DBG("SegTxLookup, SeqZero 0x%04x OBO %u Addr 0x%04x", seq_zero, obo, addr); + for (i = 0; i < ARRAY_SIZE(seg_tx); i++) { tx = &seg_tx[i]; @@ -922,6 +919,7 @@ static struct seg_tx *seg_tx_lookup(uint16_t seq_zero, uint8_t obo, uint16_t add } if (tx->dst == addr) { + BT_DBG("SegTxFound, Dst 0x%04x", addr); return tx; } @@ -931,6 +929,7 @@ static struct seg_tx *seg_tx_lookup(uint16_t seq_zero, uint8_t obo, uint16_t add * responding and therefore accept the message. */ if (obo && tx->nack_count == tx->seg_n + 1) { + BT_DBG("SegTxOboFound, Dst 0x%04x", addr); tx->dst = addr; return tx; } @@ -943,11 +942,13 @@ static int trans_ack(struct bt_mesh_net_rx *rx, uint8_t hdr, struct net_buf_simple *buf, uint64_t *seq_auth) { struct seg_tx *tx = NULL; + uint16_t seq_zero = 0U; unsigned int bit = 0; uint32_t ack = 0U; - uint16_t seq_zero = 0U; uint8_t obo = 0U; + BT_DBG("TransAck"); + if (buf->len != 6) { BT_ERR("Malformed Segment Ack (len %u)", buf->len); return -EINVAL; @@ -966,7 +967,7 @@ static int trans_ack(struct bt_mesh_net_rx *rx, uint8_t hdr, ack = net_buf_simple_pull_be32(buf); - BT_DBG("OBO %u seq_zero 0x%04x ack 0x%08x", obo, seq_zero, ack); + BT_DBG("OBO %u SeqZero 0x%04x Ack 0x%08lx", obo, seq_zero, ack); tx = seg_tx_lookup(seq_zero, obo, rx->ctx.addr); if (!tx) { @@ -997,6 +998,7 @@ static int trans_ack(struct bt_mesh_net_rx *rx, uint8_t hdr, while ((bit = find_lsb_set(ack))) { if (tx->seg[bit - 1]) { BT_INFO("Seg %u/%u acked", bit - 1, tx->seg_n); + bt_mesh_seg_tx_lock(tx); seg_tx_done(tx, bit - 1); bt_mesh_seg_tx_unlock(tx); @@ -1021,6 +1023,8 @@ static int trans_heartbeat(struct bt_mesh_net_rx *rx, uint8_t init_ttl = 0U, hops = 0U; uint16_t feat = 0U; + BT_DBG("TransHeartbeat"); + if (buf->len != 3) { BT_ERR("Malformed heartbeat message (len %u)", buf->len); return -EINVAL; @@ -1037,9 +1041,8 @@ static int trans_heartbeat(struct bt_mesh_net_rx *rx, hops = (init_ttl - rx->ctx.recv_ttl + 1); - BT_INFO("src 0x%04x TTL %u InitTTL %u (%u hop%s) feat 0x%04x", - rx->ctx.addr, rx->ctx.recv_ttl, init_ttl, hops, - (hops == 1U) ? "" : "s", feat); + BT_INFO("Src 0x%04x TTL %u InitTTL %u Hops %u Feat 0x%04x", + rx->ctx.addr, rx->ctx.recv_ttl, init_ttl, hops, feat); if (IS_ENABLED(CONFIG_BLE_MESH_NODE) && bt_mesh_is_provisioned()) { bt_mesh_heartbeat_recv(rx->ctx.addr, rx->ctx.recv_dst, hops, feat); @@ -1057,7 +1060,7 @@ static int ctl_recv(struct bt_mesh_net_rx *rx, uint8_t hdr, { uint8_t ctl_op = TRANS_CTL_OP(&hdr); - BT_DBG("OpCode 0x%02x len %u", ctl_op, buf->len); + BT_DBG("CTLRecv, OpCode 0x%02x Len %u", ctl_op, buf->len); BT_BQB(BLE_MESH_BQB_TEST_LOG_LEVEL_PRIMARY_ID_NODE | \ BLE_MESH_BQB_TEST_LOG_LEVEL_SUB_ID_TNPT, @@ -1074,6 +1077,7 @@ static int ctl_recv(struct bt_mesh_net_rx *rx, uint8_t hdr, /* Only acks and heartbeats may need processing without local_match */ if (!rx->local_match) { + BT_DBG("LocalNotMatch"); return 0; } @@ -1088,7 +1092,7 @@ static int ctl_recv(struct bt_mesh_net_rx *rx, uint8_t hdr, case TRANS_CTL_OP_PATH_REQ_SOLIC: return bt_mesh_directed_forwarding_ctl_recv(ctl_op, rx, buf); } -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND) && !bt_mesh_lpn_established()) { switch (ctl_op) { @@ -1141,7 +1145,7 @@ static int trans_unseg(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx, { uint8_t hdr = 0U; - BT_DBG("AFK %u AID 0x%02x", AKF(buf->data), AID(buf->data)); + BT_DBG("TransUnseg, AKF %u AID 0x%02x", AKF(buf->data), AID(buf->data)); if (buf->len < 1) { BT_ERR("Too small unsegmented PDU"); @@ -1149,7 +1153,7 @@ static int trans_unseg(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx, } if (bt_mesh_rpl_check(rx, NULL)) { - BT_WARN("Replay: src 0x%04x dst 0x%04x seq 0x%06x", + BT_WARN("Replay, Src 0x%04x Dst 0x%04x Seq 0x%06x", rx->ctx.addr, rx->ctx.recv_dst, rx->seq); return -EINVAL; } @@ -1162,6 +1166,7 @@ static int trans_unseg(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx, /* SDUs must match a local element or an LPN of this Friend. */ if (!rx->local_match && !rx->friend_match) { + BT_DBG("LocalAndFrndNotMatch"); return 0; } @@ -1187,6 +1192,8 @@ static inline int32_t ack_timeout(struct seg_rx *rx) /* 100 ms for every not yet received segment */ to += K_MSEC(((rx->seg_n + 1) - popcount(rx->block)) * 100U); + BT_DBG("AckTimeout, TTL %u TO %ld", ttl, to); + /* Make sure we don't send more frequently than the duration for * each packet (default is 300ms). */ @@ -1199,6 +1206,8 @@ int bt_mesh_ctl_send(struct bt_mesh_net_tx *tx, uint8_t ctl_op, void *data, { struct net_buf_simple buf = {0}; + BT_DBG("CtlSend"); + net_buf_simple_init_with_data(&buf, data, data_len); if (data_len > BLE_MESH_SDU_UNSEG_MAX) { @@ -1208,9 +1217,9 @@ int bt_mesh_ctl_send(struct bt_mesh_net_tx *tx, uint8_t ctl_op, void *data, /* Set app_idx to unused here since CTL is only encrypted with NetKey */ tx->ctx->app_idx = BLE_MESH_KEY_UNUSED; - BT_DBG("src 0x%04x dst 0x%04x ttl 0x%02x ctl 0x%02x", tx->src, - tx->ctx->addr, tx->ctx->send_ttl, ctl_op); - BT_DBG("len %zu: %s", data_len, bt_hex(data, data_len)); + BT_DBG("Src 0x%04x Dst 0x%04x TTL 0x%02x CTL 0x%02x", + tx->src, tx->ctx->addr, tx->ctx->send_ttl, ctl_op); + BT_DBG("Len %u: %s", data_len, bt_hex(data, data_len)); if (bt_mesh_tag_send_segmented(tx->ctx->send_tag)) { return send_seg(tx, &buf, cb, cb_data, &ctl_op); @@ -1242,7 +1251,7 @@ static int send_ack(struct bt_mesh_subnet *sub, uint16_t src, uint16_t dst, uint16_t seq_zero = *seq_auth & TRANS_SEQ_ZERO_MASK; uint8_t buf[6] = {0}; - BT_DBG("SeqZero 0x%04x Block 0x%08x OBO %u", seq_zero, block, obo); + BT_DBG("SendAck, SeqZero 0x%04x Block 0x%08lx OBO %u", seq_zero, block, obo); if (bt_mesh_lpn_established()) { BT_WARN("Not sending ack when LPN is enabled"); @@ -1266,6 +1275,8 @@ static int send_ack(struct bt_mesh_subnet *sub, uint16_t src, uint16_t dst, static void seg_rx_reset(struct seg_rx *rx, bool full_reset) { + BT_DBG("SegRxReset, FullReset %u", full_reset); + bt_mesh_seg_rx_lock(); k_delayed_work_cancel(&rx->ack_timer); @@ -1310,6 +1321,8 @@ static uint32_t incomplete_timeout(struct seg_rx *rx) /* The less segments being received, the shorter timeout will be used. */ timeout += K_MSEC(ttl * popcount(rx->block) * 100U); + BT_DBG("IncompleteTimeout %lu", timeout); + return MIN(timeout, K_SECONDS(60)); } @@ -1317,11 +1330,15 @@ static void seg_ack(struct k_work *work) { struct seg_rx *rx = CONTAINER_OF(work, struct seg_rx, ack_timer); + BT_DBG("SegAck, Last %lu", rx->last); + bt_mesh_seg_rx_lock(); if (k_uptime_get_32() - rx->last > incomplete_timeout(rx)) { BT_WARN("Incomplete timer expired"); + bt_mesh_seg_rx_unlock(); + seg_rx_reset(rx, false); return; } @@ -1365,9 +1382,9 @@ static struct seg_rx *seg_rx_find(struct bt_mesh_net_rx *net_rx, */ #if CONFIG_BLE_MESH_DISCARD_OLD_SEQ_AUTH if (rx->seq_auth >= *seq_auth) { -#else +#else /* CONFIG_BLE_MESH_DISCARD_OLD_SEQ_AUTH */ if (rx->seq_auth == *seq_auth) { -#endif +#endif /* CONFIG_BLE_MESH_DISCARD_OLD_SEQ_AUTH */ return rx; } @@ -1390,6 +1407,8 @@ static struct seg_rx *seg_rx_find(struct bt_mesh_net_rx *net_rx, static bool seg_rx_is_valid(struct seg_rx *rx, struct bt_mesh_net_rx *net_rx, const uint8_t *hdr, uint8_t seg_n) { + BT_DBG("IsSegRxValid"); + if (rx->hdr != *hdr || rx->seg_n != seg_n) { BT_ERR("Invalid segment for ongoing session"); return false; @@ -1454,18 +1473,20 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, uint8_t seg_o = 0U; int err = 0; + BT_DBG("TransSeg"); + if (buf->len < 5) { BT_ERR("Too short segmented message (len %u)", buf->len); return -EINVAL; } if (bt_mesh_rpl_check(net_rx, &rpl)) { - BT_WARN("Replay: src 0x%04x dst 0x%04x seq 0x%06x", + BT_WARN("Replay, Src 0x%04x Dst 0x%04x Seq 0x%06x", net_rx->ctx.addr, net_rx->ctx.recv_dst, net_rx->seq); return -EINVAL; } - BT_DBG("ASZMIC %u AKF %u AID 0x%02x", ASZMIC(hdr), AKF(hdr), AID(hdr)); + BT_DBG("Aszmic %u AKF %u AID 0x%02x", ASZMIC(hdr), AKF(hdr), AID(hdr)); net_buf_simple_pull(buf, 1); @@ -1502,13 +1523,15 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, *seg_count = seg_n + 1; + BT_DBG("Src 0x%04x Dst 0x%04x SeqAuth 0x%llx SegCount %u", + net_rx->ctx.addr, net_rx->ctx.recv_dst, *seq_auth, *seg_count); + /* Look for old RX sessions */ rx = seg_rx_find(net_rx, seq_auth); if (rx) { /* Discard old SeqAuth packet */ if (rx->seq_auth > *seq_auth) { - BT_WARN("Ignoring old SeqAuth, src 0x%04x, dst 0x%04x", - rx->src, rx->dst); + BT_WARN("SeqAuth 0x%llx vs. 0x%llx", rx->seq_auth, *seq_auth); return -EINVAL; } @@ -1523,6 +1546,7 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, if (rx->block == BLOCK_COMPLETE(rx->seg_n)) { BT_INFO("Got segment for already complete SDU"); + send_ack(net_rx->sub, net_rx->ctx.recv_dst, net_rx->ctx.addr, net_rx->ctx.send_ttl, seq_auth, rx->block, rx->obo); @@ -1560,10 +1584,11 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, net_rx->ctx.addr, net_rx->ctx.recv_dst, seq_auth, *seg_count)) { - BT_ERR("No space in Friend Queue for %u segments", *seg_count); - send_ack(net_rx->sub, net_rx->ctx.recv_dst, net_rx->ctx.addr, - net_rx->ctx.send_ttl, seq_auth, 0, - net_rx->friend_match); + BT_WARN("NoSpaceInFrndQueue, SegCount %u", *seg_count); + + send_ack(net_rx->sub, net_rx->ctx.recv_dst, + net_rx->ctx.addr, net_rx->ctx.send_ttl, + seq_auth, 0, net_rx->friend_match); return -ENOBUFS; } @@ -1574,7 +1599,7 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, * eventually be freed up and we'll be able to process * this one. */ - BT_WARN("No free slots for new incoming segmented messages, src: %04x", net_rx->ctx.addr); + BT_WARN("SegRxFull, Src %04x", net_rx->ctx.addr); return -ENOMEM; } @@ -1601,7 +1626,9 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, send_ack(net_rx->sub, net_rx->ctx.recv_dst, net_rx->ctx.addr, net_rx->ctx.send_ttl, seq_auth, 0, rx->obo); + seg_rx_reset(rx, true); + return -EMSGSIZE; } } else { @@ -1628,6 +1655,7 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, rx->block |= BIT(seg_o); if (rx->block != BLOCK_COMPLETE(seg_n)) { + BT_DBG("FrndPDUPartial"); *pdu_type = BLE_MESH_FRIEND_PDU_PARTIAL; return 0; } @@ -1648,8 +1676,8 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, if (net_rx->ctl) { err = ctl_recv(net_rx, *hdr, &rx->buf, seq_auth); } else { - err = sdu_recv(net_rx, (rx->seq_auth & 0xffffff), *hdr, - ASZMIC(hdr), &rx->buf); + err = sdu_recv(net_rx, (rx->seq_auth & 0xffffff), + *hdr, ASZMIC(hdr), &rx->buf); } seg_rx_reset(rx, false); @@ -1659,12 +1687,14 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, int bt_mesh_trans_recv(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx) { - uint64_t seq_auth = TRANS_SEQ_AUTH_NVAL; enum bt_mesh_friend_pdu_type pdu_type = BLE_MESH_FRIEND_PDU_SINGLE; struct net_buf_simple_state state = {0}; + uint64_t seq_auth = TRANS_SEQ_AUTH_NVAL; uint8_t seg_count = 0U; int err = 0; + BT_DBG("TransRecv"); + if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND)) { rx->friend_match = bt_mesh_friend_match(rx->sub->net_idx, rx->ctx.recv_dst); @@ -1672,20 +1702,21 @@ int bt_mesh_trans_recv(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx) rx->friend_match = false; } - BT_DBG("src 0x%04x dst 0x%04x seq 0x%08x friend_match %u", + BT_DBG("Src 0x%04x Dst 0x%04x Seq 0x%06x FrndMatch %u", rx->ctx.addr, rx->ctx.recv_dst, rx->seq, rx->friend_match); /* Remove network headers */ net_buf_simple_pull(buf, BLE_MESH_NET_HDR_LEN); - BT_DBG("Payload %s", bt_hex(buf->data, buf->len)); + BT_DBG("PDU %u %s", buf->len, bt_hex(buf->data, buf->len)); /* If LPN mode is enabled messages are only accepted when we've * requested the Friend to send them. The messages must also * be encrypted using the Friend Credentials. */ if (IS_ENABLED(CONFIG_BLE_MESH_LOW_POWER) && - bt_mesh_lpn_established() && rx->net_if == BLE_MESH_NET_IF_ADV && + bt_mesh_lpn_established() && + rx->net_if == BLE_MESH_NET_IF_ADV && (!bt_mesh_lpn_waiting_update() || rx->ctx.recv_cred != BLE_MESH_FRIENDSHIP_CRED)) { BT_WARN("Ignoring unexpected message in Low Power mode"); @@ -1702,12 +1733,14 @@ int bt_mesh_trans_recv(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx) * LPN of this Friend. */ if (!rx->local_match && !rx->friend_match) { + BT_DBG("LocalAndFrndNotMatch"); return 0; } err = trans_seg(buf, rx, &pdu_type, &seq_auth, &seg_count); } else { seg_count = 1U; + err = trans_unseg(buf, rx, &seq_auth); } @@ -1747,6 +1780,8 @@ void bt_mesh_rx_reset(void) { int i; + BT_DBG("RxReset"); + for (i = 0; i < ARRAY_SIZE(seg_rx); i++) { seg_rx_reset(&seg_rx[i], true); } @@ -1756,6 +1791,8 @@ void bt_mesh_tx_reset(void) { int i; + BT_DBG("TxReset"); + for (i = 0; i < ARRAY_SIZE(seg_tx); i++) { seg_tx_reset(&seg_tx[i]); } @@ -1765,6 +1802,8 @@ void bt_mesh_rx_reset_single(uint16_t src) { int i; + BT_DBG("RxResetSingle, Src 0x%04x", src); + if (!BLE_MESH_ADDR_IS_UNICAST(src)) { return; } @@ -1781,6 +1820,8 @@ void bt_mesh_tx_reset_single(uint16_t dst) { int i; + BT_DBG("TxResetSingle, Dst 0x%04x", dst); + if (!BLE_MESH_ADDR_IS_UNICAST(dst)) { return; } diff --git a/components/bt/esp_ble_mesh/core/transport.enh.c b/components/bt/esp_ble_mesh/core/transport.enh.c index a4a5130e2150..00caddac31a8 100644 --- a/components/bt/esp_ble_mesh/core/transport.enh.c +++ b/components/bt/esp_ble_mesh/core/transport.enh.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -141,121 +141,93 @@ static inline void bt_mesh_seg_rx_unlock(void) uint8_t bt_mesh_seg_send_interval(void) { - return (bt_mesh_get_sar_sis() + 1) * 10; + uint8_t interval = (bt_mesh_get_sar_sis() + 1) * 10; + + BT_DBG("SegSendInterval %u", interval); + + return interval; } uint8_t bt_mesh_get_seg_rtx_num(void) { - return bt_mesh_get_sar_urc(); + uint8_t num = bt_mesh_get_sar_urc(); + + BT_DBG("SegRTXNum %u", num); + + return num; } int32_t bt_mesh_seg_rtx_interval(uint16_t dst, uint8_t ttl) { + int32_t interval = 0; + if (BLE_MESH_ADDR_IS_UNICAST(dst)) { if (ttl == 0) { - return (bt_mesh_get_sar_uris() + 1) * 25; + interval = (bt_mesh_get_sar_uris() + 1) * 25; + } else { + interval = ((bt_mesh_get_sar_uris() + 1) * 25 + + (bt_mesh_get_sar_urii() + 1) * 25 * (ttl - 1)); } - - return ((bt_mesh_get_sar_uris() + 1) * 25 + - (bt_mesh_get_sar_urii() + 1) * 25 * (ttl - 1)); + } else { + interval = (bt_mesh_get_sar_mris() + 1) * 25; } - return (bt_mesh_get_sar_mris() + 1) * 25; + BT_DBG("SegRTXInterval %ld, Dst 0x%04x TTL %u", interval, dst, ttl); + + return interval; } int32_t bt_mesh_get_seg_rtx_timeout(uint16_t dst, uint8_t ttl) { - return bt_mesh_seg_rtx_interval(dst, ttl); + int32_t timeout = bt_mesh_seg_rtx_interval(dst, ttl); + + BT_DBG("SegRTXTimeout %ld, Dst 0x%04x TTL %u", timeout, dst, ttl); + + return timeout; } uint32_t bt_mesh_seg_discard_timeout(void) { - return K_SECONDS((bt_mesh_get_sar_dt() + 1) * 5); + uint32_t timeout = K_SECONDS((bt_mesh_get_sar_dt() + 1) * 5); + + BT_DBG("SegDiscardTimeout %lu", timeout); + + return timeout; } uint32_t bt_mesh_seg_rx_interval(void) { - return (bt_mesh_get_sar_rsis() + 1) * 10; + uint32_t interval = (bt_mesh_get_sar_rsis() + 1) * 10; + + BT_DBG("SegRxInterval %lu", interval); + + return interval; } uint32_t bt_mesh_seg_ack_timeout(uint8_t seg_n) { - float min = MIN((float)seg_n + 0.5, (float)bt_mesh_get_sar_adi() + 1.5); - return (uint32_t)(min * bt_mesh_seg_rx_interval()); -} + uint32_t timeout = 0U; + float min = 0.0; -uint32_t bt_mesh_seg_ack_period(void) -{ - float val = (float)bt_mesh_get_sar_adi() + 1.5; - return (uint32_t)(val * bt_mesh_seg_rx_interval()); -} + min = MIN((float)seg_n + 0.5, (float)bt_mesh_get_sar_adi() + 1.5); + timeout = (uint32_t)(min * bt_mesh_seg_rx_interval()); -struct bt_mesh_app_key *bt_mesh_app_key_get(uint16_t app_idx) -{ - if (bt_mesh_is_provisioned()) { -#if CONFIG_BLE_MESH_NODE - if (!IS_ENABLED(CONFIG_BLE_MESH_FAST_PROV)) { - for (int i = 0; i < ARRAY_SIZE(bt_mesh.app_keys); i++) { - if (bt_mesh.app_keys[i].net_idx != BLE_MESH_KEY_UNUSED && - bt_mesh.app_keys[i].app_idx == app_idx) { - return &bt_mesh.app_keys[i]; - } - } - } else { - return bt_mesh_fast_prov_app_key_find(app_idx); - } -#endif - } else if (bt_mesh_is_provisioner_en()) { -#if CONFIG_BLE_MESH_PROVISIONER - for (int i = 0; i < ARRAY_SIZE(bt_mesh.p_app_keys); i++) { - if (bt_mesh.p_app_keys[i] && - bt_mesh.p_app_keys[i]->net_idx != BLE_MESH_KEY_UNUSED && - bt_mesh.p_app_keys[i]->app_idx == app_idx) { - return bt_mesh.p_app_keys[i]; - } - } -#endif - } + BT_DBG("SegAckTimeout %lu, Min %f", timeout, min); - return NULL; + return timeout; } -int bt_mesh_upper_key_get(const struct bt_mesh_subnet *subnet, uint16_t app_idx, - const uint8_t **key, uint8_t *aid, uint16_t dst) +uint32_t bt_mesh_seg_ack_period(void) { - struct bt_mesh_app_key *app_key = NULL; + uint32_t period = 0U; + float val = 0.0; - if (app_idx == BLE_MESH_KEY_DEV) { - *key = bt_mesh_dev_key_get(dst); - if (!*key) { - BT_ERR("DevKey of 0x%04x not found", dst); - return -EINVAL; - } - - *aid = 0U; - return 0; - } - - if (!subnet) { - BT_ERR("Invalid subnet"); - return -EINVAL; - } - - app_key = bt_mesh_app_key_get(app_idx); - if (!app_key) { - BT_ERR("AppKey 0x%04x not found", app_idx); - return -ENOENT; - } + val = (float)bt_mesh_get_sar_adi() + 1.5; + period = (uint32_t)(val * bt_mesh_seg_rx_interval()); - if (subnet->kr_phase == BLE_MESH_KR_PHASE_2 && app_key->updated) { - *key = app_key->keys[1].val; - *aid = app_key->keys[1].id; - } else { - *key = app_key->keys[0].val; - *aid = app_key->keys[0].id; - } + BT_DBG("SegAckPeriod %lu, Val %f", period, val); - return 0; + return period; } static int send_unseg(struct bt_mesh_net_tx *tx, struct net_buf_simple *sdu, @@ -264,8 +236,10 @@ static int send_unseg(struct bt_mesh_net_tx *tx, struct net_buf_simple *sdu, { struct net_buf *buf = NULL; - BT_DBG("src 0x%04x dst 0x%04x app_idx 0x%04x sdu_len %u", - tx->src, tx->ctx->addr, tx->ctx->app_idx, sdu->len); + BT_DBG("SendUnseg"); + BT_DBG("Src 0x%04x Dst 0x%04x AppIdx 0x%04x CtlOp 0x%02x SduLen %u", + tx->src, tx->ctx->addr, tx->ctx->app_idx, + ctl_op ? *ctl_op : 0xFF, sdu->len); buf = bt_mesh_adv_create(BLE_MESH_ADV_DATA, BUF_TIMEOUT); if (!buf) { @@ -289,13 +263,14 @@ static int send_unseg(struct bt_mesh_net_tx *tx, struct net_buf_simple *sdu, if (!bt_mesh_friend_queue_has_space(tx->sub->net_idx, tx->src, tx->ctx->addr, NULL, 1)) { + BT_WARN("NoSpaceInFrndQueue, SegCount 1"); + if (BLE_MESH_ADDR_IS_UNICAST(tx->ctx->addr)) { - BT_ERR("Not enough space in Friend Queue"); + BT_ERR("NotSentToUnicast"); net_buf_unref(buf); return -ENOBUFS; } - BT_WARN("No space in Friend Queue"); goto send; } @@ -305,6 +280,8 @@ static int send_unseg(struct bt_mesh_net_tx *tx, struct net_buf_simple *sdu, /* PDUs for a specific Friend should only go * out through the Friend Queue. */ + BT_DBG("FrndTxEnqueued, SegCount 1"); + net_buf_unref(buf); send_cb_finalize(cb, cb_data); return 0; @@ -317,6 +294,8 @@ static int send_unseg(struct bt_mesh_net_tx *tx, struct net_buf_simple *sdu, static inline uint8_t seg_len(bool ctl) { + BT_DBG("Ctl %u", ctl); + if (ctl) { return BLE_MESH_CTL_SEG_SDU_MAX; } @@ -330,20 +309,28 @@ bool bt_mesh_tx_in_progress(void) for (i = 0; i < ARRAY_SIZE(seg_tx); i++) { if (seg_tx[i].nack_count) { + BT_DBG("SegTxInProgress"); return true; } } + BT_DBG("SegTxNotInProgress"); return false; } static bool seg_tx_blocks(struct seg_tx *tx, uint16_t src, uint16_t dst) { + BT_DBG("SegTxBlocks"); + BT_DBG("Src 0x%04x vs. 0x%04x", tx->src, src); + BT_DBG("Dst 0x%04x vs. 0x%04x", tx->dst, dst); + return (tx->src == src) && (tx->dst == dst); } static void seg_tx_done(struct seg_tx *tx, uint8_t seg_idx) { + BT_DBG("SegTxDone, SegIdx %u", seg_idx); + /* If the segments are sent from local network interface, buf->ref * should be smaller than 4. * For other network interfaces, buf->ref should be smaller than 3. @@ -353,12 +340,16 @@ static void seg_tx_done(struct seg_tx *tx, uint8_t seg_idx) bt_mesh_atomic_set(&BLE_MESH_ADV_BUSY(tx->seg[seg_idx]), 0); net_buf_unref(tx->seg[seg_idx]); + BT_DBG("NackCountDec %u", tx->nack_count); + tx->seg[seg_idx] = NULL; tx->nack_count--; } static void seg_tx_reset(struct seg_tx *tx) { + BT_DBG("SegTxReset"); + bt_mesh_seg_tx_lock(); k_delayed_work_free(&tx->seg_timer); @@ -390,6 +381,7 @@ static void seg_tx_reset(struct seg_tx *tx) if (bt_mesh_atomic_test_and_clear_bit(bt_mesh.flags, BLE_MESH_IVU_PENDING)) { BT_DBG("Proceeding with pending IV Update"); + /* bt_mesh_net_iv_update() will re-enable the flag if this * wasn't the only transfer. */ @@ -404,6 +396,8 @@ static void seg_tx_complete(struct seg_tx *tx, int err) const struct bt_mesh_send_cb *cb = tx->cb; void *cb_data = tx->cb_data; + BT_DBG("SegTxComplete, Err %d", err); + seg_tx_reset(tx); /* TODO: notify the completion of sending segmented message */ @@ -420,10 +414,15 @@ static bool all_seg_acked(struct seg_tx *tx, uint8_t *seg_n) if (seg_n) { *seg_n = i; } + + BT_DBG("NotAllSegAcked, SegN %u", i); + return false; } } + BT_DBG("AllSegAcked"); + return true; } @@ -447,6 +446,10 @@ static bool send_next_segment(struct seg_tx *tx, int *result) struct net_buf *seg = NULL; int err = 0; + BT_DBG("SendNextSeg"); + BT_DBG("Src 0x%04x Dst 0x%04x LastSegN %u SegN %u LSNUpdated %u", + tx->src, tx->dst, tx->last_seg_n, tx->seg_n, tx->lsn_updated); + /* Check if all the segments are acknowledged. This could happen * when the complete Segment ACK (i.e. with all ack bits set) is * received before sending the next segment, which will cause the @@ -478,6 +481,8 @@ static bool send_next_segment(struct seg_tx *tx, int *result) * not been acknowledged. */ if (tx->seg[i]) { + BT_DBG("SegFound %u", i); + tx->last_seg_n = i; seg = tx->seg[i]; break; @@ -499,16 +504,19 @@ static bool send_next_segment(struct seg_tx *tx, int *result) * Segment Retransmission timer is expired earlier. */ if (bt_mesh_atomic_get(&BLE_MESH_ADV_BUSY(seg))) { + BT_DBG("SegSentBusy"); return false; } - BT_INFO("Send next seg %u, cred %u", tx->last_seg_n, tx->cred); + BT_INFO("LastSegN %u Cred %u", tx->last_seg_n, tx->cred); if (tx->resend) { err = bt_mesh_net_resend(tx->sub, seg, tx->new_key, &tx->cred, tx->tag, &seg_sent_cb, tx); if (err) { - BT_ERR("Resend seg %u failed (err %d)", tx->last_seg_n, err); + BT_ERR("ResendSegFailed, LastSegN %u Err %d", + tx->last_seg_n, err); + *result = -EIO; return true; } @@ -517,15 +525,16 @@ static bool send_next_segment(struct seg_tx *tx, int *result) net_tx.ctx->net_idx = tx->sub->net_idx; - /** - * Add one to the ref count only if the segment can be further + /* Add one to the ref count only if the segment can be further * processed by the network. */ seg = net_buf_ref(seg); err = bt_mesh_net_send(&net_tx, seg, &seg_sent_cb, tx); if (err) { - BT_ERR("Send seg %u failed (err %d)", tx->last_seg_n, err); + BT_ERR("SendSegFailed, LastSegN %u Err %d", + tx->last_seg_n, err); + *result = -EIO; return true; } @@ -535,7 +544,9 @@ static bool send_next_segment(struct seg_tx *tx, int *result) * which will be used for retransmission later. */ if (tx->cred != net_tx.ctx->send_cred) { - BT_ERR("Mismatch seg cred %u/%u", tx->cred, net_tx.ctx->send_cred); + BT_ERR("MismatchSegCred %u vs. %u", + tx->cred, net_tx.ctx->send_cred); + *result = -EIO; return true; } @@ -553,6 +564,8 @@ static void send_next_seg(struct k_work *work) tx_complete = send_next_segment(tx, &result); bt_mesh_seg_tx_unlock(); + BT_DBG("SendNextSeg, TxComplete %u", tx_complete); + if (tx_complete) { seg_tx_complete(tx, result); } @@ -564,6 +577,8 @@ static void prepare_next_seg(struct seg_tx *tx) uint8_t seg_n = 0; uint8_t xmit = 0; + BT_DBG("PrepareNextSeg"); + /* Check if all the segments are acknowledged. This could happen * when the complete Segment ACK (i.e. with all ack bits set) is * received before the completion of sending last segment, which @@ -574,6 +589,8 @@ static void prepare_next_seg(struct seg_tx *tx) return; } + BT_DBG("LastSegN %u SegN %u SegNGet %u", tx->last_seg_n, tx->seg_n, seg_n); + /* The last_seg_n must not be larger than the seg_n */ assert(tx->last_seg_n <= tx->seg_n && "Too large last_seg_n"); @@ -607,7 +624,7 @@ static void prepare_next_seg(struct seg_tx *tx) interval = bt_mesh_seg_send_interval(); - BT_INFO("Send next segment %u after %dms", i, interval); + BT_INFO("SendNextSeg %u, Interval %ld", i, interval); k_delayed_work_submit(&tx->seg_timer, interval); return; @@ -619,6 +636,7 @@ static void prepare_next_seg(struct seg_tx *tx) * we need to decrypt it firstly. */ if (tx->resend == 0) { + BT_DBG("TxResendMarked"); tx->resend = 1; } @@ -629,7 +647,7 @@ static void prepare_next_seg(struct seg_tx *tx) /* Start the SAR retransmission timer */ interval = bt_mesh_seg_rtx_interval(tx->dst, tx->ttl); - BT_INFO("All segments sent, resend after %dms", interval); + BT_INFO("AllSegsSent, SegN %u Interval %ld", seg_n, interval); k_delayed_work_submit(&tx->rtx_timer, interval); } @@ -638,6 +656,8 @@ static void seg_send_start(uint16_t duration, int err, void *user_data) { struct seg_tx *tx = user_data; + BT_DBG("SegSendStart, Err %d", err); + /* If there's an error in transmitting the 'sent' callback will never * be called. Make sure that we kick the retransmit timer also in this * case since otherwise we risk the transmission of becoming stale. @@ -647,6 +667,8 @@ static void seg_send_start(uint16_t duration, int err, void *user_data) return; } + BT_DBG("TxResend %u LastSegN %u", tx->resend, tx->last_seg_n); + if (tx->resend == 0 && tx->last_seg_n == 0) { /* Start sending the multi-segment message */ if (tx->cb && tx->cb->start) { @@ -663,6 +685,8 @@ static void seg_send_end(int err, void *user_data) { struct seg_tx *tx = user_data; + BT_DBG("SegSendEnd, Err %d", err); + if (err) { seg_tx_complete(tx, -EIO); } @@ -678,6 +702,10 @@ static bool resend_unacked_seg(struct seg_tx *tx, int *result) struct net_buf *seg = NULL; int err = 0; + BT_DBG("ResendUnackedSeg"); + BT_DBG("Dst 0x%04x Surc %u Surwpc %u Smrc %u", + tx->dst, tx->surc, tx->surwpc, tx->smrc); + /* Check if all the segments are acknowledged. This could happen * when the complete Segment ACK(i.e. with all ack bits set) is * received before the completion of sending last segment, which @@ -747,6 +775,8 @@ static bool resend_unacked_seg(struct seg_tx *tx, int *result) */ for (size_t i = tx->last_seg_n; i <= tx->seg_n; i++) { if (tx->seg[i]) { + BT_DBG("SegFound %u", i); + tx->last_seg_n = i; seg = tx->seg[i]; break; @@ -769,10 +799,11 @@ static bool resend_unacked_seg(struct seg_tx *tx, int *result) * find that the "busy" flag of Segment A is 1. */ if (bt_mesh_atomic_get(&BLE_MESH_ADV_BUSY(seg))) { + BT_DBG("SegSentBusy"); return false; } - BT_INFO("Resend seg %u, cred %u", tx->last_seg_n, tx->cred); + BT_INFO("LastSegN %u Cred %u", tx->last_seg_n, tx->cred); /* TODO: * The "tx->new_key" should be replaced with sub->kr_flag, @@ -783,7 +814,9 @@ static bool resend_unacked_seg(struct seg_tx *tx, int *result) &tx->cred, tx->tag, &seg_sent_cb, tx); if (err) { - BT_ERR("Resend seg %u failed (err %d)", tx->last_seg_n, err); + BT_ERR("ResendSegFailed, LastSegN %u Err %d", + tx->last_seg_n, err); + *result = -EIO; return true; } @@ -803,6 +836,8 @@ static void seg_retransmit(struct k_work *work) tx_complete = resend_unacked_seg(tx, &err); bt_mesh_seg_tx_unlock(); + BT_DBG("SendRetransmit, TxComplete %u", tx_complete); + if (tx_complete) { seg_tx_complete(tx, err); } @@ -818,11 +853,14 @@ static int send_seg(struct bt_mesh_net_tx *net_tx, struct net_buf_simple *sdu, int err = 0; size_t i; - BT_DBG("src 0x%04x dst 0x%04x app_idx 0x%04x aszmic %u sdu_len %u", + BT_DBG("SendSeg"); + BT_DBG("Src 0x%04x Dst 0x%04x AppIdx 0x%04x Aszmic %u SduLen %u", net_tx->src, net_tx->ctx->addr, net_tx->ctx->app_idx, net_tx->aszmic, sdu->len); for (i = 0; i < ARRAY_SIZE(seg_tx); i++) { + BT_DBG("Seg%u: NackCount %u", i, seg_tx[i].nack_count); + if (seg_tx[i].nack_count) { /* The lower transport layer shall not transmit segmented messages * for more than one Upper Transport PDU to the same destination @@ -837,6 +875,8 @@ static int send_seg(struct bt_mesh_net_tx *net_tx, struct net_buf_simple *sdu, for (tx = NULL, i = 0; i < ARRAY_SIZE(seg_tx); i++) { if (!seg_tx[i].nack_count) { + BT_DBG("SegTxFound %u", i); + tx = &seg_tx[i]; break; } @@ -916,15 +956,18 @@ static int send_seg(struct bt_mesh_net_tx *net_tx, struct net_buf_simple *sdu, seq_zero = tx->seq_auth & TRANS_SEQ_ZERO_MASK; - BT_DBG("SeqZero 0x%04x (segs: %u)", seq_zero, tx->nack_count); + BT_DBG("SegHdr 0x%02x SegN %u NackCount %u NewKey %u TTL %u", + tx->hdr, tx->seg_n, tx->nack_count, tx->new_key, tx->ttl); + BT_DBG("SeqZero 0x%04x Surc %u Surwpc %u Smrc %u", + seq_zero, tx->surc, tx->surwpc, tx->smrc); if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND) && !bt_mesh_friend_queue_has_space(tx->sub->net_idx, net_tx->src, tx->dst, &tx->seq_auth, tx->seg_n + 1) && BLE_MESH_ADDR_IS_UNICAST(tx->dst)) { - BT_ERR("Not enough space in Friend Queue for %u segments", - tx->seg_n + 1); + BT_WARN("NoSpaceInFrndQueue, SegCount %u", tx->seg_n + 1); + seg_tx_reset(tx); return -ENOBUFS; } @@ -959,6 +1002,8 @@ static int send_seg(struct bt_mesh_net_tx *net_tx, struct net_buf_simple *sdu, type = BLE_MESH_FRIEND_PDU_PARTIAL; } + BT_DBG("FrndPDUType %u", type); + if (bt_mesh_friend_enqueue_tx(net_tx, type, &tx->seq_auth, tx->seg_n + 1, @@ -967,39 +1012,40 @@ static int send_seg(struct bt_mesh_net_tx *net_tx, struct net_buf_simple *sdu, /* PDUs for a specific Friend should only go * out through the Friend Queue. */ + BT_DBG("FrndTxEnqueued, SegCount %u", tx->seg_n + 1); + net_buf_unref(seg); continue; } } - /** - * If the net buffer allocation of the subsequent - * segments of this segment message fails, it will - * cause the ref count of the previously allocated - * successful segments to not be unref, which will - * cause the net buffer leakage to occur, so it is - * necessary to wait until all the segments have been - * allocated, and then when the segment is confirmed - * that it will be network layer for further processing, - * then ref of the net buffer should be plus one. + /* If the net buffer allocation of the subsequent segments of + * this segment message fails, it will cause the ref count of + * the previously allocated successful segments to not be unref, + * which will cause the net buffer leakage to occur, so it is + * necessary to wait until all the segments have been allocated, + * and then when the segment is confirmed that it will be network + * layer for further processing, then ref of the net buffer should + * be plus one. */ tx->seg[seg_o] = seg; - BT_DBG("Seg %u/%u prepared", seg_o, tx->seg_n); + BT_DBG("SegPrepared %u/%u", seg_o, tx->seg_n); } /* If all the segments are enqueued in the friend queue, then the * tx->seg[0] will be NULL here. */ if (tx->seg[0]) { - /** - * Add one to the ref count only if the segment can be further + /* Add one to the ref count only if the segment can be further * processed by the network. */ tx->seg[0] = net_buf_ref(tx->seg[0]); + err = bt_mesh_net_send(net_tx, tx->seg[0], &seg_sent_cb, tx); if (err) { - BT_ERR("Send 1st seg failed (err %d)", err); + BT_ERR("SendFirstSegFailed, Err %d", err); + seg_tx_reset(tx); return err; } @@ -1009,13 +1055,17 @@ static int send_seg(struct bt_mesh_net_tx *net_tx, struct net_buf_simple *sdu, * which will be used for retransmission later. */ if (tx->cred != net_tx->ctx->send_cred) { + BT_INFO("OldCred %u NewCred %u", tx->cred, net_tx->ctx->send_cred); tx->cred = net_tx->ctx->send_cred; } } /* This can happen if segments only went into the Friend Queue */ if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND) && !tx->seg[0]) { + BT_DBG("OnlyToFrndQueue"); + seg_tx_reset(tx); + /* If there was a callback notify sending immediately since * there's no other way to track this (at least currently) * with the Friend Queue. @@ -1039,6 +1089,8 @@ int bt_mesh_trans_send(struct bt_mesh_net_tx *tx, struct net_buf_simple *msg, uint8_t aid = 0U; int err = 0; + BT_DBG("transcend"); + if (msg->len < 1) { BT_ERR("Zero-length SDU not allowed"); return -EINVAL; @@ -1048,9 +1100,9 @@ int bt_mesh_trans_send(struct bt_mesh_net_tx *tx, struct net_buf_simple *msg, tx->ctx->send_tag |= BLE_MESH_TAG_SEND_SEGMENTED; } - BT_DBG("net_idx 0x%04x app_idx 0x%04x dst 0x%04x", tx->sub->net_idx, - tx->ctx->app_idx, tx->ctx->addr); - BT_DBG("len %u: %s", msg->len, bt_hex(msg->data, msg->len)); + BT_DBG("NetIdx 0x%04x AppIdx 0x%04x Dst 0x%04x", + tx->sub->net_idx, tx->ctx->app_idx, tx->ctx->addr); + BT_DBG("Len %u: %s", msg->len, bt_hex(msg->data, msg->len)); err = bt_mesh_upper_key_get(tx->sub, tx->ctx->app_idx, &key, &aid, tx->ctx->addr); @@ -1068,7 +1120,7 @@ int bt_mesh_trans_send(struct bt_mesh_net_tx *tx, struct net_buf_simple *msg, tx->aszmic = 1U; } - BT_INFO("%s, send_tag 0x%02x, send_szmic %d, aszmic %d", + BT_INFO("%s, Tag 0x%02x Szmic %u Aszmic %u", bt_mesh_tag_send_segmented(tx->ctx->send_tag) ? "Seg" : "Unseg", tx->ctx->send_tag, tx->ctx->send_szmic, tx->aszmic); @@ -1083,7 +1135,7 @@ int bt_mesh_trans_send(struct bt_mesh_net_tx *tx, struct net_buf_simple *msg, tx->ctx->addr, bt_mesh.seq, BLE_MESH_NET_IVI_TX); if (err) { - BT_ERR("Encrypt failed (err %d)", err); + BT_ERR("AppEncryptFailed, Err %d", err); return err; } @@ -1097,7 +1149,7 @@ int bt_mesh_trans_send(struct bt_mesh_net_tx *tx, struct net_buf_simple *msg, static void revoke_dev_key(const uint8_t *dev_key) { if (!memcmp(dev_key, bt_mesh.dev_key_ca, 16)) { - BT_INFO("Revoke Device Key"); + BT_INFO("RevokeDevKey"); memcpy(bt_mesh.dev_key, bt_mesh.dev_key_ca, 16); memset(bt_mesh.dev_key_ca, 0, 16); @@ -1118,8 +1170,9 @@ static int sdu_recv(struct bt_mesh_net_rx *rx, uint32_t seq, uint8_t hdr, size_t i = 0U; int err = 0; - BT_DBG("ASZMIC %u AKF %u AID 0x%02x", aszmic, AKF(&hdr), AID(&hdr)); - BT_DBG("len %u: %s", buf->len, bt_hex(buf->data, buf->len)); + BT_DBG("SduRecv"); + BT_DBG("Aszmic %u AKF %u AID 0x%02x", aszmic, AKF(&hdr), AID(&hdr)); + BT_DBG("Len %u: %s", buf->len, bt_hex(buf->data, buf->len)); if (buf->len < 1 + APP_MIC_LEN(aszmic)) { BT_ERR("Too short SDU + MIC (len %u)", buf->len); @@ -1158,7 +1211,7 @@ static int sdu_recv(struct bt_mesh_net_rx *rx, uint32_t seq, uint8_t hdr, dev_key = bt_mesh_rx_devkey_get(i, rx->ctx.addr); if (!dev_key) { - BT_DBG("DevKey not found"); + BT_DBG("DevKeyNotFound"); continue; } @@ -1169,6 +1222,7 @@ static int sdu_recv(struct bt_mesh_net_rx *rx, uint32_t seq, uint8_t hdr, rx->ctx.recv_dst, seq, BLE_MESH_NET_IVI_RX(rx)); if (err) { + BT_DBG("DevKeyNotDecrypt"); continue; } @@ -1194,6 +1248,7 @@ static int sdu_recv(struct bt_mesh_net_rx *rx, uint32_t seq, uint8_t hdr, } BT_WARN("Unable to decrypt with DevKey"); + bt_mesh_free_buf(sdu); return -ENODEV; } @@ -1206,7 +1261,7 @@ static int sdu_recv(struct bt_mesh_net_rx *rx, uint32_t seq, uint8_t hdr, key = bt_mesh_rx_appkey_get(i); if (!key) { - BT_DBG("AppKey not found"); + BT_DBG("AppKeyNotFound"); continue; } @@ -1240,8 +1295,7 @@ static int sdu_recv(struct bt_mesh_net_rx *rx, uint32_t seq, uint8_t hdr, bt_hex(sdu->data, sdu->len)); if (err) { - BT_DBG("Unable to decrypt with AppKey 0x%03x", - key->app_idx); + BT_DBG("AppKeyNotDecrypt, AppIdx 0x%04x", key->app_idx); continue; } @@ -1253,10 +1307,10 @@ static int sdu_recv(struct bt_mesh_net_rx *rx, uint32_t seq, uint8_t hdr, } if (rx->local_match) { - BT_WARN("No matching AppKey"); + BT_WARN("NoMatchAppKey"); } - bt_mesh_free_buf(sdu); + bt_mesh_free_buf(sdu); return 0; } @@ -1266,6 +1320,8 @@ static struct seg_tx *seg_tx_lookup(uint16_t seq_zero, uint8_t obo, struct seg_tx *tx = NULL; int i; + BT_DBG("SegTxLookup, SeqZero 0x%04x OBO %u Addr 0x%04x", seq_zero, obo, addr); + for (i = 0; i < ARRAY_SIZE(seg_tx); i++) { tx = &seg_tx[i]; @@ -1281,6 +1337,7 @@ static struct seg_tx *seg_tx_lookup(uint16_t seq_zero, uint8_t obo, } if (tx->dst == addr) { + BT_DBG("SegTxFound, Dst 0x%04x", addr); return tx; } @@ -1290,6 +1347,7 @@ static struct seg_tx *seg_tx_lookup(uint16_t seq_zero, uint8_t obo, * responding and therefore accept the message. */ if (obo && tx->nack_count == tx->seg_n + 1) { + BT_DBG("SegTxOboFound, Dst 0x%04x", addr); tx->dst = addr; return tx; } @@ -1316,6 +1374,8 @@ static int recv_seg_ack(struct bt_mesh_net_rx *rx, uint8_t hdr, *tx_complete = false; *result = 0; + BT_DBG("RecvSegAck"); + if (buf->len != 6) { BT_ERR("Malformed Segment Ack (len %u)", buf->len); return -EINVAL; @@ -1334,7 +1394,7 @@ static int recv_seg_ack(struct bt_mesh_net_rx *rx, uint8_t hdr, ack = net_buf_simple_pull_be32(buf); - BT_DBG("OBO %u seq_zero 0x%04x ack 0x%08x", obo, seq_zero, ack); + BT_DBG("OBO %u SeqZero 0x%04x Ack 0x%08lx", obo, seq_zero, ack); tx = seg_tx_lookup(seq_zero, obo, rx->ctx.addr, rx->ctx.net_idx); if (!tx) { @@ -1392,6 +1452,8 @@ static int recv_seg_ack(struct bt_mesh_net_rx *rx, uint8_t hdr, return 0; } + BT_DBG("NewlyMarked"); + /* If at least one segment is newly marked as acknowledged as * a result of receiving the Segment Acknowledgment message, * the lower transport layer shall set the remaining number of @@ -1401,9 +1463,12 @@ static int recv_seg_ack(struct bt_mesh_net_rx *rx, uint8_t hdr, tx->surwpc = bt_mesh_get_sar_urwpc(); } + BT_DBG("Surc %u Surwpc %u", tx->surc, tx->surwpc); + if (tx->surc == 0 || tx->surwpc == 0) { BT_WARN("Ran out of retransmission to 0x%04x (%u/%u)", tx->dst, tx->surc, tx->surwpc); + *tx_complete = true; *result = -ETIMEDOUT; return 0; @@ -1411,6 +1476,8 @@ static int recv_seg_ack(struct bt_mesh_net_rx *rx, uint8_t hdr, assert(all_seg_acked(tx, &seg_n) == false && "All segments acked"); + BT_DBG("SegN %u TxResend %u", seg_n, tx->resend); + if (tx->resend == 1) { /* Only update the last_seg_n to the first unacked SegN while * the first round transmission is finished, because we need @@ -1439,7 +1506,7 @@ static int recv_seg_ack(struct bt_mesh_net_rx *rx, uint8_t hdr, /* Restart the SAR Unicast Retransmission timer */ interval = bt_mesh_seg_rtx_interval(tx->dst, tx->ttl); - BT_INFO("Resend segments after %dms", interval); + BT_INFO("ResendSeg, Interval %ld", interval); k_delayed_work_submit(&tx->rtx_timer, interval); @@ -1458,6 +1525,8 @@ static int trans_ack(struct bt_mesh_net_rx *rx, uint8_t hdr, err = recv_seg_ack(rx, hdr, buf, seq_auth, &tx, &tx_complete, &result); bt_mesh_seg_tx_unlock(); + BT_DBG("TransAck, TxComplete %u", tx_complete); + if (tx_complete) { seg_tx_complete(tx, result); } @@ -1471,6 +1540,8 @@ static int trans_heartbeat(struct bt_mesh_net_rx *rx, uint8_t init_ttl = 0U, hops = 0U; uint16_t feat = 0U; + BT_DBG("TransHeartbeat"); + if (buf->len != 3) { BT_ERR("Malformed heartbeat message (len %u)", buf->len); return -EINVAL; @@ -1487,9 +1558,8 @@ static int trans_heartbeat(struct bt_mesh_net_rx *rx, hops = (init_ttl - rx->ctx.recv_ttl + 1); - BT_INFO("src 0x%04x TTL %u InitTTL %u (%u hop%s) feat 0x%04x", - rx->ctx.addr, rx->ctx.recv_ttl, init_ttl, hops, - (hops == 1U) ? "" : "s", feat); + BT_INFO("Src 0x%04x TTL %u InitTTL %u Hops %u Feat 0x%04x", + rx->ctx.addr, rx->ctx.recv_ttl, init_ttl, hops, feat); if (IS_ENABLED(CONFIG_BLE_MESH_NODE) && bt_mesh_is_provisioned()) { bt_mesh_heartbeat_recv(rx->ctx.addr, rx->ctx.recv_dst, hops, feat); @@ -1507,7 +1577,7 @@ static int ctl_recv(struct bt_mesh_net_rx *rx, uint8_t hdr, { uint8_t ctl_op = TRANS_CTL_OP(&hdr); - BT_DBG("OpCode 0x%02x len %u", ctl_op, buf->len); + BT_DBG("CTLRecv, OpCode 0x%02x Len %u", ctl_op, buf->len); BT_BQB(BLE_MESH_BQB_TEST_LOG_LEVEL_PRIMARY_ID_NODE | \ BLE_MESH_BQB_TEST_LOG_LEVEL_SUB_ID_TNPT, @@ -1524,21 +1594,22 @@ static int ctl_recv(struct bt_mesh_net_rx *rx, uint8_t hdr, /* Only acks and heartbeats may need processing without local_match */ if (!rx->local_match) { + BT_DBG("LocalNotMatch"); return 0; } - if (IS_ENABLED(CONFIG_BLE_MESH_DF_SRV)) { - switch (ctl_op) { - case TRANS_CTL_OP_PATH_REQ: - case TRANS_CTL_OP_PATH_REPLY: - case TRANS_CTL_OP_PATH_CFM: - case TRANS_CTL_OP_PATH_ECHO_REQ: - case TRANS_CTL_OP_PATH_ECHO_REPLY: - case TRANS_CTL_OP_DEP_NODE_UPDATE: - case TRANS_CTL_OP_PATH_REQ_SOLIC: - return bt_mesh_directed_forwarding_ctl_recv(ctl_op, rx, buf); - } +#if CONFIG_BLE_MESH_DF_SRV + switch (ctl_op) { + case TRANS_CTL_OP_PATH_REQ: + case TRANS_CTL_OP_PATH_REPLY: + case TRANS_CTL_OP_PATH_CFM: + case TRANS_CTL_OP_PATH_ECHO_REQ: + case TRANS_CTL_OP_PATH_ECHO_REPLY: + case TRANS_CTL_OP_DEP_NODE_UPDATE: + case TRANS_CTL_OP_PATH_REQ_SOLIC: + return bt_mesh_directed_forwarding_ctl_recv(ctl_op, rx, buf); } +#endif /* CONFIG_BLE_MESH_DF_SRV */ if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND) && !bt_mesh_lpn_established()) { switch (ctl_op) { @@ -1591,7 +1662,7 @@ static int trans_unseg(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx, { uint8_t hdr = 0U; - BT_DBG("AFK %u AID 0x%02x", AKF(buf->data), AID(buf->data)); + BT_DBG("TransUnseg, AKF %u AID 0x%02x", AKF(buf->data), AID(buf->data)); if (buf->len < 1) { BT_ERR("Too small unsegmented PDU"); @@ -1599,7 +1670,7 @@ static int trans_unseg(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx, } if (bt_mesh_rpl_check(rx, NULL)) { - BT_WARN("Replay: src 0x%04x dst 0x%04x seq 0x%06x", + BT_WARN("Replay, Src 0x%04x Dst 0x%04x Seq 0x%06x", rx->ctx.addr, rx->ctx.recv_dst, rx->seq); return -EINVAL; } @@ -1612,6 +1683,7 @@ static int trans_unseg(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx, /* SDUs must match a local element or an LPN of this Friend. */ if (!rx->local_match && !rx->friend_match) { + BT_DBG("LocalAndFrndNotMatch"); return 0; } @@ -1624,6 +1696,8 @@ int bt_mesh_ctl_send(struct bt_mesh_net_tx *tx, uint8_t ctl_op, void *data, { struct net_buf_simple buf = {0}; + BT_DBG("CtlSend"); + net_buf_simple_init_with_data(&buf, data, data_len); if (data_len > BLE_MESH_SDU_UNSEG_MAX) { @@ -1633,9 +1707,9 @@ int bt_mesh_ctl_send(struct bt_mesh_net_tx *tx, uint8_t ctl_op, void *data, /* Set app_idx to unused here since CTL is only encrypted with NetKey */ tx->ctx->app_idx = BLE_MESH_KEY_UNUSED; - BT_DBG("src 0x%04x dst 0x%04x ttl 0x%02x ctl 0x%02x", tx->src, - tx->ctx->addr, tx->ctx->send_ttl, ctl_op); - BT_DBG("len %zu: %s", data_len, bt_hex(data, data_len)); + BT_DBG("Src 0x%04x Dst 0x%04x TTL 0x%02x CTL 0x%02x", + tx->src, tx->ctx->addr, tx->ctx->send_ttl, ctl_op); + BT_DBG("Len %u: %s", data_len, bt_hex(data, data_len)); if (bt_mesh_tag_send_segmented(tx->ctx->send_tag)) { return send_seg(tx, &buf, cb, cb_data, &ctl_op); @@ -1648,18 +1722,21 @@ static void seg_ack_send_start(uint16_t duration, int err, void *user_data) { struct seg_rx *rx = user_data; - BT_INFO("Send segment ack start (err %d)", err); + BT_INFO("SegAckSendStart, Err %d", err); if (err) { rx->last_ack = k_uptime_get_32(); + + BT_DBG("LastAck %lu", rx->last_ack); } } static void seg_ack_send_end(int err, void *user_data) { struct seg_rx *rx = user_data; + uint32_t interval = 0U; - BT_INFO("Send segment ack end"); + BT_INFO("SegAckSendEnd, InUse %u Err %d", rx->in_use, err); /* This could happen when during the Segment ACK transaction, * the seg_rx is been reset. @@ -1670,6 +1747,9 @@ static void seg_ack_send_end(int err, void *user_data) rx->last_ack = k_uptime_get_32(); + BT_DBG("LastAck %lu SegN %u Sarc %u NewSeg %u", + rx->last_ack, rx->seg_n, rx->sarc, rx->new_seg); + /* If the seg_rx is in use, we will restart the SAR ACK timer if * the SegN is greater than the SAR Segments Threshold. * Note: @@ -1687,10 +1767,12 @@ static void seg_ack_send_end(int err, void *user_data) /* Decrement the SAR ACK Retransmissions Count */ rx->sarc -= 1; - BT_INFO("Resend segment ack after %dms", bt_mesh_seg_rx_interval()); + interval = bt_mesh_seg_rx_interval(); + + BT_INFO("ResendSeg, Interval %lu", interval); /* Introduce a delay for the Segment ACK retransmission */ - k_delayed_work_submit(&rx->ack_timer, bt_mesh_seg_rx_interval()); + k_delayed_work_submit(&rx->ack_timer, interval); } } @@ -1728,7 +1810,7 @@ static int send_ack(struct bt_mesh_subnet *sub, uint16_t src, uint16_t dst, uint16_t seq_zero = *seq_auth & TRANS_SEQ_ZERO_MASK; uint8_t buf[6] = {0}; - BT_DBG("SeqZero 0x%04x Block 0x%08x OBO %u", seq_zero, block, obo); + BT_DBG("SendAck, SeqZero 0x%04x Block 0x%08lx OBO %u", seq_zero, block, obo); if (bt_mesh_lpn_established()) { BT_WARN("Not sending ack when LPN is enabled"); @@ -1752,6 +1834,8 @@ static int send_ack(struct bt_mesh_subnet *sub, uint16_t src, uint16_t dst, static void seg_rx_reset(struct seg_rx *rx, bool full_reset) { + BT_DBG("SegRxReset, FullReset %u", full_reset); + bt_mesh_seg_rx_lock(); k_delayed_work_free(&rx->dis_timer); @@ -1792,6 +1876,8 @@ static void send_seg_ack(struct k_work *work) { struct seg_rx *rx = CONTAINER_OF(work, struct seg_rx, ack_timer); + BT_DBG("SendSegAck, Sub %p", rx->sub); + bt_mesh_seg_rx_lock(); /* This could happen when the SAR ACK timer expired, and a BTC @@ -1818,6 +1904,9 @@ static void send_seg_ack(struct k_work *work) static void discard_msg(struct k_work *work) { struct seg_rx *rx = CONTAINER_OF(work, struct seg_rx, dis_timer); + uint32_t timeout = 0U; + + BT_DBG("DiscardMsg, InUse %u Dst 0x%04x", rx->in_use, rx->dst); /* This could happen when the SAR Discard timer expired, and a * BTC event is posted to the BTC queue. @@ -1835,22 +1924,27 @@ static void discard_msg(struct k_work *work) k_delayed_work_cancel(&rx->ack_timer); } - BT_WARN("Discard timer expired (%dms)", bt_mesh_seg_discard_timeout()); + timeout = bt_mesh_seg_discard_timeout(); + + BT_WARN("DiscardTimerExpired, timeout %lu", timeout); - /* Not fully reset the seg_rx, in case any segment of this - * message is received later. + /* Not fully reset the seg_rx, in case any segment of + * this message is received later. */ seg_rx_reset(rx, false); } static inline bool sdu_len_is_ok(bool ctl, uint8_t seg_n) { + BT_DBG("IsSduLenOK,Len:%u,SegN:%u", seg_len, seg_n); return ((seg_n + 1) * seg_len(ctl) <= CONFIG_BLE_MESH_RX_SDU_MAX); } static void seg_rx_reset_pending(struct bt_mesh_net_rx *net_rx, const uint64_t *seq_auth) { + BT_DBG("SegRxResetPending, SeqAuth 0x%llx", *seq_auth); + for (size_t i = 0; i < ARRAY_SIZE(seg_rx); i++) { struct seg_rx *rx = &seg_rx[i]; @@ -1870,9 +1964,13 @@ static void seg_rx_reset_pending(struct bt_mesh_net_rx *net_rx, static struct seg_rx *seg_rx_find(struct bt_mesh_net_rx *net_rx, const uint64_t *seq_auth) { + BT_DBG("SegRxFind, SeqAuth 0x%llx", *seq_auth); for (size_t i = 0; i < ARRAY_SIZE(seg_rx); i++) { struct seg_rx *rx = &seg_rx[i]; + BT_DBG("Seg%u/%u: Src 0x%04x Dst 0x%04x SeqAuth 0x%llx", + i,rx->seg_n, rx->src, rx->dst, rx->seq_auth); + if (rx->src == net_rx->ctx.addr && rx->dst == net_rx->ctx.recv_dst && rx->seq_auth >= *seq_auth) { @@ -1886,6 +1984,8 @@ static struct seg_rx *seg_rx_find(struct bt_mesh_net_rx *net_rx, static bool seg_rx_is_valid(struct seg_rx *rx, struct bt_mesh_net_rx *net_rx, const uint8_t *hdr, uint8_t seg_n) { + BT_DBG("IsSegRxValid"); + if (rx->hdr != *hdr || rx->seg_n != seg_n) { BT_ERR("Invalid segment for ongoing session"); return false; @@ -1905,8 +2005,42 @@ static struct seg_rx *seg_rx_alloc(struct bt_mesh_net_rx *net_rx, { int err = 0; +<<<<<<< HEAD +<<<<<<< HEAD for (size_t i = 0; i < ARRAY_SIZE(seg_rx); i++) { struct seg_rx *rx = &seg_rx[i]; +======= +<<<<<<< HEAD +======= +>>>>>>> 9fc4381f187 (fix(ble_mesh): resolve miscellaneous logging issues) + /* By default, traditional seg_rx is used for allocation. + * If the first segment received is the last segment of + * the long packet, and its length is the length of the traditional packet, + * Since it is impossible to determine whether it is a long packet + * under the current situation, can only copy the rx information + * into the ext_rx buffer when the next segment received and can be + * confirmed to be a long packet*/ + struct seg_rx *seg_rx_buf = seg_rx; + uint16_t rx_buf_size = ARRAY_SIZE(seg_rx); + +#if CONFIG_BLE_MESH_LONG_PACKET + if (net_rx->ctx.enh.long_pkt_cfg_used) { + seg_rx_buf = ext_seg_rx; + rx_buf_size = ARRAY_SIZE(ext_seg_rx); + } +#endif + + for (size_t i = 0; i < rx_buf_size; i++) { + struct seg_rx *rx = &seg_rx_buf[i]; + +<<<<<<< HEAD + for (size_t i = 0; i < ARRAY_SIZE(seg_rx); i++) { + struct seg_rx *rx = &seg_rx[i]; +>>>>>>> 7652269a401 (feat(ble_mesh): Miscellaneous log enhancement for BLE Mesh) +>>>>>>> bdcd87e62fa (feat(ble_mesh): Miscellaneous log enhancement for BLE Mesh) +======= + BT_DBG("SegRxAlloc, SegN %u", seg_n); +>>>>>>> 9fc4381f187 (fix(ble_mesh): resolve miscellaneous logging issues) if (rx->in_use) { continue; @@ -1922,7 +2056,7 @@ static struct seg_rx *seg_rx_alloc(struct bt_mesh_net_rx *net_rx, err = k_delayed_work_init(&rx->ack_timer, send_seg_ack); if (err) { BT_ERR("No free ack_timer for new incoming segmented message"); - k_delayed_work_free(&rx->dis_timer); /* Must do */ + k_delayed_work_free(&rx->dis_timer); return NULL; } } @@ -1946,7 +2080,6 @@ static struct seg_rx *seg_rx_alloc(struct bt_mesh_net_rx *net_rx, return rx; } - BT_WARN("No free slots for new incoming segmented messages"); return NULL; } @@ -1962,18 +2095,20 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, uint8_t seg_o = 0U; int err = 0; + BT_DBG("TransSeg"); + if (buf->len < 5) { BT_ERR("Too short segmented message (len %u)", buf->len); return -EINVAL; } if (bt_mesh_rpl_check(net_rx, &rpl)) { - BT_WARN("Replay: src 0x%04x dst 0x%04x seq 0x%06x", + BT_WARN("Replay, Src 0x%04x Dst 0x%04x Seq 0x%06x", net_rx->ctx.addr, net_rx->ctx.recv_dst, net_rx->seq); return -EINVAL; } - BT_DBG("ASZMIC %u AKF %u AID 0x%02x", ASZMIC(hdr), AKF(hdr), AID(hdr)); + BT_DBG("Aszmic %u AKF %u AID 0x%02x", ASZMIC(hdr), AKF(hdr), AID(hdr)); net_buf_simple_pull(buf, 1); @@ -2000,6 +2135,9 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, *seg_count = seg_n + 1; + BT_DBG("Src 0x%04x Dst 0x%04x SeqAuth 0x%llx SegCount %u", + net_rx->ctx.addr, net_rx->ctx.recv_dst, *seq_auth, *seg_count); + /* If this is the first segment, check if any pending reassembly * exists. If yes, we need to discard the pending reassembly. * Note: @@ -2013,8 +2151,7 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, if (rx) { /* Processing result is SeqAuth Error, ignore the segment */ if (rx->seq_auth > *seq_auth) { - BT_WARN("Ignoring old SeqAuth, src 0x%04x, dst 0x%04x", - rx->src, rx->dst); + BT_WARN("SeqAuth 0x%llx vs. 0x%llx", rx->seq_auth, *seq_auth); return -EINVAL; } @@ -2079,7 +2216,8 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, net_rx->ctx.addr, net_rx->ctx.recv_dst, seq_auth, *seg_count)) { - BT_ERR("No space in Friend Queue for %u segments", *seg_count); + BT_ERR("NoSpaceInFrndQueue, SegCount %u", *seg_count); + send_ack(net_rx->sub, net_rx->ctx.recv_dst, net_rx->ctx.addr, net_rx->ctx.send_ttl, seq_auth, 0, net_rx->friend_match, NULL); @@ -2089,6 +2227,8 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, /* Look for free slot for a new RX session */ rx = seg_rx_alloc(net_rx, hdr, seq_auth, seg_n); if (!rx) { + BT_WARN("SegRxFull, Src %04x", net_rx->ctx.addr); + /* Processing result is Message Rejected, respond with a Segment * ACK with the AckedSegments field set to 0x00000000. */ @@ -2118,7 +2258,15 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, /* Set the expected final buffer length */ rx->buf.len = seg_n * seg_len(rx->ctl) + buf->len; +<<<<<<< HEAD +<<<<<<< HEAD BT_DBG("Target len %u * %u + %u = %u", seg_n, seg_len(rx->ctl), +======= +<<<<<<< HEAD +======= +>>>>>>> 9fc4381f187 (fix(ble_mesh): resolve miscellaneous logging issues) + BT_DBG("Target len %u * %u + %u = %u", seg_n, seg_len(&si), +>>>>>>> bdcd87e62fa (feat(ble_mesh): Miscellaneous log enhancement for BLE Mesh) buf->len, rx->buf.len); /* This should not happen, since we have made sure the whole @@ -2126,13 +2274,26 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, * But if the peer device sends the segments of a segmented * message with different CTL, then the following could happen. */ +<<<<<<< HEAD +<<<<<<< HEAD if (rx->buf.len > CONFIG_BLE_MESH_RX_SDU_MAX) { +======= +<<<<<<< HEAD +======= +>>>>>>> 9fc4381f187 (fix(ble_mesh): resolve miscellaneous logging issues) + if ((!rx->ext && rx->buf.len > CONFIG_BLE_MESH_RX_SDU_MAX) +#if CONFIG_BLE_MESH_LONG_PACKET + || (rx->ext && rx->buf.len > BLE_MESH_EXT_RX_SDU_MAX) +#endif + ) { +>>>>>>> bdcd87e62fa (feat(ble_mesh): Miscellaneous log enhancement for BLE Mesh) BT_ERR("Too large SDU len %u/%u", rx->buf.len, CONFIG_BLE_MESH_RX_SDU_MAX); send_ack(net_rx->sub, net_rx->ctx.recv_dst, net_rx->ctx.addr, net_rx->ctx.send_ttl, seq_auth, 0, rx->obo, NULL); + seg_rx_reset(rx, true); return -EMSGSIZE; @@ -2180,6 +2341,7 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, rx->block |= BIT(seg_o); if (rx->block != BLOCK_COMPLETE(seg_n)) { + BT_DBG("FrndPDUPartial"); *pdu_type = BLE_MESH_FRIEND_PDU_PARTIAL; return 0; } @@ -2203,8 +2365,8 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, if (net_rx->ctl) { err = ctl_recv(net_rx, *hdr, &rx->buf, seq_auth); } else { - err = sdu_recv(net_rx, (rx->seq_auth & 0xffffff), *hdr, - ASZMIC(hdr), &rx->buf); + err = sdu_recv(net_rx, (rx->seq_auth & 0xffffff), + *hdr, ASZMIC(hdr), &rx->buf); } seg_rx_reset(rx, false); @@ -2214,12 +2376,14 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, int bt_mesh_trans_recv(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx) { - uint64_t seq_auth = TRANS_SEQ_AUTH_NVAL; enum bt_mesh_friend_pdu_type pdu_type = BLE_MESH_FRIEND_PDU_SINGLE; struct net_buf_simple_state state = {0}; + uint64_t seq_auth = TRANS_SEQ_AUTH_NVAL; uint8_t seg_count = 0U; int err = 0; + BT_DBG("TransRecv"); + if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND)) { rx->friend_match = bt_mesh_friend_match(rx->sub->net_idx, rx->ctx.recv_dst); @@ -2227,20 +2391,21 @@ int bt_mesh_trans_recv(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx) rx->friend_match = false; } - BT_DBG("src 0x%04x dst 0x%04x seq 0x%08x friend_match %u", + BT_DBG("Src 0x%04x Dst 0x%04x Seq 0x%06x FrndMatch %u", rx->ctx.addr, rx->ctx.recv_dst, rx->seq, rx->friend_match); /* Remove network headers */ net_buf_simple_pull(buf, BLE_MESH_NET_HDR_LEN); - BT_DBG("Payload %s", bt_hex(buf->data, buf->len)); + BT_DBG("PDU %s", bt_hex(buf->data, buf->len)); /* If LPN mode is enabled messages are only accepted when we've * requested the Friend to send them. The messages must also * be encrypted using the Friend Credentials. */ if (IS_ENABLED(CONFIG_BLE_MESH_LOW_POWER) && - bt_mesh_lpn_established() && rx->net_if == BLE_MESH_NET_IF_ADV && + bt_mesh_lpn_established() && + rx->net_if == BLE_MESH_NET_IF_ADV && (!bt_mesh_lpn_waiting_update() || rx->ctx.recv_cred != BLE_MESH_FRIENDSHIP_CRED)) { BT_WARN("Ignoring unexpected message in Low Power mode"); @@ -2257,12 +2422,14 @@ int bt_mesh_trans_recv(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx) * LPN of this Friend. */ if (!rx->local_match && !rx->friend_match) { + BT_DBG("LocalAndFrndNotMatch"); return 0; } err = trans_seg(buf, rx, &pdu_type, &seq_auth, &seg_count); } else { seg_count = 1U; + err = trans_unseg(buf, rx, &seq_auth); } @@ -2300,6 +2467,8 @@ int bt_mesh_trans_recv(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx) void bt_mesh_rx_reset(void) { + BT_DBG("RxReset"); + for (size_t i = 0; i < ARRAY_SIZE(seg_rx); i++) { seg_rx_reset(&seg_rx[i], true); } @@ -2307,6 +2476,8 @@ void bt_mesh_rx_reset(void) void bt_mesh_tx_reset(void) { + BT_DBG("TxReset"); + for (size_t i = 0; i < ARRAY_SIZE(seg_tx); i++) { seg_tx_reset(&seg_tx[i]); } @@ -2314,6 +2485,8 @@ void bt_mesh_tx_reset(void) void bt_mesh_rx_reset_single(uint16_t src) { + BT_DBG("RxResetSingle, Src 0x%04x", src); + if (!BLE_MESH_ADDR_IS_UNICAST(src)) { return; } @@ -2328,6 +2501,8 @@ void bt_mesh_rx_reset_single(uint16_t src) void bt_mesh_tx_reset_single(uint16_t dst) { + BT_DBG("TxResetSingle, Dst 0x%04x", dst); + if (!BLE_MESH_ADDR_IS_UNICAST(dst)) { return; } diff --git a/components/bt/esp_ble_mesh/models/client/client_common.c b/components/bt/esp_ble_mesh/models/client/client_common.c index 7e5448707d96..211e4d84356e 100644 --- a/components/bt/esp_ble_mesh/models/client/client_common.c +++ b/components/bt/esp_ble_mesh/models/client/client_common.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,18 +16,22 @@ #if CONFIG_BLE_MESH_V11_SUPPORT #include "mesh_v1.1/utils.h" -#endif +#endif /* CONFIG_BLE_MESH_V11_SUPPORT */ #define HCI_TIME_FOR_START_ADV K_MSEC(5) /* Three adv related hci commands may take 4 ~ 5ms */ -static bt_mesh_client_node_t *bt_mesh_client_pick_node(sys_slist_t *list, uint16_t tx_dst) +static bt_mesh_client_node_t *client_pick_node(sys_slist_t *list, uint16_t tx_dst) { bt_mesh_client_node_t *node = NULL; sys_snode_t *cur = NULL; + BT_DBG("ClientPickNode, Dst 0x%04x", tx_dst); + bt_mesh_list_lock(); + if (sys_slist_is_empty(list)) { bt_mesh_list_unlock(); + BT_DBG("ListEmpty"); return NULL; } @@ -36,22 +40,28 @@ static bt_mesh_client_node_t *bt_mesh_client_pick_node(sys_slist_t *list, uint16 node = (bt_mesh_client_node_t *)cur; if (node->ctx.addr == tx_dst) { bt_mesh_list_unlock(); + BT_DBG("ListNodeFound"); return node; } } bt_mesh_list_unlock(); + + BT_DBG("ListNodeNotFound"); return NULL; } bt_mesh_client_node_t *bt_mesh_is_client_recv_publish_msg(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, - struct net_buf_simple *buf, bool need_pub) + struct net_buf_simple *buf, + bool need_pub) { bt_mesh_client_internal_data_t *data = NULL; bt_mesh_client_user_data_t *cli = NULL; bt_mesh_client_node_t *node = NULL; + BT_DBG("ClientRecvPublishMsg"); + if (!model || !ctx || !buf) { BT_ERR("%s, Invalid parameter", __func__); return NULL; @@ -63,22 +73,25 @@ bt_mesh_client_node_t *bt_mesh_is_client_recv_publish_msg(struct bt_mesh_model * return NULL; } - /** If the received message address is not a unicast address, - * the address may be a group/virtual address, and we push - * this message to the application layer. + BT_DBG("Src 0x%04x Dst 0x%04x RecvOp 0x%08lx", + ctx->addr, ctx->recv_dst, ctx->recv_op); + + /* If the received message address is not a unicast address, + * the address may be a group/virtual address, and we push + * this message to the application layer. */ if (!BLE_MESH_ADDR_IS_UNICAST(ctx->recv_dst)) { - BT_DBG("Unexpected status message 0x%08x", ctx->recv_op); + BT_DBG("MsgToNonUnicastDst"); if (cli->publish_status && need_pub) { cli->publish_status(ctx->recv_op, model, ctx, buf); } return NULL; } - /** If the source address of the received status message is - * different with the destination address of the sending - * message, then the message is from another element and - * push it to application layer. + /* If the source address of the received status message is + * different with the destination address of the sending + * message, then the message is from another element and + * push it to application layer. */ data = (bt_mesh_client_internal_data_t *)cli->internal_data; if (!data) { @@ -86,8 +99,8 @@ bt_mesh_client_node_t *bt_mesh_is_client_recv_publish_msg(struct bt_mesh_model * return NULL; } - if ((node = bt_mesh_client_pick_node(&data->queue, ctx->addr)) == NULL) { - BT_DBG("Unexpected status message 0x%08x", ctx->recv_op); + if ((node = client_pick_node(&data->queue, ctx->addr)) == NULL) { + BT_DBG("MsgFromUnknownSrc"); if (cli->publish_status && need_pub) { cli->publish_status(ctx->recv_op, model, ctx, buf); } @@ -95,7 +108,7 @@ bt_mesh_client_node_t *bt_mesh_is_client_recv_publish_msg(struct bt_mesh_model * } if (node->op_pending != ctx->recv_op) { - BT_DBG("Unexpected status message 0x%08x", ctx->recv_op); + BT_DBG("MsgWithUnknownOp"); if (cli->publish_status && need_pub) { cli->publish_status(ctx->recv_op, model, ctx, buf); } @@ -103,7 +116,7 @@ bt_mesh_client_node_t *bt_mesh_is_client_recv_publish_msg(struct bt_mesh_model * } if (k_delayed_work_remaining_get(&node->timer) == 0) { - BT_DBG("Unexpected status message 0x%08x", ctx->recv_op); + BT_DBG("MsgWithTimerExpired"); if (cli->publish_status && need_pub) { cli->publish_status(ctx->recv_op, model, ctx, buf); } @@ -113,33 +126,12 @@ bt_mesh_client_node_t *bt_mesh_is_client_recv_publish_msg(struct bt_mesh_model * return node; } -static bool bt_mesh_client_check_node_in_list(sys_slist_t *list, uint16_t tx_dst) +static uint32_t client_get_status_op(const bt_mesh_client_op_pair_t *op_pair, + int size, uint32_t opcode) { - bt_mesh_client_node_t *node = NULL; - sys_snode_t *cur = NULL; - - bt_mesh_list_lock(); - if (sys_slist_is_empty(list)) { - bt_mesh_list_unlock(); - return false; - } + BT_DBG("ClientGetStatusOp"); + BT_DBG("OpPair %p Size %u OpCode 0x%08lx", op_pair, size, opcode); - for (cur = sys_slist_peek_head(list); - cur != NULL; cur = sys_slist_peek_next(cur)) { - node = (bt_mesh_client_node_t *)cur; - if (node->ctx.addr == tx_dst) { - bt_mesh_list_unlock(); - return true; - } - } - - bt_mesh_list_unlock(); - return false; -} - -static uint32_t bt_mesh_client_get_status_op(const bt_mesh_client_op_pair_t *op_pair, - int size, uint32_t opcode) -{ if (!op_pair || size == 0) { return 0; } @@ -147,15 +139,18 @@ static uint32_t bt_mesh_client_get_status_op(const bt_mesh_client_op_pair_t *op_ const bt_mesh_client_op_pair_t *op = op_pair; for (int i = 0; i < size; i++) { if (op->cli_op == opcode) { + BT_DBG("OpCodeFound"); return op->status_op; } + op++; } + BT_DBG("OpCodeNotFound"); return 0; } -static int32_t bt_mesh_get_adv_duration(struct bt_mesh_msg_ctx *ctx) +static int32_t client_get_adv_duration(struct bt_mesh_msg_ctx *ctx) { uint16_t duration = 0, adv_int = 0; uint8_t xmit = 0; @@ -163,23 +158,28 @@ static int32_t bt_mesh_get_adv_duration(struct bt_mesh_msg_ctx *ctx) /* Initialize with network transmission */ xmit = bt_mesh_net_transmit_get(); + BT_DBG("ClientGetAdvDuration, Xmit 0x%02x", xmit); + if (bt_mesh_tag_immutable_cred(ctx->send_tag)) { #if CONFIG_BLE_MESH_DF_SRV if (ctx->send_cred == BLE_MESH_DIRECTED_CRED) { xmit = bt_mesh_direct_net_transmit_get(); /* Directed network transmission */ + BT_DBG("UseDFXmit 0x%02x", xmit); } -#endif +#endif /* CONFIG_BLE_MESH_DF_SRV */ } adv_int = BLE_MESH_TRANSMIT_INT(xmit); duration = (BLE_MESH_TRANSMIT_COUNT(xmit) + 1) * (adv_int + 10); + BT_DBG("Duration %ld", (int32_t)duration); + return (int32_t)duration; } -static int32_t bt_mesh_client_calc_timeout(struct bt_mesh_msg_ctx *ctx, - struct net_buf_simple *msg, - uint32_t opcode, int32_t timeout) +static int32_t client_calc_timeout(struct bt_mesh_msg_ctx *ctx, + struct net_buf_simple *msg, + uint32_t opcode, int32_t timeout) { int32_t seg_rtx_to = 0, duration = 0, time = 0; uint8_t seg_count = 0, seg_rtx_num = 0; @@ -195,6 +195,8 @@ static int32_t bt_mesh_client_calc_timeout(struct bt_mesh_msg_ctx *ctx, net_buf_simple_tailroom(msg) >= BLE_MESH_MIC_LONG) ? BLE_MESH_MIC_LONG : BLE_MESH_MIC_SHORT; + BT_DBG("NeedSeg %u MicSize %u", need_seg, mic_size); + if (need_seg) { /* Based on the message length, calculate how many segments are needed. * All the messages sent from here are access messages. @@ -203,7 +205,7 @@ static int32_t bt_mesh_client_calc_timeout(struct bt_mesh_msg_ctx *ctx, seg_rtx_to = bt_mesh_get_seg_rtx_timeout(ctx->addr, ctx->send_ttl); seg_count = (msg->len + mic_size - 1) / 12U + 1U; - duration = bt_mesh_get_adv_duration(ctx); + duration = client_get_adv_duration(ctx); /* Currently only consider the time consumption of the same segmented * messages, but if there are other messages between any two retrans- @@ -242,7 +244,7 @@ static void msg_send_start(uint16_t duration, int err, void *cb_data) { bt_mesh_client_node_t *node = cb_data; - BT_DBG("%s, duration %ums", __func__, duration); + BT_DBG("MsgSendStart, Duration %u Err %d", duration, err); if (err) { if (!k_delayed_work_free(&node->timer)) { @@ -268,6 +270,8 @@ int bt_mesh_client_send_msg(bt_mesh_client_common_param_t *param, bt_mesh_client_node_t *node = NULL; int err = 0; + BT_DBG("ClientSendMsg, NeedAck %u", need_ack); + if (!param || !param->model || !msg) { BT_ERR("%s, Invalid parameter", __func__); return -EINVAL; @@ -309,7 +313,7 @@ int bt_mesh_client_send_msg(bt_mesh_client_common_param_t *param, return -EINVAL; } - if (bt_mesh_client_check_node_in_list(&internal->queue, param->ctx.addr)) { + if (client_pick_node(&internal->queue, param->ctx.addr)) { BT_ERR("Busy sending message to DST 0x%04x", param->ctx.addr); return -EBUSY; } @@ -324,14 +328,15 @@ int bt_mesh_client_send_msg(bt_mesh_client_common_param_t *param, memcpy(&node->ctx, ¶m->ctx, sizeof(struct bt_mesh_msg_ctx)); node->model = param->model; node->opcode = param->opcode; - node->op_pending = bt_mesh_client_get_status_op(client->op_pair, client->op_pair_size, param->opcode); + node->op_pending = client_get_status_op(client->op_pair, client->op_pair_size, param->opcode); if (node->op_pending == 0U) { BT_ERR("Status opcode not found in op_pair list, opcode 0x%08x", param->opcode); bt_mesh_free(node); return -EINVAL; } - node->timeout = bt_mesh_client_calc_timeout(¶m->ctx, msg, param->opcode, - param->msg_timeout ? param->msg_timeout : CONFIG_BLE_MESH_CLIENT_MSG_TIMEOUT); + node->timeout = client_calc_timeout(¶m->ctx, msg, param->opcode, + (param->msg_timeout ? param->msg_timeout : + CONFIG_BLE_MESH_CLIENT_MSG_TIMEOUT)); if (k_delayed_work_init(&node->timer, timer_handler)) { BT_ERR("Failed to create a timer"); @@ -374,6 +379,8 @@ int bt_mesh_client_init(struct bt_mesh_model *model) bt_mesh_client_internal_data_t *internal = NULL; bt_mesh_client_user_data_t *client = NULL; + BT_DBG("ClientInit"); + if (!model || !model->op) { BT_ERR("Invalid vendor client model"); return -EINVAL; @@ -411,6 +418,8 @@ int bt_mesh_client_deinit(struct bt_mesh_model *model) { bt_mesh_client_user_data_t *client = NULL; + BT_DBG("ClientDeinit"); + if (!model) { BT_ERR("Invalid vendor client model"); return -EINVAL; @@ -442,6 +451,8 @@ int bt_mesh_client_free_node(bt_mesh_client_node_t *node) bt_mesh_client_internal_data_t *internal = NULL; bt_mesh_client_user_data_t *client = NULL; + BT_DBG("ClientFreeNode"); + if (!node || !node->model) { BT_ERR("Invalid client list item"); return -EINVAL; @@ -459,12 +470,10 @@ int bt_mesh_client_free_node(bt_mesh_client_node_t *node) return -EINVAL; } - // Release the client node from the queue bt_mesh_list_lock(); sys_slist_find_and_remove(&internal->queue, &node->client_node); bt_mesh_list_unlock(); - // Free the node bt_mesh_free(node); return 0; @@ -475,6 +484,8 @@ int bt_mesh_client_clear_list(void *data) bt_mesh_client_internal_data_t *internal = NULL; bt_mesh_client_node_t *node = NULL; + BT_DBG("ClientClearList"); + if (!data) { BT_ERR("%s, Invalid parameter", __func__); return -EINVAL; @@ -483,11 +494,13 @@ int bt_mesh_client_clear_list(void *data) internal = (bt_mesh_client_internal_data_t *)data; bt_mesh_list_lock(); + while (!sys_slist_is_empty(&internal->queue)) { node = (void *)sys_slist_get_not_empty(&internal->queue); k_delayed_work_free(&node->timer); bt_mesh_free(node); } + bt_mesh_list_unlock(); return 0; diff --git a/components/bt/host/bluedroid/Kconfig.in b/components/bt/host/bluedroid/Kconfig.in index 7b71a79c7e35..244924dd57fd 100644 --- a/components/bt/host/bluedroid/Kconfig.in +++ b/components/bt/host/bluedroid/Kconfig.in @@ -33,13 +33,6 @@ config BT_BTU_TASK_STACK_SIZE help This select btu task stack size -config BT_BLUEDROID_MEM_DEBUG - bool "Bluedroid memory debug" - depends on BT_BLUEDROID_ENABLED - default n - help - Bluedroid memory debug - config BT_BLUEDROID_ESP_COEX_VSC bool "Enable Espressif Vendor-specific HCI commands for coexist status configuration" depends on BT_BLUEDROID_ENABLED @@ -421,6 +414,40 @@ config BT_BLE_RPA_SUPPORTED For other BLE chips, devices support network privacy mode and device privacy mode, users can switch the two modes according to their own needs. So this option is enabled by default. +menu "Bluedroid debug option" + config BT_BLUEDROID_MEM_DEBUG + bool "Bluedroid memory debug" + depends on BT_BLUEDROID_ENABLED + default n + help + Bluedroid memory debug + + config BT_BLUEDROID_THREAD_DEBUG + bool "Bluedroid thread debug" + depends on BT_BLUEDROID_ENABLED + default n + help + Enable Bluedroid thread debug mode. + Used to debug whether the thread is blocked and + dump information about the thread’s related work queue. + + config BT_BLUEDROID_THREAD_BLOCK_TIME + int "OSI thread block time (in ms)" + depends on BT_BLUEDROID_THREAD_DEBUG + default 1000 + help + Indicates how long it takes for the thread to execute an item + before it is considered blocked. + + config BT_BLUEDROID_THREAD_BLOCK_MSG + int "OSI thread block message count" + depends on BT_BLUEDROID_THREAD_DEBUG + default 50 + help + Indicates how many messages are added to the queue + while the threadis executing an item before it is considered blocked. +endmenu #BT debug option + config BT_STACK_NO_LOG bool "Disable BT debug logs (minimize bin size)" depends on BT_BLUEDROID_ENABLED diff --git a/components/bt/host/bluedroid/api/esp_hidd_api.c b/components/bt/host/bluedroid/api/esp_hidd_api.c index d7c043666d15..483ba4129196 100644 --- a/components/bt/host/bluedroid/api/esp_hidd_api.c +++ b/components/bt/host/bluedroid/api/esp_hidd_api.c @@ -133,7 +133,7 @@ esp_err_t esp_bt_hid_device_send_report(esp_hidd_report_type_t type, uint8_t id, args.send_report.data = data; bt_status_t stat = btc_transfer_context(&msg, &args, sizeof(btc_hidd_args_t), - btc_hd_arg_deep_copy, btc_hd_cb_arg_deep_free); + btc_hd_arg_deep_copy, btc_hd_call_arg_deep_free); return (stat == BT_STATUS_SUCCESS) ? ESP_OK : ESP_FAIL; } diff --git a/components/bt/host/bluedroid/api/esp_hidh_api.c b/components/bt/host/bluedroid/api/esp_hidh_api.c index e029ee654a0b..f1c39bded884 100644 --- a/components/bt/host/bluedroid/api/esp_hidh_api.c +++ b/components/bt/host/bluedroid/api/esp_hidh_api.c @@ -117,7 +117,7 @@ esp_err_t esp_bt_hid_host_set_info(esp_bd_addr_t bd_addr, esp_hidh_hid_info_t *h arg.set_info.hid_info = hid_info; bt_status_t stat = btc_transfer_context(&msg, &arg, sizeof(btc_hidh_args_t), - btc_hh_arg_deep_copy, btc_hh_cb_arg_deep_free); + btc_hh_arg_deep_copy, btc_hh_call_arg_deep_free); return (stat == BT_STATUS_SUCCESS) ? ESP_OK : ESP_FAIL; } @@ -224,7 +224,7 @@ esp_err_t esp_bt_hid_host_set_report(esp_bd_addr_t bd_addr, esp_hidh_report_type arg.set_report.report = report; bt_status_t stat = btc_transfer_context(&msg, &arg, sizeof(btc_hidh_args_t), - btc_hh_arg_deep_copy, btc_hh_cb_arg_deep_free); + btc_hh_arg_deep_copy, btc_hh_call_arg_deep_free); return (stat == BT_STATUS_SUCCESS) ? ESP_OK : ESP_FAIL; } @@ -243,7 +243,7 @@ esp_err_t esp_bt_hid_host_send_data(esp_bd_addr_t bd_addr, uint8_t *data, size_t arg.send_data.data = data; bt_status_t stat = btc_transfer_context(&msg, &arg, sizeof(btc_hidh_args_t), - btc_hh_arg_deep_copy, btc_hh_cb_arg_deep_free); + btc_hh_arg_deep_copy, btc_hh_call_arg_deep_free); return (stat == BT_STATUS_SUCCESS) ? ESP_OK : ESP_FAIL; } diff --git a/components/bt/host/bluedroid/api/esp_spp_api.c b/components/bt/host/bluedroid/api/esp_spp_api.c index 5c01aeb2e511..18ef661c165c 100644 --- a/components/bt/host/bluedroid/api/esp_spp_api.c +++ b/components/bt/host/bluedroid/api/esp_spp_api.c @@ -145,22 +145,34 @@ esp_err_t esp_spp_disconnect(uint32_t handle) esp_err_t esp_spp_start_srv(esp_spp_sec_t sec_mask, esp_spp_role_t role, uint8_t local_scn, const char *name) +{ + esp_spp_start_srv_cfg_t cfg = {0}; + + cfg.local_scn = local_scn; + cfg.sec_mask = sec_mask; + cfg.role = role; + cfg.create_spp_record = true; + cfg.name = name; + return esp_spp_start_srv_with_cfg(&cfg); +} + +esp_err_t esp_spp_start_srv_with_cfg(const esp_spp_start_srv_cfg_t *cfg) { btc_msg_t msg; btc_spp_args_t arg; ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED); - if (name == NULL || strlen(name) > ESP_SPP_SERVER_NAME_MAX) { + if (cfg == NULL || cfg->name == NULL || strlen(cfg->name) > ESP_SPP_SERVER_NAME_MAX) { LOG_ERROR("Invalid server name!\n"); return ESP_ERR_INVALID_ARG; } - if (sec_mask != ESP_SPP_SEC_NONE && - sec_mask != ESP_SPP_SEC_AUTHENTICATE && - sec_mask != (ESP_SPP_SEC_AUTHENTICATE | ESP_SPP_SEC_ENCRYPT) && - sec_mask != ESP_SPP_SEC_IN_16_DIGITS && - sec_mask != (ESP_SPP_SEC_IN_16_DIGITS | ESP_SPP_SEC_AUTHENTICATE) && - sec_mask != (ESP_SPP_SEC_IN_16_DIGITS | ESP_SPP_SEC_AUTHENTICATE | ESP_SPP_SEC_ENCRYPT)) { + if (cfg->sec_mask != ESP_SPP_SEC_NONE && + cfg->sec_mask != ESP_SPP_SEC_AUTHENTICATE && + cfg->sec_mask != (ESP_SPP_SEC_AUTHENTICATE | ESP_SPP_SEC_ENCRYPT) && + cfg->sec_mask != ESP_SPP_SEC_IN_16_DIGITS && + cfg->sec_mask != (ESP_SPP_SEC_IN_16_DIGITS | ESP_SPP_SEC_AUTHENTICATE) && + cfg->sec_mask != (ESP_SPP_SEC_IN_16_DIGITS | ESP_SPP_SEC_AUTHENTICATE | ESP_SPP_SEC_ENCRYPT)) { LOG_WARN("Suggest to use ESP_SPP_SEC_NONE, ESP_SPP_SEC_AUTHENTICATE," "(ESP_SPP_SEC_AUTHENTICATE | ESP_SPP_SEC_ENCRYPT)," "ESP_SPP_SEC_IN_16_DIGITS, (ESP_SPP_SEC_IN_16_DIGITS | ESP_SPP_SEC_AUTHENTICATE), or" @@ -171,11 +183,12 @@ esp_err_t esp_spp_start_srv(esp_spp_sec_t sec_mask, msg.pid = BTC_PID_SPP; msg.act = BTC_SPP_ACT_START_SRV; - arg.start_srv.sec_mask = sec_mask; - arg.start_srv.role = role; - arg.start_srv.local_scn = local_scn; + arg.start_srv.sec_mask = cfg->sec_mask; + arg.start_srv.role = cfg->role; + arg.start_srv.local_scn = cfg->local_scn; + arg.start_srv.create_spp_record = cfg->create_spp_record; arg.start_srv.max_session = ESP_SPP_MAX_SESSION; - strcpy(arg.start_srv.name, name); + strcpy(arg.start_srv.name, cfg->name); return (btc_transfer_context(&msg, &arg, sizeof(btc_spp_args_t), NULL, NULL) == BT_STATUS_SUCCESS ? ESP_OK : ESP_FAIL); } diff --git a/components/bt/host/bluedroid/api/include/api/esp_spp_api.h b/components/bt/host/bluedroid/api/include/api/esp_spp_api.h index 40788667c027..e6cdf2fc6928 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_spp_api.h +++ b/components/bt/host/bluedroid/api/include/api/esp_spp_api.h @@ -74,7 +74,7 @@ typedef enum { } esp_spp_mode_t; /** - * @brief SPP configuration parameters + * @brief SPP initialization configuration parameters. */ typedef struct { esp_spp_mode_t mode; /*!< Choose the mode of SPP, ESP_SPP_MODE_CB or ESP_SPP_MODE_VFS. */ @@ -82,6 +82,17 @@ typedef struct { uint16_t tx_buffer_size; /*!< Tx buffer size for a new SPP channel. A smaller setting can save memory, but may incur a decrease in throughput. Only for ESP_SPP_MODE_VFS mode. */ } esp_spp_cfg_t; +/** + * @brief SPP start server configuration parameters. + */ +typedef struct { + uint8_t local_scn; /*!< The specific channel you want to get. If channel is 0, means get any channel. */ + bool create_spp_record; /*!< Specifies whether to create the SPP record */ + esp_spp_sec_t sec_mask; /*!< Security Setting Mask. Suggest to use ESP_SPP_SEC_NONE, ESP_SPP_SEC_AUTHORIZE or ESP_SPP_SEC_AUTHENTICATE only */ + esp_spp_role_t role; /*!< Master or slave. */ + const char *name; /*!< Server's name. */ +} esp_spp_start_srv_cfg_t; + /** * @brief SPP callback function events */ @@ -368,6 +379,19 @@ esp_err_t esp_spp_disconnect(uint32_t handle); */ esp_err_t esp_spp_start_srv(esp_spp_sec_t sec_mask, esp_spp_role_t role, uint8_t local_scn, const char *name); +/** + * @brief This function is similar to `esp_spp_start_srv`. + * The only difference is that it adds a parameter to specify whether to create the SPP record. + * @note If the SPP record is not created, it is suggested to use it together with the SDP API. + * + * @param[in] cfg: Configuration parameters for starting the server. + * + * @return + * - ESP_OK: success + * - other: failed + */ +esp_err_t esp_spp_start_srv_with_cfg(const esp_spp_start_srv_cfg_t *cfg); + /** * @brief This function stops all SPP servers. * The operation will close all active SPP connection first, then the callback function will be called diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_act.c b/components/bt/host/bluedroid/bta/dm/bta_dm_act.c index 3ec7ae2aff5a..c0383286a206 100644 --- a/components/bt/host/bluedroid/bta/dm/bta_dm_act.c +++ b/components/bt/host/bluedroid/bta/dm/bta_dm_act.c @@ -2056,7 +2056,7 @@ void bta_dm_sdp_result (tBTA_DM_MSG *p_data) #endif UINT32 num_uuids = 0; - UINT8 uuid_list[32][MAX_UUID_SIZE]; // assuming a max of 32 services + UINT8 uuid_list[MAX_UUID_NUM][MAX_UUID_SIZE]; // assuming a max of MAX_UUID_NUM services if ((p_data->sdp_event.sdp_result == SDP_SUCCESS) || (p_data->sdp_event.sdp_result == SDP_NO_RECS_MATCH) @@ -2119,8 +2119,12 @@ void bta_dm_sdp_result (tBTA_DM_MSG *p_data) (tBTA_SERVICE_MASK)(BTA_SERVICE_ID_TO_SERVICE_MASK(bta_dm_search_cb.service_index - 1)); tmp_svc = bta_service_id_to_uuid_lkup_tbl[bta_dm_search_cb.service_index - 1]; /* Add to the list of UUIDs */ - sdpu_uuid16_to_uuid128(tmp_svc, uuid_list[num_uuids]); - num_uuids++; + if (num_uuids < MAX_UUID_NUM) { + sdpu_uuid16_to_uuid128(tmp_svc, uuid_list[num_uuids]); + num_uuids++; + } else { + APPL_TRACE_WARNING("only process the first %d records\n", MAX_UUID_NUM); + } } } } @@ -2154,8 +2158,13 @@ void bta_dm_sdp_result (tBTA_DM_MSG *p_data) p_sdp_rec = SDP_FindServiceInDb_128bit(bta_dm_search_cb.p_sdp_db, p_sdp_rec); if (p_sdp_rec) { if (SDP_FindServiceUUIDInRec_128bit(p_sdp_rec, &temp_uuid)) { - memcpy(uuid_list[num_uuids], temp_uuid.uu.uuid128, MAX_UUID_SIZE); - num_uuids++; + if (num_uuids < MAX_UUID_NUM) { + memcpy(uuid_list[num_uuids], temp_uuid.uu.uuid128, MAX_UUID_SIZE); + num_uuids++; + } else { + APPL_TRACE_WARNING("only process the first %d records\n", MAX_UUID_NUM); + break; + } } } } while (p_sdp_rec); diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_co.c b/components/bt/host/bluedroid/bta/dm/bta_dm_co.c index 5c7ee9bdede2..085697acb90c 100644 --- a/components/bt/host/bluedroid/bta/dm/bta_dm_co.c +++ b/components/bt/host/bluedroid/bta/dm/bta_dm_co.c @@ -63,7 +63,15 @@ void bta_dm_co_security_param_init(void) bte_appl_cfg.ble_min_key_size = BTM_BLE_MIN_KEY_SIZE; bte_appl_cfg.ble_accept_auth_enable = BTM_BLE_ONLY_ACCEPT_SPECIFIED_SEC_AUTH_DISABLE; bte_appl_cfg.oob_support = BTM_BLE_OOB_DISABLE; -}; + + APPL_TRACE_DEBUG("%s: auth_req=%u, io_cap=%u, init_key=%u, resp_key=%u, " + "max_key_size=%u, min_key_size=%u, accept_auth=%u, oob=%u", + __func__, + bte_appl_cfg.ble_auth_req, bte_appl_cfg.ble_io_cap, + bte_appl_cfg.ble_init_key, bte_appl_cfg.ble_resp_key, + bte_appl_cfg.ble_max_key_size, bte_appl_cfg.ble_min_key_size, + bte_appl_cfg.ble_accept_auth_enable, bte_appl_cfg.oob_support); +} #endif #if (defined CLASSIC_BT_INCLUDED && CLASSIC_BT_INCLUDED == TRUE) @@ -379,6 +387,7 @@ void bta_dm_co_ble_set_io_cap(UINT8 ble_io_cap) #if (SMP_INCLUDED == TRUE) if(ble_io_cap < BTM_IO_CAP_MAX ) { bte_appl_cfg.ble_io_cap = ble_io_cap; + APPL_TRACE_DEBUG("%s: ble_io_cap set to %u", __func__, ble_io_cap); } else { APPL_TRACE_ERROR("%s error:Invalid io cap value.",__func__); } @@ -389,22 +398,25 @@ void bta_dm_co_ble_set_auth_req(UINT8 ble_auth_req) { #if (SMP_INCLUDED == TRUE) bte_appl_cfg.ble_auth_req = ble_auth_req; -#endif ///SMP_INCLUDED == TRUE + APPL_TRACE_DEBUG("%s: ble_auth_req set to %u", __func__, ble_auth_req); +#endif } void bta_dm_co_ble_set_init_key_req(UINT8 init_key) { #if (SMP_INCLUDED == TRUE) - init_key &= 0x0f; // 4~7bit reservd, only used the 0~3bit + init_key &= 0x0f; // 4~7bit reserved, only used the 0~3bit bte_appl_cfg.ble_init_key = init_key; -#endif ///SMP_INCLUDED == TRUE + APPL_TRACE_DEBUG("%s: init_key set to 0x%x", __func__, init_key); +#endif } void bta_dm_co_ble_set_rsp_key_req(UINT8 rsp_key) { #if (SMP_INCLUDED == TRUE) - rsp_key &= 0x0f; // 4~7bit reservd, only used the 0~3bit + rsp_key &= 0x0f; // 4~7bit reserved, only used the 0~3bit bte_appl_cfg.ble_resp_key = rsp_key; + APPL_TRACE_DEBUG("%s: rsp_key set to 0x%x", __func__, rsp_key); #endif ///SMP_INCLUDED == TRUE } @@ -413,6 +425,7 @@ void bta_dm_co_ble_set_max_key_size(UINT8 ble_key_size) #if (SMP_INCLUDED == TRUE) if(ble_key_size >= bte_appl_cfg.ble_min_key_size && ble_key_size <= BTM_BLE_MAX_KEY_SIZE) { bte_appl_cfg.ble_max_key_size = ble_key_size; + APPL_TRACE_DEBUG("%s: max_key_size set to %d", __func__, ble_key_size); } else { APPL_TRACE_ERROR("%s error:Invalid key size value, key_size =%d",__func__, ble_key_size); } @@ -424,6 +437,7 @@ void bta_dm_co_ble_set_min_key_size(UINT8 ble_key_size) #if (SMP_INCLUDED == TRUE) if(ble_key_size >= BTM_BLE_MIN_KEY_SIZE && ble_key_size <= bte_appl_cfg.ble_max_key_size) { bte_appl_cfg.ble_min_key_size = ble_key_size; + APPL_TRACE_DEBUG("%s: min_key_size set to %u", __func__, ble_key_size); } else { APPL_TRACE_ERROR("%s error:Invalid key size value, key_size =%d",__func__, ble_key_size); } @@ -437,6 +451,7 @@ void bta_dm_co_ble_set_accept_auth_enable(UINT8 enable) enable = BTM_BLE_ONLY_ACCEPT_SPECIFIED_SEC_AUTH_ENABLE; } bte_appl_cfg.ble_accept_auth_enable = enable; + APPL_TRACE_DEBUG("%s: accept_auth_enable set to %u", __func__, enable); #endif ///SMP_INCLUDED == TRUE } @@ -464,6 +479,7 @@ void bta_dm_co_ble_oob_support(UINT8 enable) } else { bte_appl_cfg.oob_support = BTM_BLE_OOB_DISABLE; } + APPL_TRACE_DEBUG("%s: oob_support set to %u", __func__, bte_appl_cfg.oob_support); #endif ///SMP_INCLUDED == TRUE } diff --git a/components/bt/host/bluedroid/bta/gatt/bta_gattc_act.c b/components/bt/host/bluedroid/bta/gatt/bta_gattc_act.c index eb2b091eae1d..06c565dc2d21 100644 --- a/components/bt/host/bluedroid/bta/gatt/bta_gattc_act.c +++ b/components/bt/host/bluedroid/bta/gatt/bta_gattc_act.c @@ -727,6 +727,7 @@ void bta_gattc_conn(tBTA_GATTC_CLCB *p_clcb, tBTA_GATTC_DATA *p_data) #if (GATTC_CACHE_NVS == TRUE) p_clcb->p_srcb->state = BTA_GATTC_SERV_LOAD; if (bta_gattc_cache_load(p_clcb)) { + APPL_TRACE_DEBUG("%s found gattc cache", __func__); p_clcb->p_srcb->state = BTA_GATTC_SERV_IDLE; bta_gattc_reset_discover_st(p_clcb->p_srcb, BTA_GATT_OK); //register service change @@ -734,6 +735,7 @@ void bta_gattc_conn(tBTA_GATTC_CLCB *p_clcb, tBTA_GATTC_DATA *p_data) } else #endif { /* cache is building */ + APPL_TRACE_DEBUG("%s cache not found, start discovery %u", __func__, bta_gattc_cb.auto_disc); if (bta_gattc_cb.auto_disc) { p_clcb->p_srcb->state = BTA_GATTC_SERV_DISC; /* cache load failure, start discovery */ @@ -1847,6 +1849,8 @@ void bta_gattc_process_api_refresh(tBTA_GATTC_CB *p_cb, tBTA_GATTC_DATA *p_msg) UINT8 i; UNUSED(p_cb); + APPL_TRACE_DEBUG("%s", __func__); + if (p_srvc_cb != NULL) { /* try to find a CLCB */ if (p_srvc_cb->connected && p_srvc_cb->num_clcb != 0) { @@ -1965,6 +1969,8 @@ void bta_gattc_process_api_cache_clean(tBTA_GATTC_CB *p_cb, tBTA_GATTC_DATA *p_m tBTA_GATTC_SERV *p_srvc_cb = bta_gattc_find_srvr_cache(p_msg->api_clean.remote_bda); UNUSED(p_cb); + APPL_TRACE_DEBUG("%s", __func__); + if (p_srvc_cb != NULL && p_srvc_cb->p_srvc_cache != NULL) { //mark it and delete the cache */ list_free(p_srvc_cb->p_srvc_cache); diff --git a/components/bt/host/bluedroid/bta/gatt/bta_gattc_co.c b/components/bt/host/bluedroid/bta/gatt/bta_gattc_co.c index 8ec3a55dffd9..d6ca7bca475b 100644 --- a/components/bt/host/bluedroid/bta/gatt/bta_gattc_co.c +++ b/components/bt/host/bluedroid/bta/gatt/bta_gattc_co.c @@ -444,6 +444,8 @@ void bta_gattc_co_cache_addr_init(void) void bta_gattc_co_cache_addr_deinit(void) { + APPL_TRACE_DEBUG("%s is_open=%d", __func__, cache_env->is_open); + if(!cache_env->is_open) { return; } @@ -553,7 +555,7 @@ void bta_gattc_co_cache_addr_save(BD_ADDR bd_addr, hash_key_t hash_key) memcpy(cache_env->cache_addr[new_index].addr, bd_addr, sizeof(BD_ADDR)); memcpy(cache_env->cache_addr[new_index].hash_key, hash_key, sizeof(hash_key_t)); cache_env->num_addr++; - APPL_TRACE_DEBUG("%s(), num = %d", __func__, cache_env->num_addr); + APPL_TRACE_DEBUG("%s bd_addr="MACSTR" num=%d", __func__, MAC2STR(bd_addr), cache_env->num_addr); } nvs_handle_t *fp = &cache_env->addr_fp; diff --git a/components/bt/host/bluedroid/bta/gatt/bta_gattc_utils.c b/components/bt/host/bluedroid/bta/gatt/bta_gattc_utils.c index b47a9d973345..4b2d01925295 100644 --- a/components/bt/host/bluedroid/bta/gatt/bta_gattc_utils.c +++ b/components/bt/host/bluedroid/bta/gatt/bta_gattc_utils.c @@ -327,6 +327,8 @@ void bta_gattc_clcb_dealloc_by_conn_id(UINT16 conn_id) { tBTA_GATTC_CLCB *p_clcb = bta_gattc_find_clcb_by_conn_id(conn_id); + APPL_TRACE_DEBUG("%s conn_id=%u p_clcb=%p", __func__, conn_id, p_clcb); + if (p_clcb) { tBTA_GATTC_RCB *p_clreg = p_clcb->p_rcb; bta_gattc_clcb_dealloc(p_clcb); diff --git a/components/bt/host/bluedroid/bta/include/bta/bta_gatt_api.h b/components/bt/host/bluedroid/bta/include/bta/bta_gatt_api.h index a42d14084ba2..0208edd95491 100644 --- a/components/bt/host/bluedroid/bta/include/bta/bta_gatt_api.h +++ b/components/bt/host/bluedroid/bta/include/bta/bta_gatt_api.h @@ -39,9 +39,11 @@ #endif +#if (APPL_INITIAL_TRACE_LEVEL >= BT_TRACE_LEVEL_DEBUG) #ifndef BTA_GATT_DEBUG #define BTA_GATT_DEBUG FALSE #endif +#endif typedef enum { BTGATT_DB_PRIMARY_SERVICE, diff --git a/components/bt/host/bluedroid/btc/core/btc_ble_storage.c b/components/bt/host/bluedroid/btc/core/btc_ble_storage.c index f20a7241e174..aef3863111f5 100644 --- a/components/bt/host/bluedroid/btc/core/btc_ble_storage.c +++ b/components/bt/host/bluedroid/btc/core/btc_ble_storage.c @@ -16,7 +16,7 @@ #if (SMP_INCLUDED == TRUE) //the maximum number of bonded devices -#define BONED_DEVICES_MAX_COUNT (BTM_SEC_MAX_DEVICE_RECORDS) +#define BONED_DEVICES_MAX_COUNT (BTM_SEC_MAX_BONDS) static void _btc_storage_save(void) { diff --git a/components/bt/host/bluedroid/btc/core/btc_dev.c b/components/bt/host/bluedroid/btc/core/btc_dev.c index 18cda3e0d864..424dfe93e59f 100644 --- a/components/bt/host/bluedroid/btc/core/btc_dev.c +++ b/components/bt/host/bluedroid/btc/core/btc_dev.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/bt/host/bluedroid/btc/core/btc_dm.c b/components/bt/host/bluedroid/btc/core/btc_dm.c index 782569c2993e..02b5a16ef4c3 100644 --- a/components/bt/host/bluedroid/btc/core/btc_dm.c +++ b/components/bt/host/bluedroid/btc/core/btc_dm.c @@ -784,6 +784,7 @@ void btc_dm_sec_cb_handler(btc_msg_t *msg) ble_msg->pid = BTC_PID_GAP_BLE; // tBTA_SERVICE_MASK service_mask; BTC_TRACE_DEBUG("btc_dm_upstreams_cback ev: %d\n", msg->act); + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); switch (msg->act) { case BTA_DM_ENABLE_EVT: { diff --git a/components/bt/host/bluedroid/btc/core/btc_main.c b/components/bt/host/bluedroid/btc/core/btc_main.c index d7330cc6f7d7..593bb99e0710 100644 --- a/components/bt/host/bluedroid/btc/core/btc_main.c +++ b/components/bt/host/bluedroid/btc/core/btc_main.c @@ -97,7 +97,7 @@ static void btc_deinit_bluetooth(void) void btc_main_call_handler(btc_msg_t *msg) { - BTC_TRACE_DEBUG("%s act %d\n", __func__, msg->act); + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); switch (msg->act) { case BTC_MAIN_ACT_INIT: @@ -127,101 +127,132 @@ uint32_t btc_get_ble_status(void) return status; } - #if (BLE_INCLUDED == TRUE) +#if (BLE_INCLUDED == TRUE) // Number of active advertising extern uint8_t btm_ble_adv_active_count(void); - if (btm_ble_adv_active_count()) { + uint8_t adv_cnt = btm_ble_adv_active_count(); + if (adv_cnt) { + BTC_TRACE_WARNING("%s advertising active, cnt %d", __func__, adv_cnt); status |= BIT(BTC_BLE_STATUS_ADV); } // Number of active scanning extern uint8_t btm_ble_scan_active_count(void); - if (btm_ble_scan_active_count()) { + uint8_t scan_cnt = btm_ble_scan_active_count(); + if (scan_cnt) { + BTC_TRACE_WARNING("%s scan active, cnt %d", __func__, scan_cnt); status |= BIT(BTC_BLE_STATUS_SCAN); } // Number of active GATT tcb extern uint8_t gatt_tcb_active_count(void); - if (gatt_tcb_active_count()) { + uint8_t gatt_tcb_cnt = gatt_tcb_active_count(); + if (gatt_tcb_cnt) { + BTC_TRACE_WARNING("%s gatt tcb active, cnt %d", __func__, gatt_tcb_cnt); status |= BIT(BTC_BLE_STATUS_CONN); } // Number of active ACL connection extern uint8_t btm_ble_acl_active_count(void); - if (btm_ble_acl_active_count()) { + uint8_t acl_cnt = btm_ble_acl_active_count(); + if (acl_cnt) { + BTC_TRACE_WARNING("%s acl connection active, cnt %d", __func__, acl_cnt); status |= BIT(BTC_BLE_STATUS_CONN); } // Number of active L2C plcb extern uint8_t l2cu_ble_plcb_active_count(void); - if (l2cu_ble_plcb_active_count()) { + uint8_t plcb_cnt = l2cu_ble_plcb_active_count(); + if (plcb_cnt) { + BTC_TRACE_WARNING("%s l2c plcb active, cnt %d", __func__, plcb_cnt); status |= BIT(BTC_BLE_STATUS_CONN); } // Address resolve status extern uint8_t btm_get_ble_addr_resolve_disable_status(void); - if (btm_get_ble_addr_resolve_disable_status()) { + uint8_t addr_resolve_disable = btm_get_ble_addr_resolve_disable_status(); + if (addr_resolve_disable) { + BTC_TRACE_WARNING("%s address resolve disabled", __func__); status |= BIT(BTC_BLE_STATUS_ADDR_RESOLVE_DISABLE); } - #if (SMP_INCLUDED == TRUE) +#if (SMP_INCLUDED == TRUE) // Number of recorded devices extern uint8_t btm_ble_sec_dev_record_count(void); - if (btm_ble_sec_dev_record_count()) { + uint8_t sec_dev_cnt = btm_ble_sec_dev_record_count(); + if (sec_dev_cnt) { + BTC_TRACE_WARNING("%s security device record count %d", __func__, sec_dev_cnt); status |= BIT(BTC_BLE_STATUS_DEVICE_REC); } // Number of saved bonded devices - if (btc_storage_get_num_ble_bond_devices()) { + int bond_cnt = btc_storage_get_num_ble_bond_devices(); + if (bond_cnt) { + BTC_TRACE_WARNING("%s bonded devices count %d", __func__, bond_cnt); status |= BIT(BTC_BLE_STATUS_BOND); } - #endif +#endif // SMP_INCLUDED - #if (BLE_PRIVACY_SPT == TRUE) +#if (BLE_PRIVACY_SPT == TRUE) // Privacy enabled extern uint8_t btm_ble_privacy_is_enabled(void); - if (btm_ble_privacy_is_enabled()) { + uint8_t privacy_en = btm_ble_privacy_is_enabled(); + if (privacy_en) { + BTC_TRACE_WARNING("%s privacy enabled", __func__); status |= BIT(BTC_BLE_STATUS_PRIVACY); } - #endif - #endif +#endif // BLE_PRIVACY_SPT + +#endif // BLE_INCLUDED - #if (BLE_50_EXTEND_ADV_EN == TRUE) +#if (BLE_50_EXTEND_ADV_EN == TRUE) // Number of active extended advertsing extern uint8_t btm_ble_ext_adv_active_count(void); - if (btm_ble_ext_adv_active_count()) { + uint8_t ext_adv_cnt = btm_ble_ext_adv_active_count(); + if (ext_adv_cnt) { + BTC_TRACE_WARNING("%s extended advertising active, cnt %d", __func__, ext_adv_cnt); status |= BIT(BTC_BLE_STATUS_EXT_ADV); } - #endif +#endif // (BLE_50_EXTEND_ADV_EN == TRUE) - #if (GATTC_INCLUDED == TRUE) +#if (GATTC_INCLUDED == TRUE) // Number of registered GATTC APP extern uint8_t bta_gattc_cl_rcb_active_count(void); - if (bta_gattc_cl_rcb_active_count()) { + uint8_t gattc_app_cnt = bta_gattc_cl_rcb_active_count(); + if (gattc_app_cnt) { + BTC_TRACE_WARNING("%s GATTC app active, cnt %d", __func__, gattc_app_cnt); status |= BIT(BTC_BLE_STATUS_GATTC_APP); } // Number of saved GATTC cache extern UINT8 bta_gattc_co_get_addr_num(void); - if (bta_gattc_co_get_addr_num()) { + uint8_t gattc_cache_cnt = bta_gattc_co_get_addr_num(); + if (gattc_cache_cnt) { + BTC_TRACE_WARNING("%s GATTC cache count %d", __func__, gattc_cache_cnt); status |= BIT(BTC_BLE_STATUS_GATTC_CACHE); } - #endif +#endif // GATTC_INCLUDED - #if (GATTS_INCLUDED == TRUE) +#if (GATTS_INCLUDED == TRUE) // Number of registered GATTS service extern uint8_t bta_gatts_srvc_active_count(void); - if (bta_gatts_srvc_active_count()) { + uint8_t gatts_srvc_cnt = bta_gatts_srvc_active_count(); + if (gatts_srvc_cnt) { + BTC_TRACE_WARNING("%s GATTS service active, cnt %d", __func__, gatts_srvc_cnt); status |= BIT(BTC_BLE_STATUS_GATTS_SRVC); } - #endif +#endif // GATTS_INCLUDED - #if SMP_INCLUDED == TRUE +#if (SMP_INCLUDED == TRUE) extern uint8_t smp_get_state(void); - if (smp_get_state()) { + uint8_t smp_state = smp_get_state(); + if (smp_state) { + BTC_TRACE_WARNING("%s SMP state active, state=%d", __func__, smp_state); status |= BIT(BTC_BLE_STATUS_SMP_STATE); } - #endif +#endif // SMP_INCLUDED + + BTC_TRACE_WARNING("%s exit, final status=0x%x", __func__, status); return status; } diff --git a/components/bt/host/bluedroid/btc/core/btc_profile_queue.c b/components/bt/host/bluedroid/btc/core/btc_profile_queue.c index 4f359030434d..5e63dfe54c4e 100644 --- a/components/bt/host/bluedroid/btc/core/btc_profile_queue.c +++ b/components/bt/host/bluedroid/btc/core/btc_profile_queue.c @@ -62,6 +62,9 @@ static void queue_int_advance(void) void btc_profile_queue_handler(btc_msg_t *msg) { btc_prf_que_args_t *arg = (btc_prf_que_args_t *)(msg->arg); + + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); + switch (msg->act) { case BTC_PRF_QUE_CONNECT: queue_int_add(&(arg->connect_node)); diff --git a/components/bt/host/bluedroid/btc/core/btc_storage.c b/components/bt/host/bluedroid/btc/core/btc_storage.c index 1923dea0da63..bee44e18d383 100644 --- a/components/bt/host/bluedroid/btc/core/btc_storage.c +++ b/components/bt/host/bluedroid/btc/core/btc_storage.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -40,7 +40,7 @@ bt_status_t btc_storage_add_bonded_device(bt_bdaddr_t *remote_bd_addr, bdaddr_to_string(remote_bd_addr, bdstr, sizeof(bdstr)); /* device not in bond list and exceed the maximum number of bonded devices, delete the inactive bonded device */ - if (btc_storage_get_num_all_bond_devices() >= BTM_SEC_MAX_DEVICE_RECORDS && !btc_config_has_section(bdstr)) { + if (btc_storage_get_num_all_bond_devices() >= BTM_SEC_MAX_BONDS && !btc_config_has_section(bdstr)) { const btc_config_section_iter_t *iter = btc_config_section_begin(); const btc_config_section_iter_t *remove_iter = iter; /* find the first device(the last node) */ @@ -57,7 +57,7 @@ bt_status_t btc_storage_add_bonded_device(bt_bdaddr_t *remote_bd_addr, // delete config info if (btc_config_remove_section(remove_section)) { - BTC_TRACE_WARNING("exceeded the maximum nubmer of bonded devices, delete the first device info : %02x:%02x:%02x:%02x:%02x:%02x", + BTC_TRACE_WARNING("exceeded the maximum number of bonded devices, delete the first device info : %02x:%02x:%02x:%02x:%02x:%02x", bd_addr.address[0], bd_addr.address[1], bd_addr.address[2], bd_addr.address[3], bd_addr.address[4], bd_addr.address[5]); } } @@ -141,8 +141,8 @@ static bt_status_t btc_in_fetch_bonded_devices(int add) continue; } dev_cnt ++; - /* if the number of device stored in nvs not exceed to BTM_SEC_MAX_DEVICE_RECORDS, load it */ - if (dev_cnt <= BTM_SEC_MAX_DEVICE_RECORDS) { + /* if the number of device stored in nvs not exceed to BTM_SEC_MAX_BONDS, load it */ + if (dev_cnt <= BTM_SEC_MAX_BONDS) { if (btc_config_exist(name, BTC_STORAGE_LINK_KEY_TYPE_STR) && btc_config_exist(name, BTC_STORAGE_PIN_LENGTH_STR) && btc_config_exist(name, BTC_STORAGE_SC_SUPPORT) && btc_config_exist(name, BTC_STORAGE_LINK_KEY_STR)) { /* load bt device */ diff --git a/components/bt/host/bluedroid/btc/profile/std/a2dp/btc_av.c b/components/bt/host/bluedroid/btc/profile/std/a2dp/btc_av.c index b09890332ef0..b3e76ae878f6 100644 --- a/components/bt/host/bluedroid/btc/profile/std/a2dp/btc_av.c +++ b/components/bt/host/bluedroid/btc/profile/std/a2dp/btc_av.c @@ -139,6 +139,7 @@ static BOOLEAN btc_av_state_opened_handler(btc_sm_event_t event, void *data); static BOOLEAN btc_av_state_started_handler(btc_sm_event_t event, void *data); static BOOLEAN btc_av_state_closing_handler(btc_sm_event_t event, void *data); static void clean_up(int service_id); +static BOOLEAN btc_a2d_deinit_if_ongoing(void); #if BTC_AV_SRC_INCLUDED static bt_status_t btc_a2d_src_init(void); @@ -312,11 +313,13 @@ static BOOLEAN btc_av_state_idle_handler(btc_sm_event_t event, void *p_data) switch (event) { case BTC_SM_ENTER_EVT: - /* clear the peer_bda */ - memset(&btc_av_cb.peer_bda, 0, sizeof(bt_bdaddr_t)); - btc_av_cb.flags = 0; - btc_av_cb.edr = 0; - btc_a2dp_on_idle(); + if (btc_a2d_deinit_if_ongoing() == FALSE) { + /* clear the peer_bda */ + memset(&btc_av_cb.peer_bda, 0, sizeof(bt_bdaddr_t)); + btc_av_cb.flags = 0; + btc_av_cb.edr = 0; + btc_a2dp_on_idle(); + } break; case BTC_SM_EXIT_EVT: @@ -484,22 +487,18 @@ static BOOLEAN btc_av_state_opening_handler(btc_sm_event_t event, void *p_data) /* change state to open/idle based on the status */ btc_sm_change_state(btc_av_cb.sm_handle, av_state); - if (btc_av_cb.peer_sep == AVDT_TSEP_SNK) { - /* if queued PLAY command, send it now */ - /* necessary to add this? - btc_rc_check_handle_pending_play(p_bta_data->open.bd_addr, - (p_bta_data->open.status == BTA_AV_SUCCESS)); - */ - } else if (btc_av_cb.peer_sep == AVDT_TSEP_SRC && - (p_bta_data->open.status == BTA_AV_SUCCESS)) { - /* Bring up AVRCP connection too if AVRC Initialized */ - if(g_av_with_rc) { - BTA_AvOpenRc(btc_av_cb.bta_handle); - } else { - BTC_TRACE_WARNING("AVRC not Init, not using it."); + if (p_bta_data->open.status == BTA_AV_SUCCESS && !btc_a2d_deinit_if_ongoing()) { + if (btc_av_cb.peer_sep == AVDT_TSEP_SRC) { + /* Bring up AVRCP connection too if AVRC Initialized */ + if(g_av_with_rc) { + BTA_AvOpenRc(btc_av_cb.bta_handle); + } else { + BTC_TRACE_WARNING("AVRC not Init, not using it."); + } } } btc_queue_advance(); + } break; case BTC_AV_SINK_CONFIG_REQ_EVT: { @@ -777,12 +776,6 @@ static BOOLEAN btc_av_state_opened_handler(btc_sm_event_t event, void *p_data) /* change state to idle, send acknowledgement if start is pending */ btc_sm_change_state(btc_av_cb.sm_handle, BTC_AV_STATE_IDLE); - - if (g_a2dp_source_ongoing_deinit) { - clean_up(BTA_A2DP_SOURCE_SERVICE_ID); - } else if (g_a2dp_sink_ongoing_deinit) { - clean_up(BTA_A2DP_SINK_SERVICE_ID); - } break; } @@ -986,11 +979,6 @@ static BOOLEAN btc_av_state_started_handler(btc_sm_event_t event, void *p_data) close->disc_rsn); btc_sm_change_state(btc_av_cb.sm_handle, BTC_AV_STATE_IDLE); - if (g_a2dp_source_ongoing_deinit) { - clean_up(BTA_A2DP_SOURCE_SERVICE_ID); - } else if (g_a2dp_sink_ongoing_deinit) { - clean_up(BTA_A2DP_SINK_SERVICE_ID); - } break; CHECK_RC_EVENT(event, p_data); @@ -1711,13 +1699,17 @@ static void btc_a2d_sink_get_delay_value(void) static void btc_a2d_sink_deinit(void) { + // Cleanup will only occur when the state is IDLE. + // If connected, it will first disconnect and then wait for the state to change to IDLE before performing cleanup. + // If in any other state, it will wait for the process to complete and then call btc_a2d_sink_deinit again. g_a2dp_sink_ongoing_deinit = true; if (btc_av_is_connected()) { BTA_AvClose(btc_av_cb.bta_handle); if (btc_av_cb.peer_sep == AVDT_TSEP_SRC && g_av_with_rc == true) { BTA_AvCloseRc(btc_av_cb.bta_handle); } - } else { + } else if (btc_sm_get_state(btc_av_cb.sm_handle) == BTC_AV_STATE_IDLE) { + /* Only clean up when idle */ clean_up(BTA_A2DP_SINK_SERVICE_ID); } } @@ -1744,13 +1736,16 @@ static bt_status_t btc_a2d_src_init(void) static void btc_a2d_src_deinit(void) { + // Cleanup will only occur when the state is IDLE. + // If connected, it will first disconnect and then wait for the state to change to IDLE before performing cleanup. + // If in any other state, it will wait for the process to complete and then call btc_a2d_src_deinit again. g_a2dp_source_ongoing_deinit = true; if (btc_av_is_connected()) { BTA_AvClose(btc_av_cb.bta_handle); if (btc_av_cb.peer_sep == AVDT_TSEP_SNK && g_av_with_rc == true) { BTA_AvCloseRc(btc_av_cb.bta_handle); } - } else { + } else if (btc_sm_get_state(btc_av_cb.sm_handle) == BTC_AV_STATE_IDLE) { clean_up(BTA_A2DP_SOURCE_SERVICE_ID); } } @@ -1765,4 +1760,21 @@ static bt_status_t btc_a2d_src_connect(bt_bdaddr_t *remote_bda) #endif /* BTC_AV_SRC_INCLUDED */ +static BOOLEAN btc_a2d_deinit_if_ongoing(void) +{ +#if BTC_AV_SRC_INCLUDED + if (g_a2dp_source_ongoing_deinit) { + btc_a2d_src_deinit(); + return TRUE; + } +#endif +#if BTC_AV_SINK_INCLUDED + if (g_a2dp_sink_ongoing_deinit) { + btc_a2d_sink_deinit(); + return TRUE; + } +#endif + return FALSE; +} + #endif /* #if BTC_AV_INCLUDED */ diff --git a/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c b/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c index b74ffa00f1a7..001bb74b2278 100644 --- a/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c +++ b/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c @@ -61,6 +61,7 @@ static inline void btc_gap_ble_cb_to_app(esp_gap_ble_cb_event_t event, esp_ble_g esp_gap_ble_cb_t btc_gap_ble_cb = (esp_gap_ble_cb_t)btc_profile_cb_get(BTC_PID_GAP_BLE); if (btc_gap_ble_cb) { btc_gap_ble_cb(event, param); + BTC_TRACE_DEBUG("btc_gap_ble_cb_to_app, event=%d", event); } } @@ -1768,6 +1769,8 @@ void btc_gap_ble_cb_handler(btc_msg_t *msg) { esp_ble_gap_cb_param_t *param = (esp_ble_gap_cb_param_t *)msg->arg; + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); + if (msg->act < ESP_GAP_BLE_EVT_MAX) { btc_gap_ble_cb_to_app(msg->act, param); } else { @@ -2177,7 +2180,7 @@ void btc_gap_ble_call_handler(btc_msg_t *msg) btc_ble_5_gap_args_t *arg_5 = (btc_ble_5_gap_args_t *)msg->arg; #endif // #if (BLE_50_FEATURE_SUPPORT == TRUE) - BTC_TRACE_DEBUG("%s act %d\n", __FUNCTION__, msg->act); + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); switch (msg->act) { #if (BLE_42_FEATURE_SUPPORT == TRUE) diff --git a/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_bt.c b/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_bt.c index e1278954c4ee..4d5e7a497aef 100644 --- a/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_bt.c +++ b/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_bt.c @@ -1063,7 +1063,9 @@ void btc_gap_bt_arg_deep_free(btc_msg_t *msg) void btc_gap_bt_call_handler(btc_msg_t *msg) { btc_gap_bt_args_t *arg = (btc_gap_bt_args_t *)msg->arg; - BTC_TRACE_DEBUG("%s act %d\n", __func__, msg->act); + + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); + switch (msg->act) { case BTC_GAP_BT_ACT_SET_SCAN_MODE: { btc_bt_set_scan_mode(arg->set_scan_mode.c_mode, arg->set_scan_mode.d_mode); diff --git a/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatt_common.c b/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatt_common.c index 45a2b834b52f..754878f0cb5a 100644 --- a/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatt_common.c +++ b/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatt_common.c @@ -23,7 +23,8 @@ static void btc_set_local_mtu(uint16_t mtu) void btc_gatt_com_call_handler(btc_msg_t *msg) { - BTC_TRACE_DEBUG("%s act %d\n", __func__, msg->act); + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); + switch (msg->act) { case BTC_GATT_ACT_SET_LOCAL_MTU: { diff --git a/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gattc.c b/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gattc.c index 86221e3c895e..e8f7444368ea 100644 --- a/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gattc.c +++ b/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gattc.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 @@ -24,6 +24,7 @@ static inline void btc_gattc_cb_to_app(esp_gattc_cb_event_t event, esp_gatt_if_t esp_gattc_cb_t btc_gattc_cb = (esp_gattc_cb_t )btc_profile_cb_get(BTC_PID_GATTC); if (btc_gattc_cb) { btc_gattc_cb(event, gattc_if, param); + BTC_TRACE_DEBUG("btc_gattc_cb_to_app, gattc_if %d, event=%d", gattc_if, event); } } @@ -714,6 +715,9 @@ static void btc_gattc_unreg_for_notify(btc_ble_gattc_args_t *arg) void btc_gattc_call_handler(btc_msg_t *msg) { btc_ble_gattc_args_t *arg = (btc_ble_gattc_args_t *)(msg->arg); + + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); + switch (msg->act) { case BTC_GATTC_ACT_APP_REGISTER: btc_gattc_app_register(arg); @@ -803,6 +807,8 @@ void btc_gattc_cb_handler(btc_msg_t *msg) memset(¶m, 0, sizeof(esp_ble_gattc_cb_param_t)); + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); + switch (msg->act) { case BTA_GATTC_REG_EVT: { tBTA_GATTC_REG *reg_oper = &arg->reg_oper; diff --git a/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatts.c b/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatts.c index 7eab806e2f54..e1b06cffbae7 100644 --- a/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatts.c +++ b/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatts.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -37,6 +37,7 @@ static inline void btc_gatts_cb_to_app(esp_gatts_cb_event_t event, esp_gatt_if_t { esp_gatts_cb_t btc_gatts_cb = (esp_gatts_cb_t)btc_profile_cb_get(BTC_PID_GATTS); if (btc_gatts_cb) { + BTC_TRACE_DEBUG("btc_gatts_cb_to_app, gatts_if %d, event=%d", gatts_if, event); btc_gatts_cb(event, gatts_if, param); } } @@ -616,6 +617,8 @@ void btc_gatts_call_handler(btc_msg_t *msg) { btc_ble_gatts_args_t *arg = (btc_ble_gatts_args_t *)msg->arg; + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); + switch (msg->act) { case BTC_GATTS_ACT_APP_REGISTER: { tBT_UUID uuid; @@ -764,6 +767,8 @@ void btc_gatts_cb_handler(btc_msg_t *msg) tBTA_GATTS *p_data = (tBTA_GATTS *)msg->arg; esp_gatt_if_t gatts_if; + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); + switch (msg->act) { case BTA_GATTS_REG_EVT: { gatts_if = p_data->reg_oper.server_if; diff --git a/components/bt/host/bluedroid/btc/profile/std/hf_ag/btc_hf_ag.c b/components/bt/host/bluedroid/btc/profile/std/hf_ag/btc_hf_ag.c index c7fa57f0b06b..66162261fd01 100644 --- a/components/bt/host/bluedroid/btc/profile/std/hf_ag/btc_hf_ag.c +++ b/components/bt/host/bluedroid/btc/profile/std/hf_ag/btc_hf_ag.c @@ -1097,6 +1097,8 @@ void btc_hf_call_handler(btc_msg_t *msg) { btc_hf_args_t *arg = (btc_hf_args_t *)(msg->arg); + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); + switch (msg->act) { case BTC_HF_INIT_EVT: { diff --git a/components/bt/host/bluedroid/btc/profile/std/hid/btc_hd.c b/components/bt/host/bluedroid/btc/profile/std/hid/btc_hd.c index 82ff2b8d5c8e..5986943bfa4a 100644 --- a/components/bt/host/bluedroid/btc/profile/std/hid/btc_hd.c +++ b/components/bt/host/bluedroid/btc/profile/std/hid/btc_hd.c @@ -75,6 +75,8 @@ btc_hd_cb_t btc_hd_cb = {0}; typedef void (bt_hid_copy_cb_t)(btc_msg_t *msg, void *p_dest, void *p_src); +static void btc_hd_cb_arg_deep_free(btc_msg_t *msg); + static inline void btc_hd_cb_to_app(esp_hidd_cb_event_t event, esp_hidd_cb_param_t *param) { esp_hd_cb_t btc_hd_cb = (esp_hd_cb_t)btc_profile_cb_get(BTC_PID_HD); @@ -705,7 +707,7 @@ static void btc_hd_virtual_cable_unplug(void) } } -static void btc_hd_call_arg_deep_free(btc_msg_t *msg) +void btc_hd_call_arg_deep_free(btc_msg_t *msg) { btc_hidd_args_t *arg = (btc_hidd_args_t *)msg->arg; @@ -721,6 +723,9 @@ static void btc_hd_call_arg_deep_free(btc_msg_t *msg) void btc_hd_call_handler(btc_msg_t *msg) { btc_hidd_args_t *arg = (btc_hidd_args_t *)(msg->arg); + + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); + switch (msg->act) { case BTC_HD_INIT_EVT: btc_hd_init(); @@ -756,7 +761,7 @@ void btc_hd_call_handler(btc_msg_t *msg) btc_hd_call_arg_deep_free(msg); } -void btc_hd_cb_arg_deep_free(btc_msg_t *msg) +static void btc_hd_cb_arg_deep_free(btc_msg_t *msg) { tBTA_HD *arg = (tBTA_HD *)msg->arg; @@ -779,6 +784,8 @@ void btc_hd_cb_handler(btc_msg_t *msg) esp_hidd_cb_param_t param = {0}; BTC_TRACE_API("%s: event=%s", __func__, dump_hd_event(event)); + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); + switch (event) { case BTA_HD_ENABLE_EVT: BTC_TRACE_DEBUG("%s: status=%d", __func__, p_data->status); diff --git a/components/bt/host/bluedroid/btc/profile/std/hid/btc_hh.c b/components/bt/host/bluedroid/btc/profile/std/hid/btc_hh.c index 55fe3f69b379..dda5d0bf9d1d 100644 --- a/components/bt/host/bluedroid/btc/profile/std/hid/btc_hh.c +++ b/components/bt/host/bluedroid/btc/profile/std/hid/btc_hh.c @@ -64,6 +64,8 @@ static bdstr_t bdstr; #define is_hidh_init() (btc_hh_cb.status > BTC_HH_DISABLED) #define BTC_TIMEOUT_VUP_MS (3 * 1000) +static void btc_hh_cb_arg_deep_free(btc_msg_t *msg); + static inline void btc_hh_cb_to_app(esp_hidh_cb_event_t event, esp_hidh_cb_param_t *param) { esp_hh_cb_t btc_hh_cb = (esp_hh_cb_t)btc_profile_cb_get(BTC_PID_HH); @@ -1097,7 +1099,7 @@ static void btc_hh_set_idle_time(btc_hidh_args_t *arg) } } -static void btc_hh_call_arg_deep_free(btc_msg_t *msg) +void btc_hh_call_arg_deep_free(btc_msg_t *msg) { btc_hidh_args_t *arg = (btc_hidh_args_t *)msg->arg; @@ -1119,6 +1121,8 @@ static void btc_hh_call_arg_deep_free(btc_msg_t *msg) void btc_hh_call_handler(btc_msg_t *msg) { btc_hidh_args_t *arg = (btc_hidh_args_t *)(msg->arg); + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); + switch (msg->act) { case BTC_HH_INIT_EVT: btc_hh_init(); @@ -1166,7 +1170,7 @@ void btc_hh_call_handler(btc_msg_t *msg) btc_hh_call_arg_deep_free(msg); } -void btc_hh_cb_arg_deep_free(btc_msg_t *msg) +static void btc_hh_cb_arg_deep_free(btc_msg_t *msg) { tBTA_HH *arg = (tBTA_HH *)msg->arg; @@ -1227,6 +1231,7 @@ void btc_hh_cb_handler(btc_msg_t *msg) btc_hh_device_t *p_dev = NULL; int len, i; BTC_TRACE_DEBUG("%s: event=%s dereg = %d", __func__, dump_hh_event(msg->act), btc_hh_cb.service_dereg_active); + switch (msg->act) { case BTA_HH_ENABLE_EVT: if (p_data->status == BTA_HH_OK) { diff --git a/components/bt/host/bluedroid/btc/profile/std/include/btc_hd.h b/components/bt/host/bluedroid/btc/profile/std/include/btc_hd.h index 15b59393a327..fa01953e8426 100644 --- a/components/bt/host/bluedroid/btc/profile/std/include/btc_hd.h +++ b/components/bt/host/bluedroid/btc/profile/std/include/btc_hd.h @@ -99,7 +99,7 @@ void btc_hd_call_handler(btc_msg_t *msg); void btc_hd_cb_handler(btc_msg_t *msg); void btc_hd_arg_deep_copy(btc_msg_t *msg, void *p_dest, void *p_src); -void btc_hd_cb_arg_deep_free(btc_msg_t *msg); +void btc_hd_call_arg_deep_free(btc_msg_t *msg); void btc_hd_get_profile_status(esp_hidd_profile_status_t *param); diff --git a/components/bt/host/bluedroid/btc/profile/std/include/btc_hh.h b/components/bt/host/bluedroid/btc/profile/std/include/btc_hh.h index f1158c6fddf7..827cd095c752 100644 --- a/components/bt/host/bluedroid/btc/profile/std/include/btc_hh.h +++ b/components/bt/host/bluedroid/btc/profile/std/include/btc_hh.h @@ -181,8 +181,7 @@ void btc_hh_call_handler(btc_msg_t *msg); void btc_hh_cb_handler(btc_msg_t *msg); void btc_hh_arg_deep_copy(btc_msg_t *msg, void *p_dest, void *p_src); - -void btc_hh_cb_arg_deep_free(btc_msg_t *msg); +void btc_hh_call_arg_deep_free(btc_msg_t *msg); bool btc_hh_add_added_dev(BD_ADDR bd_addr, uint16_t attr_mask); diff --git a/components/bt/host/bluedroid/btc/profile/std/include/btc_spp.h b/components/bt/host/bluedroid/btc/profile/std/include/btc_spp.h index 5082a135e13c..fd349c7de68b 100644 --- a/components/bt/host/bluedroid/btc/profile/std/include/btc_spp.h +++ b/components/bt/host/bluedroid/btc/profile/std/include/btc_spp.h @@ -67,6 +67,7 @@ typedef union { esp_spp_sec_t sec_mask; esp_spp_role_t role; UINT8 local_scn; + bool create_spp_record; UINT8 max_session; char name[ESP_SPP_SERVER_NAME_MAX + 1]; } start_srv; diff --git a/components/bt/host/bluedroid/btc/profile/std/l2cap/btc_l2cap.c b/components/bt/host/bluedroid/btc/profile/std/l2cap/btc_l2cap.c index 9155784fb852..63477d6ce544 100644 --- a/components/bt/host/bluedroid/btc/profile/std/l2cap/btc_l2cap.c +++ b/components/bt/host/bluedroid/btc/profile/std/l2cap/btc_l2cap.c @@ -300,6 +300,7 @@ static inline void btc_l2cap_cb_to_app(esp_bt_l2cap_cb_event_t event, esp_bt_l2c { esp_bt_l2cap_cb_t btc_l2cap_cb = (esp_bt_l2cap_cb_t)btc_profile_cb_get(BTC_PID_L2CAP); if (btc_l2cap_cb) { + BTC_TRACE_DEBUG("btc_l2cap_cb_to_app, event=%d", event); btc_l2cap_cb(event, param); } } @@ -772,6 +773,7 @@ static void btc_l2cap_disconnect(uint32_t handle) void btc_l2cap_call_handler(btc_msg_t *msg) { btc_l2cap_args_t *arg = (btc_l2cap_args_t *)(msg->arg); + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); switch (msg->act) { case BTC_L2CAP_ACT_INIT: btc_l2cap_init(); @@ -809,6 +811,8 @@ void btc_l2cap_cb_handler(btc_msg_t *msg) uint8_t serial = 0; uint32_t count = 0; + BTC_TRACE_DEBUG("%s act %d", __func__, msg->act); + switch (event) { case BTA_JV_ENABLE_EVT: param.init.status = p_data->status; diff --git a/components/bt/host/bluedroid/btc/profile/std/spp/btc_spp.c b/components/bt/host/bluedroid/btc/profile/std/spp/btc_spp.c index bb142531a3e9..8607e4219121 100644 --- a/components/bt/host/bluedroid/btc/profile/std/spp/btc_spp.c +++ b/components/bt/host/bluedroid/btc/profile/std/spp/btc_spp.c @@ -50,6 +50,7 @@ typedef struct { bool connected; bool is_server; bool is_writing; + bool create_spp_record; uint8_t serial; uint8_t scn; uint8_t max_session; @@ -143,6 +144,7 @@ static spp_slot_t *spp_malloc_slot(void) (*slot)->rfc_port_handle = 0; (*slot)->fd = -1; (*slot)->connected = false; + (*slot)->create_spp_record = false; (*slot)->is_server = false; (*slot)->mtu = 0; (*slot)->credit_rx = BTA_JV_MAX_CREDIT_NUM; @@ -378,6 +380,7 @@ static void *btc_spp_rfcomm_inter_cb(tBTA_JV_EVT event, tBTA_JV *p_data, void *u strcpy(slot_new->service_name, slot->service_name); slot_new->sdp_handle = slot->sdp_handle; slot_new->mtu = p_data->rfc_srv_open.peer_mtu; + slot_new->create_spp_record = slot->create_spp_record; slot_new->rfc_handle = p_data->rfc_srv_open.handle; slot_new->rfc_port_handle = BTA_JvRfcommGetPortHdl(slot_new->rfc_handle); BTA_JvSetPmProfile(p_data->rfc_srv_open.handle, BTA_JV_PM_ALL, BTA_JV_CONN_OPEN); @@ -482,7 +485,14 @@ static void btc_spp_dm_inter_cb(tBTA_JV_EVT event, tBTA_JV *p_data, void *user_d } slot->scn = p_data->scn; - BTA_JvCreateRecordByUser(slot->service_name, slot->scn, (void *)slot->id); + if (slot->create_spp_record) { + BTA_JvCreateRecordByUser(slot->service_name, slot->scn, (void *)slot->id); + } else { + slot->sdp_handle = 0xffff; + BTA_JvRfcommStartServer(slot->security, slot->role, slot->scn, + slot->max_session, (tBTA_JV_RFCOMM_CBACK *)btc_spp_rfcomm_inter_cb, (void *)slot->id); + } + osi_mutex_unlock(&spp_local_param.spp_slot_mutex); break; case BTA_JV_CREATE_RECORD_EVT: @@ -748,6 +758,7 @@ static void btc_spp_start_srv(btc_spp_args_t *arg) * make this slot become a listening slot */ slot->is_server = true; + slot->create_spp_record = arg->start_srv.create_spp_record; slot->security = arg->start_srv.sec_mask; slot->role = arg->start_srv.role; slot->scn = arg->start_srv.local_scn; @@ -832,7 +843,7 @@ static void btc_spp_stop_srv(btc_spp_args_t *arg) if (spp_local_param.spp_slots[i] != NULL && spp_local_param.spp_slots[i]->is_server && spp_local_param.spp_slots[i]->sdp_handle > 0 && spp_local_param.spp_slots[i]->scn == srv_scn_arr[j]) { - if (spp_local_param.spp_slots[i]->sdp_handle > 0) { + if (spp_local_param.spp_slots[i]->sdp_handle > 0 && spp_local_param.spp_slots[i]->create_spp_record) { BTA_JvDeleteRecord(spp_local_param.spp_slots[i]->sdp_handle); } diff --git a/components/bt/host/bluedroid/common/include/common/bt_target.h b/components/bt/host/bluedroid/common/include/common/bt_target.h index 37375dd81da0..d734717cbd93 100644 --- a/components/bt/host/bluedroid/common/include/common/bt_target.h +++ b/components/bt/host/bluedroid/common/include/common/bt_target.h @@ -1093,11 +1093,11 @@ /* The number of security records for peer devices. 15 AS Default*/ #ifndef BTM_SEC_MAX_DEVICE_RECORDS -#if (UC_BT_SMP_MAX_BONDS < UC_BT_ACL_CONNECTIONS) -#define BTM_SEC_MAX_DEVICE_RECORDS UC_BT_ACL_CONNECTIONS -#else -#define BTM_SEC_MAX_DEVICE_RECORDS UC_BT_SMP_MAX_BONDS +#define BTM_SEC_MAX_DEVICE_RECORDS (UC_BT_SMP_MAX_BONDS + UC_BT_ACL_CONNECTIONS) #endif + +#ifndef BTM_SEC_MAX_BONDS +#define BTM_SEC_MAX_BONDS UC_BT_SMP_MAX_BONDS #endif #if BTA_SDP_INCLUDED diff --git a/components/bt/host/bluedroid/common/include/common/bt_trace.h b/components/bt/host/bluedroid/common/include/common/bt_trace.h index a2bb9dd4487f..69565cc68524 100644 --- a/components/bt/host/bluedroid/common/include/common/bt_trace.h +++ b/components/bt/host/bluedroid/common/include/common/bt_trace.h @@ -57,6 +57,14 @@ static inline void trc_dump_buffer(const char *prefix, uint8_t *data, uint16_t l #define BTTRC_DUMP_BUFFER(_prefix, _data, _len) #endif +#ifndef MAC2STR +#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] +#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" +#endif + +/* Support up to 64 bytes of buffer */ +const char *bt_hex2str(const void *buf, size_t len); + //static const char BTE_LOGMSG_MODULE[] = "bte_logmsg_module"; /* BTrgs);E tracing IDs for debug purposes */ diff --git a/components/bt/host/bluedroid/hci/hci_layer.c b/components/bt/host/bluedroid/hci/hci_layer.c index e5cd263fbc19..12d36296a1f7 100644 --- a/components/bt/host/bluedroid/hci/hci_layer.c +++ b/components/bt/host/bluedroid/hci/hci_layer.c @@ -51,6 +51,10 @@ #define HCI_DOWNSTREAM_DATA_QUEUE_IDX (0) +#ifndef MIN +#define MIN(a,b) (((a)<(b))?(a):(b)) +#endif + typedef struct { bool timer_is_set; osi_alarm_t *command_response_timer; @@ -614,3 +618,120 @@ const hci_t *hci_layer_get_interface(void) init_layer_interface(); return &interface; } + +#if !UC_BT_STACK_NO_LOG +/******************************************************************************* +** +** Function hci_status_code_to_string +** +** Description Converts an HCI status code to a human-readable string. +** If the code is not defined in the specification, the +** function returns "Unknown Status (0xXX)" where XX is the +** actual code value. +** Reference: BLUETOOTH CORE SPECIFICATION Version 5.4, +** Vol 1, Part F, p. 376 +** +** Parameters status : HCI status code +** +** Returns const char* : readable description of the status +** +*******************************************************************************/ +const char *hci_status_code_to_string(uint8_t status) +{ + switch (status) { + case HCI_SUCCESS: return "Success"; /* 0x00 */ + case HCI_ERR_ILLEGAL_COMMAND: return "Illegal Command"; /* 0x01 */ + case HCI_ERR_NO_CONNECTION: return "No Connection"; /* 0x02 */ + case HCI_ERR_HW_FAILURE: return "HW Failure"; /* 0x03 */ + case HCI_ERR_PAGE_TIMEOUT: return "Page Timeout"; /* 0x04 */ + case HCI_ERR_AUTH_FAILURE: return "Auth Failure"; /* 0x05 */ + case HCI_ERR_KEY_MISSING: return "Key Missing"; /* 0x06 */ + case HCI_ERR_MEMORY_FULL: return "Memory Full"; /* 0x07 */ + case HCI_ERR_CONNECTION_TOUT: return "Conn Timeout"; /* 0x08 */ + case HCI_ERR_MAX_NUM_OF_CONNECTIONS: return "Conn Limit Exceeded"; /* 0x09 */ + case HCI_ERR_MAX_NUM_OF_SCOS: return "Sync Conn Limit Exceeded"; /* 0x0A */ + case HCI_ERR_CONNECTION_EXISTS: return "Conn Exists"; /* 0x0B */ + case HCI_ERR_COMMAND_DISALLOWED: return "Cmd Disallowed"; /* 0x0C */ + case HCI_ERR_HOST_REJECT_RESOURCES: return "Rejected: Resources"; /* 0x0D */ + case HCI_ERR_HOST_REJECT_SECURITY: return "Rejected: Security"; /* 0x0E */ + case HCI_ERR_HOST_REJECT_DEVICE: return "Rejected: BD_ADDR"; /* 0x0F */ + case HCI_ERR_HOST_TIMEOUT: return "Accept Timeout"; /* 0x10 */ + case HCI_ERR_UNSUPPORTED_VALUE: return "Unsupported Value"; /* 0x11 */ + case HCI_ERR_ILLEGAL_PARAMETER_FMT: return "Invalid Param"; /* 0x12 */ + case HCI_ERR_PEER_USER: return "Terminated by Peer"; /* 0x13 */ + case HCI_ERR_PEER_LOW_RESOURCES: return "Peer Low Resources"; /* 0x14 */ + case HCI_ERR_PEER_POWER_OFF: return "Peer Power Off"; /* 0x15 */ + case HCI_ERR_CONN_CAUSE_LOCAL_HOST: return "Terminated by Host"; /* 0x16 */ + case HCI_ERR_REPEATED_ATTEMPTS: return "Repeated Attempts"; /* 0x17 */ + case HCI_ERR_PAIRING_NOT_ALLOWED: return "Pairing Not Allowed"; /* 0x18 */ + case HCI_ERR_UNKNOWN_LMP_PDU: return "Unknown LMP PDU"; /* 0x19 */ + case HCI_ERR_UNSUPPORTED_REM_FEATURE: return "Unsupported Remote Feature"; /* 0x1A */ + case HCI_ERR_SCO_OFFSET_REJECTED: return "SCO Offset Rejected"; /* 0x1B */ + case HCI_ERR_SCO_INTERVAL_REJECTED: return "SCO Interval Rejected"; /* 0x1C */ + case HCI_ERR_SCO_AIR_MODE: return "SCO Air Mode Rejected"; /* 0x1D */ + case HCI_ERR_INVALID_LMP_PARAM: return "Invalid LMP/LL Param"; /* 0x1E */ + case HCI_ERR_UNSPECIFIED: return "Unspecified Error"; /* 0x1F */ + case HCI_ERR_UNSUPPORTED_LMP_PARAMETERS: return "Unsupported LMP/LL"; /* 0x20 */ + case HCI_ERR_ROLE_CHANGE_NOT_ALLOWED: return "Role Change Not Allowed"; /* 0x21 */ + case HCI_ERR_LMP_RESPONSE_TIMEOUT: return "LMP/LL Response Timeout"; /* 0x22 */ + case HCI_ERR_LMP_ERR_TRANS_COLLISION: return "Transaction Collision"; /* 0x23 */ + case HCI_ERR_LMP_PDU_NOT_ALLOWED: return "LMP PDU Not Allowed"; /* 0x24 */ + case HCI_ERR_ENCRY_MODE_NOT_ACCEPTABLE: return "Encryption Not Acceptable"; /* 0x25 */ + case HCI_ERR_UNIT_KEY_USED: return "Link Key Used"; /* 0x26 */ + case HCI_ERR_QOS_NOT_SUPPORTED: return "QoS Not Supported"; /* 0x27 */ + case HCI_ERR_INSTANT_PASSED: return "Instant Passed"; /* 0x28 */ + case HCI_ERR_PAIRING_WITH_UNIT_KEY_NOT_SUPPORTED: return "Pairing w/ Unit Key Not Supported"; /* 0x29 */ + case HCI_ERR_DIFF_TRANSACTION_COLLISION: return "Transaction Collision"; /* 0x2A */ + case HCI_ERR_UNDEFINED_0x2B: return "Reserved"; /* 0x2B */ + case HCI_ERR_QOS_UNACCEPTABLE_PARAM: return "QoS Unacceptable"; /* 0x2C */ + case HCI_ERR_QOS_REJECTED: return "QoS Rejected"; /* 0x2D */ + case HCI_ERR_CHAN_CLASSIF_NOT_SUPPORTED: return "Chan Classif Not Supported"; /* 0x2E */ + case HCI_ERR_INSUFFCIENT_SECURITY: return "Insufficient Security"; /* 0x2F */ + case HCI_ERR_PARAM_OUT_OF_RANGE: return "Param Out of Range"; /* 0x30 */ + case HCI_ERR_UNDEFINED_0x31: return "Reserved"; /* 0x31 */ + case HCI_ERR_ROLE_SWITCH_PENDING: return "Role Switch Pending"; /* 0x32 */ + case HCI_ERR_UNDEFINED_0x33: return "Reserved"; /* 0x33 */ + case HCI_ERR_RESERVED_SLOT_VIOLATION: return "Slot Violation"; /* 0x34 */ + case HCI_ERR_ROLE_SWITCH_FAILED: return "Role Switch Failed"; /* 0x35 */ + case HCI_ERR_INQ_RSP_DATA_TOO_LARGE: return "Inquiry Response Too Large"; /* 0x36 */ + case HCI_ERR_SIMPLE_PAIRING_NOT_SUPPORTED: return "Simple Pairing Not Supported"; /* 0x37 */ + case HCI_ERR_HOST_BUSY_PAIRING: return "Host Busy"; /* 0x38 */ + case HCI_ERR_REJ_NO_SUITABLE_CHANNEL: return "No Suitable Channel"; /* 0x39 */ + case HCI_ERR_CONTROLLER_BUSY: return "Controller Busy"; /* 0x3A */ + case HCI_ERR_UNACCEPT_CONN_INTERVAL: return "Unacceptable Conn Interval"; /* 0x3B */ + case HCI_ERR_DIRECTED_ADVERTISING_TIMEOUT: return "Adv Timeout"; /* 0x3C */ + case HCI_ERR_CONN_TOUT_DUE_TO_MIC_FAILURE: return "MIC Failure"; /* 0x3D */ + case HCI_ERR_CONN_FAILED_ESTABLISHMENT: return "Conn Failed"; /* 0x3E */ + case HCI_ERR_MAC_CONNECTION_FAILED: return "Previously Used"; /* 0x3F */ + default: { + static char buf[24]; + snprintf(buf, sizeof(buf), "Unknown Status (0x%02X)", status); + return buf; + } + } +} +#endif + +const char *bt_hex2str(const void *buf, size_t len) +{ + static const char hex[] = "0123456789abcdef"; + static char str[129]; + const uint8_t *b = buf; + size_t i; + + len = MIN(len, (sizeof(str) - 1) / 2); + + for (i = 0; i < len; i++) { + str[i * 2] = hex[b[i] >> 4]; + str[i * 2 + 1] = hex[b[i] & 0xf]; + } + + str[i * 2] = '\0'; + + return str; +} + +int get_hci_work_queue_size(int wq_idx) +{ + return osi_thread_queue_wait_size(hci_host_thread, wq_idx); +} diff --git a/components/bt/host/bluedroid/hci/include/hci/hci_layer.h b/components/bt/host/bluedroid/hci/include/hci/hci_layer.h index c48d05655e6a..356f2c044b57 100644 --- a/components/bt/host/bluedroid/hci/include/hci/hci_layer.h +++ b/components/bt/host/bluedroid/hci/include/hci/hci_layer.h @@ -112,3 +112,5 @@ int hci_adv_credits_force_release(uint16_t num); #endif #endif // #if (BLE_42_SCAN_EN == TRUE) #endif /* _HCI_LAYER_H_ */ + +const char *hci_status_code_to_string(uint8_t status); diff --git a/components/bt/host/bluedroid/hci/packet_fragmenter.c b/components/bt/host/bluedroid/hci/packet_fragmenter.c index d8f2ff918fa3..bfb9843eb396 100644 --- a/components/bt/host/bluedroid/hci/packet_fragmenter.c +++ b/components/bt/host/bluedroid/hci/packet_fragmenter.c @@ -26,7 +26,7 @@ #include "osi/hash_map.h" #include "osi/hash_functions.h" #include "common/bt_trace.h" - +#include "esp_log.h" #define APPLY_CONTINUATION_FLAG(handle) (((handle) & 0xCFFF) | 0x1000) #define APPLY_START_FLAG(handle) (((handle) & 0xCFFF) | 0x2000) @@ -173,7 +173,7 @@ static void reassemble_and_dispatch(BT_HDR *packet) partial_packet = (BT_HDR *)osi_calloc(full_length + sizeof(BT_HDR)); if (partial_packet == NULL) { - HCI_TRACE_WARNING("%s full_length %d no memory.\n", __func__, full_length); + HCI_TRACE_WARNING("%s full_length %d no memory.", __func__, full_length); assert(0); } diff --git a/components/bt/host/bluedroid/stack/btm/btm_acl.c b/components/bt/host/bluedroid/stack/btm/btm_acl.c index fdce6261ff2b..c97e09f97dba 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_acl.c +++ b/components/bt/host/bluedroid/stack/btm/btm_acl.c @@ -786,7 +786,7 @@ void btm_acl_encrypt_change (UINT16 handle, UINT8 status, UINT8 encr_enable) tBTM_SEC_DEV_REC *p_dev_rec; tBTM_BL_ROLE_CHG_DATA evt; - BTM_TRACE_DEBUG ("btm_acl_encrypt_change handle=%d status=%d encr_enabl=%d\n", + BTM_TRACE_DEBUG ("btm_acl_encrypt_change handle=%d status=%d encr_enable=%d\n", handle, status, encr_enable); p = btm_handle_to_acl(handle); if (p == NULL) { diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble.c b/components/bt/host/bluedroid/stack/btm/btm_ble.c index 8f676a655a6d..46a5ba5190ac 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_ble.c +++ b/components/bt/host/bluedroid/stack/btm/btm_ble.c @@ -77,18 +77,16 @@ BOOLEAN BTM_SecAddBleDevice (BD_ADDR bd_addr, BD_NAME bd_name, tBT_DEVICE_TYPE d tBTM_SEC_DEV_REC *p_dev_rec; tBTM_INQ_INFO *p_info = NULL; - BTM_TRACE_DEBUG ("BTM_SecAddBleDevice dev_type=0x%x", dev_type); + BTM_TRACE_DEBUG ("%s dev_type=0x%x bd_addr="MACSTR"", __func__, dev_type, MAC2STR(bd_addr)); p_dev_rec = btm_find_dev (bd_addr); if (!p_dev_rec) { - BTM_TRACE_DEBUG("Add a new device"); - /* There is no device record, allocate one. * If we can not find an empty spot for this one, let it fail. */ if (list_length(btm_cb.p_sec_dev_rec_list) < BTM_SEC_MAX_DEVICE_RECORDS) { - p_dev_rec = (tBTM_SEC_DEV_REC *)osi_malloc(sizeof(tBTM_SEC_DEV_REC)); - if(p_dev_rec) { - list_append(btm_cb.p_sec_dev_rec_list, p_dev_rec); + p_dev_rec = (tBTM_SEC_DEV_REC *)osi_malloc(sizeof(tBTM_SEC_DEV_REC)); + if (p_dev_rec) { + list_append(btm_cb.p_sec_dev_rec_list, p_dev_rec); BTM_TRACE_DEBUG ("allocate a new dev rec idx=0x%x\n", list_length(btm_cb.p_sec_dev_rec_list)); /* Mark this record as in use and initialize */ @@ -158,22 +156,20 @@ BOOLEAN BTM_SecAddBleDevice (BD_ADDR bd_addr, BD_NAME bd_name, tBT_DEVICE_TYPE d BOOLEAN BTM_SecAddBleKey (BD_ADDR bd_addr, tBTM_LE_KEY_VALUE *p_le_key, tBTM_LE_KEY_TYPE key_type) { tBTM_SEC_DEV_REC *p_dev_rec; - BTM_TRACE_DEBUG ("BTM_SecAddBleKey"); p_dev_rec = btm_find_dev (bd_addr); + if (!p_dev_rec || !p_le_key || (key_type != BTM_LE_KEY_PENC && key_type != BTM_LE_KEY_PID && key_type != BTM_LE_KEY_PCSRK && key_type != BTM_LE_KEY_LENC && key_type != BTM_LE_KEY_LCSRK && key_type != BTM_LE_KEY_LID)) { - BTM_TRACE_WARNING ("BTM_SecAddBleKey() Wrong Type, or No Device record \ - for bdaddr: %08x%04x, Type: %d", - (bd_addr[0] << 24) + (bd_addr[1] << 16) + (bd_addr[2] << 8) + bd_addr[3], - (bd_addr[4] << 8) + bd_addr[5], key_type); + BTM_TRACE_WARNING ("BTM_SecAddBleKey() Wrong Type, or No Device record \ + for bdaddr: "MACSTR", key_type: %02x", + MAC2STR(bd_addr), key_type); return (FALSE); } - BTM_TRACE_DEBUG ("BTM_SecAddLeKey() BDA: %08x%04x, Type: 0x%02x", - (bd_addr[0] << 24) + (bd_addr[1] << 16) + (bd_addr[2] << 8) + bd_addr[3], - (bd_addr[4] << 8) + bd_addr[5], key_type); + BTM_TRACE_DEBUG ("BTM_SecAddLeKey() BDA: "MACSTR", key_type: 0x%02x", + MAC2STR(bd_addr), key_type); btm_sec_save_le_key (bd_addr, key_type, p_le_key, FALSE); @@ -1704,6 +1700,9 @@ tBTM_STATUS btm_ble_start_encrypt(BD_ADDR bda, BOOLEAN use_stk, BT_OCTET16 stk) #if (SMP_INCLUDED == TRUE) void btm_ble_link_encrypted(BD_ADDR bd_addr, UINT8 encr_enable) { +#if BLE_INCLUDED == TRUE + l2cble_notify_le_connection(bd_addr); +#endif // BLE_INCLUDED == TRUE tBTM_SEC_DEV_REC *p_dev_rec = btm_find_dev (bd_addr); BOOLEAN enc_cback; @@ -1756,15 +1755,14 @@ void btm_ble_ltk_request_reply(BD_ADDR bda, BOOLEAN use_stk, BT_OCTET16 stk) tBTM_CB *p_cb = &btm_cb; if (p_rec == NULL) { - BTM_TRACE_ERROR("btm_ble_ltk_request_reply received for unknown device"); + BTM_TRACE_ERROR("%s received for unknown device "MACSTR"", __func__, MAC2STR(bda)); return; } - BTM_TRACE_DEBUG ("btm_ble_ltk_request_reply"); + BTM_TRACE_DEBUG ("%s key_type=%x key_size=%d", __func__, p_rec->ble.key_type, p_rec->ble.keys.key_size); p_cb->enc_handle = p_rec->ble_hci_handle; p_cb->key_size = p_rec->ble.keys.key_size; - BTM_TRACE_DEBUG("key size = %d", p_rec->ble.keys.key_size); if (use_stk) { btsnd_hcic_ble_ltk_req_reply(btm_cb.enc_handle, stk); } else { /* calculate LTK using peer device */ @@ -2044,7 +2042,8 @@ void btm_ble_conn_complete(UINT8 *p, UINT16 evt_len, BOOLEAN enhanced) STREAM_TO_UINT8 (role, p); STREAM_TO_UINT8 (bda_type, p); STREAM_TO_BDADDR (bda, p); - BTM_TRACE_DEBUG("status = %d, handle = %d, role = %d, bda_type = %d",status,handle,role,bda_type); + BTM_TRACE_DEBUG("status=%d handle=%d role=%d bda_type=%d bda="MACSTR"", + status, handle, role, bda_type, MAC2STR(bda)); if (status == 0) { if (enhanced) { STREAM_TO_BDADDR (local_rpa, p); @@ -2956,6 +2955,15 @@ uint8_t btm_ble_sec_dev_record_count(void) for (p_node = list_begin(btm_cb.p_sec_dev_rec_list); p_node; p_node = list_next(p_node)) { p_dev_rec = list_node(p_node); if (p_dev_rec && (p_dev_rec->sec_flags & BTM_SEC_IN_USE) && (p_dev_rec->ble.key_type != BTM_LE_KEY_NONE)) { + BTM_TRACE_DEBUG("%s BLE security device #%d: bd_addr=%02X:%02X:%02X:%02X:%02X:%02X", + __func__, + count, + p_dev_rec->bd_addr[0], + p_dev_rec->bd_addr[1], + p_dev_rec->bd_addr[2], + p_dev_rec->bd_addr[3], + p_dev_rec->bd_addr[4], + p_dev_rec->bd_addr[5]); count++; } } diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble_5_gap.c b/components/bt/host/bluedroid/stack/btm/btm_ble_5_gap.c index 76fe63c08a9e..764ca477bfed 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_ble_5_gap.c +++ b/components/bt/host/bluedroid/stack/btm/btm_ble_5_gap.c @@ -1390,6 +1390,12 @@ uint8_t btm_ble_ext_adv_active_count(void) for (uint8_t i = 0; i < MAX_BLE_ADV_INSTANCE; i++) { if (adv_record[i].enabled == true) { + BTM_TRACE_DEBUG("%s EXT ADV active #%d: instance=%d, duration=%d, max_events=%d", + __func__, + count, + adv_record[i].instance, + adv_record[i].duration, + adv_record[i].max_events); count++; } } diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble_bgconn.c b/components/bt/host/bluedroid/stack/btm/btm_ble_bgconn.c index bf9b1adbff3b..1210a26458d0 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_ble_bgconn.c +++ b/components/bt/host/bluedroid/stack/btm/btm_ble_bgconn.c @@ -821,6 +821,7 @@ tBTM_BLE_CONN_ST btm_ble_get_conn_st(void) *******************************************************************************/ void btm_ble_set_conn_st(tBTM_BLE_CONN_ST new_st) { + BTM_TRACE_DEBUG("%s old=%u new=%u", __func__, btm_cb.ble_ctr_cb.conn_state, new_st); btm_cb.ble_ctr_cb.conn_state = new_st; if (new_st == BLE_BG_CONN || new_st == BLE_DIR_CONN) { diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c b/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c index faf2e1848f0a..edb52e9e66d8 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c +++ b/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c @@ -2136,6 +2136,7 @@ void BTM_Recovery_Pre_State(void) { #if ((BLE_42_ADV_EN == TRUE) || (BLE_42_SCAN_EN == TRUE)) tBTM_BLE_INQ_CB *ble_inq_cb = &btm_cb.ble_ctr_cb.inq_var; + BTM_TRACE_DEBUG("%s state=0x%x", __func__, ble_inq_cb->state); #endif // #if ((BLE_42_ADV_EN == TRUE) || (BLE_42_SCAN_EN == TRUE)) #if (BLE_42_ADV_EN == TRUE) if (ble_inq_cb->state & BTM_BLE_ADVERTISING) { diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble_privacy.c b/components/bt/host/bluedroid/stack/btm/btm_ble_privacy.c index 39784bb11ad2..16617f3bd033 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_ble_privacy.c +++ b/components/bt/host/bluedroid/stack/btm/btm_ble_privacy.c @@ -984,6 +984,10 @@ BOOLEAN btm_ble_resolving_list_load_dev(tBTM_SEC_DEV_REC *p_dev_rec) *******************************************************************************/ void btm_ble_resolving_list_remove_dev(tBTM_SEC_DEV_REC *p_dev_rec) { + BTM_TRACE_EVENT ("%s - bd_addr=%02x:%02x:%02x:%02x:%02x:%02x", __func__, + p_dev_rec->bd_addr[0], p_dev_rec->bd_addr[1], p_dev_rec->bd_addr[2], + p_dev_rec->bd_addr[3], p_dev_rec->bd_addr[4], p_dev_rec->bd_addr[5]); + UINT8 rl_mask = btm_cb.ble_ctr_cb.rl_state; BTM_TRACE_EVENT ("%s\n", __func__); diff --git a/components/bt/host/bluedroid/stack/btm/btm_dev.c b/components/bt/host/bluedroid/stack/btm/btm_dev.c index 7e1095f4a51d..cc5ad3358b06 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_dev.c +++ b/components/bt/host/bluedroid/stack/btm/btm_dev.c @@ -73,9 +73,11 @@ BOOLEAN BTM_SecAddDevice (BD_ADDR bd_addr, DEV_CLASS dev_class, BD_NAME bd_name, /* There is no device record, allocate one. * If we can not find an empty spot for this one, let it fail. */ if (list_length(btm_cb.p_sec_dev_rec_list) < BTM_SEC_MAX_DEVICE_RECORDS) { - p_dev_rec = (tBTM_SEC_DEV_REC *)osi_malloc(sizeof(tBTM_SEC_DEV_REC)); - if(p_dev_rec) { - list_append(btm_cb.p_sec_dev_rec_list, p_dev_rec); + p_dev_rec = (tBTM_SEC_DEV_REC *)osi_malloc(sizeof(tBTM_SEC_DEV_REC)); + if(p_dev_rec) { + BTM_TRACE_DEBUG("%s alloc a new dev rec %p bd_addr="MACSTR"", + __func__, p_dev_rec, MAC2STR(bd_addr)); + list_append(btm_cb.p_sec_dev_rec_list, p_dev_rec); /* Mark this record as in use and initialize */ memset (p_dev_rec, 0, sizeof (tBTM_SEC_DEV_REC)); p_dev_rec->sec_flags = BTM_SEC_IN_USE; @@ -335,7 +337,8 @@ tBTM_SEC_DEV_REC *btm_sec_alloc_dev (BD_ADDR bd_addr) BOOLEAN new_entry_found = FALSE; BOOLEAN old_entry_found = FALSE; BOOLEAN malloc_new_entry = FALSE; - BTM_TRACE_EVENT ("btm_sec_alloc_dev\n"); + BTM_TRACE_EVENT ("btm_sec_alloc_dev - start alloc for device %02x:%02x:%02x:%02x:%02x:%02x", + bd_addr[0], bd_addr[1], bd_addr[2], bd_addr[3], bd_addr[4], bd_addr[5]); for (p_node = list_begin(btm_cb.p_sec_dev_rec_list); p_node; p_node = list_next(p_node)) { p_dev_old_rec = list_node(p_node); /* look for old entry which match the bd_addr and the BTM_SEC_IN_USE is cleared */ @@ -359,6 +362,8 @@ tBTM_SEC_DEV_REC *btm_sec_alloc_dev (BD_ADDR bd_addr) if (list_length(btm_cb.p_sec_dev_rec_list) < BTM_SEC_MAX_DEVICE_RECORDS){ p_dev_new_rec = (tBTM_SEC_DEV_REC *)osi_malloc(sizeof(tBTM_SEC_DEV_REC)); if (p_dev_new_rec) { + BTM_TRACE_DEBUG("%s alloc a new dev rec %p bd_addr="MACSTR"", + __func__, p_dev_new_rec, MAC2STR(bd_addr)); new_entry_found = TRUE; malloc_new_entry = TRUE; } else { @@ -691,6 +696,14 @@ tBTM_SEC_DEV_REC *btm_find_oldest_dev (void) old_ts = p_dev_rec->timestamp; } } + + if (p_oldest) { + BTM_TRACE_EVENT("oldest paired device found: bd_addr=%02x:%02x:%02x:%02x:%02x:%02x, timestamp=%u", + p_oldest->bd_addr[0], p_oldest->bd_addr[1], p_oldest->bd_addr[2], + p_oldest->bd_addr[3], p_oldest->bd_addr[4], p_oldest->bd_addr[5], + p_oldest->timestamp); + } + return (p_oldest); } /******************************************************************************* diff --git a/components/bt/host/bluedroid/stack/btm/btm_inq.c b/components/bt/host/bluedroid/stack/btm/btm_inq.c index 4456140df93f..41a47300e729 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_inq.c +++ b/components/bt/host/bluedroid/stack/btm/btm_inq.c @@ -240,13 +240,6 @@ tBTM_STATUS BTM_SetDiscoverability (UINT16 inq_mode, UINT16 window, UINT16 inter scan_mode |= HCI_PAGE_SCAN_ENABLED; } - if (btsnd_hcic_write_scan_enable (scan_mode)) { - btm_cb.btm_inq_vars.discoverable_mode &= (~BTM_DISCOVERABLE_MASK); - btm_cb.btm_inq_vars.discoverable_mode |= inq_mode; - } else { - return (BTM_NO_RESOURCES); - } - /* Change the service class bit if mode has changed */ p_cod = BTM_ReadDeviceClass(); BTM_COD_SERVICE_CLASS(service_class, p_cod); @@ -266,6 +259,13 @@ tBTM_STATUS BTM_SetDiscoverability (UINT16 inq_mode, UINT16 window, UINT16 inter (void) BTM_SetDeviceClass (cod); } + if (btsnd_hcic_write_scan_enable (scan_mode)) { + btm_cb.btm_inq_vars.discoverable_mode &= (~BTM_DISCOVERABLE_MASK); + btm_cb.btm_inq_vars.discoverable_mode |= inq_mode; + } else { + return (BTM_NO_RESOURCES); + } + return (BTM_SUCCESS); } diff --git a/components/bt/host/bluedroid/stack/btm/btm_main.c b/components/bt/host/bluedroid/stack/btm/btm_main.c index 67882af0efce..b109e5395b6c 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_main.c +++ b/components/bt/host/bluedroid/stack/btm/btm_main.c @@ -136,6 +136,15 @@ uint8_t btm_ble_acl_active_count(void) for (p_node = list_begin(btm_cb.p_acl_db_list); p_node; p_node = list_next(p_node)) { p_acl_conn = list_node(p_node); if (p_acl_conn && p_acl_conn->in_use && p_acl_conn->transport == BT_TRANSPORT_LE) { + BTM_TRACE_DEBUG("%s LE ACL active #%d: remote_addr=%02X:%02X:%02X:%02X:%02X:%02X", + __func__, + count, + p_acl_conn->remote_addr[0], + p_acl_conn->remote_addr[1], + p_acl_conn->remote_addr[2], + p_acl_conn->remote_addr[3], + p_acl_conn->remote_addr[4], + p_acl_conn->remote_addr[5]); count++; } } diff --git a/components/bt/host/bluedroid/stack/btu/btu_hcif.c b/components/bt/host/bluedroid/stack/btu/btu_hcif.c index eb2995b958d1..c9891b66b410 100644 --- a/components/bt/host/bluedroid/stack/btu/btu_hcif.c +++ b/components/bt/host/bluedroid/stack/btu/btu_hcif.c @@ -1128,7 +1128,9 @@ static void btu_hcif_esco_connection_chg_evt (UINT8 *p) static void btu_hcif_hdl_command_complete (UINT16 opcode, UINT8 *p, UINT16 evt_len, void *p_cplt_cback) { +#if (BLE_INCLUDED == TRUE) uint8_t status; +#endif // (BLE_INCLUDED == TRUE) switch (opcode) { #if (CLASSIC_BT_INCLUDED == TRUE) case HCI_INQUIRY_CANCEL: @@ -1395,10 +1397,6 @@ static void btu_hcif_hdl_command_complete (UINT16 opcode, UINT8 *p, UINT16 evt_l if ((opcode & HCI_GRP_VENDOR_SPECIFIC) == HCI_GRP_VENDOR_SPECIFIC) { btm_vsc_complete (p, opcode, evt_len, (tBTM_CMPL_CB *)p_cplt_cback); } - STREAM_TO_UINT8 (status, p); - if(status != HCI_SUCCESS) { - HCI_TRACE_ERROR("CC evt: op=0x%x, status=0x%x", opcode, status); - } break; } } @@ -1421,6 +1419,10 @@ static void btu_hcif_command_complete_evt_on_task(BT_HDR *event) uint8_t *stream = hack->response->data + hack->response->offset + 3; // 2 to skip the event headers, 1 to skip the command credits STREAM_TO_UINT16(opcode, stream); + if (*stream != HCI_SUCCESS) { + HCI_TRACE_WARNING("opcode=0x%04x, status= %02x: %s", opcode, *stream, hci_status_code_to_string(*stream)); + } + btu_hcif_hdl_command_complete( opcode, stream, @@ -1506,7 +1508,7 @@ static void btu_hcif_hdl_command_status (UINT16 opcode, UINT8 status, UINT8 *p_c void *p_vsc_status_cback) { if (status != HCI_SUCCESS){ - HCI_TRACE_WARNING("%s,opcode:0x%04x,status:0x%02x", __func__, opcode,status); + HCI_TRACE_WARNING("opcode=0x%04x, status= %02x: %s", opcode, status, hci_status_code_to_string(status)); } BD_ADDR bd_addr; UINT16 handle; diff --git a/components/bt/host/bluedroid/stack/gatt/att_protocol.c b/components/bt/host/bluedroid/stack/gatt/att_protocol.c index 310a9756efea..c242cc8e0535 100644 --- a/components/bt/host/bluedroid/stack/gatt/att_protocol.c +++ b/components/bt/host/bluedroid/stack/gatt/att_protocol.c @@ -33,7 +33,7 @@ #define GATT_HDR_FIND_TYPE_VALUE_LEN 21 #define GATT_OP_CODE_SIZE 1 /********************************************************************** -** ATT protocl message building utility * +** ATT protocol message building utility * ***********************************************************************/ /******************************************************************************* ** @@ -462,7 +462,7 @@ BT_HDR *attp_build_sr_msg(tGATT_TCB *p_tcb, UINT8 op_code, tGATT_SR_MSG *p_msg) ** Description This function sends the server response or indication message ** to client. ** -** Parameter p_tcb: pointer to the connecton control block. +** Parameter p_tcb: pointer to the connection control block. ** p_msg: pointer to message parameters structure. ** ** Returns GATT_SUCCESS if successfully sent; otherwise error code. @@ -628,7 +628,7 @@ tGATT_STATUS attp_send_cl_msg (tGATT_TCB *p_tcb, UINT16 clcb_idx, UINT8 op_code, if (p_cmd != NULL) { status = attp_cl_send_cmd(p_tcb, clcb_idx, op_code, p_cmd); } - + GATT_TRACE_DEBUG("%s opcode=%x status=%x", __func__, op_code, status); } else { GATT_TRACE_ERROR("Peer device not connected"); } diff --git a/components/bt/host/bluedroid/stack/gatt/gatt_main.c b/components/bt/host/bluedroid/stack/gatt/gatt_main.c index e5d982371252..0783255d0be5 100644 --- a/components/bt/host/bluedroid/stack/gatt/gatt_main.c +++ b/components/bt/host/bluedroid/stack/gatt/gatt_main.c @@ -995,6 +995,7 @@ void gatt_data_process (tGATT_TCB *p_tcb, BT_HDR *p_buf) pseudo_op_code = op_code & (~GATT_WRITE_CMD_MASK); if (pseudo_op_code < GATT_OP_CODE_MAX) { + GATT_TRACE_DEBUG("%s opcode=%x msg_len=%u", __func__, op_code, msg_len); if (op_code == GATT_SIGN_CMD_WRITE) { #if (SMP_INCLUDED == TRUE) gatt_verify_signature(p_tcb, p_buf); @@ -1220,7 +1221,6 @@ tGATT_CH_STATE gatt_get_ch_state(tGATT_TCB *p_tcb) { tGATT_CH_STATE ch_state = GATT_CH_CLOSE; if (p_tcb) { - GATT_TRACE_DEBUG ("gatt_get_ch_state: ch_state=%d", p_tcb->ch_state); ch_state = p_tcb->ch_state; } return ch_state; @@ -1233,6 +1233,7 @@ uint16_t gatt_get_local_mtu(void) void gatt_set_local_mtu(uint16_t mtu) { + GATT_TRACE_DEBUG("%s mtu=%u", __func__, mtu); gatt_default.local_mtu = mtu; } diff --git a/components/bt/host/bluedroid/stack/gatt/gatt_sr.c b/components/bt/host/bluedroid/stack/gatt/gatt_sr.c index 5947239cf1f3..585a4c921a0c 100644 --- a/components/bt/host/bluedroid/stack/gatt/gatt_sr.c +++ b/components/bt/host/bluedroid/stack/gatt/gatt_sr.c @@ -405,7 +405,7 @@ tGATT_STATUS gatt_sr_process_app_rsp (tGATT_TCB *p_tcb, tGATT_IF gatt_if, tGATT_STATUS ret_code = GATT_SUCCESS; UNUSED(trans_id); - GATT_TRACE_DEBUG("gatt_sr_process_app_rsp gatt_if=%d\n", gatt_if); + GATT_TRACE_DEBUG("gatt_sr_process_app_rsp gatt_if=%d opcode=%x\n", gatt_if, op_code); gatt_sr_update_cback_cnt(p_tcb, gatt_if, FALSE, FALSE); @@ -1827,6 +1827,7 @@ void gatt_server_handle_client_req (tGATT_TCB *p_tcb, UINT8 op_code, { /* there is pending command, discard this one */ if (!gatt_sr_cmd_empty(p_tcb) && op_code != GATT_HANDLE_VALUE_CONF) { + GATT_TRACE_WARNING("%s discard command opcode=%02x", __func__, op_code); return; } @@ -1891,6 +1892,7 @@ void gatt_server_handle_client_req (tGATT_TCB *p_tcb, UINT8 op_code, break; default: + GATT_TRACE_ERROR("%s unknown command opcode=%02x", __func__, op_code); break; } } diff --git a/components/bt/host/bluedroid/stack/gatt/gatt_utils.c b/components/bt/host/bluedroid/stack/gatt/gatt_utils.c index 5565169a782d..ae99c39a9fe4 100644 --- a/components/bt/host/bluedroid/stack/gatt/gatt_utils.c +++ b/components/bt/host/bluedroid/stack/gatt/gatt_utils.c @@ -1296,14 +1296,9 @@ BOOLEAN gatt_parse_uuid_from_cmd(tBT_UUID *p_uuid_rec, UINT16 uuid_size, UINT8 * void gatt_start_rsp_timer(UINT16 clcb_idx) { tGATT_CLCB *p_clcb = gatt_clcb_find_by_idx(clcb_idx); - UINT32 timeout = GATT_WAIT_FOR_RSP_TOUT; p_clcb->rsp_timer_ent.param = (TIMER_PARAM_TYPE)p_clcb; - if (p_clcb->operation == GATTC_OPTYPE_DISCOVERY && - p_clcb->op_subtype == GATT_DISC_SRVC_ALL) { - timeout = GATT_WAIT_FOR_DISC_RSP_TOUT; - } btu_start_timer (&p_clcb->rsp_timer_ent, BTU_TTYPE_ATT_WAIT_FOR_RSP, - timeout); + GATT_WAIT_FOR_RSP_TOUT); } /******************************************************************************* ** @@ -1369,7 +1364,8 @@ void gatt_rsp_timeout(TIMER_LIST_ENT *p_tle) } } - GATT_TRACE_WARNING("gatt_rsp_timeout disconnecting..."); + GATT_TRACE_WARNING("gatt_rsp_timeout conn_id=%x op=%u op_sub=%u retry_count=%u disconnecting...", + p_clcb->conn_id, p_clcb->operation, p_clcb->op_subtype, p_clcb->retry_count); gatt_disconnect (p_clcb->p_tcb); } @@ -1811,7 +1807,7 @@ void gatt_clcb_dealloc (tGATT_CLCB *p_clcb) btu_free_timer(&p_clcb->rsp_timer_ent); memset(p_clcb, 0, sizeof(tGATT_CLCB)); list_remove(gatt_cb.p_clcb_list, p_clcb); - p_clcb = NULL; + p_clcb = NULL; } } diff --git a/components/bt/host/bluedroid/stack/gatt/include/gatt_int.h b/components/bt/host/bluedroid/stack/gatt/include/gatt_int.h index f9d3cd8e5189..f00bed7e8ba1 100644 --- a/components/bt/host/bluedroid/stack/gatt/include/gatt_int.h +++ b/components/bt/host/bluedroid/stack/gatt/include/gatt_int.h @@ -76,9 +76,12 @@ typedef UINT8 tGATT_SEC_ACTION; #define GATT_HDR_SIZE 3 /* 1B opcode + 2B handle */ -/* wait for ATT cmd response timeout value */ -#define GATT_WAIT_FOR_RSP_TOUT 30 -#define GATT_WAIT_FOR_DISC_RSP_TOUT 15 +/** + * Wait for ATT cmd response timeout value (40 seconds). + * The max connection supervision timeout is 32 seconds, + * And The ATT cmd may not be sent out by controller immediately. + */ +#define GATT_WAIT_FOR_RSP_TOUT 40 #define GATT_REQ_RETRY_LIMIT 2 #define GATT_WAIT_FOR_IND_ACK_TOUT 5 diff --git a/components/bt/host/bluedroid/stack/hcic/hciblecmds.c b/components/bt/host/bluedroid/stack/hcic/hciblecmds.c index 5ad13216f77d..bd74d9dea15e 100644 --- a/components/bt/host/bluedroid/stack/hcic/hciblecmds.c +++ b/components/bt/host/bluedroid/stack/hcic/hciblecmds.c @@ -618,6 +618,8 @@ BOOLEAN btsnd_hcic_ble_start_enc (UINT16 handle, UINT8 rand[HCIC_BLE_RAND_DI_SIZ BT_HDR *p; UINT8 *pp; + HCI_TRACE_DEBUG("%s handle=%u LTK=%s", __func__, handle, bt_hex2str(ltk, HCIC_BLE_ENCRYT_KEY_SIZE)); + if ((p = HCI_GET_CMD_BUF(HCIC_PARAM_SIZE_BLE_START_ENC)) == NULL) { return (FALSE); } @@ -644,6 +646,8 @@ BOOLEAN btsnd_hcic_ble_ltk_req_reply (UINT16 handle, UINT8 ltk[HCIC_BLE_ENCRYT_K BT_HDR *p; UINT8 *pp; + HCI_TRACE_DEBUG("%s handle=%u LTK=%s", __func__, handle, bt_hex2str(ltk, HCIC_BLE_ENCRYT_KEY_SIZE)); + if ((p = HCI_GET_CMD_BUF(HCIC_PARAM_SIZE_LTK_REQ_REPLY)) == NULL) { return (FALSE); } @@ -668,6 +672,8 @@ BOOLEAN btsnd_hcic_ble_ltk_req_neg_reply (UINT16 handle) BT_HDR *p; UINT8 *pp; + HCI_TRACE_WARNING("%s handle=%u", __func__, handle); + if ((p = HCI_GET_CMD_BUF(HCIC_PARAM_SIZE_LTK_REQ_NEG_REPLY)) == NULL) { return (FALSE); } diff --git a/components/bt/host/bluedroid/stack/hid/hidd_conn.c b/components/bt/host/bluedroid/stack/hid/hidd_conn.c index 5a8e36ee599c..5c9164c2c539 100644 --- a/components/bt/host/bluedroid/stack/hid/hidd_conn.c +++ b/components/bt/host/bluedroid/stack/hid/hidd_conn.c @@ -775,6 +775,7 @@ tHID_STATUS hidd_conn_send_data(uint8_t channel, uint8_t msg_type, uint8_t param } return HID_SUCCESS; } + osi_free(p_buf); return HID_ERR_NO_CONNECTION; } #ifdef REPORT_TRANSFER_TIMESTAMP diff --git a/components/bt/host/bluedroid/stack/l2cap/l2c_api.c b/components/bt/host/bluedroid/stack/l2cap/l2c_api.c index fa01790d5f39..303751183130 100644 --- a/components/bt/host/bluedroid/stack/l2cap/l2c_api.c +++ b/components/bt/host/bluedroid/stack/l2cap/l2c_api.c @@ -215,7 +215,7 @@ UINT16 L2CA_ConnectReq (UINT16 psm, BD_ADDR p_bd_addr) ** ** Parameters: PSM: L2CAP PSM for the connection ** BD address of the peer -** Enhaced retransmission mode configurations +** Enhanced retransmission mode configurations ** Returns the CID of the connection, or 0 if it failed to start ** @@ -760,7 +760,7 @@ bool L2CA_GetIdentifiers(uint16_t lcid, uint16_t *rcid, uint16_t *handle) ** ** NOTE This timeout takes effect after at least 1 channel has been ** established and removed. L2CAP maintains its own timer from -** whan a connection is established till the first channel is +** when a connection is established till the first channel is ** set up. *******************************************************************************/ BOOLEAN L2CA_SetIdleTimeout (UINT16 cid, UINT16 timeout, BOOLEAN is_global) @@ -1901,6 +1901,8 @@ BOOLEAN L2CA_RemoveFixedChnl (UINT16 fixed_cid, BD_ADDR rem_bda) tL2C_CCB *p_ccb; tBT_TRANSPORT transport = BT_TRANSPORT_BR_EDR; + L2CAP_TRACE_DEBUG("%s cid=%04x bda="MACSTR"", __func__, fixed_cid, MAC2STR(rem_bda)); + /* Check CID is valid and registered */ if ( (fixed_cid < L2CAP_FIRST_FIXED_CHNL) || (fixed_cid > L2CAP_LAST_FIXED_CHNL) || (l2cb.fixed_reg[fixed_cid - L2CAP_FIRST_FIXED_CHNL].pL2CA_FixedData_Cb == NULL) ) { diff --git a/components/bt/host/bluedroid/stack/l2cap/l2c_ble.c b/components/bt/host/bluedroid/stack/l2cap/l2c_ble.c index 3ce25ab977ba..d3ae413b5fbc 100644 --- a/components/bt/host/bluedroid/stack/l2cap/l2c_ble.c +++ b/components/bt/host/bluedroid/stack/l2cap/l2c_ble.c @@ -92,6 +92,8 @@ BOOLEAN L2CA_CancelBleConnectReq (BD_ADDR rem_bda) { tL2C_LCB *p_lcb; + L2CAP_TRACE_DEBUG("%s rem_bda="MACSTR"", __func__, MAC2STR(rem_bda)); + /* There can be only one BLE connection request outstanding at a time */ if (btm_ble_get_conn_st() == BLE_CONN_IDLE) { L2CAP_TRACE_WARNING ("L2CA_CancelBleConnectReq - no connection pending"); @@ -99,10 +101,8 @@ BOOLEAN L2CA_CancelBleConnectReq (BD_ADDR rem_bda) } if (memcmp (rem_bda, l2cb.ble_connecting_bda, BD_ADDR_LEN)) { - L2CAP_TRACE_WARNING ("L2CA_CancelBleConnectReq - different BDA Connecting: %08x%04x Cancel: %08x%04x", - (l2cb.ble_connecting_bda[0] << 24) + (l2cb.ble_connecting_bda[1] << 16) + (l2cb.ble_connecting_bda[2] << 8) + l2cb.ble_connecting_bda[3], - (l2cb.ble_connecting_bda[4] << 8) + l2cb.ble_connecting_bda[5], - (rem_bda[0] << 24) + (rem_bda[1] << 16) + (rem_bda[2] << 8) + rem_bda[3], (rem_bda[4] << 8) + rem_bda[5]); + L2CAP_TRACE_WARNING ("L2CA_CancelBleConnectReq - different BDA Connecting: "MACSTR" Cancel: "MACSTR"", + MAC2STR(l2cb.ble_connecting_bda), MAC2STR(rem_bda)); return (FALSE); } @@ -148,16 +148,12 @@ BOOLEAN L2CA_UpdateBleConnParams (BD_ADDR rem_bda, UINT16 min_int, UINT16 max_in /* If we don't have one, create one and accept the connection. */ if (!p_lcb || !p_acl_cb) { - L2CAP_TRACE_WARNING ("L2CA_UpdateBleConnParams - unknown BD_ADDR %08x%04x", - (rem_bda[0] << 24) + (rem_bda[1] << 16) + (rem_bda[2] << 8) + rem_bda[3], - (rem_bda[4] << 8) + rem_bda[5]); + L2CAP_TRACE_WARNING ("L2CA_UpdateBleConnParams - unknown BD_ADDR "MACSTR"", MAC2STR(rem_bda)); return (FALSE); } if (p_lcb->transport != BT_TRANSPORT_LE) { - L2CAP_TRACE_WARNING ("L2CA_UpdateBleConnParams - BD_ADDR %08x%04x not LE", - (rem_bda[0] << 24) + (rem_bda[1] << 16) + (rem_bda[2] << 8) + rem_bda[3], - (rem_bda[4] << 8) + rem_bda[5]); + L2CAP_TRACE_WARNING ("L2CA_UpdateBleConnParams - BD_ADDR "MACSTR" not LE", MAC2STR(rem_bda)); return (FALSE); } @@ -172,7 +168,7 @@ BOOLEAN L2CA_UpdateBleConnParams (BD_ADDR rem_bda, UINT16 min_int, UINT16 max_in if (p_lcb->conn_update_mask & L2C_BLE_UPDATE_PARAM_FULL){ status = HCI_ERR_ILLEGAL_COMMAND; need_cb = true; - L2CAP_TRACE_ERROR("There are two connection parameter requests that are being updated, please try later "); + L2CAP_TRACE_ERROR("%s connection parameter update in progress, please try later", __func__); } if ((need_cb == TRUE) && (conn_callback_func.update_conn_param_cb != NULL)) { @@ -221,20 +217,16 @@ BOOLEAN L2CA_EnableUpdateBleConnParams (BD_ADDR rem_bda, BOOLEAN enable) p_lcb = l2cu_find_lcb_by_bd_addr (rem_bda, BT_TRANSPORT_LE); if (!p_lcb) { - L2CAP_TRACE_WARNING ("L2CA_EnableUpdateBleConnParams - unknown BD_ADDR %08x%04x", - (rem_bda[0] << 24) + (rem_bda[1] << 16) + (rem_bda[2] << 8) + rem_bda[3], - (rem_bda[4] << 8) + rem_bda[5]); + L2CAP_TRACE_WARNING ("L2CA_EnableUpdateBleConnParams - unknown BD_ADDR "MACSTR"", MAC2STR(rem_bda)); return (FALSE); } - L2CAP_TRACE_API ("%s - BD_ADDR %08x%04x enable %d current upd state 0x%02x", __FUNCTION__, - (rem_bda[0] << 24) + (rem_bda[1] << 16) + (rem_bda[2] << 8) + rem_bda[3], - (rem_bda[4] << 8) + rem_bda[5], enable, p_lcb->conn_update_mask); + L2CAP_TRACE_API ("%s - BD_ADDR "MACSTR" enable %d current upd state 0x%02x", + __func__, MAC2STR(rem_bda), enable, p_lcb->conn_update_mask); if (p_lcb->transport != BT_TRANSPORT_LE) { - L2CAP_TRACE_WARNING ("%s - BD_ADDR %08x%04x not LE (link role %d)", __FUNCTION__, - (rem_bda[0] << 24) + (rem_bda[1] << 16) + (rem_bda[2] << 8) + rem_bda[3], - (rem_bda[4] << 8) + rem_bda[5], p_lcb->link_role); + L2CAP_TRACE_WARNING ("%s - BD_ADDR "MACSTR" not LE (link role %d)", + __func__, MAC2STR(rem_bda), p_lcb->link_role); return (FALSE); } diff --git a/components/bt/host/bluedroid/stack/l2cap/l2c_utils.c b/components/bt/host/bluedroid/stack/l2cap/l2c_utils.c index 64ebcbd4363c..0d3fed93d1db 100644 --- a/components/bt/host/bluedroid/stack/l2cap/l2c_utils.c +++ b/components/bt/host/bluedroid/stack/l2cap/l2c_utils.c @@ -25,7 +25,6 @@ #include #include -#include "osi/allocator.h" #include "device/controller.h" #include "stack/bt_types.h" #include "stack/hcimsgs.h" @@ -36,6 +35,7 @@ #include "stack/btm_api.h" #include "btm_int.h" #include "stack/hcidefs.h" +#include "bt_common.h" #include "osi/allocator.h" #include "osi/list.h" @@ -158,6 +158,9 @@ void l2cu_release_lcb (tL2C_LCB *p_lcb) { tL2C_CCB *p_ccb; + L2CAP_TRACE_DEBUG("%s handle=%u bda="MACSTR"", + __func__, p_lcb->handle, MAC2STR(p_lcb->remote_bd_addr)); + p_lcb->in_use = FALSE; p_lcb->is_bonding = FALSE; #if (BLE_INCLUDED == TRUE) @@ -345,6 +348,15 @@ uint8_t l2cu_ble_plcb_active_count(void) for (p_node = list_begin(l2cb.p_lcb_pool); p_node; p_node = list_next(p_node)) { p_lcb = list_node(p_node); if (p_lcb && p_lcb->in_use && p_lcb->transport == BT_TRANSPORT_LE) { + L2CAP_TRACE_DEBUG("%s LE PLCB active #%d: remote_addr=%02X:%02X:%02X:%02X:%02X:%02X", + __func__, + active_count, + p_lcb->remote_bd_addr[0], + p_lcb->remote_bd_addr[1], + p_lcb->remote_bd_addr[2], + p_lcb->remote_bd_addr[3], + p_lcb->remote_bd_addr[4], + p_lcb->remote_bd_addr[5]); active_count ++; } } diff --git a/components/bt/host/bluedroid/stack/smp/smp_act.c b/components/bt/host/bluedroid/stack/smp/smp_act.c index a41fbdd1b17b..591c083c5d51 100644 --- a/components/bt/host/bluedroid/stack/smp/smp_act.c +++ b/components/bt/host/bluedroid/stack/smp/smp_act.c @@ -79,7 +79,7 @@ static bool lmp_version_below(BD_ADDR bda, uint8_t version) *******************************************************************************/ static void smp_update_key_mask (tSMP_CB *p_cb, UINT8 key_type, BOOLEAN recv) { - SMP_TRACE_DEBUG("%s before update role=%d recv=%d local_i_key = %02x, local_r_key = %02x\n", + SMP_TRACE_DEBUG("%s before update role=%d recv=%d local_i_key = %02x, local_r_key = %02x", __func__, p_cb->role, recv, p_cb->local_i_key, p_cb->local_r_key); if (((p_cb->le_secure_connections_mode_is_used) || @@ -103,8 +103,8 @@ static void smp_update_key_mask (tSMP_CB *p_cb, UINT8 key_type, BOOLEAN recv) } } - SMP_TRACE_DEBUG("updated local_i_key = %02x, local_r_key = %02x\n", p_cb->local_i_key, - p_cb->local_r_key); + SMP_TRACE_DEBUG("updated local_i_key = %02x, local_r_key = %02x", + p_cb->local_i_key, p_cb->local_r_key); } /******************************************************************************* @@ -115,7 +115,7 @@ void smp_send_app_cback(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) { tSMP_EVT_DATA cb_data; tSMP_STATUS callback_rc; - SMP_TRACE_DEBUG("%s p_cb->cb_evt=%d\n", __func__, p_cb->cb_evt); + SMP_TRACE_DEBUG("%s cb_evt=%d", __func__, p_cb->cb_evt); if (p_cb->p_callback && p_cb->cb_evt != 0) { switch (p_cb->cb_evt) { case SMP_IO_CAP_REQ_EVT: @@ -171,11 +171,11 @@ void smp_send_app_cback(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) p_cb->local_r_key = 0; } - SMP_TRACE_DEBUG ("rcvd auth_req: 0x%02x, io_cap: %d \ - loc_oob_flag: %d loc_enc_size: %d," - "local_i_key: 0x%02x, local_r_key: 0x%02x\n", - p_cb->loc_auth_req, p_cb->local_io_capability, p_cb->loc_oob_flag, - p_cb->loc_enc_size, p_cb->local_i_key, p_cb->local_r_key); + SMP_TRACE_DEBUG ("rcvd auth_req: 0x%02x, io_cap: %d," + "loc_oob_flag: %d loc_enc_size: %d," + "local_i_key: 0x%02x, local_r_key: 0x%02x", + p_cb->loc_auth_req, p_cb->local_io_capability, p_cb->loc_oob_flag, + p_cb->loc_enc_size, p_cb->local_i_key, p_cb->local_r_key); p_cb->secure_connections_only_mode_required = (btm_cb.security_mode == BTM_SEC_MODE_SC) ? TRUE : FALSE; @@ -222,8 +222,6 @@ void smp_send_app_cback(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) p_cb->discard_sec_req = FALSE; smp_sm_event(p_cb, SMP_DISCARD_SEC_REQ_EVT, NULL); } - - SMP_TRACE_DEBUG("%s return\n", __func__); } /******************************************************************************* @@ -249,7 +247,7 @@ void smp_send_pair_fail(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) *******************************************************************************/ void smp_send_pair_req(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) { - SMP_TRACE_DEBUG("%s\n", __func__); + SMP_TRACE_DEBUG("%s", __func__); #if (BLE_INCLUDED == TRUE) tBTM_SEC_DEV_REC *p_dev_rec = btm_find_dev (p_cb->pairing_bda); @@ -269,7 +267,7 @@ void smp_send_pair_req(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) *******************************************************************************/ void smp_send_pair_rsp(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) { - SMP_TRACE_DEBUG("%s\n", __func__); + SMP_TRACE_DEBUG("%s", __func__); #if (BLE_INCLUDED == TRUE) p_cb->local_i_key &= p_cb->peer_i_key; @@ -291,7 +289,7 @@ void smp_send_pair_rsp(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) *******************************************************************************/ void smp_send_confirm(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) { - SMP_TRACE_DEBUG("%s\n", __func__); + SMP_TRACE_DEBUG("%s", __func__); smp_send_cmd(SMP_OPCODE_CONFIRM, p_cb); } @@ -313,7 +311,7 @@ void smp_send_init(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) *******************************************************************************/ void smp_send_rand(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) { - SMP_TRACE_DEBUG("%s\n", __func__); + SMP_TRACE_DEBUG("%s", __func__); smp_send_cmd(SMP_OPCODE_RAND, p_cb); } @@ -323,7 +321,7 @@ void smp_send_rand(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) *******************************************************************************/ void smp_send_pair_public_key(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) { - SMP_TRACE_DEBUG("%s\n", __func__); + SMP_TRACE_DEBUG("%s", __func__); smp_send_cmd(SMP_OPCODE_PAIR_PUBLIC_KEY, p_cb); } @@ -365,7 +363,7 @@ void smp_send_enc_info(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) { tBTM_LE_LENC_KEYS le_key; - SMP_TRACE_DEBUG("%s p_cb->loc_enc_size = %d\n", __func__, p_cb->loc_enc_size); + SMP_TRACE_DEBUG("%s loc_enc_size = %d", __func__, p_cb->loc_enc_size); smp_update_key_mask (p_cb, SMP_SEC_KEY_TYPE_ENC, FALSE); smp_send_cmd(SMP_OPCODE_ENCRYPT_INFO, p_cb); @@ -383,8 +381,6 @@ void smp_send_enc_info(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) (tBTM_LE_KEY_VALUE *)&le_key, TRUE); } - SMP_TRACE_DEBUG ("%s\n", __func__); - smp_key_distribution(p_cb, NULL); #endif ///BLE_INCLUDED == TRUE } @@ -395,7 +391,7 @@ void smp_send_enc_info(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) *******************************************************************************/ void smp_send_id_info(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) { - SMP_TRACE_DEBUG("%s\n", __func__); + SMP_TRACE_DEBUG("%s", __func__); smp_update_key_mask (p_cb, SMP_SEC_KEY_TYPE_ID, FALSE); smp_send_cmd(SMP_OPCODE_IDENTITY_INFO, p_cb); @@ -420,7 +416,7 @@ void smp_send_id_info(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) void smp_send_csrk_info(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) { tBTM_LE_LCSRK_KEYS key; - SMP_TRACE_DEBUG("%s\n", __func__); + SMP_TRACE_DEBUG("%s", __func__); smp_update_key_mask (p_cb, SMP_SEC_KEY_TYPE_CSRK, FALSE); if (smp_send_cmd(SMP_OPCODE_SIGN_INFO, p_cb)) { @@ -455,12 +451,10 @@ void smp_proc_sec_req(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) tBTM_BLE_SEC_REQ_ACT sec_req_act; UINT8 reason; - SMP_TRACE_DEBUG("%s auth_req=0x%x", __func__, auth_req); - p_cb->cb_evt = 0; btm_ble_link_sec_check(p_cb->pairing_bda, auth_req, &sec_req_act); - SMP_TRACE_DEBUG("%s sec_req_act=0x%x", __func__, sec_req_act); + SMP_TRACE_DEBUG("%s auth_req=0x%x sec_req_act=0x%x", __func__, auth_req, sec_req_act); switch (sec_req_act) { case BTM_BLE_SEC_REQ_ACT_ENCRYPT: @@ -475,6 +469,8 @@ void smp_proc_sec_req(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) /* respond to non SC pairing request as failure in SC only mode */ if (p_cb->secure_connections_only_mode_required && (auth_req & SMP_SC_SUPPORT_BIT) == 0) { + SMP_TRACE_ERROR("%s SC mode not support, auth_req=0x%x", + __func__, auth_req); reason = SMP_PAIR_AUTH_FAIL; smp_sm_event(p_cb, SMP_AUTH_CMPL_EVT, &reason); } else { @@ -503,7 +499,7 @@ void smp_proc_sec_req(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) void smp_proc_sec_grant(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) { UINT8 res = *(UINT8 *)p_data; - SMP_TRACE_DEBUG("%s", __func__); + SMP_TRACE_DEBUG("%s res=0x%x", __func__, res); if (res != SMP_SUCCESS) { smp_sm_event(p_cb, SMP_AUTH_CMPL_EVT, p_data); } else { /*otherwise, start pairing */ @@ -560,7 +556,7 @@ void smp_proc_pair_cmd(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) UINT8 reason = SMP_ENC_KEY_SIZE; tBTM_SEC_DEV_REC *p_dev_rec = btm_find_dev (p_cb->pairing_bda); - SMP_TRACE_DEBUG("%s\n", __func__); + SMP_TRACE_DEBUG("%s", __func__); /* erase all keys if it is slave proc pairing req*/ if (p_dev_rec && (p_cb->role == HCI_ROLE_SLAVE)) { btm_sec_clear_ble_keys(p_dev_rec); @@ -682,7 +678,7 @@ void smp_proc_confirm(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) UINT8 *p = (UINT8 *)p_data; UINT8 reason = SMP_INVALID_PARAMETERS; - SMP_TRACE_DEBUG("%s\n", __func__); + SMP_TRACE_DEBUG("%s", __func__); if (smp_command_has_invalid_parameters(p_cb)) { smp_sm_event(p_cb, SMP_AUTH_CMPL_EVT, &reason); @@ -1170,6 +1166,7 @@ void smp_proc_compare(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) } } else { + SMP_TRACE_ERROR("%s pairing failed - check confirm value error", __func__); reason = p_cb->failure = SMP_CONFIRM_VALUE_ERR; smp_sm_event(p_cb, SMP_AUTH_CMPL_EVT, &reason); } @@ -1213,6 +1210,7 @@ void smp_start_enc(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) } if (cmd != BTM_CMD_STARTED && cmd != BTM_BUSY) { + SMP_TRACE_ERROR("%s start encryption failed, cmd=0x%x", __func__, cmd); smp_sm_event(p_cb, SMP_AUTH_CMPL_EVT, &reason); } } @@ -1239,7 +1237,7 @@ void smp_enc_cmpl(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) UINT8 enc_enable = *(UINT8 *)p_data; UINT8 reason = enc_enable ? SMP_SUCCESS : SMP_ENC_FAIL; - SMP_TRACE_DEBUG("%s\n", __func__); + SMP_TRACE_DEBUG("%s %u", __func__, enc_enable); smp_sm_event(p_cb, SMP_AUTH_CMPL_EVT, &reason); } diff --git a/components/bt/host/bluedroid/stack/smp/smp_api.c b/components/bt/host/bluedroid/stack/smp/smp_api.c index 78e295f4f1f6..28c4761413a8 100644 --- a/components/bt/host/bluedroid/stack/smp/smp_api.c +++ b/components/bt/host/bluedroid/stack/smp/smp_api.c @@ -236,7 +236,7 @@ BOOLEAN SMP_PairCancel (BD_ADDR bd_addr) if ( (p_cb->state != SMP_STATE_IDLE) && (!memcmp (p_cb->pairing_bda, bd_addr, BD_ADDR_LEN)) ) { p_cb->is_pair_cancel = TRUE; - SMP_TRACE_DEBUG("Cancel Pairing: set fail reason Unknown"); + SMP_TRACE_ERROR("%s Cancel Pairing: set fail reason Unknown", __func__); smp_sm_event(p_cb, SMP_AUTH_CMPL_EVT, &err_code); status = TRUE; } @@ -434,6 +434,8 @@ void SMP_OobDataReply(BD_ADDR bd_addr, tSMP_STATUS res, UINT8 len, UINT8 *p_data } if (res != SMP_SUCCESS || len == 0 || !p_data) { + SMP_TRACE_ERROR("%s pairing failed, res=0x%x len=%u p_data=%p", + __func__, res, len, p_data); smp_sm_event(p_cb, SMP_AUTH_CMPL_EVT, &failure); } else { if (len > BT_OCTET16_LEN) { @@ -524,10 +526,10 @@ void SMP_SecureConnectionOobDataReply(UINT8 *p_data) ** Description This function is called to encrypt the data with the specified ** key ** -** Parameters: key - Pointer to key key[0] conatins the MSB +** Parameters: key - Pointer to key key[0] contains the MSB ** key_len - key length ** plain_text - Pointer to data to be encrypted -** plain_text[0] conatins the MSB +** plain_text[0] contains the MSB ** pt_len - plain text length ** p_out - output of the encrypted texts ** diff --git a/components/bt/host/bluedroid/stack/smp/smp_keys.c b/components/bt/host/bluedroid/stack/smp/smp_keys.c index aec6f709c560..855017a76a8a 100644 --- a/components/bt/host/bluedroid/stack/smp/smp_keys.c +++ b/components/bt/host/bluedroid/stack/smp/smp_keys.c @@ -332,7 +332,7 @@ void smp_generate_stk(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) output.opcode = HCI_BLE_ENCRYPT; memcpy(output.param_buf, p_cb->ltk, SMP_ENCRYT_DATA_SIZE); } else if (!smp_calculate_legacy_short_term_key(p_cb, &output)) { - SMP_TRACE_ERROR("%s failed", __func__); + SMP_TRACE_ERROR("%s pairing failed", __func__); smp_sm_event(p_cb, SMP_AUTH_CMPL_EVT, &status); return; } @@ -459,7 +459,7 @@ void smp_compute_csrk(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) UINT16_TO_STREAM(p, r); if (!SMP_Encrypt(er, BT_OCTET16_LEN, buffer, 4, &output)) { - SMP_TRACE_ERROR("smp_generate_csrk failed\n"); + SMP_TRACE_ERROR("%s pairing failed", __func__); if (p_cb->smp_over_br) { #if (CLASSIC_BT_INCLUDED == TRUE) smp_br_state_machine_event(p_cb, SMP_BR_AUTH_CMPL_EVT, &status); @@ -549,7 +549,7 @@ void smp_concatenate_peer( tSMP_CB *p_cb, UINT8 **p_data, UINT8 op_code) ** Function smp_gen_p1_4_confirm ** ** Description Generate Confirm/Compare Step1: -** p1 = pres || preq || rat' || iat' +** p1 = press || preq || rat' || iat' ** ** Returns void ** @@ -574,22 +574,22 @@ void smp_gen_p1_4_confirm( tSMP_CB *p_cb, BT_OCTET16 p1) UINT8_TO_STREAM(p, p_cb->addr_type); /* LSB : iat': responder's address type */ UINT8_TO_STREAM(p, addr_type); - /* concatinate preq */ + /* concatenate preq */ smp_concatenate_local(p_cb, &p, SMP_OPCODE_PAIRING_REQ); - /* concatinate pres */ + /* concatenate press */ smp_concatenate_peer(p_cb, &p, SMP_OPCODE_PAIRING_RSP); } else { /* LSB : iat': initiator's address type */ UINT8_TO_STREAM(p, addr_type); /* LSB : rat': responder's(local) address type */ UINT8_TO_STREAM(p, p_cb->addr_type); - /* concatinate preq */ + /* concatenate preq */ smp_concatenate_peer(p_cb, &p, SMP_OPCODE_PAIRING_REQ); - /* concatinate pres */ + /* concatenate press */ smp_concatenate_local(p_cb, &p, SMP_OPCODE_PAIRING_RSP); } #if SMP_DEBUG == TRUE - SMP_TRACE_DEBUG("p1 = pres || preq || rat' || iat'\n"); + SMP_TRACE_DEBUG("p1 = press || preq || rat' || iat'\n"); smp_debug_print_nbyte_little_endian ((UINT8 *)p1, (const UINT8 *)"P1", 16); #endif } @@ -654,7 +654,7 @@ void smp_calculate_comfirm (tSMP_CB *p_cb, BT_OCTET16 rand, BD_ADDR bda) tSMP_STATUS status = SMP_PAIR_FAIL_UNKNOWN; SMP_TRACE_DEBUG ("smp_calculate_comfirm \n"); - /* generate p1 = pres || preq || rat' || iat' */ + /* generate p1 = press || preq || rat' || iat' */ smp_gen_p1_4_confirm(p_cb, p1); /* p1 = rand XOR p1 */ @@ -664,7 +664,7 @@ void smp_calculate_comfirm (tSMP_CB *p_cb, BT_OCTET16 rand, BD_ADDR bda) /* calculate e(k, r XOR p1), where k = TK */ if (!SMP_Encrypt(p_cb->tk, BT_OCTET16_LEN, p1, BT_OCTET16_LEN, &output)) { - SMP_TRACE_ERROR("smp_generate_csrk failed"); + SMP_TRACE_ERROR("%s calculate TK failed", __func__); smp_sm_event(p_cb, SMP_AUTH_CMPL_EVT, &status); } else { smp_calculate_comfirm_cont(p_cb, &output); @@ -701,7 +701,7 @@ static void smp_calculate_comfirm_cont(tSMP_CB *p_cb, tSMP_ENC *p) /* calculate: Confirm = E(k, p1' XOR p2) */ if (!SMP_Encrypt(p_cb->tk, BT_OCTET16_LEN, p2, BT_OCTET16_LEN, &output)) { - SMP_TRACE_ERROR("smp_calculate_comfirm_cont failed\n"); + SMP_TRACE_ERROR("%s pairing failed", __func__); smp_sm_event(p_cb, SMP_AUTH_CMPL_EVT, &status); } else { SMP_TRACE_DEBUG("p_cb->rand_enc_proc_state=%d\n", p_cb->rand_enc_proc_state); @@ -861,7 +861,7 @@ static void smp_generate_ltk_cont(tSMP_CB *p_cb, tSMP_INT_DATA *p_data) /* LTK = d1(ER, DIV, 0)= e(ER, DIV)*/ if (!SMP_Encrypt(er, BT_OCTET16_LEN, (UINT8 *)&p_cb->div, sizeof(UINT16), &output)) { - SMP_TRACE_ERROR("%s failed\n", __func__); + SMP_TRACE_ERROR("%s failed", __func__); smp_sm_event(p_cb, SMP_AUTH_CMPL_EVT, &status); } else { /* mask the LTK */ @@ -1373,6 +1373,8 @@ void smp_calculate_numeric_comparison_display_number(tSMP_CB *p_cb, } if (p_cb->number_to_display >= (BTM_MAX_PASSKEY_VAL + 1)) { + SMP_TRACE_ERROR("%s pairing failed - invalid number to display %u", + __func__, p_cb->number_to_display); UINT8 reason; reason = p_cb->failure = SMP_PAIR_FAIL_UNKNOWN; smp_sm_event(p_cb, SMP_AUTH_CMPL_EVT, &reason); diff --git a/components/bt/host/bluedroid/stack/smp/smp_main.c b/components/bt/host/bluedroid/stack/smp/smp_main.c index 512aca0a8c5c..fa4d5ffbe323 100644 --- a/components/bt/host/bluedroid/stack/smp/smp_main.c +++ b/components/bt/host/bluedroid/stack/smp/smp_main.c @@ -388,7 +388,7 @@ static const UINT8 smp_master_wait_dhk_check_table[][SMP_SM_NUM_COLS] = { static const UINT8 smp_master_dhk_check_table[][SMP_SM_NUM_COLS] = { /* Event Action Next State */ - /* locally calculated peer dhkey check is ready -> compare it withs DHKey Check actually received from peer */ + /* locally calculated peer dhkey check is ready -> compare it with DHKey Check actually received from peer */ /* SC_KEY_READY */{SMP_MATCH_DHKEY_CHECKS, SMP_SM_NO_ACTION, SMP_STATE_DHK_CHECK}, /* locally calculated peer dhkey check is ready -> calculate STK, go to sending */ /* HCI LE Start Encryption command */ @@ -580,7 +580,7 @@ static const UINT8 smp_slave_wait_dhk_check_table[][SMP_SM_NUM_COLS] = { static const UINT8 smp_slave_dhk_check_table[][SMP_SM_NUM_COLS] = { /* Event Action Next State */ - /* locally calculated peer dhkey check is ready -> compare it withs DHKey Check */ + /* locally calculated peer dhkey check is ready -> compare it with DHKey Check */ /* actually received from peer */ /* SC_KEY_READY */{SMP_MATCH_DHKEY_CHECKS, SMP_SM_NO_ACTION, SMP_STATE_DHK_CHECK}, @@ -771,6 +771,8 @@ void smp_sm_event(tSMP_CB *p_cb, tSMP_EVENT event, void *p_data) /* execute action functions */ for (i = 0; i < SMP_NUM_ACTIONS; i++) { if ((action = state_table[entry - 1][i]) != SMP_SM_NO_ACTION && smp_sm_action[action] != NULL) { + SMP_TRACE_DEBUG("smp action %d for state %s, event %s", + action, smp_get_state_name(curr_state), smp_get_event_name(event)); (*smp_sm_action[action])(p_cb, (tSMP_INT_DATA *)p_data); } else { break; diff --git a/components/bt/host/bluedroid/stack/smp/smp_utils.c b/components/bt/host/bluedroid/stack/smp/smp_utils.c index 48ba6c0ae302..f7ade05ac063 100644 --- a/components/bt/host/bluedroid/stack/smp/smp_utils.c +++ b/components/bt/host/bluedroid/stack/smp/smp_utils.c @@ -366,6 +366,7 @@ BOOLEAN smp_send_cmd(UINT8 cmd_code, tSMP_CB *p_cb) } if (!sent) { + SMP_TRACE_ERROR("%s failed, cmd_code=0x%02x", __func__, cmd_code); if (p_cb->smp_over_br) { #if (CLASSIC_BT_INCLUDED == TRUE) smp_br_state_machine_event(p_cb, SMP_BR_AUTH_CMPL_EVT, &failure); @@ -392,7 +393,7 @@ void smp_rsp_timeout(TIMER_LIST_ENT *p_tle) UINT8 failure = SMP_RSP_TIMEOUT; UNUSED(p_tle); - SMP_TRACE_EVENT("%s state:%d br_state:%d", __FUNCTION__, p_cb->state, p_cb->br_state); + SMP_TRACE_ERROR("%s state=%d br_state=%d", __func__, p_cb->state, p_cb->br_state); if (p_cb->smp_over_br) { #if (CLASSIC_BT_INCLUDED == TRUE) diff --git a/components/bt/host/nimble/Kconfig.in b/components/bt/host/nimble/Kconfig.in index fe9b86d83dc6..639293aad51b 100644 --- a/components/bt/host/nimble/Kconfig.in +++ b/components/bt/host/nimble/Kconfig.in @@ -485,6 +485,26 @@ menu "Memory Settings" default 1 help This is the service data unit buffer count for l2cap coc. + + config BT_NIMBLE_MEMPOOL_RUNTIME_ALLOC + bool "Support on-demand runtime memory allocation for mempool" + depends on BT_NIMBLE_ENABLED && !SOC_ESP_NIMBLE_CONTROLLER + default n + help + When this option is enabled, mempool does not require pre-allocating memory. + Instead, memory for each block will be dynamically allocated and released + during mempool usage. This can significantly reduce memory consumption + after mempool initialization, but may have some impact on performance. + + config BT_NIMBLE_MEMPOOL_BLOCK_REUSED + bool "Support block reuse for mempool runtime memory allocation" + depends on BT_NIMBLE_MEMPOOL_RUNTIME_ALLOC + default n + help + When this option is enabled, dynamically allocated blocks will not be freed + but will be reused instead. This ensures virtually no impact on performance + while reducing the memory consumption of the mempool. + endmenu #Memory menu "BLE 5.x Features" @@ -721,11 +741,15 @@ menu "BLE 6.x Features" if BT_NIMBLE_60_FEATURE_SUPPORT config BT_NIMBLE_CHANNEL_SOUNDING bool "ble channel souding feature" - depends on BT_NIMBLE_ENABLED default n help Used to enable/disable the channel sounding feature + config BT_NIMBLE_MONITOR_ADV + bool "Enable Monitor Advertising" + default n + help + Enable support for Monitor Advertisers. endif endmenu #BLE6.x diff --git a/components/bt/host/nimble/esp-hci/src/esp_nimble_hci.c b/components/bt/host/nimble/esp-hci/src/esp_nimble_hci.c index ec736ccc84d3..520e2a67a85a 100644 --- a/components/bt/host/nimble/esp-hci/src/esp_nimble_hci.c +++ b/components/bt/host/nimble/esp-hci/src/esp_nimble_hci.c @@ -96,7 +96,11 @@ int ble_hci_trans_hs_cmd_tx(uint8_t *cmd) rc = BLE_HS_ETIMEOUT_HCI; } +#if MYNEWT_VAL(MP_RUNTIME_ALLOC) + ble_transport_free(BLE_HCI_CMD, cmd); +#else ble_transport_free(cmd); +#endif return rc; } diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble index 8fd41d86c4ed..9551ac31af03 160000 --- a/components/bt/host/nimble/nimble +++ b/components/bt/host/nimble/nimble @@ -1 +1 @@ -Subproject commit 8fd41d86c4ed8657e6c97d6da8b3d214622db737 +Subproject commit 9551ac31af0348d7de6cbe7527de3e5ba205460d diff --git a/components/bt/host/nimble/port/include/esp_nimble_cfg.h b/components/bt/host/nimble/port/include/esp_nimble_cfg.h index 620df768e73e..445c0e295725 100644 --- a/components/bt/host/nimble/port/include/esp_nimble_cfg.h +++ b/components/bt/host/nimble/port/include/esp_nimble_cfg.h @@ -2206,4 +2206,28 @@ #endif #endif +#ifndef MYNEWT_VAL_BLE_MONITOR_ADV +#ifdef CONFIG_BT_NIMBLE_MONITOR_ADV +#define MYNEWT_VAL_BLE_MONITOR_ADV CONFIG_BT_NIMBLE_MONITOR_ADV +#else +#define MYNEWT_VAL_BLE_MONITOR_ADV (0) +#endif +#endif + +#ifndef MYNEWT_VAL_MP_RUNTIME_ALLOC +#ifdef CONFIG_BT_NIMBLE_MEMPOOL_RUNTIME_ALLOC +#define MYNEWT_VAL_MP_RUNTIME_ALLOC (1) +#else +#define MYNEWT_VAL_MP_RUNTIME_ALLOC (0) +#endif +#endif + +#ifndef MYNEWT_VAL_MP_BLOCK_REUSED +#ifdef CONFIG_BT_NIMBLE_MEMPOOL_BLOCK_REUSED +#define MYNEWT_VAL_MP_BLOCK_REUSED (1) +#else +#define MYNEWT_VAL_MP_BLOCK_REUSED (0) +#endif +#endif + #endif diff --git a/components/bt/include/esp32c6/include/esp_bt.h b/components/bt/include/esp32c6/include/esp_bt.h index 7181be6e43e4..3ccdeb7cb730 100644 --- a/components/bt/include/esp32c6/include/esp_bt.h +++ b/components/bt/include/esp32c6/include/esp_bt.h @@ -156,7 +156,7 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type */ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle); -#define CONFIG_VERSION 0x20251022 +#define CONFIG_VERSION 0x20251104 #define CONFIG_MAGIC 0x5A5AA5A5 /** @@ -235,6 +235,7 @@ typedef struct { uint8_t adv_rsv_cnt; /*!< BLE adv state machine reserve count number */ uint8_t conn_rsv_cnt; /*!< BLE conn state machine reserve count number */ uint8_t priority_level_cfg; /*!< The option for priority level configuration */ + uint8_t slv_fst_rx_lat_en; /*!< The option for enabling slave fast PDU reception during latency. */ uint32_t config_magic; /*!< Magic number for configuration validation */ } esp_bt_controller_config_t; @@ -300,6 +301,7 @@ typedef struct { .adv_rsv_cnt = BLE_LL_ADV_SM_RESERVE_CNT_N, \ .conn_rsv_cnt = BLE_LL_CONN_SM_RESERVE_CNT_N, \ .priority_level_cfg = BT_LL_CTRL_PRIO_LVL_CFG, \ + .slv_fst_rx_lat_en = DEFAULT_BT_LE_CTRL_SLV_FAST_RX_CONN_DATA_EN, \ .config_magic = CONFIG_MAGIC, \ } #elif CONFIG_IDF_TARGET_ESP32C61 @@ -362,6 +364,7 @@ typedef struct { .adv_rsv_cnt = BLE_LL_ADV_SM_RESERVE_CNT_N, \ .conn_rsv_cnt = BLE_LL_CONN_SM_RESERVE_CNT_N, \ .priority_level_cfg = BT_LL_CTRL_PRIO_LVL_CFG, \ + .slv_fst_rx_lat_en = DEFAULT_BT_LE_CTRL_SLV_FAST_RX_CONN_DATA_EN, \ .config_magic = CONFIG_MAGIC, \ } #endif diff --git a/components/bt/include/esp32h2/include/esp_bt.h b/components/bt/include/esp32h2/include/esp_bt.h index b6bb5bfb23bd..a171b52a6b36 100644 --- a/components/bt/include/esp32h2/include/esp_bt.h +++ b/components/bt/include/esp32h2/include/esp_bt.h @@ -161,7 +161,7 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type */ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle); -#define CONFIG_VERSION 0x20251022 +#define CONFIG_VERSION 0x20251104 #define CONFIG_MAGIC 0x5A5AA5A5 /** @@ -237,6 +237,7 @@ typedef struct { uint8_t adv_rsv_cnt; /*!< BLE adv state machine reserve count number */ uint8_t conn_rsv_cnt; /*!< BLE conn state machine reserve count number */ uint8_t priority_level_cfg; /*!< The option for priority level configuration */ + uint8_t slv_fst_rx_lat_en; /*!< The option for enabling slave fast PDU reception during latency. */ uint32_t config_magic; /*!< Configuration magic value */ } esp_bt_controller_config_t; @@ -300,6 +301,7 @@ typedef struct { .adv_rsv_cnt = BLE_LL_ADV_SM_RESERVE_CNT_N, \ .conn_rsv_cnt = BLE_LL_CONN_SM_RESERVE_CNT_N, \ .priority_level_cfg = BT_LL_CTRL_PRIO_LVL_CFG, \ + .slv_fst_rx_lat_en = DEFAULT_BT_LE_CTRL_SLV_FAST_RX_CONN_DATA_EN, \ .config_magic = CONFIG_MAGIC, \ } diff --git a/components/esp-tls/Kconfig b/components/esp-tls/Kconfig index 1fa28008fdf3..aedd16846d18 100644 --- a/components/esp-tls/Kconfig +++ b/components/esp-tls/Kconfig @@ -25,7 +25,7 @@ menu "ESP-TLS" config ESP_TLS_USE_DS_PERIPHERAL bool "Use Digital Signature (DS) Peripheral with ESP-TLS" - depends on ESP_TLS_USING_MBEDTLS && SOC_DIG_SIGN_SUPPORTED + depends on ESP_TLS_USING_MBEDTLS && SOC_DIG_SIGN_SUPPORTED && MBEDTLS_PK_RSA_ALT_SUPPORT default y help Enable use of the Digital Signature Peripheral for ESP-TLS.The DS peripheral diff --git a/components/esp_coex/src/coexist.c b/components/esp_coex/src/coexist.c index 22d482c7e849..41b3db3f27a1 100644 --- a/components/esp_coex/src/coexist.c +++ b/components/esp_coex/src/coexist.c @@ -189,6 +189,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex { gpio_func_sel(gpio_pin.priority, PIN_FUNC_GPIO); gpio_set_direction(gpio_pin.priority, GPIO_MODE_INPUT); + gpio_set_pull_mode(gpio_pin.priority, GPIO_PULLDOWN_ONLY); esp_rom_gpio_connect_in_signal(gpio_pin.priority, EXTERNAL_COEX_SIGNAL_I1_IDX, false); REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.priority), GPIO_PIN1_SYNC1_BYPASS, 2); REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.priority), GPIO_PIN1_SYNC2_BYPASS, 2); @@ -206,6 +207,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex { gpio_func_sel(gpio_pin.request, PIN_FUNC_GPIO); gpio_set_direction(gpio_pin.request, GPIO_MODE_INPUT); + gpio_set_pull_mode(gpio_pin.request, GPIO_PULLDOWN_ONLY); esp_rom_gpio_connect_in_signal(gpio_pin.request, EXTERNAL_COEX_SIGNAL_I0_IDX, false); REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.request), GPIO_PIN1_SYNC1_BYPASS, 2); REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.request), GPIO_PIN1_SYNC2_BYPASS, 2); @@ -224,6 +226,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex { gpio_func_sel(gpio_pin.tx_line, PIN_FUNC_GPIO); gpio_set_direction(gpio_pin.tx_line, GPIO_MODE_INPUT); + gpio_set_pull_mode(gpio_pin.tx_line, GPIO_PULLDOWN_ONLY); esp_rom_gpio_connect_in_signal(gpio_pin.tx_line, EXTERNAL_COEX_SIGNAL_I1_IDX, false); REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.tx_line), GPIO_PIN1_SYNC1_BYPASS, 2); REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.tx_line), GPIO_PIN1_SYNC2_BYPASS, 2); @@ -241,6 +244,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex { gpio_func_sel(gpio_pin.grant, PIN_FUNC_GPIO); gpio_set_direction(gpio_pin.grant, GPIO_MODE_INPUT); + gpio_set_pull_mode(gpio_pin.grant, GPIO_PULLUP_ONLY); esp_rom_gpio_connect_in_signal(gpio_pin.grant, EXTERNAL_COEX_SIGNAL_I0_IDX, false); REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.grant), GPIO_PIN1_SYNC1_BYPASS, 2); REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.grant), GPIO_PIN1_SYNC2_BYPASS, 2); diff --git a/components/esp_driver_gpio/include/driver/gpio.h b/components/esp_driver_gpio/include/driver/gpio.h index 4d5d63b57c01..74bb88653931 100644 --- a/components/esp_driver_gpio/include/driver/gpio.h +++ b/components/esp_driver_gpio/include/driver/gpio.h @@ -385,23 +385,25 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *stren * signal or the IO MUX/GPIO configuration is modified (including input enable, output enable, output value, * function, and drive strength values). This function can be used to retain the state of GPIOs when the power * domain of where GPIO/IOMUX belongs to becomes off. For example, chip or system is reset (e.g. watchdog - * time-out, deep-sleep events are triggered), or peripheral power-down in light-sleep. + * time-out, Deep-sleep events are triggered), or peripheral power-down in Light-sleep. * * This function works in both input and output modes, and only applicable to output-capable GPIOs. * If this function is enabled: * in output mode: the output level of the GPIO will be locked and can not be changed. * in input mode: the input read value can still reflect the changes of the input signal. * + * Power down or call `gpio_hold_dis` will disable this function. + * * Please be aware that, * - * On ESP32P4, the states of IOs can not be hold after waking up from Deep-sleep. + * 1. USB pads cannot hold at low level after waking up from Deep-sleep. The USB related registers are reset, so the USB pull-up is back. + * + * 2. For ESP32-P4 rev < 3.0, the states of IOs can not be hold after waking up from Deep-sleep. * - * Additionally, on ESP32/S2/C3/S3/C2, this function cannot be used to hold the state of a digital GPIO during Deep-sleep. + * 3. For ESP32/S2/C3/S3/C2, this function cannot be used to hold the state of a digital GPIO during Deep-sleep. * Even if this function is enabled, the digital GPIO will be reset to its default state when the chip wakes up from * Deep-sleep. If you want to hold the state of a digital GPIO during Deep-sleep, please call `gpio_deep_sleep_hold_en`. * - * Power down or call `gpio_hold_dis` will disable this function. - * * @param gpio_num GPIO number, only support output-capable GPIOs * * @return @@ -429,7 +431,7 @@ esp_err_t gpio_hold_en(gpio_num_t gpio_num); */ esp_err_t gpio_hold_dis(gpio_num_t gpio_num); -#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP /** * @brief Enable all digital gpio pads hold function during Deep-sleep. * @@ -453,7 +455,7 @@ void gpio_deep_sleep_hold_en(void); * @brief Disable all digital gpio pads hold function during Deep-sleep. */ void gpio_deep_sleep_hold_dis(void); -#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP /** * @brief Set pad input to a peripheral signal through the IOMUX. diff --git a/components/esp_driver_gpio/src/gpio.c b/components/esp_driver_gpio/src/gpio.c index 83b7a1b04546..af1c6a62e996 100644 --- a/components/esp_driver_gpio/src/gpio.c +++ b/components/esp_driver_gpio/src/gpio.c @@ -8,13 +8,13 @@ #include "esp_err.h" #include "freertos/FreeRTOS.h" #include "esp_heap_caps.h" +#include "sdkconfig.h" #include "driver/gpio.h" #include "driver/rtc_io.h" #include "soc/interrupts.h" #if !CONFIG_FREERTOS_UNICORE #include "esp_ipc.h" #endif - #include "soc/soc_caps.h" #include "soc/gpio_periph.h" #include "esp_log.h" @@ -207,7 +207,8 @@ esp_err_t gpio_output_disable(gpio_num_t gpio_num) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); gpio_hal_output_disable(gpio_context.gpio_hal, gpio_num); - gpio_hal_set_output_enable_ctrl(gpio_context.gpio_hal, gpio_num, false, false); // so that output disable could take effect + gpio_hal_set_output_enable_ctrl(gpio_context.gpio_hal, gpio_num, false, false); // so that output disable could always take effect when func sel is GPIO + gpio_hal_func_sel(gpio_context.gpio_hal, gpio_num, PIN_FUNC_GPIO); // otherwise the oe can only be controlled by peripheral return ESP_OK; } @@ -216,6 +217,7 @@ esp_err_t gpio_output_enable(gpio_num_t gpio_num) GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO output gpio_num error", ESP_ERR_INVALID_ARG); gpio_hal_matrix_out_default(gpio_context.gpio_hal, gpio_num); // No peripheral output signal routed to the pin, just as a simple GPIO output gpio_hal_output_enable(gpio_context.gpio_hal, gpio_num); + gpio_hal_func_sel(gpio_context.gpio_hal, gpio_num, PIN_FUNC_GPIO); // otherwise the oe can only be controlled by peripheral return ESP_OK; } @@ -755,7 +757,7 @@ esp_err_t gpio_hold_dis(gpio_num_t gpio_num) return ret; } -#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP void gpio_deep_sleep_hold_en(void) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); @@ -769,7 +771,7 @@ void gpio_deep_sleep_hold_dis(void) gpio_hal_deep_sleep_hold_dis(gpio_context.gpio_hal); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); } -#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP #if SOC_GPIO_SUPPORT_FORCE_HOLD esp_err_t IRAM_ATTR gpio_force_hold_all() @@ -1052,9 +1054,10 @@ esp_err_t gpio_dump_io_configuration(FILE *out_stream, uint64_t io_bit_mask) #endif // When the IO is used as a simple GPIO output, oe signal can only be controlled by the oe register - // When the IO is not used as a simple GPIO output, oe signal could be controlled by the peripheral + // When the IO connects to a peripheral signal through GPIO Matrix, oe signal can be controlled by the peripheral or the oe register (switch by oe_ctrl_by_periph) + // When the IO connects to a peripheral signal through IOMUX, oe signal can only be controlled by the peripheral const char *oe_str = oe ? "1" : "0"; - if (sig_out != SIG_GPIO_OUT_IDX && oe_ctrl_by_periph) { + if (fun_sel != PIN_FUNC_GPIO || oe_ctrl_by_periph) { oe_str = "[periph_sig_ctrl]"; } diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c index d528c9bdd8f4..f816d04ebf48 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c @@ -879,7 +879,7 @@ TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]") } #endif -#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP +#if SOC_DEEP_SLEEP_SUPPORTED // Pick one digital IO for each target to test is enough static void gpio_deep_sleep_hold_test_first_stage(void) { @@ -897,7 +897,9 @@ static void gpio_deep_sleep_hold_test_first_stage(void) .pull_up_en = 0, }; TEST_ESP_OK(gpio_config(&io_conf)); - TEST_ESP_OK(gpio_set_level(io_num, 0)); + + const bool initial_level = gpio_get_level(io_num); + TEST_ESP_OK(gpio_set_level(io_num, !initial_level)); // Enable global persistence TEST_ESP_OK(gpio_hold_en(io_num)); @@ -906,6 +908,10 @@ static void gpio_deep_sleep_hold_test_first_stage(void) // Extra step is required, so that all digital IOs can automatically get held when entering Deep-sleep gpio_deep_sleep_hold_en(); #endif + vTaskDelay(pdMS_TO_TICKS(200)); + TEST_ESP_OK(gpio_set_level(io_num, initial_level)); + TEST_ASSERT_EQUAL_INT(!initial_level, gpio_get_level(io_num)); + vTaskDelay(pdMS_TO_TICKS(200)); esp_deep_sleep_start(); } @@ -916,16 +922,31 @@ static void gpio_deep_sleep_hold_test_second_stage(void) // Check reset reason is waking up from deepsleep TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason()); - // Pin should stay at low level after the deep sleep - TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num)); +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // DIG-399 + bool level = gpio_get_level(io_num); // Set level should not take effect since hold is still active (and the INPUT_OUTPUT mode should still be held) - TEST_ESP_OK(gpio_set_level(io_num, 1)); - TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num)); + TEST_ESP_OK(gpio_set_level(io_num, !level)); + TEST_ASSERT_EQUAL_INT(level, gpio_get_level(io_num)); +#endif #if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP gpio_deep_sleep_hold_dis(); #endif TEST_ESP_OK(gpio_hold_dis(io_num)); + + gpio_config_t io_conf = { + .intr_type = GPIO_INTR_DISABLE, + .mode = GPIO_MODE_INPUT_OUTPUT, + .pin_bit_mask = (1ULL << io_num), + .pull_down_en = GPIO_PULLDOWN_DISABLE, + .pull_up_en = GPIO_PULLUP_DISABLE, + }; + TEST_ESP_OK(gpio_config(&io_conf)); + +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // DIG-399 + // Check that the hold level after wakeup is the level before entering deep sleep + TEST_ASSERT_EQUAL_INT(!level, gpio_get_level(io_num)); +#endif } /* @@ -937,4 +958,4 @@ static void gpio_deep_sleep_hold_test_second_stage(void) TEST_CASE_MULTIPLE_STAGES("GPIO_deep_sleep_output_hold_test", "[gpio]", gpio_deep_sleep_hold_test_first_stage, gpio_deep_sleep_hold_test_second_stage) -#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP +#endif // SOC_DEEP_SLEEP_SUPPORTED diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h index 2000b19520d0..3caa9c2001f8 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h @@ -39,6 +39,7 @@ extern "C" { #define TEST_GPIO_EXT_IN_IO (3) #define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1) #define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC250_IDX) +#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (28) #elif CONFIG_IDF_TARGET_ESP32H2 #define TEST_GPIO_EXT_OUT_IO (2) #define TEST_GPIO_EXT_IN_IO (3) diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c index 180fa89643ff..8956720dca5a 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c @@ -235,7 +235,7 @@ TEST_CASE("RTCIO_output_hold_test", "[rtcio]") #endif //SOC_RTCIO_HOLD_SUPPORTED #endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED -#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP +#if SOC_DEEP_SLEEP_SUPPORTED // It is not necessary to test every rtcio pin, it will take too much ci testing time for deep sleep // Only tests on s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX] pin // The default configuration of these pads is low level @@ -268,8 +268,10 @@ static void rtcio_deep_sleep_hold_test_second_stage(void) int io_num = s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX]; // Check reset reason is waking up from deepsleep TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason()); +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // DIG-399 // Pin should stay at high level after the deep sleep TEST_ASSERT_EQUAL_INT(1, gpio_get_level(io_num)); +#endif gpio_hold_dis(io_num); } @@ -283,4 +285,4 @@ static void rtcio_deep_sleep_hold_test_second_stage(void) TEST_CASE_MULTIPLE_STAGES("RTCIO_deep_sleep_output_hold_test", "[rtcio]", rtcio_deep_sleep_hold_test_first_stage, rtcio_deep_sleep_hold_test_second_stage) -#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP +#endif // SOC_DEEP_SLEEP_SUPPORTED diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h index e3518e742812..a0f2869a14c9 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h @@ -146,6 +146,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = { GPIO_NUM_14, //GPIO14 GPIO_NUM_15, //GPIO15 }; +#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO5 #elif CONFIG_IDF_TARGET_ESP32C61 // Has no input-only rtcio pins, all pins support pull-up/down #define RTCIO_SUPPORT_PU_PD(num) 1 diff --git a/components/esp_driver_i2s/i2s_common.c b/components/esp_driver_i2s/i2s_common.c index 4f6f720dd2b9..a057a7eee367 100644 --- a/components/esp_driver_i2s/i2s_common.c +++ b/components/esp_driver_i2s/i2s_common.c @@ -370,6 +370,40 @@ static esp_err_t i2s_register_channel(i2s_controller_t *i2s_obj, i2s_dir_t dir, return ret; } +#if SOC_I2S_HW_VERSION_1 +esp_err_t i2s_channel_change_port(i2s_chan_handle_t handle, int id) +{ + I2S_NULL_POINTER_CHECK(TAG, handle); + ESP_RETURN_ON_FALSE(id >= 0 && id < SOC_I2S_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid I2S port id"); + if (id == handle->controller->id) { + return ESP_OK; + } + i2s_controller_t *i2s_obj = i2s_acquire_controller_obj(id); + if (!i2s_obj || !i2s_take_available_channel(i2s_obj, handle->dir)) { + return ESP_ERR_NOT_FOUND; + } + i2s_controller_t *old_i2s_obj = handle->controller; + portENTER_CRITICAL(&g_i2s.spinlock); + if (handle->dir == I2S_DIR_TX) { + i2s_obj->tx_chan = handle; + i2s_obj->chan_occupancy |= I2S_DIR_TX; + old_i2s_obj->tx_chan = NULL; + old_i2s_obj->full_duplex = false; + old_i2s_obj->chan_occupancy &= ~I2S_DIR_TX; + } else { + i2s_obj->rx_chan = handle; + i2s_obj->chan_occupancy |= I2S_DIR_RX; + old_i2s_obj->rx_chan = NULL; + old_i2s_obj->full_duplex = false; + old_i2s_obj->chan_occupancy &= ~I2S_DIR_RX; + } + handle->controller = i2s_obj; + portEXIT_CRITICAL(&g_i2s.spinlock); + + return ESP_OK; +} +#endif + #ifndef __cplusplus /* To make sure the i2s_event_callbacks_t is same size as i2s_event_callbacks_internal_t */ _Static_assert(sizeof(i2s_event_callbacks_t) == sizeof(i2s_event_callbacks_internal_t), "Invalid size of i2s_event_callbacks_t structure"); @@ -416,6 +450,9 @@ uint32_t i2s_get_buf_size(i2s_chan_handle_t handle, uint32_t data_bit_width, uin uint32_t bytes_per_sample = (data_bit_width + 7) / 8; #endif // CONFIG_IDF_TARGET_ESP32 uint32_t bytes_per_frame = bytes_per_sample * active_chan; + if (bytes_per_frame == 0) { + return 0; + } uint32_t bufsize = dma_frame_num * bytes_per_frame; #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE /* bufsize need to align with cache line size */ @@ -980,6 +1017,7 @@ esp_err_t i2s_new_channel(const i2s_chan_config_t *chan_cfg, i2s_chan_handle_t * ESP_GOTO_ON_ERROR(i2s_register_channel(i2s_obj, I2S_DIR_TX, chan_cfg->dma_desc_num), err, TAG, "register I2S tx channel failed"); i2s_obj->tx_chan->role = chan_cfg->role; + i2s_obj->tx_chan->is_port_auto = id == I2S_NUM_AUTO; i2s_obj->tx_chan->intr_prio_flags = chan_cfg->intr_priority ? BIT(chan_cfg->intr_priority) : ESP_INTR_FLAG_LOWMED; i2s_obj->tx_chan->dma.auto_clear_after_cb = chan_cfg->auto_clear_after_cb; i2s_obj->tx_chan->dma.auto_clear_before_cb = chan_cfg->auto_clear_before_cb; @@ -995,6 +1033,7 @@ esp_err_t i2s_new_channel(const i2s_chan_config_t *chan_cfg, i2s_chan_handle_t * ESP_GOTO_ON_ERROR(i2s_register_channel(i2s_obj, I2S_DIR_RX, chan_cfg->dma_desc_num), err, TAG, "register I2S rx channel failed"); i2s_obj->rx_chan->role = chan_cfg->role; + i2s_obj->rx_chan->is_port_auto = id == I2S_NUM_AUTO; i2s_obj->rx_chan->intr_prio_flags = chan_cfg->intr_priority ? BIT(chan_cfg->intr_priority) : ESP_INTR_FLAG_LOWMED; i2s_obj->rx_chan->dma.desc_num = chan_cfg->dma_desc_num; i2s_obj->rx_chan->dma.frame_num = chan_cfg->dma_frame_num; diff --git a/components/esp_driver_i2s/i2s_pdm.c b/components/esp_driver_i2s/i2s_pdm.c index 6a9f8f3cd506..d47a73256901 100644 --- a/components/esp_driver_i2s/i2s_pdm.c +++ b/components/esp_driver_i2s/i2s_pdm.c @@ -94,6 +94,7 @@ static esp_err_t i2s_pdm_tx_set_slot(i2s_chan_handle_t handle, const i2s_pdm_tx_ handle->active_slot = slot_cfg->slot_mode == I2S_SLOT_MODE_MONO ? 1 : 2; uint32_t buf_size = i2s_get_buf_size(handle, slot_cfg->data_bit_width, handle->dma.frame_num); + ESP_RETURN_ON_FALSE(buf_size != 0, ESP_ERR_INVALID_ARG, TAG, "invalid data_bit_width"); /* The DMA buffer need to re-allocate if the buffer size changed */ if (handle->dma.buf_size != buf_size) { ESP_RETURN_ON_ERROR(i2s_free_dma_desc(handle), TAG, "failed to free the old dma descriptor"); @@ -397,6 +398,7 @@ static esp_err_t i2s_pdm_rx_set_slot(i2s_chan_handle_t handle, const i2s_pdm_rx_ handle->active_slot = slot_cfg->slot_mode == I2S_SLOT_MODE_MONO ? 1 : 2; uint32_t buf_size = i2s_get_buf_size(handle, slot_cfg->data_bit_width, handle->dma.frame_num); + ESP_RETURN_ON_FALSE(buf_size != 0, ESP_ERR_INVALID_ARG, TAG, "invalid data_bit_width"); /* The DMA buffer need to re-allocate if the buffer size changed */ if (handle->dma.buf_size != buf_size) { ESP_RETURN_ON_ERROR(i2s_free_dma_desc(handle), TAG, "failed to free the old dma descriptor"); diff --git a/components/esp_driver_i2s/i2s_private.h b/components/esp_driver_i2s/i2s_private.h index a65bd2440d69..678113e5c42e 100644 --- a/components/esp_driver_i2s/i2s_private.h +++ b/components/esp_driver_i2s/i2s_private.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -159,6 +159,7 @@ struct i2s_channel_obj_t { /* Stored configurations */ int intr_prio_flags;/*!< i2s interrupt priority flags */ void *mode_info; /*!< Slot, clock and gpio information of each mode */ + bool is_port_auto; /*!< Whether the port is auto-assigned */ bool is_etm_start; /*!< Whether start by etm tasks */ bool is_etm_stop; /*!< Whether stop by etm tasks */ bool full_duplex_slave; /*!< whether the channel is forced to switch to slave role for full duplex */ @@ -333,6 +334,19 @@ void i2s_output_gpio_reserve(i2s_chan_handle_t handle, int gpio_num); */ void i2s_output_gpio_revoke(i2s_chan_handle_t handle, uint64_t gpio_mask); +#if SOC_I2S_HW_VERSION_1 +/** + * @brief Change the port of the I2S channel + * + * @param handle I2S channel handle + * @param id I2S port id + * @return + * - ESP_OK Change port success + * - ESP_ERR_NOT_FOUND No available I2S port found + */ +esp_err_t i2s_channel_change_port(i2s_chan_handle_t handle, int id); +#endif + #ifdef __cplusplus } #endif diff --git a/components/esp_driver_i2s/i2s_std.c b/components/esp_driver_i2s/i2s_std.c index 60b2f90ae5bf..dc6cf07af568 100644 --- a/components/esp_driver_i2s/i2s_std.c +++ b/components/esp_driver_i2s/i2s_std.c @@ -106,6 +106,7 @@ static esp_err_t i2s_std_set_slot(i2s_chan_handle_t handle, const i2s_std_slot_c handle->active_slot = slot_cfg->slot_mode == I2S_SLOT_MODE_MONO ? 1 : 2; uint32_t buf_size = i2s_get_buf_size(handle, slot_cfg->data_bit_width, handle->dma.frame_num); + ESP_RETURN_ON_FALSE(buf_size != 0, ESP_ERR_INVALID_ARG, TAG, "invalid data_bit_width"); /* The DMA buffer need to re-allocate if the buffer size changed */ if (handle->dma.buf_size != buf_size) { ESP_RETURN_ON_ERROR(i2s_free_dma_desc(handle), TAG, "failed to free the old dma descriptor"); @@ -237,13 +238,34 @@ static esp_err_t s_i2s_channel_try_to_constitude_std_duplex(i2s_chan_handle_t ha if (memcmp(another_handle->mode_info, &curr_cfg, sizeof(i2s_std_config_t)) == 0) { handle->controller->full_duplex = true; ESP_LOGD(TAG, "Constitude full-duplex on port %d", handle->controller->id); - } + } else { #if SOC_I2S_HW_VERSION_1 - else { - ESP_LOGE(TAG, "Can't set different channel configurations on a same port"); - return ESP_ERR_INVALID_ARG; - } + bool port_changed = false; + if (handle->is_port_auto) { + ESP_LOGD(TAG, "TX & RX on I2S%d are simplex", handle->controller->id); + for (int i = 0; i < SOC_I2S_NUM; i++) { + if (i == handle->controller->id) { + continue; + } + ESP_LOGD(TAG, "Trying to move %s channel from port %d to %d", + handle->dir == I2S_DIR_TX ? "TX" : "RX", handle->controller->id, i); + if (i2s_channel_change_port(handle, i) == ESP_OK) { + ESP_LOGD(TAG, "Move success!"); + port_changed = true; + break; + } else { + ESP_LOGD(TAG, "Move failed..."); + } + } + } + if (!port_changed) { + ESP_LOGE(TAG, "Can't set different channel configurations on a same port"); + return ESP_ERR_INVALID_ARG; + } +#else + ESP_LOGD(TAG, "TX & RX on I2S%d are simplex", handle->controller->id); #endif + } } /* Switch to the slave role if needed */ if (handle->controller->full_duplex && diff --git a/components/esp_driver_i2s/i2s_tdm.c b/components/esp_driver_i2s/i2s_tdm.c index d7d7fd351038..5bf73a3633b7 100644 --- a/components/esp_driver_i2s/i2s_tdm.c +++ b/components/esp_driver_i2s/i2s_tdm.c @@ -114,6 +114,7 @@ static esp_err_t i2s_tdm_set_slot(i2s_chan_handle_t handle, const i2s_tdm_slot_c "total slots(%"PRIu32") * slot_bit_width(%"PRIu32") exceeds the maximum %d", handle->total_slot, slot_bits, (int)I2S_LL_SLOT_FRAME_BIT_MAX); uint32_t buf_size = i2s_get_buf_size(handle, slot_cfg->data_bit_width, handle->dma.frame_num); + ESP_RETURN_ON_FALSE(buf_size != 0, ESP_ERR_INVALID_ARG, TAG, "invalid data_bit_width"); /* The DMA buffer need to re-allocate if the buffer size changed */ if (handle->dma.buf_size != buf_size) { ESP_RETURN_ON_ERROR(i2s_free_dma_desc(handle), TAG, "failed to free the old dma descriptor"); @@ -245,6 +246,8 @@ static void s_i2s_channel_try_to_constitude_tdm_duplex(i2s_chan_handle_t handle, if (memcmp(another_handle->mode_info, &curr_cfg, sizeof(i2s_tdm_config_t)) == 0) { handle->controller->full_duplex = true; ESP_LOGD(TAG, "Constitude full-duplex on port %d", handle->controller->id); + } else { + ESP_LOGD(TAG, "TX & RX on I2S%d are simplex", handle->controller->id); } } /* Switch to the slave role if needed */ diff --git a/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c b/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c index 2a2ba431be5b..043929ccbba8 100644 --- a/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c +++ b/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c @@ -238,6 +238,8 @@ TEST_CASE("I2S_basic_channel_allocation_reconfig_deleting_test", "[i2s]") } static volatile bool task_run_flag; +static volatile bool read_task_success = true; +static volatile bool write_task_success = true; #define TEST_I2S_DATA 0x78 @@ -270,6 +272,7 @@ static void i2s_read_task(void *args) ret = i2s_channel_read(rx_handle, recv_buf, 2000, &recv_size, 300); if (ret == ESP_ERR_TIMEOUT) { printf("Read timeout count: %"PRIu32"\n", cnt++); + read_task_success = false; } } @@ -291,6 +294,7 @@ static void i2s_write_task(void *args) ret = i2s_channel_write(tx_handle, send_buf, 2000, &send_size, 300); if (ret == ESP_ERR_TIMEOUT) { printf("Write timeout count: %"PRIu32"\n", cnt++); + write_task_success = false; } } @@ -431,6 +435,7 @@ TEST_CASE("I2S_lazy_duplex_test", "[i2s]") }, }, }; + /* Part 1: test common lazy duplex mode */ TEST_ESP_OK(i2s_new_channel(&chan_cfg, &tx_handle, NULL)); TEST_ESP_OK(i2s_channel_init_std_mode(tx_handle, &std_cfg)); TEST_ESP_OK(i2s_channel_enable(tx_handle)); @@ -451,7 +456,70 @@ TEST_CASE("I2S_lazy_duplex_test", "[i2s]") xTaskCreate(i2s_read_check_task, "i2s_read_check_task", 4096, rx_handle, 5, NULL); printf("RX started\n"); - /* Wait 3 seconds to see if any failures occur */ + /* Wait 1 seconds to see if any failures occur */ + vTaskDelay(pdMS_TO_TICKS(1000)); + printf("Finished\n"); + + /* Stop those three tasks */ + task_run_flag = false; + + /* Wait for the three thread deleted */ + vTaskDelay(pdMS_TO_TICKS(1000)); + + /* Disable the channels, they will keep waiting until the current reading / writing finished */ + TEST_ESP_OK(i2s_channel_disable(tx_handle)); + TEST_ESP_OK(i2s_channel_disable(rx_handle)); + /* Delete the channels */ + TEST_ESP_OK(i2s_del_channel(tx_handle)); + TEST_ESP_OK(i2s_del_channel(rx_handle)); + + /* Part 2: Test no lazy duplex mode with port auto assignment */ + chan_cfg.id = I2S_NUM_AUTO; + TEST_ESP_OK(i2s_new_channel(&chan_cfg, NULL, &rx_handle)); + TEST_ESP_OK(i2s_new_channel(&chan_cfg, &tx_handle, NULL)); + TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg)); + + /* Change the config to not constitute full-duplex */ + std_cfg.gpio_cfg.mclk = I2S_GPIO_UNUSED; + std_cfg.gpio_cfg.bclk = I2S_GPIO_UNUSED; + std_cfg.gpio_cfg.ws = I2S_GPIO_UNUSED; + std_cfg.gpio_cfg.dout = I2S_GPIO_UNUSED; + std_cfg.gpio_cfg.din = I2S_GPIO_UNUSED; +#if CONFIG_IDF_TARGET_ESP32S2 + TEST_ESP_ERR(ESP_ERR_INVALID_ARG, i2s_channel_init_std_mode(tx_handle, &std_cfg)); + /* Delete the channels */ + TEST_ESP_OK(i2s_del_channel(tx_handle)); + TEST_ESP_OK(i2s_del_channel(rx_handle)); + return; +#else + TEST_ESP_OK(i2s_channel_init_std_mode(tx_handle, &std_cfg)); +#endif + +#if CONFIG_IDF_TARGET_ESP32 + /* On ESP32, if failed to constitute full-duplex with `I2S_NUM_AUTO`, + the channel will be re-assigned to the next availableport */ + i2s_chan_info_t chan_info; + TEST_ESP_OK(i2s_channel_get_info(rx_handle, &chan_info)); + TEST_ASSERT(chan_info.id == I2S_NUM_0); + TEST_ESP_OK(i2s_channel_get_info(tx_handle, &chan_info)); + TEST_ASSERT(chan_info.id == I2S_NUM_1); +#endif + + TEST_ESP_OK(i2s_channel_enable(tx_handle)); + TEST_ESP_OK(i2s_channel_enable(rx_handle)); + + task_run_flag = true; + read_task_success = true; + write_task_success = true; + /* writing task to keep writing */ + xTaskCreate(i2s_write_task, "i2s_write_task", 4096, tx_handle, 5, NULL); + printf("TX started\n"); + vTaskDelay(pdMS_TO_TICKS(1000)); + /* reading task to keep reading */ + xTaskCreate(i2s_read_task, "i2s_read_task", 4096, rx_handle, 5, NULL); + printf("RX started\n"); + + /* Wait 1 seconds to see if any failures occur */ vTaskDelay(pdMS_TO_TICKS(1000)); printf("Finished\n"); @@ -467,6 +535,9 @@ TEST_CASE("I2S_lazy_duplex_test", "[i2s]") /* Delete the channels */ TEST_ESP_OK(i2s_del_channel(tx_handle)); TEST_ESP_OK(i2s_del_channel(rx_handle)); + /* Check if the reading and writing tasks are successful */ + TEST_ASSERT(read_task_success); + TEST_ASSERT(write_task_success); } static bool whether_contains_exapected_data(uint16_t *src, uint32_t src_len, uint32_t src_step, uint32_t start_val, uint32_t val_step) @@ -742,7 +813,7 @@ TEST_CASE("I2S_loopback_test", "[i2s]") TEST_ESP_OK(i2s_del_channel(rx_handle)); } -#if SOC_I2S_NUM > 1 && !CONFIG_IDF_TARGET_ESP32P4 +#if SOC_I2S_NUM > 1 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 TEST_CASE("I2S_master_write_slave_read_test", "[i2s]") { i2s_chan_handle_t tx_handle; diff --git a/components/esp_driver_isp/CMakeLists.txt b/components/esp_driver_isp/CMakeLists.txt index ab7761edb658..f20d5847b73e 100644 --- a/components/esp_driver_isp/CMakeLists.txt +++ b/components/esp_driver_isp/CMakeLists.txt @@ -22,6 +22,10 @@ if(CONFIG_SOC_ISP_BF_SUPPORTED) list(APPEND srcs "src/isp_bf.c") endif() +if(CONFIG_SOC_ISP_BLC_SUPPORTED) + list(APPEND srcs "src/isp_blc.c") +endif() + if(CONFIG_SOC_ISP_DEMOSAIC_SUPPORTED) list(APPEND srcs "src/isp_demosaic.c") endif() @@ -38,6 +42,10 @@ if(CONFIG_SOC_ISP_LSC_SUPPORTED) list(APPEND srcs "src/isp_lsc.c") endif() +if(CONFIG_SOC_ISP_WBG_SUPPORTED) + list(APPEND srcs "src/isp_wbg.c") +endif() + if(NOT ${target} STREQUAL "linux") list(APPEND requires esp_mm) endif() diff --git a/components/esp_driver_isp/include/driver/isp.h b/components/esp_driver_isp/include/driver/isp.h index 235aca350ef6..0bdd11d8db06 100644 --- a/components/esp_driver_isp/include/driver/isp.h +++ b/components/esp_driver_isp/include/driver/isp.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,10 +16,12 @@ #include "driver/isp_af.h" #include "driver/isp_awb.h" #include "driver/isp_bf.h" +#include "driver/isp_blc.h" #include "driver/isp_ccm.h" +#include "driver/isp_color.h" #include "driver/isp_demosaic.h" #include "driver/isp_gamma.h" #include "driver/isp_hist.h" -#include "driver/isp_sharpen.h" -#include "driver/isp_color.h" #include "driver/isp_lsc.h" +#include "driver/isp_sharpen.h" +#include "driver/isp_wbg.h" diff --git a/components/esp_driver_isp/include/driver/isp_awb.h b/components/esp_driver_isp/include/driver/isp_awb.h index 8fc03709fb94..4cd508cd1001 100644 --- a/components/esp_driver_isp/include/driver/isp_awb.h +++ b/components/esp_driver_isp/include/driver/isp_awb.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_driver_isp/include/driver/isp_blc.h b/components/esp_driver_isp/include/driver/isp_blc.h new file mode 100644 index 000000000000..d4a9bd8120a5 --- /dev/null +++ b/components/esp_driver_isp/include/driver/isp_blc.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_err.h" +#include "driver/isp_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*--------------------------------------------------------------- + BLC (Black Level Correction) +---------------------------------------------------------------*/ +/** + * @brief ISP BLC threshold configurations + */ +typedef struct { + uint8_t top_left_chan_thresh; ///< Black level threshold for top left channel of the raw Bayer image + uint8_t top_right_chan_thresh; ///< Black level threshold for top right channel of the raw Bayer image + uint8_t bottom_left_chan_thresh; ///< Black level threshold for bottom left channel of the raw Bayer image + uint8_t bottom_right_chan_thresh; ///< Black level threshold for bottom right channel of the raw Bayer image +} esp_isp_blc_thresh_t; + +/** + * @brief ISP BLC stretch configurations + * + * Enable this can stretch the pixel value to 0~255 after black level correction + */ +typedef struct { + bool top_left_chan_stretch_en; ///< Enable stretch for top left channel of the raw Bayer image + bool top_right_chan_stretch_en; ///< Enable stretch for top right channel of the raw Bayer image + bool bottom_left_chan_stretch_en; ///< Enable stretch for bottom left channel of the raw Bayer image + bool bottom_right_chan_stretch_en; ///< Enable stretch for bottom right channel of the raw Bayer image +} esp_isp_blc_stretch_t; + +/** + * @brief ISP BLC configurations + */ +typedef struct { + isp_window_t window; ///< The sampling windows of BLC, only pixels within the window will be sampled + esp_isp_blc_thresh_t filter_threshold; ///< Black level threshold for each channel of the raw Bayer image + bool filter_enable; ///< Enable filter for BLC, if enabled, only pixels within the threshold will be sampled + esp_isp_blc_stretch_t stretch; ///< Stretch configurations for each channel of the raw Bayer image +} esp_isp_blc_config_t; + +/** + * @brief ISP BLC correction offset + */ +typedef struct { + uint32_t top_left_chan_offset; ///< Correction offset for top left channel of the raw Bayer image + uint32_t top_right_chan_offset; ///< Correction offset for top right channel of the raw Bayer image + uint32_t bottom_left_chan_offset; ///< Correction offset for bottom left channel of the raw Bayer image + uint32_t bottom_right_chan_offset; ///< Correction offset for bottom right channel of the raw Bayer image +} esp_isp_blc_offset_t; + +/** + * @brief ISP BLC configuration + * + * @note After calling this API, BLC doesn't take into effect until `esp_isp_blc_enable` is called + * + * @param[in] isp_proc Processor handle + * @param[in] config BLC configurations + * + * @return + * - ESP_OK On success + * - ESP_ERR_INVALID_STATE Not allowed to be called under current state + * - ESP_ERR_INVALID_ARG If the combination of arguments is invalid + * - ESP_ERR_NOT_SUPPORTED Not supported + */ +esp_err_t esp_isp_blc_configure(isp_proc_handle_t isp_proc, const esp_isp_blc_config_t *config); + +/** + * @brief Enable ISP BLC function + * + * @param[in] isp_proc Processor handle + * + * @return + * - ESP_OK On success + * - ESP_ERR_INVALID_ARG If the combination of arguments is invalid. + * - ESP_ERR_INVALID_STATE Driver state is invalid. + */ +esp_err_t esp_isp_blc_enable(isp_proc_handle_t isp_proc); + +/** + * @brief Set the correction offset of ISP BLC function + * + * @param[in] isp_proc Processor handle + * @param[in] offset Correction offset + */ +esp_err_t esp_isp_blc_set_correction_offset(isp_proc_handle_t isp_proc, esp_isp_blc_offset_t *offset); + +/** + * @brief Disable ISP BLC function + * + * @param[in] isp_proc Processor handle + * + * @return + * - ESP_OK On success + * - ESP_ERR_INVALID_ARG If the combination of arguments is invalid. + * - ESP_ERR_INVALID_STATE Driver state is invalid. + */ +esp_err_t esp_isp_blc_disable(isp_proc_handle_t isp_proc); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_driver_isp/include/driver/isp_lsc.h b/components/esp_driver_isp/include/driver/isp_lsc.h index 68ef16595533..693145eaa88e 100644 --- a/components/esp_driver_isp/include/driver/isp_lsc.h +++ b/components/esp_driver_isp/include/driver/isp_lsc.h @@ -14,6 +14,10 @@ extern "C" { #endif +/*--------------------------------------------------------------- + LSC (Lens Shading Correction) +---------------------------------------------------------------*/ + /** * @brief LSC Gain array */ diff --git a/components/esp_driver_isp/include/driver/isp_types.h b/components/esp_driver_isp/include/driver/isp_types.h index a1ff94401451..3b3131d0f398 100644 --- a/components/esp_driver_isp/include/driver/isp_types.h +++ b/components/esp_driver_isp/include/driver/isp_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -39,14 +39,25 @@ typedef struct { int luminance[ISP_AF_WINDOW_NUM]; ///< Luminance, it refers how luminant an image is } isp_af_result_t; +/** + * @brief ISP AWB subwindow result + */ +typedef struct { + uint32_t white_patch_num[ISP_AWB_WINDOW_X_NUM][ISP_AWB_WINDOW_Y_NUM]; ///< white patch number that counted by AWB in the subwindow + uint32_t sum_r[ISP_AWB_WINDOW_X_NUM][ISP_AWB_WINDOW_Y_NUM]; ///< The sum of R channel of these white patches + uint32_t sum_g[ISP_AWB_WINDOW_X_NUM][ISP_AWB_WINDOW_Y_NUM]; ///< The sum of G channel of these white patches + uint32_t sum_b[ISP_AWB_WINDOW_X_NUM][ISP_AWB_WINDOW_Y_NUM]; ///< The sum of B channel of these white patches +} isp_awb_subwin_stat_result_t; + /** * @brief ISP AWB result */ typedef struct { - uint32_t white_patch_num; ///< white patch number that counted by AWB in the window - uint32_t sum_r; ///< The sum of R channel of these white patches - uint32_t sum_g; ///< The sum of G channel of these white patches - uint32_t sum_b; ///< The sum of B channel of these white patches + uint32_t white_patch_num; ///< white patch number that counted by AWB in the window + uint32_t sum_r; ///< The sum of R channel of these white patches + uint32_t sum_g; ///< The sum of G channel of these white patches + uint32_t sum_b; ///< The sum of B channel of these white patches + isp_awb_subwin_stat_result_t subwin_result; ///< The AWB subwindow statistics result } isp_awb_stat_result_t; /** diff --git a/components/esp_driver_isp/include/driver/isp_wbg.h b/components/esp_driver_isp/include/driver/isp_wbg.h new file mode 100644 index 000000000000..b8add5cd50f3 --- /dev/null +++ b/components/esp_driver_isp/include/driver/isp_wbg.h @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_err.h" +#include "driver/isp_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*--------------------------------------------------------------- + WBG (White Balance Gain) +---------------------------------------------------------------*/ +/** + * @brief ISP BLC configurations + */ +typedef struct { + //for future proof +} esp_isp_wbg_config_t; + +/** + * @brief ISP WBG configuration + * + * @note After calling this API, WBG doesn't take into effect until `esp_isp_wbg_enable` is called + * + * @param[in] isp_proc Processor handle + * @param[in] config WBG configurations + * + * @return + * - ESP_OK On success + * - ESP_ERR_INVALID_STATE Not allowed to be called under current state + * - ESP_ERR_INVALID_ARG If the combination of arguments is invalid + * - ESP_ERR_NOT_SUPPORTED Not supported + */ +esp_err_t esp_isp_wbg_configure(isp_proc_handle_t isp_proc, const esp_isp_wbg_config_t *config); + +/** + * @brief Enable ISP WBG function + * + * @param[in] isp_proc Processor handle + * + * @return + * - ESP_OK On success + * - ESP_ERR_INVALID_ARG If the combination of arguments is invalid. + * - ESP_ERR_INVALID_STATE Driver state is invalid. + */ +esp_err_t esp_isp_wbg_enable(isp_proc_handle_t isp_proc); + +/** + * @brief Set AWB white balance gain + * + * @param[in] isp_proc Processor handle + * @param[in] gain WBG white balance gain + * @return + * - ESP_OK On success + * - ESP_ERR_INVALID_ARG Null pointer + * - ESP_ERR_INVALID_STATE Driver state is invalid. + */ +esp_err_t esp_isp_wbg_set_wb_gain(isp_proc_handle_t isp_proc, isp_wbg_gain_t gain); + +/** + * @brief Disable ISP WBG function + * + * @param[in] isp_proc Processor handle + * + * @return + * - ESP_OK On success + * - ESP_ERR_INVALID_ARG If the combination of arguments is invalid. + * - ESP_ERR_INVALID_STATE Driver state is invalid. + */ +esp_err_t esp_isp_wbg_disable(isp_proc_handle_t isp_proc); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_driver_isp/include/esp_private/isp_private.h b/components/esp_driver_isp/include/esp_private/isp_private.h index a0e6913ca59e..4576e3bd4dce 100644 --- a/components/esp_driver_isp/include/esp_private/isp_private.h +++ b/components/esp_driver_isp/include/esp_private/isp_private.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,7 @@ #include #include #include +#include #include "sdkconfig.h" #include "esp_attr.h" #include "esp_log.h" @@ -27,8 +28,12 @@ #include "soc/isp_periph.h" #endif +// Helper macros for atomic operations to ensure Clang compatibility #ifdef __cplusplus -extern "C" { +#include +#define ISP_ATOMIC_TYPE(T) std::atomic +#else +#define ISP_ATOMIC_TYPE(T) _Atomic T #endif #if CONFIG_ISP_ISR_IRAM_SAFE || CONFIG_ISP_CTRL_FUNC_IN_IRAM @@ -39,6 +44,10 @@ extern "C" { #define ISP_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT #endif +#ifdef __cplusplus +extern "C" { +#endif + typedef enum { ISP_FSM_INIT, // Controller is initialized, but not enabled ISP_FSM_ENABLE, // Controller is enabled, but is not running @@ -58,7 +67,7 @@ typedef struct isp_processor_t { int csi_brg_id; void *csi_brg_hw; #endif - isp_fsm_t isp_fsm; + ISP_ATOMIC_TYPE(isp_fsm_t) isp_fsm; portMUX_TYPE spinlock; color_space_pixel_format_t in_color_format; color_space_pixel_format_t out_color_format; @@ -70,11 +79,15 @@ typedef struct isp_processor_t { isp_awb_ctlr_t awb_ctlr; isp_ae_ctlr_t ae_ctlr; isp_hist_ctlr_t hist_ctlr; - isp_fsm_t bf_fsm; - isp_fsm_t demosaic_fsm; - isp_fsm_t sharpen_fsm; - isp_fsm_t color_fsm; - isp_fsm_t lsc_fsm; + ISP_ATOMIC_TYPE(isp_fsm_t) bf_fsm; + ISP_ATOMIC_TYPE(isp_fsm_t) blc_fsm; + ISP_ATOMIC_TYPE(isp_fsm_t) ccm_fsm; + ISP_ATOMIC_TYPE(isp_fsm_t) color_fsm; + ISP_ATOMIC_TYPE(isp_fsm_t) demosaic_fsm; + ISP_ATOMIC_TYPE(isp_fsm_t) gamma_fsm; + ISP_ATOMIC_TYPE(isp_fsm_t) lsc_fsm; + ISP_ATOMIC_TYPE(isp_fsm_t) sharpen_fsm; + ISP_ATOMIC_TYPE(isp_fsm_t) wbg_fsm; esp_isp_evt_cbs_t cbs; void *user_data; diff --git a/components/esp_driver_isp/src/isp_ae.c b/components/esp_driver_isp/src/isp_ae.c index f6d421b45014..2ef283ed1a2e 100644 --- a/components/esp_driver_isp/src/isp_ae.c +++ b/components/esp_driver_isp/src/isp_ae.c @@ -101,6 +101,7 @@ esp_err_t esp_isp_new_ae_controller(isp_proc_handle_t isp_proc, const esp_isp_ae ESP_GOTO_ON_ERROR(intr_priority != isp_proc->intr_priority, err2, TAG, "intr_priority error"); ESP_GOTO_ON_ERROR(esp_isp_register_isr(ae_ctlr->isp_proc, ISP_SUBMODULE_AE), err2, TAG, "fail to register ISR"); + isp_ll_ae_set_clk_ctrl_mode(isp_proc->hal.hw, ISP_LL_PIPELINE_CLK_CTRL_AUTO); isp_ll_ae_set_sample_point(isp_proc->hal.hw, ae_config->sample_point); isp_ll_ae_enable(isp_proc->hal.hw, false); isp_hal_ae_window_config(&isp_proc->hal, &ae_config->window); @@ -141,7 +142,6 @@ esp_err_t esp_isp_ae_controller_enable(isp_ae_ctlr_t ae_ctlr) ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&ae_ctlr->fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "controller not in init state"); - isp_ll_ae_clk_enable(ae_ctlr->isp_proc->hal.hw, true); isp_ll_enable_intr(ae_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_AE_MASK, true); isp_ll_ae_enable(ae_ctlr->isp_proc->hal.hw, true); @@ -155,7 +155,6 @@ esp_err_t esp_isp_ae_controller_disable(isp_ae_ctlr_t ae_ctlr) ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&ae_ctlr->fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "controller not in enable state"); - isp_ll_ae_clk_enable(ae_ctlr->isp_proc->hal.hw, false); isp_ll_enable_intr(ae_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_AE_MASK, false); isp_ll_ae_enable(ae_ctlr->isp_proc->hal.hw, false); esp_intr_disable(ae_ctlr->intr_handle); diff --git a/components/esp_driver_isp/src/isp_af.c b/components/esp_driver_isp/src/isp_af.c index 28c2055328d0..b64fbf326678 100644 --- a/components/esp_driver_isp/src/isp_af.c +++ b/components/esp_driver_isp/src/isp_af.c @@ -127,6 +127,7 @@ esp_err_t esp_isp_new_af_controller(isp_proc_handle_t isp_proc, const esp_isp_af isp_ll_af_set_edge_thresh_mode(isp_proc->hal.hw, ISP_LL_AF_EDGE_DETECTOR_MODE_MANUAL); isp_ll_af_set_edge_thresh(isp_proc->hal.hw, af_config->edge_thresh); isp_ll_clear_intr(isp_proc->hal.hw, ISP_LL_EVENT_AF_MASK); + isp_ll_af_set_clk_ctrl_mode(isp_proc->hal.hw, ISP_LL_PIPELINE_CLK_CTRL_AUTO); *ret_hdl = af_ctlr; @@ -168,7 +169,6 @@ esp_err_t esp_isp_af_controller_enable(isp_af_ctlr_t af_ctlr) ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&af_ctlr->fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "controller not in init state"); - isp_ll_af_clk_enable(af_ctlr->isp_proc->hal.hw, true); isp_ll_enable_intr(af_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_AF_MASK, true); isp_ll_af_enable(af_ctlr->isp_proc->hal.hw, true); @@ -182,7 +182,6 @@ esp_err_t esp_isp_af_controller_disable(isp_af_ctlr_t af_ctlr) ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&af_ctlr->fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "controller not in enable state"); - isp_ll_af_clk_enable(af_ctlr->isp_proc->hal.hw, false); isp_ll_enable_intr(af_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_AF_MASK, false); isp_ll_af_enable(af_ctlr->isp_proc->hal.hw, false); esp_intr_disable(af_ctlr->intr_handle); diff --git a/components/esp_driver_isp/src/isp_awb.c b/components/esp_driver_isp/src/isp_awb.c index eb8abbb7d73f..28ab0393bb8c 100644 --- a/components/esp_driver_isp/src/isp_awb.c +++ b/components/esp_driver_isp/src/isp_awb.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -109,6 +109,7 @@ esp_err_t esp_isp_new_awb_controller(isp_proc_handle_t isp_proc, const esp_isp_a // Configure the hardware isp_ll_awb_enable(isp_proc->hal.hw, false); + isp_ll_awb_set_clk_ctrl_mode(isp_proc->hal.hw, ISP_LL_PIPELINE_CLK_CTRL_AUTO); isp_ll_awb_enable_algorithm_mode(isp_proc->hal.hw, true); ESP_GOTO_ON_ERROR(s_esp_isp_awb_config_hardware(isp_proc, awb_cfg), err2, TAG, "configure awb hardware failed"); @@ -155,7 +156,6 @@ esp_err_t esp_isp_awb_controller_enable(isp_awb_ctlr_t awb_ctlr) ESP_ERR_INVALID_STATE, TAG, "controller not in init state"); esp_err_t ret = ESP_OK; - isp_ll_awb_clk_enable(awb_ctlr->isp_proc->hal.hw, true); isp_ll_enable_intr(awb_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_AWB_MASK, true); return ret; @@ -169,7 +169,6 @@ esp_err_t esp_isp_awb_controller_disable(isp_awb_ctlr_t awb_ctlr) ESP_ERR_INVALID_STATE, TAG, "controller not in enable state"); isp_ll_enable_intr(awb_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_AWB_MASK, false); - isp_ll_awb_clk_enable(awb_ctlr->isp_proc->hal.hw, false); esp_intr_disable(awb_ctlr->intr_handle); return ESP_OK; @@ -240,6 +239,26 @@ bool IRAM_ATTR esp_isp_awb_isr(isp_proc_handle_t proc, uint32_t awb_events) .sum_b = isp_ll_awb_get_accumulated_b_value(proc->hal.hw), }, }; + + // Get subwindow statistics + for (int x = 0; x < ISP_AWB_WINDOW_X_NUM; x++) { + for (int y = 0; y < ISP_AWB_WINDOW_Y_NUM; y++) { + int subwindow_id = x * ISP_AWB_WINDOW_Y_NUM + y; + + isp_ll_lut_awb_set_cmd(proc->hal.hw, ISP_LL_LUT_AWB_WHITE_PATCH_CNT, subwindow_id, ISP_LL_LUT_AWB); + edata.awb_result.subwin_result.white_patch_num[x][y] = isp_ll_lut_awb_get_subwindow_white_patch_cnt(proc->hal.hw); + + isp_ll_lut_awb_set_cmd(proc->hal.hw, ISP_LL_LUT_AWB_ACCUMULATED_R, subwindow_id, ISP_LL_LUT_AWB); + edata.awb_result.subwin_result.sum_r[x][y] = isp_ll_lut_awb_get_subwindow_accumulated_r(proc->hal.hw); + + isp_ll_lut_awb_set_cmd(proc->hal.hw, ISP_LL_LUT_AWB_ACCUMULATED_G, subwindow_id, ISP_LL_LUT_AWB); + edata.awb_result.subwin_result.sum_g[x][y] = isp_ll_lut_awb_get_subwindow_accumulated_g(proc->hal.hw); + + isp_ll_lut_awb_set_cmd(proc->hal.hw, ISP_LL_LUT_AWB_ACCUMULATED_B, subwindow_id, ISP_LL_LUT_AWB); + edata.awb_result.subwin_result.sum_b[x][y] = isp_ll_lut_awb_get_subwindow_accumulated_b(proc->hal.hw); + } + } + // Invoke the callback if the callback is registered if (awb_ctlr->cbs.on_statistics_done) { need_yield |= awb_ctlr->cbs.on_statistics_done(awb_ctlr, &edata, awb_ctlr->user_data); diff --git a/components/esp_driver_isp/src/isp_bf.c b/components/esp_driver_isp/src/isp_bf.c index 0d673c534ba5..1c71d0eefd0c 100644 --- a/components/esp_driver_isp/src/isp_bf.c +++ b/components/esp_driver_isp/src/isp_bf.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -24,7 +24,6 @@ static const char *TAG = "ISP_BF"; esp_err_t esp_isp_bf_configure(isp_proc_handle_t proc, const esp_isp_bf_config_t *config) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(proc->bf_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "bf is enabled already"); if (config) { bool valid_padding_setting = (!config->padding_line_tail_valid_end_pixel && !config->padding_line_tail_valid_start_pixel) || (config->padding_line_tail_valid_end_pixel > config->padding_line_tail_valid_start_pixel); @@ -39,21 +38,24 @@ esp_err_t esp_isp_bf_configure(isp_proc_handle_t proc, const esp_isp_bf_config_t }; memcpy(bf_hal_cfg.bf_template, config->bf_template, ISP_BF_TEMPLATE_X_NUMS * ISP_BF_TEMPLATE_X_NUMS * sizeof(uint8_t)); isp_hal_bf_config(&(proc->hal), &bf_hal_cfg); + isp_ll_bf_set_clk_ctrl_mode(proc->hal.hw, ISP_LL_PIPELINE_CLK_CTRL_AUTO); } else { isp_hal_bf_config(&(proc->hal), NULL); } + bool valid = isp_ll_shadow_update_bf(proc->hal.hw); + ESP_RETURN_ON_FALSE_ISR(valid, ESP_ERR_INVALID_STATE, TAG, "failed to update bf shadow register"); + return ESP_OK; } esp_err_t esp_isp_bf_enable(isp_proc_handle_t proc) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(proc->bf_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "bf is enabled already"); + isp_fsm_t expected_fsm = ISP_FSM_INIT; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->bf_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "bf is enabled already"); - isp_ll_bf_clk_enable(proc->hal.hw, true); isp_ll_bf_enable(proc->hal.hw, true); - proc->bf_fsm = ISP_FSM_ENABLE; return ESP_OK; } @@ -61,11 +63,10 @@ esp_err_t esp_isp_bf_enable(isp_proc_handle_t proc) esp_err_t esp_isp_bf_disable(isp_proc_handle_t proc) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(proc->bf_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "bf isn't enabled yet"); + isp_fsm_t expected_fsm = ISP_FSM_ENABLE; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->bf_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "bf isn't enabled yet"); isp_ll_bf_enable(proc->hal.hw, false); - isp_ll_bf_clk_enable(proc->hal.hw, false); - proc->bf_fsm = ISP_FSM_INIT; return ESP_OK; } diff --git a/components/esp_driver_isp/src/isp_blc.c b/components/esp_driver_isp/src/isp_blc.c new file mode 100644 index 000000000000..f8faa2774bcf --- /dev/null +++ b/components/esp_driver_isp/src/isp_blc.c @@ -0,0 +1,106 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include "sdkconfig.h" +#include "esp_log.h" +#include "esp_check.h" +#include "freertos/FreeRTOS.h" +#include "driver/isp_core.h" +#include "driver/isp_blc.h" +#include "esp_private/isp_private.h" +#include "hal/efuse_hal.h" +#include "soc/chip_revision.h" + +/*--------------------------------------------------------------- + BLC +---------------------------------------------------------------*/ + +static const char *TAG = "ISP_BLC"; + +esp_err_t esp_isp_blc_configure(isp_proc_handle_t isp_proc, const esp_isp_blc_config_t *config) +{ +#if CONFIG_IDF_TARGET_ESP32P4 + unsigned chip_version = efuse_hal_chip_revision(); + if (!ESP_CHIP_REV_ABOVE(chip_version, 300)) { + ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "BLC is not supported on ESP32P4 chips prior than v3.0"); + } +#endif + + ESP_RETURN_ON_FALSE(isp_proc && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE(isp_proc->blc_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "blc is enabled already"); + ESP_RETURN_ON_FALSE(config->window.top_left.x < config->window.btm_right.x, ESP_ERR_INVALID_ARG, TAG, "invalid window x coordinates"); + ESP_RETURN_ON_FALSE(config->window.top_left.y < config->window.btm_right.y, ESP_ERR_INVALID_ARG, TAG, "invalid window y coordinates"); + ESP_RETURN_ON_FALSE(config->window.btm_right.x <= isp_proc->h_res, ESP_ERR_INVALID_ARG, TAG, "window exceeds horizontal resolution"); + ESP_RETURN_ON_FALSE(config->window.btm_right.y <= isp_proc->v_res, ESP_ERR_INVALID_ARG, TAG, "window exceeds vertical resolution"); + + // Configure clock control mode + isp_ll_blc_set_clk_ctrl_mode(isp_proc->hal.hw, ISP_LL_PIPELINE_CLK_CTRL_AUTO); + + // Configure sampling window + isp_ll_blc_set_window(isp_proc->hal.hw, + config->window.top_left.x, config->window.top_left.y, + config->window.btm_right.x, config->window.btm_right.y); + + if (config->filter_enable) { + // Configure threshold values for each channel + isp_ll_blc_set_filter_threshold(isp_proc->hal.hw, config->filter_threshold.top_left_chan_thresh, config->filter_threshold.top_right_chan_thresh, config->filter_threshold.bottom_left_chan_thresh, config->filter_threshold.bottom_right_chan_thresh); + isp_ll_blc_enable_filter(isp_proc->hal.hw, true); + } else { + isp_ll_blc_enable_filter(isp_proc->hal.hw, false); + } + + // Configure stretch enable for each channel + isp_ll_blc_enable_stretch(isp_proc->hal.hw, config->stretch.top_left_chan_stretch_en, config->stretch.top_right_chan_stretch_en, config->stretch.bottom_left_chan_stretch_en, config->stretch.bottom_right_chan_stretch_en); + + bool valid = isp_ll_shadow_update_blc(isp_proc->hal.hw); + ESP_RETURN_ON_FALSE_ISR(valid, ESP_ERR_INVALID_STATE, TAG, "failed to update blc shadow register"); + + return ESP_OK; +} + +esp_err_t esp_isp_blc_enable(isp_proc_handle_t isp_proc) +{ + ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + isp_fsm_t expected_fsm = ISP_FSM_INIT; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&isp_proc->blc_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "blc is enabled already"); + + // Enable BLC module + isp_ll_blc_enable(isp_proc->hal.hw, true); + + ESP_LOGD(TAG, "BLC enabled"); + return ESP_OK; +} + +esp_err_t esp_isp_blc_set_correction_offset(isp_proc_handle_t isp_proc, esp_isp_blc_offset_t *offset) +{ + ESP_RETURN_ON_FALSE(isp_proc && offset, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE(atomic_load(&isp_proc->blc_fsm) == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "blc isn't enabled yet"); + + // Set correction offset for each channel + isp_ll_blc_set_correction_offset(isp_proc->hal.hw, offset->top_left_chan_offset, offset->top_right_chan_offset, offset->bottom_left_chan_offset, offset->bottom_right_chan_offset); + + ESP_LOGD(TAG, "BLC correction offset set: TL=%"PRIu32", TR=%"PRIu32", BL=%"PRIu32", BR=%"PRIu32, + offset->top_left_chan_offset, offset->top_right_chan_offset, + offset->bottom_left_chan_offset, offset->bottom_right_chan_offset); + + return ESP_OK; +} + +esp_err_t esp_isp_blc_disable(isp_proc_handle_t isp_proc) +{ + ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + isp_fsm_t expected_fsm = ISP_FSM_ENABLE; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&isp_proc->blc_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "blc isn't enabled yet"); + + // Disable BLC module + isp_ll_blc_enable(isp_proc->hal.hw, false); + + ESP_LOGD(TAG, "BLC disabled"); + return ESP_OK; +} diff --git a/components/esp_driver_isp/src/isp_ccm.c b/components/esp_driver_isp/src/isp_ccm.c index 5fb45984884e..4168a1ad52e6 100644 --- a/components/esp_driver_isp/src/isp_ccm.c +++ b/components/esp_driver_isp/src/isp_ccm.c @@ -22,10 +22,14 @@ esp_err_t esp_isp_ccm_configure(isp_proc_handle_t proc, const esp_isp_ccm_config ESP_RETURN_ON_FALSE(proc && ccm_cfg, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); bool ret = true; + bool valid = false; portENTER_CRITICAL(&proc->spinlock); + isp_ll_ccm_set_clk_ctrl_mode(proc->hal.hw, ISP_LL_PIPELINE_CLK_CTRL_AUTO); ret = isp_hal_ccm_set_matrix(&proc->hal, ccm_cfg->saturation, ccm_cfg->matrix); + valid = isp_ll_shadow_update_ccm(proc->hal.hw); portEXIT_CRITICAL(&proc->spinlock); ESP_RETURN_ON_FALSE(ret, ESP_ERR_INVALID_ARG, TAG, "invalid argument: ccm matrix contain NaN or out of range"); + ESP_RETURN_ON_FALSE(valid, ESP_ERR_INVALID_STATE, TAG, "failed to update ccm shadow register"); return ESP_OK; } @@ -33,9 +37,10 @@ esp_err_t esp_isp_ccm_configure(isp_proc_handle_t proc, const esp_isp_ccm_config esp_err_t esp_isp_ccm_enable(isp_proc_handle_t proc) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + isp_fsm_t expected_fsm = ISP_FSM_INIT; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->ccm_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "ccm is enabled already"); portENTER_CRITICAL(&proc->spinlock); - isp_ll_ccm_clk_enable(proc->hal.hw, true); isp_ll_ccm_enable(proc->hal.hw, true); portEXIT_CRITICAL(&proc->spinlock); @@ -45,10 +50,11 @@ esp_err_t esp_isp_ccm_enable(isp_proc_handle_t proc) esp_err_t esp_isp_ccm_disable(isp_proc_handle_t proc) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + isp_fsm_t expected_fsm = ISP_FSM_ENABLE; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->ccm_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "ccm isn't enabled yet"); portENTER_CRITICAL(&proc->spinlock); isp_ll_ccm_enable(proc->hal.hw, false); - isp_ll_ccm_clk_enable(proc->hal.hw, false); portEXIT_CRITICAL(&proc->spinlock); return ESP_OK; diff --git a/components/esp_driver_isp/src/isp_color.c b/components/esp_driver_isp/src/isp_color.c index 09e118c62685..c3da6d5cdc13 100644 --- a/components/esp_driver_isp/src/isp_color.c +++ b/components/esp_driver_isp/src/isp_color.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -38,21 +38,24 @@ esp_err_t esp_isp_color_configure(isp_proc_handle_t proc, const esp_isp_color_co .color_brightness = config->color_brightness, }; isp_hal_color_config(&(proc->hal), &color_hal_cfg); + isp_ll_color_set_clk_ctrl_mode(proc->hal.hw, ISP_LL_PIPELINE_CLK_CTRL_AUTO); } else { isp_hal_color_config(&(proc->hal), NULL); } + bool valid = isp_ll_shadow_update_color(proc->hal.hw); + ESP_RETURN_ON_FALSE_ISR(valid, ESP_ERR_INVALID_STATE, TAG, "failed to update color shadow register"); + return ESP_OK; } esp_err_t esp_isp_color_enable(isp_proc_handle_t proc) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(proc->color_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "color is enabled already"); + isp_fsm_t expected_fsm = ISP_FSM_INIT; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->color_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "color is enabled already"); - isp_ll_color_clk_enable(proc->hal.hw, true); isp_ll_color_enable(proc->hal.hw, true); - proc->color_fsm = ISP_FSM_ENABLE; return ESP_OK; } @@ -60,11 +63,10 @@ esp_err_t esp_isp_color_enable(isp_proc_handle_t proc) esp_err_t esp_isp_color_disable(isp_proc_handle_t proc) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(proc->color_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "color isn't enabled yet"); + isp_fsm_t expected_fsm = ISP_FSM_ENABLE; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->color_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "color isn't enabled yet"); isp_ll_color_enable(proc->hal.hw, false); - isp_ll_color_clk_enable(proc->hal.hw, false); - proc->color_fsm = ISP_FSM_INIT; return ESP_OK; } diff --git a/components/esp_driver_isp/src/isp_core.c b/components/esp_driver_isp/src/isp_core.c index 89fe6d79f1da..ab7af6f7da76 100644 --- a/components/esp_driver_isp/src/isp_core.c +++ b/components/esp_driver_isp/src/isp_core.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -114,7 +114,16 @@ esp_err_t esp_isp_new_processor(const esp_isp_processor_cfg_t *proc_config, isp_ isp_ll_set_clock_div(proc->hal.hw, &clk_div); } - proc->isp_fsm = ISP_FSM_INIT; + atomic_init(&proc->isp_fsm, ISP_FSM_INIT); + atomic_init(&proc->bf_fsm, ISP_FSM_INIT); + atomic_init(&proc->blc_fsm, ISP_FSM_INIT); + atomic_init(&proc->ccm_fsm, ISP_FSM_INIT); + atomic_init(&proc->color_fsm, ISP_FSM_INIT); + atomic_init(&proc->demosaic_fsm, ISP_FSM_INIT); + atomic_init(&proc->gamma_fsm, ISP_FSM_INIT); + atomic_init(&proc->lsc_fsm, ISP_FSM_INIT); + atomic_init(&proc->sharpen_fsm, ISP_FSM_INIT); + atomic_init(&proc->wbg_fsm, ISP_FSM_INIT); proc->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; //Input color format @@ -149,6 +158,8 @@ esp_err_t esp_isp_new_processor(const esp_isp_processor_cfg_t *proc_config, isp_ isp_ll_color_enable(proc->hal.hw, true); // workaround for DIG-474 } + isp_ll_shadow_set_mode(proc->hal.hw, ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC); + proc->in_color_format = in_color_format; proc->out_color_format = out_color_format; proc->h_res = proc_config->h_res; @@ -168,7 +179,7 @@ esp_err_t esp_isp_new_processor(const esp_isp_processor_cfg_t *proc_config, isp_ esp_err_t esp_isp_del_processor(isp_proc_handle_t proc) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(proc->isp_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "processor isn't in init state"); + ESP_RETURN_ON_FALSE(atomic_load(&proc->isp_fsm) == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "processor isn't in init state"); //declaim first, then do free ESP_RETURN_ON_ERROR(s_isp_declaim_processor(proc), TAG, "declaim processor fail"); @@ -183,7 +194,7 @@ esp_err_t esp_isp_del_processor(isp_proc_handle_t proc) esp_err_t esp_isp_register_event_callbacks(isp_proc_handle_t proc, const esp_isp_evt_cbs_t *cbs, void *user_data) { ESP_RETURN_ON_FALSE(proc && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - ESP_RETURN_ON_FALSE(proc->isp_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "processor isn't in the init state"); + ESP_RETURN_ON_FALSE(atomic_load(&proc->isp_fsm) == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "processor isn't in the init state"); #if CONFIG_ISP_ISR_IRAM_SAFE if (cbs->on_sharpen_frame_done) { @@ -208,10 +219,10 @@ esp_err_t esp_isp_register_event_callbacks(isp_proc_handle_t proc, const esp_isp esp_err_t esp_isp_enable(isp_proc_handle_t proc) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(proc->isp_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "processor isn't in init state"); + isp_fsm_t expected_fsm = ISP_FSM_INIT; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->isp_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "processor isn't in init state"); isp_ll_enable(proc->hal.hw, true); - proc->isp_fsm = ISP_FSM_ENABLE; return ESP_OK; } @@ -219,10 +230,10 @@ esp_err_t esp_isp_enable(isp_proc_handle_t proc) esp_err_t esp_isp_disable(isp_proc_handle_t proc) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(proc->isp_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "processor isn't in enable state"); + isp_fsm_t expected_fsm = ISP_FSM_ENABLE; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->isp_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "processor isn't in enable state"); isp_ll_enable(proc->hal.hw, false); - proc->isp_fsm = ISP_FSM_INIT; return ESP_OK; } diff --git a/components/esp_driver_isp/src/isp_demosaic.c b/components/esp_driver_isp/src/isp_demosaic.c index 92a224caae0a..37f299bd71b8 100644 --- a/components/esp_driver_isp/src/isp_demosaic.c +++ b/components/esp_driver_isp/src/isp_demosaic.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -46,10 +46,10 @@ esp_err_t esp_isp_demosaic_configure(isp_proc_handle_t proc, const esp_isp_demos esp_err_t esp_isp_demosaic_enable(isp_proc_handle_t proc) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(proc->demosaic_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "demosaic is enabled already"); + isp_fsm_t expected_fsm = ISP_FSM_INIT; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->demosaic_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "demosaic is enabled already"); isp_ll_demosaic_enable(proc->hal.hw, true); - proc->demosaic_fsm = ISP_FSM_ENABLE; return ESP_OK; } @@ -57,13 +57,13 @@ esp_err_t esp_isp_demosaic_enable(isp_proc_handle_t proc) esp_err_t esp_isp_demosaic_disable(isp_proc_handle_t proc) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(proc->demosaic_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "demosaic isn't enabled yet"); + isp_fsm_t expected_fsm = ISP_FSM_ENABLE; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->demosaic_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "demosaic isn't enabled yet"); if (proc->out_color_format.color_space == (uint32_t)COLOR_SPACE_RAW) { // for other out_color_format, demosaic module is needed for rgb interpolation algorithm isp_ll_demosaic_enable(proc->hal.hw, false); } - proc->demosaic_fsm = ISP_FSM_INIT; return ESP_OK; } diff --git a/components/esp_driver_isp/src/isp_gamma.c b/components/esp_driver_isp/src/isp_gamma.c index c8d323f4169e..52b77ba9d60e 100644 --- a/components/esp_driver_isp/src/isp_gamma.c +++ b/components/esp_driver_isp/src/isp_gamma.c @@ -58,6 +58,8 @@ esp_err_t esp_isp_gamma_configure(isp_proc_handle_t proc, color_component_t comp esp_err_t esp_isp_gamma_enable(isp_proc_handle_t proc) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + isp_fsm_t expected_fsm = ISP_FSM_INIT; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->gamma_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "gamma is enabled already"); portENTER_CRITICAL(&proc->spinlock); isp_ll_gamma_enable(proc->hal.hw, true); @@ -69,6 +71,8 @@ esp_err_t esp_isp_gamma_enable(isp_proc_handle_t proc) esp_err_t esp_isp_gamma_disable(isp_proc_handle_t proc) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + isp_fsm_t expected_fsm = ISP_FSM_ENABLE; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->gamma_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "gamma is disabled already"); portENTER_CRITICAL(&proc->spinlock); isp_ll_gamma_enable(proc->hal.hw, false); diff --git a/components/esp_driver_isp/src/isp_hist.c b/components/esp_driver_isp/src/isp_hist.c index 739a8a2ac788..f2c8620acc68 100644 --- a/components/esp_driver_isp/src/isp_hist.c +++ b/components/esp_driver_isp/src/isp_hist.c @@ -94,6 +94,7 @@ static esp_err_t s_esp_isp_hist_config_hardware(isp_proc_handle_t isp_proc, cons if (hist_cfg->hist_mode == ISP_HIST_SAMPLING_RGB) { isp_ll_hist_set_rgb_coefficient(isp_proc->hal.hw, &hist_cfg->rgb_coefficient); } + isp_ll_hist_set_clk_ctrl_mode(isp_proc->hal.hw, ISP_LL_PIPELINE_CLK_CTRL_AUTO); return ESP_OK; } @@ -158,7 +159,6 @@ esp_err_t esp_isp_hist_controller_enable(isp_hist_ctlr_t hist_ctlr) ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "controller not in init state"); - isp_ll_hist_clk_enable(hist_ctlr->isp_proc->hal.hw, true); isp_ll_enable_intr(hist_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_HIST_MASK, true); return ESP_OK; @@ -173,7 +173,6 @@ esp_err_t esp_isp_hist_controller_disable(isp_hist_ctlr_t hist_ctlr) ESP_ERR_INVALID_STATE, TAG, "controller not in enable state"); isp_ll_enable_intr(hist_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_HIST_MASK, false); - isp_ll_hist_clk_enable(hist_ctlr->isp_proc->hal.hw, false); esp_intr_disable(hist_ctlr->intr_handle); return ESP_OK; diff --git a/components/esp_driver_isp/src/isp_lsc.c b/components/esp_driver_isp/src/isp_lsc.c index d8996e290598..3c09320c783c 100644 --- a/components/esp_driver_isp/src/isp_lsc.c +++ b/components/esp_driver_isp/src/isp_lsc.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -27,8 +27,8 @@ static const char *TAG = "ISP_LSC"; esp_err_t esp_isp_lsc_allocate_gain_array(isp_proc_handle_t isp_proc, esp_isp_lsc_gain_array_t *gain_array, size_t *out_array_size_per_channel) { - ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(isp_proc->lsc_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "lsc is enabled already"); + ESP_RETURN_ON_FALSE(isp_proc && gain_array && out_array_size_per_channel, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE(atomic_load(&isp_proc->lsc_fsm) == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "lsc is enabled already"); int num_grids_x_max = ISP_LSC_GET_GRIDS(ISP_LL_HSIZE_MAX); int num_grids_y_max = ISP_LSC_GET_GRIDS(ISP_LL_VSIZE_MAX); @@ -70,15 +70,16 @@ esp_err_t esp_isp_lsc_configure(isp_proc_handle_t isp_proc, const esp_isp_lsc_co ESP_RETURN_ON_FALSE(num_grids_x <= num_grids_x_max && num_grids_y <= num_grids_y_max, ESP_ERR_INVALID_ARG, TAG, "invalid h_res or v_res"); ESP_RETURN_ON_FALSE(config->gain_array->gain_r && config->gain_array->gain_gr && config->gain_array->gain_gb && config->gain_array->gain_b, ESP_ERR_INVALID_ARG, TAG, "null pointer to gain arrays"); + isp_ll_lsc_set_clk_ctrl_mode(isp_proc->hal.hw, ISP_LL_PIPELINE_CLK_CTRL_AUTO); isp_ll_lsc_set_xtablesize(isp_proc->hal.hw, num_grids_x); for (int y = 0; y < num_grids_y; y++) { for (int x = 0; x < num_grids_x; x++) { int i = y * num_grids_x + x; - isp_ll_lut_set_wdata_r_gr(isp_proc->hal.hw, config->gain_array->gain_r[i], config->gain_array->gain_gr[i]); - isp_ll_lut_set_cmd(isp_proc->hal.hw, true, false, i, ISP_LL_LUT_LSC); - isp_ll_lut_set_wdata_gb_b(isp_proc->hal.hw, config->gain_array->gain_gb[i], config->gain_array->gain_b[i]); - isp_ll_lut_set_cmd(isp_proc->hal.hw, true, true, i, ISP_LL_LUT_LSC); + isp_ll_lut_lsc_set_wdata_r_gr(isp_proc->hal.hw, config->gain_array->gain_r[i], config->gain_array->gain_gr[i]); + isp_ll_lut_lsc_set_cmd(isp_proc->hal.hw, true, false, i, ISP_LL_LUT_LSC); + isp_ll_lut_lsc_set_wdata_gb_b(isp_proc->hal.hw, config->gain_array->gain_gb[i], config->gain_array->gain_b[i]); + isp_ll_lut_lsc_set_cmd(isp_proc->hal.hw, true, true, i, ISP_LL_LUT_LSC); } } @@ -88,11 +89,10 @@ esp_err_t esp_isp_lsc_configure(isp_proc_handle_t isp_proc, const esp_isp_lsc_co esp_err_t esp_isp_lsc_enable(isp_proc_handle_t isp_proc) { ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(isp_proc->lsc_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "lsc is enabled already"); + isp_fsm_t expected_fsm = ISP_FSM_INIT; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&isp_proc->lsc_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "lsc is enabled already"); - isp_ll_lsc_clk_enable(isp_proc->hal.hw, true); isp_ll_lsc_enable(isp_proc->hal.hw, true); - isp_proc->lsc_fsm = ISP_FSM_ENABLE; return ESP_OK; } @@ -100,11 +100,10 @@ esp_err_t esp_isp_lsc_enable(isp_proc_handle_t isp_proc) esp_err_t esp_isp_lsc_disable(isp_proc_handle_t isp_proc) { ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(isp_proc->lsc_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "lsc isn't enabled yet"); + isp_fsm_t expected_fsm = ISP_FSM_ENABLE; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&isp_proc->lsc_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "lsc isn't enabled yet"); isp_ll_lsc_enable(isp_proc->hal.hw, false); - isp_ll_lsc_clk_enable(isp_proc->hal.hw, false); - isp_proc->lsc_fsm = ISP_FSM_INIT; return ESP_OK; } diff --git a/components/esp_driver_isp/src/isp_sharpen.c b/components/esp_driver_isp/src/isp_sharpen.c index abd88956ce28..c0dd2fc25818 100644 --- a/components/esp_driver_isp/src/isp_sharpen.c +++ b/components/esp_driver_isp/src/isp_sharpen.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -40,22 +40,25 @@ esp_err_t esp_isp_sharpen_configure(isp_proc_handle_t proc, const esp_isp_sharpe }; memcpy(sharpen_hal_cfg.sharpen_template, config->sharpen_template, ISP_SHARPEN_TEMPLATE_X_NUMS * ISP_SHARPEN_TEMPLATE_X_NUMS * sizeof(uint8_t)); isp_hal_sharpen_config(&(proc->hal), &sharpen_hal_cfg); + isp_ll_sharp_set_clk_ctrl_mode(proc->hal.hw, ISP_LL_PIPELINE_CLK_CTRL_AUTO); } else { isp_hal_sharpen_config(&(proc->hal), NULL); } + bool valid = isp_ll_shadow_update_sharpen(proc->hal.hw); + ESP_RETURN_ON_FALSE_ISR(valid, ESP_ERR_INVALID_STATE, TAG, "failed to update sharp shadow register"); + return ESP_OK; } esp_err_t esp_isp_sharpen_enable(isp_proc_handle_t proc) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(proc->sharpen_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "sharpen is enabled already"); + isp_fsm_t expected_fsm = ISP_FSM_INIT; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->sharpen_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "sharpen is enabled already"); - isp_ll_sharp_clk_enable(proc->hal.hw, true); isp_ll_enable_intr(proc->hal.hw, ISP_LL_EVENT_SHARP_FRAME, true); isp_ll_sharp_enable(proc->hal.hw, true); - proc->sharpen_fsm = ISP_FSM_ENABLE; return ESP_OK; } @@ -63,12 +66,11 @@ esp_err_t esp_isp_sharpen_enable(isp_proc_handle_t proc) esp_err_t esp_isp_sharpen_disable(isp_proc_handle_t proc) { ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); - ESP_RETURN_ON_FALSE(proc->sharpen_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "sharpen isn't enabled yet"); + isp_fsm_t expected_fsm = ISP_FSM_ENABLE; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&proc->sharpen_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "sharpen isn't enabled yet"); isp_ll_sharp_enable(proc->hal.hw, false); isp_ll_enable_intr(proc->hal.hw, ISP_LL_EVENT_SHARP_FRAME, false); - isp_ll_sharp_clk_enable(proc->hal.hw, false); - proc->sharpen_fsm = ISP_FSM_INIT; return ESP_OK; } diff --git a/components/esp_driver_isp/src/isp_wbg.c b/components/esp_driver_isp/src/isp_wbg.c new file mode 100644 index 000000000000..96b809840c5a --- /dev/null +++ b/components/esp_driver_isp/src/isp_wbg.c @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include "sdkconfig.h" +#include "esp_log.h" +#include "esp_check.h" +#include "freertos/FreeRTOS.h" +#include "driver/isp_core.h" +#include "driver/isp_wbg.h" +#include "esp_private/isp_private.h" +#include "hal/efuse_hal.h" +#include "soc/chip_revision.h" + +/*--------------------------------------------------------------- + WBG +---------------------------------------------------------------*/ + +static const char *TAG = "ISP_WBG"; + +esp_err_t esp_isp_wbg_configure(isp_proc_handle_t isp_proc, const esp_isp_wbg_config_t *config) +{ +#if CONFIG_IDF_TARGET_ESP32P4 + unsigned chip_version = efuse_hal_chip_revision(); + if (!ESP_CHIP_REV_ABOVE(chip_version, 300)) { + ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "WBG is not supported on ESP32P4 chips prior than v3.0"); + } +#endif + + ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + + // Configure clock control mode + isp_ll_awb_set_wb_gain_clk_ctrl_mode(isp_proc->hal.hw, ISP_LL_PIPELINE_CLK_CTRL_AUTO); + + return ESP_OK; +} + +esp_err_t esp_isp_wbg_enable(isp_proc_handle_t isp_proc) +{ + ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + isp_fsm_t expected_fsm = ISP_FSM_INIT; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&isp_proc->wbg_fsm, &expected_fsm, ISP_FSM_ENABLE), ESP_ERR_INVALID_STATE, TAG, "wbg is enabled already"); + + // Enable WBG module + isp_ll_awb_enable_wb_gain(isp_proc->hal.hw, true); + + ESP_LOGD(TAG, "WBG enabled"); + return ESP_OK; +} + +esp_err_t esp_isp_wbg_set_wb_gain(isp_proc_handle_t isp_proc, isp_wbg_gain_t gain) +{ + ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + ESP_RETURN_ON_FALSE(atomic_load(&isp_proc->wbg_fsm) == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "wbg isn't enabled yet"); + + // Set WBG gain + isp_ll_awb_set_wb_gain(isp_proc->hal.hw, gain); + + bool valid = isp_ll_shadow_update_wbg(isp_proc->hal.hw); + ESP_RETURN_ON_FALSE_ISR(valid, ESP_ERR_INVALID_STATE, TAG, "failed to update wbg shadow register"); + + return ESP_OK; +} + +esp_err_t esp_isp_wbg_disable(isp_proc_handle_t isp_proc) +{ + ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); + isp_fsm_t expected_fsm = ISP_FSM_ENABLE; + ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&isp_proc->wbg_fsm, &expected_fsm, ISP_FSM_INIT), ESP_ERR_INVALID_STATE, TAG, "wbg isn't enabled yet"); + + // Disable WBG module + isp_ll_awb_enable_wb_gain(isp_proc->hal.hw, false); + + ESP_LOGD(TAG, "WBG disabled"); + return ESP_OK; +} diff --git a/components/esp_driver_ledc/src/ledc.c b/components/esp_driver_ledc/src/ledc.c index 4a5037650fe9..057c73b977e2 100644 --- a/components/esp_driver_ledc/src/ledc.c +++ b/components/esp_driver_ledc/src/ledc.c @@ -872,7 +872,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf) /*set channel parameters*/ /* channel parameters decide how the waveform looks like in one period */ /* set channel duty and hpoint value, duty range is [0, (2**duty_res)], hpoint range is [0, (2**duty_res)-1] */ - /* Note: On ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4, due to a hardware bug, + /* Note: On ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4 (rev < 3.0), due to a hardware bug, * 100% duty cycle (i.e. 2**duty_res) is not reachable when the binded timer selects the maximum duty * resolution. For example, the max duty resolution on ESP32C3 is 14-bit width, then set duty to (2**14) * will mess up the duty calculation in hardware. diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c index cc454aa7b448..a5494f1f9f24 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c @@ -292,7 +292,7 @@ static bool test_delimiter(parlio_rx_delimiter_handle_t deli, bool free_running_ static uint32_t task_flags = 0; xTaskCreate(sender_task_thread, "sender task", 4096, &task_flags, 5, &sender_task); // Waiting for the data ready on line - while ((task_flags & TEST_TASK_DATA_READY_BIT)) { + while (!(task_flags & TEST_TASK_DATA_READY_BIT)) { vTaskDelay(1); } diff --git a/components/esp_driver_ppa/include/driver/ppa.h b/components/esp_driver_ppa/include/driver/ppa.h index 5f209e85e05c..5a3917d88d0c 100644 --- a/components/esp_driver_ppa/include/driver/ppa.h +++ b/components/esp_driver_ppa/include/driver/ppa.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -268,7 +268,12 @@ typedef struct { uint32_t fill_block_w; /*!< The width of the block to be filled (unit: pixel) */ uint32_t fill_block_h; /*!< The height of the block to be filled (unit: pixel) */ - color_pixel_argb8888_data_t fill_argb_color; /*!< The color to be filled, in ARGB8888 format */ + union { + color_pixel_argb8888_data_t fill_argb_color; /*!< For any ARGB/RGB format color to be filled, use this field to fill A (if applicable)/R/G/B components */ + color_pixel_gray8_data_t fill_gray8_color; /*!< For GRAY8 format color to be filled */ + color_macroblock_yuv_data_t fill_yuv_color; /*!< For any YUV format color to be filled, use this field to fill Y/U/V components */ + uint32_t fill_color_val; /*!< The color to be filled, in a raw 32-bit value. The interpretation of the value depends on the selected `fill_cm` */ + }; ppa_trans_mode_t mode; /*!< Determines whether to block inside the operation functions, see `ppa_trans_mode_t` */ void *user_data; /*!< User registered data to be passed into `done_cb` callback function */ @@ -287,6 +292,23 @@ typedef struct { */ esp_err_t ppa_do_fill(ppa_client_handle_t ppa_client, const ppa_fill_oper_config_t *config); +/** + * @brief Configure the RGB888 to GRAY8 color conversion coefficients for ppa_do_scale_rotate_mirror and ppa_do_fill + * + * The gray value is calculated as: gray = (r_weight * R + g_weight * G + b_weight * B) >> 8 + * Note: (r_weight + g_weight + b_weight) should equal to 256. + * + * @param r_weight Coefficient for R component, range: [0, 255] + * @param g_weight Coefficient for G component, range: [0, 255] + * @param b_weight Coefficient for B component, range: [0, 255] + * @return + * - ESP_OK: Set the RGB888 to GRAY color conversion formula successfully + * - ESP_ERR_NOT_SUPPORTED: Set the RGB888 to GRAY color conversion formula failed because the PPA peripheral does not support this feature + * - ESP_ERR_INVALID_ARG: Set the RGB888 to GRAY color conversion formula failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Set the RGB888 to GRAY color conversion formula failed because the PPA peripheral not initialized + */ +esp_err_t ppa_set_rgb2gray_formula(uint8_t r_weight, uint8_t g_weight, uint8_t b_weight); + #ifdef __cplusplus } #endif diff --git a/components/esp_driver_ppa/src/ppa_blend.c b/components/esp_driver_ppa/src/ppa_blend.c index f8ffab01ee57..0037e480837f 100644 --- a/components/esp_driver_ppa/src/ppa_blend.c +++ b/components/esp_driver_ppa/src/ppa_blend.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -140,6 +140,10 @@ bool ppa_blend_transaction_on_picked(uint32_t num_chans, const dma2d_trans_chann // Configure PPA Blending engine ppa_ll_blend_set_rx_bg_color_mode(platform->hal.dev, blend_trans_desc->in_bg.blend_cm); + if (COLOR_SPACE_TYPE((uint32_t)blend_trans_desc->in_bg.blend_cm) == COLOR_SPACE_YUV) { + ppa_ll_blend_set_rx_bg_yuv_range(platform->hal.dev, blend_trans_desc->in_bg.yuv_range); + ppa_ll_blend_set_rx_bg_yuv2rgb_std(platform->hal.dev, blend_trans_desc->in_bg.yuv_std); + } ppa_ll_blend_enable_rx_bg_byte_swap(platform->hal.dev, blend_trans_desc->bg_byte_swap); ppa_ll_blend_enable_rx_bg_rgb_swap(platform->hal.dev, blend_trans_desc->bg_rgb_swap); ppa_ll_blend_configure_rx_bg_alpha(platform->hal.dev, blend_trans_desc->bg_alpha_update_mode, blend_trans_desc->bg_alpha_value); @@ -153,6 +157,10 @@ bool ppa_blend_transaction_on_picked(uint32_t num_chans, const dma2d_trans_chann ppa_ll_blend_configure_rx_fg_alpha(platform->hal.dev, blend_trans_desc->fg_alpha_update_mode, blend_trans_desc->fg_alpha_value); ppa_ll_blend_set_tx_color_mode(platform->hal.dev, blend_trans_desc->out.blend_cm); + if (COLOR_SPACE_TYPE((uint32_t)blend_trans_desc->out.blend_cm) == COLOR_SPACE_YUV) { + ppa_ll_blend_set_tx_yuv_range(platform->hal.dev, blend_trans_desc->out.yuv_range); + ppa_ll_blend_set_tx_rgb2yuv_std(platform->hal.dev, blend_trans_desc->out.yuv_std); + } // Color keying color_pixel_rgb888_data_t rgb888_min = {.b = 0x00, .g = 0x00, .r = 0x00}; @@ -182,6 +190,41 @@ esp_err_t ppa_do_blend(ppa_client_handle_t ppa_client, const ppa_blend_oper_conf uint32_t buf_alignment_size = (uint32_t)ppa_client->engine->platform->buf_alignment_size; ESP_RETURN_ON_FALSE(((uint32_t)config->out.buffer & (buf_alignment_size - 1)) == 0 && (config->out.buffer_size & (buf_alignment_size - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "out.buffer addr or out.buffer_size not aligned to cache line size"); + ESP_RETURN_ON_FALSE(ppa_ll_blend_is_color_mode_supported(config->in_bg.blend_cm) && ppa_ll_blend_is_color_mode_supported(config->in_fg.blend_cm) && ppa_ll_blend_is_color_mode_supported(config->out.blend_cm), ESP_ERR_INVALID_ARG, TAG, "unsupported color mode"); + // For YUV420 input/output: in desc, ha/hb/va/vb/x/y must be even number + // For YUV422 input/output: in desc, ha/hb/x must be even number + if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_YUV420) { + ESP_RETURN_ON_FALSE(config->in_bg.pic_h % 2 == 0 && config->in_bg.pic_w % 2 == 0 && + config->in_bg.block_h % 2 == 0 && config->in_bg.block_w % 2 == 0 && + config->in_bg.block_offset_x % 2 == 0 && config->in_bg.block_offset_y % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV420 input does not support odd h/w/offset_x/offset_y"); + } else if (PPA_IS_CM_YUV422(config->in_bg.blend_cm)) { + ESP_RETURN_ON_FALSE(config->in_bg.pic_w % 2 == 0 && config->in_bg.block_w % 2 == 0 && config->in_bg.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV422 input does not support odd w/offset_x"); + } + // TODO: Support CLUT to support L4/L8 color mode + // else if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_L4) { + // ESP_RETURN_ON_FALSE(config->in_bg.block_w % 2 == 0 && config->in_bg.block_offset_x % 2 == 0, + // ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w and in_bg.block_offset_x must be even"); + // } + if (config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_A4) { // || config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_L4 + ESP_RETURN_ON_FALSE(config->in_fg.block_w % 2 == 0 && config->in_fg.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "in_fg.block_w and in_fg.block_offset_x must be even"); + } + if (config->out.blend_cm == PPA_BLEND_COLOR_MODE_YUV420) { + ESP_RETURN_ON_FALSE(config->out.pic_h % 2 == 0 && config->out.pic_w % 2 == 0 && + config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y"); + } else if (PPA_IS_CM_YUV422(config->out.blend_cm)) { + ESP_RETURN_ON_FALSE(config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV422 output does not support odd w/offset_x"); + } + ESP_RETURN_ON_FALSE(config->in_bg.block_w <= (config->in_bg.pic_w - config->in_bg.block_offset_x) && + config->in_bg.block_h <= (config->in_bg.pic_h - config->in_bg.block_offset_y), + ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w/h + in_bg.block_offset_x/y does not fit in the in pic"); + ESP_RETURN_ON_FALSE(config->in_fg.block_w <= (config->in_fg.pic_w - config->in_fg.block_offset_x) && + config->in_fg.block_h <= (config->in_fg.pic_h - config->in_fg.block_offset_y), + ESP_ERR_INVALID_ARG, TAG, "in_fg.block_w/h + in_fg.block_offset_x/y does not fit in the in pic"); color_space_pixel_format_t out_pixel_format = { .color_type_id = config->out.blend_cm, }; @@ -190,6 +233,9 @@ esp_err_t ppa_do_blend(ppa_client_handle_t ppa_client, const ppa_blend_oper_conf ESP_RETURN_ON_FALSE(out_pic_len <= config->out.buffer_size, ESP_ERR_INVALID_ARG, TAG, "out.pic_w/h mismatch with out.buffer_size"); ESP_RETURN_ON_FALSE(config->in_bg.block_w == config->in_fg.block_w && config->in_bg.block_h == config->in_fg.block_h, ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w/h must be equal to in_fg.block_w/h"); + ESP_RETURN_ON_FALSE(config->in_fg.block_w <= (config->out.pic_w - config->out.block_offset_x) && + config->in_fg.block_h <= (config->out.pic_h - config->out.block_offset_y), + ESP_ERR_INVALID_ARG, TAG, "block does not fit in the out pic"); if (config->bg_byte_swap) { PPA_CHECK_CM_SUPPORT_BYTE_SWAP("in_bg.blend", (uint32_t)config->in_bg.blend_cm); } @@ -218,15 +264,7 @@ esp_err_t ppa_do_blend(ppa_client_handle_t ppa_client, const ppa_blend_oper_conf ESP_RETURN_ON_FALSE(config->fg_alpha_scale_ratio > 0 && config->fg_alpha_scale_ratio < 1, ESP_ERR_INVALID_ARG, TAG, "invalid fg_alpha_scale_ratio"); new_fg_alpha_value = (uint32_t)(config->fg_alpha_scale_ratio * 256); } - // if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_L4) { - // ESP_RETURN_ON_FALSE(config->in_bg.block_w % 2 == 0 && config->in_bg.block_offset_x % 2 == 0, - // ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w and in_bg.block_offset_x must be even"); - // } - if (config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_A4) { // || config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_L4 - ESP_RETURN_ON_FALSE(config->in_fg.block_w % 2 == 0 && config->in_fg.block_offset_x % 2 == 0, - ESP_ERR_INVALID_ARG, TAG, "in_fg.block_w and in_fg.block_offset_x must be even"); - } - // To reduce complexity, color_mode, alpha_update_mode correctness are checked in their corresponding LL functions + // To reduce complexity, specific color_mode, alpha_update_mode correctness are checked in their corresponding LL functions // Write back and invalidate necessary data (note that the window content is not continuous in the buffer) // Write back in_bg_buffer, in_fg_buffer extended windows (alignment not necessary on C2M direction) diff --git a/components/esp_driver_ppa/src/ppa_core.c b/components/esp_driver_ppa/src/ppa_core.c index a622abdbb564..a7b371478e9b 100644 --- a/components/esp_driver_ppa/src/ppa_core.c +++ b/components/esp_driver_ppa/src/ppa_core.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -513,3 +513,15 @@ bool ppa_transaction_done_cb(dma2d_channel_handle_t dma2d_chan, dma2d_event_data return need_yield; } + +esp_err_t ppa_set_rgb2gray_formula(uint8_t r_weight, uint8_t g_weight, uint8_t b_weight) +{ + ESP_RETURN_ON_FALSE(ppa_ll_srm_is_color_mode_supported(PPA_SRM_COLOR_MODE_GRAY8) || ppa_ll_blend_is_color_mode_supported(PPA_BLEND_COLOR_MODE_GRAY8), ESP_ERR_NOT_SUPPORTED, TAG, "GRAY color mode not supported"); + ESP_RETURN_ON_FALSE((r_weight + g_weight + b_weight) == 256, ESP_ERR_INVALID_ARG, TAG, "invalid rgb2gray formula"); + ESP_RETURN_ON_FALSE(s_platform.hal.dev, ESP_ERR_INVALID_STATE, TAG, "no PPA client registered yet"); + + _lock_acquire(&s_platform.mutex); + ppa_ll_set_rgb2gray_coeff(s_platform.hal.dev, r_weight, g_weight, b_weight); + _lock_release(&s_platform.mutex); + return ESP_OK; +} diff --git a/components/esp_driver_ppa/src/ppa_fill.c b/components/esp_driver_ppa/src/ppa_fill.c index 1983ea3f016d..a810c669515d 100644 --- a/components/esp_driver_ppa/src/ppa_fill.c +++ b/components/esp_driver_ppa/src/ppa_fill.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -77,7 +77,7 @@ bool ppa_fill_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channe dma2d_start(dma2d_rx_chan); // Configure PPA Blending engine - ppa_ll_blend_configure_filling_block(platform->hal.dev, &fill_trans_desc->fill_argb_color, fill_trans_desc->fill_block_w, fill_trans_desc->fill_block_h); + ppa_ll_blend_configure_filling_block(platform->hal.dev, fill_trans_desc->out.fill_cm, (void *)&fill_trans_desc->fill_color_val, fill_trans_desc->fill_block_w, fill_trans_desc->fill_block_h); ppa_ll_blend_set_tx_color_mode(platform->hal.dev, fill_trans_desc->out.fill_cm); ppa_ll_blend_start(platform->hal.dev, PPA_LL_BLEND_TRANS_MODE_FILL); @@ -96,13 +96,28 @@ esp_err_t ppa_do_fill(ppa_client_handle_t ppa_client, const ppa_fill_oper_config uint32_t buf_alignment_size = (uint32_t)ppa_client->engine->platform->buf_alignment_size; ESP_RETURN_ON_FALSE(((uint32_t)config->out.buffer & (buf_alignment_size - 1)) == 0 && (config->out.buffer_size & (buf_alignment_size - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "out.buffer addr or out.buffer_size not aligned to cache line size"); + ESP_RETURN_ON_FALSE(ppa_ll_blend_is_color_mode_supported((ppa_blend_color_mode_t)config->out.fill_cm), ESP_ERR_INVALID_ARG, TAG, "unsupported color mode"); + // For YUV420 output: in desc, ha/hb/va/vb/x/y must be even number + // For YUV422 output: in desc, ha/hb/x must be even number + // if (config->out.fill_cm == PPA_FILL_COLOR_MODE_YUV420) { + // ESP_RETURN_ON_FALSE(config->out.pic_h % 2 == 0 && config->out.pic_w % 2 == 0 && + // config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0, + // ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y"); + // } else + if (config->out.fill_cm == PPA_FILL_COLOR_MODE_YUV422_UYVY) { + ESP_RETURN_ON_FALSE(config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV422 output does not support odd w/offset_x"); + } color_space_pixel_format_t out_pixel_format = { .color_type_id = config->out.fill_cm, }; uint32_t out_pixel_depth = color_hal_pixel_format_get_bit_depth(out_pixel_format); uint32_t out_pic_len = config->out.pic_w * config->out.pic_h * out_pixel_depth / 8; ESP_RETURN_ON_FALSE(out_pic_len <= config->out.buffer_size, ESP_ERR_INVALID_ARG, TAG, "out.pic_w/h mismatch with out.buffer_size"); - // To reduce complexity, color_mode, fill_block_w/h correctness are checked in their corresponding LL functions + ESP_RETURN_ON_FALSE(config->fill_block_w <= (config->out.pic_w - config->out.block_offset_x) && + config->fill_block_h <= (config->out.pic_h - config->out.block_offset_y), + ESP_ERR_INVALID_ARG, TAG, "block does not fit in the out pic"); + // To reduce complexity, specific color_mode, fill_block_w/h correctness are checked in their corresponding LL functions // Write back and invalidate necessary data (note that the window content is not continuous in the buffer) // Write back and invalidate buffer extended window (alignment not necessary on C2M direction, but alignment strict on M2C direction) diff --git a/components/esp_driver_ppa/src/ppa_priv.h b/components/esp_driver_ppa/src/ppa_priv.h index 2a3b1e5d57de..d3f03a3b03e0 100644 --- a/components/esp_driver_ppa/src/ppa_priv.h +++ b/components/esp_driver_ppa/src/ppa_priv.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -34,6 +34,10 @@ extern "C" { ESP_RETURN_ON_FALSE(COLOR_SPACE_TYPE(color_type_id) == COLOR_SPACE_ARGB || COLOR_SPACE_TYPE(color_type_id) == COLOR_SPACE_RGB, \ ESP_ERR_INVALID_ARG, TAG, str "_cm does not support rgb_swap"); +#define PPA_IS_CM_YUV422(color_type_id) \ + (color_type_id == COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_UYVY422) || color_type_id == COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_VYUY422) || \ + color_type_id == COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUYV422) || color_type_id == COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YVYU422)) + #define PPA_ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) #define PPA_ALIGN_DOWN(num, align) ((num) & ~((align) - 1)) @@ -173,7 +177,12 @@ typedef struct { uint32_t fill_block_w; uint32_t fill_block_h; - color_pixel_argb8888_data_t fill_argb_color; + union { + color_pixel_argb8888_data_t fill_argb_color; + color_pixel_gray8_data_t fill_gray8_color; + color_macroblock_yuv_data_t fill_yuv_color; + uint32_t fill_color_val; + }; ppa_trans_mode_t mode; void *user_data; diff --git a/components/esp_driver_ppa/src/ppa_srm.c b/components/esp_driver_ppa/src/ppa_srm.c index a7e5ad6f8777..5e3f2b76ce59 100644 --- a/components/esp_driver_ppa/src/ppa_srm.c +++ b/components/esp_driver_ppa/src/ppa_srm.c @@ -100,13 +100,6 @@ bool ppa_srm_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel dma2d_set_transfer_ability(dma2d_tx_chan, &dma_transfer_ability); dma2d_set_transfer_ability(dma2d_rx_chan, &dma_transfer_ability); - // Configure the block size to be received by the SRM engine, which is passed from the 2D-DMA TX channel (i.e. 2D-DMA dscr-port mode) - dma2d_dscr_port_mode_config_t dma_dscr_port_mode_config = { - .block_h = (srm_trans_desc->in.srm_cm == PPA_SRM_COLOR_MODE_YUV420) ? PPA_LL_SRM_YUV420_BLOCK_SIZE : PPA_LL_SRM_DEFAULT_BLOCK_SIZE, - .block_v = (srm_trans_desc->in.srm_cm == PPA_SRM_COLOR_MODE_YUV420) ? PPA_LL_SRM_YUV420_BLOCK_SIZE : PPA_LL_SRM_DEFAULT_BLOCK_SIZE, - }; - dma2d_configure_dscr_port_mode(dma2d_tx_chan, &dma_dscr_port_mode_config); - // YUV444 is not supported by PPA module, need to utilize 2D-DMA color space conversion feature to do a conversion ppa_srm_color_mode_t ppa_in_color_mode = srm_trans_desc->in.srm_cm; if (ppa_in_color_mode == PPA_SRM_COLOR_MODE_YUV444) { @@ -129,6 +122,15 @@ bool ppa_srm_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel dma2d_configure_color_space_conversion(dma2d_rx_chan, &dma_rx_csc); } + // Configure the block size to be received by the SRM engine, which is passed from the 2D-DMA TX channel (i.e. 2D-DMA dscr-port mode) + uint32_t block_h = 0, block_v = 0; + ppa_ll_srm_get_dma_dscr_port_mode_block_size(platform->hal.dev, ppa_in_color_mode, ppa_ll_srm_get_mb_size(platform->hal.dev), &block_h, &block_v); + dma2d_dscr_port_mode_config_t dma_dscr_port_mode_config = { + .block_h = block_h, + .block_v = block_v, + }; + dma2d_configure_dscr_port_mode(dma2d_tx_chan, &dma_dscr_port_mode_config); + dma2d_rx_event_callbacks_t dma_event_cbs = { .on_recv_eof = ppa_transaction_done_cb, }; @@ -177,22 +179,25 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s uint32_t buf_alignment_size = (uint32_t)ppa_client->engine->platform->buf_alignment_size; ESP_RETURN_ON_FALSE(((uint32_t)config->out.buffer & (buf_alignment_size - 1)) == 0 && (config->out.buffer_size & (buf_alignment_size - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "out.buffer addr or out.buffer_size not aligned to cache line size"); + ESP_RETURN_ON_FALSE(ppa_ll_srm_is_color_mode_supported(config->in.srm_cm) && ppa_ll_srm_is_color_mode_supported(config->out.srm_cm), ESP_ERR_INVALID_ARG, TAG, "unsupported color mode"); // For YUV420 input/output: in desc, ha/hb/va/vb/x/y must be even number + // For YUV422 input/output: in desc, ha/hb/x must be even number if (config->in.srm_cm == PPA_SRM_COLOR_MODE_YUV420) { ESP_RETURN_ON_FALSE(config->in.pic_h % 2 == 0 && config->in.pic_w % 2 == 0 && config->in.block_h % 2 == 0 && config->in.block_w % 2 == 0 && config->in.block_offset_x % 2 == 0 && config->in.block_offset_y % 2 == 0, ESP_ERR_INVALID_ARG, TAG, "YUV420 input does not support odd h/w/offset_x/offset_y"); + } else if (PPA_IS_CM_YUV422(config->in.srm_cm)) { + ESP_RETURN_ON_FALSE(config->in.pic_w % 2 == 0 && config->in.block_w % 2 == 0 && config->in.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV422 input does not support odd w/offset_x"); } - // TODO: P4 ECO2 support YUV422 - // else if (config->in.srm_cm == PPA_SRM_COLOR_MODE_YUV422) { - // ESP_RETURN_ON_FALSE(config->in.pic_w % 2 == 0 && config->in.block_w % 2 == 0 && config->in.block_offset_x % 2 == 0, - // ESP_ERR_INVALID_ARG, TAG, "YUV422 input does not support odd w/offset_x"); - // } if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV420) { ESP_RETURN_ON_FALSE(config->out.pic_h % 2 == 0 && config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0, ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y"); + } else if (PPA_IS_CM_YUV422(config->out.srm_cm)) { + ESP_RETURN_ON_FALSE(config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV422 output does not support odd w/offset_x"); } ESP_RETURN_ON_FALSE(config->in.block_w <= (config->in.pic_w - config->in.block_offset_x) && config->in.block_h <= (config->in.pic_h - config->in.block_offset_y), @@ -232,7 +237,7 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s ESP_RETURN_ON_FALSE(config->alpha_scale_ratio > 0 && config->alpha_scale_ratio < 1, ESP_ERR_INVALID_ARG, TAG, "invalid alpha_scale_ratio"); new_alpha_value = (uint32_t)(config->alpha_scale_ratio * 256); } - // To reduce complexity, rotation_angle, color_mode, alpha_update_mode correctness are checked in their corresponding LL functions + // To reduce complexity, rotation_angle, alpha_update_mode correctness are checked in their corresponding LL functions // Write back and invalidate necessary data (note that the window content is not continuous in the buffer) // Write back in_buffer extended window (alignment not necessary on C2M direction) @@ -269,6 +274,8 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV420) { srm_trans_desc->scale_x_frag = srm_trans_desc->scale_x_frag & ~1; srm_trans_desc->scale_y_frag = srm_trans_desc->scale_y_frag & ~1; + } else if (PPA_IS_CM_YUV422(config->out.srm_cm)) { + srm_trans_desc->scale_x_frag = srm_trans_desc->scale_x_frag & ~1; } srm_trans_desc->alpha_value = new_alpha_value; srm_trans_desc->data_burst_length = ppa_client->data_burst_length; diff --git a/components/esp_driver_ppa/test_apps/main/ppa_performance.h b/components/esp_driver_ppa/test_apps/main/ppa_performance.h new file mode 100644 index 000000000000..edab08fc14be --- /dev/null +++ b/components/esp_driver_ppa/test_apps/main/ppa_performance.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "sdkconfig.h" + +/* + * The time spend (T) to complete a PPA transaction is proportional to the amount of pixels (x) need to be processed. + * T = k * x + b + * k = (T - b) / x + */ + +#if CONFIG_IDF_TARGET_ESP32P4 +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 +#define PPA_SRM_MIN_PERFORMANCE_PX_PER_SEC (21000 * 1000) // k_min +#define PPA_SRM_TIME_OFFSET (-26000) // b_approx +#else +#define PPA_SRM_MIN_PERFORMANCE_PX_PER_SEC (35000 * 1000) // k_min +#define PPA_SRM_TIME_OFFSET (-37000) // b_approx +#endif + +#define PPA_BLEND_MIN_PERFORMANCE_PX_PER_SEC (31500 * 1000) // k_min +#define PPA_BLEND_TIME_OFFSET (-37150) // b_approx + +#define PPA_FILL_MIN_PERFORMANCE_PX_PER_SEC (150000 * 1000) // k_min +#define PPA_FILL_TIME_OFFSET (-106000) // b_approx +#endif diff --git a/components/esp_driver_ppa/test_apps/main/test_ppa.c b/components/esp_driver_ppa/test_apps/main/test_ppa.c index b1ce98914159..011add8c2e97 100644 --- a/components/esp_driver_ppa/test_apps/main/test_ppa.c +++ b/components/esp_driver_ppa/test_apps/main/test_ppa.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,6 +17,7 @@ #include "ccomp_timer.h" #include "hal/color_hal.h" #include "esp_cache.h" +#include "ppa_performance.h" #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) @@ -350,6 +351,39 @@ TEST_CASE("ppa_srm_basic_data_correctness_check", "[PPA]") printf("\n"); TEST_ASSERT_EQUAL_UINT8_ARRAY((void *)out_buf_expected, (void *)out_buf, buf_len); +#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3) + // Test a rgb2gray color conversion + memset(out_buf, 0, out_buf_size); + esp_cache_msync((void *)out_buf, out_buf_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M); + + const uint8_t r_weight = 100; + const uint8_t g_weight = 56; + const uint8_t b_weight = 100; + TEST_ESP_OK(ppa_set_rgb2gray_formula(r_weight, g_weight, b_weight)); + oper_config.out.srm_cm = PPA_SRM_COLOR_MODE_GRAY8; + oper_config.rotation_angle = PPA_SRM_ROTATION_ANGLE_0; + uint8_t out_buf_expected_gray[16] = {}; + for (int i = 0; i < block_w * block_h; i++) { + const uint16_t pix = in_buf[(i / block_w + in_block_offset_y) * w + (i % block_w + in_block_offset_x)]; + uint8_t _r = ((pix >> 8) & 0xF8); + uint8_t _g = ((pix >> 3) & 0xFC); + uint8_t _b = ((pix << 3) & 0xF8); + out_buf_expected_gray[(i / block_w + out_block_offset_y) * w + (i % block_w + out_block_offset_x)] = (_r * r_weight + _g * g_weight + _b * b_weight) >> 8; + } + + TEST_ESP_OK(ppa_do_scale_rotate_mirror(ppa_client_handle, &oper_config)); + + // Check result + for (int i = 0; i < w * h; i++) { + if (i % 4 == 0) { + printf("\n"); + } + printf("0x%02X ", out_buf[i]); + } + printf("\n"); + TEST_ASSERT_EQUAL_UINT8_ARRAY((void *)out_buf_expected_gray, (void *)out_buf, w * h); +#endif // !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3) + TEST_ESP_OK(ppa_unregister_client(ppa_client_handle)); free(out_buf); @@ -526,6 +560,20 @@ TEST_CASE("ppa_fill_basic_data_correctness_check", "[PPA]") }; TEST_ASSERT_EACH_EQUAL_UINT16(fill_pixel_expected.val, (void *)((uint32_t)out_buf + w * block_offset_y * out_pixel_depth / 8), block_w * block_h); +#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3) + // Test a yuv color fill + oper_config.out.fill_cm = PPA_FILL_COLOR_MODE_YUV422_UYVY; // output YUV422 is with UYVY packed order + const color_macroblock_yuv_data_t fill_yuv_color = {.y = 0xFF, .u = 0x55, .v = 0xAA}; + oper_config.fill_yuv_color = fill_yuv_color; + out_pixel_format.color_type_id = PPA_FILL_COLOR_MODE_YUV422_UYVY; + out_pixel_depth = color_hal_pixel_format_get_bit_depth(out_pixel_format); // bits + TEST_ESP_OK(ppa_do_fill(ppa_client_handle, &oper_config)); + + // Check result (2 pixels per macro pixel) + const uint32_t fill_pixel_expected_yuv422 = ((fill_yuv_color.y << 24) | (fill_yuv_color.v << 16) | (fill_yuv_color.y << 8) | (fill_yuv_color.u)); + TEST_ASSERT_EACH_EQUAL_UINT32(fill_pixel_expected_yuv422, (void *)((uint32_t)out_buf + w * block_offset_y * out_pixel_depth / 8), block_w * block_h / 2); +#endif // !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3) + TEST_ESP_OK(ppa_unregister_client(ppa_client_handle)); free(out_buf); @@ -542,15 +590,6 @@ TEST_CASE("ppa_fill_basic_data_correctness_check", "[PPA]") * k = (T - b) / x */ -#define PPA_SRM_MIN_PERFORMANCE_PX_PER_SEC (21000 * 1000) // k_min -#define PPA_SRM_TIME_OFFSET (-26000) // b_approx - -#define PPA_BLEND_MIN_PERFORMANCE_PX_PER_SEC (31500 * 1000) // k_min -#define PPA_BLEND_TIME_OFFSET (-37150) // b_approx - -#define PPA_FILL_MIN_PERFORMANCE_PX_PER_SEC (150000 * 1000) // k_min -#define PPA_FILL_TIME_OFFSET (-106000) // b_approx - TEST_CASE("ppa_srm_performance", "[PPA]") { // Configurable parameters diff --git a/components/esp_driver_sdmmc/src/sdmmc_host.c b/components/esp_driver_sdmmc/src/sdmmc_host.c index fe61d0de8902..28bb15608ec1 100644 --- a/components/esp_driver_sdmmc/src/sdmmc_host.c +++ b/components/esp_driver_sdmmc/src/sdmmc_host.c @@ -925,7 +925,9 @@ esp_err_t sdmmc_host_deinit(void) return ESP_ERR_INVALID_STATE; } for (int slot = 0; slot < SOC_SDMMC_NUM_SLOTS; slot++) { - sdmmc_host_deinit_slot_internal(slot); + if (sdmmc_host_slot_initialized(slot)) { + sdmmc_host_deinit_slot_internal(slot); + } } sdmmc_host_deinit_internal(); diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/main/test_app_main.c b/components/esp_driver_sdmmc/test_apps/sdmmc/main/test_app_main.c index e36a7a945e81..f3590bc4ef58 100644 --- a/components/esp_driver_sdmmc/test_apps/sdmmc/main/test_app_main.c +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/main/test_app_main.c @@ -9,7 +9,7 @@ #include "esp_heap_caps.h" #include "sdkconfig.h" -#define TEST_MEMORY_LEAK_THRESHOLD (300) +#define TEST_MEMORY_LEAK_THRESHOLD (350) void setUp(void) { diff --git a/components/esp_driver_touch_sens/common/touch_sens_common.c b/components/esp_driver_touch_sens/common/touch_sens_common.c index 8ecbfaaf765f..4a3a57f640c3 100644 --- a/components/esp_driver_touch_sens/common/touch_sens_common.c +++ b/components/esp_driver_touch_sens/common/touch_sens_common.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,7 +12,10 @@ #include "soc/rtc.h" #include "soc/clk_tree_defs.h" #include "soc/touch_sensor_periph.h" +#include "soc/io_mux_reg.h" #include "driver/rtc_io.h" +#include "driver/gpio.h" +#include "esp_private/gpio.h" #include "driver/touch_sens.h" #if SOC_TOUCH_SENSOR_VERSION <= 2 @@ -40,10 +43,21 @@ touch_sensor_handle_t g_touch = NULL; static void touch_channel_pin_init(int id) { gpio_num_t pin = touch_sensor_channel_io_map[id]; - rtc_gpio_init(pin); - rtc_gpio_set_direction(pin, RTC_GPIO_MODE_DISABLED); - rtc_gpio_pulldown_dis(pin); - rtc_gpio_pullup_dis(pin); + gpio_config_t cfg = { + .pin_bit_mask = BIT64(pin), + .mode = GPIO_MODE_DISABLE, + .pull_up_en = GPIO_PULLUP_DISABLE, + .pull_down_en = GPIO_PULLDOWN_DISABLE, + .intr_type = GPIO_INTR_DISABLE, + }; + gpio_config(&cfg); + gpio_func_sel(pin, PIN_FUNC_GPIO); + if (pin <= MAX_RTC_GPIO_NUM) { + rtc_gpio_init(pin); + rtc_gpio_set_direction(pin, RTC_GPIO_MODE_DISABLED); + rtc_gpio_pulldown_dis(pin); + rtc_gpio_pullup_dis(pin); + } } static void s_touch_free_resource(touch_sensor_handle_t sens_handle) @@ -421,11 +435,3 @@ esp_err_t touch_channel_read_data(touch_channel_handle_t chan_handle, touch_chan TOUCH_NULL_POINTER_CHECK_ISR(data); return touch_priv_channel_read_data(chan_handle, type, data); } - -esp_err_t touch_channel_config_benchmark(touch_channel_handle_t chan_handle, const touch_chan_benchmark_config_t *benchmark_cfg) -{ - TOUCH_NULL_POINTER_CHECK_ISR(chan_handle); - TOUCH_NULL_POINTER_CHECK_ISR(benchmark_cfg); - touch_priv_config_benchmark(chan_handle, benchmark_cfg); - return ESP_OK; -} diff --git a/components/esp_driver_touch_sens/hw_ver3/include/driver/touch_version_types.h b/components/esp_driver_touch_sens/hw_ver3/include/driver/touch_version_types.h index cf15c14be8aa..e3c4f855c790 100644 --- a/components/esp_driver_touch_sens/hw_ver3/include/driver/touch_version_types.h +++ b/components/esp_driver_touch_sens/hw_ver3/include/driver/touch_version_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,8 +19,14 @@ extern "C" { #endif -#define TOUCH_MIN_CHAN_ID 0 /*!< The minimum available channel id of the touch pad */ -#define TOUCH_MAX_CHAN_ID 13 /*!< The maximum available channel id of the touch pad */ +#define TOUCH_MIN_CHAN_ID 1 /*!< The minimum available channel id of the touch pad */ +#define TOUCH_MAX_CHAN_ID 14 /*!< The maximum available channel id of the touch pad */ + +/** + * @brief The auto trigger rise count + * @note If the trigger_rise_cnt is '0', the recommended value will be selected automatically. + */ +#define TOUCH_SENSOR_AUTO_TRIGGER_RISE_CNT 0 /** * @brief Helper macro to the default configurations of the touch sensor controller @@ -32,6 +38,7 @@ extern "C" { .max_meas_time_us = 0, \ .output_mode = TOUCH_PAD_OUT_AS_CLOCK, \ .sample_cfg_num = sample_cfg_number, \ + .trigger_rise_cnt = TOUCH_SENSOR_AUTO_TRIGGER_RISE_CNT, \ .sample_cfg = sample_cfg_array, \ } @@ -147,7 +154,7 @@ typedef struct { uint8_t low_drv; /*!< Low speed touch driver, only effective when high speed driver is disabled */ uint8_t high_drv; /*!< High speed touch driver */ uint8_t bias_volt; /*!< The Internal LDO voltage, which decide the bias voltage of the sample wave, range [0,15] */ - bool bypass_shield_output; /*!< Whether to bypass the shield output, enable when the charging/discharging rate greater than 10MHz */ + bool bypass_shield_output; /*!< (Deprecated) no effect, only for compatibility */ } touch_sensor_sample_config_t; /** @@ -162,7 +169,12 @@ typedef struct { * of this sample configurations below. */ touch_out_mode_t output_mode; /*!< Touch channel counting mode of the binarized touch output */ - uint32_t sample_cfg_num; /*!< The sample configuration number that used for sampling */ + uint32_t sample_cfg_num; /*!< The sample configuration number that used for sampling, CANNOT exceed TOUCH_SAMPLE_CFG_NUM */ + uint32_t trigger_rise_cnt; /*!< The counter of triggered frequency points to judge whether a channel active. + * For example, there are 3 sample configurations activated, and the trigger_rise_cnt is 2, + * then the channel will only be active when at least 2 of 3 sample configurations triggered. + * Range: [0 ~ sample_cfg_num], '0' means select the recommended value automatically. + */ touch_sensor_sample_config_t *sample_cfg; /*!< The array of this sample configuration configurations, the length should be specified in `touch_sensor_config_t::sample_cfg_num` */ } touch_sensor_config_t; @@ -416,7 +428,10 @@ typedef struct { * */ typedef struct { - bool do_reset; /*!< Whether to reset the benchmark to the channel's latest smooth data */ + bool do_reset; /*!< Whether to reset the benchmark to the channel's latest smooth data, conflict with `do_force_update` */ + bool do_force_update; /*!< Whether to force update the benchmark to the specified value, conflict with `do_reset` */ + uint32_t benchmark; /*!< The specified benchmark value to update, only available when `do_force_update` is true */ + uint32_t sample_cfg_id; /*!< The sample configuration index to update the benchmark, only available when `do_force_update` is true */ } touch_chan_benchmark_config_t; #ifdef __cplusplus diff --git a/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c b/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c index b6ce80970a30..8c602f32c9a4 100644 --- a/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c +++ b/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -142,6 +142,12 @@ static esp_err_t s_touch_convert_to_hal_config(touch_sensor_handle_t sens_handle "at least one sample configuration required"); ESP_RETURN_ON_FALSE(sens_cfg->sample_cfg_num <= TOUCH_SAMPLE_CFG_NUM, ESP_ERR_INVALID_ARG, TAG, "at most %d sample configurations supported", (int)(TOUCH_SAMPLE_CFG_NUM)); + ESP_RETURN_ON_FALSE(sens_cfg->trigger_rise_cnt <= sens_cfg->sample_cfg_num, ESP_ERR_INVALID_ARG, TAG, + "trigger_rise_cnt should within 0 ~ sample_cfg_num"); +#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP_REV_MIN_FULL < 300 + ESP_RETURN_ON_FALSE(sens_cfg->trigger_rise_cnt < 2, ESP_ERR_INVALID_ARG, TAG, + "this target do not support trigger_rise_cnt > 1"); +#endif /* Get the source clock frequency for the first time */ if (!sens_handle->src_freq_hz) { @@ -166,10 +172,14 @@ static esp_err_t s_touch_convert_to_hal_config(touch_sensor_handle_t sens_handle ESP_RETURN_ON_FALSE(hal_cfg->timeout_ticks <= TOUCH_LL_TIMEOUT_MAX, ESP_ERR_INVALID_ARG, TAG, "max_meas_time_ms should within %"PRIu32, TOUCH_LL_TIMEOUT_MAX / src_freq_mhz); hal_cfg->sample_cfg_num = sens_cfg->sample_cfg_num; + hal_cfg->trigger_rise_cnt = sens_cfg->trigger_rise_cnt ? sens_cfg->trigger_rise_cnt : (sens_cfg->sample_cfg_num == 1 ? 1 : 2); hal_cfg->output_mode = sens_cfg->output_mode; for (uint32_t smp_cfg_id = 0; smp_cfg_id < sens_cfg->sample_cfg_num; smp_cfg_id++) { const touch_sensor_sample_config_t *sample_cfg = &(sens_cfg->sample_cfg[smp_cfg_id]); + if (sample_cfg->bypass_shield_output) { + ESP_LOGW(TAG, "bypass_shield_output is deprecated and taken no effect"); + } ESP_RETURN_ON_FALSE(sample_cfg->div_num > 0, ESP_ERR_INVALID_ARG, TAG, "div_num can't be 0"); /* Assign the hal configurations */ @@ -278,13 +288,6 @@ esp_err_t touch_priv_channel_read_data(touch_channel_handle_t chan_handle, touch return ESP_OK; } -void touch_priv_config_benchmark(touch_channel_handle_t chan_handle, const touch_chan_benchmark_config_t *benchmark_cfg) -{ - if (benchmark_cfg->do_reset) { - touch_ll_reset_chan_benchmark(BIT(chan_handle->id)); - } -} - /****************************************************************************** * Scope: public APIs * ******************************************************************************/ @@ -322,6 +325,24 @@ esp_err_t touch_sensor_config_filter(touch_sensor_handle_t sens_handle, const to return ret; } +esp_err_t touch_channel_config_benchmark(touch_channel_handle_t chan_handle, const touch_chan_benchmark_config_t *benchmark_cfg) +{ + TOUCH_NULL_POINTER_CHECK_ISR(chan_handle); + TOUCH_NULL_POINTER_CHECK_ISR(benchmark_cfg); +#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP_REV_MIN_FULL < 300 + ESP_RETURN_ON_FALSE_ISR(!benchmark_cfg->do_force_update, ESP_ERR_INVALID_ARG, TAG, "this target do not support force update benchmark"); +#else + ESP_RETURN_ON_FALSE_ISR(benchmark_cfg->do_reset != benchmark_cfg->do_force_update, ESP_ERR_INVALID_ARG, TAG, "do_reset and do_force_update cannot be both true"); +#endif + if (benchmark_cfg->do_reset) { + touch_ll_reset_chan_benchmark(BIT(chan_handle->id)); + } + if (benchmark_cfg->do_force_update) { + touch_ll_force_update_benchmark(chan_handle->id, benchmark_cfg->sample_cfg_id, benchmark_cfg->benchmark); + } + return ESP_OK; +} + esp_err_t touch_sensor_config_sleep_wakeup(touch_sensor_handle_t sens_handle, const touch_sleep_config_t *sleep_cfg) { TOUCH_NULL_POINTER_CHECK(sens_handle); diff --git a/components/esp_driver_touch_sens/linker.lf b/components/esp_driver_touch_sens/linker.lf index 9dbc60f17533..14865d42cd11 100644 --- a/components/esp_driver_touch_sens/linker.lf +++ b/components/esp_driver_touch_sens/linker.lf @@ -5,6 +5,5 @@ entries: touch_sens_common: touch_sensor_start_continuous_scanning (noflash) touch_sens_common: touch_sensor_stop_continuous_scanning (noflash) touch_sens_common: touch_channel_read_data (noflash) - touch_sens_common: touch_channel_config_benchmark (noflash) touch_sens_version_specific: touch_priv_channel_read_data (noflash) - touch_sens_version_specific: touch_priv_config_benchmark (noflash) + touch_sens_version_specific: touch_channel_config_benchmark (noflash) diff --git a/components/esp_driver_touch_sens/test_apps/touch_sens/main/test_touch_sens_common.c b/components/esp_driver_touch_sens/test_apps/touch_sens/main/test_touch_sens_common.c index 255f979133ef..30da129aa25b 100644 --- a/components/esp_driver_touch_sens/test_apps/touch_sens/main/test_touch_sens_common.c +++ b/components/esp_driver_touch_sens/test_apps/touch_sens/main/test_touch_sens_common.c @@ -146,7 +146,7 @@ TEST_CASE("touch_sens_active_inactive_test", "[touch]") /* Configuring the filter */ touch_sensor_filter_config_t filter_cfg = TOUCH_SENSOR_DEFAULT_FILTER_CONFIG(); TEST_ESP_OK(touch_sensor_config_filter(touch, &filter_cfg)); - TEST_ESP_OK(touch_sensor_new_channel(touch, 0, &s_chan_cfg, &touch_chan)); + TEST_ESP_OK(touch_sensor_new_channel(touch, TOUCH_MIN_CHAN_ID, &s_chan_cfg, &touch_chan)); /* Connect the touch channels to the internal capacitor */ touch_ll_enable_internal_capacitor(true); diff --git a/components/esp_driver_tsens/test_apps/temperature_sensor/pytest_temperature_sensor.py b/components/esp_driver_tsens/test_apps/temperature_sensor/pytest_temperature_sensor.py index 437164c0a8ad..d6e2808a97f2 100644 --- a/components/esp_driver_tsens/test_apps/temperature_sensor/pytest_temperature_sensor.py +++ b/components/esp_driver_tsens/test_apps/temperature_sensor/pytest_temperature_sensor.py @@ -38,9 +38,9 @@ def test_temperature_sensor_cbs(dut: Dut) -> None: @pytest.mark.esp32s3 @pytest.mark.esp32c2 @pytest.mark.esp32c6 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize('count', [2], indirect=True) def test_temperature_phy_cases(case_tester: CaseTester) -> None: # type: ignore for case in case_tester.test_menu: - if case.attributes.get('test_env', 'wifi_two_dut') == 'wifi_two_dut': + if case.attributes.get('test_env', 'two_duts') == 'two_duts': case_tester.run_all_multi_dev_cases(case=case, reset=True) diff --git a/components/esp_driver_uart/include/driver/uart.h b/components/esp_driver_uart/include/driver/uart.h index ec753d4955f0..ceb48cdf411b 100644 --- a/components/esp_driver_uart/include/driver/uart.h +++ b/components/esp_driver_uart/include/driver/uart.h @@ -603,7 +603,9 @@ esp_err_t uart_flush_input(uart_port_t uart_num); esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t* size); /** - * @brief UART get TX ring buffer free space size + * @brief UART get TX ring buffer free space size for the next data to be enqueued + * + * It returns the tight conservative bound for NOSPLIT ring buffer overall enqueueable payload across up to two chunks. * * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). * @param size Pointer of size_t to accept the free space size diff --git a/components/esp_driver_uart/src/uart.c b/components/esp_driver_uart/src/uart.c index a7069f870ca9..045a7f4cfe84 100644 --- a/components/esp_driver_uart/src/uart.c +++ b/components/esp_driver_uart/src/uart.c @@ -143,7 +143,6 @@ typedef struct { bool coll_det_flg; /*!< UART collision detection flag */ bool rx_always_timeout_flg; /*!< UART always detect rx timeout flag */ int rx_buffered_len; /*!< UART cached data length */ - int rx_buf_size; /*!< RX ring buffer size */ bool rx_buffer_full_flg; /*!< RX ring buffer full flag. */ uint8_t *rx_data_buf; /*!< Data buffer to stash FIFO data*/ uint8_t rx_stash_len; /*!< stashed data length.(When using flow control, after reading out FIFO data, if we fail to push to buffer, we can just stash them.) */ @@ -153,8 +152,8 @@ typedef struct { bool tx_waiting_fifo; /*!< this flag indicates that some task is waiting for FIFO empty interrupt, used to send all data without any data buffer*/ uint8_t *tx_ptr; /*!< TX data pointer to push to FIFO in TX buffer mode*/ uart_tx_data_t *tx_head; /*!< TX data pointer to head of the current buffer in TX ring buffer*/ - uint32_t tx_len_tot; /*!< Total length of current item in ring buffer*/ - uint32_t tx_len_cur; + uint32_t trans_total_remaining_len; /*!< Remaining data length of the current processing transaction in TX ring buffer*/ + uint32_t trans_chunk_remaining_len; /*!< Remaining data length of the current processing chunk of the transaction in TX ring buffer*/ uint8_t tx_brk_flg; /*!< Flag to indicate to send a break signal in the end of the item sending procedure */ uint8_t tx_brk_len; /*!< TX break signal cycle length/number */ uint8_t tx_waiting_brk; /*!< Flag to indicate that TX FIFO is ready to send break signal after FIFO is empty, do not push data into TX FIFO right now.*/ @@ -219,6 +218,10 @@ static void uart_module_enable(uart_port_t uart_num) uart_ll_enable_bus_clock(uart_num, true); } if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) { + // Workaround: Set RX signal to high to avoid false RX BRK_DET interrupt raised after register reset + if (uart_context[uart_num].rx_io_num == -1) { + esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), false); + } HP_UART_BUS_CLK_ATOMIC() { uart_ll_reset_register(uart_num); } @@ -249,6 +252,16 @@ static void uart_module_enable(uart_port_t uart_num) } #if (SOC_UART_LP_NUM >= 1) else { + // Workaround: Set RX signal to high to avoid false RX BRK_DET interrupt raised after register reset + if (uart_context[uart_num].rx_io_num == -1) { // if RX pin is already configured, then workaround not needed, skip +#if SOC_LP_GPIO_MATRIX_SUPPORTED + lp_gpio_connect_in_signal(LP_GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), false); +#else + // the signal is directly connected to its LP IO pin, the only way is to enable its pullup + uint32_t io_num = uart_periph_signal[uart_num].pins[SOC_UART_RX_PIN_IDX].default_gpio; + gpio_pullup_en(io_num); +#endif + } LP_UART_BUS_CLK_ATOMIC() { lp_uart_ll_enable_bus_clock(TO_LP_UART_NUM(uart_num), true); lp_uart_ll_reset_register(TO_LP_UART_NUM(uart_num)); @@ -714,18 +727,26 @@ static bool uart_try_set_iomux_pin(uart_port_t uart_num, int io_num, uint32_t id } rtc_gpio_init(io_num); rtc_gpio_iomux_func_sel(io_num, upin->iomux_func); + // undo the workaround done in uart_module_enable for RX pin +#if !SOC_LP_GPIO_MATRIX_SUPPORTED + if (upin->input) { + gpio_pullup_dis(io_num); + } +#endif } #endif return true; } -static void uart_release_pin(uart_port_t uart_num) +static void uart_release_pin(uart_port_t uart_num, bool release_tx, bool release_rx, bool release_rts, bool release_cts) { if (uart_num >= UART_NUM_MAX) { return; } - if (uart_context[uart_num].tx_io_num >= 0) { + + uint32_t released_io_mask = 0; + if (release_tx && uart_context[uart_num].tx_io_num >= 0) { gpio_output_disable(uart_context[uart_num].tx_io_num); #if (SOC_UART_LP_NUM >= 1) if (!(uart_num < SOC_UART_HP_NUM)) { @@ -735,9 +756,12 @@ static void uart_release_pin(uart_port_t uart_num) #if CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND || CONFIG_PM_SLP_DISABLE_GPIO gpio_sleep_sel_en(uart_context[uart_num].tx_io_num); // re-enable the switch to the sleep configuration to save power consumption #endif + + released_io_mask |= BIT64(uart_context[uart_num].tx_io_num); + uart_context[uart_num].tx_io_num = -1; } - if (uart_context[uart_num].rx_io_num >= 0) { + if (release_rx && uart_context[uart_num].rx_io_num >= 0) { if (uart_num < SOC_UART_HP_NUM) { esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), false); } @@ -752,18 +776,24 @@ static void uart_release_pin(uart_port_t uart_num) #if CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND || CONFIG_PM_SLP_DISABLE_GPIO gpio_sleep_sel_en(uart_context[uart_num].rx_io_num); // re-enable the switch to the sleep configuration to save power consumption #endif + + released_io_mask |= BIT64(uart_context[uart_num].rx_io_num); + uart_context[uart_num].rx_io_num = -1; } - if (uart_context[uart_num].rts_io_num >= 0) { + if (release_rts && uart_context[uart_num].rts_io_num >= 0) { gpio_output_disable(uart_context[uart_num].rts_io_num); #if (SOC_UART_LP_NUM >= 1) if (!(uart_num < SOC_UART_HP_NUM)) { rtc_gpio_deinit(uart_context[uart_num].rts_io_num); } #endif + + released_io_mask |= BIT64(uart_context[uart_num].rts_io_num); + uart_context[uart_num].rts_io_num = -1; } - if (uart_context[uart_num].cts_io_num >= 0) { + if (release_cts && uart_context[uart_num].cts_io_num >= 0) { if (uart_num < SOC_UART_HP_NUM) { esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), false); } @@ -775,15 +805,13 @@ static void uart_release_pin(uart_port_t uart_num) rtc_gpio_deinit(uart_context[uart_num].cts_io_num); } #endif - } - esp_gpio_revoke(uart_context[uart_num].io_reserved_mask); + released_io_mask |= BIT64(uart_context[uart_num].cts_io_num); + uart_context[uart_num].cts_io_num = -1; + } - uart_context[uart_num].tx_io_num = -1; - uart_context[uart_num].rx_io_num = -1; - uart_context[uart_num].rts_io_num = -1; - uart_context[uart_num].cts_io_num = -1; - uart_context[uart_num].io_reserved_mask = 0; + esp_gpio_revoke(uart_context[uart_num].io_reserved_mask & released_io_mask); + uart_context[uart_num].io_reserved_mask &= ~released_io_mask; } esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int rts_io_num, int cts_io_num) @@ -818,7 +846,7 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r #endif // First, release previously configured IOs if there is - uart_release_pin(uart_num); + uart_release_pin(uart_num, (tx_io_num >= 0), (rx_io_num >= 0), (rts_io_num >= 0), (cts_io_num >= 0)); // Potential IO reserved mask uint64_t io_reserve_mask = 0; @@ -1146,15 +1174,15 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param) //That would cause a watch_dog reset because empty interrupt happens so often. //Although this is a loop in ISR, this loop will execute at most 128 turns. while (tx_fifo_rem) { - if (p_uart->tx_len_tot == 0 || p_uart->tx_ptr == NULL || p_uart->tx_len_cur == 0) { + if (p_uart->trans_total_remaining_len == 0 || p_uart->tx_ptr == NULL || p_uart->trans_chunk_remaining_len == 0) { size_t size; p_uart->tx_head = (uart_tx_data_t *) xRingbufferReceiveFromISR(p_uart->tx_ring_buf, &size); if (p_uart->tx_head) { //The first item is the data description //Get the first item to get the data information - if (p_uart->tx_len_tot == 0) { + if (p_uart->trans_total_remaining_len == 0) { p_uart->tx_ptr = NULL; - p_uart->tx_len_tot = p_uart->tx_head->tx_data.size; + p_uart->trans_total_remaining_len = p_uart->tx_head->tx_data.size; if (p_uart->tx_head->type == UART_DATA_BREAK) { p_uart->tx_brk_flg = 1; p_uart->tx_brk_len = p_uart->tx_head->tx_data.brk_len; @@ -1166,22 +1194,22 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param) //Update the TX item pointer, we will need this to return item to buffer. p_uart->tx_ptr = (uint8_t *)p_uart->tx_head; en_tx_flg = true; - p_uart->tx_len_cur = size; + p_uart->trans_chunk_remaining_len = size; } } else { //Can not get data from ring buffer, return; break; } } - if (p_uart->tx_len_tot > 0 && p_uart->tx_ptr && p_uart->tx_len_cur > 0) { + if (p_uart->trans_total_remaining_len > 0 && p_uart->tx_ptr && p_uart->trans_chunk_remaining_len > 0) { // To fill the TX FIFO. uint32_t send_len = uart_enable_tx_write_fifo(uart_num, (const uint8_t *) p_uart->tx_ptr, - MIN(p_uart->tx_len_cur, tx_fifo_rem)); + MIN(p_uart->trans_chunk_remaining_len, tx_fifo_rem)); p_uart->tx_ptr += send_len; - p_uart->tx_len_tot -= send_len; - p_uart->tx_len_cur -= send_len; + p_uart->trans_total_remaining_len -= send_len; + p_uart->trans_chunk_remaining_len -= send_len; tx_fifo_rem -= send_len; - if (p_uart->tx_len_cur == 0) { + if (p_uart->trans_chunk_remaining_len == 0) { //Return item to ring buffer. vRingbufferReturnItemFromISR(p_uart->tx_ring_buf, p_uart->tx_head, &HPTaskAwoken); need_yield |= (HPTaskAwoken == pdTRUE); @@ -1189,7 +1217,7 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param) p_uart->tx_ptr = NULL; //Sending item done, now we need to send break if there is a record. //Set TX break signal after FIFO is empty - if (p_uart->tx_len_tot == 0 && p_uart->tx_brk_flg == 1) { + if (p_uart->trans_total_remaining_len == 0 && p_uart->tx_brk_flg == 1) { uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE); UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); uart_hal_tx_break(&(uart_context[uart_num].hal), p_uart->tx_brk_len); @@ -1516,6 +1544,8 @@ int uart_tx_chars(uart_port_t uart_num, const char *buffer, uint32_t len) return tx_len; } +// Per transaction in the ring buffer: +// A data description item, followed by one or more data chunk items static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool brk_en, int brk_len) { if (size == 0) { @@ -1530,7 +1560,6 @@ static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool #endif p_uart_obj[uart_num]->coll_det_flg = false; if (p_uart_obj[uart_num]->tx_buf_size > 0) { - size_t max_size = xRingbufferGetMaxItemSize(p_uart_obj[uart_num]->tx_ring_buf); int offset = 0; uart_tx_data_t evt; evt.tx_data.size = size; @@ -1542,11 +1571,14 @@ static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool } xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *) &evt, sizeof(uart_tx_data_t), portMAX_DELAY); while (size > 0) { - size_t send_size = size > max_size / 2 ? max_size / 2 : size; - xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *)(src + offset), send_size, portMAX_DELAY); - size -= send_size; - offset += send_size; - uart_enable_tx_intr(uart_num, 1, UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT)); + size_t free_size = xRingbufferGetCurFreeSize(p_uart_obj[uart_num]->tx_ring_buf); + size_t send_size = MIN(size, free_size); + if (send_size > 0) { + xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *)(src + offset), send_size, portMAX_DELAY); + size -= send_size; + offset += send_size; + uart_enable_tx_intr(uart_num, 1, UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT)); + } } } else { while (size) { @@ -1670,7 +1702,79 @@ esp_err_t uart_get_tx_buffer_free_size(uart_port_t uart_num, size_t *size) ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error"); ESP_RETURN_ON_FALSE((p_uart_obj[uart_num]), ESP_ERR_INVALID_ARG, UART_TAG, "uart driver error"); ESP_RETURN_ON_FALSE((size != NULL), ESP_ERR_INVALID_ARG, UART_TAG, "arg pointer is NULL"); - *size = p_uart_obj[uart_num]->tx_buf_size - p_uart_obj[uart_num]->tx_len_tot; + + // If tx buffer is disabled or ring buffer is full, overall enqueueable payload is 0 + if (p_uart_obj[uart_num]->tx_buf_size == 0 || xRingbufferGetCurFreeSize(p_uart_obj[uart_num]->tx_ring_buf) == 0) { + *size = 0; + return ESP_OK; + } + + // Tight conservative bound for NOSPLIT ring buffer overall enqueueable payload across up to two segments + const size_t RINGBUF_ITEM_HDR_SIZE = 8; // per public ringbuf API docs + + // Per-item cap in current state and basis to infer minimal buffer size + size_t max_item = xRingbufferGetMaxItemSize(p_uart_obj[uart_num]->tx_ring_buf); + + // Get current ring buffer pointer offsets and items waiting to detect empty + UBaseType_t off_free = 0; + UBaseType_t off_acq = 0; + UBaseType_t items_waiting = 0; + vRingbufferGetInfo(p_uart_obj[uart_num]->tx_ring_buf, &off_free, NULL, NULL, &off_acq, &items_waiting); + + // Minimal possible total buffer size for NOSPLIT: see ringbuf initialization logic + // xMaxItemSize = ALIGN4(xSize/2) - header => xSize_min = 2 * (xMaxItemSize + header - up_to_3_alignment) + size_t buf_size_min = 2 * (max_item + RINGBUF_ITEM_HDR_SIZE - 3); + buf_size_min &= ~((size_t)3); // align down to 4 bytes + + size_t total_payload = 0; + if (off_acq == off_free && items_waiting == 0) { + // Empty buffer: conservatively treat as a single large contiguous segment + total_payload = p_uart_obj[uart_num]->tx_buf_size - RINGBUF_ITEM_HDR_SIZE; + } else if (off_acq <= off_free) { + // Single contiguous free segment + size_t seg = (size_t)off_free - (size_t)off_acq; + if (seg > RINGBUF_ITEM_HDR_SIZE) { + size_t usable = seg - RINGBUF_ITEM_HDR_SIZE; + usable &= ~((size_t)3); + if (usable > max_item) { + usable = max_item; + } + total_payload = usable; + } + } else { + // Free space wraps: two segments [acq..tail) and [head..free) + size_t seg1 = buf_size_min - (size_t)off_acq; + size_t seg2 = (size_t)off_free; // from head (offset 0) to free + size_t payload1 = 0; + if (seg1 > RINGBUF_ITEM_HDR_SIZE) { + size_t usable1 = seg1 - RINGBUF_ITEM_HDR_SIZE; + usable1 &= ~((size_t)3); + if (usable1 > max_item) { + usable1 = max_item; + } + payload1 = usable1; + } + size_t payload2 = 0; + if (seg2 > RINGBUF_ITEM_HDR_SIZE) { + size_t usable2 = seg2 - RINGBUF_ITEM_HDR_SIZE; + usable2 &= ~((size_t)3); + if (usable2 > max_item) { + usable2 = max_item; + } + payload2 = usable2; + } + total_payload = payload1 + payload2; + } + + // Subtract the cost of the transaction's data description item (header + aligned struct) + size_t desc_cost = RINGBUF_ITEM_HDR_SIZE + (((sizeof(uart_tx_data_t)) + 3) & ~((size_t)3)); + if (total_payload > desc_cost) { + total_payload -= desc_cost; + } else { + total_payload = 0; + } + + *size = total_payload; return ESP_OK; } @@ -1846,7 +1950,8 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b p_uart_obj[uart_num]->event_queue_size = event_queue_size; p_uart_obj[uart_num]->tx_ptr = NULL; p_uart_obj[uart_num]->tx_head = NULL; - p_uart_obj[uart_num]->tx_len_tot = 0; + p_uart_obj[uart_num]->trans_total_remaining_len = 0; + p_uart_obj[uart_num]->trans_chunk_remaining_len = 0; p_uart_obj[uart_num]->tx_brk_flg = 0; p_uart_obj[uart_num]->tx_brk_len = 0; p_uart_obj[uart_num]->tx_waiting_brk = 0; @@ -1867,12 +1972,6 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b return ESP_FAIL; } - uart_intr_config_t uart_intr = { - .intr_enable_mask = UART_INTR_CONFIG_FLAG, - .rxfifo_full_thresh = UART_THRESHOLD_NUM(uart_num, UART_FULL_THRESH_DEFAULT), - .rx_timeout_thresh = UART_TOUT_THRESH_DEFAULT, - .txfifo_empty_intr_thresh = UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT), - }; uart_module_enable(uart_num); uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK); uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK); @@ -1882,6 +1981,12 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b &p_uart_obj[uart_num]->intr_handle); ESP_GOTO_ON_ERROR(ret, err, UART_TAG, "Could not allocate an interrupt for UART"); + uart_intr_config_t uart_intr = { + .intr_enable_mask = UART_INTR_CONFIG_FLAG, + .rxfifo_full_thresh = UART_THRESHOLD_NUM(uart_num, UART_FULL_THRESH_DEFAULT), + .rx_timeout_thresh = UART_TOUT_THRESH_DEFAULT, + .txfifo_empty_intr_thresh = UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT), + }; ret = uart_intr_config(uart_num, &uart_intr); ESP_GOTO_ON_ERROR(ret, err, UART_TAG, "Could not configure the interrupt for UART"); @@ -1901,7 +2006,7 @@ esp_err_t uart_driver_delete(uart_port_t uart_num) return ESP_OK; } - uart_release_pin(uart_num); + uart_release_pin(uart_num, true, true, true, true); esp_intr_free(p_uart_obj[uart_num]->intr_handle); uart_disable_rx_intr(uart_num); diff --git a/components/esp_driver_uart/test_apps/uart/main/test_uart.c b/components/esp_driver_uart/test_apps/uart/main/test_uart.c index 78671ae7dd93..be08ee4d60bc 100644 --- a/components/esp_driver_uart/test_apps/uart/main/test_uart.c +++ b/components/esp_driver_uart/test_apps/uart/main/test_uart.c @@ -419,23 +419,73 @@ TEST_CASE("uart tx with ringbuffer test", "[uart]") rd_data[i] = 0; } - size_t tx_buffer_free_space; - uart_get_tx_buffer_free_size(uart_num, &tx_buffer_free_space); - TEST_ASSERT_EQUAL_INT(2048, tx_buffer_free_space); // full tx buffer space is free uart_write_bytes(uart_num, (const char *)wr_data, 1024); - uart_get_tx_buffer_free_size(uart_num, &tx_buffer_free_space); - TEST_ASSERT_LESS_THAN(2048, tx_buffer_free_space); // tx transmit in progress: tx buffer has content - TEST_ASSERT_GREATER_OR_EQUAL(1024, tx_buffer_free_space); uart_wait_tx_done(uart_num, portMAX_DELAY); - uart_get_tx_buffer_free_size(uart_num, &tx_buffer_free_space); - TEST_ASSERT_EQUAL_INT(2048, tx_buffer_free_space); // tx done: tx buffer back to empty + uart_read_bytes(uart_num, rd_data, 1024, pdMS_TO_TICKS(1000)); TEST_ASSERT_EQUAL_HEX8_ARRAY(wr_data, rd_data, 1024); + TEST_ESP_OK(uart_driver_delete(uart_num)); free(rd_data); free(wr_data); } +TEST_CASE("uart tx ring buffer free space test", "[uart]") +{ + uart_port_param_t port_param = {}; + TEST_ASSERT(port_select(&port_param)); + // This is a test on the driver API, no need to test for both HP/LP uart port, call port_select() to be compatible with pytest + // Let's only test on HP UART + if (port_param.port_num < SOC_UART_HP_NUM) { + uart_port_t uart_num = port_param.port_num; + uint8_t *rd_data = (uint8_t *)malloc(1024); + TEST_ASSERT_NOT_NULL(rd_data); + uint8_t *wr_data = (uint8_t *)malloc(2048); + TEST_ASSERT_NOT_NULL(wr_data); + uart_config_t uart_config = { + .baud_rate = 2000000, + .data_bits = UART_DATA_8_BITS, + .parity = UART_PARITY_DISABLE, + .stop_bits = UART_STOP_BITS_1, + .flow_ctrl = UART_HW_FLOWCTRL_CTS_RTS, + .rx_flow_ctrl_thresh = port_param.rx_flow_ctrl_thresh, + .source_clk = port_param.default_src_clk, + }; + uart_wait_tx_idle_polling(uart_num); + TEST_ESP_OK(uart_param_config(uart_num, &uart_config)); + TEST_ESP_OK(uart_driver_install(uart_num, 256, 1024 * 2, 20, NULL, 0)); + // Let CTS be high, so that transmission is blocked + esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, uart_periph_signal[uart_num].pins[SOC_UART_CTS_PIN_IDX].signal, false); + + // When nothing pushed to the TX ring buffer, the free space should be the full capacity + size_t tx_buffer_free_space; + uart_get_tx_buffer_free_size(uart_num, &tx_buffer_free_space); + TEST_ASSERT_EQUAL_INT(2020, tx_buffer_free_space); // no-split ring buffer: 2048 - 20 (data description item) - 8 (header) + + // Push 1024 bytes to the TX ring buffer + uart_write_bytes(uart_num, (const char *)wr_data, 1024); // two chunks + vTaskDelay(pdMS_TO_TICKS(500)); + uart_get_tx_buffer_free_size(uart_num, &tx_buffer_free_space); + TEST_ASSERT_LESS_THAN(2020, tx_buffer_free_space); // tx buffer has content + TEST_ASSERT_GREATER_OR_EQUAL(952, tx_buffer_free_space); + + // Fill the remaining space in the TX ring buffer + uart_write_bytes(uart_num, (const char *)wr_data, tx_buffer_free_space); + uart_get_tx_buffer_free_size(uart_num, &tx_buffer_free_space); + TEST_ASSERT_EQUAL_INT(0, tx_buffer_free_space); // tx buffer is full + + // Let CTS be low, so that transmission is unblocked + esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, uart_periph_signal[uart_num].pins[SOC_UART_CTS_PIN_IDX].signal, false); + uart_wait_tx_done(uart_num, portMAX_DELAY); + uart_get_tx_buffer_free_size(uart_num, &tx_buffer_free_space); + TEST_ASSERT_EQUAL_INT(2020, tx_buffer_free_space); // tx buffer is back to full capacity + + TEST_ESP_OK(uart_driver_delete(uart_num)); + free(rd_data); + free(wr_data); + } +} + TEST_CASE("uart int state restored after flush", "[uart]") { uart_port_param_t port_param = {}; diff --git a/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c b/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c index 90d8addacf1d..93182763593c 100644 --- a/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c +++ b/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c @@ -182,6 +182,10 @@ static int usb_serial_jtag_rx_char_no_driver(int fd) static ssize_t usb_serial_jtag_write(int fd, const void * data, size_t size) { + if (!usb_serial_jtag_is_connected()) { + // TODO: IDF-14303 + return -1; + } const char *data_c = (const char *)data; /* Even though newlib does stream locking on each individual stream, we need * a dedicated lock if two streams (stdout and stderr) point to the @@ -226,6 +230,10 @@ static void usb_serial_jtag_return_char(int fd, int c) static ssize_t usb_serial_jtag_read(int fd, void* data, size_t size) { + if (!usb_serial_jtag_is_connected()) { + // TODO: IDF-14303 + return -1; + } assert(fd == USJ_LOCAL_FD); char *data_c = (char *) data; size_t received = 0; @@ -349,6 +357,10 @@ static int usb_serial_jtag_wait_tx_done_no_driver(int fd) static int usb_serial_jtag_fsync(int fd) { + if (!usb_serial_jtag_is_connected()) { + // TODO: IDF-14303 + return -1; + } _lock_acquire_recursive(&s_ctx.write_lock); int r = s_ctx.fsync_func(fd); _lock_release_recursive(&s_ctx.write_lock); diff --git a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/main/test_usb_serial_jtag.c b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/main/test_usb_serial_jtag.c index 9d5ced30117d..88e91fd68780 100644 --- a/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/main/test_usb_serial_jtag.c +++ b/components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/main/test_usb_serial_jtag.c @@ -113,6 +113,7 @@ TEST_CASE("see if fsync appears to work", "[usb_serial_jtag]") start_us = esp_timer_get_time(); fsync(0); end_us = esp_timer_get_time(); + vTaskDelay(pdMS_TO_TICKS(500)); printf("With data in queue: %d us\n", (int)(end_us - start_us)); TEST_ASSERT_GREATER_THAN_INT(1000, end_us - start_us); TEST_ASSERT_LESS_THAN_INT(45000, end_us - start_us); //50ms means fsync hit a timeout diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig index dba0596f5b70..a39c461ef89a 100644 --- a/components/esp_hw_support/Kconfig +++ b/components/esp_hw_support/Kconfig @@ -129,12 +129,11 @@ menu "Hardware Settings" config ESP_SLEEP_GPIO_RESET_WORKAROUND bool "light sleep GPIO reset workaround" - default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || \ - IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32C5 + default y if !(IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2) select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE help - esp32c2, esp32c3, esp32s3, esp32c5, esp32c6 and esp32h2 will reset at wake-up if GPIO is received - a small electrostatic pulse during light sleep, with specific condition + All existing chips except esp32 and esp32s2 will reset on wake-up if a GPIO receives + a small electrostatic pulse during light sleep, with specific conditions. - GPIO needs to be configured as input-mode only - The pin receives a small electrostatic pulse, and reset occurs when the pulse diff --git a/components/esp_hw_support/dma/dma2d.c b/components/esp_hw_support/dma/dma2d.c index 86666610a106..bc31ef81b010 100644 --- a/components/esp_hw_support/dma/dma2d.c +++ b/components/esp_hw_support/dma/dma2d.c @@ -23,7 +23,6 @@ #include "hal/dma2d_ll.h" #include "soc/dma2d_channel.h" #include "soc/dma2d_periph.h" -#include "soc/soc_caps.h" #include "esp_bit_defs.h" /** @@ -365,20 +364,20 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl _lock_acquire(&s_platform.mutex); if (!s_platform.groups[group_id]) { dma2d_group_t *pre_alloc_group = heap_caps_calloc(1, sizeof(dma2d_group_t), DMA2D_MEM_ALLOC_CAPS); - dma2d_tx_channel_t *pre_alloc_tx_channels = heap_caps_calloc(SOC_DMA2D_TX_CHANNELS_PER_GROUP, sizeof(dma2d_tx_channel_t), DMA2D_MEM_ALLOC_CAPS); - dma2d_rx_channel_t *pre_alloc_rx_channels = heap_caps_calloc(SOC_DMA2D_RX_CHANNELS_PER_GROUP, sizeof(dma2d_rx_channel_t), DMA2D_MEM_ALLOC_CAPS); + dma2d_tx_channel_t *pre_alloc_tx_channels = heap_caps_calloc(DMA2D_LL_TX_CHANNELS_PER_GROUP, sizeof(dma2d_tx_channel_t), DMA2D_MEM_ALLOC_CAPS); + dma2d_rx_channel_t *pre_alloc_rx_channels = heap_caps_calloc(DMA2D_LL_RX_CHANNELS_PER_GROUP, sizeof(dma2d_rx_channel_t), DMA2D_MEM_ALLOC_CAPS); if (pre_alloc_group && pre_alloc_tx_channels && pre_alloc_rx_channels) { pre_alloc_group->group_id = group_id; pre_alloc_group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; TAILQ_INIT(&pre_alloc_group->pending_trans_tailq); - pre_alloc_group->tx_channel_free_mask = (1 << SOC_DMA2D_TX_CHANNELS_PER_GROUP) - 1; - pre_alloc_group->rx_channel_free_mask = (1 << SOC_DMA2D_RX_CHANNELS_PER_GROUP) - 1; + pre_alloc_group->tx_channel_free_mask = (1 << DMA2D_LL_TX_CHANNELS_PER_GROUP) - 1; + pre_alloc_group->rx_channel_free_mask = (1 << DMA2D_LL_RX_CHANNELS_PER_GROUP) - 1; pre_alloc_group->tx_channel_reserved_mask = dma2d_tx_channel_reserved_mask[group_id]; pre_alloc_group->rx_channel_reserved_mask = dma2d_rx_channel_reserved_mask[group_id]; pre_alloc_group->tx_periph_m2m_free_id_mask = DMA2D_LL_TX_CHANNEL_PERIPH_M2M_AVAILABLE_ID_MASK; pre_alloc_group->rx_periph_m2m_free_id_mask = DMA2D_LL_RX_CHANNEL_PERIPH_M2M_AVAILABLE_ID_MASK; pre_alloc_group->intr_priority = -1; - for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) { pre_alloc_group->tx_chans[i] = &pre_alloc_tx_channels[i]; dma2d_tx_channel_t *tx_chan = pre_alloc_group->tx_chans[i]; tx_chan->base.group = pre_alloc_group; @@ -386,7 +385,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl tx_chan->base.direction = DMA2D_CHANNEL_DIRECTION_TX; tx_chan->base.spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; } - for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) { pre_alloc_group->rx_chans[i] = &pre_alloc_rx_channels[i]; dma2d_rx_channel_t *rx_chan = pre_alloc_group->rx_chans[i]; rx_chan->base.group = pre_alloc_group; @@ -435,7 +434,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl // Allocate TX and RX interrupts if (s_platform.groups[group_id]) { - for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) { dma2d_rx_channel_t *rx_chan = s_platform.groups[group_id]->rx_chans[i]; if (rx_chan->base.intr == NULL) { ret = esp_intr_alloc_intrstatus(dma2d_periph_signals.groups[group_id].rx_irq_id[i], @@ -450,7 +449,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl } } - for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) { dma2d_tx_channel_t *tx_chan = s_platform.groups[group_id]->tx_chans[i]; if (tx_chan->base.intr == NULL) { ret = esp_intr_alloc_intrstatus(dma2d_periph_signals.groups[group_id].tx_irq_id[i], @@ -510,12 +509,12 @@ esp_err_t dma2d_release_pool(dma2d_pool_handle_t dma2d_pool) } if (do_deinitialize) { - for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) { if (dma2d_group->rx_chans[i]->base.intr) { esp_intr_free(dma2d_group->rx_chans[i]->base.intr); } } - for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) { if (dma2d_group->tx_chans[i]->base.intr) { esp_intr_free(dma2d_group->tx_chans[i]->base.intr); } @@ -983,7 +982,7 @@ esp_err_t dma2d_force_end(dma2d_trans_t *trans, bool *need_yield) // Stop the RX channel and its bundled TX channels first dma2d_stop(&rx_chan->base); uint32_t tx_chans = rx_chan->bundled_tx_channel_mask; - for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) { if (tx_chans & (1 << i)) { dma2d_stop(&group->tx_chans[i]->base); } diff --git a/components/esp_hw_support/dma/dma2d_priv.h b/components/esp_hw_support/dma/dma2d_priv.h index dcf46bf328e9..074553c052af 100644 --- a/components/esp_hw_support/dma/dma2d_priv.h +++ b/components/esp_hw_support/dma/dma2d_priv.h @@ -57,8 +57,8 @@ struct dma2d_group_t { uint8_t rx_channel_reserved_mask; // Bit mask indicating the being reserved RX channels uint32_t tx_periph_m2m_free_id_mask; // Bit mask indicating the available TX M2M peripheral selelction IDs at the moment uint32_t rx_periph_m2m_free_id_mask; // Bit mask indicating the available RX M2M peripheral selelction IDs at the moment - dma2d_tx_channel_t *tx_chans[SOC_DMA2D_TX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA TX channels - dma2d_rx_channel_t *rx_chans[SOC_DMA2D_RX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA RX channels + dma2d_tx_channel_t *tx_chans[DMA2D_LL_TX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA TX channels + dma2d_rx_channel_t *rx_chans[DMA2D_LL_RX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA RX channels int intr_priority; // All channels in the same group should share the same interrupt priority }; diff --git a/components/esp_hw_support/include/esp_private/esp_sleep_internal.h b/components/esp_hw_support/include/esp_private/esp_sleep_internal.h index bd4043ad24d6..77867eea6093 100644 --- a/components/esp_hw_support/include/esp_private/esp_sleep_internal.h +++ b/components/esp_hw_support/include/esp_private/esp_sleep_internal.h @@ -74,7 +74,7 @@ esp_err_t esp_sleep_sub_mode_force_disable(esp_sleep_sub_mode_t mode); */ int32_t* esp_sleep_sub_mode_dump_config(FILE *stream); -#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP /** * @brief Isolate all digital IOs except those that are held during deep sleep * diff --git a/components/esp_hw_support/intr_alloc.c b/components/esp_hw_support/intr_alloc.c index f3513163be84..854bb9b9194a 100644 --- a/components/esp_hw_support/intr_alloc.c +++ b/components/esp_hw_support/intr_alloc.c @@ -60,7 +60,7 @@ typedef struct vector_desc_t vector_desc_t; struct shared_vector_desc_t { int disabled: 1; - int source: 8; + int source: 16; volatile uint32_t *statusreg; uint32_t statusmask; intr_handler_t isr; @@ -87,7 +87,7 @@ struct vector_desc_t { int flags: 16; //OR of VECDESC_FL_* defines unsigned int cpu: 1; unsigned int intno: 5; - int source: 8; //Interrupt mux flags, used when not shared + int source: 16; //Interrupt mux flags, used when not shared shared_vector_desc_t *shared_vec_info; //used when VECDESC_FL_SHARED vector_desc_t *next; }; diff --git a/components/esp_hw_support/port/esp32p4/Kconfig.ldo b/components/esp_hw_support/port/esp32p4/Kconfig.ldo index 0e5a20fdd8d4..804f685f87fd 100644 --- a/components/esp_hw_support/port/esp32p4/Kconfig.ldo +++ b/components/esp_hw_support/port/esp32p4/Kconfig.ldo @@ -52,15 +52,15 @@ menu "LDO Regulator Configurations" choice ESP_LDO_VOLTAGE_PSRAM_DOMAIN prompt "PSRAM power domain voltage" depends on ESP_LDO_RESERVE_PSRAM - default ESP_LDO_VOLTAGE_PSRAM_1900_MV + default ESP_LDO_VOLTAGE_PSRAM_1800_MV help Select the voltage used by the PSRAM power domain. - config ESP_LDO_VOLTAGE_PSRAM_1900_MV - bool "1.9V" + config ESP_LDO_VOLTAGE_PSRAM_1800_MV + bool "1.8V" endchoice config ESP_LDO_VOLTAGE_PSRAM_DOMAIN int - default 1900 if ESP_LDO_VOLTAGE_PSRAM_1900_MV + default 1800 if ESP_LDO_VOLTAGE_PSRAM_1800_MV endmenu diff --git a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h index 295c3f818075..41dc4c48873e 100644 --- a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h @@ -11,6 +11,7 @@ #include #include "soc/pmu_struct.h" #include "hal/pmu_hal.h" +#include "sdkconfig.h" #ifdef __cplusplus extern "C" { @@ -330,6 +331,7 @@ typedef struct { } pmu_sleep_digital_config_t; +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 #define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags) { \ .syscntl = { \ .dig_pad_slp_sel = 0, \ @@ -343,6 +345,19 @@ typedef struct { .lp_pad_hold_all = (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \ } \ } +#else // !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 +#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags) { \ + .syscntl = { \ + .dig_pad_slp_sel = 0, \ + } \ +} + +#define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags) { \ + .syscntl = { \ + .dig_pad_slp_sel = 0, \ + } \ +} +#endif typedef struct { struct { diff --git a/components/esp_hw_support/sleep_gpio.c b/components/esp_hw_support/sleep_gpio.c index c1d2fa918e48..2fc517a9a30b 100644 --- a/components/esp_hw_support/sleep_gpio.c +++ b/components/esp_hw_support/sleep_gpio.c @@ -126,7 +126,7 @@ void esp_sleep_enable_gpio_switch(bool enable) } } -#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP IRAM_ATTR void esp_sleep_isolate_digital_gpio(void) { gpio_hal_context_t gpio_hal = { @@ -164,7 +164,7 @@ IRAM_ATTR void esp_sleep_isolate_digital_gpio(void) } } } -#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP #if SOC_DEEP_SLEEP_SUPPORTED void esp_deep_sleep_wakeup_io_reset(void) diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index ef51be589989..b45ffbdad81f 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -987,7 +987,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t sleep_flags, esp_sleep_mode_ } #endif if (deep_sleep) { -#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP esp_sleep_isolate_digital_gpio(); #endif @@ -1030,10 +1030,8 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t sleep_flags, esp_sleep_mode_ if(!(sleep_flags & RTC_SLEEP_PD_VDDSDIO) && (sleep_flags & PMU_SLEEP_PD_TOP)) { #if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND /* Cache suspend also means SPI bus IDLE, then we can hold SPI CS pin safely */ -#if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359 gpio_ll_hold_en(&GPIO, MSPI_IOMUX_PIN_NUM_CS0); #endif -#endif #if CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM /* Cache suspend also means SPI bus IDLE, then we can hold SPI CS pin safely */ gpio_ll_hold_en(&GPIO, MSPI_IOMUX_PIN_NUM_CS1); @@ -1088,10 +1086,8 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t sleep_flags, esp_sleep_mode_ /* Unhold the SPI CS pin */ if(!(sleep_flags & RTC_SLEEP_PD_VDDSDIO) && (sleep_flags & PMU_SLEEP_PD_TOP)) { #if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND -#if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359 gpio_ll_hold_dis(&GPIO, MSPI_IOMUX_PIN_NUM_CS0); #endif -#endif #if CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM gpio_ll_hold_dis(&GPIO, MSPI_IOMUX_PIN_NUM_CS1); #endif @@ -2623,6 +2619,13 @@ static uint32_t get_power_down_flags(void) } } #endif + +#if CONFIG_IDF_TARGET_ESP32C6 + if (!(pd_flags & PMU_SLEEP_PD_TOP)) { + // TOP power domain depends on the RTC_PERIPH power domain on ESP32C6, RTC_PERIPH should only be disabled when the TOP domain is down. + pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH; + } +#endif return pd_flags; } diff --git a/components/esp_hw_support/test_apps/dma2d/main/test_dma2d.c b/components/esp_hw_support/test_apps/dma2d/main/test_dma2d.c index 33a49d1a4739..931688448e1b 100644 --- a/components/esp_hw_support/test_apps/dma2d/main/test_dma2d.c +++ b/components/esp_hw_support/test_apps/dma2d/main/test_dma2d.c @@ -22,7 +22,7 @@ // This tests the hardware capability of multiple 2D-DMA transactions running together, and the driver capbility of // transactions being send to a queue, and waiting for free channels becoming available, and being picked to start the // real hardware operation. -#define M2M_TRANS_TIMES (8) +#define M2M_TRANS_TIMES (12) // Descriptor and buffer address and size should aligned to 64 bytes (the cacheline size alignment restriction) to be used by CPU diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c index fbf38beb4aa6..4144bfeeda38 100644 --- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c @@ -72,7 +72,7 @@ TEST_CASE("LDO channel state dump", "[LDO][manual][ignore]") esp_ldo_channel_handle_t success_ldo_chans[3] = {}; esp_ldo_channel_config_t ldo_chan_config = { .chan_id = 2, - .voltage_mv = 1900, + .voltage_mv = 1800, }; TEST_ESP_OK(esp_ldo_acquire_channel(&ldo_chan_config, &success_ldo_chans[0])); diff --git a/components/esp_lcd/spi/esp_lcd_panel_io_spi.c b/components/esp_lcd/spi/esp_lcd_panel_io_spi.c index 13a84ca50f01..e276ef9ea347 100644 --- a/components/esp_lcd/spi/esp_lcd_panel_io_spi.c +++ b/components/esp_lcd/spi/esp_lcd_panel_io_spi.c @@ -412,6 +412,9 @@ IRAM_ATTR static void lcd_spi_pre_trans_cb(spi_transaction_t *trans) if (spi_panel_io->dc_gpio_num >= 0) { // set D/C line level if necessary // use ll function to speed up gpio_ll_set_level(&GPIO, spi_panel_io->dc_gpio_num, lcd_trans->flags.dc_gpio_level); + + // ensure the D/C output is enabled + gpio_ll_output_enable(&GPIO, spi_panel_io->dc_gpio_num); } } @@ -419,6 +422,12 @@ static void lcd_spi_post_trans_color_cb(spi_transaction_t *trans) { esp_lcd_panel_io_spi_t *spi_panel_io = trans->user; lcd_spi_trans_descriptor_t *lcd_trans = __containerof(trans, lcd_spi_trans_descriptor_t, base); + + // disable the D/C output as we no longer need it + if (spi_panel_io->dc_gpio_num >= 0) { + gpio_ll_output_disable(&GPIO, spi_panel_io->dc_gpio_num); + } + if (lcd_trans->flags.en_trans_done_cb) { if (spi_panel_io->on_color_trans_done) { spi_panel_io->on_color_trans_done(&spi_panel_io->base, NULL, spi_panel_io->user_ctx); diff --git a/components/esp_netif/include/esp_netif.h b/components/esp_netif/include/esp_netif.h index 7c873906caca..409eaabc9d80 100644 --- a/components/esp_netif/include/esp_netif.h +++ b/components/esp_netif/include/esp_netif.h @@ -18,16 +18,6 @@ extern "C" { #endif -/** - * @defgroup ESP_NETIF_INIT_API ESP-NETIF Initialization API - * @brief Initialization and deinitialization of underlying TCP/IP stack and esp-netif instances - * - */ - -/** @addtogroup ESP_NETIF_INIT_API - * @{ - */ - /** * @brief Initialize the underlying TCP/IP stack * @@ -97,30 +87,6 @@ esp_err_t esp_netif_set_driver_config(esp_netif_t *esp_netif, */ esp_err_t esp_netif_attach(esp_netif_t *esp_netif, esp_netif_iodriver_handle driver_handle); -/** - * @} - */ - -/** - * @defgroup ESP_NETIF_DATA_IO_API ESP-NETIF Input Output API - * @brief Input and Output functions to pass data packets from communication media (IO driver) - * to TCP/IP stack. - * - * These functions are usually not directly called from user code, but installed, or registered - * as callbacks in either IO driver on one hand or TCP/IP stack on the other. More specifically - * esp_netif_receive is typically called from io driver on reception callback to input the packets - * to TCP/IP stack. Similarly esp_netif_transmit is called from the TCP/IP stack whenever - * a packet ought to output to the communication media. - * - * @note These IO functions are registered (installed) automatically for default interfaces - * (interfaces with the keys such as WIFI_STA_DEF, WIFI_AP_DEF, ETH_DEF). Custom interface - * has to register these IO functions when creating interface using @ref esp_netif_new - * - */ - -/** @addtogroup ESP_NETIF_DATA_IO_API - * @{ - */ /** * @brief Passes the raw packets from communication media to the appropriate TCP/IP stack @@ -165,20 +131,7 @@ esp_err_t esp_netif_tx_rx_event_enable(esp_netif_t *esp_netif); */ esp_err_t esp_netif_tx_rx_event_disable(esp_netif_t *esp_netif); -/** - * @} - */ -/** - * @defgroup ESP_NETIF_LIFECYCLE ESP-NETIF Lifecycle control - * @brief These APIS define basic building blocks to control network interface lifecycle, i.e. - * start, stop, set_up or set_down. These functions can be directly used as event handlers - * registered to follow the events from communication media. - */ - -/** @addtogroup ESP_NETIF_LIFECYCLE - * @{ - */ /** * @brief Default building block for network interface action upon IO driver start event @@ -369,19 +322,6 @@ esp_err_t esp_netif_join_ip6_multicast_group(esp_netif_t *esp_netif, const esp_i */ esp_err_t esp_netif_leave_ip6_multicast_group(esp_netif_t *esp_netif, const esp_ip6_addr_t *addr); -/** - * @} - */ - -/** - * @defgroup ESP_NETIF_GET_SET ESP-NETIF Runtime configuration - * @brief Getters and setters for various TCP/IP related parameters - */ - -/** @addtogroup ESP_NETIF_GET_SET - * @{ - */ - /** * @brief Set the mac address for the interface instance @@ -578,18 +518,6 @@ esp_err_t esp_netif_napt_enable(esp_netif_t *esp_netif); */ esp_err_t esp_netif_napt_disable(esp_netif_t *esp_netif); -/** - * @} - */ - -/** - * @defgroup ESP_NETIF_NET_DHCP ESP-NETIF DHCP Settings - * @brief Network stack related interface to DHCP client and server - */ - -/** @addtogroup ESP_NETIF_NET_DHCP - * @{ - */ /** * @brief Set or Get DHCP server option @@ -754,18 +682,7 @@ esp_err_t esp_netif_dhcps_stop(esp_netif_t *esp_netif); */ esp_err_t esp_netif_dhcps_get_clients_by_mac(esp_netif_t *esp_netif, int num, esp_netif_pair_mac_ip_t *mac_ip_pair); -/** - * @} - */ -/** - * @defgroup ESP_NETIF_NET_DNS ESP-NETIF DNS Settings - * @brief Network stack related interface to NDS - */ - -/** @addtogroup ESP_NETIF_NET_DNS - * @{ - */ /** * @brief Set DNS Server information @@ -822,18 +739,9 @@ esp_err_t esp_netif_set_dns_info(esp_netif_t *esp_netif, esp_netif_dns_type_t ty */ esp_err_t esp_netif_get_dns_info(esp_netif_t *esp_netif, esp_netif_dns_type_t type, esp_netif_dns_info_t *dns); -/** - * @} - */ -/** - * @defgroup ESP_NETIF_NET_IP ESP-NETIF IP address related interface - * @brief Network stack related interface to IP - */ -/** @addtogroup ESP_NETIF_NET_IP - * @{ - */ + #if CONFIG_LWIP_IPV6 /** * @brief Create interface link-local IPv6 address @@ -992,18 +900,9 @@ esp_err_t esp_netif_str_to_ip4(const char *src, esp_ip4_addr_t *dst); */ esp_err_t esp_netif_str_to_ip6(const char *src, esp_ip6_addr_t *dst); -/** - * @} - */ -/** - * @defgroup ESP_NETIF_CONVERT ESP-NETIF Conversion utilities - * @brief ESP-NETIF conversion utilities to related keys, flags, implementation handle - */ -/** @addtogroup ESP_NETIF_CONVERT - * @{ - */ + /** * @brief Gets media driver handle for this esp-netif instance @@ -1071,18 +970,6 @@ int esp_netif_get_route_prio(esp_netif_t *esp_netif); */ int32_t esp_netif_get_event_id(esp_netif_t *esp_netif, esp_netif_ip_event_type_t event_type); -/** - * @} - */ - -/** - * @defgroup ESP_NETIF_LIST ESP-NETIF List of interfaces - * @brief APIs to enumerate all registered interfaces - */ - -/** @addtogroup ESP_NETIF_LIST - * @{ - */ /** * @brief Iterates over list of interfaces. Returns first netif if NULL given as parameter @@ -1154,13 +1041,6 @@ void esp_netif_netstack_buf_ref(void *netstack_buf); */ void esp_netif_netstack_buf_free(void *netstack_buf); -/** - * @} - */ - -/** @addtogroup ESP_NETIF_TCPIP_EXEC - * @{ - */ /** * @brief TCPIP thread safe callback used with esp_netif_tcpip_exec() @@ -1175,10 +1055,6 @@ typedef esp_err_t (*esp_netif_callback_fn)(void *ctx); */ esp_err_t esp_netif_tcpip_exec(esp_netif_callback_fn fn, void *ctx); -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/components/esp_netif/include/esp_netif_sntp.h b/components/esp_netif/include/esp_netif_sntp.h index 51d7e42bd419..60f4f7ac4c5e 100644 --- a/components/esp_netif/include/esp_netif_sntp.h +++ b/components/esp_netif/include/esp_netif_sntp.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,17 +16,6 @@ extern "C" { #endif -/** - * @defgroup ESP_NETIF_SNTP_API ESP-NETIF SNTP API - * @brief SNTP API for underlying TCP/IP stack - * - */ - -/** @addtogroup ESP_NETIF_SNTP_API - * @{ - */ - - /** * @brief Time sync notification function */ @@ -101,7 +90,7 @@ void esp_netif_sntp_deinit(void); /** * @brief Wait for time sync event * @param tout Specified timeout in RTOS ticks - * @return ESP_TIMEOUT if sync event didn't came withing the timeout + * @return ESP_TIMEOUT if sync event didn't came within the timeout * ESP_ERR_NOT_FINISHED if the sync event came, but we're in smooth update mode and still in progress (SNTP_SYNC_STATUS_IN_PROGRESS) * ESP_OK if time sync'ed */ @@ -118,10 +107,6 @@ esp_err_t esp_netif_sntp_sync_wait(TickType_t tout); */ esp_err_t esp_netif_sntp_reachability(unsigned int index, unsigned int *reachability); -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/components/esp_phy/lib b/components/esp_phy/lib index 4c2a23c8d2f6..fbc304747bc5 160000 --- a/components/esp_phy/lib +++ b/components/esp_phy/lib @@ -1 +1 @@ -Subproject commit 4c2a23c8d2f6ceaf462feeae31636251870713aa +Subproject commit fbc304747bc55b40ef7225130fcf87f43b981482 diff --git a/components/esp_pm/test_apps/esp_pm/main/CMakeLists.txt b/components/esp_pm/test_apps/esp_pm/main/CMakeLists.txt index 48c7ad8ed7aa..8f23c7c05742 100644 --- a/components/esp_pm/test_apps/esp_pm/main/CMakeLists.txt +++ b/components/esp_pm/test_apps/esp_pm/main/CMakeLists.txt @@ -5,5 +5,5 @@ set(sources "test_app_main.c" # the component must be registered as a WHOLE_ARCHIVE idf_component_register(SRCS ${sources} INCLUDE_DIRS "." - PRIV_REQUIRES unity esp_pm ulp driver esp_timer esp_psram + PRIV_REQUIRES unity esp_pm ulp driver esp_timer esp_psram esp_vfs_console WHOLE_ARCHIVE) diff --git a/components/esp_pm/test_apps/esp_pm/main/test_pm.c b/components/esp_pm/test_apps/esp_pm/main/test_pm.c index 9f69163629b7..8d62c3cee66b 100644 --- a/components/esp_pm/test_apps/esp_pm/main/test_pm.c +++ b/components/esp_pm/test_apps/esp_pm/main/test_pm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -400,6 +401,29 @@ TEST_CASE("esp_timer with SKIP_UNHANDLED_EVENTS does not wake up CPU from sleep" TEST_ESP_OK(esp_timer_delete(periodic_timer)); } +TEST_CASE("Test USJ printing doesn't block CPU on chip wake-up", "[pm]") +{ + light_sleep_enable(); + fflush(stdout); + fsync(fileno(stdout)); + int64_t printing_time_cost_us = 0, time_end, time_start; + + for (int i = 0; i < 20; ++i) + { + time_start = esp_timer_get_time(); + printf("Dummy print %02d\n", i); + fflush(stdout); + fsync(fileno(stdout)); + time_end = esp_timer_get_time(); + printing_time_cost_us += time_end - time_start; + vTaskDelay(10); + } + int32_t avg_cost = (int32_t)(printing_time_cost_us / 20); + printf("Average cost per print %ld\n", avg_cost); + TEST_ASSERT_LESS_THAN(5000, avg_cost); + light_sleep_disable(); +} + #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE #endif // CONFIG_PM_ENABLE diff --git a/components/esp_psram/device/esp_psram_impl_ap_hex.c b/components/esp_psram/device/esp_psram_impl_ap_hex.c index acf07e4d73ea..d8b1f8de8d8f 100644 --- a/components/esp_psram/device/esp_psram_impl_ap_hex.c +++ b/components/esp_psram/device/esp_psram_impl_ap_hex.c @@ -55,7 +55,11 @@ #define AP_HEX_PSRAM_CS_ECC_HOLD_TIME 4 #define AP_HEX_PSRAM_CS_HOLD_DELAY 3 +#if CONFIG_SPIRAM_SPEED_250M +#define AP_HEX_PSRAM_MPLL_DEFAULT_FREQ_MHZ 500 +#else #define AP_HEX_PSRAM_MPLL_DEFAULT_FREQ_MHZ 400 +#endif #define AP_HEX_PSRAM_REF_DATA 0x5a6b7c8d @@ -461,13 +465,6 @@ esp_err_t esp_psram_impl_enable(void) mode_reg.mr2.density == 0x7 ? PSRAM_SIZE_32MB : mode_reg.mr2.density == 0x6 ? PSRAM_SIZE_64MB : 0; -#if CONFIG_SPIRAM_SPEED_250M - if (mode_reg.mr2.density == 0x7) { - ESP_EARLY_LOGE(TAG, "PSRAM Not support 250MHz speed"); - return ESP_ERR_NOT_SUPPORTED; - } -#endif - s_config_mspi_for_psram(); mspi_timing_psram_tuning(); psram_ctrlr_ll_enable_variable_dummy(PSRAM_CTRLR_LL_MSPI_ID_2, true); diff --git a/components/esp_psram/esp32p4/Kconfig.spiram b/components/esp_psram/esp32p4/Kconfig.spiram index 821188d2f3ff..e687c311fbd9 100644 --- a/components/esp_psram/esp32p4/Kconfig.spiram +++ b/components/esp_psram/esp32p4/Kconfig.spiram @@ -26,12 +26,15 @@ menu "PSRAM config" choice SPIRAM_SPEED prompt "Set PSRAM clock speed" - default SPIRAM_SPEED_20M + default SPIRAM_SPEED_200M help Select the speed for the PSRAM chip. + config SPIRAM_SPEED_250M + depends on !ESP32P4_SELECTS_REV_LESS_V3 + bool "250MHz clock speed" + config SPIRAM_SPEED_200M - depends on IDF_EXPERIMENTAL_FEATURES bool "200MHz clock speed" config SPIRAM_SPEED_20M @@ -43,6 +46,7 @@ menu "PSRAM config" default 20 if SPIRAM_SPEED_20M default 100 if SPIRAM_SPEED_100M default 200 if SPIRAM_SPEED_200M + default 250 if SPIRAM_SPEED_250M config SPIRAM_FETCH_INSTRUCTIONS bool diff --git a/components/esp_rom/esp32/ld/esp32.rom.ld b/components/esp_rom/esp32/ld/esp32.rom.ld index 8fd3ab18c10a..6cca533158f7 100644 --- a/components/esp_rom/esp32/ld/esp32.rom.ld +++ b/components/esp_rom/esp32/ld/esp32.rom.ld @@ -1633,6 +1633,9 @@ PROVIDE ( ld_pscan_em_init = 0x4003e5e8 ); PROVIDE ( ld_acl_rsw_start = 0x40032e90 ); PROVIDE ( ld_acl_sniff_enter = 0x40031244 ); PROVIDE ( ld_acl_sniff_trans_sched = 0x40033734 ); +PROVIDE ( ld_acl_afh_apply = 0x40030e94 ); +PROVIDE ( ld_acl_afh_switch_on_cbk = 0x40030fa8 ); +PROVIDE ( ld_acl_afh_switch_off_cbk = 0x400310c4 ); PROVIDE ( lc_pwr_decr_ind_handler = 0x4002859c ); PROVIDE ( lc_pwr_incr_ind_handler = 0x400284a8 ); PROVIDE ( lc_pwr_max_ind_handler = 0x40028690 ); diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld index a76958638a7b..12aa1d0ed757 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld @@ -811,7 +811,7 @@ r_ble_lll_scan_sched_next_aux = 0x40001700; r_ble_lll_scan_sched_remove = 0x40001704; //r_ble_lll_scan_start = 0x40001708; //r_ble_lll_scan_start_rx = 0x4000170c; -r_ble_lll_scan_stop = 0x40001710; +//r_ble_lll_scan_stop = 0x40001710; r_ble_lll_scan_targeta_is_matched = 0x40001714; r_ble_lll_scan_timer_cb = 0x40001718; r_ble_lll_sched_adv_new = 0x4000171c; diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld index 48f40b790797..0cfe3f5c06a6 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld @@ -156,7 +156,7 @@ systimer_hal_set_tick_rate_ops = 0x40002eac; /* Functions */ sta_reset_beacon_timeout = 0x40003024; ieee80211_post_hmac_tx = 0x40003028; -sta_rx_eapol = 0x4000302c; +//sta_rx_eapol = 0x4000302c; /* Data (.data, .bss, .rodata) */ len_dh_ie_ptr = 0x3fcdfa6c; g_authmode_threshold_failure_ptr = 0x3fcdfa68; diff --git a/components/esp_system/port/CMakeLists.txt b/components/esp_system/port/CMakeLists.txt index 05a476f8cfea..6b17edf78bf4 100644 --- a/components/esp_system/port/CMakeLists.txt +++ b/components/esp_system/port/CMakeLists.txt @@ -6,6 +6,10 @@ endif() target_include_directories(${COMPONENT_LIB} PRIVATE ${INCLUDE_FILES} include/private) +if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3 AND CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_400) + message(WARNING "400 MHz CPU frequency is not guaranteed to work on all chips with revision prior to rev 3!") +endif() + set(srcs "cpu_start.c" "panic_handler.c" "esp_system_chip.c") if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index f769faefe7c1..4471a46eaf9b 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -98,6 +98,7 @@ #include "hal/cache_hal.h" #include "hal/cache_ll.h" #include "hal/efuse_ll.h" +#include "soc/uart_pins.h" #include "soc/periph_defs.h" #include "esp_cpu.h" #include "esp_private/esp_clk.h" @@ -735,8 +736,15 @@ void IRAM_ATTR call_start_cpu0(void) // In a single thread mode, the freertos is not started yet. So don't have to use a critical section. int __DECLARE_RCC_ATOMIC_ENV __attribute__((unused)); // To avoid build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE); -#endif -#endif + int console_uart_tx_pin = U0TXD_GPIO_NUM; + int console_uart_rx_pin = U0RXD_GPIO_NUM; +#if CONFIG_ESP_CONSOLE_UART_CUSTOM + console_uart_tx_pin = (CONFIG_ESP_CONSOLE_UART_TX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_TX_GPIO : U0TXD_GPIO_NUM; + console_uart_rx_pin = (CONFIG_ESP_CONSOLE_UART_RX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_RX_GPIO : U0RXD_GPIO_NUM; +#endif + ESP_EARLY_LOGI(TAG, "GPIO %d and %d are used as console UART I/O pins", console_uart_rx_pin, console_uart_tx_pin); +#endif // CONFIG_ESP_CONSOLE_UART +#endif // !CONFIG_IDF_ENV_FPGA #if SOC_DEEP_SLEEP_SUPPORTED // Need to unhold the IOs that were hold right before entering deep sleep, which are used as wakeup pins diff --git a/components/esp_system/port/soc/esp32c3/clk.c b/components/esp_system/port/soc/esp32c3/clk.c index 8fa0c256942d..55c6f2e6b30c 100644 --- a/components/esp_system/port/soc/esp32c3/clk.c +++ b/components/esp_system/port/soc/esp32c3/clk.c @@ -219,10 +219,13 @@ __attribute__((weak)) void esp_perip_clk_init(void) /* For reason that only reset CPU, do not disable the clocks * that have been enabled before reset. */ + uint32_t hwcrypto_mask_in_perip1 = (SYSTEM_CRYPTO_HMAC_CLK_EN | SYSTEM_CRYPTO_DS_CLK_EN | SYSTEM_CRYPTO_RSA_CLK_EN | SYSTEM_CRYPTO_SHA_CLK_EN | SYSTEM_CRYPTO_AES_CLK_EN); + if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW || rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) { common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); - hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG); + common_perip_clk1 = (~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG)) & (~hwcrypto_mask_in_perip1); + hwcrypto_perip_clk = (~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG)) & hwcrypto_mask_in_perip1; wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG); } else { common_perip_clk = SYSTEM_WDG_CLK_EN | @@ -242,7 +245,6 @@ __attribute__((weak)) void esp_perip_clk_init(void) SYSTEM_SPI3_CLK_EN | SYSTEM_SPI4_CLK_EN | SYSTEM_TWAI_CLK_EN | - SYSTEM_I2S0_CLK_EN | SYSTEM_SPI2_DMA_CLK_EN | SYSTEM_SPI3_DMA_CLK_EN; @@ -260,7 +262,7 @@ __attribute__((weak)) void esp_perip_clk_init(void) * declare __DECLARE_RCC_ATOMIC_ENV here. */ int __DECLARE_RCC_ATOMIC_ENV __attribute__((unused)); // Disable USB-Serial-JTAG clock and it's pad if not used - usb_serial_jtag_ll_phy_enable_pad(false); + usb_serial_jtag_ll_phy_enable_pad(false); // should not reset USJ registers in the code below, otherwises, usb pad will be enabled again usb_serial_jtag_ll_enable_bus_clock(false); #endif } @@ -281,10 +283,10 @@ __attribute__((weak)) void esp_perip_clk_init(void) SYSTEM_SPI3_CLK_EN | SYSTEM_SPI4_CLK_EN | SYSTEM_I2C_EXT1_CLK_EN | - SYSTEM_I2S0_CLK_EN | SYSTEM_SPI2_DMA_CLK_EN | SYSTEM_SPI3_DMA_CLK_EN; - common_perip_clk1 = 0; + + common_perip_clk &= ~SYSTEM_USB_DEVICE_CLK_EN; // ignore USB-Serial-JTAG module, which has already been handled above (for non-CPU-reset cases) /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock, * the current is not reduced when disable I2S clock. diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c index 5f3d0e84b29a..fb4056e08cdc 100644 --- a/components/esp_system/port/soc/esp32c5/clk.c +++ b/components/esp_system/port/soc/esp32c5/clk.c @@ -180,6 +180,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) rtc_clk_32k_enable(false); rtc_clk_32k_disable_external(); } + // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection. + pmu_lp_power_t lp_clk_power = { + .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW), + .xpd_rc32k = 0, + .xpd_fosc = 1, + .pd_osc = 0 + }; + pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val); + if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. * Improve calibration routine to wait until the frequency is stable. diff --git a/components/esp_system/port/soc/esp32c5/system_internal.c b/components/esp_system/port/soc/esp32c5/system_internal.c index c406b57e386f..81c954fe51fe 100644 --- a/components/esp_system/port/soc/esp32c5/system_internal.c +++ b/components/esp_system/port/soc/esp32c5/system_internal.c @@ -36,8 +36,11 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) { // Flush any data left in UART FIFOs before reset the UART peripheral - esp_rom_output_tx_wait_idle(0); - esp_rom_output_tx_wait_idle(1); + for (int i = 0; i < SOC_UART_HP_NUM; ++i) { + if (uart_ll_is_enabled(i)) { + esp_rom_output_tx_wait_idle(i); + } + } // TODO: IDF-8845 #if SOC_MODEM_CLOCK_SUPPORTED diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c index 0c25691a8130..d510f9568957 100644 --- a/components/esp_system/port/soc/esp32c6/clk.c +++ b/components/esp_system/port/soc/esp32c6/clk.c @@ -199,6 +199,14 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) { rtc_clk_rc32k_enable(false); } + // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection. + pmu_lp_power_t lp_clk_power = { + .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW), + .xpd_rc32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K), + .xpd_fosc = 1, + .pd_osc = 0 + }; + pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val); if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. diff --git a/components/esp_system/port/soc/esp32c61/clk.c b/components/esp_system/port/soc/esp32c61/clk.c index 8e2966afbece..6ba15a6c9ab8 100644 --- a/components/esp_system/port/soc/esp32c61/clk.c +++ b/components/esp_system/port/soc/esp32c61/clk.c @@ -159,6 +159,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) rtc_clk_32k_enable(false); rtc_clk_32k_disable_external(); } + // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection. + pmu_lp_power_t lp_clk_power = { + .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW), + .xpd_rc32k = 0, + .xpd_fosc = 1, + .pd_osc = 0 + }; + pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val); + if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. * Improve calibration routine to wait until the frequency is stable. diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c index 57daa142041b..5372dacde733 100644 --- a/components/esp_system/port/soc/esp32h2/clk.c +++ b/components/esp_system/port/soc/esp32h2/clk.c @@ -197,6 +197,14 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) { rtc_clk_rc32k_enable(false); } + // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection. + pmu_lp_power_t lp_clk_power = { + .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW), + .xpd_rc32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K), + .xpd_fosc = 1, + .pd_osc = 0 + }; + pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val); if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c index bf88f0dd6d23..6d5bf4defc1d 100644 --- a/components/esp_system/port/soc/esp32p4/clk.c +++ b/components/esp_system/port/soc/esp32p4/clk.c @@ -203,6 +203,14 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) { rtc_clk_rc32k_enable(false); } + // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection. + pmu_lp_power_t lp_clk_power = { + .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K), + .xpd_rc32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K), + .xpd_fosc = 1, + .pd_osc = 0 + }; + pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val); if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. diff --git a/components/esp_system/port/soc/esp32p4/system_internal.c b/components/esp_system/port/soc/esp32p4/system_internal.c index d046c54848b7..898a104ba6cf 100644 --- a/components/esp_system/port/soc/esp32p4/system_internal.c +++ b/components/esp_system/port/soc/esp32p4/system_internal.c @@ -53,11 +53,11 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) } } if (dma2d_ll_is_bus_clock_enabled(0)) { - for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) { dma2d_ll_rx_abort(DMA2D_LL_GET_HW(0), i, true); while (!dma2d_ll_rx_is_reset_avail(DMA2D_LL_GET_HW(0), i)); } - for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) { dma2d_ll_tx_abort(DMA2D_LL_GET_HW(0), i, true); while (!dma2d_ll_tx_is_reset_avail(DMA2D_LL_GET_HW(0), i)); } diff --git a/components/esp_system/port/soc/esp32s3/clk.c b/components/esp_system/port/soc/esp32s3/clk.c index 7e735c7c76be..9efad0687c21 100644 --- a/components/esp_system/port/soc/esp32s3/clk.c +++ b/components/esp_system/port/soc/esp32s3/clk.c @@ -26,6 +26,7 @@ #include "esp_private/esp_clk.h" #include "bootloader_clock.h" #include "soc/syscon_reg.h" +#include "hal/gpio_ll.h" static const char *TAG = "clk"; @@ -229,6 +230,8 @@ __attribute__((weak)) void esp_perip_clk_init(void) /* For reason that only reset CPU, do not disable the clocks * that have been enabled before reset. */ + uint32_t hwcrypto_mask_in_perip1 = (SYSTEM_CRYPTO_HMAC_CLK_EN | SYSTEM_CRYPTO_DS_CLK_EN | SYSTEM_CRYPTO_RSA_CLK_EN | SYSTEM_CRYPTO_SHA_CLK_EN | SYSTEM_CRYPTO_AES_CLK_EN); + if ((rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_SW || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT || rst_reas[0] == RESET_REASON_CPU0_MWDT1) #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE @@ -237,82 +240,91 @@ __attribute__((weak)) void esp_perip_clk_init(void) #endif ) { common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); - hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG); + common_perip_clk1 = (~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG)) & (~hwcrypto_mask_in_perip1); + hwcrypto_perip_clk = (~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG)) & hwcrypto_mask_in_perip1; wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG); } else { - common_perip_clk = SYSTEM_WDG_CLK_EN | - SYSTEM_I2S0_CLK_EN | + common_perip_clk = + SYSTEM_WDG_CLK_EN | + SYSTEM_I2S0_CLK_EN | #if CONFIG_ESP_CONSOLE_UART_NUM != 0 - SYSTEM_UART_CLK_EN | + SYSTEM_UART_CLK_EN | #endif #if CONFIG_ESP_CONSOLE_UART_NUM != 1 - SYSTEM_UART1_CLK_EN | + SYSTEM_UART1_CLK_EN | #endif + SYSTEM_USB_CLK_EN | + SYSTEM_SPI2_CLK_EN | + SYSTEM_I2C_EXT0_CLK_EN | + SYSTEM_UHCI0_CLK_EN | + SYSTEM_RMT_CLK_EN | + SYSTEM_PCNT_CLK_EN | + SYSTEM_LEDC_CLK_EN | + SYSTEM_TIMERGROUP1_CLK_EN | + SYSTEM_SPI3_CLK_EN | + SYSTEM_SPI4_CLK_EN | + SYSTEM_PWM0_CLK_EN | + SYSTEM_TWAI_CLK_EN | + SYSTEM_PWM1_CLK_EN | + SYSTEM_I2S1_CLK_EN | + SYSTEM_SPI2_DMA_CLK_EN | + SYSTEM_SPI3_DMA_CLK_EN | + SYSTEM_PWM2_CLK_EN | + SYSTEM_PWM3_CLK_EN; + common_perip_clk1 = #if CONFIG_ESP_CONSOLE_UART_NUM != 2 - SYSTEM_UART2_CLK_EN | + SYSTEM_UART2_CLK_EN | #endif - SYSTEM_USB_CLK_EN | - SYSTEM_SPI2_CLK_EN | - SYSTEM_I2C_EXT0_CLK_EN | - SYSTEM_UHCI0_CLK_EN | - SYSTEM_RMT_CLK_EN | - SYSTEM_PCNT_CLK_EN | - SYSTEM_LEDC_CLK_EN | - SYSTEM_TIMERGROUP1_CLK_EN | - SYSTEM_SPI3_CLK_EN | - SYSTEM_SPI4_CLK_EN | - SYSTEM_PWM0_CLK_EN | - SYSTEM_TWAI_CLK_EN | - SYSTEM_PWM1_CLK_EN | - SYSTEM_I2S1_CLK_EN | - SYSTEM_SPI2_DMA_CLK_EN | - SYSTEM_SPI3_DMA_CLK_EN | - SYSTEM_PWM2_CLK_EN | - SYSTEM_PWM3_CLK_EN; - common_perip_clk1 = 0; - hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN | - SYSTEM_CRYPTO_SHA_CLK_EN | - SYSTEM_CRYPTO_RSA_CLK_EN; - wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN | - SYSTEM_WIFI_CLK_BT_EN_M | - SYSTEM_WIFI_CLK_I2C_CLK_EN | - SYSTEM_WIFI_CLK_UNUSED_BIT12 | - SYSTEM_WIFI_CLK_SDIO_HOST_EN; + 0; + hwcrypto_perip_clk = + SYSTEM_CRYPTO_AES_CLK_EN | + SYSTEM_CRYPTO_SHA_CLK_EN | + SYSTEM_CRYPTO_RSA_CLK_EN; + wifi_bt_sdio_clk = + SYSTEM_WIFI_CLK_WIFI_EN | + SYSTEM_WIFI_CLK_BT_EN_M | + SYSTEM_WIFI_CLK_I2C_CLK_EN | + SYSTEM_WIFI_CLK_UNUSED_BIT12 | + SYSTEM_WIFI_CLK_SDIO_HOST_EN; #if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED /* This function only called on startup thus is thread safe. To avoid build errors/warnings * declare __DECLARE_RCC_ATOMIC_ENV here. */ int __DECLARE_RCC_ATOMIC_ENV __attribute__((unused)); // Disable USB-Serial-JTAG clock and it's pad if not used - usb_serial_jtag_ll_phy_enable_pad(false); + usb_serial_jtag_ll_phy_enable_pad(false); // should not reset USJ registers in the code below, otherwises, usb pad will be enabled again usb_serial_jtag_ll_enable_bus_clock(false); #endif } //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state. - common_perip_clk |= SYSTEM_I2S0_CLK_EN | + common_perip_clk |= + SYSTEM_I2S0_CLK_EN | #if CONFIG_ESP_CONSOLE_UART_NUM != 0 - SYSTEM_UART_CLK_EN | + SYSTEM_UART_CLK_EN | #endif #if CONFIG_ESP_CONSOLE_UART_NUM != 1 - SYSTEM_UART1_CLK_EN | + SYSTEM_UART1_CLK_EN | #endif + SYSTEM_USB_CLK_EN | + SYSTEM_SPI2_CLK_EN | + SYSTEM_I2C_EXT0_CLK_EN | + SYSTEM_UHCI0_CLK_EN | + SYSTEM_RMT_CLK_EN | + SYSTEM_UHCI1_CLK_EN | + SYSTEM_SPI3_CLK_EN | + SYSTEM_SPI4_CLK_EN | + SYSTEM_I2C_EXT1_CLK_EN | + SYSTEM_I2S1_CLK_EN | + SYSTEM_SPI2_DMA_CLK_EN | + SYSTEM_SPI3_DMA_CLK_EN; + common_perip_clk1 |= #if CONFIG_ESP_CONSOLE_UART_NUM != 2 - SYSTEM_UART2_CLK_EN | + SYSTEM_UART2_CLK_EN | #endif - SYSTEM_USB_CLK_EN | - SYSTEM_SPI2_CLK_EN | - SYSTEM_I2C_EXT0_CLK_EN | - SYSTEM_UHCI0_CLK_EN | - SYSTEM_RMT_CLK_EN | - SYSTEM_UHCI1_CLK_EN | - SYSTEM_SPI3_CLK_EN | - SYSTEM_SPI4_CLK_EN | - SYSTEM_I2C_EXT1_CLK_EN | - SYSTEM_I2S1_CLK_EN | - SYSTEM_SPI2_DMA_CLK_EN | - SYSTEM_SPI3_DMA_CLK_EN; - common_perip_clk1 = 0; + 0; + + common_perip_clk1 &= ~SYSTEM_USB_DEVICE_CLK_EN; // ignore USB-Serial-JTAG module, which has already been handled above (for non-CPU-reset cases) /* Disable some peripheral clocks. */ CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk); diff --git a/components/esp_wifi/include/esp_private/wifi.h b/components/esp_wifi/include/esp_private/wifi.h index d1f36f0d1b72..0ad8eea9cbe5 100644 --- a/components/esp_wifi/include/esp_private/wifi.h +++ b/components/esp_wifi/include/esp_private/wifi.h @@ -39,6 +39,19 @@ typedef struct { void *storage; /**< storage for FreeRTOS queue */ } wifi_static_queue_t; +struct nan_callbacks { + void (* service_match)(uint8_t sub_id, uint8_t pub_id, uint8_t pub_mac[6], uint16_t capab, + uint8_t ssi_ver, uint8_t *ssi, uint16_t ssi_len); + void (* replied)(uint8_t pub_id, uint8_t sub_id, uint8_t pub_mac[6], uint8_t *ssi, uint16_t ssi_len); + void (* receive)(uint8_t svc_id, uint8_t peer_svc_id, uint8_t peer_mac[6], uint8_t *ssi, uint16_t ssi_len); + void (* ndp_indication)(uint8_t pub_id, uint8_t ndp_id, uint8_t peer_nmi[6], uint8_t peer_ndi[6], + uint8_t *ssi, uint16_t ssi_len); + void (* ndp_confirm)(uint8_t status, uint8_t ndp_id, uint8_t peer_nmi[6], uint8_t peer_ndi[6], + uint8_t own_ndi[6], uint8_t *ssi, uint16_t ssi_len); + void (* ndp_terminated)(uint8_t reason, uint8_t ndp_id, uint8_t init_ndi[6]); + void (* action_txdone)(uint32_t context, bool tx_status); +}; + /** * @brief WiFi log level * @@ -703,13 +716,14 @@ esp_err_t esp_nan_internal_subscribe_service(const wifi_nan_subscribe_cfg_t *sub * * @attention This API should be called after WIFI_EVENT_NAN_SVC_MATCH event is received. * - * @param fup_params Configuration parameters for sending a Follow-up to the Peer. + * @param[in] fup_params Configuration parameters for sending a Follow-up to the Peer. + * @param[out] context Context returned for Follow-up frame to be matched in Tx done. * * @return * - ESP_OK: succeed * - others: failed */ -esp_err_t esp_nan_internal_send_followup(const wifi_nan_followup_params_t *fup_params); +esp_err_t esp_nan_internal_send_followup(const wifi_nan_followup_params_t *fup_params, uint32_t *context); /** * @brief Send Datapath Request to the Publisher with matching service @@ -750,6 +764,19 @@ esp_err_t esp_nan_internal_datapath_resp(wifi_nan_datapath_resp_t *resp); */ esp_err_t esp_nan_internal_datapath_end(wifi_nan_datapath_end_req_t *req); +/** + * @brief End NAN Datapath that is active + * + * @attention This API should be called after receiving WIFI_EVENT_NDP_CONFIRM event. + * + * @param req NAN Datapath end request parameters. + * + * @return + * - ESP_OK: succeed + * - others: failed + */ +esp_err_t esp_nan_internal_register_callbacks(struct nan_callbacks *cb); + /** * @brief Connect WiFi station to the AP. * diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index e87a28e2ded5..80f6e6d50dcc 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit e87a28e2ded519804ebbe1605ba9eee988262ecd +Subproject commit 80f6e6d50dcc7afbab4f2cb452e8194d0cd630e5 diff --git a/components/esp_wifi/test_apps/wifi_connect/pytest_wifi_connect.py b/components/esp_wifi/test_apps/wifi_connect/pytest_wifi_connect.py index 24a6076a2c25..ac724c1f05c0 100644 --- a/components/esp_wifi/test_apps/wifi_connect/pytest_wifi_connect.py +++ b/components/esp_wifi/test_apps/wifi_connect/pytest_wifi_connect.py @@ -11,14 +11,14 @@ @pytest.mark.esp32c5 @pytest.mark.esp32c6 @pytest.mark.esp32c61 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize('count', [2], indirect=True) def test_wifi_connect_cases(case_tester: CaseTester) -> None: # type: ignore case_tester.run_all_cases() @pytest.mark.esp32c2 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.xtal_26mhz @pytest.mark.parametrize( 'count, config, baud', @@ -32,7 +32,7 @@ def test_wifi_connect_cases_esp32c2_xtal26m(case_tester: CaseTester) -> None: @pytest.mark.esp32c2eco4 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.xtal_26mhz @pytest.mark.parametrize( 'count, config, target, baud', @@ -45,7 +45,7 @@ def test_wifi_connect_cases_esp32c2eco4_xtal26m(case_tester: CaseTester) -> None case_tester.run_all_cases() -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.esp32c3eco7 @pytest.mark.parametrize( 'count, config, target', diff --git a/components/esp_wifi/wifi_apps/nan_app/src/nan_app.c b/components/esp_wifi/wifi_apps/nan_app/src/nan_app.c index c4f62fba2c9a..a524a0059dc9 100644 --- a/components/esp_wifi/wifi_apps/nan_app/src/nan_app.c +++ b/components/esp_wifi/wifi_apps/nan_app/src/nan_app.c @@ -23,19 +23,22 @@ #define NAN_STOPPED_BIT BIT1 /* NAN Events */ -#define NDP_INDICATION BIT2 -#define NDP_ACCEPTED BIT3 -#define NDP_TERMINATED BIT4 -#define NDP_REJECTED BIT5 +#define NAN_TX_SUCCESS BIT2 +#define NAN_TX_FAILURE BIT3 +#define NDP_INDICATION BIT4 +#define NDP_ACCEPTED BIT5 +#define NDP_TERMINATED BIT6 +#define NDP_REJECTED BIT7 /* Macros */ #define MACADDR_LEN 6 #define MACADDR_EQUAL(a1, a2) (memcmp(a1, a2, MACADDR_LEN)) #define MACADDR_COPY(dst, src) (memcpy(dst, src, MACADDR_LEN)) #define NAN_DW_INTVL_MS 524 /* NAN DW interval (512 TU's ~= 524 mSec) */ -#define NAN_NDP_RESP_TIMEOUT_DW 8 -#define NAN_NDP_RESP_TIMEOUT NAN_NDP_RESP_TIMEOUT_DW*NAN_DW_INTVL_MS -#define NAN_NDP_TERM_TIMEOUT 2*NAN_DW_INTVL_MS /* NDP Termination Timeout - 2 DW*/ +#define NAN_ACTION_TIMEOUT 4*NAN_DW_INTVL_MS + +#define NAN_DATA_LOCK() os_mutex_lock(s_nan_data_lock) +#define NAN_DATA_UNLOCK() os_mutex_unlock(s_nan_data_lock) /* Global Variables */ static const char *TAG = "nan_app"; @@ -44,9 +47,12 @@ static bool s_app_default_handlers_set = false; static uint8_t null_mac[MACADDR_LEN] = {0}; static void *s_nan_data_lock = NULL; static const uint8_t s_wfa_oui[3] = {0x50, 0x6f, 0x9a}; +static uint32_t s_fup_context; -#define NAN_DATA_LOCK() os_mutex_lock(s_nan_data_lock) -#define NAN_DATA_UNLOCK() os_mutex_unlock(s_nan_data_lock) +/* Definitions */ +#define NAN_SDEA_CTRL_FSD_REQD BIT(0) +#define NAN_SDEA_CTRL_FSD_GAS BIT(1) +#define NAN_SDEA_CTRL_DATAPATH_REQD BIT(2) struct peer_svc_info { SLIST_ENTRY(peer_svc_info) next; @@ -373,178 +379,254 @@ static bool nan_is_datapath_active(void) return false; } -static void nan_fill_params_from_event(void *evt_data, uint8_t event) +/* types of ipv6 addresses to be displayed on ipv6 events */ +static const char *s_ipv6_addr_types[] = { + "UNKNOWN", + "GLOBAL", + "LINK_LOCAL", + "SITE_LOCAL", + "UNIQUE_LOCAL", + "IPV4_MAPPED_IPV6" +}; + +static void nan_app_action_got_ipv6(void *arg, esp_event_base_t event_base, int32_t event_id, void *data) { - switch (event) { - case WIFI_EVENT_NDP_INDICATION: { - wifi_event_ndp_indication_t *evt = (wifi_event_ndp_indication_t *)evt_data; - nan_record_new_ndl(evt->ndp_id, evt->publish_id, evt->peer_nmi, ESP_WIFI_NDP_ROLE_RESPONDER); - break; - } - case WIFI_EVENT_NDP_CONFIRM: { - wifi_event_ndp_confirm_t *evt = (wifi_event_ndp_confirm_t *)evt_data; - struct ndl_info *ndl = NULL; - - if ((ndl = nan_find_ndl(evt->ndp_id, evt->peer_nmi)) == NULL) { - ESP_LOGE(TAG, "No NDL with ndp id %d", evt->ndp_id); - return; - } - MACADDR_COPY(ndl->peer_ndi, evt->peer_ndi); - break; + if (data == NULL) { + return; } - case WIFI_EVENT_NAN_REPLIED: { - wifi_event_nan_replied_t *evt = (wifi_event_nan_replied_t *)evt_data; + ip_event_got_ip6_t *event = (ip_event_got_ip6_t *)data; - if (!nan_find_peer_svc(evt->publish_id, evt->subscribe_id, evt->sub_if_mac)) { - nan_record_peer_svc(evt->publish_id, evt->subscribe_id, evt->sub_if_mac); - } - break; + NAN_DATA_LOCK(); + if (event->esp_netif == s_nan_ctx.nan_netif) { + esp_ip6_addr_type_t ipv6_type = esp_netif_ip6_get_addr_type(&event->ip6_info.ip); + ESP_LOGD(TAG, "NAN Data Interface ready [IPv6 - "IPV6STR", type - %s]", + IPV62STR(event->ip6_info.ip), s_ipv6_addr_types[ipv6_type]); } - case WIFI_EVENT_NAN_RECEIVE: { - wifi_event_nan_receive_t *evt = (wifi_event_nan_receive_t *)evt_data; + NAN_DATA_UNLOCK(); +} - if (!nan_find_peer_svc(evt->inst_id, evt->peer_inst_id, evt->peer_if_mac)) { - nan_record_peer_svc(evt->inst_id, evt->peer_inst_id, evt->peer_if_mac); - } - break; - } - case WIFI_EVENT_NAN_SVC_MATCH: { - wifi_event_nan_svc_match_t *evt = (wifi_event_nan_svc_match_t *)evt_data; - struct peer_svc_info *peer_info = nan_find_peer_svc(evt->subscribe_id, 0, evt->pub_if_mac); +static esp_err_t nan_clear_app_default_handlers(void) +{ + esp_event_handler_unregister(IP_EVENT, IP_EVENT_GOT_IP6, nan_app_action_got_ipv6); + s_app_default_handlers_set = false; - if (peer_info && peer_info->svc_id != evt->publish_id) { - struct ndl_info *ndl = nan_find_ndl(0, evt->pub_if_mac); + return ESP_OK; +} - peer_info->svc_id = evt->publish_id; - if (ndl) { - ndl->publisher_id = evt->publish_id; - } - } else { - nan_record_peer_svc(evt->subscribe_id, evt->publish_id, evt->pub_if_mac); - } - break; - } - default: - break; +static esp_err_t nan_set_app_default_handlers(void) +{ + if (s_app_default_handlers_set) { + return ESP_OK; } + + int ret; + (void) ret; + ESP_GOTO_ON_ERROR(esp_event_handler_register(IP_EVENT, IP_EVENT_GOT_IP6, + nan_app_action_got_ipv6, NULL), fail, TAG, "Registering event handler failed"); + + s_app_default_handlers_set = true; + return ESP_OK; + +fail: + nan_clear_app_default_handlers(); + return ESP_FAIL; } -static void nan_app_action_service_match(void *arg, esp_event_base_t event_base, int32_t event_id, void *data) +static void nan_app_post_event(int32_t event_id, void* event_data, size_t event_data_size) { - if (data == NULL) { - return; - } - wifi_event_nan_svc_match_t *evt = (wifi_event_nan_svc_match_t *)data; + g_wifi_osi_funcs._event_post(WIFI_EVENT, event_id, event_data, event_data_size, OSI_FUNCS_TIME_BLOCKING); +} - ESP_LOGI(TAG, "Service matched with "MACSTR" [Peer Publish id - %d]", - MAC2STR(evt->pub_if_mac), evt->publish_id); +void nan_app_service_match_cb(uint8_t sub_id, uint8_t pub_id, uint8_t pub_mac[6], uint16_t capab, + uint8_t ssi_ver, uint8_t *ssi, uint16_t ssi_len) +{ + NAN_DATA_LOCK(); + struct peer_svc_info *peer_info = nan_find_peer_svc(sub_id, 0, pub_mac); - if (evt->ssi_len) { - ESP_LOG_BUFFER_HEXDUMP(TAG, evt->ssi, evt->ssi_len, ESP_LOG_DEBUG); + if (peer_info && peer_info->svc_id != pub_id) { + struct ndl_info *ndl = nan_find_ndl(0, pub_mac); + + peer_info->svc_id = pub_id; + if (ndl) { + ndl->publisher_id = pub_id; + } + } else { + nan_record_peer_svc(sub_id, pub_id, pub_mac); } - NAN_DATA_LOCK(); - nan_fill_params_from_event(evt, WIFI_EVENT_NAN_SVC_MATCH); NAN_DATA_UNLOCK(); -} -static void nan_app_action_replied(void *arg, esp_event_base_t event_base, int32_t event_id, void *data) -{ - if (data == NULL) { + size_t evt_data_len = sizeof(wifi_event_nan_svc_match_t) + ssi_len; + wifi_event_nan_svc_match_t *evt = (wifi_event_nan_svc_match_t *)os_zalloc(evt_data_len); + if (!evt) { + ESP_LOGE(TAG, "Failed to allocate for event"); return; } - wifi_event_nan_replied_t *evt = (wifi_event_nan_replied_t *)data; - ESP_LOGI(TAG, "Sent Publish to Peer "MACSTR" [Peer Subscribe id - %d]", - MAC2STR(evt->sub_if_mac), evt->subscribe_id); - - if (evt->ssi_len) { - ESP_LOG_BUFFER_HEXDUMP(TAG, evt->ssi, evt->ssi_len, ESP_LOG_DEBUG); + evt->subscribe_id = sub_id; + evt->publish_id = pub_id; + MACADDR_COPY(evt->pub_if_mac, pub_mac); + evt->update_pub_id = false; + evt->fsd_reqd = (capab & NAN_SDEA_CTRL_FSD_REQD) ? 1 : 0; + evt->fsd_gas = (capab & NAN_SDEA_CTRL_FSD_GAS) ? 1 : 0; + evt->datapath_reqd = (capab & NAN_SDEA_CTRL_DATAPATH_REQD) ? 1 : 0; + evt->ssi_version = ssi_ver; + if (ssi && ssi_len) { + if (ssi_ver) { + evt->ssi_version = ssi_ver; + } + memcpy(evt->ssi, ssi, ssi_len); + evt->ssi_len = ssi_len; + ESP_LOG_BUFFER_HEXDUMP(TAG, ssi, ssi_len, ESP_LOG_DEBUG); } - NAN_DATA_LOCK(); - nan_fill_params_from_event(evt, WIFI_EVENT_NAN_REPLIED); - NAN_DATA_UNLOCK(); + + ESP_LOGI(TAG, "Service matched with "MACSTR" [Peer Publish id - %d]", + MAC2STR(pub_mac), pub_id); + + nan_app_post_event(WIFI_EVENT_NAN_SVC_MATCH, evt, evt_data_len); + os_free(evt); } -static void nan_app_action_receive(void *arg, esp_event_base_t event_base, int32_t event_id, void *data) +void nan_app_replied_cb(uint8_t pub_id, uint8_t sub_id, uint8_t sub_nmi[6], uint8_t *ssi, uint16_t ssi_len) { - if (data == NULL) { + NAN_DATA_LOCK(); + if (!nan_find_peer_svc(pub_id, sub_id, sub_nmi)) { + nan_record_peer_svc(pub_id, sub_id, sub_nmi); + } + NAN_DATA_UNLOCK(); + + size_t evt_data_len = sizeof(wifi_event_nan_replied_t) + ssi_len; + + wifi_event_nan_replied_t *evt = (wifi_event_nan_replied_t *)os_zalloc(evt_data_len); + if (!evt) { + ESP_LOGE(TAG, "Failed to allocate for event"); return; } - wifi_event_nan_receive_t *evt = (wifi_event_nan_receive_t *)data; + evt->publish_id = pub_id; + evt->subscribe_id = sub_id; + MACADDR_COPY(evt->sub_if_mac, sub_nmi); - if (evt->ssi_len) { - ESP_LOGD(TAG, "Received payload from Peer "MACSTR" [Peer Service id - %d] - ", MAC2STR(evt->peer_if_mac), evt->peer_inst_id); - ESP_LOG_BUFFER_HEXDUMP(TAG, evt->ssi, evt->ssi_len, ESP_LOG_DEBUG); - } else { - ESP_LOGD(TAG, "Received message '%s' from Peer "MACSTR" [Peer Service id - %d]", - evt->peer_svc_info, MAC2STR(evt->peer_if_mac), evt->peer_inst_id); + ESP_LOGI(TAG, "Sent Publish to Peer "MACSTR" [Peer Subscribe id - %d]", MAC2STR(sub_nmi), sub_id); + if (ssi && ssi_len) { + memcpy(evt->ssi, ssi, ssi_len); + evt->ssi_len = ssi_len; + ESP_LOG_BUFFER_HEXDUMP(TAG, ssi, ssi_len, ESP_LOG_DEBUG); } - NAN_DATA_LOCK(); - nan_fill_params_from_event(evt, WIFI_EVENT_NAN_RECEIVE); - NAN_DATA_UNLOCK(); + nan_app_post_event(WIFI_EVENT_NAN_REPLIED, evt, sizeof(wifi_event_nan_replied_t)); + os_free(evt); } -static void nan_app_action_ndp_indication(void *arg, esp_event_base_t event_base, int32_t event_id, void *data) +void nan_app_receive_cb(uint8_t svc_id, uint8_t peer_svc_id, uint8_t peer_mac[6], uint8_t *ssi, uint16_t ssi_len) { - if (data == NULL) { + NAN_DATA_LOCK(); + if (!nan_find_peer_svc(svc_id, peer_svc_id, peer_mac)) { + nan_record_peer_svc(svc_id, peer_svc_id, peer_mac); + } + NAN_DATA_UNLOCK(); + + size_t evt_data_len = sizeof(wifi_event_nan_receive_t) + ssi_len; + wifi_event_nan_receive_t *evt = (wifi_event_nan_receive_t *)os_zalloc(evt_data_len); + if (!evt) { + ESP_LOGE(TAG, "Failed to allocate for event"); return; } - wifi_event_ndp_indication_t *evt = (wifi_event_ndp_indication_t *)data; + evt->inst_id = svc_id; + evt->peer_inst_id = peer_svc_id; + MACADDR_COPY(evt->peer_if_mac, peer_mac); + if (ssi && ssi_len) { + memcpy(evt->ssi, ssi, ssi_len); + evt->ssi_len = ssi_len; + if (ssi_len < ESP_WIFI_MAX_SVC_INFO_LEN) { + memcpy(evt->peer_svc_info, ssi, ssi_len); + } + ESP_LOGD(TAG, "Received payload from Peer "MACSTR" [Peer Service id - %d] - ", MAC2STR(peer_mac), peer_svc_id); + ESP_LOG_BUFFER_HEXDUMP(TAG, ssi, ssi_len, ESP_LOG_DEBUG); + } + + nan_app_post_event(WIFI_EVENT_NAN_RECEIVE, evt, evt_data_len); + os_free(evt); +} + +void nan_app_ndp_indication_cb(uint8_t pub_id, uint8_t ndp_id, uint8_t peer_nmi[6], uint8_t peer_ndi[6], + uint8_t *ssi, uint16_t ssi_len) +{ NAN_DATA_LOCK(); - struct own_svc_info *p_own_svc = nan_find_own_svc(evt->publish_id); + struct own_svc_info *p_own_svc = nan_find_own_svc(pub_id); if (!p_own_svc) { - ESP_LOGE(TAG, "No Publish found with id %d", evt->publish_id); - goto done; + ESP_LOGE(TAG, "No Publish found with id %d", pub_id); + NAN_DATA_UNLOCK(); + return; } if (ndl_limit_reached()) { ESP_LOGE(TAG, "NDP limit reached"); - goto done; + NAN_DATA_UNLOCK(); + return; } - nan_fill_params_from_event(evt, WIFI_EVENT_NDP_INDICATION); + nan_record_new_ndl(ndp_id, pub_id, peer_nmi, ESP_WIFI_NDP_ROLE_RESPONDER); + if (p_own_svc->ndp_resp_needed) { ESP_LOGI(TAG, "NDP Req from "MACSTR" [NDP Id: %d], Accept OR Deny using NDP command", - MAC2STR(evt->peer_nmi), evt->ndp_id); + MAC2STR(peer_nmi), ndp_id); s_nan_ctx.event |= NDP_INDICATION; } else { wifi_nan_datapath_resp_t ndp_resp = {0}; ndp_resp.accept = true; - ndp_resp.ndp_id = evt->ndp_id; - MACADDR_COPY(ndp_resp.peer_mac, evt->peer_nmi); + ndp_resp.ndp_id = ndp_id; + MACADDR_COPY(ndp_resp.peer_mac, peer_nmi); esp_nan_internal_datapath_resp(&ndp_resp); } - -done: NAN_DATA_UNLOCK(); + + size_t evt_data_len = sizeof(wifi_event_ndp_indication_t) + ssi_len; + wifi_event_ndp_indication_t *evt = (wifi_event_ndp_indication_t *)os_zalloc(evt_data_len); + if (!evt) { + ESP_LOGE(TAG, "Failed to allocate for event"); + return; + } + + evt->publish_id = pub_id; + evt->ndp_id = ndp_id; + MACADDR_COPY(evt->peer_nmi, peer_nmi); + MACADDR_COPY(evt->peer_ndi, peer_ndi); + if (ssi && ssi_len) { + memcpy(evt->ssi, ssi, ssi_len); + evt->ssi_len = ssi_len; + if (ssi_len < ESP_WIFI_MAX_SVC_INFO_LEN) { + memcpy(evt->svc_info, ssi, ssi_len); + } + ESP_LOG_BUFFER_HEXDUMP(TAG, ssi, ssi_len, ESP_LOG_DEBUG); + } + + nan_app_post_event(WIFI_EVENT_NDP_INDICATION, evt, evt_data_len); + os_free(evt); } -static void nan_app_action_ndp_confirm(void *arg, esp_event_base_t event_base, int32_t event_id, void *data) +void nan_app_ndp_confirm_cb(uint8_t status, uint8_t ndp_id, uint8_t peer_nmi[6], uint8_t peer_ndi[6], + uint8_t own_ndi[6], uint8_t *ssi, uint16_t ssi_len) { - if (data == NULL) { + NAN_DATA_LOCK(); + struct ndl_info *ndl = nan_find_ndl(ndp_id, peer_nmi); + if (!ndl) { + ESP_LOGE(TAG, "No NDL with ndp id %d", ndp_id); + NAN_DATA_UNLOCK(); return; } - wifi_event_ndp_confirm_t *evt = (wifi_event_ndp_confirm_t *)data; + MACADDR_COPY(ndl->peer_ndi, peer_ndi); - NAN_DATA_LOCK(); wifi_netif_driver_t driver = esp_netif_get_io_driver(s_nan_ctx.nan_netif); - ip_addr_t target_addr = {0}; if (!s_nan_ctx.nan_netif) { ESP_LOGE(TAG, "%s: NAN netif is NULL", __func__); goto done; } - if (nan_find_ndl(evt->ndp_id, NULL) == NULL) { - /* As ndl isn't found, timeout has occurred for NDP response and datapath request is rejected */ - goto done; - } - if (evt->status == NDP_STATUS_REJECTED) { - ESP_LOGE(TAG, "NDP request to Peer "MACSTR" rejected [NDP ID - %d]", MAC2STR(evt->peer_nmi), evt->ndp_id); - nan_reset_ndl(evt->ndp_id, false); + if (status == NDP_STATUS_REJECTED) { + ESP_LOGE(TAG, "NDP request to Peer "MACSTR" rejected [NDP ID - %d]", MAC2STR(peer_nmi), ndp_id); + nan_reset_ndl(ndp_id, false); os_event_group_set_bits(nan_event_group, NDP_REJECTED); goto done; } @@ -555,17 +637,45 @@ static void nan_app_action_ndp_confirm(void *arg, esp_event_base_t event_base, i goto done; } - nan_fill_params_from_event(evt, WIFI_EVENT_NDP_CONFIRM); + size_t evt_data_len = sizeof(wifi_event_ndp_confirm_t) + ssi_len; + wifi_event_ndp_confirm_t *evt = (wifi_event_ndp_confirm_t *)os_zalloc(evt_data_len); + if (!evt) { + wifi_nan_datapath_end_req_t ndp_end = {0}; - esp_netif_action_connected(s_nan_ctx.nan_netif, event_base, event_id, data); + MACADDR_COPY(ndp_end.peer_mac, peer_nmi); + ndp_end.ndp_id = ndp_id; + esp_nan_internal_datapath_end(&ndp_end); + ESP_LOGE(TAG, "Failed to allocate for event, terminate NDP"); + nan_reset_ndl(ndp_id, false); + goto done; + } + evt->status = status; + evt->ndp_id = ndp_id; + MACADDR_COPY(evt->peer_nmi, peer_nmi); + MACADDR_COPY(evt->peer_ndi, peer_ndi); + MACADDR_COPY(evt->own_ndi, own_ndi); + if (ssi && ssi_len) { + memcpy(evt->ssi, ssi, ssi_len); + evt->ssi_len = ssi_len; + if (ssi_len < ESP_WIFI_MAX_SVC_INFO_LEN) { + memcpy(evt->svc_info, ssi, ssi_len); + } + ESP_LOG_BUFFER_HEXDUMP(TAG, ssi, ssi_len, ESP_LOG_DEBUG); + } + esp_netif_action_connected(s_nan_ctx.nan_netif, WIFI_EVENT, WIFI_EVENT_NDP_CONFIRM, evt); esp_netif_create_ip6_linklocal(s_nan_ctx.nan_netif); NAN_DATA_UNLOCK(); - esp_wifi_nan_get_ipv6_linklocal_from_mac(&target_addr.u_addr.ip6, evt->peer_ndi); + + ip_addr_t target_addr = {0}; + esp_wifi_nan_get_ipv6_linklocal_from_mac(&target_addr.u_addr.ip6, peer_ndi); target_addr.type = IPADDR_TYPE_V6; ESP_LOGI(TAG, "NDP confirmed with Peer "MACSTR" [NDP ID - %d, Peer IPv6 - %s]", - MAC2STR(evt->peer_nmi), evt->ndp_id, inet6_ntoa(*ip_2_ip6(&target_addr))); + MAC2STR(peer_nmi), ndp_id, inet6_ntoa(*ip_2_ip6(&target_addr))); os_event_group_set_bits(nan_event_group, NDP_ACCEPTED); + + nan_app_post_event(WIFI_EVENT_NDP_CONFIRM, evt, evt_data_len); + os_free(evt); return; done: @@ -573,100 +683,41 @@ static void nan_app_action_ndp_confirm(void *arg, esp_event_base_t event_base, i return; } -static void nan_app_action_ndp_terminated(void *arg, esp_event_base_t event_base, int32_t event_id, void *data) +void nan_app_ndp_terminated_cb(uint8_t reason, uint8_t ndp_id, uint8_t init_ndi[6]) { - if (data == NULL) { - return; - } - wifi_event_ndp_terminated_t *evt = (wifi_event_ndp_terminated_t *)data; - NAN_DATA_LOCK(); if (s_nan_ctx.nan_netif && !nan_is_datapath_active()) { - esp_netif_action_disconnected(s_nan_ctx.nan_netif, event_base, event_id, data); + esp_netif_action_disconnected(s_nan_ctx.nan_netif, WIFI_EVENT, WIFI_EVENT_NDP_TERMINATED, NULL); } - ESP_LOGI(TAG, "NDP terminated with Peer "MACSTR" [NDP ID - %d]", MAC2STR(evt->init_ndi), evt->ndp_id); - nan_reset_ndl(evt->ndp_id, false); + ESP_LOGI(TAG, "NDP terminated with Peer "MACSTR" [NDP ID - %d]", MAC2STR(init_ndi), ndp_id); + nan_reset_ndl(ndp_id, false); s_nan_ctx.event &= ~(NDP_INDICATION); NAN_DATA_UNLOCK(); - os_event_group_set_bits(nan_event_group, NDP_TERMINATED); -} -/* types of ipv6 addresses to be displayed on ipv6 events */ -static const char *s_ipv6_addr_types[] = { - "UNKNOWN", - "GLOBAL", - "LINK_LOCAL", - "SITE_LOCAL", - "UNIQUE_LOCAL", - "IPV4_MAPPED_IPV6" -}; - -static void nan_app_action_got_ipv6(void *arg, esp_event_base_t event_base, int32_t event_id, void *data) -{ - if (data == NULL) { + wifi_event_ndp_terminated_t *evt = (wifi_event_ndp_terminated_t *)os_zalloc(sizeof(wifi_event_ndp_terminated_t)); + if (!evt) { + ESP_LOGE(TAG, "Failed to allocate for event"); return; } - ip_event_got_ip6_t *event = (ip_event_got_ip6_t *)data; - - NAN_DATA_LOCK(); - if (event->esp_netif == s_nan_ctx.nan_netif) { - esp_ip6_addr_type_t ipv6_type = esp_netif_ip6_get_addr_type(&event->ip6_info.ip); - ESP_LOGD(TAG, "NAN Data Interface ready [IPv6 - "IPV6STR", type - %s]", - IPV62STR(event->ip6_info.ip), s_ipv6_addr_types[ipv6_type]); - } - NAN_DATA_UNLOCK(); -} + evt->reason = reason; + evt->ndp_id = ndp_id; + MACADDR_COPY(evt->init_ndi, init_ndi); -static esp_err_t nan_clear_app_default_handlers(void) -{ - esp_event_handler_unregister(WIFI_EVENT, WIFI_EVENT_NAN_SVC_MATCH, nan_app_action_service_match); - esp_event_handler_unregister(WIFI_EVENT, WIFI_EVENT_NAN_REPLIED, nan_app_action_replied); - esp_event_handler_unregister(WIFI_EVENT, WIFI_EVENT_NAN_RECEIVE, nan_app_action_receive); - esp_event_handler_unregister(WIFI_EVENT, WIFI_EVENT_NDP_INDICATION, nan_app_action_ndp_indication); - esp_event_handler_unregister(WIFI_EVENT, WIFI_EVENT_NDP_CONFIRM, nan_app_action_ndp_confirm); - esp_event_handler_unregister(WIFI_EVENT, WIFI_EVENT_NDP_TERMINATED, nan_app_action_ndp_terminated); - esp_event_handler_unregister(IP_EVENT, IP_EVENT_GOT_IP6, nan_app_action_got_ipv6); - s_app_default_handlers_set = false; - - return ESP_OK; + nan_app_post_event(WIFI_EVENT_NDP_TERMINATED, evt, sizeof(wifi_event_ndp_terminated_t)); + os_free(evt); + os_event_group_set_bits(nan_event_group, NDP_TERMINATED); } -static esp_err_t nan_set_app_default_handlers(void) +void nan_action_txdone_cb(uint32_t context, bool tx_status) { - if (s_app_default_handlers_set) { - return ESP_OK; + if (nan_event_group && s_fup_context == context) { + if (tx_status) { + os_event_group_set_bits(nan_event_group, NAN_TX_SUCCESS); + } else { + os_event_group_set_bits(nan_event_group, NAN_TX_FAILURE); + } } - - int ret; - (void) ret; - ESP_GOTO_ON_ERROR(esp_event_handler_register(WIFI_EVENT, WIFI_EVENT_NAN_SVC_MATCH, - nan_app_action_service_match, NULL), fail, TAG, "Registering event handler failed"); - - ESP_GOTO_ON_ERROR(esp_event_handler_register(WIFI_EVENT, WIFI_EVENT_NAN_REPLIED, - nan_app_action_replied, NULL), fail, TAG, "Registering event handler failed"); - - ESP_GOTO_ON_ERROR(esp_event_handler_register(WIFI_EVENT, WIFI_EVENT_NAN_RECEIVE, - nan_app_action_receive, NULL), fail, TAG, "Registering event handler failed"); - - ESP_GOTO_ON_ERROR(esp_event_handler_register(WIFI_EVENT, WIFI_EVENT_NDP_INDICATION, - nan_app_action_ndp_indication, NULL), fail, TAG, "Registering event handler failed"); - - ESP_GOTO_ON_ERROR(esp_event_handler_register(WIFI_EVENT, WIFI_EVENT_NDP_CONFIRM, - nan_app_action_ndp_confirm, NULL), fail, TAG, "Registering event handler failed"); - - ESP_GOTO_ON_ERROR(esp_event_handler_register(WIFI_EVENT, WIFI_EVENT_NDP_TERMINATED, - nan_app_action_ndp_terminated, NULL), fail, TAG, "Registering event handler failed"); - - ESP_GOTO_ON_ERROR(esp_event_handler_register(IP_EVENT, IP_EVENT_GOT_IP6, - nan_app_action_got_ipv6, NULL), fail, TAG, "Registering event handler failed"); - - s_app_default_handlers_set = true; - return ESP_OK; - -fail: - nan_clear_app_default_handlers(); - return ESP_FAIL; } void esp_nan_app_deinit(void) @@ -699,23 +750,31 @@ void esp_nan_app_init(void) void esp_nan_action_start(esp_netif_t *nan_netif) { - if (nan_set_app_default_handlers() != ESP_OK) { - ESP_LOGE(TAG, "Registering NAN handlers failed"); - return; - } + nan_set_app_default_handlers(); NAN_DATA_LOCK(); s_nan_ctx.nan_netif = nan_netif; s_nan_ctx.state = NAN_STARTED_BIT; NAN_DATA_UNLOCK(); + struct nan_callbacks nan_cb = { + .service_match = nan_app_service_match_cb, + .replied = nan_app_replied_cb, + .receive = nan_app_receive_cb, + .ndp_indication = nan_app_ndp_indication_cb, + .ndp_confirm = nan_app_ndp_confirm_cb, + .ndp_terminated = nan_app_ndp_terminated_cb, + .action_txdone = nan_action_txdone_cb, + }; + esp_nan_internal_register_callbacks(&nan_cb); + ESP_LOGI(TAG, "NAN Discovery started."); os_event_group_set_bits(nan_event_group, NAN_STARTED_BIT); } void esp_nan_action_stop(void) { - nan_clear_app_default_handlers(); + nan_clear_app_default_handlers(); NAN_DATA_LOCK(); if (nan_is_datapath_active()) { @@ -728,6 +787,7 @@ void esp_nan_action_stop(void) s_nan_ctx.state |= NAN_STOPPED_BIT; NAN_DATA_UNLOCK(); + esp_nan_internal_register_callbacks(NULL); os_event_group_set_bits(nan_event_group, NAN_STOPPED_BIT); } @@ -804,9 +864,6 @@ esp_err_t esp_wifi_nan_stop(void) nan_reset_ndl(0, true); NAN_DATA_UNLOCK(); - os_event_group_clear_bits(nan_event_group, NDP_TERMINATED); - os_event_group_wait_bits(nan_event_group, NDP_TERMINATED, pdFALSE, pdFALSE, pdMS_TO_TICKS(NAN_NDP_TERM_TIMEOUT)); - os_event_group_clear_bits(nan_event_group, NDP_TERMINATED); /* Wait for 1 NAN DW interval (512 TU's ~= 524 mSec) for successful termination */ g_wifi_osi_funcs._task_delay(NAN_DW_INTVL_MS/portTICK_PERIOD_MS); } else { @@ -925,6 +982,7 @@ uint8_t esp_wifi_nan_subscribe_service(const wifi_nan_subscribe_cfg_t *subscribe esp_err_t esp_wifi_nan_send_message(wifi_nan_followup_params_t *fup_params) { struct peer_svc_info *p_peer_svc; + esp_err_t ret = ESP_OK; NAN_DATA_LOCK(); p_peer_svc = nan_find_peer_svc(fup_params->inst_id, fup_params->peer_inst_id, @@ -960,20 +1018,29 @@ esp_err_t esp_wifi_nan_send_message(wifi_nan_followup_params_t *fup_params) } NAN_DATA_UNLOCK(); - if (esp_nan_internal_send_followup(fup_params) != ESP_OK) { + os_event_group_clear_bits(nan_event_group, NAN_TX_SUCCESS | NAN_TX_FAILURE); + if ((ret = esp_nan_internal_send_followup(fup_params, &s_fup_context)) != ESP_OK) { ESP_LOGE(TAG, "Failed to send Follow-up message!"); - return ESP_FAIL; + return ret; } - if (fup_params->ssi) { - ESP_LOGD(TAG, "Sent below payload to Peer "MACSTR" with Service ID %d", - MAC2STR(fup_params->peer_mac), fup_params->peer_inst_id); - ESP_LOG_BUFFER_HEXDUMP(TAG, fup_params->ssi, fup_params->ssi_len, ESP_LOG_DEBUG); + EventBits_t bits = os_event_group_wait_bits(nan_event_group, NAN_TX_SUCCESS | NAN_TX_FAILURE, pdFALSE, pdFALSE, pdMS_TO_TICKS(NAN_ACTION_TIMEOUT)); + if (bits & NAN_TX_SUCCESS) { + if (fup_params->ssi) { + ESP_LOGD(TAG, "Sent below payload to Peer "MACSTR" with Service ID %d", + MAC2STR(fup_params->peer_mac), fup_params->peer_inst_id); + ESP_LOG_BUFFER_HEXDUMP(TAG, fup_params->ssi, fup_params->ssi_len, ESP_LOG_DEBUG); + } + ret = ESP_OK; + } else if (bits & NAN_TX_FAILURE) { + ESP_LOGE(TAG, "Failed to send Follow-up message!"); + ret = ESP_FAIL; } else { - ESP_LOGI(TAG, "Sent message '%s' to Peer "MACSTR" with Service ID %d", fup_params->svc_info, - MAC2STR(fup_params->peer_mac), fup_params->peer_inst_id); + ESP_LOGE(TAG, "Timeout, failed to send Follow-up message!"); + ret = ESP_FAIL; } - return ESP_OK; + + return ret; } esp_err_t esp_wifi_nan_cancel_service(uint8_t service_id) @@ -1038,6 +1105,7 @@ uint8_t esp_wifi_nan_datapath_req(wifi_nan_datapath_req_t *req) MACADDR_COPY(req->peer_mac, p_peer_svc->peer_nmi); } + os_event_group_clear_bits(nan_event_group, NDP_ACCEPTED | NDP_REJECTED); if (esp_nan_internal_datapath_req(req, &ndp_id) != ESP_OK) { ESP_LOGE(TAG, "Failed to initiate NDP req"); goto fail; @@ -1048,14 +1116,13 @@ uint8_t esp_wifi_nan_datapath_req(wifi_nan_datapath_req_t *req) ESP_LOGD(TAG, "Requested NDP with "MACSTR" [NDP ID - %d]", MAC2STR(req->peer_mac), ndp_id); - EventBits_t bits = os_event_group_wait_bits(nan_event_group, NDP_ACCEPTED | NDP_REJECTED, pdFALSE, pdFALSE, pdMS_TO_TICKS(NAN_NDP_RESP_TIMEOUT)); + EventBits_t bits = os_event_group_wait_bits(nan_event_group, NDP_ACCEPTED | NDP_REJECTED, pdFALSE, pdFALSE, pdMS_TO_TICKS(NAN_ACTION_TIMEOUT)); if (bits & NDP_ACCEPTED) { - os_event_group_clear_bits(nan_event_group, NDP_ACCEPTED); return ndp_id; } else if (bits & NDP_REJECTED) { - os_event_group_clear_bits(nan_event_group, NDP_REJECTED); return 0; } else { + ESP_LOGE(TAG, "NDP request timed out"); NAN_DATA_LOCK(); nan_reset_ndl(ndp_id, false); NAN_DATA_UNLOCK(); @@ -1098,6 +1165,7 @@ esp_err_t esp_wifi_nan_datapath_resp(wifi_nan_datapath_resp_t *resp) esp_err_t esp_wifi_nan_datapath_end(wifi_nan_datapath_end_req_t *req) { struct ndl_info *ndl = NULL; + esp_err_t ret; NAN_DATA_LOCK(); if (!nan_is_datapath_active()) { @@ -1118,11 +1186,19 @@ esp_err_t esp_wifi_nan_datapath_end(wifi_nan_datapath_end_req_t *req) } NAN_DATA_UNLOCK(); - if (esp_nan_internal_datapath_end(req) == ESP_OK) { - return ESP_OK; + os_event_group_clear_bits(nan_event_group, NDP_TERMINATED); + ret = esp_nan_internal_datapath_end(req); + if (ret != ESP_OK) { + ESP_LOGE(TAG, "Failed to end NDP with id %d (ret %d)", req->ndp_id, ret); + return ret; + } + EventBits_t bits = os_event_group_wait_bits(nan_event_group, NDP_TERMINATED, pdTRUE, pdFALSE, pdMS_TO_TICKS(NAN_ACTION_TIMEOUT)); + if (!(bits & NDP_TERMINATED)) { + ESP_LOGE(TAG, "Failed to end NDP with id %d", req->ndp_id); + return ESP_FAIL; } - return ESP_FAIL; + return ESP_OK; } esp_err_t esp_wifi_nan_get_own_svc_info(uint8_t *own_svc_id, char *svc_name, int *num_peer_records) diff --git a/components/hal/color_hal.c b/components/hal/color_hal.c index c26b3db6a659..632785999487 100644 --- a/components/hal/color_hal.c +++ b/components/hal/color_hal.c @@ -28,6 +28,10 @@ uint32_t color_hal_pixel_format_get_bit_depth(color_space_pixel_format_t format) return 12; case COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565): case COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422): + case COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_UYVY422): + case COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_VYUY422): + case COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUYV422): + case COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YVYU422): return 16; case COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB666): return 18; diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/hal/esp32/include/hal/gpio_ll.h index 7b08194ddc37..ba3640bbd24a 100644 --- a/components/hal/esp32/include/hal/gpio_ll.h +++ b/components/hal/esp32/include/hal/gpio_ll.h @@ -711,7 +711,7 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32c2/include/hal/gpio_ll.h b/components/hal/esp32c2/include/hal/gpio_ll.h index 2412a39c00a0..c1c71c6c74c1 100644 --- a/components/hal/esp32c2/include/hal/gpio_ll.h +++ b/components/hal/esp32c2/include/hal/gpio_ll.h @@ -513,7 +513,7 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/hal/esp32c3/include/hal/gpio_ll.h index dde10281de04..809ddf9a31c9 100644 --- a/components/hal/esp32c3/include/hal/gpio_ll.h +++ b/components/hal/esp32c3/include/hal/gpio_ll.h @@ -503,7 +503,7 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32c5/include/hal/gpio_ll.h b/components/hal/esp32c5/include/hal/gpio_ll.h index 80f92f4d97eb..e4197886781d 100644 --- a/components/hal/esp32c5/include/hal/gpio_ll.h +++ b/components/hal/esp32c5/include/hal/gpio_ll.h @@ -489,7 +489,7 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32c6/include/hal/gpio_ll.h b/components/hal/esp32c6/include/hal/gpio_ll.h index d19bbd566b1b..2e79ad4898e9 100644 --- a/components/hal/esp32c6/include/hal/gpio_ll.h +++ b/components/hal/esp32c6/include/hal/gpio_ll.h @@ -475,7 +475,7 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32c61/include/hal/gpio_ll.h b/components/hal/esp32c61/include/hal/gpio_ll.h index ab73eebd969a..0dc4e24a3bf7 100644 --- a/components/hal/esp32c61/include/hal/gpio_ll.h +++ b/components/hal/esp32c61/include/hal/gpio_ll.h @@ -521,7 +521,7 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32h2/include/hal/gpio_ll.h b/components/hal/esp32h2/include/hal/gpio_ll.h index 5ac5faa53e5a..09a711703e97 100644 --- a/components/hal/esp32h2/include/hal/gpio_ll.h +++ b/components/hal/esp32h2/include/hal/gpio_ll.h @@ -538,7 +538,7 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32p4/include/hal/dma2d_ll.h b/components/hal/esp32p4/include/hal/dma2d_ll.h index f36fcdd433b3..8c0fab888467 100644 --- a/components/hal/esp32p4/include/hal/dma2d_ll.h +++ b/components/hal/esp32p4/include/hal/dma2d_ll.h @@ -11,8 +11,10 @@ #include "hal/dma2d_types.h" #include "soc/dma2d_channel.h" #include "soc/dma2d_struct.h" +#include "soc/soc_caps.h" #include "hal/misc.h" #include "hal/assert.h" +#include "hal/config.h" #include "soc/soc.h" #include "soc/hp_sys_clkrst_struct.h" @@ -22,6 +24,14 @@ extern "C" { #define DMA2D_LL_GET_HW(id) (((id) == 0) ? (&DMA2D) : NULL) +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +#define DMA2D_LL_TX_CHANNELS_PER_GROUP SOC_DMA2D_TX_CHANNELS_PER_GROUP // Number of 2D-DMA TX (OUT) channels in each group +#define DMA2D_LL_RX_CHANNELS_PER_GROUP SOC_DMA2D_RX_CHANNELS_PER_GROUP // Number of 2D-DMA RX (IN) channels in each group +#else +#define DMA2D_LL_TX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA TX (OUT) channels in each group +#define DMA2D_LL_RX_CHANNELS_PER_GROUP (2) // Number of 2D-DMA RX (IN) channels in each group +#endif + // 2D-DMA interrupts #define DMA2D_LL_RX_EVENT_MASK (0x3FFF) #define DMA2D_LL_TX_EVENT_MASK (0x1FFF) @@ -57,8 +67,11 @@ extern "C" { // Bit masks that are used to indicate availability of some sub-features in the channels #define DMA2D_LL_TX_CHANNEL_SUPPORT_RO_MASK (0U | BIT0) // TX channels that support reorder feature +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +#define DMA2D_LL_TX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0 | BIT1 | BIT2 | BIT3) // TX channels that support color space conversion feature +#else #define DMA2D_LL_TX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0 | BIT1 | BIT2) // TX channels that support color space conversion feature - +#endif #define DMA2D_LL_RX_CHANNEL_SUPPORT_RO_MASK (0U | BIT0) // RX channels that support reorder feature #define DMA2D_LL_RX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0) // RX channels that support color space conversion feature @@ -158,16 +171,13 @@ static inline uint32_t dma2d_ll_get_scramble_order_sel(dma2d_scramble_order_t or } /////////////////////////////////////// RX /////////////////////////////////////////// -#define DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, ch, reg) ((volatile void*[]){&dev->in_channel0.reg, &dev->in_channel1.reg}[(ch)]) - /** * @brief Get 2D-DMA RX channel interrupt status word */ __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_get_interrupt_status(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_int_st_chn_reg_t *reg = (volatile dma2d_in_int_st_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_st); - return reg->val; + return dev->in_channel[channel].in_int_st.val & DMA2D_LL_RX_EVENT_MASK; } /** @@ -176,11 +186,10 @@ static inline uint32_t dma2d_ll_rx_get_interrupt_status(dma2d_dev_t *dev, uint32 __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_interrupt(dma2d_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) { - volatile dma2d_in_int_ena_chn_reg_t *reg = (volatile dma2d_in_int_ena_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_ena); if (enable) { - reg->val = reg->val | (mask & DMA2D_LL_RX_EVENT_MASK); + dev->in_channel[channel].in_int_ena.val = dev->in_channel[channel].in_int_ena.val | (mask & DMA2D_LL_RX_EVENT_MASK); } else { - reg->val = reg->val & ~(mask & DMA2D_LL_RX_EVENT_MASK); + dev->in_channel[channel].in_int_ena.val = dev->in_channel[channel].in_int_ena.val & ~(mask & DMA2D_LL_RX_EVENT_MASK); } } @@ -190,8 +199,7 @@ static inline void dma2d_ll_rx_enable_interrupt(dma2d_dev_t *dev, uint32_t chann __attribute__((always_inline)) static inline void dma2d_ll_rx_clear_interrupt_status(dma2d_dev_t *dev, uint32_t channel, uint32_t mask) { - volatile dma2d_in_int_clr_chn_reg_t *reg = (volatile dma2d_in_int_clr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_clr); - reg->val = (mask & DMA2D_LL_RX_EVENT_MASK); + dev->in_channel[channel].in_int_clr.val = (mask & DMA2D_LL_RX_EVENT_MASK); } /** @@ -199,7 +207,7 @@ static inline void dma2d_ll_rx_clear_interrupt_status(dma2d_dev_t *dev, uint32_t */ static inline volatile void *dma2d_ll_rx_get_interrupt_status_reg(dma2d_dev_t *dev, uint32_t channel) { - return (volatile void *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_st); + return (volatile void *)(&dev->in_channel[channel].in_int_st); } /** @@ -208,8 +216,7 @@ static inline volatile void *dma2d_ll_rx_get_interrupt_status_reg(dma2d_dev_t *d __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_owner_check(dma2d_dev_t *dev, uint32_t channel, bool enable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_check_owner_chn = enable; + dev->in_channel[channel].in_conf0.in_check_owner_chn = enable; } /** @@ -218,8 +225,7 @@ static inline void dma2d_ll_rx_enable_owner_check(dma2d_dev_t *dev, uint32_t cha __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_page_bound_wrap(dma2d_dev_t *dev, uint32_t channel, bool enable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_page_bound_en_chn = enable; + dev->in_channel[channel].in_conf0.in_page_bound_en_chn = enable; } /** @@ -249,8 +255,7 @@ static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t // Unsupported data burst length abort(); } - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_mem_burst_length_chn = sel; + dev->in_channel[channel].in_conf0.in_mem_burst_length_chn = sel; } /** @@ -259,8 +264,7 @@ static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_descriptor_burst(dma2d_dev_t *dev, uint32_t channel, bool enable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->indscr_burst_en_chn = enable; + dev->in_channel[channel].in_conf0.indscr_burst_en_chn = enable; } /** @@ -269,9 +273,8 @@ static inline void dma2d_ll_rx_enable_descriptor_burst(dma2d_dev_t *dev, uint32_ __attribute__((always_inline)) static inline void dma2d_ll_rx_reset_channel(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_rst_chn = 1; - reg->in_rst_chn = 0; + dev->in_channel[channel].in_conf0.in_rst_chn = 1; + dev->in_channel[channel].in_conf0.in_rst_chn = 0; } /** @@ -280,8 +283,7 @@ static inline void dma2d_ll_rx_reset_channel(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline bool dma2d_ll_rx_is_reset_avail(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_state_chn_reg_t *reg = (volatile dma2d_in_state_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_state); - return reg->in_reset_avail_chn; + return dev->in_channel[channel].in_state.in_reset_avail_chn; } /** @@ -290,8 +292,7 @@ static inline bool dma2d_ll_rx_is_reset_avail(dma2d_dev_t *dev, uint32_t channel __attribute__((always_inline)) static inline void dma2d_ll_rx_abort(dma2d_dev_t *dev, uint32_t channel, bool disable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_cmd_disable_chn = disable; + dev->in_channel[channel].in_conf0.in_cmd_disable_chn = disable; } /** @@ -300,8 +301,7 @@ static inline void dma2d_ll_rx_abort(dma2d_dev_t *dev, uint32_t channel, bool di __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_dscr_port(dma2d_dev_t *dev, uint32_t channel, bool enable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_dscr_port_en_chn = enable; + dev->in_channel[channel].in_conf0.in_dscr_port_en_chn = enable; } /** @@ -328,8 +328,7 @@ static inline void dma2d_ll_rx_set_macro_block_size(dma2d_dev_t *dev, uint32_t c // Unsupported macro block size abort(); } - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_macro_block_size_chn = sel; + dev->in_channel[channel].in_conf0.in_macro_block_size_chn = sel; } /** @@ -338,9 +337,8 @@ static inline void dma2d_ll_rx_set_macro_block_size(dma2d_dev_t *dev, uint32_t c __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_pop_data(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_pop_chn_reg_t *reg = (volatile dma2d_in_pop_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_pop); - reg->infifo_pop_chn = 1; - return reg->infifo_rdata_chn; + dev->in_channel[channel].in_pop.infifo_pop_chn = 1; + return dev->in_channel[channel].in_pop.infifo_rdata_chn; } /** @@ -349,8 +347,7 @@ static inline uint32_t dma2d_ll_rx_pop_data(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline void dma2d_ll_rx_set_desc_addr(dma2d_dev_t *dev, uint32_t channel, uint32_t addr) { - volatile dma2d_in_link_addr_chn_reg_t *reg = (volatile dma2d_in_link_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_addr); - reg->inlink_addr_chn = addr; + dev->in_channel[channel].in_link_addr.inlink_addr_chn = addr; } /** @@ -359,8 +356,7 @@ static inline void dma2d_ll_rx_set_desc_addr(dma2d_dev_t *dev, uint32_t channel, __attribute__((always_inline)) static inline void dma2d_ll_rx_start(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf); - reg->inlink_start_chn = 1; + dev->in_channel[channel].in_link_conf.inlink_start_chn = 1; } /** @@ -369,8 +365,7 @@ static inline void dma2d_ll_rx_start(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline void dma2d_ll_rx_stop(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf); - reg->inlink_stop_chn = 1; + dev->in_channel[channel].in_link_conf.inlink_stop_chn = 1; } /** @@ -379,8 +374,7 @@ static inline void dma2d_ll_rx_stop(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline void dma2d_ll_rx_restart(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf); - reg->inlink_restart_chn = 1; + dev->in_channel[channel].in_link_conf.inlink_restart_chn = 1; } /** @@ -389,8 +383,7 @@ static inline void dma2d_ll_rx_restart(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline void dma2d_ll_rx_set_auto_return_owner(dma2d_dev_t *dev, uint32_t channel, int owner) { - volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf); - reg->inlink_auto_ret_chn = owner; + dev->in_channel[channel].in_link_conf.inlink_auto_ret_chn = owner; } /** @@ -399,8 +392,7 @@ static inline void dma2d_ll_rx_set_auto_return_owner(dma2d_dev_t *dev, uint32_t __attribute__((always_inline)) static inline bool dma2d_ll_rx_is_desc_fsm_idle(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf); - return reg->inlink_park_chn; + return dev->in_channel[channel].in_link_conf.inlink_park_chn; } /** @@ -409,8 +401,7 @@ static inline bool dma2d_ll_rx_is_desc_fsm_idle(dma2d_dev_t *dev, uint32_t chann __attribute__((always_inline)) static inline bool dma2d_ll_rx_is_fsm_idle(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_state_chn_reg_t *reg = (volatile dma2d_in_state_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_state); - return (reg->in_state_chn == 0); + return (dev->in_channel[channel].in_state.in_state_chn == 0); } /** @@ -419,8 +410,7 @@ static inline bool dma2d_ll_rx_is_fsm_idle(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_get_success_eof_desc_addr(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_suc_eof_des_addr_chn_reg_t *reg = (volatile dma2d_in_suc_eof_des_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_suc_eof_des_addr); - return reg->val; + return dev->in_channel[channel].in_suc_eof_des_addr.val; } /** @@ -429,8 +419,7 @@ static inline uint32_t dma2d_ll_rx_get_success_eof_desc_addr(dma2d_dev_t *dev, u __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_get_error_eof_desc_addr(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_err_eof_des_addr_chn_reg_t *reg = (volatile dma2d_in_err_eof_des_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_err_eof_des_addr); - return reg->val; + return dev->in_channel[channel].in_err_eof_des_addr.val; } /** @@ -439,18 +428,7 @@ static inline uint32_t dma2d_ll_rx_get_error_eof_desc_addr(dma2d_dev_t *dev, uin __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_get_prefetched_desc_addr(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_dscr_chn_reg_t *reg = (volatile dma2d_in_dscr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_dscr); - return reg->val; -} - -/** - * @brief Set priority for 2D-DMA RX channel - */ -__attribute__((always_inline)) -static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t prio) -{ - volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb); - reg->in_arb_priority_chn = prio; + return dev->in_channel[channel].in_dscr.val; } /** @@ -459,10 +437,8 @@ static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel, __attribute__((always_inline)) static inline void dma2d_ll_rx_connect_to_periph(dma2d_dev_t *dev, uint32_t channel, dma2d_trigger_peripheral_t periph, int periph_id) { - volatile dma2d_in_peri_sel_chn_reg_t *peri_sel_reg = (volatile dma2d_in_peri_sel_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_peri_sel); - peri_sel_reg->in_peri_sel_chn = periph_id; - volatile dma2d_in_conf0_chn_reg_t *conf0_reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - conf0_reg->in_mem_trans_en_chn = (periph == DMA2D_TRIG_PERIPH_M2M); + dev->in_channel[channel].in_peri_sel.in_peri_sel_chn = periph_id; + dev->in_channel[channel].in_conf0.in_mem_trans_en_chn = (periph == DMA2D_TRIG_PERIPH_M2M); } /** @@ -471,10 +447,8 @@ static inline void dma2d_ll_rx_connect_to_periph(dma2d_dev_t *dev, uint32_t chan __attribute__((always_inline)) static inline void dma2d_ll_rx_disconnect_from_periph(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_peri_sel_chn_reg_t *peri_sel_reg = (volatile dma2d_in_peri_sel_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_peri_sel); - peri_sel_reg->in_peri_sel_chn = DMA2D_LL_CHANNEL_PERIPH_NO_CHOICE; - volatile dma2d_in_conf0_chn_reg_t *conf0_reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - conf0_reg->in_mem_trans_en_chn = false; + dev->in_channel[channel].in_peri_sel.in_peri_sel_chn = DMA2D_LL_CHANNEL_PERIPH_NO_CHOICE; + dev->in_channel[channel].in_conf0.in_mem_trans_en_chn = false; } // REORDER FUNCTION (Only CH0 supports this feature) @@ -485,8 +459,7 @@ static inline void dma2d_ll_rx_disconnect_from_periph(dma2d_dev_t *dev, uint32_t __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_reorder(dma2d_dev_t *dev, uint32_t channel, bool enable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_reorder_en_chn = enable; + dev->in_channel[channel].in_conf0.in_reorder_en_chn = enable; } // COLOR SPACE CONVERSION FUNCTION @@ -524,6 +497,17 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint proc_en = false; output_sel = 1; break; + case DMA2D_CSC_RX_YUV444_TO_YUV422: + input_sel = 0; + proc_en = false; + output_sel = 2; + break; + case DMA2D_CSC_RX_YUV444_TO_YUV420: + case DMA2D_CSC_RX_YUV422_TO_YUV420: + input_sel = 0; + proc_en = false; + output_sel = 3; + break; case DMA2D_CSC_RX_YUV420_TO_RGB888_601: case DMA2D_CSC_RX_YUV422_TO_RGB888_601: input_sel = 0; @@ -581,13 +565,13 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint abort(); } - dev->in_channel0.in_color_convert.in_color_input_sel_chn = input_sel; - dev->in_channel0.in_color_convert.in_color_3b_proc_en_chn = proc_en; - dev->in_channel0.in_color_convert.in_color_output_sel_chn = output_sel; + dev->in_channel[channel].in_color_convert.in_color_input_sel_chn = input_sel; + dev->in_channel[channel].in_color_convert.in_color_3b_proc_en_chn = proc_en; + dev->in_channel[channel].in_color_convert.in_color_output_sel_chn = output_sel; if (proc_en) { HAL_ASSERT(table); - typeof(dev->in_channel0.in_color_param_group) color_param_group; + typeof(dev->in_channel[channel].in_color_param_group) color_param_group; color_param_group.param_h.a = table[0][0]; color_param_group.param_h.b = table[0][1]; @@ -604,12 +588,12 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint color_param_group.param_l.c = table[2][2]; color_param_group.param_l.d = table[2][3]; - dev->in_channel0.in_color_param_group.param_h.val[0] = color_param_group.param_h.val[0]; - dev->in_channel0.in_color_param_group.param_h.val[1] = color_param_group.param_h.val[1]; - dev->in_channel0.in_color_param_group.param_m.val[0] = color_param_group.param_m.val[0]; - dev->in_channel0.in_color_param_group.param_m.val[1] = color_param_group.param_m.val[1]; - dev->in_channel0.in_color_param_group.param_l.val[0] = color_param_group.param_l.val[0]; - dev->in_channel0.in_color_param_group.param_l.val[1] = color_param_group.param_l.val[1]; + dev->in_channel[channel].in_color_param_group.param_h.val[0] = color_param_group.param_h.val[0]; + dev->in_channel[channel].in_color_param_group.param_h.val[1] = color_param_group.param_h.val[1]; + dev->in_channel[channel].in_color_param_group.param_m.val[0] = color_param_group.param_m.val[0]; + dev->in_channel[channel].in_color_param_group.param_m.val[1] = color_param_group.param_m.val[1]; + dev->in_channel[channel].in_color_param_group.param_l.val[0] = color_param_group.param_l.val[0]; + dev->in_channel[channel].in_color_param_group.param_l.val[1] = color_param_group.param_l.val[1]; } } @@ -620,7 +604,7 @@ __attribute__((always_inline)) static inline void dma2d_ll_rx_set_csc_pre_scramble(dma2d_dev_t *dev, uint32_t channel, dma2d_scramble_order_t order) { HAL_ASSERT(channel == 0); // Only channel 0 supports scramble - dev->in_channel0.in_scramble.in_scramble_sel_pre_chn = dma2d_ll_get_scramble_order_sel(order); + dev->in_channel[channel].in_scramble.in_scramble_sel_pre_chn = dma2d_ll_get_scramble_order_sel(order); } /** @@ -630,7 +614,7 @@ __attribute__((always_inline)) static inline void dma2d_ll_rx_set_csc_post_scramble(dma2d_dev_t *dev, uint32_t channel, dma2d_scramble_order_t order) { HAL_ASSERT(channel == 0); // Only channel 0 supports scramble - dev->in_channel0.in_scramble.in_scramble_sel_post_chn = dma2d_ll_get_scramble_order_sel(order); + dev->in_channel[channel].in_scramble.in_scramble_sel_post_chn = dma2d_ll_get_scramble_order_sel(order); } // Arbiter @@ -659,8 +643,7 @@ static inline void dma2d_ll_rx_set_arb_timeout(dma2d_dev_t *dev, uint32_t timeou __attribute__((always_inline)) static inline void dma2d_ll_rx_set_arb_token_num(dma2d_dev_t *dev, uint32_t channel, uint32_t token_num) { - volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb); - reg->in_arb_token_num_chn = token_num; + dev->in_channel[channel].in_arb.in_arb_token_num_chn = token_num; } /** @@ -669,20 +652,22 @@ static inline void dma2d_ll_rx_set_arb_token_num(dma2d_dev_t *dev, uint32_t chan __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_get_arb_token_num(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb); - return reg->in_arb_token_num_chn; + return dev->in_channel[channel].in_arb.in_arb_token_num_chn; } /** - * @brief Set 2D-DMA RX channel arbiter priority + * @brief Set priority for 2D-DMA RX channel */ __attribute__((always_inline)) -static inline void dma2d_ll_rx_set_arb_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority) +static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority) { - volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb); - reg->in_arb_priority_chn = priority; + dev->in_channel[channel].in_arb.in_arb_priority_chn = priority; } +// ETM + +// note that in_ch1 in_etm_conf register addr is different before and after rev3 chip! + /////////////////////////////////////// TX /////////////////////////////////////////// /** * @brief Get 2D-DMA TX channel interrupt status word @@ -954,15 +939,6 @@ static inline uint32_t dma2d_ll_tx_get_prefetched_desc_addr(dma2d_dev_t *dev, ui return dev->out_channel[channel].out_dscr.val; } -/** - * @brief Set priority for 2D-DMA TX channel - */ -__attribute__((always_inline)) -static inline void dma2d_ll_tx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t prio) -{ - dev->out_channel[channel].out_arb.out_arb_priority_chn = prio; -} - /** * @brief Connect 2D-DMA TX channel to a given peripheral */ @@ -1165,10 +1141,10 @@ static inline uint32_t dma2d_ll_tx_get_arb_token_num(dma2d_dev_t *dev, uint32_t } /** - * @brief Set 2D-DMA TX channel arbiter priority + * @brief Set priority for 2D-DMA TX channel */ __attribute__((always_inline)) -static inline void dma2d_ll_tx_set_arb_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority) +static inline void dma2d_ll_tx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority) { dev->out_channel[channel].out_arb.out_arb_priority_chn = priority; } diff --git a/components/hal/esp32p4/include/hal/gpio_ll.h b/components/hal/esp32p4/include/hal/gpio_ll.h index cc3a44cf358b..b2619ffe630d 100644 --- a/components/hal/esp32p4/include/hal/gpio_ll.h +++ b/components/hal/esp32p4/include/hal/gpio_ll.h @@ -22,6 +22,7 @@ #include "soc/io_mux_reg.h" #include "soc/io_mux_struct.h" #include "soc/hp_system_struct.h" +#include "soc/lp_system_struct.h" #include "soc/lp_iomux_struct.h" #include "soc/hp_sys_clkrst_struct.h" #include "soc/pmu_struct.h" @@ -31,6 +32,7 @@ #include "hal/gpio_types.h" #include "hal/misc.h" #include "hal/assert.h" +#include "hal/config.h" #ifdef __cplusplus extern "C" { @@ -504,6 +506,13 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu __attribute__((always_inline)) static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) { +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + if (gpio_num < 32) { + LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 |= (1 << gpio_num); + } else { + LP_SYS.pad_rtc_hold_ctrl1.pad_rtc_hold_ctrl1 |= (1 << (gpio_num - 32)); + } +#else uint64_t bit_mask = 1ULL << gpio_num; if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) { // GPIO 0-15 @@ -519,6 +528,7 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high |= (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT)); } } +#endif } /** @@ -530,6 +540,13 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) { +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + if (gpio_num < 32) { + LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 &= ~(1 << gpio_num); + } else { + LP_SYS.pad_rtc_hold_ctrl1.pad_rtc_hold_ctrl1 &= ~(1 << (gpio_num - 32)); + } +#else uint64_t bit_mask = 1ULL << gpio_num; if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) { // GPIO 0-15 @@ -545,6 +562,7 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high &= ~(bit_mask >> (32 + SOC_RTCIO_PIN_COUNT)); } } +#endif } /** @@ -567,6 +585,13 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) // GPIO 0-15 abort(); } else { +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + if (gpio_num < 32) { + return !!(LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 & (1 << gpio_num)); + } else { + return !!(LP_SYS.pad_rtc_hold_ctrl1.pad_rtc_hold_ctrl1 & (1 << (gpio_num - 32))); + } +#else if (gpio_num < 32 + SOC_RTCIO_PIN_COUNT) { // GPIO 16-47 return !!(HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low & (bit_mask >> SOC_RTCIO_PIN_COUNT)); @@ -574,6 +599,7 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) // GPIO 48-54 return !!(HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high & (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT))); } +#endif } } @@ -632,7 +658,7 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32p4/include/hal/i2s_ll.h b/components/hal/esp32p4/include/hal/i2s_ll.h index 65aeb6e9f888..7240f9f00aca 100644 --- a/components/hal/esp32p4/include/hal/i2s_ll.h +++ b/components/hal/esp32p4/include/hal/i2s_ll.h @@ -1139,7 +1139,8 @@ static inline void i2s_ll_tx_set_pdm_hp_filter_param5(i2s_dev_t *hw, uint32_t pa */ static inline void i2s_ll_tx_enable_pdm_hp_filter(i2s_dev_t *hw, bool enable) { - hw->tx_pcm2pdm_conf.tx_pdm_hp_bypass = !enable; + // Must enable on P4 + HAL_ASSERT(enable); } /** diff --git a/components/hal/esp32p4/include/hal/isp_ll.h b/components/hal/esp32p4/include/hal/isp_ll.h index 00712b12564c..0dd0da87561d 100644 --- a/components/hal/esp32p4/include/hal/isp_ll.h +++ b/components/hal/esp32p4/include/hal/isp_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,6 +13,7 @@ #include "hal/hal_utils.h" #include "hal/isp_types.h" #include "hal/color_types.h" +#include "hal/config.h" #include "soc/isp_struct.h" #include "soc/hp_sys_clkrst_struct.h" #include "soc/clk_tree_defs.h" @@ -65,11 +66,14 @@ extern "C" { #define ISP_LL_EVENT_YUV2RGB_FRAME (1<<26) #define ISP_LL_EVENT_TAIL_IDI_FRAME (1<<27) #define ISP_LL_EVENT_HEADER_IDI_FRAME (1<<28) +#define ISP_LL_EVENT_CROP_FRAME (1<<29) +#define ISP_LL_EVENT_WBG_FRAME (1<<30) +#define ISP_LL_EVENT_CROP_ERR (1<<31) #define ISP_LL_EVENT_ALL_MASK (0x1FFFFFFF) #define ISP_LL_EVENT_AF_MASK (ISP_LL_EVENT_AF_FDONE | ISP_LL_EVENT_AF_ENV) #define ISP_LL_EVENT_AE_MASK (ISP_LL_EVENT_AE_FDONE | ISP_LL_EVENT_AE_ENV) -#define ISP_LL_EVENT_AWB_MASK (ISP_LL_EVENT_AWB_FDONE) +#define ISP_LL_EVENT_AWB_MASK (ISP_LL_EVENT_AWB_FDONE | ISP_LL_EVENT_WBG_FRAME) #define ISP_LL_EVENT_SHARP_MASK (ISP_LL_EVENT_SHARP_FRAME) #define ISP_LL_EVENT_HIST_MASK (ISP_LL_EVENT_HIST_FDONE) #define ISP_LL_EVENT_COLOR_MASK (ISP_LL_EVENT_COLOR_FRAME) @@ -165,8 +169,35 @@ typedef union { typedef enum { ISP_LL_LUT_LSC, ///< LUT for LSC ISP_LL_LUT_DPC, ///< LUT for DPC + ISP_LL_LUT_AWB, ///< LUT for AWB } isp_ll_lut_t; +/** + * @brief ISP LUT AWB type + */ +typedef enum { + ISP_LL_LUT_AWB_WHITE_PATCH_CNT, ///< White patch count + ISP_LL_LUT_AWB_ACCUMULATED_R, ///< Accumulated R + ISP_LL_LUT_AWB_ACCUMULATED_G, ///< Accumulated G + ISP_LL_LUT_AWB_ACCUMULATED_B, ///< Accumulated B +} isp_ll_lut_awb_t; + +/** + * @brief ISP pipeline clock control mode + */ +typedef enum { + ISP_LL_PIPELINE_CLK_CTRL_AUTO, ///< HW control, off when in frame interval + ISP_LL_PIPELINE_CLK_CTRL_ALWAYS_ON, ///< Always on +} isp_ll_pipeline_clk_ctrl_t; + +/** + * @brief Shadow mode + */ +typedef enum { + ISP_SHADOW_MODE_DISABLE, + ISP_SHADOW_MODE_UPDATE_EVERY_VSYNC, + ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC, +} isp_ll_shadow_mode_t; /*--------------------------------------------------------------- Clock @@ -495,14 +526,14 @@ static inline void isp_ll_set_bayer_mode(isp_dev_t *hw, color_raw_element_order_ AF ---------------------------------------------------------------*/ /** - * @brief Enable / Disable AF clock + * @brief Set AF clock control mode * * @param[in] hw - * @param[in] enable Enable / Disable + * @param[in] mode 'isp_ll_pipeline_clk_ctrl_t` */ -static inline void isp_ll_af_clk_enable(isp_dev_t *hw, bool enable) +static inline void isp_ll_af_set_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode) { - hw->clk_en.clk_af_force_on = enable; + hw->clk_en.clk_af_force_on = mode; } /** @@ -730,14 +761,14 @@ static inline void isp_ll_af_env_detector_set_ratio(isp_dev_t *hw, uint32_t rati BF ---------------------------------------------------------------*/ /** - * @brief Enable / Disable BF clock + * @brief Set BF clock control mode * * @param[in] hw Hardware instance address - * @param[in] enable Enable / Disable + * @param[in] mode 'isp_ll_pipeline_clk_ctrl_t` */ -static inline void isp_ll_bf_clk_enable(isp_dev_t *hw, bool enable) +static inline void isp_ll_bf_set_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode) { - hw->clk_en.clk_bf_force_on = enable; + hw->clk_en.clk_bf_force_on = mode; } /** @@ -829,17 +860,121 @@ static inline void isp_ll_bf_set_template(isp_dev_t *hw, uint8_t template_arr[SO } /*--------------------------------------------------------------- - CCM + BLC ---------------------------------------------------------------*/ /** - * @brief Enable / Disable CCM clock + * @brief Set BLC clock control mode + * + * @param[in] hw Hardware instance address + * @param[in] mode 'isp_ll_pipeline_clk_ctrl_t` + */ +static inline void isp_ll_blc_set_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode) +{ + hw->clk_en.clk_blc_force_on = mode; +} + +/** + * @brief Enable / Disable BLC + * + * @param[in] hw Hardware instance address + * @param[in] enable Enable / Disable + */ +static inline void isp_ll_blc_enable(isp_dev_t *hw, bool enable) +{ + hw->cntl.blc_en = enable; +} + +/** + * @brief Set BLC correction offset + * + * @param[in] hw Hardware instance address + * @param[in] top_left_chan_offset Correction offset for top left channel of the raw Bayer image + * @param[in] top_right_chan_offset Correction offset for top right channel of the raw Bayer image + * @param[in] bottom_left_chan_offset Correction offset for bottom left channel of the raw Bayer image + * @param[in] bottom_right_chan_offset Correction offset for bottom right channel of the raw Bayer image + */ +static inline void isp_ll_blc_set_correction_offset(isp_dev_t *hw, uint32_t top_left_chan_offset, uint32_t top_right_chan_offset, uint32_t bottom_left_chan_offset, uint32_t bottom_right_chan_offset) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->blc_value, blc_r0_value, top_left_chan_offset); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->blc_value, blc_r1_value, top_right_chan_offset); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->blc_value, blc_r2_value, bottom_left_chan_offset); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->blc_value, blc_r3_value, bottom_right_chan_offset); +} + +/** + * @brief Enable / Disable BLC stretch + * + * @param[in] hw Hardware instance address + * @param[in] top_left_chan_stretch_en Enable / Disable stretch for top left channel of the raw Bayer image + * @param[in] top_right_chan_stretch_en Enable / Disable stretch for top right channel of the raw Bayer image + * @param[in] bottom_left_chan_stretch_en Enable / Disable stretch for bottom left channel of the raw Bayer image + * @param[in] bottom_right_chan_stretch_en Enable / Disable stretch for bottom right channel of the raw Bayer image + */ +static inline void isp_ll_blc_enable_stretch(isp_dev_t *hw, bool top_left_chan_stretch_en, bool top_right_chan_stretch_en, bool bottom_left_chan_stretch_en, bool bottom_right_chan_stretch_en) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->blc_ctrl0, blc_r0_stretch, top_left_chan_stretch_en); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->blc_ctrl0, blc_r1_stretch, top_right_chan_stretch_en); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->blc_ctrl0, blc_r2_stretch, bottom_left_chan_stretch_en); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->blc_ctrl0, blc_r3_stretch, bottom_right_chan_stretch_en); +} + +/** + * @brief Set BLC window + * + * @param[in] hw Hardware instance address + * @param[in] x_start X start position + * @param[in] y_start Y start position + * @param[in] x_size X size + * @param[in] y_size Y size + */ +static inline void isp_ll_blc_set_window(isp_dev_t *hw, uint32_t x_start, uint32_t y_start, uint32_t x_size, uint32_t y_size) +{ + hw->blc_ctrl1.blc_window_top = y_start; + hw->blc_ctrl1.blc_window_left = x_start; + hw->blc_ctrl1.blc_window_vnum = y_size; + hw->blc_ctrl1.blc_window_hnum = x_size; +} + +/** + * @brief Set BLC filter threshold + * + * @param[in] hw Hardware instance address + * @param[in] top_left_chan_thresh Filter threshold for top left channel of the raw Bayer image + * @param[in] top_right_chan_thresh Filter threshold for top right channel of the raw Bayer image + * @param[in] bottom_left_chan_thresh Filter threshold for bottom left channel of the raw Bayer image + * @param[in] bottom_right_chan_thresh Filter threshold for bottom right channel of the raw Bayer image + */ +static inline void isp_ll_blc_set_filter_threshold(isp_dev_t *hw, uint32_t top_left_chan_thresh, uint32_t top_right_chan_thresh, uint32_t bottom_left_chan_thresh, uint32_t bottom_right_chan_thresh) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->blc_ctrl2, blc_r0_th, top_left_chan_thresh); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->blc_ctrl2, blc_r1_th, top_right_chan_thresh); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->blc_ctrl2, blc_r2_th, bottom_left_chan_thresh); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->blc_ctrl2, blc_r3_th, bottom_right_chan_thresh); +} + +/** + * @brief Enable / Disable BLC filter * * @param[in] hw Hardware instance address * @param[in] enable Enable / Disable */ -static inline void isp_ll_ccm_clk_enable(isp_dev_t *hw, bool enable) +static inline void isp_ll_blc_enable_filter(isp_dev_t *hw, bool enable) +{ + hw->blc_ctrl1.blc_filter_en = enable; +} + +/*--------------------------------------------------------------- + CCM +---------------------------------------------------------------*/ +/** + * @brief Set CCM clock control mode + * + * @param[in] hw Hardware instance address + * @param[in] mode 'isp_ll_pipeline_clk_ctrl_t` + */ +static inline void isp_ll_ccm_set_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode) { - hw->clk_en.clk_ccm_force_on = enable; + hw->clk_en.clk_ccm_force_on = mode; } /** @@ -876,14 +1011,14 @@ static inline void isp_ll_ccm_set_matrix(isp_dev_t *hw, isp_ll_ccm_gain_t fixed_ Color ---------------------------------------------------------------*/ /** - * @brief Enable / Disable Color clock + * @brief Set Color clock control mode * * @param[in] hw Hardware instance address - * @param[in] enable Enable / Disable + * @param[in] mode 'isp_ll_pipeline_clk_ctrl_t` */ -static inline void isp_ll_color_clk_enable(isp_dev_t *hw, bool enable) +static inline void isp_ll_color_set_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode) { - hw->clk_en.clk_color_force_on = enable; + hw->clk_en.clk_color_force_on = mode; } /** @@ -1071,14 +1206,14 @@ static inline void isp_ll_cam_enable(isp_dev_t *hw, bool enable) ---------------------------------------------------------------*/ /** - * @brief Enable / Disable AE clock + * @brief Set AE clock control mode * * @param[in] hw Hardware instance address - * @param[in] enable Enable / Disable + * @param[in] mode 'isp_ll_pipeline_clk_ctrl_t` */ -static inline void isp_ll_ae_clk_enable(isp_dev_t *hw, bool enable) +static inline void isp_ll_ae_set_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode) { - hw->clk_en.clk_ae_force_on = enable; + hw->clk_en.clk_ae_force_on = mode; } /** @@ -1185,14 +1320,14 @@ static inline void isp_ll_ae_env_detector_set_period(isp_dev_t *hw, uint32_t per LSC ---------------------------------------------------------------*/ /** - * @brief Enable / Disable LSC clock + * @brief Set LSC clock control mode * * @param[in] hw Hardware instance address - * @param[in] enable Enable / Disable + * @param[in] mode 'isp_ll_pipeline_clk_ctrl_t` */ -static inline void isp_ll_lsc_clk_enable(isp_dev_t *hw, bool enable) +static inline void isp_ll_lsc_set_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode) { - hw->clk_en.clk_lsc_force_on = enable; + hw->clk_en.clk_lsc_force_on = mode; } /** @@ -1221,7 +1356,7 @@ static inline void isp_ll_lsc_set_xtablesize(isp_dev_t *hw, uint8_t xtablesize) LUT ---------------------------------------------------------------*/ /** - * @brief Select ISP LUT + * @brief Select ISP LUT for LSC usage * * @param[in] hw Hardware instance address * @param[in] is_write Is write or not @@ -1229,7 +1364,7 @@ static inline void isp_ll_lsc_set_xtablesize(isp_dev_t *hw, uint8_t xtablesize) * @param[in] addr LUT addr * @param[in] lut ISP LUT */ -static inline void isp_ll_lut_set_cmd(isp_dev_t *hw, bool is_write, bool is_gb_b, uint32_t addr, isp_ll_lut_t lut) +static inline void isp_ll_lut_lsc_set_cmd(isp_dev_t *hw, bool is_write, bool is_gb_b, uint32_t addr, isp_ll_lut_t lut) { uint32_t val = 0; val |= is_write ? (1 << 16) : 0; @@ -1246,7 +1381,7 @@ static inline void isp_ll_lut_set_cmd(isp_dev_t *hw, bool is_write, bool is_gb_b * @param[in] gb_gain gb gain * @param[in] b_gain b gain */ -static inline void isp_ll_lut_set_wdata_gb_b(isp_dev_t *hw, isp_lsc_gain_t gb_gain, isp_lsc_gain_t b_gain) +static inline void isp_ll_lut_lsc_set_wdata_gb_b(isp_dev_t *hw, isp_lsc_gain_t gb_gain, isp_lsc_gain_t b_gain) { hw->lut_wdata.lut_wdata = (gb_gain.val & 0x3ff) << 10 | (b_gain.val & 0x3ff); } @@ -1258,11 +1393,75 @@ static inline void isp_ll_lut_set_wdata_gb_b(isp_dev_t *hw, isp_lsc_gain_t gb_ga * @param[in] r_gain r gain * @param[in] gr_gain gr gain */ -static inline void isp_ll_lut_set_wdata_r_gr(isp_dev_t *hw, isp_lsc_gain_t r_gain, isp_lsc_gain_t gr_gain) +static inline void isp_ll_lut_lsc_set_wdata_r_gr(isp_dev_t *hw, isp_lsc_gain_t r_gain, isp_lsc_gain_t gr_gain) { hw->lut_wdata.lut_wdata = (r_gain.val & 0x3ff) << 10 | (gr_gain.val & 0x3ff); } +/** + * @brief Set AWB LUT command + * + * @param[in] hw Hardware instance address + * @param[in] type ISP LUT AWB type + * @param[in] addr AWB sub window ID + */ +static inline void isp_ll_lut_awb_set_cmd(isp_dev_t *hw, isp_ll_lut_awb_t type, uint32_t sub_window_id, isp_ll_lut_t lut) +{ + HAL_ASSERT(sub_window_id <= 25); + uint32_t val = 0; + val |= 0x2000 + 4 * sub_window_id + type; + val |= lut << 12; + hw->lut_cmd.val = val; +} + +/** + * @brief Get AWB statistics of subwindow white patch count + * + * @param[in] hw Hardware instance address + * + * @return White patch number + */ +static inline uint32_t isp_ll_lut_awb_get_subwindow_white_patch_cnt(isp_dev_t *hw) +{ + return hw->lut_rdata.lut_rdata; +} + +/** + * @brief Get AWB statistics of subwindow accumulated R + * + * @param[in] hw Hardware instance address + * + * @return Accumulated R + */ +static inline uint32_t isp_ll_lut_awb_get_subwindow_accumulated_r(isp_dev_t *hw) +{ + return hw->lut_rdata.lut_rdata; +} + +/** + * @brief Get AWB statistics of subwindow accumulated G + * + * @param[in] hw Hardware instance address + * + * @return Accumulated G + */ +static inline uint32_t isp_ll_lut_awb_get_subwindow_accumulated_g(isp_dev_t *hw) +{ + return hw->lut_rdata.lut_rdata; +} + +/** + * @brief Get AWB statistics of subwindow accumulated B + * + * @param[in] hw Hardware instance address + * + * @return Accumulated B + */ +static inline uint32_t isp_ll_lut_awb_get_subwindow_accumulated_b(isp_dev_t *hw) +{ + return hw->lut_rdata.lut_rdata; +} + /*--------------------------------------------------------------- INTR ---------------------------------------------------------------*/ @@ -1337,14 +1536,14 @@ static inline void isp_ll_clear_intr(isp_dev_t *hw, uint32_t mask) AWB ---------------------------------------------------------------*/ /** - * @brief Enable / Disable AWB clock + * @brief Set AWB clock control mode * * @param[in] hw Hardware instance address - * @param[in] enable Enable / Disable + * @param[in] mode 'isp_ll_pipeline_clk_ctrl_t` */ -static inline void isp_ll_awb_clk_enable(isp_dev_t *hw, bool enable) +static inline void isp_ll_awb_set_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode) { - hw->clk_en.clk_awb_force_on = enable; + hw->clk_en.clk_awb_force_on = mode; } /** @@ -1491,18 +1690,70 @@ static inline uint32_t isp_ll_awb_get_accumulated_b_value(isp_dev_t *hw) return hw->awb0_acc_b.awb0_acc_b; } +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +/** + * @brief Enable AWB white balance gain + * + * @param[in] hw Hardware instance address + * @param[in] enable Enable / Disable + */ +static inline void isp_ll_awb_enable_wb_gain(isp_dev_t *hw, bool enable) +{ + hw->cntl.wbg_en = enable; +} + +/** + * @brief Set AWB white balance gain clock control mode + * + * @param[in] hw Hardware instance address + * @param[in] mode 'isp_ll_pipeline_clk_ctrl_t` + */ +static inline void isp_ll_awb_set_wb_gain_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode) +{ + hw->clk_en.clk_wbg_force_on = mode; +} + +/** + * @brief Set AWB white balance gain + * + * @param[in] hw Hardware instance address + * @param[in] gain WBG white balance gain + */ +static inline void isp_ll_awb_set_wb_gain(isp_dev_t *hw, isp_wbg_gain_t gain) +{ + hw->wbg_coef_r.wbg_r = gain.gain_r; + hw->wbg_coef_g.wbg_g = gain.gain_g; + hw->wbg_coef_b.wbg_b = gain.gain_b; +} +#else +static inline void isp_ll_awb_enable_wb_gain(isp_dev_t *hw, bool enable) +{ + //for compatibility +} + +static inline void isp_ll_awb_set_wb_gain_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode) +{ + //for compatibility +} + +static inline void isp_ll_awb_set_wb_gain(isp_dev_t *hw, isp_wbg_gain_t gain) +{ + //for compatibility +} +#endif //#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + /*--------------------------------------------------------------- Demosaic ---------------------------------------------------------------*/ /** - * @brief Enable / Disable demosaic clock + * @brief Set demosaic clock control mode * * @param[in] hw Hardware instance address - * @param[in] enable Enable / Disable + * @param[in] mode 'isp_ll_pipeline_clk_ctrl_t` */ -static inline void isp_ll_demosaic_clk_enable(isp_dev_t *hw, bool enable) +static inline void isp_ll_demosaic_set_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode) { - hw->clk_en.clk_demosaic_force_on = enable; + hw->clk_en.clk_demosaic_force_on = mode; } /** @@ -1576,18 +1827,236 @@ static inline void isp_ll_demosaic_set_padding_line_tail_valid_end_pixel(isp_dev hw->demosaic_matrix_ctrl.demosaic_tail_pixen_pulse_th = end_pixel; } +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +/*--------------------------------------------------------------- + Shadow +---------------------------------------------------------------*/ +/** + * @brief Shadow mode + * + * @param[in] hw Hardware instance address + * @param[in] mode 'isp_ll_shadow_mode_t` + */ +static inline void isp_ll_shadow_set_mode(isp_dev_t *hw, isp_ll_shadow_mode_t mode) +{ + hw->shadow_reg_ctrl.shadow_update_sel = mode; +} + +/** + * @brief Update BLC shadow register + * + * @param[in] hw Hardware instance address + * @return + * - True if update is successful, False otherwise + */ +static inline bool isp_ll_shadow_update_blc(isp_dev_t *hw) +{ + //only valid when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC + HAL_ASSERT(hw->shadow_reg_ctrl.shadow_update_sel == ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC); + + if (hw->shadow_reg_ctrl.blc_update == 1) { + return false; + } + + //self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC + hw->shadow_reg_ctrl.blc_update = 1; + + return true; +} + +/** + * @brief Update DPC shadow register + * + * @param[in] hw Hardware instance address + * @return + * - True if update is successful, False otherwise + */ +static inline bool isp_ll_shadow_update_dpc(isp_dev_t *hw) +{ + //only valid when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC + HAL_ASSERT(hw->shadow_reg_ctrl.shadow_update_sel == ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC); + + if (hw->shadow_reg_ctrl.dpc_update == 1) { + return false; + } + + //self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC + hw->shadow_reg_ctrl.dpc_update = 1; + + return true; +} + +/** + * @brief Update BF shadow register + * + * @param[in] hw Hardware instance address + * @return + * - True if update is successful, False otherwise + */ +static inline bool isp_ll_shadow_update_bf(isp_dev_t *hw) +{ + //only valid when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC + HAL_ASSERT(hw->shadow_reg_ctrl.shadow_update_sel == ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC); + + if (hw->shadow_reg_ctrl.bf_update == 1) { + return false; + } + + //self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC + hw->shadow_reg_ctrl.bf_update = 1; + + return true; +} + +/** + * @brief Update WBG shadow register + * + * @param[in] hw Hardware instance address + * @return + * - True if update is successful, False otherwise + */ +static inline bool isp_ll_shadow_update_wbg(isp_dev_t *hw) +{ + //only valid when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC + HAL_ASSERT(hw->shadow_reg_ctrl.shadow_update_sel == ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC); + + if (hw->shadow_reg_ctrl.wbg_update == 1) { + return false; + } + + //self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC + hw->shadow_reg_ctrl.wbg_update = 1; + + return true; +} + +/** + * @brief Update CCM shadow register + * + * @param[in] hw Hardware instance address + * @return + * - True if update is successful, False otherwise + */ +static inline bool isp_ll_shadow_update_ccm(isp_dev_t *hw) +{ + //only valid when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC + HAL_ASSERT(hw->shadow_reg_ctrl.shadow_update_sel == ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC); + + if (hw->shadow_reg_ctrl.ccm_update == 1) { + return false; + } + + //self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC + hw->shadow_reg_ctrl.ccm_update = 1; + + return true; +} + +/** + * @brief Update Sharpen shadow register + * + * @param[in] hw Hardware instance address + * @return + * - True if update is successful, False otherwise + */ +static inline bool isp_ll_shadow_update_sharpen(isp_dev_t *hw) +{ + //only valid when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC + HAL_ASSERT(hw->shadow_reg_ctrl.shadow_update_sel == ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC); + + if (hw->shadow_reg_ctrl.sharp_update == 1) { + return false; + } + + //self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC + hw->shadow_reg_ctrl.sharp_update = 1; + + return true; +} + +/** + * @brief Update Color shadow register + * + * @param[in] hw Hardware instance address + * @return + * - True if update is successful, False otherwise + */ +static inline bool isp_ll_shadow_update_color(isp_dev_t *hw) +{ + //only valid when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC + HAL_ASSERT(hw->shadow_reg_ctrl.shadow_update_sel == ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC); + + if (hw->shadow_reg_ctrl.color_update == 1) { + return false; + } + + //self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC + hw->shadow_reg_ctrl.color_update = 1; + + return true; +} + +#else +static inline void isp_ll_shadow_set_mode(isp_dev_t *hw, isp_ll_shadow_mode_t mode) +{ + //for compatibility +} + +static inline bool isp_ll_shadow_update_blc(isp_dev_t *hw) +{ + //for compatibility + return true; +} + +static inline bool isp_ll_shadow_update_dpc(isp_dev_t *hw) +{ + //for compatibility + return true; +} + +static inline bool isp_ll_shadow_update_bf(isp_dev_t *hw) +{ + //for compatibility + return true; +} + +static inline bool isp_ll_shadow_update_wbg(isp_dev_t *hw) +{ + //for compatibility + return true; +} + +static inline bool isp_ll_shadow_update_ccm(isp_dev_t *hw) +{ + //for compatibility + return true; +} + +static inline bool isp_ll_shadow_update_sharpen(isp_dev_t *hw) +{ + //for compatibility + return true; +} + +static inline bool isp_ll_shadow_update_color(isp_dev_t *hw) +{ + //for compatibility + return true; +} +#endif + /*--------------------------------------------------------------- Sharpen ---------------------------------------------------------------*/ /** - * @brief Enable / Disable sharpen clock + * @brief Set sharpen clock control mode * * @param[in] hw Hardware instance address - * @param[in] enable Enable / Disable + * @param[in] mode 'isp_ll_pipeline_clk_ctrl_t` */ -static inline void isp_ll_sharp_clk_enable(isp_dev_t *hw, bool enable) +static inline void isp_ll_sharp_set_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode) { - hw->clk_en.clk_sharp_force_on = enable; + hw->clk_en.clk_sharp_force_on = mode; } /** @@ -1740,25 +2209,25 @@ static inline uint8_t isp_ll_sharp_get_high_freq_pixel_max(isp_dev_t *hw) RGB/YUV ---------------------------------------------------------------*/ /** - * @brief Enable / Disable rgb2yuv clock + * @brief Set rgb2yuv clock control mode * * @param[in] hw Hardware instance address - * @param[in] enable 0: hw control; 1: always on + * @param[in] mode 'isp_ll_pipeline_clk_ctrl_t` */ -static inline void isp_ll_rgb2yuv_clk_enable(isp_dev_t *hw, bool enable) +static inline void isp_ll_rgb2yuv_set_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode) { - hw->clk_en.clk_rgb2yuv_force_on = enable; + hw->clk_en.clk_rgb2yuv_force_on = mode; } /** - * @brief Enable / Disable yuv2rgb clock + * @brief Set yuv2rgb clock control mode * * @param[in] hw Hardware instance address - * @param[in] enable 0: hw control; 1: always on + * @param[in] mode 'isp_ll_pipeline_clk_ctrl_t` */ -static inline void isp_ll_yuv2rgb_clk_enable(isp_dev_t *hw, bool enable) +static inline void isp_ll_yuv2rgb_set_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode) { - hw->clk_en.clk_yuv2rgb_force_on = enable; + hw->clk_en.clk_yuv2rgb_force_on = mode; } /** @@ -1868,14 +2337,14 @@ static inline void isp_ll_gamma_set_correction_curve(isp_dev_t *hw, color_compon HIST ---------------------------------------------------------------*/ /** - * @brief enable histogram clock + * @brief Set histogram clock control mode * * @param[in] hw Hardware instance address - * @param[in] enable true: enable the clock. false: disable the clock + * @param[in] mode 'isp_ll_pipeline_clk_ctrl_t` */ -static inline void isp_ll_hist_clk_enable(isp_dev_t *hw, bool enable) +static inline void isp_ll_hist_set_clk_ctrl_mode(isp_dev_t *hw, isp_ll_pipeline_clk_ctrl_t mode) { - hw->clk_en.clk_hist_force_on = enable; + hw->clk_en.clk_hist_force_on = mode; } /** @@ -1943,7 +2412,7 @@ __attribute__((always_inline)) static inline void isp_ll_hist_get_histogram_value(isp_dev_t *hw, uint32_t *histogram_value) { for (int i = 0; i < SOC_ISP_HIST_SEGMENT_NUMS; i++) { - histogram_value[i] = hw->hist_binn[i].hist_bin_n; + histogram_value[i] = hw->hist_bin[i].hist_bin_n; } } diff --git a/components/hal/esp32p4/include/hal/ldo_ll.h b/components/hal/esp32p4/include/hal/ldo_ll.h index 2b443b49ba0e..c54d3207879f 100644 --- a/components/hal/esp32p4/include/hal/ldo_ll.h +++ b/components/hal/esp32p4/include/hal/ldo_ll.h @@ -128,7 +128,7 @@ static inline void ldo_ll_voltage_to_dref_mul(int ldo_unit, int voltage_mv, uint matched_dref = EFUSE.rd_mac_sys_2.ldo_vo1_dref; } } - if (ldo_unit == 1 && voltage_mv == 1900) { + if (ldo_unit == 1 && voltage_mv == 1800) { if (EFUSE.rd_mac_sys_2.ldo_vo2_dref && EFUSE.rd_mac_sys_3.ldo_vo2_mul) { matched_mul = EFUSE.rd_mac_sys_3.ldo_vo2_mul; matched_dref = EFUSE.rd_mac_sys_2.ldo_vo2_dref; diff --git a/components/hal/esp32p4/include/hal/ledc_ll.h b/components/hal/esp32p4/include/hal/ledc_ll.h index 1f258655724c..0876a928f046 100644 --- a/components/hal/esp32p4/include/hal/ledc_ll.h +++ b/components/hal/esp32p4/include/hal/ledc_ll.h @@ -245,7 +245,6 @@ static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_m static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src) { // The target has no timer-specific clock source option - HAL_ASSERT(hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel == 0); *clk_src = LEDC_SCLK; } @@ -365,7 +364,7 @@ static inline void ledc_ll_set_duty_int_part(ledc_dev_t *hw, ledc_mode_t speed_m */ static inline void ledc_ll_get_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *duty_val) { - *duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_r.duty >> 4); + *duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_r.duty_r >> 4); } /** @@ -406,7 +405,7 @@ static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t spee */ static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t range_num) { - hw->chn_gamma_conf[channel_num].ch0_gamma_entry_num = range_num; + hw->chn_gamma_conf[channel_num].gamma_entry_num = range_num; } /** @@ -421,7 +420,7 @@ static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mo */ static inline void ledc_ll_get_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *range_num) { - *range_num = hw->chn_gamma_conf[channel_num].ch0_gamma_entry_num; + *range_num = hw->chn_gamma_conf[channel_num].gamma_entry_num; } /** diff --git a/components/hal/esp32p4/include/hal/ppa_ll.h b/components/hal/esp32p4/include/hal/ppa_ll.h index 1d82fdce92ab..a0e7323397fc 100644 --- a/components/hal/esp32p4/include/hal/ppa_ll.h +++ b/components/hal/esp32p4/include/hal/ppa_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,6 +14,7 @@ #include "soc/hp_sys_clkrst_struct.h" #include "hal/assert.h" #include "hal/misc.h" +#include "hal/config.h" #ifdef __cplusplus extern "C" { @@ -27,9 +28,15 @@ extern "C" { #define PPA_LL_SRM_SCALING_INT_MAX (PPA_SR_SCAL_X_INT_V + 1) #define PPA_LL_SRM_SCALING_FRAG_MAX (PPA_SR_SCAL_X_FRAG_V + 1) -// TODO: On P4 ECO2, SRM block size needs update -#define PPA_LL_SRM_DEFAULT_BLOCK_SIZE 18 // 18 x 18 block size -#define PPA_LL_SRM_YUV420_BLOCK_SIZE 20 // 20 x 20 block size +/** + * @brief Enumeration of PPA SRM macro block size options + */ +typedef enum { + PPA_LL_SRM_MB_SIZE_16_16, /*!< SRM engine processes with a macro block size of 16 x 16 */ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + PPA_LL_SRM_MB_SIZE_32_32, /*!< SRM engine processes with a macro block size of 32 x 32 */ +#endif +} ppa_ll_srm_mb_size_t; /** * @brief Enumeration of PPA blending mode @@ -68,6 +75,29 @@ static inline void ppa_ll_reset_register(void) /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance #define ppa_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; ppa_ll_reset_register(__VA_ARGS__) +/** + * @brief Configure the RGB888 to GRAY8 color conversion coefficients for SRM and Blending (excluding Fill) + * + * The gray value is calculated as: gray = (r_coeff * R + g_coeff * G + b_coeff * B) >> 8 + * + * @param dev Peripheral instance address + * @param r_coeff Coefficient for Red channel, range 0-255 + * @param g_coeff Coefficient for Green channel, range 0-255 + * @param b_coeff Coefficient for Blue channel, range 0-255 + */ +static inline void ppa_ll_set_rgb2gray_coeff(ppa_dev_t *dev, uint8_t r_coeff, uint8_t g_coeff, uint8_t b_coeff) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + HAL_ASSERT((r_coeff + g_coeff + b_coeff == 256) && "Sum of RGB to GRAY coefficients must be 256"); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rgb2gray, rgb2gray_r, r_coeff); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rgb2gray, rgb2gray_g, g_coeff); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rgb2gray, rgb2gray_b, b_coeff); +#else + // GRAY8 color mode is not supported by PPA hardware before P4 ECO5 + abort(); +#endif +} + ///////////////////////// Scaling, Rotating, Mirroring (SRM) ////////////////////////////// /** * @brief Reset PPA scaling-rotating-mirroring engine @@ -169,6 +199,65 @@ static inline void ppa_ll_srm_start(ppa_dev_t *dev) dev->sr_scal_rotate.scal_rotate_start = 1; } +/** + * @brief Set PPA SRM input side YUV422 data format packing order + * + * @param dev Peripheral instance address + * @param color_mode One of the values in ppa_srm_color_mode_t + */ +static inline void ppa_ll_srm_set_rx_yuv422_pack_order(ppa_dev_t *dev, ppa_srm_color_mode_t color_mode) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (color_mode) { + case PPA_SRM_COLOR_MODE_YUV422_YVYU: + dev->sr_color_mode.yuv422_rx_byte_order = 3; + break; + case PPA_SRM_COLOR_MODE_YUV422_YUYV: + dev->sr_color_mode.yuv422_rx_byte_order = 2; + break; + case PPA_SRM_COLOR_MODE_YUV422_VYUY: + dev->sr_color_mode.yuv422_rx_byte_order = 1; + break; + case PPA_SRM_COLOR_MODE_YUV422_UYVY: + dev->sr_color_mode.yuv422_rx_byte_order = 0; + break; + default: + // Unsupported YUV422 pack order + abort(); + } +#else + // YUV422 not supported by PPA SRM hardware before P4 ECO5 + abort(); +#endif +} + +/** + * @brief Check if the given color mode is supported by PPA SRM engine + * + * @param color_mode One of the values in ppa_srm_color_mode_t + * @return true if supported; false if not supported + */ +static inline bool ppa_ll_srm_is_color_mode_supported(ppa_srm_color_mode_t color_mode) +{ + switch (color_mode) { + case PPA_SRM_COLOR_MODE_ARGB8888: + case PPA_SRM_COLOR_MODE_RGB888: + case PPA_SRM_COLOR_MODE_RGB565: + case PPA_SRM_COLOR_MODE_YUV420: + case PPA_SRM_COLOR_MODE_YUV444: // YUV444 not supported by PPA hardware, but can be converted by 2D-DMA before/after PPA +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_SRM_COLOR_MODE_YUV422_UYVY: + case PPA_SRM_COLOR_MODE_YUV422_VYUY: + case PPA_SRM_COLOR_MODE_YUV422_YUYV: + case PPA_SRM_COLOR_MODE_YUV422_YVYU: + case PPA_SRM_COLOR_MODE_GRAY8: +#endif + return true; + default: + return false; + } +} + /** * @brief Set the source image color mode for PPA Scaling-Rotating-Mirroring engine RX * @@ -178,6 +267,7 @@ static inline void ppa_ll_srm_start(ppa_dev_t *dev) static inline void ppa_ll_srm_set_rx_color_mode(ppa_dev_t *dev, ppa_srm_color_mode_t color_mode) { uint32_t val = 0; + bool is_yuv422 __attribute__ ((unused)) = false; switch (color_mode) { case PPA_SRM_COLOR_MODE_ARGB8888: val = 0; @@ -191,11 +281,30 @@ static inline void ppa_ll_srm_set_rx_color_mode(ppa_dev_t *dev, ppa_srm_color_mo case PPA_SRM_COLOR_MODE_YUV420: val = 8; break; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_SRM_COLOR_MODE_YUV422_UYVY: + case PPA_SRM_COLOR_MODE_YUV422_VYUY: + case PPA_SRM_COLOR_MODE_YUV422_YUYV: + case PPA_SRM_COLOR_MODE_YUV422_YVYU: + val = 9; + is_yuv422 = true; + break; + case PPA_SRM_COLOR_MODE_GRAY8: + val = 12; + break; +#endif default: // Unsupported SRM rx color mode abort(); } dev->sr_color_mode.sr_rx_cm = val; + +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + // set YUV422 packing order + if (is_yuv422) { + ppa_ll_srm_set_rx_yuv422_pack_order(dev, color_mode); + } +#endif } /** @@ -220,6 +329,14 @@ static inline void ppa_ll_srm_set_tx_color_mode(ppa_dev_t *dev, ppa_srm_color_mo case PPA_SRM_COLOR_MODE_YUV420: val = 8; break; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_SRM_COLOR_MODE_YUV422_UYVY: + val = 9; + break; + case PPA_SRM_COLOR_MODE_GRAY8: + val = 12; + break; +#endif default: // Unsupported SRM tx color mode abort(); @@ -371,6 +488,118 @@ static inline void ppa_ll_srm_configure_rx_alpha(ppa_dev_t *dev, ppa_alpha_updat } } +/** + * @brief Get the current configured PPA SRM macro block size + * + * @param dev Peripheral instance address + * @return The current configured macro block size, one of the values in ppa_ll_srm_mb_size_t + */ +static inline ppa_ll_srm_mb_size_t ppa_ll_srm_get_mb_size(ppa_dev_t *dev) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + return (dev->sr_byte_order.sr_bk_size_sel == 0) ? PPA_LL_SRM_MB_SIZE_32_32 : PPA_LL_SRM_MB_SIZE_16_16; +#else + return PPA_LL_SRM_MB_SIZE_16_16; +#endif +} + +/** + * @brief Set PPA SRM macro block size + * + * @param dev Peripheral instance address + * @param mb_size Macro block size to be set, one of the values in ppa_ll_srm_mb_size_t + */ +static inline void ppa_ll_srm_set_mb_size(ppa_dev_t *dev, ppa_ll_srm_mb_size_t mb_size) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (mb_size) { + case PPA_LL_SRM_MB_SIZE_16_16: + dev->sr_byte_order.sr_bk_size_sel = 1; + break; + case PPA_LL_SRM_MB_SIZE_32_32: + dev->sr_byte_order.sr_bk_size_sel = 0; + break; + default: + // Unsupported SRM macro block size + abort(); + } +#else + HAL_ASSERT(mb_size == PPA_LL_SRM_MB_SIZE_16_16); +#endif +} + +/** + * @brief Retrieve the 2D-DMA descriptor port mode block size (in pixel) according to the PPA SRM input color mode and configured macro block size + * + * @param dev Peripheral instance address + * @param in_color_mode Input color mode, one of the values in ppa_srm_color_mode_t + * @param mb_size SRM macro block size, one of the values in ppa_ll_srm_mb_size_t + * @param[out] block_h Returned block horizontal width + * @param[out] block_v Returned block wvertical height + */ +static inline void ppa_ll_srm_get_dma_dscr_port_mode_block_size(ppa_dev_t *dev, ppa_srm_color_mode_t in_color_mode, ppa_ll_srm_mb_size_t mb_size, uint32_t *block_h, uint32_t *block_v) +{ + if (mb_size == PPA_LL_SRM_MB_SIZE_16_16) { + switch (in_color_mode) { + case PPA_SRM_COLOR_MODE_ARGB8888: + case PPA_SRM_COLOR_MODE_RGB888: + case PPA_SRM_COLOR_MODE_RGB565: + case PPA_SRM_COLOR_MODE_GRAY8: + *block_h = 18; + *block_v = 18; + break; + case PPA_SRM_COLOR_MODE_YUV420: + *block_h = 20; + *block_v = 18; + break; + case PPA_SRM_COLOR_MODE_YUV422_UYVY: + case PPA_SRM_COLOR_MODE_YUV422_VYUY: + case PPA_SRM_COLOR_MODE_YUV422_YUYV: + case PPA_SRM_COLOR_MODE_YUV422_YVYU: + *block_h = 20; + *block_v = 20; + break; + default: + // Unsupported SRM input color mode + *block_h = 0; + *block_v = 0; + } + } +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + else if (mb_size == PPA_LL_SRM_MB_SIZE_32_32) { + switch (in_color_mode) { + case PPA_SRM_COLOR_MODE_ARGB8888: + case PPA_SRM_COLOR_MODE_RGB888: + case PPA_SRM_COLOR_MODE_RGB565: + case PPA_SRM_COLOR_MODE_GRAY8: + *block_h = 34; + *block_v = 34; + break; + case PPA_SRM_COLOR_MODE_YUV420: + *block_h = 36; + *block_v = 34; + break; + case PPA_SRM_COLOR_MODE_YUV422_UYVY: + case PPA_SRM_COLOR_MODE_YUV422_VYUY: + case PPA_SRM_COLOR_MODE_YUV422_YUYV: + case PPA_SRM_COLOR_MODE_YUV422_YVYU: + *block_h = 36; + *block_v = 36; + break; + default: + // Unsupported SRM input color mode + *block_h = 0; + *block_v = 0; + } + } +#endif + else { + // Unsupported SRM macro block size + *block_h = 0; + *block_v = 0; + } +} + //////////////////////////////////// Blending //////////////////////////////////////// /* * Alpha Blending Calculation: @@ -420,6 +649,68 @@ static inline void ppa_ll_blend_start(ppa_dev_t *dev, ppa_ll_blend_trans_mode_t dev->blend_trans_mode.blend_trans_mode_update = 1; } +/** + * @brief Set PPA blending source image background YUV422 data format packing order + * + * @param dev Peripheral instance address + * @param color_mode One of the values in ppa_blend_color_mode_t + */ +static inline void ppa_ll_blend_set_rx_bg_yuv422_pack_order(ppa_dev_t *dev, ppa_blend_color_mode_t color_mode) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (color_mode) { + case PPA_BLEND_COLOR_MODE_YUV422_YVYU: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 3; + break; + case PPA_BLEND_COLOR_MODE_YUV422_YUYV: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 2; + break; + case PPA_BLEND_COLOR_MODE_YUV422_VYUY: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 1; + break; + case PPA_BLEND_COLOR_MODE_YUV422_UYVY: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 0; + break; + default: + // Unsupported YUV422 pack order + abort(); + } +#else + // YUV422 not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + +/** + * @brief Check if the given color mode is supported by PPA blending engine + * + * @param color_mode One of the values in ppa_blend_color_mode_t + * @return true if supported (by any of rx_bg, rx_fg, tx); false if not supported + */ +static inline bool ppa_ll_blend_is_color_mode_supported(ppa_blend_color_mode_t color_mode) +{ + switch (color_mode) { + case PPA_BLEND_COLOR_MODE_ARGB8888: + case PPA_BLEND_COLOR_MODE_RGB888: + case PPA_BLEND_COLOR_MODE_RGB565: + case PPA_BLEND_COLOR_MODE_A8: + case PPA_BLEND_COLOR_MODE_A4: + // case PPA_BLEND_COLOR_MODE_L8: + // case PPA_BLEND_COLOR_MODE_L4: +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_BLEND_COLOR_MODE_YUV420: + case PPA_BLEND_COLOR_MODE_YUV422_UYVY: + case PPA_BLEND_COLOR_MODE_YUV422_VYUY: + case PPA_BLEND_COLOR_MODE_YUV422_YUYV: + case PPA_BLEND_COLOR_MODE_YUV422_YVYU: + case PPA_BLEND_COLOR_MODE_GRAY8: +#endif + return true; + default: + return false; + } +} + /** * @brief Set the source image color mode for background for PPA blending engine RX * @@ -429,6 +720,7 @@ static inline void ppa_ll_blend_start(ppa_dev_t *dev, ppa_ll_blend_trans_mode_t static inline void ppa_ll_blend_set_rx_bg_color_mode(ppa_dev_t *dev, ppa_blend_color_mode_t color_mode) { uint32_t val = 0; + bool is_yuv422 __attribute__ ((unused)) = false; switch (color_mode) { case PPA_BLEND_COLOR_MODE_ARGB8888: val = 0; @@ -445,11 +737,33 @@ static inline void ppa_ll_blend_set_rx_bg_color_mode(ppa_dev_t *dev, ppa_blend_c // case PPA_BLEND_COLOR_MODE_L4: // val = 5; // break; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_BLEND_COLOR_MODE_YUV420: + val = 8; + break; + case PPA_BLEND_COLOR_MODE_YUV422_UYVY: + case PPA_BLEND_COLOR_MODE_YUV422_VYUY: + case PPA_BLEND_COLOR_MODE_YUV422_YUYV: + case PPA_BLEND_COLOR_MODE_YUV422_YVYU: + val = 9; + is_yuv422 = true; + break; + case PPA_BLEND_COLOR_MODE_GRAY8: + val = 12; + break; +#endif default: // Unsupported blending rx background color mode abort(); } dev->blend_color_mode.blend0_rx_cm = val; + +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + // set YUV422 packing order + if (is_yuv422) { + ppa_ll_blend_set_rx_bg_yuv422_pack_order(dev, color_mode); + } +#endif } /** @@ -509,6 +823,17 @@ static inline void ppa_ll_blend_set_tx_color_mode(ppa_dev_t *dev, ppa_blend_colo case PPA_BLEND_COLOR_MODE_RGB565: val = 2; break; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_BLEND_COLOR_MODE_YUV420: + val = 8; + break; + case PPA_BLEND_COLOR_MODE_YUV422_UYVY: + val = 9; + break; + case PPA_BLEND_COLOR_MODE_GRAY8: + val = 12; + break; +#endif default: // Unsupported blending tx color mode abort(); @@ -516,6 +841,110 @@ static inline void ppa_ll_blend_set_tx_color_mode(ppa_dev_t *dev, ppa_blend_colo dev->blend_color_mode.blend_tx_cm = val; } +/** + * @brief Set YUV to RGB protocol when PPA blending source image background pixel color space is YUV + * + * @param dev Peripheral instance address + * @param std One of the RGB-YUV conversion standards in ppa_color_conv_std_rgb_yuv_t + */ +static inline void ppa_ll_blend_set_rx_bg_yuv2rgb_std(ppa_dev_t *dev, ppa_color_conv_std_rgb_yuv_t std) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (std) { + case PPA_COLOR_CONV_STD_RGB_YUV_BT601: + dev->blend_color_mode.blend0_rx_yuv2rgb_protocol = 0; + break; + case PPA_COLOR_CONV_STD_RGB_YUV_BT709: + dev->blend_color_mode.blend0_rx_yuv2rgb_protocol = 1; + break; + default: + // Unsupported RGB-YUV conversion standard + abort(); + } +#else + // YUV not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + +/** + * @brief Set RGB to YUV protocol when PPA blending destination image pixel color space is YUV + * + * @param dev Peripheral instance address + * @param std One of the RGB-YUV conversion standards in ppa_color_conv_std_rgb_yuv_t + */ +static inline void ppa_ll_blend_set_tx_rgb2yuv_std(ppa_dev_t *dev, ppa_color_conv_std_rgb_yuv_t std) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (std) { + case PPA_COLOR_CONV_STD_RGB_YUV_BT601: + dev->blend_color_mode.blend_tx_rgb2yuv_protocol = 0; + break; + case PPA_COLOR_CONV_STD_RGB_YUV_BT709: + dev->blend_color_mode.blend_tx_rgb2yuv_protocol = 1; + break; + default: + // Unsupported RGB-YUV conversion standard + abort(); + } +#else + // YUV not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + +/** + * @brief Set PPA blending source image background YUV input range + * + * @param dev Peripheral instance address + * @param range One of color range options in ppa_color_range_t + */ +static inline void ppa_ll_blend_set_rx_bg_yuv_range(ppa_dev_t *dev, ppa_color_range_t range) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (range) { + case PPA_COLOR_RANGE_LIMIT: + dev->blend_color_mode.blend0_rx_yuv_range = 0; + break; + case PPA_COLOR_RANGE_FULL: + dev->blend_color_mode.blend0_rx_yuv_range = 1; + break; + default: + // Unsupported color range + abort(); + } +#else + // YUV not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + +/** + * @brief Set PPA blending destination image YUV output range + * + * @param dev Peripheral instance address + * @param range One of color range options in ppa_color_range_t + */ +static inline void ppa_ll_blend_set_tx_yuv_range(ppa_dev_t *dev, ppa_color_range_t range) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (range) { + case PPA_COLOR_RANGE_LIMIT: + dev->blend_color_mode.blend_tx_yuv_range = 0; + break; + case PPA_COLOR_RANGE_FULL: + dev->blend_color_mode.blend_tx_yuv_range = 1; + break; + default: + // Unsupported color range + abort(); + } +#else + // YUV not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + /** * @brief Enable PPA blending input background data wrap in RGB (e.g. ARGB becomes BGRA, RGB becomes BGR) * @@ -639,15 +1068,44 @@ static inline void ppa_ll_blend_configure_rx_fg_alpha(ppa_dev_t *dev, ppa_alpha_ /** * @brief Configure PPA blending pixel filling image block * + * The color to be filled is directly relying on the blend_tx_fix_pixel register field value. + * For fill operation, the data does not go through any color space conversion in the blending engine. + * * @param dev Peripheral instance address - * @param data The fix data to be filled to the image block pixels in ARGB8888 format + * @param color_mode One of the values in ppa_fill_color_mode_t + * @param data The point of the fix data to be filled to the image block pixels * @param hb The horizontal width of image block that would be filled in fix pixel filling mode. The unit is pixel. * @param vb The vertical height of image block that would be filled in fix pixel filling mode. The unit is pixel. */ -static inline void ppa_ll_blend_configure_filling_block(ppa_dev_t *dev, color_pixel_argb8888_data_t *data, uint32_t hb, uint32_t vb) +static inline void ppa_ll_blend_configure_filling_block(ppa_dev_t *dev, ppa_fill_color_mode_t color_mode, void *data, uint32_t hb, uint32_t vb) { HAL_ASSERT(hb <= PPA_BLEND_HB_V && vb <= PPA_BLEND_VB_V); - dev->blend_fix_pixel.blend_tx_fix_pixel = data->val; + uint32_t fill_color_data = 0; + switch (color_mode) { + case PPA_FILL_COLOR_MODE_ARGB8888: + case PPA_FILL_COLOR_MODE_RGB888: + case PPA_FILL_COLOR_MODE_RGB565: + case PPA_FILL_COLOR_MODE_GRAY8: + fill_color_data = *(uint32_t *)data; + break; + case PPA_FILL_COLOR_MODE_YUV422_UYVY: { + color_macroblock_yuv_data_t *yuv_data = (color_macroblock_yuv_data_t *)data; + fill_color_data = ((yuv_data->y) << 24) | ((yuv_data->v) << 16) | ((yuv_data->y) << 8) | (yuv_data->u); + break; + } + // case PPA_FILL_COLOR_MODE_YUV420: { + // color_macroblock_yuv_data_t *yuv_data = (color_macroblock_yuv_data_t *)data; + // if (yuv_data->u != yuv_data->v) { + // abort(); + // } + // fill_color_data = ((yuv_data->y) << 16) | ((yuv_data->y) << 8) | (yuv_data->v); + // break; + // } + default: + // Unsupported filling color mode + abort(); + } + dev->blend_fix_pixel.blend_tx_fix_pixel = fill_color_data; dev->blend_tx_size.blend_hb = hb; dev->blend_tx_size.blend_vb = vb; } diff --git a/components/hal/esp32p4/include/hal/rtc_io_ll.h b/components/hal/esp32p4/include/hal/rtc_io_ll.h index 976564330eff..3c53f8ca6ea3 100644 --- a/components/hal/esp32p4/include/hal/rtc_io_ll.h +++ b/components/hal/esp32p4/include/hal/rtc_io_ll.h @@ -18,9 +18,11 @@ #include "soc/lp_gpio_struct.h" #include "soc/lp_iomux_struct.h" #include "soc/lp_gpio_sig_map.h" +#include "soc/lp_system_struct.h" #include "soc/pmu_struct.h" #include "hal/misc.h" #include "hal/assert.h" +#include "hal/config.h" #ifdef __cplusplus extern "C" { @@ -323,9 +325,13 @@ static inline bool rtcio_ll_is_pulldown_enabled(int rtcio_num) */ static inline void rtcio_ll_force_hold_enable(int rtcio_num) { +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 |= BIT(rtcio_num); +#else uint32_t hold_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold); hold_mask |= BIT(rtcio_num); HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold, hold_mask); +#endif } /** @@ -336,9 +342,13 @@ static inline void rtcio_ll_force_hold_enable(int rtcio_num) */ static inline void rtcio_ll_force_hold_disable(int rtcio_num) { +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 &= ~BIT(rtcio_num); +#else uint32_t hold_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold); hold_mask &= ~BIT(rtcio_num); HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold, hold_mask); +#endif } /** diff --git a/components/hal/esp32p4/include/hal/touch_sensor_hal.h b/components/hal/esp32p4/include/hal/touch_sensor_hal.h index bc6d03f503bb..43f5a15e4c29 100644 --- a/components/hal/esp32p4/include/hal/touch_sensor_hal.h +++ b/components/hal/esp32p4/include/hal/touch_sensor_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -49,6 +49,11 @@ typedef struct { */ touch_out_mode_t output_mode; /*!< Touch channel counting mode of the binarized touch output */ uint32_t sample_cfg_num; /*!< The sample configuration number that used for sampling */ + uint32_t trigger_rise_cnt; /*!< The counter of triggered frequency points to judge whether a channel active. + * For example, there are 3 sample configurations activated, and the trigger_rise_cnt is 2, + * then the channel will only be active when at least 2 of 3 sample configurations triggered. + * Range: [0 ~ sample_cfg_num], '0' means select the recommended value automatically. + */ touch_hal_sample_config_t *sample_cfg; /*!< The array of the sample configuration configurations, the length should be specified in `touch_hal_sample_config_t::sample_cfg_num` */ } touch_hal_config_t; diff --git a/components/hal/esp32p4/include/hal/touch_sensor_ll.h b/components/hal/esp32p4/include/hal/touch_sensor_ll.h index cc0339d5c8d2..3f66027ac324 100644 --- a/components/hal/esp32p4/include/hal/touch_sensor_ll.h +++ b/components/hal/esp32p4/include/hal/touch_sensor_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -25,6 +25,7 @@ #include "soc/pmu_struct.h" #include "soc/soc_caps.h" #include "hal/touch_sensor_types.h" +#include "hal/config.h" #ifdef __cplusplus extern "C" { @@ -570,6 +571,30 @@ static inline void touch_ll_sample_cfg_set_engaged_num(uint8_t sample_cfg_num) LP_ANA_PERI.touch_scan_ctrl2.freq_scan_cnt_limit = sample_cfg_num ? sample_cfg_num : 1; } +/** + * Get the engaged sample configuration number + * + * @return The engaged sample configuration number, range 0~3. + */ +static inline uint32_t touch_ll_sample_cfg_get_engaged_num(void) +{ + uint32_t sample_cfg_num = LP_ANA_PERI.touch_scan_ctrl2.freq_scan_cnt_limit; + return sample_cfg_num ? sample_cfg_num : 1; +} + +/** + * Set the number of trigger rise count (only available since P4 ver3) + * + * @param rise_cnt Configure the number of hit frequency points that need to be determined for touch + * in frequency hopping mode. + */ +static inline void touch_ll_sample_cfg_set_trigger_rise_cnt(uint8_t rise_cnt) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + LP_ANA_PERI.touch_ctrl.freq_scan_cnt_rise = rise_cnt; +#endif +} + /** * Set capacitance and resistance of the RC filter of the sampling frequency. * @@ -598,18 +623,6 @@ static inline void touch_ll_sample_cfg_set_driver(uint8_t sample_cfg_id, uint32_ LP_ANA_PERI.touch_freq_scan_para[sample_cfg_id].touch_freq_drv_hs = hs_drv; } -/** - * Bypass the shield channel output for the specify sample configuration - * - * @param sample_cfg_id The sample configuration index - * @param enable Set true to bypass the shield channel output for the current channel - */ -static inline void touch_ll_sample_cfg_bypass_shield_output(uint8_t sample_cfg_id, bool enable) -{ - HAL_ASSERT(sample_cfg_id < SOC_TOUCH_SAMPLE_CFG_NUM); - LP_ANA_PERI.touch_freq_scan_para[sample_cfg_id].touch_bypass_shield = enable; -} - /** * Set the touch internal LDO bias voltage of the sampling frequency * @@ -736,13 +749,19 @@ static inline void touch_ll_filter_enable(bool enable) } /** - * Force the update the benchmark by software + * Force the update the benchmark by software (only available since P4 ver3) * @note This benchmark will be applied to all enabled channel and all sampling frequency * + * @param pad_num The pad number, range [1-14] + * @param sample_cfg_id The sample configuration index, range [0-2] * @param benchmark The benchmark specified by software */ -static inline void touch_ll_force_update_benchmark(uint32_t benchmark) +static inline void touch_ll_force_update_benchmark(uint32_t pad_num, uint8_t sample_cfg_id, uint32_t benchmark) { +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + LP_ANA_PERI.touch_ctrl.touch_update_benchmark_pad_sel = pad_num; + LP_ANA_PERI.touch_ctrl.touch_update_benchmark_freq_sel = sample_cfg_id; +#endif HAL_FORCE_MODIFY_U32_REG_FIELD(LP_ANA_PERI.touch_filter3, touch_benchmark_sw, benchmark); LP_ANA_PERI.touch_filter3.touch_update_benchmark_sw = 1; // waiting for update diff --git a/components/hal/esp32p4/include/hal/uart_ll.h b/components/hal/esp32p4/include/hal/uart_ll.h index 2cb6cdd1368a..a0904fce9031 100644 --- a/components/hal/esp32p4/include/hal/uart_ll.h +++ b/components/hal/esp32p4/include/hal/uart_ll.h @@ -660,7 +660,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) { for (int i = 0; i < (int)rd_len; i++) { - buf[i] = hw->fifo.rxfifo_rd_byte; + buf[i] = hw->fifo.val; } } diff --git a/components/hal/esp32p4/include/hal/usb_dwc_ll.h b/components/hal/esp32p4/include/hal/usb_dwc_ll.h index 1ee7334a749a..c1b1a44e080a 100644 --- a/components/hal/esp32p4/include/hal/usb_dwc_ll.h +++ b/components/hal/esp32p4/include/hal/usb_dwc_ll.h @@ -1061,6 +1061,21 @@ FORCE_INLINE_ATTR bool usb_dwc_ll_get_stoppclk_st(usb_dwc_dev_t *hw) return hw->pcgcctl_reg.stoppclk; } +FORCE_INLINE_ATTR void usb_dwc_ll_set_gatehclk(usb_dwc_dev_t *hw, bool gate) +{ + hw->pcgcctl_reg.gatehclk = gate; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_gatehclk_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.gatehclk; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_physleep_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.physleep; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32p4/touch_sensor_hal.c b/components/hal/esp32p4/touch_sensor_hal.c index 450e3ab89ba2..19119af0909b 100644 --- a/components/hal/esp32p4/touch_sensor_hal.c +++ b/components/hal/esp32p4/touch_sensor_hal.c @@ -36,12 +36,12 @@ void touch_hal_config_controller(const touch_hal_config_t *cfg) } touch_ll_sample_cfg_set_engaged_num(cfg->sample_cfg_num); + touch_ll_sample_cfg_set_trigger_rise_cnt(cfg->trigger_rise_cnt); for (int i = 0; i < cfg->sample_cfg_num; i++) { touch_ll_set_clock_div(i, cfg->sample_cfg[i].div_num); touch_ll_set_charge_times(i, cfg->sample_cfg[i].charge_times); touch_ll_sample_cfg_set_rc_filter(i, cfg->sample_cfg[i].rc_filter_cap, cfg->sample_cfg[i].rc_filter_res); touch_ll_sample_cfg_set_driver(i, cfg->sample_cfg[i].low_drv, cfg->sample_cfg[i].high_drv); - touch_ll_sample_cfg_bypass_shield_output(i, cfg->sample_cfg[i].bypass_shield_output); touch_ll_sample_cfg_set_bias_voltage(i, cfg->sample_cfg[i].bias_volt); } } diff --git a/components/hal/esp32s2/include/hal/gpio_ll.h b/components/hal/esp32s2/include/hal/gpio_ll.h index e2251f9c4812..f6b46bf1bd88 100644 --- a/components/hal/esp32s2/include/hal/gpio_ll.h +++ b/components/hal/esp32s2/include/hal/gpio_ll.h @@ -525,7 +525,7 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32s2/include/hal/usb_dwc_ll.h b/components/hal/esp32s2/include/hal/usb_dwc_ll.h index d3eef71367be..90ad414aeb2a 100644 --- a/components/hal/esp32s2/include/hal/usb_dwc_ll.h +++ b/components/hal/esp32s2/include/hal/usb_dwc_ll.h @@ -8,6 +8,7 @@ #include #include +#include "esp_attr.h" #include "soc/usb_dwc_struct.h" #include "soc/usb_dwc_cfg.h" #include "hal/usb_dwc_types.h" @@ -976,6 +977,32 @@ static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem qtd->buffer_status_val = 0; } +// ---------------------------- Power and Clock Gating Register -------------------------------- +FORCE_INLINE_ATTR void usb_dwc_ll_set_stoppclk(usb_dwc_dev_t *hw, bool stop) +{ + hw->pcgcctl_reg.stoppclk = stop; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_stoppclk_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.stoppclk; +} + +FORCE_INLINE_ATTR void usb_dwc_ll_set_gatehclk(usb_dwc_dev_t *hw, bool gate) +{ + hw->pcgcctl_reg.gatehclk = gate; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_gatehclk_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.gatehclk; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_physleep_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.physleep; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/gpio_ll.h b/components/hal/esp32s3/include/hal/gpio_ll.h index e53df0e3f825..eda75b807411 100644 --- a/components/hal/esp32s3/include/hal/gpio_ll.h +++ b/components/hal/esp32s3/include/hal/gpio_ll.h @@ -517,7 +517,7 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) } /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number of the pad. diff --git a/components/hal/esp32s3/include/hal/usb_dwc_ll.h b/components/hal/esp32s3/include/hal/usb_dwc_ll.h index 32f7469a3e35..aaab0c9417ee 100644 --- a/components/hal/esp32s3/include/hal/usb_dwc_ll.h +++ b/components/hal/esp32s3/include/hal/usb_dwc_ll.h @@ -8,6 +8,7 @@ #include #include +#include "esp_attr.h" #include "soc/usb_dwc_struct.h" #include "soc/usb_dwc_cfg.h" #include "hal/usb_dwc_types.h" @@ -976,6 +977,32 @@ static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem qtd->buffer_status_val = 0; } +// ---------------------------- Power and Clock Gating Register -------------------------------- +FORCE_INLINE_ATTR void usb_dwc_ll_set_stoppclk(usb_dwc_dev_t *hw, bool stop) +{ + hw->pcgcctl_reg.stoppclk = stop; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_stoppclk_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.stoppclk; +} + +FORCE_INLINE_ATTR void usb_dwc_ll_set_gatehclk(usb_dwc_dev_t *hw, bool gate) +{ + hw->pcgcctl_reg.gatehclk = gate; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_gatehclk_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.gatehclk; +} + +FORCE_INLINE_ATTR bool usb_dwc_ll_get_physleep_st(usb_dwc_dev_t *hw) +{ + return hw->pcgcctl_reg.physleep; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/color_types.h b/components/hal/include/hal/color_types.h index 93c69b323d73..cb8cef6786b5 100644 --- a/components/hal/include/hal/color_types.h +++ b/components/hal/include/hal/color_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -59,6 +59,11 @@ typedef enum { COLOR_PIXEL_YUV422, ///< 16 bits, 8-bit Y per pixel, 8-bit U and V per two pixels COLOR_PIXEL_YUV420, ///< 12 bits, 8-bit Y per pixel, 8-bit U and V per four pixels COLOR_PIXEL_YUV411, ///< 12 bits, 8-bit Y per pixel, 8-bit U and V per four pixels + + COLOR_PIXEL_UYVY422, ///< 16 bits, 8-bit Y per pixel, 8-bit U and V per two pixels w/ (lowest byte) U0-Y0-V0-Y1 (highest byte) pack order + COLOR_PIXEL_VYUY422, ///< 16 bits, 8-bit Y per pixel, 8-bit U and V per two pixels w/ (lowest byte) V0-Y0-U0-Y1 (highest byte) pack order + COLOR_PIXEL_YUYV422, ///< 16 bits, 8-bit Y per pixel, 8-bit U and V per two pixels w/ (lowest byte) Y0-U0-Y1-V0 (highest byte) pack order + COLOR_PIXEL_YVYU422, ///< 16 bits, 8-bit Y per pixel, 8-bit U and V per two pixels w/ (lowest byte) Y0-V0-Y1-U0 (highest byte) pack order } color_pixel_yuv_format_t; /** @@ -179,10 +184,13 @@ typedef union { /** * @brief Data structure for RGB888 pixel unit */ -typedef struct { - uint8_t b; /*!< B component [0, 255] */ - uint8_t g; /*!< G component [0, 255] */ - uint8_t r; /*!< R component [0, 255] */ +typedef union { + struct { + uint8_t b; /*!< B component [0, 255] */ + uint8_t g; /*!< G component [0, 255] */ + uint8_t r; /*!< R component [0, 255] */ + }; + uint32_t val; /*!< 32-bit RGB888 value */ } color_pixel_rgb888_data_t; /** @@ -197,6 +205,29 @@ typedef union { uint16_t val; /*!< 16-bit RGB565 value */ } color_pixel_rgb565_data_t; +/** + * @brief Data structure for GRAY8 pixel unit + */ +typedef union { + struct { + uint8_t gray; /*!< Gray component [0, 255] */ + }; + uint8_t val; /*!< 8-bit GRAY8 value */ +} color_pixel_gray8_data_t; + +/** + * @brief Data structure for YUV macroblock unit + * + * For YUV420, a macroblock is 2x2 pixels + * For YUV422, a macroblock is 2x1 pixels + * For YUV444, a macro block is a 1x1 pixel + */ +typedef struct { + uint8_t y; /*!< Y component [0, 255] */ + uint8_t u; /*!< U component [0, 255] */ + uint8_t v; /*!< V component [0, 255] */ +} color_macroblock_yuv_data_t; + /*--------------------------------------------------------------- Color Components ---------------------------------------------------------------*/ diff --git a/components/hal/include/hal/dma2d_types.h b/components/hal/include/hal/dma2d_types.h index b66c791deb4a..3e9142f2e2ea 100644 --- a/components/hal/include/hal/dma2d_types.h +++ b/components/hal/include/hal/dma2d_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -236,20 +236,23 @@ typedef enum { typedef enum { DMA2D_CSC_RX_NONE, /*!< 2D-DMA RX perform no CSC */ DMA2D_CSC_RX_SCRAMBLE, /*!< 2D-DMA RX perform only data scramble */ - DMA2D_CSC_RX_YUV422_TO_YUV444, /*!< 2D-DMA RX perform YUV422 to YUV444 conversion */ - DMA2D_CSC_RX_YUV420_TO_YUV444, /*!< 2D-DMA RX perform YUV420 to YUV444 conversion */ - DMA2D_CSC_RX_YUV420_TO_RGB888_601, /*!< 2D-DMA RX perform YUV420 to RGB888 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV420_TO_RGB565_601, /*!< 2D-DMA RX perform YUV420 to RGB565 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV420_TO_RGB888_709, /*!< 2D-DMA RX perform YUV420 to RGB888 conversion (follow BT709 standard) */ - DMA2D_CSC_RX_YUV420_TO_RGB565_709, /*!< 2D-DMA RX perform YUV420 to RGB565 conversion (follow BT709 standard) */ - DMA2D_CSC_RX_YUV422_TO_RGB888_601, /*!< 2D-DMA RX perform YUV422 to RGB888 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV422_TO_RGB565_601, /*!< 2D-DMA RX perform YUV422 to RGB565 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV422_TO_RGB888_709, /*!< 2D-DMA RX perform YUV422 to RGB888 conversion (follow BT709 standard) */ - DMA2D_CSC_RX_YUV422_TO_RGB565_709, /*!< 2D-DMA RX perform YUV422 to RGB565 conversion (follow BT709 standard) */ - DMA2D_CSC_RX_YUV444_TO_RGB888_601, /*!< 2D-DMA RX perform YUV444 to RGB888 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV444_TO_RGB565_601, /*!< 2D-DMA RX perform YUV444 to RGB565 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV444_TO_RGB888_709, /*!< 2D-DMA RX perform YUV444 to RGB888 conversion (follow BT709 standard) */ - DMA2D_CSC_RX_YUV444_TO_RGB565_709, /*!< 2D-DMA RX perform YUV444 to RGB565 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV422_TO_YUV444, /*!< 2D-DMA RX perform YUV422-JPEG to YUV444 conversion */ + DMA2D_CSC_RX_YUV422_TO_YUV420, /*!< 2D-DMA RX perform YUV422-JPEG to YUV420 conversion */ + DMA2D_CSC_RX_YUV420_TO_YUV444, /*!< 2D-DMA RX perform YUV420-JPEG to YUV444 conversion */ + DMA2D_CSC_RX_YUV420_TO_RGB888_601, /*!< 2D-DMA RX perform YUV420-JPEG to RGB888 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV420_TO_RGB565_601, /*!< 2D-DMA RX perform YUV420-JPEG to RGB565 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV420_TO_RGB888_709, /*!< 2D-DMA RX perform YUV420-JPEG to RGB888 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV420_TO_RGB565_709, /*!< 2D-DMA RX perform YUV420-JPEG to RGB565 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV422_TO_RGB888_601, /*!< 2D-DMA RX perform YUV422-JPEG to RGB888 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV422_TO_RGB565_601, /*!< 2D-DMA RX perform YUV422-JPEG to RGB565 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV422_TO_RGB888_709, /*!< 2D-DMA RX perform YUV422-JPEG to RGB888 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV422_TO_RGB565_709, /*!< 2D-DMA RX perform YUV422-JPEG to RGB565 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV444_TO_YUV422, /*!< 2D-DMA RX perform YUV444-JPEG to YUV422-MIPI conversion */ + DMA2D_CSC_RX_YUV444_TO_YUV420, /*!< 2D-DMA RX perform YUV444-JPEG to YUV420 conversion */ + DMA2D_CSC_RX_YUV444_TO_RGB888_601, /*!< 2D-DMA RX perform YUV444-JPEG to RGB888 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV444_TO_RGB565_601, /*!< 2D-DMA RX perform YUV444-JPEG to RGB565 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV444_TO_RGB888_709, /*!< 2D-DMA RX perform YUV444-JPEG to RGB888 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV444_TO_RGB565_709, /*!< 2D-DMA RX perform YUV444-JPEG to RGB565 conversion (follow BT709 standard) */ DMA2D_CSC_RX_INVALID, /*!< Invalid 2D-DMA RX color space conversion */ } dma2d_csc_rx_option_t; diff --git a/components/hal/include/hal/gpio_hal.h b/components/hal/include/hal/gpio_hal.h index aaaac253c418..9b03c9b1e365 100644 --- a/components/hal/include/hal/gpio_hal.h +++ b/components/hal/include/hal/gpio_hal.h @@ -172,7 +172,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num); #define gpio_hal_output_enable(hal, gpio_num) gpio_ll_output_enable((hal)->dev, gpio_num) /** - * @brief Configure the source of output enable signal for the GPIO pin. + * @brief Configure the source of output enable signal for the pad (only takes effect if func sel is selected to be GPIO). * * @param hal Context of the HAL layer * @param gpio_num GPIO number @@ -334,7 +334,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num); */ #define gpio_hal_is_digital_io_hold(hal, gpio_num) gpio_ll_is_digital_io_hold((hal)->dev, gpio_num) -#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP /** * @brief Enable all digital gpio pad hold function during Deep-sleep. * @@ -365,7 +365,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num); * - false deep sleep hold is disabled */ #define gpio_hal_deep_sleep_hold_is_en(hal) gpio_ll_deep_sleep_hold_is_en((hal)->dev) -#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP /** * @brief Set pad input to a peripheral signal through the IOMUX. diff --git a/components/hal/include/hal/isp_types.h b/components/hal/include/hal/isp_types.h index 974c5a3d354b..dc72142c192c 100644 --- a/components/hal/include/hal/isp_types.h +++ b/components/hal/include/hal/isp_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -125,6 +125,14 @@ typedef enum { AWB ---------------------------------------------------------------*/ +#if SOC_ISP_AWB_WINDOW_X_NUMS +#define ISP_AWB_WINDOW_X_NUM SOC_ISP_AWB_WINDOW_X_NUMS // The AWB window number for sampling +#define ISP_AWB_WINDOW_Y_NUM SOC_ISP_AWB_WINDOW_Y_NUMS // The AWB window number for sampling +#else +#define ISP_AWB_WINDOW_X_NUM 0 +#define ISP_AWB_WINDOW_Y_NUM 0 +#endif + /** * @brief ISP AWB sample point in the ISP pipeline */ @@ -133,12 +141,21 @@ typedef enum { ISP_AWB_SAMPLE_POINT_AFTER_CCM, ///< Sample AWB data after CCM (Color Correction Matrix) } isp_awb_sample_point_t; +/** + * @brief ISP AWB gain + */ +typedef struct { + uint32_t gain_r; ///< White balance gain for R channel + uint32_t gain_g; ///< White balance gain for G channel + uint32_t gain_b; ///< White balance gain for B channel +} isp_awb_gain_t; + /*--------------------------------------------------------------- BF ---------------------------------------------------------------*/ #if SOC_ISP_BF_SUPPORTED -#define ISP_BF_TEMPLATE_X_NUMS SOC_ISP_BF_TEMPLATE_X_NUMS // BF template x field nums -#define ISP_BF_TEMPLATE_Y_NUMS SOC_ISP_BF_TEMPLATE_Y_NUMS // BF template y field nums +#define ISP_BF_TEMPLATE_X_NUMS SOC_ISP_BF_TEMPLATE_X_NUMS ///< BF template x field nums +#define ISP_BF_TEMPLATE_Y_NUMS SOC_ISP_BF_TEMPLATE_Y_NUMS ///< BF template y field nums #else #define ISP_BF_TEMPLATE_X_NUMS 0 #define ISP_BF_TEMPLATE_Y_NUMS 0 @@ -418,6 +435,18 @@ typedef union { uint32_t val; ///< 32-bit gradient ratio value } isp_lsc_gain_t; +/*--------------------------------------------------------------- + WBG (White Balance Gain) +---------------------------------------------------------------*/ +/** + * @brief ISP White Balance Gain + */ +typedef struct { + uint32_t gain_r; ///< White balance gain for R channel + uint32_t gain_g; ///< White balance gain for G channel + uint32_t gain_b; ///< White balance gain for B channel +} isp_wbg_gain_t; + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/ppa_types.h b/components/hal/include/hal/ppa_types.h index 67741433c5c0..6f9932225506 100644 --- a/components/hal/include/hal/ppa_types.h +++ b/components/hal/include/hal/ppa_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -44,8 +44,11 @@ typedef enum { // YUV444 not supported by PPA hardware, but we can use 2D-DMA to do conversion before sending into and after coming out from the PPA module // If in_pic is YUV444, then TX DMA channel could do DMA2D_CSC_TX_YUV444_TO_RGB888_601/709, so PPA in_color_mode is RGB888 // If out_pic is YUV444, then RX DMA channel could do DMA2D_CSC_RX_YUV420_TO_YUV444, so PPA out_color_mode is YUV420 - // TODO: P4 ECO2 supports YUV422 - // PPA_SRM_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA SRM color mode: YUV422 (input only, limited range only) */ + PPA_SRM_COLOR_MODE_YUV422_UYVY = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_UYVY422), /*!< PPA SRM color mode: YUV422 */ + PPA_SRM_COLOR_MODE_YUV422_VYUY = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_VYUY422), /*!< PPA SRM color mode: YUV422, only available on input */ + PPA_SRM_COLOR_MODE_YUV422_YUYV = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUYV422), /*!< PPA SRM color mode: YUV422, only available on input */ + PPA_SRM_COLOR_MODE_YUV422_YVYU = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YVYU422), /*!< PPA SRM color mode: YUV422, only available on input */ + PPA_SRM_COLOR_MODE_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< PPA SRM color mode: GRAY8 */ } ppa_srm_color_mode_t; /** @@ -57,9 +60,15 @@ typedef enum { PPA_BLEND_COLOR_MODE_RGB565 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565), /*!< PPA blend color mode: RGB565 */ PPA_BLEND_COLOR_MODE_A8 = COLOR_TYPE_ID(COLOR_SPACE_ALPHA, COLOR_PIXEL_A8), /*!< PPA blend color mode: A8, only available on blend foreground input */ PPA_BLEND_COLOR_MODE_A4 = COLOR_TYPE_ID(COLOR_SPACE_ALPHA, COLOR_PIXEL_A4), /*!< PPA blend color mode: A4, only available on blend foreground input */ + PPA_BLEND_COLOR_MODE_YUV420 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV420), /*!< PPA blend color mode: YUV420, only available on blend background input or on output */ + PPA_BLEND_COLOR_MODE_YUV422_UYVY = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_UYVY422), /*!< PPA blend color mode: YUV422, only available on blend background input or on output */ + PPA_BLEND_COLOR_MODE_YUV422_VYUY = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_VYUY422), /*!< PPA blend color mode: YUV422, only available on blend background input */ + PPA_BLEND_COLOR_MODE_YUV422_YUYV = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUYV422), /*!< PPA blend color mode: YUV422, only available on blend background input */ + PPA_BLEND_COLOR_MODE_YUV422_YVYU = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YVYU422), /*!< PPA blend color mode: YUV422, only available on blend background input */ + PPA_BLEND_COLOR_MODE_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< PPA blend color mode: GRAY8, only available on blend background input or on output */ // TODO: Support CLUT to support L4/L8 color mode - // PPA_BLEND_COLOR_MODE_L8 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L8), /*!< PPA blend color mode: L8, only available on blend inputs */ - // PPA_BLEND_COLOR_MODE_L4 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L4), /*!< PPA blend color mode: L4, only available on blend inputs */ + // PPA_BLEND_COLOR_MODE_L8 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L8), /*!< PPA blend color mode: L8, only available on blend input */ + // PPA_BLEND_COLOR_MODE_L4 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L4), /*!< PPA blend color mode: L4, only available on blend input */ } ppa_blend_color_mode_t; /** @@ -69,6 +78,9 @@ typedef enum { PPA_FILL_COLOR_MODE_ARGB8888 = COLOR_TYPE_ID(COLOR_SPACE_ARGB, COLOR_PIXEL_ARGB8888), /*!< PPA fill color mode: ARGB8888 */ PPA_FILL_COLOR_MODE_RGB888 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB888), /*!< PPA fill color mode: RGB888 */ PPA_FILL_COLOR_MODE_RGB565 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565), /*!< PPA fill color mode: RGB565 */ + // PPA_FILL_COLOR_MODE_YUV420 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV420), /*!< PPA fill color mode: YUV420 */ // Non-typical YUV420, U and V components have to be the same value + PPA_FILL_COLOR_MODE_YUV422_UYVY = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_UYVY422), /*!< PPA fill color mode: YUV422 (w/ UYVY pack order) */ + PPA_FILL_COLOR_MODE_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< PPA fill color mode: GRAY8 */ } ppa_fill_color_mode_t; /** diff --git a/components/hal/include/hal/usb_dwc_hal.h b/components/hal/include/hal/usb_dwc_hal.h index 9314bfdce61f..6178c1d4b885 100644 --- a/components/hal/include/hal/usb_dwc_hal.h +++ b/components/hal/include/hal/usb_dwc_hal.h @@ -539,6 +539,80 @@ static inline void usb_dwc_hal_disable_debounce_lock(usb_dwc_hal_context_t *hal) usb_dwc_ll_gintmsk_en_intrs(hal->dev, USB_DWC_LL_INTR_CORE_PRTINT | USB_DWC_LL_INTR_CORE_DISCONNINT); } +/** + * @brief Check if the root port is suspended + * + * This function checks if the root port entered suspended state, after calling usb_dwc_hal_port_suspend() + * + * @param hal Context of the HAL layer + * @return true The root port is suspended + * @return false The root port is not suspended + */ +static inline bool usb_dwc_hal_port_check_if_suspended(usb_dwc_hal_context_t *hal) +{ + return usb_dwc_ll_hprt_get_port_suspend(hal->dev); +} + +// ----------------------------------------------------- Power and Clock gating ---------------------------------------- + +/** + * @brief Gate internal clock of the DWC_OTG core + * + * This function gates the internal clock of the DWC_OTG core to reduce power consumption + * + * Internal clock gating: + * - stop PHY clock (PCLK) + * - gate HCLK to modules other than the AHB slave, AHB master and wakeup logic + * Internal clock un-gating: + * - un-stop PHY clock (PCLK) + * - un-gate HCLK + * + * @note This is a part of a sequence from the DWC Programming guide, chapter 14.2.2.1 + * @param hal Context of the HAL layer + * @param enable Enable or disable internal clock gating + */ +static inline void usb_dwc_hal_pwr_clk_internal_clock_gate(usb_dwc_hal_context_t *hal, bool enable) +{ + usb_dwc_ll_set_stoppclk(hal->dev, enable); // Enable/disable PHY clock stop + usb_dwc_ll_set_gatehclk(hal->dev, enable); // Gate/ungate HCLK +} + +/** + * @brief Check if the PHY clock (PCLK) stop is enabled or disabled + * + * @param hal Context of the HAL layer + * @return true The PCLK stop is enabled + * @return false The PCLK stop is not enabled + */ +static inline bool usb_dwc_hal_pwr_clk_check_phy_clk_stopped(usb_dwc_hal_context_t *hal) +{ + return usb_dwc_ll_get_stoppclk_st(hal->dev); +} + +/** + * @brief Check if the HCLK is gated or ungated + * + * @param hal Context of the HAL layer + * @return true The HCLK is gated + * @return false The HCLK is not gated + */ +static inline bool usb_dwc_hal_pwr_clk_check_hclk_gated(usb_dwc_hal_context_t *hal) +{ + return usb_dwc_ll_get_gatehclk_st(hal->dev); +} + +/** + * @brief Check if PHY is in sleep state + * + * @param hal Context of the HAL layer + * @return true The USB PHY is in sleep state + * @return false The USB PHY is not in sleep state + */ +static inline bool usb_dwc_hal_pwr_clk_check_phy_sleep(usb_dwc_hal_context_t *hal) +{ + return usb_dwc_ll_get_physleep_st(hal->dev); +} + // ----------------------------------------------------- Channel ------------------------------------------------------- // ----------------- Channel Allocation -------------------- diff --git a/components/idf_test/include/esp32/idf_performance_target.h b/components/idf_test/include/esp32/idf_performance_target.h index c222734ef4b3..c7933cf59f71 100644 --- a/components/idf_test/include/esp32/idf_performance_target.h +++ b/components/idf_test/include/esp32/idf_performance_target.h @@ -22,11 +22,11 @@ #define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 4500 #define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 19000 -#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 450000 +#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 750000 #define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP 33000 #define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP 950000 #define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 90000 -#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 1900000 +#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 3000000 // floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround) #define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70 diff --git a/components/idf_test/include/esp32s2/idf_performance_target.h b/components/idf_test/include/esp32s2/idf_performance_target.h index 07baf2ca51d2..0d2b6f0dd36f 100644 --- a/components/idf_test/include/esp32s2/idf_performance_target.h +++ b/components/idf_test/include/esp32s2/idf_performance_target.h @@ -17,11 +17,11 @@ #define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 900 #define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 13500 -#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 420000 +#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 650000 #define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP 36000 #define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP 960000 #define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 62000 -#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 1850000 +#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 2850000 #define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_NO_FILTER 3 #define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_2 3 diff --git a/components/idf_test/include/esp32s3/idf_performance_target.h b/components/idf_test/include/esp32s3/idf_performance_target.h index 9f485b382c27..3b2bbe3b42f8 100644 --- a/components/idf_test/include/esp32s3/idf_performance_target.h +++ b/components/idf_test/include/esp32s3/idf_performance_target.h @@ -15,11 +15,11 @@ #define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 900 #define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 18000 -#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 490000 +#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 700000 #define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP 45000 #define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP 1300000 #define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 80000 -#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 2500000 +#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 3500000 // floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround) #define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70 diff --git a/components/ieee802154/driver/esp_ieee802154_debug.c b/components/ieee802154/driver/esp_ieee802154_debug.c index 21c315c4b9bf..8aa30f26cc3d 100644 --- a/components/ieee802154/driver/esp_ieee802154_debug.c +++ b/components/ieee802154/driver/esp_ieee802154_debug.c @@ -210,8 +210,8 @@ void ieee802154_record_print(void) #if CONFIG_IEEE802154_RECORD_STATE ESP_EARLY_LOGW(IEEE802154_TAG, "Print the record state, current state index: %d", g_ieee802154_probe.state_index); for (uint8_t i = 0; i < IEEE802154_ASSERT_RECORD_STATE_SIZE; i++) { - ESP_EARLY_LOGW(IEEE802154_TAG, "index %2d: line:%5s, state:%10s, timestamp: %lld", - i, g_ieee802154_probe.state[i].line_str, + ESP_EARLY_LOGW(IEEE802154_TAG, "index %2d: line:%5lu, state:%10s, timestamp: %lld", + i, g_ieee802154_probe.state[i].line, ieee802154_state_string[g_ieee802154_probe.state[i].state], g_ieee802154_probe.state[i].timestamp); } @@ -221,8 +221,8 @@ void ieee802154_record_print(void) #if CONFIG_IEEE802154_RECORD_CMD ESP_EARLY_LOGW(IEEE802154_TAG, "Print the record cmd, current cmd index: %d", g_ieee802154_probe.cmd_index); for (uint8_t i = 0; i < IEEE802154_ASSERT_RECORD_CMD_SIZE; i++) { - ESP_EARLY_LOGW(IEEE802154_TAG, "index %2d: line:%5s, cmd:%10s, timestamp: %lld", - i, g_ieee802154_probe.cmd[i].line_str, + ESP_EARLY_LOGW(IEEE802154_TAG, "index %2d: line:%5lu, cmd:%10s, timestamp: %lld", + i, g_ieee802154_probe.cmd[i].line, ieee802154_get_cmd_string(g_ieee802154_probe.cmd[i].cmd), g_ieee802154_probe.cmd[i].timestamp); } diff --git a/components/ieee802154/private_include/esp_ieee802154_util.h b/components/ieee802154/private_include/esp_ieee802154_util.h index b323367b9ceb..5efdac1c26e2 100644 --- a/components/ieee802154/private_include/esp_ieee802154_util.h +++ b/components/ieee802154/private_include/esp_ieee802154_util.h @@ -78,7 +78,7 @@ typedef struct { #if CONFIG_IEEE802154_RECORD_STATE #define IEEE802154_ASSERT_RECORD_STATE_SIZE CONFIG_IEEE802154_RECORD_STATE_SIZE #define ieee802154_set_state(a) do { s_ieee802154_state = a; \ - sprintf(g_ieee802154_probe.state[g_ieee802154_probe.state_index].line_str, "%d", __LINE__); \ + g_ieee802154_probe.state[g_ieee802154_probe.state_index].line = __LINE__; \ g_ieee802154_probe.state[g_ieee802154_probe.state_index].timestamp = esp_timer_get_time(); \ g_ieee802154_probe.state[g_ieee802154_probe.state_index++].state = a; \ g_ieee802154_probe.state_index = \ @@ -89,7 +89,7 @@ typedef struct { * @brief The table of recording IEEE802154 state command. */ typedef struct { - char line_str[5]; /*!< record which line in esp_ieee802154_dev.c changes the state */ + uint32_t line; /*!< record which line in esp_ieee802154_dev.c changes the state */ ieee802154_state_t state; /*!< record current radio state */ uint64_t timestamp; /*!< record timestamp */ } ieee802154_state_info_t; @@ -100,7 +100,7 @@ typedef struct { #if CONFIG_IEEE802154_RECORD_CMD #define IEEE802154_ASSERT_RECORD_CMD_SIZE CONFIG_IEEE802154_RECORD_CMD_SIZE #define ieee802154_set_cmd(a) do { ieee802154_ll_set_cmd(a); \ - sprintf(g_ieee802154_probe.cmd[g_ieee802154_probe.cmd_index].line_str, "%d", __LINE__); \ + g_ieee802154_probe.cmd[g_ieee802154_probe.cmd_index].line = __LINE__; \ g_ieee802154_probe.cmd[g_ieee802154_probe.cmd_index].timestamp = esp_timer_get_time(); \ g_ieee802154_probe.cmd[g_ieee802154_probe.cmd_index++].cmd = a; \ g_ieee802154_probe.cmd_index = \ @@ -111,7 +111,7 @@ typedef struct { * @brief The table of recording IEEE802154 radio command. */ typedef struct { - char line_str[5]; /*!< record which line in esp_ieee802154_dev.c set the command */ + uint32_t line; /*!< record which line in esp_ieee802154_dev.c set the command */ ieee802154_ll_cmd_t cmd; /*!< record current command */ uint64_t timestamp; /*!< record timestamp */ } ieee802154_cmd_info_t; diff --git a/components/lwip/port/hooks/tcp_isn_default.c b/components/lwip/port/hooks/tcp_isn_default.c index 71020cee515f..7996b2f3d908 100644 --- a/components/lwip/port/hooks/tcp_isn_default.c +++ b/components/lwip/port/hooks/tcp_isn_default.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -82,6 +82,10 @@ #include "esp_rom_md5.h" #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY #include "esp_memory_utils.h" +#if CONFIG_IDF_TARGET_ESP32 +#include "hal/efuse_hal.h" +#include "soc/chip_revision.h" +#endif #endif #ifdef CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT @@ -169,13 +173,13 @@ lwip_hook_tcp_isn(const ip_addr_t *local_ip, u16_t local_port, /* * Generate the hash using ROM MD5 APIs - * This hook is invoked in the context of TCP/IP (tiT) task and - * it is unlikely that its stack would be placed in SPIRAM. Hence - * even with SPIRAM enabled case and ESP32 revision < 3, using ROM - * APIs should not create any issues. + * For ESP32 chips prior to ECO3, the stack pointer must not point to external RAM + * to use the ROM MD5 functions. + * Other chips (ESP32-S2, ESP32-S3, ESP32-C3, etc.) don't have this limitation. */ -#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY - assert(!esp_ptr_external_ram(esp_cpu_get_sp())); +#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY && CONFIG_IDF_TARGET_ESP32 + /* Only assert for ESP32 revision < ECO3 (revision 300) */ + assert(ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 300) || !esp_ptr_external_ram(esp_cpu_get_sp())); #endif md5_context_t ctx; diff --git a/components/mbedtls/mbedtls b/components/mbedtls/mbedtls index b5d87eaa6748..ffb280bb63c7 160000 --- a/components/mbedtls/mbedtls +++ b/components/mbedtls/mbedtls @@ -1 +1 @@ -Subproject commit b5d87eaa6748b7a6fa70593178c08b4480e9b71e +Subproject commit ffb280bb63c78bfec1e1ab55040671768c85c923 diff --git a/components/mbedtls/port/esp_hardware.c b/components/mbedtls/port/esp_hardware.c index 6376ca8f8c2c..5633cccf3a65 100644 --- a/components/mbedtls/port/esp_hardware.c +++ b/components/mbedtls/port/esp_hardware.c @@ -9,6 +9,7 @@ #include #include #include "esp_random.h" +#include "mbedtls/esp_mbedtls_random.h" #include @@ -23,3 +24,10 @@ int mbedtls_hardware_poll( void *data, *olen = len; return 0; } + +int mbedtls_esp_random(void *ctx, unsigned char *buf, size_t len) +{ + (void) ctx; // unused + esp_fill_random(buf, len); + return 0; +} diff --git a/components/mbedtls/port/include/mbedtls/esp_mbedtls_random.h b/components/mbedtls/port/include/mbedtls/esp_mbedtls_random.h new file mode 100644 index 000000000000..a89575c2dc23 --- /dev/null +++ b/components/mbedtls/port/include/mbedtls/esp_mbedtls_random.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief MbedTLS-compatible RNG function + * + * @note Suitable for passing as f_rng to various MbedTLS APIs that require it. + * It uses esp_fill_random internally, and the caller must ensure that the + * entropy sources of the RNG peripheral are enabled correctly. See the RNG + * chapter in the TRM for more details. + * + * @param ctx User-supplied context + * @param buf Pointer to a buffer to fill with random numbers + * @param len Length of the buffer in bytes + * + * @return 0 on success + */ +int mbedtls_esp_random(void *ctx, unsigned char *buf, size_t len); + +#ifdef __cplusplus +} +#endif diff --git a/components/mbedtls/test_apps/main/test_ds_sign_and_decrypt.c b/components/mbedtls/test_apps/main/test_ds_sign_and_decrypt.c index cf3f23f14e16..9ad56e3ea348 100644 --- a/components/mbedtls/test_apps/main/test_ds_sign_and_decrypt.c +++ b/components/mbedtls/test_apps/main/test_ds_sign_and_decrypt.c @@ -21,7 +21,7 @@ static heap_trace_record_t trace_record[NUM_RECORDS]; // This buffer must be in #include "esp_ds.h" #include "esp_ds/esp_ds_rsa.h" -int mbedtls_esp_random(void *ctx, unsigned char *output, size_t len) +static int mbedtls_esp_random(void *ctx, unsigned char *output, size_t len) { if (len == 0 || output == NULL) { return -1; diff --git a/components/nvs_sec_provider/nvs_sec_provider.c b/components/nvs_sec_provider/nvs_sec_provider.c index e45c84f4db99..5be47a30e6a6 100644 --- a/components/nvs_sec_provider/nvs_sec_provider.c +++ b/components/nvs_sec_provider/nvs_sec_provider.c @@ -86,15 +86,14 @@ ESP_SYSTEM_INIT_FN(nvs_sec_provider_register_flash_enc_scheme, SECONDARY, BIT(0) nvs_sec_config_flash_enc_t sec_scheme_cfg = NVS_SEC_PROVIDER_CFG_FLASH_ENC_DEFAULT(); - /* + /* * This checks partition with subtype nvs_keys from partition table, if NVS Encryption is enabled - * and "nvs_keys" do not exist in partition table, then execution gets aborted. To fix the problem, + * and "nvs_keys" do not exist in partition table, then warning message is printed. To fix the problem, * please introduce partition with subtype "nvs_keys" in the partition table. */ if (sec_scheme_cfg.nvs_keys_part == NULL) { - ESP_EARLY_LOGE(TAG, "partition with subtype \"nvs_keys\" not found"); - return ESP_FAIL; + ESP_EARLY_LOGW(TAG, "Partition with subtype \"nvs_keys\" not found"); } nvs_sec_scheme_t *sec_scheme_handle_out = NULL; diff --git a/components/openthread/Kconfig b/components/openthread/Kconfig index b113cfd1f4c0..9b814a47fef0 100644 --- a/components/openthread/Kconfig +++ b/components/openthread/Kconfig @@ -430,7 +430,7 @@ menu "OpenThread" config OPENTHREAD_PLATFORM_MSGPOOL_MANAGEMENT bool 'Allocate message pool buffer from PSRAM' - default n + default y help If enabled, the message pool is managed by platform defined logic. endmenu @@ -464,7 +464,8 @@ menu "OpenThread" config OPENTHREAD_NUM_MESSAGE_BUFFERS int "The number of openthread message buffers" - default 65 + default 65 if !OPENTHREAD_PLATFORM_MSGPOOL_MANAGEMENT + default 1024 if OPENTHREAD_PLATFORM_MSGPOOL_MANAGEMENT config OPENTHREAD_XTAL_ACCURACY int "The accuracy of the XTAL" diff --git a/components/openthread/include/esp_radio_spinel.h b/components/openthread/include/esp_radio_spinel.h index 504eda1f4f82..18638b3275cb 100644 --- a/components/openthread/include/esp_radio_spinel.h +++ b/components/openthread/include/esp_radio_spinel.h @@ -18,10 +18,6 @@ extern "C" { #define ESP_SPINEL_LOG_TAG "ESP_RADIO_SPINEL" -#define SPINEL_PROP_VENDOR_ESP_SET_COORDINATOR (SPINEL_PROP_VENDOR_ESP__BEGIN + 1) /* Vendor command for coordinator.*/ - -#define SPINEL_PROP_VENDOR_ESP_SET_PENDINGMODE (SPINEL_PROP_VENDOR_ESP__BEGIN + 2) /* Vendor command for pending mode.*/ - typedef enum { ESP_RADIO_SPINEL_ZIGBEE = 0x0, /* The index of Zigbee.*/ ESP_RADIO_SPINEL_OPENTHREAD = 0x1, /* The index of OpenThread.*/ diff --git a/components/openthread/lib b/components/openthread/lib index 52f5e03e6c53..60df1b5e8d6c 160000 --- a/components/openthread/lib +++ b/components/openthread/lib @@ -1 +1 @@ -Subproject commit 52f5e03e6c535a67750a710c4c4066b9c9a5b7d3 +Subproject commit 60df1b5e8d6c2e64730105508bef1105eccf98f4 diff --git a/components/openthread/private_include/esp_openthread_ncp.h b/components/openthread/private_include/esp_openthread_ncp.h index 65053bb56a8a..45b585cf33b8 100644 --- a/components/openthread/private_include/esp_openthread_ncp.h +++ b/components/openthread/private_include/esp_openthread_ncp.h @@ -4,19 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include #include -#if CONFIG_OPENTHREAD_NCP_VENDOR_HOOK - -#define SPINEL_PROP_VENDOR_ESP_SET_COORDINATOR (SPINEL_PROP_VENDOR_ESP__BEGIN + 1) - -#define SPINEL_PROP_VENDOR_ESP_SET_PENDINGMODE (SPINEL_PROP_VENDOR_ESP__BEGIN + 2) - -#define SPINEL_PROP_VENDOR_ESP_COEX_EVENT (SPINEL_PROP_VENDOR_ESP__BEGIN + 3) - -#endif - #ifdef __cplusplus extern "C" { #endif diff --git a/components/openthread/private_include/esp_spinel_ncp_vendor_macro.h b/components/openthread/private_include/esp_spinel_ncp_vendor_macro.h new file mode 100644 index 000000000000..3bd9f4fb8572 --- /dev/null +++ b/components/openthread/private_include/esp_spinel_ncp_vendor_macro.h @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "spinel.h" + +#define SPINEL_PROP_VENDOR_ESP_SET_COORDINATOR (SPINEL_PROP_VENDOR_ESP__BEGIN + 1) /* Vendor command for coordinator.*/ + +#define SPINEL_PROP_VENDOR_ESP_SET_PENDINGMODE (SPINEL_PROP_VENDOR_ESP__BEGIN + 2) /* Vendor command for pending mode.*/ + +#define SPINEL_PROP_VENDOR_ESP_COEX_EVENT (SPINEL_PROP_VENDOR_ESP__BEGIN + 3) diff --git a/components/openthread/src/ncp/esp_openthread_ncp.cpp b/components/openthread/src/ncp/esp_openthread_ncp.cpp index 94c31113dece..b6e70eca1fc3 100644 --- a/components/openthread/src/ncp/esp_openthread_ncp.cpp +++ b/components/openthread/src/ncp/esp_openthread_ncp.cpp @@ -7,6 +7,7 @@ #include "sdkconfig.h" #include "esp_ieee802154.h" #include "esp_openthread_ncp.h" +#include "esp_spinel_ncp_vendor_macro.h" #include "ncp_base.hpp" #if (CONFIG_ESP_COEX_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE) diff --git a/components/openthread/src/spinel/esp_radio_spinel.cpp b/components/openthread/src/spinel/esp_radio_spinel.cpp index bbcc8d2bea18..8d561d27043b 100644 --- a/components/openthread/src/spinel/esp_radio_spinel.cpp +++ b/components/openthread/src/spinel/esp_radio_spinel.cpp @@ -12,6 +12,7 @@ #include "esp_radio_spinel.h" #include "esp_radio_spinel_platform.h" #include "esp_radio_spinel_adapter.hpp" +#include "esp_spinel_ncp_vendor_macro.h" #include "esp_radio_spinel_uart_interface.hpp" #include "spinel_driver.hpp" #include "openthread/link.h" diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index bb2b588d51c6..9863806644d9 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -351,10 +351,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_I2C_NUM int default 2 diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index f6f8ff21b81a..efbf5c650c1b 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -193,9 +193,6 @@ #define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) -// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) - /*-------------------------- I2C CAPS ----------------------------------------*/ // ESP32 has 2 I2C #define SOC_I2C_NUM (2U) diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index a86595bde12d..12e0ea0b2c0f 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -331,10 +331,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM int default 8 diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index cab674000bf4..9827a2b58be3 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -145,9 +145,6 @@ #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) -// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) - /*-------------------------- Dedicated GPIO CAPS -----------------------------*/ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index 1b43b4327757..be3a00da01af 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -427,10 +427,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM int default 8 diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index 36e1c7623907..17ed62de5b74 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -184,9 +184,6 @@ #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) -// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) - /*-------------------------- Dedicated GPIO CAPS -----------------------------*/ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 6fae40650727..b139ff6c1cbd 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -539,10 +539,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index ec8bc3aba76c..5e35fa402d9f 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -229,8 +229,6 @@ // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) // Support to hold a single digital I/O when the digital domain is powered off #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 7fa2377bb50a..56c5e6c0c8fa 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -527,10 +527,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 87721fb57ba1..30107729336d 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -214,8 +214,6 @@ // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) // Support to hold a single digital I/O when the digital domain is powered off #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index bbd8f3647f16..fdf5317f2c54 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -359,10 +359,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 59b6789de722..d0d60b06b67f 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -192,8 +192,6 @@ // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// "LP"_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) // Support to hold a single digital I/O when the digital domain is powered off #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 8ac622fe181b..e234a7f28ff9 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -539,10 +539,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index d6216654fb48..d0702c811d92 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -237,8 +237,6 @@ // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) // Support to hold a single digital I/O when the digital domain is powered off #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) diff --git a/components/soc/esp32p4/dma2d_periph.c b/components/soc/esp32p4/dma2d_periph.c index e7043df94283..7cd670382a96 100644 --- a/components/soc/esp32p4/dma2d_periph.c +++ b/components/soc/esp32p4/dma2d_periph.c @@ -14,10 +14,12 @@ const dma2d_signal_conn_t dma2d_periph_signals = { [0] = ETS_DMA2D_OUT_CH0_INTR_SOURCE, [1] = ETS_DMA2D_OUT_CH1_INTR_SOURCE, [2] = ETS_DMA2D_OUT_CH2_INTR_SOURCE, + [3] = ETS_DMA2D_OUT_CH3_INTR_SOURCE, // This channel only exists on P4 ver. >= 3.0 }, .rx_irq_id = { [0] = ETS_DMA2D_IN_CH0_INTR_SOURCE, [1] = ETS_DMA2D_IN_CH1_INTR_SOURCE, + [2] = ETS_DMA2D_IN_CH2_INTR_SOURCE, // This channel only exists on P4 ver. >= 3.0 } } } diff --git a/components/soc/esp32p4/emac_periph.c b/components/soc/esp32p4/emac_periph.c index 2ae26ddd25a0..624a086ff88b 100644 --- a/components/soc/esp32p4/emac_periph.c +++ b/components/soc/esp32p4/emac_periph.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,9 +13,9 @@ const emac_io_info_t emac_io_idx = { .mii_tx_clk_i_idx = EMAC_TX_CLK_PAD_IN_IDX, .mii_tx_en_o_idx = EMAC_PHY_TXEN_PAD_OUT_IDX, .mii_txd0_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX, - .mii_txd1_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX, - .mii_txd2_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX, - .mii_txd3_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX, + .mii_txd1_o_idx = EMAC_PHY_TXD1_PAD_OUT_IDX, + .mii_txd2_o_idx = EMAC_PHY_TXD2_PAD_OUT_IDX, + .mii_txd3_o_idx = EMAC_PHY_TXD3_PAD_OUT_IDX, .mii_rx_clk_i_idx = EMAC_RX_CLK_PAD_IN_IDX, .mii_rx_dv_i_idx = EMAC_PHY_RXDV_PAD_IN_IDX, .mii_rxd0_i_idx = EMAC_PHY_RXD0_PAD_IN_IDX, diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 4bac8668ec14..18562f866032 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -621,11 +621,11 @@ config SOC_DMA2D_GROUPS config SOC_DMA2D_TX_CHANNELS_PER_GROUP int - default 3 + default 4 config SOC_DMA2D_RX_CHANNELS_PER_GROUP int - default 2 + default 3 config SOC_ETM_GROUPS int @@ -703,6 +703,14 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0x007FFFFFFFFF0000 +config SOC_GPIO_SUPPORT_FORCE_HOLD + bool + default y + +config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP + bool + default y + config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX bool default y @@ -723,10 +731,6 @@ config SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH int default 16 -config SOC_GPIO_SUPPORT_FORCE_HOLD - bool - default y - config SOC_RTCIO_PIN_COUNT int default 16 @@ -911,10 +915,18 @@ config SOC_ISP_BF_SUPPORTED bool default y +config SOC_ISP_BLC_SUPPORTED + bool + default y + config SOC_ISP_CCM_SUPPORTED bool default y +config SOC_ISP_COLOR_SUPPORTED + bool + default y + config SOC_ISP_DEMOSAIC_SUPPORTED bool default y @@ -923,15 +935,15 @@ config SOC_ISP_DVP_SUPPORTED bool default y -config SOC_ISP_SHARPEN_SUPPORTED +config SOC_ISP_LSC_SUPPORTED bool default y -config SOC_ISP_COLOR_SUPPORTED +config SOC_ISP_SHARPEN_SUPPORTED bool default y -config SOC_ISP_LSC_SUPPORTED +config SOC_ISP_WBG_SUPPORTED bool default y @@ -967,6 +979,14 @@ config SOC_ISP_AF_WINDOW_NUMS int default 3 +config SOC_ISP_AWB_WINDOW_X_NUMS + int + default 5 + +config SOC_ISP_AWB_WINDOW_Y_NUMS + int + default 5 + config SOC_ISP_BF_TEMPLATE_X_NUMS int default 3 diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h index f9df80221c5f..b23a6cb8fafe 100644 --- a/components/soc/esp32p4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h @@ -332,7 +332,7 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of I2S */ -#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_APLL, I2S_CLK_SRC_EXTERNAL} +#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_APLL, I2S_CLK_SRC_EXTERNAL} /** * @brief I2S clock source enum @@ -460,10 +460,10 @@ typedef enum { /** * @brief For backward compatibility, old macro definitions are kept. Remove it in the next major release (esp-idf v7.0) */ -#define MIPI_DSI_PHY_CLK_SRC_RC_FAST SOC_MOD_CLK_RC_FAST -#define MIPI_DSI_PHY_CLK_SRC_PLL_F25M SOC_MOD_CLK_PLL_F25M -#define MIPI_DSI_PHY_CLK_SRC_PLL_F20M SOC_MOD_CLK_PLL_F20M -#define MIPI_DSI_PHY_CLK_SRC_DEFAULT SOC_MOD_CLK_PLL_F20M +#define MIPI_DSI_PHY_CLK_SRC_RC_FAST MIPI_DSI_PHY_PLLREF_CLK_SRC_RC_FAST +#define MIPI_DSI_PHY_CLK_SRC_PLL_F25M MIPI_DSI_PHY_PLLREF_CLK_SRC_PLL_F25M +#define MIPI_DSI_PHY_CLK_SRC_PLL_F20M MIPI_DSI_PHY_PLLREF_CLK_SRC_PLL_F20M +#define MIPI_DSI_PHY_CLK_SRC_DEFAULT MIPI_DSI_PHY_PLLREF_CLK_SRC_DEFAULT_LEGACY /////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// diff --git a/components/soc/esp32p4/include/soc/gpio_sig_map.h b/components/soc/esp32p4/include/soc/gpio_sig_map.h index 00aba01a22d9..e1979fb566d0 100644 --- a/components/soc/esp32p4/include/soc/gpio_sig_map.h +++ b/components/soc/esp32p4/include/soc/gpio_sig_map.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -196,13 +196,9 @@ #define PWM1_SYNC2_PAD_IN_IDX 100 #define PWM1_CH2_B_PAD_OUT_IDX 100 #define PWM1_F0_PAD_IN_IDX 101 -#define ADP_CHRG_PAD_OUT_IDX 101 #define PWM1_F1_PAD_IN_IDX 102 -#define ADP_DISCHRG_PAD_OUT_IDX 102 #define PWM1_F2_PAD_IN_IDX 103 -#define ADP_PRB_EN_PAD_OUT_IDX 103 #define PWM1_CAP0_PAD_IN_IDX 104 -#define ADP_SNS_EN_PAD_OUT_IDX 104 #define PWM1_CAP1_PAD_IN_IDX 105 #define TWAI0_STANDBY_PAD_OUT_IDX 105 #define PWM1_CAP2_PAD_IN_IDX 106 @@ -224,7 +220,6 @@ #define USB_SRP_SESSEND_PAD_IN_IDX 114 #define USB_OTG11_DRVVBUS_PAD_OUT_IDX 114 #define USB_SRP_CHRGVBUS_PAD_OUT_IDX 115 -#define OTG_DRVVBUS_PAD_OUT_IDX 116 #define ULPI_CLK_PAD_IN_IDX 117 #define RNG_CHAIN_CLK_PAD_OUT_IDX 117 #define USB_HSPHY_REFCLK_IN_IDX 118 @@ -260,9 +255,7 @@ #define I3C_SLV_SCL_PAD_OUT_IDX 136 #define I3C_SLV_SDA_PAD_IN_IDX 137 #define I3C_SLV_SDA_PAD_OUT_IDX 137 -#define ADP_PRB_PAD_IN_IDX 138 #define I3C_MST_SCL_PULLUP_EN_PAD_OUT_IDX 138 -#define ADP_SNS_PAD_IN_IDX 139 #define I3C_MST_SDA_PULLUP_EN_PAD_OUT_IDX 139 #define USB_JTAG_TDO_BRIDGE_PAD_IN_IDX 140 #define USB_JTAG_TDI_BRIDGE_PAD_OUT_IDX 140 @@ -458,13 +451,13 @@ #define CORE_GPIO_IN_PAD_IN27_IDX 241 #define CORE_GPIO_OUT_PAD_OUT27_IDX 241 #define CORE_GPIO_IN_PAD_IN28_IDX 242 -#define CORE_GPIO_OUT_PAD_OUT28_IDX 242 +#define PARLIO_TX_CS_PAD_OUT_IDX 242 // only exists on ESP32P4 Rev. 3.0 and later #define CORE_GPIO_IN_PAD_IN29_IDX 243 -#define CORE_GPIO_OUT_PAD_OUT29_IDX 243 +#define EMAC_PTP_PPS_PAD_OUT_IDX 243 #define CORE_GPIO_IN_PAD_IN30_IDX 244 -#define CORE_GPIO_OUT_PAD_OUT30_IDX 244 +#define ANA_COMP0_OUT_IDX 244 #define CORE_GPIO_IN_PAD_IN31_IDX 245 -#define CORE_GPIO_OUT_PAD_OUT31_IDX 245 +#define ANA_COMP1_OUT_IDX 245 #define RMT_SIG_PAD_IN0_IDX 246 #define RMT_SIG_PAD_OUT0_IDX 246 #define RMT_SIG_PAD_IN1_IDX 247 @@ -485,4 +478,5 @@ #define SIG_IN_FUNC254_IDX 254 #define SIG_IN_FUNC255_IDX 255 #define SIG_IN_FUNC255_IDX 255 +// version date 230403 #define SIG_GPIO_OUT_IDX 256 diff --git a/components/soc/esp32p4/include/soc/interrupts.h b/components/soc/esp32p4/include/soc/interrupts.h index 78bde5055e83..8745eed1155e 100644 --- a/components/soc/esp32p4/include/soc/interrupts.h +++ b/components/soc/esp32p4/include/soc/interrupts.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -152,8 +152,17 @@ typedef enum { ETS_H264_REG_INTR_SOURCE, ETS_ASSIST_DEBUG_INTR_SOURCE, - ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ -} periph_interrput_t; + // The following sources' int_map_reg addr are not continuous with previous ones (check interrupt_core0/1_struct.h), + // but esp_rom_route_intr_matrix and interrupt_clic_ll_route assume all int_map_reg addr are continuous. + // Therefore, the workaround is to give the three new interrupt sources ID numbers that match with the corresponding correct addresses. + ETS_DMA2D_IN_CH2_INTR_SOURCE = 133, /**< This interrupt source only exists on chip ver. >= 3.0 */ + ETS_DMA2D_OUT_CH3_INTR_SOURCE, /**< This interrupt source only exists on chip ver. >= 3.0 */ + ETS_AXI_PERF_MON_INTR_SOURCE, /**< This interrupt source only exists on chip ver. >= 3.0 */ + + ETS_MAX_INTR_SOURCE, /**< number of interrupt sources (this value is larger than the real number of sources on ver. less than 3.0, but it should be fine)*/ +} periph_interrupt_t; + +typedef periph_interrupt_t periph_interrput_t __attribute__((deprecated("in favor of periph_interrupt_t"))); extern const char *const esp_isr_names[ETS_MAX_INTR_SOURCE]; diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 8042f0bf3faf..c905669cb0f3 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -223,8 +223,8 @@ /*-------------------------- 2D-DMA CAPS -------------------------------------*/ #define SOC_DMA2D_GROUPS (1U) // Number of 2D-DMA groups -#define SOC_DMA2D_TX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA TX (OUT) channels in each group -#define SOC_DMA2D_RX_CHANNELS_PER_GROUP (2) // Number of 2D-DMA RX (IN) channels in each group +#define SOC_DMA2D_TX_CHANNELS_PER_GROUP (4) // Number of 2D-DMA TX (OUT) channels in each group (4th channel only exists on P4 ver. >= 3.0) +#define SOC_DMA2D_RX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA RX (IN) channels in each group (3rd channel only exists on P4 ver. >= 3.0) // #define SOC_DMA2D_SUPPORT_ETM (1) // Support ETM submodule /*-------------------------- ETM CAPS --------------------------------------*/ @@ -265,6 +265,11 @@ // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL +// Support to force hold all IOs +#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) +// Support to hold a single digital I/O when the digital domain is powered off +#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) // Supported only on ESP32P4 rev >= 3.0 (see DIG-399) + // The Clock Out signal is route to the pin by GPIO matrix #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (2) @@ -273,9 +278,6 @@ #define SOC_DEBUG_PROBE_NUM_UNIT (1U) // Number of debug probe units #define SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH (16) // Maximum width of the debug probe output in each unit -// Support to force hold all IOs -#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) - /*-------------------------- RTCIO CAPS --------------------------------------*/ #define SOC_RTCIO_PIN_COUNT 16 #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature, @@ -347,12 +349,14 @@ /*-------------------------- ISP CAPS ----------------------------------------*/ #define SOC_ISP_BF_SUPPORTED 1 +#define SOC_ISP_BLC_SUPPORTED 1 #define SOC_ISP_CCM_SUPPORTED 1 +#define SOC_ISP_COLOR_SUPPORTED 1 #define SOC_ISP_DEMOSAIC_SUPPORTED 1 #define SOC_ISP_DVP_SUPPORTED 1 -#define SOC_ISP_SHARPEN_SUPPORTED 1 -#define SOC_ISP_COLOR_SUPPORTED 1 #define SOC_ISP_LSC_SUPPORTED 1 +#define SOC_ISP_SHARPEN_SUPPORTED 1 +#define SOC_ISP_WBG_SUPPORTED 1 #define SOC_ISP_SHARE_CSI_BRG 1 #define SOC_ISP_NUMS 1U @@ -362,6 +366,8 @@ #define SOC_ISP_AE_BLOCK_Y_NUMS 5 #define SOC_ISP_AF_CTLR_NUMS 1U #define SOC_ISP_AF_WINDOW_NUMS 3 +#define SOC_ISP_AWB_WINDOW_X_NUMS 5 +#define SOC_ISP_AWB_WINDOW_Y_NUMS 5 #define SOC_ISP_BF_TEMPLATE_X_NUMS 3 #define SOC_ISP_BF_TEMPLATE_Y_NUMS 3 #define SOC_ISP_CCM_DIMENSION 3 diff --git a/components/soc/esp32p4/interrupts.c b/components/soc/esp32p4/interrupts.c index 818367e9559f..c02b70eb1595 100644 --- a/components/soc/esp32p4/interrupts.c +++ b/components/soc/esp32p4/interrupts.c @@ -135,4 +135,7 @@ const char *const esp_isr_names[] = { [ETS_H264_DMA2D_IN_CH5_INTR_SOURCE] = "H264_DMA2D_IN_CH5", [ETS_H264_REG_INTR_SOURCE] = "H264_REG", [ETS_ASSIST_DEBUG_INTR_SOURCE] = "ASSIST_DEBUG", + [ETS_DMA2D_IN_CH2_INTR_SOURCE] = "DMA2D_IN_CH2", /* This interrupt source only exists on chip ver. >= 3.0 */ + [ETS_DMA2D_OUT_CH3_INTR_SOURCE] = "DMA2D_OUT_CH3", /* This interrupt source only exists on chip ver. >= 3.0 */ + [ETS_AXI_PERF_MON_INTR_SOURCE] = "AXI_PERF_MON", /* This interrupt source only exists on chip ver. >= 3.0 */ }; diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld index d4d9188c180f..16d134ae6ddf 100644 --- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld +++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld @@ -26,7 +26,7 @@ PROVIDE ( LP2HP_PERI_PMS = 0x500A5800 ); PROVIDE ( DMA_PMS = 0x500A6000 ); PROVIDE ( AXI_PERF_MON = 0x500A8000 ); PROVIDE ( LEDC = 0x500D3000 ); -PROVIDE ( LEDC_GAMMA_RAM = 0x500D3400 ); +PROVIDE ( LEDC_GAMMA_RAM = 0x500D3400 ); PROVIDE ( TIMERG0 = 0x500C2000 ); PROVIDE ( TIMERG1 = 0x500C3000 ); PROVIDE ( SYSTIMER = 0x500E2000 ); diff --git a/components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h index b3f91e92b3cb..a63f6d64ff48 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -1763,42 +1763,21 @@ typedef struct { volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel; volatile dma2d_in_arb_chn_reg_t in_arb; volatile dma2d_in_ro_status_chn_reg_t in_ro_status; - volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; - volatile dma2d_in_color_convert_chn_reg_t in_color_convert; - volatile dma2d_in_scramble_chn_reg_t in_scramble; - volatile dma2d_color_param_group_chn_reg_t in_color_param_group; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; - uint32_t reserved_570[36]; -} dma2d_in_ch0_reg_t; - -typedef struct { - volatile dma2d_in_conf0_chn_reg_t in_conf0; - volatile dma2d_in_int_raw_chn_reg_t in_int_raw; - volatile dma2d_in_int_ena_chn_reg_t in_int_ena; - volatile dma2d_in_int_st_chn_reg_t in_int_st; - volatile dma2d_in_int_clr_chn_reg_t in_int_clr; - volatile dma2d_infifo_status_chn_reg_t infifo_status; - volatile dma2d_in_pop_chn_reg_t in_pop; - volatile dma2d_in_link_conf_chn_reg_t in_link_conf; - volatile dma2d_in_link_addr_chn_reg_t in_link_addr; - volatile dma2d_in_state_chn_reg_t in_state; - volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr; - volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr; - volatile dma2d_in_dscr_chn_reg_t in_dscr; - volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0; - volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1; - volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel; - volatile dma2d_in_arb_chn_reg_t in_arb; - volatile dma2d_in_ro_status_chn_reg_t in_ro_status; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; - uint32_t reserved_64c[45]; -} dma2d_in_ch1_reg_t; + union { + volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; /* only exist on channel0 */ + volatile dma2d_in_etm_conf_chn_reg_t in1_etm_conf; /* specific for channel1 */ + }; + volatile dma2d_in_color_convert_chn_reg_t in_color_convert; /* only exist on channel0 */ + volatile dma2d_in_scramble_chn_reg_t in_scramble; /* only exist on channel0 */ + volatile dma2d_color_param_group_chn_reg_t in_color_param_group; /* only exist on channel0 */ + volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; /* On ver. less than 3.0, channel 1 in_etm_conf register is at the in_ro_pd_conf addr. Here is to only be compatible with new ECOs. Workaround should be done in LL layer. */ + uint32_t reserved_in[36]; +} dma2d_in_chn_reg_t; typedef struct dma2d_dev_t { volatile dma2d_out_chn_reg_t out_channel[3]; uint32_t reserved_300[128]; - volatile dma2d_in_ch0_reg_t in_channel0; - volatile dma2d_in_ch1_reg_t in_channel1; + volatile dma2d_in_chn_reg_t in_channel[2]; uint32_t reserved_700[192]; volatile dma2d_axi_err_reg_t axi_err; volatile dma2d_rst_conf_reg_t rst_conf; diff --git a/components/soc/esp32p4/register/hw_ver1/soc/i2s_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/i2s_struct.h index 191b9dc6a1bb..3ee8f8959f45 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/i2s_struct.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/i2s_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -282,10 +282,7 @@ typedef union { */ typedef union { struct { - /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0; - * I2S TX PDM bypass hp filter or not. The option has been removed. - */ - uint32_t tx_pdm_hp_bypass:1; + uint32_t reserved_0:1; /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2; * I2S TX PDM OSR2 value */ diff --git a/components/soc/esp32p4/register/hw_ver1/soc/isp_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/isp_struct.h index c5edfc6a19a4..404fb29912b9 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/isp_struct.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/isp_struct.h @@ -2629,7 +2629,7 @@ typedef union { uint32_t reserved_17:15; }; uint32_t val; -} isp_hist_binn_reg_t; +} isp_hist_bin_reg_t; /** Type of rdn_eco_cs register * rdn eco cs register @@ -3262,7 +3262,7 @@ typedef struct { volatile isp_hist_size_reg_t hist_size; volatile isp_hist_seg_reg_t hist_seg[4]; volatile isp_hist_weight_reg_t hist_weight[7]; - volatile isp_hist_binn_reg_t hist_binn[16]; + volatile isp_hist_bin_reg_t hist_bin[16]; volatile isp_mem_aux_ctrl_0_reg_t mem_aux_ctrl_0; volatile isp_mem_aux_ctrl_1_reg_t mem_aux_ctrl_1; volatile isp_mem_aux_ctrl_2_reg_t mem_aux_ctrl_2; diff --git a/components/soc/esp32p4/register/hw_ver1/soc/ledc_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/ledc_struct.h index 6f28cf38215c..0fa6923d6c03 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/ledc_struct.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/ledc_struct.h @@ -106,10 +106,10 @@ typedef union { */ typedef union { struct { - /** duty_ch0_r : RO; bitpos: [24:0]; default: 0; + /** duty_r : RO; bitpos: [24:0]; default: 0; * Represents the current duty of output signal on channel n. */ - uint32_t duty:25; + uint32_t duty_r:25; uint32_t reserved_25:7; }; uint32_t val; @@ -577,20 +577,20 @@ typedef union { */ typedef union { struct { - /** ch0_gamma_entry_num : R/W; bitpos: [4:0]; default: 0; + /** gamma_entry_num : R/W; bitpos: [4:0]; default: 0; * Configures the number of duty cycle fading rages for LEDC chn. */ - uint32_t ch0_gamma_entry_num:5; - /** ch0_gamma_pause : WT; bitpos: [5]; default: 0; + uint32_t gamma_entry_num:5; + /** gamma_pause : WT; bitpos: [5]; default: 0; * Configures whether or not to pause duty cycle fading of LEDC chn.\\0: Invalid. No * effect\\1: Pause */ - uint32_t ch0_gamma_pause:1; - /** ch0_gamma_resume : WT; bitpos: [6]; default: 0; + uint32_t gamma_pause:1; + /** gamma_resume : WT; bitpos: [6]; default: 0; * Configures whether or nor to resume duty cycle fading of LEDC chn.\\0: Invalid. No * effect\\1: Resume */ - uint32_t ch0_gamma_resume:1; + uint32_t gamma_resume:1; uint32_t reserved_7:25; }; uint32_t val; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_reg.h deleted file mode 100644 index 3077ad0e455a..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_reg.h +++ /dev/null @@ -1,7537 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** DMA2D_OUT_CONF0_CH0_REG register - * Configures the tx direction of channel 0 - */ -#define DMA2D_OUT_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x0) -/** DMA2D_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ -#define DMA2D_OUT_AUTO_WRBACK_CH0 (BIT(0)) -#define DMA2D_OUT_AUTO_WRBACK_CH0_M (DMA2D_OUT_AUTO_WRBACK_CH0_V << DMA2D_OUT_AUTO_WRBACK_CH0_S) -#define DMA2D_OUT_AUTO_WRBACK_CH0_V 0x00000001U -#define DMA2D_OUT_AUTO_WRBACK_CH0_S 0 -/** DMA2D_OUT_EOF_MODE_CH0 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ -#define DMA2D_OUT_EOF_MODE_CH0 (BIT(1)) -#define DMA2D_OUT_EOF_MODE_CH0_M (DMA2D_OUT_EOF_MODE_CH0_V << DMA2D_OUT_EOF_MODE_CH0_S) -#define DMA2D_OUT_EOF_MODE_CH0_V 0x00000001U -#define DMA2D_OUT_EOF_MODE_CH0_S 1 -/** DMA2D_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ -#define DMA2D_OUTDSCR_BURST_EN_CH0 (BIT(2)) -#define DMA2D_OUTDSCR_BURST_EN_CH0_M (DMA2D_OUTDSCR_BURST_EN_CH0_V << DMA2D_OUTDSCR_BURST_EN_CH0_S) -#define DMA2D_OUTDSCR_BURST_EN_CH0_V 0x00000001U -#define DMA2D_OUTDSCR_BURST_EN_CH0_S 2 -/** DMA2D_OUT_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_OUT_ECC_AES_EN_CH0 (BIT(3)) -#define DMA2D_OUT_ECC_AES_EN_CH0_M (DMA2D_OUT_ECC_AES_EN_CH0_V << DMA2D_OUT_ECC_AES_EN_CH0_S) -#define DMA2D_OUT_ECC_AES_EN_CH0_V 0x00000001U -#define DMA2D_OUT_ECC_AES_EN_CH0_S 3 -/** DMA2D_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_OUT_CHECK_OWNER_CH0 (BIT(4)) -#define DMA2D_OUT_CHECK_OWNER_CH0_M (DMA2D_OUT_CHECK_OWNER_CH0_V << DMA2D_OUT_CHECK_OWNER_CH0_S) -#define DMA2D_OUT_CHECK_OWNER_CH0_V 0x00000001U -#define DMA2D_OUT_CHECK_OWNER_CH0_S 4 -/** DMA2D_OUT_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_OUT_LOOP_TEST_CH0 (BIT(5)) -#define DMA2D_OUT_LOOP_TEST_CH0_M (DMA2D_OUT_LOOP_TEST_CH0_V << DMA2D_OUT_LOOP_TEST_CH0_S) -#define DMA2D_OUT_LOOP_TEST_CH0_V 0x00000001U -#define DMA2D_OUT_LOOP_TEST_CH0_S 5 -/** DMA2D_OUT_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_OUT_MEM_BURST_LENGTH_CH0 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_M (DMA2D_OUT_MEM_BURST_LENGTH_CH0_V << DMA2D_OUT_MEM_BURST_LENGTH_CH0_S) -#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_V 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_S 6 -/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0; - * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_M (DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S) -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S 9 -/** DMA2D_OUT_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_OUT_DSCR_PORT_EN_CH0 (BIT(11)) -#define DMA2D_OUT_DSCR_PORT_EN_CH0_M (DMA2D_OUT_DSCR_PORT_EN_CH0_V << DMA2D_OUT_DSCR_PORT_EN_CH0_S) -#define DMA2D_OUT_DSCR_PORT_EN_CH0_V 0x00000001U -#define DMA2D_OUT_DSCR_PORT_EN_CH0_S 11 -/** DMA2D_OUT_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ -#define DMA2D_OUT_PAGE_BOUND_EN_CH0 (BIT(12)) -#define DMA2D_OUT_PAGE_BOUND_EN_CH0_M (DMA2D_OUT_PAGE_BOUND_EN_CH0_V << DMA2D_OUT_PAGE_BOUND_EN_CH0_S) -#define DMA2D_OUT_PAGE_BOUND_EN_CH0_V 0x00000001U -#define DMA2D_OUT_PAGE_BOUND_EN_CH0_S 12 -/** DMA2D_OUT_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_OUT_REORDER_EN_CH0 (BIT(16)) -#define DMA2D_OUT_REORDER_EN_CH0_M (DMA2D_OUT_REORDER_EN_CH0_V << DMA2D_OUT_REORDER_EN_CH0_S) -#define DMA2D_OUT_REORDER_EN_CH0_V 0x00000001U -#define DMA2D_OUT_REORDER_EN_CH0_S 16 -/** DMA2D_OUT_RST_CH0 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ -#define DMA2D_OUT_RST_CH0 (BIT(24)) -#define DMA2D_OUT_RST_CH0_M (DMA2D_OUT_RST_CH0_V << DMA2D_OUT_RST_CH0_S) -#define DMA2D_OUT_RST_CH0_V 0x00000001U -#define DMA2D_OUT_RST_CH0_S 24 -/** DMA2D_OUT_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_OUT_CMD_DISABLE_CH0 (BIT(25)) -#define DMA2D_OUT_CMD_DISABLE_CH0_M (DMA2D_OUT_CMD_DISABLE_CH0_V << DMA2D_OUT_CMD_DISABLE_CH0_S) -#define DMA2D_OUT_CMD_DISABLE_CH0_V 0x00000001U -#define DMA2D_OUT_CMD_DISABLE_CH0_S 25 -/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0 (BIT(26)) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_M (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S 26 - -/** DMA2D_OUT_INT_RAW_CH0_REG register - * Raw interrupt status of TX channel 0 - */ -#define DMA2D_OUT_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x4) -/** DMA2D_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ -#define DMA2D_OUT_DONE_CH0_INT_RAW (BIT(0)) -#define DMA2D_OUT_DONE_CH0_INT_RAW_M (DMA2D_OUT_DONE_CH0_INT_RAW_V << DMA2D_OUT_DONE_CH0_INT_RAW_S) -#define DMA2D_OUT_DONE_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DONE_CH0_INT_RAW_S 0 -/** DMA2D_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ -#define DMA2D_OUT_EOF_CH0_INT_RAW (BIT(1)) -#define DMA2D_OUT_EOF_CH0_INT_RAW_M (DMA2D_OUT_EOF_CH0_INT_RAW_V << DMA2D_OUT_EOF_CH0_INT_RAW_S) -#define DMA2D_OUT_EOF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUT_EOF_CH0_INT_RAW_S 1 -/** DMA2D_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ -#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_M (DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_M (DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_M (DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_M (DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_M (DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_M (DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_M (DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_M (DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_M (DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_M (DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_M (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S 12 - -/** DMA2D_OUT_INT_ENA_CH0_REG register - * Interrupt enable bits of TX channel 0 - */ -#define DMA2D_OUT_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x8) -/** DMA2D_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH0_INT_ENA (BIT(0)) -#define DMA2D_OUT_DONE_CH0_INT_ENA_M (DMA2D_OUT_DONE_CH0_INT_ENA_V << DMA2D_OUT_DONE_CH0_INT_ENA_S) -#define DMA2D_OUT_DONE_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DONE_CH0_INT_ENA_S 0 -/** DMA2D_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH0_INT_ENA (BIT(1)) -#define DMA2D_OUT_EOF_CH0_INT_ENA_M (DMA2D_OUT_EOF_CH0_INT_ENA_V << DMA2D_OUT_EOF_CH0_INT_ENA_S) -#define DMA2D_OUT_EOF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUT_EOF_CH0_INT_ENA_S 1 -/** DMA2D_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_M (DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_M (DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_M (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_M (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_M (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_M (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_M (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_M (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_M (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_M (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_M (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S 12 - -/** DMA2D_OUT_INT_ST_CH0_REG register - * Masked interrupt status of TX channel 0 - */ -#define DMA2D_OUT_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0xc) -/** DMA2D_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH0_INT_ST (BIT(0)) -#define DMA2D_OUT_DONE_CH0_INT_ST_M (DMA2D_OUT_DONE_CH0_INT_ST_V << DMA2D_OUT_DONE_CH0_INT_ST_S) -#define DMA2D_OUT_DONE_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUT_DONE_CH0_INT_ST_S 0 -/** DMA2D_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH0_INT_ST (BIT(1)) -#define DMA2D_OUT_EOF_CH0_INT_ST_M (DMA2D_OUT_EOF_CH0_INT_ST_V << DMA2D_OUT_EOF_CH0_INT_ST_S) -#define DMA2D_OUT_EOF_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUT_EOF_CH0_INT_ST_S 1 -/** DMA2D_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_M (DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_M (DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_M (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_M (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_M (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_M (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_M (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_M (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_M (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_M (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_M (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S 12 - -/** DMA2D_OUT_INT_CLR_CH0_REG register - * Interrupt clear bits of TX channel 0 - */ -#define DMA2D_OUT_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x10) -/** DMA2D_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH0_INT_CLR (BIT(0)) -#define DMA2D_OUT_DONE_CH0_INT_CLR_M (DMA2D_OUT_DONE_CH0_INT_CLR_V << DMA2D_OUT_DONE_CH0_INT_CLR_S) -#define DMA2D_OUT_DONE_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DONE_CH0_INT_CLR_S 0 -/** DMA2D_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH0_INT_CLR (BIT(1)) -#define DMA2D_OUT_EOF_CH0_INT_CLR_M (DMA2D_OUT_EOF_CH0_INT_CLR_V << DMA2D_OUT_EOF_CH0_INT_CLR_S) -#define DMA2D_OUT_EOF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUT_EOF_CH0_INT_CLR_S 1 -/** DMA2D_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_M (DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_M (DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_M (DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_M (DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_M (DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_M (DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_M (DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_M (DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_M (DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_M (DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_M (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S 12 - -/** DMA2D_OUTFIFO_STATUS_CH0_REG register - * Represents the status of the tx fifo of channel 0 - */ -#define DMA2D_OUTFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x14) -/** DMA2D_OUTFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L2_CH0 (BIT(0)) -#define DMA2D_OUTFIFO_FULL_L2_CH0_M (DMA2D_OUTFIFO_FULL_L2_CH0_V << DMA2D_OUTFIFO_FULL_L2_CH0_S) -#define DMA2D_OUTFIFO_FULL_L2_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L2_CH0_S 0 -/** DMA2D_OUTFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L2_CH0 (BIT(1)) -#define DMA2D_OUTFIFO_EMPTY_L2_CH0_M (DMA2D_OUTFIFO_EMPTY_L2_CH0_V << DMA2D_OUTFIFO_EMPTY_L2_CH0_S) -#define DMA2D_OUTFIFO_EMPTY_L2_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L2_CH0_S 1 -/** DMA2D_OUTFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L2_CH0 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH0_M (DMA2D_OUTFIFO_CNT_L2_CH0_V << DMA2D_OUTFIFO_CNT_L2_CH0_S) -#define DMA2D_OUTFIFO_CNT_L2_CH0_V 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH0_S 2 -/** DMA2D_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_1B_CH0 (BIT(7)) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_M (DMA2D_OUT_REMAIN_UNDER_1B_CH0_V << DMA2D_OUT_REMAIN_UNDER_1B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_S 7 -/** DMA2D_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_2B_CH0 (BIT(8)) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_M (DMA2D_OUT_REMAIN_UNDER_2B_CH0_V << DMA2D_OUT_REMAIN_UNDER_2B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_S 8 -/** DMA2D_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_3B_CH0 (BIT(9)) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_M (DMA2D_OUT_REMAIN_UNDER_3B_CH0_V << DMA2D_OUT_REMAIN_UNDER_3B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_S 9 -/** DMA2D_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_4B_CH0 (BIT(10)) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_M (DMA2D_OUT_REMAIN_UNDER_4B_CH0_V << DMA2D_OUT_REMAIN_UNDER_4B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_S 10 -/** DMA2D_OUT_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_5B_CH0 (BIT(11)) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_M (DMA2D_OUT_REMAIN_UNDER_5B_CH0_V << DMA2D_OUT_REMAIN_UNDER_5B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_S 11 -/** DMA2D_OUT_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_6B_CH0 (BIT(12)) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_M (DMA2D_OUT_REMAIN_UNDER_6B_CH0_V << DMA2D_OUT_REMAIN_UNDER_6B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_S 12 -/** DMA2D_OUT_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_7B_CH0 (BIT(13)) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_M (DMA2D_OUT_REMAIN_UNDER_7B_CH0_V << DMA2D_OUT_REMAIN_UNDER_7B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_S 13 -/** DMA2D_OUT_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_8B_CH0 (BIT(14)) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_M (DMA2D_OUT_REMAIN_UNDER_8B_CH0_V << DMA2D_OUT_REMAIN_UNDER_8B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_S 14 -/** DMA2D_OUTFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L1_CH0 (BIT(15)) -#define DMA2D_OUTFIFO_FULL_L1_CH0_M (DMA2D_OUTFIFO_FULL_L1_CH0_V << DMA2D_OUTFIFO_FULL_L1_CH0_S) -#define DMA2D_OUTFIFO_FULL_L1_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L1_CH0_S 15 -/** DMA2D_OUTFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L1_CH0 (BIT(16)) -#define DMA2D_OUTFIFO_EMPTY_L1_CH0_M (DMA2D_OUTFIFO_EMPTY_L1_CH0_V << DMA2D_OUTFIFO_EMPTY_L1_CH0_S) -#define DMA2D_OUTFIFO_EMPTY_L1_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L1_CH0_S 16 -/** DMA2D_OUTFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L1_CH0 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH0_M (DMA2D_OUTFIFO_CNT_L1_CH0_V << DMA2D_OUTFIFO_CNT_L1_CH0_S) -#define DMA2D_OUTFIFO_CNT_L1_CH0_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH0_S 17 -/** DMA2D_OUTFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L3_CH0 (BIT(22)) -#define DMA2D_OUTFIFO_FULL_L3_CH0_M (DMA2D_OUTFIFO_FULL_L3_CH0_V << DMA2D_OUTFIFO_FULL_L3_CH0_S) -#define DMA2D_OUTFIFO_FULL_L3_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L3_CH0_S 22 -/** DMA2D_OUTFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L3_CH0 (BIT(23)) -#define DMA2D_OUTFIFO_EMPTY_L3_CH0_M (DMA2D_OUTFIFO_EMPTY_L3_CH0_V << DMA2D_OUTFIFO_EMPTY_L3_CH0_S) -#define DMA2D_OUTFIFO_EMPTY_L3_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L3_CH0_S 23 -/** DMA2D_OUTFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L3_CH0 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH0_M (DMA2D_OUTFIFO_CNT_L3_CH0_V << DMA2D_OUTFIFO_CNT_L3_CH0_S) -#define DMA2D_OUTFIFO_CNT_L3_CH0_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH0_S 24 - -/** DMA2D_OUT_PUSH_CH0_REG register - * Configures the tx fifo of channel 0 - */ -#define DMA2D_OUT_PUSH_CH0_REG (DR_REG_DMA2D_BASE + 0x18) -/** DMA2D_OUTFIFO_WDATA_CH0 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_WDATA_CH0 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH0_M (DMA2D_OUTFIFO_WDATA_CH0_V << DMA2D_OUTFIFO_WDATA_CH0_S) -#define DMA2D_OUTFIFO_WDATA_CH0_V 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH0_S 0 -/** DMA2D_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_PUSH_CH0 (BIT(10)) -#define DMA2D_OUTFIFO_PUSH_CH0_M (DMA2D_OUTFIFO_PUSH_CH0_V << DMA2D_OUTFIFO_PUSH_CH0_S) -#define DMA2D_OUTFIFO_PUSH_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_PUSH_CH0_S 10 - -/** DMA2D_OUT_LINK_CONF_CH0_REG register - * Configures the tx descriptor operations of channel 0 - */ -#define DMA2D_OUT_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x1c) -/** DMA2D_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_STOP_CH0 (BIT(20)) -#define DMA2D_OUTLINK_STOP_CH0_M (DMA2D_OUTLINK_STOP_CH0_V << DMA2D_OUTLINK_STOP_CH0_S) -#define DMA2D_OUTLINK_STOP_CH0_V 0x00000001U -#define DMA2D_OUTLINK_STOP_CH0_S 20 -/** DMA2D_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_START_CH0 (BIT(21)) -#define DMA2D_OUTLINK_START_CH0_M (DMA2D_OUTLINK_START_CH0_V << DMA2D_OUTLINK_START_CH0_S) -#define DMA2D_OUTLINK_START_CH0_V 0x00000001U -#define DMA2D_OUTLINK_START_CH0_S 21 -/** DMA2D_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ -#define DMA2D_OUTLINK_RESTART_CH0 (BIT(22)) -#define DMA2D_OUTLINK_RESTART_CH0_M (DMA2D_OUTLINK_RESTART_CH0_V << DMA2D_OUTLINK_RESTART_CH0_S) -#define DMA2D_OUTLINK_RESTART_CH0_V 0x00000001U -#define DMA2D_OUTLINK_RESTART_CH0_S 22 -/** DMA2D_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ -#define DMA2D_OUTLINK_PARK_CH0 (BIT(23)) -#define DMA2D_OUTLINK_PARK_CH0_M (DMA2D_OUTLINK_PARK_CH0_V << DMA2D_OUTLINK_PARK_CH0_S) -#define DMA2D_OUTLINK_PARK_CH0_V 0x00000001U -#define DMA2D_OUTLINK_PARK_CH0_S 23 - -/** DMA2D_OUT_LINK_ADDR_CH0_REG register - * Configures the tx descriptor address of channel 0 - */ -#define DMA2D_OUT_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x20) -/** DMA2D_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ -#define DMA2D_OUTLINK_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH0_M (DMA2D_OUTLINK_ADDR_CH0_V << DMA2D_OUTLINK_ADDR_CH0_S) -#define DMA2D_OUTLINK_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH0_S 0 - -/** DMA2D_OUT_STATE_CH0_REG register - * Represents the working status of the tx descriptor of channel 0 - */ -#define DMA2D_OUT_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x24) -/** DMA2D_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ -#define DMA2D_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH0_M (DMA2D_OUTLINK_DSCR_ADDR_CH0_V << DMA2D_OUTLINK_DSCR_ADDR_CH0_S) -#define DMA2D_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH0_S 0 -/** DMA2D_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ -#define DMA2D_OUT_DSCR_STATE_CH0 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH0_M (DMA2D_OUT_DSCR_STATE_CH0_V << DMA2D_OUT_DSCR_STATE_CH0_S) -#define DMA2D_OUT_DSCR_STATE_CH0_V 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH0_S 18 -/** DMA2D_OUT_STATE_CH0 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ -#define DMA2D_OUT_STATE_CH0 0x0000000FU -#define DMA2D_OUT_STATE_CH0_M (DMA2D_OUT_STATE_CH0_V << DMA2D_OUT_STATE_CH0_S) -#define DMA2D_OUT_STATE_CH0_V 0x0000000FU -#define DMA2D_OUT_STATE_CH0_S 20 -/** DMA2D_OUT_RESET_AVAIL_CH0 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_OUT_RESET_AVAIL_CH0 (BIT(24)) -#define DMA2D_OUT_RESET_AVAIL_CH0_M (DMA2D_OUT_RESET_AVAIL_CH0_V << DMA2D_OUT_RESET_AVAIL_CH0_S) -#define DMA2D_OUT_RESET_AVAIL_CH0_V 0x00000001U -#define DMA2D_OUT_RESET_AVAIL_CH0_S 24 - -/** DMA2D_OUT_EOF_DES_ADDR_CH0_REG register - * Represents the address associated with the outlink descriptor of channel 0 - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x28) -/** DMA2D_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH0_M (DMA2D_OUT_EOF_DES_ADDR_CH0_V << DMA2D_OUT_EOF_DES_ADDR_CH0_S) -#define DMA2D_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH0_S 0 - -/** DMA2D_OUT_DSCR_CH0_REG register - * Represents the address associated with the outlink descriptor of channel 0 - */ -#define DMA2D_OUT_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x2c) -/** DMA2D_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ -#define DMA2D_OUTLINK_DSCR_CH0 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH0_M (DMA2D_OUTLINK_DSCR_CH0_V << DMA2D_OUTLINK_DSCR_CH0_S) -#define DMA2D_OUTLINK_DSCR_CH0_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH0_S 0 - -/** DMA2D_OUT_DSCR_BF0_CH0_REG register - * Represents the address associated with the outlink descriptor of channel 0 - */ -#define DMA2D_OUT_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x30) -/** DMA2D_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ -#define DMA2D_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH0_M (DMA2D_OUTLINK_DSCR_BF0_CH0_V << DMA2D_OUTLINK_DSCR_BF0_CH0_S) -#define DMA2D_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH0_S 0 - -/** DMA2D_OUT_DSCR_BF1_CH0_REG register - * Represents the address associated with the outlink descriptor of channel 0 - */ -#define DMA2D_OUT_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x34) -/** DMA2D_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ -#define DMA2D_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH0_M (DMA2D_OUTLINK_DSCR_BF1_CH0_V << DMA2D_OUTLINK_DSCR_BF1_CH0_S) -#define DMA2D_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH0_S 0 - -/** DMA2D_OUT_PERI_SEL_CH0_REG register - * Configures the tx peripheral of channel 0 - */ -#define DMA2D_OUT_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x38) -/** DMA2D_OUT_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Tx channel 0: jpeg 1: - * display-1 2: display-2 3: display-3 7: no choose - */ -#define DMA2D_OUT_PERI_SEL_CH0 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH0_M (DMA2D_OUT_PERI_SEL_CH0_V << DMA2D_OUT_PERI_SEL_CH0_S) -#define DMA2D_OUT_PERI_SEL_CH0_V 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH0_S 0 - -/** DMA2D_OUT_ARB_CH0_REG register - * Configures the tx arbiter of channel 0 - */ -#define DMA2D_OUT_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x3c) -/** DMA2D_OUT_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_OUT_ARB_TOKEN_NUM_CH0 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_M (DMA2D_OUT_ARB_TOKEN_NUM_CH0_V << DMA2D_OUT_ARB_TOKEN_NUM_CH0_S) -#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_V 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_CH0 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH0_M (DMA2D_OUT_ARB_PRIORITY_CH0_V << DMA2D_OUT_ARB_PRIORITY_CH0_S) -#define DMA2D_OUT_ARB_PRIORITY_CH0_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH0_S 4 -/** DMA2D_OUT_ARB_PRIORITY_H_CH0 : R/W; bitpos: [7:6]; default: 0; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_H_CH0 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH0_M (DMA2D_OUT_ARB_PRIORITY_H_CH0_V << DMA2D_OUT_ARB_PRIORITY_H_CH0_S) -#define DMA2D_OUT_ARB_PRIORITY_H_CH0_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH0_S 6 - -/** DMA2D_OUT_RO_STATUS_CH0_REG register - * Represents the status of the tx reorder module of channel 0 - */ -#define DMA2D_OUT_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x40) -/** DMA2D_OUTFIFO_RO_CNT_CH0 : RO; bitpos: [5:0]; default: 0; - * The register stores the byte number of the data in color convert Tx FIFO for - * channel 0. - */ -#define DMA2D_OUTFIFO_RO_CNT_CH0 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH0_M (DMA2D_OUTFIFO_RO_CNT_CH0_V << DMA2D_OUTFIFO_RO_CNT_CH0_S) -#define DMA2D_OUTFIFO_RO_CNT_CH0_V 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH0_S 0 -/** DMA2D_OUT_RO_WR_STATE_CH0 : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_OUT_RO_WR_STATE_CH0 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH0_M (DMA2D_OUT_RO_WR_STATE_CH0_V << DMA2D_OUT_RO_WR_STATE_CH0_S) -#define DMA2D_OUT_RO_WR_STATE_CH0_V 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH0_S 6 -/** DMA2D_OUT_RO_RD_STATE_CH0 : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_OUT_RO_RD_STATE_CH0 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH0_M (DMA2D_OUT_RO_RD_STATE_CH0_V << DMA2D_OUT_RO_RD_STATE_CH0_S) -#define DMA2D_OUT_RO_RD_STATE_CH0_V 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH0_S 8 -/** DMA2D_OUT_PIXEL_BYTE_CH0 : RO; bitpos: [13:10]; default: 0; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_OUT_PIXEL_BYTE_CH0 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH0_M (DMA2D_OUT_PIXEL_BYTE_CH0_V << DMA2D_OUT_PIXEL_BYTE_CH0_S) -#define DMA2D_OUT_PIXEL_BYTE_CH0_V 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH0_S 10 -/** DMA2D_OUT_BURST_BLOCK_NUM_CH0 : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ -#define DMA2D_OUT_BURST_BLOCK_NUM_CH0 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_M (DMA2D_OUT_BURST_BLOCK_NUM_CH0_V << DMA2D_OUT_BURST_BLOCK_NUM_CH0_S) -#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_V 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_S 14 - -/** DMA2D_OUT_RO_PD_CONF_CH0_REG register - * Configures the tx reorder memory of channel 0 - */ -#define DMA2D_OUT_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x44) -/** DMA2D_OUT_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ -#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0 (BIT(4)) -#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_M (DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S) -#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V 0x00000001U -#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S 4 -/** DMA2D_OUT_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ -#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0 (BIT(5)) -#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_M (DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S) -#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V 0x00000001U -#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S 5 -/** DMA2D_OUT_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ -#define DMA2D_OUT_RO_RAM_CLK_FO_CH0 (BIT(6)) -#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_M (DMA2D_OUT_RO_RAM_CLK_FO_CH0_V << DMA2D_OUT_RO_RAM_CLK_FO_CH0_S) -#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_V 0x00000001U -#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_S 6 - -/** DMA2D_OUT_COLOR_CONVERT_CH0_REG register - * Configures the tx color convert of channel 0 - */ -#define DMA2D_OUT_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x48) -/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * YUV444 to YUV422 2: output directly - */ -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_M (DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S) -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S 0 -/** DMA2D_OUT_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0 (BIT(2)) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_M (DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V 0x00000001U -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S 2 -/** DMA2D_OUT_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: RGB565 to RGB888 1: - * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: - * disable color space convert - */ -#define DMA2D_OUT_COLOR_INPUT_SEL_CH0 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_M (DMA2D_OUT_COLOR_INPUT_SEL_CH0_V << DMA2D_OUT_COLOR_INPUT_SEL_CH0_S) -#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_V 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_S 3 - -/** DMA2D_OUT_SCRAMBLE_CH0_REG register - * Configures the tx scramble of channel 0 - */ -#define DMA2D_OUT_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x4c) -/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_M (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S) -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM0_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x50) -/** DMA2D_OUT_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H0_CH0 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH0_M (DMA2D_OUT_COLOR_PARAM_H0_CH0_V << DMA2D_OUT_COLOR_PARAM_H0_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_H0_CH0_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM1_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x54) -/** DMA2D_OUT_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H1_CH0 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH0_M (DMA2D_OUT_COLOR_PARAM_H1_CH0_V << DMA2D_OUT_COLOR_PARAM_H1_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_H1_CH0_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM2_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x58) -/** DMA2D_OUT_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M0_CH0 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH0_M (DMA2D_OUT_COLOR_PARAM_M0_CH0_V << DMA2D_OUT_COLOR_PARAM_M0_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_M0_CH0_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM3_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x5c) -/** DMA2D_OUT_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M1_CH0 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH0_M (DMA2D_OUT_COLOR_PARAM_M1_CH0_V << DMA2D_OUT_COLOR_PARAM_M1_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_M1_CH0_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM4_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x60) -/** DMA2D_OUT_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L0_CH0 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH0_M (DMA2D_OUT_COLOR_PARAM_L0_CH0_V << DMA2D_OUT_COLOR_PARAM_L0_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_L0_CH0_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM5_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x64) -/** DMA2D_OUT_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L1_CH0 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH0_M (DMA2D_OUT_COLOR_PARAM_L1_CH0_V << DMA2D_OUT_COLOR_PARAM_L1_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_L1_CH0_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH0_S 0 - -/** DMA2D_OUT_ETM_CONF_CH0_REG register - * Configures the tx etm of channel 0 - */ -#define DMA2D_OUT_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x68) -/** DMA2D_OUT_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_EN_CH0 (BIT(0)) -#define DMA2D_OUT_ETM_EN_CH0_M (DMA2D_OUT_ETM_EN_CH0_V << DMA2D_OUT_ETM_EN_CH0_S) -#define DMA2D_OUT_ETM_EN_CH0_V 0x00000001U -#define DMA2D_OUT_ETM_EN_CH0_S 0 -/** DMA2D_OUT_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_LOOP_EN_CH0 (BIT(1)) -#define DMA2D_OUT_ETM_LOOP_EN_CH0_M (DMA2D_OUT_ETM_LOOP_EN_CH0_V << DMA2D_OUT_ETM_LOOP_EN_CH0_S) -#define DMA2D_OUT_ETM_LOOP_EN_CH0_V 0x00000001U -#define DMA2D_OUT_ETM_LOOP_EN_CH0_S 1 -/** DMA2D_OUT_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_OUT_DSCR_TASK_MAK_CH0 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH0_M (DMA2D_OUT_DSCR_TASK_MAK_CH0_V << DMA2D_OUT_DSCR_TASK_MAK_CH0_S) -#define DMA2D_OUT_DSCR_TASK_MAK_CH0_V 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH0_S 2 - -/** DMA2D_OUT_DSCR_PORT_BLK_CH0_REG register - * Configures the tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_CH0_REG (DR_REG_DMA2D_BASE + 0x6c) -/** DMA2D_OUT_DSCR_PORT_BLK_H_CH0 : R/W; bitpos: [13:0]; default: 18; - * Set the vertical height of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_M (DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S) -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S 0 -/** DMA2D_OUT_DSCR_PORT_BLK_V_CH0 : R/W; bitpos: [27:14]; default: 18; - * Set the horizontal width of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_M (DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S) -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S 14 - -/** DMA2D_OUT_CONF0_CH1_REG register - * Configures the tx direction of channel 1 - */ -#define DMA2D_OUT_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x100) -/** DMA2D_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ -#define DMA2D_OUT_AUTO_WRBACK_CH1 (BIT(0)) -#define DMA2D_OUT_AUTO_WRBACK_CH1_M (DMA2D_OUT_AUTO_WRBACK_CH1_V << DMA2D_OUT_AUTO_WRBACK_CH1_S) -#define DMA2D_OUT_AUTO_WRBACK_CH1_V 0x00000001U -#define DMA2D_OUT_AUTO_WRBACK_CH1_S 0 -/** DMA2D_OUT_EOF_MODE_CH1 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ -#define DMA2D_OUT_EOF_MODE_CH1 (BIT(1)) -#define DMA2D_OUT_EOF_MODE_CH1_M (DMA2D_OUT_EOF_MODE_CH1_V << DMA2D_OUT_EOF_MODE_CH1_S) -#define DMA2D_OUT_EOF_MODE_CH1_V 0x00000001U -#define DMA2D_OUT_EOF_MODE_CH1_S 1 -/** DMA2D_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ -#define DMA2D_OUTDSCR_BURST_EN_CH1 (BIT(2)) -#define DMA2D_OUTDSCR_BURST_EN_CH1_M (DMA2D_OUTDSCR_BURST_EN_CH1_V << DMA2D_OUTDSCR_BURST_EN_CH1_S) -#define DMA2D_OUTDSCR_BURST_EN_CH1_V 0x00000001U -#define DMA2D_OUTDSCR_BURST_EN_CH1_S 2 -/** DMA2D_OUT_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_OUT_ECC_AES_EN_CH1 (BIT(3)) -#define DMA2D_OUT_ECC_AES_EN_CH1_M (DMA2D_OUT_ECC_AES_EN_CH1_V << DMA2D_OUT_ECC_AES_EN_CH1_S) -#define DMA2D_OUT_ECC_AES_EN_CH1_V 0x00000001U -#define DMA2D_OUT_ECC_AES_EN_CH1_S 3 -/** DMA2D_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_OUT_CHECK_OWNER_CH1 (BIT(4)) -#define DMA2D_OUT_CHECK_OWNER_CH1_M (DMA2D_OUT_CHECK_OWNER_CH1_V << DMA2D_OUT_CHECK_OWNER_CH1_S) -#define DMA2D_OUT_CHECK_OWNER_CH1_V 0x00000001U -#define DMA2D_OUT_CHECK_OWNER_CH1_S 4 -/** DMA2D_OUT_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_OUT_LOOP_TEST_CH1 (BIT(5)) -#define DMA2D_OUT_LOOP_TEST_CH1_M (DMA2D_OUT_LOOP_TEST_CH1_V << DMA2D_OUT_LOOP_TEST_CH1_S) -#define DMA2D_OUT_LOOP_TEST_CH1_V 0x00000001U -#define DMA2D_OUT_LOOP_TEST_CH1_S 5 -/** DMA2D_OUT_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_OUT_MEM_BURST_LENGTH_CH1 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_M (DMA2D_OUT_MEM_BURST_LENGTH_CH1_V << DMA2D_OUT_MEM_BURST_LENGTH_CH1_S) -#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_V 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_S 6 -/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0; - * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_M (DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S) -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S 9 -/** DMA2D_OUT_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_OUT_DSCR_PORT_EN_CH1 (BIT(11)) -#define DMA2D_OUT_DSCR_PORT_EN_CH1_M (DMA2D_OUT_DSCR_PORT_EN_CH1_V << DMA2D_OUT_DSCR_PORT_EN_CH1_S) -#define DMA2D_OUT_DSCR_PORT_EN_CH1_V 0x00000001U -#define DMA2D_OUT_DSCR_PORT_EN_CH1_S 11 -/** DMA2D_OUT_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ -#define DMA2D_OUT_PAGE_BOUND_EN_CH1 (BIT(12)) -#define DMA2D_OUT_PAGE_BOUND_EN_CH1_M (DMA2D_OUT_PAGE_BOUND_EN_CH1_V << DMA2D_OUT_PAGE_BOUND_EN_CH1_S) -#define DMA2D_OUT_PAGE_BOUND_EN_CH1_V 0x00000001U -#define DMA2D_OUT_PAGE_BOUND_EN_CH1_S 12 -/** DMA2D_OUT_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_OUT_REORDER_EN_CH1 (BIT(16)) -#define DMA2D_OUT_REORDER_EN_CH1_M (DMA2D_OUT_REORDER_EN_CH1_V << DMA2D_OUT_REORDER_EN_CH1_S) -#define DMA2D_OUT_REORDER_EN_CH1_V 0x00000001U -#define DMA2D_OUT_REORDER_EN_CH1_S 16 -/** DMA2D_OUT_RST_CH1 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ -#define DMA2D_OUT_RST_CH1 (BIT(24)) -#define DMA2D_OUT_RST_CH1_M (DMA2D_OUT_RST_CH1_V << DMA2D_OUT_RST_CH1_S) -#define DMA2D_OUT_RST_CH1_V 0x00000001U -#define DMA2D_OUT_RST_CH1_S 24 -/** DMA2D_OUT_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_OUT_CMD_DISABLE_CH1 (BIT(25)) -#define DMA2D_OUT_CMD_DISABLE_CH1_M (DMA2D_OUT_CMD_DISABLE_CH1_V << DMA2D_OUT_CMD_DISABLE_CH1_S) -#define DMA2D_OUT_CMD_DISABLE_CH1_V 0x00000001U -#define DMA2D_OUT_CMD_DISABLE_CH1_S 25 -/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1 (BIT(26)) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_M (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S 26 - -/** DMA2D_OUT_INT_RAW_CH1_REG register - * Raw interrupt status of TX channel 1 - */ -#define DMA2D_OUT_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x104) -/** DMA2D_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ -#define DMA2D_OUT_DONE_CH1_INT_RAW (BIT(0)) -#define DMA2D_OUT_DONE_CH1_INT_RAW_M (DMA2D_OUT_DONE_CH1_INT_RAW_V << DMA2D_OUT_DONE_CH1_INT_RAW_S) -#define DMA2D_OUT_DONE_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DONE_CH1_INT_RAW_S 0 -/** DMA2D_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ -#define DMA2D_OUT_EOF_CH1_INT_RAW (BIT(1)) -#define DMA2D_OUT_EOF_CH1_INT_RAW_M (DMA2D_OUT_EOF_CH1_INT_RAW_V << DMA2D_OUT_EOF_CH1_INT_RAW_S) -#define DMA2D_OUT_EOF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUT_EOF_CH1_INT_RAW_S 1 -/** DMA2D_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ -#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_M (DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_M (DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_M (DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_M (DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_M (DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_M (DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_M (DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_M (DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_M (DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_M (DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_M (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S 12 - -/** DMA2D_OUT_INT_ENA_CH1_REG register - * Interrupt enable bits of TX channel 1 - */ -#define DMA2D_OUT_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x108) -/** DMA2D_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH1_INT_ENA (BIT(0)) -#define DMA2D_OUT_DONE_CH1_INT_ENA_M (DMA2D_OUT_DONE_CH1_INT_ENA_V << DMA2D_OUT_DONE_CH1_INT_ENA_S) -#define DMA2D_OUT_DONE_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DONE_CH1_INT_ENA_S 0 -/** DMA2D_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH1_INT_ENA (BIT(1)) -#define DMA2D_OUT_EOF_CH1_INT_ENA_M (DMA2D_OUT_EOF_CH1_INT_ENA_V << DMA2D_OUT_EOF_CH1_INT_ENA_S) -#define DMA2D_OUT_EOF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUT_EOF_CH1_INT_ENA_S 1 -/** DMA2D_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_M (DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_M (DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_M (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_M (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_M (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_M (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_M (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_M (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_M (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_M (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_M (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S 12 - -/** DMA2D_OUT_INT_ST_CH1_REG register - * Masked interrupt status of TX channel 1 - */ -#define DMA2D_OUT_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x10c) -/** DMA2D_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH1_INT_ST (BIT(0)) -#define DMA2D_OUT_DONE_CH1_INT_ST_M (DMA2D_OUT_DONE_CH1_INT_ST_V << DMA2D_OUT_DONE_CH1_INT_ST_S) -#define DMA2D_OUT_DONE_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUT_DONE_CH1_INT_ST_S 0 -/** DMA2D_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH1_INT_ST (BIT(1)) -#define DMA2D_OUT_EOF_CH1_INT_ST_M (DMA2D_OUT_EOF_CH1_INT_ST_V << DMA2D_OUT_EOF_CH1_INT_ST_S) -#define DMA2D_OUT_EOF_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUT_EOF_CH1_INT_ST_S 1 -/** DMA2D_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_M (DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_M (DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_M (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_M (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_M (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_M (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_M (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_M (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_M (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_M (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_M (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S 12 - -/** DMA2D_OUT_INT_CLR_CH1_REG register - * Interrupt clear bits of TX channel 1 - */ -#define DMA2D_OUT_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x110) -/** DMA2D_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH1_INT_CLR (BIT(0)) -#define DMA2D_OUT_DONE_CH1_INT_CLR_M (DMA2D_OUT_DONE_CH1_INT_CLR_V << DMA2D_OUT_DONE_CH1_INT_CLR_S) -#define DMA2D_OUT_DONE_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DONE_CH1_INT_CLR_S 0 -/** DMA2D_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH1_INT_CLR (BIT(1)) -#define DMA2D_OUT_EOF_CH1_INT_CLR_M (DMA2D_OUT_EOF_CH1_INT_CLR_V << DMA2D_OUT_EOF_CH1_INT_CLR_S) -#define DMA2D_OUT_EOF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUT_EOF_CH1_INT_CLR_S 1 -/** DMA2D_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_M (DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_M (DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_M (DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_M (DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_M (DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_M (DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_M (DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_M (DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_M (DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_M (DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_M (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S 12 - -/** DMA2D_OUTFIFO_STATUS_CH1_REG register - * Represents the status of the tx fifo of channel 1 - */ -#define DMA2D_OUTFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x114) -/** DMA2D_OUTFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L2_CH1 (BIT(0)) -#define DMA2D_OUTFIFO_FULL_L2_CH1_M (DMA2D_OUTFIFO_FULL_L2_CH1_V << DMA2D_OUTFIFO_FULL_L2_CH1_S) -#define DMA2D_OUTFIFO_FULL_L2_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L2_CH1_S 0 -/** DMA2D_OUTFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L2_CH1 (BIT(1)) -#define DMA2D_OUTFIFO_EMPTY_L2_CH1_M (DMA2D_OUTFIFO_EMPTY_L2_CH1_V << DMA2D_OUTFIFO_EMPTY_L2_CH1_S) -#define DMA2D_OUTFIFO_EMPTY_L2_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L2_CH1_S 1 -/** DMA2D_OUTFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L2_CH1 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH1_M (DMA2D_OUTFIFO_CNT_L2_CH1_V << DMA2D_OUTFIFO_CNT_L2_CH1_S) -#define DMA2D_OUTFIFO_CNT_L2_CH1_V 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH1_S 2 -/** DMA2D_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_1B_CH1 (BIT(7)) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_M (DMA2D_OUT_REMAIN_UNDER_1B_CH1_V << DMA2D_OUT_REMAIN_UNDER_1B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_S 7 -/** DMA2D_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_2B_CH1 (BIT(8)) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_M (DMA2D_OUT_REMAIN_UNDER_2B_CH1_V << DMA2D_OUT_REMAIN_UNDER_2B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_S 8 -/** DMA2D_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_3B_CH1 (BIT(9)) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_M (DMA2D_OUT_REMAIN_UNDER_3B_CH1_V << DMA2D_OUT_REMAIN_UNDER_3B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_S 9 -/** DMA2D_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_4B_CH1 (BIT(10)) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_M (DMA2D_OUT_REMAIN_UNDER_4B_CH1_V << DMA2D_OUT_REMAIN_UNDER_4B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_S 10 -/** DMA2D_OUT_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_5B_CH1 (BIT(11)) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_M (DMA2D_OUT_REMAIN_UNDER_5B_CH1_V << DMA2D_OUT_REMAIN_UNDER_5B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_S 11 -/** DMA2D_OUT_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_6B_CH1 (BIT(12)) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_M (DMA2D_OUT_REMAIN_UNDER_6B_CH1_V << DMA2D_OUT_REMAIN_UNDER_6B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_S 12 -/** DMA2D_OUT_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_7B_CH1 (BIT(13)) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_M (DMA2D_OUT_REMAIN_UNDER_7B_CH1_V << DMA2D_OUT_REMAIN_UNDER_7B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_S 13 -/** DMA2D_OUT_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_8B_CH1 (BIT(14)) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_M (DMA2D_OUT_REMAIN_UNDER_8B_CH1_V << DMA2D_OUT_REMAIN_UNDER_8B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_S 14 -/** DMA2D_OUTFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L1_CH1 (BIT(15)) -#define DMA2D_OUTFIFO_FULL_L1_CH1_M (DMA2D_OUTFIFO_FULL_L1_CH1_V << DMA2D_OUTFIFO_FULL_L1_CH1_S) -#define DMA2D_OUTFIFO_FULL_L1_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L1_CH1_S 15 -/** DMA2D_OUTFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L1_CH1 (BIT(16)) -#define DMA2D_OUTFIFO_EMPTY_L1_CH1_M (DMA2D_OUTFIFO_EMPTY_L1_CH1_V << DMA2D_OUTFIFO_EMPTY_L1_CH1_S) -#define DMA2D_OUTFIFO_EMPTY_L1_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L1_CH1_S 16 -/** DMA2D_OUTFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L1_CH1 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH1_M (DMA2D_OUTFIFO_CNT_L1_CH1_V << DMA2D_OUTFIFO_CNT_L1_CH1_S) -#define DMA2D_OUTFIFO_CNT_L1_CH1_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH1_S 17 -/** DMA2D_OUTFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L3_CH1 (BIT(22)) -#define DMA2D_OUTFIFO_FULL_L3_CH1_M (DMA2D_OUTFIFO_FULL_L3_CH1_V << DMA2D_OUTFIFO_FULL_L3_CH1_S) -#define DMA2D_OUTFIFO_FULL_L3_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L3_CH1_S 22 -/** DMA2D_OUTFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L3_CH1 (BIT(23)) -#define DMA2D_OUTFIFO_EMPTY_L3_CH1_M (DMA2D_OUTFIFO_EMPTY_L3_CH1_V << DMA2D_OUTFIFO_EMPTY_L3_CH1_S) -#define DMA2D_OUTFIFO_EMPTY_L3_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L3_CH1_S 23 -/** DMA2D_OUTFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L3_CH1 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH1_M (DMA2D_OUTFIFO_CNT_L3_CH1_V << DMA2D_OUTFIFO_CNT_L3_CH1_S) -#define DMA2D_OUTFIFO_CNT_L3_CH1_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH1_S 24 - -/** DMA2D_OUT_PUSH_CH1_REG register - * Configures the tx fifo of channel 1 - */ -#define DMA2D_OUT_PUSH_CH1_REG (DR_REG_DMA2D_BASE + 0x118) -/** DMA2D_OUTFIFO_WDATA_CH1 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_WDATA_CH1 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH1_M (DMA2D_OUTFIFO_WDATA_CH1_V << DMA2D_OUTFIFO_WDATA_CH1_S) -#define DMA2D_OUTFIFO_WDATA_CH1_V 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH1_S 0 -/** DMA2D_OUTFIFO_PUSH_CH1 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_PUSH_CH1 (BIT(10)) -#define DMA2D_OUTFIFO_PUSH_CH1_M (DMA2D_OUTFIFO_PUSH_CH1_V << DMA2D_OUTFIFO_PUSH_CH1_S) -#define DMA2D_OUTFIFO_PUSH_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_PUSH_CH1_S 10 - -/** DMA2D_OUT_LINK_CONF_CH1_REG register - * Configures the tx descriptor operations of channel 1 - */ -#define DMA2D_OUT_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x11c) -/** DMA2D_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_STOP_CH1 (BIT(20)) -#define DMA2D_OUTLINK_STOP_CH1_M (DMA2D_OUTLINK_STOP_CH1_V << DMA2D_OUTLINK_STOP_CH1_S) -#define DMA2D_OUTLINK_STOP_CH1_V 0x00000001U -#define DMA2D_OUTLINK_STOP_CH1_S 20 -/** DMA2D_OUTLINK_START_CH1 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_START_CH1 (BIT(21)) -#define DMA2D_OUTLINK_START_CH1_M (DMA2D_OUTLINK_START_CH1_V << DMA2D_OUTLINK_START_CH1_S) -#define DMA2D_OUTLINK_START_CH1_V 0x00000001U -#define DMA2D_OUTLINK_START_CH1_S 21 -/** DMA2D_OUTLINK_RESTART_CH1 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ -#define DMA2D_OUTLINK_RESTART_CH1 (BIT(22)) -#define DMA2D_OUTLINK_RESTART_CH1_M (DMA2D_OUTLINK_RESTART_CH1_V << DMA2D_OUTLINK_RESTART_CH1_S) -#define DMA2D_OUTLINK_RESTART_CH1_V 0x00000001U -#define DMA2D_OUTLINK_RESTART_CH1_S 22 -/** DMA2D_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ -#define DMA2D_OUTLINK_PARK_CH1 (BIT(23)) -#define DMA2D_OUTLINK_PARK_CH1_M (DMA2D_OUTLINK_PARK_CH1_V << DMA2D_OUTLINK_PARK_CH1_S) -#define DMA2D_OUTLINK_PARK_CH1_V 0x00000001U -#define DMA2D_OUTLINK_PARK_CH1_S 23 - -/** DMA2D_OUT_LINK_ADDR_CH1_REG register - * Configures the tx descriptor address of channel 1 - */ -#define DMA2D_OUT_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x120) -/** DMA2D_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ -#define DMA2D_OUTLINK_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH1_M (DMA2D_OUTLINK_ADDR_CH1_V << DMA2D_OUTLINK_ADDR_CH1_S) -#define DMA2D_OUTLINK_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH1_S 0 - -/** DMA2D_OUT_STATE_CH1_REG register - * Represents the working status of the tx descriptor of channel 1 - */ -#define DMA2D_OUT_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x124) -/** DMA2D_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ -#define DMA2D_OUTLINK_DSCR_ADDR_CH1 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH1_M (DMA2D_OUTLINK_DSCR_ADDR_CH1_V << DMA2D_OUTLINK_DSCR_ADDR_CH1_S) -#define DMA2D_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH1_S 0 -/** DMA2D_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ -#define DMA2D_OUT_DSCR_STATE_CH1 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH1_M (DMA2D_OUT_DSCR_STATE_CH1_V << DMA2D_OUT_DSCR_STATE_CH1_S) -#define DMA2D_OUT_DSCR_STATE_CH1_V 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH1_S 18 -/** DMA2D_OUT_STATE_CH1 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ -#define DMA2D_OUT_STATE_CH1 0x0000000FU -#define DMA2D_OUT_STATE_CH1_M (DMA2D_OUT_STATE_CH1_V << DMA2D_OUT_STATE_CH1_S) -#define DMA2D_OUT_STATE_CH1_V 0x0000000FU -#define DMA2D_OUT_STATE_CH1_S 20 -/** DMA2D_OUT_RESET_AVAIL_CH1 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_OUT_RESET_AVAIL_CH1 (BIT(24)) -#define DMA2D_OUT_RESET_AVAIL_CH1_M (DMA2D_OUT_RESET_AVAIL_CH1_V << DMA2D_OUT_RESET_AVAIL_CH1_S) -#define DMA2D_OUT_RESET_AVAIL_CH1_V 0x00000001U -#define DMA2D_OUT_RESET_AVAIL_CH1_S 24 - -/** DMA2D_OUT_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 1 - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x128) -/** DMA2D_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH1_M (DMA2D_OUT_EOF_DES_ADDR_CH1_V << DMA2D_OUT_EOF_DES_ADDR_CH1_S) -#define DMA2D_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH1_S 0 - -/** DMA2D_OUT_DSCR_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 1 - */ -#define DMA2D_OUT_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x12c) -/** DMA2D_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ -#define DMA2D_OUTLINK_DSCR_CH1 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH1_M (DMA2D_OUTLINK_DSCR_CH1_V << DMA2D_OUTLINK_DSCR_CH1_S) -#define DMA2D_OUTLINK_DSCR_CH1_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH1_S 0 - -/** DMA2D_OUT_DSCR_BF0_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 1 - */ -#define DMA2D_OUT_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x130) -/** DMA2D_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ -#define DMA2D_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH1_M (DMA2D_OUTLINK_DSCR_BF0_CH1_V << DMA2D_OUTLINK_DSCR_BF0_CH1_S) -#define DMA2D_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH1_S 0 - -/** DMA2D_OUT_DSCR_BF1_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 1 - */ -#define DMA2D_OUT_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x134) -/** DMA2D_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ -#define DMA2D_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH1_M (DMA2D_OUTLINK_DSCR_BF1_CH1_V << DMA2D_OUTLINK_DSCR_BF1_CH1_S) -#define DMA2D_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH1_S 0 - -/** DMA2D_OUT_PERI_SEL_CH1_REG register - * Configures the tx peripheral of channel 1 - */ -#define DMA2D_OUT_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x138) -/** DMA2D_OUT_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Tx channel 0: jpeg 1: - * display-1 2: display-2 3: display-3 7: no choose - */ -#define DMA2D_OUT_PERI_SEL_CH1 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH1_M (DMA2D_OUT_PERI_SEL_CH1_V << DMA2D_OUT_PERI_SEL_CH1_S) -#define DMA2D_OUT_PERI_SEL_CH1_V 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH1_S 0 - -/** DMA2D_OUT_ARB_CH1_REG register - * Configures the tx arbiter of channel 1 - */ -#define DMA2D_OUT_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x13c) -/** DMA2D_OUT_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_OUT_ARB_TOKEN_NUM_CH1 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_M (DMA2D_OUT_ARB_TOKEN_NUM_CH1_V << DMA2D_OUT_ARB_TOKEN_NUM_CH1_S) -#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_V 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_CH1 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH1_M (DMA2D_OUT_ARB_PRIORITY_CH1_V << DMA2D_OUT_ARB_PRIORITY_CH1_S) -#define DMA2D_OUT_ARB_PRIORITY_CH1_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH1_S 4 -/** DMA2D_OUT_ARB_PRIORITY_H_CH1 : R/W; bitpos: [7:6]; default: 0; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_H_CH1 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH1_M (DMA2D_OUT_ARB_PRIORITY_H_CH1_V << DMA2D_OUT_ARB_PRIORITY_H_CH1_S) -#define DMA2D_OUT_ARB_PRIORITY_H_CH1_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH1_S 6 - -/** DMA2D_OUT_RO_STATUS_CH1_REG register - * Represents the status of the tx reorder module of channel 1 - */ -#define DMA2D_OUT_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x140) -/** DMA2D_OUTFIFO_RO_CNT_CH1 : RO; bitpos: [5:0]; default: 0; - * The register stores the byte number of the data in color convert Tx FIFO for - * channel 0. - */ -#define DMA2D_OUTFIFO_RO_CNT_CH1 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH1_M (DMA2D_OUTFIFO_RO_CNT_CH1_V << DMA2D_OUTFIFO_RO_CNT_CH1_S) -#define DMA2D_OUTFIFO_RO_CNT_CH1_V 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH1_S 0 -/** DMA2D_OUT_RO_WR_STATE_CH1 : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_OUT_RO_WR_STATE_CH1 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH1_M (DMA2D_OUT_RO_WR_STATE_CH1_V << DMA2D_OUT_RO_WR_STATE_CH1_S) -#define DMA2D_OUT_RO_WR_STATE_CH1_V 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH1_S 6 -/** DMA2D_OUT_RO_RD_STATE_CH1 : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_OUT_RO_RD_STATE_CH1 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH1_M (DMA2D_OUT_RO_RD_STATE_CH1_V << DMA2D_OUT_RO_RD_STATE_CH1_S) -#define DMA2D_OUT_RO_RD_STATE_CH1_V 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH1_S 8 -/** DMA2D_OUT_PIXEL_BYTE_CH1 : RO; bitpos: [13:10]; default: 0; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_OUT_PIXEL_BYTE_CH1 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH1_M (DMA2D_OUT_PIXEL_BYTE_CH1_V << DMA2D_OUT_PIXEL_BYTE_CH1_S) -#define DMA2D_OUT_PIXEL_BYTE_CH1_V 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH1_S 10 -/** DMA2D_OUT_BURST_BLOCK_NUM_CH1 : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ -#define DMA2D_OUT_BURST_BLOCK_NUM_CH1 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_M (DMA2D_OUT_BURST_BLOCK_NUM_CH1_V << DMA2D_OUT_BURST_BLOCK_NUM_CH1_S) -#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_V 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_S 14 - -/** DMA2D_OUT_COLOR_CONVERT_CH1_REG register - * Configures the tx color convert of channel 1 - */ -#define DMA2D_OUT_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x148) -/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * YUV444 to YUV422 2: output directly - */ -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_M (DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S) -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S 0 -/** DMA2D_OUT_COLOR_3B_PROC_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1 (BIT(2)) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_M (DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V 0x00000001U -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S 2 -/** DMA2D_OUT_COLOR_INPUT_SEL_CH1 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: RGB565 to RGB888 1: - * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: - * disable color space convert - */ -#define DMA2D_OUT_COLOR_INPUT_SEL_CH1 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_M (DMA2D_OUT_COLOR_INPUT_SEL_CH1_V << DMA2D_OUT_COLOR_INPUT_SEL_CH1_S) -#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_V 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_S 3 - -/** DMA2D_OUT_SCRAMBLE_CH1_REG register - * Configures the tx scramble of channel 1 - */ -#define DMA2D_OUT_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x14c) -/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_M (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S) -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM0_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x150) -/** DMA2D_OUT_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H0_CH1 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH1_M (DMA2D_OUT_COLOR_PARAM_H0_CH1_V << DMA2D_OUT_COLOR_PARAM_H0_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_H0_CH1_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM1_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x154) -/** DMA2D_OUT_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H1_CH1 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH1_M (DMA2D_OUT_COLOR_PARAM_H1_CH1_V << DMA2D_OUT_COLOR_PARAM_H1_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_H1_CH1_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM2_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x158) -/** DMA2D_OUT_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M0_CH1 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH1_M (DMA2D_OUT_COLOR_PARAM_M0_CH1_V << DMA2D_OUT_COLOR_PARAM_M0_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_M0_CH1_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM3_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x15c) -/** DMA2D_OUT_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M1_CH1 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH1_M (DMA2D_OUT_COLOR_PARAM_M1_CH1_V << DMA2D_OUT_COLOR_PARAM_M1_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_M1_CH1_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM4_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x160) -/** DMA2D_OUT_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L0_CH1 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH1_M (DMA2D_OUT_COLOR_PARAM_L0_CH1_V << DMA2D_OUT_COLOR_PARAM_L0_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_L0_CH1_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM5_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x164) -/** DMA2D_OUT_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L1_CH1 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH1_M (DMA2D_OUT_COLOR_PARAM_L1_CH1_V << DMA2D_OUT_COLOR_PARAM_L1_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_L1_CH1_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH1_S 0 - -/** DMA2D_OUT_ETM_CONF_CH1_REG register - * Configures the tx etm of channel 1 - */ -#define DMA2D_OUT_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x168) -/** DMA2D_OUT_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_EN_CH1 (BIT(0)) -#define DMA2D_OUT_ETM_EN_CH1_M (DMA2D_OUT_ETM_EN_CH1_V << DMA2D_OUT_ETM_EN_CH1_S) -#define DMA2D_OUT_ETM_EN_CH1_V 0x00000001U -#define DMA2D_OUT_ETM_EN_CH1_S 0 -/** DMA2D_OUT_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_LOOP_EN_CH1 (BIT(1)) -#define DMA2D_OUT_ETM_LOOP_EN_CH1_M (DMA2D_OUT_ETM_LOOP_EN_CH1_V << DMA2D_OUT_ETM_LOOP_EN_CH1_S) -#define DMA2D_OUT_ETM_LOOP_EN_CH1_V 0x00000001U -#define DMA2D_OUT_ETM_LOOP_EN_CH1_S 1 -/** DMA2D_OUT_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_OUT_DSCR_TASK_MAK_CH1 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH1_M (DMA2D_OUT_DSCR_TASK_MAK_CH1_V << DMA2D_OUT_DSCR_TASK_MAK_CH1_S) -#define DMA2D_OUT_DSCR_TASK_MAK_CH1_V 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH1_S 2 - -/** DMA2D_OUT_DSCR_PORT_BLK_CH1_REG register - * Configures the tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_CH1_REG (DR_REG_DMA2D_BASE + 0x16c) -/** DMA2D_OUT_DSCR_PORT_BLK_H_CH1 : R/W; bitpos: [13:0]; default: 18; - * Set the vertical height of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_M (DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S) -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S 0 -/** DMA2D_OUT_DSCR_PORT_BLK_V_CH1 : R/W; bitpos: [27:14]; default: 18; - * Set the horizontal width of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_M (DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S) -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S 14 - -/** DMA2D_OUT_CONF0_CH2_REG register - * Configures the tx direction of channel 2 - */ -#define DMA2D_OUT_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x200) -/** DMA2D_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ -#define DMA2D_OUT_AUTO_WRBACK_CH2 (BIT(0)) -#define DMA2D_OUT_AUTO_WRBACK_CH2_M (DMA2D_OUT_AUTO_WRBACK_CH2_V << DMA2D_OUT_AUTO_WRBACK_CH2_S) -#define DMA2D_OUT_AUTO_WRBACK_CH2_V 0x00000001U -#define DMA2D_OUT_AUTO_WRBACK_CH2_S 0 -/** DMA2D_OUT_EOF_MODE_CH2 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ -#define DMA2D_OUT_EOF_MODE_CH2 (BIT(1)) -#define DMA2D_OUT_EOF_MODE_CH2_M (DMA2D_OUT_EOF_MODE_CH2_V << DMA2D_OUT_EOF_MODE_CH2_S) -#define DMA2D_OUT_EOF_MODE_CH2_V 0x00000001U -#define DMA2D_OUT_EOF_MODE_CH2_S 1 -/** DMA2D_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ -#define DMA2D_OUTDSCR_BURST_EN_CH2 (BIT(2)) -#define DMA2D_OUTDSCR_BURST_EN_CH2_M (DMA2D_OUTDSCR_BURST_EN_CH2_V << DMA2D_OUTDSCR_BURST_EN_CH2_S) -#define DMA2D_OUTDSCR_BURST_EN_CH2_V 0x00000001U -#define DMA2D_OUTDSCR_BURST_EN_CH2_S 2 -/** DMA2D_OUT_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_OUT_ECC_AES_EN_CH2 (BIT(3)) -#define DMA2D_OUT_ECC_AES_EN_CH2_M (DMA2D_OUT_ECC_AES_EN_CH2_V << DMA2D_OUT_ECC_AES_EN_CH2_S) -#define DMA2D_OUT_ECC_AES_EN_CH2_V 0x00000001U -#define DMA2D_OUT_ECC_AES_EN_CH2_S 3 -/** DMA2D_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_OUT_CHECK_OWNER_CH2 (BIT(4)) -#define DMA2D_OUT_CHECK_OWNER_CH2_M (DMA2D_OUT_CHECK_OWNER_CH2_V << DMA2D_OUT_CHECK_OWNER_CH2_S) -#define DMA2D_OUT_CHECK_OWNER_CH2_V 0x00000001U -#define DMA2D_OUT_CHECK_OWNER_CH2_S 4 -/** DMA2D_OUT_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_OUT_LOOP_TEST_CH2 (BIT(5)) -#define DMA2D_OUT_LOOP_TEST_CH2_M (DMA2D_OUT_LOOP_TEST_CH2_V << DMA2D_OUT_LOOP_TEST_CH2_S) -#define DMA2D_OUT_LOOP_TEST_CH2_V 0x00000001U -#define DMA2D_OUT_LOOP_TEST_CH2_S 5 -/** DMA2D_OUT_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_OUT_MEM_BURST_LENGTH_CH2 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_M (DMA2D_OUT_MEM_BURST_LENGTH_CH2_V << DMA2D_OUT_MEM_BURST_LENGTH_CH2_S) -#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_V 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_S 6 -/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0; - * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_M (DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S) -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S 9 -/** DMA2D_OUT_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_OUT_DSCR_PORT_EN_CH2 (BIT(11)) -#define DMA2D_OUT_DSCR_PORT_EN_CH2_M (DMA2D_OUT_DSCR_PORT_EN_CH2_V << DMA2D_OUT_DSCR_PORT_EN_CH2_S) -#define DMA2D_OUT_DSCR_PORT_EN_CH2_V 0x00000001U -#define DMA2D_OUT_DSCR_PORT_EN_CH2_S 11 -/** DMA2D_OUT_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ -#define DMA2D_OUT_PAGE_BOUND_EN_CH2 (BIT(12)) -#define DMA2D_OUT_PAGE_BOUND_EN_CH2_M (DMA2D_OUT_PAGE_BOUND_EN_CH2_V << DMA2D_OUT_PAGE_BOUND_EN_CH2_S) -#define DMA2D_OUT_PAGE_BOUND_EN_CH2_V 0x00000001U -#define DMA2D_OUT_PAGE_BOUND_EN_CH2_S 12 -/** DMA2D_OUT_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_OUT_REORDER_EN_CH2 (BIT(16)) -#define DMA2D_OUT_REORDER_EN_CH2_M (DMA2D_OUT_REORDER_EN_CH2_V << DMA2D_OUT_REORDER_EN_CH2_S) -#define DMA2D_OUT_REORDER_EN_CH2_V 0x00000001U -#define DMA2D_OUT_REORDER_EN_CH2_S 16 -/** DMA2D_OUT_RST_CH2 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ -#define DMA2D_OUT_RST_CH2 (BIT(24)) -#define DMA2D_OUT_RST_CH2_M (DMA2D_OUT_RST_CH2_V << DMA2D_OUT_RST_CH2_S) -#define DMA2D_OUT_RST_CH2_V 0x00000001U -#define DMA2D_OUT_RST_CH2_S 24 -/** DMA2D_OUT_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_OUT_CMD_DISABLE_CH2 (BIT(25)) -#define DMA2D_OUT_CMD_DISABLE_CH2_M (DMA2D_OUT_CMD_DISABLE_CH2_V << DMA2D_OUT_CMD_DISABLE_CH2_S) -#define DMA2D_OUT_CMD_DISABLE_CH2_V 0x00000001U -#define DMA2D_OUT_CMD_DISABLE_CH2_S 25 -/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2 (BIT(26)) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_M (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V 0x00000001U -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S 26 - -/** DMA2D_OUT_INT_RAW_CH2_REG register - * Raw interrupt status of TX channel 2 - */ -#define DMA2D_OUT_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x204) -/** DMA2D_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ -#define DMA2D_OUT_DONE_CH2_INT_RAW (BIT(0)) -#define DMA2D_OUT_DONE_CH2_INT_RAW_M (DMA2D_OUT_DONE_CH2_INT_RAW_V << DMA2D_OUT_DONE_CH2_INT_RAW_S) -#define DMA2D_OUT_DONE_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DONE_CH2_INT_RAW_S 0 -/** DMA2D_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ -#define DMA2D_OUT_EOF_CH2_INT_RAW (BIT(1)) -#define DMA2D_OUT_EOF_CH2_INT_RAW_M (DMA2D_OUT_EOF_CH2_INT_RAW_V << DMA2D_OUT_EOF_CH2_INT_RAW_S) -#define DMA2D_OUT_EOF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUT_EOF_CH2_INT_RAW_S 1 -/** DMA2D_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ -#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_M (DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_M (DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_M (DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_M (DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_M (DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_M (DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_M (DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_M (DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_M (DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_M (DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_M (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S 12 - -/** DMA2D_OUT_INT_ENA_CH2_REG register - * Interrupt enable bits of TX channel 2 - */ -#define DMA2D_OUT_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x208) -/** DMA2D_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH2_INT_ENA (BIT(0)) -#define DMA2D_OUT_DONE_CH2_INT_ENA_M (DMA2D_OUT_DONE_CH2_INT_ENA_V << DMA2D_OUT_DONE_CH2_INT_ENA_S) -#define DMA2D_OUT_DONE_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DONE_CH2_INT_ENA_S 0 -/** DMA2D_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH2_INT_ENA (BIT(1)) -#define DMA2D_OUT_EOF_CH2_INT_ENA_M (DMA2D_OUT_EOF_CH2_INT_ENA_V << DMA2D_OUT_EOF_CH2_INT_ENA_S) -#define DMA2D_OUT_EOF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUT_EOF_CH2_INT_ENA_S 1 -/** DMA2D_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_M (DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_M (DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_M (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_M (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_M (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_M (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_M (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_M (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_M (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_M (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_M (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S 12 - -/** DMA2D_OUT_INT_ST_CH2_REG register - * Masked interrupt status of TX channel 2 - */ -#define DMA2D_OUT_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x20c) -/** DMA2D_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH2_INT_ST (BIT(0)) -#define DMA2D_OUT_DONE_CH2_INT_ST_M (DMA2D_OUT_DONE_CH2_INT_ST_V << DMA2D_OUT_DONE_CH2_INT_ST_S) -#define DMA2D_OUT_DONE_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUT_DONE_CH2_INT_ST_S 0 -/** DMA2D_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH2_INT_ST (BIT(1)) -#define DMA2D_OUT_EOF_CH2_INT_ST_M (DMA2D_OUT_EOF_CH2_INT_ST_V << DMA2D_OUT_EOF_CH2_INT_ST_S) -#define DMA2D_OUT_EOF_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUT_EOF_CH2_INT_ST_S 1 -/** DMA2D_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_M (DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_M (DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_M (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_M (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_M (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_M (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_M (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_M (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_M (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_M (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_M (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S 12 - -/** DMA2D_OUT_INT_CLR_CH2_REG register - * Interrupt clear bits of TX channel 2 - */ -#define DMA2D_OUT_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x210) -/** DMA2D_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH2_INT_CLR (BIT(0)) -#define DMA2D_OUT_DONE_CH2_INT_CLR_M (DMA2D_OUT_DONE_CH2_INT_CLR_V << DMA2D_OUT_DONE_CH2_INT_CLR_S) -#define DMA2D_OUT_DONE_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DONE_CH2_INT_CLR_S 0 -/** DMA2D_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH2_INT_CLR (BIT(1)) -#define DMA2D_OUT_EOF_CH2_INT_CLR_M (DMA2D_OUT_EOF_CH2_INT_CLR_V << DMA2D_OUT_EOF_CH2_INT_CLR_S) -#define DMA2D_OUT_EOF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUT_EOF_CH2_INT_CLR_S 1 -/** DMA2D_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_M (DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_M (DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_M (DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_M (DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_M (DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_M (DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_M (DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_M (DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_M (DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_M (DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_M (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S 12 - -/** DMA2D_OUTFIFO_STATUS_CH2_REG register - * Represents the status of the tx fifo of channel 2 - */ -#define DMA2D_OUTFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x214) -/** DMA2D_OUTFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L2_CH2 (BIT(0)) -#define DMA2D_OUTFIFO_FULL_L2_CH2_M (DMA2D_OUTFIFO_FULL_L2_CH2_V << DMA2D_OUTFIFO_FULL_L2_CH2_S) -#define DMA2D_OUTFIFO_FULL_L2_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L2_CH2_S 0 -/** DMA2D_OUTFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L2_CH2 (BIT(1)) -#define DMA2D_OUTFIFO_EMPTY_L2_CH2_M (DMA2D_OUTFIFO_EMPTY_L2_CH2_V << DMA2D_OUTFIFO_EMPTY_L2_CH2_S) -#define DMA2D_OUTFIFO_EMPTY_L2_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L2_CH2_S 1 -/** DMA2D_OUTFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L2_CH2 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH2_M (DMA2D_OUTFIFO_CNT_L2_CH2_V << DMA2D_OUTFIFO_CNT_L2_CH2_S) -#define DMA2D_OUTFIFO_CNT_L2_CH2_V 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH2_S 2 -/** DMA2D_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_1B_CH2 (BIT(7)) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_M (DMA2D_OUT_REMAIN_UNDER_1B_CH2_V << DMA2D_OUT_REMAIN_UNDER_1B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_S 7 -/** DMA2D_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_2B_CH2 (BIT(8)) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_M (DMA2D_OUT_REMAIN_UNDER_2B_CH2_V << DMA2D_OUT_REMAIN_UNDER_2B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_S 8 -/** DMA2D_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_3B_CH2 (BIT(9)) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_M (DMA2D_OUT_REMAIN_UNDER_3B_CH2_V << DMA2D_OUT_REMAIN_UNDER_3B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_S 9 -/** DMA2D_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_4B_CH2 (BIT(10)) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_M (DMA2D_OUT_REMAIN_UNDER_4B_CH2_V << DMA2D_OUT_REMAIN_UNDER_4B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_S 10 -/** DMA2D_OUT_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_5B_CH2 (BIT(11)) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_M (DMA2D_OUT_REMAIN_UNDER_5B_CH2_V << DMA2D_OUT_REMAIN_UNDER_5B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_S 11 -/** DMA2D_OUT_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_6B_CH2 (BIT(12)) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_M (DMA2D_OUT_REMAIN_UNDER_6B_CH2_V << DMA2D_OUT_REMAIN_UNDER_6B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_S 12 -/** DMA2D_OUT_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_7B_CH2 (BIT(13)) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_M (DMA2D_OUT_REMAIN_UNDER_7B_CH2_V << DMA2D_OUT_REMAIN_UNDER_7B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_S 13 -/** DMA2D_OUT_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_8B_CH2 (BIT(14)) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_M (DMA2D_OUT_REMAIN_UNDER_8B_CH2_V << DMA2D_OUT_REMAIN_UNDER_8B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_S 14 -/** DMA2D_OUTFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L1_CH2 (BIT(15)) -#define DMA2D_OUTFIFO_FULL_L1_CH2_M (DMA2D_OUTFIFO_FULL_L1_CH2_V << DMA2D_OUTFIFO_FULL_L1_CH2_S) -#define DMA2D_OUTFIFO_FULL_L1_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L1_CH2_S 15 -/** DMA2D_OUTFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L1_CH2 (BIT(16)) -#define DMA2D_OUTFIFO_EMPTY_L1_CH2_M (DMA2D_OUTFIFO_EMPTY_L1_CH2_V << DMA2D_OUTFIFO_EMPTY_L1_CH2_S) -#define DMA2D_OUTFIFO_EMPTY_L1_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L1_CH2_S 16 -/** DMA2D_OUTFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L1_CH2 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH2_M (DMA2D_OUTFIFO_CNT_L1_CH2_V << DMA2D_OUTFIFO_CNT_L1_CH2_S) -#define DMA2D_OUTFIFO_CNT_L1_CH2_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH2_S 17 -/** DMA2D_OUTFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L3_CH2 (BIT(22)) -#define DMA2D_OUTFIFO_FULL_L3_CH2_M (DMA2D_OUTFIFO_FULL_L3_CH2_V << DMA2D_OUTFIFO_FULL_L3_CH2_S) -#define DMA2D_OUTFIFO_FULL_L3_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L3_CH2_S 22 -/** DMA2D_OUTFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L3_CH2 (BIT(23)) -#define DMA2D_OUTFIFO_EMPTY_L3_CH2_M (DMA2D_OUTFIFO_EMPTY_L3_CH2_V << DMA2D_OUTFIFO_EMPTY_L3_CH2_S) -#define DMA2D_OUTFIFO_EMPTY_L3_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L3_CH2_S 23 -/** DMA2D_OUTFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L3_CH2 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH2_M (DMA2D_OUTFIFO_CNT_L3_CH2_V << DMA2D_OUTFIFO_CNT_L3_CH2_S) -#define DMA2D_OUTFIFO_CNT_L3_CH2_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH2_S 24 - -/** DMA2D_OUT_PUSH_CH2_REG register - * Configures the tx fifo of channel 2 - */ -#define DMA2D_OUT_PUSH_CH2_REG (DR_REG_DMA2D_BASE + 0x218) -/** DMA2D_OUTFIFO_WDATA_CH2 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_WDATA_CH2 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH2_M (DMA2D_OUTFIFO_WDATA_CH2_V << DMA2D_OUTFIFO_WDATA_CH2_S) -#define DMA2D_OUTFIFO_WDATA_CH2_V 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH2_S 0 -/** DMA2D_OUTFIFO_PUSH_CH2 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_PUSH_CH2 (BIT(10)) -#define DMA2D_OUTFIFO_PUSH_CH2_M (DMA2D_OUTFIFO_PUSH_CH2_V << DMA2D_OUTFIFO_PUSH_CH2_S) -#define DMA2D_OUTFIFO_PUSH_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_PUSH_CH2_S 10 - -/** DMA2D_OUT_LINK_CONF_CH2_REG register - * Configures the tx descriptor operations of channel 2 - */ -#define DMA2D_OUT_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x21c) -/** DMA2D_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_STOP_CH2 (BIT(20)) -#define DMA2D_OUTLINK_STOP_CH2_M (DMA2D_OUTLINK_STOP_CH2_V << DMA2D_OUTLINK_STOP_CH2_S) -#define DMA2D_OUTLINK_STOP_CH2_V 0x00000001U -#define DMA2D_OUTLINK_STOP_CH2_S 20 -/** DMA2D_OUTLINK_START_CH2 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_START_CH2 (BIT(21)) -#define DMA2D_OUTLINK_START_CH2_M (DMA2D_OUTLINK_START_CH2_V << DMA2D_OUTLINK_START_CH2_S) -#define DMA2D_OUTLINK_START_CH2_V 0x00000001U -#define DMA2D_OUTLINK_START_CH2_S 21 -/** DMA2D_OUTLINK_RESTART_CH2 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ -#define DMA2D_OUTLINK_RESTART_CH2 (BIT(22)) -#define DMA2D_OUTLINK_RESTART_CH2_M (DMA2D_OUTLINK_RESTART_CH2_V << DMA2D_OUTLINK_RESTART_CH2_S) -#define DMA2D_OUTLINK_RESTART_CH2_V 0x00000001U -#define DMA2D_OUTLINK_RESTART_CH2_S 22 -/** DMA2D_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ -#define DMA2D_OUTLINK_PARK_CH2 (BIT(23)) -#define DMA2D_OUTLINK_PARK_CH2_M (DMA2D_OUTLINK_PARK_CH2_V << DMA2D_OUTLINK_PARK_CH2_S) -#define DMA2D_OUTLINK_PARK_CH2_V 0x00000001U -#define DMA2D_OUTLINK_PARK_CH2_S 23 - -/** DMA2D_OUT_LINK_ADDR_CH2_REG register - * Configures the tx descriptor address of channel 2 - */ -#define DMA2D_OUT_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x220) -/** DMA2D_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ -#define DMA2D_OUTLINK_ADDR_CH2 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH2_M (DMA2D_OUTLINK_ADDR_CH2_V << DMA2D_OUTLINK_ADDR_CH2_S) -#define DMA2D_OUTLINK_ADDR_CH2_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH2_S 0 - -/** DMA2D_OUT_STATE_CH2_REG register - * Represents the working status of the tx descriptor of channel 2 - */ -#define DMA2D_OUT_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x224) -/** DMA2D_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ -#define DMA2D_OUTLINK_DSCR_ADDR_CH2 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH2_M (DMA2D_OUTLINK_DSCR_ADDR_CH2_V << DMA2D_OUTLINK_DSCR_ADDR_CH2_S) -#define DMA2D_OUTLINK_DSCR_ADDR_CH2_V 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH2_S 0 -/** DMA2D_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ -#define DMA2D_OUT_DSCR_STATE_CH2 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH2_M (DMA2D_OUT_DSCR_STATE_CH2_V << DMA2D_OUT_DSCR_STATE_CH2_S) -#define DMA2D_OUT_DSCR_STATE_CH2_V 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH2_S 18 -/** DMA2D_OUT_STATE_CH2 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ -#define DMA2D_OUT_STATE_CH2 0x0000000FU -#define DMA2D_OUT_STATE_CH2_M (DMA2D_OUT_STATE_CH2_V << DMA2D_OUT_STATE_CH2_S) -#define DMA2D_OUT_STATE_CH2_V 0x0000000FU -#define DMA2D_OUT_STATE_CH2_S 20 -/** DMA2D_OUT_RESET_AVAIL_CH2 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_OUT_RESET_AVAIL_CH2 (BIT(24)) -#define DMA2D_OUT_RESET_AVAIL_CH2_M (DMA2D_OUT_RESET_AVAIL_CH2_V << DMA2D_OUT_RESET_AVAIL_CH2_S) -#define DMA2D_OUT_RESET_AVAIL_CH2_V 0x00000001U -#define DMA2D_OUT_RESET_AVAIL_CH2_S 24 - -/** DMA2D_OUT_EOF_DES_ADDR_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 2 - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x228) -/** DMA2D_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH2_M (DMA2D_OUT_EOF_DES_ADDR_CH2_V << DMA2D_OUT_EOF_DES_ADDR_CH2_S) -#define DMA2D_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH2_S 0 - -/** DMA2D_OUT_DSCR_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 2 - */ -#define DMA2D_OUT_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x22c) -/** DMA2D_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ -#define DMA2D_OUTLINK_DSCR_CH2 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH2_M (DMA2D_OUTLINK_DSCR_CH2_V << DMA2D_OUTLINK_DSCR_CH2_S) -#define DMA2D_OUTLINK_DSCR_CH2_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH2_S 0 - -/** DMA2D_OUT_DSCR_BF0_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 2 - */ -#define DMA2D_OUT_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x230) -/** DMA2D_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ -#define DMA2D_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH2_M (DMA2D_OUTLINK_DSCR_BF0_CH2_V << DMA2D_OUTLINK_DSCR_BF0_CH2_S) -#define DMA2D_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH2_S 0 - -/** DMA2D_OUT_DSCR_BF1_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 2 - */ -#define DMA2D_OUT_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x234) -/** DMA2D_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ -#define DMA2D_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH2_M (DMA2D_OUTLINK_DSCR_BF1_CH2_V << DMA2D_OUTLINK_DSCR_BF1_CH2_S) -#define DMA2D_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH2_S 0 - -/** DMA2D_OUT_PERI_SEL_CH2_REG register - * Configures the tx peripheral of channel 2 - */ -#define DMA2D_OUT_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x238) -/** DMA2D_OUT_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Tx channel 0: jpeg 1: - * display-1 2: display-2 3: display-3 7: no choose - */ -#define DMA2D_OUT_PERI_SEL_CH2 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH2_M (DMA2D_OUT_PERI_SEL_CH2_V << DMA2D_OUT_PERI_SEL_CH2_S) -#define DMA2D_OUT_PERI_SEL_CH2_V 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH2_S 0 - -/** DMA2D_OUT_ARB_CH2_REG register - * Configures the tx arbiter of channel 2 - */ -#define DMA2D_OUT_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x23c) -/** DMA2D_OUT_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_OUT_ARB_TOKEN_NUM_CH2 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_M (DMA2D_OUT_ARB_TOKEN_NUM_CH2_V << DMA2D_OUT_ARB_TOKEN_NUM_CH2_S) -#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_V 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_CH2 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH2_M (DMA2D_OUT_ARB_PRIORITY_CH2_V << DMA2D_OUT_ARB_PRIORITY_CH2_S) -#define DMA2D_OUT_ARB_PRIORITY_CH2_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH2_S 4 -/** DMA2D_OUT_ARB_PRIORITY_H_CH2 : R/W; bitpos: [7:6]; default: 0; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_H_CH2 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH2_M (DMA2D_OUT_ARB_PRIORITY_H_CH2_V << DMA2D_OUT_ARB_PRIORITY_H_CH2_S) -#define DMA2D_OUT_ARB_PRIORITY_H_CH2_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH2_S 6 - -/** DMA2D_OUT_RO_STATUS_CH2_REG register - * Represents the status of the tx reorder module of channel 2 - */ -#define DMA2D_OUT_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x240) -/** DMA2D_OUTFIFO_RO_CNT_CH2 : RO; bitpos: [5:0]; default: 0; - * The register stores the byte number of the data in color convert Tx FIFO for - * channel 0. - */ -#define DMA2D_OUTFIFO_RO_CNT_CH2 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH2_M (DMA2D_OUTFIFO_RO_CNT_CH2_V << DMA2D_OUTFIFO_RO_CNT_CH2_S) -#define DMA2D_OUTFIFO_RO_CNT_CH2_V 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH2_S 0 -/** DMA2D_OUT_RO_WR_STATE_CH2 : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_OUT_RO_WR_STATE_CH2 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH2_M (DMA2D_OUT_RO_WR_STATE_CH2_V << DMA2D_OUT_RO_WR_STATE_CH2_S) -#define DMA2D_OUT_RO_WR_STATE_CH2_V 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH2_S 6 -/** DMA2D_OUT_RO_RD_STATE_CH2 : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_OUT_RO_RD_STATE_CH2 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH2_M (DMA2D_OUT_RO_RD_STATE_CH2_V << DMA2D_OUT_RO_RD_STATE_CH2_S) -#define DMA2D_OUT_RO_RD_STATE_CH2_V 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH2_S 8 -/** DMA2D_OUT_PIXEL_BYTE_CH2 : RO; bitpos: [13:10]; default: 0; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_OUT_PIXEL_BYTE_CH2 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH2_M (DMA2D_OUT_PIXEL_BYTE_CH2_V << DMA2D_OUT_PIXEL_BYTE_CH2_S) -#define DMA2D_OUT_PIXEL_BYTE_CH2_V 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH2_S 10 -/** DMA2D_OUT_BURST_BLOCK_NUM_CH2 : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ -#define DMA2D_OUT_BURST_BLOCK_NUM_CH2 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_M (DMA2D_OUT_BURST_BLOCK_NUM_CH2_V << DMA2D_OUT_BURST_BLOCK_NUM_CH2_S) -#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_V 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_S 14 - -/** DMA2D_OUT_COLOR_CONVERT_CH2_REG register - * Configures the tx color convert of channel 2 - */ -#define DMA2D_OUT_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x248) -/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * YUV444 to YUV422 2: output directly - */ -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_M (DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S) -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S 0 -/** DMA2D_OUT_COLOR_3B_PROC_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2 (BIT(2)) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_M (DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V 0x00000001U -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S 2 -/** DMA2D_OUT_COLOR_INPUT_SEL_CH2 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: RGB565 to RGB888 1: - * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: - * disable color space convert - */ -#define DMA2D_OUT_COLOR_INPUT_SEL_CH2 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_M (DMA2D_OUT_COLOR_INPUT_SEL_CH2_V << DMA2D_OUT_COLOR_INPUT_SEL_CH2_S) -#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_V 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_S 3 - -/** DMA2D_OUT_SCRAMBLE_CH2_REG register - * Configures the tx scramble of channel 2 - */ -#define DMA2D_OUT_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x24c) -/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_M (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S) -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM0_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x250) -/** DMA2D_OUT_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H0_CH2 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH2_M (DMA2D_OUT_COLOR_PARAM_H0_CH2_V << DMA2D_OUT_COLOR_PARAM_H0_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_H0_CH2_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM1_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x254) -/** DMA2D_OUT_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H1_CH2 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH2_M (DMA2D_OUT_COLOR_PARAM_H1_CH2_V << DMA2D_OUT_COLOR_PARAM_H1_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_H1_CH2_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM2_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x258) -/** DMA2D_OUT_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M0_CH2 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH2_M (DMA2D_OUT_COLOR_PARAM_M0_CH2_V << DMA2D_OUT_COLOR_PARAM_M0_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_M0_CH2_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM3_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x25c) -/** DMA2D_OUT_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M1_CH2 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH2_M (DMA2D_OUT_COLOR_PARAM_M1_CH2_V << DMA2D_OUT_COLOR_PARAM_M1_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_M1_CH2_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM4_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x260) -/** DMA2D_OUT_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L0_CH2 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH2_M (DMA2D_OUT_COLOR_PARAM_L0_CH2_V << DMA2D_OUT_COLOR_PARAM_L0_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_L0_CH2_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM5_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x264) -/** DMA2D_OUT_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L1_CH2 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH2_M (DMA2D_OUT_COLOR_PARAM_L1_CH2_V << DMA2D_OUT_COLOR_PARAM_L1_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_L1_CH2_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH2_S 0 - -/** DMA2D_OUT_ETM_CONF_CH2_REG register - * Configures the tx etm of channel 2 - */ -#define DMA2D_OUT_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x268) -/** DMA2D_OUT_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_EN_CH2 (BIT(0)) -#define DMA2D_OUT_ETM_EN_CH2_M (DMA2D_OUT_ETM_EN_CH2_V << DMA2D_OUT_ETM_EN_CH2_S) -#define DMA2D_OUT_ETM_EN_CH2_V 0x00000001U -#define DMA2D_OUT_ETM_EN_CH2_S 0 -/** DMA2D_OUT_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_LOOP_EN_CH2 (BIT(1)) -#define DMA2D_OUT_ETM_LOOP_EN_CH2_M (DMA2D_OUT_ETM_LOOP_EN_CH2_V << DMA2D_OUT_ETM_LOOP_EN_CH2_S) -#define DMA2D_OUT_ETM_LOOP_EN_CH2_V 0x00000001U -#define DMA2D_OUT_ETM_LOOP_EN_CH2_S 1 -/** DMA2D_OUT_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_OUT_DSCR_TASK_MAK_CH2 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH2_M (DMA2D_OUT_DSCR_TASK_MAK_CH2_V << DMA2D_OUT_DSCR_TASK_MAK_CH2_S) -#define DMA2D_OUT_DSCR_TASK_MAK_CH2_V 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH2_S 2 - -/** DMA2D_OUT_DSCR_PORT_BLK_CH2_REG register - * Configures the tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_CH2_REG (DR_REG_DMA2D_BASE + 0x26c) -/** DMA2D_OUT_DSCR_PORT_BLK_H_CH2 : R/W; bitpos: [13:0]; default: 18; - * Set the vertical height of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_M (DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S) -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S 0 -/** DMA2D_OUT_DSCR_PORT_BLK_V_CH2 : R/W; bitpos: [27:14]; default: 18; - * Set the horizontal width of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_M (DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S) -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S 14 - -/** DMA2D_OUT_CONF0_CH3_REG register - * Configures the tx direction of channel 3 - */ -#define DMA2D_OUT_CONF0_CH3_REG (DR_REG_DMA2D_BASE + 0x300) -/** DMA2D_OUT_AUTO_WRBACK_CH3 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ -#define DMA2D_OUT_AUTO_WRBACK_CH3 (BIT(0)) -#define DMA2D_OUT_AUTO_WRBACK_CH3_M (DMA2D_OUT_AUTO_WRBACK_CH3_V << DMA2D_OUT_AUTO_WRBACK_CH3_S) -#define DMA2D_OUT_AUTO_WRBACK_CH3_V 0x00000001U -#define DMA2D_OUT_AUTO_WRBACK_CH3_S 0 -/** DMA2D_OUT_EOF_MODE_CH3 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ -#define DMA2D_OUT_EOF_MODE_CH3 (BIT(1)) -#define DMA2D_OUT_EOF_MODE_CH3_M (DMA2D_OUT_EOF_MODE_CH3_V << DMA2D_OUT_EOF_MODE_CH3_S) -#define DMA2D_OUT_EOF_MODE_CH3_V 0x00000001U -#define DMA2D_OUT_EOF_MODE_CH3_S 1 -/** DMA2D_OUTDSCR_BURST_EN_CH3 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ -#define DMA2D_OUTDSCR_BURST_EN_CH3 (BIT(2)) -#define DMA2D_OUTDSCR_BURST_EN_CH3_M (DMA2D_OUTDSCR_BURST_EN_CH3_V << DMA2D_OUTDSCR_BURST_EN_CH3_S) -#define DMA2D_OUTDSCR_BURST_EN_CH3_V 0x00000001U -#define DMA2D_OUTDSCR_BURST_EN_CH3_S 2 -/** DMA2D_OUT_ECC_AES_EN_CH3 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_OUT_ECC_AES_EN_CH3 (BIT(3)) -#define DMA2D_OUT_ECC_AES_EN_CH3_M (DMA2D_OUT_ECC_AES_EN_CH3_V << DMA2D_OUT_ECC_AES_EN_CH3_S) -#define DMA2D_OUT_ECC_AES_EN_CH3_V 0x00000001U -#define DMA2D_OUT_ECC_AES_EN_CH3_S 3 -/** DMA2D_OUT_CHECK_OWNER_CH3 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_OUT_CHECK_OWNER_CH3 (BIT(4)) -#define DMA2D_OUT_CHECK_OWNER_CH3_M (DMA2D_OUT_CHECK_OWNER_CH3_V << DMA2D_OUT_CHECK_OWNER_CH3_S) -#define DMA2D_OUT_CHECK_OWNER_CH3_V 0x00000001U -#define DMA2D_OUT_CHECK_OWNER_CH3_S 4 -/** DMA2D_OUT_LOOP_TEST_CH3 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_OUT_LOOP_TEST_CH3 (BIT(5)) -#define DMA2D_OUT_LOOP_TEST_CH3_M (DMA2D_OUT_LOOP_TEST_CH3_V << DMA2D_OUT_LOOP_TEST_CH3_S) -#define DMA2D_OUT_LOOP_TEST_CH3_V 0x00000001U -#define DMA2D_OUT_LOOP_TEST_CH3_S 5 -/** DMA2D_OUT_MEM_BURST_LENGTH_CH3 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_OUT_MEM_BURST_LENGTH_CH3 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_M (DMA2D_OUT_MEM_BURST_LENGTH_CH3_V << DMA2D_OUT_MEM_BURST_LENGTH_CH3_S) -#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_V 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_S 6 -/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH3 : R/W; bitpos: [10:9]; default: 0; - * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_M (DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S) -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S 9 -/** DMA2D_OUT_DSCR_PORT_EN_CH3 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_OUT_DSCR_PORT_EN_CH3 (BIT(11)) -#define DMA2D_OUT_DSCR_PORT_EN_CH3_M (DMA2D_OUT_DSCR_PORT_EN_CH3_V << DMA2D_OUT_DSCR_PORT_EN_CH3_S) -#define DMA2D_OUT_DSCR_PORT_EN_CH3_V 0x00000001U -#define DMA2D_OUT_DSCR_PORT_EN_CH3_S 11 -/** DMA2D_OUT_PAGE_BOUND_EN_CH3 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ -#define DMA2D_OUT_PAGE_BOUND_EN_CH3 (BIT(12)) -#define DMA2D_OUT_PAGE_BOUND_EN_CH3_M (DMA2D_OUT_PAGE_BOUND_EN_CH3_V << DMA2D_OUT_PAGE_BOUND_EN_CH3_S) -#define DMA2D_OUT_PAGE_BOUND_EN_CH3_V 0x00000001U -#define DMA2D_OUT_PAGE_BOUND_EN_CH3_S 12 -/** DMA2D_OUT_REORDER_EN_CH3 : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_OUT_REORDER_EN_CH3 (BIT(16)) -#define DMA2D_OUT_REORDER_EN_CH3_M (DMA2D_OUT_REORDER_EN_CH3_V << DMA2D_OUT_REORDER_EN_CH3_S) -#define DMA2D_OUT_REORDER_EN_CH3_V 0x00000001U -#define DMA2D_OUT_REORDER_EN_CH3_S 16 -/** DMA2D_OUT_RST_CH3 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ -#define DMA2D_OUT_RST_CH3 (BIT(24)) -#define DMA2D_OUT_RST_CH3_M (DMA2D_OUT_RST_CH3_V << DMA2D_OUT_RST_CH3_S) -#define DMA2D_OUT_RST_CH3_V 0x00000001U -#define DMA2D_OUT_RST_CH3_S 24 -/** DMA2D_OUT_CMD_DISABLE_CH3 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_OUT_CMD_DISABLE_CH3 (BIT(25)) -#define DMA2D_OUT_CMD_DISABLE_CH3_M (DMA2D_OUT_CMD_DISABLE_CH3_V << DMA2D_OUT_CMD_DISABLE_CH3_S) -#define DMA2D_OUT_CMD_DISABLE_CH3_V 0x00000001U -#define DMA2D_OUT_CMD_DISABLE_CH3_S 25 -/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3 (BIT(26)) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_M (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V 0x00000001U -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S 26 - -/** DMA2D_OUT_INT_RAW_CH3_REG register - * Raw interrupt status of TX channel 3 - */ -#define DMA2D_OUT_INT_RAW_CH3_REG (DR_REG_DMA2D_BASE + 0x304) -/** DMA2D_OUT_DONE_CH3_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ -#define DMA2D_OUT_DONE_CH3_INT_RAW (BIT(0)) -#define DMA2D_OUT_DONE_CH3_INT_RAW_M (DMA2D_OUT_DONE_CH3_INT_RAW_V << DMA2D_OUT_DONE_CH3_INT_RAW_S) -#define DMA2D_OUT_DONE_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DONE_CH3_INT_RAW_S 0 -/** DMA2D_OUT_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ -#define DMA2D_OUT_EOF_CH3_INT_RAW (BIT(1)) -#define DMA2D_OUT_EOF_CH3_INT_RAW_M (DMA2D_OUT_EOF_CH3_INT_RAW_V << DMA2D_OUT_EOF_CH3_INT_RAW_S) -#define DMA2D_OUT_EOF_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUT_EOF_CH3_INT_RAW_S 1 -/** DMA2D_OUT_DSCR_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ -#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_M (DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S 12 - -/** DMA2D_OUT_INT_ENA_CH3_REG register - * Interrupt enable bits of TX channel 3 - */ -#define DMA2D_OUT_INT_ENA_CH3_REG (DR_REG_DMA2D_BASE + 0x308) -/** DMA2D_OUT_DONE_CH3_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH3_INT_ENA (BIT(0)) -#define DMA2D_OUT_DONE_CH3_INT_ENA_M (DMA2D_OUT_DONE_CH3_INT_ENA_V << DMA2D_OUT_DONE_CH3_INT_ENA_S) -#define DMA2D_OUT_DONE_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DONE_CH3_INT_ENA_S 0 -/** DMA2D_OUT_EOF_CH3_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH3_INT_ENA (BIT(1)) -#define DMA2D_OUT_EOF_CH3_INT_ENA_M (DMA2D_OUT_EOF_CH3_INT_ENA_V << DMA2D_OUT_EOF_CH3_INT_ENA_S) -#define DMA2D_OUT_EOF_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUT_EOF_CH3_INT_ENA_S 1 -/** DMA2D_OUT_DSCR_ERR_CH3_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_M (DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S 12 - -/** DMA2D_OUT_INT_ST_CH3_REG register - * Masked interrupt status of TX channel 3 - */ -#define DMA2D_OUT_INT_ST_CH3_REG (DR_REG_DMA2D_BASE + 0x30c) -/** DMA2D_OUT_DONE_CH3_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH3_INT_ST (BIT(0)) -#define DMA2D_OUT_DONE_CH3_INT_ST_M (DMA2D_OUT_DONE_CH3_INT_ST_V << DMA2D_OUT_DONE_CH3_INT_ST_S) -#define DMA2D_OUT_DONE_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUT_DONE_CH3_INT_ST_S 0 -/** DMA2D_OUT_EOF_CH3_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH3_INT_ST (BIT(1)) -#define DMA2D_OUT_EOF_CH3_INT_ST_M (DMA2D_OUT_EOF_CH3_INT_ST_V << DMA2D_OUT_EOF_CH3_INT_ST_S) -#define DMA2D_OUT_EOF_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUT_EOF_CH3_INT_ST_S 1 -/** DMA2D_OUT_DSCR_ERR_CH3_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_M (DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S 12 - -/** DMA2D_OUT_INT_CLR_CH3_REG register - * Interrupt clear bits of TX channel 3 - */ -#define DMA2D_OUT_INT_CLR_CH3_REG (DR_REG_DMA2D_BASE + 0x310) -/** DMA2D_OUT_DONE_CH3_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH3_INT_CLR (BIT(0)) -#define DMA2D_OUT_DONE_CH3_INT_CLR_M (DMA2D_OUT_DONE_CH3_INT_CLR_V << DMA2D_OUT_DONE_CH3_INT_CLR_S) -#define DMA2D_OUT_DONE_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DONE_CH3_INT_CLR_S 0 -/** DMA2D_OUT_EOF_CH3_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH3_INT_CLR (BIT(1)) -#define DMA2D_OUT_EOF_CH3_INT_CLR_M (DMA2D_OUT_EOF_CH3_INT_CLR_V << DMA2D_OUT_EOF_CH3_INT_CLR_S) -#define DMA2D_OUT_EOF_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUT_EOF_CH3_INT_CLR_S 1 -/** DMA2D_OUT_DSCR_ERR_CH3_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_M (DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S 12 - -/** DMA2D_OUTFIFO_STATUS_CH3_REG register - * Represents the status of the tx fifo of channel 3 - */ -#define DMA2D_OUTFIFO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x314) -/** DMA2D_OUTFIFO_FULL_L2_CH3 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L2_CH3 (BIT(0)) -#define DMA2D_OUTFIFO_FULL_L2_CH3_M (DMA2D_OUTFIFO_FULL_L2_CH3_V << DMA2D_OUTFIFO_FULL_L2_CH3_S) -#define DMA2D_OUTFIFO_FULL_L2_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L2_CH3_S 0 -/** DMA2D_OUTFIFO_EMPTY_L2_CH3 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L2_CH3 (BIT(1)) -#define DMA2D_OUTFIFO_EMPTY_L2_CH3_M (DMA2D_OUTFIFO_EMPTY_L2_CH3_V << DMA2D_OUTFIFO_EMPTY_L2_CH3_S) -#define DMA2D_OUTFIFO_EMPTY_L2_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L2_CH3_S 1 -/** DMA2D_OUTFIFO_CNT_L2_CH3 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L2_CH3 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH3_M (DMA2D_OUTFIFO_CNT_L2_CH3_V << DMA2D_OUTFIFO_CNT_L2_CH3_S) -#define DMA2D_OUTFIFO_CNT_L2_CH3_V 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH3_S 2 -/** DMA2D_OUT_REMAIN_UNDER_1B_CH3 : RO; bitpos: [7]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_1B_CH3 (BIT(7)) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_M (DMA2D_OUT_REMAIN_UNDER_1B_CH3_V << DMA2D_OUT_REMAIN_UNDER_1B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_S 7 -/** DMA2D_OUT_REMAIN_UNDER_2B_CH3 : RO; bitpos: [8]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_2B_CH3 (BIT(8)) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_M (DMA2D_OUT_REMAIN_UNDER_2B_CH3_V << DMA2D_OUT_REMAIN_UNDER_2B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_S 8 -/** DMA2D_OUT_REMAIN_UNDER_3B_CH3 : RO; bitpos: [9]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_3B_CH3 (BIT(9)) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_M (DMA2D_OUT_REMAIN_UNDER_3B_CH3_V << DMA2D_OUT_REMAIN_UNDER_3B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_S 9 -/** DMA2D_OUT_REMAIN_UNDER_4B_CH3 : RO; bitpos: [10]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_4B_CH3 (BIT(10)) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_M (DMA2D_OUT_REMAIN_UNDER_4B_CH3_V << DMA2D_OUT_REMAIN_UNDER_4B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_S 10 -/** DMA2D_OUT_REMAIN_UNDER_5B_CH3 : RO; bitpos: [11]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_5B_CH3 (BIT(11)) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_M (DMA2D_OUT_REMAIN_UNDER_5B_CH3_V << DMA2D_OUT_REMAIN_UNDER_5B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_S 11 -/** DMA2D_OUT_REMAIN_UNDER_6B_CH3 : RO; bitpos: [12]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_6B_CH3 (BIT(12)) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_M (DMA2D_OUT_REMAIN_UNDER_6B_CH3_V << DMA2D_OUT_REMAIN_UNDER_6B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_S 12 -/** DMA2D_OUT_REMAIN_UNDER_7B_CH3 : RO; bitpos: [13]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_7B_CH3 (BIT(13)) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_M (DMA2D_OUT_REMAIN_UNDER_7B_CH3_V << DMA2D_OUT_REMAIN_UNDER_7B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_S 13 -/** DMA2D_OUT_REMAIN_UNDER_8B_CH3 : RO; bitpos: [14]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_8B_CH3 (BIT(14)) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_M (DMA2D_OUT_REMAIN_UNDER_8B_CH3_V << DMA2D_OUT_REMAIN_UNDER_8B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_S 14 -/** DMA2D_OUTFIFO_FULL_L1_CH3 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L1_CH3 (BIT(15)) -#define DMA2D_OUTFIFO_FULL_L1_CH3_M (DMA2D_OUTFIFO_FULL_L1_CH3_V << DMA2D_OUTFIFO_FULL_L1_CH3_S) -#define DMA2D_OUTFIFO_FULL_L1_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L1_CH3_S 15 -/** DMA2D_OUTFIFO_EMPTY_L1_CH3 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L1_CH3 (BIT(16)) -#define DMA2D_OUTFIFO_EMPTY_L1_CH3_M (DMA2D_OUTFIFO_EMPTY_L1_CH3_V << DMA2D_OUTFIFO_EMPTY_L1_CH3_S) -#define DMA2D_OUTFIFO_EMPTY_L1_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L1_CH3_S 16 -/** DMA2D_OUTFIFO_CNT_L1_CH3 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L1_CH3 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH3_M (DMA2D_OUTFIFO_CNT_L1_CH3_V << DMA2D_OUTFIFO_CNT_L1_CH3_S) -#define DMA2D_OUTFIFO_CNT_L1_CH3_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH3_S 17 -/** DMA2D_OUTFIFO_FULL_L3_CH3 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L3_CH3 (BIT(22)) -#define DMA2D_OUTFIFO_FULL_L3_CH3_M (DMA2D_OUTFIFO_FULL_L3_CH3_V << DMA2D_OUTFIFO_FULL_L3_CH3_S) -#define DMA2D_OUTFIFO_FULL_L3_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L3_CH3_S 22 -/** DMA2D_OUTFIFO_EMPTY_L3_CH3 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L3_CH3 (BIT(23)) -#define DMA2D_OUTFIFO_EMPTY_L3_CH3_M (DMA2D_OUTFIFO_EMPTY_L3_CH3_V << DMA2D_OUTFIFO_EMPTY_L3_CH3_S) -#define DMA2D_OUTFIFO_EMPTY_L3_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L3_CH3_S 23 -/** DMA2D_OUTFIFO_CNT_L3_CH3 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L3_CH3 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH3_M (DMA2D_OUTFIFO_CNT_L3_CH3_V << DMA2D_OUTFIFO_CNT_L3_CH3_S) -#define DMA2D_OUTFIFO_CNT_L3_CH3_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH3_S 24 - -/** DMA2D_OUT_PUSH_CH3_REG register - * Configures the tx fifo of channel 3 - */ -#define DMA2D_OUT_PUSH_CH3_REG (DR_REG_DMA2D_BASE + 0x318) -/** DMA2D_OUTFIFO_WDATA_CH3 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_WDATA_CH3 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH3_M (DMA2D_OUTFIFO_WDATA_CH3_V << DMA2D_OUTFIFO_WDATA_CH3_S) -#define DMA2D_OUTFIFO_WDATA_CH3_V 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH3_S 0 -/** DMA2D_OUTFIFO_PUSH_CH3 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_PUSH_CH3 (BIT(10)) -#define DMA2D_OUTFIFO_PUSH_CH3_M (DMA2D_OUTFIFO_PUSH_CH3_V << DMA2D_OUTFIFO_PUSH_CH3_S) -#define DMA2D_OUTFIFO_PUSH_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_PUSH_CH3_S 10 - -/** DMA2D_OUT_LINK_CONF_CH3_REG register - * Configures the tx descriptor operations of channel 3 - */ -#define DMA2D_OUT_LINK_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x31c) -/** DMA2D_OUTLINK_STOP_CH3 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_STOP_CH3 (BIT(20)) -#define DMA2D_OUTLINK_STOP_CH3_M (DMA2D_OUTLINK_STOP_CH3_V << DMA2D_OUTLINK_STOP_CH3_S) -#define DMA2D_OUTLINK_STOP_CH3_V 0x00000001U -#define DMA2D_OUTLINK_STOP_CH3_S 20 -/** DMA2D_OUTLINK_START_CH3 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_START_CH3 (BIT(21)) -#define DMA2D_OUTLINK_START_CH3_M (DMA2D_OUTLINK_START_CH3_V << DMA2D_OUTLINK_START_CH3_S) -#define DMA2D_OUTLINK_START_CH3_V 0x00000001U -#define DMA2D_OUTLINK_START_CH3_S 21 -/** DMA2D_OUTLINK_RESTART_CH3 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ -#define DMA2D_OUTLINK_RESTART_CH3 (BIT(22)) -#define DMA2D_OUTLINK_RESTART_CH3_M (DMA2D_OUTLINK_RESTART_CH3_V << DMA2D_OUTLINK_RESTART_CH3_S) -#define DMA2D_OUTLINK_RESTART_CH3_V 0x00000001U -#define DMA2D_OUTLINK_RESTART_CH3_S 22 -/** DMA2D_OUTLINK_PARK_CH3 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ -#define DMA2D_OUTLINK_PARK_CH3 (BIT(23)) -#define DMA2D_OUTLINK_PARK_CH3_M (DMA2D_OUTLINK_PARK_CH3_V << DMA2D_OUTLINK_PARK_CH3_S) -#define DMA2D_OUTLINK_PARK_CH3_V 0x00000001U -#define DMA2D_OUTLINK_PARK_CH3_S 23 - -/** DMA2D_OUT_LINK_ADDR_CH3_REG register - * Configures the tx descriptor address of channel 3 - */ -#define DMA2D_OUT_LINK_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x320) -/** DMA2D_OUTLINK_ADDR_CH3 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ -#define DMA2D_OUTLINK_ADDR_CH3 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH3_M (DMA2D_OUTLINK_ADDR_CH3_V << DMA2D_OUTLINK_ADDR_CH3_S) -#define DMA2D_OUTLINK_ADDR_CH3_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH3_S 0 - -/** DMA2D_OUT_STATE_CH3_REG register - * Represents the working status of the tx descriptor of channel 3 - */ -#define DMA2D_OUT_STATE_CH3_REG (DR_REG_DMA2D_BASE + 0x324) -/** DMA2D_OUTLINK_DSCR_ADDR_CH3 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ -#define DMA2D_OUTLINK_DSCR_ADDR_CH3 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH3_M (DMA2D_OUTLINK_DSCR_ADDR_CH3_V << DMA2D_OUTLINK_DSCR_ADDR_CH3_S) -#define DMA2D_OUTLINK_DSCR_ADDR_CH3_V 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH3_S 0 -/** DMA2D_OUT_DSCR_STATE_CH3 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ -#define DMA2D_OUT_DSCR_STATE_CH3 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH3_M (DMA2D_OUT_DSCR_STATE_CH3_V << DMA2D_OUT_DSCR_STATE_CH3_S) -#define DMA2D_OUT_DSCR_STATE_CH3_V 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH3_S 18 -/** DMA2D_OUT_STATE_CH3 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ -#define DMA2D_OUT_STATE_CH3 0x0000000FU -#define DMA2D_OUT_STATE_CH3_M (DMA2D_OUT_STATE_CH3_V << DMA2D_OUT_STATE_CH3_S) -#define DMA2D_OUT_STATE_CH3_V 0x0000000FU -#define DMA2D_OUT_STATE_CH3_S 20 -/** DMA2D_OUT_RESET_AVAIL_CH3 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_OUT_RESET_AVAIL_CH3 (BIT(24)) -#define DMA2D_OUT_RESET_AVAIL_CH3_M (DMA2D_OUT_RESET_AVAIL_CH3_V << DMA2D_OUT_RESET_AVAIL_CH3_S) -#define DMA2D_OUT_RESET_AVAIL_CH3_V 0x00000001U -#define DMA2D_OUT_RESET_AVAIL_CH3_S 24 - -/** DMA2D_OUT_EOF_DES_ADDR_CH3_REG register - * Represents the address associated with the outlink descriptor of channel 3 - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x328) -/** DMA2D_OUT_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH3 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH3_M (DMA2D_OUT_EOF_DES_ADDR_CH3_V << DMA2D_OUT_EOF_DES_ADDR_CH3_S) -#define DMA2D_OUT_EOF_DES_ADDR_CH3_V 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH3_S 0 - -/** DMA2D_OUT_DSCR_CH3_REG register - * Represents the address associated with the outlink descriptor of channel 3 - */ -#define DMA2D_OUT_DSCR_CH3_REG (DR_REG_DMA2D_BASE + 0x32c) -/** DMA2D_OUTLINK_DSCR_CH3 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ -#define DMA2D_OUTLINK_DSCR_CH3 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH3_M (DMA2D_OUTLINK_DSCR_CH3_V << DMA2D_OUTLINK_DSCR_CH3_S) -#define DMA2D_OUTLINK_DSCR_CH3_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH3_S 0 - -/** DMA2D_OUT_DSCR_BF0_CH3_REG register - * Represents the address associated with the outlink descriptor of channel 3 - */ -#define DMA2D_OUT_DSCR_BF0_CH3_REG (DR_REG_DMA2D_BASE + 0x330) -/** DMA2D_OUTLINK_DSCR_BF0_CH3 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ -#define DMA2D_OUTLINK_DSCR_BF0_CH3 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH3_M (DMA2D_OUTLINK_DSCR_BF0_CH3_V << DMA2D_OUTLINK_DSCR_BF0_CH3_S) -#define DMA2D_OUTLINK_DSCR_BF0_CH3_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH3_S 0 - -/** DMA2D_OUT_DSCR_BF1_CH3_REG register - * Represents the address associated with the outlink descriptor of channel 3 - */ -#define DMA2D_OUT_DSCR_BF1_CH3_REG (DR_REG_DMA2D_BASE + 0x334) -/** DMA2D_OUTLINK_DSCR_BF1_CH3 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ -#define DMA2D_OUTLINK_DSCR_BF1_CH3 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH3_M (DMA2D_OUTLINK_DSCR_BF1_CH3_V << DMA2D_OUTLINK_DSCR_BF1_CH3_S) -#define DMA2D_OUTLINK_DSCR_BF1_CH3_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH3_S 0 - -/** DMA2D_OUT_PERI_SEL_CH3_REG register - * Configures the tx peripheral of channel 3 - */ -#define DMA2D_OUT_PERI_SEL_CH3_REG (DR_REG_DMA2D_BASE + 0x338) -/** DMA2D_OUT_PERI_SEL_CH3 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Tx channel 0: jpeg 1: - * display-1 2: display-2 3: display-3 7: no choose - */ -#define DMA2D_OUT_PERI_SEL_CH3 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH3_M (DMA2D_OUT_PERI_SEL_CH3_V << DMA2D_OUT_PERI_SEL_CH3_S) -#define DMA2D_OUT_PERI_SEL_CH3_V 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH3_S 0 - -/** DMA2D_OUT_ARB_CH3_REG register - * Configures the tx arbiter of channel 3 - */ -#define DMA2D_OUT_ARB_CH3_REG (DR_REG_DMA2D_BASE + 0x33c) -/** DMA2D_OUT_ARB_TOKEN_NUM_CH3 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_OUT_ARB_TOKEN_NUM_CH3 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_M (DMA2D_OUT_ARB_TOKEN_NUM_CH3_V << DMA2D_OUT_ARB_TOKEN_NUM_CH3_S) -#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_V 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH3 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_CH3 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH3_M (DMA2D_OUT_ARB_PRIORITY_CH3_V << DMA2D_OUT_ARB_PRIORITY_CH3_S) -#define DMA2D_OUT_ARB_PRIORITY_CH3_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH3_S 4 -/** DMA2D_OUT_ARB_PRIORITY_H_CH3 : R/W; bitpos: [7:6]; default: 0; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_H_CH3 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH3_M (DMA2D_OUT_ARB_PRIORITY_H_CH3_V << DMA2D_OUT_ARB_PRIORITY_H_CH3_S) -#define DMA2D_OUT_ARB_PRIORITY_H_CH3_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH3_S 6 - -/** DMA2D_OUT_RO_STATUS_CH3_REG register - * Represents the status of the tx reorder module of channel 3 - */ -#define DMA2D_OUT_RO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x340) -/** DMA2D_OUTFIFO_RO_CNT_CH3 : RO; bitpos: [5:0]; default: 0; - * The register stores the byte number of the data in color convert Tx FIFO for - * channel 0. - */ -#define DMA2D_OUTFIFO_RO_CNT_CH3 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH3_M (DMA2D_OUTFIFO_RO_CNT_CH3_V << DMA2D_OUTFIFO_RO_CNT_CH3_S) -#define DMA2D_OUTFIFO_RO_CNT_CH3_V 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH3_S 0 -/** DMA2D_OUT_RO_WR_STATE_CH3 : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_OUT_RO_WR_STATE_CH3 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH3_M (DMA2D_OUT_RO_WR_STATE_CH3_V << DMA2D_OUT_RO_WR_STATE_CH3_S) -#define DMA2D_OUT_RO_WR_STATE_CH3_V 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH3_S 6 -/** DMA2D_OUT_RO_RD_STATE_CH3 : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_OUT_RO_RD_STATE_CH3 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH3_M (DMA2D_OUT_RO_RD_STATE_CH3_V << DMA2D_OUT_RO_RD_STATE_CH3_S) -#define DMA2D_OUT_RO_RD_STATE_CH3_V 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH3_S 8 -/** DMA2D_OUT_PIXEL_BYTE_CH3 : RO; bitpos: [13:10]; default: 0; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_OUT_PIXEL_BYTE_CH3 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH3_M (DMA2D_OUT_PIXEL_BYTE_CH3_V << DMA2D_OUT_PIXEL_BYTE_CH3_S) -#define DMA2D_OUT_PIXEL_BYTE_CH3_V 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH3_S 10 -/** DMA2D_OUT_BURST_BLOCK_NUM_CH3 : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ -#define DMA2D_OUT_BURST_BLOCK_NUM_CH3 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_M (DMA2D_OUT_BURST_BLOCK_NUM_CH3_V << DMA2D_OUT_BURST_BLOCK_NUM_CH3_S) -#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_V 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_S 14 - -/** DMA2D_OUT_COLOR_CONVERT_CH3_REG register - * Configures the tx color convert of channel 3 - */ -#define DMA2D_OUT_COLOR_CONVERT_CH3_REG (DR_REG_DMA2D_BASE + 0x348) -/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * YUV444 to YUV422 2: output directly - */ -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_M (DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S) -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S 0 -/** DMA2D_OUT_COLOR_3B_PROC_EN_CH3 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3 (BIT(2)) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_M (DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V 0x00000001U -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S 2 -/** DMA2D_OUT_COLOR_INPUT_SEL_CH3 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: RGB565 to RGB888 1: - * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: - * disable color space convert - */ -#define DMA2D_OUT_COLOR_INPUT_SEL_CH3 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_M (DMA2D_OUT_COLOR_INPUT_SEL_CH3_V << DMA2D_OUT_COLOR_INPUT_SEL_CH3_S) -#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_V 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_S 3 - -/** DMA2D_OUT_SCRAMBLE_CH3_REG register - * Configures the tx scramble of channel 3 - */ -#define DMA2D_OUT_SCRAMBLE_CH3_REG (DR_REG_DMA2D_BASE + 0x34c) -/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_M (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S) -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM0_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM0_CH3_REG (DR_REG_DMA2D_BASE + 0x350) -/** DMA2D_OUT_COLOR_PARAM_H0_CH3 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H0_CH3 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH3_M (DMA2D_OUT_COLOR_PARAM_H0_CH3_V << DMA2D_OUT_COLOR_PARAM_H0_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_H0_CH3_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM1_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM1_CH3_REG (DR_REG_DMA2D_BASE + 0x354) -/** DMA2D_OUT_COLOR_PARAM_H1_CH3 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H1_CH3 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH3_M (DMA2D_OUT_COLOR_PARAM_H1_CH3_V << DMA2D_OUT_COLOR_PARAM_H1_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_H1_CH3_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM2_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM2_CH3_REG (DR_REG_DMA2D_BASE + 0x358) -/** DMA2D_OUT_COLOR_PARAM_M0_CH3 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M0_CH3 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH3_M (DMA2D_OUT_COLOR_PARAM_M0_CH3_V << DMA2D_OUT_COLOR_PARAM_M0_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_M0_CH3_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM3_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM3_CH3_REG (DR_REG_DMA2D_BASE + 0x35c) -/** DMA2D_OUT_COLOR_PARAM_M1_CH3 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M1_CH3 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH3_M (DMA2D_OUT_COLOR_PARAM_M1_CH3_V << DMA2D_OUT_COLOR_PARAM_M1_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_M1_CH3_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM4_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM4_CH3_REG (DR_REG_DMA2D_BASE + 0x360) -/** DMA2D_OUT_COLOR_PARAM_L0_CH3 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L0_CH3 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH3_M (DMA2D_OUT_COLOR_PARAM_L0_CH3_V << DMA2D_OUT_COLOR_PARAM_L0_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_L0_CH3_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM5_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM5_CH3_REG (DR_REG_DMA2D_BASE + 0x364) -/** DMA2D_OUT_COLOR_PARAM_L1_CH3 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L1_CH3 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH3_M (DMA2D_OUT_COLOR_PARAM_L1_CH3_V << DMA2D_OUT_COLOR_PARAM_L1_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_L1_CH3_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH3_S 0 - -/** DMA2D_OUT_ETM_CONF_CH3_REG register - * Configures the tx etm of channel 3 - */ -#define DMA2D_OUT_ETM_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x368) -/** DMA2D_OUT_ETM_EN_CH3 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_EN_CH3 (BIT(0)) -#define DMA2D_OUT_ETM_EN_CH3_M (DMA2D_OUT_ETM_EN_CH3_V << DMA2D_OUT_ETM_EN_CH3_S) -#define DMA2D_OUT_ETM_EN_CH3_V 0x00000001U -#define DMA2D_OUT_ETM_EN_CH3_S 0 -/** DMA2D_OUT_ETM_LOOP_EN_CH3 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_LOOP_EN_CH3 (BIT(1)) -#define DMA2D_OUT_ETM_LOOP_EN_CH3_M (DMA2D_OUT_ETM_LOOP_EN_CH3_V << DMA2D_OUT_ETM_LOOP_EN_CH3_S) -#define DMA2D_OUT_ETM_LOOP_EN_CH3_V 0x00000001U -#define DMA2D_OUT_ETM_LOOP_EN_CH3_S 1 -/** DMA2D_OUT_DSCR_TASK_MAK_CH3 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_OUT_DSCR_TASK_MAK_CH3 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH3_M (DMA2D_OUT_DSCR_TASK_MAK_CH3_V << DMA2D_OUT_DSCR_TASK_MAK_CH3_S) -#define DMA2D_OUT_DSCR_TASK_MAK_CH3_V 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH3_S 2 - -/** DMA2D_OUT_DSCR_PORT_BLK_CH3_REG register - * Configures the tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_CH3_REG (DR_REG_DMA2D_BASE + 0x36c) -/** DMA2D_OUT_DSCR_PORT_BLK_H_CH3 : R/W; bitpos: [13:0]; default: 18; - * Set the vertical height of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_M (DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S) -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S 0 -/** DMA2D_OUT_DSCR_PORT_BLK_V_CH3 : R/W; bitpos: [27:14]; default: 18; - * Set the horizontal width of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_M (DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S) -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S 14 - -/** DMA2D_IN_CONF0_CH0_REG register - * Configures the rx direction of channel 0 - */ -#define DMA2D_IN_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x500) -/** DMA2D_IN_MEM_TRANS_EN_CH0 : R/W; bitpos: [0]; default: 0; - * enable memory trans of the same channel - */ -#define DMA2D_IN_MEM_TRANS_EN_CH0 (BIT(0)) -#define DMA2D_IN_MEM_TRANS_EN_CH0_M (DMA2D_IN_MEM_TRANS_EN_CH0_V << DMA2D_IN_MEM_TRANS_EN_CH0_S) -#define DMA2D_IN_MEM_TRANS_EN_CH0_V 0x00000001U -#define DMA2D_IN_MEM_TRANS_EN_CH0_S 0 -/** DMA2D_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ -#define DMA2D_INDSCR_BURST_EN_CH0 (BIT(2)) -#define DMA2D_INDSCR_BURST_EN_CH0_M (DMA2D_INDSCR_BURST_EN_CH0_V << DMA2D_INDSCR_BURST_EN_CH0_S) -#define DMA2D_INDSCR_BURST_EN_CH0_V 0x00000001U -#define DMA2D_INDSCR_BURST_EN_CH0_S 2 -/** DMA2D_IN_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_IN_ECC_AES_EN_CH0 (BIT(3)) -#define DMA2D_IN_ECC_AES_EN_CH0_M (DMA2D_IN_ECC_AES_EN_CH0_V << DMA2D_IN_ECC_AES_EN_CH0_S) -#define DMA2D_IN_ECC_AES_EN_CH0_V 0x00000001U -#define DMA2D_IN_ECC_AES_EN_CH0_S 3 -/** DMA2D_IN_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_IN_CHECK_OWNER_CH0 (BIT(4)) -#define DMA2D_IN_CHECK_OWNER_CH0_M (DMA2D_IN_CHECK_OWNER_CH0_V << DMA2D_IN_CHECK_OWNER_CH0_S) -#define DMA2D_IN_CHECK_OWNER_CH0_V 0x00000001U -#define DMA2D_IN_CHECK_OWNER_CH0_S 4 -/** DMA2D_IN_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_IN_LOOP_TEST_CH0 (BIT(5)) -#define DMA2D_IN_LOOP_TEST_CH0_M (DMA2D_IN_LOOP_TEST_CH0_V << DMA2D_IN_LOOP_TEST_CH0_S) -#define DMA2D_IN_LOOP_TEST_CH0_V 0x00000001U -#define DMA2D_IN_LOOP_TEST_CH0_S 5 -/** DMA2D_IN_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_IN_MEM_BURST_LENGTH_CH0 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH0_M (DMA2D_IN_MEM_BURST_LENGTH_CH0_V << DMA2D_IN_MEM_BURST_LENGTH_CH0_S) -#define DMA2D_IN_MEM_BURST_LENGTH_CH0_V 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH0_S 6 -/** DMA2D_IN_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0; - * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S) -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S 9 -/** DMA2D_IN_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_IN_DSCR_PORT_EN_CH0 (BIT(11)) -#define DMA2D_IN_DSCR_PORT_EN_CH0_M (DMA2D_IN_DSCR_PORT_EN_CH0_V << DMA2D_IN_DSCR_PORT_EN_CH0_S) -#define DMA2D_IN_DSCR_PORT_EN_CH0_V 0x00000001U -#define DMA2D_IN_DSCR_PORT_EN_CH0_S 11 -/** DMA2D_IN_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ -#define DMA2D_IN_PAGE_BOUND_EN_CH0 (BIT(12)) -#define DMA2D_IN_PAGE_BOUND_EN_CH0_M (DMA2D_IN_PAGE_BOUND_EN_CH0_V << DMA2D_IN_PAGE_BOUND_EN_CH0_S) -#define DMA2D_IN_PAGE_BOUND_EN_CH0_V 0x00000001U -#define DMA2D_IN_PAGE_BOUND_EN_CH0_S 12 -/** DMA2D_IN_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0; - * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_IN_REORDER_EN_CH0 (BIT(16)) -#define DMA2D_IN_REORDER_EN_CH0_M (DMA2D_IN_REORDER_EN_CH0_V << DMA2D_IN_REORDER_EN_CH0_S) -#define DMA2D_IN_REORDER_EN_CH0_V 0x00000001U -#define DMA2D_IN_REORDER_EN_CH0_S 16 -/** DMA2D_IN_RST_CH0 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ -#define DMA2D_IN_RST_CH0 (BIT(24)) -#define DMA2D_IN_RST_CH0_M (DMA2D_IN_RST_CH0_V << DMA2D_IN_RST_CH0_S) -#define DMA2D_IN_RST_CH0_V 0x00000001U -#define DMA2D_IN_RST_CH0_S 24 -/** DMA2D_IN_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_IN_CMD_DISABLE_CH0 (BIT(25)) -#define DMA2D_IN_CMD_DISABLE_CH0_M (DMA2D_IN_CMD_DISABLE_CH0_V << DMA2D_IN_CMD_DISABLE_CH0_S) -#define DMA2D_IN_CMD_DISABLE_CH0_V 0x00000001U -#define DMA2D_IN_CMD_DISABLE_CH0_S 25 -/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0 (BIT(26)) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S 26 - -/** DMA2D_IN_INT_RAW_CH0_REG register - * Raw interrupt status of RX channel 0 - */ -#define DMA2D_IN_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x504) -/** DMA2D_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 0. - */ -#define DMA2D_IN_DONE_CH0_INT_RAW (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_RAW_M (DMA2D_IN_DONE_CH0_INT_RAW_V << DMA2D_IN_DONE_CH0_INT_RAW_S) -#define DMA2D_IN_DONE_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_RAW_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 0. - */ -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_M (DMA2D_IN_SUC_EOF_CH0_INT_RAW_V << DMA2D_IN_SUC_EOF_CH0_INT_RAW_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_M (DMA2D_IN_ERR_EOF_CH0_INT_RAW_V << DMA2D_IN_ERR_EOF_CH0_INT_RAW_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 0. - */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S 13 - -/** DMA2D_IN_INT_ENA_CH0_REG register - * Interrupt enable bits of RX channel 0 - */ -#define DMA2D_IN_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x508) -/** DMA2D_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH0_INT_ENA (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_ENA_M (DMA2D_IN_DONE_CH0_INT_ENA_V << DMA2D_IN_DONE_CH0_INT_ENA_S) -#define DMA2D_IN_DONE_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_ENA_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_M (DMA2D_IN_SUC_EOF_CH0_INT_ENA_V << DMA2D_IN_SUC_EOF_CH0_INT_ENA_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_M (DMA2D_IN_ERR_EOF_CH0_INT_ENA_V << DMA2D_IN_ERR_EOF_CH0_INT_ENA_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S 13 - -/** DMA2D_IN_INT_ST_CH0_REG register - * Masked interrupt status of RX channel 0 - */ -#define DMA2D_IN_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0x50c) -/** DMA2D_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH0_INT_ST (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_ST_M (DMA2D_IN_DONE_CH0_INT_ST_V << DMA2D_IN_DONE_CH0_INT_ST_S) -#define DMA2D_IN_DONE_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_ST_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH0_INT_ST (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_ST_M (DMA2D_IN_SUC_EOF_CH0_INT_ST_V << DMA2D_IN_SUC_EOF_CH0_INT_ST_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_ST_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH0_INT_ST (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_ST_M (DMA2D_IN_ERR_EOF_CH0_INT_ST_V << DMA2D_IN_ERR_EOF_CH0_INT_ST_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_ST_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_M (DMA2D_IN_DSCR_ERR_CH0_INT_ST_V << DMA2D_IN_DSCR_ERR_CH0_INT_ST_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S 13 - -/** DMA2D_IN_INT_CLR_CH0_REG register - * Interrupt clear bits of RX channel 0 - */ -#define DMA2D_IN_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x510) -/** DMA2D_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH0_INT_CLR (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_CLR_M (DMA2D_IN_DONE_CH0_INT_CLR_V << DMA2D_IN_DONE_CH0_INT_CLR_S) -#define DMA2D_IN_DONE_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_CLR_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_M (DMA2D_IN_SUC_EOF_CH0_INT_CLR_V << DMA2D_IN_SUC_EOF_CH0_INT_CLR_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_M (DMA2D_IN_ERR_EOF_CH0_INT_CLR_V << DMA2D_IN_ERR_EOF_CH0_INT_CLR_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S 13 - -/** DMA2D_INFIFO_STATUS_CH0_REG register - * Represents the status of the rx fifo of channel 0 - */ -#define DMA2D_INFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x514) -/** DMA2D_INFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ -#define DMA2D_INFIFO_FULL_L2_CH0 (BIT(0)) -#define DMA2D_INFIFO_FULL_L2_CH0_M (DMA2D_INFIFO_FULL_L2_CH0_V << DMA2D_INFIFO_FULL_L2_CH0_S) -#define DMA2D_INFIFO_FULL_L2_CH0_V 0x00000001U -#define DMA2D_INFIFO_FULL_L2_CH0_S 0 -/** DMA2D_INFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ -#define DMA2D_INFIFO_EMPTY_L2_CH0 (BIT(1)) -#define DMA2D_INFIFO_EMPTY_L2_CH0_M (DMA2D_INFIFO_EMPTY_L2_CH0_V << DMA2D_INFIFO_EMPTY_L2_CH0_S) -#define DMA2D_INFIFO_EMPTY_L2_CH0_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L2_CH0_S 1 -/** DMA2D_INFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ -#define DMA2D_INFIFO_CNT_L2_CH0 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH0_M (DMA2D_INFIFO_CNT_L2_CH0_V << DMA2D_INFIFO_CNT_L2_CH0_S) -#define DMA2D_INFIFO_CNT_L2_CH0_V 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH0_S 2 -/** DMA2D_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_1B_CH0 (BIT(7)) -#define DMA2D_IN_REMAIN_UNDER_1B_CH0_M (DMA2D_IN_REMAIN_UNDER_1B_CH0_V << DMA2D_IN_REMAIN_UNDER_1B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_1B_CH0_S 7 -/** DMA2D_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_2B_CH0 (BIT(8)) -#define DMA2D_IN_REMAIN_UNDER_2B_CH0_M (DMA2D_IN_REMAIN_UNDER_2B_CH0_V << DMA2D_IN_REMAIN_UNDER_2B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_2B_CH0_S 8 -/** DMA2D_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_3B_CH0 (BIT(9)) -#define DMA2D_IN_REMAIN_UNDER_3B_CH0_M (DMA2D_IN_REMAIN_UNDER_3B_CH0_V << DMA2D_IN_REMAIN_UNDER_3B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_3B_CH0_S 9 -/** DMA2D_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_4B_CH0 (BIT(10)) -#define DMA2D_IN_REMAIN_UNDER_4B_CH0_M (DMA2D_IN_REMAIN_UNDER_4B_CH0_V << DMA2D_IN_REMAIN_UNDER_4B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_4B_CH0_S 10 -/** DMA2D_IN_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_5B_CH0 (BIT(11)) -#define DMA2D_IN_REMAIN_UNDER_5B_CH0_M (DMA2D_IN_REMAIN_UNDER_5B_CH0_V << DMA2D_IN_REMAIN_UNDER_5B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_5B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_5B_CH0_S 11 -/** DMA2D_IN_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_6B_CH0 (BIT(12)) -#define DMA2D_IN_REMAIN_UNDER_6B_CH0_M (DMA2D_IN_REMAIN_UNDER_6B_CH0_V << DMA2D_IN_REMAIN_UNDER_6B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_6B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_6B_CH0_S 12 -/** DMA2D_IN_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_7B_CH0 (BIT(13)) -#define DMA2D_IN_REMAIN_UNDER_7B_CH0_M (DMA2D_IN_REMAIN_UNDER_7B_CH0_V << DMA2D_IN_REMAIN_UNDER_7B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_7B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_7B_CH0_S 13 -/** DMA2D_IN_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_8B_CH0 (BIT(14)) -#define DMA2D_IN_REMAIN_UNDER_8B_CH0_M (DMA2D_IN_REMAIN_UNDER_8B_CH0_V << DMA2D_IN_REMAIN_UNDER_8B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_8B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_8B_CH0_S 14 -/** DMA2D_INFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L1_CH0 (BIT(15)) -#define DMA2D_INFIFO_FULL_L1_CH0_M (DMA2D_INFIFO_FULL_L1_CH0_V << DMA2D_INFIFO_FULL_L1_CH0_S) -#define DMA2D_INFIFO_FULL_L1_CH0_V 0x00000001U -#define DMA2D_INFIFO_FULL_L1_CH0_S 15 -/** DMA2D_INFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L1_CH0 (BIT(16)) -#define DMA2D_INFIFO_EMPTY_L1_CH0_M (DMA2D_INFIFO_EMPTY_L1_CH0_V << DMA2D_INFIFO_EMPTY_L1_CH0_S) -#define DMA2D_INFIFO_EMPTY_L1_CH0_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L1_CH0_S 16 -/** DMA2D_INFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L1_CH0 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH0_M (DMA2D_INFIFO_CNT_L1_CH0_V << DMA2D_INFIFO_CNT_L1_CH0_S) -#define DMA2D_INFIFO_CNT_L1_CH0_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH0_S 17 -/** DMA2D_INFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L3_CH0 (BIT(22)) -#define DMA2D_INFIFO_FULL_L3_CH0_M (DMA2D_INFIFO_FULL_L3_CH0_V << DMA2D_INFIFO_FULL_L3_CH0_S) -#define DMA2D_INFIFO_FULL_L3_CH0_V 0x00000001U -#define DMA2D_INFIFO_FULL_L3_CH0_S 22 -/** DMA2D_INFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L3_CH0 (BIT(23)) -#define DMA2D_INFIFO_EMPTY_L3_CH0_M (DMA2D_INFIFO_EMPTY_L3_CH0_V << DMA2D_INFIFO_EMPTY_L3_CH0_S) -#define DMA2D_INFIFO_EMPTY_L3_CH0_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L3_CH0_S 23 -/** DMA2D_INFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L3_CH0 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH0_M (DMA2D_INFIFO_CNT_L3_CH0_V << DMA2D_INFIFO_CNT_L3_CH0_S) -#define DMA2D_INFIFO_CNT_L3_CH0_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH0_S 24 - -/** DMA2D_IN_POP_CH0_REG register - * Configures the rx fifo of channel 0 - */ -#define DMA2D_IN_POP_CH0_REG (DR_REG_DMA2D_BASE + 0x518) -/** DMA2D_INFIFO_RDATA_CH0 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_RDATA_CH0 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH0_M (DMA2D_INFIFO_RDATA_CH0_V << DMA2D_INFIFO_RDATA_CH0_S) -#define DMA2D_INFIFO_RDATA_CH0_V 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH0_S 0 -/** DMA2D_INFIFO_POP_CH0 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_POP_CH0 (BIT(11)) -#define DMA2D_INFIFO_POP_CH0_M (DMA2D_INFIFO_POP_CH0_V << DMA2D_INFIFO_POP_CH0_S) -#define DMA2D_INFIFO_POP_CH0_V 0x00000001U -#define DMA2D_INFIFO_POP_CH0_S 11 - -/** DMA2D_IN_LINK_CONF_CH0_REG register - * Configures the rx descriptor operations of channel 0 - */ -#define DMA2D_IN_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x51c) -/** DMA2D_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ -#define DMA2D_INLINK_AUTO_RET_CH0 (BIT(20)) -#define DMA2D_INLINK_AUTO_RET_CH0_M (DMA2D_INLINK_AUTO_RET_CH0_V << DMA2D_INLINK_AUTO_RET_CH0_S) -#define DMA2D_INLINK_AUTO_RET_CH0_V 0x00000001U -#define DMA2D_INLINK_AUTO_RET_CH0_S 20 -/** DMA2D_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_STOP_CH0 (BIT(21)) -#define DMA2D_INLINK_STOP_CH0_M (DMA2D_INLINK_STOP_CH0_V << DMA2D_INLINK_STOP_CH0_S) -#define DMA2D_INLINK_STOP_CH0_V 0x00000001U -#define DMA2D_INLINK_STOP_CH0_S 21 -/** DMA2D_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_START_CH0 (BIT(22)) -#define DMA2D_INLINK_START_CH0_M (DMA2D_INLINK_START_CH0_V << DMA2D_INLINK_START_CH0_S) -#define DMA2D_INLINK_START_CH0_V 0x00000001U -#define DMA2D_INLINK_START_CH0_S 22 -/** DMA2D_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ -#define DMA2D_INLINK_RESTART_CH0 (BIT(23)) -#define DMA2D_INLINK_RESTART_CH0_M (DMA2D_INLINK_RESTART_CH0_V << DMA2D_INLINK_RESTART_CH0_S) -#define DMA2D_INLINK_RESTART_CH0_V 0x00000001U -#define DMA2D_INLINK_RESTART_CH0_S 23 -/** DMA2D_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ -#define DMA2D_INLINK_PARK_CH0 (BIT(24)) -#define DMA2D_INLINK_PARK_CH0_M (DMA2D_INLINK_PARK_CH0_V << DMA2D_INLINK_PARK_CH0_S) -#define DMA2D_INLINK_PARK_CH0_V 0x00000001U -#define DMA2D_INLINK_PARK_CH0_S 24 - -/** DMA2D_IN_LINK_ADDR_CH0_REG register - * Configures the rx descriptor address of channel 0 - */ -#define DMA2D_IN_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x520) -/** DMA2D_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ -#define DMA2D_INLINK_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH0_M (DMA2D_INLINK_ADDR_CH0_V << DMA2D_INLINK_ADDR_CH0_S) -#define DMA2D_INLINK_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH0_S 0 - -/** DMA2D_IN_STATE_CH0_REG register - * Represents the working status of the rx descriptor of channel 0 - */ -#define DMA2D_IN_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x524) -/** DMA2D_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ -#define DMA2D_INLINK_DSCR_ADDR_CH0 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH0_M (DMA2D_INLINK_DSCR_ADDR_CH0_V << DMA2D_INLINK_DSCR_ADDR_CH0_S) -#define DMA2D_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH0_S 0 -/** DMA2D_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * reserved - */ -#define DMA2D_IN_DSCR_STATE_CH0 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH0_M (DMA2D_IN_DSCR_STATE_CH0_V << DMA2D_IN_DSCR_STATE_CH0_S) -#define DMA2D_IN_DSCR_STATE_CH0_V 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH0_S 18 -/** DMA2D_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; - * reserved - */ -#define DMA2D_IN_STATE_CH0 0x00000007U -#define DMA2D_IN_STATE_CH0_M (DMA2D_IN_STATE_CH0_V << DMA2D_IN_STATE_CH0_S) -#define DMA2D_IN_STATE_CH0_V 0x00000007U -#define DMA2D_IN_STATE_CH0_S 20 -/** DMA2D_IN_RESET_AVAIL_CH0 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_IN_RESET_AVAIL_CH0 (BIT(23)) -#define DMA2D_IN_RESET_AVAIL_CH0_M (DMA2D_IN_RESET_AVAIL_CH0_V << DMA2D_IN_RESET_AVAIL_CH0_S) -#define DMA2D_IN_RESET_AVAIL_CH0_V 0x00000001U -#define DMA2D_IN_RESET_AVAIL_CH0_S 23 - -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x528) -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S) -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S 0 - -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x52c) -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S) -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S 0 - -/** DMA2D_IN_DSCR_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x530) -/** DMA2D_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ -#define DMA2D_INLINK_DSCR_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH0_M (DMA2D_INLINK_DSCR_CH0_V << DMA2D_INLINK_DSCR_CH0_S) -#define DMA2D_INLINK_DSCR_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH0_S 0 - -/** DMA2D_IN_DSCR_BF0_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x534) -/** DMA2D_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ -#define DMA2D_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH0_M (DMA2D_INLINK_DSCR_BF0_CH0_V << DMA2D_INLINK_DSCR_BF0_CH0_S) -#define DMA2D_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH0_S 0 - -/** DMA2D_IN_DSCR_BF1_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x538) -/** DMA2D_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ -#define DMA2D_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH0_M (DMA2D_INLINK_DSCR_BF1_CH0_V << DMA2D_INLINK_DSCR_BF1_CH0_S) -#define DMA2D_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH0_S 0 - -/** DMA2D_IN_PERI_SEL_CH0_REG register - * Configures the rx peripheral of channel 0 - */ -#define DMA2D_IN_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x53c) -/** DMA2D_IN_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Rx channel 0: jpeg 1: - * display-1 2: display-2 7: no choose - */ -#define DMA2D_IN_PERI_SEL_CH0 0x00000007U -#define DMA2D_IN_PERI_SEL_CH0_M (DMA2D_IN_PERI_SEL_CH0_V << DMA2D_IN_PERI_SEL_CH0_S) -#define DMA2D_IN_PERI_SEL_CH0_V 0x00000007U -#define DMA2D_IN_PERI_SEL_CH0_S 0 - -/** DMA2D_IN_ARB_CH0_REG register - * Configures the rx arbiter of channel 0 - */ -#define DMA2D_IN_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x540) -/** DMA2D_IN_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_IN_ARB_TOKEN_NUM_CH0 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH0_M (DMA2D_IN_ARB_TOKEN_NUM_CH0_V << DMA2D_IN_ARB_TOKEN_NUM_CH0_S) -#define DMA2D_IN_ARB_TOKEN_NUM_CH0_V 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH0_S 0 -/** DMA2D_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_CH0 (BIT(4)) -#define DMA2D_IN_ARB_PRIORITY_CH0_M (DMA2D_IN_ARB_PRIORITY_CH0_V << DMA2D_IN_ARB_PRIORITY_CH0_S) -#define DMA2D_IN_ARB_PRIORITY_CH0_V 0x00000001U -#define DMA2D_IN_ARB_PRIORITY_CH0_S 4 -/** DMA2D_IN_ARB_PRIORITY_H_CH0 : R/W; bitpos: [7:5]; default: 0; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_H_CH0 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH0_M (DMA2D_IN_ARB_PRIORITY_H_CH0_V << DMA2D_IN_ARB_PRIORITY_H_CH0_S) -#define DMA2D_IN_ARB_PRIORITY_H_CH0_V 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH0_S 5 - -/** DMA2D_IN_RO_STATUS_CH0_REG register - * Represents the status of the rx reorder module of channel 0 - */ -#define DMA2D_IN_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x544) -/** DMA2D_INFIFO_RO_CNT_CH0 : RO; bitpos: [4:0]; default: 0; - * The register stores the byte number of the data in color convert Rx FIFO for - * channel 0. - */ -#define DMA2D_INFIFO_RO_CNT_CH0 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH0_M (DMA2D_INFIFO_RO_CNT_CH0_V << DMA2D_INFIFO_RO_CNT_CH0_S) -#define DMA2D_INFIFO_RO_CNT_CH0_V 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH0_S 0 -/** DMA2D_IN_RO_WR_STATE_CH0 : RO; bitpos: [6:5]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_IN_RO_WR_STATE_CH0 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH0_M (DMA2D_IN_RO_WR_STATE_CH0_V << DMA2D_IN_RO_WR_STATE_CH0_S) -#define DMA2D_IN_RO_WR_STATE_CH0_V 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH0_S 5 -/** DMA2D_IN_RO_RD_STATE_CH0 : RO; bitpos: [8:7]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_IN_RO_RD_STATE_CH0 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH0_M (DMA2D_IN_RO_RD_STATE_CH0_V << DMA2D_IN_RO_RD_STATE_CH0_S) -#define DMA2D_IN_RO_RD_STATE_CH0_V 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH0_S 7 -/** DMA2D_IN_PIXEL_BYTE_CH0 : RO; bitpos: [12:9]; default: 0; - * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_IN_PIXEL_BYTE_CH0 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH0_M (DMA2D_IN_PIXEL_BYTE_CH0_V << DMA2D_IN_PIXEL_BYTE_CH0_S) -#define DMA2D_IN_PIXEL_BYTE_CH0_V 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH0_S 9 -/** DMA2D_IN_BURST_BLOCK_NUM_CH0 : RO; bitpos: [16:13]; default: 0; - * the number of macro blocks contained in a burst of data at RX channel - */ -#define DMA2D_IN_BURST_BLOCK_NUM_CH0 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH0_M (DMA2D_IN_BURST_BLOCK_NUM_CH0_V << DMA2D_IN_BURST_BLOCK_NUM_CH0_S) -#define DMA2D_IN_BURST_BLOCK_NUM_CH0_V 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH0_S 13 - -/** DMA2D_IN_RO_PD_CONF_CH0_REG register - * Configures the rx reorder memory of channel 0 - */ -#define DMA2D_IN_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x548) -/** DMA2D_IN_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0 (BIT(4)) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_M (DMA2D_IN_RO_RAM_FORCE_PD_CH0_V << DMA2D_IN_RO_RAM_FORCE_PD_CH0_S) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_S 4 -/** DMA2D_IN_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0 (BIT(5)) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_M (DMA2D_IN_RO_RAM_FORCE_PU_CH0_V << DMA2D_IN_RO_RAM_FORCE_PU_CH0_S) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_S 5 -/** DMA2D_IN_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ -#define DMA2D_IN_RO_RAM_CLK_FO_CH0 (BIT(6)) -#define DMA2D_IN_RO_RAM_CLK_FO_CH0_M (DMA2D_IN_RO_RAM_CLK_FO_CH0_V << DMA2D_IN_RO_RAM_CLK_FO_CH0_S) -#define DMA2D_IN_RO_RAM_CLK_FO_CH0_V 0x00000001U -#define DMA2D_IN_RO_RAM_CLK_FO_CH0_S 6 - -/** DMA2D_IN_COLOR_CONVERT_CH0_REG register - * Configures the Rx color convert of channel 0 - */ -#define DMA2D_IN_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x54c) -/** DMA2D_IN_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 - */ -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_M (DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S) -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S 0 -/** DMA2D_IN_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0 (BIT(2)) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_M (DMA2D_IN_COLOR_3B_PROC_EN_CH0_V << DMA2D_IN_COLOR_3B_PROC_EN_CH0_S) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_V 0x00000001U -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_S 2 -/** DMA2D_IN_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: YUV422/420 to YUV444 - * 1: YUV422 2: YUV444/420 7: disable color space convert - */ -#define DMA2D_IN_COLOR_INPUT_SEL_CH0 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH0_M (DMA2D_IN_COLOR_INPUT_SEL_CH0_V << DMA2D_IN_COLOR_INPUT_SEL_CH0_S) -#define DMA2D_IN_COLOR_INPUT_SEL_CH0_V 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH0_S 3 - -/** DMA2D_IN_SCRAMBLE_CH0_REG register - * Configures the rx scramble of channel 0 - */ -#define DMA2D_IN_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x550) -/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_M (DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S) -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S 0 -/** DMA2D_IN_SCRAMBLE_SEL_POST_CH0 : R/W; bitpos: [5:3]; default: 0; - * Scramble data after color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : BYTE1-0-2 - * 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_M (DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S) -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S 3 - -/** DMA2D_IN_COLOR_PARAM0_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x554) -/** DMA2D_IN_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H0_CH0 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH0_M (DMA2D_IN_COLOR_PARAM_H0_CH0_V << DMA2D_IN_COLOR_PARAM_H0_CH0_S) -#define DMA2D_IN_COLOR_PARAM_H0_CH0_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM1_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x558) -/** DMA2D_IN_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H1_CH0 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH0_M (DMA2D_IN_COLOR_PARAM_H1_CH0_V << DMA2D_IN_COLOR_PARAM_H1_CH0_S) -#define DMA2D_IN_COLOR_PARAM_H1_CH0_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM2_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x55c) -/** DMA2D_IN_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M0_CH0 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH0_M (DMA2D_IN_COLOR_PARAM_M0_CH0_V << DMA2D_IN_COLOR_PARAM_M0_CH0_S) -#define DMA2D_IN_COLOR_PARAM_M0_CH0_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM3_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x560) -/** DMA2D_IN_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M1_CH0 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH0_M (DMA2D_IN_COLOR_PARAM_M1_CH0_V << DMA2D_IN_COLOR_PARAM_M1_CH0_S) -#define DMA2D_IN_COLOR_PARAM_M1_CH0_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM4_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x564) -/** DMA2D_IN_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L0_CH0 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH0_M (DMA2D_IN_COLOR_PARAM_L0_CH0_V << DMA2D_IN_COLOR_PARAM_L0_CH0_S) -#define DMA2D_IN_COLOR_PARAM_L0_CH0_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM5_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x568) -/** DMA2D_IN_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L1_CH0 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH0_M (DMA2D_IN_COLOR_PARAM_L1_CH0_V << DMA2D_IN_COLOR_PARAM_L1_CH0_S) -#define DMA2D_IN_COLOR_PARAM_L1_CH0_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH0_S 0 - -/** DMA2D_IN_ETM_CONF_CH0_REG register - * Configures the rx etm of channel 0 - */ -#define DMA2D_IN_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x56c) -/** DMA2D_IN_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_EN_CH0 (BIT(0)) -#define DMA2D_IN_ETM_EN_CH0_M (DMA2D_IN_ETM_EN_CH0_V << DMA2D_IN_ETM_EN_CH0_S) -#define DMA2D_IN_ETM_EN_CH0_V 0x00000001U -#define DMA2D_IN_ETM_EN_CH0_S 0 -/** DMA2D_IN_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_LOOP_EN_CH0 (BIT(1)) -#define DMA2D_IN_ETM_LOOP_EN_CH0_M (DMA2D_IN_ETM_LOOP_EN_CH0_V << DMA2D_IN_ETM_LOOP_EN_CH0_S) -#define DMA2D_IN_ETM_LOOP_EN_CH0_V 0x00000001U -#define DMA2D_IN_ETM_LOOP_EN_CH0_S 1 -/** DMA2D_IN_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_IN_DSCR_TASK_MAK_CH0 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH0_M (DMA2D_IN_DSCR_TASK_MAK_CH0_V << DMA2D_IN_DSCR_TASK_MAK_CH0_S) -#define DMA2D_IN_DSCR_TASK_MAK_CH0_V 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH0_S 2 - -/** DMA2D_IN_CONF0_CH1_REG register - * Configures the rx direction of channel 1 - */ -#define DMA2D_IN_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x600) -/** DMA2D_IN_MEM_TRANS_EN_CH1 : R/W; bitpos: [0]; default: 0; - * enable memory trans of the same channel - */ -#define DMA2D_IN_MEM_TRANS_EN_CH1 (BIT(0)) -#define DMA2D_IN_MEM_TRANS_EN_CH1_M (DMA2D_IN_MEM_TRANS_EN_CH1_V << DMA2D_IN_MEM_TRANS_EN_CH1_S) -#define DMA2D_IN_MEM_TRANS_EN_CH1_V 0x00000001U -#define DMA2D_IN_MEM_TRANS_EN_CH1_S 0 -/** DMA2D_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ -#define DMA2D_INDSCR_BURST_EN_CH1 (BIT(2)) -#define DMA2D_INDSCR_BURST_EN_CH1_M (DMA2D_INDSCR_BURST_EN_CH1_V << DMA2D_INDSCR_BURST_EN_CH1_S) -#define DMA2D_INDSCR_BURST_EN_CH1_V 0x00000001U -#define DMA2D_INDSCR_BURST_EN_CH1_S 2 -/** DMA2D_IN_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_IN_ECC_AES_EN_CH1 (BIT(3)) -#define DMA2D_IN_ECC_AES_EN_CH1_M (DMA2D_IN_ECC_AES_EN_CH1_V << DMA2D_IN_ECC_AES_EN_CH1_S) -#define DMA2D_IN_ECC_AES_EN_CH1_V 0x00000001U -#define DMA2D_IN_ECC_AES_EN_CH1_S 3 -/** DMA2D_IN_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_IN_CHECK_OWNER_CH1 (BIT(4)) -#define DMA2D_IN_CHECK_OWNER_CH1_M (DMA2D_IN_CHECK_OWNER_CH1_V << DMA2D_IN_CHECK_OWNER_CH1_S) -#define DMA2D_IN_CHECK_OWNER_CH1_V 0x00000001U -#define DMA2D_IN_CHECK_OWNER_CH1_S 4 -/** DMA2D_IN_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_IN_LOOP_TEST_CH1 (BIT(5)) -#define DMA2D_IN_LOOP_TEST_CH1_M (DMA2D_IN_LOOP_TEST_CH1_V << DMA2D_IN_LOOP_TEST_CH1_S) -#define DMA2D_IN_LOOP_TEST_CH1_V 0x00000001U -#define DMA2D_IN_LOOP_TEST_CH1_S 5 -/** DMA2D_IN_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_IN_MEM_BURST_LENGTH_CH1 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH1_M (DMA2D_IN_MEM_BURST_LENGTH_CH1_V << DMA2D_IN_MEM_BURST_LENGTH_CH1_S) -#define DMA2D_IN_MEM_BURST_LENGTH_CH1_V 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH1_S 6 -/** DMA2D_IN_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0; - * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S) -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S 9 -/** DMA2D_IN_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_IN_DSCR_PORT_EN_CH1 (BIT(11)) -#define DMA2D_IN_DSCR_PORT_EN_CH1_M (DMA2D_IN_DSCR_PORT_EN_CH1_V << DMA2D_IN_DSCR_PORT_EN_CH1_S) -#define DMA2D_IN_DSCR_PORT_EN_CH1_V 0x00000001U -#define DMA2D_IN_DSCR_PORT_EN_CH1_S 11 -/** DMA2D_IN_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ -#define DMA2D_IN_PAGE_BOUND_EN_CH1 (BIT(12)) -#define DMA2D_IN_PAGE_BOUND_EN_CH1_M (DMA2D_IN_PAGE_BOUND_EN_CH1_V << DMA2D_IN_PAGE_BOUND_EN_CH1_S) -#define DMA2D_IN_PAGE_BOUND_EN_CH1_V 0x00000001U -#define DMA2D_IN_PAGE_BOUND_EN_CH1_S 12 -/** DMA2D_IN_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0; - * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_IN_REORDER_EN_CH1 (BIT(16)) -#define DMA2D_IN_REORDER_EN_CH1_M (DMA2D_IN_REORDER_EN_CH1_V << DMA2D_IN_REORDER_EN_CH1_S) -#define DMA2D_IN_REORDER_EN_CH1_V 0x00000001U -#define DMA2D_IN_REORDER_EN_CH1_S 16 -/** DMA2D_IN_RST_CH1 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ -#define DMA2D_IN_RST_CH1 (BIT(24)) -#define DMA2D_IN_RST_CH1_M (DMA2D_IN_RST_CH1_V << DMA2D_IN_RST_CH1_S) -#define DMA2D_IN_RST_CH1_V 0x00000001U -#define DMA2D_IN_RST_CH1_S 24 -/** DMA2D_IN_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_IN_CMD_DISABLE_CH1 (BIT(25)) -#define DMA2D_IN_CMD_DISABLE_CH1_M (DMA2D_IN_CMD_DISABLE_CH1_V << DMA2D_IN_CMD_DISABLE_CH1_S) -#define DMA2D_IN_CMD_DISABLE_CH1_V 0x00000001U -#define DMA2D_IN_CMD_DISABLE_CH1_S 25 -/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1 (BIT(26)) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S 26 - -/** DMA2D_IN_INT_RAW_CH1_REG register - * Raw interrupt status of RX channel 1 - */ -#define DMA2D_IN_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x604) -/** DMA2D_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 0. - */ -#define DMA2D_IN_DONE_CH1_INT_RAW (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_RAW_M (DMA2D_IN_DONE_CH1_INT_RAW_V << DMA2D_IN_DONE_CH1_INT_RAW_S) -#define DMA2D_IN_DONE_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_RAW_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 0. - */ -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_M (DMA2D_IN_SUC_EOF_CH1_INT_RAW_V << DMA2D_IN_SUC_EOF_CH1_INT_RAW_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_M (DMA2D_IN_ERR_EOF_CH1_INT_RAW_V << DMA2D_IN_ERR_EOF_CH1_INT_RAW_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 0. - */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S 13 - -/** DMA2D_IN_INT_ENA_CH1_REG register - * Interrupt enable bits of RX channel 1 - */ -#define DMA2D_IN_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x608) -/** DMA2D_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH1_INT_ENA (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_ENA_M (DMA2D_IN_DONE_CH1_INT_ENA_V << DMA2D_IN_DONE_CH1_INT_ENA_S) -#define DMA2D_IN_DONE_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_ENA_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_M (DMA2D_IN_SUC_EOF_CH1_INT_ENA_V << DMA2D_IN_SUC_EOF_CH1_INT_ENA_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_M (DMA2D_IN_ERR_EOF_CH1_INT_ENA_V << DMA2D_IN_ERR_EOF_CH1_INT_ENA_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S 13 - -/** DMA2D_IN_INT_ST_CH1_REG register - * Masked interrupt status of RX channel 1 - */ -#define DMA2D_IN_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x60c) -/** DMA2D_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH1_INT_ST (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_ST_M (DMA2D_IN_DONE_CH1_INT_ST_V << DMA2D_IN_DONE_CH1_INT_ST_S) -#define DMA2D_IN_DONE_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_ST_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH1_INT_ST (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_ST_M (DMA2D_IN_SUC_EOF_CH1_INT_ST_V << DMA2D_IN_SUC_EOF_CH1_INT_ST_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_ST_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH1_INT_ST (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_ST_M (DMA2D_IN_ERR_EOF_CH1_INT_ST_V << DMA2D_IN_ERR_EOF_CH1_INT_ST_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_ST_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_M (DMA2D_IN_DSCR_ERR_CH1_INT_ST_V << DMA2D_IN_DSCR_ERR_CH1_INT_ST_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S 13 - -/** DMA2D_IN_INT_CLR_CH1_REG register - * Interrupt clear bits of RX channel 1 - */ -#define DMA2D_IN_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x610) -/** DMA2D_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH1_INT_CLR (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_CLR_M (DMA2D_IN_DONE_CH1_INT_CLR_V << DMA2D_IN_DONE_CH1_INT_CLR_S) -#define DMA2D_IN_DONE_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_CLR_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_M (DMA2D_IN_SUC_EOF_CH1_INT_CLR_V << DMA2D_IN_SUC_EOF_CH1_INT_CLR_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_M (DMA2D_IN_ERR_EOF_CH1_INT_CLR_V << DMA2D_IN_ERR_EOF_CH1_INT_CLR_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S 13 - -/** DMA2D_INFIFO_STATUS_CH1_REG register - * Represents the status of the rx fifo of channel 1 - */ -#define DMA2D_INFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x614) -/** DMA2D_INFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ -#define DMA2D_INFIFO_FULL_L2_CH1 (BIT(0)) -#define DMA2D_INFIFO_FULL_L2_CH1_M (DMA2D_INFIFO_FULL_L2_CH1_V << DMA2D_INFIFO_FULL_L2_CH1_S) -#define DMA2D_INFIFO_FULL_L2_CH1_V 0x00000001U -#define DMA2D_INFIFO_FULL_L2_CH1_S 0 -/** DMA2D_INFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ -#define DMA2D_INFIFO_EMPTY_L2_CH1 (BIT(1)) -#define DMA2D_INFIFO_EMPTY_L2_CH1_M (DMA2D_INFIFO_EMPTY_L2_CH1_V << DMA2D_INFIFO_EMPTY_L2_CH1_S) -#define DMA2D_INFIFO_EMPTY_L2_CH1_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L2_CH1_S 1 -/** DMA2D_INFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ -#define DMA2D_INFIFO_CNT_L2_CH1 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH1_M (DMA2D_INFIFO_CNT_L2_CH1_V << DMA2D_INFIFO_CNT_L2_CH1_S) -#define DMA2D_INFIFO_CNT_L2_CH1_V 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH1_S 2 -/** DMA2D_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_1B_CH1 (BIT(7)) -#define DMA2D_IN_REMAIN_UNDER_1B_CH1_M (DMA2D_IN_REMAIN_UNDER_1B_CH1_V << DMA2D_IN_REMAIN_UNDER_1B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_1B_CH1_S 7 -/** DMA2D_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_2B_CH1 (BIT(8)) -#define DMA2D_IN_REMAIN_UNDER_2B_CH1_M (DMA2D_IN_REMAIN_UNDER_2B_CH1_V << DMA2D_IN_REMAIN_UNDER_2B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_2B_CH1_S 8 -/** DMA2D_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_3B_CH1 (BIT(9)) -#define DMA2D_IN_REMAIN_UNDER_3B_CH1_M (DMA2D_IN_REMAIN_UNDER_3B_CH1_V << DMA2D_IN_REMAIN_UNDER_3B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_3B_CH1_S 9 -/** DMA2D_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_4B_CH1 (BIT(10)) -#define DMA2D_IN_REMAIN_UNDER_4B_CH1_M (DMA2D_IN_REMAIN_UNDER_4B_CH1_V << DMA2D_IN_REMAIN_UNDER_4B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_4B_CH1_S 10 -/** DMA2D_IN_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_5B_CH1 (BIT(11)) -#define DMA2D_IN_REMAIN_UNDER_5B_CH1_M (DMA2D_IN_REMAIN_UNDER_5B_CH1_V << DMA2D_IN_REMAIN_UNDER_5B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_5B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_5B_CH1_S 11 -/** DMA2D_IN_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_6B_CH1 (BIT(12)) -#define DMA2D_IN_REMAIN_UNDER_6B_CH1_M (DMA2D_IN_REMAIN_UNDER_6B_CH1_V << DMA2D_IN_REMAIN_UNDER_6B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_6B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_6B_CH1_S 12 -/** DMA2D_IN_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_7B_CH1 (BIT(13)) -#define DMA2D_IN_REMAIN_UNDER_7B_CH1_M (DMA2D_IN_REMAIN_UNDER_7B_CH1_V << DMA2D_IN_REMAIN_UNDER_7B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_7B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_7B_CH1_S 13 -/** DMA2D_IN_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_8B_CH1 (BIT(14)) -#define DMA2D_IN_REMAIN_UNDER_8B_CH1_M (DMA2D_IN_REMAIN_UNDER_8B_CH1_V << DMA2D_IN_REMAIN_UNDER_8B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_8B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_8B_CH1_S 14 -/** DMA2D_INFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L1_CH1 (BIT(15)) -#define DMA2D_INFIFO_FULL_L1_CH1_M (DMA2D_INFIFO_FULL_L1_CH1_V << DMA2D_INFIFO_FULL_L1_CH1_S) -#define DMA2D_INFIFO_FULL_L1_CH1_V 0x00000001U -#define DMA2D_INFIFO_FULL_L1_CH1_S 15 -/** DMA2D_INFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L1_CH1 (BIT(16)) -#define DMA2D_INFIFO_EMPTY_L1_CH1_M (DMA2D_INFIFO_EMPTY_L1_CH1_V << DMA2D_INFIFO_EMPTY_L1_CH1_S) -#define DMA2D_INFIFO_EMPTY_L1_CH1_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L1_CH1_S 16 -/** DMA2D_INFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L1_CH1 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH1_M (DMA2D_INFIFO_CNT_L1_CH1_V << DMA2D_INFIFO_CNT_L1_CH1_S) -#define DMA2D_INFIFO_CNT_L1_CH1_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH1_S 17 -/** DMA2D_INFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L3_CH1 (BIT(22)) -#define DMA2D_INFIFO_FULL_L3_CH1_M (DMA2D_INFIFO_FULL_L3_CH1_V << DMA2D_INFIFO_FULL_L3_CH1_S) -#define DMA2D_INFIFO_FULL_L3_CH1_V 0x00000001U -#define DMA2D_INFIFO_FULL_L3_CH1_S 22 -/** DMA2D_INFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L3_CH1 (BIT(23)) -#define DMA2D_INFIFO_EMPTY_L3_CH1_M (DMA2D_INFIFO_EMPTY_L3_CH1_V << DMA2D_INFIFO_EMPTY_L3_CH1_S) -#define DMA2D_INFIFO_EMPTY_L3_CH1_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L3_CH1_S 23 -/** DMA2D_INFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L3_CH1 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH1_M (DMA2D_INFIFO_CNT_L3_CH1_V << DMA2D_INFIFO_CNT_L3_CH1_S) -#define DMA2D_INFIFO_CNT_L3_CH1_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH1_S 24 - -/** DMA2D_IN_POP_CH1_REG register - * Configures the rx fifo of channel 1 - */ -#define DMA2D_IN_POP_CH1_REG (DR_REG_DMA2D_BASE + 0x618) -/** DMA2D_INFIFO_RDATA_CH1 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_RDATA_CH1 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH1_M (DMA2D_INFIFO_RDATA_CH1_V << DMA2D_INFIFO_RDATA_CH1_S) -#define DMA2D_INFIFO_RDATA_CH1_V 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH1_S 0 -/** DMA2D_INFIFO_POP_CH1 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_POP_CH1 (BIT(11)) -#define DMA2D_INFIFO_POP_CH1_M (DMA2D_INFIFO_POP_CH1_V << DMA2D_INFIFO_POP_CH1_S) -#define DMA2D_INFIFO_POP_CH1_V 0x00000001U -#define DMA2D_INFIFO_POP_CH1_S 11 - -/** DMA2D_IN_LINK_CONF_CH1_REG register - * Configures the rx descriptor operations of channel 1 - */ -#define DMA2D_IN_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x61c) -/** DMA2D_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ -#define DMA2D_INLINK_AUTO_RET_CH1 (BIT(20)) -#define DMA2D_INLINK_AUTO_RET_CH1_M (DMA2D_INLINK_AUTO_RET_CH1_V << DMA2D_INLINK_AUTO_RET_CH1_S) -#define DMA2D_INLINK_AUTO_RET_CH1_V 0x00000001U -#define DMA2D_INLINK_AUTO_RET_CH1_S 20 -/** DMA2D_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_STOP_CH1 (BIT(21)) -#define DMA2D_INLINK_STOP_CH1_M (DMA2D_INLINK_STOP_CH1_V << DMA2D_INLINK_STOP_CH1_S) -#define DMA2D_INLINK_STOP_CH1_V 0x00000001U -#define DMA2D_INLINK_STOP_CH1_S 21 -/** DMA2D_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_START_CH1 (BIT(22)) -#define DMA2D_INLINK_START_CH1_M (DMA2D_INLINK_START_CH1_V << DMA2D_INLINK_START_CH1_S) -#define DMA2D_INLINK_START_CH1_V 0x00000001U -#define DMA2D_INLINK_START_CH1_S 22 -/** DMA2D_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ -#define DMA2D_INLINK_RESTART_CH1 (BIT(23)) -#define DMA2D_INLINK_RESTART_CH1_M (DMA2D_INLINK_RESTART_CH1_V << DMA2D_INLINK_RESTART_CH1_S) -#define DMA2D_INLINK_RESTART_CH1_V 0x00000001U -#define DMA2D_INLINK_RESTART_CH1_S 23 -/** DMA2D_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ -#define DMA2D_INLINK_PARK_CH1 (BIT(24)) -#define DMA2D_INLINK_PARK_CH1_M (DMA2D_INLINK_PARK_CH1_V << DMA2D_INLINK_PARK_CH1_S) -#define DMA2D_INLINK_PARK_CH1_V 0x00000001U -#define DMA2D_INLINK_PARK_CH1_S 24 - -/** DMA2D_IN_LINK_ADDR_CH1_REG register - * Configures the rx descriptor address of channel 1 - */ -#define DMA2D_IN_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x620) -/** DMA2D_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ -#define DMA2D_INLINK_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH1_M (DMA2D_INLINK_ADDR_CH1_V << DMA2D_INLINK_ADDR_CH1_S) -#define DMA2D_INLINK_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH1_S 0 - -/** DMA2D_IN_STATE_CH1_REG register - * Represents the working status of the rx descriptor of channel 1 - */ -#define DMA2D_IN_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x624) -/** DMA2D_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ -#define DMA2D_INLINK_DSCR_ADDR_CH1 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH1_M (DMA2D_INLINK_DSCR_ADDR_CH1_V << DMA2D_INLINK_DSCR_ADDR_CH1_S) -#define DMA2D_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH1_S 0 -/** DMA2D_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * reserved - */ -#define DMA2D_IN_DSCR_STATE_CH1 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH1_M (DMA2D_IN_DSCR_STATE_CH1_V << DMA2D_IN_DSCR_STATE_CH1_S) -#define DMA2D_IN_DSCR_STATE_CH1_V 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH1_S 18 -/** DMA2D_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; - * reserved - */ -#define DMA2D_IN_STATE_CH1 0x00000007U -#define DMA2D_IN_STATE_CH1_M (DMA2D_IN_STATE_CH1_V << DMA2D_IN_STATE_CH1_S) -#define DMA2D_IN_STATE_CH1_V 0x00000007U -#define DMA2D_IN_STATE_CH1_S 20 -/** DMA2D_IN_RESET_AVAIL_CH1 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_IN_RESET_AVAIL_CH1 (BIT(23)) -#define DMA2D_IN_RESET_AVAIL_CH1_M (DMA2D_IN_RESET_AVAIL_CH1_V << DMA2D_IN_RESET_AVAIL_CH1_S) -#define DMA2D_IN_RESET_AVAIL_CH1_V 0x00000001U -#define DMA2D_IN_RESET_AVAIL_CH1_S 23 - -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 1 - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x628) -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S) -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S 0 - -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 1 - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x62c) -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S) -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S 0 - -/** DMA2D_IN_DSCR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 1 - */ -#define DMA2D_IN_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x630) -/** DMA2D_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ -#define DMA2D_INLINK_DSCR_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH1_M (DMA2D_INLINK_DSCR_CH1_V << DMA2D_INLINK_DSCR_CH1_S) -#define DMA2D_INLINK_DSCR_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH1_S 0 - -/** DMA2D_IN_DSCR_BF0_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 1 - */ -#define DMA2D_IN_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x634) -/** DMA2D_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ -#define DMA2D_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH1_M (DMA2D_INLINK_DSCR_BF0_CH1_V << DMA2D_INLINK_DSCR_BF0_CH1_S) -#define DMA2D_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH1_S 0 - -/** DMA2D_IN_DSCR_BF1_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 1 - */ -#define DMA2D_IN_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x638) -/** DMA2D_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ -#define DMA2D_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH1_M (DMA2D_INLINK_DSCR_BF1_CH1_V << DMA2D_INLINK_DSCR_BF1_CH1_S) -#define DMA2D_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH1_S 0 - -/** DMA2D_IN_PERI_SEL_CH1_REG register - * Configures the rx peripheral of channel 1 - */ -#define DMA2D_IN_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x63c) -/** DMA2D_IN_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Rx channel 0: jpeg 1: - * display-1 2: display-2 7: no choose - */ -#define DMA2D_IN_PERI_SEL_CH1 0x00000007U -#define DMA2D_IN_PERI_SEL_CH1_M (DMA2D_IN_PERI_SEL_CH1_V << DMA2D_IN_PERI_SEL_CH1_S) -#define DMA2D_IN_PERI_SEL_CH1_V 0x00000007U -#define DMA2D_IN_PERI_SEL_CH1_S 0 - -/** DMA2D_IN_ARB_CH1_REG register - * Configures the rx arbiter of channel 1 - */ -#define DMA2D_IN_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x640) -/** DMA2D_IN_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_IN_ARB_TOKEN_NUM_CH1 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH1_M (DMA2D_IN_ARB_TOKEN_NUM_CH1_V << DMA2D_IN_ARB_TOKEN_NUM_CH1_S) -#define DMA2D_IN_ARB_TOKEN_NUM_CH1_V 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH1_S 0 -/** DMA2D_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_CH1 (BIT(4)) -#define DMA2D_IN_ARB_PRIORITY_CH1_M (DMA2D_IN_ARB_PRIORITY_CH1_V << DMA2D_IN_ARB_PRIORITY_CH1_S) -#define DMA2D_IN_ARB_PRIORITY_CH1_V 0x00000001U -#define DMA2D_IN_ARB_PRIORITY_CH1_S 4 -/** DMA2D_IN_ARB_PRIORITY_H_CH1 : R/W; bitpos: [7:5]; default: 0; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_H_CH1 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH1_M (DMA2D_IN_ARB_PRIORITY_H_CH1_V << DMA2D_IN_ARB_PRIORITY_H_CH1_S) -#define DMA2D_IN_ARB_PRIORITY_H_CH1_V 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH1_S 5 - -/** DMA2D_IN_RO_STATUS_CH1_REG register - * Represents the status of the rx reorder module of channel 1 - */ -#define DMA2D_IN_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x644) -/** DMA2D_INFIFO_RO_CNT_CH1 : RO; bitpos: [4:0]; default: 0; - * The register stores the byte number of the data in color convert Rx FIFO for - * channel 0. - */ -#define DMA2D_INFIFO_RO_CNT_CH1 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH1_M (DMA2D_INFIFO_RO_CNT_CH1_V << DMA2D_INFIFO_RO_CNT_CH1_S) -#define DMA2D_INFIFO_RO_CNT_CH1_V 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH1_S 0 -/** DMA2D_IN_RO_WR_STATE_CH1 : RO; bitpos: [6:5]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_IN_RO_WR_STATE_CH1 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH1_M (DMA2D_IN_RO_WR_STATE_CH1_V << DMA2D_IN_RO_WR_STATE_CH1_S) -#define DMA2D_IN_RO_WR_STATE_CH1_V 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH1_S 5 -/** DMA2D_IN_RO_RD_STATE_CH1 : RO; bitpos: [8:7]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_IN_RO_RD_STATE_CH1 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH1_M (DMA2D_IN_RO_RD_STATE_CH1_V << DMA2D_IN_RO_RD_STATE_CH1_S) -#define DMA2D_IN_RO_RD_STATE_CH1_V 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH1_S 7 -/** DMA2D_IN_PIXEL_BYTE_CH1 : RO; bitpos: [12:9]; default: 0; - * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_IN_PIXEL_BYTE_CH1 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH1_M (DMA2D_IN_PIXEL_BYTE_CH1_V << DMA2D_IN_PIXEL_BYTE_CH1_S) -#define DMA2D_IN_PIXEL_BYTE_CH1_V 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH1_S 9 -/** DMA2D_IN_BURST_BLOCK_NUM_CH1 : RO; bitpos: [16:13]; default: 0; - * the number of macro blocks contained in a burst of data at RX channel - */ -#define DMA2D_IN_BURST_BLOCK_NUM_CH1 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH1_M (DMA2D_IN_BURST_BLOCK_NUM_CH1_V << DMA2D_IN_BURST_BLOCK_NUM_CH1_S) -#define DMA2D_IN_BURST_BLOCK_NUM_CH1_V 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH1_S 13 - -/** DMA2D_IN_RO_PD_CONF_CH1_REG register - * Configures the rx reorder memory of channel 1 - */ -#define DMA2D_IN_RO_PD_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x648) -/** DMA2D_IN_RO_RAM_FORCE_PD_CH1 : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ -#define DMA2D_IN_RO_RAM_FORCE_PD_CH1 (BIT(4)) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH1_M (DMA2D_IN_RO_RAM_FORCE_PD_CH1_V << DMA2D_IN_RO_RAM_FORCE_PD_CH1_S) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH1_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PD_CH1_S 4 -/** DMA2D_IN_RO_RAM_FORCE_PU_CH1 : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ -#define DMA2D_IN_RO_RAM_FORCE_PU_CH1 (BIT(5)) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH1_M (DMA2D_IN_RO_RAM_FORCE_PU_CH1_V << DMA2D_IN_RO_RAM_FORCE_PU_CH1_S) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH1_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PU_CH1_S 5 -/** DMA2D_IN_RO_RAM_CLK_FO_CH1 : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ -#define DMA2D_IN_RO_RAM_CLK_FO_CH1 (BIT(6)) -#define DMA2D_IN_RO_RAM_CLK_FO_CH1_M (DMA2D_IN_RO_RAM_CLK_FO_CH1_V << DMA2D_IN_RO_RAM_CLK_FO_CH1_S) -#define DMA2D_IN_RO_RAM_CLK_FO_CH1_V 0x00000001U -#define DMA2D_IN_RO_RAM_CLK_FO_CH1_S 6 - -/** DMA2D_IN_COLOR_CONVERT_CH1_REG register - * Configures the Rx color convert of channel 1 - */ -#define DMA2D_IN_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x64c) -/** DMA2D_IN_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 - */ -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1_M (DMA2D_IN_COLOR_OUTPUT_SEL_CH1_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH1_S) -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1_V 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1_S 0 -/** DMA2D_IN_COLOR_3B_PROC_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_IN_COLOR_3B_PROC_EN_CH1 (BIT(2)) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH1_M (DMA2D_IN_COLOR_3B_PROC_EN_CH1_V << DMA2D_IN_COLOR_3B_PROC_EN_CH1_S) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH1_V 0x00000001U -#define DMA2D_IN_COLOR_3B_PROC_EN_CH1_S 2 -/** DMA2D_IN_COLOR_INPUT_SEL_CH1 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: YUV422/420 to YUV444 - * 1: YUV422 2: YUV444/420 7: disable color space convert - */ -#define DMA2D_IN_COLOR_INPUT_SEL_CH1 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH1_M (DMA2D_IN_COLOR_INPUT_SEL_CH1_V << DMA2D_IN_COLOR_INPUT_SEL_CH1_S) -#define DMA2D_IN_COLOR_INPUT_SEL_CH1_V 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH1_S 3 - -/** DMA2D_IN_SCRAMBLE_CH1_REG register - * Configures the rx scramble of channel 1 - */ -#define DMA2D_IN_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x650) -/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_M (DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_S) -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_S 0 -/** DMA2D_IN_SCRAMBLE_SEL_POST_CH1 : R/W; bitpos: [5:3]; default: 0; - * Scramble data after color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : BYTE1-0-2 - * 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1_M (DMA2D_IN_SCRAMBLE_SEL_POST_CH1_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH1_S) -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1_S 3 - -/** DMA2D_IN_COLOR_PARAM0_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x654) -/** DMA2D_IN_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H0_CH1 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH1_M (DMA2D_IN_COLOR_PARAM_H0_CH1_V << DMA2D_IN_COLOR_PARAM_H0_CH1_S) -#define DMA2D_IN_COLOR_PARAM_H0_CH1_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH1_S 0 - -/** DMA2D_IN_COLOR_PARAM1_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x658) -/** DMA2D_IN_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H1_CH1 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH1_M (DMA2D_IN_COLOR_PARAM_H1_CH1_V << DMA2D_IN_COLOR_PARAM_H1_CH1_S) -#define DMA2D_IN_COLOR_PARAM_H1_CH1_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH1_S 0 - -/** DMA2D_IN_COLOR_PARAM2_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x65c) -/** DMA2D_IN_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M0_CH1 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH1_M (DMA2D_IN_COLOR_PARAM_M0_CH1_V << DMA2D_IN_COLOR_PARAM_M0_CH1_S) -#define DMA2D_IN_COLOR_PARAM_M0_CH1_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH1_S 0 - -/** DMA2D_IN_COLOR_PARAM3_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x660) -/** DMA2D_IN_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M1_CH1 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH1_M (DMA2D_IN_COLOR_PARAM_M1_CH1_V << DMA2D_IN_COLOR_PARAM_M1_CH1_S) -#define DMA2D_IN_COLOR_PARAM_M1_CH1_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH1_S 0 - -/** DMA2D_IN_COLOR_PARAM4_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x664) -/** DMA2D_IN_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L0_CH1 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH1_M (DMA2D_IN_COLOR_PARAM_L0_CH1_V << DMA2D_IN_COLOR_PARAM_L0_CH1_S) -#define DMA2D_IN_COLOR_PARAM_L0_CH1_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH1_S 0 - -/** DMA2D_IN_COLOR_PARAM5_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x668) -/** DMA2D_IN_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L1_CH1 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH1_M (DMA2D_IN_COLOR_PARAM_L1_CH1_V << DMA2D_IN_COLOR_PARAM_L1_CH1_S) -#define DMA2D_IN_COLOR_PARAM_L1_CH1_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH1_S 0 - -/** DMA2D_IN_ETM_CONF_CH1_REG register - * Configures the rx etm of channel 1 - */ -#define DMA2D_IN_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x66c) -/** DMA2D_IN_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_EN_CH1 (BIT(0)) -#define DMA2D_IN_ETM_EN_CH1_M (DMA2D_IN_ETM_EN_CH1_V << DMA2D_IN_ETM_EN_CH1_S) -#define DMA2D_IN_ETM_EN_CH1_V 0x00000001U -#define DMA2D_IN_ETM_EN_CH1_S 0 -/** DMA2D_IN_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_LOOP_EN_CH1 (BIT(1)) -#define DMA2D_IN_ETM_LOOP_EN_CH1_M (DMA2D_IN_ETM_LOOP_EN_CH1_V << DMA2D_IN_ETM_LOOP_EN_CH1_S) -#define DMA2D_IN_ETM_LOOP_EN_CH1_V 0x00000001U -#define DMA2D_IN_ETM_LOOP_EN_CH1_S 1 -/** DMA2D_IN_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_IN_DSCR_TASK_MAK_CH1 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH1_M (DMA2D_IN_DSCR_TASK_MAK_CH1_V << DMA2D_IN_DSCR_TASK_MAK_CH1_S) -#define DMA2D_IN_DSCR_TASK_MAK_CH1_V 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH1_S 2 - -/** DMA2D_IN_CONF0_CH2_REG register - * Configures the rx direction of channel 2 - */ -#define DMA2D_IN_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x700) -/** DMA2D_IN_MEM_TRANS_EN_CH2 : R/W; bitpos: [0]; default: 0; - * enable memory trans of the same channel - */ -#define DMA2D_IN_MEM_TRANS_EN_CH2 (BIT(0)) -#define DMA2D_IN_MEM_TRANS_EN_CH2_M (DMA2D_IN_MEM_TRANS_EN_CH2_V << DMA2D_IN_MEM_TRANS_EN_CH2_S) -#define DMA2D_IN_MEM_TRANS_EN_CH2_V 0x00000001U -#define DMA2D_IN_MEM_TRANS_EN_CH2_S 0 -/** DMA2D_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ -#define DMA2D_INDSCR_BURST_EN_CH2 (BIT(2)) -#define DMA2D_INDSCR_BURST_EN_CH2_M (DMA2D_INDSCR_BURST_EN_CH2_V << DMA2D_INDSCR_BURST_EN_CH2_S) -#define DMA2D_INDSCR_BURST_EN_CH2_V 0x00000001U -#define DMA2D_INDSCR_BURST_EN_CH2_S 2 -/** DMA2D_IN_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_IN_ECC_AES_EN_CH2 (BIT(3)) -#define DMA2D_IN_ECC_AES_EN_CH2_M (DMA2D_IN_ECC_AES_EN_CH2_V << DMA2D_IN_ECC_AES_EN_CH2_S) -#define DMA2D_IN_ECC_AES_EN_CH2_V 0x00000001U -#define DMA2D_IN_ECC_AES_EN_CH2_S 3 -/** DMA2D_IN_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_IN_CHECK_OWNER_CH2 (BIT(4)) -#define DMA2D_IN_CHECK_OWNER_CH2_M (DMA2D_IN_CHECK_OWNER_CH2_V << DMA2D_IN_CHECK_OWNER_CH2_S) -#define DMA2D_IN_CHECK_OWNER_CH2_V 0x00000001U -#define DMA2D_IN_CHECK_OWNER_CH2_S 4 -/** DMA2D_IN_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_IN_LOOP_TEST_CH2 (BIT(5)) -#define DMA2D_IN_LOOP_TEST_CH2_M (DMA2D_IN_LOOP_TEST_CH2_V << DMA2D_IN_LOOP_TEST_CH2_S) -#define DMA2D_IN_LOOP_TEST_CH2_V 0x00000001U -#define DMA2D_IN_LOOP_TEST_CH2_S 5 -/** DMA2D_IN_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_IN_MEM_BURST_LENGTH_CH2 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH2_M (DMA2D_IN_MEM_BURST_LENGTH_CH2_V << DMA2D_IN_MEM_BURST_LENGTH_CH2_S) -#define DMA2D_IN_MEM_BURST_LENGTH_CH2_V 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH2_S 6 -/** DMA2D_IN_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0; - * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S) -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S 9 -/** DMA2D_IN_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_IN_DSCR_PORT_EN_CH2 (BIT(11)) -#define DMA2D_IN_DSCR_PORT_EN_CH2_M (DMA2D_IN_DSCR_PORT_EN_CH2_V << DMA2D_IN_DSCR_PORT_EN_CH2_S) -#define DMA2D_IN_DSCR_PORT_EN_CH2_V 0x00000001U -#define DMA2D_IN_DSCR_PORT_EN_CH2_S 11 -/** DMA2D_IN_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ -#define DMA2D_IN_PAGE_BOUND_EN_CH2 (BIT(12)) -#define DMA2D_IN_PAGE_BOUND_EN_CH2_M (DMA2D_IN_PAGE_BOUND_EN_CH2_V << DMA2D_IN_PAGE_BOUND_EN_CH2_S) -#define DMA2D_IN_PAGE_BOUND_EN_CH2_V 0x00000001U -#define DMA2D_IN_PAGE_BOUND_EN_CH2_S 12 -/** DMA2D_IN_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0; - * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_IN_REORDER_EN_CH2 (BIT(16)) -#define DMA2D_IN_REORDER_EN_CH2_M (DMA2D_IN_REORDER_EN_CH2_V << DMA2D_IN_REORDER_EN_CH2_S) -#define DMA2D_IN_REORDER_EN_CH2_V 0x00000001U -#define DMA2D_IN_REORDER_EN_CH2_S 16 -/** DMA2D_IN_RST_CH2 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ -#define DMA2D_IN_RST_CH2 (BIT(24)) -#define DMA2D_IN_RST_CH2_M (DMA2D_IN_RST_CH2_V << DMA2D_IN_RST_CH2_S) -#define DMA2D_IN_RST_CH2_V 0x00000001U -#define DMA2D_IN_RST_CH2_S 24 -/** DMA2D_IN_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_IN_CMD_DISABLE_CH2 (BIT(25)) -#define DMA2D_IN_CMD_DISABLE_CH2_M (DMA2D_IN_CMD_DISABLE_CH2_V << DMA2D_IN_CMD_DISABLE_CH2_S) -#define DMA2D_IN_CMD_DISABLE_CH2_V 0x00000001U -#define DMA2D_IN_CMD_DISABLE_CH2_S 25 -/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2 (BIT(26)) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V 0x00000001U -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S 26 - -/** DMA2D_IN_INT_RAW_CH2_REG register - * Raw interrupt status of RX channel 2 - */ -#define DMA2D_IN_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x704) -/** DMA2D_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 0. - */ -#define DMA2D_IN_DONE_CH2_INT_RAW (BIT(0)) -#define DMA2D_IN_DONE_CH2_INT_RAW_M (DMA2D_IN_DONE_CH2_INT_RAW_V << DMA2D_IN_DONE_CH2_INT_RAW_S) -#define DMA2D_IN_DONE_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_DONE_CH2_INT_RAW_S 0 -/** DMA2D_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 0. - */ -#define DMA2D_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_M (DMA2D_IN_SUC_EOF_CH2_INT_RAW_V << DMA2D_IN_SUC_EOF_CH2_INT_RAW_S) -#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_S 1 -/** DMA2D_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ -#define DMA2D_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_M (DMA2D_IN_ERR_EOF_CH2_INT_RAW_V << DMA2D_IN_ERR_EOF_CH2_INT_RAW_S) -#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_S 2 -/** DMA2D_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 0. - */ -#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S) -#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S 3 -/** DMA2D_INFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S 4 -/** DMA2D_INFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S 5 -/** DMA2D_INFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S 6 -/** DMA2D_INFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S 7 -/** DMA2D_INFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S 8 -/** DMA2D_INFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S 10 -/** DMA2D_INFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S 11 -/** DMA2D_INFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S 13 - -/** DMA2D_IN_INT_ENA_CH2_REG register - * Interrupt enable bits of RX channel 2 - */ -#define DMA2D_IN_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x708) -/** DMA2D_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH2_INT_ENA (BIT(0)) -#define DMA2D_IN_DONE_CH2_INT_ENA_M (DMA2D_IN_DONE_CH2_INT_ENA_V << DMA2D_IN_DONE_CH2_INT_ENA_S) -#define DMA2D_IN_DONE_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_DONE_CH2_INT_ENA_S 0 -/** DMA2D_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_M (DMA2D_IN_SUC_EOF_CH2_INT_ENA_V << DMA2D_IN_SUC_EOF_CH2_INT_ENA_S) -#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_S 1 -/** DMA2D_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_M (DMA2D_IN_ERR_EOF_CH2_INT_ENA_V << DMA2D_IN_ERR_EOF_CH2_INT_ENA_S) -#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_S 2 -/** DMA2D_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S) -#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S 3 -/** DMA2D_INFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S 4 -/** DMA2D_INFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S 5 -/** DMA2D_INFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S 6 -/** DMA2D_INFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S 7 -/** DMA2D_INFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S 8 -/** DMA2D_INFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S 10 -/** DMA2D_INFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S 11 -/** DMA2D_INFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S 13 - -/** DMA2D_IN_INT_ST_CH2_REG register - * Masked interrupt status of RX channel 2 - */ -#define DMA2D_IN_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x70c) -/** DMA2D_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH2_INT_ST (BIT(0)) -#define DMA2D_IN_DONE_CH2_INT_ST_M (DMA2D_IN_DONE_CH2_INT_ST_V << DMA2D_IN_DONE_CH2_INT_ST_S) -#define DMA2D_IN_DONE_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_DONE_CH2_INT_ST_S 0 -/** DMA2D_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH2_INT_ST (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH2_INT_ST_M (DMA2D_IN_SUC_EOF_CH2_INT_ST_V << DMA2D_IN_SUC_EOF_CH2_INT_ST_S) -#define DMA2D_IN_SUC_EOF_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH2_INT_ST_S 1 -/** DMA2D_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH2_INT_ST (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH2_INT_ST_M (DMA2D_IN_ERR_EOF_CH2_INT_ST_V << DMA2D_IN_ERR_EOF_CH2_INT_ST_S) -#define DMA2D_IN_ERR_EOF_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH2_INT_ST_S 2 -/** DMA2D_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_M (DMA2D_IN_DSCR_ERR_CH2_INT_ST_V << DMA2D_IN_DSCR_ERR_CH2_INT_ST_S) -#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_S 3 -/** DMA2D_INFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S 4 -/** DMA2D_INFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S 5 -/** DMA2D_INFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S 6 -/** DMA2D_INFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S 7 -/** DMA2D_INFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S 8 -/** DMA2D_INFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S 10 -/** DMA2D_INFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S 11 -/** DMA2D_INFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S 13 - -/** DMA2D_IN_INT_CLR_CH2_REG register - * Interrupt clear bits of RX channel 2 - */ -#define DMA2D_IN_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x710) -/** DMA2D_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH2_INT_CLR (BIT(0)) -#define DMA2D_IN_DONE_CH2_INT_CLR_M (DMA2D_IN_DONE_CH2_INT_CLR_V << DMA2D_IN_DONE_CH2_INT_CLR_S) -#define DMA2D_IN_DONE_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_DONE_CH2_INT_CLR_S 0 -/** DMA2D_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_M (DMA2D_IN_SUC_EOF_CH2_INT_CLR_V << DMA2D_IN_SUC_EOF_CH2_INT_CLR_S) -#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_S 1 -/** DMA2D_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_M (DMA2D_IN_ERR_EOF_CH2_INT_CLR_V << DMA2D_IN_ERR_EOF_CH2_INT_CLR_S) -#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_S 2 -/** DMA2D_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S) -#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S 3 -/** DMA2D_INFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S 4 -/** DMA2D_INFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S 5 -/** DMA2D_INFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S 6 -/** DMA2D_INFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S 7 -/** DMA2D_INFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S 8 -/** DMA2D_INFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S 10 -/** DMA2D_INFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S 11 -/** DMA2D_INFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S 13 - -/** DMA2D_INFIFO_STATUS_CH2_REG register - * Represents the status of the rx fifo of channel 2 - */ -#define DMA2D_INFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x714) -/** DMA2D_INFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ -#define DMA2D_INFIFO_FULL_L2_CH2 (BIT(0)) -#define DMA2D_INFIFO_FULL_L2_CH2_M (DMA2D_INFIFO_FULL_L2_CH2_V << DMA2D_INFIFO_FULL_L2_CH2_S) -#define DMA2D_INFIFO_FULL_L2_CH2_V 0x00000001U -#define DMA2D_INFIFO_FULL_L2_CH2_S 0 -/** DMA2D_INFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ -#define DMA2D_INFIFO_EMPTY_L2_CH2 (BIT(1)) -#define DMA2D_INFIFO_EMPTY_L2_CH2_M (DMA2D_INFIFO_EMPTY_L2_CH2_V << DMA2D_INFIFO_EMPTY_L2_CH2_S) -#define DMA2D_INFIFO_EMPTY_L2_CH2_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L2_CH2_S 1 -/** DMA2D_INFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ -#define DMA2D_INFIFO_CNT_L2_CH2 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH2_M (DMA2D_INFIFO_CNT_L2_CH2_V << DMA2D_INFIFO_CNT_L2_CH2_S) -#define DMA2D_INFIFO_CNT_L2_CH2_V 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH2_S 2 -/** DMA2D_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_1B_CH2 (BIT(7)) -#define DMA2D_IN_REMAIN_UNDER_1B_CH2_M (DMA2D_IN_REMAIN_UNDER_1B_CH2_V << DMA2D_IN_REMAIN_UNDER_1B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_1B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_1B_CH2_S 7 -/** DMA2D_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_2B_CH2 (BIT(8)) -#define DMA2D_IN_REMAIN_UNDER_2B_CH2_M (DMA2D_IN_REMAIN_UNDER_2B_CH2_V << DMA2D_IN_REMAIN_UNDER_2B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_2B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_2B_CH2_S 8 -/** DMA2D_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_3B_CH2 (BIT(9)) -#define DMA2D_IN_REMAIN_UNDER_3B_CH2_M (DMA2D_IN_REMAIN_UNDER_3B_CH2_V << DMA2D_IN_REMAIN_UNDER_3B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_3B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_3B_CH2_S 9 -/** DMA2D_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_4B_CH2 (BIT(10)) -#define DMA2D_IN_REMAIN_UNDER_4B_CH2_M (DMA2D_IN_REMAIN_UNDER_4B_CH2_V << DMA2D_IN_REMAIN_UNDER_4B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_4B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_4B_CH2_S 10 -/** DMA2D_IN_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_5B_CH2 (BIT(11)) -#define DMA2D_IN_REMAIN_UNDER_5B_CH2_M (DMA2D_IN_REMAIN_UNDER_5B_CH2_V << DMA2D_IN_REMAIN_UNDER_5B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_5B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_5B_CH2_S 11 -/** DMA2D_IN_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_6B_CH2 (BIT(12)) -#define DMA2D_IN_REMAIN_UNDER_6B_CH2_M (DMA2D_IN_REMAIN_UNDER_6B_CH2_V << DMA2D_IN_REMAIN_UNDER_6B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_6B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_6B_CH2_S 12 -/** DMA2D_IN_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_7B_CH2 (BIT(13)) -#define DMA2D_IN_REMAIN_UNDER_7B_CH2_M (DMA2D_IN_REMAIN_UNDER_7B_CH2_V << DMA2D_IN_REMAIN_UNDER_7B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_7B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_7B_CH2_S 13 -/** DMA2D_IN_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_8B_CH2 (BIT(14)) -#define DMA2D_IN_REMAIN_UNDER_8B_CH2_M (DMA2D_IN_REMAIN_UNDER_8B_CH2_V << DMA2D_IN_REMAIN_UNDER_8B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_8B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_8B_CH2_S 14 -/** DMA2D_INFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L1_CH2 (BIT(15)) -#define DMA2D_INFIFO_FULL_L1_CH2_M (DMA2D_INFIFO_FULL_L1_CH2_V << DMA2D_INFIFO_FULL_L1_CH2_S) -#define DMA2D_INFIFO_FULL_L1_CH2_V 0x00000001U -#define DMA2D_INFIFO_FULL_L1_CH2_S 15 -/** DMA2D_INFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L1_CH2 (BIT(16)) -#define DMA2D_INFIFO_EMPTY_L1_CH2_M (DMA2D_INFIFO_EMPTY_L1_CH2_V << DMA2D_INFIFO_EMPTY_L1_CH2_S) -#define DMA2D_INFIFO_EMPTY_L1_CH2_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L1_CH2_S 16 -/** DMA2D_INFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L1_CH2 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH2_M (DMA2D_INFIFO_CNT_L1_CH2_V << DMA2D_INFIFO_CNT_L1_CH2_S) -#define DMA2D_INFIFO_CNT_L1_CH2_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH2_S 17 -/** DMA2D_INFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L3_CH2 (BIT(22)) -#define DMA2D_INFIFO_FULL_L3_CH2_M (DMA2D_INFIFO_FULL_L3_CH2_V << DMA2D_INFIFO_FULL_L3_CH2_S) -#define DMA2D_INFIFO_FULL_L3_CH2_V 0x00000001U -#define DMA2D_INFIFO_FULL_L3_CH2_S 22 -/** DMA2D_INFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L3_CH2 (BIT(23)) -#define DMA2D_INFIFO_EMPTY_L3_CH2_M (DMA2D_INFIFO_EMPTY_L3_CH2_V << DMA2D_INFIFO_EMPTY_L3_CH2_S) -#define DMA2D_INFIFO_EMPTY_L3_CH2_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L3_CH2_S 23 -/** DMA2D_INFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L3_CH2 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH2_M (DMA2D_INFIFO_CNT_L3_CH2_V << DMA2D_INFIFO_CNT_L3_CH2_S) -#define DMA2D_INFIFO_CNT_L3_CH2_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH2_S 24 - -/** DMA2D_IN_POP_CH2_REG register - * Configures the rx fifo of channel 2 - */ -#define DMA2D_IN_POP_CH2_REG (DR_REG_DMA2D_BASE + 0x718) -/** DMA2D_INFIFO_RDATA_CH2 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_RDATA_CH2 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH2_M (DMA2D_INFIFO_RDATA_CH2_V << DMA2D_INFIFO_RDATA_CH2_S) -#define DMA2D_INFIFO_RDATA_CH2_V 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH2_S 0 -/** DMA2D_INFIFO_POP_CH2 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_POP_CH2 (BIT(11)) -#define DMA2D_INFIFO_POP_CH2_M (DMA2D_INFIFO_POP_CH2_V << DMA2D_INFIFO_POP_CH2_S) -#define DMA2D_INFIFO_POP_CH2_V 0x00000001U -#define DMA2D_INFIFO_POP_CH2_S 11 - -/** DMA2D_IN_LINK_CONF_CH2_REG register - * Configures the rx descriptor operations of channel 2 - */ -#define DMA2D_IN_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x71c) -/** DMA2D_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ -#define DMA2D_INLINK_AUTO_RET_CH2 (BIT(20)) -#define DMA2D_INLINK_AUTO_RET_CH2_M (DMA2D_INLINK_AUTO_RET_CH2_V << DMA2D_INLINK_AUTO_RET_CH2_S) -#define DMA2D_INLINK_AUTO_RET_CH2_V 0x00000001U -#define DMA2D_INLINK_AUTO_RET_CH2_S 20 -/** DMA2D_INLINK_STOP_CH2 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_STOP_CH2 (BIT(21)) -#define DMA2D_INLINK_STOP_CH2_M (DMA2D_INLINK_STOP_CH2_V << DMA2D_INLINK_STOP_CH2_S) -#define DMA2D_INLINK_STOP_CH2_V 0x00000001U -#define DMA2D_INLINK_STOP_CH2_S 21 -/** DMA2D_INLINK_START_CH2 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_START_CH2 (BIT(22)) -#define DMA2D_INLINK_START_CH2_M (DMA2D_INLINK_START_CH2_V << DMA2D_INLINK_START_CH2_S) -#define DMA2D_INLINK_START_CH2_V 0x00000001U -#define DMA2D_INLINK_START_CH2_S 22 -/** DMA2D_INLINK_RESTART_CH2 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ -#define DMA2D_INLINK_RESTART_CH2 (BIT(23)) -#define DMA2D_INLINK_RESTART_CH2_M (DMA2D_INLINK_RESTART_CH2_V << DMA2D_INLINK_RESTART_CH2_S) -#define DMA2D_INLINK_RESTART_CH2_V 0x00000001U -#define DMA2D_INLINK_RESTART_CH2_S 23 -/** DMA2D_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ -#define DMA2D_INLINK_PARK_CH2 (BIT(24)) -#define DMA2D_INLINK_PARK_CH2_M (DMA2D_INLINK_PARK_CH2_V << DMA2D_INLINK_PARK_CH2_S) -#define DMA2D_INLINK_PARK_CH2_V 0x00000001U -#define DMA2D_INLINK_PARK_CH2_S 24 - -/** DMA2D_IN_LINK_ADDR_CH2_REG register - * Configures the rx descriptor address of channel 2 - */ -#define DMA2D_IN_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x720) -/** DMA2D_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ -#define DMA2D_INLINK_ADDR_CH2 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH2_M (DMA2D_INLINK_ADDR_CH2_V << DMA2D_INLINK_ADDR_CH2_S) -#define DMA2D_INLINK_ADDR_CH2_V 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH2_S 0 - -/** DMA2D_IN_STATE_CH2_REG register - * Represents the working status of the rx descriptor of channel 2 - */ -#define DMA2D_IN_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x724) -/** DMA2D_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ -#define DMA2D_INLINK_DSCR_ADDR_CH2 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH2_M (DMA2D_INLINK_DSCR_ADDR_CH2_V << DMA2D_INLINK_DSCR_ADDR_CH2_S) -#define DMA2D_INLINK_DSCR_ADDR_CH2_V 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH2_S 0 -/** DMA2D_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; - * reserved - */ -#define DMA2D_IN_DSCR_STATE_CH2 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH2_M (DMA2D_IN_DSCR_STATE_CH2_V << DMA2D_IN_DSCR_STATE_CH2_S) -#define DMA2D_IN_DSCR_STATE_CH2_V 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH2_S 18 -/** DMA2D_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; - * reserved - */ -#define DMA2D_IN_STATE_CH2 0x00000007U -#define DMA2D_IN_STATE_CH2_M (DMA2D_IN_STATE_CH2_V << DMA2D_IN_STATE_CH2_S) -#define DMA2D_IN_STATE_CH2_V 0x00000007U -#define DMA2D_IN_STATE_CH2_S 20 -/** DMA2D_IN_RESET_AVAIL_CH2 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_IN_RESET_AVAIL_CH2 (BIT(23)) -#define DMA2D_IN_RESET_AVAIL_CH2_M (DMA2D_IN_RESET_AVAIL_CH2_V << DMA2D_IN_RESET_AVAIL_CH2_S) -#define DMA2D_IN_RESET_AVAIL_CH2_V 0x00000001U -#define DMA2D_IN_RESET_AVAIL_CH2_S 23 - -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG register - * Represents the address associated with the inlink descriptor of channel 2 - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x728) -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S) -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S 0 - -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG register - * Represents the address associated with the inlink descriptor of channel 2 - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x72c) -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S) -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S 0 - -/** DMA2D_IN_DSCR_CH2_REG register - * Represents the address associated with the inlink descriptor of channel 2 - */ -#define DMA2D_IN_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x730) -/** DMA2D_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ -#define DMA2D_INLINK_DSCR_CH2 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH2_M (DMA2D_INLINK_DSCR_CH2_V << DMA2D_INLINK_DSCR_CH2_S) -#define DMA2D_INLINK_DSCR_CH2_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH2_S 0 - -/** DMA2D_IN_DSCR_BF0_CH2_REG register - * Represents the address associated with the inlink descriptor of channel 2 - */ -#define DMA2D_IN_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x734) -/** DMA2D_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ -#define DMA2D_INLINK_DSCR_BF0_CH2 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH2_M (DMA2D_INLINK_DSCR_BF0_CH2_V << DMA2D_INLINK_DSCR_BF0_CH2_S) -#define DMA2D_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH2_S 0 - -/** DMA2D_IN_DSCR_BF1_CH2_REG register - * Represents the address associated with the inlink descriptor of channel 2 - */ -#define DMA2D_IN_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x738) -/** DMA2D_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ -#define DMA2D_INLINK_DSCR_BF1_CH2 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH2_M (DMA2D_INLINK_DSCR_BF1_CH2_V << DMA2D_INLINK_DSCR_BF1_CH2_S) -#define DMA2D_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH2_S 0 - -/** DMA2D_IN_PERI_SEL_CH2_REG register - * Configures the rx peripheral of channel 2 - */ -#define DMA2D_IN_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x73c) -/** DMA2D_IN_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Rx channel 0: jpeg 1: - * display-1 2: display-2 7: no choose - */ -#define DMA2D_IN_PERI_SEL_CH2 0x00000007U -#define DMA2D_IN_PERI_SEL_CH2_M (DMA2D_IN_PERI_SEL_CH2_V << DMA2D_IN_PERI_SEL_CH2_S) -#define DMA2D_IN_PERI_SEL_CH2_V 0x00000007U -#define DMA2D_IN_PERI_SEL_CH2_S 0 - -/** DMA2D_IN_ARB_CH2_REG register - * Configures the rx arbiter of channel 2 - */ -#define DMA2D_IN_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x740) -/** DMA2D_IN_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_IN_ARB_TOKEN_NUM_CH2 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH2_M (DMA2D_IN_ARB_TOKEN_NUM_CH2_V << DMA2D_IN_ARB_TOKEN_NUM_CH2_S) -#define DMA2D_IN_ARB_TOKEN_NUM_CH2_V 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH2_S 0 -/** DMA2D_IN_ARB_PRIORITY_CH2 : R/W; bitpos: [4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_CH2 (BIT(4)) -#define DMA2D_IN_ARB_PRIORITY_CH2_M (DMA2D_IN_ARB_PRIORITY_CH2_V << DMA2D_IN_ARB_PRIORITY_CH2_S) -#define DMA2D_IN_ARB_PRIORITY_CH2_V 0x00000001U -#define DMA2D_IN_ARB_PRIORITY_CH2_S 4 -/** DMA2D_IN_ARB_PRIORITY_H_CH2 : R/W; bitpos: [7:5]; default: 0; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_H_CH2 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH2_M (DMA2D_IN_ARB_PRIORITY_H_CH2_V << DMA2D_IN_ARB_PRIORITY_H_CH2_S) -#define DMA2D_IN_ARB_PRIORITY_H_CH2_V 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH2_S 5 - -/** DMA2D_IN_RO_STATUS_CH2_REG register - * Represents the status of the rx reorder module of channel 2 - */ -#define DMA2D_IN_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x744) -/** DMA2D_INFIFO_RO_CNT_CH2 : RO; bitpos: [4:0]; default: 0; - * The register stores the byte number of the data in color convert Rx FIFO for - * channel 0. - */ -#define DMA2D_INFIFO_RO_CNT_CH2 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH2_M (DMA2D_INFIFO_RO_CNT_CH2_V << DMA2D_INFIFO_RO_CNT_CH2_S) -#define DMA2D_INFIFO_RO_CNT_CH2_V 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH2_S 0 -/** DMA2D_IN_RO_WR_STATE_CH2 : RO; bitpos: [6:5]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_IN_RO_WR_STATE_CH2 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH2_M (DMA2D_IN_RO_WR_STATE_CH2_V << DMA2D_IN_RO_WR_STATE_CH2_S) -#define DMA2D_IN_RO_WR_STATE_CH2_V 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH2_S 5 -/** DMA2D_IN_RO_RD_STATE_CH2 : RO; bitpos: [8:7]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_IN_RO_RD_STATE_CH2 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH2_M (DMA2D_IN_RO_RD_STATE_CH2_V << DMA2D_IN_RO_RD_STATE_CH2_S) -#define DMA2D_IN_RO_RD_STATE_CH2_V 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH2_S 7 -/** DMA2D_IN_PIXEL_BYTE_CH2 : RO; bitpos: [12:9]; default: 0; - * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_IN_PIXEL_BYTE_CH2 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH2_M (DMA2D_IN_PIXEL_BYTE_CH2_V << DMA2D_IN_PIXEL_BYTE_CH2_S) -#define DMA2D_IN_PIXEL_BYTE_CH2_V 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH2_S 9 -/** DMA2D_IN_BURST_BLOCK_NUM_CH2 : RO; bitpos: [16:13]; default: 0; - * the number of macro blocks contained in a burst of data at RX channel - */ -#define DMA2D_IN_BURST_BLOCK_NUM_CH2 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH2_M (DMA2D_IN_BURST_BLOCK_NUM_CH2_V << DMA2D_IN_BURST_BLOCK_NUM_CH2_S) -#define DMA2D_IN_BURST_BLOCK_NUM_CH2_V 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH2_S 13 - -/** DMA2D_IN_RO_PD_CONF_CH2_REG register - * Configures the rx reorder memory of channel 2 - */ -#define DMA2D_IN_RO_PD_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x748) -/** DMA2D_IN_RO_RAM_FORCE_PD_CH2 : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ -#define DMA2D_IN_RO_RAM_FORCE_PD_CH2 (BIT(4)) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH2_M (DMA2D_IN_RO_RAM_FORCE_PD_CH2_V << DMA2D_IN_RO_RAM_FORCE_PD_CH2_S) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH2_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PD_CH2_S 4 -/** DMA2D_IN_RO_RAM_FORCE_PU_CH2 : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ -#define DMA2D_IN_RO_RAM_FORCE_PU_CH2 (BIT(5)) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH2_M (DMA2D_IN_RO_RAM_FORCE_PU_CH2_V << DMA2D_IN_RO_RAM_FORCE_PU_CH2_S) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH2_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PU_CH2_S 5 -/** DMA2D_IN_RO_RAM_CLK_FO_CH2 : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ -#define DMA2D_IN_RO_RAM_CLK_FO_CH2 (BIT(6)) -#define DMA2D_IN_RO_RAM_CLK_FO_CH2_M (DMA2D_IN_RO_RAM_CLK_FO_CH2_V << DMA2D_IN_RO_RAM_CLK_FO_CH2_S) -#define DMA2D_IN_RO_RAM_CLK_FO_CH2_V 0x00000001U -#define DMA2D_IN_RO_RAM_CLK_FO_CH2_S 6 - -/** DMA2D_IN_COLOR_CONVERT_CH2_REG register - * Configures the Rx color convert of channel 2 - */ -#define DMA2D_IN_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x74c) -/** DMA2D_IN_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 - */ -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2_M (DMA2D_IN_COLOR_OUTPUT_SEL_CH2_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH2_S) -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2_V 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2_S 0 -/** DMA2D_IN_COLOR_3B_PROC_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_IN_COLOR_3B_PROC_EN_CH2 (BIT(2)) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH2_M (DMA2D_IN_COLOR_3B_PROC_EN_CH2_V << DMA2D_IN_COLOR_3B_PROC_EN_CH2_S) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH2_V 0x00000001U -#define DMA2D_IN_COLOR_3B_PROC_EN_CH2_S 2 -/** DMA2D_IN_COLOR_INPUT_SEL_CH2 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: YUV422/420 to YUV444 - * 1: YUV422 2: YUV444/420 7: disable color space convert - */ -#define DMA2D_IN_COLOR_INPUT_SEL_CH2 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH2_M (DMA2D_IN_COLOR_INPUT_SEL_CH2_V << DMA2D_IN_COLOR_INPUT_SEL_CH2_S) -#define DMA2D_IN_COLOR_INPUT_SEL_CH2_V 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH2_S 3 - -/** DMA2D_IN_SCRAMBLE_CH2_REG register - * Configures the rx scramble of channel 2 - */ -#define DMA2D_IN_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x750) -/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_M (DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_S) -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_S 0 -/** DMA2D_IN_SCRAMBLE_SEL_POST_CH2 : R/W; bitpos: [5:3]; default: 0; - * Scramble data after color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : BYTE1-0-2 - * 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2_M (DMA2D_IN_SCRAMBLE_SEL_POST_CH2_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH2_S) -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2_S 3 - -/** DMA2D_IN_COLOR_PARAM0_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x754) -/** DMA2D_IN_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H0_CH2 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH2_M (DMA2D_IN_COLOR_PARAM_H0_CH2_V << DMA2D_IN_COLOR_PARAM_H0_CH2_S) -#define DMA2D_IN_COLOR_PARAM_H0_CH2_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH2_S 0 - -/** DMA2D_IN_COLOR_PARAM1_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x758) -/** DMA2D_IN_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H1_CH2 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH2_M (DMA2D_IN_COLOR_PARAM_H1_CH2_V << DMA2D_IN_COLOR_PARAM_H1_CH2_S) -#define DMA2D_IN_COLOR_PARAM_H1_CH2_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH2_S 0 - -/** DMA2D_IN_COLOR_PARAM2_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x75c) -/** DMA2D_IN_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M0_CH2 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH2_M (DMA2D_IN_COLOR_PARAM_M0_CH2_V << DMA2D_IN_COLOR_PARAM_M0_CH2_S) -#define DMA2D_IN_COLOR_PARAM_M0_CH2_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH2_S 0 - -/** DMA2D_IN_COLOR_PARAM3_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x760) -/** DMA2D_IN_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M1_CH2 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH2_M (DMA2D_IN_COLOR_PARAM_M1_CH2_V << DMA2D_IN_COLOR_PARAM_M1_CH2_S) -#define DMA2D_IN_COLOR_PARAM_M1_CH2_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH2_S 0 - -/** DMA2D_IN_COLOR_PARAM4_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x764) -/** DMA2D_IN_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L0_CH2 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH2_M (DMA2D_IN_COLOR_PARAM_L0_CH2_V << DMA2D_IN_COLOR_PARAM_L0_CH2_S) -#define DMA2D_IN_COLOR_PARAM_L0_CH2_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH2_S 0 - -/** DMA2D_IN_COLOR_PARAM5_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x768) -/** DMA2D_IN_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L1_CH2 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH2_M (DMA2D_IN_COLOR_PARAM_L1_CH2_V << DMA2D_IN_COLOR_PARAM_L1_CH2_S) -#define DMA2D_IN_COLOR_PARAM_L1_CH2_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH2_S 0 - -/** DMA2D_IN_ETM_CONF_CH2_REG register - * Configures the rx etm of channel 2 - */ -#define DMA2D_IN_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x76c) -/** DMA2D_IN_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_EN_CH2 (BIT(0)) -#define DMA2D_IN_ETM_EN_CH2_M (DMA2D_IN_ETM_EN_CH2_V << DMA2D_IN_ETM_EN_CH2_S) -#define DMA2D_IN_ETM_EN_CH2_V 0x00000001U -#define DMA2D_IN_ETM_EN_CH2_S 0 -/** DMA2D_IN_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_LOOP_EN_CH2 (BIT(1)) -#define DMA2D_IN_ETM_LOOP_EN_CH2_M (DMA2D_IN_ETM_LOOP_EN_CH2_V << DMA2D_IN_ETM_LOOP_EN_CH2_S) -#define DMA2D_IN_ETM_LOOP_EN_CH2_V 0x00000001U -#define DMA2D_IN_ETM_LOOP_EN_CH2_S 1 -/** DMA2D_IN_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_IN_DSCR_TASK_MAK_CH2 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH2_M (DMA2D_IN_DSCR_TASK_MAK_CH2_V << DMA2D_IN_DSCR_TASK_MAK_CH2_S) -#define DMA2D_IN_DSCR_TASK_MAK_CH2_V 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH2_S 2 - -/** DMA2D_AXI_ERR_REG register - * Represents the status of th axi bus - */ -#define DMA2D_AXI_ERR_REG (DR_REG_DMA2D_BASE + 0xa00) -/** DMA2D_RID_ERR_CNT : RO; bitpos: [3:0]; default: 0; - * AXI read id err cnt - */ -#define DMA2D_RID_ERR_CNT 0x0000000FU -#define DMA2D_RID_ERR_CNT_M (DMA2D_RID_ERR_CNT_V << DMA2D_RID_ERR_CNT_S) -#define DMA2D_RID_ERR_CNT_V 0x0000000FU -#define DMA2D_RID_ERR_CNT_S 0 -/** DMA2D_RRESP_ERR_CNT : RO; bitpos: [7:4]; default: 0; - * AXI read resp err cnt - */ -#define DMA2D_RRESP_ERR_CNT 0x0000000FU -#define DMA2D_RRESP_ERR_CNT_M (DMA2D_RRESP_ERR_CNT_V << DMA2D_RRESP_ERR_CNT_S) -#define DMA2D_RRESP_ERR_CNT_V 0x0000000FU -#define DMA2D_RRESP_ERR_CNT_S 4 -/** DMA2D_WRESP_ERR_CNT : RO; bitpos: [11:8]; default: 0; - * AXI write resp err cnt - */ -#define DMA2D_WRESP_ERR_CNT 0x0000000FU -#define DMA2D_WRESP_ERR_CNT_M (DMA2D_WRESP_ERR_CNT_V << DMA2D_WRESP_ERR_CNT_S) -#define DMA2D_WRESP_ERR_CNT_V 0x0000000FU -#define DMA2D_WRESP_ERR_CNT_S 8 -/** DMA2D_RD_FIFO_CNT : RO; bitpos: [14:12]; default: 0; - * AXI read cmd fifo remain cmd count - */ -#define DMA2D_RD_FIFO_CNT 0x00000007U -#define DMA2D_RD_FIFO_CNT_M (DMA2D_RD_FIFO_CNT_V << DMA2D_RD_FIFO_CNT_S) -#define DMA2D_RD_FIFO_CNT_V 0x00000007U -#define DMA2D_RD_FIFO_CNT_S 12 -/** DMA2D_RD_BAK_FIFO_CNT : RO; bitpos: [18:15]; default: 0; - * AXI read backup cmd fifo remain cmd count - */ -#define DMA2D_RD_BAK_FIFO_CNT 0x0000000FU -#define DMA2D_RD_BAK_FIFO_CNT_M (DMA2D_RD_BAK_FIFO_CNT_V << DMA2D_RD_BAK_FIFO_CNT_S) -#define DMA2D_RD_BAK_FIFO_CNT_V 0x0000000FU -#define DMA2D_RD_BAK_FIFO_CNT_S 15 -/** DMA2D_WR_FIFO_CNT : RO; bitpos: [21:19]; default: 0; - * AXI write cmd fifo remain cmd count - */ -#define DMA2D_WR_FIFO_CNT 0x00000007U -#define DMA2D_WR_FIFO_CNT_M (DMA2D_WR_FIFO_CNT_V << DMA2D_WR_FIFO_CNT_S) -#define DMA2D_WR_FIFO_CNT_V 0x00000007U -#define DMA2D_WR_FIFO_CNT_S 19 -/** DMA2D_WR_BAK_FIFO_CNT : RO; bitpos: [25:22]; default: 0; - * AXI write backup cmd fifo remain cmd count - */ -#define DMA2D_WR_BAK_FIFO_CNT 0x0000000FU -#define DMA2D_WR_BAK_FIFO_CNT_M (DMA2D_WR_BAK_FIFO_CNT_V << DMA2D_WR_BAK_FIFO_CNT_S) -#define DMA2D_WR_BAK_FIFO_CNT_V 0x0000000FU -#define DMA2D_WR_BAK_FIFO_CNT_S 22 - -/** DMA2D_RST_CONF_REG register - * Configures the reset of axi - */ -#define DMA2D_RST_CONF_REG (DR_REG_DMA2D_BASE + 0xa04) -/** DMA2D_AXIM_RD_RST : R/W; bitpos: [0]; default: 0; - * Write 1 then write 0 to this bit to reset axi master read data FIFO. - */ -#define DMA2D_AXIM_RD_RST (BIT(0)) -#define DMA2D_AXIM_RD_RST_M (DMA2D_AXIM_RD_RST_V << DMA2D_AXIM_RD_RST_S) -#define DMA2D_AXIM_RD_RST_V 0x00000001U -#define DMA2D_AXIM_RD_RST_S 0 -/** DMA2D_AXIM_WR_RST : R/W; bitpos: [1]; default: 0; - * Write 1 then write 0 to this bit to reset axi master write data FIFO. - */ -#define DMA2D_AXIM_WR_RST (BIT(1)) -#define DMA2D_AXIM_WR_RST_M (DMA2D_AXIM_WR_RST_V << DMA2D_AXIM_WR_RST_S) -#define DMA2D_AXIM_WR_RST_V 0x00000001U -#define DMA2D_AXIM_WR_RST_S 1 -/** DMA2D_CLK_EN : R/W; bitpos: [2]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes - * registers. - */ -#define DMA2D_CLK_EN (BIT(2)) -#define DMA2D_CLK_EN_M (DMA2D_CLK_EN_V << DMA2D_CLK_EN_S) -#define DMA2D_CLK_EN_V 0x00000001U -#define DMA2D_CLK_EN_S 2 - -/** DMA2D_INTR_MEM_START_ADDR_REG register - * The start address of accessible address space. - */ -#define DMA2D_INTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa08) -/** DMA2D_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ -#define DMA2D_ACCESS_INTR_MEM_START_ADDR 0xFFFFFFFFU -#define DMA2D_ACCESS_INTR_MEM_START_ADDR_M (DMA2D_ACCESS_INTR_MEM_START_ADDR_V << DMA2D_ACCESS_INTR_MEM_START_ADDR_S) -#define DMA2D_ACCESS_INTR_MEM_START_ADDR_V 0xFFFFFFFFU -#define DMA2D_ACCESS_INTR_MEM_START_ADDR_S 0 - -/** DMA2D_INTR_MEM_END_ADDR_REG register - * The end address of accessible address space. - */ -#define DMA2D_INTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa0c) -/** DMA2D_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ -#define DMA2D_ACCESS_INTR_MEM_END_ADDR 0xFFFFFFFFU -#define DMA2D_ACCESS_INTR_MEM_END_ADDR_M (DMA2D_ACCESS_INTR_MEM_END_ADDR_V << DMA2D_ACCESS_INTR_MEM_END_ADDR_S) -#define DMA2D_ACCESS_INTR_MEM_END_ADDR_V 0xFFFFFFFFU -#define DMA2D_ACCESS_INTR_MEM_END_ADDR_S 0 - -/** DMA2D_EXTR_MEM_START_ADDR_REG register - * The start address of accessible address space. - */ -#define DMA2D_EXTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa10) -/** DMA2D_ACCESS_EXTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ -#define DMA2D_ACCESS_EXTR_MEM_START_ADDR 0xFFFFFFFFU -#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_M (DMA2D_ACCESS_EXTR_MEM_START_ADDR_V << DMA2D_ACCESS_EXTR_MEM_START_ADDR_S) -#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_V 0xFFFFFFFFU -#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_S 0 - -/** DMA2D_EXTR_MEM_END_ADDR_REG register - * The end address of accessible address space. - */ -#define DMA2D_EXTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa14) -/** DMA2D_ACCESS_EXTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ -#define DMA2D_ACCESS_EXTR_MEM_END_ADDR 0xFFFFFFFFU -#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_M (DMA2D_ACCESS_EXTR_MEM_END_ADDR_V << DMA2D_ACCESS_EXTR_MEM_END_ADDR_S) -#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_V 0xFFFFFFFFU -#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_S 0 - -/** DMA2D_OUT_ARB_CONFIG_REG register - * Configures the tx arbiter - */ -#define DMA2D_OUT_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa18) -/** DMA2D_OUT_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0; - * Set the max number of timeout count of arbiter - */ -#define DMA2D_OUT_ARB_TIMEOUT_NUM 0x0000FFFFU -#define DMA2D_OUT_ARB_TIMEOUT_NUM_M (DMA2D_OUT_ARB_TIMEOUT_NUM_V << DMA2D_OUT_ARB_TIMEOUT_NUM_S) -#define DMA2D_OUT_ARB_TIMEOUT_NUM_V 0x0000FFFFU -#define DMA2D_OUT_ARB_TIMEOUT_NUM_S 0 -/** DMA2D_OUT_WEIGHT_EN : R/W; bitpos: [16]; default: 0; - * reserved - */ -#define DMA2D_OUT_WEIGHT_EN (BIT(16)) -#define DMA2D_OUT_WEIGHT_EN_M (DMA2D_OUT_WEIGHT_EN_V << DMA2D_OUT_WEIGHT_EN_S) -#define DMA2D_OUT_WEIGHT_EN_V 0x00000001U -#define DMA2D_OUT_WEIGHT_EN_S 16 - -/** DMA2D_IN_ARB_CONFIG_REG register - * Configures the rx arbiter - */ -#define DMA2D_IN_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa1c) -/** DMA2D_IN_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0; - * Set the max number of timeout count of arbiter - */ -#define DMA2D_IN_ARB_TIMEOUT_NUM 0x0000FFFFU -#define DMA2D_IN_ARB_TIMEOUT_NUM_M (DMA2D_IN_ARB_TIMEOUT_NUM_V << DMA2D_IN_ARB_TIMEOUT_NUM_S) -#define DMA2D_IN_ARB_TIMEOUT_NUM_V 0x0000FFFFU -#define DMA2D_IN_ARB_TIMEOUT_NUM_S 0 -/** DMA2D_IN_WEIGHT_EN : R/W; bitpos: [16]; default: 0; - * reserved - */ -#define DMA2D_IN_WEIGHT_EN (BIT(16)) -#define DMA2D_IN_WEIGHT_EN_M (DMA2D_IN_WEIGHT_EN_V << DMA2D_IN_WEIGHT_EN_S) -#define DMA2D_IN_WEIGHT_EN_V 0x00000001U -#define DMA2D_IN_WEIGHT_EN_S 16 - -/** DMA2D_RDN_RESULT_REG register - * reserved - */ -#define DMA2D_RDN_RESULT_REG (DR_REG_DMA2D_BASE + 0xa20) -/** DMA2D_RDN_ENA : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define DMA2D_RDN_ENA (BIT(0)) -#define DMA2D_RDN_ENA_M (DMA2D_RDN_ENA_V << DMA2D_RDN_ENA_S) -#define DMA2D_RDN_ENA_V 0x00000001U -#define DMA2D_RDN_ENA_S 0 -/** DMA2D_RDN_RESULT : RO; bitpos: [1]; default: 0; - * reserved - */ -#define DMA2D_RDN_RESULT (BIT(1)) -#define DMA2D_RDN_RESULT_M (DMA2D_RDN_RESULT_V << DMA2D_RDN_RESULT_S) -#define DMA2D_RDN_RESULT_V 0x00000001U -#define DMA2D_RDN_RESULT_S 1 - -/** DMA2D_RDN_ECO_HIGH_REG register - * reserved - */ -#define DMA2D_RDN_ECO_HIGH_REG (DR_REG_DMA2D_BASE + 0xa24) -/** DMA2D_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; - * The start address of accessible address space. - */ -#define DMA2D_RDN_ECO_HIGH 0xFFFFFFFFU -#define DMA2D_RDN_ECO_HIGH_M (DMA2D_RDN_ECO_HIGH_V << DMA2D_RDN_ECO_HIGH_S) -#define DMA2D_RDN_ECO_HIGH_V 0xFFFFFFFFU -#define DMA2D_RDN_ECO_HIGH_S 0 - -/** DMA2D_RDN_ECO_LOW_REG register - * reserved - */ -#define DMA2D_RDN_ECO_LOW_REG (DR_REG_DMA2D_BASE + 0xa28) -/** DMA2D_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; - * The start address of accessible address space. - */ -#define DMA2D_RDN_ECO_LOW 0xFFFFFFFFU -#define DMA2D_RDN_ECO_LOW_M (DMA2D_RDN_ECO_LOW_V << DMA2D_RDN_ECO_LOW_S) -#define DMA2D_RDN_ECO_LOW_V 0xFFFFFFFFU -#define DMA2D_RDN_ECO_LOW_S 0 - -/** DMA2D_DATE_REG register - * register version. - */ -#define DMA2D_DATE_REG (DR_REG_DMA2D_BASE + 0xa2c) -/** DMA2D_DATE : R/W; bitpos: [31:0]; default: 37822864; - * register version. - */ -#define DMA2D_DATE 0xFFFFFFFFU -#define DMA2D_DATE_M (DMA2D_DATE_V << DMA2D_DATE_S) -#define DMA2D_DATE_V 0xFFFFFFFFU -#define DMA2D_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_struct.h deleted file mode 100644 index d637f6ecabe9..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_struct.h +++ /dev/null @@ -1,2085 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of out_conf0_chn register - * Configures the tx direction of channel n - */ -typedef union { - struct { - /** out_auto_wrback_chn : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ - uint32_t out_auto_wrback_chn:1; - /** out_eof_mode_chn : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ - uint32_t out_eof_mode_chn:1; - /** outdscr_burst_en_chn : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t outdscr_burst_en_chn:1; - /** out_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t out_ecc_aes_en_chn:1; - /** out_check_owner_chn : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t out_check_owner_chn:1; - /** out_loop_test_chn : R/W; bitpos: [5]; default: 0; - * reserved - */ - uint32_t out_loop_test_chn:1; - /** out_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t out_mem_burst_length_chn:3; - /** out_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0; - * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ - uint32_t out_macro_block_size_chn:2; - /** out_dscr_port_en_chn : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ - uint32_t out_dscr_port_en_chn:1; - /** out_page_bound_en_chn : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ - uint32_t out_page_bound_en_chn:1; - uint32_t reserved_13:3; - /** out_reorder_en_chn : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ - uint32_t out_reorder_en_chn:1; - uint32_t reserved_17:7; - /** out_rst_chn : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ - uint32_t out_rst_chn:1; - /** out_cmd_disable_chn : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t out_cmd_disable_chn:1; - /** out_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t out_arb_weight_opt_dis_chn:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} dma2d_out_conf0_chn_reg_t; - -/** Type of out_push_chn register - * Configures the tx fifo of channel n - */ -typedef union { - struct { - /** outfifo_wdata_chn : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ - uint32_t outfifo_wdata_chn:10; - /** outfifo_push_chn : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ - uint32_t outfifo_push_chn:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} dma2d_out_push_chn_reg_t; - -/** Type of out_link_conf_chn register - * Configures the tx descriptor operations of channel n - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** outlink_stop_chn : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - uint32_t outlink_stop_chn:1; - /** outlink_start_chn : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - uint32_t outlink_start_chn:1; - /** outlink_restart_chn : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - uint32_t outlink_restart_chn:1; - /** outlink_park_chn : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ - uint32_t outlink_park_chn:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} dma2d_out_link_conf_chn_reg_t; - -/** Type of out_link_addr_chn register - * Configures the tx descriptor address of channel n - */ -typedef union { - struct { - /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ - uint32_t outlink_addr_chn:32; - }; - uint32_t val; -} dma2d_out_link_addr_chn_reg_t; - -/** Type of out_arb_chn register - * Configures the tx arbiter of channel n - */ -typedef union { - struct { - /** out_arb_token_num_chn : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t out_arb_token_num_chn:4; - /** out_arb_priority_chn : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ - uint32_t out_arb_priority_chn:2; - /** out_arb_priority_h_chn : R/W; bitpos: [7:6]; default: 0; - * Set the priority of channel - */ - uint32_t out_arb_priority_h_chn:2; - uint32_t reserved_8:24; - }; - uint32_t val; -} dma2d_out_arb_chn_reg_t; - -/** Type of out_ro_pd_conf_chn register - * Configures the tx reorder memory of channel 0 - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** out_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ - uint32_t out_ro_ram_force_pd_chn:1; - /** out_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ - uint32_t out_ro_ram_force_pu_chn:1; - /** out_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ - uint32_t out_ro_ram_clk_fo_chn:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} dma2d_out_ro_pd_conf_chn_reg_t; - -/** Type of out_color_convert_chn register - * Configures the tx color convert of channel n - */ -typedef union { - struct { - /** out_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * YUV444 to YUV422 2: output directly - */ - uint32_t out_color_output_sel_chn:2; - /** out_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ - uint32_t out_color_3b_proc_en_chn:1; - /** out_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: RGB565 to RGB888 1: - * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: - * disable color space convert - */ - uint32_t out_color_input_sel_chn:3; - uint32_t reserved_6:26; - }; - uint32_t val; -} dma2d_out_color_convert_chn_reg_t; - -/** Type of out_scramble_chn register - * Configures the tx scramble of channel n - */ -typedef union { - struct { - /** out_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ - uint32_t out_scramble_sel_pre_chn:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} dma2d_out_scramble_chn_reg_t; - -/** Type of out_color_param0_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_h0_chn : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ - uint32_t out_color_param_h0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_out_color_param0_chn_reg_t; - -/** Type of out_color_param1_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_h1_chn : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ - uint32_t out_color_param_h1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_out_color_param1_chn_reg_t; - -/** Type of out_color_param2_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_m0_chn : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ - uint32_t out_color_param_m0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_out_color_param2_chn_reg_t; - -/** Type of out_color_param3_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_m1_chn : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ - uint32_t out_color_param_m1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_out_color_param3_chn_reg_t; - -/** Type of out_color_param4_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_l0_chn : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ - uint32_t out_color_param_l0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_out_color_param4_chn_reg_t; - -/** Type of out_color_param5_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_l1_chn : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ - uint32_t out_color_param_l1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_out_color_param5_chn_reg_t; - -/** Type of out_etm_conf_chn register - * Configures the tx etm of channel n - */ -typedef union { - struct { - /** out_etm_en_chn : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ - uint32_t out_etm_en_chn:1; - /** out_etm_loop_en_chn : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ - uint32_t out_etm_loop_en_chn:1; - /** out_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ - uint32_t out_dscr_task_mak_chn:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} dma2d_out_etm_conf_chn_reg_t; - -/** Type of out_dscr_port_blk_chn register - * Configures the tx block size in dscr port mode - */ -typedef union { - struct { - /** out_dscr_port_blk_h_chn : R/W; bitpos: [13:0]; default: 18; - * Set the vertical height of tx block size in dscr port mode - */ - uint32_t out_dscr_port_blk_h_chn:14; - /** out_dscr_port_blk_v_chn : R/W; bitpos: [27:14]; default: 18; - * Set the horizontal width of tx block size in dscr port mode - */ - uint32_t out_dscr_port_blk_v_chn:14; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_out_dscr_port_blk_chn_reg_t; - -/** Type of in_conf0_chn register - * Configures the rx direction of channel n - */ -typedef union { - struct { - /** in_mem_trans_en_chn : R/W; bitpos: [0]; default: 0; - * enable memory trans of the same channel - */ - uint32_t in_mem_trans_en_chn:1; - uint32_t reserved_1:1; - /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ - uint32_t indscr_burst_en_chn:1; - /** in_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t in_ecc_aes_en_chn:1; - /** in_check_owner_chn : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t in_check_owner_chn:1; - /** in_loop_test_chn : R/W; bitpos: [5]; default: 0; - * reserved - */ - uint32_t in_loop_test_chn:1; - /** in_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t in_mem_burst_length_chn:3; - /** in_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0; - * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ - uint32_t in_macro_block_size_chn:2; - /** in_dscr_port_en_chn : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ - uint32_t in_dscr_port_en_chn:1; - /** in_page_bound_en_chn : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ - uint32_t in_page_bound_en_chn:1; - uint32_t reserved_13:3; - /** in_reorder_en_chn : R/W; bitpos: [16]; default: 0; - * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ - uint32_t in_reorder_en_chn:1; - uint32_t reserved_17:7; - /** in_rst_chn : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ - uint32_t in_rst_chn:1; - /** in_cmd_disable_chn : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t in_cmd_disable_chn:1; - /** in_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t in_arb_weight_opt_dis_chn:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} dma2d_in_conf0_chn_reg_t; - -/** Type of in_pop_chn register - * Configures the rx fifo of channel n - */ -typedef union { - struct { - /** infifo_rdata_chn : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ - uint32_t infifo_rdata_chn:11; - /** infifo_pop_chn : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ - uint32_t infifo_pop_chn:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} dma2d_in_pop_chn_reg_t; - -/** Type of in_link_conf_chn register - * Configures the rx descriptor operations of channel n - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ - uint32_t inlink_auto_ret_chn:1; - /** inlink_stop_chn : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ - uint32_t inlink_stop_chn:1; - /** inlink_start_chn : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ - uint32_t inlink_start_chn:1; - /** inlink_restart_chn : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ - uint32_t inlink_restart_chn:1; - /** inlink_park_chn : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ - uint32_t inlink_park_chn:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} dma2d_in_link_conf_chn_reg_t; - -/** Type of in_link_addr_chn register - * Configures the rx descriptor address of channel n - */ -typedef union { - struct { - /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ - uint32_t inlink_addr_chn:32; - }; - uint32_t val; -} dma2d_in_link_addr_chn_reg_t; - -/** Type of in_arb_chn register - * Configures the rx arbiter of channel n - */ -typedef union { - struct { - /** in_arb_token_num_chn : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t in_arb_token_num_chn:4; - /** in_arb_priority_chn : R/W; bitpos: [4]; default: 1; - * Set the priority of channel - */ - uint32_t in_arb_priority_chn:1; - /** in_arb_priority_h_chn : R/W; bitpos: [7:5]; default: 0; - * Set the priority of channel - */ - uint32_t in_arb_priority_h_chn:3; - uint32_t reserved_8:24; - }; - uint32_t val; -} dma2d_in_arb_chn_reg_t; - -/** Type of in_ro_pd_conf_chn register - * Configures the rx reorder memory of channel n - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** in_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ - uint32_t in_ro_ram_force_pd_chn:1; - /** in_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ - uint32_t in_ro_ram_force_pu_chn:1; - /** in_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ - uint32_t in_ro_ram_clk_fo_chn:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} dma2d_in_ro_pd_conf_chn_reg_t; - -/** Type of in_color_convert_chn register - * Configures the Rx color convert of channel n - */ -typedef union { - struct { - /** in_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 - */ - uint32_t in_color_output_sel_chn:2; - /** in_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ - uint32_t in_color_3b_proc_en_chn:1; - /** in_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: YUV422/420 to YUV444 - * 1: YUV422 2: YUV444/420 7: disable color space convert - */ - uint32_t in_color_input_sel_chn:3; - uint32_t reserved_6:26; - }; - uint32_t val; -} dma2d_in_color_convert_chn_reg_t; - -/** Type of in_scramble_chn register - * Configures the rx scramble of channel n - */ -typedef union { - struct { - /** in_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ - uint32_t in_scramble_sel_pre_chn:3; - /** in_scramble_sel_post_chn : R/W; bitpos: [5:3]; default: 0; - * Scramble data after color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : BYTE1-0-2 - * 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ - uint32_t in_scramble_sel_post_chn:3; - uint32_t reserved_6:26; - }; - uint32_t val; -} dma2d_in_scramble_chn_reg_t; - -/** Type of in_color_param0_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_h0_chn : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ - uint32_t in_color_param_h0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_in_color_param0_chn_reg_t; - -/** Type of in_color_param1_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_h1_chn : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ - uint32_t in_color_param_h1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_in_color_param1_chn_reg_t; - -/** Type of in_color_param2_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_m0_chn : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ - uint32_t in_color_param_m0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_in_color_param2_chn_reg_t; - -/** Type of in_color_param3_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_m1_chn : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ - uint32_t in_color_param_m1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_in_color_param3_chn_reg_t; - -/** Type of in_color_param4_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_l0_chn : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ - uint32_t in_color_param_l0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_in_color_param4_chn_reg_t; - -/** Type of in_color_param5_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_l1_chn : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ - uint32_t in_color_param_l1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_in_color_param5_chn_reg_t; - -/** Type of in_etm_conf_chn register - * Configures the rx etm of channel n - */ -typedef union { - struct { - /** in_etm_en_chn : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ - uint32_t in_etm_en_chn:1; - /** in_etm_loop_en_chn : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ - uint32_t in_etm_loop_en_chn:1; - /** in_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ - uint32_t in_dscr_task_mak_chn:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} dma2d_in_etm_conf_chn_reg_t; - -/** Type of rst_conf register - * Configures the reset of axi - */ -typedef union { - struct { - /** axim_rd_rst : R/W; bitpos: [0]; default: 0; - * Write 1 then write 0 to this bit to reset axi master read data FIFO. - */ - uint32_t axim_rd_rst:1; - /** axim_wr_rst : R/W; bitpos: [1]; default: 0; - * Write 1 then write 0 to this bit to reset axi master write data FIFO. - */ - uint32_t axim_wr_rst:1; - /** clk_en : R/W; bitpos: [2]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes - * registers. - */ - uint32_t clk_en:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} dma2d_rst_conf_reg_t; - -/** Type of intr_mem_start_addr register - * The start address of accessible address space. - */ -typedef union { - struct { - /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ - uint32_t access_intr_mem_start_addr:32; - }; - uint32_t val; -} dma2d_intr_mem_start_addr_reg_t; - -/** Type of intr_mem_end_addr register - * The end address of accessible address space. - */ -typedef union { - struct { - /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ - uint32_t access_intr_mem_end_addr:32; - }; - uint32_t val; -} dma2d_intr_mem_end_addr_reg_t; - -/** Type of extr_mem_start_addr register - * The start address of accessible address space. - */ -typedef union { - struct { - /** access_extr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ - uint32_t access_extr_mem_start_addr:32; - }; - uint32_t val; -} dma2d_extr_mem_start_addr_reg_t; - -/** Type of extr_mem_end_addr register - * The end address of accessible address space. - */ -typedef union { - struct { - /** access_extr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ - uint32_t access_extr_mem_end_addr:32; - }; - uint32_t val; -} dma2d_extr_mem_end_addr_reg_t; - -/** Type of out_arb_config register - * Configures the tx arbiter - */ -typedef union { - struct { - /** out_arb_timeout_num : R/W; bitpos: [15:0]; default: 0; - * Set the max number of timeout count of arbiter - */ - uint32_t out_arb_timeout_num:16; - /** out_weight_en : R/W; bitpos: [16]; default: 0; - * reserved - */ - uint32_t out_weight_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} dma2d_out_arb_config_reg_t; - -/** Type of in_arb_config register - * Configures the rx arbiter - */ -typedef union { - struct { - /** in_arb_timeout_num : R/W; bitpos: [15:0]; default: 0; - * Set the max number of timeout count of arbiter - */ - uint32_t in_arb_timeout_num:16; - /** in_weight_en : R/W; bitpos: [16]; default: 0; - * reserved - */ - uint32_t in_weight_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} dma2d_in_arb_config_reg_t; - -/** Type of rdn_result register - * reserved - */ -typedef union { - struct { - /** rdn_ena : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t rdn_ena:1; - /** rdn_result : RO; bitpos: [1]; default: 0; - * reserved - */ - uint32_t rdn_result:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} dma2d_rdn_result_reg_t; - -/** Type of rdn_eco_high register - * reserved - */ -typedef union { - struct { - /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; - * The start address of accessible address space. - */ - uint32_t rdn_eco_high:32; - }; - uint32_t val; -} dma2d_rdn_eco_high_reg_t; - -/** Type of rdn_eco_low register - * reserved - */ -typedef union { - struct { - /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0; - * The start address of accessible address space. - */ - uint32_t rdn_eco_low:32; - }; - uint32_t val; -} dma2d_rdn_eco_low_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of out_int_raw_chn register - * Raw interrupt status of TX channel n - */ -typedef union { - struct { - /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ - uint32_t out_done_chn_int_raw:1; - /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ - uint32_t out_eof_chn_int_raw:1; - /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ - uint32_t out_dscr_err_chn_int_raw:1; - /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ - uint32_t out_total_eof_chn_int_raw:1; - /** outfifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l1_chn_int_raw:1; - /** outfifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l1_chn_int_raw:1; - /** outfifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l2_chn_int_raw:1; - /** outfifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l2_chn_int_raw:1; - /** outfifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l3_chn_int_raw:1; - /** outfifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l3_chn_int_raw:1; - /** outfifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ - uint32_t outfifo_ro_ovf_chn_int_raw:1; - /** outfifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ - uint32_t outfifo_ro_udf_chn_int_raw:1; - /** out_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t out_dscr_task_ovf_chn_int_raw:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} dma2d_out_int_raw_chn_reg_t; - -/** Type of out_int_ena_chn register - * Interrupt enable bits of TX channel n - */ -typedef union { - struct { - /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_chn_int_ena:1; - /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_chn_int_ena:1; - /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_chn_int_ena:1; - /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_chn_int_ena:1; - /** outfifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_chn_int_ena:1; - /** outfifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_chn_int_ena:1; - /** outfifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_chn_int_ena:1; - /** outfifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_chn_int_ena:1; - /** outfifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l3_chn_int_ena:1; - /** outfifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t outfifo_udf_l3_chn_int_ena:1; - /** outfifo_ro_ovf_chn_int_ena : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t outfifo_ro_ovf_chn_int_ena:1; - /** outfifo_ro_udf_chn_int_ena : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t outfifo_ro_udf_chn_int_ena:1; - /** out_dscr_task_ovf_chn_int_ena : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_chn_int_ena:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} dma2d_out_int_ena_chn_reg_t; - -/** Type of out_int_st_chn register - * Masked interrupt status of TX channel n - */ -typedef union { - struct { - /** out_done_chn_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_chn_int_st:1; - /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_chn_int_st:1; - /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_chn_int_st:1; - /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_chn_int_st:1; - /** outfifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_chn_int_st:1; - /** outfifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_chn_int_st:1; - /** outfifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_chn_int_st:1; - /** outfifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_chn_int_st:1; - /** outfifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l3_chn_int_st:1; - /** outfifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t outfifo_udf_l3_chn_int_st:1; - /** outfifo_ro_ovf_chn_int_st : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t outfifo_ro_ovf_chn_int_st:1; - /** outfifo_ro_udf_chn_int_st : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t outfifo_ro_udf_chn_int_st:1; - /** out_dscr_task_ovf_chn_int_st : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_chn_int_st:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} dma2d_out_int_st_chn_reg_t; - -/** Type of out_int_clr_chn register - * Interrupt clear bits of TX channel n - */ -typedef union { - struct { - /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_chn_int_clr:1; - /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_chn_int_clr:1; - /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_chn_int_clr:1; - /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_chn_int_clr:1; - /** outfifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_chn_int_clr:1; - /** outfifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_chn_int_clr:1; - /** outfifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_chn_int_clr:1; - /** outfifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_chn_int_clr:1; - /** outfifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l3_chn_int_clr:1; - /** outfifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t outfifo_udf_l3_chn_int_clr:1; - /** outfifo_ro_ovf_chn_int_clr : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t outfifo_ro_ovf_chn_int_clr:1; - /** outfifo_ro_udf_chn_int_clr : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t outfifo_ro_udf_chn_int_clr:1; - /** out_dscr_task_ovf_chn_int_clr : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_chn_int_clr:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} dma2d_out_int_clr_chn_reg_t; - -/** Type of in_int_raw_chn register - * Raw interrupt status of RX channel n - */ -typedef union { - struct { - /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 0. - */ - uint32_t in_done_chn_int_raw:1; - /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 0. - */ - uint32_t in_suc_eof_chn_int_raw:1; - /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ - uint32_t in_err_eof_chn_int_raw:1; - /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 0. - */ - uint32_t in_dscr_err_chn_int_raw:1; - /** infifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l1_chn_int_raw:1; - /** infifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l1_chn_int_raw:1; - /** infifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l2_chn_int_raw:1; - /** infifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l2_chn_int_raw:1; - /** infifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l3_chn_int_raw:1; - /** infifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l3_chn_int_raw:1; - /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ - uint32_t in_dscr_empty_chn_int_raw:1; - /** infifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ - uint32_t infifo_ro_ovf_chn_int_raw:1; - /** infifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ - uint32_t infifo_ro_udf_chn_int_raw:1; - /** in_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t in_dscr_task_ovf_chn_int_raw:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} dma2d_in_int_raw_chn_reg_t; - -/** Type of in_int_ena_chn register - * Interrupt enable bits of RX channel n - */ -typedef union { - struct { - /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_chn_int_ena:1; - /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_chn_int_ena:1; - /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_chn_int_ena:1; - /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_chn_int_ena:1; - /** infifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_chn_int_ena:1; - /** infifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_chn_int_ena:1; - /** infifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_chn_int_ena:1; - /** infifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_chn_int_ena:1; - /** infifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t infifo_ovf_l3_chn_int_ena:1; - /** infifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t infifo_udf_l3_chn_int_ena:1; - /** in_dscr_empty_chn_int_ena : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_chn_int_ena:1; - /** infifo_ro_ovf_chn_int_ena : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t infifo_ro_ovf_chn_int_ena:1; - /** infifo_ro_udf_chn_int_ena : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t infifo_ro_udf_chn_int_ena:1; - /** in_dscr_task_ovf_chn_int_ena : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_chn_int_ena:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} dma2d_in_int_ena_chn_reg_t; - -/** Type of in_int_st_chn register - * Masked interrupt status of RX channel n - */ -typedef union { - struct { - /** in_done_chn_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_chn_int_st:1; - /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_chn_int_st:1; - /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_chn_int_st:1; - /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_chn_int_st:1; - /** infifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_chn_int_st:1; - /** infifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_chn_int_st:1; - /** infifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_chn_int_st:1; - /** infifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_chn_int_st:1; - /** infifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t infifo_ovf_l3_chn_int_st:1; - /** infifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t infifo_udf_l3_chn_int_st:1; - /** in_dscr_empty_chn_int_st : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_chn_int_st:1; - /** infifo_ro_ovf_chn_int_st : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t infifo_ro_ovf_chn_int_st:1; - /** infifo_ro_udf_chn_int_st : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t infifo_ro_udf_chn_int_st:1; - /** in_dscr_task_ovf_chn_int_st : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_chn_int_st:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} dma2d_in_int_st_chn_reg_t; - -/** Type of in_int_clr_chn register - * Interrupt clear bits of RX channel n - */ -typedef union { - struct { - /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_chn_int_clr:1; - /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_chn_int_clr:1; - /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_chn_int_clr:1; - /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_chn_int_clr:1; - /** infifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_chn_int_clr:1; - /** infifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_chn_int_clr:1; - /** infifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_chn_int_clr:1; - /** infifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_chn_int_clr:1; - /** infifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t infifo_ovf_l3_chn_int_clr:1; - /** infifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t infifo_udf_l3_chn_int_clr:1; - /** in_dscr_empty_chn_int_clr : WT; bitpos: [10]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_chn_int_clr:1; - /** infifo_ro_ovf_chn_int_clr : WT; bitpos: [11]; default: 0; - * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t infifo_ro_ovf_chn_int_clr:1; - /** infifo_ro_udf_chn_int_clr : WT; bitpos: [12]; default: 0; - * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t infifo_ro_udf_chn_int_clr:1; - /** in_dscr_task_ovf_chn_int_clr : WT; bitpos: [13]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_chn_int_clr:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} dma2d_in_int_clr_chn_reg_t; - - -/** Group: Status Registers */ -/** Type of outfifo_status_chn register - * Represents the status of the tx fifo of channel n - */ -typedef union { - struct { - /** outfifo_full_l2_chn : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ - uint32_t outfifo_full_l2_chn:1; - /** outfifo_empty_l2_chn : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ - uint32_t outfifo_empty_l2_chn:1; - /** outfifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ - uint32_t outfifo_cnt_l2_chn:4; - uint32_t reserved_6:1; - /** out_remain_under_1b_chn : RO; bitpos: [7]; default: 1; - * reserved - */ - uint32_t out_remain_under_1b_chn:1; - /** out_remain_under_2b_chn : RO; bitpos: [8]; default: 1; - * reserved - */ - uint32_t out_remain_under_2b_chn:1; - /** out_remain_under_3b_chn : RO; bitpos: [9]; default: 1; - * reserved - */ - uint32_t out_remain_under_3b_chn:1; - /** out_remain_under_4b_chn : RO; bitpos: [10]; default: 1; - * reserved - */ - uint32_t out_remain_under_4b_chn:1; - /** out_remain_under_5b_chn : RO; bitpos: [11]; default: 1; - * reserved - */ - uint32_t out_remain_under_5b_chn:1; - /** out_remain_under_6b_chn : RO; bitpos: [12]; default: 1; - * reserved - */ - uint32_t out_remain_under_6b_chn:1; - /** out_remain_under_7b_chn : RO; bitpos: [13]; default: 1; - * reserved - */ - uint32_t out_remain_under_7b_chn:1; - /** out_remain_under_8b_chn : RO; bitpos: [14]; default: 1; - * reserved - */ - uint32_t out_remain_under_8b_chn:1; - /** outfifo_full_l1_chn : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ - uint32_t outfifo_full_l1_chn:1; - /** outfifo_empty_l1_chn : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ - uint32_t outfifo_empty_l1_chn:1; - /** outfifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ - uint32_t outfifo_cnt_l1_chn:5; - /** outfifo_full_l3_chn : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ - uint32_t outfifo_full_l3_chn:1; - /** outfifo_empty_l3_chn : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ - uint32_t outfifo_empty_l3_chn:1; - /** outfifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ - uint32_t outfifo_cnt_l3_chn:5; - uint32_t reserved_29:3; - }; - uint32_t val; -} dma2d_outfifo_status_chn_reg_t; - -/** Type of out_state_chn register - * Represents the working status of the tx descriptor of channel n - */ -typedef union { - struct { - /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - uint32_t outlink_dscr_addr_chn:18; - /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t out_dscr_state_chn:2; - /** out_state_chn : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t out_state_chn:4; - /** out_reset_avail_chn : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t out_reset_avail_chn:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} dma2d_out_state_chn_reg_t; - -/** Type of out_eof_des_addr_chn register - * Represents the address associated with the outlink descriptor of channel n - */ -typedef union { - struct { - /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_chn:32; - }; - uint32_t val; -} dma2d_out_eof_des_addr_chn_reg_t; - -/** Type of out_dscr_chn register - * Represents the address associated with the outlink descriptor of channel n - */ -typedef union { - struct { - /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ - uint32_t outlink_dscr_chn:32; - }; - uint32_t val; -} dma2d_out_dscr_chn_reg_t; - -/** Type of out_dscr_bf0_chn register - * Represents the address associated with the outlink descriptor of channel n - */ -typedef union { - struct { - /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ - uint32_t outlink_dscr_bf0_chn:32; - }; - uint32_t val; -} dma2d_out_dscr_bf0_chn_reg_t; - -/** Type of out_dscr_bf1_chn register - * Represents the address associated with the outlink descriptor of channel n - */ -typedef union { - struct { - /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ - uint32_t outlink_dscr_bf1_chn:32; - }; - uint32_t val; -} dma2d_out_dscr_bf1_chn_reg_t; - -/** Type of out_ro_status_chn register - * Represents the status of the tx reorder module of channel n - */ -typedef union { - struct { - /** outfifo_ro_cnt_chn : RO; bitpos: [5:0]; default: 0; - * The register stores the byte number of the data in color convert Tx FIFO for - * channel 0. - */ - uint32_t outfifo_ro_cnt_chn:6; - /** out_ro_wr_state_chn : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ - uint32_t out_ro_wr_state_chn:2; - /** out_ro_rd_state_chn : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ - uint32_t out_ro_rd_state_chn:2; - /** out_pixel_byte_chn : RO; bitpos: [13:10]; default: 0; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ - uint32_t out_pixel_byte_chn:4; - /** out_burst_block_num_chn : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ - uint32_t out_burst_block_num_chn:4; - uint32_t reserved_18:14; - }; - uint32_t val; -} dma2d_out_ro_status_chn_reg_t; - -/** Type of infifo_status_chn register - * Represents the status of the rx fifo of channel n - */ -typedef union { - struct { - /** infifo_full_l2_chn : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ - uint32_t infifo_full_l2_chn:1; - /** infifo_empty_l2_chn : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ - uint32_t infifo_empty_l2_chn:1; - /** infifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ - uint32_t infifo_cnt_l2_chn:4; - uint32_t reserved_6:1; - /** in_remain_under_1b_chn : RO; bitpos: [7]; default: 0; - * reserved - */ - uint32_t in_remain_under_1b_chn:1; - /** in_remain_under_2b_chn : RO; bitpos: [8]; default: 0; - * reserved - */ - uint32_t in_remain_under_2b_chn:1; - /** in_remain_under_3b_chn : RO; bitpos: [9]; default: 0; - * reserved - */ - uint32_t in_remain_under_3b_chn:1; - /** in_remain_under_4b_chn : RO; bitpos: [10]; default: 0; - * reserved - */ - uint32_t in_remain_under_4b_chn:1; - /** in_remain_under_5b_chn : RO; bitpos: [11]; default: 0; - * reserved - */ - uint32_t in_remain_under_5b_chn:1; - /** in_remain_under_6b_chn : RO; bitpos: [12]; default: 0; - * reserved - */ - uint32_t in_remain_under_6b_chn:1; - /** in_remain_under_7b_chn : RO; bitpos: [13]; default: 0; - * reserved - */ - uint32_t in_remain_under_7b_chn:1; - /** in_remain_under_8b_chn : RO; bitpos: [14]; default: 0; - * reserved - */ - uint32_t in_remain_under_8b_chn:1; - /** infifo_full_l1_chn : RO; bitpos: [15]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ - uint32_t infifo_full_l1_chn:1; - /** infifo_empty_l1_chn : RO; bitpos: [16]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ - uint32_t infifo_empty_l1_chn:1; - /** infifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ - uint32_t infifo_cnt_l1_chn:5; - /** infifo_full_l3_chn : RO; bitpos: [22]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ - uint32_t infifo_full_l3_chn:1; - /** infifo_empty_l3_chn : RO; bitpos: [23]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ - uint32_t infifo_empty_l3_chn:1; - /** infifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ - uint32_t infifo_cnt_l3_chn:5; - uint32_t reserved_29:3; - }; - uint32_t val; -} dma2d_infifo_status_chn_reg_t; - -/** Type of in_state_chn register - * Represents the working status of the rx descriptor of channel n - */ -typedef union { - struct { - /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - uint32_t inlink_dscr_addr_chn:18; - /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t in_dscr_state_chn:2; - /** in_state_chn : RO; bitpos: [22:20]; default: 0; - * reserved - */ - uint32_t in_state_chn:3; - /** in_reset_avail_chn : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t in_reset_avail_chn:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} dma2d_in_state_chn_reg_t; - -/** Type of in_suc_eof_des_addr_chn register - * Represents the address associated with the inlink descriptor of channel n - */ -typedef union { - struct { - /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_chn:32; - }; - uint32_t val; -} dma2d_in_suc_eof_des_addr_chn_reg_t; - -/** Type of in_err_eof_des_addr_chn register - * Represents the address associated with the inlink descriptor of channel n - */ -typedef union { - struct { - /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ - uint32_t in_err_eof_des_addr_chn:32; - }; - uint32_t val; -} dma2d_in_err_eof_des_addr_chn_reg_t; - -/** Type of in_dscr_chn register - * Represents the address associated with the inlink descriptor of channel n - */ -typedef union { - struct { - /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ - uint32_t inlink_dscr_chn:32; - }; - uint32_t val; -} dma2d_in_dscr_chn_reg_t; - -/** Type of in_dscr_bf0_chn register - * Represents the address associated with the inlink descriptor of channel n - */ -typedef union { - struct { - /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ - uint32_t inlink_dscr_bf0_chn:32; - }; - uint32_t val; -} dma2d_in_dscr_bf0_chn_reg_t; - -/** Type of in_dscr_bf1_chn register - * Represents the address associated with the inlink descriptor of channel n - */ -typedef union { - struct { - /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ - uint32_t inlink_dscr_bf1_chn:32; - }; - uint32_t val; -} dma2d_in_dscr_bf1_chn_reg_t; - -/** Type of in_ro_status_chn register - * Represents the status of the rx reorder module of channel n - */ -typedef union { - struct { - /** infifo_ro_cnt_chn : RO; bitpos: [4:0]; default: 0; - * The register stores the byte number of the data in color convert Rx FIFO for - * channel 0. - */ - uint32_t infifo_ro_cnt_chn:5; - /** in_ro_wr_state_chn : RO; bitpos: [6:5]; default: 0; - * The register stores the state of read ram of reorder - */ - uint32_t in_ro_wr_state_chn:2; - /** in_ro_rd_state_chn : RO; bitpos: [8:7]; default: 0; - * The register stores the state of write ram of reorder - */ - uint32_t in_ro_rd_state_chn:2; - /** in_pixel_byte_chn : RO; bitpos: [12:9]; default: 0; - * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ - uint32_t in_pixel_byte_chn:4; - /** in_burst_block_num_chn : RO; bitpos: [16:13]; default: 0; - * the number of macro blocks contained in a burst of data at RX channel - */ - uint32_t in_burst_block_num_chn:4; - uint32_t reserved_17:15; - }; - uint32_t val; -} dma2d_in_ro_status_chn_reg_t; - -/** Type of axi_err register - * Represents the status of th axi bus - */ -typedef union { - struct { - /** rid_err_cnt : RO; bitpos: [3:0]; default: 0; - * AXI read id err cnt - */ - uint32_t rid_err_cnt:4; - /** rresp_err_cnt : RO; bitpos: [7:4]; default: 0; - * AXI read resp err cnt - */ - uint32_t rresp_err_cnt:4; - /** wresp_err_cnt : RO; bitpos: [11:8]; default: 0; - * AXI write resp err cnt - */ - uint32_t wresp_err_cnt:4; - /** rd_fifo_cnt : RO; bitpos: [14:12]; default: 0; - * AXI read cmd fifo remain cmd count - */ - uint32_t rd_fifo_cnt:3; - /** rd_bak_fifo_cnt : RO; bitpos: [18:15]; default: 0; - * AXI read backup cmd fifo remain cmd count - */ - uint32_t rd_bak_fifo_cnt:4; - /** wr_fifo_cnt : RO; bitpos: [21:19]; default: 0; - * AXI write cmd fifo remain cmd count - */ - uint32_t wr_fifo_cnt:3; - /** wr_bak_fifo_cnt : RO; bitpos: [25:22]; default: 0; - * AXI write backup cmd fifo remain cmd count - */ - uint32_t wr_bak_fifo_cnt:4; - uint32_t reserved_26:6; - }; - uint32_t val; -} dma2d_axi_err_reg_t; - -/** Type of date register - * register version. - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 37822864; - * register version. - */ - uint32_t date:32; - }; - uint32_t val; -} dma2d_date_reg_t; - - -/** Group: Peripheral Select Registers */ -/** Type of out_peri_sel_chn register - * Configures the tx peripheral of channel n - */ -typedef union { - struct { - /** out_peri_sel_chn : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Tx channel 0: jpeg 1: - * display-1 2: display-2 3: display-3 7: no choose - */ - uint32_t out_peri_sel_chn:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} dma2d_out_peri_sel_chn_reg_t; - -/** Type of in_peri_sel_chn register - * Configures the rx peripheral of channel n - */ -typedef union { - struct { - /** in_peri_sel_chn : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Rx channel 0: jpeg 1: - * display-1 2: display-2 7: no choose - */ - uint32_t in_peri_sel_chn:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} dma2d_in_peri_sel_chn_reg_t; - - -typedef struct { - volatile dma2d_out_conf0_chn_reg_t out_conf0_ch0; - volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch0; - volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch0; - volatile dma2d_out_int_st_chn_reg_t out_int_st_ch0; - volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch0; - volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch0; - volatile dma2d_out_push_chn_reg_t out_push_ch0; - volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch0; - volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch0; - volatile dma2d_out_state_chn_reg_t out_state_ch0; - volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0; - volatile dma2d_out_dscr_chn_reg_t out_dscr_ch0; - volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0; - volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0; - volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch0; - volatile dma2d_out_arb_chn_reg_t out_arb_ch0; - volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch0; - volatile dma2d_out_ro_pd_conf_chn_reg_t out_ro_pd_conf_ch0; - volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch0; - volatile dma2d_out_scramble_chn_reg_t out_scramble_ch0; - volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch0; - volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch0; - volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch0; - volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch0; - volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch0; - volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch0; - volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch0; - volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch0; - uint32_t reserved_070[36]; - volatile dma2d_out_conf0_chn_reg_t out_conf0_ch1; - volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch1; - volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch1; - volatile dma2d_out_int_st_chn_reg_t out_int_st_ch1; - volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch1; - volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch1; - volatile dma2d_out_push_chn_reg_t out_push_ch1; - volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch1; - volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch1; - volatile dma2d_out_state_chn_reg_t out_state_ch1; - volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1; - volatile dma2d_out_dscr_chn_reg_t out_dscr_ch1; - volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1; - volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1; - volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch1; - volatile dma2d_out_arb_chn_reg_t out_arb_ch1; - volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch1; - uint32_t reserved_144; - volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch1; - volatile dma2d_out_scramble_chn_reg_t out_scramble_ch1; - volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch1; - volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch1; - volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch1; - volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch1; - volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch1; - volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch1; - volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch1; - volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch1; - uint32_t reserved_170[36]; - volatile dma2d_out_conf0_chn_reg_t out_conf0_ch2; - volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch2; - volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch2; - volatile dma2d_out_int_st_chn_reg_t out_int_st_ch2; - volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch2; - volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch2; - volatile dma2d_out_push_chn_reg_t out_push_ch2; - volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch2; - volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch2; - volatile dma2d_out_state_chn_reg_t out_state_ch2; - volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2; - volatile dma2d_out_dscr_chn_reg_t out_dscr_ch2; - volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2; - volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2; - volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch2; - volatile dma2d_out_arb_chn_reg_t out_arb_ch2; - volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch2; - uint32_t reserved_244; - volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch2; - volatile dma2d_out_scramble_chn_reg_t out_scramble_ch2; - volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch2; - volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch2; - volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch2; - volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch2; - volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch2; - volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch2; - volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch2; - volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch2; - uint32_t reserved_270[36]; - volatile dma2d_out_conf0_chn_reg_t out_conf0_ch3; - volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch3; - volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch3; - volatile dma2d_out_int_st_chn_reg_t out_int_st_ch3; - volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch3; - volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch3; - volatile dma2d_out_push_chn_reg_t out_push_ch3; - volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch3; - volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch3; - volatile dma2d_out_state_chn_reg_t out_state_ch3; - volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch3; - volatile dma2d_out_dscr_chn_reg_t out_dscr_ch3; - volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch3; - volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch3; - volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch3; - volatile dma2d_out_arb_chn_reg_t out_arb_ch3; - volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch3; - uint32_t reserved_344; - volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch3; - volatile dma2d_out_scramble_chn_reg_t out_scramble_ch3; - volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch3; - volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch3; - volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch3; - volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch3; - volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch3; - volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch3; - volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch3; - volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch3; - uint32_t reserved_370[100]; - volatile dma2d_in_conf0_chn_reg_t in_conf0_ch0; - volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch0; - volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch0; - volatile dma2d_in_int_st_chn_reg_t in_int_st_ch0; - volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch0; - volatile dma2d_infifo_status_chn_reg_t infifo_status_ch0; - volatile dma2d_in_pop_chn_reg_t in_pop_ch0; - volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch0; - volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch0; - volatile dma2d_in_state_chn_reg_t in_state_ch0; - volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0; - volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0; - volatile dma2d_in_dscr_chn_reg_t in_dscr_ch0; - volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0; - volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0; - volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch0; - volatile dma2d_in_arb_chn_reg_t in_arb_ch0; - volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch0; - volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch0; - volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch0; - volatile dma2d_in_scramble_chn_reg_t in_scramble_ch0; - volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch0; - volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch0; - volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch0; - volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch0; - volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch0; - volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch0; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch0; - uint32_t reserved_570[36]; - volatile dma2d_in_conf0_chn_reg_t in_conf0_ch1; - volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch1; - volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch1; - volatile dma2d_in_int_st_chn_reg_t in_int_st_ch1; - volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch1; - volatile dma2d_infifo_status_chn_reg_t infifo_status_ch1; - volatile dma2d_in_pop_chn_reg_t in_pop_ch1; - volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch1; - volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch1; - volatile dma2d_in_state_chn_reg_t in_state_ch1; - volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1; - volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1; - volatile dma2d_in_dscr_chn_reg_t in_dscr_ch1; - volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1; - volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1; - volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch1; - volatile dma2d_in_arb_chn_reg_t in_arb_ch1; - volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch1; - volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch1; - volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch1; - volatile dma2d_in_scramble_chn_reg_t in_scramble_ch1; - volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch1; - volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch1; - volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch1; - volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch1; - volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch1; - volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch1; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch1; - uint32_t reserved_670[36]; - volatile dma2d_in_conf0_chn_reg_t in_conf0_ch2; - volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch2; - volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch2; - volatile dma2d_in_int_st_chn_reg_t in_int_st_ch2; - volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch2; - volatile dma2d_infifo_status_chn_reg_t infifo_status_ch2; - volatile dma2d_in_pop_chn_reg_t in_pop_ch2; - volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch2; - volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch2; - volatile dma2d_in_state_chn_reg_t in_state_ch2; - volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2; - volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2; - volatile dma2d_in_dscr_chn_reg_t in_dscr_ch2; - volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2; - volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2; - volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch2; - volatile dma2d_in_arb_chn_reg_t in_arb_ch2; - volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch2; - volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch2; - volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch2; - volatile dma2d_in_scramble_chn_reg_t in_scramble_ch2; - volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch2; - volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch2; - volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch2; - volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch2; - volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch2; - volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch2; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch2; - uint32_t reserved_770[164]; - volatile dma2d_axi_err_reg_t axi_err; - volatile dma2d_rst_conf_reg_t rst_conf; - volatile dma2d_intr_mem_start_addr_reg_t intr_mem_start_addr; - volatile dma2d_intr_mem_end_addr_reg_t intr_mem_end_addr; - volatile dma2d_extr_mem_start_addr_reg_t extr_mem_start_addr; - volatile dma2d_extr_mem_end_addr_reg_t extr_mem_end_addr; - volatile dma2d_out_arb_config_reg_t out_arb_config; - volatile dma2d_in_arb_config_reg_t in_arb_config; - volatile dma2d_rdn_result_reg_t rdn_result; - volatile dma2d_rdn_eco_high_reg_t rdn_eco_high; - volatile dma2d_rdn_eco_low_reg_t rdn_eco_low; - volatile dma2d_date_reg_t date; -} dma2d_dev_t; - -extern dma2d_dev_t DMA2D; - -#ifndef __cplusplus -_Static_assert(sizeof(dma2d_dev_t) == 0xa30, "Invalid size of dma2d_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h index b16c0654e9b3..861ee70e05ba 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h @@ -11,8 +11,6 @@ extern "C" { #endif -//TODO: IDF-13427 - /** DMA2D_OUT_CONF0_CH0_REG register * Configures the tx direction of channel 0 */ @@ -811,12 +809,12 @@ extern "C" { #define DMA2D_OUT_ARB_TOKEN_NUM_CH0_M (DMA2D_OUT_ARB_TOKEN_NUM_CH0_V << DMA2D_OUT_ARB_TOKEN_NUM_CH0_S) #define DMA2D_OUT_ARB_TOKEN_NUM_CH0_V 0x0000000FU #define DMA2D_OUT_ARB_TOKEN_NUM_CH0_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [5:4]; default: 1; +/** DMA2D_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ -#define DMA2D_OUT_ARB_PRIORITY_CH0 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH0 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH0_M (DMA2D_OUT_ARB_PRIORITY_CH0_V << DMA2D_OUT_ARB_PRIORITY_CH0_S) -#define DMA2D_OUT_ARB_PRIORITY_CH0_V 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH0_V 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH0_S 4 /** DMA2D_OUT_RO_STATUS_CH0_REG register @@ -1049,7 +1047,7 @@ extern "C" { #define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S 14 /** DMA2D_OUT_CONF0_CH1_REG register - * Configures the tx direction of channel 0 + * Configures the tx direction of channel 1 */ #define DMA2D_OUT_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x100) /** DMA2D_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [0]; default: 0; @@ -1162,7 +1160,7 @@ extern "C" { #define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S 26 /** DMA2D_OUT_INT_RAW_CH1_REG register - * Raw interrupt status of TX channel 0 + * Raw interrupt status of TX channel 1 */ #define DMA2D_OUT_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x104) /** DMA2D_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; @@ -1264,7 +1262,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S 12 /** DMA2D_OUT_INT_ENA_CH1_REG register - * Interrupt enable bits of TX channel 0 + * Interrupt enable bits of TX channel 1 */ #define DMA2D_OUT_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x108) /** DMA2D_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -1360,7 +1358,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S 12 /** DMA2D_OUT_INT_ST_CH1_REG register - * Masked interrupt status of TX channel 0 + * Masked interrupt status of TX channel 1 */ #define DMA2D_OUT_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x10c) /** DMA2D_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; @@ -1456,7 +1454,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S 12 /** DMA2D_OUT_INT_CLR_CH1_REG register - * Interrupt clear bits of TX channel 0 + * Interrupt clear bits of TX channel 1 */ #define DMA2D_OUT_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x110) /** DMA2D_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; @@ -1552,7 +1550,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S 12 /** DMA2D_OUTFIFO_STATUS_CH1_REG register - * Represents the status of the tx fifo of channel 0 + * Represents the status of the tx fifo of channel 1 */ #define DMA2D_OUTFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x114) /** DMA2D_OUTFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0; @@ -1676,7 +1674,7 @@ extern "C" { #define DMA2D_OUTFIFO_CNT_L3_CH1_S 24 /** DMA2D_OUT_PUSH_CH1_REG register - * Configures the tx fifo of channel 0 + * Configures the tx fifo of channel 1 */ #define DMA2D_OUT_PUSH_CH1_REG (DR_REG_DMA2D_BASE + 0x118) /** DMA2D_OUTFIFO_WDATA_CH1 : R/W; bitpos: [9:0]; default: 0; @@ -1695,7 +1693,7 @@ extern "C" { #define DMA2D_OUTFIFO_PUSH_CH1_S 10 /** DMA2D_OUT_LINK_CONF_CH1_REG register - * Configures the tx descriptor operations of channel 0 + * Configures the tx descriptor operations of channel 1 */ #define DMA2D_OUT_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x11c) /** DMA2D_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0; @@ -1729,7 +1727,7 @@ extern "C" { #define DMA2D_OUTLINK_PARK_CH1_S 23 /** DMA2D_OUT_LINK_ADDR_CH1_REG register - * Configures the tx descriptor address of channel 0 + * Configures the tx descriptor address of channel 1 */ #define DMA2D_OUT_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x120) /** DMA2D_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; @@ -1741,7 +1739,7 @@ extern "C" { #define DMA2D_OUTLINK_ADDR_CH1_S 0 /** DMA2D_OUT_STATE_CH1_REG register - * Represents the working status of the tx descriptor of channel 0 + * Represents the working status of the tx descriptor of channel 1 */ #define DMA2D_OUT_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x124) /** DMA2D_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; @@ -1774,7 +1772,7 @@ extern "C" { #define DMA2D_OUT_RESET_AVAIL_CH1_S 24 /** DMA2D_OUT_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 1 */ #define DMA2D_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x128) /** DMA2D_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -1787,7 +1785,7 @@ extern "C" { #define DMA2D_OUT_EOF_DES_ADDR_CH1_S 0 /** DMA2D_OUT_DSCR_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 1 */ #define DMA2D_OUT_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x12c) /** DMA2D_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -1799,7 +1797,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_CH1_S 0 /** DMA2D_OUT_DSCR_BF0_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 1 */ #define DMA2D_OUT_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x130) /** DMA2D_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; @@ -1811,7 +1809,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_BF0_CH1_S 0 /** DMA2D_OUT_DSCR_BF1_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 1 */ #define DMA2D_OUT_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x134) /** DMA2D_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; @@ -1823,7 +1821,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_BF1_CH1_S 0 /** DMA2D_OUT_PERI_SEL_CH1_REG register - * Configures the tx peripheral of channel 0 + * Configures the tx peripheral of channel 1 */ #define DMA2D_OUT_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x138) /** DMA2D_OUT_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7; @@ -1836,7 +1834,7 @@ extern "C" { #define DMA2D_OUT_PERI_SEL_CH1_S 0 /** DMA2D_OUT_ARB_CH1_REG register - * Configures the tx arbiter of channel 0 + * Configures the tx arbiter of channel 1 */ #define DMA2D_OUT_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x13c) /** DMA2D_OUT_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1; @@ -1846,16 +1844,16 @@ extern "C" { #define DMA2D_OUT_ARB_TOKEN_NUM_CH1_M (DMA2D_OUT_ARB_TOKEN_NUM_CH1_V << DMA2D_OUT_ARB_TOKEN_NUM_CH1_S) #define DMA2D_OUT_ARB_TOKEN_NUM_CH1_V 0x0000000FU #define DMA2D_OUT_ARB_TOKEN_NUM_CH1_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [5:4]; default: 1; +/** DMA2D_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ -#define DMA2D_OUT_ARB_PRIORITY_CH1 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH1 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH1_M (DMA2D_OUT_ARB_PRIORITY_CH1_V << DMA2D_OUT_ARB_PRIORITY_CH1_S) -#define DMA2D_OUT_ARB_PRIORITY_CH1_V 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH1_V 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH1_S 4 /** DMA2D_OUT_RO_STATUS_CH1_REG register - * Represents the status of the tx reorder module of channel 0 + * Represents the status of the tx reorder module of channel 1 */ #define DMA2D_OUT_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x140) /** DMA2D_OUTFIFO_RO_CNT_CH1 : RO; bitpos: [5:0]; default: 0; @@ -1897,7 +1895,7 @@ extern "C" { #define DMA2D_OUT_BURST_BLOCK_NUM_CH1_S 14 /** DMA2D_OUT_COLOR_CONVERT_CH1_REG register - * Configures the tx color convert of channel 0 + * Configures the tx color convert of channel 1 */ #define DMA2D_OUT_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x148) /** DMA2D_OUT_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; @@ -1927,7 +1925,7 @@ extern "C" { #define DMA2D_OUT_COLOR_INPUT_SEL_CH1_S 3 /** DMA2D_OUT_SCRAMBLE_CH1_REG register - * Configures the tx scramble of channel 0 + * Configures the tx scramble of channel 1 */ #define DMA2D_OUT_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x14c) /** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0; @@ -1940,7 +1938,7 @@ extern "C" { #define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM0_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x150) /** DMA2D_OUT_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298; @@ -1952,7 +1950,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_H0_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM1_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x154) /** DMA2D_OUT_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121; @@ -1964,7 +1962,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_H1_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM2_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x158) /** DMA2D_OUT_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050; @@ -1976,7 +1974,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_M0_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM3_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x15c) /** DMA2D_OUT_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784; @@ -1988,7 +1986,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_M1_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM4_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x160) /** DMA2D_OUT_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682; @@ -2000,7 +1998,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_L0_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM5_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x164) /** DMA2D_OUT_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392; @@ -2012,7 +2010,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_L1_CH1_S 0 /** DMA2D_OUT_ETM_CONF_CH1_REG register - * Configures the tx etm of channel 0 + * Configures the tx etm of channel 1 */ #define DMA2D_OUT_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x168) /** DMA2D_OUT_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0; @@ -2057,7 +2055,7 @@ extern "C" { #define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S 14 /** DMA2D_OUT_CONF0_CH2_REG register - * Configures the tx direction of channel 0 + * Configures the tx direction of channel 2 */ #define DMA2D_OUT_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x200) /** DMA2D_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [0]; default: 0; @@ -2170,7 +2168,7 @@ extern "C" { #define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S 26 /** DMA2D_OUT_INT_RAW_CH2_REG register - * Raw interrupt status of TX channel 0 + * Raw interrupt status of TX channel 2 */ #define DMA2D_OUT_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x204) /** DMA2D_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; @@ -2272,7 +2270,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S 12 /** DMA2D_OUT_INT_ENA_CH2_REG register - * Interrupt enable bits of TX channel 0 + * Interrupt enable bits of TX channel 2 */ #define DMA2D_OUT_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x208) /** DMA2D_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -2368,7 +2366,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S 12 /** DMA2D_OUT_INT_ST_CH2_REG register - * Masked interrupt status of TX channel 0 + * Masked interrupt status of TX channel 2 */ #define DMA2D_OUT_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x20c) /** DMA2D_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; @@ -2464,7 +2462,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S 12 /** DMA2D_OUT_INT_CLR_CH2_REG register - * Interrupt clear bits of TX channel 0 + * Interrupt clear bits of TX channel 2 */ #define DMA2D_OUT_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x210) /** DMA2D_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; @@ -2560,7 +2558,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S 12 /** DMA2D_OUTFIFO_STATUS_CH2_REG register - * Represents the status of the tx fifo of channel 0 + * Represents the status of the tx fifo of channel 2 */ #define DMA2D_OUTFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x214) /** DMA2D_OUTFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0; @@ -2684,7 +2682,7 @@ extern "C" { #define DMA2D_OUTFIFO_CNT_L3_CH2_S 24 /** DMA2D_OUT_PUSH_CH2_REG register - * Configures the tx fifo of channel 0 + * Configures the tx fifo of channel 2 */ #define DMA2D_OUT_PUSH_CH2_REG (DR_REG_DMA2D_BASE + 0x218) /** DMA2D_OUTFIFO_WDATA_CH2 : R/W; bitpos: [9:0]; default: 0; @@ -2703,7 +2701,7 @@ extern "C" { #define DMA2D_OUTFIFO_PUSH_CH2_S 10 /** DMA2D_OUT_LINK_CONF_CH2_REG register - * Configures the tx descriptor operations of channel 0 + * Configures the tx descriptor operations of channel 2 */ #define DMA2D_OUT_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x21c) /** DMA2D_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0; @@ -2737,7 +2735,7 @@ extern "C" { #define DMA2D_OUTLINK_PARK_CH2_S 23 /** DMA2D_OUT_LINK_ADDR_CH2_REG register - * Configures the tx descriptor address of channel 0 + * Configures the tx descriptor address of channel 2 */ #define DMA2D_OUT_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x220) /** DMA2D_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; @@ -2749,7 +2747,7 @@ extern "C" { #define DMA2D_OUTLINK_ADDR_CH2_S 0 /** DMA2D_OUT_STATE_CH2_REG register - * Represents the working status of the tx descriptor of channel 0 + * Represents the working status of the tx descriptor of channel 2 */ #define DMA2D_OUT_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x224) /** DMA2D_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; @@ -2782,7 +2780,7 @@ extern "C" { #define DMA2D_OUT_RESET_AVAIL_CH2_S 24 /** DMA2D_OUT_EOF_DES_ADDR_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 2 */ #define DMA2D_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x228) /** DMA2D_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2795,7 +2793,7 @@ extern "C" { #define DMA2D_OUT_EOF_DES_ADDR_CH2_S 0 /** DMA2D_OUT_DSCR_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 2 */ #define DMA2D_OUT_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x22c) /** DMA2D_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2807,7 +2805,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_CH2_S 0 /** DMA2D_OUT_DSCR_BF0_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 2 */ #define DMA2D_OUT_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x230) /** DMA2D_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2819,7 +2817,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_BF0_CH2_S 0 /** DMA2D_OUT_DSCR_BF1_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 2 */ #define DMA2D_OUT_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x234) /** DMA2D_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2831,7 +2829,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_BF1_CH2_S 0 /** DMA2D_OUT_PERI_SEL_CH2_REG register - * Configures the tx peripheral of channel 0 + * Configures the tx peripheral of channel 2 */ #define DMA2D_OUT_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x238) /** DMA2D_OUT_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7; @@ -2844,7 +2842,7 @@ extern "C" { #define DMA2D_OUT_PERI_SEL_CH2_S 0 /** DMA2D_OUT_ARB_CH2_REG register - * Configures the tx arbiter of channel 0 + * Configures the tx arbiter of channel 2 */ #define DMA2D_OUT_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x23c) /** DMA2D_OUT_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1; @@ -2854,16 +2852,16 @@ extern "C" { #define DMA2D_OUT_ARB_TOKEN_NUM_CH2_M (DMA2D_OUT_ARB_TOKEN_NUM_CH2_V << DMA2D_OUT_ARB_TOKEN_NUM_CH2_S) #define DMA2D_OUT_ARB_TOKEN_NUM_CH2_V 0x0000000FU #define DMA2D_OUT_ARB_TOKEN_NUM_CH2_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [5:4]; default: 1; +/** DMA2D_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ -#define DMA2D_OUT_ARB_PRIORITY_CH2 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH2 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH2_M (DMA2D_OUT_ARB_PRIORITY_CH2_V << DMA2D_OUT_ARB_PRIORITY_CH2_S) -#define DMA2D_OUT_ARB_PRIORITY_CH2_V 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH2_V 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH2_S 4 /** DMA2D_OUT_RO_STATUS_CH2_REG register - * Represents the status of the tx reorder module of channel 0 + * Represents the status of the tx reorder module of channel 2 */ #define DMA2D_OUT_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x240) /** DMA2D_OUTFIFO_RO_CNT_CH2 : RO; bitpos: [5:0]; default: 0; @@ -2905,7 +2903,7 @@ extern "C" { #define DMA2D_OUT_BURST_BLOCK_NUM_CH2_S 14 /** DMA2D_OUT_COLOR_CONVERT_CH2_REG register - * Configures the tx color convert of channel 0 + * Configures the tx color convert of channel 2 */ #define DMA2D_OUT_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x248) /** DMA2D_OUT_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; @@ -2935,7 +2933,7 @@ extern "C" { #define DMA2D_OUT_COLOR_INPUT_SEL_CH2_S 3 /** DMA2D_OUT_SCRAMBLE_CH2_REG register - * Configures the tx scramble of channel 0 + * Configures the tx scramble of channel 2 */ #define DMA2D_OUT_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x24c) /** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0; @@ -2948,7 +2946,7 @@ extern "C" { #define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM0_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x250) /** DMA2D_OUT_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298; @@ -2960,7 +2958,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_H0_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM1_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x254) /** DMA2D_OUT_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121; @@ -2972,7 +2970,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_H1_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM2_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x258) /** DMA2D_OUT_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050; @@ -2984,7 +2982,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_M0_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM3_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x25c) /** DMA2D_OUT_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784; @@ -2996,7 +2994,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_M1_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM4_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x260) /** DMA2D_OUT_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682; @@ -3008,7 +3006,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_L0_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM5_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x264) /** DMA2D_OUT_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392; @@ -3020,7 +3018,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_L1_CH2_S 0 /** DMA2D_OUT_ETM_CONF_CH2_REG register - * Configures the tx etm of channel 0 + * Configures the tx etm of channel 2 */ #define DMA2D_OUT_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x268) /** DMA2D_OUT_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0; @@ -3064,1982 +3062,3904 @@ extern "C" { #define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V 0x00003FFFU #define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S 14 -/** DMA2D_IN_CONF0_CH0_REG register - * Configures the rx direction of channel 0 +/** DMA2D_OUT_CONF0_CH3_REG register + * Configures the tx direction of channel 3 */ -#define DMA2D_IN_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x500) -/** DMA2D_IN_MEM_TRANS_EN_CH0 : R/W; bitpos: [0]; default: 0; - * enable memory trans of the same channel +#define DMA2D_OUT_CONF0_CH3_REG (DR_REG_DMA2D_BASE + 0x300) +/** DMA2D_OUT_AUTO_WRBACK_CH3 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data pointed by + * outlink descriptor has been received. */ -#define DMA2D_IN_MEM_TRANS_EN_CH0 (BIT(0)) -#define DMA2D_IN_MEM_TRANS_EN_CH0_M (DMA2D_IN_MEM_TRANS_EN_CH0_V << DMA2D_IN_MEM_TRANS_EN_CH0_S) -#define DMA2D_IN_MEM_TRANS_EN_CH0_V 0x00000001U -#define DMA2D_IN_MEM_TRANS_EN_CH0_S 0 -/** DMA2D_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. +#define DMA2D_OUT_AUTO_WRBACK_CH3 (BIT(0)) +#define DMA2D_OUT_AUTO_WRBACK_CH3_M (DMA2D_OUT_AUTO_WRBACK_CH3_V << DMA2D_OUT_AUTO_WRBACK_CH3_S) +#define DMA2D_OUT_AUTO_WRBACK_CH3_V 0x00000001U +#define DMA2D_OUT_AUTO_WRBACK_CH3_S 0 +/** DMA2D_OUT_EOF_MODE_CH3 : R/W; bitpos: [1]; default: 1; + * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is + * generated when data need to read has been popped from FIFO in DMA */ -#define DMA2D_INDSCR_BURST_EN_CH0 (BIT(2)) -#define DMA2D_INDSCR_BURST_EN_CH0_M (DMA2D_INDSCR_BURST_EN_CH0_V << DMA2D_INDSCR_BURST_EN_CH0_S) -#define DMA2D_INDSCR_BURST_EN_CH0_V 0x00000001U -#define DMA2D_INDSCR_BURST_EN_CH0_S 2 -/** DMA2D_IN_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0; +#define DMA2D_OUT_EOF_MODE_CH3 (BIT(1)) +#define DMA2D_OUT_EOF_MODE_CH3_M (DMA2D_OUT_EOF_MODE_CH3_V << DMA2D_OUT_EOF_MODE_CH3_S) +#define DMA2D_OUT_EOF_MODE_CH3_V 0x00000001U +#define DMA2D_OUT_EOF_MODE_CH3_S 1 +/** DMA2D_OUTDSCR_BURST_EN_CH3 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define DMA2D_OUTDSCR_BURST_EN_CH3 (BIT(2)) +#define DMA2D_OUTDSCR_BURST_EN_CH3_M (DMA2D_OUTDSCR_BURST_EN_CH3_V << DMA2D_OUTDSCR_BURST_EN_CH3_S) +#define DMA2D_OUTDSCR_BURST_EN_CH3_V 0x00000001U +#define DMA2D_OUTDSCR_BURST_EN_CH3_S 2 +/** DMA2D_OUT_ECC_AES_EN_CH3 : R/W; bitpos: [3]; default: 0; * When access address space is ecc/aes area, this bit should be set to 1. In this * case, the start address of square should be 16-bit aligned. The width of square * multiply byte number of one pixel should be 16-bit aligned. */ -#define DMA2D_IN_ECC_AES_EN_CH0 (BIT(3)) -#define DMA2D_IN_ECC_AES_EN_CH0_M (DMA2D_IN_ECC_AES_EN_CH0_V << DMA2D_IN_ECC_AES_EN_CH0_S) -#define DMA2D_IN_ECC_AES_EN_CH0_V 0x00000001U -#define DMA2D_IN_ECC_AES_EN_CH0_S 3 -/** DMA2D_IN_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0; +#define DMA2D_OUT_ECC_AES_EN_CH3 (BIT(3)) +#define DMA2D_OUT_ECC_AES_EN_CH3_M (DMA2D_OUT_ECC_AES_EN_CH3_V << DMA2D_OUT_ECC_AES_EN_CH3_S) +#define DMA2D_OUT_ECC_AES_EN_CH3_V 0x00000001U +#define DMA2D_OUT_ECC_AES_EN_CH3_S 3 +/** DMA2D_OUT_CHECK_OWNER_CH3 : R/W; bitpos: [4]; default: 0; * Set this bit to enable checking the owner attribute of the link descriptor. */ -#define DMA2D_IN_CHECK_OWNER_CH0 (BIT(4)) -#define DMA2D_IN_CHECK_OWNER_CH0_M (DMA2D_IN_CHECK_OWNER_CH0_V << DMA2D_IN_CHECK_OWNER_CH0_S) -#define DMA2D_IN_CHECK_OWNER_CH0_V 0x00000001U -#define DMA2D_IN_CHECK_OWNER_CH0_S 4 -/** DMA2D_IN_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0; +#define DMA2D_OUT_CHECK_OWNER_CH3 (BIT(4)) +#define DMA2D_OUT_CHECK_OWNER_CH3_M (DMA2D_OUT_CHECK_OWNER_CH3_V << DMA2D_OUT_CHECK_OWNER_CH3_S) +#define DMA2D_OUT_CHECK_OWNER_CH3_V 0x00000001U +#define DMA2D_OUT_CHECK_OWNER_CH3_S 4 +/** DMA2D_OUT_LOOP_TEST_CH3 : R/W; bitpos: [5]; default: 0; * reserved */ -#define DMA2D_IN_LOOP_TEST_CH0 (BIT(5)) -#define DMA2D_IN_LOOP_TEST_CH0_M (DMA2D_IN_LOOP_TEST_CH0_V << DMA2D_IN_LOOP_TEST_CH0_S) -#define DMA2D_IN_LOOP_TEST_CH0_V 0x00000001U -#define DMA2D_IN_LOOP_TEST_CH0_S 5 -/** DMA2D_IN_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 +#define DMA2D_OUT_LOOP_TEST_CH3 (BIT(5)) +#define DMA2D_OUT_LOOP_TEST_CH3_M (DMA2D_OUT_LOOP_TEST_CH3_V << DMA2D_OUT_LOOP_TEST_CH3_S) +#define DMA2D_OUT_LOOP_TEST_CH3_V 0x00000001U +#define DMA2D_OUT_LOOP_TEST_CH3_S 5 +/** DMA2D_OUT_MEM_BURST_LENGTH_CH3 : R/W; bitpos: [8:6]; default: 0; + * Block size of Tx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 * bytes 4: 128 bytes */ -#define DMA2D_IN_MEM_BURST_LENGTH_CH0 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH0_M (DMA2D_IN_MEM_BURST_LENGTH_CH0_V << DMA2D_IN_MEM_BURST_LENGTH_CH0_S) -#define DMA2D_IN_MEM_BURST_LENGTH_CH0_V 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH0_S 6 -/** DMA2D_IN_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0; - * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: +#define DMA2D_OUT_MEM_BURST_LENGTH_CH3 0x00000007U +#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_M (DMA2D_OUT_MEM_BURST_LENGTH_CH3_V << DMA2D_OUT_MEM_BURST_LENGTH_CH3_S) +#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_V 0x00000007U +#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_S 6 +/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH3 : R/W; bitpos: [10:9]; default: 0; + * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link * descriptor */ -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S) -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S 9 -/** DMA2D_IN_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0; +#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3 0x00000003U +#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_M (DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S) +#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V 0x00000003U +#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S 9 +/** DMA2D_OUT_DSCR_PORT_EN_CH3 : R/W; bitpos: [11]; default: 0; * Set this bit to 1 to obtain descriptor from IP port */ -#define DMA2D_IN_DSCR_PORT_EN_CH0 (BIT(11)) -#define DMA2D_IN_DSCR_PORT_EN_CH0_M (DMA2D_IN_DSCR_PORT_EN_CH0_V << DMA2D_IN_DSCR_PORT_EN_CH0_S) -#define DMA2D_IN_DSCR_PORT_EN_CH0_V 0x00000001U -#define DMA2D_IN_DSCR_PORT_EN_CH0_S 11 -/** DMA2D_IN_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length +#define DMA2D_OUT_DSCR_PORT_EN_CH3 (BIT(11)) +#define DMA2D_OUT_DSCR_PORT_EN_CH3_M (DMA2D_OUT_DSCR_PORT_EN_CH3_V << DMA2D_OUT_DSCR_PORT_EN_CH3_S) +#define DMA2D_OUT_DSCR_PORT_EN_CH3_V 0x00000001U +#define DMA2D_OUT_DSCR_PORT_EN_CH3_S 11 +/** DMA2D_OUT_PAGE_BOUND_EN_CH3 : R/W; bitpos: [12]; default: 0; + * Set this bit to 1 to make sure AXI read data don't cross the address boundary which + * define by mem_burst_length */ -#define DMA2D_IN_PAGE_BOUND_EN_CH0 (BIT(12)) -#define DMA2D_IN_PAGE_BOUND_EN_CH0_M (DMA2D_IN_PAGE_BOUND_EN_CH0_V << DMA2D_IN_PAGE_BOUND_EN_CH0_S) -#define DMA2D_IN_PAGE_BOUND_EN_CH0_V 0x00000001U -#define DMA2D_IN_PAGE_BOUND_EN_CH0_S 12 -/** DMA2D_IN_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0; - * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this +#define DMA2D_OUT_PAGE_BOUND_EN_CH3 (BIT(12)) +#define DMA2D_OUT_PAGE_BOUND_EN_CH3_M (DMA2D_OUT_PAGE_BOUND_EN_CH3_V << DMA2D_OUT_PAGE_BOUND_EN_CH3_S) +#define DMA2D_OUT_PAGE_BOUND_EN_CH3_V 0x00000001U +#define DMA2D_OUT_PAGE_BOUND_EN_CH3_S 12 +/** DMA2D_OUT_REORDER_EN_CH3 : R/W; bitpos: [16]; default: 0; + * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this * selection */ -#define DMA2D_IN_REORDER_EN_CH0 (BIT(16)) -#define DMA2D_IN_REORDER_EN_CH0_M (DMA2D_IN_REORDER_EN_CH0_V << DMA2D_IN_REORDER_EN_CH0_S) -#define DMA2D_IN_REORDER_EN_CH0_V 0x00000001U -#define DMA2D_IN_REORDER_EN_CH0_S 16 -/** DMA2D_IN_RST_CH0 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel +#define DMA2D_OUT_REORDER_EN_CH3 (BIT(16)) +#define DMA2D_OUT_REORDER_EN_CH3_M (DMA2D_OUT_REORDER_EN_CH3_V << DMA2D_OUT_REORDER_EN_CH3_S) +#define DMA2D_OUT_REORDER_EN_CH3_V 0x00000001U +#define DMA2D_OUT_REORDER_EN_CH3_S 16 +/** DMA2D_OUT_RST_CH3 : R/W; bitpos: [24]; default: 0; + * Write 1 then write 0 to this bit to reset TX channel */ -#define DMA2D_IN_RST_CH0 (BIT(24)) -#define DMA2D_IN_RST_CH0_M (DMA2D_IN_RST_CH0_V << DMA2D_IN_RST_CH0_S) -#define DMA2D_IN_RST_CH0_V 0x00000001U -#define DMA2D_IN_RST_CH0_S 24 -/** DMA2D_IN_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0; +#define DMA2D_OUT_RST_CH3 (BIT(24)) +#define DMA2D_OUT_RST_CH3_M (DMA2D_OUT_RST_CH3_V << DMA2D_OUT_RST_CH3_S) +#define DMA2D_OUT_RST_CH3_V 0x00000001U +#define DMA2D_OUT_RST_CH3_S 24 +/** DMA2D_OUT_CMD_DISABLE_CH3 : R/W; bitpos: [25]; default: 0; * Write 1 before reset and write 0 after reset */ -#define DMA2D_IN_CMD_DISABLE_CH0 (BIT(25)) -#define DMA2D_IN_CMD_DISABLE_CH0_M (DMA2D_IN_CMD_DISABLE_CH0_V << DMA2D_IN_CMD_DISABLE_CH0_S) -#define DMA2D_IN_CMD_DISABLE_CH0_V 0x00000001U -#define DMA2D_IN_CMD_DISABLE_CH0_S 25 -/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0; +#define DMA2D_OUT_CMD_DISABLE_CH3 (BIT(25)) +#define DMA2D_OUT_CMD_DISABLE_CH3_M (DMA2D_OUT_CMD_DISABLE_CH3_V << DMA2D_OUT_CMD_DISABLE_CH3_S) +#define DMA2D_OUT_CMD_DISABLE_CH3_V 0x00000001U +#define DMA2D_OUT_CMD_DISABLE_CH3_S 25 +/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3 : R/W; bitpos: [26]; default: 0; * Set this bit to 1 to disable arbiter optimum weight function. */ -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0 (BIT(26)) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S 26 +#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3 (BIT(26)) +#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_M (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S) +#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V 0x00000001U +#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S 26 -/** DMA2D_IN_INT_RAW_CH0_REG register - * Raw interrupt status of RX channel 0 - */ -#define DMA2D_IN_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x504) -/** DMA2D_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 0. +/** DMA2D_OUT_INT_RAW_CH3_REG register + * Raw interrupt status of TX channel 3 */ -#define DMA2D_IN_DONE_CH0_INT_RAW (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_RAW_M (DMA2D_IN_DONE_CH0_INT_RAW_V << DMA2D_IN_DONE_CH0_INT_RAW_S) -#define DMA2D_IN_DONE_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_RAW_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 0. +#define DMA2D_OUT_INT_RAW_CH3_REG (DR_REG_DMA2D_BASE + 0x304) +/** DMA2D_OUT_DONE_CH3_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. */ -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_M (DMA2D_IN_SUC_EOF_CH0_INT_RAW_V << DMA2D_IN_SUC_EOF_CH0_INT_RAW_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected +#define DMA2D_OUT_DONE_CH3_INT_RAW (BIT(0)) +#define DMA2D_OUT_DONE_CH3_INT_RAW_M (DMA2D_OUT_DONE_CH3_INT_RAW_V << DMA2D_OUT_DONE_CH3_INT_RAW_S) +#define DMA2D_OUT_DONE_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUT_DONE_CH3_INT_RAW_S 0 +/** DMA2D_OUT_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. */ -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_M (DMA2D_IN_ERR_EOF_CH0_INT_RAW_V << DMA2D_IN_ERR_EOF_CH0_INT_RAW_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx +#define DMA2D_OUT_EOF_CH3_INT_RAW (BIT(1)) +#define DMA2D_OUT_EOF_CH3_INT_RAW_M (DMA2D_OUT_EOF_CH3_INT_RAW_V << DMA2D_OUT_EOF_CH3_INT_RAW_S) +#define DMA2D_OUT_EOF_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUT_EOF_CH3_INT_RAW_S 1 +/** DMA2D_OUT_DSCR_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error, + * including owner error, the second and third word error of outlink descriptor for Tx * channel 0. */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. +#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW (BIT(2)) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_M (DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S 2 +/** DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW (BIT(3)) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S 3 +/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when fifo is overflow. */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW (BIT(4)) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S 4 +/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when fifo is underflow. */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW (BIT(5)) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S 5 +/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when fifo is overflow. */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW (BIT(6)) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S 6 +/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when fifo is underflow. */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW (BIT(7)) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S 7 +/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when fifo is overflow. */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW (BIT(8)) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S 8 +/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when fifo is underflow. */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW (BIT(9)) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S 9 +/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; * The raw interrupt bit turns to high level when reorder fifo is overflow. */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW (BIT(10)) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S 10 +/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; * The raw interrupt bit turns to high level when reorder fifo is underflow. */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW (BIT(11)) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S 11 +/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S 13 +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW (BIT(12)) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S 12 -/** DMA2D_IN_INT_ENA_CH0_REG register - * Interrupt enable bits of RX channel 0 +/** DMA2D_OUT_INT_ENA_CH3_REG register + * Interrupt enable bits of TX channel 3 */ -#define DMA2D_IN_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x508) -/** DMA2D_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. +#define DMA2D_OUT_INT_ENA_CH3_REG (DR_REG_DMA2D_BASE + 0x308) +/** DMA2D_OUT_DONE_CH3_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ -#define DMA2D_IN_DONE_CH0_INT_ENA (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_ENA_M (DMA2D_IN_DONE_CH0_INT_ENA_V << DMA2D_IN_DONE_CH0_INT_ENA_S) -#define DMA2D_IN_DONE_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_ENA_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_M (DMA2D_IN_SUC_EOF_CH0_INT_ENA_V << DMA2D_IN_SUC_EOF_CH0_INT_ENA_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. +#define DMA2D_OUT_DONE_CH3_INT_ENA (BIT(0)) +#define DMA2D_OUT_DONE_CH3_INT_ENA_M (DMA2D_OUT_DONE_CH3_INT_ENA_V << DMA2D_OUT_DONE_CH3_INT_ENA_S) +#define DMA2D_OUT_DONE_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUT_DONE_CH3_INT_ENA_S 0 +/** DMA2D_OUT_EOF_CH3_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_M (DMA2D_IN_ERR_EOF_CH0_INT_ENA_V << DMA2D_IN_ERR_EOF_CH0_INT_ENA_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. +#define DMA2D_OUT_EOF_CH3_INT_ENA (BIT(1)) +#define DMA2D_OUT_EOF_CH3_INT_ENA_M (DMA2D_OUT_EOF_CH3_INT_ENA_V << DMA2D_OUT_EOF_CH3_INT_ENA_S) +#define DMA2D_OUT_EOF_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUT_EOF_CH3_INT_ENA_S 1 +/** DMA2D_OUT_DSCR_ERR_CH3_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA (BIT(2)) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_M (DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S 2 +/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA (BIT(3)) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S 3 +/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA (BIT(4)) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S 4 +/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA (BIT(5)) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S 5 +/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA (BIT(6)) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S 6 +/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA (BIT(7)) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S 7 +/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA (BIT(8)) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S 8 +/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA (BIT(9)) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S 9 +/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA (BIT(10)) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S 10 +/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA (BIT(11)) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S 11 +/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S 13 +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA (BIT(12)) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S 12 -/** DMA2D_IN_INT_ST_CH0_REG register - * Masked interrupt status of RX channel 0 - */ -#define DMA2D_IN_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0x50c) -/** DMA2D_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. +/** DMA2D_OUT_INT_ST_CH3_REG register + * Masked interrupt status of TX channel 3 */ -#define DMA2D_IN_DONE_CH0_INT_ST (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_ST_M (DMA2D_IN_DONE_CH0_INT_ST_V << DMA2D_IN_DONE_CH0_INT_ST_S) -#define DMA2D_IN_DONE_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_ST_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. +#define DMA2D_OUT_INT_ST_CH3_REG (DR_REG_DMA2D_BASE + 0x30c) +/** DMA2D_OUT_DONE_CH3_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ -#define DMA2D_IN_SUC_EOF_CH0_INT_ST (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_ST_M (DMA2D_IN_SUC_EOF_CH0_INT_ST_V << DMA2D_IN_SUC_EOF_CH0_INT_ST_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_ST_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. +#define DMA2D_OUT_DONE_CH3_INT_ST (BIT(0)) +#define DMA2D_OUT_DONE_CH3_INT_ST_M (DMA2D_OUT_DONE_CH3_INT_ST_V << DMA2D_OUT_DONE_CH3_INT_ST_S) +#define DMA2D_OUT_DONE_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUT_DONE_CH3_INT_ST_S 0 +/** DMA2D_OUT_EOF_CH3_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ -#define DMA2D_IN_ERR_EOF_CH0_INT_ST (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_ST_M (DMA2D_IN_ERR_EOF_CH0_INT_ST_V << DMA2D_IN_ERR_EOF_CH0_INT_ST_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_ST_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. +#define DMA2D_OUT_EOF_CH3_INT_ST (BIT(1)) +#define DMA2D_OUT_EOF_CH3_INT_ST_M (DMA2D_OUT_EOF_CH3_INT_ST_V << DMA2D_OUT_EOF_CH3_INT_ST_S) +#define DMA2D_OUT_EOF_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUT_EOF_CH3_INT_ST_S 1 +/** DMA2D_OUT_DSCR_ERR_CH3_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_M (DMA2D_IN_DSCR_ERR_CH0_INT_ST_V << DMA2D_IN_DSCR_ERR_CH0_INT_ST_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST (BIT(2)) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_M (DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S 2 +/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST (BIT(3)) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S 3 +/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST (BIT(4)) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S 4 +/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST (BIT(5)) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S 5 +/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST (BIT(6)) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S 6 +/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST (BIT(7)) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S 7 +/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST (BIT(8)) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S 8 +/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST (BIT(9)) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S 9 +/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST (BIT(10)) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S 10 +/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST (BIT(11)) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S 11 +/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S 13 +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST (BIT(12)) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S 12 -/** DMA2D_IN_INT_CLR_CH0_REG register - * Interrupt clear bits of RX channel 0 +/** DMA2D_OUT_INT_CLR_CH3_REG register + * Interrupt clear bits of TX channel 3 */ -#define DMA2D_IN_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x510) -/** DMA2D_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. +#define DMA2D_OUT_INT_CLR_CH3_REG (DR_REG_DMA2D_BASE + 0x310) +/** DMA2D_OUT_DONE_CH3_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. */ -#define DMA2D_IN_DONE_CH0_INT_CLR (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_CLR_M (DMA2D_IN_DONE_CH0_INT_CLR_V << DMA2D_IN_DONE_CH0_INT_CLR_S) -#define DMA2D_IN_DONE_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_CLR_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. +#define DMA2D_OUT_DONE_CH3_INT_CLR (BIT(0)) +#define DMA2D_OUT_DONE_CH3_INT_CLR_M (DMA2D_OUT_DONE_CH3_INT_CLR_V << DMA2D_OUT_DONE_CH3_INT_CLR_S) +#define DMA2D_OUT_DONE_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUT_DONE_CH3_INT_CLR_S 0 +/** DMA2D_OUT_EOF_CH3_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. */ -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_M (DMA2D_IN_SUC_EOF_CH0_INT_CLR_V << DMA2D_IN_SUC_EOF_CH0_INT_CLR_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. +#define DMA2D_OUT_EOF_CH3_INT_CLR (BIT(1)) +#define DMA2D_OUT_EOF_CH3_INT_CLR_M (DMA2D_OUT_EOF_CH3_INT_CLR_V << DMA2D_OUT_EOF_CH3_INT_CLR_S) +#define DMA2D_OUT_EOF_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUT_EOF_CH3_INT_CLR_S 1 +/** DMA2D_OUT_DSCR_ERR_CH3_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_M (DMA2D_IN_ERR_EOF_CH0_INT_CLR_V << DMA2D_IN_ERR_EOF_CH0_INT_CLR_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. +#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR (BIT(2)) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_M (DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S 2 +/** DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR (BIT(3)) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S 3 +/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR (BIT(4)) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S 4 +/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR (BIT(5)) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S 5 +/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR (BIT(6)) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S 6 +/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR (BIT(7)) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S 7 +/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR (BIT(8)) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S 8 +/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR (BIT(9)) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S 9 +/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR (BIT(10)) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S 10 +/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR (BIT(11)) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S 11 +/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S 13 +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR (BIT(12)) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S 12 -/** DMA2D_INFIFO_STATUS_CH0_REG register - * Represents the status of the rx fifo of channel 0 +/** DMA2D_OUTFIFO_STATUS_CH3_REG register + * Represents the status of the tx fifo of channel 3 */ -#define DMA2D_INFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x514) -/** DMA2D_INFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. +#define DMA2D_OUTFIFO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x314) +/** DMA2D_OUTFIFO_FULL_L2_CH3 : RO; bitpos: [0]; default: 0; + * Tx FIFO full signal for Tx channel 0. */ -#define DMA2D_INFIFO_FULL_L2_CH0 (BIT(0)) -#define DMA2D_INFIFO_FULL_L2_CH0_M (DMA2D_INFIFO_FULL_L2_CH0_V << DMA2D_INFIFO_FULL_L2_CH0_S) -#define DMA2D_INFIFO_FULL_L2_CH0_V 0x00000001U -#define DMA2D_INFIFO_FULL_L2_CH0_S 0 -/** DMA2D_INFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. +#define DMA2D_OUTFIFO_FULL_L2_CH3 (BIT(0)) +#define DMA2D_OUTFIFO_FULL_L2_CH3_M (DMA2D_OUTFIFO_FULL_L2_CH3_V << DMA2D_OUTFIFO_FULL_L2_CH3_S) +#define DMA2D_OUTFIFO_FULL_L2_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_FULL_L2_CH3_S 0 +/** DMA2D_OUTFIFO_EMPTY_L2_CH3 : RO; bitpos: [1]; default: 1; + * Tx FIFO empty signal for Tx channel 0. */ -#define DMA2D_INFIFO_EMPTY_L2_CH0 (BIT(1)) -#define DMA2D_INFIFO_EMPTY_L2_CH0_M (DMA2D_INFIFO_EMPTY_L2_CH0_V << DMA2D_INFIFO_EMPTY_L2_CH0_S) -#define DMA2D_INFIFO_EMPTY_L2_CH0_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L2_CH0_S 1 -/** DMA2D_INFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. +#define DMA2D_OUTFIFO_EMPTY_L2_CH3 (BIT(1)) +#define DMA2D_OUTFIFO_EMPTY_L2_CH3_M (DMA2D_OUTFIFO_EMPTY_L2_CH3_V << DMA2D_OUTFIFO_EMPTY_L2_CH3_S) +#define DMA2D_OUTFIFO_EMPTY_L2_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_EMPTY_L2_CH3_S 1 +/** DMA2D_OUTFIFO_CNT_L2_CH3 : RO; bitpos: [5:2]; default: 0; + * The register stores the byte number of the data in Tx FIFO for Tx channel 0. */ -#define DMA2D_INFIFO_CNT_L2_CH0 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH0_M (DMA2D_INFIFO_CNT_L2_CH0_V << DMA2D_INFIFO_CNT_L2_CH0_S) -#define DMA2D_INFIFO_CNT_L2_CH0_V 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH0_S 2 -/** DMA2D_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 0; +#define DMA2D_OUTFIFO_CNT_L2_CH3 0x0000000FU +#define DMA2D_OUTFIFO_CNT_L2_CH3_M (DMA2D_OUTFIFO_CNT_L2_CH3_V << DMA2D_OUTFIFO_CNT_L2_CH3_S) +#define DMA2D_OUTFIFO_CNT_L2_CH3_V 0x0000000FU +#define DMA2D_OUTFIFO_CNT_L2_CH3_S 2 +/** DMA2D_OUT_REMAIN_UNDER_1B_CH3 : RO; bitpos: [7]; default: 1; * reserved */ -#define DMA2D_IN_REMAIN_UNDER_1B_CH0 (BIT(7)) -#define DMA2D_IN_REMAIN_UNDER_1B_CH0_M (DMA2D_IN_REMAIN_UNDER_1B_CH0_V << DMA2D_IN_REMAIN_UNDER_1B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_1B_CH0_S 7 -/** DMA2D_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 0; +#define DMA2D_OUT_REMAIN_UNDER_1B_CH3 (BIT(7)) +#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_M (DMA2D_OUT_REMAIN_UNDER_1B_CH3_V << DMA2D_OUT_REMAIN_UNDER_1B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_S 7 +/** DMA2D_OUT_REMAIN_UNDER_2B_CH3 : RO; bitpos: [8]; default: 1; * reserved */ -#define DMA2D_IN_REMAIN_UNDER_2B_CH0 (BIT(8)) -#define DMA2D_IN_REMAIN_UNDER_2B_CH0_M (DMA2D_IN_REMAIN_UNDER_2B_CH0_V << DMA2D_IN_REMAIN_UNDER_2B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_2B_CH0_S 8 -/** DMA2D_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 0; +#define DMA2D_OUT_REMAIN_UNDER_2B_CH3 (BIT(8)) +#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_M (DMA2D_OUT_REMAIN_UNDER_2B_CH3_V << DMA2D_OUT_REMAIN_UNDER_2B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_S 8 +/** DMA2D_OUT_REMAIN_UNDER_3B_CH3 : RO; bitpos: [9]; default: 1; * reserved */ -#define DMA2D_IN_REMAIN_UNDER_3B_CH0 (BIT(9)) -#define DMA2D_IN_REMAIN_UNDER_3B_CH0_M (DMA2D_IN_REMAIN_UNDER_3B_CH0_V << DMA2D_IN_REMAIN_UNDER_3B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_3B_CH0_S 9 -/** DMA2D_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 0; +#define DMA2D_OUT_REMAIN_UNDER_3B_CH3 (BIT(9)) +#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_M (DMA2D_OUT_REMAIN_UNDER_3B_CH3_V << DMA2D_OUT_REMAIN_UNDER_3B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_S 9 +/** DMA2D_OUT_REMAIN_UNDER_4B_CH3 : RO; bitpos: [10]; default: 1; * reserved */ -#define DMA2D_IN_REMAIN_UNDER_4B_CH0 (BIT(10)) -#define DMA2D_IN_REMAIN_UNDER_4B_CH0_M (DMA2D_IN_REMAIN_UNDER_4B_CH0_V << DMA2D_IN_REMAIN_UNDER_4B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_4B_CH0_S 10 -/** DMA2D_IN_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 0; +#define DMA2D_OUT_REMAIN_UNDER_4B_CH3 (BIT(10)) +#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_M (DMA2D_OUT_REMAIN_UNDER_4B_CH3_V << DMA2D_OUT_REMAIN_UNDER_4B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_S 10 +/** DMA2D_OUT_REMAIN_UNDER_5B_CH3 : RO; bitpos: [11]; default: 1; * reserved */ -#define DMA2D_IN_REMAIN_UNDER_5B_CH0 (BIT(11)) -#define DMA2D_IN_REMAIN_UNDER_5B_CH0_M (DMA2D_IN_REMAIN_UNDER_5B_CH0_V << DMA2D_IN_REMAIN_UNDER_5B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_5B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_5B_CH0_S 11 -/** DMA2D_IN_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 0; +#define DMA2D_OUT_REMAIN_UNDER_5B_CH3 (BIT(11)) +#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_M (DMA2D_OUT_REMAIN_UNDER_5B_CH3_V << DMA2D_OUT_REMAIN_UNDER_5B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_S 11 +/** DMA2D_OUT_REMAIN_UNDER_6B_CH3 : RO; bitpos: [12]; default: 1; * reserved */ -#define DMA2D_IN_REMAIN_UNDER_6B_CH0 (BIT(12)) -#define DMA2D_IN_REMAIN_UNDER_6B_CH0_M (DMA2D_IN_REMAIN_UNDER_6B_CH0_V << DMA2D_IN_REMAIN_UNDER_6B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_6B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_6B_CH0_S 12 -/** DMA2D_IN_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 0; +#define DMA2D_OUT_REMAIN_UNDER_6B_CH3 (BIT(12)) +#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_M (DMA2D_OUT_REMAIN_UNDER_6B_CH3_V << DMA2D_OUT_REMAIN_UNDER_6B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_S 12 +/** DMA2D_OUT_REMAIN_UNDER_7B_CH3 : RO; bitpos: [13]; default: 1; * reserved */ -#define DMA2D_IN_REMAIN_UNDER_7B_CH0 (BIT(13)) -#define DMA2D_IN_REMAIN_UNDER_7B_CH0_M (DMA2D_IN_REMAIN_UNDER_7B_CH0_V << DMA2D_IN_REMAIN_UNDER_7B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_7B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_7B_CH0_S 13 -/** DMA2D_IN_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 0; +#define DMA2D_OUT_REMAIN_UNDER_7B_CH3 (BIT(13)) +#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_M (DMA2D_OUT_REMAIN_UNDER_7B_CH3_V << DMA2D_OUT_REMAIN_UNDER_7B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_S 13 +/** DMA2D_OUT_REMAIN_UNDER_8B_CH3 : RO; bitpos: [14]; default: 1; * reserved */ -#define DMA2D_IN_REMAIN_UNDER_8B_CH0 (BIT(14)) -#define DMA2D_IN_REMAIN_UNDER_8B_CH0_M (DMA2D_IN_REMAIN_UNDER_8B_CH0_V << DMA2D_IN_REMAIN_UNDER_8B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_8B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_8B_CH0_S 14 -/** DMA2D_INFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0; +#define DMA2D_OUT_REMAIN_UNDER_8B_CH3 (BIT(14)) +#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_M (DMA2D_OUT_REMAIN_UNDER_8B_CH3_V << DMA2D_OUT_REMAIN_UNDER_8B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_S 14 +/** DMA2D_OUTFIFO_FULL_L1_CH3 : RO; bitpos: [15]; default: 0; * Tx FIFO full signal for Tx channel 0. */ -#define DMA2D_INFIFO_FULL_L1_CH0 (BIT(15)) -#define DMA2D_INFIFO_FULL_L1_CH0_M (DMA2D_INFIFO_FULL_L1_CH0_V << DMA2D_INFIFO_FULL_L1_CH0_S) -#define DMA2D_INFIFO_FULL_L1_CH0_V 0x00000001U -#define DMA2D_INFIFO_FULL_L1_CH0_S 15 -/** DMA2D_INFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1; +#define DMA2D_OUTFIFO_FULL_L1_CH3 (BIT(15)) +#define DMA2D_OUTFIFO_FULL_L1_CH3_M (DMA2D_OUTFIFO_FULL_L1_CH3_V << DMA2D_OUTFIFO_FULL_L1_CH3_S) +#define DMA2D_OUTFIFO_FULL_L1_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_FULL_L1_CH3_S 15 +/** DMA2D_OUTFIFO_EMPTY_L1_CH3 : RO; bitpos: [16]; default: 1; * Tx FIFO empty signal for Tx channel 0. */ -#define DMA2D_INFIFO_EMPTY_L1_CH0 (BIT(16)) -#define DMA2D_INFIFO_EMPTY_L1_CH0_M (DMA2D_INFIFO_EMPTY_L1_CH0_V << DMA2D_INFIFO_EMPTY_L1_CH0_S) -#define DMA2D_INFIFO_EMPTY_L1_CH0_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L1_CH0_S 16 -/** DMA2D_INFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0; +#define DMA2D_OUTFIFO_EMPTY_L1_CH3 (BIT(16)) +#define DMA2D_OUTFIFO_EMPTY_L1_CH3_M (DMA2D_OUTFIFO_EMPTY_L1_CH3_V << DMA2D_OUTFIFO_EMPTY_L1_CH3_S) +#define DMA2D_OUTFIFO_EMPTY_L1_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_EMPTY_L1_CH3_S 16 +/** DMA2D_OUTFIFO_CNT_L1_CH3 : RO; bitpos: [21:17]; default: 0; * The register stores the byte number of the data in Tx FIFO for Tx channel 0. */ -#define DMA2D_INFIFO_CNT_L1_CH0 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH0_M (DMA2D_INFIFO_CNT_L1_CH0_V << DMA2D_INFIFO_CNT_L1_CH0_S) -#define DMA2D_INFIFO_CNT_L1_CH0_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH0_S 17 -/** DMA2D_INFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0; +#define DMA2D_OUTFIFO_CNT_L1_CH3 0x0000001FU +#define DMA2D_OUTFIFO_CNT_L1_CH3_M (DMA2D_OUTFIFO_CNT_L1_CH3_V << DMA2D_OUTFIFO_CNT_L1_CH3_S) +#define DMA2D_OUTFIFO_CNT_L1_CH3_V 0x0000001FU +#define DMA2D_OUTFIFO_CNT_L1_CH3_S 17 +/** DMA2D_OUTFIFO_FULL_L3_CH3 : RO; bitpos: [22]; default: 0; * Tx FIFO full signal for Tx channel 0. */ -#define DMA2D_INFIFO_FULL_L3_CH0 (BIT(22)) -#define DMA2D_INFIFO_FULL_L3_CH0_M (DMA2D_INFIFO_FULL_L3_CH0_V << DMA2D_INFIFO_FULL_L3_CH0_S) -#define DMA2D_INFIFO_FULL_L3_CH0_V 0x00000001U -#define DMA2D_INFIFO_FULL_L3_CH0_S 22 -/** DMA2D_INFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1; +#define DMA2D_OUTFIFO_FULL_L3_CH3 (BIT(22)) +#define DMA2D_OUTFIFO_FULL_L3_CH3_M (DMA2D_OUTFIFO_FULL_L3_CH3_V << DMA2D_OUTFIFO_FULL_L3_CH3_S) +#define DMA2D_OUTFIFO_FULL_L3_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_FULL_L3_CH3_S 22 +/** DMA2D_OUTFIFO_EMPTY_L3_CH3 : RO; bitpos: [23]; default: 1; * Tx FIFO empty signal for Tx channel 0. */ -#define DMA2D_INFIFO_EMPTY_L3_CH0 (BIT(23)) -#define DMA2D_INFIFO_EMPTY_L3_CH0_M (DMA2D_INFIFO_EMPTY_L3_CH0_V << DMA2D_INFIFO_EMPTY_L3_CH0_S) -#define DMA2D_INFIFO_EMPTY_L3_CH0_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L3_CH0_S 23 -/** DMA2D_INFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0; +#define DMA2D_OUTFIFO_EMPTY_L3_CH3 (BIT(23)) +#define DMA2D_OUTFIFO_EMPTY_L3_CH3_M (DMA2D_OUTFIFO_EMPTY_L3_CH3_V << DMA2D_OUTFIFO_EMPTY_L3_CH3_S) +#define DMA2D_OUTFIFO_EMPTY_L3_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_EMPTY_L3_CH3_S 23 +/** DMA2D_OUTFIFO_CNT_L3_CH3 : RO; bitpos: [28:24]; default: 0; * The register stores the byte number of the data in Tx FIFO for Tx channel 0. */ -#define DMA2D_INFIFO_CNT_L3_CH0 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH0_M (DMA2D_INFIFO_CNT_L3_CH0_V << DMA2D_INFIFO_CNT_L3_CH0_S) -#define DMA2D_INFIFO_CNT_L3_CH0_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH0_S 24 +#define DMA2D_OUTFIFO_CNT_L3_CH3 0x0000001FU +#define DMA2D_OUTFIFO_CNT_L3_CH3_M (DMA2D_OUTFIFO_CNT_L3_CH3_V << DMA2D_OUTFIFO_CNT_L3_CH3_S) +#define DMA2D_OUTFIFO_CNT_L3_CH3_V 0x0000001FU +#define DMA2D_OUTFIFO_CNT_L3_CH3_S 24 -/** DMA2D_IN_POP_CH0_REG register - * Configures the rx fifo of channel 0 +/** DMA2D_OUT_PUSH_CH3_REG register + * Configures the tx fifo of channel 3 */ -#define DMA2D_IN_POP_CH0_REG (DR_REG_DMA2D_BASE + 0x518) -/** DMA2D_INFIFO_RDATA_CH0 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. +#define DMA2D_OUT_PUSH_CH3_REG (DR_REG_DMA2D_BASE + 0x318) +/** DMA2D_OUTFIFO_WDATA_CH3 : R/W; bitpos: [9:0]; default: 0; + * This register stores the data that need to be pushed into DMA Tx FIFO. */ -#define DMA2D_INFIFO_RDATA_CH0 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH0_M (DMA2D_INFIFO_RDATA_CH0_V << DMA2D_INFIFO_RDATA_CH0_S) -#define DMA2D_INFIFO_RDATA_CH0_V 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH0_S 0 -/** DMA2D_INFIFO_POP_CH0 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. +#define DMA2D_OUTFIFO_WDATA_CH3 0x000003FFU +#define DMA2D_OUTFIFO_WDATA_CH3_M (DMA2D_OUTFIFO_WDATA_CH3_V << DMA2D_OUTFIFO_WDATA_CH3_S) +#define DMA2D_OUTFIFO_WDATA_CH3_V 0x000003FFU +#define DMA2D_OUTFIFO_WDATA_CH3_S 0 +/** DMA2D_OUTFIFO_PUSH_CH3 : R/W/SC; bitpos: [10]; default: 0; + * Set this bit to push data into DMA Tx FIFO. */ -#define DMA2D_INFIFO_POP_CH0 (BIT(11)) -#define DMA2D_INFIFO_POP_CH0_M (DMA2D_INFIFO_POP_CH0_V << DMA2D_INFIFO_POP_CH0_S) -#define DMA2D_INFIFO_POP_CH0_V 0x00000001U -#define DMA2D_INFIFO_POP_CH0_S 11 +#define DMA2D_OUTFIFO_PUSH_CH3 (BIT(10)) +#define DMA2D_OUTFIFO_PUSH_CH3_M (DMA2D_OUTFIFO_PUSH_CH3_V << DMA2D_OUTFIFO_PUSH_CH3_S) +#define DMA2D_OUTFIFO_PUSH_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_PUSH_CH3_S 10 -/** DMA2D_IN_LINK_CONF_CH0_REG register - * Configures the rx descriptor operations of channel 0 +/** DMA2D_OUT_LINK_CONF_CH3_REG register + * Configures the tx descriptor operations of channel 3 */ -#define DMA2D_IN_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x51c) -/** DMA2D_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1; - * Configure the value of the owner field written back to the inlink descriptor. - * 1: Write back 1. 0: Write back 0. - */ -#define DMA2D_INLINK_AUTO_RET_CH0 (BIT(20)) -#define DMA2D_INLINK_AUTO_RET_CH0_M (DMA2D_INLINK_AUTO_RET_CH0_V << DMA2D_INLINK_AUTO_RET_CH0_S) -#define DMA2D_INLINK_AUTO_RET_CH0_V 0x00000001U -#define DMA2D_INLINK_AUTO_RET_CH0_S 20 -/** DMA2D_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. +#define DMA2D_OUT_LINK_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x31c) +/** DMA2D_OUTLINK_STOP_CH3 : R/W/SC; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. */ -#define DMA2D_INLINK_STOP_CH0 (BIT(21)) -#define DMA2D_INLINK_STOP_CH0_M (DMA2D_INLINK_STOP_CH0_V << DMA2D_INLINK_STOP_CH0_S) -#define DMA2D_INLINK_STOP_CH0_V 0x00000001U -#define DMA2D_INLINK_STOP_CH0_S 21 -/** DMA2D_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. +#define DMA2D_OUTLINK_STOP_CH3 (BIT(20)) +#define DMA2D_OUTLINK_STOP_CH3_M (DMA2D_OUTLINK_STOP_CH3_V << DMA2D_OUTLINK_STOP_CH3_S) +#define DMA2D_OUTLINK_STOP_CH3_V 0x00000001U +#define DMA2D_OUTLINK_STOP_CH3_S 20 +/** DMA2D_OUTLINK_START_CH3 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. */ -#define DMA2D_INLINK_START_CH0 (BIT(22)) -#define DMA2D_INLINK_START_CH0_M (DMA2D_INLINK_START_CH0_V << DMA2D_INLINK_START_CH0_S) -#define DMA2D_INLINK_START_CH0_V 0x00000001U -#define DMA2D_INLINK_START_CH0_S 22 -/** DMA2D_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. +#define DMA2D_OUTLINK_START_CH3 (BIT(21)) +#define DMA2D_OUTLINK_START_CH3_M (DMA2D_OUTLINK_START_CH3_V << DMA2D_OUTLINK_START_CH3_S) +#define DMA2D_OUTLINK_START_CH3_V 0x00000001U +#define DMA2D_OUTLINK_START_CH3_S 21 +/** DMA2D_OUTLINK_RESTART_CH3 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. */ -#define DMA2D_INLINK_RESTART_CH0 (BIT(23)) -#define DMA2D_INLINK_RESTART_CH0_M (DMA2D_INLINK_RESTART_CH0_V << DMA2D_INLINK_RESTART_CH0_S) -#define DMA2D_INLINK_RESTART_CH0_V 0x00000001U -#define DMA2D_INLINK_RESTART_CH0_S 23 -/** DMA2D_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. +#define DMA2D_OUTLINK_RESTART_CH3 (BIT(22)) +#define DMA2D_OUTLINK_RESTART_CH3_M (DMA2D_OUTLINK_RESTART_CH3_V << DMA2D_OUTLINK_RESTART_CH3_S) +#define DMA2D_OUTLINK_RESTART_CH3_V 0x00000001U +#define DMA2D_OUTLINK_RESTART_CH3_S 22 +/** DMA2D_OUTLINK_PARK_CH3 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. */ -#define DMA2D_INLINK_PARK_CH0 (BIT(24)) -#define DMA2D_INLINK_PARK_CH0_M (DMA2D_INLINK_PARK_CH0_V << DMA2D_INLINK_PARK_CH0_S) -#define DMA2D_INLINK_PARK_CH0_V 0x00000001U -#define DMA2D_INLINK_PARK_CH0_S 24 +#define DMA2D_OUTLINK_PARK_CH3 (BIT(23)) +#define DMA2D_OUTLINK_PARK_CH3_M (DMA2D_OUTLINK_PARK_CH3_V << DMA2D_OUTLINK_PARK_CH3_S) +#define DMA2D_OUTLINK_PARK_CH3_V 0x00000001U +#define DMA2D_OUTLINK_PARK_CH3_S 23 -/** DMA2D_IN_LINK_ADDR_CH0_REG register - * Configures the rx descriptor address of channel 0 +/** DMA2D_OUT_LINK_ADDR_CH3_REG register + * Configures the tx descriptor address of channel 3 */ -#define DMA2D_IN_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x520) -/** DMA2D_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. +#define DMA2D_OUT_LINK_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x320) +/** DMA2D_OUTLINK_ADDR_CH3 : R/W; bitpos: [31:0]; default: 0; + * This register stores the first outlink descriptor's address. */ -#define DMA2D_INLINK_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH0_M (DMA2D_INLINK_ADDR_CH0_V << DMA2D_INLINK_ADDR_CH0_S) -#define DMA2D_INLINK_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH0_S 0 +#define DMA2D_OUTLINK_ADDR_CH3 0xFFFFFFFFU +#define DMA2D_OUTLINK_ADDR_CH3_M (DMA2D_OUTLINK_ADDR_CH3_V << DMA2D_OUTLINK_ADDR_CH3_S) +#define DMA2D_OUTLINK_ADDR_CH3_V 0xFFFFFFFFU +#define DMA2D_OUTLINK_ADDR_CH3_S 0 -/** DMA2D_IN_STATE_CH0_REG register - * Represents the working status of the rx descriptor of channel 0 +/** DMA2D_OUT_STATE_CH3_REG register + * Represents the working status of the tx descriptor of channel 3 */ -#define DMA2D_IN_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x524) -/** DMA2D_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. +#define DMA2D_OUT_STATE_CH3_REG (DR_REG_DMA2D_BASE + 0x324) +/** DMA2D_OUTLINK_DSCR_ADDR_CH3 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. */ -#define DMA2D_INLINK_DSCR_ADDR_CH0 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH0_M (DMA2D_INLINK_DSCR_ADDR_CH0_V << DMA2D_INLINK_DSCR_ADDR_CH0_S) -#define DMA2D_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH0_S 0 -/** DMA2D_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * reserved +#define DMA2D_OUTLINK_DSCR_ADDR_CH3 0x0003FFFFU +#define DMA2D_OUTLINK_DSCR_ADDR_CH3_M (DMA2D_OUTLINK_DSCR_ADDR_CH3_V << DMA2D_OUTLINK_DSCR_ADDR_CH3_S) +#define DMA2D_OUTLINK_DSCR_ADDR_CH3_V 0x0003FFFFU +#define DMA2D_OUTLINK_DSCR_ADDR_CH3_S 0 +/** DMA2D_OUT_DSCR_STATE_CH3 : RO; bitpos: [19:18]; default: 0; + * This register stores the current descriptor state machine state. */ -#define DMA2D_IN_DSCR_STATE_CH0 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH0_M (DMA2D_IN_DSCR_STATE_CH0_V << DMA2D_IN_DSCR_STATE_CH0_S) -#define DMA2D_IN_DSCR_STATE_CH0_V 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH0_S 18 -/** DMA2D_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; - * reserved +#define DMA2D_OUT_DSCR_STATE_CH3 0x00000003U +#define DMA2D_OUT_DSCR_STATE_CH3_M (DMA2D_OUT_DSCR_STATE_CH3_V << DMA2D_OUT_DSCR_STATE_CH3_S) +#define DMA2D_OUT_DSCR_STATE_CH3_V 0x00000003U +#define DMA2D_OUT_DSCR_STATE_CH3_S 18 +/** DMA2D_OUT_STATE_CH3 : RO; bitpos: [23:20]; default: 0; + * This register stores the current control module state machine state. */ -#define DMA2D_IN_STATE_CH0 0x00000007U -#define DMA2D_IN_STATE_CH0_M (DMA2D_IN_STATE_CH0_V << DMA2D_IN_STATE_CH0_S) -#define DMA2D_IN_STATE_CH0_V 0x00000007U -#define DMA2D_IN_STATE_CH0_S 20 -/** DMA2D_IN_RESET_AVAIL_CH0 : RO; bitpos: [23]; default: 1; +#define DMA2D_OUT_STATE_CH3 0x0000000FU +#define DMA2D_OUT_STATE_CH3_M (DMA2D_OUT_STATE_CH3_V << DMA2D_OUT_STATE_CH3_S) +#define DMA2D_OUT_STATE_CH3_V 0x0000000FU +#define DMA2D_OUT_STATE_CH3_S 20 +/** DMA2D_OUT_RESET_AVAIL_CH3 : RO; bitpos: [24]; default: 1; * This register indicate that if the channel reset is safety. */ -#define DMA2D_IN_RESET_AVAIL_CH0 (BIT(23)) -#define DMA2D_IN_RESET_AVAIL_CH0_M (DMA2D_IN_RESET_AVAIL_CH0_V << DMA2D_IN_RESET_AVAIL_CH0_S) -#define DMA2D_IN_RESET_AVAIL_CH0_V 0x00000001U -#define DMA2D_IN_RESET_AVAIL_CH0_S 23 +#define DMA2D_OUT_RESET_AVAIL_CH3 (BIT(24)) +#define DMA2D_OUT_RESET_AVAIL_CH3_M (DMA2D_OUT_RESET_AVAIL_CH3_V << DMA2D_OUT_RESET_AVAIL_CH3_S) +#define DMA2D_OUT_RESET_AVAIL_CH3_V 0x00000001U +#define DMA2D_OUT_RESET_AVAIL_CH3_S 24 -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 +/** DMA2D_OUT_EOF_DES_ADDR_CH3_REG register + * Represents the address associated with the outlink descriptor of channel 3 */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x528) -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this +#define DMA2D_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x328) +/** DMA2D_OUT_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this * descriptor is 1. */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S) -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S 0 +#define DMA2D_OUT_EOF_DES_ADDR_CH3 0xFFFFFFFFU +#define DMA2D_OUT_EOF_DES_ADDR_CH3_M (DMA2D_OUT_EOF_DES_ADDR_CH3_V << DMA2D_OUT_EOF_DES_ADDR_CH3_S) +#define DMA2D_OUT_EOF_DES_ADDR_CH3_V 0xFFFFFFFFU +#define DMA2D_OUT_EOF_DES_ADDR_CH3_S 0 -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 +/** DMA2D_OUT_DSCR_CH3_REG register + * Represents the address associated with the outlink descriptor of channel 3 */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x52c) -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. +#define DMA2D_OUT_DSCR_CH3_REG (DR_REG_DMA2D_BASE + 0x32c) +/** DMA2D_OUTLINK_DSCR_CH3 : RO; bitpos: [31:0]; default: 0; + * The address of the next outlink descriptor address y. */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S) -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S 0 +#define DMA2D_OUTLINK_DSCR_CH3 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_CH3_M (DMA2D_OUTLINK_DSCR_CH3_V << DMA2D_OUTLINK_DSCR_CH3_S) +#define DMA2D_OUTLINK_DSCR_CH3_V 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_CH3_S 0 -/** DMA2D_IN_DSCR_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 +/** DMA2D_OUT_DSCR_BF0_CH3_REG register + * Represents the address associated with the outlink descriptor of channel 3 */ -#define DMA2D_IN_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x530) -/** DMA2D_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ -#define DMA2D_INLINK_DSCR_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH0_M (DMA2D_INLINK_DSCR_CH0_V << DMA2D_INLINK_DSCR_CH0_S) -#define DMA2D_INLINK_DSCR_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH0_S 0 - -/** DMA2D_IN_DSCR_BF0_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x534) -/** DMA2D_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. +#define DMA2D_OUT_DSCR_BF0_CH3_REG (DR_REG_DMA2D_BASE + 0x330) +/** DMA2D_OUTLINK_DSCR_BF0_CH3 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor's next address y-1. */ -#define DMA2D_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH0_M (DMA2D_INLINK_DSCR_BF0_CH0_V << DMA2D_INLINK_DSCR_BF0_CH0_S) -#define DMA2D_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH0_S 0 +#define DMA2D_OUTLINK_DSCR_BF0_CH3 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_BF0_CH3_M (DMA2D_OUTLINK_DSCR_BF0_CH3_V << DMA2D_OUTLINK_DSCR_BF0_CH3_S) +#define DMA2D_OUTLINK_DSCR_BF0_CH3_V 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_BF0_CH3_S 0 -/** DMA2D_IN_DSCR_BF1_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 +/** DMA2D_OUT_DSCR_BF1_CH3_REG register + * Represents the address associated with the outlink descriptor of channel 3 */ -#define DMA2D_IN_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x538) -/** DMA2D_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. +#define DMA2D_OUT_DSCR_BF1_CH3_REG (DR_REG_DMA2D_BASE + 0x334) +/** DMA2D_OUTLINK_DSCR_BF1_CH3 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last outlink descriptor's next address y-2. */ -#define DMA2D_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH0_M (DMA2D_INLINK_DSCR_BF1_CH0_V << DMA2D_INLINK_DSCR_BF1_CH0_S) -#define DMA2D_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH0_S 0 +#define DMA2D_OUTLINK_DSCR_BF1_CH3 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_BF1_CH3_M (DMA2D_OUTLINK_DSCR_BF1_CH3_V << DMA2D_OUTLINK_DSCR_BF1_CH3_S) +#define DMA2D_OUTLINK_DSCR_BF1_CH3_V 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_BF1_CH3_S 0 -/** DMA2D_IN_PERI_SEL_CH0_REG register - * Configures the rx peripheral of channel 0 +/** DMA2D_OUT_PERI_SEL_CH3_REG register + * Configures the tx peripheral of channel 3 */ -#define DMA2D_IN_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x53c) -/** DMA2D_IN_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Rx channel 0: jpeg 1: - * display-1 2: display-2 7: no choose +#define DMA2D_OUT_PERI_SEL_CH3_REG (DR_REG_DMA2D_BASE + 0x338) +/** DMA2D_OUT_PERI_SEL_CH3 : R/W; bitpos: [2:0]; default: 7; + * This register is used to select peripheral for Tx channel 0: jpeg 1: + * display-1 2: display-2 3: display-3 7: no choose */ -#define DMA2D_IN_PERI_SEL_CH0 0x00000007U -#define DMA2D_IN_PERI_SEL_CH0_M (DMA2D_IN_PERI_SEL_CH0_V << DMA2D_IN_PERI_SEL_CH0_S) -#define DMA2D_IN_PERI_SEL_CH0_V 0x00000007U -#define DMA2D_IN_PERI_SEL_CH0_S 0 +#define DMA2D_OUT_PERI_SEL_CH3 0x00000007U +#define DMA2D_OUT_PERI_SEL_CH3_M (DMA2D_OUT_PERI_SEL_CH3_V << DMA2D_OUT_PERI_SEL_CH3_S) +#define DMA2D_OUT_PERI_SEL_CH3_V 0x00000007U +#define DMA2D_OUT_PERI_SEL_CH3_S 0 -/** DMA2D_IN_ARB_CH0_REG register - * Configures the rx arbiter of channel 0 +/** DMA2D_OUT_ARB_CH3_REG register + * Configures the tx arbiter of channel 3 */ -#define DMA2D_IN_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x540) -/** DMA2D_IN_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1; +#define DMA2D_OUT_ARB_CH3_REG (DR_REG_DMA2D_BASE + 0x33c) +/** DMA2D_OUT_ARB_TOKEN_NUM_CH3 : R/W; bitpos: [3:0]; default: 1; * Set the max number of token count of arbiter */ -#define DMA2D_IN_ARB_TOKEN_NUM_CH0 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH0_M (DMA2D_IN_ARB_TOKEN_NUM_CH0_V << DMA2D_IN_ARB_TOKEN_NUM_CH0_S) -#define DMA2D_IN_ARB_TOKEN_NUM_CH0_V 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH0_S 0 -/** DMA2D_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [4]; default: 1; +#define DMA2D_OUT_ARB_TOKEN_NUM_CH3 0x0000000FU +#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_M (DMA2D_OUT_ARB_TOKEN_NUM_CH3_V << DMA2D_OUT_ARB_TOKEN_NUM_CH3_S) +#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_V 0x0000000FU +#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_S 0 +/** DMA2D_OUT_ARB_PRIORITY_CH3 : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ -#define DMA2D_IN_ARB_PRIORITY_CH0 (BIT(4)) -#define DMA2D_IN_ARB_PRIORITY_CH0_M (DMA2D_IN_ARB_PRIORITY_CH0_V << DMA2D_IN_ARB_PRIORITY_CH0_S) -#define DMA2D_IN_ARB_PRIORITY_CH0_V 0x00000001U -#define DMA2D_IN_ARB_PRIORITY_CH0_S 4 +#define DMA2D_OUT_ARB_PRIORITY_CH3 0x0000000FU +#define DMA2D_OUT_ARB_PRIORITY_CH3_M (DMA2D_OUT_ARB_PRIORITY_CH3_V << DMA2D_OUT_ARB_PRIORITY_CH3_S) +#define DMA2D_OUT_ARB_PRIORITY_CH3_V 0x0000000FU +#define DMA2D_OUT_ARB_PRIORITY_CH3_S 4 -/** DMA2D_IN_RO_STATUS_CH0_REG register - * Represents the status of the rx reorder module of channel 0 +/** DMA2D_OUT_RO_STATUS_CH3_REG register + * Represents the status of the tx reorder module of channel 3 */ -#define DMA2D_IN_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x544) -/** DMA2D_INFIFO_RO_CNT_CH0 : RO; bitpos: [4:0]; default: 0; - * The register stores the byte number of the data in color convert Rx FIFO for +#define DMA2D_OUT_RO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x340) +/** DMA2D_OUTFIFO_RO_CNT_CH3 : RO; bitpos: [5:0]; default: 0; + * The register stores the byte number of the data in color convert Tx FIFO for * channel 0. */ -#define DMA2D_INFIFO_RO_CNT_CH0 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH0_M (DMA2D_INFIFO_RO_CNT_CH0_V << DMA2D_INFIFO_RO_CNT_CH0_S) -#define DMA2D_INFIFO_RO_CNT_CH0_V 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH0_S 0 -/** DMA2D_IN_RO_WR_STATE_CH0 : RO; bitpos: [6:5]; default: 0; +#define DMA2D_OUTFIFO_RO_CNT_CH3 0x0000003FU +#define DMA2D_OUTFIFO_RO_CNT_CH3_M (DMA2D_OUTFIFO_RO_CNT_CH3_V << DMA2D_OUTFIFO_RO_CNT_CH3_S) +#define DMA2D_OUTFIFO_RO_CNT_CH3_V 0x0000003FU +#define DMA2D_OUTFIFO_RO_CNT_CH3_S 0 +/** DMA2D_OUT_RO_WR_STATE_CH3 : RO; bitpos: [7:6]; default: 0; * The register stores the state of read ram of reorder */ -#define DMA2D_IN_RO_WR_STATE_CH0 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH0_M (DMA2D_IN_RO_WR_STATE_CH0_V << DMA2D_IN_RO_WR_STATE_CH0_S) -#define DMA2D_IN_RO_WR_STATE_CH0_V 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH0_S 5 -/** DMA2D_IN_RO_RD_STATE_CH0 : RO; bitpos: [8:7]; default: 0; +#define DMA2D_OUT_RO_WR_STATE_CH3 0x00000003U +#define DMA2D_OUT_RO_WR_STATE_CH3_M (DMA2D_OUT_RO_WR_STATE_CH3_V << DMA2D_OUT_RO_WR_STATE_CH3_S) +#define DMA2D_OUT_RO_WR_STATE_CH3_V 0x00000003U +#define DMA2D_OUT_RO_WR_STATE_CH3_S 6 +/** DMA2D_OUT_RO_RD_STATE_CH3 : RO; bitpos: [9:8]; default: 0; * The register stores the state of write ram of reorder */ -#define DMA2D_IN_RO_RD_STATE_CH0 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH0_M (DMA2D_IN_RO_RD_STATE_CH0_V << DMA2D_IN_RO_RD_STATE_CH0_S) -#define DMA2D_IN_RO_RD_STATE_CH0_V 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH0_S 7 -/** DMA2D_IN_PIXEL_BYTE_CH0 : RO; bitpos: [12:9]; default: 0; - * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes +#define DMA2D_OUT_RO_RD_STATE_CH3 0x00000003U +#define DMA2D_OUT_RO_RD_STATE_CH3_M (DMA2D_OUT_RO_RD_STATE_CH3_V << DMA2D_OUT_RO_RD_STATE_CH3_S) +#define DMA2D_OUT_RO_RD_STATE_CH3_V 0x00000003U +#define DMA2D_OUT_RO_RD_STATE_CH3_S 8 +/** DMA2D_OUT_PIXEL_BYTE_CH3 : RO; bitpos: [13:10]; default: 0; + * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes */ -#define DMA2D_IN_PIXEL_BYTE_CH0 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH0_M (DMA2D_IN_PIXEL_BYTE_CH0_V << DMA2D_IN_PIXEL_BYTE_CH0_S) -#define DMA2D_IN_PIXEL_BYTE_CH0_V 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH0_S 9 -/** DMA2D_IN_BURST_BLOCK_NUM_CH0 : RO; bitpos: [16:13]; default: 0; - * the number of macro blocks contained in a burst of data at RX channel - */ -#define DMA2D_IN_BURST_BLOCK_NUM_CH0 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH0_M (DMA2D_IN_BURST_BLOCK_NUM_CH0_V << DMA2D_IN_BURST_BLOCK_NUM_CH0_S) -#define DMA2D_IN_BURST_BLOCK_NUM_CH0_V 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH0_S 13 - -/** DMA2D_IN_RO_PD_CONF_CH0_REG register - * Configures the rx reorder memory of channel 0 - */ -#define DMA2D_IN_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x548) -/** DMA2D_IN_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0 (BIT(4)) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_M (DMA2D_IN_RO_RAM_FORCE_PD_CH0_V << DMA2D_IN_RO_RAM_FORCE_PD_CH0_S) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_S 4 -/** DMA2D_IN_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0 (BIT(5)) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_M (DMA2D_IN_RO_RAM_FORCE_PU_CH0_V << DMA2D_IN_RO_RAM_FORCE_PU_CH0_S) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_S 5 -/** DMA2D_IN_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. +#define DMA2D_OUT_PIXEL_BYTE_CH3 0x0000000FU +#define DMA2D_OUT_PIXEL_BYTE_CH3_M (DMA2D_OUT_PIXEL_BYTE_CH3_V << DMA2D_OUT_PIXEL_BYTE_CH3_S) +#define DMA2D_OUT_PIXEL_BYTE_CH3_V 0x0000000FU +#define DMA2D_OUT_PIXEL_BYTE_CH3_S 10 +/** DMA2D_OUT_BURST_BLOCK_NUM_CH3 : RO; bitpos: [17:14]; default: 0; + * the number of macro blocks contained in a burst of data at TX channel */ -#define DMA2D_IN_RO_RAM_CLK_FO_CH0 (BIT(6)) -#define DMA2D_IN_RO_RAM_CLK_FO_CH0_M (DMA2D_IN_RO_RAM_CLK_FO_CH0_V << DMA2D_IN_RO_RAM_CLK_FO_CH0_S) -#define DMA2D_IN_RO_RAM_CLK_FO_CH0_V 0x00000001U -#define DMA2D_IN_RO_RAM_CLK_FO_CH0_S 6 +#define DMA2D_OUT_BURST_BLOCK_NUM_CH3 0x0000000FU +#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_M (DMA2D_OUT_BURST_BLOCK_NUM_CH3_V << DMA2D_OUT_BURST_BLOCK_NUM_CH3_S) +#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_V 0x0000000FU +#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_S 14 -/** DMA2D_IN_COLOR_CONVERT_CH0_REG register - * Configures the tx color convert of channel 0 +/** DMA2D_OUT_COLOR_CONVERT_CH3_REG register + * Configures the tx color convert of channel 3 */ -#define DMA2D_IN_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x54c) -/** DMA2D_IN_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; +#define DMA2D_OUT_COLOR_CONVERT_CH3_REG (DR_REG_DMA2D_BASE + 0x348) +/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly + * YUV444 to YUV422 2: output directly */ -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_M (DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S) -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S 0 -/** DMA2D_IN_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0; +#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3 0x00000003U +#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_M (DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S) +#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V 0x00000003U +#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S 0 +/** DMA2D_OUT_COLOR_3B_PROC_EN_CH3 : R/W; bitpos: [2]; default: 0; * Enable generic color convert module between color input & color output, need to * configure parameter. */ -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0 (BIT(2)) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_M (DMA2D_IN_COLOR_3B_PROC_EN_CH0_V << DMA2D_IN_COLOR_3B_PROC_EN_CH0_S) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_V 0x00000001U -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_S 2 -/** DMA2D_IN_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: YUV422/420 to YUV444 - * 1: YUV422 2: YUV444/420 7: disable color space convert +#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3 (BIT(2)) +#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_M (DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S) +#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V 0x00000001U +#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S 2 +/** DMA2D_OUT_COLOR_INPUT_SEL_CH3 : R/W; bitpos: [5:3]; default: 7; + * Set first color convert process and input color type 0: RGB565 to RGB888 1: + * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: + * disable color space convert */ -#define DMA2D_IN_COLOR_INPUT_SEL_CH0 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH0_M (DMA2D_IN_COLOR_INPUT_SEL_CH0_V << DMA2D_IN_COLOR_INPUT_SEL_CH0_S) -#define DMA2D_IN_COLOR_INPUT_SEL_CH0_V 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH0_S 3 +#define DMA2D_OUT_COLOR_INPUT_SEL_CH3 0x00000007U +#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_M (DMA2D_OUT_COLOR_INPUT_SEL_CH3_V << DMA2D_OUT_COLOR_INPUT_SEL_CH3_S) +#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_V 0x00000007U +#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_S 3 -/** DMA2D_IN_SCRAMBLE_CH0_REG register - * Configures the rx scramble of channel 0 +/** DMA2D_OUT_SCRAMBLE_CH3_REG register + * Configures the tx scramble of channel 3 */ -#define DMA2D_IN_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x550) -/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0; +#define DMA2D_OUT_SCRAMBLE_CH3_REG (DR_REG_DMA2D_BASE + 0x34c) +/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3 : R/W; bitpos: [2:0]; default: 0; * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 */ -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_M (DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S) -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S 0 -/** DMA2D_IN_SCRAMBLE_SEL_POST_CH0 : R/W; bitpos: [5:3]; default: 0; - * Scramble data after color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : BYTE1-0-2 - * 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_M (DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S) -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S 3 +#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3 0x00000007U +#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_M (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S) +#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V 0x00000007U +#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S 0 -/** DMA2D_IN_COLOR_PARAM0_CH0_REG register - * Configures the rx color convert parameter of channel 0 +/** DMA2D_OUT_COLOR_PARAM0_CH3_REG register + * Configures the tx color convert parameter of channel 3 */ -#define DMA2D_IN_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x554) -/** DMA2D_IN_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298; +#define DMA2D_OUT_COLOR_PARAM0_CH3_REG (DR_REG_DMA2D_BASE + 0x350) +/** DMA2D_OUT_COLOR_PARAM_H0_CH3 : R/W; bitpos: [20:0]; default: 298; * Set first 2 parameter of most significant byte of pending 3 bytes */ -#define DMA2D_IN_COLOR_PARAM_H0_CH0 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH0_M (DMA2D_IN_COLOR_PARAM_H0_CH0_V << DMA2D_IN_COLOR_PARAM_H0_CH0_S) -#define DMA2D_IN_COLOR_PARAM_H0_CH0_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH0_S 0 +#define DMA2D_OUT_COLOR_PARAM_H0_CH3 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_H0_CH3_M (DMA2D_OUT_COLOR_PARAM_H0_CH3_V << DMA2D_OUT_COLOR_PARAM_H0_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_H0_CH3_V 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_H0_CH3_S 0 -/** DMA2D_IN_COLOR_PARAM1_CH0_REG register - * Configures the rx color convert parameter of channel 0 +/** DMA2D_OUT_COLOR_PARAM1_CH3_REG register + * Configures the tx color convert parameter of channel 3 */ -#define DMA2D_IN_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x558) -/** DMA2D_IN_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121; +#define DMA2D_OUT_COLOR_PARAM1_CH3_REG (DR_REG_DMA2D_BASE + 0x354) +/** DMA2D_OUT_COLOR_PARAM_H1_CH3 : R/W; bitpos: [27:0]; default: 210164121; * Set last 2 parameter of most significant byte of pending 3 bytes */ -#define DMA2D_IN_COLOR_PARAM_H1_CH0 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH0_M (DMA2D_IN_COLOR_PARAM_H1_CH0_V << DMA2D_IN_COLOR_PARAM_H1_CH0_S) -#define DMA2D_IN_COLOR_PARAM_H1_CH0_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH0_S 0 +#define DMA2D_OUT_COLOR_PARAM_H1_CH3 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_H1_CH3_M (DMA2D_OUT_COLOR_PARAM_H1_CH3_V << DMA2D_OUT_COLOR_PARAM_H1_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_H1_CH3_V 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_H1_CH3_S 0 -/** DMA2D_IN_COLOR_PARAM2_CH0_REG register - * Configures the rx color convert parameter of channel 0 +/** DMA2D_OUT_COLOR_PARAM2_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM2_CH3_REG (DR_REG_DMA2D_BASE + 0x358) +/** DMA2D_OUT_COLOR_PARAM_M0_CH3 : R/W; bitpos: [20:0]; default: 1995050; + * Set first 2 parameter of midium significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_M0_CH3 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_M0_CH3_M (DMA2D_OUT_COLOR_PARAM_M0_CH3_V << DMA2D_OUT_COLOR_PARAM_M0_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_M0_CH3_V 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_M0_CH3_S 0 + +/** DMA2D_OUT_COLOR_PARAM3_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM3_CH3_REG (DR_REG_DMA2D_BASE + 0x35c) +/** DMA2D_OUT_COLOR_PARAM_M1_CH3 : R/W; bitpos: [27:0]; default: 35540784; + * Set last 2 parameter of midium significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_M1_CH3 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_M1_CH3_M (DMA2D_OUT_COLOR_PARAM_M1_CH3_V << DMA2D_OUT_COLOR_PARAM_M1_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_M1_CH3_V 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_M1_CH3_S 0 + +/** DMA2D_OUT_COLOR_PARAM4_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM4_CH3_REG (DR_REG_DMA2D_BASE + 0x360) +/** DMA2D_OUT_COLOR_PARAM_L0_CH3 : R/W; bitpos: [20:0]; default: 528682; + * Set first 2 parameter of least significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_L0_CH3 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_L0_CH3_M (DMA2D_OUT_COLOR_PARAM_L0_CH3_V << DMA2D_OUT_COLOR_PARAM_L0_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_L0_CH3_V 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_L0_CH3_S 0 + +/** DMA2D_OUT_COLOR_PARAM5_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM5_CH3_REG (DR_REG_DMA2D_BASE + 0x364) +/** DMA2D_OUT_COLOR_PARAM_L1_CH3 : R/W; bitpos: [27:0]; default: 195899392; + * Set last 2 parameter of least significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_L1_CH3 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_L1_CH3_M (DMA2D_OUT_COLOR_PARAM_L1_CH3_V << DMA2D_OUT_COLOR_PARAM_L1_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_L1_CH3_V 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_L1_CH3_S 0 + +/** DMA2D_OUT_ETM_CONF_CH3_REG register + * Configures the tx etm of channel 3 + */ +#define DMA2D_OUT_ETM_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x368) +/** DMA2D_OUT_ETM_EN_CH3 : R/W; bitpos: [0]; default: 0; + * Configures the enable of the etm function, 1 is enable. + */ +#define DMA2D_OUT_ETM_EN_CH3 (BIT(0)) +#define DMA2D_OUT_ETM_EN_CH3_M (DMA2D_OUT_ETM_EN_CH3_V << DMA2D_OUT_ETM_EN_CH3_S) +#define DMA2D_OUT_ETM_EN_CH3_V 0x00000001U +#define DMA2D_OUT_ETM_EN_CH3_S 0 +/** DMA2D_OUT_ETM_LOOP_EN_CH3 : R/W; bitpos: [1]; default: 0; + * Configures the enable of the descriptors loop etm function, 1 is enable. + */ +#define DMA2D_OUT_ETM_LOOP_EN_CH3 (BIT(1)) +#define DMA2D_OUT_ETM_LOOP_EN_CH3_M (DMA2D_OUT_ETM_LOOP_EN_CH3_V << DMA2D_OUT_ETM_LOOP_EN_CH3_S) +#define DMA2D_OUT_ETM_LOOP_EN_CH3_V 0x00000001U +#define DMA2D_OUT_ETM_LOOP_EN_CH3_S 1 +/** DMA2D_OUT_DSCR_TASK_MAK_CH3 : R/W; bitpos: [3:2]; default: 1; + * Configures the maximum number of cacheable descriptors. + */ +#define DMA2D_OUT_DSCR_TASK_MAK_CH3 0x00000003U +#define DMA2D_OUT_DSCR_TASK_MAK_CH3_M (DMA2D_OUT_DSCR_TASK_MAK_CH3_V << DMA2D_OUT_DSCR_TASK_MAK_CH3_S) +#define DMA2D_OUT_DSCR_TASK_MAK_CH3_V 0x00000003U +#define DMA2D_OUT_DSCR_TASK_MAK_CH3_S 2 + +/** DMA2D_OUT_DSCR_PORT_BLK_CH3_REG register + * Configures the tx block size in dscr port mode + */ +#define DMA2D_OUT_DSCR_PORT_BLK_CH3_REG (DR_REG_DMA2D_BASE + 0x36c) +/** DMA2D_OUT_DSCR_PORT_BLK_H_CH3 : R/W; bitpos: [13:0]; default: 18; + * Set the horizontal width of tx block size in dscr port mode + */ +#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3 0x00003FFFU +#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_M (DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S) +#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V 0x00003FFFU +#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S 0 +/** DMA2D_OUT_DSCR_PORT_BLK_V_CH3 : R/W; bitpos: [27:14]; default: 18; + * Set the vertical height of tx block size in dscr port mode + */ +#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3 0x00003FFFU +#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_M (DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S) +#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V 0x00003FFFU +#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S 14 + +/** DMA2D_IN_CONF0_CH0_REG register + * Configures the rx direction of channel 0 + */ +#define DMA2D_IN_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x500) +/** DMA2D_IN_MEM_TRANS_EN_CH0 : R/W; bitpos: [0]; default: 0; + * enable memory trans of the same channel + */ +#define DMA2D_IN_MEM_TRANS_EN_CH0 (BIT(0)) +#define DMA2D_IN_MEM_TRANS_EN_CH0_M (DMA2D_IN_MEM_TRANS_EN_CH0_V << DMA2D_IN_MEM_TRANS_EN_CH0_S) +#define DMA2D_IN_MEM_TRANS_EN_CH0_V 0x00000001U +#define DMA2D_IN_MEM_TRANS_EN_CH0_S 0 +/** DMA2D_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor + * when accessing SRAM. + */ +#define DMA2D_INDSCR_BURST_EN_CH0 (BIT(2)) +#define DMA2D_INDSCR_BURST_EN_CH0_M (DMA2D_INDSCR_BURST_EN_CH0_V << DMA2D_INDSCR_BURST_EN_CH0_S) +#define DMA2D_INDSCR_BURST_EN_CH0_V 0x00000001U +#define DMA2D_INDSCR_BURST_EN_CH0_S 2 +/** DMA2D_IN_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0; + * When access address space is ecc/aes area, this bit should be set to 1. In this + * case, the start address of square should be 16-bit aligned. The width of square + * multiply byte number of one pixel should be 16-bit aligned. + */ +#define DMA2D_IN_ECC_AES_EN_CH0 (BIT(3)) +#define DMA2D_IN_ECC_AES_EN_CH0_M (DMA2D_IN_ECC_AES_EN_CH0_V << DMA2D_IN_ECC_AES_EN_CH0_S) +#define DMA2D_IN_ECC_AES_EN_CH0_V 0x00000001U +#define DMA2D_IN_ECC_AES_EN_CH0_S 3 +/** DMA2D_IN_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define DMA2D_IN_CHECK_OWNER_CH0 (BIT(4)) +#define DMA2D_IN_CHECK_OWNER_CH0_M (DMA2D_IN_CHECK_OWNER_CH0_V << DMA2D_IN_CHECK_OWNER_CH0_S) +#define DMA2D_IN_CHECK_OWNER_CH0_V 0x00000001U +#define DMA2D_IN_CHECK_OWNER_CH0_S 4 +/** DMA2D_IN_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0; + * reserved + */ +#define DMA2D_IN_LOOP_TEST_CH0 (BIT(5)) +#define DMA2D_IN_LOOP_TEST_CH0_M (DMA2D_IN_LOOP_TEST_CH0_V << DMA2D_IN_LOOP_TEST_CH0_S) +#define DMA2D_IN_LOOP_TEST_CH0_V 0x00000001U +#define DMA2D_IN_LOOP_TEST_CH0_S 5 +/** DMA2D_IN_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0; + * Block size of Rx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 + * bytes 4: 128 bytes + */ +#define DMA2D_IN_MEM_BURST_LENGTH_CH0 0x00000007U +#define DMA2D_IN_MEM_BURST_LENGTH_CH0_M (DMA2D_IN_MEM_BURST_LENGTH_CH0_V << DMA2D_IN_MEM_BURST_LENGTH_CH0_S) +#define DMA2D_IN_MEM_BURST_LENGTH_CH0_V 0x00000007U +#define DMA2D_IN_MEM_BURST_LENGTH_CH0_S 6 +/** DMA2D_IN_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0; + * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: + * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link + * descriptor + */ +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0 0x00000003U +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S) +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V 0x00000003U +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S 9 +/** DMA2D_IN_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0; + * Set this bit to 1 to obtain descriptor from IP port + */ +#define DMA2D_IN_DSCR_PORT_EN_CH0 (BIT(11)) +#define DMA2D_IN_DSCR_PORT_EN_CH0_M (DMA2D_IN_DSCR_PORT_EN_CH0_V << DMA2D_IN_DSCR_PORT_EN_CH0_S) +#define DMA2D_IN_DSCR_PORT_EN_CH0_V 0x00000001U +#define DMA2D_IN_DSCR_PORT_EN_CH0_S 11 +/** DMA2D_IN_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to 1 to make sure AXI write data don't cross the address boundary + * which define by mem_burst_length + */ +#define DMA2D_IN_PAGE_BOUND_EN_CH0 (BIT(12)) +#define DMA2D_IN_PAGE_BOUND_EN_CH0_M (DMA2D_IN_PAGE_BOUND_EN_CH0_V << DMA2D_IN_PAGE_BOUND_EN_CH0_S) +#define DMA2D_IN_PAGE_BOUND_EN_CH0_V 0x00000001U +#define DMA2D_IN_PAGE_BOUND_EN_CH0_S 12 +/** DMA2D_IN_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0; + * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this + * selection + */ +#define DMA2D_IN_REORDER_EN_CH0 (BIT(16)) +#define DMA2D_IN_REORDER_EN_CH0_M (DMA2D_IN_REORDER_EN_CH0_V << DMA2D_IN_REORDER_EN_CH0_S) +#define DMA2D_IN_REORDER_EN_CH0_V 0x00000001U +#define DMA2D_IN_REORDER_EN_CH0_S 16 +/** DMA2D_IN_RST_CH0 : R/W; bitpos: [24]; default: 0; + * Write 1 then write 0 to this bit to reset Rx channel + */ +#define DMA2D_IN_RST_CH0 (BIT(24)) +#define DMA2D_IN_RST_CH0_M (DMA2D_IN_RST_CH0_V << DMA2D_IN_RST_CH0_S) +#define DMA2D_IN_RST_CH0_V 0x00000001U +#define DMA2D_IN_RST_CH0_S 24 +/** DMA2D_IN_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0; + * Write 1 before reset and write 0 after reset + */ +#define DMA2D_IN_CMD_DISABLE_CH0 (BIT(25)) +#define DMA2D_IN_CMD_DISABLE_CH0_M (DMA2D_IN_CMD_DISABLE_CH0_V << DMA2D_IN_CMD_DISABLE_CH0_S) +#define DMA2D_IN_CMD_DISABLE_CH0_V 0x00000001U +#define DMA2D_IN_CMD_DISABLE_CH0_S 25 +/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0; + * Set this bit to 1 to disable arbiter optimum weight function. + */ +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0 (BIT(26)) +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S) +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S 26 + +/** DMA2D_IN_INT_RAW_CH0_REG register + * Raw interrupt status of RX channel 0 + */ +#define DMA2D_IN_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x504) +/** DMA2D_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been transmitted to peripherals for Rx channel 0. + */ +#define DMA2D_IN_DONE_CH0_INT_RAW (BIT(0)) +#define DMA2D_IN_DONE_CH0_INT_RAW_M (DMA2D_IN_DONE_CH0_INT_RAW_V << DMA2D_IN_DONE_CH0_INT_RAW_S) +#define DMA2D_IN_DONE_CH0_INT_RAW_V 0x00000001U +#define DMA2D_IN_DONE_CH0_INT_RAW_S 0 +/** DMA2D_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received and no data error is detected for Rx channel 0. + */ +#define DMA2D_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_M (DMA2D_IN_SUC_EOF_CH0_INT_RAW_V << DMA2D_IN_SUC_EOF_CH0_INT_RAW_S) +#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_S 1 +/** DMA2D_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received and data error is detected + */ +#define DMA2D_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_M (DMA2D_IN_ERR_EOF_CH0_INT_RAW_V << DMA2D_IN_ERR_EOF_CH0_INT_RAW_S) +#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_S 2 +/** DMA2D_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error, + * including owner error, the second and third word error of inlink descriptor for Rx + * channel 0. + */ +#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S) +#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S 3 +/** DMA2D_INFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + */ +#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S) +#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S 4 +/** DMA2D_INFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + */ +#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S) +#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S 5 +/** DMA2D_INFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + */ +#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S) +#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S 6 +/** DMA2D_INFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + */ +#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S) +#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S 7 +/** DMA2D_INFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + */ +#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S) +#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S 8 +/** DMA2D_INFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + */ +#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S) +#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when the last descriptor is done but fifo + * also remain data. + */ +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S) +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S 10 +/** DMA2D_INFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when reorder fifo is overflow. + */ +#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S) +#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S 11 +/** DMA2D_INFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when reorder fifo is underflow. + */ +#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S) +#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S 13 + +/** DMA2D_IN_INT_ENA_CH0_REG register + * Interrupt enable bits of RX channel 0 + */ +#define DMA2D_IN_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x508) +/** DMA2D_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define DMA2D_IN_DONE_CH0_INT_ENA (BIT(0)) +#define DMA2D_IN_DONE_CH0_INT_ENA_M (DMA2D_IN_DONE_CH0_INT_ENA_V << DMA2D_IN_DONE_CH0_INT_ENA_S) +#define DMA2D_IN_DONE_CH0_INT_ENA_V 0x00000001U +#define DMA2D_IN_DONE_CH0_INT_ENA_S 0 +/** DMA2D_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_M (DMA2D_IN_SUC_EOF_CH0_INT_ENA_V << DMA2D_IN_SUC_EOF_CH0_INT_ENA_S) +#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_S 1 +/** DMA2D_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_M (DMA2D_IN_ERR_EOF_CH0_INT_ENA_V << DMA2D_IN_ERR_EOF_CH0_INT_ENA_S) +#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_S 2 +/** DMA2D_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S) +#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S 3 +/** DMA2D_INFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S) +#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S 4 +/** DMA2D_INFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S) +#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S 5 +/** DMA2D_INFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S) +#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S 6 +/** DMA2D_INFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S) +#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S 7 +/** DMA2D_INFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S) +#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S 8 +/** DMA2D_INFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S) +#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S) +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S 10 +/** DMA2D_INFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S) +#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S 11 +/** DMA2D_INFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S) +#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S 13 + +/** DMA2D_IN_INT_ST_CH0_REG register + * Masked interrupt status of RX channel 0 + */ +#define DMA2D_IN_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0x50c) +/** DMA2D_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define DMA2D_IN_DONE_CH0_INT_ST (BIT(0)) +#define DMA2D_IN_DONE_CH0_INT_ST_M (DMA2D_IN_DONE_CH0_INT_ST_V << DMA2D_IN_DONE_CH0_INT_ST_S) +#define DMA2D_IN_DONE_CH0_INT_ST_V 0x00000001U +#define DMA2D_IN_DONE_CH0_INT_ST_S 0 +/** DMA2D_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_SUC_EOF_CH0_INT_ST (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH0_INT_ST_M (DMA2D_IN_SUC_EOF_CH0_INT_ST_V << DMA2D_IN_SUC_EOF_CH0_INT_ST_S) +#define DMA2D_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH0_INT_ST_S 1 +/** DMA2D_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_ERR_EOF_CH0_INT_ST (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH0_INT_ST_M (DMA2D_IN_ERR_EOF_CH0_INT_ST_V << DMA2D_IN_ERR_EOF_CH0_INT_ST_S) +#define DMA2D_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH0_INT_ST_S 2 +/** DMA2D_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_M (DMA2D_IN_DSCR_ERR_CH0_INT_ST_V << DMA2D_IN_DSCR_ERR_CH0_INT_ST_S) +#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_S 3 +/** DMA2D_INFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S) +#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S 4 +/** DMA2D_INFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S) +#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S 5 +/** DMA2D_INFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S) +#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S 6 +/** DMA2D_INFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S) +#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S 7 +/** DMA2D_INFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S) +#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S 8 +/** DMA2D_INFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S) +#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S) +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S 10 +/** DMA2D_INFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S) +#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S 11 +/** DMA2D_INFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S) +#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S 13 + +/** DMA2D_IN_INT_CLR_CH0_REG register + * Interrupt clear bits of RX channel 0 + */ +#define DMA2D_IN_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x510) +/** DMA2D_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define DMA2D_IN_DONE_CH0_INT_CLR (BIT(0)) +#define DMA2D_IN_DONE_CH0_INT_CLR_M (DMA2D_IN_DONE_CH0_INT_CLR_V << DMA2D_IN_DONE_CH0_INT_CLR_S) +#define DMA2D_IN_DONE_CH0_INT_CLR_V 0x00000001U +#define DMA2D_IN_DONE_CH0_INT_CLR_S 0 +/** DMA2D_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_M (DMA2D_IN_SUC_EOF_CH0_INT_CLR_V << DMA2D_IN_SUC_EOF_CH0_INT_CLR_S) +#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_S 1 +/** DMA2D_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_M (DMA2D_IN_ERR_EOF_CH0_INT_CLR_V << DMA2D_IN_ERR_EOF_CH0_INT_CLR_S) +#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_S 2 +/** DMA2D_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S) +#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S 3 +/** DMA2D_INFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S) +#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S 4 +/** DMA2D_INFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S) +#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S 5 +/** DMA2D_INFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S) +#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S 6 +/** DMA2D_INFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S) +#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S 7 +/** DMA2D_INFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S) +#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S 8 +/** DMA2D_INFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S) +#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S) +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S 10 +/** DMA2D_INFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S) +#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S 11 +/** DMA2D_INFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S) +#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S 13 + +/** DMA2D_INFIFO_STATUS_CH0_REG register + * Represents the status of the rx fifo of channel 0 + */ +#define DMA2D_INFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x514) +/** DMA2D_INFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0; + * Rx FIFO full signal for Rx channel. + */ +#define DMA2D_INFIFO_FULL_L2_CH0 (BIT(0)) +#define DMA2D_INFIFO_FULL_L2_CH0_M (DMA2D_INFIFO_FULL_L2_CH0_V << DMA2D_INFIFO_FULL_L2_CH0_S) +#define DMA2D_INFIFO_FULL_L2_CH0_V 0x00000001U +#define DMA2D_INFIFO_FULL_L2_CH0_S 0 +/** DMA2D_INFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1; + * Rx FIFO empty signal for Rx channel. + */ +#define DMA2D_INFIFO_EMPTY_L2_CH0 (BIT(1)) +#define DMA2D_INFIFO_EMPTY_L2_CH0_M (DMA2D_INFIFO_EMPTY_L2_CH0_V << DMA2D_INFIFO_EMPTY_L2_CH0_S) +#define DMA2D_INFIFO_EMPTY_L2_CH0_V 0x00000001U +#define DMA2D_INFIFO_EMPTY_L2_CH0_S 1 +/** DMA2D_INFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel. + */ +#define DMA2D_INFIFO_CNT_L2_CH0 0x0000000FU +#define DMA2D_INFIFO_CNT_L2_CH0_M (DMA2D_INFIFO_CNT_L2_CH0_V << DMA2D_INFIFO_CNT_L2_CH0_S) +#define DMA2D_INFIFO_CNT_L2_CH0_V 0x0000000FU +#define DMA2D_INFIFO_CNT_L2_CH0_S 2 +/** DMA2D_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_1B_CH0 (BIT(7)) +#define DMA2D_IN_REMAIN_UNDER_1B_CH0_M (DMA2D_IN_REMAIN_UNDER_1B_CH0_V << DMA2D_IN_REMAIN_UNDER_1B_CH0_S) +#define DMA2D_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_1B_CH0_S 7 +/** DMA2D_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_2B_CH0 (BIT(8)) +#define DMA2D_IN_REMAIN_UNDER_2B_CH0_M (DMA2D_IN_REMAIN_UNDER_2B_CH0_V << DMA2D_IN_REMAIN_UNDER_2B_CH0_S) +#define DMA2D_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_2B_CH0_S 8 +/** DMA2D_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_3B_CH0 (BIT(9)) +#define DMA2D_IN_REMAIN_UNDER_3B_CH0_M (DMA2D_IN_REMAIN_UNDER_3B_CH0_V << DMA2D_IN_REMAIN_UNDER_3B_CH0_S) +#define DMA2D_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_3B_CH0_S 9 +/** DMA2D_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_4B_CH0 (BIT(10)) +#define DMA2D_IN_REMAIN_UNDER_4B_CH0_M (DMA2D_IN_REMAIN_UNDER_4B_CH0_V << DMA2D_IN_REMAIN_UNDER_4B_CH0_S) +#define DMA2D_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_4B_CH0_S 10 +/** DMA2D_IN_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_5B_CH0 (BIT(11)) +#define DMA2D_IN_REMAIN_UNDER_5B_CH0_M (DMA2D_IN_REMAIN_UNDER_5B_CH0_V << DMA2D_IN_REMAIN_UNDER_5B_CH0_S) +#define DMA2D_IN_REMAIN_UNDER_5B_CH0_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_5B_CH0_S 11 +/** DMA2D_IN_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_6B_CH0 (BIT(12)) +#define DMA2D_IN_REMAIN_UNDER_6B_CH0_M (DMA2D_IN_REMAIN_UNDER_6B_CH0_V << DMA2D_IN_REMAIN_UNDER_6B_CH0_S) +#define DMA2D_IN_REMAIN_UNDER_6B_CH0_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_6B_CH0_S 12 +/** DMA2D_IN_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_7B_CH0 (BIT(13)) +#define DMA2D_IN_REMAIN_UNDER_7B_CH0_M (DMA2D_IN_REMAIN_UNDER_7B_CH0_V << DMA2D_IN_REMAIN_UNDER_7B_CH0_S) +#define DMA2D_IN_REMAIN_UNDER_7B_CH0_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_7B_CH0_S 13 +/** DMA2D_IN_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_8B_CH0 (BIT(14)) +#define DMA2D_IN_REMAIN_UNDER_8B_CH0_M (DMA2D_IN_REMAIN_UNDER_8B_CH0_V << DMA2D_IN_REMAIN_UNDER_8B_CH0_S) +#define DMA2D_IN_REMAIN_UNDER_8B_CH0_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_8B_CH0_S 14 +/** DMA2D_INFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0; + * Rx FIFO full signal for Rx channel 0. + */ +#define DMA2D_INFIFO_FULL_L1_CH0 (BIT(15)) +#define DMA2D_INFIFO_FULL_L1_CH0_M (DMA2D_INFIFO_FULL_L1_CH0_V << DMA2D_INFIFO_FULL_L1_CH0_S) +#define DMA2D_INFIFO_FULL_L1_CH0_V 0x00000001U +#define DMA2D_INFIFO_FULL_L1_CH0_S 15 +/** DMA2D_INFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1; + * Rx FIFO empty signal for Rx channel 0. + */ +#define DMA2D_INFIFO_EMPTY_L1_CH0 (BIT(16)) +#define DMA2D_INFIFO_EMPTY_L1_CH0_M (DMA2D_INFIFO_EMPTY_L1_CH0_V << DMA2D_INFIFO_EMPTY_L1_CH0_S) +#define DMA2D_INFIFO_EMPTY_L1_CH0_V 0x00000001U +#define DMA2D_INFIFO_EMPTY_L1_CH0_S 16 +/** DMA2D_INFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. + */ +#define DMA2D_INFIFO_CNT_L1_CH0 0x0000001FU +#define DMA2D_INFIFO_CNT_L1_CH0_M (DMA2D_INFIFO_CNT_L1_CH0_V << DMA2D_INFIFO_CNT_L1_CH0_S) +#define DMA2D_INFIFO_CNT_L1_CH0_V 0x0000001FU +#define DMA2D_INFIFO_CNT_L1_CH0_S 17 +/** DMA2D_INFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0; + * Rx FIFO full signal for Rx channel 0. + */ +#define DMA2D_INFIFO_FULL_L3_CH0 (BIT(22)) +#define DMA2D_INFIFO_FULL_L3_CH0_M (DMA2D_INFIFO_FULL_L3_CH0_V << DMA2D_INFIFO_FULL_L3_CH0_S) +#define DMA2D_INFIFO_FULL_L3_CH0_V 0x00000001U +#define DMA2D_INFIFO_FULL_L3_CH0_S 22 +/** DMA2D_INFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1; + * Rx FIFO empty signal for Rx channel 0. + */ +#define DMA2D_INFIFO_EMPTY_L3_CH0 (BIT(23)) +#define DMA2D_INFIFO_EMPTY_L3_CH0_M (DMA2D_INFIFO_EMPTY_L3_CH0_V << DMA2D_INFIFO_EMPTY_L3_CH0_S) +#define DMA2D_INFIFO_EMPTY_L3_CH0_V 0x00000001U +#define DMA2D_INFIFO_EMPTY_L3_CH0_S 23 +/** DMA2D_INFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. + */ +#define DMA2D_INFIFO_CNT_L3_CH0 0x0000001FU +#define DMA2D_INFIFO_CNT_L3_CH0_M (DMA2D_INFIFO_CNT_L3_CH0_V << DMA2D_INFIFO_CNT_L3_CH0_S) +#define DMA2D_INFIFO_CNT_L3_CH0_V 0x0000001FU +#define DMA2D_INFIFO_CNT_L3_CH0_S 24 + +/** DMA2D_IN_POP_CH0_REG register + * Configures the rx fifo of channel 0 + */ +#define DMA2D_IN_POP_CH0_REG (DR_REG_DMA2D_BASE + 0x518) +/** DMA2D_INFIFO_RDATA_CH0 : RO; bitpos: [10:0]; default: 1024; + * This register stores the data popping from DMA Rx FIFO. + */ +#define DMA2D_INFIFO_RDATA_CH0 0x000007FFU +#define DMA2D_INFIFO_RDATA_CH0_M (DMA2D_INFIFO_RDATA_CH0_V << DMA2D_INFIFO_RDATA_CH0_S) +#define DMA2D_INFIFO_RDATA_CH0_V 0x000007FFU +#define DMA2D_INFIFO_RDATA_CH0_S 0 +/** DMA2D_INFIFO_POP_CH0 : R/W/SC; bitpos: [11]; default: 0; + * Set this bit to pop data from DMA Rx FIFO. + */ +#define DMA2D_INFIFO_POP_CH0 (BIT(11)) +#define DMA2D_INFIFO_POP_CH0_M (DMA2D_INFIFO_POP_CH0_V << DMA2D_INFIFO_POP_CH0_S) +#define DMA2D_INFIFO_POP_CH0_V 0x00000001U +#define DMA2D_INFIFO_POP_CH0_S 11 + +/** DMA2D_IN_LINK_CONF_CH0_REG register + * Configures the rx descriptor operations of channel 0 + */ +#define DMA2D_IN_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x51c) +/** DMA2D_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1; + * Configure the value of the owner field written back to the inlink descriptor. + * 1: Write back 1. 0: Write back 0. + */ +#define DMA2D_INLINK_AUTO_RET_CH0 (BIT(20)) +#define DMA2D_INLINK_AUTO_RET_CH0_M (DMA2D_INLINK_AUTO_RET_CH0_V << DMA2D_INLINK_AUTO_RET_CH0_S) +#define DMA2D_INLINK_AUTO_RET_CH0_V 0x00000001U +#define DMA2D_INLINK_AUTO_RET_CH0_S 20 +/** DMA2D_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define DMA2D_INLINK_STOP_CH0 (BIT(21)) +#define DMA2D_INLINK_STOP_CH0_M (DMA2D_INLINK_STOP_CH0_V << DMA2D_INLINK_STOP_CH0_S) +#define DMA2D_INLINK_STOP_CH0_V 0x00000001U +#define DMA2D_INLINK_STOP_CH0_S 21 +/** DMA2D_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define DMA2D_INLINK_START_CH0 (BIT(22)) +#define DMA2D_INLINK_START_CH0_M (DMA2D_INLINK_START_CH0_V << DMA2D_INLINK_START_CH0_S) +#define DMA2D_INLINK_START_CH0_V 0x00000001U +#define DMA2D_INLINK_START_CH0_S 22 +/** DMA2D_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define DMA2D_INLINK_RESTART_CH0 (BIT(23)) +#define DMA2D_INLINK_RESTART_CH0_M (DMA2D_INLINK_RESTART_CH0_V << DMA2D_INLINK_RESTART_CH0_S) +#define DMA2D_INLINK_RESTART_CH0_V 0x00000001U +#define DMA2D_INLINK_RESTART_CH0_S 23 +/** DMA2D_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define DMA2D_INLINK_PARK_CH0 (BIT(24)) +#define DMA2D_INLINK_PARK_CH0_M (DMA2D_INLINK_PARK_CH0_V << DMA2D_INLINK_PARK_CH0_S) +#define DMA2D_INLINK_PARK_CH0_V 0x00000001U +#define DMA2D_INLINK_PARK_CH0_S 24 + +/** DMA2D_IN_LINK_ADDR_CH0_REG register + * Configures the rx descriptor address of channel 0 + */ +#define DMA2D_IN_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x520) +/** DMA2D_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; + * This register stores the first inlink descriptor's address. + */ +#define DMA2D_INLINK_ADDR_CH0 0xFFFFFFFFU +#define DMA2D_INLINK_ADDR_CH0_M (DMA2D_INLINK_ADDR_CH0_V << DMA2D_INLINK_ADDR_CH0_S) +#define DMA2D_INLINK_ADDR_CH0_V 0xFFFFFFFFU +#define DMA2D_INLINK_ADDR_CH0_S 0 + +/** DMA2D_IN_STATE_CH0_REG register + * Represents the working status of the rx descriptor of channel 0 + */ +#define DMA2D_IN_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x524) +/** DMA2D_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define DMA2D_INLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define DMA2D_INLINK_DSCR_ADDR_CH0_M (DMA2D_INLINK_DSCR_ADDR_CH0_V << DMA2D_INLINK_DSCR_ADDR_CH0_S) +#define DMA2D_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define DMA2D_INLINK_DSCR_ADDR_CH0_S 0 +/** DMA2D_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define DMA2D_IN_DSCR_STATE_CH0 0x00000003U +#define DMA2D_IN_DSCR_STATE_CH0_M (DMA2D_IN_DSCR_STATE_CH0_V << DMA2D_IN_DSCR_STATE_CH0_S) +#define DMA2D_IN_DSCR_STATE_CH0_V 0x00000003U +#define DMA2D_IN_DSCR_STATE_CH0_S 18 +/** DMA2D_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define DMA2D_IN_STATE_CH0 0x00000007U +#define DMA2D_IN_STATE_CH0_M (DMA2D_IN_STATE_CH0_V << DMA2D_IN_STATE_CH0_S) +#define DMA2D_IN_STATE_CH0_V 0x00000007U +#define DMA2D_IN_STATE_CH0_S 20 +/** DMA2D_IN_RESET_AVAIL_CH0 : RO; bitpos: [23]; default: 1; + * This register indicate that if the channel reset is safety. + */ +#define DMA2D_IN_RESET_AVAIL_CH0 (BIT(23)) +#define DMA2D_IN_RESET_AVAIL_CH0_M (DMA2D_IN_RESET_AVAIL_CH0_V << DMA2D_IN_RESET_AVAIL_CH0_S) +#define DMA2D_IN_RESET_AVAIL_CH0_V 0x00000001U +#define DMA2D_IN_RESET_AVAIL_CH0_S 23 + +/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG register + * Represents the address associated with the inlink descriptor of channel 0 + */ +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x528) +/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S) +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S 0 + +/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG register + * Represents the address associated with the inlink descriptor of channel 0 + */ +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x52c) +/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. + */ +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S) +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S 0 + +/** DMA2D_IN_DSCR_CH0_REG register + * Represents the address associated with the inlink descriptor of channel 0 + */ +#define DMA2D_IN_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x530) +/** DMA2D_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the next inlink descriptor address x. + */ +#define DMA2D_INLINK_DSCR_CH0 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_CH0_M (DMA2D_INLINK_DSCR_CH0_V << DMA2D_INLINK_DSCR_CH0_S) +#define DMA2D_INLINK_DSCR_CH0_V 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_CH0_S 0 + +/** DMA2D_IN_DSCR_BF0_CH0_REG register + * Represents the address associated with the inlink descriptor of channel 0 + */ +#define DMA2D_IN_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x534) +/** DMA2D_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor's next address x-1. + */ +#define DMA2D_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF0_CH0_M (DMA2D_INLINK_DSCR_BF0_CH0_V << DMA2D_INLINK_DSCR_BF0_CH0_S) +#define DMA2D_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF0_CH0_S 0 + +/** DMA2D_IN_DSCR_BF1_CH0_REG register + * Represents the address associated with the inlink descriptor of channel 0 + */ +#define DMA2D_IN_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x538) +/** DMA2D_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor's next address x-2. + */ +#define DMA2D_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF1_CH0_M (DMA2D_INLINK_DSCR_BF1_CH0_V << DMA2D_INLINK_DSCR_BF1_CH0_S) +#define DMA2D_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF1_CH0_S 0 + +/** DMA2D_IN_PERI_SEL_CH0_REG register + * Configures the rx peripheral of channel 0 + */ +#define DMA2D_IN_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x53c) +/** DMA2D_IN_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7; + * This register is used to select peripheral for Rx channel 0: jpeg 1: + * display-1 2: display-2 7: no choose + */ +#define DMA2D_IN_PERI_SEL_CH0 0x00000007U +#define DMA2D_IN_PERI_SEL_CH0_M (DMA2D_IN_PERI_SEL_CH0_V << DMA2D_IN_PERI_SEL_CH0_S) +#define DMA2D_IN_PERI_SEL_CH0_V 0x00000007U +#define DMA2D_IN_PERI_SEL_CH0_S 0 + +/** DMA2D_IN_ARB_CH0_REG register + * Configures the rx arbiter of channel 0 + */ +#define DMA2D_IN_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x540) +/** DMA2D_IN_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1; + * Set the max number of token count of arbiter + */ +#define DMA2D_IN_ARB_TOKEN_NUM_CH0 0x0000000FU +#define DMA2D_IN_ARB_TOKEN_NUM_CH0_M (DMA2D_IN_ARB_TOKEN_NUM_CH0_V << DMA2D_IN_ARB_TOKEN_NUM_CH0_S) +#define DMA2D_IN_ARB_TOKEN_NUM_CH0_V 0x0000000FU +#define DMA2D_IN_ARB_TOKEN_NUM_CH0_S 0 +/** DMA2D_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [7:4]; default: 1; + * Set the priority of channel + */ +#define DMA2D_IN_ARB_PRIORITY_CH0 0x0000000FU +#define DMA2D_IN_ARB_PRIORITY_CH0_M (DMA2D_IN_ARB_PRIORITY_CH0_V << DMA2D_IN_ARB_PRIORITY_CH0_S) +#define DMA2D_IN_ARB_PRIORITY_CH0_V 0x0000000FU +#define DMA2D_IN_ARB_PRIORITY_CH0_S 4 + +/** DMA2D_IN_RO_STATUS_CH0_REG register + * Represents the status of the rx reorder module of channel 0 + */ +#define DMA2D_IN_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x544) +/** DMA2D_INFIFO_RO_CNT_CH0 : RO; bitpos: [4:0]; default: 0; + * The register stores the byte number of the data in color convert Rx FIFO for + * channel 0. + */ +#define DMA2D_INFIFO_RO_CNT_CH0 0x0000001FU +#define DMA2D_INFIFO_RO_CNT_CH0_M (DMA2D_INFIFO_RO_CNT_CH0_V << DMA2D_INFIFO_RO_CNT_CH0_S) +#define DMA2D_INFIFO_RO_CNT_CH0_V 0x0000001FU +#define DMA2D_INFIFO_RO_CNT_CH0_S 0 +/** DMA2D_IN_RO_WR_STATE_CH0 : RO; bitpos: [6:5]; default: 0; + * The register stores the state of read ram of reorder + */ +#define DMA2D_IN_RO_WR_STATE_CH0 0x00000003U +#define DMA2D_IN_RO_WR_STATE_CH0_M (DMA2D_IN_RO_WR_STATE_CH0_V << DMA2D_IN_RO_WR_STATE_CH0_S) +#define DMA2D_IN_RO_WR_STATE_CH0_V 0x00000003U +#define DMA2D_IN_RO_WR_STATE_CH0_S 5 +/** DMA2D_IN_RO_RD_STATE_CH0 : RO; bitpos: [8:7]; default: 0; + * The register stores the state of write ram of reorder + */ +#define DMA2D_IN_RO_RD_STATE_CH0 0x00000003U +#define DMA2D_IN_RO_RD_STATE_CH0_M (DMA2D_IN_RO_RD_STATE_CH0_V << DMA2D_IN_RO_RD_STATE_CH0_S) +#define DMA2D_IN_RO_RD_STATE_CH0_V 0x00000003U +#define DMA2D_IN_RO_RD_STATE_CH0_S 7 +/** DMA2D_IN_PIXEL_BYTE_CH0 : RO; bitpos: [12:9]; default: 0; + * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes + * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes + */ +#define DMA2D_IN_PIXEL_BYTE_CH0 0x0000000FU +#define DMA2D_IN_PIXEL_BYTE_CH0_M (DMA2D_IN_PIXEL_BYTE_CH0_V << DMA2D_IN_PIXEL_BYTE_CH0_S) +#define DMA2D_IN_PIXEL_BYTE_CH0_V 0x0000000FU +#define DMA2D_IN_PIXEL_BYTE_CH0_S 9 +/** DMA2D_IN_BURST_BLOCK_NUM_CH0 : RO; bitpos: [16:13]; default: 0; + * the number of macro blocks contained in a burst of data at RX channel + */ +#define DMA2D_IN_BURST_BLOCK_NUM_CH0 0x0000000FU +#define DMA2D_IN_BURST_BLOCK_NUM_CH0_M (DMA2D_IN_BURST_BLOCK_NUM_CH0_V << DMA2D_IN_BURST_BLOCK_NUM_CH0_S) +#define DMA2D_IN_BURST_BLOCK_NUM_CH0_V 0x0000000FU +#define DMA2D_IN_BURST_BLOCK_NUM_CH0_S 13 + +/** DMA2D_IN_RO_PD_CONF_CH0_REG register + * Configures the rx reorder memory of channel 0 + */ +#define DMA2D_IN_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x548) +/** DMA2D_IN_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0; + * dma reorder ram power down + */ +#define DMA2D_IN_RO_RAM_FORCE_PD_CH0 (BIT(4)) +#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_M (DMA2D_IN_RO_RAM_FORCE_PD_CH0_V << DMA2D_IN_RO_RAM_FORCE_PD_CH0_S) +#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_V 0x00000001U +#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_S 4 +/** DMA2D_IN_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1; + * dma reorder ram power up + */ +#define DMA2D_IN_RO_RAM_FORCE_PU_CH0 (BIT(5)) +#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_M (DMA2D_IN_RO_RAM_FORCE_PU_CH0_V << DMA2D_IN_RO_RAM_FORCE_PU_CH0_S) +#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_V 0x00000001U +#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_S 5 +/** DMA2D_IN_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. + * 0: A gate-clock will be used when accessing the RAM in DMA. + */ +#define DMA2D_IN_RO_RAM_CLK_FO_CH0 (BIT(6)) +#define DMA2D_IN_RO_RAM_CLK_FO_CH0_M (DMA2D_IN_RO_RAM_CLK_FO_CH0_V << DMA2D_IN_RO_RAM_CLK_FO_CH0_S) +#define DMA2D_IN_RO_RAM_CLK_FO_CH0_V 0x00000001U +#define DMA2D_IN_RO_RAM_CLK_FO_CH0_S 6 + +/** DMA2D_IN_COLOR_CONVERT_CH0_REG register + * Configures the Rx color convert of channel 0 + */ +#define DMA2D_IN_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x54c) +/** DMA2D_IN_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; + * Set final color convert process and output type 0: RGB888 to RGB565 1: + * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 + */ +#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0 0x00000003U +#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_M (DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S) +#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V 0x00000003U +#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S 0 +/** DMA2D_IN_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Enable generic color convert module between color input & color output, need to + * configure parameter. + */ +#define DMA2D_IN_COLOR_3B_PROC_EN_CH0 (BIT(2)) +#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_M (DMA2D_IN_COLOR_3B_PROC_EN_CH0_V << DMA2D_IN_COLOR_3B_PROC_EN_CH0_S) +#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_V 0x00000001U +#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_S 2 +/** DMA2D_IN_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7; + * Set first color convert process and input color type 0: YUV422/420 to YUV444 + * 1: YUV422 2: YUV444/420 7: disable color space convert + */ +#define DMA2D_IN_COLOR_INPUT_SEL_CH0 0x00000007U +#define DMA2D_IN_COLOR_INPUT_SEL_CH0_M (DMA2D_IN_COLOR_INPUT_SEL_CH0_V << DMA2D_IN_COLOR_INPUT_SEL_CH0_S) +#define DMA2D_IN_COLOR_INPUT_SEL_CH0_V 0x00000007U +#define DMA2D_IN_COLOR_INPUT_SEL_CH0_S 3 + +/** DMA2D_IN_SCRAMBLE_CH0_REG register + * Configures the rx scramble of channel 0 + */ +#define DMA2D_IN_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x550) +/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0; + * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : + * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 + */ +#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0 0x00000007U +#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_M (DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S) +#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V 0x00000007U +#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S 0 +/** DMA2D_IN_SCRAMBLE_SEL_POST_CH0 : R/W; bitpos: [5:3]; default: 0; + * Scramble data after color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : BYTE1-0-2 + * 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 + */ +#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0 0x00000007U +#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_M (DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S) +#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V 0x00000007U +#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S 3 + +/** DMA2D_IN_COLOR_PARAM0_CH0_REG register + * Configures the rx color convert parameter of channel 0 + */ +#define DMA2D_IN_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x554) +/** DMA2D_IN_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298; + * Set first 2 parameter of most significant byte of pending 3 bytes + */ +#define DMA2D_IN_COLOR_PARAM_H0_CH0 0x001FFFFFU +#define DMA2D_IN_COLOR_PARAM_H0_CH0_M (DMA2D_IN_COLOR_PARAM_H0_CH0_V << DMA2D_IN_COLOR_PARAM_H0_CH0_S) +#define DMA2D_IN_COLOR_PARAM_H0_CH0_V 0x001FFFFFU +#define DMA2D_IN_COLOR_PARAM_H0_CH0_S 0 + +/** DMA2D_IN_COLOR_PARAM1_CH0_REG register + * Configures the rx color convert parameter of channel 0 + */ +#define DMA2D_IN_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x558) +/** DMA2D_IN_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121; + * Set last 2 parameter of most significant byte of pending 3 bytes + */ +#define DMA2D_IN_COLOR_PARAM_H1_CH0 0x0FFFFFFFU +#define DMA2D_IN_COLOR_PARAM_H1_CH0_M (DMA2D_IN_COLOR_PARAM_H1_CH0_V << DMA2D_IN_COLOR_PARAM_H1_CH0_S) +#define DMA2D_IN_COLOR_PARAM_H1_CH0_V 0x0FFFFFFFU +#define DMA2D_IN_COLOR_PARAM_H1_CH0_S 0 + +/** DMA2D_IN_COLOR_PARAM2_CH0_REG register + * Configures the rx color convert parameter of channel 0 + */ +#define DMA2D_IN_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x55c) +/** DMA2D_IN_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050; + * Set first 2 parameter of midium significant byte of pending 3 bytes + */ +#define DMA2D_IN_COLOR_PARAM_M0_CH0 0x001FFFFFU +#define DMA2D_IN_COLOR_PARAM_M0_CH0_M (DMA2D_IN_COLOR_PARAM_M0_CH0_V << DMA2D_IN_COLOR_PARAM_M0_CH0_S) +#define DMA2D_IN_COLOR_PARAM_M0_CH0_V 0x001FFFFFU +#define DMA2D_IN_COLOR_PARAM_M0_CH0_S 0 + +/** DMA2D_IN_COLOR_PARAM3_CH0_REG register + * Configures the rx color convert parameter of channel 0 + */ +#define DMA2D_IN_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x560) +/** DMA2D_IN_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784; + * Set last 2 parameter of midium significant byte of pending 3 bytes + */ +#define DMA2D_IN_COLOR_PARAM_M1_CH0 0x0FFFFFFFU +#define DMA2D_IN_COLOR_PARAM_M1_CH0_M (DMA2D_IN_COLOR_PARAM_M1_CH0_V << DMA2D_IN_COLOR_PARAM_M1_CH0_S) +#define DMA2D_IN_COLOR_PARAM_M1_CH0_V 0x0FFFFFFFU +#define DMA2D_IN_COLOR_PARAM_M1_CH0_S 0 + +/** DMA2D_IN_COLOR_PARAM4_CH0_REG register + * Configures the rx color convert parameter of channel 0 + */ +#define DMA2D_IN_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x564) +/** DMA2D_IN_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682; + * Set first 2 parameter of least significant byte of pending 3 bytes + */ +#define DMA2D_IN_COLOR_PARAM_L0_CH0 0x001FFFFFU +#define DMA2D_IN_COLOR_PARAM_L0_CH0_M (DMA2D_IN_COLOR_PARAM_L0_CH0_V << DMA2D_IN_COLOR_PARAM_L0_CH0_S) +#define DMA2D_IN_COLOR_PARAM_L0_CH0_V 0x001FFFFFU +#define DMA2D_IN_COLOR_PARAM_L0_CH0_S 0 + +/** DMA2D_IN_COLOR_PARAM5_CH0_REG register + * Configures the rx color convert parameter of channel 0 + */ +#define DMA2D_IN_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x568) +/** DMA2D_IN_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392; + * Set last 2 parameter of least significant byte of pending 3 bytes + */ +#define DMA2D_IN_COLOR_PARAM_L1_CH0 0x0FFFFFFFU +#define DMA2D_IN_COLOR_PARAM_L1_CH0_M (DMA2D_IN_COLOR_PARAM_L1_CH0_V << DMA2D_IN_COLOR_PARAM_L1_CH0_S) +#define DMA2D_IN_COLOR_PARAM_L1_CH0_V 0x0FFFFFFFU +#define DMA2D_IN_COLOR_PARAM_L1_CH0_S 0 + +/** DMA2D_IN_ETM_CONF_CH0_REG register + * Configures the rx etm of channel 0 + */ +#define DMA2D_IN_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x56c) +/** DMA2D_IN_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0; + * Configures the enable of the etm function, 1 is enable. + */ +#define DMA2D_IN_ETM_EN_CH0 (BIT(0)) +#define DMA2D_IN_ETM_EN_CH0_M (DMA2D_IN_ETM_EN_CH0_V << DMA2D_IN_ETM_EN_CH0_S) +#define DMA2D_IN_ETM_EN_CH0_V 0x00000001U +#define DMA2D_IN_ETM_EN_CH0_S 0 +/** DMA2D_IN_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0; + * Configures the enable of the descriptors loop etm function, 1 is enable. + */ +#define DMA2D_IN_ETM_LOOP_EN_CH0 (BIT(1)) +#define DMA2D_IN_ETM_LOOP_EN_CH0_M (DMA2D_IN_ETM_LOOP_EN_CH0_V << DMA2D_IN_ETM_LOOP_EN_CH0_S) +#define DMA2D_IN_ETM_LOOP_EN_CH0_V 0x00000001U +#define DMA2D_IN_ETM_LOOP_EN_CH0_S 1 +/** DMA2D_IN_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1; + * Configures the maximum number of cacheable descriptors. + */ +#define DMA2D_IN_DSCR_TASK_MAK_CH0 0x00000003U +#define DMA2D_IN_DSCR_TASK_MAK_CH0_M (DMA2D_IN_DSCR_TASK_MAK_CH0_V << DMA2D_IN_DSCR_TASK_MAK_CH0_S) +#define DMA2D_IN_DSCR_TASK_MAK_CH0_V 0x00000003U +#define DMA2D_IN_DSCR_TASK_MAK_CH0_S 2 + +/** DMA2D_IN_CONF0_CH1_REG register + * Configures the rx direction of channel 1 + */ +#define DMA2D_IN_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x600) +/** DMA2D_IN_MEM_TRANS_EN_CH1 : R/W; bitpos: [0]; default: 0; + * enable memory trans of the same channel + */ +#define DMA2D_IN_MEM_TRANS_EN_CH1 (BIT(0)) +#define DMA2D_IN_MEM_TRANS_EN_CH1_M (DMA2D_IN_MEM_TRANS_EN_CH1_V << DMA2D_IN_MEM_TRANS_EN_CH1_S) +#define DMA2D_IN_MEM_TRANS_EN_CH1_V 0x00000001U +#define DMA2D_IN_MEM_TRANS_EN_CH1_S 0 +/** DMA2D_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor + * when accessing SRAM. + */ +#define DMA2D_INDSCR_BURST_EN_CH1 (BIT(2)) +#define DMA2D_INDSCR_BURST_EN_CH1_M (DMA2D_INDSCR_BURST_EN_CH1_V << DMA2D_INDSCR_BURST_EN_CH1_S) +#define DMA2D_INDSCR_BURST_EN_CH1_V 0x00000001U +#define DMA2D_INDSCR_BURST_EN_CH1_S 2 +/** DMA2D_IN_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0; + * When access address space is ecc/aes area, this bit should be set to 1. In this + * case, the start address of square should be 16-bit aligned. The width of square + * multiply byte number of one pixel should be 16-bit aligned. + */ +#define DMA2D_IN_ECC_AES_EN_CH1 (BIT(3)) +#define DMA2D_IN_ECC_AES_EN_CH1_M (DMA2D_IN_ECC_AES_EN_CH1_V << DMA2D_IN_ECC_AES_EN_CH1_S) +#define DMA2D_IN_ECC_AES_EN_CH1_V 0x00000001U +#define DMA2D_IN_ECC_AES_EN_CH1_S 3 +/** DMA2D_IN_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define DMA2D_IN_CHECK_OWNER_CH1 (BIT(4)) +#define DMA2D_IN_CHECK_OWNER_CH1_M (DMA2D_IN_CHECK_OWNER_CH1_V << DMA2D_IN_CHECK_OWNER_CH1_S) +#define DMA2D_IN_CHECK_OWNER_CH1_V 0x00000001U +#define DMA2D_IN_CHECK_OWNER_CH1_S 4 +/** DMA2D_IN_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0; + * reserved + */ +#define DMA2D_IN_LOOP_TEST_CH1 (BIT(5)) +#define DMA2D_IN_LOOP_TEST_CH1_M (DMA2D_IN_LOOP_TEST_CH1_V << DMA2D_IN_LOOP_TEST_CH1_S) +#define DMA2D_IN_LOOP_TEST_CH1_V 0x00000001U +#define DMA2D_IN_LOOP_TEST_CH1_S 5 +/** DMA2D_IN_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0; + * Block size of Rx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 + * bytes 4: 128 bytes + */ +#define DMA2D_IN_MEM_BURST_LENGTH_CH1 0x00000007U +#define DMA2D_IN_MEM_BURST_LENGTH_CH1_M (DMA2D_IN_MEM_BURST_LENGTH_CH1_V << DMA2D_IN_MEM_BURST_LENGTH_CH1_S) +#define DMA2D_IN_MEM_BURST_LENGTH_CH1_V 0x00000007U +#define DMA2D_IN_MEM_BURST_LENGTH_CH1_S 6 +/** DMA2D_IN_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0; + * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: + * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link + * descriptor + */ +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1 0x00000003U +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S) +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V 0x00000003U +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S 9 +/** DMA2D_IN_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0; + * Set this bit to 1 to obtain descriptor from IP port + */ +#define DMA2D_IN_DSCR_PORT_EN_CH1 (BIT(11)) +#define DMA2D_IN_DSCR_PORT_EN_CH1_M (DMA2D_IN_DSCR_PORT_EN_CH1_V << DMA2D_IN_DSCR_PORT_EN_CH1_S) +#define DMA2D_IN_DSCR_PORT_EN_CH1_V 0x00000001U +#define DMA2D_IN_DSCR_PORT_EN_CH1_S 11 +/** DMA2D_IN_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to 1 to make sure AXI write data don't cross the address boundary + * which define by mem_burst_length + */ +#define DMA2D_IN_PAGE_BOUND_EN_CH1 (BIT(12)) +#define DMA2D_IN_PAGE_BOUND_EN_CH1_M (DMA2D_IN_PAGE_BOUND_EN_CH1_V << DMA2D_IN_PAGE_BOUND_EN_CH1_S) +#define DMA2D_IN_PAGE_BOUND_EN_CH1_V 0x00000001U +#define DMA2D_IN_PAGE_BOUND_EN_CH1_S 12 +/** DMA2D_IN_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0; + * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this + * selection + */ +#define DMA2D_IN_REORDER_EN_CH1 (BIT(16)) +#define DMA2D_IN_REORDER_EN_CH1_M (DMA2D_IN_REORDER_EN_CH1_V << DMA2D_IN_REORDER_EN_CH1_S) +#define DMA2D_IN_REORDER_EN_CH1_V 0x00000001U +#define DMA2D_IN_REORDER_EN_CH1_S 16 +/** DMA2D_IN_RST_CH1 : R/W; bitpos: [24]; default: 0; + * Write 1 then write 0 to this bit to reset Rx channel + */ +#define DMA2D_IN_RST_CH1 (BIT(24)) +#define DMA2D_IN_RST_CH1_M (DMA2D_IN_RST_CH1_V << DMA2D_IN_RST_CH1_S) +#define DMA2D_IN_RST_CH1_V 0x00000001U +#define DMA2D_IN_RST_CH1_S 24 +/** DMA2D_IN_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0; + * Write 1 before reset and write 0 after reset + */ +#define DMA2D_IN_CMD_DISABLE_CH1 (BIT(25)) +#define DMA2D_IN_CMD_DISABLE_CH1_M (DMA2D_IN_CMD_DISABLE_CH1_V << DMA2D_IN_CMD_DISABLE_CH1_S) +#define DMA2D_IN_CMD_DISABLE_CH1_V 0x00000001U +#define DMA2D_IN_CMD_DISABLE_CH1_S 25 +/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0; + * Set this bit to 1 to disable arbiter optimum weight function. + */ +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1 (BIT(26)) +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S) +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S 26 + +/** DMA2D_IN_INT_RAW_CH1_REG register + * Raw interrupt status of RX channel 1 + */ +#define DMA2D_IN_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x604) +/** DMA2D_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been transmitted to peripherals for Rx channel 0. + */ +#define DMA2D_IN_DONE_CH1_INT_RAW (BIT(0)) +#define DMA2D_IN_DONE_CH1_INT_RAW_M (DMA2D_IN_DONE_CH1_INT_RAW_V << DMA2D_IN_DONE_CH1_INT_RAW_S) +#define DMA2D_IN_DONE_CH1_INT_RAW_V 0x00000001U +#define DMA2D_IN_DONE_CH1_INT_RAW_S 0 +/** DMA2D_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received and no data error is detected for Rx channel 0. + */ +#define DMA2D_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_M (DMA2D_IN_SUC_EOF_CH1_INT_RAW_V << DMA2D_IN_SUC_EOF_CH1_INT_RAW_S) +#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_S 1 +/** DMA2D_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received and data error is detected + */ +#define DMA2D_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_M (DMA2D_IN_ERR_EOF_CH1_INT_RAW_V << DMA2D_IN_ERR_EOF_CH1_INT_RAW_S) +#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_S 2 +/** DMA2D_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error, + * including owner error, the second and third word error of inlink descriptor for Rx + * channel 0. + */ +#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S) +#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S 3 +/** DMA2D_INFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + */ +#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S) +#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S 4 +/** DMA2D_INFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + */ +#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S) +#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S 5 +/** DMA2D_INFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + */ +#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S) +#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S 6 +/** DMA2D_INFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + */ +#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S) +#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S 7 +/** DMA2D_INFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + */ +#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S) +#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S 8 +/** DMA2D_INFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + */ +#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S) +#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when the last descriptor is done but fifo + * also remain data. + */ +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S) +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S 10 +/** DMA2D_INFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when reorder fifo is overflow. + */ +#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S) +#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S 11 +/** DMA2D_INFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when reorder fifo is underflow. + */ +#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S) +#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S 13 + +/** DMA2D_IN_INT_ENA_CH1_REG register + * Interrupt enable bits of RX channel 1 + */ +#define DMA2D_IN_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x608) +/** DMA2D_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define DMA2D_IN_DONE_CH1_INT_ENA (BIT(0)) +#define DMA2D_IN_DONE_CH1_INT_ENA_M (DMA2D_IN_DONE_CH1_INT_ENA_V << DMA2D_IN_DONE_CH1_INT_ENA_S) +#define DMA2D_IN_DONE_CH1_INT_ENA_V 0x00000001U +#define DMA2D_IN_DONE_CH1_INT_ENA_S 0 +/** DMA2D_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_M (DMA2D_IN_SUC_EOF_CH1_INT_ENA_V << DMA2D_IN_SUC_EOF_CH1_INT_ENA_S) +#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_S 1 +/** DMA2D_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_M (DMA2D_IN_ERR_EOF_CH1_INT_ENA_V << DMA2D_IN_ERR_EOF_CH1_INT_ENA_S) +#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_S 2 +/** DMA2D_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S) +#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S 3 +/** DMA2D_INFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S) +#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S 4 +/** DMA2D_INFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S) +#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S 5 +/** DMA2D_INFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S) +#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S 6 +/** DMA2D_INFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S) +#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S 7 +/** DMA2D_INFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S) +#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S 8 +/** DMA2D_INFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S) +#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S) +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S 10 +/** DMA2D_INFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S) +#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S 11 +/** DMA2D_INFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S) +#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S 13 + +/** DMA2D_IN_INT_ST_CH1_REG register + * Masked interrupt status of RX channel 1 + */ +#define DMA2D_IN_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x60c) +/** DMA2D_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define DMA2D_IN_DONE_CH1_INT_ST (BIT(0)) +#define DMA2D_IN_DONE_CH1_INT_ST_M (DMA2D_IN_DONE_CH1_INT_ST_V << DMA2D_IN_DONE_CH1_INT_ST_S) +#define DMA2D_IN_DONE_CH1_INT_ST_V 0x00000001U +#define DMA2D_IN_DONE_CH1_INT_ST_S 0 +/** DMA2D_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_SUC_EOF_CH1_INT_ST (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH1_INT_ST_M (DMA2D_IN_SUC_EOF_CH1_INT_ST_V << DMA2D_IN_SUC_EOF_CH1_INT_ST_S) +#define DMA2D_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH1_INT_ST_S 1 +/** DMA2D_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_ERR_EOF_CH1_INT_ST (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH1_INT_ST_M (DMA2D_IN_ERR_EOF_CH1_INT_ST_V << DMA2D_IN_ERR_EOF_CH1_INT_ST_S) +#define DMA2D_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH1_INT_ST_S 2 +/** DMA2D_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_M (DMA2D_IN_DSCR_ERR_CH1_INT_ST_V << DMA2D_IN_DSCR_ERR_CH1_INT_ST_S) +#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_S 3 +/** DMA2D_INFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S) +#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S 4 +/** DMA2D_INFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S) +#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S 5 +/** DMA2D_INFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S) +#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S 6 +/** DMA2D_INFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S) +#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S 7 +/** DMA2D_INFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S) +#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S 8 +/** DMA2D_INFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S) +#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S) +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S 10 +/** DMA2D_INFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S) +#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S 11 +/** DMA2D_INFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S) +#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S 13 + +/** DMA2D_IN_INT_CLR_CH1_REG register + * Interrupt clear bits of RX channel 1 + */ +#define DMA2D_IN_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x610) +/** DMA2D_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define DMA2D_IN_DONE_CH1_INT_CLR (BIT(0)) +#define DMA2D_IN_DONE_CH1_INT_CLR_M (DMA2D_IN_DONE_CH1_INT_CLR_V << DMA2D_IN_DONE_CH1_INT_CLR_S) +#define DMA2D_IN_DONE_CH1_INT_CLR_V 0x00000001U +#define DMA2D_IN_DONE_CH1_INT_CLR_S 0 +/** DMA2D_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_M (DMA2D_IN_SUC_EOF_CH1_INT_CLR_V << DMA2D_IN_SUC_EOF_CH1_INT_CLR_S) +#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_S 1 +/** DMA2D_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_M (DMA2D_IN_ERR_EOF_CH1_INT_CLR_V << DMA2D_IN_ERR_EOF_CH1_INT_CLR_S) +#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_S 2 +/** DMA2D_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S) +#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S 3 +/** DMA2D_INFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S) +#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S 4 +/** DMA2D_INFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S) +#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S 5 +/** DMA2D_INFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S) +#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S 6 +/** DMA2D_INFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S) +#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S 7 +/** DMA2D_INFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S) +#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S 8 +/** DMA2D_INFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S) +#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S) +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S 10 +/** DMA2D_INFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S) +#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S 11 +/** DMA2D_INFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S) +#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S 13 + +/** DMA2D_INFIFO_STATUS_CH1_REG register + * Represents the status of the rx fifo of channel 1 + */ +#define DMA2D_INFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x614) +/** DMA2D_INFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0; + * Rx FIFO full signal for Rx channel. + */ +#define DMA2D_INFIFO_FULL_L2_CH1 (BIT(0)) +#define DMA2D_INFIFO_FULL_L2_CH1_M (DMA2D_INFIFO_FULL_L2_CH1_V << DMA2D_INFIFO_FULL_L2_CH1_S) +#define DMA2D_INFIFO_FULL_L2_CH1_V 0x00000001U +#define DMA2D_INFIFO_FULL_L2_CH1_S 0 +/** DMA2D_INFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1; + * Rx FIFO empty signal for Rx channel. + */ +#define DMA2D_INFIFO_EMPTY_L2_CH1 (BIT(1)) +#define DMA2D_INFIFO_EMPTY_L2_CH1_M (DMA2D_INFIFO_EMPTY_L2_CH1_V << DMA2D_INFIFO_EMPTY_L2_CH1_S) +#define DMA2D_INFIFO_EMPTY_L2_CH1_V 0x00000001U +#define DMA2D_INFIFO_EMPTY_L2_CH1_S 1 +/** DMA2D_INFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel. + */ +#define DMA2D_INFIFO_CNT_L2_CH1 0x0000000FU +#define DMA2D_INFIFO_CNT_L2_CH1_M (DMA2D_INFIFO_CNT_L2_CH1_V << DMA2D_INFIFO_CNT_L2_CH1_S) +#define DMA2D_INFIFO_CNT_L2_CH1_V 0x0000000FU +#define DMA2D_INFIFO_CNT_L2_CH1_S 2 +/** DMA2D_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_1B_CH1 (BIT(7)) +#define DMA2D_IN_REMAIN_UNDER_1B_CH1_M (DMA2D_IN_REMAIN_UNDER_1B_CH1_V << DMA2D_IN_REMAIN_UNDER_1B_CH1_S) +#define DMA2D_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_1B_CH1_S 7 +/** DMA2D_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_2B_CH1 (BIT(8)) +#define DMA2D_IN_REMAIN_UNDER_2B_CH1_M (DMA2D_IN_REMAIN_UNDER_2B_CH1_V << DMA2D_IN_REMAIN_UNDER_2B_CH1_S) +#define DMA2D_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_2B_CH1_S 8 +/** DMA2D_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_3B_CH1 (BIT(9)) +#define DMA2D_IN_REMAIN_UNDER_3B_CH1_M (DMA2D_IN_REMAIN_UNDER_3B_CH1_V << DMA2D_IN_REMAIN_UNDER_3B_CH1_S) +#define DMA2D_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_3B_CH1_S 9 +/** DMA2D_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_4B_CH1 (BIT(10)) +#define DMA2D_IN_REMAIN_UNDER_4B_CH1_M (DMA2D_IN_REMAIN_UNDER_4B_CH1_V << DMA2D_IN_REMAIN_UNDER_4B_CH1_S) +#define DMA2D_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_4B_CH1_S 10 +/** DMA2D_IN_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_5B_CH1 (BIT(11)) +#define DMA2D_IN_REMAIN_UNDER_5B_CH1_M (DMA2D_IN_REMAIN_UNDER_5B_CH1_V << DMA2D_IN_REMAIN_UNDER_5B_CH1_S) +#define DMA2D_IN_REMAIN_UNDER_5B_CH1_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_5B_CH1_S 11 +/** DMA2D_IN_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_6B_CH1 (BIT(12)) +#define DMA2D_IN_REMAIN_UNDER_6B_CH1_M (DMA2D_IN_REMAIN_UNDER_6B_CH1_V << DMA2D_IN_REMAIN_UNDER_6B_CH1_S) +#define DMA2D_IN_REMAIN_UNDER_6B_CH1_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_6B_CH1_S 12 +/** DMA2D_IN_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_7B_CH1 (BIT(13)) +#define DMA2D_IN_REMAIN_UNDER_7B_CH1_M (DMA2D_IN_REMAIN_UNDER_7B_CH1_V << DMA2D_IN_REMAIN_UNDER_7B_CH1_S) +#define DMA2D_IN_REMAIN_UNDER_7B_CH1_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_7B_CH1_S 13 +/** DMA2D_IN_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_8B_CH1 (BIT(14)) +#define DMA2D_IN_REMAIN_UNDER_8B_CH1_M (DMA2D_IN_REMAIN_UNDER_8B_CH1_V << DMA2D_IN_REMAIN_UNDER_8B_CH1_S) +#define DMA2D_IN_REMAIN_UNDER_8B_CH1_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_8B_CH1_S 14 +/** DMA2D_INFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0; + * Rx FIFO full signal for Rx channel 0. + */ +#define DMA2D_INFIFO_FULL_L1_CH1 (BIT(15)) +#define DMA2D_INFIFO_FULL_L1_CH1_M (DMA2D_INFIFO_FULL_L1_CH1_V << DMA2D_INFIFO_FULL_L1_CH1_S) +#define DMA2D_INFIFO_FULL_L1_CH1_V 0x00000001U +#define DMA2D_INFIFO_FULL_L1_CH1_S 15 +/** DMA2D_INFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1; + * Rx FIFO empty signal for Rx channel 0. + */ +#define DMA2D_INFIFO_EMPTY_L1_CH1 (BIT(16)) +#define DMA2D_INFIFO_EMPTY_L1_CH1_M (DMA2D_INFIFO_EMPTY_L1_CH1_V << DMA2D_INFIFO_EMPTY_L1_CH1_S) +#define DMA2D_INFIFO_EMPTY_L1_CH1_V 0x00000001U +#define DMA2D_INFIFO_EMPTY_L1_CH1_S 16 +/** DMA2D_INFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. + */ +#define DMA2D_INFIFO_CNT_L1_CH1 0x0000001FU +#define DMA2D_INFIFO_CNT_L1_CH1_M (DMA2D_INFIFO_CNT_L1_CH1_V << DMA2D_INFIFO_CNT_L1_CH1_S) +#define DMA2D_INFIFO_CNT_L1_CH1_V 0x0000001FU +#define DMA2D_INFIFO_CNT_L1_CH1_S 17 +/** DMA2D_INFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0; + * Rx FIFO full signal for Rx channel 0. + */ +#define DMA2D_INFIFO_FULL_L3_CH1 (BIT(22)) +#define DMA2D_INFIFO_FULL_L3_CH1_M (DMA2D_INFIFO_FULL_L3_CH1_V << DMA2D_INFIFO_FULL_L3_CH1_S) +#define DMA2D_INFIFO_FULL_L3_CH1_V 0x00000001U +#define DMA2D_INFIFO_FULL_L3_CH1_S 22 +/** DMA2D_INFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1; + * Rx FIFO empty signal for Rx channel 0. + */ +#define DMA2D_INFIFO_EMPTY_L3_CH1 (BIT(23)) +#define DMA2D_INFIFO_EMPTY_L3_CH1_M (DMA2D_INFIFO_EMPTY_L3_CH1_V << DMA2D_INFIFO_EMPTY_L3_CH1_S) +#define DMA2D_INFIFO_EMPTY_L3_CH1_V 0x00000001U +#define DMA2D_INFIFO_EMPTY_L3_CH1_S 23 +/** DMA2D_INFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. + */ +#define DMA2D_INFIFO_CNT_L3_CH1 0x0000001FU +#define DMA2D_INFIFO_CNT_L3_CH1_M (DMA2D_INFIFO_CNT_L3_CH1_V << DMA2D_INFIFO_CNT_L3_CH1_S) +#define DMA2D_INFIFO_CNT_L3_CH1_V 0x0000001FU +#define DMA2D_INFIFO_CNT_L3_CH1_S 24 + +/** DMA2D_IN_POP_CH1_REG register + * Configures the rx fifo of channel 1 + */ +#define DMA2D_IN_POP_CH1_REG (DR_REG_DMA2D_BASE + 0x618) +/** DMA2D_INFIFO_RDATA_CH1 : RO; bitpos: [10:0]; default: 1024; + * This register stores the data popping from DMA Rx FIFO. + */ +#define DMA2D_INFIFO_RDATA_CH1 0x000007FFU +#define DMA2D_INFIFO_RDATA_CH1_M (DMA2D_INFIFO_RDATA_CH1_V << DMA2D_INFIFO_RDATA_CH1_S) +#define DMA2D_INFIFO_RDATA_CH1_V 0x000007FFU +#define DMA2D_INFIFO_RDATA_CH1_S 0 +/** DMA2D_INFIFO_POP_CH1 : R/W/SC; bitpos: [11]; default: 0; + * Set this bit to pop data from DMA Rx FIFO. + */ +#define DMA2D_INFIFO_POP_CH1 (BIT(11)) +#define DMA2D_INFIFO_POP_CH1_M (DMA2D_INFIFO_POP_CH1_V << DMA2D_INFIFO_POP_CH1_S) +#define DMA2D_INFIFO_POP_CH1_V 0x00000001U +#define DMA2D_INFIFO_POP_CH1_S 11 + +/** DMA2D_IN_LINK_CONF_CH1_REG register + * Configures the rx descriptor operations of channel 1 + */ +#define DMA2D_IN_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x61c) +/** DMA2D_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; + * Configure the value of the owner field written back to the inlink descriptor. + * 1: Write back 1. 0: Write back 0. + */ +#define DMA2D_INLINK_AUTO_RET_CH1 (BIT(20)) +#define DMA2D_INLINK_AUTO_RET_CH1_M (DMA2D_INLINK_AUTO_RET_CH1_V << DMA2D_INLINK_AUTO_RET_CH1_S) +#define DMA2D_INLINK_AUTO_RET_CH1_V 0x00000001U +#define DMA2D_INLINK_AUTO_RET_CH1_S 20 +/** DMA2D_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define DMA2D_INLINK_STOP_CH1 (BIT(21)) +#define DMA2D_INLINK_STOP_CH1_M (DMA2D_INLINK_STOP_CH1_V << DMA2D_INLINK_STOP_CH1_S) +#define DMA2D_INLINK_STOP_CH1_V 0x00000001U +#define DMA2D_INLINK_STOP_CH1_S 21 +/** DMA2D_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define DMA2D_INLINK_START_CH1 (BIT(22)) +#define DMA2D_INLINK_START_CH1_M (DMA2D_INLINK_START_CH1_V << DMA2D_INLINK_START_CH1_S) +#define DMA2D_INLINK_START_CH1_V 0x00000001U +#define DMA2D_INLINK_START_CH1_S 22 +/** DMA2D_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define DMA2D_INLINK_RESTART_CH1 (BIT(23)) +#define DMA2D_INLINK_RESTART_CH1_M (DMA2D_INLINK_RESTART_CH1_V << DMA2D_INLINK_RESTART_CH1_S) +#define DMA2D_INLINK_RESTART_CH1_V 0x00000001U +#define DMA2D_INLINK_RESTART_CH1_S 23 +/** DMA2D_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define DMA2D_INLINK_PARK_CH1 (BIT(24)) +#define DMA2D_INLINK_PARK_CH1_M (DMA2D_INLINK_PARK_CH1_V << DMA2D_INLINK_PARK_CH1_S) +#define DMA2D_INLINK_PARK_CH1_V 0x00000001U +#define DMA2D_INLINK_PARK_CH1_S 24 + +/** DMA2D_IN_LINK_ADDR_CH1_REG register + * Configures the rx descriptor address of channel 1 + */ +#define DMA2D_IN_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x620) +/** DMA2D_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; + * This register stores the first inlink descriptor's address. + */ +#define DMA2D_INLINK_ADDR_CH1 0xFFFFFFFFU +#define DMA2D_INLINK_ADDR_CH1_M (DMA2D_INLINK_ADDR_CH1_V << DMA2D_INLINK_ADDR_CH1_S) +#define DMA2D_INLINK_ADDR_CH1_V 0xFFFFFFFFU +#define DMA2D_INLINK_ADDR_CH1_S 0 + +/** DMA2D_IN_STATE_CH1_REG register + * Represents the working status of the rx descriptor of channel 1 + */ +#define DMA2D_IN_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x624) +/** DMA2D_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define DMA2D_INLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define DMA2D_INLINK_DSCR_ADDR_CH1_M (DMA2D_INLINK_DSCR_ADDR_CH1_V << DMA2D_INLINK_DSCR_ADDR_CH1_S) +#define DMA2D_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define DMA2D_INLINK_DSCR_ADDR_CH1_S 0 +/** DMA2D_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define DMA2D_IN_DSCR_STATE_CH1 0x00000003U +#define DMA2D_IN_DSCR_STATE_CH1_M (DMA2D_IN_DSCR_STATE_CH1_V << DMA2D_IN_DSCR_STATE_CH1_S) +#define DMA2D_IN_DSCR_STATE_CH1_V 0x00000003U +#define DMA2D_IN_DSCR_STATE_CH1_S 18 +/** DMA2D_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define DMA2D_IN_STATE_CH1 0x00000007U +#define DMA2D_IN_STATE_CH1_M (DMA2D_IN_STATE_CH1_V << DMA2D_IN_STATE_CH1_S) +#define DMA2D_IN_STATE_CH1_V 0x00000007U +#define DMA2D_IN_STATE_CH1_S 20 +/** DMA2D_IN_RESET_AVAIL_CH1 : RO; bitpos: [23]; default: 1; + * This register indicate that if the channel reset is safety. + */ +#define DMA2D_IN_RESET_AVAIL_CH1 (BIT(23)) +#define DMA2D_IN_RESET_AVAIL_CH1_M (DMA2D_IN_RESET_AVAIL_CH1_V << DMA2D_IN_RESET_AVAIL_CH1_S) +#define DMA2D_IN_RESET_AVAIL_CH1_V 0x00000001U +#define DMA2D_IN_RESET_AVAIL_CH1_S 23 + +/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG register + * Represents the address associated with the inlink descriptor of channel 1 + */ +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x628) +/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S) +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S 0 + +/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG register + * Represents the address associated with the inlink descriptor of channel 1 + */ +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x62c) +/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. + */ +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S) +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S 0 + +/** DMA2D_IN_DSCR_CH1_REG register + * Represents the address associated with the inlink descriptor of channel 1 + */ +#define DMA2D_IN_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x630) +/** DMA2D_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the next inlink descriptor address x. + */ +#define DMA2D_INLINK_DSCR_CH1 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_CH1_M (DMA2D_INLINK_DSCR_CH1_V << DMA2D_INLINK_DSCR_CH1_S) +#define DMA2D_INLINK_DSCR_CH1_V 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_CH1_S 0 + +/** DMA2D_IN_DSCR_BF0_CH1_REG register + * Represents the address associated with the inlink descriptor of channel 1 + */ +#define DMA2D_IN_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x634) +/** DMA2D_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor's next address x-1. + */ +#define DMA2D_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF0_CH1_M (DMA2D_INLINK_DSCR_BF0_CH1_V << DMA2D_INLINK_DSCR_BF0_CH1_S) +#define DMA2D_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF0_CH1_S 0 + +/** DMA2D_IN_DSCR_BF1_CH1_REG register + * Represents the address associated with the inlink descriptor of channel 1 + */ +#define DMA2D_IN_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x638) +/** DMA2D_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor's next address x-2. + */ +#define DMA2D_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF1_CH1_M (DMA2D_INLINK_DSCR_BF1_CH1_V << DMA2D_INLINK_DSCR_BF1_CH1_S) +#define DMA2D_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF1_CH1_S 0 + +/** DMA2D_IN_PERI_SEL_CH1_REG register + * Configures the rx peripheral of channel 1 + */ +#define DMA2D_IN_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x63c) +/** DMA2D_IN_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7; + * This register is used to select peripheral for Rx channel 0: jpeg 1: + * display-1 2: display-2 7: no choose + */ +#define DMA2D_IN_PERI_SEL_CH1 0x00000007U +#define DMA2D_IN_PERI_SEL_CH1_M (DMA2D_IN_PERI_SEL_CH1_V << DMA2D_IN_PERI_SEL_CH1_S) +#define DMA2D_IN_PERI_SEL_CH1_V 0x00000007U +#define DMA2D_IN_PERI_SEL_CH1_S 0 + +/** DMA2D_IN_ARB_CH1_REG register + * Configures the rx arbiter of channel 1 */ -#define DMA2D_IN_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x55c) -/** DMA2D_IN_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes +#define DMA2D_IN_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x640) +/** DMA2D_IN_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1; + * Set the max number of token count of arbiter */ -#define DMA2D_IN_COLOR_PARAM_M0_CH0 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH0_M (DMA2D_IN_COLOR_PARAM_M0_CH0_V << DMA2D_IN_COLOR_PARAM_M0_CH0_S) -#define DMA2D_IN_COLOR_PARAM_M0_CH0_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH0_S 0 +#define DMA2D_IN_ARB_TOKEN_NUM_CH1 0x0000000FU +#define DMA2D_IN_ARB_TOKEN_NUM_CH1_M (DMA2D_IN_ARB_TOKEN_NUM_CH1_V << DMA2D_IN_ARB_TOKEN_NUM_CH1_S) +#define DMA2D_IN_ARB_TOKEN_NUM_CH1_V 0x0000000FU +#define DMA2D_IN_ARB_TOKEN_NUM_CH1_S 0 +/** DMA2D_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [7:4]; default: 1; + * Set the priority of channel + */ +#define DMA2D_IN_ARB_PRIORITY_CH1 0x0000000FU +#define DMA2D_IN_ARB_PRIORITY_CH1_M (DMA2D_IN_ARB_PRIORITY_CH1_V << DMA2D_IN_ARB_PRIORITY_CH1_S) +#define DMA2D_IN_ARB_PRIORITY_CH1_V 0x0000000FU +#define DMA2D_IN_ARB_PRIORITY_CH1_S 4 -/** DMA2D_IN_COLOR_PARAM3_CH0_REG register - * Configures the rx color convert parameter of channel 0 +/** DMA2D_IN_RO_STATUS_CH1_REG register + * Represents the status of the rx reorder module of channel 1 */ -#define DMA2D_IN_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x560) -/** DMA2D_IN_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes +#define DMA2D_IN_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x644) +/** DMA2D_INFIFO_RO_CNT_CH1 : RO; bitpos: [4:0]; default: 0; + * The register stores the byte number of the data in color convert Rx FIFO for + * channel 0. */ -#define DMA2D_IN_COLOR_PARAM_M1_CH0 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH0_M (DMA2D_IN_COLOR_PARAM_M1_CH0_V << DMA2D_IN_COLOR_PARAM_M1_CH0_S) -#define DMA2D_IN_COLOR_PARAM_M1_CH0_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM4_CH0_REG register - * Configures the rx color convert parameter of channel 0 +#define DMA2D_INFIFO_RO_CNT_CH1 0x0000001FU +#define DMA2D_INFIFO_RO_CNT_CH1_M (DMA2D_INFIFO_RO_CNT_CH1_V << DMA2D_INFIFO_RO_CNT_CH1_S) +#define DMA2D_INFIFO_RO_CNT_CH1_V 0x0000001FU +#define DMA2D_INFIFO_RO_CNT_CH1_S 0 +/** DMA2D_IN_RO_WR_STATE_CH1 : RO; bitpos: [6:5]; default: 0; + * The register stores the state of read ram of reorder */ -#define DMA2D_IN_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x564) -/** DMA2D_IN_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes +#define DMA2D_IN_RO_WR_STATE_CH1 0x00000003U +#define DMA2D_IN_RO_WR_STATE_CH1_M (DMA2D_IN_RO_WR_STATE_CH1_V << DMA2D_IN_RO_WR_STATE_CH1_S) +#define DMA2D_IN_RO_WR_STATE_CH1_V 0x00000003U +#define DMA2D_IN_RO_WR_STATE_CH1_S 5 +/** DMA2D_IN_RO_RD_STATE_CH1 : RO; bitpos: [8:7]; default: 0; + * The register stores the state of write ram of reorder */ -#define DMA2D_IN_COLOR_PARAM_L0_CH0 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH0_M (DMA2D_IN_COLOR_PARAM_L0_CH0_V << DMA2D_IN_COLOR_PARAM_L0_CH0_S) -#define DMA2D_IN_COLOR_PARAM_L0_CH0_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM5_CH0_REG register - * Configures the rx color convert parameter of channel 0 +#define DMA2D_IN_RO_RD_STATE_CH1 0x00000003U +#define DMA2D_IN_RO_RD_STATE_CH1_M (DMA2D_IN_RO_RD_STATE_CH1_V << DMA2D_IN_RO_RD_STATE_CH1_S) +#define DMA2D_IN_RO_RD_STATE_CH1_V 0x00000003U +#define DMA2D_IN_RO_RD_STATE_CH1_S 7 +/** DMA2D_IN_PIXEL_BYTE_CH1 : RO; bitpos: [12:9]; default: 0; + * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes + * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes */ -#define DMA2D_IN_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x568) -/** DMA2D_IN_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes +#define DMA2D_IN_PIXEL_BYTE_CH1 0x0000000FU +#define DMA2D_IN_PIXEL_BYTE_CH1_M (DMA2D_IN_PIXEL_BYTE_CH1_V << DMA2D_IN_PIXEL_BYTE_CH1_S) +#define DMA2D_IN_PIXEL_BYTE_CH1_V 0x0000000FU +#define DMA2D_IN_PIXEL_BYTE_CH1_S 9 +/** DMA2D_IN_BURST_BLOCK_NUM_CH1 : RO; bitpos: [16:13]; default: 0; + * the number of macro blocks contained in a burst of data at RX channel */ -#define DMA2D_IN_COLOR_PARAM_L1_CH0 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH0_M (DMA2D_IN_COLOR_PARAM_L1_CH0_V << DMA2D_IN_COLOR_PARAM_L1_CH0_S) -#define DMA2D_IN_COLOR_PARAM_L1_CH0_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH0_S 0 +#define DMA2D_IN_BURST_BLOCK_NUM_CH1 0x0000000FU +#define DMA2D_IN_BURST_BLOCK_NUM_CH1_M (DMA2D_IN_BURST_BLOCK_NUM_CH1_V << DMA2D_IN_BURST_BLOCK_NUM_CH1_S) +#define DMA2D_IN_BURST_BLOCK_NUM_CH1_V 0x0000000FU +#define DMA2D_IN_BURST_BLOCK_NUM_CH1_S 13 -/** DMA2D_IN_ETM_CONF_CH0_REG register - * Configures the rx etm of channel 0 +/** DMA2D_IN_ETM_CONF_CH1_REG register + * Configures the rx etm of channel 1 */ -#define DMA2D_IN_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x56c) -/** DMA2D_IN_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0; +#define DMA2D_IN_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x66c) +/** DMA2D_IN_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0; * Configures the enable of the etm function, 1 is enable. */ -#define DMA2D_IN_ETM_EN_CH0 (BIT(0)) -#define DMA2D_IN_ETM_EN_CH0_M (DMA2D_IN_ETM_EN_CH0_V << DMA2D_IN_ETM_EN_CH0_S) -#define DMA2D_IN_ETM_EN_CH0_V 0x00000001U -#define DMA2D_IN_ETM_EN_CH0_S 0 -/** DMA2D_IN_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0; +#define DMA2D_IN_ETM_EN_CH1 (BIT(0)) +#define DMA2D_IN_ETM_EN_CH1_M (DMA2D_IN_ETM_EN_CH1_V << DMA2D_IN_ETM_EN_CH1_S) +#define DMA2D_IN_ETM_EN_CH1_V 0x00000001U +#define DMA2D_IN_ETM_EN_CH1_S 0 +/** DMA2D_IN_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0; * Configures the enable of the descriptors loop etm function, 1 is enable. */ -#define DMA2D_IN_ETM_LOOP_EN_CH0 (BIT(1)) -#define DMA2D_IN_ETM_LOOP_EN_CH0_M (DMA2D_IN_ETM_LOOP_EN_CH0_V << DMA2D_IN_ETM_LOOP_EN_CH0_S) -#define DMA2D_IN_ETM_LOOP_EN_CH0_V 0x00000001U -#define DMA2D_IN_ETM_LOOP_EN_CH0_S 1 -/** DMA2D_IN_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1; +#define DMA2D_IN_ETM_LOOP_EN_CH1 (BIT(1)) +#define DMA2D_IN_ETM_LOOP_EN_CH1_M (DMA2D_IN_ETM_LOOP_EN_CH1_V << DMA2D_IN_ETM_LOOP_EN_CH1_S) +#define DMA2D_IN_ETM_LOOP_EN_CH1_V 0x00000001U +#define DMA2D_IN_ETM_LOOP_EN_CH1_S 1 +/** DMA2D_IN_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1; * Configures the maximum number of cacheable descriptors. */ -#define DMA2D_IN_DSCR_TASK_MAK_CH0 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH0_M (DMA2D_IN_DSCR_TASK_MAK_CH0_V << DMA2D_IN_DSCR_TASK_MAK_CH0_S) -#define DMA2D_IN_DSCR_TASK_MAK_CH0_V 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH0_S 2 +#define DMA2D_IN_DSCR_TASK_MAK_CH1 0x00000003U +#define DMA2D_IN_DSCR_TASK_MAK_CH1_M (DMA2D_IN_DSCR_TASK_MAK_CH1_V << DMA2D_IN_DSCR_TASK_MAK_CH1_S) +#define DMA2D_IN_DSCR_TASK_MAK_CH1_V 0x00000003U +#define DMA2D_IN_DSCR_TASK_MAK_CH1_S 2 -/** DMA2D_IN_CONF0_CH1_REG register - * Configures the rx direction of channel 0 +/** DMA2D_IN_CONF0_CH2_REG register + * Configures the rx direction of channel 2 */ -#define DMA2D_IN_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x600) -/** DMA2D_IN_MEM_TRANS_EN_CH1 : R/W; bitpos: [0]; default: 0; +#define DMA2D_IN_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x700) +/** DMA2D_IN_MEM_TRANS_EN_CH2 : R/W; bitpos: [0]; default: 0; * enable memory trans of the same channel */ -#define DMA2D_IN_MEM_TRANS_EN_CH1 (BIT(0)) -#define DMA2D_IN_MEM_TRANS_EN_CH1_M (DMA2D_IN_MEM_TRANS_EN_CH1_V << DMA2D_IN_MEM_TRANS_EN_CH1_S) -#define DMA2D_IN_MEM_TRANS_EN_CH1_V 0x00000001U -#define DMA2D_IN_MEM_TRANS_EN_CH1_S 0 -/** DMA2D_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; +#define DMA2D_IN_MEM_TRANS_EN_CH2 (BIT(0)) +#define DMA2D_IN_MEM_TRANS_EN_CH2_M (DMA2D_IN_MEM_TRANS_EN_CH2_V << DMA2D_IN_MEM_TRANS_EN_CH2_S) +#define DMA2D_IN_MEM_TRANS_EN_CH2_V 0x00000001U +#define DMA2D_IN_MEM_TRANS_EN_CH2_S 0 +/** DMA2D_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor * when accessing SRAM. */ -#define DMA2D_INDSCR_BURST_EN_CH1 (BIT(2)) -#define DMA2D_INDSCR_BURST_EN_CH1_M (DMA2D_INDSCR_BURST_EN_CH1_V << DMA2D_INDSCR_BURST_EN_CH1_S) -#define DMA2D_INDSCR_BURST_EN_CH1_V 0x00000001U -#define DMA2D_INDSCR_BURST_EN_CH1_S 2 -/** DMA2D_IN_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0; +#define DMA2D_INDSCR_BURST_EN_CH2 (BIT(2)) +#define DMA2D_INDSCR_BURST_EN_CH2_M (DMA2D_INDSCR_BURST_EN_CH2_V << DMA2D_INDSCR_BURST_EN_CH2_S) +#define DMA2D_INDSCR_BURST_EN_CH2_V 0x00000001U +#define DMA2D_INDSCR_BURST_EN_CH2_S 2 +/** DMA2D_IN_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0; * When access address space is ecc/aes area, this bit should be set to 1. In this * case, the start address of square should be 16-bit aligned. The width of square * multiply byte number of one pixel should be 16-bit aligned. */ -#define DMA2D_IN_ECC_AES_EN_CH1 (BIT(3)) -#define DMA2D_IN_ECC_AES_EN_CH1_M (DMA2D_IN_ECC_AES_EN_CH1_V << DMA2D_IN_ECC_AES_EN_CH1_S) -#define DMA2D_IN_ECC_AES_EN_CH1_V 0x00000001U -#define DMA2D_IN_ECC_AES_EN_CH1_S 3 -/** DMA2D_IN_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0; +#define DMA2D_IN_ECC_AES_EN_CH2 (BIT(3)) +#define DMA2D_IN_ECC_AES_EN_CH2_M (DMA2D_IN_ECC_AES_EN_CH2_V << DMA2D_IN_ECC_AES_EN_CH2_S) +#define DMA2D_IN_ECC_AES_EN_CH2_V 0x00000001U +#define DMA2D_IN_ECC_AES_EN_CH2_S 3 +/** DMA2D_IN_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0; * Set this bit to enable checking the owner attribute of the link descriptor. */ -#define DMA2D_IN_CHECK_OWNER_CH1 (BIT(4)) -#define DMA2D_IN_CHECK_OWNER_CH1_M (DMA2D_IN_CHECK_OWNER_CH1_V << DMA2D_IN_CHECK_OWNER_CH1_S) -#define DMA2D_IN_CHECK_OWNER_CH1_V 0x00000001U -#define DMA2D_IN_CHECK_OWNER_CH1_S 4 -/** DMA2D_IN_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0; +#define DMA2D_IN_CHECK_OWNER_CH2 (BIT(4)) +#define DMA2D_IN_CHECK_OWNER_CH2_M (DMA2D_IN_CHECK_OWNER_CH2_V << DMA2D_IN_CHECK_OWNER_CH2_S) +#define DMA2D_IN_CHECK_OWNER_CH2_V 0x00000001U +#define DMA2D_IN_CHECK_OWNER_CH2_S 4 +/** DMA2D_IN_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0; * reserved */ -#define DMA2D_IN_LOOP_TEST_CH1 (BIT(5)) -#define DMA2D_IN_LOOP_TEST_CH1_M (DMA2D_IN_LOOP_TEST_CH1_V << DMA2D_IN_LOOP_TEST_CH1_S) -#define DMA2D_IN_LOOP_TEST_CH1_V 0x00000001U -#define DMA2D_IN_LOOP_TEST_CH1_S 5 -/** DMA2D_IN_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0; +#define DMA2D_IN_LOOP_TEST_CH2 (BIT(5)) +#define DMA2D_IN_LOOP_TEST_CH2_M (DMA2D_IN_LOOP_TEST_CH2_V << DMA2D_IN_LOOP_TEST_CH2_S) +#define DMA2D_IN_LOOP_TEST_CH2_V 0x00000001U +#define DMA2D_IN_LOOP_TEST_CH2_S 5 +/** DMA2D_IN_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0; * Block size of Rx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 * bytes 4: 128 bytes */ -#define DMA2D_IN_MEM_BURST_LENGTH_CH1 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH1_M (DMA2D_IN_MEM_BURST_LENGTH_CH1_V << DMA2D_IN_MEM_BURST_LENGTH_CH1_S) -#define DMA2D_IN_MEM_BURST_LENGTH_CH1_V 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH1_S 6 -/** DMA2D_IN_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0; +#define DMA2D_IN_MEM_BURST_LENGTH_CH2 0x00000007U +#define DMA2D_IN_MEM_BURST_LENGTH_CH2_M (DMA2D_IN_MEM_BURST_LENGTH_CH2_V << DMA2D_IN_MEM_BURST_LENGTH_CH2_S) +#define DMA2D_IN_MEM_BURST_LENGTH_CH2_V 0x00000007U +#define DMA2D_IN_MEM_BURST_LENGTH_CH2_S 6 +/** DMA2D_IN_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0; * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link * descriptor */ -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S) -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S 9 -/** DMA2D_IN_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0; +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2 0x00000003U +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S) +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V 0x00000003U +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S 9 +/** DMA2D_IN_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0; * Set this bit to 1 to obtain descriptor from IP port */ -#define DMA2D_IN_DSCR_PORT_EN_CH1 (BIT(11)) -#define DMA2D_IN_DSCR_PORT_EN_CH1_M (DMA2D_IN_DSCR_PORT_EN_CH1_V << DMA2D_IN_DSCR_PORT_EN_CH1_S) -#define DMA2D_IN_DSCR_PORT_EN_CH1_V 0x00000001U -#define DMA2D_IN_DSCR_PORT_EN_CH1_S 11 -/** DMA2D_IN_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0; +#define DMA2D_IN_DSCR_PORT_EN_CH2 (BIT(11)) +#define DMA2D_IN_DSCR_PORT_EN_CH2_M (DMA2D_IN_DSCR_PORT_EN_CH2_V << DMA2D_IN_DSCR_PORT_EN_CH2_S) +#define DMA2D_IN_DSCR_PORT_EN_CH2_V 0x00000001U +#define DMA2D_IN_DSCR_PORT_EN_CH2_S 11 +/** DMA2D_IN_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0; * Set this bit to 1 to make sure AXI write data don't cross the address boundary * which define by mem_burst_length */ -#define DMA2D_IN_PAGE_BOUND_EN_CH1 (BIT(12)) -#define DMA2D_IN_PAGE_BOUND_EN_CH1_M (DMA2D_IN_PAGE_BOUND_EN_CH1_V << DMA2D_IN_PAGE_BOUND_EN_CH1_S) -#define DMA2D_IN_PAGE_BOUND_EN_CH1_V 0x00000001U -#define DMA2D_IN_PAGE_BOUND_EN_CH1_S 12 -/** DMA2D_IN_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0; +#define DMA2D_IN_PAGE_BOUND_EN_CH2 (BIT(12)) +#define DMA2D_IN_PAGE_BOUND_EN_CH2_M (DMA2D_IN_PAGE_BOUND_EN_CH2_V << DMA2D_IN_PAGE_BOUND_EN_CH2_S) +#define DMA2D_IN_PAGE_BOUND_EN_CH2_V 0x00000001U +#define DMA2D_IN_PAGE_BOUND_EN_CH2_S 12 +/** DMA2D_IN_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0; * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this * selection */ -#define DMA2D_IN_REORDER_EN_CH1 (BIT(16)) -#define DMA2D_IN_REORDER_EN_CH1_M (DMA2D_IN_REORDER_EN_CH1_V << DMA2D_IN_REORDER_EN_CH1_S) -#define DMA2D_IN_REORDER_EN_CH1_V 0x00000001U -#define DMA2D_IN_REORDER_EN_CH1_S 16 -/** DMA2D_IN_RST_CH1 : R/W; bitpos: [24]; default: 0; +#define DMA2D_IN_REORDER_EN_CH2 (BIT(16)) +#define DMA2D_IN_REORDER_EN_CH2_M (DMA2D_IN_REORDER_EN_CH2_V << DMA2D_IN_REORDER_EN_CH2_S) +#define DMA2D_IN_REORDER_EN_CH2_V 0x00000001U +#define DMA2D_IN_REORDER_EN_CH2_S 16 +/** DMA2D_IN_RST_CH2 : R/W; bitpos: [24]; default: 0; * Write 1 then write 0 to this bit to reset Rx channel */ -#define DMA2D_IN_RST_CH1 (BIT(24)) -#define DMA2D_IN_RST_CH1_M (DMA2D_IN_RST_CH1_V << DMA2D_IN_RST_CH1_S) -#define DMA2D_IN_RST_CH1_V 0x00000001U -#define DMA2D_IN_RST_CH1_S 24 -/** DMA2D_IN_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0; +#define DMA2D_IN_RST_CH2 (BIT(24)) +#define DMA2D_IN_RST_CH2_M (DMA2D_IN_RST_CH2_V << DMA2D_IN_RST_CH2_S) +#define DMA2D_IN_RST_CH2_V 0x00000001U +#define DMA2D_IN_RST_CH2_S 24 +/** DMA2D_IN_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0; * Write 1 before reset and write 0 after reset */ -#define DMA2D_IN_CMD_DISABLE_CH1 (BIT(25)) -#define DMA2D_IN_CMD_DISABLE_CH1_M (DMA2D_IN_CMD_DISABLE_CH1_V << DMA2D_IN_CMD_DISABLE_CH1_S) -#define DMA2D_IN_CMD_DISABLE_CH1_V 0x00000001U -#define DMA2D_IN_CMD_DISABLE_CH1_S 25 -/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0; +#define DMA2D_IN_CMD_DISABLE_CH2 (BIT(25)) +#define DMA2D_IN_CMD_DISABLE_CH2_M (DMA2D_IN_CMD_DISABLE_CH2_V << DMA2D_IN_CMD_DISABLE_CH2_S) +#define DMA2D_IN_CMD_DISABLE_CH2_V 0x00000001U +#define DMA2D_IN_CMD_DISABLE_CH2_S 25 +/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0; * Set this bit to 1 to disable arbiter optimum weight function. */ -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1 (BIT(26)) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S 26 +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2 (BIT(26)) +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S) +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V 0x00000001U +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S 26 -/** DMA2D_IN_INT_RAW_CH1_REG register - * Raw interrupt status of RX channel 0 +/** DMA2D_IN_INT_RAW_CH2_REG register + * Raw interrupt status of RX channel 2 */ -#define DMA2D_IN_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x604) -/** DMA2D_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; +#define DMA2D_IN_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x704) +/** DMA2D_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink * descriptor has been transmitted to peripherals for Rx channel 0. */ -#define DMA2D_IN_DONE_CH1_INT_RAW (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_RAW_M (DMA2D_IN_DONE_CH1_INT_RAW_V << DMA2D_IN_DONE_CH1_INT_RAW_S) -#define DMA2D_IN_DONE_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_RAW_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; +#define DMA2D_IN_DONE_CH2_INT_RAW (BIT(0)) +#define DMA2D_IN_DONE_CH2_INT_RAW_M (DMA2D_IN_DONE_CH2_INT_RAW_V << DMA2D_IN_DONE_CH2_INT_RAW_S) +#define DMA2D_IN_DONE_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_DONE_CH2_INT_RAW_S 0 +/** DMA2D_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink * descriptor has been received and no data error is detected for Rx channel 0. */ -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_M (DMA2D_IN_SUC_EOF_CH1_INT_RAW_V << DMA2D_IN_SUC_EOF_CH1_INT_RAW_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; +#define DMA2D_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_M (DMA2D_IN_SUC_EOF_CH2_INT_RAW_V << DMA2D_IN_SUC_EOF_CH2_INT_RAW_S) +#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_S 1 +/** DMA2D_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink * descriptor has been received and data error is detected */ -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_M (DMA2D_IN_ERR_EOF_CH1_INT_RAW_V << DMA2D_IN_ERR_EOF_CH1_INT_RAW_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; +#define DMA2D_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_M (DMA2D_IN_ERR_EOF_CH2_INT_RAW_V << DMA2D_IN_ERR_EOF_CH2_INT_RAW_S) +#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_S 2 +/** DMA2D_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; * The raw interrupt bit turns to high level when detecting inlink descriptor error, * including owner error, the second and third word error of inlink descriptor for Rx * channel 0. */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; +#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S) +#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S 3 +/** DMA2D_INFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; +#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S 4 +/** DMA2D_INFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; +#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S 5 +/** DMA2D_INFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; +#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S 6 +/** DMA2D_INFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; +#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S 7 +/** DMA2D_INFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; +#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S 8 +/** DMA2D_INFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; +#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; * The raw interrupt bit turns to high level when the last descriptor is done but fifo * also remain data. */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S 10 +/** DMA2D_INFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; * The raw interrupt bit turns to high level when reorder fifo is overflow. */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; +#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S 11 +/** DMA2D_INFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when reorder fifo is underflow. + */ +#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S 13 +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S 13 -/** DMA2D_IN_INT_ENA_CH1_REG register - * Interrupt enable bits of RX channel 0 +/** DMA2D_IN_INT_ENA_CH2_REG register + * Interrupt enable bits of RX channel 2 */ -#define DMA2D_IN_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x608) -/** DMA2D_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; +#define DMA2D_IN_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x708) +/** DMA2D_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ -#define DMA2D_IN_DONE_CH1_INT_ENA (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_ENA_M (DMA2D_IN_DONE_CH1_INT_ENA_V << DMA2D_IN_DONE_CH1_INT_ENA_S) -#define DMA2D_IN_DONE_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_ENA_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; +#define DMA2D_IN_DONE_CH2_INT_ENA (BIT(0)) +#define DMA2D_IN_DONE_CH2_INT_ENA_M (DMA2D_IN_DONE_CH2_INT_ENA_V << DMA2D_IN_DONE_CH2_INT_ENA_S) +#define DMA2D_IN_DONE_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_DONE_CH2_INT_ENA_S 0 +/** DMA2D_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_M (DMA2D_IN_SUC_EOF_CH1_INT_ENA_V << DMA2D_IN_SUC_EOF_CH1_INT_ENA_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; +#define DMA2D_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_M (DMA2D_IN_SUC_EOF_CH2_INT_ENA_V << DMA2D_IN_SUC_EOF_CH2_INT_ENA_S) +#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_S 1 +/** DMA2D_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_M (DMA2D_IN_ERR_EOF_CH1_INT_ENA_V << DMA2D_IN_ERR_EOF_CH1_INT_ENA_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; +#define DMA2D_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_M (DMA2D_IN_ERR_EOF_CH2_INT_ENA_V << DMA2D_IN_ERR_EOF_CH2_INT_ENA_S) +#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_S 2 +/** DMA2D_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; +#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S) +#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S 3 +/** DMA2D_INFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S 4 +/** DMA2D_INFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S 5 +/** DMA2D_INFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S 6 +/** DMA2D_INFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0; * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0; +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S 7 +/** DMA2D_INFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0; * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0; +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S 8 +/** DMA2D_INFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0; * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [10]; default: 0; +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [10]; default: 0; * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0; +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S 10 +/** DMA2D_INFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0; * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0; +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S 11 +/** DMA2D_INFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0; * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [13]; default: 0; * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S 13 +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S 13 -/** DMA2D_IN_INT_ST_CH1_REG register - * Masked interrupt status of RX channel 0 +/** DMA2D_IN_INT_ST_CH2_REG register + * Masked interrupt status of RX channel 2 */ -#define DMA2D_IN_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x60c) -/** DMA2D_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; +#define DMA2D_IN_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x70c) +/** DMA2D_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ -#define DMA2D_IN_DONE_CH1_INT_ST (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_ST_M (DMA2D_IN_DONE_CH1_INT_ST_V << DMA2D_IN_DONE_CH1_INT_ST_S) -#define DMA2D_IN_DONE_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_ST_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; +#define DMA2D_IN_DONE_CH2_INT_ST (BIT(0)) +#define DMA2D_IN_DONE_CH2_INT_ST_M (DMA2D_IN_DONE_CH2_INT_ST_V << DMA2D_IN_DONE_CH2_INT_ST_S) +#define DMA2D_IN_DONE_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_DONE_CH2_INT_ST_S 0 +/** DMA2D_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ -#define DMA2D_IN_SUC_EOF_CH1_INT_ST (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_ST_M (DMA2D_IN_SUC_EOF_CH1_INT_ST_V << DMA2D_IN_SUC_EOF_CH1_INT_ST_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_ST_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; +#define DMA2D_IN_SUC_EOF_CH2_INT_ST (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH2_INT_ST_M (DMA2D_IN_SUC_EOF_CH2_INT_ST_V << DMA2D_IN_SUC_EOF_CH2_INT_ST_S) +#define DMA2D_IN_SUC_EOF_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH2_INT_ST_S 1 +/** DMA2D_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ -#define DMA2D_IN_ERR_EOF_CH1_INT_ST (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_ST_M (DMA2D_IN_ERR_EOF_CH1_INT_ST_V << DMA2D_IN_ERR_EOF_CH1_INT_ST_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_ST_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; +#define DMA2D_IN_ERR_EOF_CH2_INT_ST (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH2_INT_ST_M (DMA2D_IN_ERR_EOF_CH2_INT_ST_V << DMA2D_IN_ERR_EOF_CH2_INT_ST_S) +#define DMA2D_IN_ERR_EOF_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH2_INT_ST_S 2 +/** DMA2D_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0; * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_M (DMA2D_IN_DSCR_ERR_CH1_INT_ST_V << DMA2D_IN_DSCR_ERR_CH1_INT_ST_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0; +#define DMA2D_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_M (DMA2D_IN_DSCR_ERR_CH2_INT_ST_V << DMA2D_IN_DSCR_ERR_CH2_INT_ST_S) +#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_S 3 +/** DMA2D_INFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0; * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0; +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S 4 +/** DMA2D_INFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0; * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0; +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S 5 +/** DMA2D_INFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0; * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0; +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S 6 +/** DMA2D_INFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0; * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0; +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S 7 +/** DMA2D_INFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0; * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0; +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S 8 +/** DMA2D_INFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0; * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [10]; default: 0; +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [10]; default: 0; * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [11]; default: 0; +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S 10 +/** DMA2D_INFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [11]; default: 0; * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [12]; default: 0; +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S 11 +/** DMA2D_INFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [12]; default: 0; * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [13]; default: 0; +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [13]; default: 0; * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S 13 +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S 13 -/** DMA2D_IN_INT_CLR_CH1_REG register - * Interrupt clear bits of RX channel 0 +/** DMA2D_IN_INT_CLR_CH2_REG register + * Interrupt clear bits of RX channel 2 */ -#define DMA2D_IN_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x610) -/** DMA2D_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; +#define DMA2D_IN_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x710) +/** DMA2D_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; * Set this bit to clear the IN_DONE_CH_INT interrupt. */ -#define DMA2D_IN_DONE_CH1_INT_CLR (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_CLR_M (DMA2D_IN_DONE_CH1_INT_CLR_V << DMA2D_IN_DONE_CH1_INT_CLR_S) -#define DMA2D_IN_DONE_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_CLR_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; +#define DMA2D_IN_DONE_CH2_INT_CLR (BIT(0)) +#define DMA2D_IN_DONE_CH2_INT_CLR_M (DMA2D_IN_DONE_CH2_INT_CLR_V << DMA2D_IN_DONE_CH2_INT_CLR_S) +#define DMA2D_IN_DONE_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_DONE_CH2_INT_CLR_S 0 +/** DMA2D_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_M (DMA2D_IN_SUC_EOF_CH1_INT_CLR_V << DMA2D_IN_SUC_EOF_CH1_INT_CLR_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; +#define DMA2D_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_M (DMA2D_IN_SUC_EOF_CH2_INT_CLR_V << DMA2D_IN_SUC_EOF_CH2_INT_CLR_S) +#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_S 1 +/** DMA2D_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_M (DMA2D_IN_ERR_EOF_CH1_INT_CLR_V << DMA2D_IN_ERR_EOF_CH1_INT_CLR_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; +#define DMA2D_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_M (DMA2D_IN_ERR_EOF_CH2_INT_CLR_V << DMA2D_IN_ERR_EOF_CH2_INT_CLR_S) +#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_S 2 +/** DMA2D_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0; * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0; +#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S) +#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S 3 +/** DMA2D_INFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0; * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0; +#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S 4 +/** DMA2D_INFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0; * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0; +#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S 5 +/** DMA2D_INFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0; * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0; +#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S 6 +/** DMA2D_INFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0; * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0; +#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S 7 +/** DMA2D_INFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0; * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0; +#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S 8 +/** DMA2D_INFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0; * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [10]; default: 0; +#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [10]; default: 0; * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [11]; default: 0; +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S 10 +/** DMA2D_INFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [11]; default: 0; * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [12]; default: 0; +#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S 11 +/** DMA2D_INFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [12]; default: 0; * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [13]; default: 0; +#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [13]; default: 0; * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S 13 +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S 13 -/** DMA2D_INFIFO_STATUS_CH1_REG register - * Represents the status of the rx fifo of channel 0 +/** DMA2D_INFIFO_STATUS_CH2_REG register + * Represents the status of the rx fifo of channel 2 */ -#define DMA2D_INFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x614) -/** DMA2D_INFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0; +#define DMA2D_INFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x714) +/** DMA2D_INFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0; * Rx FIFO full signal for Rx channel. */ -#define DMA2D_INFIFO_FULL_L2_CH1 (BIT(0)) -#define DMA2D_INFIFO_FULL_L2_CH1_M (DMA2D_INFIFO_FULL_L2_CH1_V << DMA2D_INFIFO_FULL_L2_CH1_S) -#define DMA2D_INFIFO_FULL_L2_CH1_V 0x00000001U -#define DMA2D_INFIFO_FULL_L2_CH1_S 0 -/** DMA2D_INFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ -#define DMA2D_INFIFO_EMPTY_L2_CH1 (BIT(1)) -#define DMA2D_INFIFO_EMPTY_L2_CH1_M (DMA2D_INFIFO_EMPTY_L2_CH1_V << DMA2D_INFIFO_EMPTY_L2_CH1_S) -#define DMA2D_INFIFO_EMPTY_L2_CH1_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L2_CH1_S 1 -/** DMA2D_INFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ -#define DMA2D_INFIFO_CNT_L2_CH1 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH1_M (DMA2D_INFIFO_CNT_L2_CH1_V << DMA2D_INFIFO_CNT_L2_CH1_S) -#define DMA2D_INFIFO_CNT_L2_CH1_V 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH1_S 2 -/** DMA2D_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_1B_CH1 (BIT(7)) -#define DMA2D_IN_REMAIN_UNDER_1B_CH1_M (DMA2D_IN_REMAIN_UNDER_1B_CH1_V << DMA2D_IN_REMAIN_UNDER_1B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_1B_CH1_S 7 -/** DMA2D_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 0; - * reserved +#define DMA2D_INFIFO_FULL_L2_CH2 (BIT(0)) +#define DMA2D_INFIFO_FULL_L2_CH2_M (DMA2D_INFIFO_FULL_L2_CH2_V << DMA2D_INFIFO_FULL_L2_CH2_S) +#define DMA2D_INFIFO_FULL_L2_CH2_V 0x00000001U +#define DMA2D_INFIFO_FULL_L2_CH2_S 0 +/** DMA2D_INFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1; + * Rx FIFO empty signal for Rx channel. */ -#define DMA2D_IN_REMAIN_UNDER_2B_CH1 (BIT(8)) -#define DMA2D_IN_REMAIN_UNDER_2B_CH1_M (DMA2D_IN_REMAIN_UNDER_2B_CH1_V << DMA2D_IN_REMAIN_UNDER_2B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_2B_CH1_S 8 -/** DMA2D_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 0; - * reserved +#define DMA2D_INFIFO_EMPTY_L2_CH2 (BIT(1)) +#define DMA2D_INFIFO_EMPTY_L2_CH2_M (DMA2D_INFIFO_EMPTY_L2_CH2_V << DMA2D_INFIFO_EMPTY_L2_CH2_S) +#define DMA2D_INFIFO_EMPTY_L2_CH2_V 0x00000001U +#define DMA2D_INFIFO_EMPTY_L2_CH2_S 1 +/** DMA2D_INFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel. */ -#define DMA2D_IN_REMAIN_UNDER_3B_CH1 (BIT(9)) -#define DMA2D_IN_REMAIN_UNDER_3B_CH1_M (DMA2D_IN_REMAIN_UNDER_3B_CH1_V << DMA2D_IN_REMAIN_UNDER_3B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_3B_CH1_S 9 -/** DMA2D_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 0; +#define DMA2D_INFIFO_CNT_L2_CH2 0x0000000FU +#define DMA2D_INFIFO_CNT_L2_CH2_M (DMA2D_INFIFO_CNT_L2_CH2_V << DMA2D_INFIFO_CNT_L2_CH2_S) +#define DMA2D_INFIFO_CNT_L2_CH2_V 0x0000000FU +#define DMA2D_INFIFO_CNT_L2_CH2_S 2 +/** DMA2D_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 0; * reserved */ -#define DMA2D_IN_REMAIN_UNDER_4B_CH1 (BIT(10)) -#define DMA2D_IN_REMAIN_UNDER_4B_CH1_M (DMA2D_IN_REMAIN_UNDER_4B_CH1_V << DMA2D_IN_REMAIN_UNDER_4B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_4B_CH1_S 10 -/** DMA2D_IN_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 0; +#define DMA2D_IN_REMAIN_UNDER_1B_CH2 (BIT(7)) +#define DMA2D_IN_REMAIN_UNDER_1B_CH2_M (DMA2D_IN_REMAIN_UNDER_1B_CH2_V << DMA2D_IN_REMAIN_UNDER_1B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_1B_CH2_S 7 +/** DMA2D_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 0; * reserved */ -#define DMA2D_IN_REMAIN_UNDER_5B_CH1 (BIT(11)) -#define DMA2D_IN_REMAIN_UNDER_5B_CH1_M (DMA2D_IN_REMAIN_UNDER_5B_CH1_V << DMA2D_IN_REMAIN_UNDER_5B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_5B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_5B_CH1_S 11 -/** DMA2D_IN_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 0; +#define DMA2D_IN_REMAIN_UNDER_2B_CH2 (BIT(8)) +#define DMA2D_IN_REMAIN_UNDER_2B_CH2_M (DMA2D_IN_REMAIN_UNDER_2B_CH2_V << DMA2D_IN_REMAIN_UNDER_2B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_2B_CH2_S 8 +/** DMA2D_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 0; * reserved */ -#define DMA2D_IN_REMAIN_UNDER_6B_CH1 (BIT(12)) -#define DMA2D_IN_REMAIN_UNDER_6B_CH1_M (DMA2D_IN_REMAIN_UNDER_6B_CH1_V << DMA2D_IN_REMAIN_UNDER_6B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_6B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_6B_CH1_S 12 -/** DMA2D_IN_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 0; +#define DMA2D_IN_REMAIN_UNDER_3B_CH2 (BIT(9)) +#define DMA2D_IN_REMAIN_UNDER_3B_CH2_M (DMA2D_IN_REMAIN_UNDER_3B_CH2_V << DMA2D_IN_REMAIN_UNDER_3B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_3B_CH2_S 9 +/** DMA2D_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 0; * reserved */ -#define DMA2D_IN_REMAIN_UNDER_7B_CH1 (BIT(13)) -#define DMA2D_IN_REMAIN_UNDER_7B_CH1_M (DMA2D_IN_REMAIN_UNDER_7B_CH1_V << DMA2D_IN_REMAIN_UNDER_7B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_7B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_7B_CH1_S 13 -/** DMA2D_IN_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 0; +#define DMA2D_IN_REMAIN_UNDER_4B_CH2 (BIT(10)) +#define DMA2D_IN_REMAIN_UNDER_4B_CH2_M (DMA2D_IN_REMAIN_UNDER_4B_CH2_V << DMA2D_IN_REMAIN_UNDER_4B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_4B_CH2_S 10 +/** DMA2D_IN_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 0; * reserved */ -#define DMA2D_IN_REMAIN_UNDER_8B_CH1 (BIT(14)) -#define DMA2D_IN_REMAIN_UNDER_8B_CH1_M (DMA2D_IN_REMAIN_UNDER_8B_CH1_V << DMA2D_IN_REMAIN_UNDER_8B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_8B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_8B_CH1_S 14 -/** DMA2D_INFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_INFIFO_FULL_L1_CH1 (BIT(15)) -#define DMA2D_INFIFO_FULL_L1_CH1_M (DMA2D_INFIFO_FULL_L1_CH1_V << DMA2D_INFIFO_FULL_L1_CH1_S) -#define DMA2D_INFIFO_FULL_L1_CH1_V 0x00000001U -#define DMA2D_INFIFO_FULL_L1_CH1_S 15 -/** DMA2D_INFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L1_CH1 (BIT(16)) -#define DMA2D_INFIFO_EMPTY_L1_CH1_M (DMA2D_INFIFO_EMPTY_L1_CH1_V << DMA2D_INFIFO_EMPTY_L1_CH1_S) -#define DMA2D_INFIFO_EMPTY_L1_CH1_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L1_CH1_S 16 -/** DMA2D_INFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_INFIFO_CNT_L1_CH1 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH1_M (DMA2D_INFIFO_CNT_L1_CH1_V << DMA2D_INFIFO_CNT_L1_CH1_S) -#define DMA2D_INFIFO_CNT_L1_CH1_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH1_S 17 -/** DMA2D_INFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_INFIFO_FULL_L3_CH1 (BIT(22)) -#define DMA2D_INFIFO_FULL_L3_CH1_M (DMA2D_INFIFO_FULL_L3_CH1_V << DMA2D_INFIFO_FULL_L3_CH1_S) -#define DMA2D_INFIFO_FULL_L3_CH1_V 0x00000001U -#define DMA2D_INFIFO_FULL_L3_CH1_S 22 -/** DMA2D_INFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. +#define DMA2D_IN_REMAIN_UNDER_5B_CH2 (BIT(11)) +#define DMA2D_IN_REMAIN_UNDER_5B_CH2_M (DMA2D_IN_REMAIN_UNDER_5B_CH2_V << DMA2D_IN_REMAIN_UNDER_5B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_5B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_5B_CH2_S 11 +/** DMA2D_IN_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 0; + * reserved */ -#define DMA2D_INFIFO_EMPTY_L3_CH1 (BIT(23)) -#define DMA2D_INFIFO_EMPTY_L3_CH1_M (DMA2D_INFIFO_EMPTY_L3_CH1_V << DMA2D_INFIFO_EMPTY_L3_CH1_S) -#define DMA2D_INFIFO_EMPTY_L3_CH1_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L3_CH1_S 23 -/** DMA2D_INFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. +#define DMA2D_IN_REMAIN_UNDER_6B_CH2 (BIT(12)) +#define DMA2D_IN_REMAIN_UNDER_6B_CH2_M (DMA2D_IN_REMAIN_UNDER_6B_CH2_V << DMA2D_IN_REMAIN_UNDER_6B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_6B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_6B_CH2_S 12 +/** DMA2D_IN_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 0; + * reserved */ -#define DMA2D_INFIFO_CNT_L3_CH1 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH1_M (DMA2D_INFIFO_CNT_L3_CH1_V << DMA2D_INFIFO_CNT_L3_CH1_S) -#define DMA2D_INFIFO_CNT_L3_CH1_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH1_S 24 - -/** DMA2D_IN_POP_CH1_REG register - * Configures the rx fifo of channel 0 +#define DMA2D_IN_REMAIN_UNDER_7B_CH2 (BIT(13)) +#define DMA2D_IN_REMAIN_UNDER_7B_CH2_M (DMA2D_IN_REMAIN_UNDER_7B_CH2_V << DMA2D_IN_REMAIN_UNDER_7B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_7B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_7B_CH2_S 13 +/** DMA2D_IN_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 0; + * reserved */ -#define DMA2D_IN_POP_CH1_REG (DR_REG_DMA2D_BASE + 0x618) -/** DMA2D_INFIFO_RDATA_CH1 : RO; bitpos: [10:0]; default: 1024; +#define DMA2D_IN_REMAIN_UNDER_8B_CH2 (BIT(14)) +#define DMA2D_IN_REMAIN_UNDER_8B_CH2_M (DMA2D_IN_REMAIN_UNDER_8B_CH2_V << DMA2D_IN_REMAIN_UNDER_8B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_8B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_8B_CH2_S 14 +/** DMA2D_INFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0; + * Rx FIFO full signal for Rx channel 0. + */ +#define DMA2D_INFIFO_FULL_L1_CH2 (BIT(15)) +#define DMA2D_INFIFO_FULL_L1_CH2_M (DMA2D_INFIFO_FULL_L1_CH2_V << DMA2D_INFIFO_FULL_L1_CH2_S) +#define DMA2D_INFIFO_FULL_L1_CH2_V 0x00000001U +#define DMA2D_INFIFO_FULL_L1_CH2_S 15 +/** DMA2D_INFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1; + * Rx FIFO empty signal for Rx channel 0. + */ +#define DMA2D_INFIFO_EMPTY_L1_CH2 (BIT(16)) +#define DMA2D_INFIFO_EMPTY_L1_CH2_M (DMA2D_INFIFO_EMPTY_L1_CH2_V << DMA2D_INFIFO_EMPTY_L1_CH2_S) +#define DMA2D_INFIFO_EMPTY_L1_CH2_V 0x00000001U +#define DMA2D_INFIFO_EMPTY_L1_CH2_S 16 +/** DMA2D_INFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. + */ +#define DMA2D_INFIFO_CNT_L1_CH2 0x0000001FU +#define DMA2D_INFIFO_CNT_L1_CH2_M (DMA2D_INFIFO_CNT_L1_CH2_V << DMA2D_INFIFO_CNT_L1_CH2_S) +#define DMA2D_INFIFO_CNT_L1_CH2_V 0x0000001FU +#define DMA2D_INFIFO_CNT_L1_CH2_S 17 +/** DMA2D_INFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0; + * Rx FIFO full signal for Rx channel 0. + */ +#define DMA2D_INFIFO_FULL_L3_CH2 (BIT(22)) +#define DMA2D_INFIFO_FULL_L3_CH2_M (DMA2D_INFIFO_FULL_L3_CH2_V << DMA2D_INFIFO_FULL_L3_CH2_S) +#define DMA2D_INFIFO_FULL_L3_CH2_V 0x00000001U +#define DMA2D_INFIFO_FULL_L3_CH2_S 22 +/** DMA2D_INFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1; + * Rx FIFO empty signal for Rx channel 0. + */ +#define DMA2D_INFIFO_EMPTY_L3_CH2 (BIT(23)) +#define DMA2D_INFIFO_EMPTY_L3_CH2_M (DMA2D_INFIFO_EMPTY_L3_CH2_V << DMA2D_INFIFO_EMPTY_L3_CH2_S) +#define DMA2D_INFIFO_EMPTY_L3_CH2_V 0x00000001U +#define DMA2D_INFIFO_EMPTY_L3_CH2_S 23 +/** DMA2D_INFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. + */ +#define DMA2D_INFIFO_CNT_L3_CH2 0x0000001FU +#define DMA2D_INFIFO_CNT_L3_CH2_M (DMA2D_INFIFO_CNT_L3_CH2_V << DMA2D_INFIFO_CNT_L3_CH2_S) +#define DMA2D_INFIFO_CNT_L3_CH2_V 0x0000001FU +#define DMA2D_INFIFO_CNT_L3_CH2_S 24 + +/** DMA2D_IN_POP_CH2_REG register + * Configures the rx fifo of channel 2 + */ +#define DMA2D_IN_POP_CH2_REG (DR_REG_DMA2D_BASE + 0x718) +/** DMA2D_INFIFO_RDATA_CH2 : RO; bitpos: [10:0]; default: 1024; * This register stores the data popping from DMA Rx FIFO. */ -#define DMA2D_INFIFO_RDATA_CH1 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH1_M (DMA2D_INFIFO_RDATA_CH1_V << DMA2D_INFIFO_RDATA_CH1_S) -#define DMA2D_INFIFO_RDATA_CH1_V 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH1_S 0 -/** DMA2D_INFIFO_POP_CH1 : R/W/SC; bitpos: [11]; default: 0; +#define DMA2D_INFIFO_RDATA_CH2 0x000007FFU +#define DMA2D_INFIFO_RDATA_CH2_M (DMA2D_INFIFO_RDATA_CH2_V << DMA2D_INFIFO_RDATA_CH2_S) +#define DMA2D_INFIFO_RDATA_CH2_V 0x000007FFU +#define DMA2D_INFIFO_RDATA_CH2_S 0 +/** DMA2D_INFIFO_POP_CH2 : R/W/SC; bitpos: [11]; default: 0; * Set this bit to pop data from DMA Rx FIFO. */ -#define DMA2D_INFIFO_POP_CH1 (BIT(11)) -#define DMA2D_INFIFO_POP_CH1_M (DMA2D_INFIFO_POP_CH1_V << DMA2D_INFIFO_POP_CH1_S) -#define DMA2D_INFIFO_POP_CH1_V 0x00000001U -#define DMA2D_INFIFO_POP_CH1_S 11 +#define DMA2D_INFIFO_POP_CH2 (BIT(11)) +#define DMA2D_INFIFO_POP_CH2_M (DMA2D_INFIFO_POP_CH2_V << DMA2D_INFIFO_POP_CH2_S) +#define DMA2D_INFIFO_POP_CH2_V 0x00000001U +#define DMA2D_INFIFO_POP_CH2_S 11 -/** DMA2D_IN_LINK_CONF_CH1_REG register - * Configures the rx descriptor operations of channel 0 +/** DMA2D_IN_LINK_CONF_CH2_REG register + * Configures the rx descriptor operations of channel 2 */ -#define DMA2D_IN_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x61c) -/** DMA2D_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; +#define DMA2D_IN_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x71c) +/** DMA2D_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1; * Configure the value of the owner field written back to the inlink descriptor. * 1: Write back 1. 0: Write back 0. */ -#define DMA2D_INLINK_AUTO_RET_CH1 (BIT(20)) -#define DMA2D_INLINK_AUTO_RET_CH1_M (DMA2D_INLINK_AUTO_RET_CH1_V << DMA2D_INLINK_AUTO_RET_CH1_S) -#define DMA2D_INLINK_AUTO_RET_CH1_V 0x00000001U -#define DMA2D_INLINK_AUTO_RET_CH1_S 20 -/** DMA2D_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0; +#define DMA2D_INLINK_AUTO_RET_CH2 (BIT(20)) +#define DMA2D_INLINK_AUTO_RET_CH2_M (DMA2D_INLINK_AUTO_RET_CH2_V << DMA2D_INLINK_AUTO_RET_CH2_S) +#define DMA2D_INLINK_AUTO_RET_CH2_V 0x00000001U +#define DMA2D_INLINK_AUTO_RET_CH2_S 20 +/** DMA2D_INLINK_STOP_CH2 : R/W/SC; bitpos: [21]; default: 0; * Set this bit to stop dealing with the inlink descriptors. */ -#define DMA2D_INLINK_STOP_CH1 (BIT(21)) -#define DMA2D_INLINK_STOP_CH1_M (DMA2D_INLINK_STOP_CH1_V << DMA2D_INLINK_STOP_CH1_S) -#define DMA2D_INLINK_STOP_CH1_V 0x00000001U -#define DMA2D_INLINK_STOP_CH1_S 21 -/** DMA2D_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0; +#define DMA2D_INLINK_STOP_CH2 (BIT(21)) +#define DMA2D_INLINK_STOP_CH2_M (DMA2D_INLINK_STOP_CH2_V << DMA2D_INLINK_STOP_CH2_S) +#define DMA2D_INLINK_STOP_CH2_V 0x00000001U +#define DMA2D_INLINK_STOP_CH2_S 21 +/** DMA2D_INLINK_START_CH2 : R/W/SC; bitpos: [22]; default: 0; * Set this bit to start dealing with the inlink descriptors. */ -#define DMA2D_INLINK_START_CH1 (BIT(22)) -#define DMA2D_INLINK_START_CH1_M (DMA2D_INLINK_START_CH1_V << DMA2D_INLINK_START_CH1_S) -#define DMA2D_INLINK_START_CH1_V 0x00000001U -#define DMA2D_INLINK_START_CH1_S 22 -/** DMA2D_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0; +#define DMA2D_INLINK_START_CH2 (BIT(22)) +#define DMA2D_INLINK_START_CH2_M (DMA2D_INLINK_START_CH2_V << DMA2D_INLINK_START_CH2_S) +#define DMA2D_INLINK_START_CH2_V 0x00000001U +#define DMA2D_INLINK_START_CH2_S 22 +/** DMA2D_INLINK_RESTART_CH2 : R/W/SC; bitpos: [23]; default: 0; * Set this bit to mount a new inlink descriptor. */ -#define DMA2D_INLINK_RESTART_CH1 (BIT(23)) -#define DMA2D_INLINK_RESTART_CH1_M (DMA2D_INLINK_RESTART_CH1_V << DMA2D_INLINK_RESTART_CH1_S) -#define DMA2D_INLINK_RESTART_CH1_V 0x00000001U -#define DMA2D_INLINK_RESTART_CH1_S 23 -/** DMA2D_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1; +#define DMA2D_INLINK_RESTART_CH2 (BIT(23)) +#define DMA2D_INLINK_RESTART_CH2_M (DMA2D_INLINK_RESTART_CH2_V << DMA2D_INLINK_RESTART_CH2_S) +#define DMA2D_INLINK_RESTART_CH2_V 0x00000001U +#define DMA2D_INLINK_RESTART_CH2_S 23 +/** DMA2D_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1; * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is * working. */ -#define DMA2D_INLINK_PARK_CH1 (BIT(24)) -#define DMA2D_INLINK_PARK_CH1_M (DMA2D_INLINK_PARK_CH1_V << DMA2D_INLINK_PARK_CH1_S) -#define DMA2D_INLINK_PARK_CH1_V 0x00000001U -#define DMA2D_INLINK_PARK_CH1_S 24 +#define DMA2D_INLINK_PARK_CH2 (BIT(24)) +#define DMA2D_INLINK_PARK_CH2_M (DMA2D_INLINK_PARK_CH2_V << DMA2D_INLINK_PARK_CH2_S) +#define DMA2D_INLINK_PARK_CH2_V 0x00000001U +#define DMA2D_INLINK_PARK_CH2_S 24 -/** DMA2D_IN_LINK_ADDR_CH1_REG register - * Configures the rx descriptor address of channel 0 +/** DMA2D_IN_LINK_ADDR_CH2_REG register + * Configures the rx descriptor address of channel 2 */ -#define DMA2D_IN_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x620) -/** DMA2D_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; +#define DMA2D_IN_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x720) +/** DMA2D_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; * This register stores the first inlink descriptor's address. */ -#define DMA2D_INLINK_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH1_M (DMA2D_INLINK_ADDR_CH1_V << DMA2D_INLINK_ADDR_CH1_S) -#define DMA2D_INLINK_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH1_S 0 +#define DMA2D_INLINK_ADDR_CH2 0xFFFFFFFFU +#define DMA2D_INLINK_ADDR_CH2_M (DMA2D_INLINK_ADDR_CH2_V << DMA2D_INLINK_ADDR_CH2_S) +#define DMA2D_INLINK_ADDR_CH2_V 0xFFFFFFFFU +#define DMA2D_INLINK_ADDR_CH2_S 0 -/** DMA2D_IN_STATE_CH1_REG register - * Represents the working status of the rx descriptor of channel 0 +/** DMA2D_IN_STATE_CH2_REG register + * Represents the working status of the rx descriptor of channel 2 */ -#define DMA2D_IN_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x624) -/** DMA2D_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; +#define DMA2D_IN_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x724) +/** DMA2D_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; * This register stores the current inlink descriptor's address. */ -#define DMA2D_INLINK_DSCR_ADDR_CH1 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH1_M (DMA2D_INLINK_DSCR_ADDR_CH1_V << DMA2D_INLINK_DSCR_ADDR_CH1_S) -#define DMA2D_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH1_S 0 -/** DMA2D_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; +#define DMA2D_INLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define DMA2D_INLINK_DSCR_ADDR_CH2_M (DMA2D_INLINK_DSCR_ADDR_CH2_V << DMA2D_INLINK_DSCR_ADDR_CH2_S) +#define DMA2D_INLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define DMA2D_INLINK_DSCR_ADDR_CH2_S 0 +/** DMA2D_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; * reserved */ -#define DMA2D_IN_DSCR_STATE_CH1 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH1_M (DMA2D_IN_DSCR_STATE_CH1_V << DMA2D_IN_DSCR_STATE_CH1_S) -#define DMA2D_IN_DSCR_STATE_CH1_V 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH1_S 18 -/** DMA2D_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; +#define DMA2D_IN_DSCR_STATE_CH2 0x00000003U +#define DMA2D_IN_DSCR_STATE_CH2_M (DMA2D_IN_DSCR_STATE_CH2_V << DMA2D_IN_DSCR_STATE_CH2_S) +#define DMA2D_IN_DSCR_STATE_CH2_V 0x00000003U +#define DMA2D_IN_DSCR_STATE_CH2_S 18 +/** DMA2D_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; * reserved */ -#define DMA2D_IN_STATE_CH1 0x00000007U -#define DMA2D_IN_STATE_CH1_M (DMA2D_IN_STATE_CH1_V << DMA2D_IN_STATE_CH1_S) -#define DMA2D_IN_STATE_CH1_V 0x00000007U -#define DMA2D_IN_STATE_CH1_S 20 -/** DMA2D_IN_RESET_AVAIL_CH1 : RO; bitpos: [23]; default: 1; +#define DMA2D_IN_STATE_CH2 0x00000007U +#define DMA2D_IN_STATE_CH2_M (DMA2D_IN_STATE_CH2_V << DMA2D_IN_STATE_CH2_S) +#define DMA2D_IN_STATE_CH2_V 0x00000007U +#define DMA2D_IN_STATE_CH2_S 20 +/** DMA2D_IN_RESET_AVAIL_CH2 : RO; bitpos: [23]; default: 1; * This register indicate that if the channel reset is safety. */ -#define DMA2D_IN_RESET_AVAIL_CH1 (BIT(23)) -#define DMA2D_IN_RESET_AVAIL_CH1_M (DMA2D_IN_RESET_AVAIL_CH1_V << DMA2D_IN_RESET_AVAIL_CH1_S) -#define DMA2D_IN_RESET_AVAIL_CH1_V 0x00000001U -#define DMA2D_IN_RESET_AVAIL_CH1_S 23 +#define DMA2D_IN_RESET_AVAIL_CH2 (BIT(23)) +#define DMA2D_IN_RESET_AVAIL_CH2_M (DMA2D_IN_RESET_AVAIL_CH2_V << DMA2D_IN_RESET_AVAIL_CH2_S) +#define DMA2D_IN_RESET_AVAIL_CH2_V 0x00000001U +#define DMA2D_IN_RESET_AVAIL_CH2_S 23 -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 0 +/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG register + * Represents the address associated with the inlink descriptor of channel 2 */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x628) -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x728) +/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; * This register stores the address of the inlink descriptor when the EOF bit in this * descriptor is 1. */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S) -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S 0 +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S) +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S 0 -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 0 +/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG register + * Represents the address associated with the inlink descriptor of channel 2 */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x62c) -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x72c) +/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; * This register stores the address of the inlink descriptor when there are some * errors in current receiving data. */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S) -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S 0 +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S) +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S 0 -/** DMA2D_IN_DSCR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 0 +/** DMA2D_IN_DSCR_CH2_REG register + * Represents the address associated with the inlink descriptor of channel 2 */ -#define DMA2D_IN_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x630) -/** DMA2D_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; +#define DMA2D_IN_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x730) +/** DMA2D_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; * The address of the next inlink descriptor address x. */ -#define DMA2D_INLINK_DSCR_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH1_M (DMA2D_INLINK_DSCR_CH1_V << DMA2D_INLINK_DSCR_CH1_S) -#define DMA2D_INLINK_DSCR_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH1_S 0 +#define DMA2D_INLINK_DSCR_CH2 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_CH2_M (DMA2D_INLINK_DSCR_CH2_V << DMA2D_INLINK_DSCR_CH2_S) +#define DMA2D_INLINK_DSCR_CH2_V 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_CH2_S 0 -/** DMA2D_IN_DSCR_BF0_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 0 +/** DMA2D_IN_DSCR_BF0_CH2_REG register + * Represents the address associated with the inlink descriptor of channel 2 */ -#define DMA2D_IN_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x634) -/** DMA2D_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; +#define DMA2D_IN_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x734) +/** DMA2D_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; * The address of the last inlink descriptor's next address x-1. */ -#define DMA2D_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH1_M (DMA2D_INLINK_DSCR_BF0_CH1_V << DMA2D_INLINK_DSCR_BF0_CH1_S) -#define DMA2D_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH1_S 0 +#define DMA2D_INLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF0_CH2_M (DMA2D_INLINK_DSCR_BF0_CH2_V << DMA2D_INLINK_DSCR_BF0_CH2_S) +#define DMA2D_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF0_CH2_S 0 -/** DMA2D_IN_DSCR_BF1_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 0 +/** DMA2D_IN_DSCR_BF1_CH2_REG register + * Represents the address associated with the inlink descriptor of channel 2 */ -#define DMA2D_IN_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x638) -/** DMA2D_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; +#define DMA2D_IN_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x738) +/** DMA2D_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; * The address of the second-to-last inlink descriptor's next address x-2. */ -#define DMA2D_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH1_M (DMA2D_INLINK_DSCR_BF1_CH1_V << DMA2D_INLINK_DSCR_BF1_CH1_S) -#define DMA2D_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH1_S 0 +#define DMA2D_INLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF1_CH2_M (DMA2D_INLINK_DSCR_BF1_CH2_V << DMA2D_INLINK_DSCR_BF1_CH2_S) +#define DMA2D_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF1_CH2_S 0 -/** DMA2D_IN_PERI_SEL_CH1_REG register - * Configures the rx peripheral of channel 0 +/** DMA2D_IN_PERI_SEL_CH2_REG register + * Configures the rx peripheral of channel 2 */ -#define DMA2D_IN_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x63c) -/** DMA2D_IN_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7; +#define DMA2D_IN_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x73c) +/** DMA2D_IN_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7; * This register is used to select peripheral for Rx channel 0: jpeg 1: * display-1 2: display-2 7: no choose */ -#define DMA2D_IN_PERI_SEL_CH1 0x00000007U -#define DMA2D_IN_PERI_SEL_CH1_M (DMA2D_IN_PERI_SEL_CH1_V << DMA2D_IN_PERI_SEL_CH1_S) -#define DMA2D_IN_PERI_SEL_CH1_V 0x00000007U -#define DMA2D_IN_PERI_SEL_CH1_S 0 +#define DMA2D_IN_PERI_SEL_CH2 0x00000007U +#define DMA2D_IN_PERI_SEL_CH2_M (DMA2D_IN_PERI_SEL_CH2_V << DMA2D_IN_PERI_SEL_CH2_S) +#define DMA2D_IN_PERI_SEL_CH2_V 0x00000007U +#define DMA2D_IN_PERI_SEL_CH2_S 0 -/** DMA2D_IN_ARB_CH1_REG register - * Configures the rx arbiter of channel 0 +/** DMA2D_IN_ARB_CH2_REG register + * Configures the rx arbiter of channel 2 */ -#define DMA2D_IN_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x640) -/** DMA2D_IN_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1; +#define DMA2D_IN_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x740) +/** DMA2D_IN_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1; * Set the max number of token count of arbiter */ -#define DMA2D_IN_ARB_TOKEN_NUM_CH1 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH1_M (DMA2D_IN_ARB_TOKEN_NUM_CH1_V << DMA2D_IN_ARB_TOKEN_NUM_CH1_S) -#define DMA2D_IN_ARB_TOKEN_NUM_CH1_V 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH1_S 0 -/** DMA2D_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [4]; default: 1; +#define DMA2D_IN_ARB_TOKEN_NUM_CH2 0x0000000FU +#define DMA2D_IN_ARB_TOKEN_NUM_CH2_M (DMA2D_IN_ARB_TOKEN_NUM_CH2_V << DMA2D_IN_ARB_TOKEN_NUM_CH2_S) +#define DMA2D_IN_ARB_TOKEN_NUM_CH2_V 0x0000000FU +#define DMA2D_IN_ARB_TOKEN_NUM_CH2_S 0 +/** DMA2D_IN_ARB_PRIORITY_CH2 : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ -#define DMA2D_IN_ARB_PRIORITY_CH1 (BIT(4)) -#define DMA2D_IN_ARB_PRIORITY_CH1_M (DMA2D_IN_ARB_PRIORITY_CH1_V << DMA2D_IN_ARB_PRIORITY_CH1_S) -#define DMA2D_IN_ARB_PRIORITY_CH1_V 0x00000001U -#define DMA2D_IN_ARB_PRIORITY_CH1_S 4 +#define DMA2D_IN_ARB_PRIORITY_CH2 0x0000000FU +#define DMA2D_IN_ARB_PRIORITY_CH2_M (DMA2D_IN_ARB_PRIORITY_CH2_V << DMA2D_IN_ARB_PRIORITY_CH2_S) +#define DMA2D_IN_ARB_PRIORITY_CH2_V 0x0000000FU +#define DMA2D_IN_ARB_PRIORITY_CH2_S 4 -/** DMA2D_IN_RO_STATUS_CH1_REG register - * Represents the status of the rx reorder module of channel 0 +/** DMA2D_IN_RO_STATUS_CH2_REG register + * Represents the status of the rx reorder module of channel 2 */ -#define DMA2D_IN_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x644) -/** DMA2D_INFIFO_RO_CNT_CH1 : RO; bitpos: [4:0]; default: 0; +#define DMA2D_IN_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x744) +/** DMA2D_INFIFO_RO_CNT_CH2 : RO; bitpos: [4:0]; default: 0; * The register stores the byte number of the data in color convert Rx FIFO for * channel 0. */ -#define DMA2D_INFIFO_RO_CNT_CH1 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH1_M (DMA2D_INFIFO_RO_CNT_CH1_V << DMA2D_INFIFO_RO_CNT_CH1_S) -#define DMA2D_INFIFO_RO_CNT_CH1_V 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH1_S 0 -/** DMA2D_IN_RO_WR_STATE_CH1 : RO; bitpos: [6:5]; default: 0; +#define DMA2D_INFIFO_RO_CNT_CH2 0x0000001FU +#define DMA2D_INFIFO_RO_CNT_CH2_M (DMA2D_INFIFO_RO_CNT_CH2_V << DMA2D_INFIFO_RO_CNT_CH2_S) +#define DMA2D_INFIFO_RO_CNT_CH2_V 0x0000001FU +#define DMA2D_INFIFO_RO_CNT_CH2_S 0 +/** DMA2D_IN_RO_WR_STATE_CH2 : RO; bitpos: [6:5]; default: 0; * The register stores the state of read ram of reorder */ -#define DMA2D_IN_RO_WR_STATE_CH1 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH1_M (DMA2D_IN_RO_WR_STATE_CH1_V << DMA2D_IN_RO_WR_STATE_CH1_S) -#define DMA2D_IN_RO_WR_STATE_CH1_V 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH1_S 5 -/** DMA2D_IN_RO_RD_STATE_CH1 : RO; bitpos: [8:7]; default: 0; +#define DMA2D_IN_RO_WR_STATE_CH2 0x00000003U +#define DMA2D_IN_RO_WR_STATE_CH2_M (DMA2D_IN_RO_WR_STATE_CH2_V << DMA2D_IN_RO_WR_STATE_CH2_S) +#define DMA2D_IN_RO_WR_STATE_CH2_V 0x00000003U +#define DMA2D_IN_RO_WR_STATE_CH2_S 5 +/** DMA2D_IN_RO_RD_STATE_CH2 : RO; bitpos: [8:7]; default: 0; * The register stores the state of write ram of reorder */ -#define DMA2D_IN_RO_RD_STATE_CH1 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH1_M (DMA2D_IN_RO_RD_STATE_CH1_V << DMA2D_IN_RO_RD_STATE_CH1_S) -#define DMA2D_IN_RO_RD_STATE_CH1_V 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH1_S 7 -/** DMA2D_IN_PIXEL_BYTE_CH1 : RO; bitpos: [12:9]; default: 0; +#define DMA2D_IN_RO_RD_STATE_CH2 0x00000003U +#define DMA2D_IN_RO_RD_STATE_CH2_M (DMA2D_IN_RO_RD_STATE_CH2_V << DMA2D_IN_RO_RD_STATE_CH2_S) +#define DMA2D_IN_RO_RD_STATE_CH2_V 0x00000003U +#define DMA2D_IN_RO_RD_STATE_CH2_S 7 +/** DMA2D_IN_PIXEL_BYTE_CH2 : RO; bitpos: [12:9]; default: 0; * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes */ -#define DMA2D_IN_PIXEL_BYTE_CH1 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH1_M (DMA2D_IN_PIXEL_BYTE_CH1_V << DMA2D_IN_PIXEL_BYTE_CH1_S) -#define DMA2D_IN_PIXEL_BYTE_CH1_V 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH1_S 9 -/** DMA2D_IN_BURST_BLOCK_NUM_CH1 : RO; bitpos: [16:13]; default: 0; +#define DMA2D_IN_PIXEL_BYTE_CH2 0x0000000FU +#define DMA2D_IN_PIXEL_BYTE_CH2_M (DMA2D_IN_PIXEL_BYTE_CH2_V << DMA2D_IN_PIXEL_BYTE_CH2_S) +#define DMA2D_IN_PIXEL_BYTE_CH2_V 0x0000000FU +#define DMA2D_IN_PIXEL_BYTE_CH2_S 9 +/** DMA2D_IN_BURST_BLOCK_NUM_CH2 : RO; bitpos: [16:13]; default: 0; * the number of macro blocks contained in a burst of data at RX channel */ -#define DMA2D_IN_BURST_BLOCK_NUM_CH1 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH1_M (DMA2D_IN_BURST_BLOCK_NUM_CH1_V << DMA2D_IN_BURST_BLOCK_NUM_CH1_S) -#define DMA2D_IN_BURST_BLOCK_NUM_CH1_V 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH1_S 13 +#define DMA2D_IN_BURST_BLOCK_NUM_CH2 0x0000000FU +#define DMA2D_IN_BURST_BLOCK_NUM_CH2_M (DMA2D_IN_BURST_BLOCK_NUM_CH2_V << DMA2D_IN_BURST_BLOCK_NUM_CH2_S) +#define DMA2D_IN_BURST_BLOCK_NUM_CH2_V 0x0000000FU +#define DMA2D_IN_BURST_BLOCK_NUM_CH2_S 13 -/** DMA2D_IN_ETM_CONF_CH1_REG register - * Configures the rx etm of channel 0 +/** DMA2D_IN_ETM_CONF_CH2_REG register + * Configures the rx etm of channel 2 */ -#define DMA2D_IN_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x648) -/** DMA2D_IN_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0; +#define DMA2D_IN_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x76c) +/** DMA2D_IN_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0; * Configures the enable of the etm function, 1 is enable. */ -#define DMA2D_IN_ETM_EN_CH1 (BIT(0)) -#define DMA2D_IN_ETM_EN_CH1_M (DMA2D_IN_ETM_EN_CH1_V << DMA2D_IN_ETM_EN_CH1_S) -#define DMA2D_IN_ETM_EN_CH1_V 0x00000001U -#define DMA2D_IN_ETM_EN_CH1_S 0 -/** DMA2D_IN_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0; +#define DMA2D_IN_ETM_EN_CH2 (BIT(0)) +#define DMA2D_IN_ETM_EN_CH2_M (DMA2D_IN_ETM_EN_CH2_V << DMA2D_IN_ETM_EN_CH2_S) +#define DMA2D_IN_ETM_EN_CH2_V 0x00000001U +#define DMA2D_IN_ETM_EN_CH2_S 0 +/** DMA2D_IN_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0; * Configures the enable of the descriptors loop etm function, 1 is enable. */ -#define DMA2D_IN_ETM_LOOP_EN_CH1 (BIT(1)) -#define DMA2D_IN_ETM_LOOP_EN_CH1_M (DMA2D_IN_ETM_LOOP_EN_CH1_V << DMA2D_IN_ETM_LOOP_EN_CH1_S) -#define DMA2D_IN_ETM_LOOP_EN_CH1_V 0x00000001U -#define DMA2D_IN_ETM_LOOP_EN_CH1_S 1 -/** DMA2D_IN_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1; +#define DMA2D_IN_ETM_LOOP_EN_CH2 (BIT(1)) +#define DMA2D_IN_ETM_LOOP_EN_CH2_M (DMA2D_IN_ETM_LOOP_EN_CH2_V << DMA2D_IN_ETM_LOOP_EN_CH2_S) +#define DMA2D_IN_ETM_LOOP_EN_CH2_V 0x00000001U +#define DMA2D_IN_ETM_LOOP_EN_CH2_S 1 +/** DMA2D_IN_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1; * Configures the maximum number of cacheable descriptors. */ -#define DMA2D_IN_DSCR_TASK_MAK_CH1 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH1_M (DMA2D_IN_DSCR_TASK_MAK_CH1_V << DMA2D_IN_DSCR_TASK_MAK_CH1_S) -#define DMA2D_IN_DSCR_TASK_MAK_CH1_V 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH1_S 2 +#define DMA2D_IN_DSCR_TASK_MAK_CH2 0x00000003U +#define DMA2D_IN_DSCR_TASK_MAK_CH2_M (DMA2D_IN_DSCR_TASK_MAK_CH2_V << DMA2D_IN_DSCR_TASK_MAK_CH2_S) +#define DMA2D_IN_DSCR_TASK_MAK_CH2_V 0x00000003U +#define DMA2D_IN_DSCR_TASK_MAK_CH2_S 2 /** DMA2D_AXI_ERR_REG register * Represents the status of th axi bus @@ -5257,7 +7177,7 @@ extern "C" { * register version. */ #define DMA2D_DATE_REG (DR_REG_DMA2D_BASE + 0xa2c) -/** DMA2D_DATE : R/W; bitpos: [31:0]; default: 36716816; +/** DMA2D_DATE : R/W; bitpos: [31:0]; default: 37822864; * register version. */ #define DMA2D_DATE 0xFFFFFFFFU diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h index 30fef532dbdb..7105d670bcf9 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h @@ -10,11 +10,8 @@ extern "C" { #endif -//TODO: IDF-13427 - -/** Group: out */ /** Type of out_conf0_chn register - * Configures the tx direction of channel 0 + * Configures the tx direction of channel n */ typedef union { struct { @@ -48,7 +45,7 @@ typedef union { */ uint32_t out_loop_test_chn:1; /** out_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 + * Block size of Tx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 * bytes 4: 128 bytes */ uint32_t out_mem_burst_length_chn:3; @@ -92,7 +89,7 @@ typedef union { } dma2d_out_conf0_chn_reg_t; /** Type of out_int_raw_chn register - * Raw interrupt status of TX channel 0 + * Raw interrupt status of TX channel n */ typedef union { struct { @@ -160,7 +157,7 @@ typedef union { } dma2d_out_int_raw_chn_reg_t; /** Type of out_int_ena_chn register - * Interrupt enable bits of TX channel 0 + * Interrupt enable bits of TX channel n */ typedef union { struct { @@ -222,7 +219,7 @@ typedef union { } dma2d_out_int_ena_chn_reg_t; /** Type of out_int_st_chn register - * Masked interrupt status of TX channel 0 + * Masked interrupt status of TX channel n */ typedef union { struct { @@ -284,7 +281,7 @@ typedef union { } dma2d_out_int_st_chn_reg_t; /** Type of out_int_clr_chn register - * Interrupt clear bits of TX channel 0 + * Interrupt clear bits of TX channel n */ typedef union { struct { @@ -346,20 +343,20 @@ typedef union { } dma2d_out_int_clr_chn_reg_t; /** Type of outfifo_status_chn register - * Represents the status of the tx fifo of channel 0 + * Represents the status of the tx fifo of channel n */ typedef union { struct { /** outfifo_full_l2_chn : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Tx FIFO full signal for Tx channel n. */ uint32_t outfifo_full_l2_chn:1; /** outfifo_empty_l2_chn : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Tx FIFO empty signal for Tx channel n. */ uint32_t outfifo_empty_l2_chn:1; /** outfifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Tx FIFO for Tx channel n. */ uint32_t outfifo_cnt_l2_chn:4; uint32_t reserved_6:1; @@ -396,27 +393,27 @@ typedef union { */ uint32_t out_remain_under_8b_chn:1; /** outfifo_full_l1_chn : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Tx FIFO full signal for Tx channel n. */ uint32_t outfifo_full_l1_chn:1; /** outfifo_empty_l1_chn : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Tx FIFO empty signal for Tx channel n. */ uint32_t outfifo_empty_l1_chn:1; /** outfifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Tx FIFO for Tx channel n. */ uint32_t outfifo_cnt_l1_chn:5; /** outfifo_full_l3_chn : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Tx FIFO full signal for Tx channel n. */ uint32_t outfifo_full_l3_chn:1; /** outfifo_empty_l3_chn : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Tx FIFO empty signal for Tx channel n. */ uint32_t outfifo_empty_l3_chn:1; /** outfifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Tx FIFO for Tx channel n. */ uint32_t outfifo_cnt_l3_chn:5; uint32_t reserved_29:3; @@ -425,7 +422,7 @@ typedef union { } dma2d_outfifo_status_chn_reg_t; /** Type of out_push_chn register - * Configures the tx fifo of channel 0 + * Configures the tx fifo of channel n */ typedef union { struct { @@ -443,7 +440,7 @@ typedef union { } dma2d_out_push_chn_reg_t; /** Type of out_link_conf_chn register - * Configures the tx descriptor operations of channel 0 + * Configures the tx descriptor operations of channel n */ typedef union { struct { @@ -471,7 +468,7 @@ typedef union { } dma2d_out_link_conf_chn_reg_t; /** Type of out_link_addr_chn register - * Configures the tx descriptor address of channel 0 + * Configures the tx descriptor address of channel n */ typedef union { struct { @@ -484,7 +481,7 @@ typedef union { } dma2d_out_link_addr_chn_reg_t; /** Type of out_state_chn register - * Represents the working status of the tx descriptor of channel 0 + * Represents the working status of the tx descriptor of channel n */ typedef union { struct { @@ -510,7 +507,7 @@ typedef union { } dma2d_out_state_chn_reg_t; /** Type of out_eof_des_addr_chn register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel n */ typedef union { struct { @@ -524,7 +521,7 @@ typedef union { } dma2d_out_eof_des_addr_chn_reg_t; /** Type of out_dscr_chn register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel n */ typedef union { struct { @@ -537,7 +534,7 @@ typedef union { } dma2d_out_dscr_chn_reg_t; /** Type of out_dscr_bf0_chn register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel n */ typedef union { struct { @@ -550,7 +547,7 @@ typedef union { } dma2d_out_dscr_bf0_chn_reg_t; /** Type of out_dscr_bf1_chn register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel n */ typedef union { struct { @@ -563,7 +560,7 @@ typedef union { } dma2d_out_dscr_bf1_chn_reg_t; /** Type of out_peri_sel_chn register - * Configures the tx peripheral of channel 0 + * Configures the tx peripheral of channel n */ typedef union { struct { @@ -578,7 +575,7 @@ typedef union { } dma2d_out_peri_sel_chn_reg_t; /** Type of out_arb_chn register - * Configures the tx arbiter of channel 0 + * Configures the tx arbiter of channel n */ typedef union { struct { @@ -586,17 +583,17 @@ typedef union { * Set the max number of token count of arbiter */ uint32_t out_arb_token_num_chn:4; - /** out_arb_priority_chn : R/W; bitpos: [5:4]; default: 1; + /** out_arb_priority_chn : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ - uint32_t out_arb_priority_chn:2; - uint32_t reserved_6:26; + uint32_t out_arb_priority_chn:4; + uint32_t reserved_8:24; }; uint32_t val; } dma2d_out_arb_chn_reg_t; /** Type of out_ro_status_chn register - * Represents the status of the tx reorder module of channel 0 + * Represents the status of the tx reorder module of channel n */ typedef union { struct { @@ -628,7 +625,7 @@ typedef union { } dma2d_out_ro_status_chn_reg_t; /** Type of out_ro_pd_conf_chn register - * Configures the tx reorder memory of channel 0 + * Configures the tx reorder memory of channel n */ typedef union { struct { @@ -652,7 +649,7 @@ typedef union { } dma2d_out_ro_pd_conf_chn_reg_t; /** Type of out_color_convert_chn register - * Configures the tx color convert of channel 0 + * Configures the tx color convert of channel n */ typedef union { struct { @@ -678,7 +675,7 @@ typedef union { } dma2d_out_color_convert_chn_reg_t; /** Type of out_scramble_chn register - * Configures the tx scramble of channel 0 + * Configures the tx scramble of channel n */ typedef union { struct { @@ -693,7 +690,7 @@ typedef union { } dma2d_out_scramble_chn_reg_t; /** Type of out_etm_conf_chn register - * Configures the tx etm of channel 0 + * Configures the tx etm of channel n */ typedef union { struct { @@ -732,10 +729,8 @@ typedef union { uint32_t val; } dma2d_out_dscr_port_blk_chn_reg_t; - -/** Group: in */ /** Type of in_conf0_chn register - * Configures the rx direction of channel 0 + * Configures the rx direction of channel n */ typedef union { struct { @@ -808,7 +803,7 @@ typedef union { } dma2d_in_conf0_chn_reg_t; /** Type of in_int_raw_chn register - * Raw interrupt status of RX channel 0 + * Raw interrupt status of RX channel n */ typedef union { struct { @@ -880,7 +875,7 @@ typedef union { } dma2d_in_int_raw_chn_reg_t; /** Type of in_int_ena_chn register - * Interrupt enable bits of RX channel 0 + * Interrupt enable bits of RX channel n */ typedef union { struct { @@ -946,7 +941,7 @@ typedef union { } dma2d_in_int_ena_chn_reg_t; /** Type of in_int_st_chn register - * Masked interrupt status of RX channel 0 + * Masked interrupt status of RX channel n */ typedef union { struct { @@ -1012,7 +1007,7 @@ typedef union { } dma2d_in_int_st_chn_reg_t; /** Type of in_int_clr_chn register - * Interrupt clear bits of RX channel 0 + * Interrupt clear bits of RX channel n */ typedef union { struct { @@ -1078,20 +1073,20 @@ typedef union { } dma2d_in_int_clr_chn_reg_t; /** Type of infifo_status_chn register - * Represents the status of the rx fifo of channel 0 + * Represents the status of the rx fifo of channel n */ typedef union { struct { /** infifo_full_l2_chn : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. + * Rx FIFO full signal for Rx channel n. */ uint32_t infifo_full_l2_chn:1; /** infifo_empty_l2_chn : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. + * Rx FIFO empty signal for Rx channel n. */ uint32_t infifo_empty_l2_chn:1; /** infifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. + * The register stores the byte number of the data in Rx FIFO for Rx channel n. */ uint32_t infifo_cnt_l2_chn:4; uint32_t reserved_6:1; @@ -1128,27 +1123,27 @@ typedef union { */ uint32_t in_remain_under_8b_chn:1; /** infifo_full_l1_chn : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Rx FIFO full signal for Tx channel n. */ uint32_t infifo_full_l1_chn:1; /** infifo_empty_l1_chn : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Rx FIFO empty signal for Tx channel n. */ uint32_t infifo_empty_l1_chn:1; /** infifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Rx FIFO for Rx channel n. */ uint32_t infifo_cnt_l1_chn:5; /** infifo_full_l3_chn : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Rx FIFO full signal for Rx channel n. */ uint32_t infifo_full_l3_chn:1; /** infifo_empty_l3_chn : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Rx FIFO empty signal for Rx channel n. */ uint32_t infifo_empty_l3_chn:1; /** infifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Rx FIFO for Rx channel n. */ uint32_t infifo_cnt_l3_chn:5; uint32_t reserved_29:3; @@ -1157,7 +1152,7 @@ typedef union { } dma2d_infifo_status_chn_reg_t; /** Type of in_pop_chn register - * Configures the rx fifo of channel 0 + * Configures the rx fifo of channel n */ typedef union { struct { @@ -1175,7 +1170,7 @@ typedef union { } dma2d_in_pop_chn_reg_t; /** Type of in_link_conf_chn register - * Configures the rx descriptor operations of channel 0 + * Configures the rx descriptor operations of channel n */ typedef union { struct { @@ -1208,7 +1203,7 @@ typedef union { } dma2d_in_link_conf_chn_reg_t; /** Type of in_link_addr_chn register - * Configures the rx descriptor address of channel 0 + * Configures the rx descriptor address of channel n */ typedef union { struct { @@ -1221,7 +1216,7 @@ typedef union { } dma2d_in_link_addr_chn_reg_t; /** Type of in_state_chn register - * Represents the working status of the rx descriptor of channel 0 + * Represents the working status of the rx descriptor of channel n */ typedef union { struct { @@ -1247,7 +1242,7 @@ typedef union { } dma2d_in_state_chn_reg_t; /** Type of in_suc_eof_des_addr_chn register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel n */ typedef union { struct { @@ -1261,7 +1256,7 @@ typedef union { } dma2d_in_suc_eof_des_addr_chn_reg_t; /** Type of in_err_eof_des_addr_chn register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel n */ typedef union { struct { @@ -1275,7 +1270,7 @@ typedef union { } dma2d_in_err_eof_des_addr_chn_reg_t; /** Type of in_dscr_chn register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel n */ typedef union { struct { @@ -1288,7 +1283,7 @@ typedef union { } dma2d_in_dscr_chn_reg_t; /** Type of in_dscr_bf0_chn register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel n */ typedef union { struct { @@ -1301,7 +1296,7 @@ typedef union { } dma2d_in_dscr_bf0_chn_reg_t; /** Type of in_dscr_bf1_chn register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel n */ typedef union { struct { @@ -1314,7 +1309,7 @@ typedef union { } dma2d_in_dscr_bf1_chn_reg_t; /** Type of in_peri_sel_chn register - * Configures the rx peripheral of channel 0 + * Configures the rx peripheral of channel n */ typedef union { struct { @@ -1329,7 +1324,7 @@ typedef union { } dma2d_in_peri_sel_chn_reg_t; /** Type of in_arb_chn register - * Configures the rx arbiter of channel 0 + * Configures the rx arbiter of channel n */ typedef union { struct { @@ -1337,17 +1332,17 @@ typedef union { * Set the max number of token count of arbiter */ uint32_t in_arb_token_num_chn:4; - /** in_arb_priority_chn : R/W; bitpos: [4]; default: 1; + /** in_arb_priority_chn : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ - uint32_t in_arb_priority_chn:1; - uint32_t reserved_5:27; + uint32_t in_arb_priority_chn:4; + uint32_t reserved_8:24; }; uint32_t val; } dma2d_in_arb_chn_reg_t; /** Type of in_ro_status_chn register - * Represents the status of the rx reorder module of channel 0 + * Represents the status of the rx reorder module of channel n */ typedef union { struct { @@ -1379,7 +1374,7 @@ typedef union { } dma2d_in_ro_status_chn_reg_t; /** Type of in_ro_pd_conf_chn register - * Configures the rx reorder memory of channel 0 + * Configures the rx reorder memory of channel n */ typedef union { struct { @@ -1403,13 +1398,13 @@ typedef union { } dma2d_in_ro_pd_conf_chn_reg_t; /** Type of in_color_convert_chn register - * Configures the tx color convert of channel 0 + * Configures the Rx color convert of channel n */ typedef union { struct { /** in_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0; * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly + * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 */ uint32_t in_color_output_sel_chn:2; /** in_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0; @@ -1428,7 +1423,7 @@ typedef union { } dma2d_in_color_convert_chn_reg_t; /** Type of in_scramble_chn register - * Configures the rx scramble of channel 0 + * Configures the rx scramble of channel n */ typedef union { struct { @@ -1448,7 +1443,7 @@ typedef union { } dma2d_in_scramble_chn_reg_t; /** Type of in_etm_conf_chn register - * Configures the rx etm of channel 0 + * Configures the rx etm of channel n */ typedef union { struct { @@ -1469,8 +1464,6 @@ typedef union { uint32_t val; } dma2d_in_etm_conf_chn_reg_t; - -/** Group: Status Registers */ /** Type of axi_err register * Represents the status of th axi bus */ @@ -1514,7 +1507,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [31:0]; default: 36716816; + /** date : R/W; bitpos: [31:0]; default: 37822864; * register version. */ uint32_t date:32; @@ -1522,8 +1515,6 @@ typedef union { uint32_t val; } dma2d_date_reg_t; - -/** Group: Configuration Registers */ /** Type of rst_conf register * Configures the reset of axi */ @@ -1681,7 +1672,6 @@ typedef union { uint32_t val; } dma2d_rdn_eco_low_reg_t; - /** Type of in/out_color_param_h/m/l_chn register * Configures the rx/tx color convert parameter of channel n */ @@ -1713,12 +1703,14 @@ typedef union { uint32_t val[2]; } dma2d_color_param_reg_t; + typedef struct { volatile dma2d_color_param_reg_t param_h; volatile dma2d_color_param_reg_t param_m; volatile dma2d_color_param_reg_t param_l; } dma2d_color_param_group_chn_reg_t; + typedef struct { volatile dma2d_out_conf0_chn_reg_t out_conf0; volatile dma2d_out_int_raw_chn_reg_t out_int_raw; @@ -1746,32 +1738,6 @@ typedef struct { uint32_t reserved_out[36]; } dma2d_out_chn_reg_t; -typedef struct { - volatile dma2d_in_conf0_chn_reg_t in_conf0; - volatile dma2d_in_int_raw_chn_reg_t in_int_raw; - volatile dma2d_in_int_ena_chn_reg_t in_int_ena; - volatile dma2d_in_int_st_chn_reg_t in_int_st; - volatile dma2d_in_int_clr_chn_reg_t in_int_clr; - volatile dma2d_infifo_status_chn_reg_t infifo_status; - volatile dma2d_in_pop_chn_reg_t in_pop; - volatile dma2d_in_link_conf_chn_reg_t in_link_conf; - volatile dma2d_in_link_addr_chn_reg_t in_link_addr; - volatile dma2d_in_state_chn_reg_t in_state; - volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr; - volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr; - volatile dma2d_in_dscr_chn_reg_t in_dscr; - volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0; - volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1; - volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel; - volatile dma2d_in_arb_chn_reg_t in_arb; - volatile dma2d_in_ro_status_chn_reg_t in_ro_status; - volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; - volatile dma2d_in_color_convert_chn_reg_t in_color_convert; - volatile dma2d_in_scramble_chn_reg_t in_scramble; - volatile dma2d_color_param_group_chn_reg_t in_color_param_group; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; - uint32_t reserved_570[36]; -} dma2d_in_ch0_reg_t; typedef struct { volatile dma2d_in_conf0_chn_reg_t in_conf0; @@ -1792,16 +1758,20 @@ typedef struct { volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel; volatile dma2d_in_arb_chn_reg_t in_arb; volatile dma2d_in_ro_status_chn_reg_t in_ro_status; + volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; /* only exist on channel0 */ + volatile dma2d_in_color_convert_chn_reg_t in_color_convert; /* only exist on channel0 */ + volatile dma2d_in_scramble_chn_reg_t in_scramble; /* only exist on channel0 */ + volatile dma2d_color_param_group_chn_reg_t in_color_param_group; /* only exist on channel0 */ volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; - uint32_t reserved_64c[45]; -} dma2d_in_ch1_reg_t; + uint32_t reserved_in[36]; +} dma2d_in_chn_reg_t; + typedef struct dma2d_dev_t { - volatile dma2d_out_chn_reg_t out_channel[3]; - uint32_t reserved_300[128]; - volatile dma2d_in_ch0_reg_t in_channel0; - volatile dma2d_in_ch1_reg_t in_channel1; - uint32_t reserved_700[192]; + volatile dma2d_out_chn_reg_t out_channel[4]; + uint32_t reserved_400[64]; + volatile dma2d_in_chn_reg_t in_channel[3]; + uint32_t reserved_800[128]; volatile dma2d_axi_err_reg_t axi_err; volatile dma2d_rst_conf_reg_t rst_conf; volatile dma2d_intr_mem_start_addr_reg_t intr_mem_start_addr; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_eco5_struct.h deleted file mode 100644 index a3b88516fa41..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_eco5_struct.h +++ /dev/null @@ -1,772 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: SDM Configure Registers */ -/** Type of sigmadeltan register - * Duty Cycle Configure Register of SDMn - */ -typedef union { - struct { - /** sdn_in : R/W; bitpos: [7:0]; default: 0; - * This field is used to configure the duty cycle of sigma delta modulation output. - */ - uint32_t sdn_in:8; - /** sdn_prescale : R/W; bitpos: [15:8]; default: 255; - * This field is used to set a divider value to divide APB clock. - */ - uint32_t sdn_prescale:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} gpiosd_sigmadeltan_reg_t; - -/** Type of sigmadelta_misc register - * MISC Register - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** function_clk_en : R/W; bitpos: [30]; default: 0; - * Clock enable bit of sigma delta modulation. - */ - uint32_t function_clk_en:1; - /** spi_swap : R/W; bitpos: [31]; default: 0; - * Reserved. - */ - uint32_t spi_swap:1; - }; - uint32_t val; -} gpiosd_sigmadelta_misc_reg_t; - - -/** Group: Glitch filter Configure Registers */ -/** Type of glitch_filter_chn register - * Glitch Filter Configure Register of Channeln - */ -typedef union { - struct { - /** filter_ch0_en : R/W; bitpos: [0]; default: 0; - * Glitch Filter channel enable bit. - */ - uint32_t filter_ch0_en:1; - /** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0; - * Glitch Filter input io number. - */ - uint32_t filter_ch0_input_io_num:6; - /** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0; - * Glitch Filter window threshold. - */ - uint32_t filter_ch0_window_thres:6; - /** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0; - * Glitch Filter window width. - */ - uint32_t filter_ch0_window_width:6; - uint32_t reserved_19:13; - }; - uint32_t val; -} gpiosd_glitch_filter_chn_reg_t; - - -/** Group: Etm Configure Registers */ -/** Type of etm_event_chn_cfg register - * Etm Config register of Channeln - */ -typedef union { - struct { - /** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0; - * Etm event channel select gpio. - */ - uint32_t etm_ch0_event_sel:6; - uint32_t reserved_6:1; - /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0; - * Etm event send enable bit. - */ - uint32_t etm_ch0_event_en:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpiosd_etm_event_chn_cfg_reg_t; - -/** Type of etm_task_p0_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio0_en:1; - /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio0_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio1_en:1; - /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio1_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio2_en:1; - /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio2_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio3_en:1; - /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio3_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p0_cfg_reg_t; - -/** Type of etm_task_p1_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio4_en:1; - /** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio4_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio5_en:1; - /** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio5_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio6_en:1; - /** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio6_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio7_en:1; - /** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio7_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p1_cfg_reg_t; - -/** Type of etm_task_p2_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio8_en:1; - /** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio8_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio9_en:1; - /** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio9_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio10_en:1; - /** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio10_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio11_en:1; - /** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio11_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p2_cfg_reg_t; - -/** Type of etm_task_p3_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio12_en:1; - /** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio12_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio13_en:1; - /** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio13_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio14_en:1; - /** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio14_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio15_en:1; - /** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio15_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p3_cfg_reg_t; - -/** Type of etm_task_p4_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio16_en:1; - /** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio16_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio17_en:1; - /** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio17_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio18_en:1; - /** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio18_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio19_en:1; - /** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio19_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p4_cfg_reg_t; - -/** Type of etm_task_p5_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio20_en:1; - /** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio20_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio21_en:1; - /** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio21_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio22_en:1; - /** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio22_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio23_en:1; - /** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio23_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p5_cfg_reg_t; - -/** Type of etm_task_p6_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio24_en:1; - /** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio24_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio25_en:1; - /** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio25_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio26_en:1; - /** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio26_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio27_en:1; - /** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio27_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p6_cfg_reg_t; - -/** Type of etm_task_p7_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio28_en:1; - /** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio28_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio29_en:1; - /** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio29_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio30_en:1; - /** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio30_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio31_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio31_en:1; - /** etm_task_gpio31_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio31_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p7_cfg_reg_t; - -/** Type of etm_task_p8_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio32_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio32_en:1; - /** etm_task_gpio32_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio32_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio33_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio33_en:1; - /** etm_task_gpio33_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio33_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio34_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio34_en:1; - /** etm_task_gpio34_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio34_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio35_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio35_en:1; - /** etm_task_gpio35_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio35_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p8_cfg_reg_t; - -/** Type of etm_task_p9_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio36_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio36_en:1; - /** etm_task_gpio36_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio36_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio37_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio37_en:1; - /** etm_task_gpio37_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio37_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio38_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio38_en:1; - /** etm_task_gpio38_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio38_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio39_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio39_en:1; - /** etm_task_gpio39_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio39_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p9_cfg_reg_t; - -/** Type of etm_task_p10_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio40_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio40_en:1; - /** etm_task_gpio40_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio40_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio41_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio41_en:1; - /** etm_task_gpio41_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio41_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio42_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio42_en:1; - /** etm_task_gpio42_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio42_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio43_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio43_en:1; - /** etm_task_gpio43_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio43_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p10_cfg_reg_t; - -/** Type of etm_task_p11_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio44_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio44_en:1; - /** etm_task_gpio44_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio44_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio45_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio45_en:1; - /** etm_task_gpio45_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio45_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio46_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio46_en:1; - /** etm_task_gpio46_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio46_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio47_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio47_en:1; - /** etm_task_gpio47_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio47_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p11_cfg_reg_t; - -/** Type of etm_task_p12_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio48_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio48_en:1; - /** etm_task_gpio48_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio48_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio49_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio49_en:1; - /** etm_task_gpio49_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio49_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio50_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio50_en:1; - /** etm_task_gpio50_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio50_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio51_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio51_en:1; - /** etm_task_gpio51_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio51_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p12_cfg_reg_t; - -/** Type of etm_task_p13_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio52_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio52_en:1; - /** etm_task_gpio52_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio52_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio53_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio53_en:1; - /** etm_task_gpio53_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio53_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio54_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio54_en:1; - /** etm_task_gpio54_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio54_sel:3; - uint32_t reserved_20:12; - }; - uint32_t val; -} gpiosd_etm_task_p13_cfg_reg_t; - - -/** Group: Version Register */ -/** Type of version register - * Version Control Register - */ -typedef union { - struct { - /** gpio_sd_date : R/W; bitpos: [27:0]; default: 35663952; - * Version control register. - */ - uint32_t gpio_sd_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_version_reg_t; - - -typedef struct { - volatile gpiosd_sigmadeltan_reg_t sigmadeltan[8]; - uint32_t reserved_020; - volatile gpiosd_sigmadelta_misc_reg_t sigmadelta_misc; - uint32_t reserved_028[2]; - volatile gpiosd_glitch_filter_chn_reg_t glitch_filter_chn[8]; - uint32_t reserved_050[4]; - volatile gpiosd_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; - uint32_t reserved_080[8]; - volatile gpiosd_etm_task_p0_cfg_reg_t etm_task_p0_cfg; - volatile gpiosd_etm_task_p1_cfg_reg_t etm_task_p1_cfg; - volatile gpiosd_etm_task_p2_cfg_reg_t etm_task_p2_cfg; - volatile gpiosd_etm_task_p3_cfg_reg_t etm_task_p3_cfg; - volatile gpiosd_etm_task_p4_cfg_reg_t etm_task_p4_cfg; - volatile gpiosd_etm_task_p5_cfg_reg_t etm_task_p5_cfg; - volatile gpiosd_etm_task_p6_cfg_reg_t etm_task_p6_cfg; - volatile gpiosd_etm_task_p7_cfg_reg_t etm_task_p7_cfg; - volatile gpiosd_etm_task_p8_cfg_reg_t etm_task_p8_cfg; - volatile gpiosd_etm_task_p9_cfg_reg_t etm_task_p9_cfg; - volatile gpiosd_etm_task_p10_cfg_reg_t etm_task_p10_cfg; - volatile gpiosd_etm_task_p11_cfg_reg_t etm_task_p11_cfg; - volatile gpiosd_etm_task_p12_cfg_reg_t etm_task_p12_cfg; - volatile gpiosd_etm_task_p13_cfg_reg_t etm_task_p13_cfg; - uint32_t reserved_0d8[9]; - volatile gpiosd_version_reg_t version; -} gpiosd_dev_t; - -extern gpiosd_dev_t GPIO; - -#ifndef __cplusplus -_Static_assert(sizeof(gpiosd_dev_t) == 0x100, "Invalid size of gpiosd_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/gpio_sig_map.h b/components/soc/esp32p4/register/hw_ver3/soc/gpio_sig_map.h deleted file mode 100644 index 65c4a503c068..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/gpio_sig_map.h +++ /dev/null @@ -1,483 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#define SD_CARD_CCLK_2_PAD_OUT_IDX 0 -#define SD_CARD_CCMD_2_PAD_IN_IDX 1 -#define SD_CARD_CCMD_2_PAD_OUT_IDX 1 -#define SD_CARD_CDATA0_2_PAD_IN_IDX 2 -#define SD_CARD_CDATA0_2_PAD_OUT_IDX 2 -#define SD_CARD_CDATA1_2_PAD_IN_IDX 3 -#define SD_CARD_CDATA1_2_PAD_OUT_IDX 3 -#define SD_CARD_CDATA2_2_PAD_IN_IDX 4 -#define SD_CARD_CDATA2_2_PAD_OUT_IDX 4 -#define SD_CARD_CDATA3_2_PAD_IN_IDX 5 -#define SD_CARD_CDATA3_2_PAD_OUT_IDX 5 -#define SD_CARD_CDATA4_2_PAD_IN_IDX 6 -#define SD_CARD_CDATA4_2_PAD_OUT_IDX 6 -#define SD_CARD_CDATA5_2_PAD_IN_IDX 7 -#define SD_CARD_CDATA5_2_PAD_OUT_IDX 7 -#define SD_CARD_CDATA6_2_PAD_IN_IDX 8 -#define SD_CARD_CDATA6_2_PAD_OUT_IDX 8 -#define SD_CARD_CDATA7_2_PAD_IN_IDX 9 -#define SD_CARD_CDATA7_2_PAD_OUT_IDX 9 -#define UART0_RXD_PAD_IN_IDX 10 -#define UART0_TXD_PAD_OUT_IDX 10 -#define UART0_CTS_PAD_IN_IDX 11 -#define UART0_RTS_PAD_OUT_IDX 11 -#define UART0_DSR_PAD_IN_IDX 12 -#define UART0_DTR_PAD_OUT_IDX 12 -#define UART1_RXD_PAD_IN_IDX 13 -#define UART1_TXD_PAD_OUT_IDX 13 -#define UART1_CTS_PAD_IN_IDX 14 -#define UART1_RTS_PAD_OUT_IDX 14 -#define UART1_DSR_PAD_IN_IDX 15 -#define UART1_DTR_PAD_OUT_IDX 15 -#define UART2_RXD_PAD_IN_IDX 16 -#define UART2_TXD_PAD_OUT_IDX 16 -#define UART2_CTS_PAD_IN_IDX 17 -#define UART2_RTS_PAD_OUT_IDX 17 -#define UART2_DSR_PAD_IN_IDX 18 -#define UART2_DTR_PAD_OUT_IDX 18 -#define UART3_RXD_PAD_IN_IDX 19 -#define UART3_TXD_PAD_OUT_IDX 19 -#define UART3_CTS_PAD_IN_IDX 20 -#define UART3_RTS_PAD_OUT_IDX 20 -#define UART3_DSR_PAD_IN_IDX 21 -#define UART3_DTR_PAD_OUT_IDX 21 -#define UART4_RXD_PAD_IN_IDX 22 -#define UART4_TXD_PAD_OUT_IDX 22 -#define UART4_CTS_PAD_IN_IDX 23 -#define UART4_RTS_PAD_OUT_IDX 23 -#define UART4_DSR_PAD_IN_IDX 24 -#define UART4_DTR_PAD_OUT_IDX 24 -#define I2S0_O_BCK_PAD_IN_IDX 25 -#define I2S0_O_BCK_PAD_OUT_IDX 25 -#define I2S0_MCLK_PAD_IN_IDX 26 -#define I2S0_MCLK_PAD_OUT_IDX 26 -#define I2S0_O_WS_PAD_IN_IDX 27 -#define I2S0_O_WS_PAD_OUT_IDX 27 -#define I2S0_I_SD_PAD_IN_IDX 28 -#define I2S0_O_SD_PAD_OUT_IDX 28 -#define I2S0_I_BCK_PAD_IN_IDX 29 -#define I2S0_I_BCK_PAD_OUT_IDX 29 -#define I2S0_I_WS_PAD_IN_IDX 30 -#define I2S0_I_WS_PAD_OUT_IDX 30 -#define I2S1_O_BCK_PAD_IN_IDX 31 -#define I2S1_O_BCK_PAD_OUT_IDX 31 -#define I2S1_MCLK_PAD_IN_IDX 32 -#define I2S1_MCLK_PAD_OUT_IDX 32 -#define I2S1_O_WS_PAD_IN_IDX 33 -#define I2S1_O_WS_PAD_OUT_IDX 33 -#define I2S1_I_SD_PAD_IN_IDX 34 -#define I2S1_O_SD_PAD_OUT_IDX 34 -#define I2S1_I_BCK_PAD_IN_IDX 35 -#define I2S1_I_BCK_PAD_OUT_IDX 35 -#define I2S1_I_WS_PAD_IN_IDX 36 -#define I2S1_I_WS_PAD_OUT_IDX 36 -#define I2S2_O_BCK_PAD_IN_IDX 37 -#define I2S2_O_BCK_PAD_OUT_IDX 37 -#define I2S2_MCLK_PAD_IN_IDX 38 -#define I2S2_MCLK_PAD_OUT_IDX 38 -#define I2S2_O_WS_PAD_IN_IDX 39 -#define I2S2_O_WS_PAD_OUT_IDX 39 -#define I2S2_I_SD_PAD_IN_IDX 40 -#define I2S2_O_SD_PAD_OUT_IDX 40 -#define I2S2_I_BCK_PAD_IN_IDX 41 -#define I2S2_I_BCK_PAD_OUT_IDX 41 -#define I2S2_I_WS_PAD_IN_IDX 42 -#define I2S2_I_WS_PAD_OUT_IDX 42 -#define I2S0_I_SD1_PAD_IN_IDX 43 -#define I2S0_O_SD1_PAD_OUT_IDX 43 -#define I2S0_I_SD2_PAD_IN_IDX 44 -#define SPI2_DQS_PAD_OUT_IDX 44 -#define I2S0_I_SD3_PAD_IN_IDX 45 -#define SPI3_CS2_PAD_OUT_IDX 45 -#define SPI3_CS1_PAD_OUT_IDX 46 -#define SPI3_CK_PAD_IN_IDX 47 -#define SPI3_CK_PAD_OUT_IDX 47 -#define SPI3_Q_PAD_IN_IDX 48 -#define SPI3_QO_PAD_OUT_IDX 48 -#define SPI3_D_PAD_IN_IDX 49 -#define SPI3_D_PAD_OUT_IDX 49 -#define SPI3_HOLD_PAD_IN_IDX 50 -#define SPI3_HOLD_PAD_OUT_IDX 50 -#define SPI3_WP_PAD_IN_IDX 51 -#define SPI3_WP_PAD_OUT_IDX 51 -#define SPI3_CS_PAD_IN_IDX 52 -#define SPI3_CS_PAD_OUT_IDX 52 -#define SPI2_CK_PAD_IN_IDX 53 -#define SPI2_CK_PAD_OUT_IDX 53 -#define SPI2_Q_PAD_IN_IDX 54 -#define SPI2_Q_PAD_OUT_IDX 54 -#define SPI2_D_PAD_IN_IDX 55 -#define SPI2_D_PAD_OUT_IDX 55 -#define SPI2_HOLD_PAD_IN_IDX 56 -#define SPI2_HOLD_PAD_OUT_IDX 56 -#define SPI2_WP_PAD_IN_IDX 57 -#define SPI2_WP_PAD_OUT_IDX 57 -#define SPI2_IO4_PAD_IN_IDX 58 -#define SPI2_IO4_PAD_OUT_IDX 58 -#define SPI2_IO5_PAD_IN_IDX 59 -#define SPI2_IO5_PAD_OUT_IDX 59 -#define SPI2_IO6_PAD_IN_IDX 60 -#define SPI2_IO6_PAD_OUT_IDX 60 -#define SPI2_IO7_PAD_IN_IDX 61 -#define SPI2_IO7_PAD_OUT_IDX 61 -#define SPI2_CS_PAD_IN_IDX 62 -#define SPI2_CS_PAD_OUT_IDX 62 -#define PCNT_RST_PAD_IN0_IDX 63 -#define SPI2_CS1_PAD_OUT_IDX 63 -#define PCNT_RST_PAD_IN1_IDX 64 -#define SPI2_CS2_PAD_OUT_IDX 64 -#define PCNT_RST_PAD_IN2_IDX 65 -#define SPI2_CS3_PAD_OUT_IDX 65 -#define PCNT_RST_PAD_IN3_IDX 66 -#define SPI2_CS4_PAD_OUT_IDX 66 -#define SPI2_CS5_PAD_OUT_IDX 67 -#define I2C0_SCL_PAD_IN_IDX 68 -#define I2C0_SCL_PAD_OUT_IDX 68 -#define I2C0_SDA_PAD_IN_IDX 69 -#define I2C0_SDA_PAD_OUT_IDX 69 -#define I2C1_SCL_PAD_IN_IDX 70 -#define I2C1_SCL_PAD_OUT_IDX 70 -#define I2C1_SDA_PAD_IN_IDX 71 -#define I2C1_SDA_PAD_OUT_IDX 71 -#define GPIO_SD0_OUT_IDX 72 -#define GPIO_SD1_OUT_IDX 73 -#define UART0_SLP_CLK_PAD_IN_IDX 74 -#define GPIO_SD2_OUT_IDX 74 -#define UART1_SLP_CLK_PAD_IN_IDX 75 -#define GPIO_SD3_OUT_IDX 75 -#define UART2_SLP_CLK_PAD_IN_IDX 76 -#define GPIO_SD4_OUT_IDX 76 -#define UART3_SLP_CLK_PAD_IN_IDX 77 -#define GPIO_SD5_OUT_IDX 77 -#define UART4_SLP_CLK_PAD_IN_IDX 78 -#define GPIO_SD6_OUT_IDX 78 -#define GPIO_SD7_OUT_IDX 79 -#define TWAI0_RX_PAD_IN_IDX 80 -#define TWAI0_TX_PAD_OUT_IDX 80 -#define TWAI0_BUS_OFF_ON_PAD_OUT_IDX 81 -#define TWAI0_CLKOUT_PAD_OUT_IDX 82 -#define TWAI1_RX_PAD_IN_IDX 83 -#define TWAI1_TX_PAD_OUT_IDX 83 -#define TWAI1_BUS_OFF_ON_PAD_OUT_IDX 84 -#define TWAI1_CLKOUT_PAD_OUT_IDX 85 -#define TWAI2_RX_PAD_IN_IDX 86 -#define TWAI2_TX_PAD_OUT_IDX 86 -#define TWAI2_BUS_OFF_ON_PAD_OUT_IDX 87 -#define TWAI2_CLKOUT_PAD_OUT_IDX 88 -#define PWM0_SYNC0_PAD_IN_IDX 89 -#define PWM0_CH0_A_PAD_OUT_IDX 89 -#define PWM0_SYNC1_PAD_IN_IDX 90 -#define PWM0_CH0_B_PAD_OUT_IDX 90 -#define PWM0_SYNC2_PAD_IN_IDX 91 -#define PWM0_CH1_A_PAD_OUT_IDX 91 -#define PWM0_F0_PAD_IN_IDX 92 -#define PWM0_CH1_B_PAD_OUT_IDX 92 -#define PWM0_F1_PAD_IN_IDX 93 -#define PWM0_CH2_A_PAD_OUT_IDX 93 -#define PWM0_F2_PAD_IN_IDX 94 -#define PWM0_CH2_B_PAD_OUT_IDX 94 -#define PWM0_CAP0_PAD_IN_IDX 95 -#define PWM1_CH0_A_PAD_OUT_IDX 95 -#define PWM0_CAP1_PAD_IN_IDX 96 -#define PWM1_CH0_B_PAD_OUT_IDX 96 -#define PWM0_CAP2_PAD_IN_IDX 97 -#define PWM1_CH1_A_PAD_OUT_IDX 97 -#define PWM1_SYNC0_PAD_IN_IDX 98 -#define PWM1_CH1_B_PAD_OUT_IDX 98 -#define PWM1_SYNC1_PAD_IN_IDX 99 -#define PWM1_CH2_A_PAD_OUT_IDX 99 -#define PWM1_SYNC2_PAD_IN_IDX 100 -#define PWM1_CH2_B_PAD_OUT_IDX 100 -#define PWM1_F0_PAD_IN_IDX 101 -#define PWM1_F1_PAD_IN_IDX 102 -#define PWM1_F2_PAD_IN_IDX 103 -#define PWM1_CAP0_PAD_IN_IDX 104 -#define PWM1_CAP1_PAD_IN_IDX 105 -#define TWAI0_STANDBY_PAD_OUT_IDX 105 -#define PWM1_CAP2_PAD_IN_IDX 106 -#define TWAI1_STANDBY_PAD_OUT_IDX 106 -#define GMII_MDI_PAD_IN_IDX 107 -#define TWAI2_STANDBY_PAD_OUT_IDX 107 -#define GMAC_PHY_COL_PAD_IN_IDX 108 -#define GMII_MDC_PAD_OUT_IDX 108 -#define GMAC_PHY_CRS_PAD_IN_IDX 109 -#define GMII_MDO_PAD_OUT_IDX 109 -#define USB_OTG11_IDDIG_PAD_IN_IDX 110 -#define USB_SRP_DISCHRGVBUS_PAD_OUT_IDX 110 -#define USB_OTG11_AVALID_PAD_IN_IDX 111 -#define USB_OTG11_IDPULLUP_PAD_OUT_IDX 111 -#define USB_SRP_BVALID_PAD_IN_IDX 112 -#define USB_OTG11_DPPULLDOWN_PAD_OUT_IDX 112 -#define USB_OTG11_VBUSVALID_PAD_IN_IDX 113 -#define USB_OTG11_DMPULLDOWN_PAD_OUT_IDX 113 -#define USB_SRP_SESSEND_PAD_IN_IDX 114 -#define USB_OTG11_DRVVBUS_PAD_OUT_IDX 114 -#define USB_SRP_CHRGVBUS_PAD_OUT_IDX 115 -#define ULPI_CLK_PAD_IN_IDX 117 -#define RNG_CHAIN_CLK_PAD_OUT_IDX 117 -#define USB_HSPHY_REFCLK_IN_IDX 118 -#define HP_PROBE_TOP_OUT0_IDX 118 -#define HP_PROBE_TOP_OUT1_IDX 119 -#define HP_PROBE_TOP_OUT2_IDX 120 -#define HP_PROBE_TOP_OUT3_IDX 121 -#define HP_PROBE_TOP_OUT4_IDX 122 -#define HP_PROBE_TOP_OUT5_IDX 123 -#define HP_PROBE_TOP_OUT6_IDX 124 -#define HP_PROBE_TOP_OUT7_IDX 125 -#define SD_CARD_DETECT_N_1_PAD_IN_IDX 126 -#define LEDC_LS_SIG_OUT_PAD_OUT0_IDX 126 -#define SD_CARD_DETECT_N_2_PAD_IN_IDX 127 -#define LEDC_LS_SIG_OUT_PAD_OUT1_IDX 127 -#define SD_CARD_INT_N_1_PAD_IN_IDX 128 -#define LEDC_LS_SIG_OUT_PAD_OUT2_IDX 128 -#define SD_CARD_INT_N_2_PAD_IN_IDX 129 -#define LEDC_LS_SIG_OUT_PAD_OUT3_IDX 129 -#define SD_CARD_WRITE_PRT_1_PAD_IN_IDX 130 -#define LEDC_LS_SIG_OUT_PAD_OUT4_IDX 130 -#define SD_CARD_WRITE_PRT_2_PAD_IN_IDX 131 -#define LEDC_LS_SIG_OUT_PAD_OUT5_IDX 131 -#define SD_DATA_STROBE_1_PAD_IN_IDX 132 -#define LEDC_LS_SIG_OUT_PAD_OUT6_IDX 132 -#define SD_DATA_STROBE_2_PAD_IN_IDX 133 -#define LEDC_LS_SIG_OUT_PAD_OUT7_IDX 133 -#define I3C_MST_SCL_PAD_IN_IDX 134 -#define I3C_MST_SCL_PAD_OUT_IDX 134 -#define I3C_MST_SDA_PAD_IN_IDX 135 -#define I3C_MST_SDA_PAD_OUT_IDX 135 -#define I3C_SLV_SCL_PAD_IN_IDX 136 -#define I3C_SLV_SCL_PAD_OUT_IDX 136 -#define I3C_SLV_SDA_PAD_IN_IDX 137 -#define I3C_SLV_SDA_PAD_OUT_IDX 137 -#define I3C_MST_SCL_PULLUP_EN_PAD_OUT_IDX 138 -#define I3C_MST_SDA_PULLUP_EN_PAD_OUT_IDX 139 -#define USB_JTAG_TDO_BRIDGE_PAD_IN_IDX 140 -#define USB_JTAG_TDI_BRIDGE_PAD_OUT_IDX 140 -#define PCNT_SIG_CH0_PAD_IN0_IDX 141 -#define USB_JTAG_TMS_BRIDGE_PAD_OUT_IDX 141 -#define PCNT_SIG_CH0_PAD_IN1_IDX 142 -#define USB_JTAG_TCK_BRIDGE_PAD_OUT_IDX 142 -#define PCNT_SIG_CH0_PAD_IN2_IDX 143 -#define USB_JTAG_TRST_BRIDGE_PAD_OUT_IDX 143 -#define PCNT_SIG_CH0_PAD_IN3_IDX 144 -#define LCD_CS_PAD_OUT_IDX 144 -#define PCNT_SIG_CH1_PAD_IN0_IDX 145 -#define LCD_DC_PAD_OUT_IDX 145 -#define PCNT_SIG_CH1_PAD_IN1_IDX 146 -#define SD_RST_N_1_PAD_OUT_IDX 146 -#define PCNT_SIG_CH1_PAD_IN2_IDX 147 -#define SD_RST_N_2_PAD_OUT_IDX 147 -#define PCNT_SIG_CH1_PAD_IN3_IDX 148 -#define SD_CCMD_OD_PULLUP_EN_N_PAD_OUT_IDX 148 -#define PCNT_CTRL_CH0_PAD_IN0_IDX 149 -#define LCD_PCLK_PAD_OUT_IDX 149 -#define PCNT_CTRL_CH0_PAD_IN1_IDX 150 -#define CAM_CLK_PAD_OUT_IDX 150 -#define PCNT_CTRL_CH0_PAD_IN2_IDX 151 -#define LCD_H_ENABLE_PAD_OUT_IDX 151 -#define PCNT_CTRL_CH0_PAD_IN3_IDX 152 -#define LCD_H_SYNC_PAD_OUT_IDX 152 -#define PCNT_CTRL_CH1_PAD_IN0_IDX 153 -#define LCD_V_SYNC_PAD_OUT_IDX 153 -#define PCNT_CTRL_CH1_PAD_IN1_IDX 154 -#define LCD_DATA_OUT_PAD_OUT0_IDX 154 -#define PCNT_CTRL_CH1_PAD_IN2_IDX 155 -#define LCD_DATA_OUT_PAD_OUT1_IDX 155 -#define PCNT_CTRL_CH1_PAD_IN3_IDX 156 -#define LCD_DATA_OUT_PAD_OUT2_IDX 156 -#define LCD_DATA_OUT_PAD_OUT3_IDX 157 -#define CAM_PCLK_PAD_IN_IDX 158 -#define LCD_DATA_OUT_PAD_OUT4_IDX 158 -#define CAM_H_ENABLE_PAD_IN_IDX 159 -#define LCD_DATA_OUT_PAD_OUT5_IDX 159 -#define CAM_H_SYNC_PAD_IN_IDX 160 -#define LCD_DATA_OUT_PAD_OUT6_IDX 160 -#define CAM_V_SYNC_PAD_IN_IDX 161 -#define LCD_DATA_OUT_PAD_OUT7_IDX 161 -#define CAM_DATA_IN_PAD_IN0_IDX 162 -#define LCD_DATA_OUT_PAD_OUT8_IDX 162 -#define CAM_DATA_IN_PAD_IN1_IDX 163 -#define LCD_DATA_OUT_PAD_OUT9_IDX 163 -#define CAM_DATA_IN_PAD_IN2_IDX 164 -#define LCD_DATA_OUT_PAD_OUT10_IDX 164 -#define CAM_DATA_IN_PAD_IN3_IDX 165 -#define LCD_DATA_OUT_PAD_OUT11_IDX 165 -#define CAM_DATA_IN_PAD_IN4_IDX 166 -#define LCD_DATA_OUT_PAD_OUT12_IDX 166 -#define CAM_DATA_IN_PAD_IN5_IDX 167 -#define LCD_DATA_OUT_PAD_OUT13_IDX 167 -#define CAM_DATA_IN_PAD_IN6_IDX 168 -#define LCD_DATA_OUT_PAD_OUT14_IDX 168 -#define CAM_DATA_IN_PAD_IN7_IDX 169 -#define LCD_DATA_OUT_PAD_OUT15_IDX 169 -#define CAM_DATA_IN_PAD_IN8_IDX 170 -#define LCD_DATA_OUT_PAD_OUT16_IDX 170 -#define CAM_DATA_IN_PAD_IN9_IDX 171 -#define LCD_DATA_OUT_PAD_OUT17_IDX 171 -#define CAM_DATA_IN_PAD_IN10_IDX 172 -#define LCD_DATA_OUT_PAD_OUT18_IDX 172 -#define CAM_DATA_IN_PAD_IN11_IDX 173 -#define LCD_DATA_OUT_PAD_OUT19_IDX 173 -#define CAM_DATA_IN_PAD_IN12_IDX 174 -#define LCD_DATA_OUT_PAD_OUT20_IDX 174 -#define CAM_DATA_IN_PAD_IN13_IDX 175 -#define LCD_DATA_OUT_PAD_OUT21_IDX 175 -#define CAM_DATA_IN_PAD_IN14_IDX 176 -#define LCD_DATA_OUT_PAD_OUT22_IDX 176 -#define CAM_DATA_IN_PAD_IN15_IDX 177 -#define LCD_DATA_OUT_PAD_OUT23_IDX 177 -#define GMAC_PHY_RXDV_PAD_IN_IDX 178 -#define GMAC_PHY_TXEN_PAD_OUT_IDX 178 -#define GMAC_PHY_RXD0_PAD_IN_IDX 179 -#define GMAC_PHY_TXD0_PAD_OUT_IDX 179 -#define GMAC_PHY_RXD1_PAD_IN_IDX 180 -#define GMAC_PHY_TXD1_PAD_OUT_IDX 180 -#define GMAC_PHY_RXD2_PAD_IN_IDX 181 -#define GMAC_PHY_TXD2_PAD_OUT_IDX 181 -#define GMAC_PHY_RXD3_PAD_IN_IDX 182 -#define GMAC_PHY_TXD3_PAD_OUT_IDX 182 -#define GMAC_PHY_RXER_PAD_IN_IDX 183 -#define GMAC_PHY_TXER_PAD_OUT_IDX 183 -#define GMAC_RX_CLK_PAD_IN_IDX 184 -#define DBG_CH0_CLK_IDX 184 -#define GMAC_TX_CLK_PAD_IN_IDX 185 -#define DBG_CH1_CLK_IDX 185 -#define PARLIO_RX_CLK_PAD_IN_IDX 186 -#define PARLIO_RX_CLK_PAD_OUT_IDX 186 -#define PARLIO_TX_CLK_PAD_IN_IDX 187 -#define PARLIO_TX_CLK_PAD_OUT_IDX 187 -#define PARLIO_RX_DATA0_PAD_IN_IDX 188 -#define PARLIO_TX_DATA0_PAD_OUT_IDX 188 -#define PARLIO_RX_DATA1_PAD_IN_IDX 189 -#define PARLIO_TX_DATA1_PAD_OUT_IDX 189 -#define PARLIO_RX_DATA2_PAD_IN_IDX 190 -#define PARLIO_TX_DATA2_PAD_OUT_IDX 190 -#define PARLIO_RX_DATA3_PAD_IN_IDX 191 -#define PARLIO_TX_DATA3_PAD_OUT_IDX 191 -#define PARLIO_RX_DATA4_PAD_IN_IDX 192 -#define PARLIO_TX_DATA4_PAD_OUT_IDX 192 -#define PARLIO_RX_DATA5_PAD_IN_IDX 193 -#define PARLIO_TX_DATA5_PAD_OUT_IDX 193 -#define PARLIO_RX_DATA6_PAD_IN_IDX 194 -#define PARLIO_TX_DATA6_PAD_OUT_IDX 194 -#define PARLIO_RX_DATA7_PAD_IN_IDX 195 -#define PARLIO_TX_DATA7_PAD_OUT_IDX 195 -#define PARLIO_RX_DATA8_PAD_IN_IDX 196 -#define PARLIO_TX_DATA8_PAD_OUT_IDX 196 -#define PARLIO_RX_DATA9_PAD_IN_IDX 197 -#define PARLIO_TX_DATA9_PAD_OUT_IDX 197 -#define PARLIO_RX_DATA10_PAD_IN_IDX 198 -#define PARLIO_TX_DATA10_PAD_OUT_IDX 198 -#define PARLIO_RX_DATA11_PAD_IN_IDX 199 -#define PARLIO_TX_DATA11_PAD_OUT_IDX 199 -#define PARLIO_RX_DATA12_PAD_IN_IDX 200 -#define PARLIO_TX_DATA12_PAD_OUT_IDX 200 -#define PARLIO_RX_DATA13_PAD_IN_IDX 201 -#define PARLIO_TX_DATA13_PAD_OUT_IDX 201 -#define PARLIO_RX_DATA14_PAD_IN_IDX 202 -#define PARLIO_TX_DATA14_PAD_OUT_IDX 202 -#define PARLIO_RX_DATA15_PAD_IN_IDX 203 -#define PARLIO_TX_DATA15_PAD_OUT_IDX 203 -#define HP_PROBE_TOP_OUT8_IDX 204 -#define HP_PROBE_TOP_OUT9_IDX 205 -#define HP_PROBE_TOP_OUT10_IDX 206 -#define HP_PROBE_TOP_OUT11_IDX 207 -#define HP_PROBE_TOP_OUT12_IDX 208 -#define HP_PROBE_TOP_OUT13_IDX 209 -#define HP_PROBE_TOP_OUT14_IDX 210 -#define HP_PROBE_TOP_OUT15_IDX 211 -#define CONSTANT0_PAD_OUT_IDX 212 -#define CONSTANT1_PAD_OUT_IDX 213 -#define CORE_GPIO_IN_PAD_IN0_IDX 214 -#define CORE_GPIO_OUT_PAD_OUT0_IDX 214 -#define CORE_GPIO_IN_PAD_IN1_IDX 215 -#define CORE_GPIO_OUT_PAD_OUT1_IDX 215 -#define CORE_GPIO_IN_PAD_IN2_IDX 216 -#define CORE_GPIO_OUT_PAD_OUT2_IDX 216 -#define CORE_GPIO_IN_PAD_IN3_IDX 217 -#define CORE_GPIO_OUT_PAD_OUT3_IDX 217 -#define CORE_GPIO_IN_PAD_IN4_IDX 218 -#define CORE_GPIO_OUT_PAD_OUT4_IDX 218 -#define CORE_GPIO_IN_PAD_IN5_IDX 219 -#define CORE_GPIO_OUT_PAD_OUT5_IDX 219 -#define CORE_GPIO_IN_PAD_IN6_IDX 220 -#define CORE_GPIO_OUT_PAD_OUT6_IDX 220 -#define CORE_GPIO_IN_PAD_IN7_IDX 221 -#define CORE_GPIO_OUT_PAD_OUT7_IDX 221 -#define CORE_GPIO_IN_PAD_IN8_IDX 222 -#define CORE_GPIO_OUT_PAD_OUT8_IDX 222 -#define CORE_GPIO_IN_PAD_IN9_IDX 223 -#define CORE_GPIO_OUT_PAD_OUT9_IDX 223 -#define CORE_GPIO_IN_PAD_IN10_IDX 224 -#define CORE_GPIO_OUT_PAD_OUT10_IDX 224 -#define CORE_GPIO_IN_PAD_IN11_IDX 225 -#define CORE_GPIO_OUT_PAD_OUT11_IDX 225 -#define CORE_GPIO_IN_PAD_IN12_IDX 226 -#define CORE_GPIO_OUT_PAD_OUT12_IDX 226 -#define CORE_GPIO_IN_PAD_IN13_IDX 227 -#define CORE_GPIO_OUT_PAD_OUT13_IDX 227 -#define CORE_GPIO_IN_PAD_IN14_IDX 228 -#define CORE_GPIO_OUT_PAD_OUT14_IDX 228 -#define CORE_GPIO_IN_PAD_IN15_IDX 229 -#define CORE_GPIO_OUT_PAD_OUT15_IDX 229 -#define CORE_GPIO_IN_PAD_IN16_IDX 230 -#define CORE_GPIO_OUT_PAD_OUT16_IDX 230 -#define CORE_GPIO_IN_PAD_IN17_IDX 231 -#define CORE_GPIO_OUT_PAD_OUT17_IDX 231 -#define CORE_GPIO_IN_PAD_IN18_IDX 232 -#define CORE_GPIO_OUT_PAD_OUT18_IDX 232 -#define CORE_GPIO_IN_PAD_IN19_IDX 233 -#define CORE_GPIO_OUT_PAD_OUT19_IDX 233 -#define CORE_GPIO_IN_PAD_IN20_IDX 234 -#define CORE_GPIO_OUT_PAD_OUT20_IDX 234 -#define CORE_GPIO_IN_PAD_IN21_IDX 235 -#define CORE_GPIO_OUT_PAD_OUT21_IDX 235 -#define CORE_GPIO_IN_PAD_IN22_IDX 236 -#define CORE_GPIO_OUT_PAD_OUT22_IDX 236 -#define CORE_GPIO_IN_PAD_IN23_IDX 237 -#define CORE_GPIO_OUT_PAD_OUT23_IDX 237 -#define CORE_GPIO_IN_PAD_IN24_IDX 238 -#define CORE_GPIO_OUT_PAD_OUT24_IDX 238 -#define CORE_GPIO_IN_PAD_IN25_IDX 239 -#define CORE_GPIO_OUT_PAD_OUT25_IDX 239 -#define CORE_GPIO_IN_PAD_IN26_IDX 240 -#define CORE_GPIO_OUT_PAD_OUT26_IDX 240 -#define CORE_GPIO_IN_PAD_IN27_IDX 241 -#define CORE_GPIO_OUT_PAD_OUT27_IDX 241 -#define CORE_GPIO_IN_PAD_IN28_IDX 242 -#define PARLIO_TX_CS_PAD_OUT_IDX 242 -#define CORE_GPIO_IN_PAD_IN29_IDX 243 -#define EMAC_PTP_PPS_PAD_OUT_IDX 243 -#define CORE_GPIO_IN_PAD_IN30_IDX 244 -#define ANA_COMP0_OUT_IDX 244 -#define CORE_GPIO_IN_PAD_IN31_IDX 245 -#define ANA_COMP1_OUT_IDX 245 -#define RMT_SIG_PAD_IN0_IDX 246 -#define RMT_SIG_PAD_OUT0_IDX 246 -#define RMT_SIG_PAD_IN1_IDX 247 -#define RMT_SIG_PAD_OUT1_IDX 247 -#define RMT_SIG_PAD_IN2_IDX 248 -#define RMT_SIG_PAD_OUT2_IDX 248 -#define RMT_SIG_PAD_IN3_IDX 249 -#define RMT_SIG_PAD_OUT3_IDX 249 -#define SIG_IN_FUNC250_IDX 250 -#define SIG_IN_FUNC250_IDX 250 -#define SIG_IN_FUNC251_IDX 251 -#define SIG_IN_FUNC251_IDX 251 -#define SIG_IN_FUNC252_IDX 252 -#define SIG_IN_FUNC252_IDX 252 -#define SIG_IN_FUNC253_IDX 253 -#define SIG_IN_FUNC253_IDX 253 -#define SIG_IN_FUNC254_IDX 254 -#define SIG_IN_FUNC254_IDX 254 -#define SIG_IN_FUNC255_IDX 255 -#define SIG_IN_FUNC255_IDX 255 -// version date 230403 -#define SIG_GPIO_OUT_IDX 256 diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h index 86a980f8e0e6..8e62f2bec847 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h @@ -413,37 +413,6 @@ typedef union { } hp_crypto_ctrl_reg_t; -/** Group: HP GPIO O HOLD CTRL0 REG */ -/** Type of gpio_o_hold_ctrl0 register - * NA - */ -typedef union { - struct { - /** reg_gpio_0_hold_low : R/W; bitpos: [31:0]; default: 0; - * hold control for gpio47~16 - */ - uint32_t reg_gpio_0_hold_low:32; - }; - uint32_t val; -} hp_gpio_o_hold_ctrl0_reg_t; - - -/** Group: HP GPIO O HOLD CTRL1 REG */ -/** Type of gpio_o_hold_ctrl1 register - * NA - */ -typedef union { - struct { - /** reg_gpio_0_hold_high : R/W; bitpos: [8:0]; default: 0; - * hold control for gpio56~48 - */ - uint32_t reg_gpio_0_hold_high:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} hp_gpio_o_hold_ctrl1_reg_t; - - /** Group: HP SYS RDN ECO CS REG */ /** Type of sys_rdn_eco_cs register * NA @@ -2149,8 +2118,7 @@ typedef struct hp_system_dev_t { volatile hp_cpu_corestalled_st_reg_t cpu_corestalled_st; uint32_t reserved_068[2]; volatile hp_crypto_ctrl_reg_t crypto_ctrl; - volatile hp_gpio_o_hold_ctrl0_reg_t gpio_o_hold_ctrl0; - volatile hp_gpio_o_hold_ctrl1_reg_t gpio_o_hold_ctrl1; + uint32_t reserved_074[2]; volatile hp_sys_rdn_eco_cs_reg_t sys_rdn_eco_cs; volatile hp_cache_apb_postw_en_reg_t cache_apb_postw_en; volatile hp_l2_mem_subsize_reg_t l2_mem_subsize; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i2s_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/i2s_eco5_struct.h deleted file mode 100644 index fac3b8b8fd2a..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/i2s_eco5_struct.h +++ /dev/null @@ -1,1009 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Interrupt registers */ -/** Type of int_raw register - * I2S interrupt raw register, valid in level. - */ -typedef union { - struct { - /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status bit for the i2s_rx_done_int interrupt - */ - uint32_t rx_done_int_raw:1; - /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status bit for the i2s_tx_done_int interrupt - */ - uint32_t tx_done_int_raw:1; - /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status bit for the i2s_rx_hung_int interrupt - */ - uint32_t rx_hung_int_raw:1; - /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status bit for the i2s_tx_hung_int interrupt - */ - uint32_t tx_hung_int_raw:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} i2s_int_raw_reg_t; - -/** Type of int_st register - * I2S interrupt status register. - */ -typedef union { - struct { - /** rx_done_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for the i2s_rx_done_int interrupt - */ - uint32_t rx_done_int_st:1; - /** tx_done_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for the i2s_tx_done_int interrupt - */ - uint32_t tx_done_int_st:1; - /** rx_hung_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for the i2s_rx_hung_int interrupt - */ - uint32_t rx_hung_int_st:1; - /** tx_hung_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status bit for the i2s_tx_hung_int interrupt - */ - uint32_t tx_hung_int_st:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} i2s_int_st_reg_t; - -/** Type of int_ena register - * I2S interrupt enable register. - */ -typedef union { - struct { - /** rx_done_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the i2s_rx_done_int interrupt - */ - uint32_t rx_done_int_ena:1; - /** tx_done_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the i2s_tx_done_int interrupt - */ - uint32_t tx_done_int_ena:1; - /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the i2s_rx_hung_int interrupt - */ - uint32_t rx_hung_int_ena:1; - /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the i2s_tx_hung_int interrupt - */ - uint32_t tx_hung_int_ena:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} i2s_int_ena_reg_t; - -/** Type of int_clr register - * I2S interrupt clear register. - */ -typedef union { - struct { - /** rx_done_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the i2s_rx_done_int interrupt - */ - uint32_t rx_done_int_clr:1; - /** tx_done_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the i2s_tx_done_int interrupt - */ - uint32_t tx_done_int_clr:1; - /** rx_hung_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the i2s_rx_hung_int interrupt - */ - uint32_t rx_hung_int_clr:1; - /** tx_hung_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the i2s_tx_hung_int interrupt - */ - uint32_t tx_hung_int_clr:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} i2s_int_clr_reg_t; - - -/** Group: RX Control and configuration registers */ -/** Type of rx_conf register - * I2S RX configure register - */ -typedef union { - struct { - /** rx_reset : WT; bitpos: [0]; default: 0; - * Set this bit to reset receiver - */ - uint32_t rx_reset:1; - /** rx_fifo_reset : WT; bitpos: [1]; default: 0; - * Set this bit to reset Rx AFIFO - */ - uint32_t rx_fifo_reset:1; - /** rx_start : R/W/SC; bitpos: [2]; default: 0; - * Set this bit to start receiving data - */ - uint32_t rx_start:1; - /** rx_slave_mod : R/W; bitpos: [3]; default: 0; - * Set this bit to enable slave receiver mode - */ - uint32_t rx_slave_mod:1; - /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0; - * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is - * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. - */ - uint32_t rx_stop_mode:2; - /** rx_mono : R/W; bitpos: [6]; default: 0; - * Set this bit to enable receiver in mono mode - */ - uint32_t rx_mono:1; - /** rx_big_endian : R/W; bitpos: [7]; default: 0; - * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. - */ - uint32_t rx_big_endian:1; - /** rx_update : R/W/SC; bitpos: [8]; default: 0; - * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This - * bit will be cleared by hardware after update register done. - */ - uint32_t rx_update:1; - /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1; - * 1: The first channel data value is valid in I2S RX mono mode. 0: The second - * channel data value is valid in I2S RX mono mode. - */ - uint32_t rx_mono_fst_vld:1; - /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1; - * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 - * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & - */ - uint32_t rx_pcm_conf:2; - /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1; - * Set this bit to bypass Compress/Decompress module for received data. - */ - uint32_t rx_pcm_bypass:1; - /** rx_msb_shift : R/W; bitpos: [13]; default: 1; - * Set this bit to enable receiver in Phillips standard mode - */ - uint32_t rx_msb_shift:1; - uint32_t reserved_14:1; - /** rx_left_align : R/W; bitpos: [15]; default: 1; - * 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. - */ - uint32_t rx_left_align:1; - /** rx_24_fill_en : R/W; bitpos: [16]; default: 0; - * 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. - */ - uint32_t rx_24_fill_en:1; - /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0; - * 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. - * 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. - */ - uint32_t rx_ws_idle_pol:1; - /** rx_bit_order : R/W; bitpos: [18]; default: 0; - * I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB - * is received first. - */ - uint32_t rx_bit_order:1; - /** rx_tdm_en : R/W; bitpos: [19]; default: 0; - * 1: Enable I2S TDM Rx mode . 0: Disable. - */ - uint32_t rx_tdm_en:1; - /** rx_pdm_en : R/W; bitpos: [20]; default: 0; - * 1: Enable I2S PDM Rx mode . 0: Disable. - */ - uint32_t rx_pdm_en:1; - /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6; - * Bit clock configuration bits in receiver mode. - */ - uint32_t rx_bck_div_num:6; - uint32_t reserved_27:5; - }; - uint32_t val; -} i2s_rx_conf_reg_t; - -/** Type of rx_conf1 register - * I2S RX configure register 1 - */ -typedef union { - struct { - /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0; - * The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * - * T_bck - */ - uint32_t rx_tdm_ws_width:9; - uint32_t reserved_9:5; - /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15; - * Set the bits to configure the valid data bit length of I2S receiver channel. 7: all - * the valid channel data is in 8-bit-mode. 15: all the valid channel data is in - * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid - * channel data is in 32-bit-mode. - */ - uint32_t rx_bits_mod:5; - /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15; - * I2S Rx half sample bits -1. - */ - uint32_t rx_half_sample_bits:8; - /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15; - * The Rx bit number for each channel minus 1in TDM mode. - */ - uint32_t rx_tdm_chan_bits:5; - }; - uint32_t val; -} i2s_rx_conf1_reg_t; - -/** Type of rx_pdm2pcm_conf register - * I2S RX configure register - */ -typedef union { - struct { - uint32_t reserved_0:19; - /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0; - * 1: Enable PDM2PCM RX mode. 0: DIsable. - */ - uint32_t rx_pdm2pcm_en:1; - /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0; - * Configure the down sampling rate of PDM RX filter group1 module. 1: The down - * sampling rate is 128. 0: down sampling rate is 64. - */ - uint32_t rx_pdm_sinc_dsr_16_en:1; - /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1; - * Configure PDM RX amplify number. - */ - uint32_t rx_pdm2pcm_amplify_num:4; - /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0; - * I2S PDM RX bypass hp filter or not. - */ - uint32_t rx_pdm_hp_bypass:1; - /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6; - * The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + - * LP_I2S_RX_IIR_HP_MULT12_5[2:0]) - */ - uint32_t rx_iir_hp_mult12_5:3; - /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7; - * The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + - * LP_I2S_RX_IIR_HP_MULT12_0[2:0]) - */ - uint32_t rx_iir_hp_mult12_0:3; - }; - uint32_t val; -} i2s_rx_pdm2pcm_conf_reg_t; - -/** Type of rx_tdm_ctrl register - * I2S TX TDM mode control register - */ -typedef union { - struct { - /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1; - * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just - * input 0 in this channel. - */ - uint32_t rx_tdm_pdm_chan0_en:1; - /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1; - * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just - * input 0 in this channel. - */ - uint32_t rx_tdm_pdm_chan1_en:1; - /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1; - * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just - * input 0 in this channel. - */ - uint32_t rx_tdm_pdm_chan2_en:1; - /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1; - * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just - * input 0 in this channel. - */ - uint32_t rx_tdm_pdm_chan3_en:1; - /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1; - * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just - * input 0 in this channel. - */ - uint32_t rx_tdm_pdm_chan4_en:1; - /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1; - * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just - * input 0 in this channel. - */ - uint32_t rx_tdm_pdm_chan5_en:1; - /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1; - * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just - * input 0 in this channel. - */ - uint32_t rx_tdm_pdm_chan6_en:1; - /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1; - * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just - * input 0 in this channel. - */ - uint32_t rx_tdm_pdm_chan7_en:1; - /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1; - * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 - * in this channel. - */ - uint32_t rx_tdm_chan8_en:1; - /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1; - * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 - * in this channel. - */ - uint32_t rx_tdm_chan9_en:1; - /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1; - * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 - * in this channel. - */ - uint32_t rx_tdm_chan10_en:1; - /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1; - * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 - * in this channel. - */ - uint32_t rx_tdm_chan11_en:1; - /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1; - * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 - * in this channel. - */ - uint32_t rx_tdm_chan12_en:1; - /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1; - * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 - * in this channel. - */ - uint32_t rx_tdm_chan13_en:1; - /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1; - * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 - * in this channel. - */ - uint32_t rx_tdm_chan14_en:1; - /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1; - * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 - * in this channel. - */ - uint32_t rx_tdm_chan15_en:1; - /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0; - * The total channel number of I2S TX TDM mode. - */ - uint32_t rx_tdm_tot_chan_num:4; - uint32_t reserved_20:12; - }; - uint32_t val; -} i2s_rx_tdm_ctrl_reg_t; - -/** Type of rxeof_num register - * I2S RX data number control register. - */ -typedef union { - struct { - /** rx_eof_num : R/W; bitpos: [11:0]; default: 64; - * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + - * 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. - */ - uint32_t rx_eof_num:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} i2s_rxeof_num_reg_t; - - -/** Group: TX Control and configuration registers */ -/** Type of tx_conf register - * I2S TX configure register - */ -typedef union { - struct { - /** tx_reset : WT; bitpos: [0]; default: 0; - * Set this bit to reset transmitter - */ - uint32_t tx_reset:1; - /** tx_fifo_reset : WT; bitpos: [1]; default: 0; - * Set this bit to reset Tx AFIFO - */ - uint32_t tx_fifo_reset:1; - /** tx_start : R/W/SC; bitpos: [2]; default: 0; - * Set this bit to start transmitting data - */ - uint32_t tx_start:1; - /** tx_slave_mod : R/W; bitpos: [3]; default: 0; - * Set this bit to enable slave transmitter mode - */ - uint32_t tx_slave_mod:1; - /** tx_stop_en : R/W; bitpos: [4]; default: 1; - * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty - */ - uint32_t tx_stop_en:1; - /** tx_chan_equal : R/W; bitpos: [5]; default: 0; - * 1: The value of Left channel data is equal to the value of right channel data in - * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is - * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. - */ - uint32_t tx_chan_equal:1; - /** tx_mono : R/W; bitpos: [6]; default: 0; - * Set this bit to enable transmitter in mono mode - */ - uint32_t tx_mono:1; - /** tx_big_endian : R/W; bitpos: [7]; default: 0; - * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr - * value. - */ - uint32_t tx_big_endian:1; - /** tx_update : R/W/SC; bitpos: [8]; default: 0; - * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This - * bit will be cleared by hardware after update register done. - */ - uint32_t tx_update:1; - /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1; - * 1: The first channel data value is valid in I2S TX mono mode. 0: The second - * channel data value is valid in I2S TX mono mode. - */ - uint32_t tx_mono_fst_vld:1; - /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0; - * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 - * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & - */ - uint32_t tx_pcm_conf:2; - /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1; - * Set this bit to bypass Compress/Decompress module for transmitted data. - */ - uint32_t tx_pcm_bypass:1; - /** tx_msb_shift : R/W; bitpos: [13]; default: 1; - * Set this bit to enable transmitter in Phillips standard mode - */ - uint32_t tx_msb_shift:1; - /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1; - * 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to - * generate pos/neg edge in master mode. - */ - uint32_t tx_bck_no_dly:1; - /** tx_left_align : R/W; bitpos: [15]; default: 1; - * 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. - */ - uint32_t tx_left_align:1; - /** tx_24_fill_en : R/W; bitpos: [16]; default: 0; - * 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode - */ - uint32_t tx_24_fill_en:1; - /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0; - * 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: - * WS should be 1 when sending left channel data, and WS is 0in right channel. - */ - uint32_t tx_ws_idle_pol:1; - /** tx_bit_order : R/W; bitpos: [18]; default: 0; - * I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is - * sent first. - */ - uint32_t tx_bit_order:1; - /** tx_tdm_en : R/W; bitpos: [19]; default: 0; - * 1: Enable I2S TDM Tx mode . 0: Disable. - */ - uint32_t tx_tdm_en:1; - /** tx_pdm_en : R/W; bitpos: [20]; default: 0; - * 1: Enable I2S PDM Tx mode . 0: Disable. - */ - uint32_t tx_pdm_en:1; - /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6; - * Bit clock configuration bits in transmitter mode. - */ - uint32_t tx_bck_div_num:6; - /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0; - * I2S transmitter channel mode configuration bits. - */ - uint32_t tx_chan_mod:3; - /** sig_loopback : R/W; bitpos: [30]; default: 0; - * Enable signal loop back mode with transmitter module and receiver module sharing - * the same WS and BCK signals. - */ - uint32_t sig_loopback:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} i2s_tx_conf_reg_t; - -/** Type of tx_conf1 register - * I2S TX configure register 1 - */ -typedef union { - struct { - /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0; - * The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * - * T_bck - */ - uint32_t tx_tdm_ws_width:9; - uint32_t reserved_9:5; - /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15; - * Set the bits to configure the valid data bit length of I2S transmitter channel. 7: - * all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in - * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid - * channel data is in 32-bit-mode. - */ - uint32_t tx_bits_mod:5; - /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15; - * I2S Tx half sample bits -1. - */ - uint32_t tx_half_sample_bits:8; - /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15; - * The Tx bit number for each channel minus 1in TDM mode. - */ - uint32_t tx_tdm_chan_bits:5; - }; - uint32_t val; -} i2s_tx_conf1_reg_t; - -/** Type of tx_pcm2pdm_conf register - * I2S TX PCM2PDM configuration register - */ -typedef union { - struct { - uint32_t reserved_0:1; - /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2; - * I2S TX PDM OSR2 value - */ - uint32_t tx_pdm_sinc_osr2:4; - /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0; - * I2S TX PDM prescale for sigmadelta - */ - uint32_t tx_pdm_prescale:8; - /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1; - * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - */ - uint32_t tx_pdm_hp_in_shift:2; - /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1; - * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - */ - uint32_t tx_pdm_lp_in_shift:2; - /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1; - * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - */ - uint32_t tx_pdm_sinc_in_shift:2; - /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1; - * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - */ - uint32_t tx_pdm_sigmadelta_in_shift:2; - /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0; - * I2S TX PDM sigmadelta dither2 value - */ - uint32_t tx_pdm_sigmadelta_dither2:1; - /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1; - * I2S TX PDM sigmadelta dither value - */ - uint32_t tx_pdm_sigmadelta_dither:1; - /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0; - * I2S TX PDM dac mode enable - */ - uint32_t tx_pdm_dac_2out_en:1; - /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0; - * I2S TX PDM dac 2channel enable - */ - uint32_t tx_pdm_dac_mode_en:1; - /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0; - * I2S TX PDM Converter enable - */ - uint32_t pcm2pdm_conv_en:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} i2s_tx_pcm2pdm_conf_reg_t; - -/** Type of tx_pcm2pdm_conf1 register - * I2S TX PCM2PDM configuration register - */ -typedef union { - struct { - /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960; - * I2S TX PDM Fp - */ - uint32_t tx_pdm_fp:10; - /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480; - * I2S TX PDM Fs - */ - uint32_t tx_pdm_fs:10; - /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7; - * The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + - * I2S_TX_IIR_HP_MULT12_5[2:0]) - */ - uint32_t tx_iir_hp_mult12_5:3; - /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7; - * The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + - * I2S_TX_IIR_HP_MULT12_0[2:0]) - */ - uint32_t tx_iir_hp_mult12_0:3; - uint32_t reserved_26:6; - }; - uint32_t val; -} i2s_tx_pcm2pdm_conf1_reg_t; - -/** Type of tx_tdm_ctrl register - * I2S TX TDM mode control register - */ -typedef union { - struct { - /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan0_en:1; - /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan1_en:1; - /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan2_en:1; - /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan3_en:1; - /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan4_en:1; - /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan5_en:1; - /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan6_en:1; - /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan7_en:1; - /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan8_en:1; - /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan9_en:1; - /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan10_en:1; - /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan11_en:1; - /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan12_en:1; - /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan13_en:1; - /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan14_en:1; - /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1; - * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output - * 0 in this channel. - */ - uint32_t tx_tdm_chan15_en:1; - /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0; - * The total channel number of I2S TX TDM mode. - */ - uint32_t tx_tdm_tot_chan_num:4; - /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0; - * When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and - * only the data of the enabled channels is sent, then this bit should be set. Clear - * it when all the data stored in DMA TX buffer is for enabled channels. - */ - uint32_t tx_tdm_skip_msk_en:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} i2s_tx_tdm_ctrl_reg_t; - - -/** Group: RX clock and timing registers */ -/** Type of rx_timing register - * I2S RX timing control register - */ -typedef union { - struct { - /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0; - * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: - * delay by neg edge. 3: not used. - */ - uint32_t rx_sd_in_dm:2; - uint32_t reserved_2:2; - /** rx_sd1_in_dm : R/W; bitpos: [5:4]; default: 0; - * The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: - * delay by neg edge. 3: not used. - */ - uint32_t rx_sd1_in_dm:2; - uint32_t reserved_6:2; - /** rx_sd2_in_dm : R/W; bitpos: [9:8]; default: 0; - * The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: - * delay by neg edge. 3: not used. - */ - uint32_t rx_sd2_in_dm:2; - uint32_t reserved_10:2; - /** rx_sd3_in_dm : R/W; bitpos: [13:12]; default: 0; - * The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: - * delay by neg edge. 3: not used. - */ - uint32_t rx_sd3_in_dm:2; - uint32_t reserved_14:2; - /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0; - * The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: - * delay by neg edge. 3: not used. - */ - uint32_t rx_ws_out_dm:2; - uint32_t reserved_18:2; - /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0; - * The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: - * delay by neg edge. 3: not used. - */ - uint32_t rx_bck_out_dm:2; - uint32_t reserved_22:2; - /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0; - * The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: - * delay by neg edge. 3: not used. - */ - uint32_t rx_ws_in_dm:2; - uint32_t reserved_26:2; - /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0; - * The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: - * delay by neg edge. 3: not used. - */ - uint32_t rx_bck_in_dm:2; - uint32_t reserved_30:2; - }; - uint32_t val; -} i2s_rx_timing_reg_t; - - -/** Group: TX clock and timing registers */ -/** Type of tx_timing register - * I2S TX timing control register - */ -typedef union { - struct { - /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0; - * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: - * delay by neg edge. 3: not used. - */ - uint32_t tx_sd_out_dm:2; - uint32_t reserved_2:2; - /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0; - * The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: - * delay by neg edge. 3: not used. - */ - uint32_t tx_sd1_out_dm:2; - uint32_t reserved_6:10; - /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0; - * The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: - * delay by neg edge. 3: not used. - */ - uint32_t tx_ws_out_dm:2; - uint32_t reserved_18:2; - /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0; - * The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: - * delay by neg edge. 3: not used. - */ - uint32_t tx_bck_out_dm:2; - uint32_t reserved_22:2; - /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0; - * The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: - * delay by neg edge. 3: not used. - */ - uint32_t tx_ws_in_dm:2; - uint32_t reserved_26:2; - /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0; - * The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: - * delay by neg edge. 3: not used. - */ - uint32_t tx_bck_in_dm:2; - uint32_t reserved_30:2; - }; - uint32_t val; -} i2s_tx_timing_reg_t; - - -/** Group: Control and configuration registers */ -/** Type of lc_hung_conf register - * I2S HUNG configure register. - */ -typedef union { - struct { - /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16; - * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered - * when fifo hung counter is equal to this value - */ - uint32_t lc_fifo_timeout:8; - /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; - * The bits are used to scale tick counter threshold. The tick counter is reset when - * counter value >= 88000/2^i2s_lc_fifo_timeout_shift - */ - uint32_t lc_fifo_timeout_shift:3; - /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1; - * The enable bit for FIFO timeout - */ - uint32_t lc_fifo_timeout_ena:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} i2s_lc_hung_conf_reg_t; - -/** Type of conf_sigle_data register - * I2S signal data register - */ -typedef union { - struct { - /** single_data : R/W; bitpos: [31:0]; default: 0; - * The configured constant channel data to be sent out. - */ - uint32_t single_data:32; - }; - uint32_t val; -} i2s_conf_sigle_data_reg_t; - - -/** Group: TX status registers */ -/** Type of state register - * I2S TX status register - */ -typedef union { - struct { - /** tx_idle : RO; bitpos: [0]; default: 1; - * 1: i2s_tx is idle state. 0: i2s_tx is working. - */ - uint32_t tx_idle:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} i2s_state_reg_t; - - -/** Group: ETM registers */ -/** Type of etm_conf register - * I2S ETM configure register - */ -typedef union { - struct { - /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64; - * I2S ETM send x words event. When sending word number of - * reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. - */ - uint32_t etm_tx_send_word_num:10; - /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64; - * I2S ETM receive x words event. When receiving word number of - * reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. - */ - uint32_t etm_rx_receive_word_num:10; - uint32_t reserved_20:12; - }; - uint32_t val; -} i2s_etm_conf_reg_t; - - -/** Group: Sync counter registers */ -/** Type of fifo_cnt register - * I2S sync counter register - */ -typedef union { - struct { - /** tx_fifo_cnt : RO; bitpos: [30:0]; default: 0; - * tx fifo counter value. - */ - uint32_t tx_fifo_cnt:31; - /** tx_fifo_cnt_rst : WT; bitpos: [31]; default: 0; - * Set this bit to reset tx fifo counter. - */ - uint32_t tx_fifo_cnt_rst:1; - }; - uint32_t val; -} i2s_fifo_cnt_reg_t; - -/** Type of bck_cnt register - * I2S sync counter register - */ -typedef union { - struct { - /** tx_bck_cnt : RO; bitpos: [30:0]; default: 0; - * tx bck counter value. - */ - uint32_t tx_bck_cnt:31; - /** tx_bck_cnt_rst : WT; bitpos: [31]; default: 0; - * Set this bit to reset tx bck counter. - */ - uint32_t tx_bck_cnt_rst:1; - }; - uint32_t val; -} i2s_bck_cnt_reg_t; - - -/** Group: Clock registers */ -/** Type of clk_gate register - * Clock gate register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * set this bit to enable clock gate - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} i2s_clk_gate_reg_t; - - -/** Group: Version register */ -/** Type of date register - * Version control register - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 36713024; - * I2S version control register - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} i2s_date_reg_t; - - -typedef struct { - uint32_t reserved_000[3]; - volatile i2s_int_raw_reg_t int_raw; - volatile i2s_int_st_reg_t int_st; - volatile i2s_int_ena_reg_t int_ena; - volatile i2s_int_clr_reg_t int_clr; - uint32_t reserved_01c; - volatile i2s_rx_conf_reg_t rx_conf; - volatile i2s_tx_conf_reg_t tx_conf; - volatile i2s_rx_conf1_reg_t rx_conf1; - volatile i2s_tx_conf1_reg_t tx_conf1; - uint32_t reserved_030[4]; - volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf; - volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1; - volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf; - uint32_t reserved_04c; - volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl; - volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl; - volatile i2s_rx_timing_reg_t rx_timing; - volatile i2s_tx_timing_reg_t tx_timing; - volatile i2s_lc_hung_conf_reg_t lc_hung_conf; - volatile i2s_rxeof_num_reg_t rxeof_num; - volatile i2s_conf_sigle_data_reg_t conf_sigle_data; - volatile i2s_state_reg_t state; - volatile i2s_etm_conf_reg_t etm_conf; - volatile i2s_fifo_cnt_reg_t fifo_cnt; - volatile i2s_bck_cnt_reg_t bck_cnt; - volatile i2s_clk_gate_reg_t clk_gate; - volatile i2s_date_reg_t date; -} i2s_dev_t; - -extern i2s_dev_t I2S0; -extern i2s_dev_t I2S1; -extern i2s_dev_t I2S2; - -#ifndef __cplusplus -_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/i2s_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/i2s_struct.h index 727e9aae71d9..cdf8e401580b 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/i2s_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/i2s_struct.h @@ -282,10 +282,7 @@ typedef union { */ typedef union { struct { - /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0; - * I2S TX PDM bypass hp filter or not. The option has been removed. - */ - uint32_t tx_pdm_hp_bypass:1; + uint32_t reserved_0:1; /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2; * I2S TX PDM OSR2 value */ diff --git a/components/soc/esp32p4/register/hw_ver3/soc/interrupts.h b/components/soc/esp32p4/register/hw_ver3/soc/interrupts.h deleted file mode 100644 index 2b03a849a4e3..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/interrupts.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include - -#ifdef __cplusplus -extern "C" -{ -#endif - -//Interrupt hardware source table -//This table is decided by hardware, don't touch this. -typedef enum { - ETS_LP_RTC_INT_SOURCE, - ETS_LP_WDT_INT_SOURCE, - ETS_LP_TIMER_REG_0_INT_SOURCE, - ETS_LP_TIMER_REG_1_INT_SOURCE, - ETS_MB_HP_INT_SOURCE, - ETS_MB_LP_INT_SOURCE, - ETS_PMU_REG_0_INT_SOURCE, - ETS_PMU_REG_1_INT_SOURCE, - ETS_LP_ANAPERI_INT_SOURCE, - ETS_LP_ADC_INT_SOURCE, - ETS_LP_GPIO_INT_SOURCE, - ETS_LP_I2C_INT_SOURCE, - ETS_LP_I2S_INT_SOURCE, - ETS_LP_SPI_INT_SOURCE, - ETS_LP_TOUCH_INT_SOURCE, - ETS_LP_TSENS_INT_SOURCE, - ETS_LP_UART_INT_SOURCE, - ETS_LP_EFUSE_INT_SOURCE, - ETS_LP_SW_INT_SOURCE, - ETS_LP_SYSREG_INT_SOURCE, - ETS_LP_HUK_INT_SOURCE, - ETS_SYS_ICM_INT_SOURCE, - ETS_USB_DEVICE_INT_SOURCE, - ETS_SDIO_HOST_INT_SOURCE, - ETS_GDMA_INT_SOURCE, - ETS_SPI2_INT_SOURCE, - ETS_SPI3_INT_SOURCE, - ETS_I2S0_INT_SOURCE, - ETS_I2S1_INT_SOURCE, - ETS_I2S2_INT_SOURCE, - ETS_UHCI0_INT_SOURCE, - ETS_UART0_INT_SOURCE, - ETS_UART1_INT_SOURCE, - ETS_UART2_INT_SOURCE, - ETS_UART3_INT_SOURCE, - ETS_UART4_INT_SOURCE, - ETS_LCD_CAM_INT_SOURCE, - ETS_ADC_INT_SOURCE, - ETS_PWM0_INT_SOURCE, - ETS_PWM1_INT_SOURCE, - ETS_TWAI0_INT_SOURCE, - ETS_TWAI1_INT_SOURCE, - ETS_TWAI2_INT_SOURCE, - ETS_RMT_INT_SOURCE, - ETS_I2C0_INT_SOURCE, - ETS_I2C1_INT_SOURCE, - ETS_TIMERGRP0_T0_INT_SOURCE, - ETS_TIMERGRP0_T1_INT_SOURCE, - ETS_TIMERGRP0_WDT_INT_SOURCE, - ETS_TIMERGRP1_T0_INT_SOURCE, - ETS_TIMERGRP1_T1_INT_SOURCE, - ETS_TIMERGRP1_WDT_INT_SOURCE, - ETS_LEDC_INT_SOURCE, - ETS_SYSTIMER_TARGET0_INT_SOURCE, - ETS_SYSTIMER_TARGET1_INT_SOURCE, - ETS_SYSTIMER_TARGET2_INT_SOURCE, - ETS_AHB_PDMA_IN_CH0_INT_SOURCE, - ETS_AHB_PDMA_IN_CH1_INT_SOURCE, - ETS_AHB_PDMA_IN_CH2_INT_SOURCE, - ETS_AHB_PDMA_OUT_CH0_INT_SOURCE, - ETS_AHB_PDMA_OUT_CH1_INT_SOURCE, - ETS_AHB_PDMA_OUT_CH2_INT_SOURCE, - ETS_AXI_PDMA_IN_CH0_INT_SOURCE, - ETS_AXI_PDMA_IN_CH1_INT_SOURCE, - ETS_AXI_PDMA_IN_CH2_INT_SOURCE, - ETS_AXI_PDMA_OUT_CH0_INT_SOURCE, - ETS_AXI_PDMA_OUT_CH1_INT_SOURCE, - ETS_AXI_PDMA_OUT_CH2_INT_SOURCE, - ETS_RSA_INT_SOURCE, - ETS_AES_INT_SOURCE, - ETS_SHA_INT_SOURCE, - ETS_ECC_INT_SOURCE, - ETS_ECDSA_INT_SOURCE, - ETS_KM_INT_SOURCE, - ETS_GPIO_INT0_SOURCE, - ETS_GPIO_INT1_SOURCE, - ETS_GPIO_INT2_SOURCE, - ETS_GPIO_INT3_SOURCE, - ETS_GPIO_PAD_COMP_INT_SOURCE, - ETS_CPU_INT_FROM_CPU_0_SOURCE, - ETS_CPU_INT_FROM_CPU_1_SOURCE, - ETS_CPU_INT_FROM_CPU_2_SOURCE, - ETS_CPU_INT_FROM_CPU_3_SOURCE, - ETS_CACHE_INT_SOURCE, - ETS_FLASH_MSPI_INT_SOURCE, - ETS_CSI_BRIDGE_INT_SOURCE, - ETS_DSI_BRIDGE_INT_SOURCE, - ETS_CSI_INT_SOURCE, - ETS_DSI_INT_SOURCE, - ETS_GMII_PHY_INT_SOURCE, - ETS_LPI_INT_SOURCE, - ETS_PMT_INT_SOURCE, - ETS_SBD_INT_SOURCE, - ETS_USB_OTG_INT_SOURCE, - ETS_USB_OTG_ENDP_MULTI_PROC_INT_SOURCE, - ETS_JPEG_INT_SOURCE, - ETS_PPA_INT_SOURCE, - ETS_CORE0_TRACE_INT_SOURCE, - ETS_CORE1_TRACE_INT_SOURCE, - ETS_HP_CORE_CTRL_INT_SOURCE, - ETS_ISP_INT_SOURCE, - ETS_I3C_MST_INT_SOURCE, - ETS_I3C_SLV_INT_SOURCE, - ETS_USB_OTG11_INT_SOURCE, - ETS_DMA2D_IN_CH0_INT_SOURCE, - ETS_DMA2D_IN_CH1_INT_SOURCE, - ETS_DMA2D_OUT_CH0_INT_SOURCE, - ETS_DMA2D_OUT_CH1_INT_SOURCE, - ETS_DMA2D_OUT_CH2_INT_SOURCE, - ETS_PSRAM_MSPI_INT_SOURCE, - ETS_HP_SYSREG_INT_SOURCE, - ETS_PCNT_INT_SOURCE, - ETS_HP_PAU_INT_SOURCE, - ETS_HP_PARLIO_RX_INT_SOURCE, - ETS_HP_PARLIO_TX_INT_SOURCE, - ETS_H264_DMA2D_OUT_CH0_INT_SOURCE, - ETS_H264_DMA2D_OUT_CH1_INT_SOURCE, - ETS_H264_DMA2D_OUT_CH2_INT_SOURCE, - ETS_H264_DMA2D_OUT_CH3_INT_SOURCE, - ETS_H264_DMA2D_OUT_CH4_INT_SOURCE, - ETS_H264_DMA2D_IN_CH0_INT_SOURCE, - ETS_H264_DMA2D_IN_CH1_INT_SOURCE, - ETS_H264_DMA2D_IN_CH2_INT_SOURCE, - ETS_H264_DMA2D_IN_CH3_INT_SOURCE, - ETS_H264_DMA2D_IN_CH4_INT_SOURCE, - ETS_H264_DMA2D_IN_CH5_INT_SOURCE, - ETS_H264_REG_INT_SOURCE, - ETS_ASSIST_DEBUG_INT_SOURCE, - ETS_DMA2D_IN_CH2_INT_SOURCE, - ETS_DMA2D_OUT_CH3_INT_SOURCE, - ETS_AXI_PERF_MON_INT_SOURCE, - ETS_MAX_INTR_SOURCE, -} periph_interrupt_t; - -extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_reg.h deleted file mode 100644 index c651fb6e5613..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_reg.h +++ /dev/null @@ -1,5466 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -// definitions below are generated from pin_txt.csv -#define PERIPHS_IO_MUX_U_PAD_GPIO0 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO0_GPIO0_0 0 -#define FUNC_GPIO0_GPIO0 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO1 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO1_GPIO1_0 0 -#define FUNC_GPIO1_GPIO1 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO2 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO2_MTCK 0 -#define FUNC_GPIO2_GPIO2 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO3 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO3_MTDI 0 -#define FUNC_GPIO3_GPIO3 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO4 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO4_MTMS 0 -#define FUNC_GPIO4_GPIO4 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO5 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO5_MTDO 0 -#define FUNC_GPIO5_GPIO5 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO6 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO6_GPIO6_0 0 -#define FUNC_GPIO6_GPIO6 1 -#define FUNC_GPIO6_SPI2_HOLD_PAD 3 - -#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO7_GPIO7_0 0 -#define FUNC_GPIO7_GPIO7 1 -#define FUNC_GPIO7_SPI2_CS_PAD 3 - -#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO8_GPIO8_0 0 -#define FUNC_GPIO8_GPIO8 1 -#define FUNC_GPIO8_UART0_RTS_PAD 2 -#define FUNC_GPIO8_SPI2_D_PAD 3 - -#define PERIPHS_IO_MUX_U_PAD_GPIO9 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO9_GPIO9_0 0 -#define FUNC_GPIO9_GPIO9 1 -#define FUNC_GPIO9_UART0_CTS_PAD 2 -#define FUNC_GPIO9_SPI2_CK_PAD 3 - -#define PERIPHS_IO_MUX_U_PAD_GPIO10 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO10_GPIO10_0 0 -#define FUNC_GPIO10_GPIO10 1 -#define FUNC_GPIO10_UART1_TXD_PAD 2 -#define FUNC_GPIO10_SPI2_Q_PAD 3 - -#define PERIPHS_IO_MUX_U_PAD_GPIO11 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO11_GPIO11_0 0 -#define FUNC_GPIO11_GPIO11 1 -#define FUNC_GPIO11_UART1_RXD_PAD 2 -#define FUNC_GPIO11_SPI2_WP_PAD 3 - -#define PERIPHS_IO_MUX_U_PAD_GPIO12 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO12_GPIO12_0 0 -#define FUNC_GPIO12_GPIO12 1 -#define FUNC_GPIO12_UART1_RTS_PAD 2 - -#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO13_GPIO13_0 0 -#define FUNC_GPIO13_GPIO13 1 -#define FUNC_GPIO13_UART1_CTS_PAD 2 - -#define PERIPHS_IO_MUX_U_PAD_GPIO14 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO14_GPIO14_0 0 -#define FUNC_GPIO14_GPIO14 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO15 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO15_GPIO15_0 0 -#define FUNC_GPIO15_GPIO15 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO16 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO16_GPIO16_0 0 -#define FUNC_GPIO16_GPIO16 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO17 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO17_GPIO17_0 0 -#define FUNC_GPIO17_GPIO17 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO18 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO18_GPIO18_0 0 -#define FUNC_GPIO18_GPIO18 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO19 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO19_GPIO19_0 0 -#define FUNC_GPIO19_GPIO19 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO20 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO20_GPIO20_0 0 -#define FUNC_GPIO20_GPIO20 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO21 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO21_GPIO21_0 0 -#define FUNC_GPIO21_GPIO21 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO22_GPIO22_0 0 -#define FUNC_GPIO22_GPIO22 1 -#define FUNC_GPIO22_DBG_PSRAM_CK_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO23 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO23_GPIO23_0 0 -#define FUNC_GPIO23_GPIO23 1 -#define FUNC_GPIO23_REF_50M_CLK_PAD 3 -#define FUNC_GPIO23_DBG_PSRAM_CS_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO24 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO24_GPIO24_0 0 -#define FUNC_GPIO24_GPIO24 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO25 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO25_GPIO25_0 0 -#define FUNC_GPIO25_GPIO25 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO26 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO26_GPIO26_0 0 -#define FUNC_GPIO26_GPIO26 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO27 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO27_GPIO27_0 0 -#define FUNC_GPIO27_GPIO27 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO28 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO28_GPIO28_0 0 -#define FUNC_GPIO28_GPIO28 1 -#define FUNC_GPIO28_SPI2_CS_PAD 2 -#define FUNC_GPIO28_GMAC_PHY_RXDV_PAD 3 -#define FUNC_GPIO28_DBG_PSRAM_D_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO29 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO29_GPIO29_0 0 -#define FUNC_GPIO29_GPIO29 1 -#define FUNC_GPIO29_SPI2_D_PAD 2 -#define FUNC_GPIO29_GMAC_PHY_RXD0_PAD 3 -#define FUNC_GPIO29_DBG_PSRAM_Q_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO30 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO30_GPIO30_0 0 -#define FUNC_GPIO30_GPIO30 1 -#define FUNC_GPIO30_SPI2_CK_PAD 2 -#define FUNC_GPIO30_GMAC_PHY_RXD1_PAD 3 -#define FUNC_GPIO30_DBG_PSRAM_WP_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO31 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO31_GPIO31_0 0 -#define FUNC_GPIO31_GPIO31 1 -#define FUNC_GPIO31_SPI2_Q_PAD 2 -#define FUNC_GPIO31_GMAC_PHY_RXER_PAD 3 -#define FUNC_GPIO31_DBG_PSRAM_HOLD_PAD 4 - -// Strapping: Diag Group Sel1 -#define PERIPHS_IO_MUX_U_PAD_GPIO32 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO32_GPIO32_0 0 -#define FUNC_GPIO32_GPIO32 1 -#define FUNC_GPIO32_SPI2_HOLD_PAD 2 -#define FUNC_GPIO32_GMAC_RMII_CLK_PAD 3 -#define FUNC_GPIO32_DBG_PSRAM_DQ4_PAD 4 - -// Strapping: Diag Group Sel0 -#define PERIPHS_IO_MUX_U_PAD_GPIO33 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO33_GPIO33_0 0 -#define FUNC_GPIO33_GPIO33 1 -#define FUNC_GPIO33_SPI2_WP_PAD 2 -#define FUNC_GPIO33_GMAC_PHY_TXEN_PAD 3 -#define FUNC_GPIO33_DBG_PSRAM_DQ5_PAD 4 - -// Strapping: USB2JTAG select: 1->usb2jtag 0-> pad_jtag -#define PERIPHS_IO_MUX_U_PAD_GPIO34 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO34_GPIO34_0 0 -#define FUNC_GPIO34_GPIO34 1 -#define FUNC_GPIO34_SPI2_IO4_PAD 2 -#define FUNC_GPIO34_GMAC_PHY_TXD0_PAD 3 -#define FUNC_GPIO34_DBG_PSRAM_DQ6_PAD 4 - -// Strapping: Boot Mode select 3 -#define PERIPHS_IO_MUX_U_PAD_GPIO35 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO35_GPIO35_0 0 -#define FUNC_GPIO35_GPIO35 1 -#define FUNC_GPIO35_SPI2_IO5_PAD 2 -#define FUNC_GPIO35_GMAC_PHY_TXD1_PAD 3 -#define FUNC_GPIO35_DBG_PSRAM_DQ7_PAD 4 - -// Strapping: Boot Mode select 2 -#define PERIPHS_IO_MUX_U_PAD_GPIO36 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO36_GPIO36_0 0 -#define FUNC_GPIO36_GPIO36 1 -#define FUNC_GPIO36_SPI2_IO6_PAD 2 -#define FUNC_GPIO36_GMAC_PHY_TXER_PAD 3 -#define FUNC_GPIO36_DBG_PSRAM_DQS_0_PAD 4 - -// Strapping: Boot Mode select 1 -#define PERIPHS_IO_MUX_U_PAD_GPIO37 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO37_UART0_TXD_PAD 0 -#define FUNC_GPIO37_GPIO37 1 -#define FUNC_GPIO37_SPI2_IO7_PAD 2 - -// Strapping: Boot Mode select 0 -#define PERIPHS_IO_MUX_U_PAD_GPIO38 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO38_UART0_RXD_PAD 0 -#define FUNC_GPIO38_GPIO38 1 -#define FUNC_GPIO38_SPI2_DQS_PAD 2 - -#define PERIPHS_IO_MUX_U_PAD_GPIO39 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO39_SD1_CDATA0_PAD 0 -#define FUNC_GPIO39_GPIO39 1 -#define FUNC_GPIO39_BIST_PAD 2 -#define FUNC_GPIO39_REF_50M_CLK_PAD 3 -#define FUNC_GPIO39_DBG_PSRAM_DQ8_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO40 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO40_SD1_CDATA1_PAD 0 -#define FUNC_GPIO40_GPIO40 1 -#define FUNC_GPIO40_BIST_PAD 2 -#define FUNC_GPIO40_GMAC_PHY_TXEN_PAD 3 -#define FUNC_GPIO40_DBG_PSRAM_DQ9_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO41 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO41_SD1_CDATA2_PAD 0 -#define FUNC_GPIO41_GPIO41 1 -#define FUNC_GPIO41_BIST_PAD 2 -#define FUNC_GPIO41_GMAC_PHY_TXD0_PAD 3 -#define FUNC_GPIO41_DBG_PSRAM_DQ10_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO42 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO42_SD1_CDATA3_PAD 0 -#define FUNC_GPIO42_GPIO42 1 -#define FUNC_GPIO42_BIST_PAD 2 -#define FUNC_GPIO42_GMAC_PHY_TXD1_PAD 3 -#define FUNC_GPIO42_DBG_PSRAM_DQ11_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO43 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO43_SD1_CCLK_PAD 0 -#define FUNC_GPIO43_GPIO43 1 -#define FUNC_GPIO43_BIST_PAD 2 -#define FUNC_GPIO43_GMAC_PHY_TXER_PAD 3 -#define FUNC_GPIO43_DBG_PSRAM_DQ12_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO44 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO44_SD1_CCMD_PAD 0 -#define FUNC_GPIO44_GPIO44 1 -#define FUNC_GPIO44_BIST_PAD 2 -#define FUNC_GPIO44_GMAC_RMII_CLK_PAD 3 -#define FUNC_GPIO44_DBG_PSRAM_DQ13_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO45 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO45_SD1_CDATA4_PAD 0 -#define FUNC_GPIO45_GPIO45 1 -#define FUNC_GPIO45_BIST_PAD 2 -#define FUNC_GPIO45_GMAC_PHY_RXDV_PAD 3 -#define FUNC_GPIO45_DBG_PSRAM_DQ14_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO46 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO46_SD1_CDATA5_PAD 0 -#define FUNC_GPIO46_GPIO46 1 -#define FUNC_GPIO46_BIST_PAD 2 -#define FUNC_GPIO46_GMAC_PHY_RXD0_PAD 3 -#define FUNC_GPIO46_DBG_PSRAM_DQ15_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO47 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO47_SD1_CDATA6_PAD 0 -#define FUNC_GPIO47_GPIO47 1 -#define FUNC_GPIO47_BIST_PAD 2 -#define FUNC_GPIO47_GMAC_PHY_RXD1_PAD 3 -#define FUNC_GPIO47_DBG_PSRAM_DQS_1_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO48 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO48_SD1_CDATA7_PAD 0 -#define FUNC_GPIO48_GPIO48 1 -#define FUNC_GPIO48_BIST_PAD 2 -#define FUNC_GPIO48_GMAC_PHY_RXER_PAD 3 - -#define PERIPHS_IO_MUX_U_PAD_GPIO49 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO49_GPIO49_0 0 -#define FUNC_GPIO49_GPIO49 1 -#define FUNC_GPIO49_GMAC_PHY_TXEN_PAD 3 -#define FUNC_GPIO49_DBG_FLASH_CS_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO50 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO50_GPIO50_0 0 -#define FUNC_GPIO50_GPIO50 1 -#define FUNC_GPIO50_GMAC_RMII_CLK_PAD 3 -#define FUNC_GPIO50_DBG_FLASH_Q_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO51 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO51_GPIO51_0 0 -#define FUNC_GPIO51_GPIO51 1 -#define FUNC_GPIO51_GMAC_PHY_RXDV_PAD 3 -#define FUNC_GPIO51_DBG_FLASH_WP_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO52 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO52_GPIO52_0 0 -#define FUNC_GPIO52_GPIO52 1 -#define FUNC_GPIO52_GMAC_PHY_RXD0_PAD 3 -#define FUNC_GPIO52_DBG_FLASH_HOLD_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO53 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO53_GPIO53_0 0 -#define FUNC_GPIO53_GPIO53 1 -#define FUNC_GPIO53_GMAC_PHY_RXD1_PAD 3 -#define FUNC_GPIO53_DBG_FLASH_CK_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO54 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO54_GPIO54_0 0 -#define FUNC_GPIO54_GPIO54 1 -#define FUNC_GPIO54_GMAC_PHY_RXER_PAD 3 -#define FUNC_GPIO54_DBG_FLASH_D_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO55 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO55_GPIO55_0 0 -#define FUNC_GPIO55_GPIO55 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO56 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO56_GPIO56_0 0 -#define FUNC_GPIO56_GPIO56 1 - - -/** IO_MUX_gpio0_REG register - * iomux control register for gpio0 - */ -#define IO_MUX_GPIO0_REG (DR_REG_IO_MUX_BASE + 0x4) -/** IO_MUX_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO0_MCU_OE (BIT(0)) -#define IO_MUX_GPIO0_MCU_OE_M (IO_MUX_GPIO0_MCU_OE_V << IO_MUX_GPIO0_MCU_OE_S) -#define IO_MUX_GPIO0_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO0_MCU_OE_S 0 -/** IO_MUX_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO0_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO0_SLP_SEL_M (IO_MUX_GPIO0_SLP_SEL_V << IO_MUX_GPIO0_SLP_SEL_S) -#define IO_MUX_GPIO0_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO0_SLP_SEL_S 1 -/** IO_MUX_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO0_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO0_MCU_WPD_M (IO_MUX_GPIO0_MCU_WPD_V << IO_MUX_GPIO0_MCU_WPD_S) -#define IO_MUX_GPIO0_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO0_MCU_WPD_S 2 -/** IO_MUX_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO0_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO0_MCU_WPU_M (IO_MUX_GPIO0_MCU_WPU_V << IO_MUX_GPIO0_MCU_WPU_S) -#define IO_MUX_GPIO0_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO0_MCU_WPU_S 3 -/** IO_MUX_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO0_MCU_IE (BIT(4)) -#define IO_MUX_GPIO0_MCU_IE_M (IO_MUX_GPIO0_MCU_IE_V << IO_MUX_GPIO0_MCU_IE_S) -#define IO_MUX_GPIO0_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO0_MCU_IE_S 4 -/** IO_MUX_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO0_MCU_DRV 0x00000003U -#define IO_MUX_GPIO0_MCU_DRV_M (IO_MUX_GPIO0_MCU_DRV_V << IO_MUX_GPIO0_MCU_DRV_S) -#define IO_MUX_GPIO0_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO0_MCU_DRV_S 5 -/** IO_MUX_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO0_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO0_FUN_WPD_M (IO_MUX_GPIO0_FUN_WPD_V << IO_MUX_GPIO0_FUN_WPD_S) -#define IO_MUX_GPIO0_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO0_FUN_WPD_S 7 -/** IO_MUX_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO0_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO0_FUN_WPU_M (IO_MUX_GPIO0_FUN_WPU_V << IO_MUX_GPIO0_FUN_WPU_S) -#define IO_MUX_GPIO0_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO0_FUN_WPU_S 8 -/** IO_MUX_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO0_FUN_IE (BIT(9)) -#define IO_MUX_GPIO0_FUN_IE_M (IO_MUX_GPIO0_FUN_IE_V << IO_MUX_GPIO0_FUN_IE_S) -#define IO_MUX_GPIO0_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO0_FUN_IE_S 9 -/** IO_MUX_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO0_FUN_DRV 0x00000003U -#define IO_MUX_GPIO0_FUN_DRV_M (IO_MUX_GPIO0_FUN_DRV_V << IO_MUX_GPIO0_FUN_DRV_S) -#define IO_MUX_GPIO0_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO0_FUN_DRV_S 10 -/** IO_MUX_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO0_MCU_SEL 0x00000007U -#define IO_MUX_GPIO0_MCU_SEL_M (IO_MUX_GPIO0_MCU_SEL_V << IO_MUX_GPIO0_MCU_SEL_S) -#define IO_MUX_GPIO0_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO0_MCU_SEL_S 12 -/** IO_MUX_GPIO0_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO0_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO0_FILTER_EN_M (IO_MUX_GPIO0_FILTER_EN_V << IO_MUX_GPIO0_FILTER_EN_S) -#define IO_MUX_GPIO0_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO0_FILTER_EN_S 15 - -/** IO_MUX_gpio1_REG register - * iomux control register for gpio1 - */ -#define IO_MUX_GPIO1_REG (DR_REG_IO_MUX_BASE + 0x8) -/** IO_MUX_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO1_MCU_OE (BIT(0)) -#define IO_MUX_GPIO1_MCU_OE_M (IO_MUX_GPIO1_MCU_OE_V << IO_MUX_GPIO1_MCU_OE_S) -#define IO_MUX_GPIO1_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO1_MCU_OE_S 0 -/** IO_MUX_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO1_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO1_SLP_SEL_M (IO_MUX_GPIO1_SLP_SEL_V << IO_MUX_GPIO1_SLP_SEL_S) -#define IO_MUX_GPIO1_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO1_SLP_SEL_S 1 -/** IO_MUX_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO1_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO1_MCU_WPD_M (IO_MUX_GPIO1_MCU_WPD_V << IO_MUX_GPIO1_MCU_WPD_S) -#define IO_MUX_GPIO1_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO1_MCU_WPD_S 2 -/** IO_MUX_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO1_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO1_MCU_WPU_M (IO_MUX_GPIO1_MCU_WPU_V << IO_MUX_GPIO1_MCU_WPU_S) -#define IO_MUX_GPIO1_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO1_MCU_WPU_S 3 -/** IO_MUX_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO1_MCU_IE (BIT(4)) -#define IO_MUX_GPIO1_MCU_IE_M (IO_MUX_GPIO1_MCU_IE_V << IO_MUX_GPIO1_MCU_IE_S) -#define IO_MUX_GPIO1_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO1_MCU_IE_S 4 -/** IO_MUX_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO1_MCU_DRV 0x00000003U -#define IO_MUX_GPIO1_MCU_DRV_M (IO_MUX_GPIO1_MCU_DRV_V << IO_MUX_GPIO1_MCU_DRV_S) -#define IO_MUX_GPIO1_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO1_MCU_DRV_S 5 -/** IO_MUX_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO1_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO1_FUN_WPD_M (IO_MUX_GPIO1_FUN_WPD_V << IO_MUX_GPIO1_FUN_WPD_S) -#define IO_MUX_GPIO1_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO1_FUN_WPD_S 7 -/** IO_MUX_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO1_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO1_FUN_WPU_M (IO_MUX_GPIO1_FUN_WPU_V << IO_MUX_GPIO1_FUN_WPU_S) -#define IO_MUX_GPIO1_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO1_FUN_WPU_S 8 -/** IO_MUX_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO1_FUN_IE (BIT(9)) -#define IO_MUX_GPIO1_FUN_IE_M (IO_MUX_GPIO1_FUN_IE_V << IO_MUX_GPIO1_FUN_IE_S) -#define IO_MUX_GPIO1_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO1_FUN_IE_S 9 -/** IO_MUX_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO1_FUN_DRV 0x00000003U -#define IO_MUX_GPIO1_FUN_DRV_M (IO_MUX_GPIO1_FUN_DRV_V << IO_MUX_GPIO1_FUN_DRV_S) -#define IO_MUX_GPIO1_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO1_FUN_DRV_S 10 -/** IO_MUX_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO1_MCU_SEL 0x00000007U -#define IO_MUX_GPIO1_MCU_SEL_M (IO_MUX_GPIO1_MCU_SEL_V << IO_MUX_GPIO1_MCU_SEL_S) -#define IO_MUX_GPIO1_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO1_MCU_SEL_S 12 -/** IO_MUX_GPIO1_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO1_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO1_FILTER_EN_M (IO_MUX_GPIO1_FILTER_EN_V << IO_MUX_GPIO1_FILTER_EN_S) -#define IO_MUX_GPIO1_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO1_FILTER_EN_S 15 - -/** IO_MUX_gpio2_REG register - * iomux control register for gpio2 - */ -#define IO_MUX_GPIO2_REG (DR_REG_IO_MUX_BASE + 0xc) -/** IO_MUX_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO2_MCU_OE (BIT(0)) -#define IO_MUX_GPIO2_MCU_OE_M (IO_MUX_GPIO2_MCU_OE_V << IO_MUX_GPIO2_MCU_OE_S) -#define IO_MUX_GPIO2_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO2_MCU_OE_S 0 -/** IO_MUX_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO2_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO2_SLP_SEL_M (IO_MUX_GPIO2_SLP_SEL_V << IO_MUX_GPIO2_SLP_SEL_S) -#define IO_MUX_GPIO2_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO2_SLP_SEL_S 1 -/** IO_MUX_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO2_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO2_MCU_WPD_M (IO_MUX_GPIO2_MCU_WPD_V << IO_MUX_GPIO2_MCU_WPD_S) -#define IO_MUX_GPIO2_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO2_MCU_WPD_S 2 -/** IO_MUX_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO2_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO2_MCU_WPU_M (IO_MUX_GPIO2_MCU_WPU_V << IO_MUX_GPIO2_MCU_WPU_S) -#define IO_MUX_GPIO2_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO2_MCU_WPU_S 3 -/** IO_MUX_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO2_MCU_IE (BIT(4)) -#define IO_MUX_GPIO2_MCU_IE_M (IO_MUX_GPIO2_MCU_IE_V << IO_MUX_GPIO2_MCU_IE_S) -#define IO_MUX_GPIO2_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO2_MCU_IE_S 4 -/** IO_MUX_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO2_MCU_DRV 0x00000003U -#define IO_MUX_GPIO2_MCU_DRV_M (IO_MUX_GPIO2_MCU_DRV_V << IO_MUX_GPIO2_MCU_DRV_S) -#define IO_MUX_GPIO2_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO2_MCU_DRV_S 5 -/** IO_MUX_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO2_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO2_FUN_WPD_M (IO_MUX_GPIO2_FUN_WPD_V << IO_MUX_GPIO2_FUN_WPD_S) -#define IO_MUX_GPIO2_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO2_FUN_WPD_S 7 -/** IO_MUX_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO2_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO2_FUN_WPU_M (IO_MUX_GPIO2_FUN_WPU_V << IO_MUX_GPIO2_FUN_WPU_S) -#define IO_MUX_GPIO2_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO2_FUN_WPU_S 8 -/** IO_MUX_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO2_FUN_IE (BIT(9)) -#define IO_MUX_GPIO2_FUN_IE_M (IO_MUX_GPIO2_FUN_IE_V << IO_MUX_GPIO2_FUN_IE_S) -#define IO_MUX_GPIO2_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO2_FUN_IE_S 9 -/** IO_MUX_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO2_FUN_DRV 0x00000003U -#define IO_MUX_GPIO2_FUN_DRV_M (IO_MUX_GPIO2_FUN_DRV_V << IO_MUX_GPIO2_FUN_DRV_S) -#define IO_MUX_GPIO2_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO2_FUN_DRV_S 10 -/** IO_MUX_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO2_MCU_SEL 0x00000007U -#define IO_MUX_GPIO2_MCU_SEL_M (IO_MUX_GPIO2_MCU_SEL_V << IO_MUX_GPIO2_MCU_SEL_S) -#define IO_MUX_GPIO2_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO2_MCU_SEL_S 12 -/** IO_MUX_GPIO2_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO2_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO2_FILTER_EN_M (IO_MUX_GPIO2_FILTER_EN_V << IO_MUX_GPIO2_FILTER_EN_S) -#define IO_MUX_GPIO2_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO2_FILTER_EN_S 15 - -/** IO_MUX_gpio3_REG register - * iomux control register for gpio3 - */ -#define IO_MUX_GPIO3_REG (DR_REG_IO_MUX_BASE + 0x10) -/** IO_MUX_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO3_MCU_OE (BIT(0)) -#define IO_MUX_GPIO3_MCU_OE_M (IO_MUX_GPIO3_MCU_OE_V << IO_MUX_GPIO3_MCU_OE_S) -#define IO_MUX_GPIO3_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO3_MCU_OE_S 0 -/** IO_MUX_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO3_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO3_SLP_SEL_M (IO_MUX_GPIO3_SLP_SEL_V << IO_MUX_GPIO3_SLP_SEL_S) -#define IO_MUX_GPIO3_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO3_SLP_SEL_S 1 -/** IO_MUX_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO3_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO3_MCU_WPD_M (IO_MUX_GPIO3_MCU_WPD_V << IO_MUX_GPIO3_MCU_WPD_S) -#define IO_MUX_GPIO3_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO3_MCU_WPD_S 2 -/** IO_MUX_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO3_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO3_MCU_WPU_M (IO_MUX_GPIO3_MCU_WPU_V << IO_MUX_GPIO3_MCU_WPU_S) -#define IO_MUX_GPIO3_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO3_MCU_WPU_S 3 -/** IO_MUX_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO3_MCU_IE (BIT(4)) -#define IO_MUX_GPIO3_MCU_IE_M (IO_MUX_GPIO3_MCU_IE_V << IO_MUX_GPIO3_MCU_IE_S) -#define IO_MUX_GPIO3_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO3_MCU_IE_S 4 -/** IO_MUX_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO3_MCU_DRV 0x00000003U -#define IO_MUX_GPIO3_MCU_DRV_M (IO_MUX_GPIO3_MCU_DRV_V << IO_MUX_GPIO3_MCU_DRV_S) -#define IO_MUX_GPIO3_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO3_MCU_DRV_S 5 -/** IO_MUX_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO3_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO3_FUN_WPD_M (IO_MUX_GPIO3_FUN_WPD_V << IO_MUX_GPIO3_FUN_WPD_S) -#define IO_MUX_GPIO3_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO3_FUN_WPD_S 7 -/** IO_MUX_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO3_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO3_FUN_WPU_M (IO_MUX_GPIO3_FUN_WPU_V << IO_MUX_GPIO3_FUN_WPU_S) -#define IO_MUX_GPIO3_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO3_FUN_WPU_S 8 -/** IO_MUX_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO3_FUN_IE (BIT(9)) -#define IO_MUX_GPIO3_FUN_IE_M (IO_MUX_GPIO3_FUN_IE_V << IO_MUX_GPIO3_FUN_IE_S) -#define IO_MUX_GPIO3_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO3_FUN_IE_S 9 -/** IO_MUX_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO3_FUN_DRV 0x00000003U -#define IO_MUX_GPIO3_FUN_DRV_M (IO_MUX_GPIO3_FUN_DRV_V << IO_MUX_GPIO3_FUN_DRV_S) -#define IO_MUX_GPIO3_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO3_FUN_DRV_S 10 -/** IO_MUX_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO3_MCU_SEL 0x00000007U -#define IO_MUX_GPIO3_MCU_SEL_M (IO_MUX_GPIO3_MCU_SEL_V << IO_MUX_GPIO3_MCU_SEL_S) -#define IO_MUX_GPIO3_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO3_MCU_SEL_S 12 -/** IO_MUX_GPIO3_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO3_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO3_FILTER_EN_M (IO_MUX_GPIO3_FILTER_EN_V << IO_MUX_GPIO3_FILTER_EN_S) -#define IO_MUX_GPIO3_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO3_FILTER_EN_S 15 - -/** IO_MUX_gpio4_REG register - * iomux control register for gpio4 - */ -#define IO_MUX_GPIO4_REG (DR_REG_IO_MUX_BASE + 0x14) -/** IO_MUX_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO4_MCU_OE (BIT(0)) -#define IO_MUX_GPIO4_MCU_OE_M (IO_MUX_GPIO4_MCU_OE_V << IO_MUX_GPIO4_MCU_OE_S) -#define IO_MUX_GPIO4_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO4_MCU_OE_S 0 -/** IO_MUX_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO4_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO4_SLP_SEL_M (IO_MUX_GPIO4_SLP_SEL_V << IO_MUX_GPIO4_SLP_SEL_S) -#define IO_MUX_GPIO4_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO4_SLP_SEL_S 1 -/** IO_MUX_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO4_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO4_MCU_WPD_M (IO_MUX_GPIO4_MCU_WPD_V << IO_MUX_GPIO4_MCU_WPD_S) -#define IO_MUX_GPIO4_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO4_MCU_WPD_S 2 -/** IO_MUX_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO4_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO4_MCU_WPU_M (IO_MUX_GPIO4_MCU_WPU_V << IO_MUX_GPIO4_MCU_WPU_S) -#define IO_MUX_GPIO4_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO4_MCU_WPU_S 3 -/** IO_MUX_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO4_MCU_IE (BIT(4)) -#define IO_MUX_GPIO4_MCU_IE_M (IO_MUX_GPIO4_MCU_IE_V << IO_MUX_GPIO4_MCU_IE_S) -#define IO_MUX_GPIO4_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO4_MCU_IE_S 4 -/** IO_MUX_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO4_MCU_DRV 0x00000003U -#define IO_MUX_GPIO4_MCU_DRV_M (IO_MUX_GPIO4_MCU_DRV_V << IO_MUX_GPIO4_MCU_DRV_S) -#define IO_MUX_GPIO4_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO4_MCU_DRV_S 5 -/** IO_MUX_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO4_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO4_FUN_WPD_M (IO_MUX_GPIO4_FUN_WPD_V << IO_MUX_GPIO4_FUN_WPD_S) -#define IO_MUX_GPIO4_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO4_FUN_WPD_S 7 -/** IO_MUX_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO4_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO4_FUN_WPU_M (IO_MUX_GPIO4_FUN_WPU_V << IO_MUX_GPIO4_FUN_WPU_S) -#define IO_MUX_GPIO4_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO4_FUN_WPU_S 8 -/** IO_MUX_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO4_FUN_IE (BIT(9)) -#define IO_MUX_GPIO4_FUN_IE_M (IO_MUX_GPIO4_FUN_IE_V << IO_MUX_GPIO4_FUN_IE_S) -#define IO_MUX_GPIO4_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO4_FUN_IE_S 9 -/** IO_MUX_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO4_FUN_DRV 0x00000003U -#define IO_MUX_GPIO4_FUN_DRV_M (IO_MUX_GPIO4_FUN_DRV_V << IO_MUX_GPIO4_FUN_DRV_S) -#define IO_MUX_GPIO4_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO4_FUN_DRV_S 10 -/** IO_MUX_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO4_MCU_SEL 0x00000007U -#define IO_MUX_GPIO4_MCU_SEL_M (IO_MUX_GPIO4_MCU_SEL_V << IO_MUX_GPIO4_MCU_SEL_S) -#define IO_MUX_GPIO4_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO4_MCU_SEL_S 12 -/** IO_MUX_GPIO4_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO4_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO4_FILTER_EN_M (IO_MUX_GPIO4_FILTER_EN_V << IO_MUX_GPIO4_FILTER_EN_S) -#define IO_MUX_GPIO4_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO4_FILTER_EN_S 15 - -/** IO_MUX_gpio5_REG register - * iomux control register for gpio5 - */ -#define IO_MUX_GPIO5_REG (DR_REG_IO_MUX_BASE + 0x18) -/** IO_MUX_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO5_MCU_OE (BIT(0)) -#define IO_MUX_GPIO5_MCU_OE_M (IO_MUX_GPIO5_MCU_OE_V << IO_MUX_GPIO5_MCU_OE_S) -#define IO_MUX_GPIO5_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO5_MCU_OE_S 0 -/** IO_MUX_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO5_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO5_SLP_SEL_M (IO_MUX_GPIO5_SLP_SEL_V << IO_MUX_GPIO5_SLP_SEL_S) -#define IO_MUX_GPIO5_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO5_SLP_SEL_S 1 -/** IO_MUX_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO5_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO5_MCU_WPD_M (IO_MUX_GPIO5_MCU_WPD_V << IO_MUX_GPIO5_MCU_WPD_S) -#define IO_MUX_GPIO5_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO5_MCU_WPD_S 2 -/** IO_MUX_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO5_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO5_MCU_WPU_M (IO_MUX_GPIO5_MCU_WPU_V << IO_MUX_GPIO5_MCU_WPU_S) -#define IO_MUX_GPIO5_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO5_MCU_WPU_S 3 -/** IO_MUX_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO5_MCU_IE (BIT(4)) -#define IO_MUX_GPIO5_MCU_IE_M (IO_MUX_GPIO5_MCU_IE_V << IO_MUX_GPIO5_MCU_IE_S) -#define IO_MUX_GPIO5_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO5_MCU_IE_S 4 -/** IO_MUX_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO5_MCU_DRV 0x00000003U -#define IO_MUX_GPIO5_MCU_DRV_M (IO_MUX_GPIO5_MCU_DRV_V << IO_MUX_GPIO5_MCU_DRV_S) -#define IO_MUX_GPIO5_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO5_MCU_DRV_S 5 -/** IO_MUX_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO5_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO5_FUN_WPD_M (IO_MUX_GPIO5_FUN_WPD_V << IO_MUX_GPIO5_FUN_WPD_S) -#define IO_MUX_GPIO5_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO5_FUN_WPD_S 7 -/** IO_MUX_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO5_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO5_FUN_WPU_M (IO_MUX_GPIO5_FUN_WPU_V << IO_MUX_GPIO5_FUN_WPU_S) -#define IO_MUX_GPIO5_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO5_FUN_WPU_S 8 -/** IO_MUX_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO5_FUN_IE (BIT(9)) -#define IO_MUX_GPIO5_FUN_IE_M (IO_MUX_GPIO5_FUN_IE_V << IO_MUX_GPIO5_FUN_IE_S) -#define IO_MUX_GPIO5_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO5_FUN_IE_S 9 -/** IO_MUX_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO5_FUN_DRV 0x00000003U -#define IO_MUX_GPIO5_FUN_DRV_M (IO_MUX_GPIO5_FUN_DRV_V << IO_MUX_GPIO5_FUN_DRV_S) -#define IO_MUX_GPIO5_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO5_FUN_DRV_S 10 -/** IO_MUX_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO5_MCU_SEL 0x00000007U -#define IO_MUX_GPIO5_MCU_SEL_M (IO_MUX_GPIO5_MCU_SEL_V << IO_MUX_GPIO5_MCU_SEL_S) -#define IO_MUX_GPIO5_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO5_MCU_SEL_S 12 -/** IO_MUX_GPIO5_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO5_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO5_FILTER_EN_M (IO_MUX_GPIO5_FILTER_EN_V << IO_MUX_GPIO5_FILTER_EN_S) -#define IO_MUX_GPIO5_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO5_FILTER_EN_S 15 - -/** IO_MUX_gpio6_REG register - * iomux control register for gpio6 - */ -#define IO_MUX_GPIO6_REG (DR_REG_IO_MUX_BASE + 0x1c) -/** IO_MUX_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO6_MCU_OE (BIT(0)) -#define IO_MUX_GPIO6_MCU_OE_M (IO_MUX_GPIO6_MCU_OE_V << IO_MUX_GPIO6_MCU_OE_S) -#define IO_MUX_GPIO6_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO6_MCU_OE_S 0 -/** IO_MUX_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO6_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO6_SLP_SEL_M (IO_MUX_GPIO6_SLP_SEL_V << IO_MUX_GPIO6_SLP_SEL_S) -#define IO_MUX_GPIO6_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO6_SLP_SEL_S 1 -/** IO_MUX_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO6_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO6_MCU_WPD_M (IO_MUX_GPIO6_MCU_WPD_V << IO_MUX_GPIO6_MCU_WPD_S) -#define IO_MUX_GPIO6_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO6_MCU_WPD_S 2 -/** IO_MUX_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO6_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO6_MCU_WPU_M (IO_MUX_GPIO6_MCU_WPU_V << IO_MUX_GPIO6_MCU_WPU_S) -#define IO_MUX_GPIO6_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO6_MCU_WPU_S 3 -/** IO_MUX_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO6_MCU_IE (BIT(4)) -#define IO_MUX_GPIO6_MCU_IE_M (IO_MUX_GPIO6_MCU_IE_V << IO_MUX_GPIO6_MCU_IE_S) -#define IO_MUX_GPIO6_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO6_MCU_IE_S 4 -/** IO_MUX_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO6_MCU_DRV 0x00000003U -#define IO_MUX_GPIO6_MCU_DRV_M (IO_MUX_GPIO6_MCU_DRV_V << IO_MUX_GPIO6_MCU_DRV_S) -#define IO_MUX_GPIO6_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO6_MCU_DRV_S 5 -/** IO_MUX_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO6_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO6_FUN_WPD_M (IO_MUX_GPIO6_FUN_WPD_V << IO_MUX_GPIO6_FUN_WPD_S) -#define IO_MUX_GPIO6_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO6_FUN_WPD_S 7 -/** IO_MUX_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO6_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO6_FUN_WPU_M (IO_MUX_GPIO6_FUN_WPU_V << IO_MUX_GPIO6_FUN_WPU_S) -#define IO_MUX_GPIO6_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO6_FUN_WPU_S 8 -/** IO_MUX_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO6_FUN_IE (BIT(9)) -#define IO_MUX_GPIO6_FUN_IE_M (IO_MUX_GPIO6_FUN_IE_V << IO_MUX_GPIO6_FUN_IE_S) -#define IO_MUX_GPIO6_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO6_FUN_IE_S 9 -/** IO_MUX_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO6_FUN_DRV 0x00000003U -#define IO_MUX_GPIO6_FUN_DRV_M (IO_MUX_GPIO6_FUN_DRV_V << IO_MUX_GPIO6_FUN_DRV_S) -#define IO_MUX_GPIO6_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO6_FUN_DRV_S 10 -/** IO_MUX_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO6_MCU_SEL 0x00000007U -#define IO_MUX_GPIO6_MCU_SEL_M (IO_MUX_GPIO6_MCU_SEL_V << IO_MUX_GPIO6_MCU_SEL_S) -#define IO_MUX_GPIO6_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO6_MCU_SEL_S 12 -/** IO_MUX_GPIO6_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO6_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO6_FILTER_EN_M (IO_MUX_GPIO6_FILTER_EN_V << IO_MUX_GPIO6_FILTER_EN_S) -#define IO_MUX_GPIO6_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO6_FILTER_EN_S 15 - -/** IO_MUX_gpio7_REG register - * iomux control register for gpio7 - */ -#define IO_MUX_GPIO7_REG (DR_REG_IO_MUX_BASE + 0x20) -/** IO_MUX_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO7_MCU_OE (BIT(0)) -#define IO_MUX_GPIO7_MCU_OE_M (IO_MUX_GPIO7_MCU_OE_V << IO_MUX_GPIO7_MCU_OE_S) -#define IO_MUX_GPIO7_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO7_MCU_OE_S 0 -/** IO_MUX_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO7_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO7_SLP_SEL_M (IO_MUX_GPIO7_SLP_SEL_V << IO_MUX_GPIO7_SLP_SEL_S) -#define IO_MUX_GPIO7_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO7_SLP_SEL_S 1 -/** IO_MUX_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO7_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO7_MCU_WPD_M (IO_MUX_GPIO7_MCU_WPD_V << IO_MUX_GPIO7_MCU_WPD_S) -#define IO_MUX_GPIO7_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO7_MCU_WPD_S 2 -/** IO_MUX_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO7_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO7_MCU_WPU_M (IO_MUX_GPIO7_MCU_WPU_V << IO_MUX_GPIO7_MCU_WPU_S) -#define IO_MUX_GPIO7_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO7_MCU_WPU_S 3 -/** IO_MUX_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO7_MCU_IE (BIT(4)) -#define IO_MUX_GPIO7_MCU_IE_M (IO_MUX_GPIO7_MCU_IE_V << IO_MUX_GPIO7_MCU_IE_S) -#define IO_MUX_GPIO7_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO7_MCU_IE_S 4 -/** IO_MUX_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO7_MCU_DRV 0x00000003U -#define IO_MUX_GPIO7_MCU_DRV_M (IO_MUX_GPIO7_MCU_DRV_V << IO_MUX_GPIO7_MCU_DRV_S) -#define IO_MUX_GPIO7_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO7_MCU_DRV_S 5 -/** IO_MUX_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO7_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO7_FUN_WPD_M (IO_MUX_GPIO7_FUN_WPD_V << IO_MUX_GPIO7_FUN_WPD_S) -#define IO_MUX_GPIO7_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO7_FUN_WPD_S 7 -/** IO_MUX_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO7_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO7_FUN_WPU_M (IO_MUX_GPIO7_FUN_WPU_V << IO_MUX_GPIO7_FUN_WPU_S) -#define IO_MUX_GPIO7_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO7_FUN_WPU_S 8 -/** IO_MUX_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO7_FUN_IE (BIT(9)) -#define IO_MUX_GPIO7_FUN_IE_M (IO_MUX_GPIO7_FUN_IE_V << IO_MUX_GPIO7_FUN_IE_S) -#define IO_MUX_GPIO7_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO7_FUN_IE_S 9 -/** IO_MUX_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO7_FUN_DRV 0x00000003U -#define IO_MUX_GPIO7_FUN_DRV_M (IO_MUX_GPIO7_FUN_DRV_V << IO_MUX_GPIO7_FUN_DRV_S) -#define IO_MUX_GPIO7_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO7_FUN_DRV_S 10 -/** IO_MUX_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO7_MCU_SEL 0x00000007U -#define IO_MUX_GPIO7_MCU_SEL_M (IO_MUX_GPIO7_MCU_SEL_V << IO_MUX_GPIO7_MCU_SEL_S) -#define IO_MUX_GPIO7_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO7_MCU_SEL_S 12 -/** IO_MUX_GPIO7_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO7_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO7_FILTER_EN_M (IO_MUX_GPIO7_FILTER_EN_V << IO_MUX_GPIO7_FILTER_EN_S) -#define IO_MUX_GPIO7_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO7_FILTER_EN_S 15 - -/** IO_MUX_gpio8_REG register - * iomux control register for gpio8 - */ -#define IO_MUX_GPIO8_REG (DR_REG_IO_MUX_BASE + 0x24) -/** IO_MUX_GPIO8_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO8_MCU_OE (BIT(0)) -#define IO_MUX_GPIO8_MCU_OE_M (IO_MUX_GPIO8_MCU_OE_V << IO_MUX_GPIO8_MCU_OE_S) -#define IO_MUX_GPIO8_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO8_MCU_OE_S 0 -/** IO_MUX_GPIO8_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO8_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO8_SLP_SEL_M (IO_MUX_GPIO8_SLP_SEL_V << IO_MUX_GPIO8_SLP_SEL_S) -#define IO_MUX_GPIO8_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO8_SLP_SEL_S 1 -/** IO_MUX_GPIO8_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO8_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO8_MCU_WPD_M (IO_MUX_GPIO8_MCU_WPD_V << IO_MUX_GPIO8_MCU_WPD_S) -#define IO_MUX_GPIO8_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO8_MCU_WPD_S 2 -/** IO_MUX_GPIO8_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO8_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO8_MCU_WPU_M (IO_MUX_GPIO8_MCU_WPU_V << IO_MUX_GPIO8_MCU_WPU_S) -#define IO_MUX_GPIO8_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO8_MCU_WPU_S 3 -/** IO_MUX_GPIO8_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO8_MCU_IE (BIT(4)) -#define IO_MUX_GPIO8_MCU_IE_M (IO_MUX_GPIO8_MCU_IE_V << IO_MUX_GPIO8_MCU_IE_S) -#define IO_MUX_GPIO8_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO8_MCU_IE_S 4 -/** IO_MUX_GPIO8_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO8_MCU_DRV 0x00000003U -#define IO_MUX_GPIO8_MCU_DRV_M (IO_MUX_GPIO8_MCU_DRV_V << IO_MUX_GPIO8_MCU_DRV_S) -#define IO_MUX_GPIO8_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO8_MCU_DRV_S 5 -/** IO_MUX_GPIO8_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO8_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO8_FUN_WPD_M (IO_MUX_GPIO8_FUN_WPD_V << IO_MUX_GPIO8_FUN_WPD_S) -#define IO_MUX_GPIO8_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO8_FUN_WPD_S 7 -/** IO_MUX_GPIO8_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO8_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO8_FUN_WPU_M (IO_MUX_GPIO8_FUN_WPU_V << IO_MUX_GPIO8_FUN_WPU_S) -#define IO_MUX_GPIO8_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO8_FUN_WPU_S 8 -/** IO_MUX_GPIO8_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO8_FUN_IE (BIT(9)) -#define IO_MUX_GPIO8_FUN_IE_M (IO_MUX_GPIO8_FUN_IE_V << IO_MUX_GPIO8_FUN_IE_S) -#define IO_MUX_GPIO8_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO8_FUN_IE_S 9 -/** IO_MUX_GPIO8_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO8_FUN_DRV 0x00000003U -#define IO_MUX_GPIO8_FUN_DRV_M (IO_MUX_GPIO8_FUN_DRV_V << IO_MUX_GPIO8_FUN_DRV_S) -#define IO_MUX_GPIO8_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO8_FUN_DRV_S 10 -/** IO_MUX_GPIO8_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO8_MCU_SEL 0x00000007U -#define IO_MUX_GPIO8_MCU_SEL_M (IO_MUX_GPIO8_MCU_SEL_V << IO_MUX_GPIO8_MCU_SEL_S) -#define IO_MUX_GPIO8_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO8_MCU_SEL_S 12 -/** IO_MUX_GPIO8_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO8_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO8_FILTER_EN_M (IO_MUX_GPIO8_FILTER_EN_V << IO_MUX_GPIO8_FILTER_EN_S) -#define IO_MUX_GPIO8_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO8_FILTER_EN_S 15 - -/** IO_MUX_gpio9_REG register - * iomux control register for gpio9 - */ -#define IO_MUX_GPIO9_REG (DR_REG_IO_MUX_BASE + 0x28) -/** IO_MUX_GPIO9_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO9_MCU_OE (BIT(0)) -#define IO_MUX_GPIO9_MCU_OE_M (IO_MUX_GPIO9_MCU_OE_V << IO_MUX_GPIO9_MCU_OE_S) -#define IO_MUX_GPIO9_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO9_MCU_OE_S 0 -/** IO_MUX_GPIO9_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO9_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO9_SLP_SEL_M (IO_MUX_GPIO9_SLP_SEL_V << IO_MUX_GPIO9_SLP_SEL_S) -#define IO_MUX_GPIO9_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO9_SLP_SEL_S 1 -/** IO_MUX_GPIO9_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO9_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO9_MCU_WPD_M (IO_MUX_GPIO9_MCU_WPD_V << IO_MUX_GPIO9_MCU_WPD_S) -#define IO_MUX_GPIO9_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO9_MCU_WPD_S 2 -/** IO_MUX_GPIO9_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO9_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO9_MCU_WPU_M (IO_MUX_GPIO9_MCU_WPU_V << IO_MUX_GPIO9_MCU_WPU_S) -#define IO_MUX_GPIO9_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO9_MCU_WPU_S 3 -/** IO_MUX_GPIO9_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO9_MCU_IE (BIT(4)) -#define IO_MUX_GPIO9_MCU_IE_M (IO_MUX_GPIO9_MCU_IE_V << IO_MUX_GPIO9_MCU_IE_S) -#define IO_MUX_GPIO9_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO9_MCU_IE_S 4 -/** IO_MUX_GPIO9_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO9_MCU_DRV 0x00000003U -#define IO_MUX_GPIO9_MCU_DRV_M (IO_MUX_GPIO9_MCU_DRV_V << IO_MUX_GPIO9_MCU_DRV_S) -#define IO_MUX_GPIO9_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO9_MCU_DRV_S 5 -/** IO_MUX_GPIO9_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO9_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO9_FUN_WPD_M (IO_MUX_GPIO9_FUN_WPD_V << IO_MUX_GPIO9_FUN_WPD_S) -#define IO_MUX_GPIO9_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO9_FUN_WPD_S 7 -/** IO_MUX_GPIO9_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO9_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO9_FUN_WPU_M (IO_MUX_GPIO9_FUN_WPU_V << IO_MUX_GPIO9_FUN_WPU_S) -#define IO_MUX_GPIO9_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO9_FUN_WPU_S 8 -/** IO_MUX_GPIO9_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO9_FUN_IE (BIT(9)) -#define IO_MUX_GPIO9_FUN_IE_M (IO_MUX_GPIO9_FUN_IE_V << IO_MUX_GPIO9_FUN_IE_S) -#define IO_MUX_GPIO9_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO9_FUN_IE_S 9 -/** IO_MUX_GPIO9_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO9_FUN_DRV 0x00000003U -#define IO_MUX_GPIO9_FUN_DRV_M (IO_MUX_GPIO9_FUN_DRV_V << IO_MUX_GPIO9_FUN_DRV_S) -#define IO_MUX_GPIO9_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO9_FUN_DRV_S 10 -/** IO_MUX_GPIO9_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO9_MCU_SEL 0x00000007U -#define IO_MUX_GPIO9_MCU_SEL_M (IO_MUX_GPIO9_MCU_SEL_V << IO_MUX_GPIO9_MCU_SEL_S) -#define IO_MUX_GPIO9_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO9_MCU_SEL_S 12 -/** IO_MUX_GPIO9_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO9_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO9_FILTER_EN_M (IO_MUX_GPIO9_FILTER_EN_V << IO_MUX_GPIO9_FILTER_EN_S) -#define IO_MUX_GPIO9_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO9_FILTER_EN_S 15 - -/** IO_MUX_gpio10_REG register - * iomux control register for gpio10 - */ -#define IO_MUX_GPIO10_REG (DR_REG_IO_MUX_BASE + 0x2c) -/** IO_MUX_GPIO10_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO10_MCU_OE (BIT(0)) -#define IO_MUX_GPIO10_MCU_OE_M (IO_MUX_GPIO10_MCU_OE_V << IO_MUX_GPIO10_MCU_OE_S) -#define IO_MUX_GPIO10_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO10_MCU_OE_S 0 -/** IO_MUX_GPIO10_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO10_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO10_SLP_SEL_M (IO_MUX_GPIO10_SLP_SEL_V << IO_MUX_GPIO10_SLP_SEL_S) -#define IO_MUX_GPIO10_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO10_SLP_SEL_S 1 -/** IO_MUX_GPIO10_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO10_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO10_MCU_WPD_M (IO_MUX_GPIO10_MCU_WPD_V << IO_MUX_GPIO10_MCU_WPD_S) -#define IO_MUX_GPIO10_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO10_MCU_WPD_S 2 -/** IO_MUX_GPIO10_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO10_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO10_MCU_WPU_M (IO_MUX_GPIO10_MCU_WPU_V << IO_MUX_GPIO10_MCU_WPU_S) -#define IO_MUX_GPIO10_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO10_MCU_WPU_S 3 -/** IO_MUX_GPIO10_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO10_MCU_IE (BIT(4)) -#define IO_MUX_GPIO10_MCU_IE_M (IO_MUX_GPIO10_MCU_IE_V << IO_MUX_GPIO10_MCU_IE_S) -#define IO_MUX_GPIO10_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO10_MCU_IE_S 4 -/** IO_MUX_GPIO10_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO10_MCU_DRV 0x00000003U -#define IO_MUX_GPIO10_MCU_DRV_M (IO_MUX_GPIO10_MCU_DRV_V << IO_MUX_GPIO10_MCU_DRV_S) -#define IO_MUX_GPIO10_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO10_MCU_DRV_S 5 -/** IO_MUX_GPIO10_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO10_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO10_FUN_WPD_M (IO_MUX_GPIO10_FUN_WPD_V << IO_MUX_GPIO10_FUN_WPD_S) -#define IO_MUX_GPIO10_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO10_FUN_WPD_S 7 -/** IO_MUX_GPIO10_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO10_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO10_FUN_WPU_M (IO_MUX_GPIO10_FUN_WPU_V << IO_MUX_GPIO10_FUN_WPU_S) -#define IO_MUX_GPIO10_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO10_FUN_WPU_S 8 -/** IO_MUX_GPIO10_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO10_FUN_IE (BIT(9)) -#define IO_MUX_GPIO10_FUN_IE_M (IO_MUX_GPIO10_FUN_IE_V << IO_MUX_GPIO10_FUN_IE_S) -#define IO_MUX_GPIO10_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO10_FUN_IE_S 9 -/** IO_MUX_GPIO10_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO10_FUN_DRV 0x00000003U -#define IO_MUX_GPIO10_FUN_DRV_M (IO_MUX_GPIO10_FUN_DRV_V << IO_MUX_GPIO10_FUN_DRV_S) -#define IO_MUX_GPIO10_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO10_FUN_DRV_S 10 -/** IO_MUX_GPIO10_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO10_MCU_SEL 0x00000007U -#define IO_MUX_GPIO10_MCU_SEL_M (IO_MUX_GPIO10_MCU_SEL_V << IO_MUX_GPIO10_MCU_SEL_S) -#define IO_MUX_GPIO10_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO10_MCU_SEL_S 12 -/** IO_MUX_GPIO10_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO10_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO10_FILTER_EN_M (IO_MUX_GPIO10_FILTER_EN_V << IO_MUX_GPIO10_FILTER_EN_S) -#define IO_MUX_GPIO10_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO10_FILTER_EN_S 15 - -/** IO_MUX_gpio11_REG register - * iomux control register for gpio11 - */ -#define IO_MUX_GPIO11_REG (DR_REG_IO_MUX_BASE + 0x30) -/** IO_MUX_GPIO11_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO11_MCU_OE (BIT(0)) -#define IO_MUX_GPIO11_MCU_OE_M (IO_MUX_GPIO11_MCU_OE_V << IO_MUX_GPIO11_MCU_OE_S) -#define IO_MUX_GPIO11_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO11_MCU_OE_S 0 -/** IO_MUX_GPIO11_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO11_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO11_SLP_SEL_M (IO_MUX_GPIO11_SLP_SEL_V << IO_MUX_GPIO11_SLP_SEL_S) -#define IO_MUX_GPIO11_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO11_SLP_SEL_S 1 -/** IO_MUX_GPIO11_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO11_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO11_MCU_WPD_M (IO_MUX_GPIO11_MCU_WPD_V << IO_MUX_GPIO11_MCU_WPD_S) -#define IO_MUX_GPIO11_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO11_MCU_WPD_S 2 -/** IO_MUX_GPIO11_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO11_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO11_MCU_WPU_M (IO_MUX_GPIO11_MCU_WPU_V << IO_MUX_GPIO11_MCU_WPU_S) -#define IO_MUX_GPIO11_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO11_MCU_WPU_S 3 -/** IO_MUX_GPIO11_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO11_MCU_IE (BIT(4)) -#define IO_MUX_GPIO11_MCU_IE_M (IO_MUX_GPIO11_MCU_IE_V << IO_MUX_GPIO11_MCU_IE_S) -#define IO_MUX_GPIO11_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO11_MCU_IE_S 4 -/** IO_MUX_GPIO11_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO11_MCU_DRV 0x00000003U -#define IO_MUX_GPIO11_MCU_DRV_M (IO_MUX_GPIO11_MCU_DRV_V << IO_MUX_GPIO11_MCU_DRV_S) -#define IO_MUX_GPIO11_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO11_MCU_DRV_S 5 -/** IO_MUX_GPIO11_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO11_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO11_FUN_WPD_M (IO_MUX_GPIO11_FUN_WPD_V << IO_MUX_GPIO11_FUN_WPD_S) -#define IO_MUX_GPIO11_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO11_FUN_WPD_S 7 -/** IO_MUX_GPIO11_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO11_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO11_FUN_WPU_M (IO_MUX_GPIO11_FUN_WPU_V << IO_MUX_GPIO11_FUN_WPU_S) -#define IO_MUX_GPIO11_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO11_FUN_WPU_S 8 -/** IO_MUX_GPIO11_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO11_FUN_IE (BIT(9)) -#define IO_MUX_GPIO11_FUN_IE_M (IO_MUX_GPIO11_FUN_IE_V << IO_MUX_GPIO11_FUN_IE_S) -#define IO_MUX_GPIO11_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO11_FUN_IE_S 9 -/** IO_MUX_GPIO11_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO11_FUN_DRV 0x00000003U -#define IO_MUX_GPIO11_FUN_DRV_M (IO_MUX_GPIO11_FUN_DRV_V << IO_MUX_GPIO11_FUN_DRV_S) -#define IO_MUX_GPIO11_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO11_FUN_DRV_S 10 -/** IO_MUX_GPIO11_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO11_MCU_SEL 0x00000007U -#define IO_MUX_GPIO11_MCU_SEL_M (IO_MUX_GPIO11_MCU_SEL_V << IO_MUX_GPIO11_MCU_SEL_S) -#define IO_MUX_GPIO11_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO11_MCU_SEL_S 12 -/** IO_MUX_GPIO11_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO11_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO11_FILTER_EN_M (IO_MUX_GPIO11_FILTER_EN_V << IO_MUX_GPIO11_FILTER_EN_S) -#define IO_MUX_GPIO11_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO11_FILTER_EN_S 15 - -/** IO_MUX_gpio12_REG register - * iomux control register for gpio12 - */ -#define IO_MUX_GPIO12_REG (DR_REG_IO_MUX_BASE + 0x34) -/** IO_MUX_GPIO12_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO12_MCU_OE (BIT(0)) -#define IO_MUX_GPIO12_MCU_OE_M (IO_MUX_GPIO12_MCU_OE_V << IO_MUX_GPIO12_MCU_OE_S) -#define IO_MUX_GPIO12_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO12_MCU_OE_S 0 -/** IO_MUX_GPIO12_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO12_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO12_SLP_SEL_M (IO_MUX_GPIO12_SLP_SEL_V << IO_MUX_GPIO12_SLP_SEL_S) -#define IO_MUX_GPIO12_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO12_SLP_SEL_S 1 -/** IO_MUX_GPIO12_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO12_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO12_MCU_WPD_M (IO_MUX_GPIO12_MCU_WPD_V << IO_MUX_GPIO12_MCU_WPD_S) -#define IO_MUX_GPIO12_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO12_MCU_WPD_S 2 -/** IO_MUX_GPIO12_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO12_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO12_MCU_WPU_M (IO_MUX_GPIO12_MCU_WPU_V << IO_MUX_GPIO12_MCU_WPU_S) -#define IO_MUX_GPIO12_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO12_MCU_WPU_S 3 -/** IO_MUX_GPIO12_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO12_MCU_IE (BIT(4)) -#define IO_MUX_GPIO12_MCU_IE_M (IO_MUX_GPIO12_MCU_IE_V << IO_MUX_GPIO12_MCU_IE_S) -#define IO_MUX_GPIO12_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO12_MCU_IE_S 4 -/** IO_MUX_GPIO12_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO12_MCU_DRV 0x00000003U -#define IO_MUX_GPIO12_MCU_DRV_M (IO_MUX_GPIO12_MCU_DRV_V << IO_MUX_GPIO12_MCU_DRV_S) -#define IO_MUX_GPIO12_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO12_MCU_DRV_S 5 -/** IO_MUX_GPIO12_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO12_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO12_FUN_WPD_M (IO_MUX_GPIO12_FUN_WPD_V << IO_MUX_GPIO12_FUN_WPD_S) -#define IO_MUX_GPIO12_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO12_FUN_WPD_S 7 -/** IO_MUX_GPIO12_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO12_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO12_FUN_WPU_M (IO_MUX_GPIO12_FUN_WPU_V << IO_MUX_GPIO12_FUN_WPU_S) -#define IO_MUX_GPIO12_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO12_FUN_WPU_S 8 -/** IO_MUX_GPIO12_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO12_FUN_IE (BIT(9)) -#define IO_MUX_GPIO12_FUN_IE_M (IO_MUX_GPIO12_FUN_IE_V << IO_MUX_GPIO12_FUN_IE_S) -#define IO_MUX_GPIO12_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO12_FUN_IE_S 9 -/** IO_MUX_GPIO12_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO12_FUN_DRV 0x00000003U -#define IO_MUX_GPIO12_FUN_DRV_M (IO_MUX_GPIO12_FUN_DRV_V << IO_MUX_GPIO12_FUN_DRV_S) -#define IO_MUX_GPIO12_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO12_FUN_DRV_S 10 -/** IO_MUX_GPIO12_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO12_MCU_SEL 0x00000007U -#define IO_MUX_GPIO12_MCU_SEL_M (IO_MUX_GPIO12_MCU_SEL_V << IO_MUX_GPIO12_MCU_SEL_S) -#define IO_MUX_GPIO12_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO12_MCU_SEL_S 12 -/** IO_MUX_GPIO12_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO12_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO12_FILTER_EN_M (IO_MUX_GPIO12_FILTER_EN_V << IO_MUX_GPIO12_FILTER_EN_S) -#define IO_MUX_GPIO12_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO12_FILTER_EN_S 15 - -/** IO_MUX_gpio13_REG register - * iomux control register for gpio13 - */ -#define IO_MUX_GPIO13_REG (DR_REG_IO_MUX_BASE + 0x38) -/** IO_MUX_GPIO13_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO13_MCU_OE (BIT(0)) -#define IO_MUX_GPIO13_MCU_OE_M (IO_MUX_GPIO13_MCU_OE_V << IO_MUX_GPIO13_MCU_OE_S) -#define IO_MUX_GPIO13_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO13_MCU_OE_S 0 -/** IO_MUX_GPIO13_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO13_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO13_SLP_SEL_M (IO_MUX_GPIO13_SLP_SEL_V << IO_MUX_GPIO13_SLP_SEL_S) -#define IO_MUX_GPIO13_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO13_SLP_SEL_S 1 -/** IO_MUX_GPIO13_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO13_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO13_MCU_WPD_M (IO_MUX_GPIO13_MCU_WPD_V << IO_MUX_GPIO13_MCU_WPD_S) -#define IO_MUX_GPIO13_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO13_MCU_WPD_S 2 -/** IO_MUX_GPIO13_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO13_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO13_MCU_WPU_M (IO_MUX_GPIO13_MCU_WPU_V << IO_MUX_GPIO13_MCU_WPU_S) -#define IO_MUX_GPIO13_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO13_MCU_WPU_S 3 -/** IO_MUX_GPIO13_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO13_MCU_IE (BIT(4)) -#define IO_MUX_GPIO13_MCU_IE_M (IO_MUX_GPIO13_MCU_IE_V << IO_MUX_GPIO13_MCU_IE_S) -#define IO_MUX_GPIO13_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO13_MCU_IE_S 4 -/** IO_MUX_GPIO13_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO13_MCU_DRV 0x00000003U -#define IO_MUX_GPIO13_MCU_DRV_M (IO_MUX_GPIO13_MCU_DRV_V << IO_MUX_GPIO13_MCU_DRV_S) -#define IO_MUX_GPIO13_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO13_MCU_DRV_S 5 -/** IO_MUX_GPIO13_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO13_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO13_FUN_WPD_M (IO_MUX_GPIO13_FUN_WPD_V << IO_MUX_GPIO13_FUN_WPD_S) -#define IO_MUX_GPIO13_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO13_FUN_WPD_S 7 -/** IO_MUX_GPIO13_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO13_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO13_FUN_WPU_M (IO_MUX_GPIO13_FUN_WPU_V << IO_MUX_GPIO13_FUN_WPU_S) -#define IO_MUX_GPIO13_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO13_FUN_WPU_S 8 -/** IO_MUX_GPIO13_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO13_FUN_IE (BIT(9)) -#define IO_MUX_GPIO13_FUN_IE_M (IO_MUX_GPIO13_FUN_IE_V << IO_MUX_GPIO13_FUN_IE_S) -#define IO_MUX_GPIO13_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO13_FUN_IE_S 9 -/** IO_MUX_GPIO13_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO13_FUN_DRV 0x00000003U -#define IO_MUX_GPIO13_FUN_DRV_M (IO_MUX_GPIO13_FUN_DRV_V << IO_MUX_GPIO13_FUN_DRV_S) -#define IO_MUX_GPIO13_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO13_FUN_DRV_S 10 -/** IO_MUX_GPIO13_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO13_MCU_SEL 0x00000007U -#define IO_MUX_GPIO13_MCU_SEL_M (IO_MUX_GPIO13_MCU_SEL_V << IO_MUX_GPIO13_MCU_SEL_S) -#define IO_MUX_GPIO13_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO13_MCU_SEL_S 12 -/** IO_MUX_GPIO13_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO13_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO13_FILTER_EN_M (IO_MUX_GPIO13_FILTER_EN_V << IO_MUX_GPIO13_FILTER_EN_S) -#define IO_MUX_GPIO13_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO13_FILTER_EN_S 15 - -/** IO_MUX_gpio14_REG register - * iomux control register for gpio14 - */ -#define IO_MUX_GPIO14_REG (DR_REG_IO_MUX_BASE + 0x3c) -/** IO_MUX_GPIO14_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO14_MCU_OE (BIT(0)) -#define IO_MUX_GPIO14_MCU_OE_M (IO_MUX_GPIO14_MCU_OE_V << IO_MUX_GPIO14_MCU_OE_S) -#define IO_MUX_GPIO14_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO14_MCU_OE_S 0 -/** IO_MUX_GPIO14_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO14_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO14_SLP_SEL_M (IO_MUX_GPIO14_SLP_SEL_V << IO_MUX_GPIO14_SLP_SEL_S) -#define IO_MUX_GPIO14_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO14_SLP_SEL_S 1 -/** IO_MUX_GPIO14_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO14_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO14_MCU_WPD_M (IO_MUX_GPIO14_MCU_WPD_V << IO_MUX_GPIO14_MCU_WPD_S) -#define IO_MUX_GPIO14_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO14_MCU_WPD_S 2 -/** IO_MUX_GPIO14_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO14_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO14_MCU_WPU_M (IO_MUX_GPIO14_MCU_WPU_V << IO_MUX_GPIO14_MCU_WPU_S) -#define IO_MUX_GPIO14_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO14_MCU_WPU_S 3 -/** IO_MUX_GPIO14_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO14_MCU_IE (BIT(4)) -#define IO_MUX_GPIO14_MCU_IE_M (IO_MUX_GPIO14_MCU_IE_V << IO_MUX_GPIO14_MCU_IE_S) -#define IO_MUX_GPIO14_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO14_MCU_IE_S 4 -/** IO_MUX_GPIO14_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO14_MCU_DRV 0x00000003U -#define IO_MUX_GPIO14_MCU_DRV_M (IO_MUX_GPIO14_MCU_DRV_V << IO_MUX_GPIO14_MCU_DRV_S) -#define IO_MUX_GPIO14_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO14_MCU_DRV_S 5 -/** IO_MUX_GPIO14_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO14_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO14_FUN_WPD_M (IO_MUX_GPIO14_FUN_WPD_V << IO_MUX_GPIO14_FUN_WPD_S) -#define IO_MUX_GPIO14_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO14_FUN_WPD_S 7 -/** IO_MUX_GPIO14_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO14_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO14_FUN_WPU_M (IO_MUX_GPIO14_FUN_WPU_V << IO_MUX_GPIO14_FUN_WPU_S) -#define IO_MUX_GPIO14_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO14_FUN_WPU_S 8 -/** IO_MUX_GPIO14_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO14_FUN_IE (BIT(9)) -#define IO_MUX_GPIO14_FUN_IE_M (IO_MUX_GPIO14_FUN_IE_V << IO_MUX_GPIO14_FUN_IE_S) -#define IO_MUX_GPIO14_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO14_FUN_IE_S 9 -/** IO_MUX_GPIO14_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO14_FUN_DRV 0x00000003U -#define IO_MUX_GPIO14_FUN_DRV_M (IO_MUX_GPIO14_FUN_DRV_V << IO_MUX_GPIO14_FUN_DRV_S) -#define IO_MUX_GPIO14_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO14_FUN_DRV_S 10 -/** IO_MUX_GPIO14_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO14_MCU_SEL 0x00000007U -#define IO_MUX_GPIO14_MCU_SEL_M (IO_MUX_GPIO14_MCU_SEL_V << IO_MUX_GPIO14_MCU_SEL_S) -#define IO_MUX_GPIO14_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO14_MCU_SEL_S 12 -/** IO_MUX_GPIO14_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO14_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO14_FILTER_EN_M (IO_MUX_GPIO14_FILTER_EN_V << IO_MUX_GPIO14_FILTER_EN_S) -#define IO_MUX_GPIO14_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO14_FILTER_EN_S 15 - -/** IO_MUX_gpio15_REG register - * iomux control register for gpio15 - */ -#define IO_MUX_GPIO15_REG (DR_REG_IO_MUX_BASE + 0x40) -/** IO_MUX_GPIO15_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO15_MCU_OE (BIT(0)) -#define IO_MUX_GPIO15_MCU_OE_M (IO_MUX_GPIO15_MCU_OE_V << IO_MUX_GPIO15_MCU_OE_S) -#define IO_MUX_GPIO15_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO15_MCU_OE_S 0 -/** IO_MUX_GPIO15_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO15_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO15_SLP_SEL_M (IO_MUX_GPIO15_SLP_SEL_V << IO_MUX_GPIO15_SLP_SEL_S) -#define IO_MUX_GPIO15_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO15_SLP_SEL_S 1 -/** IO_MUX_GPIO15_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO15_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO15_MCU_WPD_M (IO_MUX_GPIO15_MCU_WPD_V << IO_MUX_GPIO15_MCU_WPD_S) -#define IO_MUX_GPIO15_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO15_MCU_WPD_S 2 -/** IO_MUX_GPIO15_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO15_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO15_MCU_WPU_M (IO_MUX_GPIO15_MCU_WPU_V << IO_MUX_GPIO15_MCU_WPU_S) -#define IO_MUX_GPIO15_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO15_MCU_WPU_S 3 -/** IO_MUX_GPIO15_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO15_MCU_IE (BIT(4)) -#define IO_MUX_GPIO15_MCU_IE_M (IO_MUX_GPIO15_MCU_IE_V << IO_MUX_GPIO15_MCU_IE_S) -#define IO_MUX_GPIO15_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO15_MCU_IE_S 4 -/** IO_MUX_GPIO15_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO15_MCU_DRV 0x00000003U -#define IO_MUX_GPIO15_MCU_DRV_M (IO_MUX_GPIO15_MCU_DRV_V << IO_MUX_GPIO15_MCU_DRV_S) -#define IO_MUX_GPIO15_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO15_MCU_DRV_S 5 -/** IO_MUX_GPIO15_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO15_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO15_FUN_WPD_M (IO_MUX_GPIO15_FUN_WPD_V << IO_MUX_GPIO15_FUN_WPD_S) -#define IO_MUX_GPIO15_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO15_FUN_WPD_S 7 -/** IO_MUX_GPIO15_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO15_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO15_FUN_WPU_M (IO_MUX_GPIO15_FUN_WPU_V << IO_MUX_GPIO15_FUN_WPU_S) -#define IO_MUX_GPIO15_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO15_FUN_WPU_S 8 -/** IO_MUX_GPIO15_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO15_FUN_IE (BIT(9)) -#define IO_MUX_GPIO15_FUN_IE_M (IO_MUX_GPIO15_FUN_IE_V << IO_MUX_GPIO15_FUN_IE_S) -#define IO_MUX_GPIO15_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO15_FUN_IE_S 9 -/** IO_MUX_GPIO15_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO15_FUN_DRV 0x00000003U -#define IO_MUX_GPIO15_FUN_DRV_M (IO_MUX_GPIO15_FUN_DRV_V << IO_MUX_GPIO15_FUN_DRV_S) -#define IO_MUX_GPIO15_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO15_FUN_DRV_S 10 -/** IO_MUX_GPIO15_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO15_MCU_SEL 0x00000007U -#define IO_MUX_GPIO15_MCU_SEL_M (IO_MUX_GPIO15_MCU_SEL_V << IO_MUX_GPIO15_MCU_SEL_S) -#define IO_MUX_GPIO15_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO15_MCU_SEL_S 12 -/** IO_MUX_GPIO15_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO15_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO15_FILTER_EN_M (IO_MUX_GPIO15_FILTER_EN_V << IO_MUX_GPIO15_FILTER_EN_S) -#define IO_MUX_GPIO15_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO15_FILTER_EN_S 15 - -/** IO_MUX_gpio16_REG register - * iomux control register for gpio16 - */ -#define IO_MUX_GPIO16_REG (DR_REG_IO_MUX_BASE + 0x44) -/** IO_MUX_GPIO16_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO16_MCU_OE (BIT(0)) -#define IO_MUX_GPIO16_MCU_OE_M (IO_MUX_GPIO16_MCU_OE_V << IO_MUX_GPIO16_MCU_OE_S) -#define IO_MUX_GPIO16_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO16_MCU_OE_S 0 -/** IO_MUX_GPIO16_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO16_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO16_SLP_SEL_M (IO_MUX_GPIO16_SLP_SEL_V << IO_MUX_GPIO16_SLP_SEL_S) -#define IO_MUX_GPIO16_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO16_SLP_SEL_S 1 -/** IO_MUX_GPIO16_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO16_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO16_MCU_WPD_M (IO_MUX_GPIO16_MCU_WPD_V << IO_MUX_GPIO16_MCU_WPD_S) -#define IO_MUX_GPIO16_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO16_MCU_WPD_S 2 -/** IO_MUX_GPIO16_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO16_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO16_MCU_WPU_M (IO_MUX_GPIO16_MCU_WPU_V << IO_MUX_GPIO16_MCU_WPU_S) -#define IO_MUX_GPIO16_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO16_MCU_WPU_S 3 -/** IO_MUX_GPIO16_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO16_MCU_IE (BIT(4)) -#define IO_MUX_GPIO16_MCU_IE_M (IO_MUX_GPIO16_MCU_IE_V << IO_MUX_GPIO16_MCU_IE_S) -#define IO_MUX_GPIO16_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO16_MCU_IE_S 4 -/** IO_MUX_GPIO16_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO16_MCU_DRV 0x00000003U -#define IO_MUX_GPIO16_MCU_DRV_M (IO_MUX_GPIO16_MCU_DRV_V << IO_MUX_GPIO16_MCU_DRV_S) -#define IO_MUX_GPIO16_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO16_MCU_DRV_S 5 -/** IO_MUX_GPIO16_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO16_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO16_FUN_WPD_M (IO_MUX_GPIO16_FUN_WPD_V << IO_MUX_GPIO16_FUN_WPD_S) -#define IO_MUX_GPIO16_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO16_FUN_WPD_S 7 -/** IO_MUX_GPIO16_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO16_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO16_FUN_WPU_M (IO_MUX_GPIO16_FUN_WPU_V << IO_MUX_GPIO16_FUN_WPU_S) -#define IO_MUX_GPIO16_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO16_FUN_WPU_S 8 -/** IO_MUX_GPIO16_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO16_FUN_IE (BIT(9)) -#define IO_MUX_GPIO16_FUN_IE_M (IO_MUX_GPIO16_FUN_IE_V << IO_MUX_GPIO16_FUN_IE_S) -#define IO_MUX_GPIO16_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO16_FUN_IE_S 9 -/** IO_MUX_GPIO16_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO16_FUN_DRV 0x00000003U -#define IO_MUX_GPIO16_FUN_DRV_M (IO_MUX_GPIO16_FUN_DRV_V << IO_MUX_GPIO16_FUN_DRV_S) -#define IO_MUX_GPIO16_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO16_FUN_DRV_S 10 -/** IO_MUX_GPIO16_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO16_MCU_SEL 0x00000007U -#define IO_MUX_GPIO16_MCU_SEL_M (IO_MUX_GPIO16_MCU_SEL_V << IO_MUX_GPIO16_MCU_SEL_S) -#define IO_MUX_GPIO16_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO16_MCU_SEL_S 12 -/** IO_MUX_GPIO16_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO16_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO16_FILTER_EN_M (IO_MUX_GPIO16_FILTER_EN_V << IO_MUX_GPIO16_FILTER_EN_S) -#define IO_MUX_GPIO16_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO16_FILTER_EN_S 15 - -/** IO_MUX_gpio17_REG register - * iomux control register for gpio17 - */ -#define IO_MUX_GPIO17_REG (DR_REG_IO_MUX_BASE + 0x48) -/** IO_MUX_GPIO17_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO17_MCU_OE (BIT(0)) -#define IO_MUX_GPIO17_MCU_OE_M (IO_MUX_GPIO17_MCU_OE_V << IO_MUX_GPIO17_MCU_OE_S) -#define IO_MUX_GPIO17_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO17_MCU_OE_S 0 -/** IO_MUX_GPIO17_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO17_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO17_SLP_SEL_M (IO_MUX_GPIO17_SLP_SEL_V << IO_MUX_GPIO17_SLP_SEL_S) -#define IO_MUX_GPIO17_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO17_SLP_SEL_S 1 -/** IO_MUX_GPIO17_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO17_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO17_MCU_WPD_M (IO_MUX_GPIO17_MCU_WPD_V << IO_MUX_GPIO17_MCU_WPD_S) -#define IO_MUX_GPIO17_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO17_MCU_WPD_S 2 -/** IO_MUX_GPIO17_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO17_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO17_MCU_WPU_M (IO_MUX_GPIO17_MCU_WPU_V << IO_MUX_GPIO17_MCU_WPU_S) -#define IO_MUX_GPIO17_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO17_MCU_WPU_S 3 -/** IO_MUX_GPIO17_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO17_MCU_IE (BIT(4)) -#define IO_MUX_GPIO17_MCU_IE_M (IO_MUX_GPIO17_MCU_IE_V << IO_MUX_GPIO17_MCU_IE_S) -#define IO_MUX_GPIO17_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO17_MCU_IE_S 4 -/** IO_MUX_GPIO17_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO17_MCU_DRV 0x00000003U -#define IO_MUX_GPIO17_MCU_DRV_M (IO_MUX_GPIO17_MCU_DRV_V << IO_MUX_GPIO17_MCU_DRV_S) -#define IO_MUX_GPIO17_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO17_MCU_DRV_S 5 -/** IO_MUX_GPIO17_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO17_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO17_FUN_WPD_M (IO_MUX_GPIO17_FUN_WPD_V << IO_MUX_GPIO17_FUN_WPD_S) -#define IO_MUX_GPIO17_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO17_FUN_WPD_S 7 -/** IO_MUX_GPIO17_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO17_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO17_FUN_WPU_M (IO_MUX_GPIO17_FUN_WPU_V << IO_MUX_GPIO17_FUN_WPU_S) -#define IO_MUX_GPIO17_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO17_FUN_WPU_S 8 -/** IO_MUX_GPIO17_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO17_FUN_IE (BIT(9)) -#define IO_MUX_GPIO17_FUN_IE_M (IO_MUX_GPIO17_FUN_IE_V << IO_MUX_GPIO17_FUN_IE_S) -#define IO_MUX_GPIO17_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO17_FUN_IE_S 9 -/** IO_MUX_GPIO17_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO17_FUN_DRV 0x00000003U -#define IO_MUX_GPIO17_FUN_DRV_M (IO_MUX_GPIO17_FUN_DRV_V << IO_MUX_GPIO17_FUN_DRV_S) -#define IO_MUX_GPIO17_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO17_FUN_DRV_S 10 -/** IO_MUX_GPIO17_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO17_MCU_SEL 0x00000007U -#define IO_MUX_GPIO17_MCU_SEL_M (IO_MUX_GPIO17_MCU_SEL_V << IO_MUX_GPIO17_MCU_SEL_S) -#define IO_MUX_GPIO17_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO17_MCU_SEL_S 12 -/** IO_MUX_GPIO17_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO17_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO17_FILTER_EN_M (IO_MUX_GPIO17_FILTER_EN_V << IO_MUX_GPIO17_FILTER_EN_S) -#define IO_MUX_GPIO17_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO17_FILTER_EN_S 15 - -/** IO_MUX_gpio18_REG register - * iomux control register for gpio18 - */ -#define IO_MUX_GPIO18_REG (DR_REG_IO_MUX_BASE + 0x4c) -/** IO_MUX_GPIO18_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO18_MCU_OE (BIT(0)) -#define IO_MUX_GPIO18_MCU_OE_M (IO_MUX_GPIO18_MCU_OE_V << IO_MUX_GPIO18_MCU_OE_S) -#define IO_MUX_GPIO18_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO18_MCU_OE_S 0 -/** IO_MUX_GPIO18_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO18_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO18_SLP_SEL_M (IO_MUX_GPIO18_SLP_SEL_V << IO_MUX_GPIO18_SLP_SEL_S) -#define IO_MUX_GPIO18_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO18_SLP_SEL_S 1 -/** IO_MUX_GPIO18_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO18_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO18_MCU_WPD_M (IO_MUX_GPIO18_MCU_WPD_V << IO_MUX_GPIO18_MCU_WPD_S) -#define IO_MUX_GPIO18_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO18_MCU_WPD_S 2 -/** IO_MUX_GPIO18_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO18_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO18_MCU_WPU_M (IO_MUX_GPIO18_MCU_WPU_V << IO_MUX_GPIO18_MCU_WPU_S) -#define IO_MUX_GPIO18_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO18_MCU_WPU_S 3 -/** IO_MUX_GPIO18_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO18_MCU_IE (BIT(4)) -#define IO_MUX_GPIO18_MCU_IE_M (IO_MUX_GPIO18_MCU_IE_V << IO_MUX_GPIO18_MCU_IE_S) -#define IO_MUX_GPIO18_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO18_MCU_IE_S 4 -/** IO_MUX_GPIO18_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO18_MCU_DRV 0x00000003U -#define IO_MUX_GPIO18_MCU_DRV_M (IO_MUX_GPIO18_MCU_DRV_V << IO_MUX_GPIO18_MCU_DRV_S) -#define IO_MUX_GPIO18_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO18_MCU_DRV_S 5 -/** IO_MUX_GPIO18_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO18_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO18_FUN_WPD_M (IO_MUX_GPIO18_FUN_WPD_V << IO_MUX_GPIO18_FUN_WPD_S) -#define IO_MUX_GPIO18_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO18_FUN_WPD_S 7 -/** IO_MUX_GPIO18_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO18_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO18_FUN_WPU_M (IO_MUX_GPIO18_FUN_WPU_V << IO_MUX_GPIO18_FUN_WPU_S) -#define IO_MUX_GPIO18_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO18_FUN_WPU_S 8 -/** IO_MUX_GPIO18_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO18_FUN_IE (BIT(9)) -#define IO_MUX_GPIO18_FUN_IE_M (IO_MUX_GPIO18_FUN_IE_V << IO_MUX_GPIO18_FUN_IE_S) -#define IO_MUX_GPIO18_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO18_FUN_IE_S 9 -/** IO_MUX_GPIO18_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO18_FUN_DRV 0x00000003U -#define IO_MUX_GPIO18_FUN_DRV_M (IO_MUX_GPIO18_FUN_DRV_V << IO_MUX_GPIO18_FUN_DRV_S) -#define IO_MUX_GPIO18_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO18_FUN_DRV_S 10 -/** IO_MUX_GPIO18_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO18_MCU_SEL 0x00000007U -#define IO_MUX_GPIO18_MCU_SEL_M (IO_MUX_GPIO18_MCU_SEL_V << IO_MUX_GPIO18_MCU_SEL_S) -#define IO_MUX_GPIO18_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO18_MCU_SEL_S 12 -/** IO_MUX_GPIO18_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO18_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO18_FILTER_EN_M (IO_MUX_GPIO18_FILTER_EN_V << IO_MUX_GPIO18_FILTER_EN_S) -#define IO_MUX_GPIO18_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO18_FILTER_EN_S 15 - -/** IO_MUX_gpio19_REG register - * iomux control register for gpio19 - */ -#define IO_MUX_GPIO19_REG (DR_REG_IO_MUX_BASE + 0x50) -/** IO_MUX_GPIO19_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO19_MCU_OE (BIT(0)) -#define IO_MUX_GPIO19_MCU_OE_M (IO_MUX_GPIO19_MCU_OE_V << IO_MUX_GPIO19_MCU_OE_S) -#define IO_MUX_GPIO19_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO19_MCU_OE_S 0 -/** IO_MUX_GPIO19_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO19_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO19_SLP_SEL_M (IO_MUX_GPIO19_SLP_SEL_V << IO_MUX_GPIO19_SLP_SEL_S) -#define IO_MUX_GPIO19_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO19_SLP_SEL_S 1 -/** IO_MUX_GPIO19_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO19_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO19_MCU_WPD_M (IO_MUX_GPIO19_MCU_WPD_V << IO_MUX_GPIO19_MCU_WPD_S) -#define IO_MUX_GPIO19_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO19_MCU_WPD_S 2 -/** IO_MUX_GPIO19_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO19_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO19_MCU_WPU_M (IO_MUX_GPIO19_MCU_WPU_V << IO_MUX_GPIO19_MCU_WPU_S) -#define IO_MUX_GPIO19_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO19_MCU_WPU_S 3 -/** IO_MUX_GPIO19_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO19_MCU_IE (BIT(4)) -#define IO_MUX_GPIO19_MCU_IE_M (IO_MUX_GPIO19_MCU_IE_V << IO_MUX_GPIO19_MCU_IE_S) -#define IO_MUX_GPIO19_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO19_MCU_IE_S 4 -/** IO_MUX_GPIO19_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO19_MCU_DRV 0x00000003U -#define IO_MUX_GPIO19_MCU_DRV_M (IO_MUX_GPIO19_MCU_DRV_V << IO_MUX_GPIO19_MCU_DRV_S) -#define IO_MUX_GPIO19_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO19_MCU_DRV_S 5 -/** IO_MUX_GPIO19_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO19_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO19_FUN_WPD_M (IO_MUX_GPIO19_FUN_WPD_V << IO_MUX_GPIO19_FUN_WPD_S) -#define IO_MUX_GPIO19_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO19_FUN_WPD_S 7 -/** IO_MUX_GPIO19_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO19_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO19_FUN_WPU_M (IO_MUX_GPIO19_FUN_WPU_V << IO_MUX_GPIO19_FUN_WPU_S) -#define IO_MUX_GPIO19_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO19_FUN_WPU_S 8 -/** IO_MUX_GPIO19_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO19_FUN_IE (BIT(9)) -#define IO_MUX_GPIO19_FUN_IE_M (IO_MUX_GPIO19_FUN_IE_V << IO_MUX_GPIO19_FUN_IE_S) -#define IO_MUX_GPIO19_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO19_FUN_IE_S 9 -/** IO_MUX_GPIO19_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO19_FUN_DRV 0x00000003U -#define IO_MUX_GPIO19_FUN_DRV_M (IO_MUX_GPIO19_FUN_DRV_V << IO_MUX_GPIO19_FUN_DRV_S) -#define IO_MUX_GPIO19_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO19_FUN_DRV_S 10 -/** IO_MUX_GPIO19_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO19_MCU_SEL 0x00000007U -#define IO_MUX_GPIO19_MCU_SEL_M (IO_MUX_GPIO19_MCU_SEL_V << IO_MUX_GPIO19_MCU_SEL_S) -#define IO_MUX_GPIO19_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO19_MCU_SEL_S 12 -/** IO_MUX_GPIO19_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO19_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO19_FILTER_EN_M (IO_MUX_GPIO19_FILTER_EN_V << IO_MUX_GPIO19_FILTER_EN_S) -#define IO_MUX_GPIO19_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO19_FILTER_EN_S 15 - -/** IO_MUX_gpio20_REG register - * iomux control register for gpio20 - */ -#define IO_MUX_GPIO20_REG (DR_REG_IO_MUX_BASE + 0x54) -/** IO_MUX_GPIO20_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO20_MCU_OE (BIT(0)) -#define IO_MUX_GPIO20_MCU_OE_M (IO_MUX_GPIO20_MCU_OE_V << IO_MUX_GPIO20_MCU_OE_S) -#define IO_MUX_GPIO20_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO20_MCU_OE_S 0 -/** IO_MUX_GPIO20_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO20_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO20_SLP_SEL_M (IO_MUX_GPIO20_SLP_SEL_V << IO_MUX_GPIO20_SLP_SEL_S) -#define IO_MUX_GPIO20_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO20_SLP_SEL_S 1 -/** IO_MUX_GPIO20_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO20_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO20_MCU_WPD_M (IO_MUX_GPIO20_MCU_WPD_V << IO_MUX_GPIO20_MCU_WPD_S) -#define IO_MUX_GPIO20_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO20_MCU_WPD_S 2 -/** IO_MUX_GPIO20_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO20_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO20_MCU_WPU_M (IO_MUX_GPIO20_MCU_WPU_V << IO_MUX_GPIO20_MCU_WPU_S) -#define IO_MUX_GPIO20_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO20_MCU_WPU_S 3 -/** IO_MUX_GPIO20_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO20_MCU_IE (BIT(4)) -#define IO_MUX_GPIO20_MCU_IE_M (IO_MUX_GPIO20_MCU_IE_V << IO_MUX_GPIO20_MCU_IE_S) -#define IO_MUX_GPIO20_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO20_MCU_IE_S 4 -/** IO_MUX_GPIO20_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO20_MCU_DRV 0x00000003U -#define IO_MUX_GPIO20_MCU_DRV_M (IO_MUX_GPIO20_MCU_DRV_V << IO_MUX_GPIO20_MCU_DRV_S) -#define IO_MUX_GPIO20_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO20_MCU_DRV_S 5 -/** IO_MUX_GPIO20_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO20_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO20_FUN_WPD_M (IO_MUX_GPIO20_FUN_WPD_V << IO_MUX_GPIO20_FUN_WPD_S) -#define IO_MUX_GPIO20_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO20_FUN_WPD_S 7 -/** IO_MUX_GPIO20_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO20_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO20_FUN_WPU_M (IO_MUX_GPIO20_FUN_WPU_V << IO_MUX_GPIO20_FUN_WPU_S) -#define IO_MUX_GPIO20_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO20_FUN_WPU_S 8 -/** IO_MUX_GPIO20_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO20_FUN_IE (BIT(9)) -#define IO_MUX_GPIO20_FUN_IE_M (IO_MUX_GPIO20_FUN_IE_V << IO_MUX_GPIO20_FUN_IE_S) -#define IO_MUX_GPIO20_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO20_FUN_IE_S 9 -/** IO_MUX_GPIO20_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO20_FUN_DRV 0x00000003U -#define IO_MUX_GPIO20_FUN_DRV_M (IO_MUX_GPIO20_FUN_DRV_V << IO_MUX_GPIO20_FUN_DRV_S) -#define IO_MUX_GPIO20_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO20_FUN_DRV_S 10 -/** IO_MUX_GPIO20_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO20_MCU_SEL 0x00000007U -#define IO_MUX_GPIO20_MCU_SEL_M (IO_MUX_GPIO20_MCU_SEL_V << IO_MUX_GPIO20_MCU_SEL_S) -#define IO_MUX_GPIO20_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO20_MCU_SEL_S 12 -/** IO_MUX_GPIO20_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO20_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO20_FILTER_EN_M (IO_MUX_GPIO20_FILTER_EN_V << IO_MUX_GPIO20_FILTER_EN_S) -#define IO_MUX_GPIO20_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO20_FILTER_EN_S 15 - -/** IO_MUX_gpio21_REG register - * iomux control register for gpio21 - */ -#define IO_MUX_GPIO21_REG (DR_REG_IO_MUX_BASE + 0x58) -/** IO_MUX_GPIO21_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO21_MCU_OE (BIT(0)) -#define IO_MUX_GPIO21_MCU_OE_M (IO_MUX_GPIO21_MCU_OE_V << IO_MUX_GPIO21_MCU_OE_S) -#define IO_MUX_GPIO21_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO21_MCU_OE_S 0 -/** IO_MUX_GPIO21_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO21_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO21_SLP_SEL_M (IO_MUX_GPIO21_SLP_SEL_V << IO_MUX_GPIO21_SLP_SEL_S) -#define IO_MUX_GPIO21_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO21_SLP_SEL_S 1 -/** IO_MUX_GPIO21_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO21_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO21_MCU_WPD_M (IO_MUX_GPIO21_MCU_WPD_V << IO_MUX_GPIO21_MCU_WPD_S) -#define IO_MUX_GPIO21_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO21_MCU_WPD_S 2 -/** IO_MUX_GPIO21_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO21_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO21_MCU_WPU_M (IO_MUX_GPIO21_MCU_WPU_V << IO_MUX_GPIO21_MCU_WPU_S) -#define IO_MUX_GPIO21_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO21_MCU_WPU_S 3 -/** IO_MUX_GPIO21_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO21_MCU_IE (BIT(4)) -#define IO_MUX_GPIO21_MCU_IE_M (IO_MUX_GPIO21_MCU_IE_V << IO_MUX_GPIO21_MCU_IE_S) -#define IO_MUX_GPIO21_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO21_MCU_IE_S 4 -/** IO_MUX_GPIO21_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO21_MCU_DRV 0x00000003U -#define IO_MUX_GPIO21_MCU_DRV_M (IO_MUX_GPIO21_MCU_DRV_V << IO_MUX_GPIO21_MCU_DRV_S) -#define IO_MUX_GPIO21_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO21_MCU_DRV_S 5 -/** IO_MUX_GPIO21_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO21_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO21_FUN_WPD_M (IO_MUX_GPIO21_FUN_WPD_V << IO_MUX_GPIO21_FUN_WPD_S) -#define IO_MUX_GPIO21_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO21_FUN_WPD_S 7 -/** IO_MUX_GPIO21_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO21_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO21_FUN_WPU_M (IO_MUX_GPIO21_FUN_WPU_V << IO_MUX_GPIO21_FUN_WPU_S) -#define IO_MUX_GPIO21_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO21_FUN_WPU_S 8 -/** IO_MUX_GPIO21_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO21_FUN_IE (BIT(9)) -#define IO_MUX_GPIO21_FUN_IE_M (IO_MUX_GPIO21_FUN_IE_V << IO_MUX_GPIO21_FUN_IE_S) -#define IO_MUX_GPIO21_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO21_FUN_IE_S 9 -/** IO_MUX_GPIO21_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO21_FUN_DRV 0x00000003U -#define IO_MUX_GPIO21_FUN_DRV_M (IO_MUX_GPIO21_FUN_DRV_V << IO_MUX_GPIO21_FUN_DRV_S) -#define IO_MUX_GPIO21_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO21_FUN_DRV_S 10 -/** IO_MUX_GPIO21_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO21_MCU_SEL 0x00000007U -#define IO_MUX_GPIO21_MCU_SEL_M (IO_MUX_GPIO21_MCU_SEL_V << IO_MUX_GPIO21_MCU_SEL_S) -#define IO_MUX_GPIO21_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO21_MCU_SEL_S 12 -/** IO_MUX_GPIO21_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO21_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO21_FILTER_EN_M (IO_MUX_GPIO21_FILTER_EN_V << IO_MUX_GPIO21_FILTER_EN_S) -#define IO_MUX_GPIO21_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO21_FILTER_EN_S 15 - -/** IO_MUX_gpio22_REG register - * iomux control register for gpio22 - */ -#define IO_MUX_GPIO22_REG (DR_REG_IO_MUX_BASE + 0x5c) -/** IO_MUX_GPIO22_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO22_MCU_OE (BIT(0)) -#define IO_MUX_GPIO22_MCU_OE_M (IO_MUX_GPIO22_MCU_OE_V << IO_MUX_GPIO22_MCU_OE_S) -#define IO_MUX_GPIO22_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO22_MCU_OE_S 0 -/** IO_MUX_GPIO22_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO22_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO22_SLP_SEL_M (IO_MUX_GPIO22_SLP_SEL_V << IO_MUX_GPIO22_SLP_SEL_S) -#define IO_MUX_GPIO22_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO22_SLP_SEL_S 1 -/** IO_MUX_GPIO22_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO22_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO22_MCU_WPD_M (IO_MUX_GPIO22_MCU_WPD_V << IO_MUX_GPIO22_MCU_WPD_S) -#define IO_MUX_GPIO22_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO22_MCU_WPD_S 2 -/** IO_MUX_GPIO22_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO22_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO22_MCU_WPU_M (IO_MUX_GPIO22_MCU_WPU_V << IO_MUX_GPIO22_MCU_WPU_S) -#define IO_MUX_GPIO22_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO22_MCU_WPU_S 3 -/** IO_MUX_GPIO22_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO22_MCU_IE (BIT(4)) -#define IO_MUX_GPIO22_MCU_IE_M (IO_MUX_GPIO22_MCU_IE_V << IO_MUX_GPIO22_MCU_IE_S) -#define IO_MUX_GPIO22_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO22_MCU_IE_S 4 -/** IO_MUX_GPIO22_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO22_MCU_DRV 0x00000003U -#define IO_MUX_GPIO22_MCU_DRV_M (IO_MUX_GPIO22_MCU_DRV_V << IO_MUX_GPIO22_MCU_DRV_S) -#define IO_MUX_GPIO22_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO22_MCU_DRV_S 5 -/** IO_MUX_GPIO22_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO22_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO22_FUN_WPD_M (IO_MUX_GPIO22_FUN_WPD_V << IO_MUX_GPIO22_FUN_WPD_S) -#define IO_MUX_GPIO22_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO22_FUN_WPD_S 7 -/** IO_MUX_GPIO22_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO22_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO22_FUN_WPU_M (IO_MUX_GPIO22_FUN_WPU_V << IO_MUX_GPIO22_FUN_WPU_S) -#define IO_MUX_GPIO22_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO22_FUN_WPU_S 8 -/** IO_MUX_GPIO22_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO22_FUN_IE (BIT(9)) -#define IO_MUX_GPIO22_FUN_IE_M (IO_MUX_GPIO22_FUN_IE_V << IO_MUX_GPIO22_FUN_IE_S) -#define IO_MUX_GPIO22_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO22_FUN_IE_S 9 -/** IO_MUX_GPIO22_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO22_FUN_DRV 0x00000003U -#define IO_MUX_GPIO22_FUN_DRV_M (IO_MUX_GPIO22_FUN_DRV_V << IO_MUX_GPIO22_FUN_DRV_S) -#define IO_MUX_GPIO22_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO22_FUN_DRV_S 10 -/** IO_MUX_GPIO22_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO22_MCU_SEL 0x00000007U -#define IO_MUX_GPIO22_MCU_SEL_M (IO_MUX_GPIO22_MCU_SEL_V << IO_MUX_GPIO22_MCU_SEL_S) -#define IO_MUX_GPIO22_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO22_MCU_SEL_S 12 -/** IO_MUX_GPIO22_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO22_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO22_FILTER_EN_M (IO_MUX_GPIO22_FILTER_EN_V << IO_MUX_GPIO22_FILTER_EN_S) -#define IO_MUX_GPIO22_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO22_FILTER_EN_S 15 - -/** IO_MUX_gpio23_REG register - * iomux control register for gpio23 - */ -#define IO_MUX_GPIO23_REG (DR_REG_IO_MUX_BASE + 0x60) -/** IO_MUX_GPIO23_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO23_MCU_OE (BIT(0)) -#define IO_MUX_GPIO23_MCU_OE_M (IO_MUX_GPIO23_MCU_OE_V << IO_MUX_GPIO23_MCU_OE_S) -#define IO_MUX_GPIO23_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO23_MCU_OE_S 0 -/** IO_MUX_GPIO23_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO23_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO23_SLP_SEL_M (IO_MUX_GPIO23_SLP_SEL_V << IO_MUX_GPIO23_SLP_SEL_S) -#define IO_MUX_GPIO23_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO23_SLP_SEL_S 1 -/** IO_MUX_GPIO23_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO23_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO23_MCU_WPD_M (IO_MUX_GPIO23_MCU_WPD_V << IO_MUX_GPIO23_MCU_WPD_S) -#define IO_MUX_GPIO23_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO23_MCU_WPD_S 2 -/** IO_MUX_GPIO23_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO23_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO23_MCU_WPU_M (IO_MUX_GPIO23_MCU_WPU_V << IO_MUX_GPIO23_MCU_WPU_S) -#define IO_MUX_GPIO23_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO23_MCU_WPU_S 3 -/** IO_MUX_GPIO23_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO23_MCU_IE (BIT(4)) -#define IO_MUX_GPIO23_MCU_IE_M (IO_MUX_GPIO23_MCU_IE_V << IO_MUX_GPIO23_MCU_IE_S) -#define IO_MUX_GPIO23_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO23_MCU_IE_S 4 -/** IO_MUX_GPIO23_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO23_MCU_DRV 0x00000003U -#define IO_MUX_GPIO23_MCU_DRV_M (IO_MUX_GPIO23_MCU_DRV_V << IO_MUX_GPIO23_MCU_DRV_S) -#define IO_MUX_GPIO23_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO23_MCU_DRV_S 5 -/** IO_MUX_GPIO23_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO23_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO23_FUN_WPD_M (IO_MUX_GPIO23_FUN_WPD_V << IO_MUX_GPIO23_FUN_WPD_S) -#define IO_MUX_GPIO23_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO23_FUN_WPD_S 7 -/** IO_MUX_GPIO23_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO23_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO23_FUN_WPU_M (IO_MUX_GPIO23_FUN_WPU_V << IO_MUX_GPIO23_FUN_WPU_S) -#define IO_MUX_GPIO23_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO23_FUN_WPU_S 8 -/** IO_MUX_GPIO23_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO23_FUN_IE (BIT(9)) -#define IO_MUX_GPIO23_FUN_IE_M (IO_MUX_GPIO23_FUN_IE_V << IO_MUX_GPIO23_FUN_IE_S) -#define IO_MUX_GPIO23_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO23_FUN_IE_S 9 -/** IO_MUX_GPIO23_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO23_FUN_DRV 0x00000003U -#define IO_MUX_GPIO23_FUN_DRV_M (IO_MUX_GPIO23_FUN_DRV_V << IO_MUX_GPIO23_FUN_DRV_S) -#define IO_MUX_GPIO23_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO23_FUN_DRV_S 10 -/** IO_MUX_GPIO23_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO23_MCU_SEL 0x00000007U -#define IO_MUX_GPIO23_MCU_SEL_M (IO_MUX_GPIO23_MCU_SEL_V << IO_MUX_GPIO23_MCU_SEL_S) -#define IO_MUX_GPIO23_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO23_MCU_SEL_S 12 -/** IO_MUX_GPIO23_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO23_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO23_FILTER_EN_M (IO_MUX_GPIO23_FILTER_EN_V << IO_MUX_GPIO23_FILTER_EN_S) -#define IO_MUX_GPIO23_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO23_FILTER_EN_S 15 - -/** IO_MUX_gpio24_REG register - * iomux control register for gpio24 - */ -#define IO_MUX_GPIO24_REG (DR_REG_IO_MUX_BASE + 0x64) -/** IO_MUX_GPIO24_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO24_MCU_OE (BIT(0)) -#define IO_MUX_GPIO24_MCU_OE_M (IO_MUX_GPIO24_MCU_OE_V << IO_MUX_GPIO24_MCU_OE_S) -#define IO_MUX_GPIO24_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO24_MCU_OE_S 0 -/** IO_MUX_GPIO24_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO24_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO24_SLP_SEL_M (IO_MUX_GPIO24_SLP_SEL_V << IO_MUX_GPIO24_SLP_SEL_S) -#define IO_MUX_GPIO24_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO24_SLP_SEL_S 1 -/** IO_MUX_GPIO24_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO24_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO24_MCU_WPD_M (IO_MUX_GPIO24_MCU_WPD_V << IO_MUX_GPIO24_MCU_WPD_S) -#define IO_MUX_GPIO24_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO24_MCU_WPD_S 2 -/** IO_MUX_GPIO24_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO24_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO24_MCU_WPU_M (IO_MUX_GPIO24_MCU_WPU_V << IO_MUX_GPIO24_MCU_WPU_S) -#define IO_MUX_GPIO24_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO24_MCU_WPU_S 3 -/** IO_MUX_GPIO24_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO24_MCU_IE (BIT(4)) -#define IO_MUX_GPIO24_MCU_IE_M (IO_MUX_GPIO24_MCU_IE_V << IO_MUX_GPIO24_MCU_IE_S) -#define IO_MUX_GPIO24_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO24_MCU_IE_S 4 -/** IO_MUX_GPIO24_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO24_MCU_DRV 0x00000003U -#define IO_MUX_GPIO24_MCU_DRV_M (IO_MUX_GPIO24_MCU_DRV_V << IO_MUX_GPIO24_MCU_DRV_S) -#define IO_MUX_GPIO24_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO24_MCU_DRV_S 5 -/** IO_MUX_GPIO24_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO24_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO24_FUN_WPD_M (IO_MUX_GPIO24_FUN_WPD_V << IO_MUX_GPIO24_FUN_WPD_S) -#define IO_MUX_GPIO24_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO24_FUN_WPD_S 7 -/** IO_MUX_GPIO24_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO24_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO24_FUN_WPU_M (IO_MUX_GPIO24_FUN_WPU_V << IO_MUX_GPIO24_FUN_WPU_S) -#define IO_MUX_GPIO24_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO24_FUN_WPU_S 8 -/** IO_MUX_GPIO24_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO24_FUN_IE (BIT(9)) -#define IO_MUX_GPIO24_FUN_IE_M (IO_MUX_GPIO24_FUN_IE_V << IO_MUX_GPIO24_FUN_IE_S) -#define IO_MUX_GPIO24_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO24_FUN_IE_S 9 -/** IO_MUX_GPIO24_FUN_DRV : R/W; bitpos: [11:10]; default: 3; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO24_FUN_DRV 0x00000003U -#define IO_MUX_GPIO24_FUN_DRV_M (IO_MUX_GPIO24_FUN_DRV_V << IO_MUX_GPIO24_FUN_DRV_S) -#define IO_MUX_GPIO24_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO24_FUN_DRV_S 10 -/** IO_MUX_GPIO24_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO24_MCU_SEL 0x00000007U -#define IO_MUX_GPIO24_MCU_SEL_M (IO_MUX_GPIO24_MCU_SEL_V << IO_MUX_GPIO24_MCU_SEL_S) -#define IO_MUX_GPIO24_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO24_MCU_SEL_S 12 -/** IO_MUX_GPIO24_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO24_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO24_FILTER_EN_M (IO_MUX_GPIO24_FILTER_EN_V << IO_MUX_GPIO24_FILTER_EN_S) -#define IO_MUX_GPIO24_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO24_FILTER_EN_S 15 - -/** IO_MUX_gpio25_REG register - * iomux control register for gpio25 - */ -#define IO_MUX_GPIO25_REG (DR_REG_IO_MUX_BASE + 0x68) -/** IO_MUX_GPIO25_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO25_MCU_OE (BIT(0)) -#define IO_MUX_GPIO25_MCU_OE_M (IO_MUX_GPIO25_MCU_OE_V << IO_MUX_GPIO25_MCU_OE_S) -#define IO_MUX_GPIO25_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO25_MCU_OE_S 0 -/** IO_MUX_GPIO25_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO25_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO25_SLP_SEL_M (IO_MUX_GPIO25_SLP_SEL_V << IO_MUX_GPIO25_SLP_SEL_S) -#define IO_MUX_GPIO25_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO25_SLP_SEL_S 1 -/** IO_MUX_GPIO25_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO25_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO25_MCU_WPD_M (IO_MUX_GPIO25_MCU_WPD_V << IO_MUX_GPIO25_MCU_WPD_S) -#define IO_MUX_GPIO25_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO25_MCU_WPD_S 2 -/** IO_MUX_GPIO25_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO25_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO25_MCU_WPU_M (IO_MUX_GPIO25_MCU_WPU_V << IO_MUX_GPIO25_MCU_WPU_S) -#define IO_MUX_GPIO25_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO25_MCU_WPU_S 3 -/** IO_MUX_GPIO25_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO25_MCU_IE (BIT(4)) -#define IO_MUX_GPIO25_MCU_IE_M (IO_MUX_GPIO25_MCU_IE_V << IO_MUX_GPIO25_MCU_IE_S) -#define IO_MUX_GPIO25_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO25_MCU_IE_S 4 -/** IO_MUX_GPIO25_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO25_MCU_DRV 0x00000003U -#define IO_MUX_GPIO25_MCU_DRV_M (IO_MUX_GPIO25_MCU_DRV_V << IO_MUX_GPIO25_MCU_DRV_S) -#define IO_MUX_GPIO25_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO25_MCU_DRV_S 5 -/** IO_MUX_GPIO25_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO25_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO25_FUN_WPD_M (IO_MUX_GPIO25_FUN_WPD_V << IO_MUX_GPIO25_FUN_WPD_S) -#define IO_MUX_GPIO25_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO25_FUN_WPD_S 7 -/** IO_MUX_GPIO25_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO25_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO25_FUN_WPU_M (IO_MUX_GPIO25_FUN_WPU_V << IO_MUX_GPIO25_FUN_WPU_S) -#define IO_MUX_GPIO25_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO25_FUN_WPU_S 8 -/** IO_MUX_GPIO25_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO25_FUN_IE (BIT(9)) -#define IO_MUX_GPIO25_FUN_IE_M (IO_MUX_GPIO25_FUN_IE_V << IO_MUX_GPIO25_FUN_IE_S) -#define IO_MUX_GPIO25_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO25_FUN_IE_S 9 -/** IO_MUX_GPIO25_FUN_DRV : R/W; bitpos: [11:10]; default: 3; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO25_FUN_DRV 0x00000003U -#define IO_MUX_GPIO25_FUN_DRV_M (IO_MUX_GPIO25_FUN_DRV_V << IO_MUX_GPIO25_FUN_DRV_S) -#define IO_MUX_GPIO25_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO25_FUN_DRV_S 10 -/** IO_MUX_GPIO25_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO25_MCU_SEL 0x00000007U -#define IO_MUX_GPIO25_MCU_SEL_M (IO_MUX_GPIO25_MCU_SEL_V << IO_MUX_GPIO25_MCU_SEL_S) -#define IO_MUX_GPIO25_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO25_MCU_SEL_S 12 -/** IO_MUX_GPIO25_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO25_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO25_FILTER_EN_M (IO_MUX_GPIO25_FILTER_EN_V << IO_MUX_GPIO25_FILTER_EN_S) -#define IO_MUX_GPIO25_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO25_FILTER_EN_S 15 - -/** IO_MUX_gpio26_REG register - * iomux control register for gpio26 - */ -#define IO_MUX_GPIO26_REG (DR_REG_IO_MUX_BASE + 0x6c) -/** IO_MUX_GPIO26_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO26_MCU_OE (BIT(0)) -#define IO_MUX_GPIO26_MCU_OE_M (IO_MUX_GPIO26_MCU_OE_V << IO_MUX_GPIO26_MCU_OE_S) -#define IO_MUX_GPIO26_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO26_MCU_OE_S 0 -/** IO_MUX_GPIO26_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO26_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO26_SLP_SEL_M (IO_MUX_GPIO26_SLP_SEL_V << IO_MUX_GPIO26_SLP_SEL_S) -#define IO_MUX_GPIO26_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO26_SLP_SEL_S 1 -/** IO_MUX_GPIO26_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO26_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO26_MCU_WPD_M (IO_MUX_GPIO26_MCU_WPD_V << IO_MUX_GPIO26_MCU_WPD_S) -#define IO_MUX_GPIO26_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO26_MCU_WPD_S 2 -/** IO_MUX_GPIO26_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO26_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO26_MCU_WPU_M (IO_MUX_GPIO26_MCU_WPU_V << IO_MUX_GPIO26_MCU_WPU_S) -#define IO_MUX_GPIO26_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO26_MCU_WPU_S 3 -/** IO_MUX_GPIO26_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO26_MCU_IE (BIT(4)) -#define IO_MUX_GPIO26_MCU_IE_M (IO_MUX_GPIO26_MCU_IE_V << IO_MUX_GPIO26_MCU_IE_S) -#define IO_MUX_GPIO26_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO26_MCU_IE_S 4 -/** IO_MUX_GPIO26_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO26_MCU_DRV 0x00000003U -#define IO_MUX_GPIO26_MCU_DRV_M (IO_MUX_GPIO26_MCU_DRV_V << IO_MUX_GPIO26_MCU_DRV_S) -#define IO_MUX_GPIO26_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO26_MCU_DRV_S 5 -/** IO_MUX_GPIO26_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO26_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO26_FUN_WPD_M (IO_MUX_GPIO26_FUN_WPD_V << IO_MUX_GPIO26_FUN_WPD_S) -#define IO_MUX_GPIO26_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO26_FUN_WPD_S 7 -/** IO_MUX_GPIO26_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO26_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO26_FUN_WPU_M (IO_MUX_GPIO26_FUN_WPU_V << IO_MUX_GPIO26_FUN_WPU_S) -#define IO_MUX_GPIO26_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO26_FUN_WPU_S 8 -/** IO_MUX_GPIO26_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO26_FUN_IE (BIT(9)) -#define IO_MUX_GPIO26_FUN_IE_M (IO_MUX_GPIO26_FUN_IE_V << IO_MUX_GPIO26_FUN_IE_S) -#define IO_MUX_GPIO26_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO26_FUN_IE_S 9 -/** IO_MUX_GPIO26_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO26_FUN_DRV 0x00000003U -#define IO_MUX_GPIO26_FUN_DRV_M (IO_MUX_GPIO26_FUN_DRV_V << IO_MUX_GPIO26_FUN_DRV_S) -#define IO_MUX_GPIO26_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO26_FUN_DRV_S 10 -/** IO_MUX_GPIO26_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO26_MCU_SEL 0x00000007U -#define IO_MUX_GPIO26_MCU_SEL_M (IO_MUX_GPIO26_MCU_SEL_V << IO_MUX_GPIO26_MCU_SEL_S) -#define IO_MUX_GPIO26_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO26_MCU_SEL_S 12 -/** IO_MUX_GPIO26_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO26_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO26_FILTER_EN_M (IO_MUX_GPIO26_FILTER_EN_V << IO_MUX_GPIO26_FILTER_EN_S) -#define IO_MUX_GPIO26_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO26_FILTER_EN_S 15 - -/** IO_MUX_gpio27_REG register - * iomux control register for gpio27 - */ -#define IO_MUX_GPIO27_REG (DR_REG_IO_MUX_BASE + 0x70) -/** IO_MUX_GPIO27_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO27_MCU_OE (BIT(0)) -#define IO_MUX_GPIO27_MCU_OE_M (IO_MUX_GPIO27_MCU_OE_V << IO_MUX_GPIO27_MCU_OE_S) -#define IO_MUX_GPIO27_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO27_MCU_OE_S 0 -/** IO_MUX_GPIO27_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO27_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO27_SLP_SEL_M (IO_MUX_GPIO27_SLP_SEL_V << IO_MUX_GPIO27_SLP_SEL_S) -#define IO_MUX_GPIO27_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO27_SLP_SEL_S 1 -/** IO_MUX_GPIO27_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO27_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO27_MCU_WPD_M (IO_MUX_GPIO27_MCU_WPD_V << IO_MUX_GPIO27_MCU_WPD_S) -#define IO_MUX_GPIO27_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO27_MCU_WPD_S 2 -/** IO_MUX_GPIO27_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO27_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO27_MCU_WPU_M (IO_MUX_GPIO27_MCU_WPU_V << IO_MUX_GPIO27_MCU_WPU_S) -#define IO_MUX_GPIO27_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO27_MCU_WPU_S 3 -/** IO_MUX_GPIO27_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO27_MCU_IE (BIT(4)) -#define IO_MUX_GPIO27_MCU_IE_M (IO_MUX_GPIO27_MCU_IE_V << IO_MUX_GPIO27_MCU_IE_S) -#define IO_MUX_GPIO27_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO27_MCU_IE_S 4 -/** IO_MUX_GPIO27_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO27_MCU_DRV 0x00000003U -#define IO_MUX_GPIO27_MCU_DRV_M (IO_MUX_GPIO27_MCU_DRV_V << IO_MUX_GPIO27_MCU_DRV_S) -#define IO_MUX_GPIO27_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO27_MCU_DRV_S 5 -/** IO_MUX_GPIO27_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO27_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO27_FUN_WPD_M (IO_MUX_GPIO27_FUN_WPD_V << IO_MUX_GPIO27_FUN_WPD_S) -#define IO_MUX_GPIO27_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO27_FUN_WPD_S 7 -/** IO_MUX_GPIO27_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO27_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO27_FUN_WPU_M (IO_MUX_GPIO27_FUN_WPU_V << IO_MUX_GPIO27_FUN_WPU_S) -#define IO_MUX_GPIO27_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO27_FUN_WPU_S 8 -/** IO_MUX_GPIO27_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO27_FUN_IE (BIT(9)) -#define IO_MUX_GPIO27_FUN_IE_M (IO_MUX_GPIO27_FUN_IE_V << IO_MUX_GPIO27_FUN_IE_S) -#define IO_MUX_GPIO27_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO27_FUN_IE_S 9 -/** IO_MUX_GPIO27_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO27_FUN_DRV 0x00000003U -#define IO_MUX_GPIO27_FUN_DRV_M (IO_MUX_GPIO27_FUN_DRV_V << IO_MUX_GPIO27_FUN_DRV_S) -#define IO_MUX_GPIO27_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO27_FUN_DRV_S 10 -/** IO_MUX_GPIO27_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO27_MCU_SEL 0x00000007U -#define IO_MUX_GPIO27_MCU_SEL_M (IO_MUX_GPIO27_MCU_SEL_V << IO_MUX_GPIO27_MCU_SEL_S) -#define IO_MUX_GPIO27_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO27_MCU_SEL_S 12 -/** IO_MUX_GPIO27_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO27_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO27_FILTER_EN_M (IO_MUX_GPIO27_FILTER_EN_V << IO_MUX_GPIO27_FILTER_EN_S) -#define IO_MUX_GPIO27_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO27_FILTER_EN_S 15 - -/** IO_MUX_gpio28_REG register - * iomux control register for gpio28 - */ -#define IO_MUX_GPIO28_REG (DR_REG_IO_MUX_BASE + 0x74) -/** IO_MUX_GPIO28_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO28_MCU_OE (BIT(0)) -#define IO_MUX_GPIO28_MCU_OE_M (IO_MUX_GPIO28_MCU_OE_V << IO_MUX_GPIO28_MCU_OE_S) -#define IO_MUX_GPIO28_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO28_MCU_OE_S 0 -/** IO_MUX_GPIO28_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO28_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO28_SLP_SEL_M (IO_MUX_GPIO28_SLP_SEL_V << IO_MUX_GPIO28_SLP_SEL_S) -#define IO_MUX_GPIO28_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO28_SLP_SEL_S 1 -/** IO_MUX_GPIO28_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO28_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO28_MCU_WPD_M (IO_MUX_GPIO28_MCU_WPD_V << IO_MUX_GPIO28_MCU_WPD_S) -#define IO_MUX_GPIO28_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO28_MCU_WPD_S 2 -/** IO_MUX_GPIO28_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO28_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO28_MCU_WPU_M (IO_MUX_GPIO28_MCU_WPU_V << IO_MUX_GPIO28_MCU_WPU_S) -#define IO_MUX_GPIO28_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO28_MCU_WPU_S 3 -/** IO_MUX_GPIO28_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO28_MCU_IE (BIT(4)) -#define IO_MUX_GPIO28_MCU_IE_M (IO_MUX_GPIO28_MCU_IE_V << IO_MUX_GPIO28_MCU_IE_S) -#define IO_MUX_GPIO28_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO28_MCU_IE_S 4 -/** IO_MUX_GPIO28_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO28_MCU_DRV 0x00000003U -#define IO_MUX_GPIO28_MCU_DRV_M (IO_MUX_GPIO28_MCU_DRV_V << IO_MUX_GPIO28_MCU_DRV_S) -#define IO_MUX_GPIO28_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO28_MCU_DRV_S 5 -/** IO_MUX_GPIO28_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO28_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO28_FUN_WPD_M (IO_MUX_GPIO28_FUN_WPD_V << IO_MUX_GPIO28_FUN_WPD_S) -#define IO_MUX_GPIO28_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO28_FUN_WPD_S 7 -/** IO_MUX_GPIO28_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO28_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO28_FUN_WPU_M (IO_MUX_GPIO28_FUN_WPU_V << IO_MUX_GPIO28_FUN_WPU_S) -#define IO_MUX_GPIO28_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO28_FUN_WPU_S 8 -/** IO_MUX_GPIO28_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO28_FUN_IE (BIT(9)) -#define IO_MUX_GPIO28_FUN_IE_M (IO_MUX_GPIO28_FUN_IE_V << IO_MUX_GPIO28_FUN_IE_S) -#define IO_MUX_GPIO28_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO28_FUN_IE_S 9 -/** IO_MUX_GPIO28_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO28_FUN_DRV 0x00000003U -#define IO_MUX_GPIO28_FUN_DRV_M (IO_MUX_GPIO28_FUN_DRV_V << IO_MUX_GPIO28_FUN_DRV_S) -#define IO_MUX_GPIO28_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO28_FUN_DRV_S 10 -/** IO_MUX_GPIO28_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO28_MCU_SEL 0x00000007U -#define IO_MUX_GPIO28_MCU_SEL_M (IO_MUX_GPIO28_MCU_SEL_V << IO_MUX_GPIO28_MCU_SEL_S) -#define IO_MUX_GPIO28_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO28_MCU_SEL_S 12 -/** IO_MUX_GPIO28_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO28_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO28_FILTER_EN_M (IO_MUX_GPIO28_FILTER_EN_V << IO_MUX_GPIO28_FILTER_EN_S) -#define IO_MUX_GPIO28_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO28_FILTER_EN_S 15 - -/** IO_MUX_gpio29_REG register - * iomux control register for gpio29 - */ -#define IO_MUX_GPIO29_REG (DR_REG_IO_MUX_BASE + 0x78) -/** IO_MUX_GPIO29_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO29_MCU_OE (BIT(0)) -#define IO_MUX_GPIO29_MCU_OE_M (IO_MUX_GPIO29_MCU_OE_V << IO_MUX_GPIO29_MCU_OE_S) -#define IO_MUX_GPIO29_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO29_MCU_OE_S 0 -/** IO_MUX_GPIO29_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO29_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO29_SLP_SEL_M (IO_MUX_GPIO29_SLP_SEL_V << IO_MUX_GPIO29_SLP_SEL_S) -#define IO_MUX_GPIO29_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO29_SLP_SEL_S 1 -/** IO_MUX_GPIO29_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO29_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO29_MCU_WPD_M (IO_MUX_GPIO29_MCU_WPD_V << IO_MUX_GPIO29_MCU_WPD_S) -#define IO_MUX_GPIO29_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO29_MCU_WPD_S 2 -/** IO_MUX_GPIO29_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO29_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO29_MCU_WPU_M (IO_MUX_GPIO29_MCU_WPU_V << IO_MUX_GPIO29_MCU_WPU_S) -#define IO_MUX_GPIO29_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO29_MCU_WPU_S 3 -/** IO_MUX_GPIO29_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO29_MCU_IE (BIT(4)) -#define IO_MUX_GPIO29_MCU_IE_M (IO_MUX_GPIO29_MCU_IE_V << IO_MUX_GPIO29_MCU_IE_S) -#define IO_MUX_GPIO29_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO29_MCU_IE_S 4 -/** IO_MUX_GPIO29_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO29_MCU_DRV 0x00000003U -#define IO_MUX_GPIO29_MCU_DRV_M (IO_MUX_GPIO29_MCU_DRV_V << IO_MUX_GPIO29_MCU_DRV_S) -#define IO_MUX_GPIO29_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO29_MCU_DRV_S 5 -/** IO_MUX_GPIO29_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO29_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO29_FUN_WPD_M (IO_MUX_GPIO29_FUN_WPD_V << IO_MUX_GPIO29_FUN_WPD_S) -#define IO_MUX_GPIO29_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO29_FUN_WPD_S 7 -/** IO_MUX_GPIO29_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO29_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO29_FUN_WPU_M (IO_MUX_GPIO29_FUN_WPU_V << IO_MUX_GPIO29_FUN_WPU_S) -#define IO_MUX_GPIO29_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO29_FUN_WPU_S 8 -/** IO_MUX_GPIO29_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO29_FUN_IE (BIT(9)) -#define IO_MUX_GPIO29_FUN_IE_M (IO_MUX_GPIO29_FUN_IE_V << IO_MUX_GPIO29_FUN_IE_S) -#define IO_MUX_GPIO29_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO29_FUN_IE_S 9 -/** IO_MUX_GPIO29_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO29_FUN_DRV 0x00000003U -#define IO_MUX_GPIO29_FUN_DRV_M (IO_MUX_GPIO29_FUN_DRV_V << IO_MUX_GPIO29_FUN_DRV_S) -#define IO_MUX_GPIO29_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO29_FUN_DRV_S 10 -/** IO_MUX_GPIO29_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO29_MCU_SEL 0x00000007U -#define IO_MUX_GPIO29_MCU_SEL_M (IO_MUX_GPIO29_MCU_SEL_V << IO_MUX_GPIO29_MCU_SEL_S) -#define IO_MUX_GPIO29_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO29_MCU_SEL_S 12 -/** IO_MUX_GPIO29_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO29_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO29_FILTER_EN_M (IO_MUX_GPIO29_FILTER_EN_V << IO_MUX_GPIO29_FILTER_EN_S) -#define IO_MUX_GPIO29_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO29_FILTER_EN_S 15 - -/** IO_MUX_gpio30_REG register - * iomux control register for gpio30 - */ -#define IO_MUX_GPIO30_REG (DR_REG_IO_MUX_BASE + 0x7c) -/** IO_MUX_GPIO30_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO30_MCU_OE (BIT(0)) -#define IO_MUX_GPIO30_MCU_OE_M (IO_MUX_GPIO30_MCU_OE_V << IO_MUX_GPIO30_MCU_OE_S) -#define IO_MUX_GPIO30_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO30_MCU_OE_S 0 -/** IO_MUX_GPIO30_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO30_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO30_SLP_SEL_M (IO_MUX_GPIO30_SLP_SEL_V << IO_MUX_GPIO30_SLP_SEL_S) -#define IO_MUX_GPIO30_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO30_SLP_SEL_S 1 -/** IO_MUX_GPIO30_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO30_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO30_MCU_WPD_M (IO_MUX_GPIO30_MCU_WPD_V << IO_MUX_GPIO30_MCU_WPD_S) -#define IO_MUX_GPIO30_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO30_MCU_WPD_S 2 -/** IO_MUX_GPIO30_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO30_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO30_MCU_WPU_M (IO_MUX_GPIO30_MCU_WPU_V << IO_MUX_GPIO30_MCU_WPU_S) -#define IO_MUX_GPIO30_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO30_MCU_WPU_S 3 -/** IO_MUX_GPIO30_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO30_MCU_IE (BIT(4)) -#define IO_MUX_GPIO30_MCU_IE_M (IO_MUX_GPIO30_MCU_IE_V << IO_MUX_GPIO30_MCU_IE_S) -#define IO_MUX_GPIO30_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO30_MCU_IE_S 4 -/** IO_MUX_GPIO30_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO30_MCU_DRV 0x00000003U -#define IO_MUX_GPIO30_MCU_DRV_M (IO_MUX_GPIO30_MCU_DRV_V << IO_MUX_GPIO30_MCU_DRV_S) -#define IO_MUX_GPIO30_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO30_MCU_DRV_S 5 -/** IO_MUX_GPIO30_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO30_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO30_FUN_WPD_M (IO_MUX_GPIO30_FUN_WPD_V << IO_MUX_GPIO30_FUN_WPD_S) -#define IO_MUX_GPIO30_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO30_FUN_WPD_S 7 -/** IO_MUX_GPIO30_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO30_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO30_FUN_WPU_M (IO_MUX_GPIO30_FUN_WPU_V << IO_MUX_GPIO30_FUN_WPU_S) -#define IO_MUX_GPIO30_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO30_FUN_WPU_S 8 -/** IO_MUX_GPIO30_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO30_FUN_IE (BIT(9)) -#define IO_MUX_GPIO30_FUN_IE_M (IO_MUX_GPIO30_FUN_IE_V << IO_MUX_GPIO30_FUN_IE_S) -#define IO_MUX_GPIO30_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO30_FUN_IE_S 9 -/** IO_MUX_GPIO30_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO30_FUN_DRV 0x00000003U -#define IO_MUX_GPIO30_FUN_DRV_M (IO_MUX_GPIO30_FUN_DRV_V << IO_MUX_GPIO30_FUN_DRV_S) -#define IO_MUX_GPIO30_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO30_FUN_DRV_S 10 -/** IO_MUX_GPIO30_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO30_MCU_SEL 0x00000007U -#define IO_MUX_GPIO30_MCU_SEL_M (IO_MUX_GPIO30_MCU_SEL_V << IO_MUX_GPIO30_MCU_SEL_S) -#define IO_MUX_GPIO30_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO30_MCU_SEL_S 12 -/** IO_MUX_GPIO30_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO30_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO30_FILTER_EN_M (IO_MUX_GPIO30_FILTER_EN_V << IO_MUX_GPIO30_FILTER_EN_S) -#define IO_MUX_GPIO30_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO30_FILTER_EN_S 15 - -/** IO_MUX_gpio31_REG register - * iomux control register for gpio31 - */ -#define IO_MUX_GPIO31_REG (DR_REG_IO_MUX_BASE + 0x80) -/** IO_MUX_GPIO31_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO31_MCU_OE (BIT(0)) -#define IO_MUX_GPIO31_MCU_OE_M (IO_MUX_GPIO31_MCU_OE_V << IO_MUX_GPIO31_MCU_OE_S) -#define IO_MUX_GPIO31_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO31_MCU_OE_S 0 -/** IO_MUX_GPIO31_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO31_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO31_SLP_SEL_M (IO_MUX_GPIO31_SLP_SEL_V << IO_MUX_GPIO31_SLP_SEL_S) -#define IO_MUX_GPIO31_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO31_SLP_SEL_S 1 -/** IO_MUX_GPIO31_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO31_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO31_MCU_WPD_M (IO_MUX_GPIO31_MCU_WPD_V << IO_MUX_GPIO31_MCU_WPD_S) -#define IO_MUX_GPIO31_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO31_MCU_WPD_S 2 -/** IO_MUX_GPIO31_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO31_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO31_MCU_WPU_M (IO_MUX_GPIO31_MCU_WPU_V << IO_MUX_GPIO31_MCU_WPU_S) -#define IO_MUX_GPIO31_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO31_MCU_WPU_S 3 -/** IO_MUX_GPIO31_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO31_MCU_IE (BIT(4)) -#define IO_MUX_GPIO31_MCU_IE_M (IO_MUX_GPIO31_MCU_IE_V << IO_MUX_GPIO31_MCU_IE_S) -#define IO_MUX_GPIO31_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO31_MCU_IE_S 4 -/** IO_MUX_GPIO31_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO31_MCU_DRV 0x00000003U -#define IO_MUX_GPIO31_MCU_DRV_M (IO_MUX_GPIO31_MCU_DRV_V << IO_MUX_GPIO31_MCU_DRV_S) -#define IO_MUX_GPIO31_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO31_MCU_DRV_S 5 -/** IO_MUX_GPIO31_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO31_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO31_FUN_WPD_M (IO_MUX_GPIO31_FUN_WPD_V << IO_MUX_GPIO31_FUN_WPD_S) -#define IO_MUX_GPIO31_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO31_FUN_WPD_S 7 -/** IO_MUX_GPIO31_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO31_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO31_FUN_WPU_M (IO_MUX_GPIO31_FUN_WPU_V << IO_MUX_GPIO31_FUN_WPU_S) -#define IO_MUX_GPIO31_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO31_FUN_WPU_S 8 -/** IO_MUX_GPIO31_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO31_FUN_IE (BIT(9)) -#define IO_MUX_GPIO31_FUN_IE_M (IO_MUX_GPIO31_FUN_IE_V << IO_MUX_GPIO31_FUN_IE_S) -#define IO_MUX_GPIO31_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO31_FUN_IE_S 9 -/** IO_MUX_GPIO31_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO31_FUN_DRV 0x00000003U -#define IO_MUX_GPIO31_FUN_DRV_M (IO_MUX_GPIO31_FUN_DRV_V << IO_MUX_GPIO31_FUN_DRV_S) -#define IO_MUX_GPIO31_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO31_FUN_DRV_S 10 -/** IO_MUX_GPIO31_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO31_MCU_SEL 0x00000007U -#define IO_MUX_GPIO31_MCU_SEL_M (IO_MUX_GPIO31_MCU_SEL_V << IO_MUX_GPIO31_MCU_SEL_S) -#define IO_MUX_GPIO31_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO31_MCU_SEL_S 12 -/** IO_MUX_GPIO31_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO31_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO31_FILTER_EN_M (IO_MUX_GPIO31_FILTER_EN_V << IO_MUX_GPIO31_FILTER_EN_S) -#define IO_MUX_GPIO31_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO31_FILTER_EN_S 15 - -/** IO_MUX_gpio32_REG register - * iomux control register for gpio32 - */ -#define IO_MUX_GPIO32_REG (DR_REG_IO_MUX_BASE + 0x84) -/** IO_MUX_GPIO32_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO32_MCU_OE (BIT(0)) -#define IO_MUX_GPIO32_MCU_OE_M (IO_MUX_GPIO32_MCU_OE_V << IO_MUX_GPIO32_MCU_OE_S) -#define IO_MUX_GPIO32_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO32_MCU_OE_S 0 -/** IO_MUX_GPIO32_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO32_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO32_SLP_SEL_M (IO_MUX_GPIO32_SLP_SEL_V << IO_MUX_GPIO32_SLP_SEL_S) -#define IO_MUX_GPIO32_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO32_SLP_SEL_S 1 -/** IO_MUX_GPIO32_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO32_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO32_MCU_WPD_M (IO_MUX_GPIO32_MCU_WPD_V << IO_MUX_GPIO32_MCU_WPD_S) -#define IO_MUX_GPIO32_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO32_MCU_WPD_S 2 -/** IO_MUX_GPIO32_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO32_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO32_MCU_WPU_M (IO_MUX_GPIO32_MCU_WPU_V << IO_MUX_GPIO32_MCU_WPU_S) -#define IO_MUX_GPIO32_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO32_MCU_WPU_S 3 -/** IO_MUX_GPIO32_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO32_MCU_IE (BIT(4)) -#define IO_MUX_GPIO32_MCU_IE_M (IO_MUX_GPIO32_MCU_IE_V << IO_MUX_GPIO32_MCU_IE_S) -#define IO_MUX_GPIO32_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO32_MCU_IE_S 4 -/** IO_MUX_GPIO32_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO32_MCU_DRV 0x00000003U -#define IO_MUX_GPIO32_MCU_DRV_M (IO_MUX_GPIO32_MCU_DRV_V << IO_MUX_GPIO32_MCU_DRV_S) -#define IO_MUX_GPIO32_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO32_MCU_DRV_S 5 -/** IO_MUX_GPIO32_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO32_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO32_FUN_WPD_M (IO_MUX_GPIO32_FUN_WPD_V << IO_MUX_GPIO32_FUN_WPD_S) -#define IO_MUX_GPIO32_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO32_FUN_WPD_S 7 -/** IO_MUX_GPIO32_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO32_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO32_FUN_WPU_M (IO_MUX_GPIO32_FUN_WPU_V << IO_MUX_GPIO32_FUN_WPU_S) -#define IO_MUX_GPIO32_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO32_FUN_WPU_S 8 -/** IO_MUX_GPIO32_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO32_FUN_IE (BIT(9)) -#define IO_MUX_GPIO32_FUN_IE_M (IO_MUX_GPIO32_FUN_IE_V << IO_MUX_GPIO32_FUN_IE_S) -#define IO_MUX_GPIO32_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO32_FUN_IE_S 9 -/** IO_MUX_GPIO32_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO32_FUN_DRV 0x00000003U -#define IO_MUX_GPIO32_FUN_DRV_M (IO_MUX_GPIO32_FUN_DRV_V << IO_MUX_GPIO32_FUN_DRV_S) -#define IO_MUX_GPIO32_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO32_FUN_DRV_S 10 -/** IO_MUX_GPIO32_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO32_MCU_SEL 0x00000007U -#define IO_MUX_GPIO32_MCU_SEL_M (IO_MUX_GPIO32_MCU_SEL_V << IO_MUX_GPIO32_MCU_SEL_S) -#define IO_MUX_GPIO32_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO32_MCU_SEL_S 12 -/** IO_MUX_GPIO32_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO32_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO32_FILTER_EN_M (IO_MUX_GPIO32_FILTER_EN_V << IO_MUX_GPIO32_FILTER_EN_S) -#define IO_MUX_GPIO32_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO32_FILTER_EN_S 15 -/** IO_MUX_GPIO32_RUE_I3C : R/W; bitpos: [16]; default: 0; - * NA - */ -#define IO_MUX_GPIO32_RUE_I3C (BIT(16)) -#define IO_MUX_GPIO32_RUE_I3C_M (IO_MUX_GPIO32_RUE_I3C_V << IO_MUX_GPIO32_RUE_I3C_S) -#define IO_MUX_GPIO32_RUE_I3C_V 0x00000001U -#define IO_MUX_GPIO32_RUE_I3C_S 16 -/** IO_MUX_GPIO32_RU_I3C : R/W; bitpos: [18:17]; default: 0; - * NA - */ -#define IO_MUX_GPIO32_RU_I3C 0x00000003U -#define IO_MUX_GPIO32_RU_I3C_M (IO_MUX_GPIO32_RU_I3C_V << IO_MUX_GPIO32_RU_I3C_S) -#define IO_MUX_GPIO32_RU_I3C_V 0x00000003U -#define IO_MUX_GPIO32_RU_I3C_S 17 -/** IO_MUX_GPIO32_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0; - * NA - */ -#define IO_MUX_GPIO32_RUE_SEL_I3C (BIT(19)) -#define IO_MUX_GPIO32_RUE_SEL_I3C_M (IO_MUX_GPIO32_RUE_SEL_I3C_V << IO_MUX_GPIO32_RUE_SEL_I3C_S) -#define IO_MUX_GPIO32_RUE_SEL_I3C_V 0x00000001U -#define IO_MUX_GPIO32_RUE_SEL_I3C_S 19 - -/** IO_MUX_gpio33_REG register - * iomux control register for gpio33 - */ -#define IO_MUX_GPIO33_REG (DR_REG_IO_MUX_BASE + 0x88) -/** IO_MUX_GPIO33_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO33_MCU_OE (BIT(0)) -#define IO_MUX_GPIO33_MCU_OE_M (IO_MUX_GPIO33_MCU_OE_V << IO_MUX_GPIO33_MCU_OE_S) -#define IO_MUX_GPIO33_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO33_MCU_OE_S 0 -/** IO_MUX_GPIO33_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO33_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO33_SLP_SEL_M (IO_MUX_GPIO33_SLP_SEL_V << IO_MUX_GPIO33_SLP_SEL_S) -#define IO_MUX_GPIO33_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO33_SLP_SEL_S 1 -/** IO_MUX_GPIO33_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO33_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO33_MCU_WPD_M (IO_MUX_GPIO33_MCU_WPD_V << IO_MUX_GPIO33_MCU_WPD_S) -#define IO_MUX_GPIO33_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO33_MCU_WPD_S 2 -/** IO_MUX_GPIO33_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO33_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO33_MCU_WPU_M (IO_MUX_GPIO33_MCU_WPU_V << IO_MUX_GPIO33_MCU_WPU_S) -#define IO_MUX_GPIO33_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO33_MCU_WPU_S 3 -/** IO_MUX_GPIO33_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO33_MCU_IE (BIT(4)) -#define IO_MUX_GPIO33_MCU_IE_M (IO_MUX_GPIO33_MCU_IE_V << IO_MUX_GPIO33_MCU_IE_S) -#define IO_MUX_GPIO33_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO33_MCU_IE_S 4 -/** IO_MUX_GPIO33_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO33_MCU_DRV 0x00000003U -#define IO_MUX_GPIO33_MCU_DRV_M (IO_MUX_GPIO33_MCU_DRV_V << IO_MUX_GPIO33_MCU_DRV_S) -#define IO_MUX_GPIO33_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO33_MCU_DRV_S 5 -/** IO_MUX_GPIO33_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO33_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO33_FUN_WPD_M (IO_MUX_GPIO33_FUN_WPD_V << IO_MUX_GPIO33_FUN_WPD_S) -#define IO_MUX_GPIO33_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO33_FUN_WPD_S 7 -/** IO_MUX_GPIO33_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO33_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO33_FUN_WPU_M (IO_MUX_GPIO33_FUN_WPU_V << IO_MUX_GPIO33_FUN_WPU_S) -#define IO_MUX_GPIO33_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO33_FUN_WPU_S 8 -/** IO_MUX_GPIO33_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO33_FUN_IE (BIT(9)) -#define IO_MUX_GPIO33_FUN_IE_M (IO_MUX_GPIO33_FUN_IE_V << IO_MUX_GPIO33_FUN_IE_S) -#define IO_MUX_GPIO33_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO33_FUN_IE_S 9 -/** IO_MUX_GPIO33_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO33_FUN_DRV 0x00000003U -#define IO_MUX_GPIO33_FUN_DRV_M (IO_MUX_GPIO33_FUN_DRV_V << IO_MUX_GPIO33_FUN_DRV_S) -#define IO_MUX_GPIO33_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO33_FUN_DRV_S 10 -/** IO_MUX_GPIO33_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO33_MCU_SEL 0x00000007U -#define IO_MUX_GPIO33_MCU_SEL_M (IO_MUX_GPIO33_MCU_SEL_V << IO_MUX_GPIO33_MCU_SEL_S) -#define IO_MUX_GPIO33_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO33_MCU_SEL_S 12 -/** IO_MUX_GPIO33_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO33_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO33_FILTER_EN_M (IO_MUX_GPIO33_FILTER_EN_V << IO_MUX_GPIO33_FILTER_EN_S) -#define IO_MUX_GPIO33_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO33_FILTER_EN_S 15 -/** IO_MUX_GPIO33_RUE_I3C : R/W; bitpos: [16]; default: 0; - * NA - */ -#define IO_MUX_GPIO33_RUE_I3C (BIT(16)) -#define IO_MUX_GPIO33_RUE_I3C_M (IO_MUX_GPIO33_RUE_I3C_V << IO_MUX_GPIO33_RUE_I3C_S) -#define IO_MUX_GPIO33_RUE_I3C_V 0x00000001U -#define IO_MUX_GPIO33_RUE_I3C_S 16 -/** IO_MUX_GPIO33_RU_I3C : R/W; bitpos: [18:17]; default: 0; - * NA - */ -#define IO_MUX_GPIO33_RU_I3C 0x00000003U -#define IO_MUX_GPIO33_RU_I3C_M (IO_MUX_GPIO33_RU_I3C_V << IO_MUX_GPIO33_RU_I3C_S) -#define IO_MUX_GPIO33_RU_I3C_V 0x00000003U -#define IO_MUX_GPIO33_RU_I3C_S 17 -/** IO_MUX_GPIO33_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0; - * NA - */ -#define IO_MUX_GPIO33_RUE_SEL_I3C (BIT(19)) -#define IO_MUX_GPIO33_RUE_SEL_I3C_M (IO_MUX_GPIO33_RUE_SEL_I3C_V << IO_MUX_GPIO33_RUE_SEL_I3C_S) -#define IO_MUX_GPIO33_RUE_SEL_I3C_V 0x00000001U -#define IO_MUX_GPIO33_RUE_SEL_I3C_S 19 - -/** IO_MUX_gpio34_REG register - * iomux control register for gpio34 - */ -#define IO_MUX_GPIO34_REG (DR_REG_IO_MUX_BASE + 0x8c) -/** IO_MUX_GPIO34_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO34_MCU_OE (BIT(0)) -#define IO_MUX_GPIO34_MCU_OE_M (IO_MUX_GPIO34_MCU_OE_V << IO_MUX_GPIO34_MCU_OE_S) -#define IO_MUX_GPIO34_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO34_MCU_OE_S 0 -/** IO_MUX_GPIO34_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO34_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO34_SLP_SEL_M (IO_MUX_GPIO34_SLP_SEL_V << IO_MUX_GPIO34_SLP_SEL_S) -#define IO_MUX_GPIO34_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO34_SLP_SEL_S 1 -/** IO_MUX_GPIO34_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO34_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO34_MCU_WPD_M (IO_MUX_GPIO34_MCU_WPD_V << IO_MUX_GPIO34_MCU_WPD_S) -#define IO_MUX_GPIO34_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO34_MCU_WPD_S 2 -/** IO_MUX_GPIO34_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO34_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO34_MCU_WPU_M (IO_MUX_GPIO34_MCU_WPU_V << IO_MUX_GPIO34_MCU_WPU_S) -#define IO_MUX_GPIO34_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO34_MCU_WPU_S 3 -/** IO_MUX_GPIO34_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO34_MCU_IE (BIT(4)) -#define IO_MUX_GPIO34_MCU_IE_M (IO_MUX_GPIO34_MCU_IE_V << IO_MUX_GPIO34_MCU_IE_S) -#define IO_MUX_GPIO34_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO34_MCU_IE_S 4 -/** IO_MUX_GPIO34_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO34_MCU_DRV 0x00000003U -#define IO_MUX_GPIO34_MCU_DRV_M (IO_MUX_GPIO34_MCU_DRV_V << IO_MUX_GPIO34_MCU_DRV_S) -#define IO_MUX_GPIO34_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO34_MCU_DRV_S 5 -/** IO_MUX_GPIO34_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO34_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO34_FUN_WPD_M (IO_MUX_GPIO34_FUN_WPD_V << IO_MUX_GPIO34_FUN_WPD_S) -#define IO_MUX_GPIO34_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO34_FUN_WPD_S 7 -/** IO_MUX_GPIO34_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO34_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO34_FUN_WPU_M (IO_MUX_GPIO34_FUN_WPU_V << IO_MUX_GPIO34_FUN_WPU_S) -#define IO_MUX_GPIO34_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO34_FUN_WPU_S 8 -/** IO_MUX_GPIO34_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO34_FUN_IE (BIT(9)) -#define IO_MUX_GPIO34_FUN_IE_M (IO_MUX_GPIO34_FUN_IE_V << IO_MUX_GPIO34_FUN_IE_S) -#define IO_MUX_GPIO34_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO34_FUN_IE_S 9 -/** IO_MUX_GPIO34_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO34_FUN_DRV 0x00000003U -#define IO_MUX_GPIO34_FUN_DRV_M (IO_MUX_GPIO34_FUN_DRV_V << IO_MUX_GPIO34_FUN_DRV_S) -#define IO_MUX_GPIO34_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO34_FUN_DRV_S 10 -/** IO_MUX_GPIO34_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO34_MCU_SEL 0x00000007U -#define IO_MUX_GPIO34_MCU_SEL_M (IO_MUX_GPIO34_MCU_SEL_V << IO_MUX_GPIO34_MCU_SEL_S) -#define IO_MUX_GPIO34_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO34_MCU_SEL_S 12 -/** IO_MUX_GPIO34_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO34_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO34_FILTER_EN_M (IO_MUX_GPIO34_FILTER_EN_V << IO_MUX_GPIO34_FILTER_EN_S) -#define IO_MUX_GPIO34_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO34_FILTER_EN_S 15 - -/** IO_MUX_gpio35_REG register - * iomux control register for gpio35 - */ -#define IO_MUX_GPIO35_REG (DR_REG_IO_MUX_BASE + 0x90) -/** IO_MUX_GPIO35_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO35_MCU_OE (BIT(0)) -#define IO_MUX_GPIO35_MCU_OE_M (IO_MUX_GPIO35_MCU_OE_V << IO_MUX_GPIO35_MCU_OE_S) -#define IO_MUX_GPIO35_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO35_MCU_OE_S 0 -/** IO_MUX_GPIO35_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO35_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO35_SLP_SEL_M (IO_MUX_GPIO35_SLP_SEL_V << IO_MUX_GPIO35_SLP_SEL_S) -#define IO_MUX_GPIO35_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO35_SLP_SEL_S 1 -/** IO_MUX_GPIO35_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO35_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO35_MCU_WPD_M (IO_MUX_GPIO35_MCU_WPD_V << IO_MUX_GPIO35_MCU_WPD_S) -#define IO_MUX_GPIO35_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO35_MCU_WPD_S 2 -/** IO_MUX_GPIO35_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO35_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO35_MCU_WPU_M (IO_MUX_GPIO35_MCU_WPU_V << IO_MUX_GPIO35_MCU_WPU_S) -#define IO_MUX_GPIO35_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO35_MCU_WPU_S 3 -/** IO_MUX_GPIO35_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO35_MCU_IE (BIT(4)) -#define IO_MUX_GPIO35_MCU_IE_M (IO_MUX_GPIO35_MCU_IE_V << IO_MUX_GPIO35_MCU_IE_S) -#define IO_MUX_GPIO35_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO35_MCU_IE_S 4 -/** IO_MUX_GPIO35_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO35_MCU_DRV 0x00000003U -#define IO_MUX_GPIO35_MCU_DRV_M (IO_MUX_GPIO35_MCU_DRV_V << IO_MUX_GPIO35_MCU_DRV_S) -#define IO_MUX_GPIO35_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO35_MCU_DRV_S 5 -/** IO_MUX_GPIO35_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO35_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO35_FUN_WPD_M (IO_MUX_GPIO35_FUN_WPD_V << IO_MUX_GPIO35_FUN_WPD_S) -#define IO_MUX_GPIO35_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO35_FUN_WPD_S 7 -/** IO_MUX_GPIO35_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO35_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO35_FUN_WPU_M (IO_MUX_GPIO35_FUN_WPU_V << IO_MUX_GPIO35_FUN_WPU_S) -#define IO_MUX_GPIO35_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO35_FUN_WPU_S 8 -/** IO_MUX_GPIO35_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO35_FUN_IE (BIT(9)) -#define IO_MUX_GPIO35_FUN_IE_M (IO_MUX_GPIO35_FUN_IE_V << IO_MUX_GPIO35_FUN_IE_S) -#define IO_MUX_GPIO35_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO35_FUN_IE_S 9 -/** IO_MUX_GPIO35_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO35_FUN_DRV 0x00000003U -#define IO_MUX_GPIO35_FUN_DRV_M (IO_MUX_GPIO35_FUN_DRV_V << IO_MUX_GPIO35_FUN_DRV_S) -#define IO_MUX_GPIO35_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO35_FUN_DRV_S 10 -/** IO_MUX_GPIO35_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO35_MCU_SEL 0x00000007U -#define IO_MUX_GPIO35_MCU_SEL_M (IO_MUX_GPIO35_MCU_SEL_V << IO_MUX_GPIO35_MCU_SEL_S) -#define IO_MUX_GPIO35_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO35_MCU_SEL_S 12 -/** IO_MUX_GPIO35_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO35_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO35_FILTER_EN_M (IO_MUX_GPIO35_FILTER_EN_V << IO_MUX_GPIO35_FILTER_EN_S) -#define IO_MUX_GPIO35_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO35_FILTER_EN_S 15 - -/** IO_MUX_gpio36_REG register - * iomux control register for gpio36 - */ -#define IO_MUX_GPIO36_REG (DR_REG_IO_MUX_BASE + 0x94) -/** IO_MUX_GPIO36_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO36_MCU_OE (BIT(0)) -#define IO_MUX_GPIO36_MCU_OE_M (IO_MUX_GPIO36_MCU_OE_V << IO_MUX_GPIO36_MCU_OE_S) -#define IO_MUX_GPIO36_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO36_MCU_OE_S 0 -/** IO_MUX_GPIO36_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO36_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO36_SLP_SEL_M (IO_MUX_GPIO36_SLP_SEL_V << IO_MUX_GPIO36_SLP_SEL_S) -#define IO_MUX_GPIO36_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO36_SLP_SEL_S 1 -/** IO_MUX_GPIO36_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO36_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO36_MCU_WPD_M (IO_MUX_GPIO36_MCU_WPD_V << IO_MUX_GPIO36_MCU_WPD_S) -#define IO_MUX_GPIO36_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO36_MCU_WPD_S 2 -/** IO_MUX_GPIO36_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO36_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO36_MCU_WPU_M (IO_MUX_GPIO36_MCU_WPU_V << IO_MUX_GPIO36_MCU_WPU_S) -#define IO_MUX_GPIO36_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO36_MCU_WPU_S 3 -/** IO_MUX_GPIO36_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO36_MCU_IE (BIT(4)) -#define IO_MUX_GPIO36_MCU_IE_M (IO_MUX_GPIO36_MCU_IE_V << IO_MUX_GPIO36_MCU_IE_S) -#define IO_MUX_GPIO36_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO36_MCU_IE_S 4 -/** IO_MUX_GPIO36_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO36_MCU_DRV 0x00000003U -#define IO_MUX_GPIO36_MCU_DRV_M (IO_MUX_GPIO36_MCU_DRV_V << IO_MUX_GPIO36_MCU_DRV_S) -#define IO_MUX_GPIO36_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO36_MCU_DRV_S 5 -/** IO_MUX_GPIO36_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO36_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO36_FUN_WPD_M (IO_MUX_GPIO36_FUN_WPD_V << IO_MUX_GPIO36_FUN_WPD_S) -#define IO_MUX_GPIO36_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO36_FUN_WPD_S 7 -/** IO_MUX_GPIO36_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO36_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO36_FUN_WPU_M (IO_MUX_GPIO36_FUN_WPU_V << IO_MUX_GPIO36_FUN_WPU_S) -#define IO_MUX_GPIO36_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO36_FUN_WPU_S 8 -/** IO_MUX_GPIO36_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO36_FUN_IE (BIT(9)) -#define IO_MUX_GPIO36_FUN_IE_M (IO_MUX_GPIO36_FUN_IE_V << IO_MUX_GPIO36_FUN_IE_S) -#define IO_MUX_GPIO36_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO36_FUN_IE_S 9 -/** IO_MUX_GPIO36_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO36_FUN_DRV 0x00000003U -#define IO_MUX_GPIO36_FUN_DRV_M (IO_MUX_GPIO36_FUN_DRV_V << IO_MUX_GPIO36_FUN_DRV_S) -#define IO_MUX_GPIO36_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO36_FUN_DRV_S 10 -/** IO_MUX_GPIO36_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO36_MCU_SEL 0x00000007U -#define IO_MUX_GPIO36_MCU_SEL_M (IO_MUX_GPIO36_MCU_SEL_V << IO_MUX_GPIO36_MCU_SEL_S) -#define IO_MUX_GPIO36_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO36_MCU_SEL_S 12 -/** IO_MUX_GPIO36_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO36_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO36_FILTER_EN_M (IO_MUX_GPIO36_FILTER_EN_V << IO_MUX_GPIO36_FILTER_EN_S) -#define IO_MUX_GPIO36_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO36_FILTER_EN_S 15 - -/** IO_MUX_gpio37_REG register - * iomux control register for gpio37 - */ -#define IO_MUX_GPIO37_REG (DR_REG_IO_MUX_BASE + 0x98) -/** IO_MUX_GPIO37_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO37_MCU_OE (BIT(0)) -#define IO_MUX_GPIO37_MCU_OE_M (IO_MUX_GPIO37_MCU_OE_V << IO_MUX_GPIO37_MCU_OE_S) -#define IO_MUX_GPIO37_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO37_MCU_OE_S 0 -/** IO_MUX_GPIO37_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO37_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO37_SLP_SEL_M (IO_MUX_GPIO37_SLP_SEL_V << IO_MUX_GPIO37_SLP_SEL_S) -#define IO_MUX_GPIO37_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO37_SLP_SEL_S 1 -/** IO_MUX_GPIO37_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO37_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO37_MCU_WPD_M (IO_MUX_GPIO37_MCU_WPD_V << IO_MUX_GPIO37_MCU_WPD_S) -#define IO_MUX_GPIO37_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO37_MCU_WPD_S 2 -/** IO_MUX_GPIO37_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO37_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO37_MCU_WPU_M (IO_MUX_GPIO37_MCU_WPU_V << IO_MUX_GPIO37_MCU_WPU_S) -#define IO_MUX_GPIO37_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO37_MCU_WPU_S 3 -/** IO_MUX_GPIO37_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO37_MCU_IE (BIT(4)) -#define IO_MUX_GPIO37_MCU_IE_M (IO_MUX_GPIO37_MCU_IE_V << IO_MUX_GPIO37_MCU_IE_S) -#define IO_MUX_GPIO37_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO37_MCU_IE_S 4 -/** IO_MUX_GPIO37_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO37_MCU_DRV 0x00000003U -#define IO_MUX_GPIO37_MCU_DRV_M (IO_MUX_GPIO37_MCU_DRV_V << IO_MUX_GPIO37_MCU_DRV_S) -#define IO_MUX_GPIO37_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO37_MCU_DRV_S 5 -/** IO_MUX_GPIO37_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO37_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO37_FUN_WPD_M (IO_MUX_GPIO37_FUN_WPD_V << IO_MUX_GPIO37_FUN_WPD_S) -#define IO_MUX_GPIO37_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO37_FUN_WPD_S 7 -/** IO_MUX_GPIO37_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO37_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO37_FUN_WPU_M (IO_MUX_GPIO37_FUN_WPU_V << IO_MUX_GPIO37_FUN_WPU_S) -#define IO_MUX_GPIO37_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO37_FUN_WPU_S 8 -/** IO_MUX_GPIO37_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO37_FUN_IE (BIT(9)) -#define IO_MUX_GPIO37_FUN_IE_M (IO_MUX_GPIO37_FUN_IE_V << IO_MUX_GPIO37_FUN_IE_S) -#define IO_MUX_GPIO37_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO37_FUN_IE_S 9 -/** IO_MUX_GPIO37_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO37_FUN_DRV 0x00000003U -#define IO_MUX_GPIO37_FUN_DRV_M (IO_MUX_GPIO37_FUN_DRV_V << IO_MUX_GPIO37_FUN_DRV_S) -#define IO_MUX_GPIO37_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO37_FUN_DRV_S 10 -/** IO_MUX_GPIO37_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO37_MCU_SEL 0x00000007U -#define IO_MUX_GPIO37_MCU_SEL_M (IO_MUX_GPIO37_MCU_SEL_V << IO_MUX_GPIO37_MCU_SEL_S) -#define IO_MUX_GPIO37_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO37_MCU_SEL_S 12 -/** IO_MUX_GPIO37_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO37_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO37_FILTER_EN_M (IO_MUX_GPIO37_FILTER_EN_V << IO_MUX_GPIO37_FILTER_EN_S) -#define IO_MUX_GPIO37_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO37_FILTER_EN_S 15 - -/** IO_MUX_gpio38_REG register - * iomux control register for gpio38 - */ -#define IO_MUX_GPIO38_REG (DR_REG_IO_MUX_BASE + 0x9c) -/** IO_MUX_GPIO38_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO38_MCU_OE (BIT(0)) -#define IO_MUX_GPIO38_MCU_OE_M (IO_MUX_GPIO38_MCU_OE_V << IO_MUX_GPIO38_MCU_OE_S) -#define IO_MUX_GPIO38_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO38_MCU_OE_S 0 -/** IO_MUX_GPIO38_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO38_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO38_SLP_SEL_M (IO_MUX_GPIO38_SLP_SEL_V << IO_MUX_GPIO38_SLP_SEL_S) -#define IO_MUX_GPIO38_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO38_SLP_SEL_S 1 -/** IO_MUX_GPIO38_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO38_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO38_MCU_WPD_M (IO_MUX_GPIO38_MCU_WPD_V << IO_MUX_GPIO38_MCU_WPD_S) -#define IO_MUX_GPIO38_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO38_MCU_WPD_S 2 -/** IO_MUX_GPIO38_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO38_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO38_MCU_WPU_M (IO_MUX_GPIO38_MCU_WPU_V << IO_MUX_GPIO38_MCU_WPU_S) -#define IO_MUX_GPIO38_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO38_MCU_WPU_S 3 -/** IO_MUX_GPIO38_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO38_MCU_IE (BIT(4)) -#define IO_MUX_GPIO38_MCU_IE_M (IO_MUX_GPIO38_MCU_IE_V << IO_MUX_GPIO38_MCU_IE_S) -#define IO_MUX_GPIO38_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO38_MCU_IE_S 4 -/** IO_MUX_GPIO38_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO38_MCU_DRV 0x00000003U -#define IO_MUX_GPIO38_MCU_DRV_M (IO_MUX_GPIO38_MCU_DRV_V << IO_MUX_GPIO38_MCU_DRV_S) -#define IO_MUX_GPIO38_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO38_MCU_DRV_S 5 -/** IO_MUX_GPIO38_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO38_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO38_FUN_WPD_M (IO_MUX_GPIO38_FUN_WPD_V << IO_MUX_GPIO38_FUN_WPD_S) -#define IO_MUX_GPIO38_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO38_FUN_WPD_S 7 -/** IO_MUX_GPIO38_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO38_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO38_FUN_WPU_M (IO_MUX_GPIO38_FUN_WPU_V << IO_MUX_GPIO38_FUN_WPU_S) -#define IO_MUX_GPIO38_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO38_FUN_WPU_S 8 -/** IO_MUX_GPIO38_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO38_FUN_IE (BIT(9)) -#define IO_MUX_GPIO38_FUN_IE_M (IO_MUX_GPIO38_FUN_IE_V << IO_MUX_GPIO38_FUN_IE_S) -#define IO_MUX_GPIO38_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO38_FUN_IE_S 9 -/** IO_MUX_GPIO38_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO38_FUN_DRV 0x00000003U -#define IO_MUX_GPIO38_FUN_DRV_M (IO_MUX_GPIO38_FUN_DRV_V << IO_MUX_GPIO38_FUN_DRV_S) -#define IO_MUX_GPIO38_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO38_FUN_DRV_S 10 -/** IO_MUX_GPIO38_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO38_MCU_SEL 0x00000007U -#define IO_MUX_GPIO38_MCU_SEL_M (IO_MUX_GPIO38_MCU_SEL_V << IO_MUX_GPIO38_MCU_SEL_S) -#define IO_MUX_GPIO38_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO38_MCU_SEL_S 12 -/** IO_MUX_GPIO38_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO38_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO38_FILTER_EN_M (IO_MUX_GPIO38_FILTER_EN_V << IO_MUX_GPIO38_FILTER_EN_S) -#define IO_MUX_GPIO38_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO38_FILTER_EN_S 15 - -/** IO_MUX_gpio39_REG register - * iomux control register for gpio39 - */ -#define IO_MUX_GPIO39_REG (DR_REG_IO_MUX_BASE + 0xa0) -/** IO_MUX_GPIO39_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO39_MCU_OE (BIT(0)) -#define IO_MUX_GPIO39_MCU_OE_M (IO_MUX_GPIO39_MCU_OE_V << IO_MUX_GPIO39_MCU_OE_S) -#define IO_MUX_GPIO39_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO39_MCU_OE_S 0 -/** IO_MUX_GPIO39_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO39_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO39_SLP_SEL_M (IO_MUX_GPIO39_SLP_SEL_V << IO_MUX_GPIO39_SLP_SEL_S) -#define IO_MUX_GPIO39_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO39_SLP_SEL_S 1 -/** IO_MUX_GPIO39_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO39_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO39_MCU_WPD_M (IO_MUX_GPIO39_MCU_WPD_V << IO_MUX_GPIO39_MCU_WPD_S) -#define IO_MUX_GPIO39_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO39_MCU_WPD_S 2 -/** IO_MUX_GPIO39_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO39_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO39_MCU_WPU_M (IO_MUX_GPIO39_MCU_WPU_V << IO_MUX_GPIO39_MCU_WPU_S) -#define IO_MUX_GPIO39_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO39_MCU_WPU_S 3 -/** IO_MUX_GPIO39_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO39_MCU_IE (BIT(4)) -#define IO_MUX_GPIO39_MCU_IE_M (IO_MUX_GPIO39_MCU_IE_V << IO_MUX_GPIO39_MCU_IE_S) -#define IO_MUX_GPIO39_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO39_MCU_IE_S 4 -/** IO_MUX_GPIO39_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO39_MCU_DRV 0x00000003U -#define IO_MUX_GPIO39_MCU_DRV_M (IO_MUX_GPIO39_MCU_DRV_V << IO_MUX_GPIO39_MCU_DRV_S) -#define IO_MUX_GPIO39_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO39_MCU_DRV_S 5 -/** IO_MUX_GPIO39_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO39_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO39_FUN_WPD_M (IO_MUX_GPIO39_FUN_WPD_V << IO_MUX_GPIO39_FUN_WPD_S) -#define IO_MUX_GPIO39_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO39_FUN_WPD_S 7 -/** IO_MUX_GPIO39_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO39_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO39_FUN_WPU_M (IO_MUX_GPIO39_FUN_WPU_V << IO_MUX_GPIO39_FUN_WPU_S) -#define IO_MUX_GPIO39_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO39_FUN_WPU_S 8 -/** IO_MUX_GPIO39_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO39_FUN_IE (BIT(9)) -#define IO_MUX_GPIO39_FUN_IE_M (IO_MUX_GPIO39_FUN_IE_V << IO_MUX_GPIO39_FUN_IE_S) -#define IO_MUX_GPIO39_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO39_FUN_IE_S 9 -/** IO_MUX_GPIO39_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO39_FUN_DRV 0x00000003U -#define IO_MUX_GPIO39_FUN_DRV_M (IO_MUX_GPIO39_FUN_DRV_V << IO_MUX_GPIO39_FUN_DRV_S) -#define IO_MUX_GPIO39_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO39_FUN_DRV_S 10 -/** IO_MUX_GPIO39_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO39_MCU_SEL 0x00000007U -#define IO_MUX_GPIO39_MCU_SEL_M (IO_MUX_GPIO39_MCU_SEL_V << IO_MUX_GPIO39_MCU_SEL_S) -#define IO_MUX_GPIO39_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO39_MCU_SEL_S 12 -/** IO_MUX_GPIO39_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO39_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO39_FILTER_EN_M (IO_MUX_GPIO39_FILTER_EN_V << IO_MUX_GPIO39_FILTER_EN_S) -#define IO_MUX_GPIO39_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO39_FILTER_EN_S 15 - -/** IO_MUX_gpio40_REG register - * iomux control register for gpio40 - */ -#define IO_MUX_GPIO40_REG (DR_REG_IO_MUX_BASE + 0xa4) -/** IO_MUX_GPIO40_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO40_MCU_OE (BIT(0)) -#define IO_MUX_GPIO40_MCU_OE_M (IO_MUX_GPIO40_MCU_OE_V << IO_MUX_GPIO40_MCU_OE_S) -#define IO_MUX_GPIO40_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO40_MCU_OE_S 0 -/** IO_MUX_GPIO40_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO40_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO40_SLP_SEL_M (IO_MUX_GPIO40_SLP_SEL_V << IO_MUX_GPIO40_SLP_SEL_S) -#define IO_MUX_GPIO40_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO40_SLP_SEL_S 1 -/** IO_MUX_GPIO40_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO40_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO40_MCU_WPD_M (IO_MUX_GPIO40_MCU_WPD_V << IO_MUX_GPIO40_MCU_WPD_S) -#define IO_MUX_GPIO40_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO40_MCU_WPD_S 2 -/** IO_MUX_GPIO40_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO40_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO40_MCU_WPU_M (IO_MUX_GPIO40_MCU_WPU_V << IO_MUX_GPIO40_MCU_WPU_S) -#define IO_MUX_GPIO40_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO40_MCU_WPU_S 3 -/** IO_MUX_GPIO40_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO40_MCU_IE (BIT(4)) -#define IO_MUX_GPIO40_MCU_IE_M (IO_MUX_GPIO40_MCU_IE_V << IO_MUX_GPIO40_MCU_IE_S) -#define IO_MUX_GPIO40_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO40_MCU_IE_S 4 -/** IO_MUX_GPIO40_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO40_MCU_DRV 0x00000003U -#define IO_MUX_GPIO40_MCU_DRV_M (IO_MUX_GPIO40_MCU_DRV_V << IO_MUX_GPIO40_MCU_DRV_S) -#define IO_MUX_GPIO40_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO40_MCU_DRV_S 5 -/** IO_MUX_GPIO40_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO40_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO40_FUN_WPD_M (IO_MUX_GPIO40_FUN_WPD_V << IO_MUX_GPIO40_FUN_WPD_S) -#define IO_MUX_GPIO40_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO40_FUN_WPD_S 7 -/** IO_MUX_GPIO40_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO40_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO40_FUN_WPU_M (IO_MUX_GPIO40_FUN_WPU_V << IO_MUX_GPIO40_FUN_WPU_S) -#define IO_MUX_GPIO40_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO40_FUN_WPU_S 8 -/** IO_MUX_GPIO40_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO40_FUN_IE (BIT(9)) -#define IO_MUX_GPIO40_FUN_IE_M (IO_MUX_GPIO40_FUN_IE_V << IO_MUX_GPIO40_FUN_IE_S) -#define IO_MUX_GPIO40_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO40_FUN_IE_S 9 -/** IO_MUX_GPIO40_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO40_FUN_DRV 0x00000003U -#define IO_MUX_GPIO40_FUN_DRV_M (IO_MUX_GPIO40_FUN_DRV_V << IO_MUX_GPIO40_FUN_DRV_S) -#define IO_MUX_GPIO40_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO40_FUN_DRV_S 10 -/** IO_MUX_GPIO40_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO40_MCU_SEL 0x00000007U -#define IO_MUX_GPIO40_MCU_SEL_M (IO_MUX_GPIO40_MCU_SEL_V << IO_MUX_GPIO40_MCU_SEL_S) -#define IO_MUX_GPIO40_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO40_MCU_SEL_S 12 -/** IO_MUX_GPIO40_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO40_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO40_FILTER_EN_M (IO_MUX_GPIO40_FILTER_EN_V << IO_MUX_GPIO40_FILTER_EN_S) -#define IO_MUX_GPIO40_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO40_FILTER_EN_S 15 - -/** IO_MUX_gpio41_REG register - * iomux control register for gpio41 - */ -#define IO_MUX_GPIO41_REG (DR_REG_IO_MUX_BASE + 0xa8) -/** IO_MUX_GPIO41_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO41_MCU_OE (BIT(0)) -#define IO_MUX_GPIO41_MCU_OE_M (IO_MUX_GPIO41_MCU_OE_V << IO_MUX_GPIO41_MCU_OE_S) -#define IO_MUX_GPIO41_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO41_MCU_OE_S 0 -/** IO_MUX_GPIO41_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO41_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO41_SLP_SEL_M (IO_MUX_GPIO41_SLP_SEL_V << IO_MUX_GPIO41_SLP_SEL_S) -#define IO_MUX_GPIO41_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO41_SLP_SEL_S 1 -/** IO_MUX_GPIO41_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO41_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO41_MCU_WPD_M (IO_MUX_GPIO41_MCU_WPD_V << IO_MUX_GPIO41_MCU_WPD_S) -#define IO_MUX_GPIO41_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO41_MCU_WPD_S 2 -/** IO_MUX_GPIO41_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO41_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO41_MCU_WPU_M (IO_MUX_GPIO41_MCU_WPU_V << IO_MUX_GPIO41_MCU_WPU_S) -#define IO_MUX_GPIO41_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO41_MCU_WPU_S 3 -/** IO_MUX_GPIO41_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO41_MCU_IE (BIT(4)) -#define IO_MUX_GPIO41_MCU_IE_M (IO_MUX_GPIO41_MCU_IE_V << IO_MUX_GPIO41_MCU_IE_S) -#define IO_MUX_GPIO41_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO41_MCU_IE_S 4 -/** IO_MUX_GPIO41_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO41_MCU_DRV 0x00000003U -#define IO_MUX_GPIO41_MCU_DRV_M (IO_MUX_GPIO41_MCU_DRV_V << IO_MUX_GPIO41_MCU_DRV_S) -#define IO_MUX_GPIO41_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO41_MCU_DRV_S 5 -/** IO_MUX_GPIO41_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO41_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO41_FUN_WPD_M (IO_MUX_GPIO41_FUN_WPD_V << IO_MUX_GPIO41_FUN_WPD_S) -#define IO_MUX_GPIO41_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO41_FUN_WPD_S 7 -/** IO_MUX_GPIO41_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO41_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO41_FUN_WPU_M (IO_MUX_GPIO41_FUN_WPU_V << IO_MUX_GPIO41_FUN_WPU_S) -#define IO_MUX_GPIO41_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO41_FUN_WPU_S 8 -/** IO_MUX_GPIO41_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO41_FUN_IE (BIT(9)) -#define IO_MUX_GPIO41_FUN_IE_M (IO_MUX_GPIO41_FUN_IE_V << IO_MUX_GPIO41_FUN_IE_S) -#define IO_MUX_GPIO41_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO41_FUN_IE_S 9 -/** IO_MUX_GPIO41_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO41_FUN_DRV 0x00000003U -#define IO_MUX_GPIO41_FUN_DRV_M (IO_MUX_GPIO41_FUN_DRV_V << IO_MUX_GPIO41_FUN_DRV_S) -#define IO_MUX_GPIO41_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO41_FUN_DRV_S 10 -/** IO_MUX_GPIO41_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO41_MCU_SEL 0x00000007U -#define IO_MUX_GPIO41_MCU_SEL_M (IO_MUX_GPIO41_MCU_SEL_V << IO_MUX_GPIO41_MCU_SEL_S) -#define IO_MUX_GPIO41_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO41_MCU_SEL_S 12 -/** IO_MUX_GPIO41_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO41_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO41_FILTER_EN_M (IO_MUX_GPIO41_FILTER_EN_V << IO_MUX_GPIO41_FILTER_EN_S) -#define IO_MUX_GPIO41_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO41_FILTER_EN_S 15 - -/** IO_MUX_gpio42_REG register - * iomux control register for gpio42 - */ -#define IO_MUX_GPIO42_REG (DR_REG_IO_MUX_BASE + 0xac) -/** IO_MUX_GPIO42_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO42_MCU_OE (BIT(0)) -#define IO_MUX_GPIO42_MCU_OE_M (IO_MUX_GPIO42_MCU_OE_V << IO_MUX_GPIO42_MCU_OE_S) -#define IO_MUX_GPIO42_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO42_MCU_OE_S 0 -/** IO_MUX_GPIO42_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO42_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO42_SLP_SEL_M (IO_MUX_GPIO42_SLP_SEL_V << IO_MUX_GPIO42_SLP_SEL_S) -#define IO_MUX_GPIO42_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO42_SLP_SEL_S 1 -/** IO_MUX_GPIO42_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO42_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO42_MCU_WPD_M (IO_MUX_GPIO42_MCU_WPD_V << IO_MUX_GPIO42_MCU_WPD_S) -#define IO_MUX_GPIO42_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO42_MCU_WPD_S 2 -/** IO_MUX_GPIO42_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO42_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO42_MCU_WPU_M (IO_MUX_GPIO42_MCU_WPU_V << IO_MUX_GPIO42_MCU_WPU_S) -#define IO_MUX_GPIO42_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO42_MCU_WPU_S 3 -/** IO_MUX_GPIO42_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO42_MCU_IE (BIT(4)) -#define IO_MUX_GPIO42_MCU_IE_M (IO_MUX_GPIO42_MCU_IE_V << IO_MUX_GPIO42_MCU_IE_S) -#define IO_MUX_GPIO42_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO42_MCU_IE_S 4 -/** IO_MUX_GPIO42_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO42_MCU_DRV 0x00000003U -#define IO_MUX_GPIO42_MCU_DRV_M (IO_MUX_GPIO42_MCU_DRV_V << IO_MUX_GPIO42_MCU_DRV_S) -#define IO_MUX_GPIO42_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO42_MCU_DRV_S 5 -/** IO_MUX_GPIO42_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO42_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO42_FUN_WPD_M (IO_MUX_GPIO42_FUN_WPD_V << IO_MUX_GPIO42_FUN_WPD_S) -#define IO_MUX_GPIO42_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO42_FUN_WPD_S 7 -/** IO_MUX_GPIO42_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO42_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO42_FUN_WPU_M (IO_MUX_GPIO42_FUN_WPU_V << IO_MUX_GPIO42_FUN_WPU_S) -#define IO_MUX_GPIO42_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO42_FUN_WPU_S 8 -/** IO_MUX_GPIO42_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO42_FUN_IE (BIT(9)) -#define IO_MUX_GPIO42_FUN_IE_M (IO_MUX_GPIO42_FUN_IE_V << IO_MUX_GPIO42_FUN_IE_S) -#define IO_MUX_GPIO42_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO42_FUN_IE_S 9 -/** IO_MUX_GPIO42_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO42_FUN_DRV 0x00000003U -#define IO_MUX_GPIO42_FUN_DRV_M (IO_MUX_GPIO42_FUN_DRV_V << IO_MUX_GPIO42_FUN_DRV_S) -#define IO_MUX_GPIO42_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO42_FUN_DRV_S 10 -/** IO_MUX_GPIO42_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO42_MCU_SEL 0x00000007U -#define IO_MUX_GPIO42_MCU_SEL_M (IO_MUX_GPIO42_MCU_SEL_V << IO_MUX_GPIO42_MCU_SEL_S) -#define IO_MUX_GPIO42_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO42_MCU_SEL_S 12 -/** IO_MUX_GPIO42_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO42_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO42_FILTER_EN_M (IO_MUX_GPIO42_FILTER_EN_V << IO_MUX_GPIO42_FILTER_EN_S) -#define IO_MUX_GPIO42_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO42_FILTER_EN_S 15 - -/** IO_MUX_gpio43_REG register - * iomux control register for gpio43 - */ -#define IO_MUX_GPIO43_REG (DR_REG_IO_MUX_BASE + 0xb0) -/** IO_MUX_GPIO43_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO43_MCU_OE (BIT(0)) -#define IO_MUX_GPIO43_MCU_OE_M (IO_MUX_GPIO43_MCU_OE_V << IO_MUX_GPIO43_MCU_OE_S) -#define IO_MUX_GPIO43_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO43_MCU_OE_S 0 -/** IO_MUX_GPIO43_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO43_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO43_SLP_SEL_M (IO_MUX_GPIO43_SLP_SEL_V << IO_MUX_GPIO43_SLP_SEL_S) -#define IO_MUX_GPIO43_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO43_SLP_SEL_S 1 -/** IO_MUX_GPIO43_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO43_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO43_MCU_WPD_M (IO_MUX_GPIO43_MCU_WPD_V << IO_MUX_GPIO43_MCU_WPD_S) -#define IO_MUX_GPIO43_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO43_MCU_WPD_S 2 -/** IO_MUX_GPIO43_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO43_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO43_MCU_WPU_M (IO_MUX_GPIO43_MCU_WPU_V << IO_MUX_GPIO43_MCU_WPU_S) -#define IO_MUX_GPIO43_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO43_MCU_WPU_S 3 -/** IO_MUX_GPIO43_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO43_MCU_IE (BIT(4)) -#define IO_MUX_GPIO43_MCU_IE_M (IO_MUX_GPIO43_MCU_IE_V << IO_MUX_GPIO43_MCU_IE_S) -#define IO_MUX_GPIO43_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO43_MCU_IE_S 4 -/** IO_MUX_GPIO43_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO43_MCU_DRV 0x00000003U -#define IO_MUX_GPIO43_MCU_DRV_M (IO_MUX_GPIO43_MCU_DRV_V << IO_MUX_GPIO43_MCU_DRV_S) -#define IO_MUX_GPIO43_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO43_MCU_DRV_S 5 -/** IO_MUX_GPIO43_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO43_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO43_FUN_WPD_M (IO_MUX_GPIO43_FUN_WPD_V << IO_MUX_GPIO43_FUN_WPD_S) -#define IO_MUX_GPIO43_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO43_FUN_WPD_S 7 -/** IO_MUX_GPIO43_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO43_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO43_FUN_WPU_M (IO_MUX_GPIO43_FUN_WPU_V << IO_MUX_GPIO43_FUN_WPU_S) -#define IO_MUX_GPIO43_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO43_FUN_WPU_S 8 -/** IO_MUX_GPIO43_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO43_FUN_IE (BIT(9)) -#define IO_MUX_GPIO43_FUN_IE_M (IO_MUX_GPIO43_FUN_IE_V << IO_MUX_GPIO43_FUN_IE_S) -#define IO_MUX_GPIO43_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO43_FUN_IE_S 9 -/** IO_MUX_GPIO43_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO43_FUN_DRV 0x00000003U -#define IO_MUX_GPIO43_FUN_DRV_M (IO_MUX_GPIO43_FUN_DRV_V << IO_MUX_GPIO43_FUN_DRV_S) -#define IO_MUX_GPIO43_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO43_FUN_DRV_S 10 -/** IO_MUX_GPIO43_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO43_MCU_SEL 0x00000007U -#define IO_MUX_GPIO43_MCU_SEL_M (IO_MUX_GPIO43_MCU_SEL_V << IO_MUX_GPIO43_MCU_SEL_S) -#define IO_MUX_GPIO43_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO43_MCU_SEL_S 12 -/** IO_MUX_GPIO43_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO43_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO43_FILTER_EN_M (IO_MUX_GPIO43_FILTER_EN_V << IO_MUX_GPIO43_FILTER_EN_S) -#define IO_MUX_GPIO43_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO43_FILTER_EN_S 15 - -/** IO_MUX_gpio44_REG register - * iomux control register for gpio44 - */ -#define IO_MUX_GPIO44_REG (DR_REG_IO_MUX_BASE + 0xb4) -/** IO_MUX_GPIO44_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO44_MCU_OE (BIT(0)) -#define IO_MUX_GPIO44_MCU_OE_M (IO_MUX_GPIO44_MCU_OE_V << IO_MUX_GPIO44_MCU_OE_S) -#define IO_MUX_GPIO44_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO44_MCU_OE_S 0 -/** IO_MUX_GPIO44_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO44_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO44_SLP_SEL_M (IO_MUX_GPIO44_SLP_SEL_V << IO_MUX_GPIO44_SLP_SEL_S) -#define IO_MUX_GPIO44_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO44_SLP_SEL_S 1 -/** IO_MUX_GPIO44_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO44_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO44_MCU_WPD_M (IO_MUX_GPIO44_MCU_WPD_V << IO_MUX_GPIO44_MCU_WPD_S) -#define IO_MUX_GPIO44_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO44_MCU_WPD_S 2 -/** IO_MUX_GPIO44_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO44_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO44_MCU_WPU_M (IO_MUX_GPIO44_MCU_WPU_V << IO_MUX_GPIO44_MCU_WPU_S) -#define IO_MUX_GPIO44_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO44_MCU_WPU_S 3 -/** IO_MUX_GPIO44_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO44_MCU_IE (BIT(4)) -#define IO_MUX_GPIO44_MCU_IE_M (IO_MUX_GPIO44_MCU_IE_V << IO_MUX_GPIO44_MCU_IE_S) -#define IO_MUX_GPIO44_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO44_MCU_IE_S 4 -/** IO_MUX_GPIO44_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO44_MCU_DRV 0x00000003U -#define IO_MUX_GPIO44_MCU_DRV_M (IO_MUX_GPIO44_MCU_DRV_V << IO_MUX_GPIO44_MCU_DRV_S) -#define IO_MUX_GPIO44_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO44_MCU_DRV_S 5 -/** IO_MUX_GPIO44_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO44_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO44_FUN_WPD_M (IO_MUX_GPIO44_FUN_WPD_V << IO_MUX_GPIO44_FUN_WPD_S) -#define IO_MUX_GPIO44_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO44_FUN_WPD_S 7 -/** IO_MUX_GPIO44_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO44_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO44_FUN_WPU_M (IO_MUX_GPIO44_FUN_WPU_V << IO_MUX_GPIO44_FUN_WPU_S) -#define IO_MUX_GPIO44_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO44_FUN_WPU_S 8 -/** IO_MUX_GPIO44_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO44_FUN_IE (BIT(9)) -#define IO_MUX_GPIO44_FUN_IE_M (IO_MUX_GPIO44_FUN_IE_V << IO_MUX_GPIO44_FUN_IE_S) -#define IO_MUX_GPIO44_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO44_FUN_IE_S 9 -/** IO_MUX_GPIO44_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO44_FUN_DRV 0x00000003U -#define IO_MUX_GPIO44_FUN_DRV_M (IO_MUX_GPIO44_FUN_DRV_V << IO_MUX_GPIO44_FUN_DRV_S) -#define IO_MUX_GPIO44_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO44_FUN_DRV_S 10 -/** IO_MUX_GPIO44_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO44_MCU_SEL 0x00000007U -#define IO_MUX_GPIO44_MCU_SEL_M (IO_MUX_GPIO44_MCU_SEL_V << IO_MUX_GPIO44_MCU_SEL_S) -#define IO_MUX_GPIO44_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO44_MCU_SEL_S 12 -/** IO_MUX_GPIO44_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO44_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO44_FILTER_EN_M (IO_MUX_GPIO44_FILTER_EN_V << IO_MUX_GPIO44_FILTER_EN_S) -#define IO_MUX_GPIO44_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO44_FILTER_EN_S 15 - -/** IO_MUX_gpio45_REG register - * iomux control register for gpio45 - */ -#define IO_MUX_GPIO45_REG (DR_REG_IO_MUX_BASE + 0xb8) -/** IO_MUX_GPIO45_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO45_MCU_OE (BIT(0)) -#define IO_MUX_GPIO45_MCU_OE_M (IO_MUX_GPIO45_MCU_OE_V << IO_MUX_GPIO45_MCU_OE_S) -#define IO_MUX_GPIO45_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO45_MCU_OE_S 0 -/** IO_MUX_GPIO45_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO45_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO45_SLP_SEL_M (IO_MUX_GPIO45_SLP_SEL_V << IO_MUX_GPIO45_SLP_SEL_S) -#define IO_MUX_GPIO45_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO45_SLP_SEL_S 1 -/** IO_MUX_GPIO45_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO45_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO45_MCU_WPD_M (IO_MUX_GPIO45_MCU_WPD_V << IO_MUX_GPIO45_MCU_WPD_S) -#define IO_MUX_GPIO45_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO45_MCU_WPD_S 2 -/** IO_MUX_GPIO45_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO45_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO45_MCU_WPU_M (IO_MUX_GPIO45_MCU_WPU_V << IO_MUX_GPIO45_MCU_WPU_S) -#define IO_MUX_GPIO45_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO45_MCU_WPU_S 3 -/** IO_MUX_GPIO45_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO45_MCU_IE (BIT(4)) -#define IO_MUX_GPIO45_MCU_IE_M (IO_MUX_GPIO45_MCU_IE_V << IO_MUX_GPIO45_MCU_IE_S) -#define IO_MUX_GPIO45_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO45_MCU_IE_S 4 -/** IO_MUX_GPIO45_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO45_MCU_DRV 0x00000003U -#define IO_MUX_GPIO45_MCU_DRV_M (IO_MUX_GPIO45_MCU_DRV_V << IO_MUX_GPIO45_MCU_DRV_S) -#define IO_MUX_GPIO45_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO45_MCU_DRV_S 5 -/** IO_MUX_GPIO45_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO45_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO45_FUN_WPD_M (IO_MUX_GPIO45_FUN_WPD_V << IO_MUX_GPIO45_FUN_WPD_S) -#define IO_MUX_GPIO45_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO45_FUN_WPD_S 7 -/** IO_MUX_GPIO45_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO45_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO45_FUN_WPU_M (IO_MUX_GPIO45_FUN_WPU_V << IO_MUX_GPIO45_FUN_WPU_S) -#define IO_MUX_GPIO45_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO45_FUN_WPU_S 8 -/** IO_MUX_GPIO45_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO45_FUN_IE (BIT(9)) -#define IO_MUX_GPIO45_FUN_IE_M (IO_MUX_GPIO45_FUN_IE_V << IO_MUX_GPIO45_FUN_IE_S) -#define IO_MUX_GPIO45_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO45_FUN_IE_S 9 -/** IO_MUX_GPIO45_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO45_FUN_DRV 0x00000003U -#define IO_MUX_GPIO45_FUN_DRV_M (IO_MUX_GPIO45_FUN_DRV_V << IO_MUX_GPIO45_FUN_DRV_S) -#define IO_MUX_GPIO45_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO45_FUN_DRV_S 10 -/** IO_MUX_GPIO45_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO45_MCU_SEL 0x00000007U -#define IO_MUX_GPIO45_MCU_SEL_M (IO_MUX_GPIO45_MCU_SEL_V << IO_MUX_GPIO45_MCU_SEL_S) -#define IO_MUX_GPIO45_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO45_MCU_SEL_S 12 -/** IO_MUX_GPIO45_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO45_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO45_FILTER_EN_M (IO_MUX_GPIO45_FILTER_EN_V << IO_MUX_GPIO45_FILTER_EN_S) -#define IO_MUX_GPIO45_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO45_FILTER_EN_S 15 - -/** IO_MUX_gpio46_REG register - * iomux control register for gpio46 - */ -#define IO_MUX_GPIO46_REG (DR_REG_IO_MUX_BASE + 0xbc) -/** IO_MUX_GPIO46_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO46_MCU_OE (BIT(0)) -#define IO_MUX_GPIO46_MCU_OE_M (IO_MUX_GPIO46_MCU_OE_V << IO_MUX_GPIO46_MCU_OE_S) -#define IO_MUX_GPIO46_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO46_MCU_OE_S 0 -/** IO_MUX_GPIO46_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO46_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO46_SLP_SEL_M (IO_MUX_GPIO46_SLP_SEL_V << IO_MUX_GPIO46_SLP_SEL_S) -#define IO_MUX_GPIO46_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO46_SLP_SEL_S 1 -/** IO_MUX_GPIO46_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO46_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO46_MCU_WPD_M (IO_MUX_GPIO46_MCU_WPD_V << IO_MUX_GPIO46_MCU_WPD_S) -#define IO_MUX_GPIO46_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO46_MCU_WPD_S 2 -/** IO_MUX_GPIO46_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO46_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO46_MCU_WPU_M (IO_MUX_GPIO46_MCU_WPU_V << IO_MUX_GPIO46_MCU_WPU_S) -#define IO_MUX_GPIO46_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO46_MCU_WPU_S 3 -/** IO_MUX_GPIO46_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO46_MCU_IE (BIT(4)) -#define IO_MUX_GPIO46_MCU_IE_M (IO_MUX_GPIO46_MCU_IE_V << IO_MUX_GPIO46_MCU_IE_S) -#define IO_MUX_GPIO46_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO46_MCU_IE_S 4 -/** IO_MUX_GPIO46_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO46_MCU_DRV 0x00000003U -#define IO_MUX_GPIO46_MCU_DRV_M (IO_MUX_GPIO46_MCU_DRV_V << IO_MUX_GPIO46_MCU_DRV_S) -#define IO_MUX_GPIO46_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO46_MCU_DRV_S 5 -/** IO_MUX_GPIO46_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO46_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO46_FUN_WPD_M (IO_MUX_GPIO46_FUN_WPD_V << IO_MUX_GPIO46_FUN_WPD_S) -#define IO_MUX_GPIO46_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO46_FUN_WPD_S 7 -/** IO_MUX_GPIO46_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO46_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO46_FUN_WPU_M (IO_MUX_GPIO46_FUN_WPU_V << IO_MUX_GPIO46_FUN_WPU_S) -#define IO_MUX_GPIO46_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO46_FUN_WPU_S 8 -/** IO_MUX_GPIO46_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO46_FUN_IE (BIT(9)) -#define IO_MUX_GPIO46_FUN_IE_M (IO_MUX_GPIO46_FUN_IE_V << IO_MUX_GPIO46_FUN_IE_S) -#define IO_MUX_GPIO46_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO46_FUN_IE_S 9 -/** IO_MUX_GPIO46_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO46_FUN_DRV 0x00000003U -#define IO_MUX_GPIO46_FUN_DRV_M (IO_MUX_GPIO46_FUN_DRV_V << IO_MUX_GPIO46_FUN_DRV_S) -#define IO_MUX_GPIO46_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO46_FUN_DRV_S 10 -/** IO_MUX_GPIO46_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO46_MCU_SEL 0x00000007U -#define IO_MUX_GPIO46_MCU_SEL_M (IO_MUX_GPIO46_MCU_SEL_V << IO_MUX_GPIO46_MCU_SEL_S) -#define IO_MUX_GPIO46_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO46_MCU_SEL_S 12 -/** IO_MUX_GPIO46_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO46_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO46_FILTER_EN_M (IO_MUX_GPIO46_FILTER_EN_V << IO_MUX_GPIO46_FILTER_EN_S) -#define IO_MUX_GPIO46_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO46_FILTER_EN_S 15 - -/** IO_MUX_gpio47_REG register - * iomux control register for gpio47 - */ -#define IO_MUX_GPIO47_REG (DR_REG_IO_MUX_BASE + 0xc0) -/** IO_MUX_GPIO47_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO47_MCU_OE (BIT(0)) -#define IO_MUX_GPIO47_MCU_OE_M (IO_MUX_GPIO47_MCU_OE_V << IO_MUX_GPIO47_MCU_OE_S) -#define IO_MUX_GPIO47_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO47_MCU_OE_S 0 -/** IO_MUX_GPIO47_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO47_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO47_SLP_SEL_M (IO_MUX_GPIO47_SLP_SEL_V << IO_MUX_GPIO47_SLP_SEL_S) -#define IO_MUX_GPIO47_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO47_SLP_SEL_S 1 -/** IO_MUX_GPIO47_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO47_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO47_MCU_WPD_M (IO_MUX_GPIO47_MCU_WPD_V << IO_MUX_GPIO47_MCU_WPD_S) -#define IO_MUX_GPIO47_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO47_MCU_WPD_S 2 -/** IO_MUX_GPIO47_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO47_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO47_MCU_WPU_M (IO_MUX_GPIO47_MCU_WPU_V << IO_MUX_GPIO47_MCU_WPU_S) -#define IO_MUX_GPIO47_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO47_MCU_WPU_S 3 -/** IO_MUX_GPIO47_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO47_MCU_IE (BIT(4)) -#define IO_MUX_GPIO47_MCU_IE_M (IO_MUX_GPIO47_MCU_IE_V << IO_MUX_GPIO47_MCU_IE_S) -#define IO_MUX_GPIO47_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO47_MCU_IE_S 4 -/** IO_MUX_GPIO47_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO47_MCU_DRV 0x00000003U -#define IO_MUX_GPIO47_MCU_DRV_M (IO_MUX_GPIO47_MCU_DRV_V << IO_MUX_GPIO47_MCU_DRV_S) -#define IO_MUX_GPIO47_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO47_MCU_DRV_S 5 -/** IO_MUX_GPIO47_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO47_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO47_FUN_WPD_M (IO_MUX_GPIO47_FUN_WPD_V << IO_MUX_GPIO47_FUN_WPD_S) -#define IO_MUX_GPIO47_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO47_FUN_WPD_S 7 -/** IO_MUX_GPIO47_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO47_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO47_FUN_WPU_M (IO_MUX_GPIO47_FUN_WPU_V << IO_MUX_GPIO47_FUN_WPU_S) -#define IO_MUX_GPIO47_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO47_FUN_WPU_S 8 -/** IO_MUX_GPIO47_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO47_FUN_IE (BIT(9)) -#define IO_MUX_GPIO47_FUN_IE_M (IO_MUX_GPIO47_FUN_IE_V << IO_MUX_GPIO47_FUN_IE_S) -#define IO_MUX_GPIO47_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO47_FUN_IE_S 9 -/** IO_MUX_GPIO47_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO47_FUN_DRV 0x00000003U -#define IO_MUX_GPIO47_FUN_DRV_M (IO_MUX_GPIO47_FUN_DRV_V << IO_MUX_GPIO47_FUN_DRV_S) -#define IO_MUX_GPIO47_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO47_FUN_DRV_S 10 -/** IO_MUX_GPIO47_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO47_MCU_SEL 0x00000007U -#define IO_MUX_GPIO47_MCU_SEL_M (IO_MUX_GPIO47_MCU_SEL_V << IO_MUX_GPIO47_MCU_SEL_S) -#define IO_MUX_GPIO47_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO47_MCU_SEL_S 12 -/** IO_MUX_GPIO47_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO47_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO47_FILTER_EN_M (IO_MUX_GPIO47_FILTER_EN_V << IO_MUX_GPIO47_FILTER_EN_S) -#define IO_MUX_GPIO47_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO47_FILTER_EN_S 15 - -/** IO_MUX_gpio48_REG register - * iomux control register for gpio48 - */ -#define IO_MUX_GPIO48_REG (DR_REG_IO_MUX_BASE + 0xc4) -/** IO_MUX_GPIO48_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO48_MCU_OE (BIT(0)) -#define IO_MUX_GPIO48_MCU_OE_M (IO_MUX_GPIO48_MCU_OE_V << IO_MUX_GPIO48_MCU_OE_S) -#define IO_MUX_GPIO48_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO48_MCU_OE_S 0 -/** IO_MUX_GPIO48_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO48_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO48_SLP_SEL_M (IO_MUX_GPIO48_SLP_SEL_V << IO_MUX_GPIO48_SLP_SEL_S) -#define IO_MUX_GPIO48_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO48_SLP_SEL_S 1 -/** IO_MUX_GPIO48_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO48_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO48_MCU_WPD_M (IO_MUX_GPIO48_MCU_WPD_V << IO_MUX_GPIO48_MCU_WPD_S) -#define IO_MUX_GPIO48_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO48_MCU_WPD_S 2 -/** IO_MUX_GPIO48_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO48_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO48_MCU_WPU_M (IO_MUX_GPIO48_MCU_WPU_V << IO_MUX_GPIO48_MCU_WPU_S) -#define IO_MUX_GPIO48_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO48_MCU_WPU_S 3 -/** IO_MUX_GPIO48_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO48_MCU_IE (BIT(4)) -#define IO_MUX_GPIO48_MCU_IE_M (IO_MUX_GPIO48_MCU_IE_V << IO_MUX_GPIO48_MCU_IE_S) -#define IO_MUX_GPIO48_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO48_MCU_IE_S 4 -/** IO_MUX_GPIO48_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO48_MCU_DRV 0x00000003U -#define IO_MUX_GPIO48_MCU_DRV_M (IO_MUX_GPIO48_MCU_DRV_V << IO_MUX_GPIO48_MCU_DRV_S) -#define IO_MUX_GPIO48_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO48_MCU_DRV_S 5 -/** IO_MUX_GPIO48_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO48_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO48_FUN_WPD_M (IO_MUX_GPIO48_FUN_WPD_V << IO_MUX_GPIO48_FUN_WPD_S) -#define IO_MUX_GPIO48_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO48_FUN_WPD_S 7 -/** IO_MUX_GPIO48_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO48_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO48_FUN_WPU_M (IO_MUX_GPIO48_FUN_WPU_V << IO_MUX_GPIO48_FUN_WPU_S) -#define IO_MUX_GPIO48_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO48_FUN_WPU_S 8 -/** IO_MUX_GPIO48_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO48_FUN_IE (BIT(9)) -#define IO_MUX_GPIO48_FUN_IE_M (IO_MUX_GPIO48_FUN_IE_V << IO_MUX_GPIO48_FUN_IE_S) -#define IO_MUX_GPIO48_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO48_FUN_IE_S 9 -/** IO_MUX_GPIO48_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO48_FUN_DRV 0x00000003U -#define IO_MUX_GPIO48_FUN_DRV_M (IO_MUX_GPIO48_FUN_DRV_V << IO_MUX_GPIO48_FUN_DRV_S) -#define IO_MUX_GPIO48_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO48_FUN_DRV_S 10 -/** IO_MUX_GPIO48_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO48_MCU_SEL 0x00000007U -#define IO_MUX_GPIO48_MCU_SEL_M (IO_MUX_GPIO48_MCU_SEL_V << IO_MUX_GPIO48_MCU_SEL_S) -#define IO_MUX_GPIO48_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO48_MCU_SEL_S 12 -/** IO_MUX_GPIO48_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO48_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO48_FILTER_EN_M (IO_MUX_GPIO48_FILTER_EN_V << IO_MUX_GPIO48_FILTER_EN_S) -#define IO_MUX_GPIO48_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO48_FILTER_EN_S 15 - -/** IO_MUX_gpio49_REG register - * iomux control register for gpio49 - */ -#define IO_MUX_GPIO49_REG (DR_REG_IO_MUX_BASE + 0xc8) -/** IO_MUX_GPIO49_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO49_MCU_OE (BIT(0)) -#define IO_MUX_GPIO49_MCU_OE_M (IO_MUX_GPIO49_MCU_OE_V << IO_MUX_GPIO49_MCU_OE_S) -#define IO_MUX_GPIO49_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO49_MCU_OE_S 0 -/** IO_MUX_GPIO49_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO49_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO49_SLP_SEL_M (IO_MUX_GPIO49_SLP_SEL_V << IO_MUX_GPIO49_SLP_SEL_S) -#define IO_MUX_GPIO49_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO49_SLP_SEL_S 1 -/** IO_MUX_GPIO49_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO49_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO49_MCU_WPD_M (IO_MUX_GPIO49_MCU_WPD_V << IO_MUX_GPIO49_MCU_WPD_S) -#define IO_MUX_GPIO49_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO49_MCU_WPD_S 2 -/** IO_MUX_GPIO49_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO49_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO49_MCU_WPU_M (IO_MUX_GPIO49_MCU_WPU_V << IO_MUX_GPIO49_MCU_WPU_S) -#define IO_MUX_GPIO49_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO49_MCU_WPU_S 3 -/** IO_MUX_GPIO49_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO49_MCU_IE (BIT(4)) -#define IO_MUX_GPIO49_MCU_IE_M (IO_MUX_GPIO49_MCU_IE_V << IO_MUX_GPIO49_MCU_IE_S) -#define IO_MUX_GPIO49_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO49_MCU_IE_S 4 -/** IO_MUX_GPIO49_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO49_MCU_DRV 0x00000003U -#define IO_MUX_GPIO49_MCU_DRV_M (IO_MUX_GPIO49_MCU_DRV_V << IO_MUX_GPIO49_MCU_DRV_S) -#define IO_MUX_GPIO49_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO49_MCU_DRV_S 5 -/** IO_MUX_GPIO49_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO49_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO49_FUN_WPD_M (IO_MUX_GPIO49_FUN_WPD_V << IO_MUX_GPIO49_FUN_WPD_S) -#define IO_MUX_GPIO49_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO49_FUN_WPD_S 7 -/** IO_MUX_GPIO49_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO49_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO49_FUN_WPU_M (IO_MUX_GPIO49_FUN_WPU_V << IO_MUX_GPIO49_FUN_WPU_S) -#define IO_MUX_GPIO49_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO49_FUN_WPU_S 8 -/** IO_MUX_GPIO49_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO49_FUN_IE (BIT(9)) -#define IO_MUX_GPIO49_FUN_IE_M (IO_MUX_GPIO49_FUN_IE_V << IO_MUX_GPIO49_FUN_IE_S) -#define IO_MUX_GPIO49_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO49_FUN_IE_S 9 -/** IO_MUX_GPIO49_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO49_FUN_DRV 0x00000003U -#define IO_MUX_GPIO49_FUN_DRV_M (IO_MUX_GPIO49_FUN_DRV_V << IO_MUX_GPIO49_FUN_DRV_S) -#define IO_MUX_GPIO49_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO49_FUN_DRV_S 10 -/** IO_MUX_GPIO49_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO49_MCU_SEL 0x00000007U -#define IO_MUX_GPIO49_MCU_SEL_M (IO_MUX_GPIO49_MCU_SEL_V << IO_MUX_GPIO49_MCU_SEL_S) -#define IO_MUX_GPIO49_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO49_MCU_SEL_S 12 -/** IO_MUX_GPIO49_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO49_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO49_FILTER_EN_M (IO_MUX_GPIO49_FILTER_EN_V << IO_MUX_GPIO49_FILTER_EN_S) -#define IO_MUX_GPIO49_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO49_FILTER_EN_S 15 - -/** IO_MUX_gpio50_REG register - * iomux control register for gpio50 - */ -#define IO_MUX_GPIO50_REG (DR_REG_IO_MUX_BASE + 0xcc) -/** IO_MUX_GPIO50_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO50_MCU_OE (BIT(0)) -#define IO_MUX_GPIO50_MCU_OE_M (IO_MUX_GPIO50_MCU_OE_V << IO_MUX_GPIO50_MCU_OE_S) -#define IO_MUX_GPIO50_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO50_MCU_OE_S 0 -/** IO_MUX_GPIO50_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO50_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO50_SLP_SEL_M (IO_MUX_GPIO50_SLP_SEL_V << IO_MUX_GPIO50_SLP_SEL_S) -#define IO_MUX_GPIO50_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO50_SLP_SEL_S 1 -/** IO_MUX_GPIO50_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO50_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO50_MCU_WPD_M (IO_MUX_GPIO50_MCU_WPD_V << IO_MUX_GPIO50_MCU_WPD_S) -#define IO_MUX_GPIO50_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO50_MCU_WPD_S 2 -/** IO_MUX_GPIO50_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO50_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO50_MCU_WPU_M (IO_MUX_GPIO50_MCU_WPU_V << IO_MUX_GPIO50_MCU_WPU_S) -#define IO_MUX_GPIO50_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO50_MCU_WPU_S 3 -/** IO_MUX_GPIO50_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO50_MCU_IE (BIT(4)) -#define IO_MUX_GPIO50_MCU_IE_M (IO_MUX_GPIO50_MCU_IE_V << IO_MUX_GPIO50_MCU_IE_S) -#define IO_MUX_GPIO50_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO50_MCU_IE_S 4 -/** IO_MUX_GPIO50_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO50_MCU_DRV 0x00000003U -#define IO_MUX_GPIO50_MCU_DRV_M (IO_MUX_GPIO50_MCU_DRV_V << IO_MUX_GPIO50_MCU_DRV_S) -#define IO_MUX_GPIO50_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO50_MCU_DRV_S 5 -/** IO_MUX_GPIO50_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO50_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO50_FUN_WPD_M (IO_MUX_GPIO50_FUN_WPD_V << IO_MUX_GPIO50_FUN_WPD_S) -#define IO_MUX_GPIO50_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO50_FUN_WPD_S 7 -/** IO_MUX_GPIO50_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO50_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO50_FUN_WPU_M (IO_MUX_GPIO50_FUN_WPU_V << IO_MUX_GPIO50_FUN_WPU_S) -#define IO_MUX_GPIO50_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO50_FUN_WPU_S 8 -/** IO_MUX_GPIO50_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO50_FUN_IE (BIT(9)) -#define IO_MUX_GPIO50_FUN_IE_M (IO_MUX_GPIO50_FUN_IE_V << IO_MUX_GPIO50_FUN_IE_S) -#define IO_MUX_GPIO50_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO50_FUN_IE_S 9 -/** IO_MUX_GPIO50_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO50_FUN_DRV 0x00000003U -#define IO_MUX_GPIO50_FUN_DRV_M (IO_MUX_GPIO50_FUN_DRV_V << IO_MUX_GPIO50_FUN_DRV_S) -#define IO_MUX_GPIO50_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO50_FUN_DRV_S 10 -/** IO_MUX_GPIO50_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO50_MCU_SEL 0x00000007U -#define IO_MUX_GPIO50_MCU_SEL_M (IO_MUX_GPIO50_MCU_SEL_V << IO_MUX_GPIO50_MCU_SEL_S) -#define IO_MUX_GPIO50_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO50_MCU_SEL_S 12 -/** IO_MUX_GPIO50_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO50_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO50_FILTER_EN_M (IO_MUX_GPIO50_FILTER_EN_V << IO_MUX_GPIO50_FILTER_EN_S) -#define IO_MUX_GPIO50_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO50_FILTER_EN_S 15 - -/** IO_MUX_gpio51_REG register - * iomux control register for gpio51 - */ -#define IO_MUX_GPIO51_REG (DR_REG_IO_MUX_BASE + 0xd0) -/** IO_MUX_GPIO51_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO51_MCU_OE (BIT(0)) -#define IO_MUX_GPIO51_MCU_OE_M (IO_MUX_GPIO51_MCU_OE_V << IO_MUX_GPIO51_MCU_OE_S) -#define IO_MUX_GPIO51_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO51_MCU_OE_S 0 -/** IO_MUX_GPIO51_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO51_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO51_SLP_SEL_M (IO_MUX_GPIO51_SLP_SEL_V << IO_MUX_GPIO51_SLP_SEL_S) -#define IO_MUX_GPIO51_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO51_SLP_SEL_S 1 -/** IO_MUX_GPIO51_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO51_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO51_MCU_WPD_M (IO_MUX_GPIO51_MCU_WPD_V << IO_MUX_GPIO51_MCU_WPD_S) -#define IO_MUX_GPIO51_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO51_MCU_WPD_S 2 -/** IO_MUX_GPIO51_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO51_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO51_MCU_WPU_M (IO_MUX_GPIO51_MCU_WPU_V << IO_MUX_GPIO51_MCU_WPU_S) -#define IO_MUX_GPIO51_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO51_MCU_WPU_S 3 -/** IO_MUX_GPIO51_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO51_MCU_IE (BIT(4)) -#define IO_MUX_GPIO51_MCU_IE_M (IO_MUX_GPIO51_MCU_IE_V << IO_MUX_GPIO51_MCU_IE_S) -#define IO_MUX_GPIO51_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO51_MCU_IE_S 4 -/** IO_MUX_GPIO51_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO51_MCU_DRV 0x00000003U -#define IO_MUX_GPIO51_MCU_DRV_M (IO_MUX_GPIO51_MCU_DRV_V << IO_MUX_GPIO51_MCU_DRV_S) -#define IO_MUX_GPIO51_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO51_MCU_DRV_S 5 -/** IO_MUX_GPIO51_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO51_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO51_FUN_WPD_M (IO_MUX_GPIO51_FUN_WPD_V << IO_MUX_GPIO51_FUN_WPD_S) -#define IO_MUX_GPIO51_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO51_FUN_WPD_S 7 -/** IO_MUX_GPIO51_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO51_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO51_FUN_WPU_M (IO_MUX_GPIO51_FUN_WPU_V << IO_MUX_GPIO51_FUN_WPU_S) -#define IO_MUX_GPIO51_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO51_FUN_WPU_S 8 -/** IO_MUX_GPIO51_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO51_FUN_IE (BIT(9)) -#define IO_MUX_GPIO51_FUN_IE_M (IO_MUX_GPIO51_FUN_IE_V << IO_MUX_GPIO51_FUN_IE_S) -#define IO_MUX_GPIO51_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO51_FUN_IE_S 9 -/** IO_MUX_GPIO51_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO51_FUN_DRV 0x00000003U -#define IO_MUX_GPIO51_FUN_DRV_M (IO_MUX_GPIO51_FUN_DRV_V << IO_MUX_GPIO51_FUN_DRV_S) -#define IO_MUX_GPIO51_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO51_FUN_DRV_S 10 -/** IO_MUX_GPIO51_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO51_MCU_SEL 0x00000007U -#define IO_MUX_GPIO51_MCU_SEL_M (IO_MUX_GPIO51_MCU_SEL_V << IO_MUX_GPIO51_MCU_SEL_S) -#define IO_MUX_GPIO51_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO51_MCU_SEL_S 12 -/** IO_MUX_GPIO51_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO51_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO51_FILTER_EN_M (IO_MUX_GPIO51_FILTER_EN_V << IO_MUX_GPIO51_FILTER_EN_S) -#define IO_MUX_GPIO51_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO51_FILTER_EN_S 15 - -/** IO_MUX_gpio52_REG register - * iomux control register for gpio52 - */ -#define IO_MUX_GPIO52_REG (DR_REG_IO_MUX_BASE + 0xd4) -/** IO_MUX_GPIO52_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO52_MCU_OE (BIT(0)) -#define IO_MUX_GPIO52_MCU_OE_M (IO_MUX_GPIO52_MCU_OE_V << IO_MUX_GPIO52_MCU_OE_S) -#define IO_MUX_GPIO52_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO52_MCU_OE_S 0 -/** IO_MUX_GPIO52_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO52_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO52_SLP_SEL_M (IO_MUX_GPIO52_SLP_SEL_V << IO_MUX_GPIO52_SLP_SEL_S) -#define IO_MUX_GPIO52_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO52_SLP_SEL_S 1 -/** IO_MUX_GPIO52_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO52_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO52_MCU_WPD_M (IO_MUX_GPIO52_MCU_WPD_V << IO_MUX_GPIO52_MCU_WPD_S) -#define IO_MUX_GPIO52_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO52_MCU_WPD_S 2 -/** IO_MUX_GPIO52_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO52_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO52_MCU_WPU_M (IO_MUX_GPIO52_MCU_WPU_V << IO_MUX_GPIO52_MCU_WPU_S) -#define IO_MUX_GPIO52_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO52_MCU_WPU_S 3 -/** IO_MUX_GPIO52_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO52_MCU_IE (BIT(4)) -#define IO_MUX_GPIO52_MCU_IE_M (IO_MUX_GPIO52_MCU_IE_V << IO_MUX_GPIO52_MCU_IE_S) -#define IO_MUX_GPIO52_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO52_MCU_IE_S 4 -/** IO_MUX_GPIO52_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO52_MCU_DRV 0x00000003U -#define IO_MUX_GPIO52_MCU_DRV_M (IO_MUX_GPIO52_MCU_DRV_V << IO_MUX_GPIO52_MCU_DRV_S) -#define IO_MUX_GPIO52_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO52_MCU_DRV_S 5 -/** IO_MUX_GPIO52_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO52_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO52_FUN_WPD_M (IO_MUX_GPIO52_FUN_WPD_V << IO_MUX_GPIO52_FUN_WPD_S) -#define IO_MUX_GPIO52_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO52_FUN_WPD_S 7 -/** IO_MUX_GPIO52_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO52_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO52_FUN_WPU_M (IO_MUX_GPIO52_FUN_WPU_V << IO_MUX_GPIO52_FUN_WPU_S) -#define IO_MUX_GPIO52_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO52_FUN_WPU_S 8 -/** IO_MUX_GPIO52_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO52_FUN_IE (BIT(9)) -#define IO_MUX_GPIO52_FUN_IE_M (IO_MUX_GPIO52_FUN_IE_V << IO_MUX_GPIO52_FUN_IE_S) -#define IO_MUX_GPIO52_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO52_FUN_IE_S 9 -/** IO_MUX_GPIO52_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO52_FUN_DRV 0x00000003U -#define IO_MUX_GPIO52_FUN_DRV_M (IO_MUX_GPIO52_FUN_DRV_V << IO_MUX_GPIO52_FUN_DRV_S) -#define IO_MUX_GPIO52_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO52_FUN_DRV_S 10 -/** IO_MUX_GPIO52_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO52_MCU_SEL 0x00000007U -#define IO_MUX_GPIO52_MCU_SEL_M (IO_MUX_GPIO52_MCU_SEL_V << IO_MUX_GPIO52_MCU_SEL_S) -#define IO_MUX_GPIO52_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO52_MCU_SEL_S 12 -/** IO_MUX_GPIO52_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO52_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO52_FILTER_EN_M (IO_MUX_GPIO52_FILTER_EN_V << IO_MUX_GPIO52_FILTER_EN_S) -#define IO_MUX_GPIO52_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO52_FILTER_EN_S 15 - -/** IO_MUX_gpio53_REG register - * iomux control register for gpio53 - */ -#define IO_MUX_GPIO53_REG (DR_REG_IO_MUX_BASE + 0xd8) -/** IO_MUX_GPIO53_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO53_MCU_OE (BIT(0)) -#define IO_MUX_GPIO53_MCU_OE_M (IO_MUX_GPIO53_MCU_OE_V << IO_MUX_GPIO53_MCU_OE_S) -#define IO_MUX_GPIO53_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO53_MCU_OE_S 0 -/** IO_MUX_GPIO53_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO53_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO53_SLP_SEL_M (IO_MUX_GPIO53_SLP_SEL_V << IO_MUX_GPIO53_SLP_SEL_S) -#define IO_MUX_GPIO53_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO53_SLP_SEL_S 1 -/** IO_MUX_GPIO53_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO53_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO53_MCU_WPD_M (IO_MUX_GPIO53_MCU_WPD_V << IO_MUX_GPIO53_MCU_WPD_S) -#define IO_MUX_GPIO53_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO53_MCU_WPD_S 2 -/** IO_MUX_GPIO53_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO53_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO53_MCU_WPU_M (IO_MUX_GPIO53_MCU_WPU_V << IO_MUX_GPIO53_MCU_WPU_S) -#define IO_MUX_GPIO53_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO53_MCU_WPU_S 3 -/** IO_MUX_GPIO53_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO53_MCU_IE (BIT(4)) -#define IO_MUX_GPIO53_MCU_IE_M (IO_MUX_GPIO53_MCU_IE_V << IO_MUX_GPIO53_MCU_IE_S) -#define IO_MUX_GPIO53_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO53_MCU_IE_S 4 -/** IO_MUX_GPIO53_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO53_MCU_DRV 0x00000003U -#define IO_MUX_GPIO53_MCU_DRV_M (IO_MUX_GPIO53_MCU_DRV_V << IO_MUX_GPIO53_MCU_DRV_S) -#define IO_MUX_GPIO53_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO53_MCU_DRV_S 5 -/** IO_MUX_GPIO53_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO53_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO53_FUN_WPD_M (IO_MUX_GPIO53_FUN_WPD_V << IO_MUX_GPIO53_FUN_WPD_S) -#define IO_MUX_GPIO53_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO53_FUN_WPD_S 7 -/** IO_MUX_GPIO53_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO53_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO53_FUN_WPU_M (IO_MUX_GPIO53_FUN_WPU_V << IO_MUX_GPIO53_FUN_WPU_S) -#define IO_MUX_GPIO53_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO53_FUN_WPU_S 8 -/** IO_MUX_GPIO53_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO53_FUN_IE (BIT(9)) -#define IO_MUX_GPIO53_FUN_IE_M (IO_MUX_GPIO53_FUN_IE_V << IO_MUX_GPIO53_FUN_IE_S) -#define IO_MUX_GPIO53_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO53_FUN_IE_S 9 -/** IO_MUX_GPIO53_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO53_FUN_DRV 0x00000003U -#define IO_MUX_GPIO53_FUN_DRV_M (IO_MUX_GPIO53_FUN_DRV_V << IO_MUX_GPIO53_FUN_DRV_S) -#define IO_MUX_GPIO53_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO53_FUN_DRV_S 10 -/** IO_MUX_GPIO53_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO53_MCU_SEL 0x00000007U -#define IO_MUX_GPIO53_MCU_SEL_M (IO_MUX_GPIO53_MCU_SEL_V << IO_MUX_GPIO53_MCU_SEL_S) -#define IO_MUX_GPIO53_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO53_MCU_SEL_S 12 -/** IO_MUX_GPIO53_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO53_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO53_FILTER_EN_M (IO_MUX_GPIO53_FILTER_EN_V << IO_MUX_GPIO53_FILTER_EN_S) -#define IO_MUX_GPIO53_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO53_FILTER_EN_S 15 - -/** IO_MUX_gpio54_REG register - * iomux control register for gpio54 - */ -#define IO_MUX_GPIO54_REG (DR_REG_IO_MUX_BASE + 0xdc) -/** IO_MUX_GPIO54_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO54_MCU_OE (BIT(0)) -#define IO_MUX_GPIO54_MCU_OE_M (IO_MUX_GPIO54_MCU_OE_V << IO_MUX_GPIO54_MCU_OE_S) -#define IO_MUX_GPIO54_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO54_MCU_OE_S 0 -/** IO_MUX_GPIO54_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO54_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO54_SLP_SEL_M (IO_MUX_GPIO54_SLP_SEL_V << IO_MUX_GPIO54_SLP_SEL_S) -#define IO_MUX_GPIO54_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO54_SLP_SEL_S 1 -/** IO_MUX_GPIO54_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO54_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO54_MCU_WPD_M (IO_MUX_GPIO54_MCU_WPD_V << IO_MUX_GPIO54_MCU_WPD_S) -#define IO_MUX_GPIO54_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO54_MCU_WPD_S 2 -/** IO_MUX_GPIO54_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO54_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO54_MCU_WPU_M (IO_MUX_GPIO54_MCU_WPU_V << IO_MUX_GPIO54_MCU_WPU_S) -#define IO_MUX_GPIO54_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO54_MCU_WPU_S 3 -/** IO_MUX_GPIO54_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO54_MCU_IE (BIT(4)) -#define IO_MUX_GPIO54_MCU_IE_M (IO_MUX_GPIO54_MCU_IE_V << IO_MUX_GPIO54_MCU_IE_S) -#define IO_MUX_GPIO54_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO54_MCU_IE_S 4 -/** IO_MUX_GPIO54_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO54_MCU_DRV 0x00000003U -#define IO_MUX_GPIO54_MCU_DRV_M (IO_MUX_GPIO54_MCU_DRV_V << IO_MUX_GPIO54_MCU_DRV_S) -#define IO_MUX_GPIO54_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO54_MCU_DRV_S 5 -/** IO_MUX_GPIO54_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO54_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO54_FUN_WPD_M (IO_MUX_GPIO54_FUN_WPD_V << IO_MUX_GPIO54_FUN_WPD_S) -#define IO_MUX_GPIO54_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO54_FUN_WPD_S 7 -/** IO_MUX_GPIO54_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO54_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO54_FUN_WPU_M (IO_MUX_GPIO54_FUN_WPU_V << IO_MUX_GPIO54_FUN_WPU_S) -#define IO_MUX_GPIO54_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO54_FUN_WPU_S 8 -/** IO_MUX_GPIO54_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO54_FUN_IE (BIT(9)) -#define IO_MUX_GPIO54_FUN_IE_M (IO_MUX_GPIO54_FUN_IE_V << IO_MUX_GPIO54_FUN_IE_S) -#define IO_MUX_GPIO54_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO54_FUN_IE_S 9 -/** IO_MUX_GPIO54_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO54_FUN_DRV 0x00000003U -#define IO_MUX_GPIO54_FUN_DRV_M (IO_MUX_GPIO54_FUN_DRV_V << IO_MUX_GPIO54_FUN_DRV_S) -#define IO_MUX_GPIO54_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO54_FUN_DRV_S 10 -/** IO_MUX_GPIO54_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO54_MCU_SEL 0x00000007U -#define IO_MUX_GPIO54_MCU_SEL_M (IO_MUX_GPIO54_MCU_SEL_V << IO_MUX_GPIO54_MCU_SEL_S) -#define IO_MUX_GPIO54_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO54_MCU_SEL_S 12 -/** IO_MUX_GPIO54_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO54_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO54_FILTER_EN_M (IO_MUX_GPIO54_FILTER_EN_V << IO_MUX_GPIO54_FILTER_EN_S) -#define IO_MUX_GPIO54_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO54_FILTER_EN_S 15 - -/** IO_MUX_gpio55_REG register - * iomux control register for gpio55 - */ -#define IO_MUX_GPIO55_REG (DR_REG_IO_MUX_BASE + 0xe0) -/** IO_MUX_GPIO55_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO55_MCU_OE (BIT(0)) -#define IO_MUX_GPIO55_MCU_OE_M (IO_MUX_GPIO55_MCU_OE_V << IO_MUX_GPIO55_MCU_OE_S) -#define IO_MUX_GPIO55_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO55_MCU_OE_S 0 -/** IO_MUX_GPIO55_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO55_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO55_SLP_SEL_M (IO_MUX_GPIO55_SLP_SEL_V << IO_MUX_GPIO55_SLP_SEL_S) -#define IO_MUX_GPIO55_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO55_SLP_SEL_S 1 -/** IO_MUX_GPIO55_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO55_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO55_MCU_WPD_M (IO_MUX_GPIO55_MCU_WPD_V << IO_MUX_GPIO55_MCU_WPD_S) -#define IO_MUX_GPIO55_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO55_MCU_WPD_S 2 -/** IO_MUX_GPIO55_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO55_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO55_MCU_WPU_M (IO_MUX_GPIO55_MCU_WPU_V << IO_MUX_GPIO55_MCU_WPU_S) -#define IO_MUX_GPIO55_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO55_MCU_WPU_S 3 -/** IO_MUX_GPIO55_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO55_MCU_IE (BIT(4)) -#define IO_MUX_GPIO55_MCU_IE_M (IO_MUX_GPIO55_MCU_IE_V << IO_MUX_GPIO55_MCU_IE_S) -#define IO_MUX_GPIO55_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO55_MCU_IE_S 4 -/** IO_MUX_GPIO55_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO55_MCU_DRV 0x00000003U -#define IO_MUX_GPIO55_MCU_DRV_M (IO_MUX_GPIO55_MCU_DRV_V << IO_MUX_GPIO55_MCU_DRV_S) -#define IO_MUX_GPIO55_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO55_MCU_DRV_S 5 -/** IO_MUX_GPIO55_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO55_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO55_FUN_WPD_M (IO_MUX_GPIO55_FUN_WPD_V << IO_MUX_GPIO55_FUN_WPD_S) -#define IO_MUX_GPIO55_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO55_FUN_WPD_S 7 -/** IO_MUX_GPIO55_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO55_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO55_FUN_WPU_M (IO_MUX_GPIO55_FUN_WPU_V << IO_MUX_GPIO55_FUN_WPU_S) -#define IO_MUX_GPIO55_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO55_FUN_WPU_S 8 -/** IO_MUX_GPIO55_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO55_FUN_IE (BIT(9)) -#define IO_MUX_GPIO55_FUN_IE_M (IO_MUX_GPIO55_FUN_IE_V << IO_MUX_GPIO55_FUN_IE_S) -#define IO_MUX_GPIO55_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO55_FUN_IE_S 9 -/** IO_MUX_GPIO55_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO55_FUN_DRV 0x00000003U -#define IO_MUX_GPIO55_FUN_DRV_M (IO_MUX_GPIO55_FUN_DRV_V << IO_MUX_GPIO55_FUN_DRV_S) -#define IO_MUX_GPIO55_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO55_FUN_DRV_S 10 -/** IO_MUX_GPIO55_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO55_MCU_SEL 0x00000007U -#define IO_MUX_GPIO55_MCU_SEL_M (IO_MUX_GPIO55_MCU_SEL_V << IO_MUX_GPIO55_MCU_SEL_S) -#define IO_MUX_GPIO55_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO55_MCU_SEL_S 12 -/** IO_MUX_GPIO55_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO55_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO55_FILTER_EN_M (IO_MUX_GPIO55_FILTER_EN_V << IO_MUX_GPIO55_FILTER_EN_S) -#define IO_MUX_GPIO55_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO55_FILTER_EN_S 15 - -/** IO_MUX_gpio56_REG register - * iomux control register for gpio56 - */ -#define IO_MUX_GPIO56_REG (DR_REG_IO_MUX_BASE + 0xe4) -/** IO_MUX_GPIO56_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO56_MCU_OE (BIT(0)) -#define IO_MUX_GPIO56_MCU_OE_M (IO_MUX_GPIO56_MCU_OE_V << IO_MUX_GPIO56_MCU_OE_S) -#define IO_MUX_GPIO56_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO56_MCU_OE_S 0 -/** IO_MUX_GPIO56_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO56_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO56_SLP_SEL_M (IO_MUX_GPIO56_SLP_SEL_V << IO_MUX_GPIO56_SLP_SEL_S) -#define IO_MUX_GPIO56_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO56_SLP_SEL_S 1 -/** IO_MUX_GPIO56_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO56_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO56_MCU_WPD_M (IO_MUX_GPIO56_MCU_WPD_V << IO_MUX_GPIO56_MCU_WPD_S) -#define IO_MUX_GPIO56_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO56_MCU_WPD_S 2 -/** IO_MUX_GPIO56_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO56_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO56_MCU_WPU_M (IO_MUX_GPIO56_MCU_WPU_V << IO_MUX_GPIO56_MCU_WPU_S) -#define IO_MUX_GPIO56_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO56_MCU_WPU_S 3 -/** IO_MUX_GPIO56_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO56_MCU_IE (BIT(4)) -#define IO_MUX_GPIO56_MCU_IE_M (IO_MUX_GPIO56_MCU_IE_V << IO_MUX_GPIO56_MCU_IE_S) -#define IO_MUX_GPIO56_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO56_MCU_IE_S 4 -/** IO_MUX_GPIO56_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO56_MCU_DRV 0x00000003U -#define IO_MUX_GPIO56_MCU_DRV_M (IO_MUX_GPIO56_MCU_DRV_V << IO_MUX_GPIO56_MCU_DRV_S) -#define IO_MUX_GPIO56_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO56_MCU_DRV_S 5 -/** IO_MUX_GPIO56_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO56_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO56_FUN_WPD_M (IO_MUX_GPIO56_FUN_WPD_V << IO_MUX_GPIO56_FUN_WPD_S) -#define IO_MUX_GPIO56_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO56_FUN_WPD_S 7 -/** IO_MUX_GPIO56_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO56_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO56_FUN_WPU_M (IO_MUX_GPIO56_FUN_WPU_V << IO_MUX_GPIO56_FUN_WPU_S) -#define IO_MUX_GPIO56_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO56_FUN_WPU_S 8 -/** IO_MUX_GPIO56_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO56_FUN_IE (BIT(9)) -#define IO_MUX_GPIO56_FUN_IE_M (IO_MUX_GPIO56_FUN_IE_V << IO_MUX_GPIO56_FUN_IE_S) -#define IO_MUX_GPIO56_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO56_FUN_IE_S 9 -/** IO_MUX_GPIO56_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO56_FUN_DRV 0x00000003U -#define IO_MUX_GPIO56_FUN_DRV_M (IO_MUX_GPIO56_FUN_DRV_V << IO_MUX_GPIO56_FUN_DRV_S) -#define IO_MUX_GPIO56_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO56_FUN_DRV_S 10 -/** IO_MUX_GPIO56_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO56_MCU_SEL 0x00000007U -#define IO_MUX_GPIO56_MCU_SEL_M (IO_MUX_GPIO56_MCU_SEL_V << IO_MUX_GPIO56_MCU_SEL_S) -#define IO_MUX_GPIO56_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO56_MCU_SEL_S 12 -/** IO_MUX_GPIO56_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO56_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO56_FILTER_EN_M (IO_MUX_GPIO56_FILTER_EN_V << IO_MUX_GPIO56_FILTER_EN_S) -#define IO_MUX_GPIO56_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO56_FILTER_EN_S 15 - -/** IO_MUX_DATE_REG register - * iomux version - */ -#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0x104) -/** IO_MUX_DATE : R/W; bitpos: [27:0]; default: 2101794; - * csv date - */ -#define IO_MUX_DATE 0x0FFFFFFFU -#define IO_MUX_DATE_M (IO_MUX_DATE_V << IO_MUX_DATE_S) -#define IO_MUX_DATE_V 0x0FFFFFFFU -#define IO_MUX_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_struct.h deleted file mode 100644 index 0ebee78c3498..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_struct.h +++ /dev/null @@ -1,3430 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: IOMUX Register */ -/** Type of gpio0 register - * iomux control register for gpio0 - */ -typedef union { - struct { - /** gpio0_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio0_mcu_oe:1; - /** gpio0_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio0_slp_sel:1; - /** gpio0_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio0_mcu_wpd:1; - /** gpio0_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio0_mcu_wpu:1; - /** gpio0_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio0_mcu_ie:1; - /** gpio0_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio0_mcu_drv:2; - /** gpio0_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio0_fun_wpd:1; - /** gpio0_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio0_fun_wpu:1; - /** gpio0_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio0_fun_ie:1; - /** gpio0_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio0_fun_drv:2; - /** gpio0_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio0_mcu_sel:3; - /** gpio0_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio0_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio0_reg_t; - -/** Type of gpio1 register - * iomux control register for gpio1 - */ -typedef union { - struct { - /** gpio1_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio1_mcu_oe:1; - /** gpio1_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio1_slp_sel:1; - /** gpio1_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio1_mcu_wpd:1; - /** gpio1_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio1_mcu_wpu:1; - /** gpio1_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio1_mcu_ie:1; - /** gpio1_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio1_mcu_drv:2; - /** gpio1_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio1_fun_wpd:1; - /** gpio1_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio1_fun_wpu:1; - /** gpio1_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio1_fun_ie:1; - /** gpio1_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio1_fun_drv:2; - /** gpio1_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio1_mcu_sel:3; - /** gpio1_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio1_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio1_reg_t; - -/** Type of gpio2 register - * iomux control register for gpio2 - */ -typedef union { - struct { - /** gpio2_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio2_mcu_oe:1; - /** gpio2_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio2_slp_sel:1; - /** gpio2_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio2_mcu_wpd:1; - /** gpio2_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio2_mcu_wpu:1; - /** gpio2_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio2_mcu_ie:1; - /** gpio2_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio2_mcu_drv:2; - /** gpio2_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio2_fun_wpd:1; - /** gpio2_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio2_fun_wpu:1; - /** gpio2_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio2_fun_ie:1; - /** gpio2_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio2_fun_drv:2; - /** gpio2_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio2_mcu_sel:3; - /** gpio2_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio2_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio2_reg_t; - -/** Type of gpio3 register - * iomux control register for gpio3 - */ -typedef union { - struct { - /** gpio3_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio3_mcu_oe:1; - /** gpio3_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio3_slp_sel:1; - /** gpio3_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio3_mcu_wpd:1; - /** gpio3_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio3_mcu_wpu:1; - /** gpio3_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio3_mcu_ie:1; - /** gpio3_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio3_mcu_drv:2; - /** gpio3_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio3_fun_wpd:1; - /** gpio3_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio3_fun_wpu:1; - /** gpio3_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio3_fun_ie:1; - /** gpio3_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio3_fun_drv:2; - /** gpio3_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio3_mcu_sel:3; - /** gpio3_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio3_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio3_reg_t; - -/** Type of gpio4 register - * iomux control register for gpio4 - */ -typedef union { - struct { - /** gpio4_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio4_mcu_oe:1; - /** gpio4_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio4_slp_sel:1; - /** gpio4_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio4_mcu_wpd:1; - /** gpio4_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio4_mcu_wpu:1; - /** gpio4_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio4_mcu_ie:1; - /** gpio4_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio4_mcu_drv:2; - /** gpio4_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio4_fun_wpd:1; - /** gpio4_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio4_fun_wpu:1; - /** gpio4_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio4_fun_ie:1; - /** gpio4_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio4_fun_drv:2; - /** gpio4_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio4_mcu_sel:3; - /** gpio4_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio4_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio4_reg_t; - -/** Type of gpio5 register - * iomux control register for gpio5 - */ -typedef union { - struct { - /** gpio5_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio5_mcu_oe:1; - /** gpio5_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio5_slp_sel:1; - /** gpio5_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio5_mcu_wpd:1; - /** gpio5_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio5_mcu_wpu:1; - /** gpio5_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio5_mcu_ie:1; - /** gpio5_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio5_mcu_drv:2; - /** gpio5_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio5_fun_wpd:1; - /** gpio5_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio5_fun_wpu:1; - /** gpio5_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio5_fun_ie:1; - /** gpio5_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio5_fun_drv:2; - /** gpio5_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio5_mcu_sel:3; - /** gpio5_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio5_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio5_reg_t; - -/** Type of gpio6 register - * iomux control register for gpio6 - */ -typedef union { - struct { - /** gpio6_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio6_mcu_oe:1; - /** gpio6_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio6_slp_sel:1; - /** gpio6_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio6_mcu_wpd:1; - /** gpio6_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio6_mcu_wpu:1; - /** gpio6_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio6_mcu_ie:1; - /** gpio6_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio6_mcu_drv:2; - /** gpio6_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio6_fun_wpd:1; - /** gpio6_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio6_fun_wpu:1; - /** gpio6_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio6_fun_ie:1; - /** gpio6_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio6_fun_drv:2; - /** gpio6_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio6_mcu_sel:3; - /** gpio6_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio6_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio6_reg_t; - -/** Type of gpio7 register - * iomux control register for gpio7 - */ -typedef union { - struct { - /** gpio7_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio7_mcu_oe:1; - /** gpio7_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio7_slp_sel:1; - /** gpio7_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio7_mcu_wpd:1; - /** gpio7_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio7_mcu_wpu:1; - /** gpio7_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio7_mcu_ie:1; - /** gpio7_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio7_mcu_drv:2; - /** gpio7_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio7_fun_wpd:1; - /** gpio7_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio7_fun_wpu:1; - /** gpio7_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio7_fun_ie:1; - /** gpio7_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio7_fun_drv:2; - /** gpio7_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio7_mcu_sel:3; - /** gpio7_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio7_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio7_reg_t; - -/** Type of gpio8 register - * iomux control register for gpio8 - */ -typedef union { - struct { - /** gpio8_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio8_mcu_oe:1; - /** gpio8_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio8_slp_sel:1; - /** gpio8_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio8_mcu_wpd:1; - /** gpio8_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio8_mcu_wpu:1; - /** gpio8_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio8_mcu_ie:1; - /** gpio8_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio8_mcu_drv:2; - /** gpio8_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio8_fun_wpd:1; - /** gpio8_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio8_fun_wpu:1; - /** gpio8_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio8_fun_ie:1; - /** gpio8_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio8_fun_drv:2; - /** gpio8_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio8_mcu_sel:3; - /** gpio8_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio8_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio8_reg_t; - -/** Type of gpio9 register - * iomux control register for gpio9 - */ -typedef union { - struct { - /** gpio9_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio9_mcu_oe:1; - /** gpio9_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio9_slp_sel:1; - /** gpio9_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio9_mcu_wpd:1; - /** gpio9_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio9_mcu_wpu:1; - /** gpio9_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio9_mcu_ie:1; - /** gpio9_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio9_mcu_drv:2; - /** gpio9_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio9_fun_wpd:1; - /** gpio9_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio9_fun_wpu:1; - /** gpio9_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio9_fun_ie:1; - /** gpio9_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio9_fun_drv:2; - /** gpio9_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio9_mcu_sel:3; - /** gpio9_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio9_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio9_reg_t; - -/** Type of gpio10 register - * iomux control register for gpio10 - */ -typedef union { - struct { - /** gpio10_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio10_mcu_oe:1; - /** gpio10_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio10_slp_sel:1; - /** gpio10_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio10_mcu_wpd:1; - /** gpio10_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio10_mcu_wpu:1; - /** gpio10_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio10_mcu_ie:1; - /** gpio10_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio10_mcu_drv:2; - /** gpio10_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio10_fun_wpd:1; - /** gpio10_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio10_fun_wpu:1; - /** gpio10_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio10_fun_ie:1; - /** gpio10_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio10_fun_drv:2; - /** gpio10_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio10_mcu_sel:3; - /** gpio10_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio10_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio10_reg_t; - -/** Type of gpio11 register - * iomux control register for gpio11 - */ -typedef union { - struct { - /** gpio11_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio11_mcu_oe:1; - /** gpio11_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio11_slp_sel:1; - /** gpio11_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio11_mcu_wpd:1; - /** gpio11_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio11_mcu_wpu:1; - /** gpio11_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio11_mcu_ie:1; - /** gpio11_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio11_mcu_drv:2; - /** gpio11_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio11_fun_wpd:1; - /** gpio11_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio11_fun_wpu:1; - /** gpio11_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio11_fun_ie:1; - /** gpio11_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio11_fun_drv:2; - /** gpio11_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio11_mcu_sel:3; - /** gpio11_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio11_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio11_reg_t; - -/** Type of gpio12 register - * iomux control register for gpio12 - */ -typedef union { - struct { - /** gpio12_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio12_mcu_oe:1; - /** gpio12_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio12_slp_sel:1; - /** gpio12_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio12_mcu_wpd:1; - /** gpio12_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio12_mcu_wpu:1; - /** gpio12_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio12_mcu_ie:1; - /** gpio12_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio12_mcu_drv:2; - /** gpio12_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio12_fun_wpd:1; - /** gpio12_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio12_fun_wpu:1; - /** gpio12_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio12_fun_ie:1; - /** gpio12_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio12_fun_drv:2; - /** gpio12_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio12_mcu_sel:3; - /** gpio12_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio12_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio12_reg_t; - -/** Type of gpio13 register - * iomux control register for gpio13 - */ -typedef union { - struct { - /** gpio13_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio13_mcu_oe:1; - /** gpio13_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio13_slp_sel:1; - /** gpio13_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio13_mcu_wpd:1; - /** gpio13_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio13_mcu_wpu:1; - /** gpio13_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio13_mcu_ie:1; - /** gpio13_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio13_mcu_drv:2; - /** gpio13_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio13_fun_wpd:1; - /** gpio13_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio13_fun_wpu:1; - /** gpio13_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio13_fun_ie:1; - /** gpio13_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio13_fun_drv:2; - /** gpio13_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio13_mcu_sel:3; - /** gpio13_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio13_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio13_reg_t; - -/** Type of gpio14 register - * iomux control register for gpio14 - */ -typedef union { - struct { - /** gpio14_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio14_mcu_oe:1; - /** gpio14_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio14_slp_sel:1; - /** gpio14_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio14_mcu_wpd:1; - /** gpio14_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio14_mcu_wpu:1; - /** gpio14_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio14_mcu_ie:1; - /** gpio14_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio14_mcu_drv:2; - /** gpio14_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio14_fun_wpd:1; - /** gpio14_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio14_fun_wpu:1; - /** gpio14_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio14_fun_ie:1; - /** gpio14_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio14_fun_drv:2; - /** gpio14_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio14_mcu_sel:3; - /** gpio14_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio14_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio14_reg_t; - -/** Type of gpio15 register - * iomux control register for gpio15 - */ -typedef union { - struct { - /** gpio15_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio15_mcu_oe:1; - /** gpio15_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio15_slp_sel:1; - /** gpio15_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio15_mcu_wpd:1; - /** gpio15_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio15_mcu_wpu:1; - /** gpio15_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio15_mcu_ie:1; - /** gpio15_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio15_mcu_drv:2; - /** gpio15_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio15_fun_wpd:1; - /** gpio15_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio15_fun_wpu:1; - /** gpio15_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio15_fun_ie:1; - /** gpio15_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio15_fun_drv:2; - /** gpio15_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio15_mcu_sel:3; - /** gpio15_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio15_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio15_reg_t; - -/** Type of gpio16 register - * iomux control register for gpio16 - */ -typedef union { - struct { - /** gpio16_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio16_mcu_oe:1; - /** gpio16_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio16_slp_sel:1; - /** gpio16_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio16_mcu_wpd:1; - /** gpio16_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio16_mcu_wpu:1; - /** gpio16_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio16_mcu_ie:1; - /** gpio16_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio16_mcu_drv:2; - /** gpio16_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio16_fun_wpd:1; - /** gpio16_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio16_fun_wpu:1; - /** gpio16_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio16_fun_ie:1; - /** gpio16_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio16_fun_drv:2; - /** gpio16_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio16_mcu_sel:3; - /** gpio16_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio16_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio16_reg_t; - -/** Type of gpio17 register - * iomux control register for gpio17 - */ -typedef union { - struct { - /** gpio17_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio17_mcu_oe:1; - /** gpio17_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio17_slp_sel:1; - /** gpio17_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio17_mcu_wpd:1; - /** gpio17_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio17_mcu_wpu:1; - /** gpio17_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio17_mcu_ie:1; - /** gpio17_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio17_mcu_drv:2; - /** gpio17_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio17_fun_wpd:1; - /** gpio17_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio17_fun_wpu:1; - /** gpio17_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio17_fun_ie:1; - /** gpio17_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio17_fun_drv:2; - /** gpio17_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio17_mcu_sel:3; - /** gpio17_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio17_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio17_reg_t; - -/** Type of gpio18 register - * iomux control register for gpio18 - */ -typedef union { - struct { - /** gpio18_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio18_mcu_oe:1; - /** gpio18_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio18_slp_sel:1; - /** gpio18_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio18_mcu_wpd:1; - /** gpio18_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio18_mcu_wpu:1; - /** gpio18_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio18_mcu_ie:1; - /** gpio18_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio18_mcu_drv:2; - /** gpio18_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio18_fun_wpd:1; - /** gpio18_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio18_fun_wpu:1; - /** gpio18_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio18_fun_ie:1; - /** gpio18_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio18_fun_drv:2; - /** gpio18_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio18_mcu_sel:3; - /** gpio18_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio18_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio18_reg_t; - -/** Type of gpio19 register - * iomux control register for gpio19 - */ -typedef union { - struct { - /** gpio19_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio19_mcu_oe:1; - /** gpio19_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio19_slp_sel:1; - /** gpio19_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio19_mcu_wpd:1; - /** gpio19_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio19_mcu_wpu:1; - /** gpio19_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio19_mcu_ie:1; - /** gpio19_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio19_mcu_drv:2; - /** gpio19_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio19_fun_wpd:1; - /** gpio19_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio19_fun_wpu:1; - /** gpio19_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio19_fun_ie:1; - /** gpio19_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio19_fun_drv:2; - /** gpio19_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio19_mcu_sel:3; - /** gpio19_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio19_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio19_reg_t; - -/** Type of gpio20 register - * iomux control register for gpio20 - */ -typedef union { - struct { - /** gpio20_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio20_mcu_oe:1; - /** gpio20_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio20_slp_sel:1; - /** gpio20_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio20_mcu_wpd:1; - /** gpio20_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio20_mcu_wpu:1; - /** gpio20_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio20_mcu_ie:1; - /** gpio20_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio20_mcu_drv:2; - /** gpio20_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio20_fun_wpd:1; - /** gpio20_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio20_fun_wpu:1; - /** gpio20_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio20_fun_ie:1; - /** gpio20_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio20_fun_drv:2; - /** gpio20_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio20_mcu_sel:3; - /** gpio20_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio20_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio20_reg_t; - -/** Type of gpio21 register - * iomux control register for gpio21 - */ -typedef union { - struct { - /** gpio21_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio21_mcu_oe:1; - /** gpio21_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio21_slp_sel:1; - /** gpio21_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio21_mcu_wpd:1; - /** gpio21_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio21_mcu_wpu:1; - /** gpio21_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio21_mcu_ie:1; - /** gpio21_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio21_mcu_drv:2; - /** gpio21_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio21_fun_wpd:1; - /** gpio21_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio21_fun_wpu:1; - /** gpio21_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio21_fun_ie:1; - /** gpio21_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio21_fun_drv:2; - /** gpio21_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio21_mcu_sel:3; - /** gpio21_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio21_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio21_reg_t; - -/** Type of gpio22 register - * iomux control register for gpio22 - */ -typedef union { - struct { - /** gpio22_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio22_mcu_oe:1; - /** gpio22_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio22_slp_sel:1; - /** gpio22_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio22_mcu_wpd:1; - /** gpio22_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio22_mcu_wpu:1; - /** gpio22_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio22_mcu_ie:1; - /** gpio22_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio22_mcu_drv:2; - /** gpio22_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio22_fun_wpd:1; - /** gpio22_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio22_fun_wpu:1; - /** gpio22_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio22_fun_ie:1; - /** gpio22_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio22_fun_drv:2; - /** gpio22_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio22_mcu_sel:3; - /** gpio22_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio22_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio22_reg_t; - -/** Type of gpio23 register - * iomux control register for gpio23 - */ -typedef union { - struct { - /** gpio23_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio23_mcu_oe:1; - /** gpio23_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio23_slp_sel:1; - /** gpio23_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio23_mcu_wpd:1; - /** gpio23_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio23_mcu_wpu:1; - /** gpio23_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio23_mcu_ie:1; - /** gpio23_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio23_mcu_drv:2; - /** gpio23_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio23_fun_wpd:1; - /** gpio23_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio23_fun_wpu:1; - /** gpio23_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio23_fun_ie:1; - /** gpio23_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio23_fun_drv:2; - /** gpio23_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio23_mcu_sel:3; - /** gpio23_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio23_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio23_reg_t; - -/** Type of gpio24 register - * iomux control register for gpio24 - */ -typedef union { - struct { - /** gpio24_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio24_mcu_oe:1; - /** gpio24_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio24_slp_sel:1; - /** gpio24_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio24_mcu_wpd:1; - /** gpio24_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio24_mcu_wpu:1; - /** gpio24_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio24_mcu_ie:1; - /** gpio24_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio24_mcu_drv:2; - /** gpio24_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio24_fun_wpd:1; - /** gpio24_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio24_fun_wpu:1; - /** gpio24_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio24_fun_ie:1; - /** gpio24_fun_drv : R/W; bitpos: [11:10]; default: 3; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio24_fun_drv:2; - /** gpio24_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio24_mcu_sel:3; - /** gpio24_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio24_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio24_reg_t; - -/** Type of gpio25 register - * iomux control register for gpio25 - */ -typedef union { - struct { - /** gpio25_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio25_mcu_oe:1; - /** gpio25_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio25_slp_sel:1; - /** gpio25_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio25_mcu_wpd:1; - /** gpio25_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio25_mcu_wpu:1; - /** gpio25_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio25_mcu_ie:1; - /** gpio25_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio25_mcu_drv:2; - /** gpio25_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio25_fun_wpd:1; - /** gpio25_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio25_fun_wpu:1; - /** gpio25_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio25_fun_ie:1; - /** gpio25_fun_drv : R/W; bitpos: [11:10]; default: 3; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio25_fun_drv:2; - /** gpio25_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio25_mcu_sel:3; - /** gpio25_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio25_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio25_reg_t; - -/** Type of gpio26 register - * iomux control register for gpio26 - */ -typedef union { - struct { - /** gpio26_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio26_mcu_oe:1; - /** gpio26_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio26_slp_sel:1; - /** gpio26_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio26_mcu_wpd:1; - /** gpio26_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio26_mcu_wpu:1; - /** gpio26_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio26_mcu_ie:1; - /** gpio26_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio26_mcu_drv:2; - /** gpio26_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio26_fun_wpd:1; - /** gpio26_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio26_fun_wpu:1; - /** gpio26_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio26_fun_ie:1; - /** gpio26_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio26_fun_drv:2; - /** gpio26_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio26_mcu_sel:3; - /** gpio26_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio26_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio26_reg_t; - -/** Type of gpio27 register - * iomux control register for gpio27 - */ -typedef union { - struct { - /** gpio27_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio27_mcu_oe:1; - /** gpio27_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio27_slp_sel:1; - /** gpio27_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio27_mcu_wpd:1; - /** gpio27_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio27_mcu_wpu:1; - /** gpio27_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio27_mcu_ie:1; - /** gpio27_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio27_mcu_drv:2; - /** gpio27_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio27_fun_wpd:1; - /** gpio27_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio27_fun_wpu:1; - /** gpio27_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio27_fun_ie:1; - /** gpio27_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio27_fun_drv:2; - /** gpio27_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio27_mcu_sel:3; - /** gpio27_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio27_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio27_reg_t; - -/** Type of gpio28 register - * iomux control register for gpio28 - */ -typedef union { - struct { - /** gpio28_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio28_mcu_oe:1; - /** gpio28_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio28_slp_sel:1; - /** gpio28_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio28_mcu_wpd:1; - /** gpio28_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio28_mcu_wpu:1; - /** gpio28_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio28_mcu_ie:1; - /** gpio28_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio28_mcu_drv:2; - /** gpio28_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio28_fun_wpd:1; - /** gpio28_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio28_fun_wpu:1; - /** gpio28_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio28_fun_ie:1; - /** gpio28_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio28_fun_drv:2; - /** gpio28_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio28_mcu_sel:3; - /** gpio28_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio28_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio28_reg_t; - -/** Type of gpio29 register - * iomux control register for gpio29 - */ -typedef union { - struct { - /** gpio29_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio29_mcu_oe:1; - /** gpio29_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio29_slp_sel:1; - /** gpio29_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio29_mcu_wpd:1; - /** gpio29_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio29_mcu_wpu:1; - /** gpio29_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio29_mcu_ie:1; - /** gpio29_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio29_mcu_drv:2; - /** gpio29_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio29_fun_wpd:1; - /** gpio29_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio29_fun_wpu:1; - /** gpio29_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio29_fun_ie:1; - /** gpio29_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio29_fun_drv:2; - /** gpio29_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio29_mcu_sel:3; - /** gpio29_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio29_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio29_reg_t; - -/** Type of gpio30 register - * iomux control register for gpio30 - */ -typedef union { - struct { - /** gpio30_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio30_mcu_oe:1; - /** gpio30_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio30_slp_sel:1; - /** gpio30_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio30_mcu_wpd:1; - /** gpio30_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio30_mcu_wpu:1; - /** gpio30_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio30_mcu_ie:1; - /** gpio30_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio30_mcu_drv:2; - /** gpio30_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio30_fun_wpd:1; - /** gpio30_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio30_fun_wpu:1; - /** gpio30_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio30_fun_ie:1; - /** gpio30_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio30_fun_drv:2; - /** gpio30_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio30_mcu_sel:3; - /** gpio30_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio30_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio30_reg_t; - -/** Type of gpio31 register - * iomux control register for gpio31 - */ -typedef union { - struct { - /** gpio31_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio31_mcu_oe:1; - /** gpio31_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio31_slp_sel:1; - /** gpio31_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio31_mcu_wpd:1; - /** gpio31_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio31_mcu_wpu:1; - /** gpio31_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio31_mcu_ie:1; - /** gpio31_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio31_mcu_drv:2; - /** gpio31_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio31_fun_wpd:1; - /** gpio31_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio31_fun_wpu:1; - /** gpio31_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio31_fun_ie:1; - /** gpio31_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio31_fun_drv:2; - /** gpio31_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio31_mcu_sel:3; - /** gpio31_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio31_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio31_reg_t; - -/** Type of gpio32 register - * iomux control register for gpio32 - */ -typedef union { - struct { - /** gpio32_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio32_mcu_oe:1; - /** gpio32_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio32_slp_sel:1; - /** gpio32_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio32_mcu_wpd:1; - /** gpio32_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio32_mcu_wpu:1; - /** gpio32_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio32_mcu_ie:1; - /** gpio32_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio32_mcu_drv:2; - /** gpio32_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio32_fun_wpd:1; - /** gpio32_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio32_fun_wpu:1; - /** gpio32_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio32_fun_ie:1; - /** gpio32_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio32_fun_drv:2; - /** gpio32_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio32_mcu_sel:3; - /** gpio32_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio32_filter_en:1; - /** gpio32_rue_i3c : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t gpio32_rue_i3c:1; - /** gpio32_ru_i3c : R/W; bitpos: [18:17]; default: 0; - * NA - */ - uint32_t gpio32_ru_i3c:2; - /** gpio32_rue_sel_i3c : R/W; bitpos: [19]; default: 0; - * NA - */ - uint32_t gpio32_rue_sel_i3c:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} io_mux_gpio32_reg_t; - -/** Type of gpio33 register - * iomux control register for gpio33 - */ -typedef union { - struct { - /** gpio33_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio33_mcu_oe:1; - /** gpio33_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio33_slp_sel:1; - /** gpio33_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio33_mcu_wpd:1; - /** gpio33_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio33_mcu_wpu:1; - /** gpio33_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio33_mcu_ie:1; - /** gpio33_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio33_mcu_drv:2; - /** gpio33_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio33_fun_wpd:1; - /** gpio33_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio33_fun_wpu:1; - /** gpio33_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio33_fun_ie:1; - /** gpio33_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio33_fun_drv:2; - /** gpio33_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio33_mcu_sel:3; - /** gpio33_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio33_filter_en:1; - /** gpio33_rue_i3c : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t gpio33_rue_i3c:1; - /** gpio33_ru_i3c : R/W; bitpos: [18:17]; default: 0; - * NA - */ - uint32_t gpio33_ru_i3c:2; - /** gpio33_rue_sel_i3c : R/W; bitpos: [19]; default: 0; - * NA - */ - uint32_t gpio33_rue_sel_i3c:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} io_mux_gpio33_reg_t; - -/** Type of gpio34 register - * iomux control register for gpio34 - */ -typedef union { - struct { - /** gpio34_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio34_mcu_oe:1; - /** gpio34_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio34_slp_sel:1; - /** gpio34_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio34_mcu_wpd:1; - /** gpio34_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio34_mcu_wpu:1; - /** gpio34_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio34_mcu_ie:1; - /** gpio34_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio34_mcu_drv:2; - /** gpio34_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio34_fun_wpd:1; - /** gpio34_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio34_fun_wpu:1; - /** gpio34_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio34_fun_ie:1; - /** gpio34_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio34_fun_drv:2; - /** gpio34_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio34_mcu_sel:3; - /** gpio34_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio34_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio34_reg_t; - -/** Type of gpio35 register - * iomux control register for gpio35 - */ -typedef union { - struct { - /** gpio35_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio35_mcu_oe:1; - /** gpio35_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio35_slp_sel:1; - /** gpio35_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio35_mcu_wpd:1; - /** gpio35_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio35_mcu_wpu:1; - /** gpio35_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio35_mcu_ie:1; - /** gpio35_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio35_mcu_drv:2; - /** gpio35_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio35_fun_wpd:1; - /** gpio35_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio35_fun_wpu:1; - /** gpio35_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio35_fun_ie:1; - /** gpio35_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio35_fun_drv:2; - /** gpio35_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio35_mcu_sel:3; - /** gpio35_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio35_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio35_reg_t; - -/** Type of gpio36 register - * iomux control register for gpio36 - */ -typedef union { - struct { - /** gpio36_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio36_mcu_oe:1; - /** gpio36_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio36_slp_sel:1; - /** gpio36_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio36_mcu_wpd:1; - /** gpio36_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio36_mcu_wpu:1; - /** gpio36_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio36_mcu_ie:1; - /** gpio36_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio36_mcu_drv:2; - /** gpio36_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio36_fun_wpd:1; - /** gpio36_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio36_fun_wpu:1; - /** gpio36_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio36_fun_ie:1; - /** gpio36_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio36_fun_drv:2; - /** gpio36_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio36_mcu_sel:3; - /** gpio36_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio36_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio36_reg_t; - -/** Type of gpio37 register - * iomux control register for gpio37 - */ -typedef union { - struct { - /** gpio37_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio37_mcu_oe:1; - /** gpio37_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio37_slp_sel:1; - /** gpio37_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio37_mcu_wpd:1; - /** gpio37_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio37_mcu_wpu:1; - /** gpio37_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio37_mcu_ie:1; - /** gpio37_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio37_mcu_drv:2; - /** gpio37_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio37_fun_wpd:1; - /** gpio37_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio37_fun_wpu:1; - /** gpio37_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio37_fun_ie:1; - /** gpio37_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio37_fun_drv:2; - /** gpio37_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio37_mcu_sel:3; - /** gpio37_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio37_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio37_reg_t; - -/** Type of gpio38 register - * iomux control register for gpio38 - */ -typedef union { - struct { - /** gpio38_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio38_mcu_oe:1; - /** gpio38_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio38_slp_sel:1; - /** gpio38_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio38_mcu_wpd:1; - /** gpio38_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio38_mcu_wpu:1; - /** gpio38_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio38_mcu_ie:1; - /** gpio38_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio38_mcu_drv:2; - /** gpio38_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio38_fun_wpd:1; - /** gpio38_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio38_fun_wpu:1; - /** gpio38_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio38_fun_ie:1; - /** gpio38_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio38_fun_drv:2; - /** gpio38_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio38_mcu_sel:3; - /** gpio38_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio38_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio38_reg_t; - -/** Type of gpio39 register - * iomux control register for gpio39 - */ -typedef union { - struct { - /** gpio39_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio39_mcu_oe:1; - /** gpio39_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio39_slp_sel:1; - /** gpio39_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio39_mcu_wpd:1; - /** gpio39_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio39_mcu_wpu:1; - /** gpio39_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio39_mcu_ie:1; - /** gpio39_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio39_mcu_drv:2; - /** gpio39_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio39_fun_wpd:1; - /** gpio39_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio39_fun_wpu:1; - /** gpio39_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio39_fun_ie:1; - /** gpio39_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio39_fun_drv:2; - /** gpio39_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio39_mcu_sel:3; - /** gpio39_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio39_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio39_reg_t; - -/** Type of gpio40 register - * iomux control register for gpio40 - */ -typedef union { - struct { - /** gpio40_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio40_mcu_oe:1; - /** gpio40_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio40_slp_sel:1; - /** gpio40_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio40_mcu_wpd:1; - /** gpio40_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio40_mcu_wpu:1; - /** gpio40_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio40_mcu_ie:1; - /** gpio40_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio40_mcu_drv:2; - /** gpio40_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio40_fun_wpd:1; - /** gpio40_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio40_fun_wpu:1; - /** gpio40_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio40_fun_ie:1; - /** gpio40_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio40_fun_drv:2; - /** gpio40_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio40_mcu_sel:3; - /** gpio40_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio40_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio40_reg_t; - -/** Type of gpio41 register - * iomux control register for gpio41 - */ -typedef union { - struct { - /** gpio41_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio41_mcu_oe:1; - /** gpio41_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio41_slp_sel:1; - /** gpio41_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio41_mcu_wpd:1; - /** gpio41_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio41_mcu_wpu:1; - /** gpio41_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio41_mcu_ie:1; - /** gpio41_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio41_mcu_drv:2; - /** gpio41_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio41_fun_wpd:1; - /** gpio41_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio41_fun_wpu:1; - /** gpio41_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio41_fun_ie:1; - /** gpio41_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio41_fun_drv:2; - /** gpio41_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio41_mcu_sel:3; - /** gpio41_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio41_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio41_reg_t; - -/** Type of gpio42 register - * iomux control register for gpio42 - */ -typedef union { - struct { - /** gpio42_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio42_mcu_oe:1; - /** gpio42_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio42_slp_sel:1; - /** gpio42_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio42_mcu_wpd:1; - /** gpio42_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio42_mcu_wpu:1; - /** gpio42_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio42_mcu_ie:1; - /** gpio42_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio42_mcu_drv:2; - /** gpio42_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio42_fun_wpd:1; - /** gpio42_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio42_fun_wpu:1; - /** gpio42_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio42_fun_ie:1; - /** gpio42_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio42_fun_drv:2; - /** gpio42_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio42_mcu_sel:3; - /** gpio42_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio42_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio42_reg_t; - -/** Type of gpio43 register - * iomux control register for gpio43 - */ -typedef union { - struct { - /** gpio43_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio43_mcu_oe:1; - /** gpio43_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio43_slp_sel:1; - /** gpio43_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio43_mcu_wpd:1; - /** gpio43_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio43_mcu_wpu:1; - /** gpio43_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio43_mcu_ie:1; - /** gpio43_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio43_mcu_drv:2; - /** gpio43_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio43_fun_wpd:1; - /** gpio43_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio43_fun_wpu:1; - /** gpio43_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio43_fun_ie:1; - /** gpio43_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio43_fun_drv:2; - /** gpio43_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio43_mcu_sel:3; - /** gpio43_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio43_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio43_reg_t; - -/** Type of gpio44 register - * iomux control register for gpio44 - */ -typedef union { - struct { - /** gpio44_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio44_mcu_oe:1; - /** gpio44_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio44_slp_sel:1; - /** gpio44_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio44_mcu_wpd:1; - /** gpio44_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio44_mcu_wpu:1; - /** gpio44_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio44_mcu_ie:1; - /** gpio44_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio44_mcu_drv:2; - /** gpio44_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio44_fun_wpd:1; - /** gpio44_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio44_fun_wpu:1; - /** gpio44_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio44_fun_ie:1; - /** gpio44_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio44_fun_drv:2; - /** gpio44_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio44_mcu_sel:3; - /** gpio44_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio44_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio44_reg_t; - -/** Type of gpio45 register - * iomux control register for gpio45 - */ -typedef union { - struct { - /** gpio45_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio45_mcu_oe:1; - /** gpio45_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio45_slp_sel:1; - /** gpio45_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio45_mcu_wpd:1; - /** gpio45_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio45_mcu_wpu:1; - /** gpio45_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio45_mcu_ie:1; - /** gpio45_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio45_mcu_drv:2; - /** gpio45_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio45_fun_wpd:1; - /** gpio45_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio45_fun_wpu:1; - /** gpio45_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio45_fun_ie:1; - /** gpio45_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio45_fun_drv:2; - /** gpio45_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio45_mcu_sel:3; - /** gpio45_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio45_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio45_reg_t; - -/** Type of gpio46 register - * iomux control register for gpio46 - */ -typedef union { - struct { - /** gpio46_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio46_mcu_oe:1; - /** gpio46_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio46_slp_sel:1; - /** gpio46_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio46_mcu_wpd:1; - /** gpio46_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio46_mcu_wpu:1; - /** gpio46_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio46_mcu_ie:1; - /** gpio46_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio46_mcu_drv:2; - /** gpio46_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio46_fun_wpd:1; - /** gpio46_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio46_fun_wpu:1; - /** gpio46_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio46_fun_ie:1; - /** gpio46_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio46_fun_drv:2; - /** gpio46_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio46_mcu_sel:3; - /** gpio46_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio46_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio46_reg_t; - -/** Type of gpio47 register - * iomux control register for gpio47 - */ -typedef union { - struct { - /** gpio47_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio47_mcu_oe:1; - /** gpio47_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio47_slp_sel:1; - /** gpio47_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio47_mcu_wpd:1; - /** gpio47_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio47_mcu_wpu:1; - /** gpio47_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio47_mcu_ie:1; - /** gpio47_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio47_mcu_drv:2; - /** gpio47_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio47_fun_wpd:1; - /** gpio47_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio47_fun_wpu:1; - /** gpio47_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio47_fun_ie:1; - /** gpio47_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio47_fun_drv:2; - /** gpio47_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio47_mcu_sel:3; - /** gpio47_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio47_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio47_reg_t; - -/** Type of gpio48 register - * iomux control register for gpio48 - */ -typedef union { - struct { - /** gpio48_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio48_mcu_oe:1; - /** gpio48_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio48_slp_sel:1; - /** gpio48_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio48_mcu_wpd:1; - /** gpio48_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio48_mcu_wpu:1; - /** gpio48_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio48_mcu_ie:1; - /** gpio48_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio48_mcu_drv:2; - /** gpio48_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio48_fun_wpd:1; - /** gpio48_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio48_fun_wpu:1; - /** gpio48_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio48_fun_ie:1; - /** gpio48_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio48_fun_drv:2; - /** gpio48_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio48_mcu_sel:3; - /** gpio48_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio48_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio48_reg_t; - -/** Type of gpio49 register - * iomux control register for gpio49 - */ -typedef union { - struct { - /** gpio49_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio49_mcu_oe:1; - /** gpio49_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio49_slp_sel:1; - /** gpio49_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio49_mcu_wpd:1; - /** gpio49_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio49_mcu_wpu:1; - /** gpio49_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio49_mcu_ie:1; - /** gpio49_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio49_mcu_drv:2; - /** gpio49_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio49_fun_wpd:1; - /** gpio49_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio49_fun_wpu:1; - /** gpio49_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio49_fun_ie:1; - /** gpio49_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio49_fun_drv:2; - /** gpio49_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio49_mcu_sel:3; - /** gpio49_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio49_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio49_reg_t; - -/** Type of gpio50 register - * iomux control register for gpio50 - */ -typedef union { - struct { - /** gpio50_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio50_mcu_oe:1; - /** gpio50_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio50_slp_sel:1; - /** gpio50_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio50_mcu_wpd:1; - /** gpio50_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio50_mcu_wpu:1; - /** gpio50_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio50_mcu_ie:1; - /** gpio50_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio50_mcu_drv:2; - /** gpio50_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio50_fun_wpd:1; - /** gpio50_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio50_fun_wpu:1; - /** gpio50_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio50_fun_ie:1; - /** gpio50_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio50_fun_drv:2; - /** gpio50_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio50_mcu_sel:3; - /** gpio50_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio50_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio50_reg_t; - -/** Type of gpio51 register - * iomux control register for gpio51 - */ -typedef union { - struct { - /** gpio51_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio51_mcu_oe:1; - /** gpio51_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio51_slp_sel:1; - /** gpio51_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio51_mcu_wpd:1; - /** gpio51_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio51_mcu_wpu:1; - /** gpio51_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio51_mcu_ie:1; - /** gpio51_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio51_mcu_drv:2; - /** gpio51_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio51_fun_wpd:1; - /** gpio51_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio51_fun_wpu:1; - /** gpio51_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio51_fun_ie:1; - /** gpio51_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio51_fun_drv:2; - /** gpio51_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio51_mcu_sel:3; - /** gpio51_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio51_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio51_reg_t; - -/** Type of gpio52 register - * iomux control register for gpio52 - */ -typedef union { - struct { - /** gpio52_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio52_mcu_oe:1; - /** gpio52_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio52_slp_sel:1; - /** gpio52_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio52_mcu_wpd:1; - /** gpio52_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio52_mcu_wpu:1; - /** gpio52_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio52_mcu_ie:1; - /** gpio52_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio52_mcu_drv:2; - /** gpio52_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio52_fun_wpd:1; - /** gpio52_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio52_fun_wpu:1; - /** gpio52_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio52_fun_ie:1; - /** gpio52_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio52_fun_drv:2; - /** gpio52_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio52_mcu_sel:3; - /** gpio52_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio52_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio52_reg_t; - -/** Type of gpio53 register - * iomux control register for gpio53 - */ -typedef union { - struct { - /** gpio53_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio53_mcu_oe:1; - /** gpio53_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio53_slp_sel:1; - /** gpio53_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio53_mcu_wpd:1; - /** gpio53_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio53_mcu_wpu:1; - /** gpio53_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio53_mcu_ie:1; - /** gpio53_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio53_mcu_drv:2; - /** gpio53_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio53_fun_wpd:1; - /** gpio53_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio53_fun_wpu:1; - /** gpio53_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio53_fun_ie:1; - /** gpio53_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio53_fun_drv:2; - /** gpio53_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio53_mcu_sel:3; - /** gpio53_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio53_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio53_reg_t; - -/** Type of gpio54 register - * iomux control register for gpio54 - */ -typedef union { - struct { - /** gpio54_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio54_mcu_oe:1; - /** gpio54_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio54_slp_sel:1; - /** gpio54_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio54_mcu_wpd:1; - /** gpio54_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio54_mcu_wpu:1; - /** gpio54_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio54_mcu_ie:1; - /** gpio54_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio54_mcu_drv:2; - /** gpio54_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio54_fun_wpd:1; - /** gpio54_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio54_fun_wpu:1; - /** gpio54_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio54_fun_ie:1; - /** gpio54_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio54_fun_drv:2; - /** gpio54_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio54_mcu_sel:3; - /** gpio54_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio54_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio54_reg_t; - -/** Type of gpio55 register - * iomux control register for gpio55 - */ -typedef union { - struct { - /** gpio55_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio55_mcu_oe:1; - /** gpio55_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio55_slp_sel:1; - /** gpio55_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio55_mcu_wpd:1; - /** gpio55_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio55_mcu_wpu:1; - /** gpio55_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio55_mcu_ie:1; - /** gpio55_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio55_mcu_drv:2; - /** gpio55_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio55_fun_wpd:1; - /** gpio55_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio55_fun_wpu:1; - /** gpio55_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio55_fun_ie:1; - /** gpio55_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio55_fun_drv:2; - /** gpio55_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio55_mcu_sel:3; - /** gpio55_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio55_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio55_reg_t; - -/** Type of gpio56 register - * iomux control register for gpio56 - */ -typedef union { - struct { - /** gpio56_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio56_mcu_oe:1; - /** gpio56_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio56_slp_sel:1; - /** gpio56_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio56_mcu_wpd:1; - /** gpio56_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio56_mcu_wpu:1; - /** gpio56_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio56_mcu_ie:1; - /** gpio56_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio56_mcu_drv:2; - /** gpio56_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio56_fun_wpd:1; - /** gpio56_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio56_fun_wpu:1; - /** gpio56_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio56_fun_ie:1; - /** gpio56_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio56_fun_drv:2; - /** gpio56_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio56_mcu_sel:3; - /** gpio56_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio56_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio56_reg_t; - -/** Type of date register - * iomux version - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 2101794; - * csv date - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} io_mux_date_reg_t; - - -typedef struct { - uint32_t reserved_000; - volatile io_mux_gpio0_reg_t gpio0; - volatile io_mux_gpio1_reg_t gpio1; - volatile io_mux_gpio2_reg_t gpio2; - volatile io_mux_gpio3_reg_t gpio3; - volatile io_mux_gpio4_reg_t gpio4; - volatile io_mux_gpio5_reg_t gpio5; - volatile io_mux_gpio6_reg_t gpio6; - volatile io_mux_gpio7_reg_t gpio7; - volatile io_mux_gpio8_reg_t gpio8; - volatile io_mux_gpio9_reg_t gpio9; - volatile io_mux_gpio10_reg_t gpio10; - volatile io_mux_gpio11_reg_t gpio11; - volatile io_mux_gpio12_reg_t gpio12; - volatile io_mux_gpio13_reg_t gpio13; - volatile io_mux_gpio14_reg_t gpio14; - volatile io_mux_gpio15_reg_t gpio15; - volatile io_mux_gpio16_reg_t gpio16; - volatile io_mux_gpio17_reg_t gpio17; - volatile io_mux_gpio18_reg_t gpio18; - volatile io_mux_gpio19_reg_t gpio19; - volatile io_mux_gpio20_reg_t gpio20; - volatile io_mux_gpio21_reg_t gpio21; - volatile io_mux_gpio22_reg_t gpio22; - volatile io_mux_gpio23_reg_t gpio23; - volatile io_mux_gpio24_reg_t gpio24; - volatile io_mux_gpio25_reg_t gpio25; - volatile io_mux_gpio26_reg_t gpio26; - volatile io_mux_gpio27_reg_t gpio27; - volatile io_mux_gpio28_reg_t gpio28; - volatile io_mux_gpio29_reg_t gpio29; - volatile io_mux_gpio30_reg_t gpio30; - volatile io_mux_gpio31_reg_t gpio31; - volatile io_mux_gpio32_reg_t gpio32; - volatile io_mux_gpio33_reg_t gpio33; - volatile io_mux_gpio34_reg_t gpio34; - volatile io_mux_gpio35_reg_t gpio35; - volatile io_mux_gpio36_reg_t gpio36; - volatile io_mux_gpio37_reg_t gpio37; - volatile io_mux_gpio38_reg_t gpio38; - volatile io_mux_gpio39_reg_t gpio39; - volatile io_mux_gpio40_reg_t gpio40; - volatile io_mux_gpio41_reg_t gpio41; - volatile io_mux_gpio42_reg_t gpio42; - volatile io_mux_gpio43_reg_t gpio43; - volatile io_mux_gpio44_reg_t gpio44; - volatile io_mux_gpio45_reg_t gpio45; - volatile io_mux_gpio46_reg_t gpio46; - volatile io_mux_gpio47_reg_t gpio47; - volatile io_mux_gpio48_reg_t gpio48; - volatile io_mux_gpio49_reg_t gpio49; - volatile io_mux_gpio50_reg_t gpio50; - volatile io_mux_gpio51_reg_t gpio51; - volatile io_mux_gpio52_reg_t gpio52; - volatile io_mux_gpio53_reg_t gpio53; - volatile io_mux_gpio54_reg_t gpio54; - volatile io_mux_gpio55_reg_t gpio55; - volatile io_mux_gpio56_reg_t gpio56; - uint32_t reserved_0e8[7]; - volatile io_mux_date_reg_t date; -} io_mux_dev_t; - -extern io_mux_dev_t IO_MUX; - -#ifndef __cplusplus -_Static_assert(sizeof(io_mux_dev_t) == 0x108, "Invalid size of io_mux_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h index b8eac91be1c7..8e9cbb504092 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h @@ -7,8 +7,6 @@ #pragma once #include "soc/soc.h" -//TODO: IDF-13419 - /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ /* Output enable in sleep mode */ #define SLP_OE (BIT(0)) @@ -357,6 +355,7 @@ #define FUNC_GPIO31_GPIO31 1 #define FUNC_GPIO31_GPIO31_0 0 +// Strapping: Diag Group Sel1 #define PERIPHS_IO_MUX_U_PAD_GPIO32 (REG_IO_MUX_BASE + 0x84) #define FUNC_GPIO32_DBG_PSRAM_DQ4_PAD 4 #define FUNC_GPIO32_EMAC_RMII_CLK_PAD 3 @@ -364,6 +363,7 @@ #define FUNC_GPIO32_GPIO32 1 #define FUNC_GPIO32_GPIO32_0 0 +// Strapping: Diag Group Sel0 #define PERIPHS_IO_MUX_U_PAD_GPIO33 (REG_IO_MUX_BASE + 0x88) #define FUNC_GPIO33_DBG_PSRAM_DQ5_PAD 4 #define FUNC_GPIO33_EMAC_PHY_TXEN_PAD 3 @@ -371,6 +371,7 @@ #define FUNC_GPIO33_GPIO33 1 #define FUNC_GPIO33_GPIO33_0 0 +// Strapping: USB2JTAG select: 1->usb2jtag 0-> pad_jtag #define PERIPHS_IO_MUX_U_PAD_GPIO34 (REG_IO_MUX_BASE + 0x8C) #define FUNC_GPIO34_DBG_PSRAM_DQ6_PAD 4 #define FUNC_GPIO34_EMAC_PHY_TXD0_PAD 3 @@ -378,6 +379,7 @@ #define FUNC_GPIO34_GPIO34 1 #define FUNC_GPIO34_GPIO34_0 0 +// Strapping: Boot Mode select 3 #define PERIPHS_IO_MUX_U_PAD_GPIO35 (REG_IO_MUX_BASE + 0x90) #define FUNC_GPIO35_DBG_PSRAM_DQ7_PAD 4 #define FUNC_GPIO35_EMAC_PHY_TXD1_PAD 3 @@ -385,6 +387,7 @@ #define FUNC_GPIO35_GPIO35 1 #define FUNC_GPIO35_GPIO35_0 0 +// Strapping: Boot Mode select 2 #define PERIPHS_IO_MUX_U_PAD_GPIO36 (REG_IO_MUX_BASE + 0x94) #define FUNC_GPIO36_DBG_PSRAM_DQS_0_PAD 4 #define FUNC_GPIO36_EMAC_PHY_TXER_PAD 3 @@ -392,11 +395,13 @@ #define FUNC_GPIO36_GPIO36 1 #define FUNC_GPIO36_GPIO36_0 0 +// Strapping: Boot Mode select 1 #define PERIPHS_IO_MUX_U_PAD_GPIO37 (REG_IO_MUX_BASE + 0x98) #define FUNC_GPIO37_SPI2_IO7_PAD 2 #define FUNC_GPIO37_GPIO37 1 #define FUNC_GPIO37_UART0_TXD_PAD 0 +// Strapping: Boot Mode select 0 #define PERIPHS_IO_MUX_U_PAD_GPIO38 (REG_IO_MUX_BASE + 0x9C) #define FUNC_GPIO38_SPI2_DQS_PAD 2 #define FUNC_GPIO38_GPIO38 1 diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h index b2b0e6630623..e187ba74596c 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h @@ -10,7 +10,6 @@ extern "C" { #endif -//TODO: IDF-13419 /** Type of GPIO register * IO MUX gpio configuration register */ diff --git a/components/soc/esp32p4/register/hw_ver3/soc/isp_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/isp_eco5_struct.h deleted file mode 100644 index ce7d9518aa73..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/isp_eco5_struct.h +++ /dev/null @@ -1,4182 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Version Register */ -/** Type of ver_date register - * version control register - */ -typedef union { - struct { - /** ver_data : R/W; bitpos: [31:0]; default: 539035144; - * csv version - */ - uint32_t ver_data:32; - }; - uint32_t val; -} isp_ver_date_reg_t; - - -/** Group: Configuration Registers */ -/** Type of clk_en register - * isp clk control register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * this bit configures the clk force on of isp reg. 0: disable, 1: enable - */ - uint32_t clk_en:1; - /** clk_blc_force_on : R/W; bitpos: [1]; default: 0; - * this bit configures the clk force on of blc. 0: disable, 1: enable - */ - uint32_t clk_blc_force_on:1; - /** clk_dpc_force_on : R/W; bitpos: [2]; default: 0; - * this bit configures the clk force on of dpc. 0: disable, 1: enable - */ - uint32_t clk_dpc_force_on:1; - /** clk_bf_force_on : R/W; bitpos: [3]; default: 0; - * this bit configures the clk force on of bf. 0: disable, 1: enable - */ - uint32_t clk_bf_force_on:1; - /** clk_lsc_force_on : R/W; bitpos: [4]; default: 0; - * this bit configures the clk force on of lsc. 0: disable, 1: enable - */ - uint32_t clk_lsc_force_on:1; - /** clk_demosaic_force_on : R/W; bitpos: [5]; default: 0; - * this bit configures the clk force on of demosaic. 0: disable, 1: enable - */ - uint32_t clk_demosaic_force_on:1; - /** clk_median_force_on : R/W; bitpos: [6]; default: 0; - * this bit configures the clk force on of median. 0: disable, 1: enable - */ - uint32_t clk_median_force_on:1; - /** clk_ccm_force_on : R/W; bitpos: [7]; default: 0; - * this bit configures the clk force on of ccm. 0: disable, 1: enable - */ - uint32_t clk_ccm_force_on:1; - /** clk_gamma_force_on : R/W; bitpos: [8]; default: 0; - * this bit configures the clk force on of gamma. 0: disable, 1: enable - */ - uint32_t clk_gamma_force_on:1; - /** clk_rgb2yuv_force_on : R/W; bitpos: [9]; default: 0; - * this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable - */ - uint32_t clk_rgb2yuv_force_on:1; - /** clk_sharp_force_on : R/W; bitpos: [10]; default: 0; - * this bit configures the clk force on of sharp. 0: disable, 1: enable - */ - uint32_t clk_sharp_force_on:1; - /** clk_color_force_on : R/W; bitpos: [11]; default: 0; - * this bit configures the clk force on of color. 0: disable, 1: enable - */ - uint32_t clk_color_force_on:1; - /** clk_yuv2rgb_force_on : R/W; bitpos: [12]; default: 0; - * this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable - */ - uint32_t clk_yuv2rgb_force_on:1; - /** clk_ae_force_on : R/W; bitpos: [13]; default: 0; - * this bit configures the clk force on of ae. 0: disable, 1: enable - */ - uint32_t clk_ae_force_on:1; - /** clk_af_force_on : R/W; bitpos: [14]; default: 0; - * this bit configures the clk force on of af. 0: disable, 1: enable - */ - uint32_t clk_af_force_on:1; - /** clk_awb_force_on : R/W; bitpos: [15]; default: 0; - * this bit configures the clk force on of awb. 0: disable, 1: enable - */ - uint32_t clk_awb_force_on:1; - /** clk_hist_force_on : R/W; bitpos: [16]; default: 0; - * this bit configures the clk force on of hist. 0: disable, 1: enable - */ - uint32_t clk_hist_force_on:1; - /** clk_mipi_idi_force_on : R/W; bitpos: [17]; default: 0; - * this bit configures the clk force on of mipi idi input. 0: disable, 1: enable - */ - uint32_t clk_mipi_idi_force_on:1; - /** isp_mem_clk_force_on : R/W; bitpos: [18]; default: 0; - * this bit configures the clk force on of all isp memory. 0: disable, 1: enable - */ - uint32_t isp_mem_clk_force_on:1; - /** clk_crop_force_on : R/W; bitpos: [19]; default: 0; - * this bit configures the clk force on of crop. 0: disable, 1: enable - */ - uint32_t clk_crop_force_on:1; - /** clk_wbg_force_on : R/W; bitpos: [20]; default: 0; - * this bit configures the clk force on of wbg. 0: disable, 1: enable - */ - uint32_t clk_wbg_force_on:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} isp_clk_en_reg_t; - -/** Type of cntl register - * isp module enable control register - */ -typedef union { - struct { - /** mipi_data_en : R/W; bitpos: [0]; default: 0; - * this bit configures mipi input data enable. 0: disable, 1: enable - */ - uint32_t mipi_data_en:1; - /** isp_en : R/W; bitpos: [1]; default: 1; - * this bit configures isp global enable. 0: disable, 1: enable - */ - uint32_t isp_en:1; - /** blc_en : R/W; bitpos: [2]; default: 0; - * this bit configures blc enable. 0: disable, 1: enable - */ - uint32_t blc_en:1; - /** dpc_en : R/W; bitpos: [3]; default: 0; - * this bit configures dpc enable. 0: disable, 1: enable - */ - uint32_t dpc_en:1; - /** bf_en : R/W; bitpos: [4]; default: 0; - * this bit configures bf enable. 0: disable, 1: enable - */ - uint32_t bf_en:1; - /** lsc_en : R/W; bitpos: [5]; default: 0; - * this bit configures lsc enable. 0: disable, 1: enable - */ - uint32_t lsc_en:1; - /** demosaic_en : R/W; bitpos: [6]; default: 1; - * this bit configures demosaic enable. 0: disable, 1: enable - */ - uint32_t demosaic_en:1; - /** median_en : R/W; bitpos: [7]; default: 0; - * this bit configures median enable. 0: disable, 1: enable - */ - uint32_t median_en:1; - /** ccm_en : R/W; bitpos: [8]; default: 0; - * this bit configures ccm enable. 0: disable, 1: enable - */ - uint32_t ccm_en:1; - /** gamma_en : R/W; bitpos: [9]; default: 0; - * this bit configures gamma enable. 0: disable, 1: enable - */ - uint32_t gamma_en:1; - /** rgb2yuv_en : R/W; bitpos: [10]; default: 1; - * this bit configures rgb2yuv enable. 0: disable, 1: enable - */ - uint32_t rgb2yuv_en:1; - /** sharp_en : R/W; bitpos: [11]; default: 0; - * this bit configures sharp enable. 0: disable, 1: enable - */ - uint32_t sharp_en:1; - /** color_en : R/W; bitpos: [12]; default: 0; - * this bit configures color enable. 0: disable, 1: enable - */ - uint32_t color_en:1; - /** yuv2rgb_en : R/W; bitpos: [13]; default: 1; - * this bit configures yuv2rgb enable. 0: disable, 1: enable - */ - uint32_t yuv2rgb_en:1; - /** ae_en : R/W; bitpos: [14]; default: 0; - * this bit configures ae enable. 0: disable, 1: enable - */ - uint32_t ae_en:1; - /** af_en : R/W; bitpos: [15]; default: 0; - * this bit configures af enable. 0: disable, 1: enable - */ - uint32_t af_en:1; - /** awb_en : R/W; bitpos: [16]; default: 0; - * this bit configures awb enable. 0: disable, 1: enable - */ - uint32_t awb_en:1; - /** hist_en : R/W; bitpos: [17]; default: 0; - * this bit configures hist enable. 0: disable, 1: enable - */ - uint32_t hist_en:1; - /** crop_en : R/W; bitpos: [18]; default: 0; - * this bit configures crop enable. 0: disable, 1: enable - */ - uint32_t crop_en:1; - /** wbg_en : R/W; bitpos: [19]; default: 0; - * this bit configures wbg enable. 0: disable, 1: enable - */ - uint32_t wbg_en:1; - uint32_t reserved_20:4; - /** byte_endian_order : R/W; bitpos: [24]; default: 0; - * select input idi data byte_endian_order when isp is bypass, 0: csi_data[31:0], 1: - * {[7:0], [15:8], [23:16], [31:24]} - */ - uint32_t byte_endian_order:1; - /** isp_data_type : R/W; bitpos: [26:25]; default: 0; - * this field configures input data type, 0:RAW8 1:RAW10 2:RAW12 - */ - uint32_t isp_data_type:2; - /** isp_in_src : R/W; bitpos: [28:27]; default: 0; - * this field configures input data source, 0:CSI HOST 1:CAM 2:DMA - */ - uint32_t isp_in_src:2; - /** isp_out_type : R/W; bitpos: [31:29]; default: 2; - * this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4: - * RGB565 - */ - uint32_t isp_out_type:3; - }; - uint32_t val; -} isp_cntl_reg_t; - -/** Type of hsync_cnt register - * header hsync interval control register - */ -typedef union { - struct { - /** hsync_cnt : R/W; bitpos: [7:0]; default: 7; - * this field configures the number of clock before hsync and after vsync and line_end - * when decodes pix data from idi to isp - */ - uint32_t hsync_cnt:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} isp_hsync_cnt_reg_t; - -/** Type of frame_cfg register - * frame control parameter register - */ -typedef union { - struct { - /** vadr_num : R/W; bitpos: [11:0]; default: 480; - * this field configures input image size in y-direction, image row number - 1 - */ - uint32_t vadr_num:12; - /** hadr_num : R/W; bitpos: [23:12]; default: 480; - * this field configures input image size in x-direction, image line number - 1 - */ - uint32_t hadr_num:12; - uint32_t reserved_24:3; - /** bayer_mode : R/W; bitpos: [28:27]; default: 0; - * this field configures the bayer mode of input pixel. 00 : BG/GR 01 : GB/RG 10 - * : GR/BG 11 : RG/GB - */ - uint32_t bayer_mode:2; - /** hsync_start_exist : R/W; bitpos: [29]; default: 1; - * this bit configures the line end packet exist or not. 0: not exist, 1: exist - */ - uint32_t hsync_start_exist:1; - /** hsync_end_exist : R/W; bitpos: [30]; default: 1; - * this bit configures the line start packet exist or not. 0: not exist, 1: exist - */ - uint32_t hsync_end_exist:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} isp_frame_cfg_reg_t; - -/** Type of ccm_coef0 register - * ccm coef register 0 - */ -typedef union { - struct { - /** ccm_rr : R/W; bitpos: [12:0]; default: 256; - * this field configures the color correction matrix coefficient - */ - uint32_t ccm_rr:13; - /** ccm_rg : R/W; bitpos: [25:13]; default: 0; - * this field configures the color correction matrix coefficient - */ - uint32_t ccm_rg:13; - uint32_t reserved_26:6; - }; - uint32_t val; -} isp_ccm_coef0_reg_t; - -/** Type of ccm_coef1 register - * ccm coef register 1 - */ -typedef union { - struct { - /** ccm_rb : R/W; bitpos: [12:0]; default: 0; - * this field configures the color correction matrix coefficient - */ - uint32_t ccm_rb:13; - /** ccm_gr : R/W; bitpos: [25:13]; default: 0; - * this field configures the color correction matrix coefficient - */ - uint32_t ccm_gr:13; - uint32_t reserved_26:6; - }; - uint32_t val; -} isp_ccm_coef1_reg_t; - -/** Type of ccm_coef3 register - * ccm coef register 3 - */ -typedef union { - struct { - /** ccm_gg : R/W; bitpos: [12:0]; default: 256; - * this field configures the color correction matrix coefficient - */ - uint32_t ccm_gg:13; - /** ccm_gb : R/W; bitpos: [25:13]; default: 0; - * this field configures the color correction matrix coefficient - */ - uint32_t ccm_gb:13; - uint32_t reserved_26:6; - }; - uint32_t val; -} isp_ccm_coef3_reg_t; - -/** Type of ccm_coef4 register - * ccm coef register 4 - */ -typedef union { - struct { - /** ccm_br : R/W; bitpos: [12:0]; default: 0; - * this field configures the color correction matrix coefficient - */ - uint32_t ccm_br:13; - /** ccm_bg : R/W; bitpos: [25:13]; default: 0; - * this field configures the color correction matrix coefficient - */ - uint32_t ccm_bg:13; - uint32_t reserved_26:6; - }; - uint32_t val; -} isp_ccm_coef4_reg_t; - -/** Type of ccm_coef5 register - * ccm coef register 5 - */ -typedef union { - struct { - /** ccm_bb : R/W; bitpos: [12:0]; default: 256; - * this field configures the color correction matrix coefficient - */ - uint32_t ccm_bb:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} isp_ccm_coef5_reg_t; - -/** Type of bf_matrix_ctrl register - * bf pix2matrix ctrl - */ -typedef union { - struct { - /** bf_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0; - * matrix tail pixen low level threshold, should not to large to prevent expanding to - * next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 - * and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse - * function - */ - uint32_t bf_tail_pixen_pulse_tl:8; - /** bf_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0; - * matrix tail pixen high level threshold, must < hnum-1, only - * reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and - * reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse - * function - */ - uint32_t bf_tail_pixen_pulse_th:8; - /** bf_padding_data : R/W; bitpos: [23:16]; default: 0; - * this field configures bf matrix padding data - */ - uint32_t bf_padding_data:8; - /** bf_padding_mode : R/W; bitpos: [24]; default: 0; - * this bit configures the padding mode of bf matrix. 0: use pixel in image to do - * padding 1: use reg_padding_data to do padding - */ - uint32_t bf_padding_mode:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} isp_bf_matrix_ctrl_reg_t; - -/** Type of bf_sigma register - * bf denoising level control register - */ -typedef union { - struct { - /** sigma : R/W; bitpos: [5:0]; default: 2; - * this field configures the bayer denoising level, valid data from 2 to 20 - */ - uint32_t sigma:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} isp_bf_sigma_reg_t; - -/** Type of bf_gau0 register - * bf gau template register 0 - */ -typedef union { - struct { - /** gau_template21 : R/W; bitpos: [3:0]; default: 15; - * this field configures index 21 of gaussian template - */ - uint32_t gau_template21:4; - /** gau_template20 : R/W; bitpos: [7:4]; default: 15; - * this field configures index 20 of gaussian template - */ - uint32_t gau_template20:4; - /** gau_template12 : R/W; bitpos: [11:8]; default: 15; - * this field configures index 12 of gaussian template - */ - uint32_t gau_template12:4; - /** gau_template11 : R/W; bitpos: [15:12]; default: 15; - * this field configures index 11 of gaussian template - */ - uint32_t gau_template11:4; - /** gau_template10 : R/W; bitpos: [19:16]; default: 15; - * this field configures index 10 of gaussian template - */ - uint32_t gau_template10:4; - /** gau_template02 : R/W; bitpos: [23:20]; default: 15; - * this field configures index 02 of gaussian template - */ - uint32_t gau_template02:4; - /** gau_template01 : R/W; bitpos: [27:24]; default: 15; - * this field configures index 01 of gaussian template - */ - uint32_t gau_template01:4; - /** gau_template00 : R/W; bitpos: [31:28]; default: 15; - * this field configures index 00 of gaussian template - */ - uint32_t gau_template00:4; - }; - uint32_t val; -} isp_bf_gau0_reg_t; - -/** Type of bf_gau1 register - * bf gau template register 1 - */ -typedef union { - struct { - /** gau_template22 : R/W; bitpos: [3:0]; default: 15; - * this field configures index 22 of gaussian template - */ - uint32_t gau_template22:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} isp_bf_gau1_reg_t; - -/** Type of dpc_ctrl register - * DPC mode control register - */ -typedef union { - struct { - /** dpc_check_en : R/W; bitpos: [0]; default: 0; - * this bit configures the check mode enable. 0: disable, 1: enable - */ - uint32_t dpc_check_en:1; - /** sta_en : R/W; bitpos: [1]; default: 0; - * this bit configures the sta dpc enable. 0: disable, 1: enable - */ - uint32_t sta_en:1; - /** dyn_en : R/W; bitpos: [2]; default: 1; - * this bit configures the dyn dpc enable. 0: disable, 1: enable - */ - uint32_t dyn_en:1; - /** dpc_black_en : R/W; bitpos: [3]; default: 0; - * this bit configures input image type select when in check mode, 0: white img, 1: - * black img - */ - uint32_t dpc_black_en:1; - /** dpc_method_sel : R/W; bitpos: [4]; default: 0; - * this bit configures dyn dpc method select. 0: simple method, 1: hard method - */ - uint32_t dpc_method_sel:1; - /** dpc_check_od_en : R/W; bitpos: [5]; default: 0; - * this bit configures output pixel data when in check mode or not. 0: no data output, - * 1: data output - */ - uint32_t dpc_check_od_en:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} isp_dpc_ctrl_reg_t; - -/** Type of dpc_conf register - * DPC parameter config register - */ -typedef union { - struct { - /** dpc_threshold_l : R/W; bitpos: [7:0]; default: 48; - * this bit configures the threshold to detect black img in check mode, or the low - * threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit - * 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 - */ - uint32_t dpc_threshold_l:8; - /** dpc_threshold_h : R/W; bitpos: [15:8]; default: 48; - * this bit configures the threshold to detect white img in check mode, or the high - * threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit - * 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 - */ - uint32_t dpc_threshold_h:8; - /** dpc_factor_dark : R/W; bitpos: [21:16]; default: 16; - * this field configures the dynamic correction method 1 dark factor - */ - uint32_t dpc_factor_dark:6; - /** dpc_factor_brig : R/W; bitpos: [27:22]; default: 16; - * this field configures the dynamic correction method 1 bright factor - */ - uint32_t dpc_factor_brig:6; - uint32_t reserved_28:4; - }; - uint32_t val; -} isp_dpc_conf_reg_t; - -/** Type of dpc_matrix_ctrl register - * dpc pix2matrix ctrl - */ -typedef union { - struct { - /** dpc_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0; - * matrix tail pixen low level threshold, should not to large to prevent expanding to - * next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 - * and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail - * pulse function - */ - uint32_t dpc_tail_pixen_pulse_tl:8; - /** dpc_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0; - * matrix tail pixen high level threshold, must < hnum-1, only - * reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and - * reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse - * function - */ - uint32_t dpc_tail_pixen_pulse_th:8; - /** dpc_padding_data : R/W; bitpos: [23:16]; default: 0; - * this field configures dpc matrix padding data - */ - uint32_t dpc_padding_data:8; - /** dpc_padding_mode : R/W; bitpos: [24]; default: 0; - * this bit configures the padding mode of dpc matrix. 0: use pixel in image to do - * padding 1: use reg_padding_data to do padding - */ - uint32_t dpc_padding_mode:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} isp_dpc_matrix_ctrl_reg_t; - -/** Type of lut_cmd register - * LUT command register - */ -typedef union { - struct { - /** lut_addr : WT; bitpos: [11:0]; default: 0; - * this field configures the lut access addr, when select lsc lut, [11:10]:00 sel gb_b - * lut, 01 sel r_gr lut - */ - uint32_t lut_addr:12; - /** lut_num : WT; bitpos: [15:12]; default: 0; - * this field configures the lut selection. 0000:LSC LUT. 0001:DPC LUT. 0010:AWB LUT - */ - uint32_t lut_num:4; - /** lut_cmd : WT; bitpos: [16]; default: 0; - * this bit configures the access event of lut. 0:rd 1: wr - */ - uint32_t lut_cmd:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_lut_cmd_reg_t; - -/** Type of lut_wdata register - * LUT write data register - */ -typedef union { - struct { - /** lut_wdata : R/W; bitpos: [31:0]; default: 0; - * this field configures the write data of lut. please initial ISP_LUT_WDATA before - * write ISP_LUT_CMD register - */ - uint32_t lut_wdata:32; - }; - uint32_t val; -} isp_lut_wdata_reg_t; - -/** Type of lsc_tablesize register - * LSC point in x-direction - */ -typedef union { - struct { - /** lsc_xtablesize : R/W; bitpos: [4:0]; default: 31; - * this field configures lsc table size in x-direction - */ - uint32_t lsc_xtablesize:5; - uint32_t reserved_5:27; - }; - uint32_t val; -} isp_lsc_tablesize_reg_t; - -/** Type of demosaic_matrix_ctrl register - * demosaic pix2matrix ctrl - */ -typedef union { - struct { - /** demosaic_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0; - * matrix tail pixen low level threshold, should not to large to prevent expanding to - * next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and - * reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < - * reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function - */ - uint32_t demosaic_tail_pixen_pulse_tl:8; - /** demosaic_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0; - * matrix tail pixen high level threshold, must < hnum-1, only - * reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and - * reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable - * tail pulse function - */ - uint32_t demosaic_tail_pixen_pulse_th:8; - /** demosaic_padding_data : R/W; bitpos: [23:16]; default: 0; - * this field configures demosaic matrix padding data - */ - uint32_t demosaic_padding_data:8; - /** demosaic_padding_mode : R/W; bitpos: [24]; default: 0; - * this bit configures the padding mode of demosaic matrix. 0: use pixel in image to - * do padding 1: use reg_padding_data to do padding - */ - uint32_t demosaic_padding_mode:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} isp_demosaic_matrix_ctrl_reg_t; - -/** Type of demosaic_grad_ratio register - * demosaic gradient select ratio - */ -typedef union { - struct { - /** demosaic_grad_ratio : R/W; bitpos: [5:0]; default: 16; - * this field configures demosaic gradient select ratio - */ - uint32_t demosaic_grad_ratio:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} isp_demosaic_grad_ratio_reg_t; - -/** Type of median_matrix_ctrl register - * median pix2matrix ctrl - */ -typedef union { - struct { - /** median_padding_data : R/W; bitpos: [7:0]; default: 0; - * this field configures median matrix padding data - */ - uint32_t median_padding_data:8; - /** median_padding_mode : R/W; bitpos: [8]; default: 0; - * this bit configures the padding mode of median matrix. 0: use pixel in image to do - * padding 1: use reg_padding_data to do padding - */ - uint32_t median_padding_mode:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} isp_median_matrix_ctrl_reg_t; - -/** Type of gamma_ctrl register - * gamma control register - */ -typedef union { - struct { - /** gamma_update : R/W; bitpos: [0]; default: 0; - * Indicates that gamma register configuration is complete - */ - uint32_t gamma_update:1; - /** gamma_b_last_correct : R/W; bitpos: [1]; default: 1; - * this bit configures enable of last b segment correcction. 0: disable, 1: enable - */ - uint32_t gamma_b_last_correct:1; - /** gamma_g_last_correct : R/W; bitpos: [2]; default: 1; - * this bit configures enable of last g segment correcction. 0: disable, 1: enable - */ - uint32_t gamma_g_last_correct:1; - /** gamma_r_last_correct : R/W; bitpos: [3]; default: 1; - * this bit configures enable of last r segment correcction. 0: disable, 1: enable - */ - uint32_t gamma_r_last_correct:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} isp_gamma_ctrl_reg_t; - -/** Type of gamma_ry1 register - * point of Y-axis of r channel gamma curve register 1 - */ -typedef union { - struct { - /** gamma_r_y03 : R/W; bitpos: [7:0]; default: 64; - * this field configures the point 3 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y03:8; - /** gamma_r_y02 : R/W; bitpos: [15:8]; default: 48; - * this field configures the point 2 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y02:8; - /** gamma_r_y01 : R/W; bitpos: [23:16]; default: 32; - * this field configures the point 1 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y01:8; - /** gamma_r_y00 : R/W; bitpos: [31:24]; default: 16; - * this field configures the point 0 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y00:8; - }; - uint32_t val; -} isp_gamma_ry1_reg_t; - -/** Type of gamma_ry2 register - * point of Y-axis of r channel gamma curve register 2 - */ -typedef union { - struct { - /** gamma_r_y07 : R/W; bitpos: [7:0]; default: 128; - * this field configures the point 7 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y07:8; - /** gamma_r_y06 : R/W; bitpos: [15:8]; default: 112; - * this field configures the point 6 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y06:8; - /** gamma_r_y05 : R/W; bitpos: [23:16]; default: 96; - * this field configures the point 5 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y05:8; - /** gamma_r_y04 : R/W; bitpos: [31:24]; default: 80; - * this field configures the point 4 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y04:8; - }; - uint32_t val; -} isp_gamma_ry2_reg_t; - -/** Type of gamma_ry3 register - * point of Y-axis of r channel gamma curve register 3 - */ -typedef union { - struct { - /** gamma_r_y0b : R/W; bitpos: [7:0]; default: 192; - * this field configures the point 11 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y0b:8; - /** gamma_r_y0a : R/W; bitpos: [15:8]; default: 176; - * this field configures the point 10 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y0a:8; - /** gamma_r_y09 : R/W; bitpos: [23:16]; default: 160; - * this field configures the point 9 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y09:8; - /** gamma_r_y08 : R/W; bitpos: [31:24]; default: 144; - * this field configures the point 8 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y08:8; - }; - uint32_t val; -} isp_gamma_ry3_reg_t; - -/** Type of gamma_ry4 register - * point of Y-axis of r channel gamma curve register 4 - */ -typedef union { - struct { - /** gamma_r_y0f : R/W; bitpos: [7:0]; default: 255; - * this field configures the point 15 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y0f:8; - /** gamma_r_y0e : R/W; bitpos: [15:8]; default: 240; - * this field configures the point 14 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y0e:8; - /** gamma_r_y0d : R/W; bitpos: [23:16]; default: 224; - * this field configures the point 13 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y0d:8; - /** gamma_r_y0c : R/W; bitpos: [31:24]; default: 208; - * this field configures the point 12 of Y-axis of r channel gamma curve - */ - uint32_t gamma_r_y0c:8; - }; - uint32_t val; -} isp_gamma_ry4_reg_t; - -/** Type of gamma_gy1 register - * point of Y-axis of g channel gamma curve register 1 - */ -typedef union { - struct { - /** gamma_g_y03 : R/W; bitpos: [7:0]; default: 64; - * this field configures the point 3 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y03:8; - /** gamma_g_y02 : R/W; bitpos: [15:8]; default: 48; - * this field configures the point 2 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y02:8; - /** gamma_g_y01 : R/W; bitpos: [23:16]; default: 32; - * this field configures the point 1 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y01:8; - /** gamma_g_y00 : R/W; bitpos: [31:24]; default: 16; - * this field configures the point 0 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y00:8; - }; - uint32_t val; -} isp_gamma_gy1_reg_t; - -/** Type of gamma_gy2 register - * point of Y-axis of g channel gamma curve register 2 - */ -typedef union { - struct { - /** gamma_g_y07 : R/W; bitpos: [7:0]; default: 128; - * this field configures the point 7 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y07:8; - /** gamma_g_y06 : R/W; bitpos: [15:8]; default: 112; - * this field configures the point 6 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y06:8; - /** gamma_g_y05 : R/W; bitpos: [23:16]; default: 96; - * this field configures the point 5 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y05:8; - /** gamma_g_y04 : R/W; bitpos: [31:24]; default: 80; - * this field configures the point 4 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y04:8; - }; - uint32_t val; -} isp_gamma_gy2_reg_t; - -/** Type of gamma_gy3 register - * point of Y-axis of g channel gamma curve register 3 - */ -typedef union { - struct { - /** gamma_g_y0b : R/W; bitpos: [7:0]; default: 192; - * this field configures the point 11 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y0b:8; - /** gamma_g_y0a : R/W; bitpos: [15:8]; default: 176; - * this field configures the point 10 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y0a:8; - /** gamma_g_y09 : R/W; bitpos: [23:16]; default: 160; - * this field configures the point 9 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y09:8; - /** gamma_g_y08 : R/W; bitpos: [31:24]; default: 144; - * this field configures the point 8 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y08:8; - }; - uint32_t val; -} isp_gamma_gy3_reg_t; - -/** Type of gamma_gy4 register - * point of Y-axis of g channel gamma curve register 4 - */ -typedef union { - struct { - /** gamma_g_y0f : R/W; bitpos: [7:0]; default: 255; - * this field configures the point 15 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y0f:8; - /** gamma_g_y0e : R/W; bitpos: [15:8]; default: 240; - * this field configures the point 14 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y0e:8; - /** gamma_g_y0d : R/W; bitpos: [23:16]; default: 224; - * this field configures the point 13 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y0d:8; - /** gamma_g_y0c : R/W; bitpos: [31:24]; default: 208; - * this field configures the point 12 of Y-axis of g channel gamma curve - */ - uint32_t gamma_g_y0c:8; - }; - uint32_t val; -} isp_gamma_gy4_reg_t; - -/** Type of gamma_by1 register - * point of Y-axis of b channel gamma curve register 1 - */ -typedef union { - struct { - /** gamma_b_y03 : R/W; bitpos: [7:0]; default: 64; - * this field configures the point 3 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y03:8; - /** gamma_b_y02 : R/W; bitpos: [15:8]; default: 48; - * this field configures the point 2 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y02:8; - /** gamma_b_y01 : R/W; bitpos: [23:16]; default: 32; - * this field configures the point 1 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y01:8; - /** gamma_b_y00 : R/W; bitpos: [31:24]; default: 16; - * this field configures the point 0 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y00:8; - }; - uint32_t val; -} isp_gamma_by1_reg_t; - -/** Type of gamma_by2 register - * point of Y-axis of b channel gamma curve register 2 - */ -typedef union { - struct { - /** gamma_b_y07 : R/W; bitpos: [7:0]; default: 128; - * this field configures the point 7 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y07:8; - /** gamma_b_y06 : R/W; bitpos: [15:8]; default: 112; - * this field configures the point 6 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y06:8; - /** gamma_b_y05 : R/W; bitpos: [23:16]; default: 96; - * this field configures the point 5 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y05:8; - /** gamma_b_y04 : R/W; bitpos: [31:24]; default: 80; - * this field configures the point 4 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y04:8; - }; - uint32_t val; -} isp_gamma_by2_reg_t; - -/** Type of gamma_by3 register - * point of Y-axis of b channel gamma curve register 3 - */ -typedef union { - struct { - /** gamma_b_y0b : R/W; bitpos: [7:0]; default: 192; - * this field configures the point 11 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y0b:8; - /** gamma_b_y0a : R/W; bitpos: [15:8]; default: 176; - * this field configures the point 10 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y0a:8; - /** gamma_b_y09 : R/W; bitpos: [23:16]; default: 160; - * this field configures the point 9 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y09:8; - /** gamma_b_y08 : R/W; bitpos: [31:24]; default: 144; - * this field configures the point 8 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y08:8; - }; - uint32_t val; -} isp_gamma_by3_reg_t; - -/** Type of gamma_by4 register - * point of Y-axis of b channel gamma curve register 4 - */ -typedef union { - struct { - /** gamma_b_y0f : R/W; bitpos: [7:0]; default: 255; - * this field configures the point 15 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y0f:8; - /** gamma_b_y0e : R/W; bitpos: [15:8]; default: 240; - * this field configures the point 14 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y0e:8; - /** gamma_b_y0d : R/W; bitpos: [23:16]; default: 224; - * this field configures the point 13 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y0d:8; - /** gamma_b_y0c : R/W; bitpos: [31:24]; default: 208; - * this field configures the point 12 of Y-axis of b channel gamma curve - */ - uint32_t gamma_b_y0c:8; - }; - uint32_t val; -} isp_gamma_by4_reg_t; - -/** Type of gamma_rx1 register - * point of X-axis of r channel gamma curve register 1 - */ -typedef union { - struct { - /** gamma_r_x07 : R/W; bitpos: [2:0]; default: 4; - * this field configures the point 7 of X-axis of r channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_r_x07:3; - /** gamma_r_x06 : R/W; bitpos: [5:3]; default: 4; - * this field configures the point 6 of X-axis of r channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_r_x06:3; - /** gamma_r_x05 : R/W; bitpos: [8:6]; default: 4; - * this field configures the point 5 of X-axis of r channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_r_x05:3; - /** gamma_r_x04 : R/W; bitpos: [11:9]; default: 4; - * this field configures the point 4 of X-axis of r channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_r_x04:3; - /** gamma_r_x03 : R/W; bitpos: [14:12]; default: 4; - * this field configures the point 3 of X-axis of r channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_r_x03:3; - /** gamma_r_x02 : R/W; bitpos: [17:15]; default: 4; - * this field configures the point 2 of X-axis of r channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_r_x02:3; - /** gamma_r_x01 : R/W; bitpos: [20:18]; default: 4; - * this field configures the point 1 of X-axis of r channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_r_x01:3; - /** gamma_r_x00 : R/W; bitpos: [23:21]; default: 4; - * this field configures the point 0 of X-axis of r channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_r_x00:3; - uint32_t reserved_24:8; - }; - uint32_t val; -} isp_gamma_rx1_reg_t; - -/** Type of gamma_rx2 register - * point of X-axis of r channel gamma curve register 2 - */ -typedef union { - struct { - /** gamma_r_x0f : R/W; bitpos: [2:0]; default: 4; - * this field configures the point 15 of X-axis of r channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_r_x0f:3; - /** gamma_r_x0e : R/W; bitpos: [5:3]; default: 4; - * this field configures the point 14 of X-axis of r channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_r_x0e:3; - /** gamma_r_x0d : R/W; bitpos: [8:6]; default: 4; - * this field configures the point 13 of X-axis of r channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_r_x0d:3; - /** gamma_r_x0c : R/W; bitpos: [11:9]; default: 4; - * this field configures the point 12 of X-axis of r channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_r_x0c:3; - /** gamma_r_x0b : R/W; bitpos: [14:12]; default: 4; - * this field configures the point 11 of X-axis of r channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_r_x0b:3; - /** gamma_r_x0a : R/W; bitpos: [17:15]; default: 4; - * this field configures the point 10 of X-axis of r channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_r_x0a:3; - /** gamma_r_x09 : R/W; bitpos: [20:18]; default: 4; - * this field configures the point 9 of X-axis of r channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_r_x09:3; - /** gamma_r_x08 : R/W; bitpos: [23:21]; default: 4; - * this field configures the point 8 of X-axis of r channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_r_x08:3; - uint32_t reserved_24:8; - }; - uint32_t val; -} isp_gamma_rx2_reg_t; - -/** Type of gamma_gx1 register - * point of X-axis of g channel gamma curve register 1 - */ -typedef union { - struct { - /** gamma_g_x07 : R/W; bitpos: [2:0]; default: 4; - * this field configures the point 7 of X-axis of g channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_g_x07:3; - /** gamma_g_x06 : R/W; bitpos: [5:3]; default: 4; - * this field configures the point 6 of X-axis of g channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_g_x06:3; - /** gamma_g_x05 : R/W; bitpos: [8:6]; default: 4; - * this field configures the point 5 of X-axis of g channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_g_x05:3; - /** gamma_g_x04 : R/W; bitpos: [11:9]; default: 4; - * this field configures the point 4 of X-axis of g channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_g_x04:3; - /** gamma_g_x03 : R/W; bitpos: [14:12]; default: 4; - * this field configures the point 3 of X-axis of g channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_g_x03:3; - /** gamma_g_x02 : R/W; bitpos: [17:15]; default: 4; - * this field configures the point 2 of X-axis of g channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_g_x02:3; - /** gamma_g_x01 : R/W; bitpos: [20:18]; default: 4; - * this field configures the point 1 of X-axis of g channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_g_x01:3; - /** gamma_g_x00 : R/W; bitpos: [23:21]; default: 4; - * this field configures the point 0 of X-axis of g channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_g_x00:3; - uint32_t reserved_24:8; - }; - uint32_t val; -} isp_gamma_gx1_reg_t; - -/** Type of gamma_gx2 register - * point of X-axis of g channel gamma curve register 2 - */ -typedef union { - struct { - /** gamma_g_x0f : R/W; bitpos: [2:0]; default: 4; - * this field configures the point 15 of X-axis of g channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_g_x0f:3; - /** gamma_g_x0e : R/W; bitpos: [5:3]; default: 4; - * this field configures the point 14 of X-axis of g channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_g_x0e:3; - /** gamma_g_x0d : R/W; bitpos: [8:6]; default: 4; - * this field configures the point 13 of X-axis of g channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_g_x0d:3; - /** gamma_g_x0c : R/W; bitpos: [11:9]; default: 4; - * this field configures the point 12 of X-axis of g channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_g_x0c:3; - /** gamma_g_x0b : R/W; bitpos: [14:12]; default: 4; - * this field configures the point 11 of X-axis of g channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_g_x0b:3; - /** gamma_g_x0a : R/W; bitpos: [17:15]; default: 4; - * this field configures the point 10 of X-axis of g channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_g_x0a:3; - /** gamma_g_x09 : R/W; bitpos: [20:18]; default: 4; - * this field configures the point 9 of X-axis of g channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_g_x09:3; - /** gamma_g_x08 : R/W; bitpos: [23:21]; default: 4; - * this field configures the point 8 of X-axis of g channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_g_x08:3; - uint32_t reserved_24:8; - }; - uint32_t val; -} isp_gamma_gx2_reg_t; - -/** Type of gamma_bx1 register - * point of X-axis of b channel gamma curve register 1 - */ -typedef union { - struct { - /** gamma_b_x07 : R/W; bitpos: [2:0]; default: 4; - * this field configures the point 7 of X-axis of b channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_b_x07:3; - /** gamma_b_x06 : R/W; bitpos: [5:3]; default: 4; - * this field configures the point 6 of X-axis of b channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_b_x06:3; - /** gamma_b_x05 : R/W; bitpos: [8:6]; default: 4; - * this field configures the point 5 of X-axis of b channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_b_x05:3; - /** gamma_b_x04 : R/W; bitpos: [11:9]; default: 4; - * this field configures the point 4 of X-axis of b channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_b_x04:3; - /** gamma_b_x03 : R/W; bitpos: [14:12]; default: 4; - * this field configures the point 3 of X-axis of b channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_b_x03:3; - /** gamma_b_x02 : R/W; bitpos: [17:15]; default: 4; - * this field configures the point 2 of X-axis of b channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_b_x02:3; - /** gamma_b_x01 : R/W; bitpos: [20:18]; default: 4; - * this field configures the point 1 of X-axis of b channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_b_x01:3; - /** gamma_b_x00 : R/W; bitpos: [23:21]; default: 4; - * this field configures the point 0 of X-axis of b channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_b_x00:3; - uint32_t reserved_24:8; - }; - uint32_t val; -} isp_gamma_bx1_reg_t; - -/** Type of gamma_bx2 register - * point of X-axis of b channel gamma curve register 2 - */ -typedef union { - struct { - /** gamma_b_x0f : R/W; bitpos: [2:0]; default: 4; - * this field configures the point 15 of X-axis of b channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_b_x0f:3; - /** gamma_b_x0e : R/W; bitpos: [5:3]; default: 4; - * this field configures the point 14 of X-axis of b channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_b_x0e:3; - /** gamma_b_x0d : R/W; bitpos: [8:6]; default: 4; - * this field configures the point 13 of X-axis of b channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_b_x0d:3; - /** gamma_b_x0c : R/W; bitpos: [11:9]; default: 4; - * this field configures the point 12 of X-axis of b channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_b_x0c:3; - /** gamma_b_x0b : R/W; bitpos: [14:12]; default: 4; - * this field configures the point 11 of X-axis of b channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_b_x0b:3; - /** gamma_b_x0a : R/W; bitpos: [17:15]; default: 4; - * this field configures the point 10 of X-axis of b channel gamma curve, it - * represents the power of the distance from the previous point - */ - uint32_t gamma_b_x0a:3; - /** gamma_b_x09 : R/W; bitpos: [20:18]; default: 4; - * this field configures the point 9 of X-axis of b channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_b_x09:3; - /** gamma_b_x08 : R/W; bitpos: [23:21]; default: 4; - * this field configures the point 8 of X-axis of b channel gamma curve, it represents - * the power of the distance from the previous point - */ - uint32_t gamma_b_x08:3; - uint32_t reserved_24:8; - }; - uint32_t val; -} isp_gamma_bx2_reg_t; - -/** Type of ae_ctrl register - * ae control register - */ -typedef union { - struct { - /** ae_update : WT; bitpos: [0]; default: 0; - * write 1 to this bit triggers one statistic event - */ - uint32_t ae_update:1; - /** ae_select : R/W; bitpos: [1]; default: 0; - * this field configures ae input data source, 0: data from median, 1: data from gama - */ - uint32_t ae_select:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} isp_ae_ctrl_reg_t; - -/** Type of ae_monitor register - * ae monitor control register - */ -typedef union { - struct { - /** ae_monitor_tl : R/W; bitpos: [7:0]; default: 0; - * this field configures the lower lum threshold of ae monitor - */ - uint32_t ae_monitor_tl:8; - /** ae_monitor_th : R/W; bitpos: [15:8]; default: 0; - * this field configures the higher lum threshold of ae monitor - */ - uint32_t ae_monitor_th:8; - /** ae_monitor_period : R/W; bitpos: [21:16]; default: 0; - * this field configures ae monitor frame period - */ - uint32_t ae_monitor_period:6; - uint32_t reserved_22:10; - }; - uint32_t val; -} isp_ae_monitor_reg_t; - -/** Type of ae_bx register - * ae window register in x-direction - */ -typedef union { - struct { - /** ae_x_bsize : R/W; bitpos: [10:0]; default: 384; - * this field configures every block x size - */ - uint32_t ae_x_bsize:11; - /** ae_x_start : R/W; bitpos: [21:11]; default: 0; - * this field configures first block start x address - */ - uint32_t ae_x_start:11; - uint32_t reserved_22:10; - }; - uint32_t val; -} isp_ae_bx_reg_t; - -/** Type of ae_by register - * ae window register in y-direction - */ -typedef union { - struct { - /** ae_y_bsize : R/W; bitpos: [10:0]; default: 216; - * this field configures every block y size - */ - uint32_t ae_y_bsize:11; - /** ae_y_start : R/W; bitpos: [21:11]; default: 0; - * this field configures first block start y address - */ - uint32_t ae_y_start:11; - uint32_t reserved_22:10; - }; - uint32_t val; -} isp_ae_by_reg_t; - -/** Type of ae_winpixnum register - * ae sub-window pix num register - */ -typedef union { - struct { - /** ae_subwin_pixnum : R/W; bitpos: [16:0]; default: 82944; - * this field configures the pixel number of each sub win - */ - uint32_t ae_subwin_pixnum:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_ae_winpixnum_reg_t; - -/** Type of ae_win_reciprocal register - * reciprocal of ae sub-window pixel number - */ -typedef union { - struct { - /** ae_subwin_recip : R/W; bitpos: [19:0]; default: 0; - * this field configures the reciprocal of each subwin_pixnum, 20bit fraction - */ - uint32_t ae_subwin_recip:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} isp_ae_win_reciprocal_reg_t; - -/** Type of sharp_ctrl0 register - * sharp control register 0 - */ -typedef union { - struct { - /** sharp_threshold_low : R/W; bitpos: [7:0]; default: 0; - * this field configures sharpen threshold for detail - */ - uint32_t sharp_threshold_low:8; - /** sharp_threshold_high : R/W; bitpos: [15:8]; default: 0; - * this field configures sharpen threshold for edge - */ - uint32_t sharp_threshold_high:8; - /** sharp_amount_low : R/W; bitpos: [23:16]; default: 0; - * this field configures sharpen amount for detail - */ - uint32_t sharp_amount_low:8; - /** sharp_amount_high : R/W; bitpos: [31:24]; default: 0; - * this field configures sharpen amount for edge - */ - uint32_t sharp_amount_high:8; - }; - uint32_t val; -} isp_sharp_ctrl0_reg_t; - -/** Type of sharp_filter0 register - * sharp usm config register 0 - */ -typedef union { - struct { - /** sharp_filter_coe00 : R/W; bitpos: [4:0]; default: 1; - * this field configures unsharp masking(usm) filter coefficient - */ - uint32_t sharp_filter_coe00:5; - /** sharp_filter_coe01 : R/W; bitpos: [9:5]; default: 2; - * this field configures usm filter coefficient - */ - uint32_t sharp_filter_coe01:5; - /** sharp_filter_coe02 : R/W; bitpos: [14:10]; default: 1; - * this field configures usm filter coefficient - */ - uint32_t sharp_filter_coe02:5; - uint32_t reserved_15:17; - }; - uint32_t val; -} isp_sharp_filter0_reg_t; - -/** Type of sharp_filter1 register - * sharp usm config register 1 - */ -typedef union { - struct { - /** sharp_filter_coe10 : R/W; bitpos: [4:0]; default: 2; - * this field configures usm filter coefficient - */ - uint32_t sharp_filter_coe10:5; - /** sharp_filter_coe11 : R/W; bitpos: [9:5]; default: 4; - * this field configures usm filter coefficient - */ - uint32_t sharp_filter_coe11:5; - /** sharp_filter_coe12 : R/W; bitpos: [14:10]; default: 2; - * this field configures usm filter coefficient - */ - uint32_t sharp_filter_coe12:5; - uint32_t reserved_15:17; - }; - uint32_t val; -} isp_sharp_filter1_reg_t; - -/** Type of sharp_filter2 register - * sharp usm config register 2 - */ -typedef union { - struct { - /** sharp_filter_coe20 : R/W; bitpos: [4:0]; default: 1; - * this field configures usm filter coefficient - */ - uint32_t sharp_filter_coe20:5; - /** sharp_filter_coe21 : R/W; bitpos: [9:5]; default: 2; - * this field configures usm filter coefficient - */ - uint32_t sharp_filter_coe21:5; - /** sharp_filter_coe22 : R/W; bitpos: [14:10]; default: 1; - * this field configures usm filter coefficient - */ - uint32_t sharp_filter_coe22:5; - uint32_t reserved_15:17; - }; - uint32_t val; -} isp_sharp_filter2_reg_t; - -/** Type of sharp_matrix_ctrl register - * sharp pix2matrix ctrl - */ -typedef union { - struct { - /** sharp_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0; - * matrix tail pixen low level threshold, should not to large to prevent expanding to - * next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and - * reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < - * reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function - */ - uint32_t sharp_tail_pixen_pulse_tl:8; - /** sharp_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0; - * matrix tail pixen high level threshold, must < hnum-1, only - * reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and - * reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail - * pulse function - */ - uint32_t sharp_tail_pixen_pulse_th:8; - /** sharp_padding_data : R/W; bitpos: [23:16]; default: 0; - * this field configures sharp padding data - */ - uint32_t sharp_padding_data:8; - /** sharp_padding_mode : R/W; bitpos: [24]; default: 0; - * this field configures sharp padding mode - */ - uint32_t sharp_padding_mode:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} isp_sharp_matrix_ctrl_reg_t; - -/** Type of sharp_ctrl1 register - * sharp control register 1 - */ -typedef union { - struct { - /** sharp_gradient_max : RO; bitpos: [7:0]; default: 0; - * this field configures sharp max gradient, refresh at the end of each frame end - */ - uint32_t sharp_gradient_max:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} isp_sharp_ctrl1_reg_t; - -/** Type of dma_cntl register - * isp dma source trans control register - */ -typedef union { - struct { - /** dma_en : WT; bitpos: [0]; default: 0; - * write 1 to trigger dma to get 1 frame - */ - uint32_t dma_en:1; - /** dma_update_reg : R/W; bitpos: [1]; default: 0; - * write 1 to update reg_dma_burst_len & reg_dma_data_type - */ - uint32_t dma_update_reg:1; - /** dma_data_type : R/W; bitpos: [7:2]; default: 42; - * this field configures the idi data type for image data - */ - uint32_t dma_data_type:6; - /** dma_burst_len : R/W; bitpos: [19:8]; default: 128; - * this field configures dma burst len when data source is dma. set according to - * dma_msize, it is the number of 64bits in a dma transfer - */ - uint32_t dma_burst_len:12; - /** dma_interval : R/W; bitpos: [31:20]; default: 1; - * this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ... - */ - uint32_t dma_interval:12; - }; - uint32_t val; -} isp_dma_cntl_reg_t; - -/** Type of dma_raw_data register - * isp dma source total raw number set register - */ -typedef union { - struct { - /** dma_raw_num_total : R/W; bitpos: [21:0]; default: 0; - * this field configures the the number of 64bits in a frame - */ - uint32_t dma_raw_num_total:22; - uint32_t reserved_22:9; - /** dma_raw_num_total_set : WT; bitpos: [31]; default: 0; - * write 1 to update reg_dma_raw_num_total - */ - uint32_t dma_raw_num_total_set:1; - }; - uint32_t val; -} isp_dma_raw_data_reg_t; - -/** Type of cam_cntl register - * isp cam source control register - */ -typedef union { - struct { - /** cam_en : R/W; bitpos: [0]; default: 0; - * write 1 to start receive camera data, write 0 to disable - */ - uint32_t cam_en:1; - /** cam_update_reg : R/W; bitpos: [1]; default: 0; - * write 1 to update ISP_CAM_CONF - */ - uint32_t cam_update_reg:1; - /** cam_reset : R/W; bitpos: [2]; default: 1; - * this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset - */ - uint32_t cam_reset:1; - /** cam_clk_inv : R/W; bitpos: [3]; default: 0; - * this bit configures the inversion of cam clk from pad. 0: not invert cam clk, 1: - * invert cam clk - */ - uint32_t cam_clk_inv:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} isp_cam_cntl_reg_t; - -/** Type of cam_conf register - * isp cam source config register - */ -typedef union { - struct { - /** cam_data_order : R/W; bitpos: [0]; default: 0; - * this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in[7:0], - * cam_data_in[15:8]} - */ - uint32_t cam_data_order:1; - /** cam_2byte_mode : R/W; bitpos: [1]; default: 0; - * this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0: - * disable, 1: enable - */ - uint32_t cam_2byte_mode:1; - /** cam_data_type : R/W; bitpos: [7:2]; default: 42; - * this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c: - * RAW12 - */ - uint32_t cam_data_type:6; - /** cam_de_inv : R/W; bitpos: [8]; default: 0; - * this bit configures cam data enable invert. 0: not invert, 1: invert - */ - uint32_t cam_de_inv:1; - /** cam_hsync_inv : R/W; bitpos: [9]; default: 0; - * this bit configures cam hsync invert. 0: not invert, 1: invert - */ - uint32_t cam_hsync_inv:1; - /** cam_vsync_inv : R/W; bitpos: [10]; default: 0; - * this bit configures cam vsync invert. 0: not invert, 1: invert - */ - uint32_t cam_vsync_inv:1; - /** cam_vsync_filter_thres : R/W; bitpos: [13:11]; default: 0; - * this bit configures the number of clock of vsync filter length - */ - uint32_t cam_vsync_filter_thres:3; - /** cam_vsync_filter_en : R/W; bitpos: [14]; default: 0; - * this bit configures vsync filter en - */ - uint32_t cam_vsync_filter_en:1; - /** cam_de_only : R/W; bitpos: [15]; default: 0; - * configures whether cam inf only has de, no hsync data. 0: has hsync, 1: no hsync - */ - uint32_t cam_de_only:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} isp_cam_conf_reg_t; - -/** Type of af_ctrl0 register - * af control register 0 - */ -typedef union { - struct { - /** af_auto_update : R/W; bitpos: [0]; default: 0; - * this bit configures auto_update enable. when set to 1, will update sum and lum each - * frame - */ - uint32_t af_auto_update:1; - uint32_t reserved_1:3; - /** af_manual_update : WT; bitpos: [4]; default: 0; - * write 1 to this bit will update the sum and lum once - */ - uint32_t af_manual_update:1; - uint32_t reserved_5:3; - /** af_env_threshold : R/W; bitpos: [11:8]; default: 0; - * this field configures env threshold. when both sum and lum changes larger than this - * value, consider environment changes and need to trigger a new autofocus. 4Bit - * fractional - */ - uint32_t af_env_threshold:4; - uint32_t reserved_12:4; - /** af_env_period : R/W; bitpos: [23:16]; default: 0; - * this field configures environment changes detection period (frame). When set to 0, - * disable this function - */ - uint32_t af_env_period:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} isp_af_ctrl0_reg_t; - -/** Type of af_ctrl1 register - * af control register 1 - */ -typedef union { - struct { - /** af_thpixnum : R/W; bitpos: [21:0]; default: 0; - * this field configures pixnum used when calculating the autofocus threshold. Set to - * 0 to disable threshold calculation - */ - uint32_t af_thpixnum:22; - uint32_t reserved_22:10; - }; - uint32_t val; -} isp_af_ctrl1_reg_t; - -/** Type of af_gen_th_ctrl register - * af gen threshold control register - */ -typedef union { - struct { - /** af_gen_threshold_min : R/W; bitpos: [15:0]; default: 128; - * this field configures min threshold when use auto_threshold - */ - uint32_t af_gen_threshold_min:16; - /** af_gen_threshold_max : R/W; bitpos: [31:16]; default: 1088; - * this field configures max threshold when use auto_threshold - */ - uint32_t af_gen_threshold_max:16; - }; - uint32_t val; -} isp_af_gen_th_ctrl_reg_t; - -/** Type of af_env_user_th_sum register - * af monitor user sum threshold register - */ -typedef union { - struct { - /** af_env_user_threshold_sum : R/W; bitpos: [31:0]; default: 0; - * this field configures user setup env detect sum threshold - */ - uint32_t af_env_user_threshold_sum:32; - }; - uint32_t val; -} isp_af_env_user_th_sum_reg_t; - -/** Type of af_env_user_th_lum register - * af monitor user lum threshold register - */ -typedef union { - struct { - /** af_env_user_threshold_lum : R/W; bitpos: [29:0]; default: 0; - * this field configures user setup env detect lum threshold - */ - uint32_t af_env_user_threshold_lum:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} isp_af_env_user_th_lum_reg_t; - -/** Type of af_threshold register - * af threshold register - */ -typedef union { - struct { - /** af_threshold : R/W; bitpos: [15:0]; default: 256; - * this field configures user threshold. When set to non-zero, autofocus will use this - * threshold - */ - uint32_t af_threshold:16; - /** af_gen_threshold : RO; bitpos: [31:16]; default: 0; - * this field represents the last calculated threshold - */ - uint32_t af_gen_threshold:16; - }; - uint32_t val; -} isp_af_threshold_reg_t; - -/** Type of af_hscale_a register - * h-scale of af window a register - */ -typedef union { - struct { - /** af_rpoint_a : R/W; bitpos: [11:0]; default: 128; - * this field configures left coordinate of focus window a, must >= 2 - */ - uint32_t af_rpoint_a:12; - uint32_t reserved_12:4; - /** af_lpoint_a : R/W; bitpos: [27:16]; default: 1; - * this field configures top coordinate of focus window a, must >= 2 - */ - uint32_t af_lpoint_a:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} isp_af_hscale_a_reg_t; - -/** Type of af_vscale_a register - * v-scale of af window a register - */ -typedef union { - struct { - /** af_bpoint_a : R/W; bitpos: [11:0]; default: 128; - * this field configures right coordinate of focus window a, must <= hnum-2 - */ - uint32_t af_bpoint_a:12; - uint32_t reserved_12:4; - /** af_tpoint_a : R/W; bitpos: [27:16]; default: 1; - * this field configures bottom coordinate of focus window a, must <= hnum-2 - */ - uint32_t af_tpoint_a:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} isp_af_vscale_a_reg_t; - -/** Type of af_hscale_b register - * h-scale of af window b register - */ -typedef union { - struct { - /** af_rpoint_b : R/W; bitpos: [11:0]; default: 128; - * this field configures left coordinate of focus window b, must >= 2 - */ - uint32_t af_rpoint_b:12; - uint32_t reserved_12:4; - /** af_lpoint_b : R/W; bitpos: [27:16]; default: 1; - * this field configures top coordinate of focus window b, must >= 2 - */ - uint32_t af_lpoint_b:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} isp_af_hscale_b_reg_t; - -/** Type of af_vscale_b register - * v-scale of af window b register - */ -typedef union { - struct { - /** af_bpoint_b : R/W; bitpos: [11:0]; default: 128; - * this field configures right coordinate of focus window b, must <= hnum-2 - */ - uint32_t af_bpoint_b:12; - uint32_t reserved_12:4; - /** af_tpoint_b : R/W; bitpos: [27:16]; default: 1; - * this field configures bottom coordinate of focus window b, must <= hnum-2 - */ - uint32_t af_tpoint_b:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} isp_af_vscale_b_reg_t; - -/** Type of af_hscale_c register - * v-scale of af window c register - */ -typedef union { - struct { - /** af_rpoint_c : R/W; bitpos: [11:0]; default: 128; - * this field configures left coordinate of focus window c, must >= 2 - */ - uint32_t af_rpoint_c:12; - uint32_t reserved_12:4; - /** af_lpoint_c : R/W; bitpos: [27:16]; default: 1; - * this field configures top coordinate of focus window c, must >= 2 - */ - uint32_t af_lpoint_c:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} isp_af_hscale_c_reg_t; - -/** Type of af_vscale_c register - * v-scale of af window c register - */ -typedef union { - struct { - /** af_bpoint_c : R/W; bitpos: [11:0]; default: 128; - * this field configures right coordinate of focus window c, must <= hnum-2 - */ - uint32_t af_bpoint_c:12; - uint32_t reserved_12:4; - /** af_tpoint_c : R/W; bitpos: [27:16]; default: 1; - * this field configures bottom coordinate of focus window c, must <= hnum-2 - */ - uint32_t af_tpoint_c:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} isp_af_vscale_c_reg_t; - -/** Type of awb_mode register - * awb mode control register - */ -typedef union { - struct { - /** awb_mode : R/W; bitpos: [1:0]; default: 3; - * this field configures awb algo sel. 00: none selected. 01: sel algo0. 10: sel - * algo1. 11: sel both algo0 and algo1 - */ - uint32_t awb_mode:2; - uint32_t reserved_2:2; - /** awb_sample : R/W; bitpos: [4]; default: 0; - * this bit configures awb sample location, 0:before ccm, 1:after ccm - */ - uint32_t awb_sample:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} isp_awb_mode_reg_t; - -/** Type of awb_hscale register - * h-scale of awb window - */ -typedef union { - struct { - /** awb_rpoint : R/W; bitpos: [11:0]; default: 1919; - * this field configures awb window right coordinate - */ - uint32_t awb_rpoint:12; - uint32_t reserved_12:4; - /** awb_lpoint : R/W; bitpos: [27:16]; default: 0; - * this field configures awb window left coordinate - */ - uint32_t awb_lpoint:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} isp_awb_hscale_reg_t; - -/** Type of awb_vscale register - * v-scale of awb window - */ -typedef union { - struct { - /** awb_bpoint : R/W; bitpos: [11:0]; default: 1079; - * this field configures awb window bottom coordinate - */ - uint32_t awb_bpoint:12; - uint32_t reserved_12:4; - /** awb_tpoint : R/W; bitpos: [27:16]; default: 0; - * this field configures awb window top coordinate - */ - uint32_t awb_tpoint:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} isp_awb_vscale_reg_t; - -/** Type of awb_th_lum register - * awb lum threshold register - */ -typedef union { - struct { - /** awb_min_lum : R/W; bitpos: [9:0]; default: 0; - * this field configures lower threshold of r+g+b - */ - uint32_t awb_min_lum:10; - uint32_t reserved_10:6; - /** awb_max_lum : R/W; bitpos: [25:16]; default: 765; - * this field configures upper threshold of r+g+b - */ - uint32_t awb_max_lum:10; - uint32_t reserved_26:6; - }; - uint32_t val; -} isp_awb_th_lum_reg_t; - -/** Type of awb_th_rg register - * awb r/g threshold register - */ -typedef union { - struct { - /** awb_min_rg : R/W; bitpos: [9:0]; default: 0; - * this field configures lower threshold of r/g, 2bit integer and 8bit fraction - */ - uint32_t awb_min_rg:10; - uint32_t reserved_10:6; - /** awb_max_rg : R/W; bitpos: [25:16]; default: 1023; - * this field configures upper threshold of r/g, 2bit integer and 8bit fraction - */ - uint32_t awb_max_rg:10; - uint32_t reserved_26:6; - }; - uint32_t val; -} isp_awb_th_rg_reg_t; - -/** Type of awb_th_bg register - * awb b/g threshold register - */ -typedef union { - struct { - /** awb_min_bg : R/W; bitpos: [9:0]; default: 0; - * this field configures lower threshold of b/g, 2bit integer and 8bit fraction - */ - uint32_t awb_min_bg:10; - uint32_t reserved_10:6; - /** awb_max_bg : R/W; bitpos: [25:16]; default: 1023; - * this field configures upper threshold of b/g, 2bit integer and 8bit fraction - */ - uint32_t awb_max_bg:10; - uint32_t reserved_26:6; - }; - uint32_t val; -} isp_awb_th_bg_reg_t; - -/** Type of color_ctrl register - * color control register - */ -typedef union { - struct { - /** color_saturation : R/W; bitpos: [7:0]; default: 128; - * this field configures the color saturation value - */ - uint32_t color_saturation:8; - /** color_hue : R/W; bitpos: [15:8]; default: 0; - * this field configures the color hue angle - */ - uint32_t color_hue:8; - /** color_contrast : R/W; bitpos: [23:16]; default: 128; - * this field configures the color contrast value - */ - uint32_t color_contrast:8; - /** color_brightness : R/W; bitpos: [31:24]; default: 0; - * this field configures the color brightness value, signed 2's complement - */ - uint32_t color_brightness:8; - }; - uint32_t val; -} isp_color_ctrl_reg_t; - -/** Type of blc_value register - * blc black level register - */ -typedef union { - struct { - /** blc_r3_value : R/W; bitpos: [7:0]; default: 0; - * this field configures the black level of bottom right channel of bayer img - */ - uint32_t blc_r3_value:8; - /** blc_r2_value : R/W; bitpos: [15:8]; default: 0; - * this field configures the black level of bottom left channel of bayer img - */ - uint32_t blc_r2_value:8; - /** blc_r1_value : R/W; bitpos: [23:16]; default: 0; - * this field configures the black level of top right channel of bayer img - */ - uint32_t blc_r1_value:8; - /** blc_r0_value : R/W; bitpos: [31:24]; default: 0; - * this field configures the black level of top left channel of bayer img - */ - uint32_t blc_r0_value:8; - }; - uint32_t val; -} isp_blc_value_reg_t; - -/** Type of blc_ctrl0 register - * blc stretch control register - */ -typedef union { - struct { - /** blc_r3_stretch : R/W; bitpos: [0]; default: 0; - * this bit configures the stretch feature of bottom right channel. 0: stretch - * disable, 1: stretch enable - */ - uint32_t blc_r3_stretch:1; - /** blc_r2_stretch : R/W; bitpos: [1]; default: 0; - * this bit configures the stretch feature of bottom left channel. 0: stretch disable, - * 1: stretch enable - */ - uint32_t blc_r2_stretch:1; - /** blc_r1_stretch : R/W; bitpos: [2]; default: 0; - * this bit configures the stretch feature of top right channel. 0: stretch disable, - * 1: stretch enable - */ - uint32_t blc_r1_stretch:1; - /** blc_r0_stretch : R/W; bitpos: [3]; default: 0; - * this bit configures the stretch feature of top left channel. 0: stretch disable, 1: - * stretch enable - */ - uint32_t blc_r0_stretch:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} isp_blc_ctrl0_reg_t; - -/** Type of blc_ctrl1 register - * blc window control register - */ -typedef union { - struct { - /** blc_window_top : R/W; bitpos: [10:0]; default: 0; - * this field configures blc average calculation window top - */ - uint32_t blc_window_top:11; - /** blc_window_left : R/W; bitpos: [21:11]; default: 0; - * this field configures blc average calculation window left - */ - uint32_t blc_window_left:11; - /** blc_window_vnum : R/W; bitpos: [25:22]; default: 0; - * this field configures blc average calculation window vnum - */ - uint32_t blc_window_vnum:4; - /** blc_window_hnum : R/W; bitpos: [29:26]; default: 0; - * this field configures blc average calculation window hnum - */ - uint32_t blc_window_hnum:4; - /** blc_filter_en : R/W; bitpos: [30]; default: 0; - * this bit configures enable blc average input filter. 0: disable, 1: enable - */ - uint32_t blc_filter_en:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} isp_blc_ctrl1_reg_t; - -/** Type of blc_ctrl2 register - * blc black threshold control register - */ -typedef union { - struct { - /** blc_r3_th : R/W; bitpos: [7:0]; default: 0; - * this field configures black threshold when get blc average of bottom right channel - */ - uint32_t blc_r3_th:8; - /** blc_r2_th : R/W; bitpos: [15:8]; default: 0; - * this field configures black threshold when get blc average of bottom left channel - */ - uint32_t blc_r2_th:8; - /** blc_r1_th : R/W; bitpos: [23:16]; default: 0; - * this field configures black threshold when get blc average of top right channel - */ - uint32_t blc_r1_th:8; - /** blc_r0_th : R/W; bitpos: [31:24]; default: 0; - * this field configures black threshold when get blc average of top left channel - */ - uint32_t blc_r0_th:8; - }; - uint32_t val; -} isp_blc_ctrl2_reg_t; - -/** Type of hist_mode register - * histogram mode control register - */ -typedef union { - struct { - /** hist_mode : R/W; bitpos: [2:0]; default: 4; - * this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4: - * RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V - */ - uint32_t hist_mode:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} isp_hist_mode_reg_t; - -/** Type of hist_coeff register - * histogram rgb to gray coefficients register - */ -typedef union { - struct { - /** hist_coeff_b : R/W; bitpos: [7:0]; default: 85; - * this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r - * and coeff_g and coeff_b should be 256 - */ - uint32_t hist_coeff_b:8; - /** hist_coeff_g : R/W; bitpos: [15:8]; default: 85; - * this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r - * and coeff_g and coeff_b should be 256 - */ - uint32_t hist_coeff_g:8; - /** hist_coeff_r : R/W; bitpos: [23:16]; default: 85; - * this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r - * and coeff_g and coeff_b should be 256 - */ - uint32_t hist_coeff_r:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} isp_hist_coeff_reg_t; - -/** Type of hist_offs register - * histogram window offsets register - */ -typedef union { - struct { - /** hist_y_offs : R/W; bitpos: [11:0]; default: 0; - * this field configures y coordinate of first window - */ - uint32_t hist_y_offs:12; - uint32_t reserved_12:4; - /** hist_x_offs : R/W; bitpos: [27:16]; default: 0; - * this field configures x coordinate of first window - */ - uint32_t hist_x_offs:12; - uint32_t reserved_28:4; - }; - uint32_t val; -} isp_hist_offs_reg_t; - -/** Type of hist_size register - * histogram sub-window size register - */ -typedef union { - struct { - /** hist_y_size : R/W; bitpos: [8:0]; default: 32; - * this field configures y direction size of subwindow - */ - uint32_t hist_y_size:9; - uint32_t reserved_9:7; - /** hist_x_size : R/W; bitpos: [24:16]; default: 18; - * this field configures x direction size of subwindow - */ - uint32_t hist_x_size:9; - uint32_t reserved_25:7; - }; - uint32_t val; -} isp_hist_size_reg_t; - -/** Type of hist_seg0 register - * histogram bin control register 0 - */ -typedef union { - struct { - /** hist_seg_3_4 : R/W; bitpos: [7:0]; default: 64; - * this field configures threshold of histogram bin 3 and bin 4 - */ - uint32_t hist_seg_3_4:8; - /** hist_seg_2_3 : R/W; bitpos: [15:8]; default: 48; - * this field configures threshold of histogram bin 2 and bin 3 - */ - uint32_t hist_seg_2_3:8; - /** hist_seg_1_2 : R/W; bitpos: [23:16]; default: 32; - * this field configures threshold of histogram bin 1 and bin 2 - */ - uint32_t hist_seg_1_2:8; - /** hist_seg_0_1 : R/W; bitpos: [31:24]; default: 16; - * this field configures threshold of histogram bin 0 and bin 1 - */ - uint32_t hist_seg_0_1:8; - }; - uint32_t val; -} isp_hist_seg0_reg_t; - -/** Type of hist_seg1 register - * histogram bin control register 1 - */ -typedef union { - struct { - /** hist_seg_7_8 : R/W; bitpos: [7:0]; default: 128; - * this field configures threshold of histogram bin 7 and bin 8 - */ - uint32_t hist_seg_7_8:8; - /** hist_seg_6_7 : R/W; bitpos: [15:8]; default: 112; - * this field configures threshold of histogram bin 6 and bin 7 - */ - uint32_t hist_seg_6_7:8; - /** hist_seg_5_6 : R/W; bitpos: [23:16]; default: 96; - * this field configures threshold of histogram bin 5 and bin 6 - */ - uint32_t hist_seg_5_6:8; - /** hist_seg_4_5 : R/W; bitpos: [31:24]; default: 80; - * this field configures threshold of histogram bin 4 and bin 5 - */ - uint32_t hist_seg_4_5:8; - }; - uint32_t val; -} isp_hist_seg1_reg_t; - -/** Type of hist_seg2 register - * histogram bin control register 2 - */ -typedef union { - struct { - /** hist_seg_11_12 : R/W; bitpos: [7:0]; default: 192; - * this field configures threshold of histogram bin 11 and bin 12 - */ - uint32_t hist_seg_11_12:8; - /** hist_seg_10_11 : R/W; bitpos: [15:8]; default: 176; - * this field configures threshold of histogram bin 10 and bin 11 - */ - uint32_t hist_seg_10_11:8; - /** hist_seg_9_10 : R/W; bitpos: [23:16]; default: 160; - * this field configures threshold of histogram bin 9 and bin 10 - */ - uint32_t hist_seg_9_10:8; - /** hist_seg_8_9 : R/W; bitpos: [31:24]; default: 144; - * this field configures threshold of histogram bin 8 and bin 9 - */ - uint32_t hist_seg_8_9:8; - }; - uint32_t val; -} isp_hist_seg2_reg_t; - -/** Type of hist_seg3 register - * histogram bin control register 3 - */ -typedef union { - struct { - /** hist_seg_14_15 : R/W; bitpos: [7:0]; default: 240; - * this field configures threshold of histogram bin 14 and bin 15 - */ - uint32_t hist_seg_14_15:8; - /** hist_seg_13_14 : R/W; bitpos: [15:8]; default: 224; - * this field configures threshold of histogram bin 13 and bin 14 - */ - uint32_t hist_seg_13_14:8; - /** hist_seg_12_13 : R/W; bitpos: [23:16]; default: 208; - * this field configures threshold of histogram bin 12 and bin 13 - */ - uint32_t hist_seg_12_13:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} isp_hist_seg3_reg_t; - -/** Type of hist_weight0 register - * histogram sub-window weight register 0 - */ -typedef union { - struct { - /** hist_weight_03 : R/W; bitpos: [7:0]; default: 1; - * this field configures weight of subwindow 03 - */ - uint32_t hist_weight_03:8; - /** hist_weight_02 : R/W; bitpos: [15:8]; default: 1; - * this field configures weight of subwindow 02 - */ - uint32_t hist_weight_02:8; - /** hist_weight_01 : R/W; bitpos: [23:16]; default: 1; - * this field configures weight of subwindow 01 - */ - uint32_t hist_weight_01:8; - /** hist_weight_00 : R/W; bitpos: [31:24]; default: 1; - * this field configures weight of subwindow 00 and sum of all weight should be 256 - */ - uint32_t hist_weight_00:8; - }; - uint32_t val; -} isp_hist_weight0_reg_t; - -/** Type of hist_weight1 register - * histogram sub-window weight register 1 - */ -typedef union { - struct { - /** hist_weight_12 : R/W; bitpos: [7:0]; default: 1; - * this field configures weight of subwindow 12 - */ - uint32_t hist_weight_12:8; - /** hist_weight_11 : R/W; bitpos: [15:8]; default: 1; - * this field configures weight of subwindow 11 - */ - uint32_t hist_weight_11:8; - /** hist_weight_10 : R/W; bitpos: [23:16]; default: 1; - * this field configures weight of subwindow 10 - */ - uint32_t hist_weight_10:8; - /** hist_weight_04 : R/W; bitpos: [31:24]; default: 1; - * this field configures weight of subwindow 04 - */ - uint32_t hist_weight_04:8; - }; - uint32_t val; -} isp_hist_weight1_reg_t; - -/** Type of hist_weight2 register - * histogram sub-window weight register 2 - */ -typedef union { - struct { - /** hist_weight_21 : R/W; bitpos: [7:0]; default: 1; - * this field configures weight of subwindow 21 - */ - uint32_t hist_weight_21:8; - /** hist_weight_20 : R/W; bitpos: [15:8]; default: 1; - * this field configures weight of subwindow 20 - */ - uint32_t hist_weight_20:8; - /** hist_weight_14 : R/W; bitpos: [23:16]; default: 1; - * this field configures weight of subwindow 04 - */ - uint32_t hist_weight_14:8; - /** hist_weight_13 : R/W; bitpos: [31:24]; default: 1; - * this field configures weight of subwindow 13 - */ - uint32_t hist_weight_13:8; - }; - uint32_t val; -} isp_hist_weight2_reg_t; - -/** Type of hist_weight3 register - * histogram sub-window weight register 3 - */ -typedef union { - struct { - /** hist_weight_30 : R/W; bitpos: [7:0]; default: 1; - * this field configures weight of subwindow 30 - */ - uint32_t hist_weight_30:8; - /** hist_weight_24 : R/W; bitpos: [15:8]; default: 1; - * this field configures weight of subwindow 24 - */ - uint32_t hist_weight_24:8; - /** hist_weight_23 : R/W; bitpos: [23:16]; default: 1; - * this field configures weight of subwindow 23 - */ - uint32_t hist_weight_23:8; - /** hist_weight_22 : R/W; bitpos: [31:24]; default: 232; - * this field configures weight of subwindow 22 - */ - uint32_t hist_weight_22:8; - }; - uint32_t val; -} isp_hist_weight3_reg_t; - -/** Type of hist_weight4 register - * histogram sub-window weight register 4 - */ -typedef union { - struct { - /** hist_weight_34 : R/W; bitpos: [7:0]; default: 1; - * this field configures weight of subwindow 34 - */ - uint32_t hist_weight_34:8; - /** hist_weight_33 : R/W; bitpos: [15:8]; default: 1; - * this field configures weight of subwindow 33 - */ - uint32_t hist_weight_33:8; - /** hist_weight_32 : R/W; bitpos: [23:16]; default: 1; - * this field configures weight of subwindow 32 - */ - uint32_t hist_weight_32:8; - /** hist_weight_31 : R/W; bitpos: [31:24]; default: 1; - * this field configures weight of subwindow 31 - */ - uint32_t hist_weight_31:8; - }; - uint32_t val; -} isp_hist_weight4_reg_t; - -/** Type of hist_weight5 register - * histogram sub-window weight register 5 - */ -typedef union { - struct { - /** hist_weight_43 : R/W; bitpos: [7:0]; default: 1; - * this field configures weight of subwindow 43 - */ - uint32_t hist_weight_43:8; - /** hist_weight_42 : R/W; bitpos: [15:8]; default: 1; - * this field configures weight of subwindow 42 - */ - uint32_t hist_weight_42:8; - /** hist_weight_41 : R/W; bitpos: [23:16]; default: 1; - * this field configures weight of subwindow 41 - */ - uint32_t hist_weight_41:8; - /** hist_weight_40 : R/W; bitpos: [31:24]; default: 1; - * this field configures weight of subwindow 40 - */ - uint32_t hist_weight_40:8; - }; - uint32_t val; -} isp_hist_weight5_reg_t; - -/** Type of hist_weight6 register - * histogram sub-window weight register 6 - */ -typedef union { - struct { - /** hist_weight_44 : R/W; bitpos: [7:0]; default: 1; - * this field configures weight of subwindow 44 - */ - uint32_t hist_weight_44:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} isp_hist_weight6_reg_t; - -/** Type of mem_aux_ctrl_0 register - * mem aux control register 0 - */ -typedef union { - struct { - /** header_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; - * this field configures the mem_aux of isp input buffer memory - */ - uint32_t header_mem_aux_ctrl:14; - uint32_t reserved_14:2; - /** dpc_lut_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; - * this field represents this field configures the mem_aux of dpc lut memory - */ - uint32_t dpc_lut_mem_aux_ctrl:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} isp_mem_aux_ctrl_0_reg_t; - -/** Type of mem_aux_ctrl_1 register - * mem aux control register 1 - */ -typedef union { - struct { - /** lsc_lut_r_gr_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; - * this field configures the mem_aux of lsc r gr lut memory - */ - uint32_t lsc_lut_r_gr_mem_aux_ctrl:14; - uint32_t reserved_14:2; - /** lsc_lut_gb_b_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; - * this field configures the mem_aux of lsc gb b lut memory - */ - uint32_t lsc_lut_gb_b_mem_aux_ctrl:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} isp_mem_aux_ctrl_1_reg_t; - -/** Type of mem_aux_ctrl_2 register - * mem aux control register 2 - */ -typedef union { - struct { - /** bf_matrix_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; - * this field configures the mem_aux of bf line buffer memory - */ - uint32_t bf_matrix_mem_aux_ctrl:14; - uint32_t reserved_14:2; - /** dpc_matrix_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; - * this field configures the mem_aux of dpc line buffer memory - */ - uint32_t dpc_matrix_mem_aux_ctrl:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} isp_mem_aux_ctrl_2_reg_t; - -/** Type of mem_aux_ctrl_3 register - * mem aux control register 3 - */ -typedef union { - struct { - /** sharp_matrix_y_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; - * this field configures the mem_aux of sharp y line buffer memory - */ - uint32_t sharp_matrix_y_mem_aux_ctrl:14; - uint32_t reserved_14:2; - /** demosaic_matrix_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; - * this field configures the mem_aux of demosaic line buffer memory - */ - uint32_t demosaic_matrix_mem_aux_ctrl:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} isp_mem_aux_ctrl_3_reg_t; - -/** Type of mem_aux_ctrl_4 register - * mem aux control register 4 - */ -typedef union { - struct { - /** sharp_matrix_uv_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; - * this field configures the mem_aux of sharp uv line buffer memory - */ - uint32_t sharp_matrix_uv_mem_aux_ctrl:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} isp_mem_aux_ctrl_4_reg_t; - -/** Type of yuv_format register - * yuv format control register - */ -typedef union { - struct { - /** yuv_mode : R/W; bitpos: [0]; default: 0; - * this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709 - */ - uint32_t yuv_mode:1; - /** yuv_range : R/W; bitpos: [1]; default: 0; - * this bit configures the yuv range. 0: full range, 1: limit range - */ - uint32_t yuv_range:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} isp_yuv_format_reg_t; - -/** Type of rdn_eco_low register - * rdn eco all low register - */ -typedef union { - struct { - /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0; - * rdn_eco_low - */ - uint32_t rdn_eco_low:32; - }; - uint32_t val; -} isp_rdn_eco_low_reg_t; - -/** Type of rdn_eco_high register - * rdn eco all high register - */ -typedef union { - struct { - /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; - * rdn_eco_high - */ - uint32_t rdn_eco_high:32; - }; - uint32_t val; -} isp_rdn_eco_high_reg_t; - -/** Type of crop_ctrl register - * isp_crop ctrl register - */ -typedef union { - struct { - /** crop_sft_rst : WT; bitpos: [0]; default: 0; - * Write 1 to clear err st - */ - uint32_t crop_sft_rst:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} isp_crop_ctrl_reg_t; - -/** Type of crop_y_capture register - * isp_crop row capture range register - */ -typedef union { - struct { - /** crop_y_start : R/W; bitpos: [11:0]; default: 0; - * isp_crop capture row start index - */ - uint32_t crop_y_start:12; - /** crop_y_end : R/W; bitpos: [23:12]; default: 0; - * isp_crop capture row end index - */ - uint32_t crop_y_end:12; - uint32_t reserved_24:8; - }; - uint32_t val; -} isp_crop_y_capture_reg_t; - -/** Type of crop_x_capture register - * isp_crop col capture range register - */ -typedef union { - struct { - /** crop_x_start : R/W; bitpos: [11:0]; default: 0; - * isp_crop capture col start index - */ - uint32_t crop_x_start:12; - /** crop_x_end : R/W; bitpos: [23:12]; default: 0; - * isp_crop capture col end index - */ - uint32_t crop_x_end:12; - uint32_t reserved_24:8; - }; - uint32_t val; -} isp_crop_x_capture_reg_t; - -/** Type of crop_err_st register - * crop error state register - */ -typedef union { - struct { - /** crop_y_mismatch : RO; bitpos: [0]; default: 0; - * Represents isp_corp row end index over image size - */ - uint32_t crop_y_mismatch:1; - /** crop_x_mismatch : RO; bitpos: [1]; default: 0; - * Represents isp_corp col end index over image size - */ - uint32_t crop_x_mismatch:1; - /** crop_y_end_even : RO; bitpos: [2]; default: 0; - * Represents isp_corp row end index is an even number - */ - uint32_t crop_y_end_even:1; - /** crop_x_end_even : RO; bitpos: [3]; default: 0; - * Represents isp_corp col end index is an even number - */ - uint32_t crop_x_end_even:1; - /** crop_y_start_odd : RO; bitpos: [4]; default: 0; - * Represents isp_corp row start index is an odd number - */ - uint32_t crop_y_start_odd:1; - /** crop_x_start_odd : RO; bitpos: [5]; default: 0; - * Represents isp_corp col start index is an odd number - */ - uint32_t crop_x_start_odd:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} isp_crop_err_st_reg_t; - -/** Type of wbg_coef_r register - * white balance red gain register 0 - */ -typedef union { - struct { - /** wbg_r : R/W; bitpos: [11:0]; default: 256; - * Configures the white balance red gain - */ - uint32_t wbg_r:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} isp_wbg_coef_r_reg_t; - -/** Type of wbg_coef_g register - * white balance green gain register 0 - */ -typedef union { - struct { - /** wbg_g : R/W; bitpos: [11:0]; default: 256; - * Configures the white balance green gain - */ - uint32_t wbg_g:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} isp_wbg_coef_g_reg_t; - -/** Type of wbg_coef_b register - * white balance blue gain register 0 - */ -typedef union { - struct { - /** wbg_b : R/W; bitpos: [11:0]; default: 256; - * Configures the white balance blue gain - */ - uint32_t wbg_b:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} isp_wbg_coef_b_reg_t; - -/** Type of color_hue_ctrl register - * color control register - */ -typedef union { - struct { - /** color_hue_h : R/W; bitpos: [0]; default: 0; - * Configures the color hue angle most bit - */ - uint32_t color_hue_h:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} isp_color_hue_ctrl_reg_t; - -/** Type of awb_bx register - * awb window register in x-direction - */ -typedef union { - struct { - /** awb_x_bsize : R/W; bitpos: [11:0]; default: 0; - * Configures every block x size, min number is 4 - */ - uint32_t awb_x_bsize:12; - /** awb_x_start : R/W; bitpos: [23:12]; default: 0; - * Configures first block start x address - */ - uint32_t awb_x_start:12; - uint32_t reserved_24:8; - }; - uint32_t val; -} isp_awb_bx_reg_t; - -/** Type of awb_by register - * awb window register in y-direction - */ -typedef union { - struct { - /** awb_y_bsize : R/W; bitpos: [11:0]; default: 0; - * Configures every block y size - */ - uint32_t awb_y_bsize:12; - /** awb_y_start : R/W; bitpos: [23:12]; default: 0; - * Configures first block start y address - */ - uint32_t awb_y_start:12; - uint32_t reserved_24:8; - }; - uint32_t val; -} isp_awb_by_reg_t; - -/** Type of state register - * awb window register in y-direction - */ -typedef union { - struct { - /** tail_busy : RO; bitpos: [0]; default: 0; - * Represents isp_tail state - */ - uint32_t tail_busy:1; - /** header_busy : RO; bitpos: [1]; default: 0; - * Represents isp_header state - */ - uint32_t header_busy:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} isp_state_reg_t; - -/** Type of shadow_reg_ctrl register - * shadow register ctrl register - */ -typedef union { - struct { - /** blc_update : R/W; bitpos: [0]; default: 0; - * Write 1 to update blc configuration register - */ - uint32_t blc_update:1; - /** dpc_update : R/W; bitpos: [1]; default: 0; - * Write 1 to update dpc configuration register - */ - uint32_t dpc_update:1; - /** bf_update : R/W; bitpos: [2]; default: 0; - * Write 1 to update bf configuration register - */ - uint32_t bf_update:1; - /** wbg_update : R/W; bitpos: [3]; default: 0; - * Write 1 to update wbg configuration register - */ - uint32_t wbg_update:1; - /** ccm_update : R/W; bitpos: [4]; default: 0; - * Write 1 to update ccm configuration register - */ - uint32_t ccm_update:1; - uint32_t reserved_5:1; - /** sharp_update : R/W; bitpos: [6]; default: 0; - * Write 1 to update sharp configuration register - */ - uint32_t sharp_update:1; - /** color_update : R/W; bitpos: [7]; default: 0; - * Write 1 to update color configuration register - */ - uint32_t color_update:1; - uint32_t reserved_8:22; - /** shadow_update_sel : R/W; bitpos: [31:30]; default: 1; - * Configures shadow register update type. 0: no shadow register. 1: update every - * vsyn. 2: update only the next vsync after write reg_xxx_update - */ - uint32_t shadow_update_sel:2; - }; - uint32_t val; -} isp_shadow_reg_ctrl_reg_t; - - -/** Group: Status Registers */ -/** Type of dpc_deadpix_cnt register - * DPC dead-pix number register - */ -typedef union { - struct { - /** dpc_deadpix_cnt : RO; bitpos: [9:0]; default: 0; - * this field represents the dead pixel count - */ - uint32_t dpc_deadpix_cnt:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} isp_dpc_deadpix_cnt_reg_t; - -/** Type of lut_rdata register - * LUT read data register - */ -typedef union { - struct { - /** lut_rdata : RO; bitpos: [31:0]; default: 0; - * this field represents the read data of lut. read ISP_LUT_RDATA after write - * ISP_LUT_CMD register - */ - uint32_t lut_rdata:32; - }; - uint32_t val; -} isp_lut_rdata_reg_t; - -/** Type of ae_block_mean_0 register - * ae statistic result register 0 - */ -typedef union { - struct { - /** ae_b03_mean : RO; bitpos: [7:0]; default: 0; - * this field configures block03 Y mean data - */ - uint32_t ae_b03_mean:8; - /** ae_b02_mean : RO; bitpos: [15:8]; default: 0; - * this field configures block02 Y mean data - */ - uint32_t ae_b02_mean:8; - /** ae_b01_mean : RO; bitpos: [23:16]; default: 0; - * this field configures block01 Y mean data - */ - uint32_t ae_b01_mean:8; - /** ae_b00_mean : RO; bitpos: [31:24]; default: 0; - * this field configures block00 Y mean data - */ - uint32_t ae_b00_mean:8; - }; - uint32_t val; -} isp_ae_block_mean_0_reg_t; - -/** Type of ae_block_mean_1 register - * ae statistic result register 1 - */ -typedef union { - struct { - /** ae_b12_mean : RO; bitpos: [7:0]; default: 0; - * this field configures block12 Y mean data - */ - uint32_t ae_b12_mean:8; - /** ae_b11_mean : RO; bitpos: [15:8]; default: 0; - * this field configures block11 Y mean data - */ - uint32_t ae_b11_mean:8; - /** ae_b10_mean : RO; bitpos: [23:16]; default: 0; - * this field configures block10 Y mean data - */ - uint32_t ae_b10_mean:8; - /** ae_b04_mean : RO; bitpos: [31:24]; default: 0; - * this field configures block04 Y mean data - */ - uint32_t ae_b04_mean:8; - }; - uint32_t val; -} isp_ae_block_mean_1_reg_t; - -/** Type of ae_block_mean_2 register - * ae statistic result register 2 - */ -typedef union { - struct { - /** ae_b21_mean : RO; bitpos: [7:0]; default: 0; - * this field configures block21 Y mean data - */ - uint32_t ae_b21_mean:8; - /** ae_b20_mean : RO; bitpos: [15:8]; default: 0; - * this field configures block20 Y mean data - */ - uint32_t ae_b20_mean:8; - /** ae_b14_mean : RO; bitpos: [23:16]; default: 0; - * this field configures block14 Y mean data - */ - uint32_t ae_b14_mean:8; - /** ae_b13_mean : RO; bitpos: [31:24]; default: 0; - * this field configures block13 Y mean data - */ - uint32_t ae_b13_mean:8; - }; - uint32_t val; -} isp_ae_block_mean_2_reg_t; - -/** Type of ae_block_mean_3 register - * ae statistic result register 3 - */ -typedef union { - struct { - /** ae_b30_mean : RO; bitpos: [7:0]; default: 0; - * this field configures block30 Y mean data - */ - uint32_t ae_b30_mean:8; - /** ae_b24_mean : RO; bitpos: [15:8]; default: 0; - * this field configures block24 Y mean data - */ - uint32_t ae_b24_mean:8; - /** ae_b23_mean : RO; bitpos: [23:16]; default: 0; - * this field configures block23 Y mean data - */ - uint32_t ae_b23_mean:8; - /** ae_b22_mean : RO; bitpos: [31:24]; default: 0; - * this field configures block22 Y mean data - */ - uint32_t ae_b22_mean:8; - }; - uint32_t val; -} isp_ae_block_mean_3_reg_t; - -/** Type of ae_block_mean_4 register - * ae statistic result register 4 - */ -typedef union { - struct { - /** ae_b34_mean : RO; bitpos: [7:0]; default: 0; - * this field configures block34 Y mean data - */ - uint32_t ae_b34_mean:8; - /** ae_b33_mean : RO; bitpos: [15:8]; default: 0; - * this field configures block33 Y mean data - */ - uint32_t ae_b33_mean:8; - /** ae_b32_mean : RO; bitpos: [23:16]; default: 0; - * this field configures block32 Y mean data - */ - uint32_t ae_b32_mean:8; - /** ae_b31_mean : RO; bitpos: [31:24]; default: 0; - * this field configures block31 Y mean data - */ - uint32_t ae_b31_mean:8; - }; - uint32_t val; -} isp_ae_block_mean_4_reg_t; - -/** Type of ae_block_mean_5 register - * ae statistic result register 5 - */ -typedef union { - struct { - /** ae_b43_mean : RO; bitpos: [7:0]; default: 0; - * this field configures block43 Y mean data - */ - uint32_t ae_b43_mean:8; - /** ae_b42_mean : RO; bitpos: [15:8]; default: 0; - * this field configures block42 Y mean data - */ - uint32_t ae_b42_mean:8; - /** ae_b41_mean : RO; bitpos: [23:16]; default: 0; - * this field configures block41 Y mean data - */ - uint32_t ae_b41_mean:8; - /** ae_b40_mean : RO; bitpos: [31:24]; default: 0; - * this field configures block40 Y mean data - */ - uint32_t ae_b40_mean:8; - }; - uint32_t val; -} isp_ae_block_mean_5_reg_t; - -/** Type of ae_block_mean_6 register - * ae statistic result register 6 - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** ae_b44_mean : RO; bitpos: [31:24]; default: 0; - * this field configures block44 Y mean data - */ - uint32_t ae_b44_mean:8; - }; - uint32_t val; -} isp_ae_block_mean_6_reg_t; - -/** Type of af_sum_a register - * result of sum of af window a - */ -typedef union { - struct { - /** af_suma : RO; bitpos: [29:0]; default: 0; - * this field represents the result of accumulation of pix grad of focus window a - */ - uint32_t af_suma:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} isp_af_sum_a_reg_t; - -/** Type of af_sum_b register - * result of sum of af window b - */ -typedef union { - struct { - /** af_sumb : RO; bitpos: [29:0]; default: 0; - * this field represents the result of accumulation of pix grad of focus window b - */ - uint32_t af_sumb:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} isp_af_sum_b_reg_t; - -/** Type of af_sum_c register - * result of sum of af window c - */ -typedef union { - struct { - /** af_sumc : RO; bitpos: [29:0]; default: 0; - * this field represents the result of accumulation of pix grad of focus window c - */ - uint32_t af_sumc:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} isp_af_sum_c_reg_t; - -/** Type of af_lum_a register - * result of lum of af window a - */ -typedef union { - struct { - /** af_luma : RO; bitpos: [27:0]; default: 0; - * this field represents the result of accumulation of pix light of focus window a - */ - uint32_t af_luma:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} isp_af_lum_a_reg_t; - -/** Type of af_lum_b register - * result of lum of af window b - */ -typedef union { - struct { - /** af_lumb : RO; bitpos: [27:0]; default: 0; - * this field represents the result of accumulation of pix light of focus window b - */ - uint32_t af_lumb:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} isp_af_lum_b_reg_t; - -/** Type of af_lum_c register - * result of lum of af window c - */ -typedef union { - struct { - /** af_lumc : RO; bitpos: [27:0]; default: 0; - * this field represents the result of accumulation of pix light of focus window c - */ - uint32_t af_lumc:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} isp_af_lum_c_reg_t; - -/** Type of awb0_white_cnt register - * result of awb white point number - */ -typedef union { - struct { - /** awb0_white_cnt : RO; bitpos: [23:0]; default: 0; - * this field configures number of white point detected of algo0 - */ - uint32_t awb0_white_cnt:24; - uint32_t reserved_24:8; - }; - uint32_t val; -} isp_awb0_white_cnt_reg_t; - -/** Type of awb0_acc_r register - * result of accumulate of r channel of all white points - */ -typedef union { - struct { - /** awb0_acc_r : RO; bitpos: [31:0]; default: 0; - * this field represents accumulate of channel r of all white point of algo0 - */ - uint32_t awb0_acc_r:32; - }; - uint32_t val; -} isp_awb0_acc_r_reg_t; - -/** Type of awb0_acc_g register - * result of accumulate of g channel of all white points - */ -typedef union { - struct { - /** awb0_acc_g : RO; bitpos: [31:0]; default: 0; - * this field represents accumulate of channel g of all white point of algo0 - */ - uint32_t awb0_acc_g:32; - }; - uint32_t val; -} isp_awb0_acc_g_reg_t; - -/** Type of awb0_acc_b register - * result of accumulate of b channel of all white points - */ -typedef union { - struct { - /** awb0_acc_b : RO; bitpos: [31:0]; default: 0; - * this field represents accumulate of channel b of all white point of algo0 - */ - uint32_t awb0_acc_b:32; - }; - uint32_t val; -} isp_awb0_acc_b_reg_t; - -/** Type of blc_mean register - * results of the average of black window - */ -typedef union { - struct { - /** blc_r3_mean : RO; bitpos: [7:0]; default: 0; - * this field represents the average black value of bottom right channel - */ - uint32_t blc_r3_mean:8; - /** blc_r2_mean : RO; bitpos: [15:8]; default: 0; - * this field represents the average black value of bottom left channel - */ - uint32_t blc_r2_mean:8; - /** blc_r1_mean : RO; bitpos: [23:16]; default: 0; - * this field represents the average black value of top right channel - */ - uint32_t blc_r1_mean:8; - /** blc_r0_mean : RO; bitpos: [31:24]; default: 0; - * this field represents the average black value of top left channel - */ - uint32_t blc_r0_mean:8; - }; - uint32_t val; -} isp_blc_mean_reg_t; - -/** Type of hist_bin0 register - * result of histogram bin 0 - */ -typedef union { - struct { - /** hist_bin_0 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 0 - */ - uint32_t hist_bin_0:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin0_reg_t; - -/** Type of hist_bin1 register - * result of histogram bin 1 - */ -typedef union { - struct { - /** hist_bin_1 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 1 - */ - uint32_t hist_bin_1:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin1_reg_t; - -/** Type of hist_bin2 register - * result of histogram bin 2 - */ -typedef union { - struct { - /** hist_bin_2 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 2 - */ - uint32_t hist_bin_2:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin2_reg_t; - -/** Type of hist_bin3 register - * result of histogram bin 3 - */ -typedef union { - struct { - /** hist_bin_3 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 3 - */ - uint32_t hist_bin_3:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin3_reg_t; - -/** Type of hist_bin4 register - * result of histogram bin 4 - */ -typedef union { - struct { - /** hist_bin_4 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 4 - */ - uint32_t hist_bin_4:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin4_reg_t; - -/** Type of hist_bin5 register - * result of histogram bin 5 - */ -typedef union { - struct { - /** hist_bin_5 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 5 - */ - uint32_t hist_bin_5:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin5_reg_t; - -/** Type of hist_bin6 register - * result of histogram bin 6 - */ -typedef union { - struct { - /** hist_bin_6 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 6 - */ - uint32_t hist_bin_6:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin6_reg_t; - -/** Type of hist_bin7 register - * result of histogram bin 7 - */ -typedef union { - struct { - /** hist_bin_7 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 7 - */ - uint32_t hist_bin_7:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin7_reg_t; - -/** Type of hist_bin8 register - * result of histogram bin 8 - */ -typedef union { - struct { - /** hist_bin_8 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 8 - */ - uint32_t hist_bin_8:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin8_reg_t; - -/** Type of hist_bin9 register - * result of histogram bin 9 - */ -typedef union { - struct { - /** hist_bin_9 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 9 - */ - uint32_t hist_bin_9:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin9_reg_t; - -/** Type of hist_bin10 register - * result of histogram bin 10 - */ -typedef union { - struct { - /** hist_bin_10 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 10 - */ - uint32_t hist_bin_10:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin10_reg_t; - -/** Type of hist_bin11 register - * result of histogram bin 11 - */ -typedef union { - struct { - /** hist_bin_11 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 11 - */ - uint32_t hist_bin_11:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin11_reg_t; - -/** Type of hist_bin12 register - * result of histogram bin 12 - */ -typedef union { - struct { - /** hist_bin_12 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 12 - */ - uint32_t hist_bin_12:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin12_reg_t; - -/** Type of hist_bin13 register - * result of histogram bin 13 - */ -typedef union { - struct { - /** hist_bin_13 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 13 - */ - uint32_t hist_bin_13:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin13_reg_t; - -/** Type of hist_bin14 register - * result of histogram bin 14 - */ -typedef union { - struct { - /** hist_bin_14 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 14 - */ - uint32_t hist_bin_14:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin14_reg_t; - -/** Type of hist_bin15 register - * result of histogram bin 15 - */ -typedef union { - struct { - /** hist_bin_15 : RO; bitpos: [16:0]; default: 0; - * this field represents result of histogram bin 15 - */ - uint32_t hist_bin_15:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} isp_hist_bin15_reg_t; - -/** Type of rdn_eco_cs register - * rdn eco cs register - */ -typedef union { - struct { - /** rdn_eco_en : R/W; bitpos: [0]; default: 0; - * rdn_eco_en - */ - uint32_t rdn_eco_en:1; - /** rdn_eco_result : RO; bitpos: [1]; default: 0; - * rdn_eco_result - */ - uint32_t rdn_eco_result:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} isp_rdn_eco_cs_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of int_raw register - * raw interrupt register - */ -typedef union { - struct { - /** isp_data_type_err_int_raw : R/SS/WTC; bitpos: [0]; default: 0; - * the raw interrupt status of input data type error. isp only support RGB bayer data - * type, other type will report type_err_int - */ - uint32_t isp_data_type_err_int_raw:1; - /** isp_async_fifo_ovf_int_raw : R/SS/WTC; bitpos: [1]; default: 0; - * the raw interrupt status of isp input fifo overflow - */ - uint32_t isp_async_fifo_ovf_int_raw:1; - /** isp_buf_full_int_raw : R/SS/WTC; bitpos: [2]; default: 0; - * the raw interrupt status of isp input buffer full - */ - uint32_t isp_buf_full_int_raw:1; - /** isp_hvnum_setting_err_int_raw : R/SS/WTC; bitpos: [3]; default: 0; - * the raw interrupt status of hnum and vnum setting format error - */ - uint32_t isp_hvnum_setting_err_int_raw:1; - /** isp_data_type_setting_err_int_raw : R/SS/WTC; bitpos: [4]; default: 0; - * the raw interrupt status of setting invalid reg_data_type - */ - uint32_t isp_data_type_setting_err_int_raw:1; - /** isp_mipi_hnum_unmatch_int_raw : R/SS/WTC; bitpos: [5]; default: 0; - * the raw interrupt status of hnum setting unmatch with mipi input - */ - uint32_t isp_mipi_hnum_unmatch_int_raw:1; - /** dpc_check_done_int_raw : R/SS/WTC; bitpos: [6]; default: 0; - * the raw interrupt status of dpc check done - */ - uint32_t dpc_check_done_int_raw:1; - /** gamma_xcoord_err_int_raw : R/SS/WTC; bitpos: [7]; default: 0; - * the raw interrupt status of gamma setting error. it report the sum of the lengths - * represented by reg_gamma_x00~x0F isn't equal to 256 - */ - uint32_t gamma_xcoord_err_int_raw:1; - /** ae_monitor_int_raw : R/SS/WTC; bitpos: [8]; default: 0; - * the raw interrupt status of ae monitor - */ - uint32_t ae_monitor_int_raw:1; - /** ae_frame_done_int_raw : R/SS/WTC; bitpos: [9]; default: 0; - * the raw interrupt status of ae. - */ - uint32_t ae_frame_done_int_raw:1; - /** af_fdone_int_raw : R/SS/WTC; bitpos: [10]; default: 0; - * the raw interrupt status of af statistic. when auto_update enable, each frame done - * will send one int pulse when manual_update, each time when write 1 to - * reg_manual_update will send a int pulse when next frame done - */ - uint32_t af_fdone_int_raw:1; - /** af_env_int_raw : R/SS/WTC; bitpos: [11]; default: 0; - * the raw interrupt status of af monitor. send a int pulse when env_det function - * enabled and environment changes detected - */ - uint32_t af_env_int_raw:1; - /** awb_fdone_int_raw : R/SS/WTC; bitpos: [12]; default: 0; - * the raw interrupt status of awb. send a int pulse when statistic of one awb frame - * done - */ - uint32_t awb_fdone_int_raw:1; - /** hist_fdone_int_raw : R/SS/WTC; bitpos: [13]; default: 0; - * the raw interrupt status of histogram. send a int pulse when statistic of one frame - * histogram done - */ - uint32_t hist_fdone_int_raw:1; - /** frame_int_raw : R/SS/WTC; bitpos: [14]; default: 0; - * the raw interrupt status of isp frame end - */ - uint32_t frame_int_raw:1; - /** blc_frame_int_raw : R/SS/WTC; bitpos: [15]; default: 0; - * the raw interrupt status of blc frame done - */ - uint32_t blc_frame_int_raw:1; - /** lsc_frame_int_raw : R/SS/WTC; bitpos: [16]; default: 0; - * the raw interrupt status of lsc frame done - */ - uint32_t lsc_frame_int_raw:1; - /** dpc_frame_int_raw : R/SS/WTC; bitpos: [17]; default: 0; - * the raw interrupt status of dpc frame done - */ - uint32_t dpc_frame_int_raw:1; - /** bf_frame_int_raw : R/SS/WTC; bitpos: [18]; default: 0; - * the raw interrupt status of bf frame done - */ - uint32_t bf_frame_int_raw:1; - /** demosaic_frame_int_raw : R/SS/WTC; bitpos: [19]; default: 0; - * the raw interrupt status of demosaic frame done - */ - uint32_t demosaic_frame_int_raw:1; - /** median_frame_int_raw : R/SS/WTC; bitpos: [20]; default: 0; - * the raw interrupt status of median frame done - */ - uint32_t median_frame_int_raw:1; - /** ccm_frame_int_raw : R/SS/WTC; bitpos: [21]; default: 0; - * the raw interrupt status of ccm frame done - */ - uint32_t ccm_frame_int_raw:1; - /** gamma_frame_int_raw : R/SS/WTC; bitpos: [22]; default: 0; - * the raw interrupt status of gamma frame done - */ - uint32_t gamma_frame_int_raw:1; - /** rgb2yuv_frame_int_raw : R/SS/WTC; bitpos: [23]; default: 0; - * the raw interrupt status of rgb2yuv frame done - */ - uint32_t rgb2yuv_frame_int_raw:1; - /** sharp_frame_int_raw : R/SS/WTC; bitpos: [24]; default: 0; - * the raw interrupt status of sharp frame done - */ - uint32_t sharp_frame_int_raw:1; - /** color_frame_int_raw : R/SS/WTC; bitpos: [25]; default: 0; - * the raw interrupt status of color frame done - */ - uint32_t color_frame_int_raw:1; - /** yuv2rgb_frame_int_raw : R/SS/WTC; bitpos: [26]; default: 0; - * the raw interrupt status of yuv2rgb frame done - */ - uint32_t yuv2rgb_frame_int_raw:1; - /** tail_idi_frame_int_raw : R/SS/WTC; bitpos: [27]; default: 0; - * the raw interrupt status of isp_tail idi frame_end - */ - uint32_t tail_idi_frame_int_raw:1; - /** header_idi_frame_int_raw : R/SS/WTC; bitpos: [28]; default: 0; - * the raw interrupt status of real input frame end of isp_input - */ - uint32_t header_idi_frame_int_raw:1; - /** crop_frame_int_raw : R/SS/WTC; bitpos: [29]; default: 0; - * the raw interrupt status of crop frame done - */ - uint32_t crop_frame_int_raw:1; - /** wbg_frame_int_raw : R/SS/WTC; bitpos: [30]; default: 0; - * the raw interrupt status of wbg frame done - */ - uint32_t wbg_frame_int_raw:1; - /** crop_err_int_raw : R/SS/WTC; bitpos: [31]; default: 0; - * the raw interrupt status of crop error - */ - uint32_t crop_err_int_raw:1; - }; - uint32_t val; -} isp_int_raw_reg_t; - -/** Type of int_st register - * masked interrupt register - */ -typedef union { - struct { - /** isp_data_type_err_int_st : RO; bitpos: [0]; default: 0; - * the masked interrupt status of input data type error - */ - uint32_t isp_data_type_err_int_st:1; - /** isp_async_fifo_ovf_int_st : RO; bitpos: [1]; default: 0; - * the masked interrupt status of isp input fifo overflow - */ - uint32_t isp_async_fifo_ovf_int_st:1; - /** isp_buf_full_int_st : RO; bitpos: [2]; default: 0; - * the masked interrupt status of isp input buffer full - */ - uint32_t isp_buf_full_int_st:1; - /** isp_hvnum_setting_err_int_st : RO; bitpos: [3]; default: 0; - * the masked interrupt status of hnum and vnum setting format error - */ - uint32_t isp_hvnum_setting_err_int_st:1; - /** isp_data_type_setting_err_int_st : RO; bitpos: [4]; default: 0; - * the masked interrupt status of setting invalid reg_data_type - */ - uint32_t isp_data_type_setting_err_int_st:1; - /** isp_mipi_hnum_unmatch_int_st : RO; bitpos: [5]; default: 0; - * the masked interrupt status of hnum setting unmatch with mipi input - */ - uint32_t isp_mipi_hnum_unmatch_int_st:1; - /** dpc_check_done_int_st : RO; bitpos: [6]; default: 0; - * the masked interrupt status of dpc check done - */ - uint32_t dpc_check_done_int_st:1; - /** gamma_xcoord_err_int_st : RO; bitpos: [7]; default: 0; - * the masked interrupt status of gamma setting error - */ - uint32_t gamma_xcoord_err_int_st:1; - /** ae_monitor_int_st : RO; bitpos: [8]; default: 0; - * the masked interrupt status of ae monitor - */ - uint32_t ae_monitor_int_st:1; - /** ae_frame_done_int_st : RO; bitpos: [9]; default: 0; - * the masked interrupt status of ae - */ - uint32_t ae_frame_done_int_st:1; - /** af_fdone_int_st : RO; bitpos: [10]; default: 0; - * the masked interrupt status of af statistic - */ - uint32_t af_fdone_int_st:1; - /** af_env_int_st : RO; bitpos: [11]; default: 0; - * the masked interrupt status of af monitor - */ - uint32_t af_env_int_st:1; - /** awb_fdone_int_st : RO; bitpos: [12]; default: 0; - * the masked interrupt status of awb - */ - uint32_t awb_fdone_int_st:1; - /** hist_fdone_int_st : RO; bitpos: [13]; default: 0; - * the masked interrupt status of histogram - */ - uint32_t hist_fdone_int_st:1; - /** frame_int_st : RO; bitpos: [14]; default: 0; - * the masked interrupt status of isp frame end - */ - uint32_t frame_int_st:1; - /** blc_frame_int_st : RO; bitpos: [15]; default: 0; - * the masked interrupt status of blc frame done - */ - uint32_t blc_frame_int_st:1; - /** lsc_frame_int_st : RO; bitpos: [16]; default: 0; - * the masked interrupt status of lsc frame done - */ - uint32_t lsc_frame_int_st:1; - /** dpc_frame_int_st : RO; bitpos: [17]; default: 0; - * the masked interrupt status of dpc frame done - */ - uint32_t dpc_frame_int_st:1; - /** bf_frame_int_st : RO; bitpos: [18]; default: 0; - * the masked interrupt status of bf frame done - */ - uint32_t bf_frame_int_st:1; - /** demosaic_frame_int_st : RO; bitpos: [19]; default: 0; - * the masked interrupt status of demosaic frame done - */ - uint32_t demosaic_frame_int_st:1; - /** median_frame_int_st : RO; bitpos: [20]; default: 0; - * the masked interrupt status of median frame done - */ - uint32_t median_frame_int_st:1; - /** ccm_frame_int_st : RO; bitpos: [21]; default: 0; - * the masked interrupt status of ccm frame done - */ - uint32_t ccm_frame_int_st:1; - /** gamma_frame_int_st : RO; bitpos: [22]; default: 0; - * the masked interrupt status of gamma frame done - */ - uint32_t gamma_frame_int_st:1; - /** rgb2yuv_frame_int_st : RO; bitpos: [23]; default: 0; - * the masked interrupt status of rgb2yuv frame done - */ - uint32_t rgb2yuv_frame_int_st:1; - /** sharp_frame_int_st : RO; bitpos: [24]; default: 0; - * the masked interrupt status of sharp frame done - */ - uint32_t sharp_frame_int_st:1; - /** color_frame_int_st : RO; bitpos: [25]; default: 0; - * the masked interrupt status of color frame done - */ - uint32_t color_frame_int_st:1; - /** yuv2rgb_frame_int_st : RO; bitpos: [26]; default: 0; - * the masked interrupt status of yuv2rgb frame done - */ - uint32_t yuv2rgb_frame_int_st:1; - /** tail_idi_frame_int_st : RO; bitpos: [27]; default: 0; - * the masked interrupt status of isp_tail idi frame_end - */ - uint32_t tail_idi_frame_int_st:1; - /** header_idi_frame_int_st : RO; bitpos: [28]; default: 0; - * the masked interrupt status of real input frame end of isp_input - */ - uint32_t header_idi_frame_int_st:1; - /** crop_frame_int_st : RO; bitpos: [29]; default: 0; - * the masked interrupt status of crop frame done - */ - uint32_t crop_frame_int_st:1; - /** wbg_frame_int_st : RO; bitpos: [30]; default: 0; - * the masked interrupt status of wbg frame done - */ - uint32_t wbg_frame_int_st:1; - /** crop_err_int_st : RO; bitpos: [31]; default: 0; - * the masked interrupt status of crop error - */ - uint32_t crop_err_int_st:1; - }; - uint32_t val; -} isp_int_st_reg_t; - -/** Type of int_ena register - * interrupt enable register - */ -typedef union { - struct { - /** isp_data_type_err_int_ena : R/W; bitpos: [0]; default: 1; - * write 1 to enable input data type error - */ - uint32_t isp_data_type_err_int_ena:1; - /** isp_async_fifo_ovf_int_ena : R/W; bitpos: [1]; default: 1; - * write 1 to enable isp input fifo overflow - */ - uint32_t isp_async_fifo_ovf_int_ena:1; - /** isp_buf_full_int_ena : R/W; bitpos: [2]; default: 0; - * write 1 to enable isp input buffer full - */ - uint32_t isp_buf_full_int_ena:1; - /** isp_hvnum_setting_err_int_ena : R/W; bitpos: [3]; default: 0; - * write 1 to enable hnum and vnum setting format error - */ - uint32_t isp_hvnum_setting_err_int_ena:1; - /** isp_data_type_setting_err_int_ena : R/W; bitpos: [4]; default: 0; - * write 1 to enable setting invalid reg_data_type - */ - uint32_t isp_data_type_setting_err_int_ena:1; - /** isp_mipi_hnum_unmatch_int_ena : R/W; bitpos: [5]; default: 0; - * write 1 to enable hnum setting unmatch with mipi input - */ - uint32_t isp_mipi_hnum_unmatch_int_ena:1; - /** dpc_check_done_int_ena : R/W; bitpos: [6]; default: 1; - * write 1 to enable dpc check done - */ - uint32_t dpc_check_done_int_ena:1; - /** gamma_xcoord_err_int_ena : R/W; bitpos: [7]; default: 1; - * write 1 to enable gamma setting error - */ - uint32_t gamma_xcoord_err_int_ena:1; - /** ae_monitor_int_ena : R/W; bitpos: [8]; default: 0; - * write 1 to enable ae monitor - */ - uint32_t ae_monitor_int_ena:1; - /** ae_frame_done_int_ena : R/W; bitpos: [9]; default: 0; - * write 1 to enable ae - */ - uint32_t ae_frame_done_int_ena:1; - /** af_fdone_int_ena : R/W; bitpos: [10]; default: 0; - * write 1 to enable af statistic - */ - uint32_t af_fdone_int_ena:1; - /** af_env_int_ena : R/W; bitpos: [11]; default: 0; - * write 1 to enable af monitor - */ - uint32_t af_env_int_ena:1; - /** awb_fdone_int_ena : R/W; bitpos: [12]; default: 0; - * write 1 to enable awb - */ - uint32_t awb_fdone_int_ena:1; - /** hist_fdone_int_ena : R/W; bitpos: [13]; default: 0; - * write 1 to enable histogram - */ - uint32_t hist_fdone_int_ena:1; - /** frame_int_ena : R/W; bitpos: [14]; default: 0; - * write 1 to enable isp frame end - */ - uint32_t frame_int_ena:1; - /** blc_frame_int_ena : R/W; bitpos: [15]; default: 0; - * write 1 to enable blc frame done - */ - uint32_t blc_frame_int_ena:1; - /** lsc_frame_int_ena : R/W; bitpos: [16]; default: 0; - * write 1 to enable lsc frame done - */ - uint32_t lsc_frame_int_ena:1; - /** dpc_frame_int_ena : R/W; bitpos: [17]; default: 0; - * write 1 to enable dpc frame done - */ - uint32_t dpc_frame_int_ena:1; - /** bf_frame_int_ena : R/W; bitpos: [18]; default: 0; - * write 1 to enable bf frame done - */ - uint32_t bf_frame_int_ena:1; - /** demosaic_frame_int_ena : R/W; bitpos: [19]; default: 0; - * write 1 to enable demosaic frame done - */ - uint32_t demosaic_frame_int_ena:1; - /** median_frame_int_ena : R/W; bitpos: [20]; default: 0; - * write 1 to enable median frame done - */ - uint32_t median_frame_int_ena:1; - /** ccm_frame_int_ena : R/W; bitpos: [21]; default: 0; - * write 1 to enable ccm frame done - */ - uint32_t ccm_frame_int_ena:1; - /** gamma_frame_int_ena : R/W; bitpos: [22]; default: 0; - * write 1 to enable gamma frame done - */ - uint32_t gamma_frame_int_ena:1; - /** rgb2yuv_frame_int_ena : R/W; bitpos: [23]; default: 0; - * write 1 to enable rgb2yuv frame done - */ - uint32_t rgb2yuv_frame_int_ena:1; - /** sharp_frame_int_ena : R/W; bitpos: [24]; default: 0; - * write 1 to enable sharp frame done - */ - uint32_t sharp_frame_int_ena:1; - /** color_frame_int_ena : R/W; bitpos: [25]; default: 0; - * write 1 to enable color frame done - */ - uint32_t color_frame_int_ena:1; - /** yuv2rgb_frame_int_ena : R/W; bitpos: [26]; default: 0; - * write 1 to enable yuv2rgb frame done - */ - uint32_t yuv2rgb_frame_int_ena:1; - /** tail_idi_frame_int_ena : R/W; bitpos: [27]; default: 0; - * write 1 to enable isp_tail idi frame_end - */ - uint32_t tail_idi_frame_int_ena:1; - /** header_idi_frame_int_ena : R/W; bitpos: [28]; default: 0; - * write 1 to enable real input frame end of isp_input - */ - uint32_t header_idi_frame_int_ena:1; - /** crop_frame_int_ena : R/W; bitpos: [29]; default: 0; - * write 1 to enable crop frame done - */ - uint32_t crop_frame_int_ena:1; - /** wbg_frame_int_ena : R/W; bitpos: [30]; default: 0; - * write 1 to enable wbg frame done - */ - uint32_t wbg_frame_int_ena:1; - /** crop_err_int_ena : R/W; bitpos: [31]; default: 0; - * write 1 to enable crop error - */ - uint32_t crop_err_int_ena:1; - }; - uint32_t val; -} isp_int_ena_reg_t; - -/** Type of int_clr register - * interrupt clear register - */ -typedef union { - struct { - /** isp_data_type_err_int_clr : WT; bitpos: [0]; default: 0; - * write 1 to clear input data type error - */ - uint32_t isp_data_type_err_int_clr:1; - /** isp_async_fifo_ovf_int_clr : WT; bitpos: [1]; default: 0; - * write 1 to clear isp input fifo overflow - */ - uint32_t isp_async_fifo_ovf_int_clr:1; - /** isp_buf_full_int_clr : WT; bitpos: [2]; default: 0; - * write 1 to clear isp input buffer full - */ - uint32_t isp_buf_full_int_clr:1; - /** isp_hvnum_setting_err_int_clr : WT; bitpos: [3]; default: 0; - * write 1 to clear hnum and vnum setting format error - */ - uint32_t isp_hvnum_setting_err_int_clr:1; - /** isp_data_type_setting_err_int_clr : WT; bitpos: [4]; default: 0; - * write 1 to clear setting invalid reg_data_type - */ - uint32_t isp_data_type_setting_err_int_clr:1; - /** isp_mipi_hnum_unmatch_int_clr : WT; bitpos: [5]; default: 0; - * write 1 to clear hnum setting unmatch with mipi input - */ - uint32_t isp_mipi_hnum_unmatch_int_clr:1; - /** dpc_check_done_int_clr : WT; bitpos: [6]; default: 0; - * write 1 to clear dpc check done - */ - uint32_t dpc_check_done_int_clr:1; - /** gamma_xcoord_err_int_clr : WT; bitpos: [7]; default: 0; - * write 1 to clear gamma setting error - */ - uint32_t gamma_xcoord_err_int_clr:1; - /** ae_monitor_int_clr : WT; bitpos: [8]; default: 0; - * write 1 to clear ae monitor - */ - uint32_t ae_monitor_int_clr:1; - /** ae_frame_done_int_clr : WT; bitpos: [9]; default: 0; - * write 1 to clear ae - */ - uint32_t ae_frame_done_int_clr:1; - /** af_fdone_int_clr : WT; bitpos: [10]; default: 0; - * write 1 to clear af statistic - */ - uint32_t af_fdone_int_clr:1; - /** af_env_int_clr : WT; bitpos: [11]; default: 0; - * write 1 to clear af monitor - */ - uint32_t af_env_int_clr:1; - /** awb_fdone_int_clr : WT; bitpos: [12]; default: 0; - * write 1 to clear awb - */ - uint32_t awb_fdone_int_clr:1; - /** hist_fdone_int_clr : WT; bitpos: [13]; default: 0; - * write 1 to clear histogram - */ - uint32_t hist_fdone_int_clr:1; - /** frame_int_clr : WT; bitpos: [14]; default: 0; - * write 1 to clear isp frame end - */ - uint32_t frame_int_clr:1; - /** blc_frame_int_clr : WT; bitpos: [15]; default: 0; - * write 1 to clear blc frame done - */ - uint32_t blc_frame_int_clr:1; - /** lsc_frame_int_clr : WT; bitpos: [16]; default: 0; - * write 1 to clear lsc frame done - */ - uint32_t lsc_frame_int_clr:1; - /** dpc_frame_int_clr : WT; bitpos: [17]; default: 0; - * write 1 to clear dpc frame done - */ - uint32_t dpc_frame_int_clr:1; - /** bf_frame_int_clr : WT; bitpos: [18]; default: 0; - * write 1 to clear bf frame done - */ - uint32_t bf_frame_int_clr:1; - /** demosaic_frame_int_clr : WT; bitpos: [19]; default: 0; - * write 1 to clear demosaic frame done - */ - uint32_t demosaic_frame_int_clr:1; - /** median_frame_int_clr : WT; bitpos: [20]; default: 0; - * write 1 to clear median frame done - */ - uint32_t median_frame_int_clr:1; - /** ccm_frame_int_clr : WT; bitpos: [21]; default: 0; - * write 1 to clear ccm frame done - */ - uint32_t ccm_frame_int_clr:1; - /** gamma_frame_int_clr : WT; bitpos: [22]; default: 0; - * write 1 to clear gamma frame done - */ - uint32_t gamma_frame_int_clr:1; - /** rgb2yuv_frame_int_clr : WT; bitpos: [23]; default: 0; - * write 1 to clear rgb2yuv frame done - */ - uint32_t rgb2yuv_frame_int_clr:1; - /** sharp_frame_int_clr : WT; bitpos: [24]; default: 0; - * write 1 to clear sharp frame done - */ - uint32_t sharp_frame_int_clr:1; - /** color_frame_int_clr : WT; bitpos: [25]; default: 0; - * write 1 to clear color frame done - */ - uint32_t color_frame_int_clr:1; - /** yuv2rgb_frame_int_clr : WT; bitpos: [26]; default: 0; - * write 1 to clear yuv2rgb frame done - */ - uint32_t yuv2rgb_frame_int_clr:1; - /** tail_idi_frame_int_clr : WT; bitpos: [27]; default: 0; - * write 1 to clear isp_tail idi frame_end - */ - uint32_t tail_idi_frame_int_clr:1; - /** header_idi_frame_int_clr : WT; bitpos: [28]; default: 0; - * write 1 to clear real input frame end of isp_input - */ - uint32_t header_idi_frame_int_clr:1; - /** crop_frame_int_clr : WT; bitpos: [29]; default: 0; - * write 1 to clear crop frame done - */ - uint32_t crop_frame_int_clr:1; - /** wbg_frame_int_clr : WT; bitpos: [30]; default: 0; - * write 1 to clear wbg frame done - */ - uint32_t wbg_frame_int_clr:1; - /** crop_err_int_clr : WT; bitpos: [31]; default: 0; - * write 1 to clear crop error - */ - uint32_t crop_err_int_clr:1; - }; - uint32_t val; -} isp_int_clr_reg_t; - - -typedef struct { - volatile isp_ver_date_reg_t ver_date; - volatile isp_clk_en_reg_t clk_en; - volatile isp_cntl_reg_t cntl; - volatile isp_hsync_cnt_reg_t hsync_cnt; - volatile isp_frame_cfg_reg_t frame_cfg; - volatile isp_ccm_coef0_reg_t ccm_coef0; - volatile isp_ccm_coef1_reg_t ccm_coef1; - volatile isp_ccm_coef3_reg_t ccm_coef3; - volatile isp_ccm_coef4_reg_t ccm_coef4; - volatile isp_ccm_coef5_reg_t ccm_coef5; - volatile isp_bf_matrix_ctrl_reg_t bf_matrix_ctrl; - volatile isp_bf_sigma_reg_t bf_sigma; - volatile isp_bf_gau0_reg_t bf_gau0; - volatile isp_bf_gau1_reg_t bf_gau1; - volatile isp_dpc_ctrl_reg_t dpc_ctrl; - volatile isp_dpc_conf_reg_t dpc_conf; - volatile isp_dpc_matrix_ctrl_reg_t dpc_matrix_ctrl; - volatile isp_dpc_deadpix_cnt_reg_t dpc_deadpix_cnt; - volatile isp_lut_cmd_reg_t lut_cmd; - volatile isp_lut_wdata_reg_t lut_wdata; - volatile isp_lut_rdata_reg_t lut_rdata; - volatile isp_lsc_tablesize_reg_t lsc_tablesize; - volatile isp_demosaic_matrix_ctrl_reg_t demosaic_matrix_ctrl; - volatile isp_demosaic_grad_ratio_reg_t demosaic_grad_ratio; - volatile isp_median_matrix_ctrl_reg_t median_matrix_ctrl; - volatile isp_int_raw_reg_t int_raw; - volatile isp_int_st_reg_t int_st; - volatile isp_int_ena_reg_t int_ena; - volatile isp_int_clr_reg_t int_clr; - volatile isp_gamma_ctrl_reg_t gamma_ctrl; - volatile isp_gamma_ry1_reg_t gamma_ry1; - volatile isp_gamma_ry2_reg_t gamma_ry2; - volatile isp_gamma_ry3_reg_t gamma_ry3; - volatile isp_gamma_ry4_reg_t gamma_ry4; - volatile isp_gamma_gy1_reg_t gamma_gy1; - volatile isp_gamma_gy2_reg_t gamma_gy2; - volatile isp_gamma_gy3_reg_t gamma_gy3; - volatile isp_gamma_gy4_reg_t gamma_gy4; - volatile isp_gamma_by1_reg_t gamma_by1; - volatile isp_gamma_by2_reg_t gamma_by2; - volatile isp_gamma_by3_reg_t gamma_by3; - volatile isp_gamma_by4_reg_t gamma_by4; - volatile isp_gamma_rx1_reg_t gamma_rx1; - volatile isp_gamma_rx2_reg_t gamma_rx2; - volatile isp_gamma_gx1_reg_t gamma_gx1; - volatile isp_gamma_gx2_reg_t gamma_gx2; - volatile isp_gamma_bx1_reg_t gamma_bx1; - volatile isp_gamma_bx2_reg_t gamma_bx2; - volatile isp_ae_ctrl_reg_t ae_ctrl; - volatile isp_ae_monitor_reg_t ae_monitor; - volatile isp_ae_bx_reg_t ae_bx; - volatile isp_ae_by_reg_t ae_by; - volatile isp_ae_winpixnum_reg_t ae_winpixnum; - volatile isp_ae_win_reciprocal_reg_t ae_win_reciprocal; - volatile isp_ae_block_mean_0_reg_t ae_block_mean_0; - volatile isp_ae_block_mean_1_reg_t ae_block_mean_1; - volatile isp_ae_block_mean_2_reg_t ae_block_mean_2; - volatile isp_ae_block_mean_3_reg_t ae_block_mean_3; - volatile isp_ae_block_mean_4_reg_t ae_block_mean_4; - volatile isp_ae_block_mean_5_reg_t ae_block_mean_5; - volatile isp_ae_block_mean_6_reg_t ae_block_mean_6; - volatile isp_sharp_ctrl0_reg_t sharp_ctrl0; - volatile isp_sharp_filter0_reg_t sharp_filter0; - volatile isp_sharp_filter1_reg_t sharp_filter1; - volatile isp_sharp_filter2_reg_t sharp_filter2; - volatile isp_sharp_matrix_ctrl_reg_t sharp_matrix_ctrl; - volatile isp_sharp_ctrl1_reg_t sharp_ctrl1; - volatile isp_dma_cntl_reg_t dma_cntl; - volatile isp_dma_raw_data_reg_t dma_raw_data; - volatile isp_cam_cntl_reg_t cam_cntl; - volatile isp_cam_conf_reg_t cam_conf; - volatile isp_af_ctrl0_reg_t af_ctrl0; - volatile isp_af_ctrl1_reg_t af_ctrl1; - volatile isp_af_gen_th_ctrl_reg_t af_gen_th_ctrl; - volatile isp_af_env_user_th_sum_reg_t af_env_user_th_sum; - volatile isp_af_env_user_th_lum_reg_t af_env_user_th_lum; - volatile isp_af_threshold_reg_t af_threshold; - volatile isp_af_hscale_a_reg_t af_hscale_a; - volatile isp_af_vscale_a_reg_t af_vscale_a; - volatile isp_af_hscale_b_reg_t af_hscale_b; - volatile isp_af_vscale_b_reg_t af_vscale_b; - volatile isp_af_hscale_c_reg_t af_hscale_c; - volatile isp_af_vscale_c_reg_t af_vscale_c; - volatile isp_af_sum_a_reg_t af_sum_a; - volatile isp_af_sum_b_reg_t af_sum_b; - volatile isp_af_sum_c_reg_t af_sum_c; - volatile isp_af_lum_a_reg_t af_lum_a; - volatile isp_af_lum_b_reg_t af_lum_b; - volatile isp_af_lum_c_reg_t af_lum_c; - volatile isp_awb_mode_reg_t awb_mode; - volatile isp_awb_hscale_reg_t awb_hscale; - volatile isp_awb_vscale_reg_t awb_vscale; - volatile isp_awb_th_lum_reg_t awb_th_lum; - volatile isp_awb_th_rg_reg_t awb_th_rg; - volatile isp_awb_th_bg_reg_t awb_th_bg; - volatile isp_awb0_white_cnt_reg_t awb0_white_cnt; - volatile isp_awb0_acc_r_reg_t awb0_acc_r; - volatile isp_awb0_acc_g_reg_t awb0_acc_g; - volatile isp_awb0_acc_b_reg_t awb0_acc_b; - volatile isp_color_ctrl_reg_t color_ctrl; - volatile isp_blc_value_reg_t blc_value; - volatile isp_blc_ctrl0_reg_t blc_ctrl0; - volatile isp_blc_ctrl1_reg_t blc_ctrl1; - volatile isp_blc_ctrl2_reg_t blc_ctrl2; - volatile isp_blc_mean_reg_t blc_mean; - volatile isp_hist_mode_reg_t hist_mode; - volatile isp_hist_coeff_reg_t hist_coeff; - volatile isp_hist_offs_reg_t hist_offs; - volatile isp_hist_size_reg_t hist_size; - volatile isp_hist_seg0_reg_t hist_seg0; - volatile isp_hist_seg1_reg_t hist_seg1; - volatile isp_hist_seg2_reg_t hist_seg2; - volatile isp_hist_seg3_reg_t hist_seg3; - volatile isp_hist_weight0_reg_t hist_weight0; - volatile isp_hist_weight1_reg_t hist_weight1; - volatile isp_hist_weight2_reg_t hist_weight2; - volatile isp_hist_weight3_reg_t hist_weight3; - volatile isp_hist_weight4_reg_t hist_weight4; - volatile isp_hist_weight5_reg_t hist_weight5; - volatile isp_hist_weight6_reg_t hist_weight6; - volatile isp_hist_bin0_reg_t hist_bin0; - volatile isp_hist_bin1_reg_t hist_bin1; - volatile isp_hist_bin2_reg_t hist_bin2; - volatile isp_hist_bin3_reg_t hist_bin3; - volatile isp_hist_bin4_reg_t hist_bin4; - volatile isp_hist_bin5_reg_t hist_bin5; - volatile isp_hist_bin6_reg_t hist_bin6; - volatile isp_hist_bin7_reg_t hist_bin7; - volatile isp_hist_bin8_reg_t hist_bin8; - volatile isp_hist_bin9_reg_t hist_bin9; - volatile isp_hist_bin10_reg_t hist_bin10; - volatile isp_hist_bin11_reg_t hist_bin11; - volatile isp_hist_bin12_reg_t hist_bin12; - volatile isp_hist_bin13_reg_t hist_bin13; - volatile isp_hist_bin14_reg_t hist_bin14; - volatile isp_hist_bin15_reg_t hist_bin15; - volatile isp_mem_aux_ctrl_0_reg_t mem_aux_ctrl_0; - volatile isp_mem_aux_ctrl_1_reg_t mem_aux_ctrl_1; - volatile isp_mem_aux_ctrl_2_reg_t mem_aux_ctrl_2; - volatile isp_mem_aux_ctrl_3_reg_t mem_aux_ctrl_3; - volatile isp_mem_aux_ctrl_4_reg_t mem_aux_ctrl_4; - volatile isp_yuv_format_reg_t yuv_format; - volatile isp_rdn_eco_cs_reg_t rdn_eco_cs; - volatile isp_rdn_eco_low_reg_t rdn_eco_low; - volatile isp_rdn_eco_high_reg_t rdn_eco_high; - volatile isp_crop_ctrl_reg_t crop_ctrl; - volatile isp_crop_y_capture_reg_t crop_y_capture; - volatile isp_crop_x_capture_reg_t crop_x_capture; - volatile isp_crop_err_st_reg_t crop_err_st; - volatile isp_wbg_coef_r_reg_t wbg_coef_r; - volatile isp_wbg_coef_g_reg_t wbg_coef_g; - volatile isp_wbg_coef_b_reg_t wbg_coef_b; - volatile isp_color_hue_ctrl_reg_t color_hue_ctrl; - volatile isp_awb_bx_reg_t awb_bx; - volatile isp_awb_by_reg_t awb_by; - volatile isp_state_reg_t state; - volatile isp_shadow_reg_ctrl_reg_t shadow_reg_ctrl; -} isp_dev_t; - -extern isp_dev_t ISP; - -#ifndef __cplusplus -_Static_assert(sizeof(isp_dev_t) == 0x274, "Invalid size of isp_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/isp_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/isp_struct.h index 8f65f76752c2..550392851342 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/isp_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/isp_struct.h @@ -107,7 +107,15 @@ typedef union { * this bit configures the clk force on of all isp memory. 0: disable, 1: enable */ uint32_t isp_mem_clk_force_on:1; - uint32_t reserved_19:13; + /** clk_crop_force_on : R/W; bitpos: [19]; default: 0; + * this bit configures the clk force on of crop. 0: disable, 1: enable + */ + uint32_t clk_crop_force_on:1; + /** clk_wbg_force_on : R/W; bitpos: [20]; default: 0; + * this bit configures the clk force on of wbg. 0: disable, 1: enable + */ + uint32_t clk_wbg_force_on:1; + uint32_t reserved_21:11; }; uint32_t val; } isp_clk_en_reg_t; @@ -189,7 +197,15 @@ typedef union { * this bit configures hist enable. 0: disable, 1: enable */ uint32_t hist_en:1; - uint32_t reserved_18:6; + /** crop_en : R/W; bitpos: [18]; default: 0; + * this bit configures crop enable. 0: disable, 1: enable + */ + uint32_t crop_en:1; + /** wbg_en : R/W; bitpos: [19]; default: 0; + * this bit configures wbg enable. 0: disable, 1: enable + */ + uint32_t wbg_en:1; + uint32_t reserved_20:4; /** byte_endian_order : R/W; bitpos: [24]; default: 0; * select input idi data byte_endian_order when isp is bypass, 0: csi_data[31:0], 1: * {[7:0], [15:8], [23:16], [31:24]} @@ -247,11 +263,11 @@ typedef union { */ uint32_t bayer_mode:2; /** hsync_start_exist : R/W; bitpos: [29]; default: 1; - * this bit configures the line end start exist or not. 0: not exist, 1: exist + * this bit configures the line end packet exist or not. 0: not exist, 1: exist */ uint32_t hsync_start_exist:1; /** hsync_end_exist : R/W; bitpos: [30]; default: 1; - * this bit configures the line end packet exist or not. 0: not exist, 1: exist + * this bit configures the line start packet exist or not. 0: not exist, 1: exist */ uint32_t hsync_end_exist:1; uint32_t reserved_31:1; @@ -264,11 +280,11 @@ typedef union { */ typedef union { struct { - /** ccm_rr : R/W; bitpos: [12:0]; default: 1856; + /** ccm_rr : R/W; bitpos: [12:0]; default: 256; * this field configures the color correction matrix coefficient */ uint32_t ccm_rr:13; - /** ccm_rg : R/W; bitpos: [25:13]; default: 4736; + /** ccm_rg : R/W; bitpos: [25:13]; default: 0; * this field configures the color correction matrix coefficient */ uint32_t ccm_rg:13; @@ -282,11 +298,11 @@ typedef union { */ typedef union { struct { - /** ccm_rb : R/W; bitpos: [12:0]; default: 4288; + /** ccm_rb : R/W; bitpos: [12:0]; default: 0; * this field configures the color correction matrix coefficient */ uint32_t ccm_rb:13; - /** ccm_gr : R/W; bitpos: [25:13]; default: 4416; + /** ccm_gr : R/W; bitpos: [25:13]; default: 0; * this field configures the color correction matrix coefficient */ uint32_t ccm_gr:13; @@ -300,11 +316,11 @@ typedef union { */ typedef union { struct { - /** ccm_gg : R/W; bitpos: [12:0]; default: 1664; + /** ccm_gg : R/W; bitpos: [12:0]; default: 256; * this field configures the color correction matrix coefficient */ uint32_t ccm_gg:13; - /** ccm_gb : R/W; bitpos: [25:13]; default: 4352; + /** ccm_gb : R/W; bitpos: [25:13]; default: 0; * this field configures the color correction matrix coefficient */ uint32_t ccm_gb:13; @@ -318,11 +334,11 @@ typedef union { */ typedef union { struct { - /** ccm_br : R/W; bitpos: [12:0]; default: 4160; + /** ccm_br : R/W; bitpos: [12:0]; default: 0; * this field configures the color correction matrix coefficient */ uint32_t ccm_br:13; - /** ccm_bg : R/W; bitpos: [25:13]; default: 4800; + /** ccm_bg : R/W; bitpos: [25:13]; default: 0; * this field configures the color correction matrix coefficient */ uint32_t ccm_bg:13; @@ -336,7 +352,7 @@ typedef union { */ typedef union { struct { - /** ccm_bb : R/W; bitpos: [12:0]; default: 1856; + /** ccm_bb : R/W; bitpos: [12:0]; default: 256; * this field configures the color correction matrix coefficient */ uint32_t ccm_bb:13; @@ -557,7 +573,7 @@ typedef union { */ uint32_t lut_addr:12; /** lut_num : WT; bitpos: [15:12]; default: 0; - * this field configures the lut selection. 0000:LSC LUT 0001:DPC LUT + * this field configures the lut selection. 0000:LSC LUT. 0001:DPC LUT. 0010:AWB LUT */ uint32_t lut_num:4; /** lut_cmd : WT; bitpos: [16]; default: 0; @@ -689,6 +705,7 @@ typedef union { uint32_t val; } isp_gamma_ctrl_reg_t; + /** Type of gamma_y1 register * point of Y-axis of r/g/b channel gamma curve register 1 */ @@ -1018,6 +1035,28 @@ typedef union { uint32_t val; } isp_sharp_ctrl0_reg_t; +/** Type of sharp_filter0 register + * sharp usm config register + */ +typedef union { + struct { + /** sharp_filter_coe0 : R/W; bitpos: [4:0]; default: 1; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe0:5; + /** sharp_filter_coe1 : R/W; bitpos: [9:5]; default: 2; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe1:5; + /** sharp_filter_coe2 : R/W; bitpos: [14:10]; default: 1; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe2:5; + uint32_t reserved_15:17; + }; + uint32_t val; +} isp_sharp_filter_reg_t; + /** Type of sharp_filter0 register * sharp usm config register 0 */ @@ -1084,25 +1123,6 @@ typedef union { uint32_t val; } isp_sharp_filter2_reg_t; -typedef union { - struct { - /** sharp_filter_coe0 : R/W; bitpos: [4:0]; default: 1; - * this field configures usm filter coefficient - */ - uint32_t sharp_filter_coe0:5; - /** sharp_filter_coe1 : R/W; bitpos: [9:5]; default: 2; - * this field configures usm filter coefficient - */ - uint32_t sharp_filter_coe1:5; - /** sharp_filter_coe2 : R/W; bitpos: [14:10]; default: 1; - * this field configures usm filter coefficient - */ - uint32_t sharp_filter_coe2:5; - uint32_t reserved_15:17; - }; - uint32_t val; -} isp_sharp_filter_reg_t; - /** Type of sharp_matrix_ctrl register * sharp pix2matrix ctrl */ @@ -1264,7 +1284,11 @@ typedef union { * this bit configures vsync filter en */ uint32_t cam_vsync_filter_en:1; - uint32_t reserved_15:17; + /** cam_de_only : R/W; bitpos: [15]; default: 0; + * configures whether cam inf only has de, no hsync data. 0: has hsync, 1: no hsync + */ + uint32_t cam_de_only:1; + uint32_t reserved_16:16; }; uint32_t val; } isp_cam_conf_reg_t; @@ -1839,7 +1863,6 @@ typedef union { uint32_t val; } isp_hist_seg_reg_t; - /** Type of hist_seg0 register * histogram bin control register 0 */ @@ -1938,7 +1961,7 @@ typedef union { } isp_hist_seg3_reg_t; /** Type of hist_weight register - * histogram sub-window weight register 0 + * histogram sub-window weight register */ typedef union { struct { @@ -2249,6 +2272,244 @@ typedef union { uint32_t val; } isp_rdn_eco_high_reg_t; +/** Type of crop_ctrl register + * isp_crop ctrl register + */ +typedef union { + struct { + /** crop_sft_rst : WT; bitpos: [0]; default: 0; + * Write 1 to clear err st + */ + uint32_t crop_sft_rst:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} isp_crop_ctrl_reg_t; + +/** Type of crop_y_capture register + * isp_crop row capture range register + */ +typedef union { + struct { + /** crop_y_start : R/W; bitpos: [11:0]; default: 0; + * isp_crop capture row start index + */ + uint32_t crop_y_start:12; + /** crop_y_end : R/W; bitpos: [23:12]; default: 0; + * isp_crop capture row end index + */ + uint32_t crop_y_end:12; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_crop_y_capture_reg_t; + +/** Type of crop_x_capture register + * isp_crop col capture range register + */ +typedef union { + struct { + /** crop_x_start : R/W; bitpos: [11:0]; default: 0; + * isp_crop capture col start index + */ + uint32_t crop_x_start:12; + /** crop_x_end : R/W; bitpos: [23:12]; default: 0; + * isp_crop capture col end index + */ + uint32_t crop_x_end:12; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_crop_x_capture_reg_t; + +/** Type of crop_err_st register + * crop error state register + */ +typedef union { + struct { + /** crop_y_mismatch : RO; bitpos: [0]; default: 0; + * Represents isp_corp row end index over image size + */ + uint32_t crop_y_mismatch:1; + /** crop_x_mismatch : RO; bitpos: [1]; default: 0; + * Represents isp_corp col end index over image size + */ + uint32_t crop_x_mismatch:1; + /** crop_y_end_even : RO; bitpos: [2]; default: 0; + * Represents isp_corp row end index is an even number + */ + uint32_t crop_y_end_even:1; + /** crop_x_end_even : RO; bitpos: [3]; default: 0; + * Represents isp_corp col end index is an even number + */ + uint32_t crop_x_end_even:1; + /** crop_y_start_odd : RO; bitpos: [4]; default: 0; + * Represents isp_corp row start index is an odd number + */ + uint32_t crop_y_start_odd:1; + /** crop_x_start_odd : RO; bitpos: [5]; default: 0; + * Represents isp_corp col start index is an odd number + */ + uint32_t crop_x_start_odd:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} isp_crop_err_st_reg_t; + +/** Type of wbg_coef_r register + * white balance red gain register 0 + */ +typedef union { + struct { + /** wbg_r : R/W; bitpos: [11:0]; default: 256; + * Configures the white balance red gain + */ + uint32_t wbg_r:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} isp_wbg_coef_r_reg_t; + +/** Type of wbg_coef_g register + * white balance green gain register 0 + */ +typedef union { + struct { + /** wbg_g : R/W; bitpos: [11:0]; default: 256; + * Configures the white balance green gain + */ + uint32_t wbg_g:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} isp_wbg_coef_g_reg_t; + +/** Type of wbg_coef_b register + * white balance blue gain register 0 + */ +typedef union { + struct { + /** wbg_b : R/W; bitpos: [11:0]; default: 256; + * Configures the white balance blue gain + */ + uint32_t wbg_b:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} isp_wbg_coef_b_reg_t; + +/** Type of color_hue_ctrl register + * color control register + */ +typedef union { + struct { + /** color_hue_h : R/W; bitpos: [0]; default: 0; + * Configures the color hue angle most bit + */ + uint32_t color_hue_h:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} isp_color_hue_ctrl_reg_t; + +/** Type of awb_bx register + * awb window register in x-direction + */ +typedef union { + struct { + /** awb_x_bsize : R/W; bitpos: [11:0]; default: 0; + * Configures every block x size, min number is 4 + */ + uint32_t awb_x_bsize:12; + /** awb_x_start : R/W; bitpos: [23:12]; default: 0; + * Configures first block start x address + */ + uint32_t awb_x_start:12; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_awb_bx_reg_t; + +/** Type of awb_by register + * awb window register in y-direction + */ +typedef union { + struct { + /** awb_y_bsize : R/W; bitpos: [11:0]; default: 0; + * Configures every block y size + */ + uint32_t awb_y_bsize:12; + /** awb_y_start : R/W; bitpos: [23:12]; default: 0; + * Configures first block start y address + */ + uint32_t awb_y_start:12; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_awb_by_reg_t; + +/** Type of state register + * awb window register in y-direction + */ +typedef union { + struct { + /** tail_busy : RO; bitpos: [0]; default: 0; + * Represents isp_tail state + */ + uint32_t tail_busy:1; + /** header_busy : RO; bitpos: [1]; default: 0; + * Represents isp_header state + */ + uint32_t header_busy:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} isp_state_reg_t; + +/** Type of shadow_reg_ctrl register + * shadow register ctrl register + */ +typedef union { + struct { + /** blc_update : R/W; bitpos: [0]; default: 0; + * Write 1 to update blc configuration register + */ + uint32_t blc_update:1; + /** dpc_update : R/W; bitpos: [1]; default: 0; + * Write 1 to update dpc configuration register + */ + uint32_t dpc_update:1; + /** bf_update : R/W; bitpos: [2]; default: 0; + * Write 1 to update bf configuration register + */ + uint32_t bf_update:1; + /** wbg_update : R/W; bitpos: [3]; default: 0; + * Write 1 to update wbg configuration register + */ + uint32_t wbg_update:1; + /** ccm_update : R/W; bitpos: [4]; default: 0; + * Write 1 to update ccm configuration register + */ + uint32_t ccm_update:1; + uint32_t reserved_5:1; + /** sharp_update : R/W; bitpos: [6]; default: 0; + * Write 1 to update sharp configuration register + */ + uint32_t sharp_update:1; + /** color_update : R/W; bitpos: [7]; default: 0; + * Write 1 to update color configuration register + */ + uint32_t color_update:1; + uint32_t reserved_8:22; + /** shadow_update_sel : R/W; bitpos: [31:30]; default: 1; + * Configures shadow register update type. 0: no shadow register. 1: update every + * vsyn. 2: update only the next vsync after write reg_xxx_update + */ + uint32_t shadow_update_sel:2; + }; + uint32_t val; +} isp_shadow_reg_ctrl_reg_t; + /** Group: Status Registers */ /** Type of dpc_deadpix_cnt register @@ -2455,6 +2716,7 @@ typedef union { }; uint32_t val; } isp_ae_block_mean_6_reg_t; + /** Type of af_sum_a register * result of sum of af window a */ @@ -2629,7 +2891,231 @@ typedef union { uint32_t reserved_17:15; }; uint32_t val; -} isp_hist_binn_reg_t; +} isp_hist_bin_reg_t; + +/** Type of hist_bin0 register + * result of histogram bin 0 + */ +typedef union { + struct { + /** hist_bin_0 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 0 + */ + uint32_t hist_bin_0:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin0_reg_t; + +/** Type of hist_bin1 register + * result of histogram bin 1 + */ +typedef union { + struct { + /** hist_bin_1 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 1 + */ + uint32_t hist_bin_1:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin1_reg_t; + +/** Type of hist_bin2 register + * result of histogram bin 2 + */ +typedef union { + struct { + /** hist_bin_2 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 2 + */ + uint32_t hist_bin_2:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin2_reg_t; + +/** Type of hist_bin3 register + * result of histogram bin 3 + */ +typedef union { + struct { + /** hist_bin_3 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 3 + */ + uint32_t hist_bin_3:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin3_reg_t; + +/** Type of hist_bin4 register + * result of histogram bin 4 + */ +typedef union { + struct { + /** hist_bin_4 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 4 + */ + uint32_t hist_bin_4:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin4_reg_t; + +/** Type of hist_bin5 register + * result of histogram bin 5 + */ +typedef union { + struct { + /** hist_bin_5 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 5 + */ + uint32_t hist_bin_5:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin5_reg_t; + +/** Type of hist_bin6 register + * result of histogram bin 6 + */ +typedef union { + struct { + /** hist_bin_6 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 6 + */ + uint32_t hist_bin_6:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin6_reg_t; + +/** Type of hist_bin7 register + * result of histogram bin 7 + */ +typedef union { + struct { + /** hist_bin_7 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 7 + */ + uint32_t hist_bin_7:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin7_reg_t; + +/** Type of hist_bin8 register + * result of histogram bin 8 + */ +typedef union { + struct { + /** hist_bin_8 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 8 + */ + uint32_t hist_bin_8:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin8_reg_t; + +/** Type of hist_bin9 register + * result of histogram bin 9 + */ +typedef union { + struct { + /** hist_bin_9 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 9 + */ + uint32_t hist_bin_9:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin9_reg_t; + +/** Type of hist_bin10 register + * result of histogram bin 10 + */ +typedef union { + struct { + /** hist_bin_10 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 10 + */ + uint32_t hist_bin_10:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin10_reg_t; + +/** Type of hist_bin11 register + * result of histogram bin 11 + */ +typedef union { + struct { + /** hist_bin_11 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 11 + */ + uint32_t hist_bin_11:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin11_reg_t; + +/** Type of hist_bin12 register + * result of histogram bin 12 + */ +typedef union { + struct { + /** hist_bin_12 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 12 + */ + uint32_t hist_bin_12:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin12_reg_t; + +/** Type of hist_bin13 register + * result of histogram bin 13 + */ +typedef union { + struct { + /** hist_bin_13 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 13 + */ + uint32_t hist_bin_13:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin13_reg_t; + +/** Type of hist_bin14 register + * result of histogram bin 14 + */ +typedef union { + struct { + /** hist_bin_14 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 14 + */ + uint32_t hist_bin_14:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin14_reg_t; + +/** Type of hist_bin15 register + * result of histogram bin 15 + */ +typedef union { + struct { + /** hist_bin_15 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 15 + */ + uint32_t hist_bin_15:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin15_reg_t; /** Type of rdn_eco_cs register * rdn eco cs register @@ -2779,7 +3265,18 @@ typedef union { * the raw interrupt status of real input frame end of isp_input */ uint32_t header_idi_frame_int_raw:1; - uint32_t reserved_29:3; + /** crop_frame_int_raw : R/SS/WTC; bitpos: [29]; default: 0; + * the raw interrupt status of crop frame done + */ + uint32_t crop_frame_int_raw:1; + /** wbg_frame_int_raw : R/SS/WTC; bitpos: [30]; default: 0; + * the raw interrupt status of wbg frame done + */ + uint32_t wbg_frame_int_raw:1; + /** crop_err_int_raw : R/SS/WTC; bitpos: [31]; default: 0; + * the raw interrupt status of crop error + */ + uint32_t crop_err_int_raw:1; }; uint32_t val; } isp_int_raw_reg_t; @@ -2905,7 +3402,18 @@ typedef union { * the masked interrupt status of real input frame end of isp_input */ uint32_t header_idi_frame_int_st:1; - uint32_t reserved_29:3; + /** crop_frame_int_st : RO; bitpos: [29]; default: 0; + * the masked interrupt status of crop frame done + */ + uint32_t crop_frame_int_st:1; + /** wbg_frame_int_st : RO; bitpos: [30]; default: 0; + * the masked interrupt status of wbg frame done + */ + uint32_t wbg_frame_int_st:1; + /** crop_err_int_st : RO; bitpos: [31]; default: 0; + * the masked interrupt status of crop error + */ + uint32_t crop_err_int_st:1; }; uint32_t val; } isp_int_st_reg_t; @@ -3031,7 +3539,18 @@ typedef union { * write 1 to enable real input frame end of isp_input */ uint32_t header_idi_frame_int_ena:1; - uint32_t reserved_29:3; + /** crop_frame_int_ena : R/W; bitpos: [29]; default: 0; + * write 1 to enable crop frame done + */ + uint32_t crop_frame_int_ena:1; + /** wbg_frame_int_ena : R/W; bitpos: [30]; default: 0; + * write 1 to enable wbg frame done + */ + uint32_t wbg_frame_int_ena:1; + /** crop_err_int_ena : R/W; bitpos: [31]; default: 0; + * write 1 to enable crop error + */ + uint32_t crop_err_int_ena:1; }; uint32_t val; } isp_int_ena_reg_t; @@ -3157,7 +3676,18 @@ typedef union { * write 1 to clear real input frame end of isp_input */ uint32_t header_idi_frame_int_clr:1; - uint32_t reserved_29:3; + /** crop_frame_int_clr : WT; bitpos: [29]; default: 0; + * write 1 to clear crop frame done + */ + uint32_t crop_frame_int_clr:1; + /** wbg_frame_int_clr : WT; bitpos: [30]; default: 0; + * write 1 to clear wbg frame done + */ + uint32_t wbg_frame_int_clr:1; + /** crop_err_int_clr : WT; bitpos: [31]; default: 0; + * write 1 to clear crop error + */ + uint32_t crop_err_int_clr:1; }; uint32_t val; } isp_int_clr_reg_t; @@ -3174,7 +3704,7 @@ typedef struct { volatile isp_gamma_x2_reg_t gamma_x2; } isp_gamma_x_reg_t; -typedef struct { +typedef struct isp_dev_t { volatile isp_ver_date_reg_t ver_date; volatile isp_clk_en_reg_t clk_en; volatile isp_cntl_reg_t cntl; @@ -3262,7 +3792,7 @@ typedef struct { volatile isp_hist_size_reg_t hist_size; volatile isp_hist_seg_reg_t hist_seg[4]; volatile isp_hist_weight_reg_t hist_weight[7]; - volatile isp_hist_binn_reg_t hist_binn[16]; + volatile isp_hist_bin_reg_t hist_bin[16]; volatile isp_mem_aux_ctrl_0_reg_t mem_aux_ctrl_0; volatile isp_mem_aux_ctrl_1_reg_t mem_aux_ctrl_1; volatile isp_mem_aux_ctrl_2_reg_t mem_aux_ctrl_2; @@ -3272,12 +3802,24 @@ typedef struct { volatile isp_rdn_eco_cs_reg_t rdn_eco_cs; volatile isp_rdn_eco_low_reg_t rdn_eco_low; volatile isp_rdn_eco_high_reg_t rdn_eco_high; + volatile isp_crop_ctrl_reg_t crop_ctrl; + volatile isp_crop_y_capture_reg_t crop_y_capture; + volatile isp_crop_x_capture_reg_t crop_x_capture; + volatile isp_crop_err_st_reg_t crop_err_st; + volatile isp_wbg_coef_r_reg_t wbg_coef_r; + volatile isp_wbg_coef_g_reg_t wbg_coef_g; + volatile isp_wbg_coef_b_reg_t wbg_coef_b; + volatile isp_color_hue_ctrl_reg_t color_hue_ctrl; + volatile isp_awb_bx_reg_t awb_bx; + volatile isp_awb_by_reg_t awb_by; + volatile isp_state_reg_t state; + volatile isp_shadow_reg_ctrl_reg_t shadow_reg_ctrl; } isp_dev_t; extern isp_dev_t ISP; #ifndef __cplusplus -_Static_assert(sizeof(isp_dev_t) == 0x244, "Invalid size of isp_dev_t structure"); +_Static_assert(sizeof(isp_dev_t) == 0x274, "Invalid size of isp_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_reg.h deleted file mode 100644 index b10ff9f37930..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_reg.h +++ /dev/null @@ -1,3116 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** LEDC_CH0_CONF0_REG register - * Configuration register 0 for channel 0 - */ -#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) -/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 0 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH0 0x00000003U -#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) -#define LEDC_TIMER_SEL_CH0_V 0x00000003U -#define LEDC_TIMER_SEL_CH0_S 0 -/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 0. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) -#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH0_S 2 -/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 0 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH0 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH0 (BIT(3)) -#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) -#define LEDC_IDLE_LV_CH0_V 0x00000001U -#define LEDC_IDLE_LV_CH0_S 3 -/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0, - * LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0, LEDC_DUTY_CYCLE_CH0, - * LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and LEDC_OVF_CNT_EN_CH0 fields for channel - * 0, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH0 (BIT(4)) -#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) -#define LEDC_PARA_UP_CH0_V 0x00000001U -#define LEDC_PARA_UP_CH0_S 4 -/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH0_INT interrupt - * will be triggered when channel 0 overflows for (LEDC_OVF_NUM_CH0 + 1) times. - */ -#define LEDC_OVF_NUM_CH0 0x000003FFU -#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) -#define LEDC_OVF_NUM_CH0_V 0x000003FFU -#define LEDC_OVF_NUM_CH0_S 5 -/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 0. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) -#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH0_S 15 -/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 0. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) -#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH0_S 16 - -/** LEDC_CH0_HPOINT_REG register - * High point register for channel 0 - */ -#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4) -/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 0. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH0 0x000FFFFFU -#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) -#define LEDC_HPOINT_CH0_V 0x000FFFFFU -#define LEDC_HPOINT_CH0_S 0 - -/** LEDC_CH0_DUTY_REG register - * Initial duty cycle register for channel 0 - */ -#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8) -/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 0. - */ -#define LEDC_DUTY_CH0 0x01FFFFFFU -#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) -#define LEDC_DUTY_CH0_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_S 0 - -/** LEDC_CH0_CONF1_REG register - * Configuration register 1 for channel 0 - */ -#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) -/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH0 (BIT(31)) -#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) -#define LEDC_DUTY_START_CH0_V 0x00000001U -#define LEDC_DUTY_START_CH0_S 31 - -/** LEDC_CH0_DUTY_R_REG register - * Current duty cycle register for channel 0 - */ -#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10) -/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 0. - */ -#define LEDC_DUTY_CH0_R 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) -#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_S 0 - -/** LEDC_CH1_CONF0_REG register - * Configuration register 0 for channel 1 - */ -#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) -/** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 1 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH1 0x00000003U -#define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) -#define LEDC_TIMER_SEL_CH1_V 0x00000003U -#define LEDC_TIMER_SEL_CH1_S 0 -/** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 1. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH1 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) -#define LEDC_SIG_OUT_EN_CH1_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH1_S 2 -/** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 1 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH1 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH1 (BIT(3)) -#define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) -#define LEDC_IDLE_LV_CH1_V 0x00000001U -#define LEDC_IDLE_LV_CH1_S 3 -/** LEDC_PARA_UP_CH1 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1, - * LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1, - * LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel - * 1, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH1 (BIT(4)) -#define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) -#define LEDC_PARA_UP_CH1_V 0x00000001U -#define LEDC_PARA_UP_CH1_S 4 -/** LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH1_INT interrupt - * will be triggered when channel 1 overflows for (LEDC_OVF_NUM_CH1 + 1) times. - */ -#define LEDC_OVF_NUM_CH1 0x000003FFU -#define LEDC_OVF_NUM_CH1_M (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S) -#define LEDC_OVF_NUM_CH1_V 0x000003FFU -#define LEDC_OVF_NUM_CH1_S 5 -/** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 1. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH1 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) -#define LEDC_OVF_CNT_EN_CH1_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH1_S 15 -/** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 1. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) -#define LEDC_OVF_CNT_RESET_CH1_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH1_S 16 - -/** LEDC_CH1_HPOINT_REG register - * High point register for channel 1 - */ -#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18) -/** LEDC_HPOINT_CH1 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 1. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH1 0x000FFFFFU -#define LEDC_HPOINT_CH1_M (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S) -#define LEDC_HPOINT_CH1_V 0x000FFFFFU -#define LEDC_HPOINT_CH1_S 0 - -/** LEDC_CH1_DUTY_REG register - * Initial duty cycle register for channel 1 - */ -#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c) -/** LEDC_DUTY_CH1 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 1. - */ -#define LEDC_DUTY_CH1 0x01FFFFFFU -#define LEDC_DUTY_CH1_M (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S) -#define LEDC_DUTY_CH1_V 0x01FFFFFFU -#define LEDC_DUTY_CH1_S 0 - -/** LEDC_CH1_CONF1_REG register - * Configuration register 1 for channel 1 - */ -#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) -/** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH1 (BIT(31)) -#define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) -#define LEDC_DUTY_START_CH1_V 0x00000001U -#define LEDC_DUTY_START_CH1_S 31 - -/** LEDC_CH1_DUTY_R_REG register - * Current duty cycle register for channel 1 - */ -#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24) -/** LEDC_DUTY_CH1_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 1. - */ -#define LEDC_DUTY_CH1_R 0x01FFFFFFU -#define LEDC_DUTY_CH1_R_M (LEDC_DUTY_CH1_R_V << LEDC_DUTY_CH1_R_S) -#define LEDC_DUTY_CH1_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH1_R_S 0 - -/** LEDC_CH2_CONF0_REG register - * Configuration register 0 for channel 2 - */ -#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) -/** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 2 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH2 0x00000003U -#define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) -#define LEDC_TIMER_SEL_CH2_V 0x00000003U -#define LEDC_TIMER_SEL_CH2_S 0 -/** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 2. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH2 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) -#define LEDC_SIG_OUT_EN_CH2_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH2_S 2 -/** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 2 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH2 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH2 (BIT(3)) -#define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) -#define LEDC_IDLE_LV_CH2_V 0x00000001U -#define LEDC_IDLE_LV_CH2_S 3 -/** LEDC_PARA_UP_CH2 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2, - * LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2, - * LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel - * 2, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH2 (BIT(4)) -#define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) -#define LEDC_PARA_UP_CH2_V 0x00000001U -#define LEDC_PARA_UP_CH2_S 4 -/** LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH2_INT interrupt - * will be triggered when channel 2 overflows for (LEDC_OVF_NUM_CH2 + 1) times. - */ -#define LEDC_OVF_NUM_CH2 0x000003FFU -#define LEDC_OVF_NUM_CH2_M (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S) -#define LEDC_OVF_NUM_CH2_V 0x000003FFU -#define LEDC_OVF_NUM_CH2_S 5 -/** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 2. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH2 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) -#define LEDC_OVF_CNT_EN_CH2_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH2_S 15 -/** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 2. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) -#define LEDC_OVF_CNT_RESET_CH2_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH2_S 16 - -/** LEDC_CH2_HPOINT_REG register - * High point register for channel 2 - */ -#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c) -/** LEDC_HPOINT_CH2 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 2. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH2 0x000FFFFFU -#define LEDC_HPOINT_CH2_M (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S) -#define LEDC_HPOINT_CH2_V 0x000FFFFFU -#define LEDC_HPOINT_CH2_S 0 - -/** LEDC_CH2_DUTY_REG register - * Initial duty cycle register for channel 2 - */ -#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30) -/** LEDC_DUTY_CH2 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 2. - */ -#define LEDC_DUTY_CH2 0x01FFFFFFU -#define LEDC_DUTY_CH2_M (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S) -#define LEDC_DUTY_CH2_V 0x01FFFFFFU -#define LEDC_DUTY_CH2_S 0 - -/** LEDC_CH2_CONF1_REG register - * Configuration register 1 for channel 2 - */ -#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) -/** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH2 (BIT(31)) -#define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) -#define LEDC_DUTY_START_CH2_V 0x00000001U -#define LEDC_DUTY_START_CH2_S 31 - -/** LEDC_CH2_DUTY_R_REG register - * Current duty cycle register for channel 2 - */ -#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38) -/** LEDC_DUTY_CH2_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 2. - */ -#define LEDC_DUTY_CH2_R 0x01FFFFFFU -#define LEDC_DUTY_CH2_R_M (LEDC_DUTY_CH2_R_V << LEDC_DUTY_CH2_R_S) -#define LEDC_DUTY_CH2_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH2_R_S 0 - -/** LEDC_CH3_CONF0_REG register - * Configuration register 0 for channel 3 - */ -#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) -/** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 3 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH3 0x00000003U -#define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) -#define LEDC_TIMER_SEL_CH3_V 0x00000003U -#define LEDC_TIMER_SEL_CH3_S 0 -/** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 3. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH3 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) -#define LEDC_SIG_OUT_EN_CH3_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH3_S 2 -/** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 3 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH3 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH3 (BIT(3)) -#define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) -#define LEDC_IDLE_LV_CH3_V 0x00000001U -#define LEDC_IDLE_LV_CH3_S 3 -/** LEDC_PARA_UP_CH3 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3, - * LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3, - * LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel - * 3, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH3 (BIT(4)) -#define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) -#define LEDC_PARA_UP_CH3_V 0x00000001U -#define LEDC_PARA_UP_CH3_S 4 -/** LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH3_INT interrupt - * will be triggered when channel 3 overflows for (LEDC_OVF_NUM_CH3 + 1) times. - */ -#define LEDC_OVF_NUM_CH3 0x000003FFU -#define LEDC_OVF_NUM_CH3_M (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S) -#define LEDC_OVF_NUM_CH3_V 0x000003FFU -#define LEDC_OVF_NUM_CH3_S 5 -/** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 3. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH3 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) -#define LEDC_OVF_CNT_EN_CH3_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH3_S 15 -/** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 3. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) -#define LEDC_OVF_CNT_RESET_CH3_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH3_S 16 - -/** LEDC_CH3_HPOINT_REG register - * High point register for channel 3 - */ -#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40) -/** LEDC_HPOINT_CH3 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 3. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH3 0x000FFFFFU -#define LEDC_HPOINT_CH3_M (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S) -#define LEDC_HPOINT_CH3_V 0x000FFFFFU -#define LEDC_HPOINT_CH3_S 0 - -/** LEDC_CH3_DUTY_REG register - * Initial duty cycle register for channel 3 - */ -#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44) -/** LEDC_DUTY_CH3 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 3. - */ -#define LEDC_DUTY_CH3 0x01FFFFFFU -#define LEDC_DUTY_CH3_M (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S) -#define LEDC_DUTY_CH3_V 0x01FFFFFFU -#define LEDC_DUTY_CH3_S 0 - -/** LEDC_CH3_CONF1_REG register - * Configuration register 1 for channel 3 - */ -#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) -/** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH3 (BIT(31)) -#define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) -#define LEDC_DUTY_START_CH3_V 0x00000001U -#define LEDC_DUTY_START_CH3_S 31 - -/** LEDC_CH3_DUTY_R_REG register - * Current duty cycle register for channel 3 - */ -#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c) -/** LEDC_DUTY_CH3_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 3. - */ -#define LEDC_DUTY_CH3_R 0x01FFFFFFU -#define LEDC_DUTY_CH3_R_M (LEDC_DUTY_CH3_R_V << LEDC_DUTY_CH3_R_S) -#define LEDC_DUTY_CH3_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH3_R_S 0 - -/** LEDC_CH4_CONF0_REG register - * Configuration register 0 for channel 4 - */ -#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) -/** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 4 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH4 0x00000003U -#define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) -#define LEDC_TIMER_SEL_CH4_V 0x00000003U -#define LEDC_TIMER_SEL_CH4_S 0 -/** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 4. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH4 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) -#define LEDC_SIG_OUT_EN_CH4_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH4_S 2 -/** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 4 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH4 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH4 (BIT(3)) -#define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) -#define LEDC_IDLE_LV_CH4_V 0x00000001U -#define LEDC_IDLE_LV_CH4_S 3 -/** LEDC_PARA_UP_CH4 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4, - * LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4, - * LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel - * 4, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH4 (BIT(4)) -#define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) -#define LEDC_PARA_UP_CH4_V 0x00000001U -#define LEDC_PARA_UP_CH4_S 4 -/** LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH4_INT interrupt - * will be triggered when channel 4 overflows for (LEDC_OVF_NUM_CH4 + 1) times. - */ -#define LEDC_OVF_NUM_CH4 0x000003FFU -#define LEDC_OVF_NUM_CH4_M (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S) -#define LEDC_OVF_NUM_CH4_V 0x000003FFU -#define LEDC_OVF_NUM_CH4_S 5 -/** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 4. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH4 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) -#define LEDC_OVF_CNT_EN_CH4_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH4_S 15 -/** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 4. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) -#define LEDC_OVF_CNT_RESET_CH4_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH4_S 16 - -/** LEDC_CH4_HPOINT_REG register - * High point register for channel 4 - */ -#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54) -/** LEDC_HPOINT_CH4 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 4. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH4 0x000FFFFFU -#define LEDC_HPOINT_CH4_M (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S) -#define LEDC_HPOINT_CH4_V 0x000FFFFFU -#define LEDC_HPOINT_CH4_S 0 - -/** LEDC_CH4_DUTY_REG register - * Initial duty cycle register for channel 4 - */ -#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58) -/** LEDC_DUTY_CH4 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 4. - */ -#define LEDC_DUTY_CH4 0x01FFFFFFU -#define LEDC_DUTY_CH4_M (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S) -#define LEDC_DUTY_CH4_V 0x01FFFFFFU -#define LEDC_DUTY_CH4_S 0 - -/** LEDC_CH4_CONF1_REG register - * Configuration register 1 for channel 4 - */ -#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) -/** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH4 (BIT(31)) -#define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) -#define LEDC_DUTY_START_CH4_V 0x00000001U -#define LEDC_DUTY_START_CH4_S 31 - -/** LEDC_CH4_DUTY_R_REG register - * Current duty cycle register for channel 4 - */ -#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60) -/** LEDC_DUTY_CH4_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 4. - */ -#define LEDC_DUTY_CH4_R 0x01FFFFFFU -#define LEDC_DUTY_CH4_R_M (LEDC_DUTY_CH4_R_V << LEDC_DUTY_CH4_R_S) -#define LEDC_DUTY_CH4_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH4_R_S 0 - -/** LEDC_CH5_CONF0_REG register - * Configuration register 0 for channel 5 - */ -#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) -/** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 5 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH5 0x00000003U -#define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) -#define LEDC_TIMER_SEL_CH5_V 0x00000003U -#define LEDC_TIMER_SEL_CH5_S 0 -/** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 5. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH5 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) -#define LEDC_SIG_OUT_EN_CH5_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH5_S 2 -/** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 5 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH5 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH5 (BIT(3)) -#define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) -#define LEDC_IDLE_LV_CH5_V 0x00000001U -#define LEDC_IDLE_LV_CH5_S 3 -/** LEDC_PARA_UP_CH5 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5, - * LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5, - * LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel - * 5, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH5 (BIT(4)) -#define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) -#define LEDC_PARA_UP_CH5_V 0x00000001U -#define LEDC_PARA_UP_CH5_S 4 -/** LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH5_INT interrupt - * will be triggered when channel 5 overflows for (LEDC_OVF_NUM_CH5 + 1) times. - */ -#define LEDC_OVF_NUM_CH5 0x000003FFU -#define LEDC_OVF_NUM_CH5_M (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S) -#define LEDC_OVF_NUM_CH5_V 0x000003FFU -#define LEDC_OVF_NUM_CH5_S 5 -/** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 5. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH5 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) -#define LEDC_OVF_CNT_EN_CH5_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH5_S 15 -/** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 5. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) -#define LEDC_OVF_CNT_RESET_CH5_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH5_S 16 - -/** LEDC_CH5_HPOINT_REG register - * High point register for channel 5 - */ -#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68) -/** LEDC_HPOINT_CH5 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 5. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH5 0x000FFFFFU -#define LEDC_HPOINT_CH5_M (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S) -#define LEDC_HPOINT_CH5_V 0x000FFFFFU -#define LEDC_HPOINT_CH5_S 0 - -/** LEDC_CH5_DUTY_REG register - * Initial duty cycle register for channel 5 - */ -#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c) -/** LEDC_DUTY_CH5 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 5. - */ -#define LEDC_DUTY_CH5 0x01FFFFFFU -#define LEDC_DUTY_CH5_M (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S) -#define LEDC_DUTY_CH5_V 0x01FFFFFFU -#define LEDC_DUTY_CH5_S 0 - -/** LEDC_CH5_CONF1_REG register - * Configuration register 1 for channel 5 - */ -#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) -/** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH5 (BIT(31)) -#define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) -#define LEDC_DUTY_START_CH5_V 0x00000001U -#define LEDC_DUTY_START_CH5_S 31 - -/** LEDC_CH5_DUTY_R_REG register - * Current duty cycle register for channel 5 - */ -#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74) -/** LEDC_DUTY_CH5_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 5. - */ -#define LEDC_DUTY_CH5_R 0x01FFFFFFU -#define LEDC_DUTY_CH5_R_M (LEDC_DUTY_CH5_R_V << LEDC_DUTY_CH5_R_S) -#define LEDC_DUTY_CH5_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH5_R_S 0 - -/** LEDC_CH6_CONF0_REG register - * Configuration register 0 for channel 6 - */ -#define LEDC_CH6_CONF0_REG (DR_REG_LEDC_BASE + 0x78) -/** LEDC_TIMER_SEL_CH6 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 6 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH6 0x00000003U -#define LEDC_TIMER_SEL_CH6_M (LEDC_TIMER_SEL_CH6_V << LEDC_TIMER_SEL_CH6_S) -#define LEDC_TIMER_SEL_CH6_V 0x00000003U -#define LEDC_TIMER_SEL_CH6_S 0 -/** LEDC_SIG_OUT_EN_CH6 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 6. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH6 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH6_M (LEDC_SIG_OUT_EN_CH6_V << LEDC_SIG_OUT_EN_CH6_S) -#define LEDC_SIG_OUT_EN_CH6_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH6_S 2 -/** LEDC_IDLE_LV_CH6 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 6 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH6 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH6 (BIT(3)) -#define LEDC_IDLE_LV_CH6_M (LEDC_IDLE_LV_CH6_V << LEDC_IDLE_LV_CH6_S) -#define LEDC_IDLE_LV_CH6_V 0x00000001U -#define LEDC_IDLE_LV_CH6_S 3 -/** LEDC_PARA_UP_CH6 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH6, LEDC_DUTY_START_CH6, - * LEDC_SIG_OUT_EN_CH6, LEDC_TIMER_SEL_CH6, LEDC_DUTY_NUM_CH6, LEDC_DUTY_CYCLE_CH6, - * LEDC_DUTY_SCALE_CH6, LEDC_DUTY_INC_CH6, and LEDC_OVF_CNT_EN_CH6 fields for channel - * 6, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH6 (BIT(4)) -#define LEDC_PARA_UP_CH6_M (LEDC_PARA_UP_CH6_V << LEDC_PARA_UP_CH6_S) -#define LEDC_PARA_UP_CH6_V 0x00000001U -#define LEDC_PARA_UP_CH6_S 4 -/** LEDC_OVF_NUM_CH6 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH6_INT interrupt - * will be triggered when channel 6 overflows for (LEDC_OVF_NUM_CH6 + 1) times. - */ -#define LEDC_OVF_NUM_CH6 0x000003FFU -#define LEDC_OVF_NUM_CH6_M (LEDC_OVF_NUM_CH6_V << LEDC_OVF_NUM_CH6_S) -#define LEDC_OVF_NUM_CH6_V 0x000003FFU -#define LEDC_OVF_NUM_CH6_S 5 -/** LEDC_OVF_CNT_EN_CH6 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 6. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH6 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH6_M (LEDC_OVF_CNT_EN_CH6_V << LEDC_OVF_CNT_EN_CH6_S) -#define LEDC_OVF_CNT_EN_CH6_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH6_S 15 -/** LEDC_OVF_CNT_RESET_CH6 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 6. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH6 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH6_M (LEDC_OVF_CNT_RESET_CH6_V << LEDC_OVF_CNT_RESET_CH6_S) -#define LEDC_OVF_CNT_RESET_CH6_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH6_S 16 - -/** LEDC_CH6_HPOINT_REG register - * High point register for channel 6 - */ -#define LEDC_CH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x7c) -/** LEDC_HPOINT_CH6 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 6. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH6 0x000FFFFFU -#define LEDC_HPOINT_CH6_M (LEDC_HPOINT_CH6_V << LEDC_HPOINT_CH6_S) -#define LEDC_HPOINT_CH6_V 0x000FFFFFU -#define LEDC_HPOINT_CH6_S 0 - -/** LEDC_CH6_DUTY_REG register - * Initial duty cycle register for channel 6 - */ -#define LEDC_CH6_DUTY_REG (DR_REG_LEDC_BASE + 0x80) -/** LEDC_DUTY_CH6 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 6. - */ -#define LEDC_DUTY_CH6 0x01FFFFFFU -#define LEDC_DUTY_CH6_M (LEDC_DUTY_CH6_V << LEDC_DUTY_CH6_S) -#define LEDC_DUTY_CH6_V 0x01FFFFFFU -#define LEDC_DUTY_CH6_S 0 - -/** LEDC_CH6_CONF1_REG register - * Configuration register 1 for channel 6 - */ -#define LEDC_CH6_CONF1_REG (DR_REG_LEDC_BASE + 0x84) -/** LEDC_DUTY_START_CH6 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH6 (BIT(31)) -#define LEDC_DUTY_START_CH6_M (LEDC_DUTY_START_CH6_V << LEDC_DUTY_START_CH6_S) -#define LEDC_DUTY_START_CH6_V 0x00000001U -#define LEDC_DUTY_START_CH6_S 31 - -/** LEDC_CH6_DUTY_R_REG register - * Current duty cycle register for channel 6 - */ -#define LEDC_CH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x88) -/** LEDC_DUTY_CH6_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 6. - */ -#define LEDC_DUTY_CH6_R 0x01FFFFFFU -#define LEDC_DUTY_CH6_R_M (LEDC_DUTY_CH6_R_V << LEDC_DUTY_CH6_R_S) -#define LEDC_DUTY_CH6_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH6_R_S 0 - -/** LEDC_CH7_CONF0_REG register - * Configuration register 0 for channel 7 - */ -#define LEDC_CH7_CONF0_REG (DR_REG_LEDC_BASE + 0x8c) -/** LEDC_TIMER_SEL_CH7 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 7 selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ -#define LEDC_TIMER_SEL_CH7 0x00000003U -#define LEDC_TIMER_SEL_CH7_M (LEDC_TIMER_SEL_CH7_V << LEDC_TIMER_SEL_CH7_S) -#define LEDC_TIMER_SEL_CH7_V 0x00000003U -#define LEDC_TIMER_SEL_CH7_S 0 -/** LEDC_SIG_OUT_EN_CH7 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 7. - * 0: Signal output disable - * 1: Signal output enable - */ -#define LEDC_SIG_OUT_EN_CH7 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH7_M (LEDC_SIG_OUT_EN_CH7_V << LEDC_SIG_OUT_EN_CH7_S) -#define LEDC_SIG_OUT_EN_CH7_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH7_S 2 -/** LEDC_IDLE_LV_CH7 : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel 7 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH7 is 0. - * 0: Output level is low - * 1: Output level is high - */ -#define LEDC_IDLE_LV_CH7 (BIT(3)) -#define LEDC_IDLE_LV_CH7_M (LEDC_IDLE_LV_CH7_V << LEDC_IDLE_LV_CH7_S) -#define LEDC_IDLE_LV_CH7_V 0x00000001U -#define LEDC_IDLE_LV_CH7_S 3 -/** LEDC_PARA_UP_CH7 : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CH7, LEDC_DUTY_START_CH7, - * LEDC_SIG_OUT_EN_CH7, LEDC_TIMER_SEL_CH7, LEDC_DUTY_NUM_CH7, LEDC_DUTY_CYCLE_CH7, - * LEDC_DUTY_SCALE_CH7, LEDC_DUTY_INC_CH7, and LEDC_OVF_CNT_EN_CH7 fields for channel - * 7, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_PARA_UP_CH7 (BIT(4)) -#define LEDC_PARA_UP_CH7_M (LEDC_PARA_UP_CH7_V << LEDC_PARA_UP_CH7_S) -#define LEDC_PARA_UP_CH7_V 0x00000001U -#define LEDC_PARA_UP_CH7_S 4 -/** LEDC_OVF_NUM_CH7 : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH7_INT interrupt - * will be triggered when channel 7 overflows for (LEDC_OVF_NUM_CH7 + 1) times. - */ -#define LEDC_OVF_NUM_CH7 0x000003FFU -#define LEDC_OVF_NUM_CH7_M (LEDC_OVF_NUM_CH7_V << LEDC_OVF_NUM_CH7_S) -#define LEDC_OVF_NUM_CH7_V 0x000003FFU -#define LEDC_OVF_NUM_CH7_S 5 -/** LEDC_OVF_CNT_EN_CH7 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 7. - * 0: Disable - * 1: Enable - */ -#define LEDC_OVF_CNT_EN_CH7 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH7_M (LEDC_OVF_CNT_EN_CH7_V << LEDC_OVF_CNT_EN_CH7_S) -#define LEDC_OVF_CNT_EN_CH7_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH7_S 15 -/** LEDC_OVF_CNT_RESET_CH7 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 7. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ -#define LEDC_OVF_CNT_RESET_CH7 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH7_M (LEDC_OVF_CNT_RESET_CH7_V << LEDC_OVF_CNT_RESET_CH7_S) -#define LEDC_OVF_CNT_RESET_CH7_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH7_S 16 - -/** LEDC_CH7_HPOINT_REG register - * High point register for channel 7 - */ -#define LEDC_CH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x90) -/** LEDC_HPOINT_CH7 : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel 7. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ -#define LEDC_HPOINT_CH7 0x000FFFFFU -#define LEDC_HPOINT_CH7_M (LEDC_HPOINT_CH7_V << LEDC_HPOINT_CH7_S) -#define LEDC_HPOINT_CH7_V 0x000FFFFFU -#define LEDC_HPOINT_CH7_S 0 - -/** LEDC_CH7_DUTY_REG register - * Initial duty cycle register for channel 7 - */ -#define LEDC_CH7_DUTY_REG (DR_REG_LEDC_BASE + 0x94) -/** LEDC_DUTY_CH7 : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel 7. - */ -#define LEDC_DUTY_CH7 0x01FFFFFFU -#define LEDC_DUTY_CH7_M (LEDC_DUTY_CH7_V << LEDC_DUTY_CH7_S) -#define LEDC_DUTY_CH7_V 0x01FFFFFFU -#define LEDC_DUTY_CH7_S 0 - -/** LEDC_CH7_CONF1_REG register - * Configuration register 1 for channel 7 - */ -#define LEDC_CH7_CONF1_REG (DR_REG_LEDC_BASE + 0x98) -/** LEDC_DUTY_START_CH7 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ -#define LEDC_DUTY_START_CH7 (BIT(31)) -#define LEDC_DUTY_START_CH7_M (LEDC_DUTY_START_CH7_V << LEDC_DUTY_START_CH7_S) -#define LEDC_DUTY_START_CH7_V 0x00000001U -#define LEDC_DUTY_START_CH7_S 31 - -/** LEDC_CH7_DUTY_R_REG register - * Current duty cycle register for channel 7 - */ -#define LEDC_CH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x9c) -/** LEDC_DUTY_CH7_R : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel 7. - */ -#define LEDC_DUTY_CH7_R 0x01FFFFFFU -#define LEDC_DUTY_CH7_R_M (LEDC_DUTY_CH7_R_V << LEDC_DUTY_CH7_R_S) -#define LEDC_DUTY_CH7_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH7_R_S 0 - -/** LEDC_TIMER0_CONF_REG register - * Timer 0 configuration register - */ -#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0) -/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0; - * Configures the range of the counter in timer 0. - */ -#define LEDC_TIMER0_DUTY_RES 0x0000001FU -#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) -#define LEDC_TIMER0_DUTY_RES_V 0x0000001FU -#define LEDC_TIMER0_DUTY_RES_S 0 -/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer 0.The least significant eight bits - * represent the fractional part. - */ -#define LEDC_CLK_DIV_TIMER0 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) -#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER0_S 5 -/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 0. - * 0: Normal - * 1: Pause - */ -#define LEDC_TIMER0_PAUSE (BIT(23)) -#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) -#define LEDC_TIMER0_PAUSE_V 0x00000001U -#define LEDC_TIMER0_PAUSE_S 23 -/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 0. The counter will show 0 after reset. - * 0: Not reset - * 1: Reset - */ -#define LEDC_TIMER0_RST (BIT(24)) -#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) -#define LEDC_TIMER0_RST_V 0x00000001U -#define LEDC_TIMER0_RST_S 24 -/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER0 and LEDC_TIMER0_DUTY_RES. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_TIMER0_PARA_UP (BIT(26)) -#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) -#define LEDC_TIMER0_PARA_UP_V 0x00000001U -#define LEDC_TIMER0_PARA_UP_S 26 - -/** LEDC_TIMER0_VALUE_REG register - * Timer 0 current counter value register - */ -#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4) -/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer 0. - */ -#define LEDC_TIMER0_CNT 0x000FFFFFU -#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) -#define LEDC_TIMER0_CNT_V 0x000FFFFFU -#define LEDC_TIMER0_CNT_S 0 - -/** LEDC_TIMER1_CONF_REG register - * Timer 1 configuration register - */ -#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8) -/** LEDC_TIMER1_DUTY_RES : R/W; bitpos: [4:0]; default: 0; - * Configures the range of the counter in timer 1. - */ -#define LEDC_TIMER1_DUTY_RES 0x0000001FU -#define LEDC_TIMER1_DUTY_RES_M (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S) -#define LEDC_TIMER1_DUTY_RES_V 0x0000001FU -#define LEDC_TIMER1_DUTY_RES_S 0 -/** LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer 1.The least significant eight bits - * represent the fractional part. - */ -#define LEDC_CLK_DIV_TIMER1 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER1_M (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S) -#define LEDC_CLK_DIV_TIMER1_V 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER1_S 5 -/** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 1. - * 0: Normal - * 1: Pause - */ -#define LEDC_TIMER1_PAUSE (BIT(23)) -#define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) -#define LEDC_TIMER1_PAUSE_V 0x00000001U -#define LEDC_TIMER1_PAUSE_S 23 -/** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 1. The counter will show 0 after reset. - * 0: Not reset - * 1: Reset - */ -#define LEDC_TIMER1_RST (BIT(24)) -#define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) -#define LEDC_TIMER1_RST_V 0x00000001U -#define LEDC_TIMER1_RST_S 24 -/** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER1 and LEDC_TIMER1_DUTY_RES. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_TIMER1_PARA_UP (BIT(26)) -#define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) -#define LEDC_TIMER1_PARA_UP_V 0x00000001U -#define LEDC_TIMER1_PARA_UP_S 26 - -/** LEDC_TIMER1_VALUE_REG register - * Timer 1 current counter value register - */ -#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac) -/** LEDC_TIMER1_CNT : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer 1. - */ -#define LEDC_TIMER1_CNT 0x000FFFFFU -#define LEDC_TIMER1_CNT_M (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S) -#define LEDC_TIMER1_CNT_V 0x000FFFFFU -#define LEDC_TIMER1_CNT_S 0 - -/** LEDC_TIMER2_CONF_REG register - * Timer 2 configuration register - */ -#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0) -/** LEDC_TIMER2_DUTY_RES : R/W; bitpos: [4:0]; default: 0; - * Configures the range of the counter in timer 2. - */ -#define LEDC_TIMER2_DUTY_RES 0x0000001FU -#define LEDC_TIMER2_DUTY_RES_M (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S) -#define LEDC_TIMER2_DUTY_RES_V 0x0000001FU -#define LEDC_TIMER2_DUTY_RES_S 0 -/** LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer 2.The least significant eight bits - * represent the fractional part. - */ -#define LEDC_CLK_DIV_TIMER2 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER2_M (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S) -#define LEDC_CLK_DIV_TIMER2_V 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER2_S 5 -/** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 2. - * 0: Normal - * 1: Pause - */ -#define LEDC_TIMER2_PAUSE (BIT(23)) -#define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) -#define LEDC_TIMER2_PAUSE_V 0x00000001U -#define LEDC_TIMER2_PAUSE_S 23 -/** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 2. The counter will show 0 after reset. - * 0: Not reset - * 1: Reset - */ -#define LEDC_TIMER2_RST (BIT(24)) -#define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) -#define LEDC_TIMER2_RST_V 0x00000001U -#define LEDC_TIMER2_RST_S 24 -/** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER2 and LEDC_TIMER2_DUTY_RES. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_TIMER2_PARA_UP (BIT(26)) -#define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) -#define LEDC_TIMER2_PARA_UP_V 0x00000001U -#define LEDC_TIMER2_PARA_UP_S 26 - -/** LEDC_TIMER2_VALUE_REG register - * Timer 2 current counter value register - */ -#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4) -/** LEDC_TIMER2_CNT : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer 2. - */ -#define LEDC_TIMER2_CNT 0x000FFFFFU -#define LEDC_TIMER2_CNT_M (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S) -#define LEDC_TIMER2_CNT_V 0x000FFFFFU -#define LEDC_TIMER2_CNT_S 0 - -/** LEDC_TIMER3_CONF_REG register - * Timer 3 configuration register - */ -#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8) -/** LEDC_TIMER3_DUTY_RES : R/W; bitpos: [4:0]; default: 0; - * Configures the range of the counter in timer 3. - */ -#define LEDC_TIMER3_DUTY_RES 0x0000001FU -#define LEDC_TIMER3_DUTY_RES_M (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S) -#define LEDC_TIMER3_DUTY_RES_V 0x0000001FU -#define LEDC_TIMER3_DUTY_RES_S 0 -/** LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer 3.The least significant eight bits - * represent the fractional part. - */ -#define LEDC_CLK_DIV_TIMER3 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER3_M (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S) -#define LEDC_CLK_DIV_TIMER3_V 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER3_S 5 -/** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 3. - * 0: Normal - * 1: Pause - */ -#define LEDC_TIMER3_PAUSE (BIT(23)) -#define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) -#define LEDC_TIMER3_PAUSE_V 0x00000001U -#define LEDC_TIMER3_PAUSE_S 23 -/** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 3. The counter will show 0 after reset. - * 0: Not reset - * 1: Reset - */ -#define LEDC_TIMER3_RST (BIT(24)) -#define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) -#define LEDC_TIMER3_RST_V 0x00000001U -#define LEDC_TIMER3_RST_S 24 -/** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER3 and LEDC_TIMER3_DUTY_RES. - * 0: Invalid. No effect - * 1: Update - */ -#define LEDC_TIMER3_PARA_UP (BIT(26)) -#define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) -#define LEDC_TIMER3_PARA_UP_V 0x00000001U -#define LEDC_TIMER3_PARA_UP_S 26 - -/** LEDC_TIMER3_VALUE_REG register - * Timer 3 current counter value register - */ -#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc) -/** LEDC_TIMER3_CNT : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer 3. - */ -#define LEDC_TIMER3_CNT 0x000FFFFFU -#define LEDC_TIMER3_CNT_M (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S) -#define LEDC_TIMER3_CNT_V 0x000FFFFFU -#define LEDC_TIMER3_CNT_S 0 - -/** LEDC_INT_RAW_REG register - * Interrupt raw status register - */ -#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0) -/** LEDC_TIMER0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the - * timer0 has reached its maximum counter value. - */ -#define LEDC_TIMER0_OVF_INT_RAW (BIT(0)) -#define LEDC_TIMER0_OVF_INT_RAW_M (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S) -#define LEDC_TIMER0_OVF_INT_RAW_V 0x00000001U -#define LEDC_TIMER0_OVF_INT_RAW_S 0 -/** LEDC_TIMER1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the - * timer1 has reached its maximum counter value. - */ -#define LEDC_TIMER1_OVF_INT_RAW (BIT(1)) -#define LEDC_TIMER1_OVF_INT_RAW_M (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S) -#define LEDC_TIMER1_OVF_INT_RAW_V 0x00000001U -#define LEDC_TIMER1_OVF_INT_RAW_S 1 -/** LEDC_TIMER2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the - * timer2 has reached its maximum counter value. - */ -#define LEDC_TIMER2_OVF_INT_RAW (BIT(2)) -#define LEDC_TIMER2_OVF_INT_RAW_M (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S) -#define LEDC_TIMER2_OVF_INT_RAW_V 0x00000001U -#define LEDC_TIMER2_OVF_INT_RAW_S 2 -/** LEDC_TIMER3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the - * timer3 has reached its maximum counter value. - */ -#define LEDC_TIMER3_OVF_INT_RAW (BIT(3)) -#define LEDC_TIMER3_OVF_INT_RAW_M (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S) -#define LEDC_TIMER3_OVF_INT_RAW_V 0x00000001U -#define LEDC_TIMER3_OVF_INT_RAW_S 3 -/** LEDC_DUTY_CHNG_END_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S 4 -/** LEDC_DUTY_CHNG_END_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S 5 -/** LEDC_DUTY_CHNG_END_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S 6 -/** LEDC_DUTY_CHNG_END_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S 7 -/** LEDC_DUTY_CHNG_END_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S 8 -/** LEDC_DUTY_CHNG_END_CH5_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S 9 -/** LEDC_DUTY_CHNG_END_CH6_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_M (LEDC_DUTY_CHNG_END_CH6_INT_RAW_V << LEDC_DUTY_CHNG_END_CH6_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_S 10 -/** LEDC_DUTY_CHNG_END_CH7_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered - * when the fading of duty has finished. - */ -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_M (LEDC_DUTY_CHNG_END_CH7_INT_RAW_V << LEDC_DUTY_CHNG_END_CH7_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_S 11 -/** LEDC_OVF_CNT_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. - */ -#define LEDC_OVF_CNT_CH0_INT_RAW (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_RAW_M (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S) -#define LEDC_OVF_CNT_CH0_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH0_INT_RAW_S 12 -/** LEDC_OVF_CNT_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. - */ -#define LEDC_OVF_CNT_CH1_INT_RAW (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_RAW_M (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S) -#define LEDC_OVF_CNT_CH1_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH1_INT_RAW_S 13 -/** LEDC_OVF_CNT_CH2_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. - */ -#define LEDC_OVF_CNT_CH2_INT_RAW (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_RAW_M (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S) -#define LEDC_OVF_CNT_CH2_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH2_INT_RAW_S 14 -/** LEDC_OVF_CNT_CH3_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. - */ -#define LEDC_OVF_CNT_CH3_INT_RAW (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_RAW_M (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S) -#define LEDC_OVF_CNT_CH3_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH3_INT_RAW_S 15 -/** LEDC_OVF_CNT_CH4_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. - */ -#define LEDC_OVF_CNT_CH4_INT_RAW (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_RAW_M (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S) -#define LEDC_OVF_CNT_CH4_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH4_INT_RAW_S 16 -/** LEDC_OVF_CNT_CH5_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. - */ -#define LEDC_OVF_CNT_CH5_INT_RAW (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_RAW_M (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S) -#define LEDC_OVF_CNT_CH5_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH5_INT_RAW_S 17 -/** LEDC_OVF_CNT_CH6_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. - */ -#define LEDC_OVF_CNT_CH6_INT_RAW (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_RAW_M (LEDC_OVF_CNT_CH6_INT_RAW_V << LEDC_OVF_CNT_CH6_INT_RAW_S) -#define LEDC_OVF_CNT_CH6_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH6_INT_RAW_S 18 -/** LEDC_OVF_CNT_CH7_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. - */ -#define LEDC_OVF_CNT_CH7_INT_RAW (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_RAW_M (LEDC_OVF_CNT_CH7_INT_RAW_V << LEDC_OVF_CNT_CH7_INT_RAW_S) -#define LEDC_OVF_CNT_CH7_INT_RAW_V 0x00000001U -#define LEDC_OVF_CNT_CH7_INT_RAW_S 19 - -/** LEDC_INT_ST_REG register - * Interrupt masked status register - */ -#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4) -/** LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only - * when LEDC_TIMER0_OVF_INT_ENA is set to 1. - */ -#define LEDC_TIMER0_OVF_INT_ST (BIT(0)) -#define LEDC_TIMER0_OVF_INT_ST_M (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S) -#define LEDC_TIMER0_OVF_INT_ST_V 0x00000001U -#define LEDC_TIMER0_OVF_INT_ST_S 0 -/** LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only - * when LEDC_TIMER1_OVF_INT_ENA is set to 1. - */ -#define LEDC_TIMER1_OVF_INT_ST (BIT(1)) -#define LEDC_TIMER1_OVF_INT_ST_M (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S) -#define LEDC_TIMER1_OVF_INT_ST_V 0x00000001U -#define LEDC_TIMER1_OVF_INT_ST_S 1 -/** LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only - * when LEDC_TIMER2_OVF_INT_ENA is set to 1. - */ -#define LEDC_TIMER2_OVF_INT_ST (BIT(2)) -#define LEDC_TIMER2_OVF_INT_ST_M (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S) -#define LEDC_TIMER2_OVF_INT_ST_V 0x00000001U -#define LEDC_TIMER2_OVF_INT_ST_S 2 -/** LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only - * when LEDC_TIMER3_OVF_INT_ENA is set to 1. - */ -#define LEDC_TIMER3_OVF_INT_ST (BIT(3)) -#define LEDC_TIMER3_OVF_INT_ST_M (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S) -#define LEDC_TIMER3_OVF_INT_ST_V 0x00000001U -#define LEDC_TIMER3_OVF_INT_ST_S 3 -/** LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH0_INT_ST (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S 4 -/** LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH1_INT_ST (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S 5 -/** LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH2_INT_ST (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S 6 -/** LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH3_INT_ST (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S 7 -/** LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH4_INT_ST (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S 8 -/** LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH5_INT_ST (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S 9 -/** LEDC_DUTY_CHNG_END_CH6_INT_ST : RO; bitpos: [10]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH6_INT_ST (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_ST_M (LEDC_DUTY_CHNG_END_CH6_INT_ST_V << LEDC_DUTY_CHNG_END_CH6_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH6_INT_ST_S 10 -/** LEDC_DUTY_CHNG_END_CH7_INT_ST : RO; bitpos: [11]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. - */ -#define LEDC_DUTY_CHNG_END_CH7_INT_ST (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_ST_M (LEDC_DUTY_CHNG_END_CH7_INT_ST_V << LEDC_DUTY_CHNG_END_CH7_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_ST_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH7_INT_ST_S 11 -/** LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only - * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH0_INT_ST (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_ST_M (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S) -#define LEDC_OVF_CNT_CH0_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH0_INT_ST_S 12 -/** LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only - * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH1_INT_ST (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_ST_M (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S) -#define LEDC_OVF_CNT_CH1_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH1_INT_ST_S 13 -/** LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only - * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH2_INT_ST (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_ST_M (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S) -#define LEDC_OVF_CNT_CH2_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH2_INT_ST_S 14 -/** LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only - * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH3_INT_ST (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_ST_M (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S) -#define LEDC_OVF_CNT_CH3_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH3_INT_ST_S 15 -/** LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only - * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH4_INT_ST (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_ST_M (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S) -#define LEDC_OVF_CNT_CH4_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH4_INT_ST_S 16 -/** LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only - * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH5_INT_ST (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_ST_M (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S) -#define LEDC_OVF_CNT_CH5_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH5_INT_ST_S 17 -/** LEDC_OVF_CNT_CH6_INT_ST : RO; bitpos: [18]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only - * when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH6_INT_ST (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_ST_M (LEDC_OVF_CNT_CH6_INT_ST_V << LEDC_OVF_CNT_CH6_INT_ST_S) -#define LEDC_OVF_CNT_CH6_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH6_INT_ST_S 18 -/** LEDC_OVF_CNT_CH7_INT_ST : RO; bitpos: [19]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only - * when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. - */ -#define LEDC_OVF_CNT_CH7_INT_ST (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_ST_M (LEDC_OVF_CNT_CH7_INT_ST_V << LEDC_OVF_CNT_CH7_INT_ST_S) -#define LEDC_OVF_CNT_CH7_INT_ST_V 0x00000001U -#define LEDC_OVF_CNT_CH7_INT_ST_S 19 - -/** LEDC_INT_ENA_REG register - * Interrupt enable register - */ -#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8) -/** LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. - */ -#define LEDC_TIMER0_OVF_INT_ENA (BIT(0)) -#define LEDC_TIMER0_OVF_INT_ENA_M (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S) -#define LEDC_TIMER0_OVF_INT_ENA_V 0x00000001U -#define LEDC_TIMER0_OVF_INT_ENA_S 0 -/** LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. - */ -#define LEDC_TIMER1_OVF_INT_ENA (BIT(1)) -#define LEDC_TIMER1_OVF_INT_ENA_M (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S) -#define LEDC_TIMER1_OVF_INT_ENA_V 0x00000001U -#define LEDC_TIMER1_OVF_INT_ENA_S 1 -/** LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. - */ -#define LEDC_TIMER2_OVF_INT_ENA (BIT(2)) -#define LEDC_TIMER2_OVF_INT_ENA_M (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S) -#define LEDC_TIMER2_OVF_INT_ENA_V 0x00000001U -#define LEDC_TIMER2_OVF_INT_ENA_S 2 -/** LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. - */ -#define LEDC_TIMER3_OVF_INT_ENA (BIT(3)) -#define LEDC_TIMER3_OVF_INT_ENA_M (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S) -#define LEDC_TIMER3_OVF_INT_ENA_V 0x00000001U -#define LEDC_TIMER3_OVF_INT_ENA_S 3 -/** LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. - */ -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S 4 -/** LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. - */ -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S 5 -/** LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. - */ -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S 6 -/** LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. - */ -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S 7 -/** LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. - */ -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S 8 -/** LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. - */ -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S 9 -/** LEDC_DUTY_CHNG_END_CH6_INT_ENA : R/W; bitpos: [10]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. - */ -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_M (LEDC_DUTY_CHNG_END_CH6_INT_ENA_V << LEDC_DUTY_CHNG_END_CH6_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_S 10 -/** LEDC_DUTY_CHNG_END_CH7_INT_ENA : R/W; bitpos: [11]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. - */ -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_M (LEDC_DUTY_CHNG_END_CH7_INT_ENA_V << LEDC_DUTY_CHNG_END_CH7_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_S 11 -/** LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. - */ -#define LEDC_OVF_CNT_CH0_INT_ENA (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_ENA_M (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S) -#define LEDC_OVF_CNT_CH0_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH0_INT_ENA_S 12 -/** LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. - */ -#define LEDC_OVF_CNT_CH1_INT_ENA (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_ENA_M (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S) -#define LEDC_OVF_CNT_CH1_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH1_INT_ENA_S 13 -/** LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. - */ -#define LEDC_OVF_CNT_CH2_INT_ENA (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_ENA_M (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S) -#define LEDC_OVF_CNT_CH2_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH2_INT_ENA_S 14 -/** LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. - */ -#define LEDC_OVF_CNT_CH3_INT_ENA (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_ENA_M (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S) -#define LEDC_OVF_CNT_CH3_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH3_INT_ENA_S 15 -/** LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. - */ -#define LEDC_OVF_CNT_CH4_INT_ENA (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_ENA_M (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S) -#define LEDC_OVF_CNT_CH4_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH4_INT_ENA_S 16 -/** LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. - */ -#define LEDC_OVF_CNT_CH5_INT_ENA (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_ENA_M (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S) -#define LEDC_OVF_CNT_CH5_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH5_INT_ENA_S 17 -/** LEDC_OVF_CNT_CH6_INT_ENA : R/W; bitpos: [18]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. - */ -#define LEDC_OVF_CNT_CH6_INT_ENA (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_ENA_M (LEDC_OVF_CNT_CH6_INT_ENA_V << LEDC_OVF_CNT_CH6_INT_ENA_S) -#define LEDC_OVF_CNT_CH6_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH6_INT_ENA_S 18 -/** LEDC_OVF_CNT_CH7_INT_ENA : R/W; bitpos: [19]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. - */ -#define LEDC_OVF_CNT_CH7_INT_ENA (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_ENA_M (LEDC_OVF_CNT_CH7_INT_ENA_V << LEDC_OVF_CNT_CH7_INT_ENA_S) -#define LEDC_OVF_CNT_CH7_INT_ENA_V 0x00000001U -#define LEDC_OVF_CNT_CH7_INT_ENA_S 19 - -/** LEDC_INT_CLR_REG register - * Interrupt clear register - */ -#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc) -/** LEDC_TIMER0_OVF_INT_CLR : WT; bitpos: [0]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. - */ -#define LEDC_TIMER0_OVF_INT_CLR (BIT(0)) -#define LEDC_TIMER0_OVF_INT_CLR_M (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S) -#define LEDC_TIMER0_OVF_INT_CLR_V 0x00000001U -#define LEDC_TIMER0_OVF_INT_CLR_S 0 -/** LEDC_TIMER1_OVF_INT_CLR : WT; bitpos: [1]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. - */ -#define LEDC_TIMER1_OVF_INT_CLR (BIT(1)) -#define LEDC_TIMER1_OVF_INT_CLR_M (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S) -#define LEDC_TIMER1_OVF_INT_CLR_V 0x00000001U -#define LEDC_TIMER1_OVF_INT_CLR_S 1 -/** LEDC_TIMER2_OVF_INT_CLR : WT; bitpos: [2]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. - */ -#define LEDC_TIMER2_OVF_INT_CLR (BIT(2)) -#define LEDC_TIMER2_OVF_INT_CLR_M (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S) -#define LEDC_TIMER2_OVF_INT_CLR_V 0x00000001U -#define LEDC_TIMER2_OVF_INT_CLR_S 2 -/** LEDC_TIMER3_OVF_INT_CLR : WT; bitpos: [3]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. - */ -#define LEDC_TIMER3_OVF_INT_CLR (BIT(3)) -#define LEDC_TIMER3_OVF_INT_CLR_M (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S) -#define LEDC_TIMER3_OVF_INT_CLR_V 0x00000001U -#define LEDC_TIMER3_OVF_INT_CLR_S 3 -/** LEDC_DUTY_CHNG_END_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. - */ -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S 4 -/** LEDC_DUTY_CHNG_END_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. - */ -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S 5 -/** LEDC_DUTY_CHNG_END_CH2_INT_CLR : WT; bitpos: [6]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. - */ -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S 6 -/** LEDC_DUTY_CHNG_END_CH3_INT_CLR : WT; bitpos: [7]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. - */ -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S 7 -/** LEDC_DUTY_CHNG_END_CH4_INT_CLR : WT; bitpos: [8]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. - */ -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S 8 -/** LEDC_DUTY_CHNG_END_CH5_INT_CLR : WT; bitpos: [9]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. - */ -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S 9 -/** LEDC_DUTY_CHNG_END_CH6_INT_CLR : WT; bitpos: [10]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. - */ -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_M (LEDC_DUTY_CHNG_END_CH6_INT_CLR_V << LEDC_DUTY_CHNG_END_CH6_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_S 10 -/** LEDC_DUTY_CHNG_END_CH7_INT_CLR : WT; bitpos: [11]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. - */ -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_M (LEDC_DUTY_CHNG_END_CH7_INT_CLR_V << LEDC_DUTY_CHNG_END_CH7_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_V 0x00000001U -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_S 11 -/** LEDC_OVF_CNT_CH0_INT_CLR : WT; bitpos: [12]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. - */ -#define LEDC_OVF_CNT_CH0_INT_CLR (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_CLR_M (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S) -#define LEDC_OVF_CNT_CH0_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH0_INT_CLR_S 12 -/** LEDC_OVF_CNT_CH1_INT_CLR : WT; bitpos: [13]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. - */ -#define LEDC_OVF_CNT_CH1_INT_CLR (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_CLR_M (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S) -#define LEDC_OVF_CNT_CH1_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH1_INT_CLR_S 13 -/** LEDC_OVF_CNT_CH2_INT_CLR : WT; bitpos: [14]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. - */ -#define LEDC_OVF_CNT_CH2_INT_CLR (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_CLR_M (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S) -#define LEDC_OVF_CNT_CH2_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH2_INT_CLR_S 14 -/** LEDC_OVF_CNT_CH3_INT_CLR : WT; bitpos: [15]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. - */ -#define LEDC_OVF_CNT_CH3_INT_CLR (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_CLR_M (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S) -#define LEDC_OVF_CNT_CH3_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH3_INT_CLR_S 15 -/** LEDC_OVF_CNT_CH4_INT_CLR : WT; bitpos: [16]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. - */ -#define LEDC_OVF_CNT_CH4_INT_CLR (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_CLR_M (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S) -#define LEDC_OVF_CNT_CH4_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH4_INT_CLR_S 16 -/** LEDC_OVF_CNT_CH5_INT_CLR : WT; bitpos: [17]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. - */ -#define LEDC_OVF_CNT_CH5_INT_CLR (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_CLR_M (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S) -#define LEDC_OVF_CNT_CH5_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH5_INT_CLR_S 17 -/** LEDC_OVF_CNT_CH6_INT_CLR : WT; bitpos: [18]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. - */ -#define LEDC_OVF_CNT_CH6_INT_CLR (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_CLR_M (LEDC_OVF_CNT_CH6_INT_CLR_V << LEDC_OVF_CNT_CH6_INT_CLR_S) -#define LEDC_OVF_CNT_CH6_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH6_INT_CLR_S 18 -/** LEDC_OVF_CNT_CH7_INT_CLR : WT; bitpos: [19]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. - */ -#define LEDC_OVF_CNT_CH7_INT_CLR (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_CLR_M (LEDC_OVF_CNT_CH7_INT_CLR_V << LEDC_OVF_CNT_CH7_INT_CLR_S) -#define LEDC_OVF_CNT_CH7_INT_CLR_V 0x00000001U -#define LEDC_OVF_CNT_CH7_INT_CLR_S 19 - -/** LEDC_CH0_GAMMA_CONF_REG register - * Ledc ch0 gamma config register. - */ -#define LEDC_CH0_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x100) -/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch0. - */ -#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) -#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch0. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) -#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH0_GAMMA_PAUSE_S 5 -/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch0. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH0_GAMMA_RESUME (BIT(6)) -#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) -#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH0_GAMMA_RESUME_S 6 - -/** LEDC_CH1_GAMMA_CONF_REG register - * Ledc ch1 gamma config register. - */ -#define LEDC_CH1_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x104) -/** LEDC_CH1_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch1. - */ -#define LEDC_CH1_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH1_GAMMA_ENTRY_NUM_M (LEDC_CH1_GAMMA_ENTRY_NUM_V << LEDC_CH1_GAMMA_ENTRY_NUM_S) -#define LEDC_CH1_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH1_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch1. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH1_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH1_GAMMA_PAUSE_M (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S) -#define LEDC_CH1_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH1_GAMMA_PAUSE_S 5 -/** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch1. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH1_GAMMA_RESUME (BIT(6)) -#define LEDC_CH1_GAMMA_RESUME_M (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S) -#define LEDC_CH1_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH1_GAMMA_RESUME_S 6 - -/** LEDC_CH2_GAMMA_CONF_REG register - * Ledc ch2 gamma config register. - */ -#define LEDC_CH2_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x108) -/** LEDC_CH2_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch2. - */ -#define LEDC_CH2_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH2_GAMMA_ENTRY_NUM_M (LEDC_CH2_GAMMA_ENTRY_NUM_V << LEDC_CH2_GAMMA_ENTRY_NUM_S) -#define LEDC_CH2_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH2_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch2. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH2_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH2_GAMMA_PAUSE_M (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S) -#define LEDC_CH2_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH2_GAMMA_PAUSE_S 5 -/** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch2. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH2_GAMMA_RESUME (BIT(6)) -#define LEDC_CH2_GAMMA_RESUME_M (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S) -#define LEDC_CH2_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH2_GAMMA_RESUME_S 6 - -/** LEDC_CH3_GAMMA_CONF_REG register - * Ledc ch3 gamma config register. - */ -#define LEDC_CH3_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x10c) -/** LEDC_CH3_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch3. - */ -#define LEDC_CH3_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH3_GAMMA_ENTRY_NUM_M (LEDC_CH3_GAMMA_ENTRY_NUM_V << LEDC_CH3_GAMMA_ENTRY_NUM_S) -#define LEDC_CH3_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH3_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch3. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH3_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH3_GAMMA_PAUSE_M (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S) -#define LEDC_CH3_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH3_GAMMA_PAUSE_S 5 -/** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch3. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH3_GAMMA_RESUME (BIT(6)) -#define LEDC_CH3_GAMMA_RESUME_M (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S) -#define LEDC_CH3_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH3_GAMMA_RESUME_S 6 - -/** LEDC_CH4_GAMMA_CONF_REG register - * Ledc ch4 gamma config register. - */ -#define LEDC_CH4_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x110) -/** LEDC_CH4_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch4. - */ -#define LEDC_CH4_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH4_GAMMA_ENTRY_NUM_M (LEDC_CH4_GAMMA_ENTRY_NUM_V << LEDC_CH4_GAMMA_ENTRY_NUM_S) -#define LEDC_CH4_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH4_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch4. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH4_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH4_GAMMA_PAUSE_M (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S) -#define LEDC_CH4_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH4_GAMMA_PAUSE_S 5 -/** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch4. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH4_GAMMA_RESUME (BIT(6)) -#define LEDC_CH4_GAMMA_RESUME_M (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S) -#define LEDC_CH4_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH4_GAMMA_RESUME_S 6 - -/** LEDC_CH5_GAMMA_CONF_REG register - * Ledc ch5 gamma config register. - */ -#define LEDC_CH5_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x114) -/** LEDC_CH5_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch5. - */ -#define LEDC_CH5_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH5_GAMMA_ENTRY_NUM_M (LEDC_CH5_GAMMA_ENTRY_NUM_V << LEDC_CH5_GAMMA_ENTRY_NUM_S) -#define LEDC_CH5_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH5_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch5. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH5_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH5_GAMMA_PAUSE_M (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S) -#define LEDC_CH5_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH5_GAMMA_PAUSE_S 5 -/** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch5. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH5_GAMMA_RESUME (BIT(6)) -#define LEDC_CH5_GAMMA_RESUME_M (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S) -#define LEDC_CH5_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH5_GAMMA_RESUME_S 6 - -/** LEDC_CH6_GAMMA_CONF_REG register - * Ledc ch6 gamma config register. - */ -#define LEDC_CH6_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x118) -/** LEDC_CH6_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch6. - */ -#define LEDC_CH6_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH6_GAMMA_ENTRY_NUM_M (LEDC_CH6_GAMMA_ENTRY_NUM_V << LEDC_CH6_GAMMA_ENTRY_NUM_S) -#define LEDC_CH6_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH6_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH6_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch6. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH6_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH6_GAMMA_PAUSE_M (LEDC_CH6_GAMMA_PAUSE_V << LEDC_CH6_GAMMA_PAUSE_S) -#define LEDC_CH6_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH6_GAMMA_PAUSE_S 5 -/** LEDC_CH6_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch6. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH6_GAMMA_RESUME (BIT(6)) -#define LEDC_CH6_GAMMA_RESUME_M (LEDC_CH6_GAMMA_RESUME_V << LEDC_CH6_GAMMA_RESUME_S) -#define LEDC_CH6_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH6_GAMMA_RESUME_S 6 - -/** LEDC_CH7_GAMMA_CONF_REG register - * Ledc ch7 gamma config register. - */ -#define LEDC_CH7_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x11c) -/** LEDC_CH7_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC ch7. - */ -#define LEDC_CH7_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH7_GAMMA_ENTRY_NUM_M (LEDC_CH7_GAMMA_ENTRY_NUM_V << LEDC_CH7_GAMMA_ENTRY_NUM_S) -#define LEDC_CH7_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH7_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH7_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch7. - * 0: Invalid. No effect - * 1: Pause - */ -#define LEDC_CH7_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH7_GAMMA_PAUSE_M (LEDC_CH7_GAMMA_PAUSE_V << LEDC_CH7_GAMMA_PAUSE_S) -#define LEDC_CH7_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH7_GAMMA_PAUSE_S 5 -/** LEDC_CH7_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch7. - * 0: Invalid. No effect - * 1: Resume - */ -#define LEDC_CH7_GAMMA_RESUME (BIT(6)) -#define LEDC_CH7_GAMMA_RESUME_M (LEDC_CH7_GAMMA_RESUME_V << LEDC_CH7_GAMMA_RESUME_S) -#define LEDC_CH7_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH7_GAMMA_RESUME_S 6 - -/** LEDC_EVT_TASK_EN0_REG register - * Ledc event task enable bit register0. - */ -#define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x120) -/** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH0_EN (BIT(0)) -#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S 0 -/** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH1_EN (BIT(1)) -#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S 1 -/** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH2_EN (BIT(2)) -#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S 2 -/** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH3_EN (BIT(3)) -#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S 3 -/** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH4_EN (BIT(4)) -#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S 4 -/** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH5_EN (BIT(5)) -#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S 5 -/** LEDC_EVT_DUTY_CHNG_END_CH6_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH6_EN (BIT(6)) -#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_M (LEDC_EVT_DUTY_CHNG_END_CH6_EN_V << LEDC_EVT_DUTY_CHNG_END_CH6_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_S 6 -/** LEDC_EVT_DUTY_CHNG_END_CH7_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_chng_end event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_DUTY_CHNG_END_CH7_EN (BIT(7)) -#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_M (LEDC_EVT_DUTY_CHNG_END_CH7_EN_V << LEDC_EVT_DUTY_CHNG_END_CH7_EN_S) -#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_V 0x00000001U -#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_S 7 -/** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH0_EN (BIT(8)) -#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S 8 -/** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH1_EN (BIT(9)) -#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S 9 -/** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH2_EN (BIT(10)) -#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S 10 -/** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH3_EN (BIT(11)) -#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S 11 -/** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH4_EN (BIT(12)) -#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S 12 -/** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH5_EN (BIT(13)) -#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S 13 -/** LEDC_EVT_OVF_CNT_PLS_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH6_EN (BIT(14)) -#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_M (LEDC_EVT_OVF_CNT_PLS_CH6_EN_V << LEDC_EVT_OVF_CNT_PLS_CH6_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_S 14 -/** LEDC_EVT_OVF_CNT_PLS_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_OVF_CNT_PLS_CH7_EN (BIT(15)) -#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_M (LEDC_EVT_OVF_CNT_PLS_CH7_EN_V << LEDC_EVT_OVF_CNT_PLS_CH7_EN_S) -#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_V 0x00000001U -#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_S 15 -/** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the ledc_timer0_ovf event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME_OVF_TIMER0_EN (BIT(16)) -#define LEDC_EVT_TIME_OVF_TIMER0_EN_M (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S) -#define LEDC_EVT_TIME_OVF_TIMER0_EN_V 0x00000001U -#define LEDC_EVT_TIME_OVF_TIMER0_EN_S 16 -/** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable the ledc_timer1_ovf event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME_OVF_TIMER1_EN (BIT(17)) -#define LEDC_EVT_TIME_OVF_TIMER1_EN_M (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S) -#define LEDC_EVT_TIME_OVF_TIMER1_EN_V 0x00000001U -#define LEDC_EVT_TIME_OVF_TIMER1_EN_S 17 -/** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable the ledc_timer2_ovf event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME_OVF_TIMER2_EN (BIT(18)) -#define LEDC_EVT_TIME_OVF_TIMER2_EN_M (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S) -#define LEDC_EVT_TIME_OVF_TIMER2_EN_V 0x00000001U -#define LEDC_EVT_TIME_OVF_TIMER2_EN_S 18 -/** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable the ledc_timer3_ovf event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME_OVF_TIMER3_EN (BIT(19)) -#define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S) -#define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U -#define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19 -/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable the ledc_timer0_cmp event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME0_CMP_EN (BIT(20)) -#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S) -#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIME0_CMP_EN_S 20 -/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable the ledc_timer1_cmp event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME1_CMP_EN (BIT(21)) -#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S) -#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIME1_CMP_EN_S 21 -/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable the ledc_timer2_cmp event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME2_CMP_EN (BIT(22)) -#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S) -#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIME2_CMP_EN_S 22 -/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable the ledc_timer3_cmp event. - * 0: Disable - * 1: Enable - */ -#define LEDC_EVT_TIME3_CMP_EN (BIT(23)) -#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S) -#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIME3_CMP_EN_S 23 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN (BIT(24)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S 24 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN (BIT(25)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S 25 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN (BIT(26)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S 26 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN (BIT(27)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S 27 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN (BIT(28)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S 28 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN (BIT(29)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S 29 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN (BIT(30)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S 30 -/** LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_scale_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN (BIT(31)) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S) -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V 0x00000001U -#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S 31 - -/** LEDC_EVT_TASK_EN1_REG register - * Ledc event task enable bit register1. - */ -#define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x124) -/** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_timer0_res_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER0_RES_UPDATE_EN (BIT(0)) -#define LEDC_TASK_TIMER0_RES_UPDATE_EN_M (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S) -#define LEDC_TASK_TIMER0_RES_UPDATE_EN_V 0x00000001U -#define LEDC_TASK_TIMER0_RES_UPDATE_EN_S 0 -/** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_timer1_res_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER1_RES_UPDATE_EN (BIT(1)) -#define LEDC_TASK_TIMER1_RES_UPDATE_EN_M (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S) -#define LEDC_TASK_TIMER1_RES_UPDATE_EN_V 0x00000001U -#define LEDC_TASK_TIMER1_RES_UPDATE_EN_S 1 -/** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_timer2_res_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER2_RES_UPDATE_EN (BIT(2)) -#define LEDC_TASK_TIMER2_RES_UPDATE_EN_M (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S) -#define LEDC_TASK_TIMER2_RES_UPDATE_EN_V 0x00000001U -#define LEDC_TASK_TIMER2_RES_UPDATE_EN_S 2 -/** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_timer3_res_update task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER3_RES_UPDATE_EN (BIT(3)) -#define LEDC_TASK_TIMER3_RES_UPDATE_EN_M (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S) -#define LEDC_TASK_TIMER3_RES_UPDATE_EN_V 0x00000001U -#define LEDC_TASK_TIMER3_RES_UPDATE_EN_S 3 -/** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_timer0_cap task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER0_CAP_EN (BIT(4)) -#define LEDC_TASK_TIMER0_CAP_EN_M (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S) -#define LEDC_TASK_TIMER0_CAP_EN_V 0x00000001U -#define LEDC_TASK_TIMER0_CAP_EN_S 4 -/** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_timer1_cap task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER1_CAP_EN (BIT(5)) -#define LEDC_TASK_TIMER1_CAP_EN_M (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S) -#define LEDC_TASK_TIMER1_CAP_EN_V 0x00000001U -#define LEDC_TASK_TIMER1_CAP_EN_S 5 -/** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_timer2_cap task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER2_CAP_EN (BIT(6)) -#define LEDC_TASK_TIMER2_CAP_EN_M (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S) -#define LEDC_TASK_TIMER2_CAP_EN_V 0x00000001U -#define LEDC_TASK_TIMER2_CAP_EN_S 6 -/** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_timer3_cap task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER3_CAP_EN (BIT(7)) -#define LEDC_TASK_TIMER3_CAP_EN_M (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S) -#define LEDC_TASK_TIMER3_CAP_EN_V 0x00000001U -#define LEDC_TASK_TIMER3_CAP_EN_S 7 -/** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH0_EN (BIT(8)) -#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S 8 -/** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH1_EN (BIT(9)) -#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S 9 -/** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH2_EN (BIT(10)) -#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S 10 -/** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH3_EN (BIT(11)) -#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S 11 -/** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH4_EN (BIT(12)) -#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S 12 -/** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH5_EN (BIT(13)) -#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S 13 -/** LEDC_TASK_SIG_OUT_DIS_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH6_EN (BIT(14)) -#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_M (LEDC_TASK_SIG_OUT_DIS_CH6_EN_V << LEDC_TASK_SIG_OUT_DIS_CH6_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_S 14 -/** LEDC_TASK_SIG_OUT_DIS_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_sig_out_dis task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_SIG_OUT_DIS_CH7_EN (BIT(15)) -#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_M (LEDC_TASK_SIG_OUT_DIS_CH7_EN_V << LEDC_TASK_SIG_OUT_DIS_CH7_EN_S) -#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_V 0x00000001U -#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_S 15 -/** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH0_EN (BIT(16)) -#define LEDC_TASK_OVF_CNT_RST_CH0_EN_M (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH0_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH0_EN_S 16 -/** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH1_EN (BIT(17)) -#define LEDC_TASK_OVF_CNT_RST_CH1_EN_M (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH1_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH1_EN_S 17 -/** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH2_EN (BIT(18)) -#define LEDC_TASK_OVF_CNT_RST_CH2_EN_M (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH2_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH2_EN_S 18 -/** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH3_EN (BIT(19)) -#define LEDC_TASK_OVF_CNT_RST_CH3_EN_M (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH3_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH3_EN_S 19 -/** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH4_EN (BIT(20)) -#define LEDC_TASK_OVF_CNT_RST_CH4_EN_M (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH4_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH4_EN_S 20 -/** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH5_EN (BIT(21)) -#define LEDC_TASK_OVF_CNT_RST_CH5_EN_M (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH5_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH5_EN_S 21 -/** LEDC_TASK_OVF_CNT_RST_CH6_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH6_EN (BIT(22)) -#define LEDC_TASK_OVF_CNT_RST_CH6_EN_M (LEDC_TASK_OVF_CNT_RST_CH6_EN_V << LEDC_TASK_OVF_CNT_RST_CH6_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH6_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH6_EN_S 22 -/** LEDC_TASK_OVF_CNT_RST_CH7_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_OVF_CNT_RST_CH7_EN (BIT(23)) -#define LEDC_TASK_OVF_CNT_RST_CH7_EN_M (LEDC_TASK_OVF_CNT_RST_CH7_EN_V << LEDC_TASK_OVF_CNT_RST_CH7_EN_S) -#define LEDC_TASK_OVF_CNT_RST_CH7_EN_V 0x00000001U -#define LEDC_TASK_OVF_CNT_RST_CH7_EN_S 23 -/** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable ledc_timer0_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER0_RST_EN (BIT(24)) -#define LEDC_TASK_TIMER0_RST_EN_M (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S) -#define LEDC_TASK_TIMER0_RST_EN_V 0x00000001U -#define LEDC_TASK_TIMER0_RST_EN_S 24 -/** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable ledc_timer1_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER1_RST_EN (BIT(25)) -#define LEDC_TASK_TIMER1_RST_EN_M (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S) -#define LEDC_TASK_TIMER1_RST_EN_V 0x00000001U -#define LEDC_TASK_TIMER1_RST_EN_S 25 -/** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable ledc_timer2_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER2_RST_EN (BIT(26)) -#define LEDC_TASK_TIMER2_RST_EN_M (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S) -#define LEDC_TASK_TIMER2_RST_EN_V 0x00000001U -#define LEDC_TASK_TIMER2_RST_EN_S 26 -/** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable ledc_timer3_rst task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER3_RST_EN (BIT(27)) -#define LEDC_TASK_TIMER3_RST_EN_M (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S) -#define LEDC_TASK_TIMER3_RST_EN_V 0x00000001U -#define LEDC_TASK_TIMER3_RST_EN_S 27 -/** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable ledc_timer0_pause_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN (BIT(28)) -#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S) -#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V 0x00000001U -#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S 28 -/** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable ledc_timer1_pause_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN (BIT(29)) -#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S) -#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V 0x00000001U -#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S 29 -/** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable ledc_timer2_pause_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN (BIT(30)) -#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S) -#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V 0x00000001U -#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S 30 -/** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable ledc_timer3_pause_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN (BIT(31)) -#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S) -#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V 0x00000001U -#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S 31 - -/** LEDC_EVT_TASK_EN2_REG register - * Ledc event task enable bit register2. - */ -#define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x128) -/** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH0_EN (BIT(0)) -#define LEDC_TASK_GAMMA_RESTART_CH0_EN_M (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH0_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH0_EN_S 0 -/** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH1_EN (BIT(1)) -#define LEDC_TASK_GAMMA_RESTART_CH1_EN_M (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH1_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH1_EN_S 1 -/** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH2_EN (BIT(2)) -#define LEDC_TASK_GAMMA_RESTART_CH2_EN_M (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH2_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH2_EN_S 2 -/** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH3_EN (BIT(3)) -#define LEDC_TASK_GAMMA_RESTART_CH3_EN_M (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH3_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH3_EN_S 3 -/** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH4_EN (BIT(4)) -#define LEDC_TASK_GAMMA_RESTART_CH4_EN_M (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH4_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH4_EN_S 4 -/** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH5_EN (BIT(5)) -#define LEDC_TASK_GAMMA_RESTART_CH5_EN_M (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH5_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH5_EN_S 5 -/** LEDC_TASK_GAMMA_RESTART_CH6_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH6_EN (BIT(6)) -#define LEDC_TASK_GAMMA_RESTART_CH6_EN_M (LEDC_TASK_GAMMA_RESTART_CH6_EN_V << LEDC_TASK_GAMMA_RESTART_CH6_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH6_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH6_EN_S 6 -/** LEDC_TASK_GAMMA_RESTART_CH7_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_restart task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESTART_CH7_EN (BIT(7)) -#define LEDC_TASK_GAMMA_RESTART_CH7_EN_M (LEDC_TASK_GAMMA_RESTART_CH7_EN_V << LEDC_TASK_GAMMA_RESTART_CH7_EN_S) -#define LEDC_TASK_GAMMA_RESTART_CH7_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESTART_CH7_EN_S 7 -/** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH0_EN (BIT(8)) -#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S 8 -/** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH1_EN (BIT(9)) -#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S 9 -/** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH2_EN (BIT(10)) -#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S 10 -/** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH3_EN (BIT(11)) -#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S 11 -/** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH4_EN (BIT(12)) -#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S 12 -/** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH5_EN (BIT(13)) -#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S 13 -/** LEDC_TASK_GAMMA_PAUSE_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH6_EN (BIT(14)) -#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_M (LEDC_TASK_GAMMA_PAUSE_CH6_EN_V << LEDC_TASK_GAMMA_PAUSE_CH6_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_S 14 -/** LEDC_TASK_GAMMA_PAUSE_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_pause task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_PAUSE_CH7_EN (BIT(15)) -#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_M (LEDC_TASK_GAMMA_PAUSE_CH7_EN_V << LEDC_TASK_GAMMA_PAUSE_CH7_EN_S) -#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_S 15 -/** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH0_EN (BIT(16)) -#define LEDC_TASK_GAMMA_RESUME_CH0_EN_M (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH0_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH0_EN_S 16 -/** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH1_EN (BIT(17)) -#define LEDC_TASK_GAMMA_RESUME_CH1_EN_M (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH1_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH1_EN_S 17 -/** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH2_EN (BIT(18)) -#define LEDC_TASK_GAMMA_RESUME_CH2_EN_M (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH2_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH2_EN_S 18 -/** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH3_EN (BIT(19)) -#define LEDC_TASK_GAMMA_RESUME_CH3_EN_M (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH3_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH3_EN_S 19 -/** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH4_EN (BIT(20)) -#define LEDC_TASK_GAMMA_RESUME_CH4_EN_M (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH4_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH4_EN_S 20 -/** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH5_EN (BIT(21)) -#define LEDC_TASK_GAMMA_RESUME_CH5_EN_M (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH5_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH5_EN_S 21 -/** LEDC_TASK_GAMMA_RESUME_CH6_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH6_EN (BIT(22)) -#define LEDC_TASK_GAMMA_RESUME_CH6_EN_M (LEDC_TASK_GAMMA_RESUME_CH6_EN_V << LEDC_TASK_GAMMA_RESUME_CH6_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH6_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH6_EN_S 22 -/** LEDC_TASK_GAMMA_RESUME_CH7_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_resume task. - * 0: Disable - * 1: Enable - */ -#define LEDC_TASK_GAMMA_RESUME_CH7_EN (BIT(23)) -#define LEDC_TASK_GAMMA_RESUME_CH7_EN_M (LEDC_TASK_GAMMA_RESUME_CH7_EN_V << LEDC_TASK_GAMMA_RESUME_CH7_EN_S) -#define LEDC_TASK_GAMMA_RESUME_CH7_EN_V 0x00000001U -#define LEDC_TASK_GAMMA_RESUME_CH7_EN_S 23 - -/** LEDC_TIMER0_CMP_REG register - * Ledc timer0 compare value register. - */ -#define LEDC_TIMER0_CMP_REG (DR_REG_LEDC_BASE + 0x140) -/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timer0. - */ -#define LEDC_TIMER0_CMP 0x000FFFFFU -#define LEDC_TIMER0_CMP_M (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S) -#define LEDC_TIMER0_CMP_V 0x000FFFFFU -#define LEDC_TIMER0_CMP_S 0 - -/** LEDC_TIMER1_CMP_REG register - * Ledc timer1 compare value register. - */ -#define LEDC_TIMER1_CMP_REG (DR_REG_LEDC_BASE + 0x144) -/** LEDC_TIMER1_CMP : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timer1. - */ -#define LEDC_TIMER1_CMP 0x000FFFFFU -#define LEDC_TIMER1_CMP_M (LEDC_TIMER1_CMP_V << LEDC_TIMER1_CMP_S) -#define LEDC_TIMER1_CMP_V 0x000FFFFFU -#define LEDC_TIMER1_CMP_S 0 - -/** LEDC_TIMER2_CMP_REG register - * Ledc timer2 compare value register. - */ -#define LEDC_TIMER2_CMP_REG (DR_REG_LEDC_BASE + 0x148) -/** LEDC_TIMER2_CMP : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timer2. - */ -#define LEDC_TIMER2_CMP 0x000FFFFFU -#define LEDC_TIMER2_CMP_M (LEDC_TIMER2_CMP_V << LEDC_TIMER2_CMP_S) -#define LEDC_TIMER2_CMP_V 0x000FFFFFU -#define LEDC_TIMER2_CMP_S 0 - -/** LEDC_TIMER3_CMP_REG register - * Ledc timer3 compare value register. - */ -#define LEDC_TIMER3_CMP_REG (DR_REG_LEDC_BASE + 0x14c) -/** LEDC_TIMER3_CMP : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timer3. - */ -#define LEDC_TIMER3_CMP 0x000FFFFFU -#define LEDC_TIMER3_CMP_M (LEDC_TIMER3_CMP_V << LEDC_TIMER3_CMP_S) -#define LEDC_TIMER3_CMP_V 0x000FFFFFU -#define LEDC_TIMER3_CMP_S 0 - -/** LEDC_TIMER0_CNT_CAP_REG register - * Ledc timer0 captured count value register. - */ -#define LEDC_TIMER0_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x150) -/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timer0 count value. - */ -#define LEDC_TIMER0_CNT_CAP 0x000FFFFFU -#define LEDC_TIMER0_CNT_CAP_M (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S) -#define LEDC_TIMER0_CNT_CAP_V 0x000FFFFFU -#define LEDC_TIMER0_CNT_CAP_S 0 - -/** LEDC_TIMER1_CNT_CAP_REG register - * Ledc timer1 captured count value register. - */ -#define LEDC_TIMER1_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x154) -/** LEDC_TIMER1_CNT_CAP : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timer1 count value. - */ -#define LEDC_TIMER1_CNT_CAP 0x000FFFFFU -#define LEDC_TIMER1_CNT_CAP_M (LEDC_TIMER1_CNT_CAP_V << LEDC_TIMER1_CNT_CAP_S) -#define LEDC_TIMER1_CNT_CAP_V 0x000FFFFFU -#define LEDC_TIMER1_CNT_CAP_S 0 - -/** LEDC_TIMER2_CNT_CAP_REG register - * Ledc timer2 captured count value register. - */ -#define LEDC_TIMER2_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x158) -/** LEDC_TIMER2_CNT_CAP : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timer2 count value. - */ -#define LEDC_TIMER2_CNT_CAP 0x000FFFFFU -#define LEDC_TIMER2_CNT_CAP_M (LEDC_TIMER2_CNT_CAP_V << LEDC_TIMER2_CNT_CAP_S) -#define LEDC_TIMER2_CNT_CAP_V 0x000FFFFFU -#define LEDC_TIMER2_CNT_CAP_S 0 - -/** LEDC_TIMER3_CNT_CAP_REG register - * Ledc timer3 captured count value register. - */ -#define LEDC_TIMER3_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x15c) -/** LEDC_TIMER3_CNT_CAP : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timer3 count value. - */ -#define LEDC_TIMER3_CNT_CAP 0x000FFFFFU -#define LEDC_TIMER3_CNT_CAP_M (LEDC_TIMER3_CNT_CAP_V << LEDC_TIMER3_CNT_CAP_S) -#define LEDC_TIMER3_CNT_CAP_V 0x000FFFFFU -#define LEDC_TIMER3_CNT_CAP_S 0 - -/** LEDC_CONF_REG register - * LEDC global configuration register - */ -#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x170) -/** LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0; - * Configures the clock source for the four timers. - * 0: APB_CLK - * 1: RC_FAST_CLK - * 2: XTAL_CLK - * 3: Invalid. No clock - */ -#define LEDC_APB_CLK_SEL 0x00000003U -#define LEDC_APB_CLK_SEL_M (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S) -#define LEDC_APB_CLK_SEL_V 0x00000003U -#define LEDC_APB_CLK_SEL_S 0 -/** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to open LEDC ch0 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram - * 1: Force open the clock gate for LEDC ch0 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH0 (BIT(2)) -#define LEDC_GAMMA_RAM_CLK_EN_CH0_M (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH0_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH0_S 2 -/** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0; - * Configures whether or not to open LEDC ch1 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram - * 1: Force open the clock gate for LEDC ch1 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH1 (BIT(3)) -#define LEDC_GAMMA_RAM_CLK_EN_CH1_M (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH1_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH1_S 3 -/** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to open LEDC ch2 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram - * 1: Force open the clock gate for LEDC ch2 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH2 (BIT(4)) -#define LEDC_GAMMA_RAM_CLK_EN_CH2_M (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH2_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH2_S 4 -/** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to open LEDC ch3 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram - * 1: Force open the clock gate for LEDC ch3 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH3 (BIT(5)) -#define LEDC_GAMMA_RAM_CLK_EN_CH3_M (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH3_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH3_S 5 -/** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to open LEDC ch4 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram - * 1: Force open the clock gate for LEDC ch4 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH4 (BIT(6)) -#define LEDC_GAMMA_RAM_CLK_EN_CH4_M (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH4_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH4_S 6 -/** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0; - * Configures whether or not to open LEDC ch5 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram - * 1: Force open the clock gate for LEDC ch5 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH5 (BIT(7)) -#define LEDC_GAMMA_RAM_CLK_EN_CH5_M (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH5_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH5_S 7 -/** LEDC_GAMMA_RAM_CLK_EN_CH6 : R/W; bitpos: [8]; default: 0; - * Configures whether or not to open LEDC ch6 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram - * 1: Force open the clock gate for LEDC ch6 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH6 (BIT(8)) -#define LEDC_GAMMA_RAM_CLK_EN_CH6_M (LEDC_GAMMA_RAM_CLK_EN_CH6_V << LEDC_GAMMA_RAM_CLK_EN_CH6_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH6_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH6_S 8 -/** LEDC_GAMMA_RAM_CLK_EN_CH7 : R/W; bitpos: [9]; default: 0; - * Configures whether or not to open LEDC ch7 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram - * 1: Force open the clock gate for LEDC ch7 gamma ram - */ -#define LEDC_GAMMA_RAM_CLK_EN_CH7 (BIT(9)) -#define LEDC_GAMMA_RAM_CLK_EN_CH7_M (LEDC_GAMMA_RAM_CLK_EN_CH7_V << LEDC_GAMMA_RAM_CLK_EN_CH7_S) -#define LEDC_GAMMA_RAM_CLK_EN_CH7_V 0x00000001U -#define LEDC_GAMMA_RAM_CLK_EN_CH7_S 9 -/** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to open register clock gate. - * 0: Open the clock gate only when application writes registers - * 1: Force open the clock gate for register - */ -#define LEDC_CLK_EN (BIT(31)) -#define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) -#define LEDC_CLK_EN_V 0x00000001U -#define LEDC_CLK_EN_S 31 - -/** LEDC_DATE_REG register - * Version control register - */ -#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x174) -/** LEDC_LEDC_DATE : R/W; bitpos: [27:0]; default: 37765152; - * Configures the version. - */ -#define LEDC_LEDC_DATE 0x0FFFFFFFU -#define LEDC_LEDC_DATE_M (LEDC_LEDC_DATE_V << LEDC_LEDC_DATE_S) -#define LEDC_LEDC_DATE_V 0x0FFFFFFFU -#define LEDC_LEDC_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_struct.h deleted file mode 100644 index ef59597dedd0..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_struct.h +++ /dev/null @@ -1,1359 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Register */ -/** Type of chn_conf0 register - * Configuration register 0 for channel n - */ -typedef union { - struct { - /** timer_sel_chn : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel n selected. - * 0: Select timer0 - * 1: Select timer1 - * 2: Select timer2 - * 3: Select timer3 - */ - uint32_t timer_sel_chn:2; - /** sig_out_en_chn : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel n. - * 0: Signal output disable - * 1: Signal output enable - */ - uint32_t sig_out_en_chn:1; - /** idle_lv_chn : R/W; bitpos: [3]; default: 0; - * Configures the output value when channel n is inactive. Valid only when - * LEDC_SIG_OUT_EN_CHn is 0. - * 0: Output level is low - * 1: Output level is high - */ - uint32_t idle_lv_chn:1; - /** para_up_chn : WT; bitpos: [4]; default: 0; - * Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, - * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn, - * LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel - * n, and will be automatically cleared by hardware. - * 0: Invalid. No effect - * 1: Update - */ - uint32_t para_up_chn:1; - /** ovf_num_chn : R/W; bitpos: [14:5]; default: 0; - * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt - * will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times. - */ - uint32_t ovf_num_chn:10; - /** ovf_cnt_en_chn : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel n. - * 0: Disable - * 1: Enable - */ - uint32_t ovf_cnt_en_chn:1; - /** ovf_cnt_reset_chn : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel n. - * 0: Invalid. No effect - * 1: Reset the ovf_cnt - */ - uint32_t ovf_cnt_reset_chn:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} ledc_chn_conf0_reg_t; - -/** Type of chn_hpoint register - * High point register for channel n - */ -typedef union { - struct { - /** hpoint_chn : R/W; bitpos: [19:0]; default: 0; - * Configures high point of signal output on channel n. The output value changes to - * high when the selected timers has reached the value specified by this register. - */ - uint32_t hpoint_chn:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_chn_hpoint_reg_t; - -/** Type of chn_duty register - * Initial duty cycle register for channel n - */ -typedef union { - struct { - /** duty_chn : R/W; bitpos: [24:0]; default: 0; - * Configures the duty of signal output on channel n. - */ - uint32_t duty_chn:25; - uint32_t reserved_25:7; - }; - uint32_t val; -} ledc_chn_duty_reg_t; - -/** Type of chn_conf1 register - * Configuration register 1 for channel n - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** duty_start_chn : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect. - * 0: Not take effect - * 1: Take effect - */ - uint32_t duty_start_chn:1; - }; - uint32_t val; -} ledc_chn_conf1_reg_t; - -/** Type of timern_conf register - * Timer n configuration register - */ -typedef union { - struct { - /** timern_duty_res : R/W; bitpos: [4:0]; default: 0; - * Configures the range of the counter in timer n. - */ - uint32_t timern_duty_res:5; - /** clk_div_timern : R/W; bitpos: [22:5]; default: 0; - * Configures the divisor for the divider in timer n.The least significant eight bits - * represent the fractional part. - */ - uint32_t clk_div_timern:18; - /** timern_pause : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer n. - * 0: Normal - * 1: Pause - */ - uint32_t timern_pause:1; - /** timern_rst : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer n. The counter will show 0 after reset. - * 0: Not reset - * 1: Reset - */ - uint32_t timern_rst:1; - uint32_t reserved_25:1; - /** timern_para_up : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMERn and LEDC_TIMERn_DUTY_RES. - * 0: Invalid. No effect - * 1: Update - */ - uint32_t timern_para_up:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} ledc_timern_conf_reg_t; - -/** Type of chn_gamma_conf register - * Ledc chn gamma config register. - */ -typedef union { - struct { - /** chn_gamma_entry_num : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC chn. - */ - uint32_t chn_gamma_entry_num:5; - /** chn_gamma_pause : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC chn. - * 0: Invalid. No effect - * 1: Pause - */ - uint32_t chn_gamma_pause:1; - /** chn_gamma_resume : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC chn. - * 0: Invalid. No effect - * 1: Resume - */ - uint32_t chn_gamma_resume:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ledc_chn_gamma_conf_reg_t; - -/** Type of evt_task_en0 register - * Ledc event task enable bit register0. - */ -typedef union { - struct { - /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch0_en:1; - /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch1_en:1; - /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch2_en:1; - /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch3_en:1; - /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch4_en:1; - /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch5_en:1; - /** evt_duty_chng_end_ch6_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch6_en:1; - /** evt_duty_chng_end_ch7_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_chng_end event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_duty_chng_end_ch7_en:1; - /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch0_en:1; - /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch1_en:1; - /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch2_en:1; - /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch3_en:1; - /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch4_en:1; - /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch5_en:1; - /** evt_ovf_cnt_pls_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch6_en:1; - /** evt_ovf_cnt_pls_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_ovf_cnt_pls_ch7_en:1; - /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the ledc_timer0_ovf event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time_ovf_timer0_en:1; - /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable the ledc_timer1_ovf event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time_ovf_timer1_en:1; - /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable the ledc_timer2_ovf event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time_ovf_timer2_en:1; - /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable the ledc_timer3_ovf event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time_ovf_timer3_en:1; - /** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable the ledc_timer0_cmp event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time0_cmp_en:1; - /** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable the ledc_timer1_cmp event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time1_cmp_en:1; - /** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable the ledc_timer2_cmp event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time2_cmp_en:1; - /** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable the ledc_timer3_cmp event. - * 0: Disable - * 1: Enable - */ - uint32_t evt_time3_cmp_en:1; - /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch0_en:1; - /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch1_en:1; - /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch2_en:1; - /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch3_en:1; - /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch4_en:1; - /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch5_en:1; - /** task_duty_scale_update_ch6_en : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch6_en:1; - /** task_duty_scale_update_ch7_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_scale_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_duty_scale_update_ch7_en:1; - }; - uint32_t val; -} ledc_evt_task_en0_reg_t; - -/** Type of evt_task_en1 register - * Ledc event task enable bit register1. - */ -typedef union { - struct { - /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_timer0_res_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer0_res_update_en:1; - /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_timer1_res_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer1_res_update_en:1; - /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_timer2_res_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer2_res_update_en:1; - /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_timer3_res_update task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer3_res_update_en:1; - /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_timer0_cap task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer0_cap_en:1; - /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_timer1_cap task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer1_cap_en:1; - /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_timer2_cap task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer2_cap_en:1; - /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_timer3_cap task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer3_cap_en:1; - /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch0_en:1; - /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch1_en:1; - /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch2_en:1; - /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch3_en:1; - /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch4_en:1; - /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch5_en:1; - /** task_sig_out_dis_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch6_en:1; - /** task_sig_out_dis_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_sig_out_dis task. - * 0: Disable - * 1: Enable - */ - uint32_t task_sig_out_dis_ch7_en:1; - /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch0_en:1; - /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch1_en:1; - /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch2_en:1; - /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch3_en:1; - /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch4_en:1; - /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch5_en:1; - /** task_ovf_cnt_rst_ch6_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch6_en:1; - /** task_ovf_cnt_rst_ch7_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_ovf_cnt_rst_ch7_en:1; - /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable ledc_timer0_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer0_rst_en:1; - /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable ledc_timer1_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer1_rst_en:1; - /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable ledc_timer2_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer2_rst_en:1; - /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable ledc_timer3_rst task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer3_rst_en:1; - /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable ledc_timer0_pause_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer0_pause_resume_en:1; - /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable ledc_timer1_pause_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer1_pause_resume_en:1; - /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable ledc_timer2_pause_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer2_pause_resume_en:1; - /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable ledc_timer3_pause_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer3_pause_resume_en:1; - }; - uint32_t val; -} ledc_evt_task_en1_reg_t; - -/** Type of evt_task_en2 register - * Ledc event task enable bit register2. - */ -typedef union { - struct { - /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch0_en:1; - /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch1_en:1; - /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch2_en:1; - /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch3_en:1; - /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch4_en:1; - /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch5_en:1; - /** task_gamma_restart_ch6_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch6_en:1; - /** task_gamma_restart_ch7_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_restart task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_restart_ch7_en:1; - /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch0_en:1; - /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch1_en:1; - /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch2_en:1; - /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch3_en:1; - /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch4_en:1; - /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch5_en:1; - /** task_gamma_pause_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch6_en:1; - /** task_gamma_pause_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_pause task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_pause_ch7_en:1; - /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch0_en:1; - /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch1_en:1; - /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch2_en:1; - /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch3_en:1; - /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch4_en:1; - /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch5_en:1; - /** task_gamma_resume_ch6_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch6_en:1; - /** task_gamma_resume_ch7_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_resume task. - * 0: Disable - * 1: Enable - */ - uint32_t task_gamma_resume_ch7_en:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} ledc_evt_task_en2_reg_t; - -/** Type of timern_cmp register - * Ledc timern compare value register. - */ -typedef union { - struct { - /** timern_cmp : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timern. - */ - uint32_t timern_cmp:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_timern_cmp_reg_t; - -/** Type of conf register - * LEDC global configuration register - */ -typedef union { - struct { - /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0; - * Configures the clock source for the four timers. - * 0: APB_CLK - * 1: RC_FAST_CLK - * 2: XTAL_CLK - * 3: Invalid. No clock - */ - uint32_t apb_clk_sel:2; - /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to open LEDC ch0 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram - * 1: Force open the clock gate for LEDC ch0 gamma ram - */ - uint32_t gamma_ram_clk_en_ch0:1; - /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; - * Configures whether or not to open LEDC ch1 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram - * 1: Force open the clock gate for LEDC ch1 gamma ram - */ - uint32_t gamma_ram_clk_en_ch1:1; - /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to open LEDC ch2 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram - * 1: Force open the clock gate for LEDC ch2 gamma ram - */ - uint32_t gamma_ram_clk_en_ch2:1; - /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to open LEDC ch3 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram - * 1: Force open the clock gate for LEDC ch3 gamma ram - */ - uint32_t gamma_ram_clk_en_ch3:1; - /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to open LEDC ch4 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram - * 1: Force open the clock gate for LEDC ch4 gamma ram - */ - uint32_t gamma_ram_clk_en_ch4:1; - /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; - * Configures whether or not to open LEDC ch5 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram - * 1: Force open the clock gate for LEDC ch5 gamma ram - */ - uint32_t gamma_ram_clk_en_ch5:1; - /** gamma_ram_clk_en_ch6 : R/W; bitpos: [8]; default: 0; - * Configures whether or not to open LEDC ch6 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram - * 1: Force open the clock gate for LEDC ch6 gamma ram - */ - uint32_t gamma_ram_clk_en_ch6:1; - /** gamma_ram_clk_en_ch7 : R/W; bitpos: [9]; default: 0; - * Configures whether or not to open LEDC ch7 gamma ram clock gate. - * 0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram - * 1: Force open the clock gate for LEDC ch7 gamma ram - */ - uint32_t gamma_ram_clk_en_ch7:1; - uint32_t reserved_10:21; - /** clk_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to open register clock gate. - * 0: Open the clock gate only when application writes registers - * 1: Force open the clock gate for register - */ - uint32_t clk_en:1; - }; - uint32_t val; -} ledc_conf_reg_t; - - -/** Group: Status Register */ -/** Type of chn_duty_r register - * Current duty cycle register for channel n - */ -typedef union { - struct { - /** duty_chn_r : RO; bitpos: [24:0]; default: 0; - * Represents the current duty of output signal on channel n. - */ - uint32_t duty_chn_r:25; - uint32_t reserved_25:7; - }; - uint32_t val; -} ledc_chn_duty_r_reg_t; - -/** Type of timern_value register - * Timer n current counter value register - */ -typedef union { - struct { - /** timern_cnt : RO; bitpos: [19:0]; default: 0; - * Represents the current counter value of timer n. - */ - uint32_t timern_cnt:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_timern_value_reg_t; - -/** Type of timern_cnt_cap register - * Ledc timern captured count value register. - */ -typedef union { - struct { - /** timern_cnt_cap : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timern count value. - */ - uint32_t timern_cnt_cap:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_timern_cnt_cap_reg_t; - - -/** Group: Interrupt Register */ -/** Type of int_raw register - * Interrupt raw status register - */ -typedef union { - struct { - /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the - * timer0 has reached its maximum counter value. - */ - uint32_t timer0_ovf_int_raw:1; - /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the - * timer1 has reached its maximum counter value. - */ - uint32_t timer1_ovf_int_raw:1; - /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the - * timer2 has reached its maximum counter value. - */ - uint32_t timer2_ovf_int_raw:1; - /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the - * timer3 has reached its maximum counter value. - */ - uint32_t timer3_ovf_int_raw:1; - /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch0_int_raw:1; - /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch1_int_raw:1; - /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch2_int_raw:1; - /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch3_int_raw:1; - /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch4_int_raw:1; - /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch5_int_raw:1; - /** duty_chng_end_ch6_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch6_int_raw:1; - /** duty_chng_end_ch7_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch7_int_raw:1; - /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. - */ - uint32_t ovf_cnt_ch0_int_raw:1; - /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. - */ - uint32_t ovf_cnt_ch1_int_raw:1; - /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. - */ - uint32_t ovf_cnt_ch2_int_raw:1; - /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. - */ - uint32_t ovf_cnt_ch3_int_raw:1; - /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. - */ - uint32_t ovf_cnt_ch4_int_raw:1; - /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. - */ - uint32_t ovf_cnt_ch5_int_raw:1; - /** ovf_cnt_ch6_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. - */ - uint32_t ovf_cnt_ch6_int_raw:1; - /** ovf_cnt_ch7_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. - */ - uint32_t ovf_cnt_ch7_int_raw:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_int_raw_reg_t; - -/** Type of int_st register - * Interrupt masked status register - */ -typedef union { - struct { - /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only - * when LEDC_TIMER0_OVF_INT_ENA is set to 1. - */ - uint32_t timer0_ovf_int_st:1; - /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only - * when LEDC_TIMER1_OVF_INT_ENA is set to 1. - */ - uint32_t timer1_ovf_int_st:1; - /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only - * when LEDC_TIMER2_OVF_INT_ENA is set to 1. - */ - uint32_t timer2_ovf_int_st:1; - /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only - * when LEDC_TIMER3_OVF_INT_ENA is set to 1. - */ - uint32_t timer3_ovf_int_st:1; - /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch0_int_st:1; - /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch1_int_st:1; - /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch2_int_st:1; - /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch3_int_st:1; - /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch4_int_st:1; - /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch5_int_st:1; - /** duty_chng_end_ch6_int_st : RO; bitpos: [10]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch6_int_st:1; - /** duty_chng_end_ch7_int_st : RO; bitpos: [11]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. - */ - uint32_t duty_chng_end_ch7_int_st:1; - /** ovf_cnt_ch0_int_st : RO; bitpos: [12]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only - * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch0_int_st:1; - /** ovf_cnt_ch1_int_st : RO; bitpos: [13]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only - * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch1_int_st:1; - /** ovf_cnt_ch2_int_st : RO; bitpos: [14]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only - * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch2_int_st:1; - /** ovf_cnt_ch3_int_st : RO; bitpos: [15]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only - * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch3_int_st:1; - /** ovf_cnt_ch4_int_st : RO; bitpos: [16]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only - * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch4_int_st:1; - /** ovf_cnt_ch5_int_st : RO; bitpos: [17]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only - * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch5_int_st:1; - /** ovf_cnt_ch6_int_st : RO; bitpos: [18]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only - * when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch6_int_st:1; - /** ovf_cnt_ch7_int_st : RO; bitpos: [19]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only - * when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. - */ - uint32_t ovf_cnt_ch7_int_st:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_int_st_reg_t; - -/** Type of int_ena register - * Interrupt enable register - */ -typedef union { - struct { - /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. - */ - uint32_t timer0_ovf_int_ena:1; - /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. - */ - uint32_t timer1_ovf_int_ena:1; - /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. - */ - uint32_t timer2_ovf_int_ena:1; - /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. - */ - uint32_t timer3_ovf_int_ena:1; - /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. - */ - uint32_t duty_chng_end_ch0_int_ena:1; - /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. - */ - uint32_t duty_chng_end_ch1_int_ena:1; - /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. - */ - uint32_t duty_chng_end_ch2_int_ena:1; - /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. - */ - uint32_t duty_chng_end_ch3_int_ena:1; - /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. - */ - uint32_t duty_chng_end_ch4_int_ena:1; - /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. - */ - uint32_t duty_chng_end_ch5_int_ena:1; - /** duty_chng_end_ch6_int_ena : R/W; bitpos: [10]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. - */ - uint32_t duty_chng_end_ch6_int_ena:1; - /** duty_chng_end_ch7_int_ena : R/W; bitpos: [11]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. - */ - uint32_t duty_chng_end_ch7_int_ena:1; - /** ovf_cnt_ch0_int_ena : R/W; bitpos: [12]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. - */ - uint32_t ovf_cnt_ch0_int_ena:1; - /** ovf_cnt_ch1_int_ena : R/W; bitpos: [13]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. - */ - uint32_t ovf_cnt_ch1_int_ena:1; - /** ovf_cnt_ch2_int_ena : R/W; bitpos: [14]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. - */ - uint32_t ovf_cnt_ch2_int_ena:1; - /** ovf_cnt_ch3_int_ena : R/W; bitpos: [15]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. - */ - uint32_t ovf_cnt_ch3_int_ena:1; - /** ovf_cnt_ch4_int_ena : R/W; bitpos: [16]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. - */ - uint32_t ovf_cnt_ch4_int_ena:1; - /** ovf_cnt_ch5_int_ena : R/W; bitpos: [17]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. - */ - uint32_t ovf_cnt_ch5_int_ena:1; - /** ovf_cnt_ch6_int_ena : R/W; bitpos: [18]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. - */ - uint32_t ovf_cnt_ch6_int_ena:1; - /** ovf_cnt_ch7_int_ena : R/W; bitpos: [19]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. - */ - uint32_t ovf_cnt_ch7_int_ena:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_int_ena_reg_t; - -/** Type of int_clr register - * Interrupt clear register - */ -typedef union { - struct { - /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. - */ - uint32_t timer0_ovf_int_clr:1; - /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. - */ - uint32_t timer1_ovf_int_clr:1; - /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. - */ - uint32_t timer2_ovf_int_clr:1; - /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. - */ - uint32_t timer3_ovf_int_clr:1; - /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. - */ - uint32_t duty_chng_end_ch0_int_clr:1; - /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. - */ - uint32_t duty_chng_end_ch1_int_clr:1; - /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. - */ - uint32_t duty_chng_end_ch2_int_clr:1; - /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. - */ - uint32_t duty_chng_end_ch3_int_clr:1; - /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. - */ - uint32_t duty_chng_end_ch4_int_clr:1; - /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. - */ - uint32_t duty_chng_end_ch5_int_clr:1; - /** duty_chng_end_ch6_int_clr : WT; bitpos: [10]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. - */ - uint32_t duty_chng_end_ch6_int_clr:1; - /** duty_chng_end_ch7_int_clr : WT; bitpos: [11]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. - */ - uint32_t duty_chng_end_ch7_int_clr:1; - /** ovf_cnt_ch0_int_clr : WT; bitpos: [12]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. - */ - uint32_t ovf_cnt_ch0_int_clr:1; - /** ovf_cnt_ch1_int_clr : WT; bitpos: [13]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. - */ - uint32_t ovf_cnt_ch1_int_clr:1; - /** ovf_cnt_ch2_int_clr : WT; bitpos: [14]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. - */ - uint32_t ovf_cnt_ch2_int_clr:1; - /** ovf_cnt_ch3_int_clr : WT; bitpos: [15]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. - */ - uint32_t ovf_cnt_ch3_int_clr:1; - /** ovf_cnt_ch4_int_clr : WT; bitpos: [16]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. - */ - uint32_t ovf_cnt_ch4_int_clr:1; - /** ovf_cnt_ch5_int_clr : WT; bitpos: [17]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. - */ - uint32_t ovf_cnt_ch5_int_clr:1; - /** ovf_cnt_ch6_int_clr : WT; bitpos: [18]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. - */ - uint32_t ovf_cnt_ch6_int_clr:1; - /** ovf_cnt_ch7_int_clr : WT; bitpos: [19]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. - */ - uint32_t ovf_cnt_ch7_int_clr:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_int_clr_reg_t; - - -/** Group: Version Register */ -/** Type of date register - * Version control register - */ -typedef union { - struct { - /** ledc_date : R/W; bitpos: [27:0]; default: 37765152; - * Configures the version. - */ - uint32_t ledc_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} ledc_date_reg_t; - - -typedef struct { - volatile ledc_chn_conf0_reg_t ch0_conf0; - volatile ledc_chn_hpoint_reg_t ch0_hpoint; - volatile ledc_chn_duty_reg_t ch0_duty; - volatile ledc_chn_conf1_reg_t ch0_conf1; - volatile ledc_chn_duty_r_reg_t ch0_duty_r; - volatile ledc_chn_conf0_reg_t ch1_conf0; - volatile ledc_chn_hpoint_reg_t ch1_hpoint; - volatile ledc_chn_duty_reg_t ch1_duty; - volatile ledc_chn_conf1_reg_t ch1_conf1; - volatile ledc_chn_duty_r_reg_t ch1_duty_r; - volatile ledc_chn_conf0_reg_t ch2_conf0; - volatile ledc_chn_hpoint_reg_t ch2_hpoint; - volatile ledc_chn_duty_reg_t ch2_duty; - volatile ledc_chn_conf1_reg_t ch2_conf1; - volatile ledc_chn_duty_r_reg_t ch2_duty_r; - volatile ledc_chn_conf0_reg_t ch3_conf0; - volatile ledc_chn_hpoint_reg_t ch3_hpoint; - volatile ledc_chn_duty_reg_t ch3_duty; - volatile ledc_chn_conf1_reg_t ch3_conf1; - volatile ledc_chn_duty_r_reg_t ch3_duty_r; - volatile ledc_chn_conf0_reg_t ch4_conf0; - volatile ledc_chn_hpoint_reg_t ch4_hpoint; - volatile ledc_chn_duty_reg_t ch4_duty; - volatile ledc_chn_conf1_reg_t ch4_conf1; - volatile ledc_chn_duty_r_reg_t ch4_duty_r; - volatile ledc_chn_conf0_reg_t ch5_conf0; - volatile ledc_chn_hpoint_reg_t ch5_hpoint; - volatile ledc_chn_duty_reg_t ch5_duty; - volatile ledc_chn_conf1_reg_t ch5_conf1; - volatile ledc_chn_duty_r_reg_t ch5_duty_r; - volatile ledc_chn_conf0_reg_t ch6_conf0; - volatile ledc_chn_hpoint_reg_t ch6_hpoint; - volatile ledc_chn_duty_reg_t ch6_duty; - volatile ledc_chn_conf1_reg_t ch6_conf1; - volatile ledc_chn_duty_r_reg_t ch6_duty_r; - volatile ledc_chn_conf0_reg_t ch7_conf0; - volatile ledc_chn_hpoint_reg_t ch7_hpoint; - volatile ledc_chn_duty_reg_t ch7_duty; - volatile ledc_chn_conf1_reg_t ch7_conf1; - volatile ledc_chn_duty_r_reg_t ch7_duty_r; - volatile ledc_timern_conf_reg_t timer0_conf; - volatile ledc_timern_value_reg_t timer0_value; - volatile ledc_timern_conf_reg_t timer1_conf; - volatile ledc_timern_value_reg_t timer1_value; - volatile ledc_timern_conf_reg_t timer2_conf; - volatile ledc_timern_value_reg_t timer2_value; - volatile ledc_timern_conf_reg_t timer3_conf; - volatile ledc_timern_value_reg_t timer3_value; - volatile ledc_int_raw_reg_t int_raw; - volatile ledc_int_st_reg_t int_st; - volatile ledc_int_ena_reg_t int_ena; - volatile ledc_int_clr_reg_t int_clr; - uint32_t reserved_0d0[12]; - volatile ledc_chn_gamma_conf_reg_t chn_gamma_conf[8]; - volatile ledc_evt_task_en0_reg_t evt_task_en0; - volatile ledc_evt_task_en1_reg_t evt_task_en1; - volatile ledc_evt_task_en2_reg_t evt_task_en2; - uint32_t reserved_12c[5]; - volatile ledc_timern_cmp_reg_t timern_cmp[4]; - volatile ledc_timern_cnt_cap_reg_t timern_cnt_cap[4]; - uint32_t reserved_160[4]; - volatile ledc_conf_reg_t conf; - volatile ledc_date_reg_t date; -} ledc_dev_t; - -extern ledc_dev_t LEDC; - -#ifndef __cplusplus -_Static_assert(sizeof(ledc_dev_t) == 0x178, "Invalid size of ledc_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h index 05d7e02bbc18..6599e1dab012 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h @@ -16,16 +16,20 @@ extern "C" { */ #define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) /** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 0 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 0 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH0 0x00000003U #define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) #define LEDC_TIMER_SEL_CH0_V 0x00000003U #define LEDC_TIMER_SEL_CH0_S 0 /** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 0.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 0. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH0 (BIT(2)) #define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) @@ -33,7 +37,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH0_S 2 /** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 0 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH0 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH0 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH0 (BIT(3)) #define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) @@ -43,7 +49,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0, * LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0, LEDC_DUTY_CYCLE_CH0, * LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and LEDC_OVF_CNT_EN_CH0 fields for channel - * 0, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 0, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH0 (BIT(4)) #define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) @@ -58,15 +66,18 @@ extern "C" { #define LEDC_OVF_NUM_CH0_V 0x000003FFU #define LEDC_OVF_NUM_CH0_S 5 /** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 0.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 0. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH0 (BIT(15)) #define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) #define LEDC_OVF_CNT_EN_CH0_V 0x00000001U #define LEDC_OVF_CNT_EN_CH0_S 15 /** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 0.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 0. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) @@ -103,8 +114,9 @@ extern "C" { */ #define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) /** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH0 (BIT(31)) #define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) @@ -128,16 +140,20 @@ extern "C" { */ #define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) /** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 1 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 1 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH1 0x00000003U #define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) #define LEDC_TIMER_SEL_CH1_V 0x00000003U #define LEDC_TIMER_SEL_CH1_S 0 /** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 1.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 1. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH1 (BIT(2)) #define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) @@ -145,7 +161,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH1_S 2 /** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 1 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH1 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH1 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH1 (BIT(3)) #define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) @@ -155,7 +173,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1, * LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1, * LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel - * 1, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 1, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH1 (BIT(4)) #define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) @@ -170,15 +190,18 @@ extern "C" { #define LEDC_OVF_NUM_CH1_V 0x000003FFU #define LEDC_OVF_NUM_CH1_S 5 /** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 1.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 1. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH1 (BIT(15)) #define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) #define LEDC_OVF_CNT_EN_CH1_V 0x00000001U #define LEDC_OVF_CNT_EN_CH1_S 15 /** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 1.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 1. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) @@ -215,8 +238,9 @@ extern "C" { */ #define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) /** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH1 (BIT(31)) #define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) @@ -240,16 +264,20 @@ extern "C" { */ #define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) /** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 2 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 2 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH2 0x00000003U #define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) #define LEDC_TIMER_SEL_CH2_V 0x00000003U #define LEDC_TIMER_SEL_CH2_S 0 /** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 2.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 2. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH2 (BIT(2)) #define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) @@ -257,7 +285,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH2_S 2 /** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 2 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH2 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH2 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH2 (BIT(3)) #define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) @@ -267,7 +297,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2, * LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2, * LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel - * 2, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 2, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH2 (BIT(4)) #define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) @@ -282,15 +314,18 @@ extern "C" { #define LEDC_OVF_NUM_CH2_V 0x000003FFU #define LEDC_OVF_NUM_CH2_S 5 /** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 2.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 2. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH2 (BIT(15)) #define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) #define LEDC_OVF_CNT_EN_CH2_V 0x00000001U #define LEDC_OVF_CNT_EN_CH2_S 15 /** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 2.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 2. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) @@ -327,8 +362,9 @@ extern "C" { */ #define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) /** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH2 (BIT(31)) #define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) @@ -352,16 +388,20 @@ extern "C" { */ #define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) /** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 3 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 3 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH3 0x00000003U #define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) #define LEDC_TIMER_SEL_CH3_V 0x00000003U #define LEDC_TIMER_SEL_CH3_S 0 /** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 3.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 3. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH3 (BIT(2)) #define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) @@ -369,7 +409,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH3_S 2 /** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 3 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH3 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH3 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH3 (BIT(3)) #define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) @@ -379,7 +421,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3, * LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3, * LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel - * 3, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 3, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH3 (BIT(4)) #define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) @@ -394,15 +438,18 @@ extern "C" { #define LEDC_OVF_NUM_CH3_V 0x000003FFU #define LEDC_OVF_NUM_CH3_S 5 /** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 3.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 3. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH3 (BIT(15)) #define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) #define LEDC_OVF_CNT_EN_CH3_V 0x00000001U #define LEDC_OVF_CNT_EN_CH3_S 15 /** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 3.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 3. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) @@ -439,8 +486,9 @@ extern "C" { */ #define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) /** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH3 (BIT(31)) #define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) @@ -464,16 +512,20 @@ extern "C" { */ #define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) /** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 4 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 4 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH4 0x00000003U #define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) #define LEDC_TIMER_SEL_CH4_V 0x00000003U #define LEDC_TIMER_SEL_CH4_S 0 /** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 4.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 4. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH4 (BIT(2)) #define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) @@ -481,7 +533,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH4_S 2 /** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 4 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH4 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH4 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH4 (BIT(3)) #define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) @@ -491,7 +545,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4, * LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4, * LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel - * 4, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 4, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH4 (BIT(4)) #define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) @@ -506,15 +562,18 @@ extern "C" { #define LEDC_OVF_NUM_CH4_V 0x000003FFU #define LEDC_OVF_NUM_CH4_S 5 /** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 4.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 4. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH4 (BIT(15)) #define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) #define LEDC_OVF_CNT_EN_CH4_V 0x00000001U #define LEDC_OVF_CNT_EN_CH4_S 15 /** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 4.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 4. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) @@ -551,8 +610,9 @@ extern "C" { */ #define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) /** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH4 (BIT(31)) #define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) @@ -576,16 +636,20 @@ extern "C" { */ #define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) /** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 5 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 5 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH5 0x00000003U #define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) #define LEDC_TIMER_SEL_CH5_V 0x00000003U #define LEDC_TIMER_SEL_CH5_S 0 /** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 5.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 5. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH5 (BIT(2)) #define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) @@ -593,7 +657,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH5_S 2 /** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 5 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH5 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH5 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH5 (BIT(3)) #define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) @@ -603,7 +669,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5, * LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5, * LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel - * 5, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 5, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH5 (BIT(4)) #define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) @@ -618,15 +686,18 @@ extern "C" { #define LEDC_OVF_NUM_CH5_V 0x000003FFU #define LEDC_OVF_NUM_CH5_S 5 /** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 5.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 5. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH5 (BIT(15)) #define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) #define LEDC_OVF_CNT_EN_CH5_V 0x00000001U #define LEDC_OVF_CNT_EN_CH5_S 15 /** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 5.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 5. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) @@ -663,8 +734,9 @@ extern "C" { */ #define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) /** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH5 (BIT(31)) #define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) @@ -688,16 +760,20 @@ extern "C" { */ #define LEDC_CH6_CONF0_REG (DR_REG_LEDC_BASE + 0x78) /** LEDC_TIMER_SEL_CH6 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 6 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 6 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH6 0x00000003U #define LEDC_TIMER_SEL_CH6_M (LEDC_TIMER_SEL_CH6_V << LEDC_TIMER_SEL_CH6_S) #define LEDC_TIMER_SEL_CH6_V 0x00000003U #define LEDC_TIMER_SEL_CH6_S 0 /** LEDC_SIG_OUT_EN_CH6 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 6.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 6. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH6 (BIT(2)) #define LEDC_SIG_OUT_EN_CH6_M (LEDC_SIG_OUT_EN_CH6_V << LEDC_SIG_OUT_EN_CH6_S) @@ -705,7 +781,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH6_S 2 /** LEDC_IDLE_LV_CH6 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 6 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH6 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH6 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH6 (BIT(3)) #define LEDC_IDLE_LV_CH6_M (LEDC_IDLE_LV_CH6_V << LEDC_IDLE_LV_CH6_S) @@ -715,7 +793,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH6, LEDC_DUTY_START_CH6, * LEDC_SIG_OUT_EN_CH6, LEDC_TIMER_SEL_CH6, LEDC_DUTY_NUM_CH6, LEDC_DUTY_CYCLE_CH6, * LEDC_DUTY_SCALE_CH6, LEDC_DUTY_INC_CH6, and LEDC_OVF_CNT_EN_CH6 fields for channel - * 6, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 6, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH6 (BIT(4)) #define LEDC_PARA_UP_CH6_M (LEDC_PARA_UP_CH6_V << LEDC_PARA_UP_CH6_S) @@ -730,15 +810,18 @@ extern "C" { #define LEDC_OVF_NUM_CH6_V 0x000003FFU #define LEDC_OVF_NUM_CH6_S 5 /** LEDC_OVF_CNT_EN_CH6 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 6.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 6. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH6 (BIT(15)) #define LEDC_OVF_CNT_EN_CH6_M (LEDC_OVF_CNT_EN_CH6_V << LEDC_OVF_CNT_EN_CH6_S) #define LEDC_OVF_CNT_EN_CH6_V 0x00000001U #define LEDC_OVF_CNT_EN_CH6_S 15 /** LEDC_OVF_CNT_RESET_CH6 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 6.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 6. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH6 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH6_M (LEDC_OVF_CNT_RESET_CH6_V << LEDC_OVF_CNT_RESET_CH6_S) @@ -775,8 +858,9 @@ extern "C" { */ #define LEDC_CH6_CONF1_REG (DR_REG_LEDC_BASE + 0x84) /** LEDC_DUTY_START_CH6 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH6 (BIT(31)) #define LEDC_DUTY_START_CH6_M (LEDC_DUTY_START_CH6_V << LEDC_DUTY_START_CH6_S) @@ -800,16 +884,20 @@ extern "C" { */ #define LEDC_CH7_CONF0_REG (DR_REG_LEDC_BASE + 0x8c) /** LEDC_TIMER_SEL_CH7 : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel 7 selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel 7 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ #define LEDC_TIMER_SEL_CH7 0x00000003U #define LEDC_TIMER_SEL_CH7_M (LEDC_TIMER_SEL_CH7_V << LEDC_TIMER_SEL_CH7_S) #define LEDC_TIMER_SEL_CH7_V 0x00000003U #define LEDC_TIMER_SEL_CH7_S 0 /** LEDC_SIG_OUT_EN_CH7 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel 7.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel 7. + * 0: Signal output disable + * 1: Signal output enable */ #define LEDC_SIG_OUT_EN_CH7 (BIT(2)) #define LEDC_SIG_OUT_EN_CH7_M (LEDC_SIG_OUT_EN_CH7_V << LEDC_SIG_OUT_EN_CH7_S) @@ -817,7 +905,9 @@ extern "C" { #define LEDC_SIG_OUT_EN_CH7_S 2 /** LEDC_IDLE_LV_CH7 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 7 is inactive. Valid only when - * LEDC_SIG_OUT_EN_CH7 is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CH7 is 0. + * 0: Output level is low + * 1: Output level is high */ #define LEDC_IDLE_LV_CH7 (BIT(3)) #define LEDC_IDLE_LV_CH7_M (LEDC_IDLE_LV_CH7_V << LEDC_IDLE_LV_CH7_S) @@ -827,7 +917,9 @@ extern "C" { * Configures whether or not to update LEDC_HPOINT_CH7, LEDC_DUTY_START_CH7, * LEDC_SIG_OUT_EN_CH7, LEDC_TIMER_SEL_CH7, LEDC_DUTY_NUM_CH7, LEDC_DUTY_CYCLE_CH7, * LEDC_DUTY_SCALE_CH7, LEDC_DUTY_INC_CH7, and LEDC_OVF_CNT_EN_CH7 fields for channel - * 7, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * 7, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_PARA_UP_CH7 (BIT(4)) #define LEDC_PARA_UP_CH7_M (LEDC_PARA_UP_CH7_V << LEDC_PARA_UP_CH7_S) @@ -842,15 +934,18 @@ extern "C" { #define LEDC_OVF_NUM_CH7_V 0x000003FFU #define LEDC_OVF_NUM_CH7_S 5 /** LEDC_OVF_CNT_EN_CH7 : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel 7.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel 7. + * 0: Disable + * 1: Enable */ #define LEDC_OVF_CNT_EN_CH7 (BIT(15)) #define LEDC_OVF_CNT_EN_CH7_M (LEDC_OVF_CNT_EN_CH7_V << LEDC_OVF_CNT_EN_CH7_S) #define LEDC_OVF_CNT_EN_CH7_V 0x00000001U #define LEDC_OVF_CNT_EN_CH7_S 15 /** LEDC_OVF_CNT_RESET_CH7 : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel 7.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel 7. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ #define LEDC_OVF_CNT_RESET_CH7 (BIT(16)) #define LEDC_OVF_CNT_RESET_CH7_M (LEDC_OVF_CNT_RESET_CH7_V << LEDC_OVF_CNT_RESET_CH7_S) @@ -887,8 +982,9 @@ extern "C" { */ #define LEDC_CH7_CONF1_REG (DR_REG_LEDC_BASE + 0x98) /** LEDC_DUTY_START_CH7 : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ #define LEDC_DUTY_START_CH7 (BIT(31)) #define LEDC_DUTY_START_CH7_M (LEDC_DUTY_START_CH7_V << LEDC_DUTY_START_CH7_S) @@ -927,30 +1023,27 @@ extern "C" { #define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU #define LEDC_CLK_DIV_TIMER0_S 5 /** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 0.\\0: Normal\\1: Pause + * Configures whether or not to pause the counter in timer 0. + * 0: Normal + * 1: Pause */ #define LEDC_TIMER0_PAUSE (BIT(23)) #define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) #define LEDC_TIMER0_PAUSE_V 0x00000001U #define LEDC_TIMER0_PAUSE_S 23 /** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 0. The counter will show 0 after - * reset.\\0: Not reset\\1: Reset + * Configures whether or not to reset timer 0. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset */ #define LEDC_TIMER0_RST (BIT(24)) #define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) #define LEDC_TIMER0_RST_V 0x00000001U #define LEDC_TIMER0_RST_S 24 -/** LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [25]; default: 0; - * Configures which clock is timer 0 selected. Unused. - */ -#define LEDC_TICK_SEL_TIMER0 (BIT(25)) -#define LEDC_TICK_SEL_TIMER0_M (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S) -#define LEDC_TICK_SEL_TIMER0_V 0x00000001U -#define LEDC_TICK_SEL_TIMER0_S 25 /** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER0 and - * LEDC_TIMER0_DUTY_RES.\\0: Invalid. No effect\\1: Update + * Configures whether or not to update LEDC_CLK_DIV_TIMER0 and LEDC_TIMER0_DUTY_RES. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_TIMER0_PARA_UP (BIT(26)) #define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) @@ -989,30 +1082,27 @@ extern "C" { #define LEDC_CLK_DIV_TIMER1_V 0x0003FFFFU #define LEDC_CLK_DIV_TIMER1_S 5 /** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 1.\\0: Normal\\1: Pause + * Configures whether or not to pause the counter in timer 1. + * 0: Normal + * 1: Pause */ #define LEDC_TIMER1_PAUSE (BIT(23)) #define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) #define LEDC_TIMER1_PAUSE_V 0x00000001U #define LEDC_TIMER1_PAUSE_S 23 /** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 1. The counter will show 0 after - * reset.\\0: Not reset\\1: Reset + * Configures whether or not to reset timer 1. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset */ #define LEDC_TIMER1_RST (BIT(24)) #define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) #define LEDC_TIMER1_RST_V 0x00000001U #define LEDC_TIMER1_RST_S 24 -/** LEDC_TICK_SEL_TIMER1 : R/W; bitpos: [25]; default: 0; - * Configures which clock is timer 1 selected. Unused. - */ -#define LEDC_TICK_SEL_TIMER1 (BIT(25)) -#define LEDC_TICK_SEL_TIMER1_M (LEDC_TICK_SEL_TIMER1_V << LEDC_TICK_SEL_TIMER1_S) -#define LEDC_TICK_SEL_TIMER1_V 0x00000001U -#define LEDC_TICK_SEL_TIMER1_S 25 /** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER1 and - * LEDC_TIMER1_DUTY_RES.\\0: Invalid. No effect\\1: Update + * Configures whether or not to update LEDC_CLK_DIV_TIMER1 and LEDC_TIMER1_DUTY_RES. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_TIMER1_PARA_UP (BIT(26)) #define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) @@ -1051,30 +1141,27 @@ extern "C" { #define LEDC_CLK_DIV_TIMER2_V 0x0003FFFFU #define LEDC_CLK_DIV_TIMER2_S 5 /** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 2.\\0: Normal\\1: Pause + * Configures whether or not to pause the counter in timer 2. + * 0: Normal + * 1: Pause */ #define LEDC_TIMER2_PAUSE (BIT(23)) #define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) #define LEDC_TIMER2_PAUSE_V 0x00000001U #define LEDC_TIMER2_PAUSE_S 23 /** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 2. The counter will show 0 after - * reset.\\0: Not reset\\1: Reset + * Configures whether or not to reset timer 2. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset */ #define LEDC_TIMER2_RST (BIT(24)) #define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) #define LEDC_TIMER2_RST_V 0x00000001U #define LEDC_TIMER2_RST_S 24 -/** LEDC_TICK_SEL_TIMER2 : R/W; bitpos: [25]; default: 0; - * Configures which clock is timer 2 selected. Unused. - */ -#define LEDC_TICK_SEL_TIMER2 (BIT(25)) -#define LEDC_TICK_SEL_TIMER2_M (LEDC_TICK_SEL_TIMER2_V << LEDC_TICK_SEL_TIMER2_S) -#define LEDC_TICK_SEL_TIMER2_V 0x00000001U -#define LEDC_TICK_SEL_TIMER2_S 25 /** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER2 and - * LEDC_TIMER2_DUTY_RES.\\0: Invalid. No effect\\1: Update + * Configures whether or not to update LEDC_CLK_DIV_TIMER2 and LEDC_TIMER2_DUTY_RES. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_TIMER2_PARA_UP (BIT(26)) #define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) @@ -1113,30 +1200,27 @@ extern "C" { #define LEDC_CLK_DIV_TIMER3_V 0x0003FFFFU #define LEDC_CLK_DIV_TIMER3_S 5 /** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer 3.\\0: Normal\\1: Pause + * Configures whether or not to pause the counter in timer 3. + * 0: Normal + * 1: Pause */ #define LEDC_TIMER3_PAUSE (BIT(23)) #define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) #define LEDC_TIMER3_PAUSE_V 0x00000001U #define LEDC_TIMER3_PAUSE_S 23 /** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer 3. The counter will show 0 after - * reset.\\0: Not reset\\1: Reset + * Configures whether or not to reset timer 3. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset */ #define LEDC_TIMER3_RST (BIT(24)) #define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) #define LEDC_TIMER3_RST_V 0x00000001U #define LEDC_TIMER3_RST_S 24 -/** LEDC_TICK_SEL_TIMER3 : R/W; bitpos: [25]; default: 0; - * Configures which clock is timer 3 selected. Unused. - */ -#define LEDC_TICK_SEL_TIMER3 (BIT(25)) -#define LEDC_TICK_SEL_TIMER3_M (LEDC_TICK_SEL_TIMER3_V << LEDC_TICK_SEL_TIMER3_S) -#define LEDC_TICK_SEL_TIMER3_V 0x00000001U -#define LEDC_TICK_SEL_TIMER3_S 25 /** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMER3 and - * LEDC_TIMER3_DUTY_RES.\\0: Invalid. No effect\\1: Update + * Configures whether or not to update LEDC_CLK_DIV_TIMER3 and LEDC_TIMER3_DUTY_RES. + * 0: Invalid. No effect + * 1: Update */ #define LEDC_TIMER3_PARA_UP (BIT(26)) #define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) @@ -1787,16 +1871,18 @@ extern "C" { #define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch0.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch0. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH0_GAMMA_PAUSE (BIT(5)) #define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) #define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH0_GAMMA_PAUSE_S 5 /** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch0.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch0. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH0_GAMMA_RESUME (BIT(6)) #define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) @@ -1815,16 +1901,18 @@ extern "C" { #define LEDC_CH1_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH1_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch1.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch1. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH1_GAMMA_PAUSE (BIT(5)) #define LEDC_CH1_GAMMA_PAUSE_M (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S) #define LEDC_CH1_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH1_GAMMA_PAUSE_S 5 /** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch1.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch1. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH1_GAMMA_RESUME (BIT(6)) #define LEDC_CH1_GAMMA_RESUME_M (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S) @@ -1843,16 +1931,18 @@ extern "C" { #define LEDC_CH2_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH2_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch2.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch2. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH2_GAMMA_PAUSE (BIT(5)) #define LEDC_CH2_GAMMA_PAUSE_M (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S) #define LEDC_CH2_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH2_GAMMA_PAUSE_S 5 /** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch2.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch2. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH2_GAMMA_RESUME (BIT(6)) #define LEDC_CH2_GAMMA_RESUME_M (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S) @@ -1871,16 +1961,18 @@ extern "C" { #define LEDC_CH3_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH3_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch3.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch3. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH3_GAMMA_PAUSE (BIT(5)) #define LEDC_CH3_GAMMA_PAUSE_M (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S) #define LEDC_CH3_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH3_GAMMA_PAUSE_S 5 /** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch3.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch3. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH3_GAMMA_RESUME (BIT(6)) #define LEDC_CH3_GAMMA_RESUME_M (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S) @@ -1899,16 +1991,18 @@ extern "C" { #define LEDC_CH4_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH4_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch4.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch4. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH4_GAMMA_PAUSE (BIT(5)) #define LEDC_CH4_GAMMA_PAUSE_M (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S) #define LEDC_CH4_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH4_GAMMA_PAUSE_S 5 /** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch4.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch4. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH4_GAMMA_RESUME (BIT(6)) #define LEDC_CH4_GAMMA_RESUME_M (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S) @@ -1927,16 +2021,18 @@ extern "C" { #define LEDC_CH5_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH5_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch5.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch5. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH5_GAMMA_PAUSE (BIT(5)) #define LEDC_CH5_GAMMA_PAUSE_M (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S) #define LEDC_CH5_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH5_GAMMA_PAUSE_S 5 /** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch5.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch5. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH5_GAMMA_RESUME (BIT(6)) #define LEDC_CH5_GAMMA_RESUME_M (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S) @@ -1955,16 +2051,18 @@ extern "C" { #define LEDC_CH6_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH6_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH6_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch6.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch6. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH6_GAMMA_PAUSE (BIT(5)) #define LEDC_CH6_GAMMA_PAUSE_M (LEDC_CH6_GAMMA_PAUSE_V << LEDC_CH6_GAMMA_PAUSE_S) #define LEDC_CH6_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH6_GAMMA_PAUSE_S 5 /** LEDC_CH6_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch6.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch6. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH6_GAMMA_RESUME (BIT(6)) #define LEDC_CH6_GAMMA_RESUME_M (LEDC_CH6_GAMMA_RESUME_V << LEDC_CH6_GAMMA_RESUME_S) @@ -1983,16 +2081,18 @@ extern "C" { #define LEDC_CH7_GAMMA_ENTRY_NUM_V 0x0000001FU #define LEDC_CH7_GAMMA_ENTRY_NUM_S 0 /** LEDC_CH7_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC ch7.\\0: Invalid. No - * effect\\1: Pause + * Configures whether or not to pause duty cycle fading of LEDC ch7. + * 0: Invalid. No effect + * 1: Pause */ #define LEDC_CH7_GAMMA_PAUSE (BIT(5)) #define LEDC_CH7_GAMMA_PAUSE_M (LEDC_CH7_GAMMA_PAUSE_V << LEDC_CH7_GAMMA_PAUSE_S) #define LEDC_CH7_GAMMA_PAUSE_V 0x00000001U #define LEDC_CH7_GAMMA_PAUSE_S 5 /** LEDC_CH7_GAMMA_RESUME : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC ch7.\\0: Invalid. No - * effect\\1: Resume + * Configures whether or nor to resume duty cycle fading of LEDC ch7. + * 0: Invalid. No effect + * 1: Resume */ #define LEDC_CH7_GAMMA_RESUME (BIT(6)) #define LEDC_CH7_GAMMA_RESUME_M (LEDC_CH7_GAMMA_RESUME_V << LEDC_CH7_GAMMA_RESUME_S) @@ -2004,256 +2104,288 @@ extern "C" { */ #define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x120) /** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch0_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH0_EN (BIT(0)) #define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S 0 /** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch1_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH1_EN (BIT(1)) #define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S 1 /** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch2_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH2_EN (BIT(2)) #define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S 2 /** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch3_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH3_EN (BIT(3)) #define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S 3 /** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch4_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH4_EN (BIT(4)) #define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S 4 /** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch5_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH5_EN (BIT(5)) #define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S 5 /** LEDC_EVT_DUTY_CHNG_END_CH6_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch6_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH6_EN (BIT(6)) #define LEDC_EVT_DUTY_CHNG_END_CH6_EN_M (LEDC_EVT_DUTY_CHNG_END_CH6_EN_V << LEDC_EVT_DUTY_CHNG_END_CH6_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH6_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH6_EN_S 6 /** LEDC_EVT_DUTY_CHNG_END_CH7_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch7_duty_chng_end event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_DUTY_CHNG_END_CH7_EN (BIT(7)) #define LEDC_EVT_DUTY_CHNG_END_CH7_EN_M (LEDC_EVT_DUTY_CHNG_END_CH7_EN_V << LEDC_EVT_DUTY_CHNG_END_CH7_EN_S) #define LEDC_EVT_DUTY_CHNG_END_CH7_EN_V 0x00000001U #define LEDC_EVT_DUTY_CHNG_END_CH7_EN_S 7 /** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH0_EN (BIT(8)) #define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S 8 /** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH1_EN (BIT(9)) #define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S 9 /** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH2_EN (BIT(10)) #define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S 10 /** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH3_EN (BIT(11)) #define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S 11 /** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH4_EN (BIT(12)) #define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S 12 /** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH5_EN (BIT(13)) #define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S 13 /** LEDC_EVT_OVF_CNT_PLS_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH6_EN (BIT(14)) #define LEDC_EVT_OVF_CNT_PLS_CH6_EN_M (LEDC_EVT_OVF_CNT_PLS_CH6_EN_V << LEDC_EVT_OVF_CNT_PLS_CH6_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH6_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH6_EN_S 14 /** LEDC_EVT_OVF_CNT_PLS_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_OVF_CNT_PLS_CH7_EN (BIT(15)) #define LEDC_EVT_OVF_CNT_PLS_CH7_EN_M (LEDC_EVT_OVF_CNT_PLS_CH7_EN_V << LEDC_EVT_OVF_CNT_PLS_CH7_EN_S) #define LEDC_EVT_OVF_CNT_PLS_CH7_EN_V 0x00000001U #define LEDC_EVT_OVF_CNT_PLS_CH7_EN_S 15 /** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_timer0_ovf event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_TIME_OVF_TIMER0_EN (BIT(16)) #define LEDC_EVT_TIME_OVF_TIMER0_EN_M (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S) #define LEDC_EVT_TIME_OVF_TIMER0_EN_V 0x00000001U #define LEDC_EVT_TIME_OVF_TIMER0_EN_S 16 /** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_timer1_ovf event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_TIME_OVF_TIMER1_EN (BIT(17)) #define LEDC_EVT_TIME_OVF_TIMER1_EN_M (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S) #define LEDC_EVT_TIME_OVF_TIMER1_EN_V 0x00000001U #define LEDC_EVT_TIME_OVF_TIMER1_EN_S 17 /** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_timer2_ovf event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_TIME_OVF_TIMER2_EN (BIT(18)) #define LEDC_EVT_TIME_OVF_TIMER2_EN_M (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S) #define LEDC_EVT_TIME_OVF_TIMER2_EN_V 0x00000001U #define LEDC_EVT_TIME_OVF_TIMER2_EN_S 18 /** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: - * Enable + * Configures whether or not to enable the ledc_timer3_ovf event. + * 0: Disable + * 1: Enable */ #define LEDC_EVT_TIME_OVF_TIMER3_EN (BIT(19)) #define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S) #define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U #define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19 -/** LEDC_EVT_TIMER0_CMP_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: - * Enable - */ -#define LEDC_EVT_TIMER0_CMP_EN (BIT(20)) -#define LEDC_EVT_TIMER0_CMP_EN_M (LEDC_EVT_TIMER0_CMP_EN_V << LEDC_EVT_TIMER0_CMP_EN_S) -#define LEDC_EVT_TIMER0_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIMER0_CMP_EN_S 20 -/** LEDC_EVT_TIMER1_CMP_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: - * Enable - */ -#define LEDC_EVT_TIMER1_CMP_EN (BIT(21)) -#define LEDC_EVT_TIMER1_CMP_EN_M (LEDC_EVT_TIMER1_CMP_EN_V << LEDC_EVT_TIMER1_CMP_EN_S) -#define LEDC_EVT_TIMER1_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIMER1_CMP_EN_S 21 -/** LEDC_EVT_TIMER2_CMP_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: - * Enable - */ -#define LEDC_EVT_TIMER2_CMP_EN (BIT(22)) -#define LEDC_EVT_TIMER2_CMP_EN_M (LEDC_EVT_TIMER2_CMP_EN_V << LEDC_EVT_TIMER2_CMP_EN_S) -#define LEDC_EVT_TIMER2_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIMER2_CMP_EN_S 22 -/** LEDC_EVT_TIMER3_CMP_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: - * Enable - */ -#define LEDC_EVT_TIMER3_CMP_EN (BIT(23)) -#define LEDC_EVT_TIMER3_CMP_EN_M (LEDC_EVT_TIMER3_CMP_EN_V << LEDC_EVT_TIMER3_CMP_EN_S) -#define LEDC_EVT_TIMER3_CMP_EN_V 0x00000001U -#define LEDC_EVT_TIMER3_CMP_EN_S 23 +/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the ledc_timer0_cmp event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_TIME0_CMP_EN (BIT(20)) +#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S) +#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME0_CMP_EN_S 20 +/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the ledc_timer1_cmp event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_TIME1_CMP_EN (BIT(21)) +#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S) +#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME1_CMP_EN_S 21 +/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the ledc_timer2_cmp event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_TIME2_CMP_EN (BIT(22)) +#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S) +#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME2_CMP_EN_S 22 +/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the ledc_timer3_cmp event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_TIME3_CMP_EN (BIT(23)) +#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S) +#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME3_CMP_EN_S 23 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch0_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN (BIT(24)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S 24 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch1_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN (BIT(25)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S 25 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch2_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN (BIT(26)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S 26 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch3_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN (BIT(27)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S 27 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch4_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN (BIT(28)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S 28 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch5_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN (BIT(29)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S 29 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch6_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN (BIT(30)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V 0x00000001U #define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S 30 /** LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\0: - * Disable\\1: Enable + * Configures whether or not to enable the ledc_ch7_duty_scale_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN (BIT(31)) #define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S) @@ -2265,248 +2397,288 @@ extern "C" { */ #define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x124) /** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer0_res_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER0_RES_UPDATE_EN (BIT(0)) #define LEDC_TASK_TIMER0_RES_UPDATE_EN_M (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S) #define LEDC_TASK_TIMER0_RES_UPDATE_EN_V 0x00000001U #define LEDC_TASK_TIMER0_RES_UPDATE_EN_S 0 /** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer1_res_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER1_RES_UPDATE_EN (BIT(1)) #define LEDC_TASK_TIMER1_RES_UPDATE_EN_M (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S) #define LEDC_TASK_TIMER1_RES_UPDATE_EN_V 0x00000001U #define LEDC_TASK_TIMER1_RES_UPDATE_EN_S 1 /** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer2_res_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER2_RES_UPDATE_EN (BIT(2)) #define LEDC_TASK_TIMER2_RES_UPDATE_EN_M (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S) #define LEDC_TASK_TIMER2_RES_UPDATE_EN_V 0x00000001U #define LEDC_TASK_TIMER2_RES_UPDATE_EN_S 2 /** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer3_res_update task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER3_RES_UPDATE_EN (BIT(3)) #define LEDC_TASK_TIMER3_RES_UPDATE_EN_M (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S) #define LEDC_TASK_TIMER3_RES_UPDATE_EN_V 0x00000001U #define LEDC_TASK_TIMER3_RES_UPDATE_EN_S 3 /** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer0_cap task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER0_CAP_EN (BIT(4)) #define LEDC_TASK_TIMER0_CAP_EN_M (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S) #define LEDC_TASK_TIMER0_CAP_EN_V 0x00000001U #define LEDC_TASK_TIMER0_CAP_EN_S 4 /** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer1_cap task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER1_CAP_EN (BIT(5)) #define LEDC_TASK_TIMER1_CAP_EN_M (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S) #define LEDC_TASK_TIMER1_CAP_EN_V 0x00000001U #define LEDC_TASK_TIMER1_CAP_EN_S 5 /** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer2_cap task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER2_CAP_EN (BIT(6)) #define LEDC_TASK_TIMER2_CAP_EN_M (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S) #define LEDC_TASK_TIMER2_CAP_EN_V 0x00000001U #define LEDC_TASK_TIMER2_CAP_EN_S 6 /** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer3_cap task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER3_CAP_EN (BIT(7)) #define LEDC_TASK_TIMER3_CAP_EN_M (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S) #define LEDC_TASK_TIMER3_CAP_EN_V 0x00000001U #define LEDC_TASK_TIMER3_CAP_EN_S 7 /** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch0_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH0_EN (BIT(8)) #define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S 8 /** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch1_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH1_EN (BIT(9)) #define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S 9 /** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch2_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH2_EN (BIT(10)) #define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S 10 /** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch3_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH3_EN (BIT(11)) #define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S 11 /** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch4_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH4_EN (BIT(12)) #define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S 12 /** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch5_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH5_EN (BIT(13)) #define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S 13 /** LEDC_TASK_SIG_OUT_DIS_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch6_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH6_EN (BIT(14)) #define LEDC_TASK_SIG_OUT_DIS_CH6_EN_M (LEDC_TASK_SIG_OUT_DIS_CH6_EN_V << LEDC_TASK_SIG_OUT_DIS_CH6_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH6_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH6_EN_S 14 /** LEDC_TASK_SIG_OUT_DIS_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch7_sig_out_dis task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_SIG_OUT_DIS_CH7_EN (BIT(15)) #define LEDC_TASK_SIG_OUT_DIS_CH7_EN_M (LEDC_TASK_SIG_OUT_DIS_CH7_EN_V << LEDC_TASK_SIG_OUT_DIS_CH7_EN_S) #define LEDC_TASK_SIG_OUT_DIS_CH7_EN_V 0x00000001U #define LEDC_TASK_SIG_OUT_DIS_CH7_EN_S 15 /** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH0_EN (BIT(16)) #define LEDC_TASK_OVF_CNT_RST_CH0_EN_M (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH0_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH0_EN_S 16 /** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH1_EN (BIT(17)) #define LEDC_TASK_OVF_CNT_RST_CH1_EN_M (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH1_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH1_EN_S 17 /** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH2_EN (BIT(18)) #define LEDC_TASK_OVF_CNT_RST_CH2_EN_M (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH2_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH2_EN_S 18 /** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH3_EN (BIT(19)) #define LEDC_TASK_OVF_CNT_RST_CH3_EN_M (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH3_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH3_EN_S 19 /** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH4_EN (BIT(20)) #define LEDC_TASK_OVF_CNT_RST_CH4_EN_M (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH4_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH4_EN_S 20 /** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH5_EN (BIT(21)) #define LEDC_TASK_OVF_CNT_RST_CH5_EN_M (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH5_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH5_EN_S 21 /** LEDC_TASK_OVF_CNT_RST_CH6_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH6_EN (BIT(22)) #define LEDC_TASK_OVF_CNT_RST_CH6_EN_M (LEDC_TASK_OVF_CNT_RST_CH6_EN_V << LEDC_TASK_OVF_CNT_RST_CH6_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH6_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH6_EN_S 22 /** LEDC_TASK_OVF_CNT_RST_CH7_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_OVF_CNT_RST_CH7_EN (BIT(23)) #define LEDC_TASK_OVF_CNT_RST_CH7_EN_M (LEDC_TASK_OVF_CNT_RST_CH7_EN_V << LEDC_TASK_OVF_CNT_RST_CH7_EN_S) #define LEDC_TASK_OVF_CNT_RST_CH7_EN_V 0x00000001U #define LEDC_TASK_OVF_CNT_RST_CH7_EN_S 23 /** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer0_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER0_RST_EN (BIT(24)) #define LEDC_TASK_TIMER0_RST_EN_M (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S) #define LEDC_TASK_TIMER0_RST_EN_V 0x00000001U #define LEDC_TASK_TIMER0_RST_EN_S 24 /** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer1_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER1_RST_EN (BIT(25)) #define LEDC_TASK_TIMER1_RST_EN_M (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S) #define LEDC_TASK_TIMER1_RST_EN_V 0x00000001U #define LEDC_TASK_TIMER1_RST_EN_S 25 /** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer2_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER2_RST_EN (BIT(26)) #define LEDC_TASK_TIMER2_RST_EN_M (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S) #define LEDC_TASK_TIMER2_RST_EN_V 0x00000001U #define LEDC_TASK_TIMER2_RST_EN_S 26 /** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable + * Configures whether or not to enable ledc_timer3_rst task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER3_RST_EN (BIT(27)) #define LEDC_TASK_TIMER3_RST_EN_M (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S) #define LEDC_TASK_TIMER3_RST_EN_V 0x00000001U #define LEDC_TASK_TIMER3_RST_EN_S 27 /** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer0_pause_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER0_PAUSE_RESUME_EN (BIT(28)) #define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S) #define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V 0x00000001U #define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S 28 /** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer1_pause_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER1_PAUSE_RESUME_EN (BIT(29)) #define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S) #define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V 0x00000001U #define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S 29 /** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer2_pause_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER2_PAUSE_RESUME_EN (BIT(30)) #define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S) #define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V 0x00000001U #define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S 30 /** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_timer3_pause_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_TIMER3_PAUSE_RESUME_EN (BIT(31)) #define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S) @@ -2518,192 +2690,216 @@ extern "C" { */ #define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x128) /** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch0_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH0_EN (BIT(0)) #define LEDC_TASK_GAMMA_RESTART_CH0_EN_M (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH0_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH0_EN_S 0 /** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch1_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH1_EN (BIT(1)) #define LEDC_TASK_GAMMA_RESTART_CH1_EN_M (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH1_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH1_EN_S 1 /** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch2_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH2_EN (BIT(2)) #define LEDC_TASK_GAMMA_RESTART_CH2_EN_M (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH2_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH2_EN_S 2 /** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch3_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH3_EN (BIT(3)) #define LEDC_TASK_GAMMA_RESTART_CH3_EN_M (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH3_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH3_EN_S 3 /** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch4_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH4_EN (BIT(4)) #define LEDC_TASK_GAMMA_RESTART_CH4_EN_M (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH4_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH4_EN_S 4 /** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch5_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH5_EN (BIT(5)) #define LEDC_TASK_GAMMA_RESTART_CH5_EN_M (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH5_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH5_EN_S 5 /** LEDC_TASK_GAMMA_RESTART_CH6_EN : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch6_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH6_EN (BIT(6)) #define LEDC_TASK_GAMMA_RESTART_CH6_EN_M (LEDC_TASK_GAMMA_RESTART_CH6_EN_V << LEDC_TASK_GAMMA_RESTART_CH6_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH6_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH6_EN_S 6 /** LEDC_TASK_GAMMA_RESTART_CH7_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch7_gamma_restart task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESTART_CH7_EN (BIT(7)) #define LEDC_TASK_GAMMA_RESTART_CH7_EN_M (LEDC_TASK_GAMMA_RESTART_CH7_EN_V << LEDC_TASK_GAMMA_RESTART_CH7_EN_S) #define LEDC_TASK_GAMMA_RESTART_CH7_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESTART_CH7_EN_S 7 /** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch0_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH0_EN (BIT(8)) #define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S 8 /** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch1_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH1_EN (BIT(9)) #define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S 9 /** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch2_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH2_EN (BIT(10)) #define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S 10 /** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch3_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH3_EN (BIT(11)) #define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S 11 /** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch4_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH4_EN (BIT(12)) #define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S 12 /** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch5_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH5_EN (BIT(13)) #define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S 13 /** LEDC_TASK_GAMMA_PAUSE_CH6_EN : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch6_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH6_EN (BIT(14)) #define LEDC_TASK_GAMMA_PAUSE_CH6_EN_M (LEDC_TASK_GAMMA_PAUSE_CH6_EN_V << LEDC_TASK_GAMMA_PAUSE_CH6_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH6_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH6_EN_S 14 /** LEDC_TASK_GAMMA_PAUSE_CH7_EN : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch7_gamma_pause task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_PAUSE_CH7_EN (BIT(15)) #define LEDC_TASK_GAMMA_PAUSE_CH7_EN_M (LEDC_TASK_GAMMA_PAUSE_CH7_EN_V << LEDC_TASK_GAMMA_PAUSE_CH7_EN_S) #define LEDC_TASK_GAMMA_PAUSE_CH7_EN_V 0x00000001U #define LEDC_TASK_GAMMA_PAUSE_CH7_EN_S 15 /** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch0_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH0_EN (BIT(16)) #define LEDC_TASK_GAMMA_RESUME_CH0_EN_M (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH0_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH0_EN_S 16 /** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch1_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH1_EN (BIT(17)) #define LEDC_TASK_GAMMA_RESUME_CH1_EN_M (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH1_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH1_EN_S 17 /** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch2_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH2_EN (BIT(18)) #define LEDC_TASK_GAMMA_RESUME_CH2_EN_M (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH2_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH2_EN_S 18 /** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch3_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH3_EN (BIT(19)) #define LEDC_TASK_GAMMA_RESUME_CH3_EN_M (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH3_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH3_EN_S 19 /** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch4_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH4_EN (BIT(20)) #define LEDC_TASK_GAMMA_RESUME_CH4_EN_M (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH4_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH4_EN_S 20 /** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch5_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH5_EN (BIT(21)) #define LEDC_TASK_GAMMA_RESUME_CH5_EN_M (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH5_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH5_EN_S 21 /** LEDC_TASK_GAMMA_RESUME_CH6_EN : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch6_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH6_EN (BIT(22)) #define LEDC_TASK_GAMMA_RESUME_CH6_EN_M (LEDC_TASK_GAMMA_RESUME_CH6_EN_V << LEDC_TASK_GAMMA_RESUME_CH6_EN_S) #define LEDC_TASK_GAMMA_RESUME_CH6_EN_V 0x00000001U #define LEDC_TASK_GAMMA_RESUME_CH6_EN_S 22 /** LEDC_TASK_GAMMA_RESUME_CH7_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: Disable\\1: - * Enable + * Configures whether or not to enable ledc_ch7_gamma_resume task. + * 0: Disable + * 1: Enable */ #define LEDC_TASK_GAMMA_RESUME_CH7_EN (BIT(23)) #define LEDC_TASK_GAMMA_RESUME_CH7_EN_M (LEDC_TASK_GAMMA_RESUME_CH7_EN_V << LEDC_TASK_GAMMA_RESUME_CH7_EN_S) @@ -2811,88 +3007,92 @@ extern "C" { */ #define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x170) /** LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0; - * Configures the clock source for the four timers.\\0: APB_CLK\\1: RC_FAST_CLK\\2: - * XTAL_CLK\\3: Invalid. No clock + * Configures the clock source for the four timers. + * 0: APB_CLK + * 1: RC_FAST_CLK + * 2: XTAL_CLK + * 3: Invalid. No clock */ #define LEDC_APB_CLK_SEL 0x00000003U #define LEDC_APB_CLK_SEL_M (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S) #define LEDC_APB_CLK_SEL_V 0x00000003U #define LEDC_APB_CLK_SEL_S 0 /** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the - * clock gate for LEDC ch0 gamma ram + * Configures whether or not to open LEDC ch0 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram + * 1: Force open the clock gate for LEDC ch0 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH0 (BIT(2)) #define LEDC_GAMMA_RAM_CLK_EN_CH0_M (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S) #define LEDC_GAMMA_RAM_CLK_EN_CH0_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH0_S 2 /** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0; - * Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the - * clock gate for LEDC ch1 gamma ram + * Configures whether or not to open LEDC ch1 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram + * 1: Force open the clock gate for LEDC ch1 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH1 (BIT(3)) #define LEDC_GAMMA_RAM_CLK_EN_CH1_M (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S) #define LEDC_GAMMA_RAM_CLK_EN_CH1_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH1_S 3 /** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the - * clock gate for LEDC ch2 gamma ram + * Configures whether or not to open LEDC ch2 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram + * 1: Force open the clock gate for LEDC ch2 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH2 (BIT(4)) #define LEDC_GAMMA_RAM_CLK_EN_CH2_M (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S) #define LEDC_GAMMA_RAM_CLK_EN_CH2_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH2_S 4 /** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the - * clock gate for LEDC ch3 gamma ram + * Configures whether or not to open LEDC ch3 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram + * 1: Force open the clock gate for LEDC ch3 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH3 (BIT(5)) #define LEDC_GAMMA_RAM_CLK_EN_CH3_M (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S) #define LEDC_GAMMA_RAM_CLK_EN_CH3_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH3_S 5 /** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the - * clock gate for LEDC ch4 gamma ram + * Configures whether or not to open LEDC ch4 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram + * 1: Force open the clock gate for LEDC ch4 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH4 (BIT(6)) #define LEDC_GAMMA_RAM_CLK_EN_CH4_M (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S) #define LEDC_GAMMA_RAM_CLK_EN_CH4_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH4_S 6 /** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0; - * Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the - * clock gate for LEDC ch5 gamma ram + * Configures whether or not to open LEDC ch5 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram + * 1: Force open the clock gate for LEDC ch5 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH5 (BIT(7)) #define LEDC_GAMMA_RAM_CLK_EN_CH5_M (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S) #define LEDC_GAMMA_RAM_CLK_EN_CH5_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH5_S 7 /** LEDC_GAMMA_RAM_CLK_EN_CH6 : R/W; bitpos: [8]; default: 0; - * Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch6 gamma ram\\1: Force open the - * clock gate for LEDC ch6 gamma ram + * Configures whether or not to open LEDC ch6 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram + * 1: Force open the clock gate for LEDC ch6 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH6 (BIT(8)) #define LEDC_GAMMA_RAM_CLK_EN_CH6_M (LEDC_GAMMA_RAM_CLK_EN_CH6_V << LEDC_GAMMA_RAM_CLK_EN_CH6_S) #define LEDC_GAMMA_RAM_CLK_EN_CH6_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH6_S 8 /** LEDC_GAMMA_RAM_CLK_EN_CH7 : R/W; bitpos: [9]; default: 0; - * Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch7 gamma ram\\1: Force open the - * clock gate for LEDC ch7 gamma ram + * Configures whether or not to open LEDC ch7 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram + * 1: Force open the clock gate for LEDC ch7 gamma ram */ #define LEDC_GAMMA_RAM_CLK_EN_CH7 (BIT(9)) #define LEDC_GAMMA_RAM_CLK_EN_CH7_M (LEDC_GAMMA_RAM_CLK_EN_CH7_V << LEDC_GAMMA_RAM_CLK_EN_CH7_S) #define LEDC_GAMMA_RAM_CLK_EN_CH7_V 0x00000001U #define LEDC_GAMMA_RAM_CLK_EN_CH7_S 9 /** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; - * Configures whether or not to open register clock gate.\\0: Open the clock gate only - * when application writes registers\\1: Force open the clock gate for register + * Configures whether or not to open register clock gate. + * 0: Open the clock gate only when application writes registers + * 1: Force open the clock gate for register */ #define LEDC_CLK_EN (BIT(31)) #define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h index 23029726e817..668767aa6852 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h @@ -10,32 +10,40 @@ extern "C" { #endif -/** Group: conf0 */ +/** Group: Configuration Register */ /** Type of chn_conf0 register * Configuration register 0 for channel n */ typedef union { struct { /** timer_sel : R/W; bitpos: [1:0]; default: 0; - * Configures which timer is channel n selected.\\0: Select timer0\\1: Select - * timer1\\2: Select timer2\\3: Select timer3 + * Configures which timer is channel n selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 */ uint32_t timer_sel:2; /** sig_out_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable signal output on channel n.\\0: Signal output - * disable\\1: Signal output enable + * Configures whether or not to enable signal output on channel n. + * 0: Signal output disable + * 1: Signal output enable */ uint32_t sig_out_en:1; /** idle_lv : R/W; bitpos: [3]; default: 0; * Configures the output value when channel n is inactive. Valid only when - * LEDC_SIG_OUT_EN_CHn is 0.\\0: Output level is low\\1: Output level is high + * LEDC_SIG_OUT_EN_CHn is 0. + * 0: Output level is low + * 1: Output level is high */ uint32_t idle_lv:1; /** para_up : WT; bitpos: [4]; default: 0; * Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn, * LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel - * n, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + * n, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update */ uint32_t para_up:1; /** ovf_num : R/W; bitpos: [14:5]; default: 0; @@ -44,12 +52,15 @@ typedef union { */ uint32_t ovf_num:10; /** ovf_cnt_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ovf_cnt of channel n.\\0: Disable\\1: Enable + * Configures whether or not to enable the ovf_cnt of channel n. + * 0: Disable + * 1: Enable */ uint32_t ovf_cnt_en:1; /** ovf_cnt_reset : WT; bitpos: [16]; default: 0; - * Configures whether or not to reset the ovf_cnt of channel n.\\0: Invalid. No - * effect\\1: Reset the ovf_cnt + * Configures whether or not to reset the ovf_cnt of channel n. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt */ uint32_t ovf_cnt_reset:1; uint32_t reserved_17:15; @@ -93,30 +104,30 @@ typedef union { struct { uint32_t reserved_0:31; /** duty_start : R/W/SC; bitpos: [31]; default: 0; - * Configures whether the duty cycle fading configurations take effect.\\0: Not take - * effect\\1: Take effect + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect */ uint32_t duty_start:1; }; uint32_t val; } ledc_chn_conf1_reg_t; +/** Group: Status Register */ /** Type of chn_duty_r register * Current duty cycle register for channel n */ typedef union { struct { - /** duty_ch0_r : RO; bitpos: [24:0]; default: 0; + /** duty_r : RO; bitpos: [24:0]; default: 0; * Represents the current duty of output signal on channel n. */ - uint32_t duty:25; + uint32_t duty_r:25; uint32_t reserved_25:7; }; uint32_t val; } ledc_chn_duty_r_reg_t; - -/** Group: conf1 */ /** Type of timern_conf register * Timer n configuration register */ @@ -132,21 +143,22 @@ typedef union { */ uint32_t clk_div:18; /** pause : R/W; bitpos: [23]; default: 0; - * Configures whether or not to pause the counter in timer n.\\0: Normal\\1: Pause + * Configures whether or not to pause the counter in timer n. + * 0: Normal + * 1: Pause */ uint32_t pause:1; /** rst : R/W; bitpos: [24]; default: 1; - * Configures whether or not to reset timer n. The counter will show 0 after - * reset.\\0: Not reset\\1: Reset + * Configures whether or not to reset timer n. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset */ uint32_t rst:1; - /** tick_sel : R/W; bitpos: [25]; default: 0; - * Configures which clock is timer n selected. Unused. - */ - uint32_t tick_sel:1; + uint32_t reserved_25:1; /** para_up : WT; bitpos: [26]; default: 0; - * Configures whether or not to update LEDC_CLK_DIV_TIMERn and - * LEDC_TIMERn_DUTY_RES.\\0: Invalid. No effect\\1: Update + * Configures whether or not to update LEDC_CLK_DIV_TIMERn and LEDC_TIMERn_DUTY_RES. + * 0: Invalid. No effect + * 1: Update */ uint32_t para_up:1; uint32_t reserved_27:5; @@ -168,1001 +180,1089 @@ typedef union { uint32_t val; } ledc_timern_value_reg_t; - -/** Group: Interrupt Register */ -/** Type of int_raw register - * Interrupt raw status register +/** Type of conf register + * LEDC global configuration register */ typedef union { struct { - /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the - * timer0 has reached its maximum counter value. - */ - uint32_t timer0_ovf_int_raw:1; - /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the - * timer1 has reached its maximum counter value. - */ - uint32_t timer1_ovf_int_raw:1; - /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the - * timer2 has reached its maximum counter value. - */ - uint32_t timer2_ovf_int_raw:1; - /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the - * timer3 has reached its maximum counter value. - */ - uint32_t timer3_ovf_int_raw:1; - /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch0_int_raw:1; - /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch1_int_raw:1; - /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered - * when the fading of duty has finished. - */ - uint32_t duty_chng_end_ch2_int_raw:1; - /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered - * when the fading of duty has finished. + /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0; + * Configures the clock source for the four timers. + * 0: APB_CLK + * 1: RC_FAST_CLK + * 2: XTAL_CLK + * 3: Invalid. No clock */ - uint32_t duty_chng_end_ch3_int_raw:1; - /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered - * when the fading of duty has finished. + uint32_t apb_clk_sel:2; + /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to open LEDC ch0 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram + * 1: Force open the clock gate for LEDC ch0 gamma ram */ - uint32_t duty_chng_end_ch4_int_raw:1; - /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered - * when the fading of duty has finished. + uint32_t gamma_ram_clk_en_ch0:1; + /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; + * Configures whether or not to open LEDC ch1 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram + * 1: Force open the clock gate for LEDC ch1 gamma ram */ - uint32_t duty_chng_end_ch5_int_raw:1; - /** duty_chng_end_ch6_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered - * when the fading of duty has finished. + uint32_t gamma_ram_clk_en_ch1:1; + /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to open LEDC ch2 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram + * 1: Force open the clock gate for LEDC ch2 gamma ram */ - uint32_t duty_chng_end_ch6_int_raw:1; - /** duty_chng_end_ch7_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered - * when the fading of duty has finished. + uint32_t gamma_ram_clk_en_ch2:1; + /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; + * Configures whether or not to open LEDC ch3 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram + * 1: Force open the clock gate for LEDC ch3 gamma ram */ - uint32_t duty_chng_end_ch7_int_raw:1; - /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + uint32_t gamma_ram_clk_en_ch3:1; + /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to open LEDC ch4 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram + * 1: Force open the clock gate for LEDC ch4 gamma ram */ - uint32_t ovf_cnt_ch0_int_raw:1; - /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + uint32_t gamma_ram_clk_en_ch4:1; + /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; + * Configures whether or not to open LEDC ch5 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram + * 1: Force open the clock gate for LEDC ch5 gamma ram */ - uint32_t ovf_cnt_ch1_int_raw:1; - /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + uint32_t gamma_ram_clk_en_ch5:1; + /** gamma_ram_clk_en_ch6 : R/W; bitpos: [8]; default: 0; + * Configures whether or not to open LEDC ch6 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram + * 1: Force open the clock gate for LEDC ch6 gamma ram */ - uint32_t ovf_cnt_ch2_int_raw:1; - /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + uint32_t gamma_ram_clk_en_ch6:1; + /** gamma_ram_clk_en_ch7 : R/W; bitpos: [9]; default: 0; + * Configures whether or not to open LEDC ch7 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram + * 1: Force open the clock gate for LEDC ch7 gamma ram */ - uint32_t ovf_cnt_ch3_int_raw:1; - /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + uint32_t gamma_ram_clk_en_ch7:1; + uint32_t reserved_10:21; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to open register clock gate. + * 0: Open the clock gate only when application writes registers + * 1: Force open the clock gate for register */ - uint32_t ovf_cnt_ch4_int_raw:1; - /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + uint32_t clk_en:1; + }; + uint32_t val; +} ledc_conf_reg_t; + +/** Type of chn_gamma_conf register + * Ledc chn gamma config register. + */ +typedef union { + struct { + /** gamma_entry_num : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC chn. */ - uint32_t ovf_cnt_ch5_int_raw:1; - /** ovf_cnt_ch6_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. + uint32_t gamma_entry_num:5; + /** gamma_pause : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC chn. + * 0: Invalid. No effect + * 1: Pause */ - uint32_t ovf_cnt_ch6_int_raw:1; - /** ovf_cnt_ch7_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when - * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. + uint32_t gamma_pause:1; + /** gamma_resume : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC chn. + * 0: Invalid. No effect + * 1: Resume */ - uint32_t ovf_cnt_ch7_int_raw:1; - uint32_t reserved_20:12; + uint32_t gamma_resume:1; + uint32_t reserved_7:25; }; uint32_t val; -} ledc_int_raw_reg_t; +} ledc_chn_gamma_conf_reg_t; -/** Type of int_st register - * Interrupt masked status register +/** Type of evt_task_en0 register + * Ledc event task enable bit register0. */ typedef union { struct { - /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only - * when LEDC_TIMER0_OVF_INT_ENA is set to 1. + /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_chng_end event. + * 0: Disable + * 1: Enable */ - uint32_t timer0_ovf_int_st:1; - /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only - * when LEDC_TIMER1_OVF_INT_ENA is set to 1. + uint32_t evt_duty_chng_end_ch0_en:1; + /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_chng_end event. + * 0: Disable + * 1: Enable */ - uint32_t timer1_ovf_int_st:1; - /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only - * when LEDC_TIMER2_OVF_INT_ENA is set to 1. + uint32_t evt_duty_chng_end_ch1_en:1; + /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_chng_end event. + * 0: Disable + * 1: Enable */ - uint32_t timer2_ovf_int_st:1; - /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only - * when LEDC_TIMER3_OVF_INT_ENA is set to 1. + uint32_t evt_duty_chng_end_ch2_en:1; + /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_chng_end event. + * 0: Disable + * 1: Enable */ - uint32_t timer3_ovf_int_st:1; - /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + uint32_t evt_duty_chng_end_ch3_en:1; + /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_chng_end event. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch0_int_st:1; - /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + uint32_t evt_duty_chng_end_ch4_en:1; + /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_chng_end event. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch1_int_st:1; - /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + uint32_t evt_duty_chng_end_ch5_en:1; + /** evt_duty_chng_end_ch6_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable the ledc_ch6_duty_chng_end event. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch2_int_st:1; - /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + uint32_t evt_duty_chng_end_ch6_en:1; + /** evt_duty_chng_end_ch7_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable the ledc_ch7_duty_chng_end event. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch3_int_st:1; - /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + uint32_t evt_duty_chng_end_ch7_en:1; + /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch4_int_st:1; - /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + uint32_t evt_ovf_cnt_pls_ch0_en:1; + /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch5_int_st:1; - /** duty_chng_end_ch6_int_st : RO; bitpos: [10]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. + uint32_t evt_ovf_cnt_pls_ch1_en:1; + /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch6_int_st:1; - /** duty_chng_end_ch7_int_st : RO; bitpos: [11]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid - * only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. + uint32_t evt_ovf_cnt_pls_ch2_en:1; + /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch7_int_st:1; - /** ovf_cnt_ch0_int_st : RO; bitpos: [12]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only - * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + uint32_t evt_ovf_cnt_pls_ch3_en:1; + /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch0_int_st:1; - /** ovf_cnt_ch1_int_st : RO; bitpos: [13]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only - * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + uint32_t evt_ovf_cnt_pls_ch4_en:1; + /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch1_int_st:1; - /** ovf_cnt_ch2_int_st : RO; bitpos: [14]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only - * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + uint32_t evt_ovf_cnt_pls_ch5_en:1; + /** evt_ovf_cnt_pls_ch6_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch2_int_st:1; - /** ovf_cnt_ch3_int_st : RO; bitpos: [15]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only - * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + uint32_t evt_ovf_cnt_pls_ch6_en:1; + /** evt_ovf_cnt_pls_ch7_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch3_int_st:1; - /** ovf_cnt_ch4_int_st : RO; bitpos: [16]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only - * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + uint32_t evt_ovf_cnt_pls_ch7_en:1; + /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the ledc_timer0_ovf event. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch4_int_st:1; - /** ovf_cnt_ch5_int_st : RO; bitpos: [17]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only - * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + uint32_t evt_time_ovf_timer0_en:1; + /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable the ledc_timer1_ovf event. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch5_int_st:1; - /** ovf_cnt_ch6_int_st : RO; bitpos: [18]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only - * when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + uint32_t evt_time_ovf_timer1_en:1; + /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable the ledc_timer2_ovf event. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch6_int_st:1; - /** ovf_cnt_ch7_int_st : RO; bitpos: [19]; default: 0; - * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only - * when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + uint32_t evt_time_ovf_timer2_en:1; + /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable the ledc_timer3_ovf event. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch7_int_st:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_int_st_reg_t; - -/** Type of int_ena register - * Interrupt enable register - */ -typedef union { - struct { - /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. + uint32_t evt_time_ovf_timer3_en:1; + /** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the ledc_timer0_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time0_cmp_en:1; + /** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the ledc_timer1_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time1_cmp_en:1; + /** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the ledc_timer2_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time2_cmp_en:1; + /** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the ledc_timer3_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time3_cmp_en:1; + /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_scale_update task. + * 0: Disable + * 1: Enable */ - uint32_t timer0_ovf_int_ena:1; - /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. + uint32_t task_duty_scale_update_ch0_en:1; + /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_scale_update task. + * 0: Disable + * 1: Enable */ - uint32_t timer1_ovf_int_ena:1; - /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. + uint32_t task_duty_scale_update_ch1_en:1; + /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_scale_update task. + * 0: Disable + * 1: Enable */ - uint32_t timer2_ovf_int_ena:1; - /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0; - * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. + uint32_t task_duty_scale_update_ch2_en:1; + /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_scale_update task. + * 0: Disable + * 1: Enable */ - uint32_t timer3_ovf_int_ena:1; - /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. + uint32_t task_duty_scale_update_ch3_en:1; + /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_scale_update task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch0_int_ena:1; - /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. + uint32_t task_duty_scale_update_ch4_en:1; + /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_scale_update task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch1_int_ena:1; - /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. + uint32_t task_duty_scale_update_ch5_en:1; + /** task_duty_scale_update_ch6_en : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable the ledc_ch6_duty_scale_update task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch2_int_ena:1; - /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. + uint32_t task_duty_scale_update_ch6_en:1; + /** task_duty_scale_update_ch7_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable the ledc_ch7_duty_scale_update task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch3_int_ena:1; - /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. + uint32_t task_duty_scale_update_ch7_en:1; + }; + uint32_t val; +} ledc_evt_task_en0_reg_t; + +/** Type of evt_task_en1 register + * Ledc event task enable bit register1. + */ +typedef union { + struct { + /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_timer0_res_update task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch4_int_ena:1; - /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. + uint32_t task_timer0_res_update_en:1; + /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_timer1_res_update task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch5_int_ena:1; - /** duty_chng_end_ch6_int_ena : R/W; bitpos: [10]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. + uint32_t task_timer1_res_update_en:1; + /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_timer2_res_update task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch6_int_ena:1; - /** duty_chng_end_ch7_int_ena : R/W; bitpos: [11]; default: 0; - * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. + uint32_t task_timer2_res_update_en:1; + /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_timer3_res_update task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch7_int_ena:1; - /** ovf_cnt_ch0_int_ena : R/W; bitpos: [12]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. + uint32_t task_timer3_res_update_en:1; + /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_timer0_cap task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch0_int_ena:1; - /** ovf_cnt_ch1_int_ena : R/W; bitpos: [13]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. + uint32_t task_timer0_cap_en:1; + /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_timer1_cap task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch1_int_ena:1; - /** ovf_cnt_ch2_int_ena : R/W; bitpos: [14]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. + uint32_t task_timer1_cap_en:1; + /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_timer2_cap task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch2_int_ena:1; - /** ovf_cnt_ch3_int_ena : R/W; bitpos: [15]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. + uint32_t task_timer2_cap_en:1; + /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_timer3_cap task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch3_int_ena:1; - /** ovf_cnt_ch4_int_ena : R/W; bitpos: [16]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. + uint32_t task_timer3_cap_en:1; + /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_sig_out_dis task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch4_int_ena:1; - /** ovf_cnt_ch5_int_ena : R/W; bitpos: [17]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. + uint32_t task_sig_out_dis_ch0_en:1; + /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_sig_out_dis task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch5_int_ena:1; - /** ovf_cnt_ch6_int_ena : R/W; bitpos: [18]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. + uint32_t task_sig_out_dis_ch1_en:1; + /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_sig_out_dis task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch6_int_ena:1; - /** ovf_cnt_ch7_int_ena : R/W; bitpos: [19]; default: 0; - * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. + uint32_t task_sig_out_dis_ch2_en:1; + /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_sig_out_dis task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch7_int_ena:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_int_ena_reg_t; - -/** Type of int_clr register - * Interrupt clear register - */ -typedef union { - struct { - /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. + uint32_t task_sig_out_dis_ch3_en:1; + /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_sig_out_dis task. + * 0: Disable + * 1: Enable */ - uint32_t timer0_ovf_int_clr:1; - /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. + uint32_t task_sig_out_dis_ch4_en:1; + /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_sig_out_dis task. + * 0: Disable + * 1: Enable */ - uint32_t timer1_ovf_int_clr:1; - /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. + uint32_t task_sig_out_dis_ch5_en:1; + /** task_sig_out_dis_ch6_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable ledc_ch6_sig_out_dis task. + * 0: Disable + * 1: Enable */ - uint32_t timer2_ovf_int_clr:1; - /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0; - * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. + uint32_t task_sig_out_dis_ch6_en:1; + /** task_sig_out_dis_ch7_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable ledc_ch7_sig_out_dis task. + * 0: Disable + * 1: Enable */ - uint32_t timer3_ovf_int_clr:1; - /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. + uint32_t task_sig_out_dis_ch7_en:1; + /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch0_int_clr:1; - /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. + uint32_t task_ovf_cnt_rst_ch0_en:1; + /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch1_int_clr:1; - /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. + uint32_t task_ovf_cnt_rst_ch1_en:1; + /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch2_int_clr:1; - /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. + uint32_t task_ovf_cnt_rst_ch2_en:1; + /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch3_int_clr:1; - /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. + uint32_t task_ovf_cnt_rst_ch3_en:1; + /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch4_int_clr:1; - /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. + uint32_t task_ovf_cnt_rst_ch4_en:1; + /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch5_int_clr:1; - /** duty_chng_end_ch6_int_clr : WT; bitpos: [10]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. + uint32_t task_ovf_cnt_rst_ch5_en:1; + /** task_ovf_cnt_rst_ch6_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch6_int_clr:1; - /** duty_chng_end_ch7_int_clr : WT; bitpos: [11]; default: 0; - * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. + uint32_t task_ovf_cnt_rst_ch6_en:1; + /** task_ovf_cnt_rst_ch7_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task. + * 0: Disable + * 1: Enable */ - uint32_t duty_chng_end_ch7_int_clr:1; - /** ovf_cnt_ch0_int_clr : WT; bitpos: [12]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. + uint32_t task_ovf_cnt_rst_ch7_en:1; + /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable ledc_timer0_rst task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch0_int_clr:1; - /** ovf_cnt_ch1_int_clr : WT; bitpos: [13]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. + uint32_t task_timer0_rst_en:1; + /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable ledc_timer1_rst task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch1_int_clr:1; - /** ovf_cnt_ch2_int_clr : WT; bitpos: [14]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. + uint32_t task_timer1_rst_en:1; + /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable ledc_timer2_rst task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch2_int_clr:1; - /** ovf_cnt_ch3_int_clr : WT; bitpos: [15]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. + uint32_t task_timer2_rst_en:1; + /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable ledc_timer3_rst task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch3_int_clr:1; - /** ovf_cnt_ch4_int_clr : WT; bitpos: [16]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. + uint32_t task_timer3_rst_en:1; + /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable ledc_timer0_pause_resume task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch4_int_clr:1; - /** ovf_cnt_ch5_int_clr : WT; bitpos: [17]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. + uint32_t task_timer0_pause_resume_en:1; + /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable ledc_timer1_pause_resume task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch5_int_clr:1; - /** ovf_cnt_ch6_int_clr : WT; bitpos: [18]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. + uint32_t task_timer1_pause_resume_en:1; + /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable ledc_timer2_pause_resume task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch6_int_clr:1; - /** ovf_cnt_ch7_int_clr : WT; bitpos: [19]; default: 0; - * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. + uint32_t task_timer2_pause_resume_en:1; + /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable ledc_timer3_pause_resume task. + * 0: Disable + * 1: Enable */ - uint32_t ovf_cnt_ch7_int_clr:1; - uint32_t reserved_20:12; + uint32_t task_timer3_pause_resume_en:1; }; uint32_t val; -} ledc_int_clr_reg_t; - +} ledc_evt_task_en1_reg_t; -/** Group: gamma */ -/** Type of chn_gamma_conf register - * Ledc chn gamma config register. +/** Type of evt_task_en2 register + * Ledc event task enable bit register2. */ typedef union { struct { - /** ch0_gamma_entry_num : R/W; bitpos: [4:0]; default: 0; - * Configures the number of duty cycle fading rages for LEDC chn. - */ - uint32_t ch0_gamma_entry_num:5; - /** ch0_gamma_pause : WT; bitpos: [5]; default: 0; - * Configures whether or not to pause duty cycle fading of LEDC chn.\\0: Invalid. No - * effect\\1: Pause + /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_restart task. + * 0: Disable + * 1: Enable */ - uint32_t ch0_gamma_pause:1; - /** ch0_gamma_resume : WT; bitpos: [6]; default: 0; - * Configures whether or nor to resume duty cycle fading of LEDC chn.\\0: Invalid. No - * effect\\1: Resume + uint32_t task_gamma_restart_ch0_en:1; + /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_restart task. + * 0: Disable + * 1: Enable */ - uint32_t ch0_gamma_resume:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ledc_chn_gamma_conf_reg_t; - - -/** Group: en0 */ -/** Type of evt_task_en0 register - * Ledc event task enable bit register0. - */ -typedef union { - struct { - /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: - * Disable\\1: Enable + uint32_t task_gamma_restart_ch1_en:1; + /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_restart task. + * 0: Disable + * 1: Enable */ - uint32_t evt_duty_chng_end_ch0_en:1; - /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch1_en:1; - /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch2_en:1; - /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch3_en:1; - /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: - * Disable\\1: Enable - */ - uint32_t evt_duty_chng_end_ch4_en:1; - /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: - * Disable\\1: Enable + uint32_t task_gamma_restart_ch2_en:1; + /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_restart task. + * 0: Disable + * 1: Enable */ - uint32_t evt_duty_chng_end_ch5_en:1; - /** evt_duty_chng_end_ch6_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\0: - * Disable\\1: Enable + uint32_t task_gamma_restart_ch3_en:1; + /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_restart task. + * 0: Disable + * 1: Enable */ - uint32_t evt_duty_chng_end_ch6_en:1; - /** evt_duty_chng_end_ch7_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\0: - * Disable\\1: Enable + uint32_t task_gamma_restart_ch4_en:1; + /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_restart task. + * 0: Disable + * 1: Enable */ - uint32_t evt_duty_chng_end_ch7_en:1; - /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + uint32_t task_gamma_restart_ch5_en:1; + /** task_gamma_restart_ch6_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_restart task. + * 0: Disable + * 1: Enable */ - uint32_t evt_ovf_cnt_pls_ch0_en:1; - /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + uint32_t task_gamma_restart_ch6_en:1; + /** task_gamma_restart_ch7_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_restart task. + * 0: Disable + * 1: Enable */ - uint32_t evt_ovf_cnt_pls_ch1_en:1; - /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + uint32_t task_gamma_restart_ch7_en:1; + /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_pause task. + * 0: Disable + * 1: Enable */ - uint32_t evt_ovf_cnt_pls_ch2_en:1; - /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + uint32_t task_gamma_pause_ch0_en:1; + /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_pause task. + * 0: Disable + * 1: Enable */ - uint32_t evt_ovf_cnt_pls_ch3_en:1; - /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + uint32_t task_gamma_pause_ch1_en:1; + /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_pause task. + * 0: Disable + * 1: Enable */ - uint32_t evt_ovf_cnt_pls_ch4_en:1; - /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + uint32_t task_gamma_pause_ch2_en:1; + /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_pause task. + * 0: Disable + * 1: Enable */ - uint32_t evt_ovf_cnt_pls_ch5_en:1; - /** evt_ovf_cnt_pls_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + uint32_t task_gamma_pause_ch3_en:1; + /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_pause task. + * 0: Disable + * 1: Enable */ - uint32_t evt_ovf_cnt_pls_ch6_en:1; - /** evt_ovf_cnt_pls_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\0: Disable\\1: - * Enable + uint32_t task_gamma_pause_ch4_en:1; + /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_pause task. + * 0: Disable + * 1: Enable */ - uint32_t evt_ovf_cnt_pls_ch7_en:1; - /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: - * Enable + uint32_t task_gamma_pause_ch5_en:1; + /** task_gamma_pause_ch6_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_pause task. + * 0: Disable + * 1: Enable */ - uint32_t evt_time_ovf_timer0_en:1; - /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: - * Enable + uint32_t task_gamma_pause_ch6_en:1; + /** task_gamma_pause_ch7_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_pause task. + * 0: Disable + * 1: Enable */ - uint32_t evt_time_ovf_timer1_en:1; - /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: - * Enable + uint32_t task_gamma_pause_ch7_en:1; + /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_resume task. + * 0: Disable + * 1: Enable */ - uint32_t evt_time_ovf_timer2_en:1; - /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: - * Enable + uint32_t task_gamma_resume_ch0_en:1; + /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_resume task. + * 0: Disable + * 1: Enable */ - uint32_t evt_time_ovf_timer3_en:1; - /** evt_timer0_cmp_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_timer0_cmp_en:1; - /** evt_timer1_cmp_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_timer1_cmp_en:1; - /** evt_timer2_cmp_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_timer2_cmp_en:1; - /** evt_timer3_cmp_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: - * Enable - */ - uint32_t evt_timer3_cmp_en:1; - /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: - * Disable\\1: Enable + uint32_t task_gamma_resume_ch1_en:1; + /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_resume task. + * 0: Disable + * 1: Enable */ - uint32_t task_duty_scale_update_ch0_en:1; - /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: - * Disable\\1: Enable + uint32_t task_gamma_resume_ch2_en:1; + /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_resume task. + * 0: Disable + * 1: Enable */ - uint32_t task_duty_scale_update_ch1_en:1; - /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: - * Disable\\1: Enable + uint32_t task_gamma_resume_ch3_en:1; + /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_resume task. + * 0: Disable + * 1: Enable */ - uint32_t task_duty_scale_update_ch2_en:1; - /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: - * Disable\\1: Enable + uint32_t task_gamma_resume_ch4_en:1; + /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_resume task. + * 0: Disable + * 1: Enable */ - uint32_t task_duty_scale_update_ch3_en:1; - /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: - * Disable\\1: Enable + uint32_t task_gamma_resume_ch5_en:1; + /** task_gamma_resume_ch6_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_resume task. + * 0: Disable + * 1: Enable */ - uint32_t task_duty_scale_update_ch4_en:1; - /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: - * Disable\\1: Enable + uint32_t task_gamma_resume_ch6_en:1; + /** task_gamma_resume_ch7_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_resume task. + * 0: Disable + * 1: Enable */ - uint32_t task_duty_scale_update_ch5_en:1; - /** task_duty_scale_update_ch6_en : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\0: - * Disable\\1: Enable + uint32_t task_gamma_resume_ch7_en:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} ledc_evt_task_en2_reg_t; + +/** Type of timern_cmp register + * Ledc timern compare value register. + */ +typedef union { + struct { + /** timer_cmp : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timern. */ - uint32_t task_duty_scale_update_ch6_en:1; - /** task_duty_scale_update_ch7_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\0: - * Disable\\1: Enable + uint32_t timer_cmp:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cmp_reg_t; + +/** Type of timern_cnt_cap register + * Ledc timern captured count value register. + */ +typedef union { + struct { + /** timer_cnt_cap : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timern count value. */ - uint32_t task_duty_scale_update_ch7_en:1; + uint32_t timer_cnt_cap:20; + uint32_t reserved_20:12; }; uint32_t val; -} ledc_evt_task_en0_reg_t; +} ledc_timern_cnt_cap_reg_t; -/** Group: en1 */ -/** Type of evt_task_en1 register - * Ledc event task enable bit register1. +/** Group: Interrupt Register */ +/** Type of int_raw register + * Interrupt raw status register */ typedef union { struct { - /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: - * Enable + /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the + * timer0 has reached its maximum counter value. */ - uint32_t task_timer0_res_update_en:1; - /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: - * Enable + uint32_t timer0_ovf_int_raw:1; + /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the + * timer1 has reached its maximum counter value. */ - uint32_t task_timer1_res_update_en:1; - /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: - * Enable + uint32_t timer1_ovf_int_raw:1; + /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the + * timer2 has reached its maximum counter value. */ - uint32_t task_timer2_res_update_en:1; - /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: - * Enable + uint32_t timer2_ovf_int_raw:1; + /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the + * timer3 has reached its maximum counter value. */ - uint32_t task_timer3_res_update_en:1; - /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable + uint32_t timer3_ovf_int_raw:1; + /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered + * when the fading of duty has finished. */ - uint32_t task_timer0_cap_en:1; - /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable + uint32_t duty_chng_end_ch0_int_raw:1; + /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered + * when the fading of duty has finished. */ - uint32_t task_timer1_cap_en:1; - /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable + uint32_t duty_chng_end_ch1_int_raw:1; + /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered + * when the fading of duty has finished. */ - uint32_t task_timer2_cap_en:1; - /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable + uint32_t duty_chng_end_ch2_int_raw:1; + /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered + * when the fading of duty has finished. */ - uint32_t task_timer3_cap_en:1; - /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch3_int_raw:1; + /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered + * when the fading of duty has finished. */ - uint32_t task_sig_out_dis_ch0_en:1; - /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch4_int_raw:1; + /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered + * when the fading of duty has finished. */ - uint32_t task_sig_out_dis_ch1_en:1; - /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch5_int_raw:1; + /** duty_chng_end_ch6_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered + * when the fading of duty has finished. */ - uint32_t task_sig_out_dis_ch2_en:1; - /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch6_int_raw:1; + /** duty_chng_end_ch7_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered + * when the fading of duty has finished. */ - uint32_t task_sig_out_dis_ch3_en:1; - /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch7_int_raw:1; + /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. */ - uint32_t task_sig_out_dis_ch4_en:1; - /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: - * Enable + uint32_t ovf_cnt_ch0_int_raw:1; + /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. */ - uint32_t task_sig_out_dis_ch5_en:1; - /** task_sig_out_dis_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: Disable\\1: - * Enable + uint32_t ovf_cnt_ch1_int_raw:1; + /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. */ - uint32_t task_sig_out_dis_ch6_en:1; - /** task_sig_out_dis_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: Disable\\1: - * Enable + uint32_t ovf_cnt_ch2_int_raw:1; + /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. */ - uint32_t task_sig_out_dis_ch7_en:1; - /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + uint32_t ovf_cnt_ch3_int_raw:1; + /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. */ - uint32_t task_ovf_cnt_rst_ch0_en:1; - /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + uint32_t ovf_cnt_ch4_int_raw:1; + /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. */ - uint32_t task_ovf_cnt_rst_ch1_en:1; - /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + uint32_t ovf_cnt_ch5_int_raw:1; + /** ovf_cnt_ch6_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. */ - uint32_t task_ovf_cnt_rst_ch2_en:1; - /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + uint32_t ovf_cnt_ch6_int_raw:1; + /** ovf_cnt_ch7_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. */ - uint32_t task_ovf_cnt_rst_ch3_en:1; - /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + uint32_t ovf_cnt_ch7_int_raw:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_int_raw_reg_t; + +/** Type of int_st register + * Interrupt masked status register + */ +typedef union { + struct { + /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only + * when LEDC_TIMER0_OVF_INT_ENA is set to 1. */ - uint32_t task_ovf_cnt_rst_ch4_en:1; - /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + uint32_t timer0_ovf_int_st:1; + /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only + * when LEDC_TIMER1_OVF_INT_ENA is set to 1. */ - uint32_t task_ovf_cnt_rst_ch5_en:1; - /** task_ovf_cnt_rst_ch6_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + uint32_t timer1_ovf_int_st:1; + /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only + * when LEDC_TIMER2_OVF_INT_ENA is set to 1. */ - uint32_t task_ovf_cnt_rst_ch6_en:1; - /** task_ovf_cnt_rst_ch7_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: Disable\\1: - * Enable + uint32_t timer2_ovf_int_st:1; + /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only + * when LEDC_TIMER3_OVF_INT_ENA is set to 1. */ - uint32_t task_ovf_cnt_rst_ch7_en:1; - /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable + uint32_t timer3_ovf_int_st:1; + /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. */ - uint32_t task_timer0_rst_en:1; - /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable + uint32_t duty_chng_end_ch0_int_st:1; + /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. */ - uint32_t task_timer1_rst_en:1; - /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable + uint32_t duty_chng_end_ch1_int_st:1; + /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. */ - uint32_t task_timer2_rst_en:1; - /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable + uint32_t duty_chng_end_ch2_int_st:1; + /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. */ - uint32_t task_timer3_rst_en:1; - /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch3_int_st:1; + /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. */ - uint32_t task_timer0_pause_resume_en:1; - /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch4_int_st:1; + /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. */ - uint32_t task_timer1_pause_resume_en:1; - /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch5_int_st:1; + /** duty_chng_end_ch6_int_st : RO; bitpos: [10]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. */ - uint32_t task_timer2_pause_resume_en:1; - /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch6_int_st:1; + /** duty_chng_end_ch7_int_st : RO; bitpos: [11]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch7_int_st:1; + /** ovf_cnt_ch0_int_st : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only + * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch0_int_st:1; + /** ovf_cnt_ch1_int_st : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only + * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch1_int_st:1; + /** ovf_cnt_ch2_int_st : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only + * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch2_int_st:1; + /** ovf_cnt_ch3_int_st : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only + * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch3_int_st:1; + /** ovf_cnt_ch4_int_st : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only + * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch4_int_st:1; + /** ovf_cnt_ch5_int_st : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only + * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch5_int_st:1; + /** ovf_cnt_ch6_int_st : RO; bitpos: [18]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only + * when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch6_int_st:1; + /** ovf_cnt_ch7_int_st : RO; bitpos: [19]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only + * when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. */ - uint32_t task_timer3_pause_resume_en:1; + uint32_t ovf_cnt_ch7_int_st:1; + uint32_t reserved_20:12; }; uint32_t val; -} ledc_evt_task_en1_reg_t; - +} ledc_int_st_reg_t; -/** Group: en2 */ -/** Type of evt_task_en2 register - * Ledc event task enable bit register2. +/** Type of int_ena register + * Interrupt enable register */ typedef union { struct { - /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch0_en:1; - /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch1_en:1; - /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch2_en:1; - /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch3_en:1; - /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: - * Enable - */ - uint32_t task_gamma_restart_ch4_en:1; - /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: - * Enable + /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. */ - uint32_t task_gamma_restart_ch5_en:1; - /** task_gamma_restart_ch6_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: Disable\\1: - * Enable + uint32_t timer0_ovf_int_ena:1; + /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. */ - uint32_t task_gamma_restart_ch6_en:1; - /** task_gamma_restart_ch7_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: Disable\\1: - * Enable + uint32_t timer1_ovf_int_ena:1; + /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. */ - uint32_t task_gamma_restart_ch7_en:1; - /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: - * Enable + uint32_t timer2_ovf_int_ena:1; + /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. */ - uint32_t task_gamma_pause_ch0_en:1; - /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: - * Enable + uint32_t timer3_ovf_int_ena:1; + /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. */ - uint32_t task_gamma_pause_ch1_en:1; - /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch0_int_ena:1; + /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. */ - uint32_t task_gamma_pause_ch2_en:1; - /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch1_int_ena:1; + /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. */ - uint32_t task_gamma_pause_ch3_en:1; - /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch2_int_ena:1; + /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. */ - uint32_t task_gamma_pause_ch4_en:1; - /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch3_int_ena:1; + /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. */ - uint32_t task_gamma_pause_ch5_en:1; - /** task_gamma_pause_ch6_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch4_int_ena:1; + /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. */ - uint32_t task_gamma_pause_ch6_en:1; - /** task_gamma_pause_ch7_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch5_int_ena:1; + /** duty_chng_end_ch6_int_ena : R/W; bitpos: [10]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. */ - uint32_t task_gamma_pause_ch7_en:1; - /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch6_int_ena:1; + /** duty_chng_end_ch7_int_ena : R/W; bitpos: [11]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. */ - uint32_t task_gamma_resume_ch0_en:1; - /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: - * Enable + uint32_t duty_chng_end_ch7_int_ena:1; + /** ovf_cnt_ch0_int_ena : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. */ - uint32_t task_gamma_resume_ch1_en:1; - /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: - * Enable + uint32_t ovf_cnt_ch0_int_ena:1; + /** ovf_cnt_ch1_int_ena : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. */ - uint32_t task_gamma_resume_ch2_en:1; - /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: - * Enable + uint32_t ovf_cnt_ch1_int_ena:1; + /** ovf_cnt_ch2_int_ena : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. */ - uint32_t task_gamma_resume_ch3_en:1; - /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: - * Enable + uint32_t ovf_cnt_ch2_int_ena:1; + /** ovf_cnt_ch3_int_ena : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. */ - uint32_t task_gamma_resume_ch4_en:1; - /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: - * Enable + uint32_t ovf_cnt_ch3_int_ena:1; + /** ovf_cnt_ch4_int_ena : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. */ - uint32_t task_gamma_resume_ch5_en:1; - /** task_gamma_resume_ch6_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: Disable\\1: - * Enable + uint32_t ovf_cnt_ch4_int_ena:1; + /** ovf_cnt_ch5_int_ena : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. */ - uint32_t task_gamma_resume_ch6_en:1; - /** task_gamma_resume_ch7_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: Disable\\1: - * Enable + uint32_t ovf_cnt_ch5_int_ena:1; + /** ovf_cnt_ch6_int_ena : R/W; bitpos: [18]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. */ - uint32_t task_gamma_resume_ch7_en:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} ledc_evt_task_en2_reg_t; - - -/** Group: cmp */ -/** Type of timern_cmp register - * Ledc timern compare value register. - */ -typedef union { - struct { - /** timer0_cmp : R/W; bitpos: [19:0]; default: 0; - * Configures the comparison value for LEDC timern. + uint32_t ovf_cnt_ch6_int_ena:1; + /** ovf_cnt_ch7_int_ena : R/W; bitpos: [19]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. */ - uint32_t timer0_cmp:20; + uint32_t ovf_cnt_ch7_int_ena:1; uint32_t reserved_20:12; }; uint32_t val; -} ledc_timern_cmp_reg_t; - +} ledc_int_ena_reg_t; -/** Group: cap */ -/** Type of timern_cnt_cap register - * Ledc timern captured count value register. +/** Type of int_clr register + * Interrupt clear register */ typedef union { struct { - /** timer0_cnt_cap : RO; bitpos: [19:0]; default: 0; - * Represents the captured LEDC timern count value. + /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. */ - uint32_t timer_cnt_cap:20; - uint32_t reserved_20:12; - }; - uint32_t val; -} ledc_timern_cnt_cap_reg_t; - - -/** Group: Configuration Register */ -/** Type of conf register - * LEDC global configuration register - */ -typedef union { - struct { - /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0; - * Configures the clock source for the four timers.\\0: APB_CLK\\1: RC_FAST_CLK\\2: - * XTAL_CLK\\3: Invalid. No clock + uint32_t timer0_ovf_int_clr:1; + /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. */ - uint32_t apb_clk_sel:2; - /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the - * clock gate for LEDC ch0 gamma ram + uint32_t timer1_ovf_int_clr:1; + /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. */ - uint32_t gamma_ram_clk_en_ch0:1; - /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; - * Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the - * clock gate for LEDC ch1 gamma ram + uint32_t timer2_ovf_int_clr:1; + /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. */ - uint32_t gamma_ram_clk_en_ch1:1; - /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the - * clock gate for LEDC ch2 gamma ram + uint32_t timer3_ovf_int_clr:1; + /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. */ - uint32_t gamma_ram_clk_en_ch2:1; - /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the - * clock gate for LEDC ch3 gamma ram + uint32_t duty_chng_end_ch0_int_clr:1; + /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. */ - uint32_t gamma_ram_clk_en_ch3:1; - /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the - * clock gate for LEDC ch4 gamma ram + uint32_t duty_chng_end_ch1_int_clr:1; + /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. */ - uint32_t gamma_ram_clk_en_ch4:1; - /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; - * Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the - * clock gate for LEDC ch5 gamma ram + uint32_t duty_chng_end_ch2_int_clr:1; + /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. */ - uint32_t gamma_ram_clk_en_ch5:1; - /** gamma_ram_clk_en_ch6 : R/W; bitpos: [8]; default: 0; - * Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch6 gamma ram\\1: Force open the - * clock gate for LEDC ch6 gamma ram + uint32_t duty_chng_end_ch3_int_clr:1; + /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. */ - uint32_t gamma_ram_clk_en_ch6:1; - /** gamma_ram_clk_en_ch7 : R/W; bitpos: [9]; default: 0; - * Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: Open the clock - * gate only when application writes or reads LEDC ch7 gamma ram\\1: Force open the - * clock gate for LEDC ch7 gamma ram + uint32_t duty_chng_end_ch4_int_clr:1; + /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. */ - uint32_t gamma_ram_clk_en_ch7:1; - uint32_t reserved_10:21; - /** clk_en : R/W; bitpos: [31]; default: 0; - * Configures whether or not to open register clock gate.\\0: Open the clock gate only - * when application writes registers\\1: Force open the clock gate for register + uint32_t duty_chng_end_ch5_int_clr:1; + /** duty_chng_end_ch6_int_clr : WT; bitpos: [10]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. */ - uint32_t clk_en:1; + uint32_t duty_chng_end_ch6_int_clr:1; + /** duty_chng_end_ch7_int_clr : WT; bitpos: [11]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. + */ + uint32_t duty_chng_end_ch7_int_clr:1; + /** ovf_cnt_ch0_int_clr : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. + */ + uint32_t ovf_cnt_ch0_int_clr:1; + /** ovf_cnt_ch1_int_clr : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. + */ + uint32_t ovf_cnt_ch1_int_clr:1; + /** ovf_cnt_ch2_int_clr : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. + */ + uint32_t ovf_cnt_ch2_int_clr:1; + /** ovf_cnt_ch3_int_clr : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. + */ + uint32_t ovf_cnt_ch3_int_clr:1; + /** ovf_cnt_ch4_int_clr : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. + */ + uint32_t ovf_cnt_ch4_int_clr:1; + /** ovf_cnt_ch5_int_clr : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. + */ + uint32_t ovf_cnt_ch5_int_clr:1; + /** ovf_cnt_ch6_int_clr : WT; bitpos: [18]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. + */ + uint32_t ovf_cnt_ch6_int_clr:1; + /** ovf_cnt_ch7_int_clr : WT; bitpos: [19]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. + */ + uint32_t ovf_cnt_ch7_int_clr:1; + uint32_t reserved_20:12; }; uint32_t val; -} ledc_conf_reg_t; +} ledc_int_clr_reg_t; /** Group: Version Register */ @@ -1171,7 +1271,7 @@ typedef union { */ typedef union { struct { - /** ledc_date : R/W; bitpos: [27:0]; default: 36712560; + /** ledc_date : R/W; bitpos: [27:0]; default: 37765152; * Configures the version. */ uint32_t ledc_date:28; @@ -1180,6 +1280,7 @@ typedef union { uint32_t val; } ledc_date_reg_t; + typedef struct { volatile ledc_chn_conf0_reg_t conf0; volatile ledc_chn_hpoint_reg_t hpoint; @@ -1205,7 +1306,7 @@ typedef struct { volatile ledc_ch_group_reg_t channel_group[1]; volatile ledc_timer_group_reg_t timer_group[1]; volatile ledc_int_raw_reg_t int_raw; - volatile ledc_int_st_reg_t int_st; + volatile ledc_int_st_reg_t int_st; volatile ledc_int_ena_reg_t int_ena; volatile ledc_int_clr_reg_t int_clr; uint32_t reserved_0d0[12]; @@ -1221,7 +1322,6 @@ typedef struct { volatile ledc_date_reg_t date; } ledc_dev_t; - /** * Gamma fade param group ram type */ @@ -1244,7 +1344,6 @@ typedef struct { volatile ledc_gamma_channel_t channel[8]; } ledc_gamma_ram_t; - extern ledc_dev_t LEDC; extern ledc_gamma_ram_t LEDC_GAMMA_RAM; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_reg.h index aa2d39a1cfd5..b2974561e26c 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_reg.h @@ -11,8 +11,6 @@ extern "C" { #endif -// TODO: IDF-13424 - /** LP_ANALOG_PERI_BOD_MODE0_CNTL_REG register * need_des */ @@ -199,6 +197,18 @@ extern "C" { #define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V 0x000003FFU #define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S 22 +/** LP_ANALOG_PERI_CK_GLITCH_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_CK_GLITCH_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x14) +/** LP_ANALOG_PERI_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA (BIT(31)) +#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_M (LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_V << LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_S) +#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_V 0x00000001U +#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_S 31 + /** LP_ANALOG_PERI_PG_GLITCH_CNTL_REG register * need_des */ @@ -223,8 +233,6 @@ extern "C" { #define LP_ANALOG_PERI_ANA_FIB_ENA_V 0xFFFFFFFFU #define LP_ANALOG_PERI_ANA_FIB_ENA_S 0 -#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1) - /** LP_ANALOG_PERI_INT_RAW_REG register * need_des */ @@ -1595,11 +1603,38 @@ extern "C" { #define LP_ANALOG_PERI_TOUCH_PAD14_TH2_V 0x0000FFFFU #define LP_ANALOG_PERI_TOUCH_PAD14_TH2_S 16 +/** LP_ANALOG_PERI_TOUCH_CTRL_REG register + * Touch Control Register + */ +#define LP_ANALOG_PERI_TOUCH_CTRL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1fc) +/** LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_FREQ_SEL : R/W; bitpos: [1:0]; default: 0; + * Configure the frequency point for software to update the baseline + */ +#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_FREQ_SEL 0x00000003U +#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_FREQ_SEL_M (LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_FREQ_SEL_V << LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_FREQ_SEL_S) +#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_FREQ_SEL_V 0x00000003U +#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_FREQ_SEL_S 0 +/** LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_PAD_SEL : R/W; bitpos: [5:2]; default: 0; + * Configure the channel for software to update the baseline. + */ +#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_PAD_SEL 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_PAD_SEL_M (LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_PAD_SEL_V << LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_PAD_SEL_S) +#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_PAD_SEL_V 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_PAD_SEL_S 2 +/** LP_ANALOG_PERI_FREQ_SCAN_CNT_RISE : R/W; bitpos: [7:6]; default: 1; + * Configure the number of hit frequency points that need to be determined for touch + * in frequency hopping mode. + */ +#define LP_ANALOG_PERI_FREQ_SCAN_CNT_RISE 0x00000003U +#define LP_ANALOG_PERI_FREQ_SCAN_CNT_RISE_M (LP_ANALOG_PERI_FREQ_SCAN_CNT_RISE_V << LP_ANALOG_PERI_FREQ_SCAN_CNT_RISE_S) +#define LP_ANALOG_PERI_FREQ_SCAN_CNT_RISE_V 0x00000003U +#define LP_ANALOG_PERI_FREQ_SCAN_CNT_RISE_S 6 + /** LP_ANALOG_PERI_DATE_REG register * need_des */ #define LP_ANALOG_PERI_DATE_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x3fc) -/** LP_ANALOG_PERI_LP_ANALOG_PERI_DATE : R/W; bitpos: [30:0]; default: 2294816; +/** LP_ANALOG_PERI_LP_ANALOG_PERI_DATE : R/W; bitpos: [30:0]; default: 2425376; * need_des */ #define LP_ANALOG_PERI_LP_ANALOG_PERI_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_struct.h index 919afa0f2714..8b0b3b326846 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_struct.h @@ -10,8 +10,6 @@ extern "C" { #endif -// TODO: IDF-13424 - /** Group: configure_register */ /** Type of bod_mode0_cntl register * need_des @@ -154,6 +152,20 @@ typedef union { uint32_t val; } lp_analog_peri_vddbat_charge_cntl_reg_t; +/** Type of ck_glitch_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ck_glitch_reset_ena:1; + }; + uint32_t val; +} lp_analog_peri_ck_glitch_cntl_reg_t; + /** Type of pg_glitch_cntl register * need_des */ @@ -692,14 +704,10 @@ typedef union { * High speed touch driver */ uint32_t touch_freq_drv_hs:5; - /** touch_bypass_shield : R/W; bitpos: [18]; default: 0; - * bypass the shield channel output (only available since ECO1) - */ - uint32_t touch_bypass_shield:1; - /** touch_freq_dbias : R/W; bitpos: [22:19]; default: 0; + /** touch_freq_dbias : R/W; bitpos: [22:18]; default: 0; * Internal LDO voltage */ - uint32_t touch_freq_dbias:4; + uint32_t touch_freq_dbias:5; uint32_t reserved_23:9; }; uint32_t val; @@ -799,7 +807,7 @@ typedef union { uint32_t val; } lp_analog_peri_touch_mux1_reg_t; -/** Type of touch_pad0_th0 register +/** Type of touch_pad_thn register * need_des */ typedef union { @@ -813,12 +821,35 @@ typedef union { uint32_t val; } lp_analog_peri_touch_pad_thn_reg_t; +/** Type of touch_ctrl register + * Touch Control Register + */ +typedef union { + struct { + /** touch_update_benchmark_freq_sel : R/W; bitpos: [1:0]; default: 0; + * Configure the frequency point for software to update the benchmark + */ + uint32_t touch_update_benchmark_freq_sel:2; + /** touch_update_benchmark_pad_sel : R/W; bitpos: [5:2]; default: 0; + * Configure the channel for software to update the benchmark. + */ + uint32_t touch_update_benchmark_pad_sel:4; + /** freq_scan_cnt_rise : R/W; bitpos: [7:6]; default: 1; + * Configure the number of hit frequency points that need to be determined for touch + * in frequency hopping mode. + */ + uint32_t freq_scan_cnt_rise:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_analog_peri_touch_ctrl_reg_t; + /** Type of date register * need_des */ typedef union { struct { - /** lp_analog_peri_date : R/W; bitpos: [30:0]; default: 2294816; + /** lp_analog_peri_date : R/W; bitpos: [30:0]; default: 2425376; * need_des */ uint32_t lp_analog_peri_date:31; @@ -841,7 +872,7 @@ typedef struct { volatile lp_analog_peri_vdd_source_cntl_reg_t vdd_source_cntl; volatile lp_analog_peri_vddbat_bod_cntl_reg_t vddbat_bod_cntl; volatile lp_analog_peri_vddbat_charge_cntl_reg_t vddbat_charge_cntl; - uint32_t reserved_014; + volatile lp_analog_peri_ck_glitch_cntl_reg_t ck_glitch_cntl; volatile lp_analog_peri_pg_glitch_cntl_reg_t pg_glitch_cntl; volatile lp_analog_peri_fib_enable_reg_t fib_enable; volatile lp_analog_peri_int_raw_reg_t int_raw; @@ -870,7 +901,9 @@ typedef struct { volatile lp_analog_peri_touch_mux0_reg_t touch_mux0; volatile lp_analog_peri_touch_mux1_reg_t touch_mux1; volatile lp_analog_peri_touch_padx_thn_reg_t touch_padx_thn[15]; - uint32_t reserved_1f8[129]; + uint32_t reserved_1f8; + volatile lp_analog_peri_touch_ctrl_reg_t touch_ctrl; + uint32_t reserved_200[127]; volatile lp_analog_peri_date_reg_t date; } lp_analog_peri_dev_t; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h index 740839aecdcd..c445ffbd1661 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h @@ -114,22 +114,6 @@ typedef union { } lp_iomux_ext_wakeup0_sel_reg_t; -/** Group: lp_pad_hold */ -/** Type of lp_pad_hold register - * Reserved - */ -typedef union { - struct { - /** reg_lp_gpio_hold : R/W; bitpos: [15:0]; default: 0; - * Reserved - */ - uint32_t reg_lp_gpio_hold:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} lp_iomux_lp_pad_hold_reg_t; - - /** Group: lp_pad_hys */ /** Type of lp_pad_hys register * Reserved @@ -151,7 +135,7 @@ typedef struct lp_iomux_dev_t { volatile lp_iomux_ver_date_reg_t ver_date; volatile lp_iomux_pad_reg_t pad[16]; volatile lp_iomux_ext_wakeup0_sel_reg_t ext_wakeup0_sel; - volatile lp_iomux_lp_pad_hold_reg_t lp_pad_hold; + uint32_t reserved_04c; volatile lp_iomux_lp_pad_hys_reg_t lp_pad_hys; } lp_iomux_dev_t; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mcpwm_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mcpwm_eco5_struct.h deleted file mode 100644 index 2ee5ebb57cdc..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/mcpwm_eco5_struct.h +++ /dev/null @@ -1,2347 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration register */ -/** Type of clk_cfg register - * PWM clock prescaler register. - */ -typedef union { - struct { - /** clk_prescale : R/W; bitpos: [7:0]; default: 0; - * Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * - * (PWM_CLK_PRESCALE + 1). - */ - uint32_t clk_prescale:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} mcpwm_clk_cfg_reg_t; - -/** Type of timern_cfg0 register - * PWM timern period and update method configuration register. - */ -typedef union { - struct { - /** timern_prescale : R/W; bitpos: [7:0]; default: 0; - * Configures the prescaler value of timern, so that the period of PT0_clk = Period of - * PWM_clk * (PWM_TIMERn_PRESCALE + 1) - */ - uint32_t timern_prescale:8; - /** timern_period : R/W; bitpos: [23:8]; default: 255; - * Configures the period shadow of PWM timern - */ - uint32_t timern_period:16; - /** timern_period_upmethod : R/W; bitpos: [25:24]; default: 0; - * Configures the update method for active register of PWM timern period. - * 0: Immediate - * 1: TEZ - * 2: Sync - * 3: TEZ or sync - * TEZ here and below means timer equal zero event - */ - uint32_t timern_period_upmethod:2; - uint32_t reserved_26:6; - }; - uint32_t val; -} mcpwm_timern_cfg0_reg_t; - -/** Type of timern_cfg1 register - * PWM timern working mode and start/stop control register. - */ -typedef union { - struct { - /** timern_start : R/W/SC; bitpos: [2:0]; default: 0; - * Configures whether or not to start/stop PWM timern. - * 0: If PWM timern starts, then stops at TEZ - * 1: If timern starts, then stops at TEP - * 2: PWM timern starts and runs on - * 3: Timern starts and stops at the next TEZ - * 4: Timer0 starts and stops at the next TEP. - * TEP here and below means the event that happens when the timer equals to period - */ - uint32_t timern_start:3; - /** timern_mod : R/W; bitpos: [4:3]; default: 0; - * Configures the working mode of PWM timern. - * 0: Freeze - * 1: Increase mode - * 2: Decrease mode - * 3: Up-down mode - */ - uint32_t timern_mod:2; - uint32_t reserved_5:27; - }; - uint32_t val; -} mcpwm_timern_cfg1_reg_t; - -/** Type of timern_sync register - * PWM timern sync function configuration register. - */ -typedef union { - struct { - /** timern_synci_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable timern reloading with phase on sync input event - * is enabled. - * 0: Disable - * 1: Enable - */ - uint32_t timern_synci_en:1; - /** timern_sync_sw : R/W; bitpos: [1]; default: 0; - * Configures the generation of software sync. Toggling this bit will trigger a - * software sync. - */ - uint32_t timern_sync_sw:1; - /** timern_synco_sel : R/W; bitpos: [3:2]; default: 0; - * Configures the selection of PWM timern sync_out. - * 0: Sync_in - * 1: TEZ - * 2: TEP - * 3: Invalid, sync_out selects noting - */ - uint32_t timern_synco_sel:2; - /** timern_phase : R/W; bitpos: [19:4]; default: 0; - * Configures the phase for timern reload on sync event. - */ - uint32_t timern_phase:16; - /** timern_phase_direction : R/W; bitpos: [20]; default: 0; - * Configures the PWM timern's direction when timern mode is up-down mode. - * 0: Increase - * 1: Decrease - */ - uint32_t timern_phase_direction:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} mcpwm_timern_sync_reg_t; - -/** Type of timer_synci_cfg register - * Synchronization input selection register for PWM timers. - */ -typedef union { - struct { - /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0; - * Configures the selection of sync input for PWM timer0. - * 1: PWM timer0 sync_out - * 2: PWM timer1 sync_out - * 3: PWM timer2 sync_out - * 4: SYNC0 from GPIO matrix - * 5: SYNC1 from GPIO matrix - * 6: SYNC2 from GPIO matrix - * Other values: No sync input selected - */ - uint32_t timer0_syncisel:3; - /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0; - * Configures the selection of sync input for PWM timer1. - * 1: PWM timer0 sync_out - * 2: PWM timer1 sync_out - * 3: PWM timer2 sync_out - * 4: SYNC0 from GPIO matrix - * 5: SYNC1 from GPIO matrix - * 6: SYNC2 from GPIO matrix - * Other values: No sync input selected - */ - uint32_t timer1_syncisel:3; - /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0; - * Configures the selection of sync input for PWM timer2. - * 1: PWM timer0 sync_out - * 2: PWM timer1 sync_out - * 3: PWM timer2 sync_out - * 4: SYNC0 from GPIO matrix - * 5: SYNC1 from GPIO matrix - * 6: SYNC2 from GPIO matrix - * Other values: No sync input selected - */ - uint32_t timer2_syncisel:3; - /** external_synci0_invert : R/W; bitpos: [9]; default: 0; - * Configures whether or not to invert SYNC0 from GPIO matrix. - * 0: Not invert - * 1: Invert - */ - uint32_t external_synci0_invert:1; - /** external_synci1_invert : R/W; bitpos: [10]; default: 0; - * Configures whether or not to invert SYNC1 from GPIO matrix. - * 0: Not invert - * 1: Invert - */ - uint32_t external_synci1_invert:1; - /** external_synci2_invert : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert SYNC2 from GPIO matrix. - * 0: Not invert - * 1: Invert - */ - uint32_t external_synci2_invert:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} mcpwm_timer_synci_cfg_reg_t; - -/** Type of operator_timersel register - * PWM operator's timer select register - */ -typedef union { - struct { - /** operator0_timersel : R/W; bitpos: [1:0]; default: 0; - * Configures which PWM timer will be the timing reference for PWM operator0. - * 0: Timer0 - * 1: Timer1 - * 2: Timer2 - * 3: Invalid, will select timer2 - */ - uint32_t operator0_timersel:2; - /** operator1_timersel : R/W; bitpos: [3:2]; default: 0; - * Configures which PWM timer will be the timing reference for PWM operator1. - * 0: Timer0 - * 1: Timer1 - * 2: Timer2 - * 3: Invalid, will select timer2 - */ - uint32_t operator1_timersel:2; - /** operator2_timersel : R/W; bitpos: [5:4]; default: 0; - * Configures which PWM timer will be the timing reference for PWM operator2. - * 0: Timer0 - * 1: Timer1 - * 2: Timer2 - * 3: Invalid, will select timer2 - */ - uint32_t operator2_timersel:2; - uint32_t reserved_6:26; - }; - uint32_t val; -} mcpwm_operator_timersel_reg_t; - -/** Type of genn_stmp_cfg register - * Generatorn time stamp registers A and B transfer status and update method register - */ -typedef union { - struct { - /** cmprn_a_upmethod : R/W; bitpos: [3:0]; default: 0; - * Configures the update method for PWM generator n time stamp A's active register. - * 0: Immediately - * Bit0 is set to 1: TEZ - * Bit1 is set to 1: TEP - * Bit2 is set to 1: Sync - * Bit3 is set to 1: Disable the update - */ - uint32_t cmprn_a_upmethod:4; - /** cmprn_b_upmethod : R/W; bitpos: [7:4]; default: 0; - * Configures the update method for PWM generator n time stamp B's active register. - * 0: Immediately - * Bit0 is set to 1: TEZ - * Bit1 is set to 1: TEP - * Bit2 is set to 1: Sync - * Bit3 is set to 1: Disable the update - */ - uint32_t cmprn_b_upmethod:4; - /** cmprn_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; - * Represents whether or not generatorn time stamp A's shadow reg is transferred. - * 0: A's active reg has been updated with shadow register latest value. - * 1: A's shadow reg is filled and waiting to be transferred to A's active reg - */ - uint32_t cmprn_a_shdw_full:1; - /** cmprn_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; - * Represents whether or not generatorn time stamp B's shadow reg is transferred. - * 0: B's active reg has been updated with shadow register latest value. - * 1: B's shadow reg is filled and waiting to be transferred to B's active reg - */ - uint32_t cmprn_b_shdw_full:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} mcpwm_genn_stmp_cfg_reg_t; - -/** Type of genn_tstmp_a register - * Generatorn time stamp A's shadow register - */ -typedef union { - struct { - /** cmprn_a : R/W; bitpos: [15:0]; default: 0; - * Configures the value of PWM generator n time stamp A's shadow register. - */ - uint32_t cmprn_a:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_genn_tstmp_a_reg_t; - -/** Type of genn_tstmp_b register - * Generatorn time stamp B's shadow register - */ -typedef union { - struct { - /** cmprn_b : R/W; bitpos: [15:0]; default: 0; - * Configures the value of PWM generator n time stamp B's shadow register. - */ - uint32_t cmprn_b:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_genn_tstmp_b_reg_t; - -/** Type of genn_cfg0 register - * Generatorn fault event T0 and T1 configuration register - */ -typedef union { - struct { - /** genn_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; - * Configures update method for PWM generator n's active register. - * 0: Immediately - * Bit0 is set to 1: TEZ - * Bit1 is set to 1: TEP - * Bit2 is set to 1: Sync - * Bit3 is set to 1: Disable the update - */ - uint32_t genn_cfg_upmethod:4; - /** genn_t0_sel : R/W; bitpos: [6:4]; default: 0; - * Configures source selection for PWM generator n event_t0, take effect immediately. - * 0: fault_event0 - * 1: fault_event1 - * 2: fault_event2 - * 3: sync_taken - * 4: Invalid, Select nothing - */ - uint32_t genn_t0_sel:3; - /** genn_t1_sel : R/W; bitpos: [9:7]; default: 0; - * Configures source selection for PWM generator n event_t1, take effect immediately. - * 0: fault_event0 - * 1: fault_event1 - * 2: fault_event2 - * 3: sync_taken - * 4: Invalid, Select nothing - */ - uint32_t genn_t1_sel:3; - uint32_t reserved_10:22; - }; - uint32_t val; -} mcpwm_genn_cfg0_reg_t; - -/** Type of genn_force register - * Generatorn output signal force mode register. - */ -typedef union { - struct { - /** genn_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; - * Configures update method for continuous software force of PWM generatorn. - * 0: Immediately - * Bit0 is set to 1: TEZ - * Bit1 is set to 1: TEP - * Bit2 is set to 1: TEA - * Bit3 is set to 1: TEB - * Bit4 is set to 1: Sync - * Bit5 is set to 1: Disable update. TEA/B here and below means an event generated - * when the timer's value equals to that of register A/B. - */ - uint32_t genn_cntuforce_upmethod:6; - /** genn_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; - * Configures continuous software force mode for PWMn A. - * 0: Disabled - * 1: Low - * 2: High - * 3: Disabled - */ - uint32_t genn_a_cntuforce_mode:2; - /** genn_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; - * Configures continuous software force mode for PWMn B. - * 0: Disabled - * 1: Low - * 2: High - * 3: Disabled - */ - uint32_t genn_b_cntuforce_mode:2; - /** genn_a_nciforce : R/W; bitpos: [10]; default: 0; - * Configures the generation of non-continuous immediate software-force event for PWMn - * A, a toggle will trigger a force event. - */ - uint32_t genn_a_nciforce:1; - /** genn_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; - * Configures non-continuous immediate software force mode for PWMn A. - * 0: Disabled - * 1: Low - * 2: High - * 3: Disabled - */ - uint32_t genn_a_nciforce_mode:2; - /** genn_b_nciforce : R/W; bitpos: [13]; default: 0; - * Configures the generation of non-continuous immediate software-force event for PWMn - * B, a toggle will trigger a force event. - */ - uint32_t genn_b_nciforce:1; - /** genn_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; - * Configures non-continuous immediate software force mode for PWMn B. - * 0: Disabled - * 1: Low - * 2: High - * 3: Disabled - */ - uint32_t genn_b_nciforce_mode:2; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_genn_force_reg_t; - -/** Type of genn_a register - * PWMn output signal A actions configuration register - */ -typedef union { - struct { - /** genn_a_utez : R/W; bitpos: [1:0]; default: 0; - * Configures action on PWMn A triggered by event TEZ when timer increasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_a_utez:2; - /** genn_a_utep : R/W; bitpos: [3:2]; default: 0; - * Configures action on PWMn A triggered by event TEP when timer increasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_a_utep:2; - /** genn_a_utea : R/W; bitpos: [5:4]; default: 0; - * Configures action on PWMn A triggered by event TEA when timer increasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_a_utea:2; - /** genn_a_uteb : R/W; bitpos: [7:6]; default: 0; - * Configures action on PWMn A triggered by event TEB when timer increasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_a_uteb:2; - /** genn_a_ut0 : R/W; bitpos: [9:8]; default: 0; - * Configures action on PWMn A triggered by event_t0 when timer increasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_a_ut0:2; - /** genn_a_ut1 : R/W; bitpos: [11:10]; default: 0; - * Configures action on PWMn A triggered by event_t1 when timer increasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_a_ut1:2; - /** genn_a_dtez : R/W; bitpos: [13:12]; default: 0; - * Configures action on PWMn A triggered by event TEZ when timer decreasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_a_dtez:2; - /** genn_a_dtep : R/W; bitpos: [15:14]; default: 0; - * Configures action on PWMn A triggered by event TEP when timer decreasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_a_dtep:2; - /** genn_a_dtea : R/W; bitpos: [17:16]; default: 0; - * Configures action on PWMn A triggered by event TEA when timer decreasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_a_dtea:2; - /** genn_a_dteb : R/W; bitpos: [19:18]; default: 0; - * Configures action on PWMn A triggered by event TEB when timer decreasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_a_dteb:2; - /** genn_a_dt0 : R/W; bitpos: [21:20]; default: 0; - * Configures action on PWMn A triggered by event_t0 when timer decreasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_a_dt0:2; - /** genn_a_dt1 : R/W; bitpos: [23:22]; default: 0; - * Configures action on PWMn A triggered by event_t1 when timer decreasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_a_dt1:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} mcpwm_genn_a_reg_t; - -/** Type of genn_b register - * PWMn output signal B actions configuration register - */ -typedef union { - struct { - /** genn_b_utez : R/W; bitpos: [1:0]; default: 0; - * Configures action on PWMn B triggered by event TEZ when timer increasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_b_utez:2; - /** genn_b_utep : R/W; bitpos: [3:2]; default: 0; - * Configures action on PWMn B triggered by event TEP when timer increasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_b_utep:2; - /** genn_b_utea : R/W; bitpos: [5:4]; default: 0; - * Configures action on PWMn B triggered by event TEA when timer increasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_b_utea:2; - /** genn_b_uteb : R/W; bitpos: [7:6]; default: 0; - * Configures action on PWMn B triggered by event TEB when timer increasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_b_uteb:2; - /** genn_b_ut0 : R/W; bitpos: [9:8]; default: 0; - * Configures action on PWMn B triggered by event_t0 when timer increasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_b_ut0:2; - /** genn_b_ut1 : R/W; bitpos: [11:10]; default: 0; - * Configures action on PWMn B triggered by event_t1 when timer increasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_b_ut1:2; - /** genn_b_dtez : R/W; bitpos: [13:12]; default: 0; - * Configures action on PWMn B triggered by event TEZ when timer decreasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_b_dtez:2; - /** genn_b_dtep : R/W; bitpos: [15:14]; default: 0; - * Configures action on PWMn B triggered by event TEP when timer decreasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_b_dtep:2; - /** genn_b_dtea : R/W; bitpos: [17:16]; default: 0; - * Configures action on PWMn B triggered by event TEA when timer decreasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_b_dtea:2; - /** genn_b_dteb : R/W; bitpos: [19:18]; default: 0; - * Configures action on PWMn B triggered by event TEB when timer decreasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_b_dteb:2; - /** genn_b_dt0 : R/W; bitpos: [21:20]; default: 0; - * Configures action on PWMn B triggered by event_t0 when timer decreasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_b_dt0:2; - /** genn_b_dt1 : R/W; bitpos: [23:22]; default: 0; - * Configures action on PWMn B triggered by event_t1 when timer decreasing. - * 0: No change - * 1: Low - * 2: High - * 3: Toggle - */ - uint32_t genn_b_dt1:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} mcpwm_genn_b_reg_t; - -/** Type of dtn_cfg register - * Dead time configuration register - */ -typedef union { - struct { - /** dbn_fed_upmethod : R/W; bitpos: [3:0]; default: 0; - * Configures update method for FED (Falling edge delay) active register. - * 0: Immediate - * Bit0 is set to 1: TEZ - * Bit1 is set to 1: TEP - * Bit2 is set to 1: Sync - * Bit3 is set to 1: Disable the update - */ - uint32_t dbn_fed_upmethod:4; - /** dbn_red_upmethod : R/W; bitpos: [7:4]; default: 0; - * Configures update method for RED (rising edge delay) active register. - * 0: Immediate - * Bit0 is set to 1: TEZ - * Bit1 is set to 1: TEP - * Bit2 is set to 1: Sync - * Bit3 is set to 1: Disable the update - */ - uint32_t dbn_red_upmethod:4; - /** dbn_deb_mode : R/W; bitpos: [8]; default: 0; - * Configures S8 in table, dual-edge B mode. - * 0: fed/red take effect on different path separately - * 1: fed/red take effect on B path, A out is in bypass or dulpB mode - */ - uint32_t dbn_deb_mode:1; - /** dbn_a_outswap : R/W; bitpos: [9]; default: 0; - * Configures S6 in table. - */ - uint32_t dbn_a_outswap:1; - /** dbn_b_outswap : R/W; bitpos: [10]; default: 0; - * Configures S7 in table. - */ - uint32_t dbn_b_outswap:1; - /** dbn_red_insel : R/W; bitpos: [11]; default: 0; - * Configures S4 in table. - */ - uint32_t dbn_red_insel:1; - /** dbn_fed_insel : R/W; bitpos: [12]; default: 0; - * Configures S5 in table. - */ - uint32_t dbn_fed_insel:1; - /** dbn_red_outinvert : R/W; bitpos: [13]; default: 0; - * Configures S2 in table. - */ - uint32_t dbn_red_outinvert:1; - /** dbn_fed_outinvert : R/W; bitpos: [14]; default: 0; - * Configures S3 in table. - */ - uint32_t dbn_fed_outinvert:1; - /** dbn_a_outbypass : R/W; bitpos: [15]; default: 1; - * Configures S1 in table. - */ - uint32_t dbn_a_outbypass:1; - /** dbn_b_outbypass : R/W; bitpos: [16]; default: 1; - * Configures S0 in table. - */ - uint32_t dbn_b_outbypass:1; - /** dbn_clk_sel : R/W; bitpos: [17]; default: 0; - * Configures dead time generator n clock selection. - * 0: PWM_clk - * 1: PT_clk - */ - uint32_t dbn_clk_sel:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} mcpwm_dtn_cfg_reg_t; - -/** Type of dtn_fed_cfg register - * Falling edge delay (FED) shadow register - */ -typedef union { - struct { - /** dbn_fed : R/W; bitpos: [15:0]; default: 0; - * Configures shadow register for FED. - */ - uint32_t dbn_fed:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_dtn_fed_cfg_reg_t; - -/** Type of dtn_red_cfg register - * Rising edge delay (RED) shadow register - */ -typedef union { - struct { - /** dbn_red : R/W; bitpos: [15:0]; default: 0; - * Configures shadow register for RED. - */ - uint32_t dbn_red:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_dtn_red_cfg_reg_t; - -/** Type of carriern_cfg register - * Carriern configuration register - */ -typedef union { - struct { - /** choppern_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable carriern. - * 0: Bypassed - * 1: Enabled - */ - uint32_t choppern_en:1; - /** choppern_prescale : R/W; bitpos: [4:1]; default: 0; - * Configures the prescale value of PWM carriern clock (PC_clk), so that period of - * PC_clk = period of PWM_clk * (PWM_CARRIERn_PRESCALE + 1) - */ - uint32_t choppern_prescale:4; - /** choppern_duty : R/W; bitpos: [7:5]; default: 0; - * Configures carrier duty. Duty = PWM_CARRIERn_DUTY / 8 - */ - uint32_t choppern_duty:3; - /** choppern_oshtwth : R/W; bitpos: [11:8]; default: 0; - * Configures width of the first pulse. Measurement unit: Periods of the carrier. - */ - uint32_t choppern_oshtwth:4; - /** choppern_out_invert : R/W; bitpos: [12]; default: 0; - * Configures whether or not to invert the output of PWMn A and PWMn B for this - * submodule. - * 0: Normal - * 1: Invert - */ - uint32_t choppern_out_invert:1; - /** choppern_in_invert : R/W; bitpos: [13]; default: 0; - * Configures whether or not to invert the input of PWMn A and PWMn B for this - * submodule. - * 0: Normal - * 1: Invert - */ - uint32_t choppern_in_invert:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} mcpwm_carriern_cfg_reg_t; - -/** Type of fhn_cfg0 register - * PWMn A and PWMn B trip events actions configuration register - */ -typedef union { - struct { - /** tzn_sw_cbc : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable software force cycle-by-cycle mode action. - * 0: Disable - * 1: Enable - */ - uint32_t tzn_sw_cbc:1; - /** tzn_f2_cbc : R/W; bitpos: [1]; default: 0; - * Configures whether or not event_f2 will trigger cycle-by-cycle mode action. - * 0: Disable - * 1: Enable - */ - uint32_t tzn_f2_cbc:1; - /** tzn_f1_cbc : R/W; bitpos: [2]; default: 0; - * Configures whether or not event_f1 will trigger cycle-by-cycle mode action. - * 0: Disable - * 1: Enable - */ - uint32_t tzn_f1_cbc:1; - /** tzn_f0_cbc : R/W; bitpos: [3]; default: 0; - * Configures whether or not event_f0 will trigger cycle-by-cycle mode action. - * 0: Disable - * 1: Enable - */ - uint32_t tzn_f0_cbc:1; - /** tzn_sw_ost : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable software force one-shot mode action. - * 0: Disable - * 1: Enable - */ - uint32_t tzn_sw_ost:1; - /** tzn_f2_ost : R/W; bitpos: [5]; default: 0; - * Configures whether or not event_f2 will trigger one-shot mode action. - * 0: Disable - * 1: Enable - */ - uint32_t tzn_f2_ost:1; - /** tzn_f1_ost : R/W; bitpos: [6]; default: 0; - * Configures whether or not event_f1 will trigger one-shot mode action. - * 0: Disable - * 1: Enable - */ - uint32_t tzn_f1_ost:1; - /** tzn_f0_ost : R/W; bitpos: [7]; default: 0; - * Configures whether or not event_f0 will trigger one-shot mode action. - * 0: Disable - * 1: Enable - */ - uint32_t tzn_f0_ost:1; - /** tzn_a_cbc_d : R/W; bitpos: [9:8]; default: 0; - * Configures cycle-by-cycle mode action on PWMn A when fault event occurs and timer - * is decreasing. - * 0: Do nothing - * 1: Force low - * 2: Force high - * 3: Toggle - */ - uint32_t tzn_a_cbc_d:2; - /** tzn_a_cbc_u : R/W; bitpos: [11:10]; default: 0; - * Configures cycle-by-cycle mode action on PWMn A when fault event occurs and timer - * is increasing. - * 0: Do nothing - * 1: Force low - * 2: Force high - * 3: Toggle - */ - uint32_t tzn_a_cbc_u:2; - /** tzn_a_ost_d : R/W; bitpos: [13:12]; default: 0; - * Configures one-shot mode action on PWMn A when fault event occurs and timer is - * decreasing. - * 0: Do nothing - * 1: Force low - * 2: Force high - * 3: Toggle - */ - uint32_t tzn_a_ost_d:2; - /** tzn_a_ost_u : R/W; bitpos: [15:14]; default: 0; - * Configures one-shot mode action on PWMn A when fault event occurs and timer is - * increasing. - * 0: Do nothing - * 1: Force low - * 2: Force high - * 3: Toggle - */ - uint32_t tzn_a_ost_u:2; - /** tzn_b_cbc_d : R/W; bitpos: [17:16]; default: 0; - * Configures cycle-by-cycle mode action on PWMn B when fault event occurs and timer - * is decreasing. - * 0: Do nothing - * 1: Force low - * 2: Force high - * 3: Toggle - */ - uint32_t tzn_b_cbc_d:2; - /** tzn_b_cbc_u : R/W; bitpos: [19:18]; default: 0; - * Configures cycle-by-cycle mode action on PWMn B when fault event occurs and timer - * is increasing. - * 0: Do nothing - * 1: Force low - * 2: Force high - * 3: Toggle - */ - uint32_t tzn_b_cbc_u:2; - /** tzn_b_ost_d : R/W; bitpos: [21:20]; default: 0; - * Configures one-shot mode action on PWMn B when fault event occurs and timer is - * decreasing. - * 0: Do nothing - * 1: Force low - * 2: Force high - * 3: Toggle - */ - uint32_t tzn_b_ost_d:2; - /** tzn_b_ost_u : R/W; bitpos: [23:22]; default: 0; - * Configures one-shot mode action on PWMn B when fault event occurs and timer is - * increasing. - * 0: Do nothing - * 1: Force low - * 2: Force high - * 3: Toggle - */ - uint32_t tzn_b_ost_u:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} mcpwm_fhn_cfg0_reg_t; - -/** Type of fhn_cfg1 register - * Software triggers for fault handler actions configuration register - */ -typedef union { - struct { - /** tzn_clr_ost : R/W; bitpos: [0]; default: 0; - * Configures the generation of software one-shot mode action clear. A toggle - * (software negate its value) triggers a clear for on going one-shot mode action. - */ - uint32_t tzn_clr_ost:1; - /** tzn_cbcpulse : R/W; bitpos: [2:1]; default: 0; - * Configures the refresh moment selection of cycle-by-cycle mode action. - * 0: Select nothing, will not refresh - * Bit0 is set to 1: TEZ - * Bit1 is set to 1: TEP - */ - uint32_t tzn_cbcpulse:2; - /** tzn_force_cbc : R/W; bitpos: [3]; default: 0; - * Configures the generation of software cycle-by-cycle mode action. A toggle - * (software negate its value) triggers a cycle-by-cycle mode action. - */ - uint32_t tzn_force_cbc:1; - /** tzn_force_ost : R/W; bitpos: [4]; default: 0; - * Configures the generation of software one-shot mode action. A toggle (software - * negate its value) triggers a one-shot mode action. - */ - uint32_t tzn_force_ost:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} mcpwm_fhn_cfg1_reg_t; - -/** Type of fault_detect register - * Fault detection configuration and status register - */ -typedef union { - struct { - /** f0_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable event_f0 generation. - * 0: Disable - * 1: Enable - */ - uint32_t f0_en:1; - /** f1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable event_f1 generation. - * 0: Disable - * 1: Enable - */ - uint32_t f1_en:1; - /** f2_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable event_f2 generation. - * 0: Disable - * 1: Enable - */ - uint32_t f2_en:1; - /** f0_pole : R/W; bitpos: [3]; default: 0; - * Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix. - * 0: Level low - * 1: Level high - */ - uint32_t f0_pole:1; - /** f1_pole : R/W; bitpos: [4]; default: 0; - * Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix. - * 0: Level low - * 1: Level high - */ - uint32_t f1_pole:1; - /** f2_pole : R/W; bitpos: [5]; default: 0; - * Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix. - * 0: Level low - * 1: Level high - */ - uint32_t f2_pole:1; - /** event_f0 : RO; bitpos: [6]; default: 0; - * Represents whether or not an event_f0 is on going. - * 0: No action - * 1: On going - */ - uint32_t event_f0:1; - /** event_f1 : RO; bitpos: [7]; default: 0; - * Represents whether or not an event_f1 is on going. - * 0: No action - * 1: On going - */ - uint32_t event_f1:1; - /** event_f2 : RO; bitpos: [8]; default: 0; - * Represents whether or not an event_f2 is on going. - * 0: No action - * 1: On going - */ - uint32_t event_f2:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} mcpwm_fault_detect_reg_t; - -/** Type of cap_timer_cfg register - * Capture timer configuration register - */ -typedef union { - struct { - /** cap_timer_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable capture timer increment. - * 0: Disable - * 1: Enable - */ - uint32_t cap_timer_en:1; - /** cap_synci_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable capture timer sync. - * 0: Disable - * 1: Enable - */ - uint32_t cap_synci_en:1; - /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0; - * Configures the selection of capture module sync input. - * 0: None - * 1: Timer0 sync_out - * 2: Timer1 sync_out - * 3: Timer2 sync_out - * 4: SYNC0 from GPIO matrix - * 5: SYNC1 from GPIO matrix - * 6: SYNC2 from GPIO matrix - * 7: None - */ - uint32_t cap_synci_sel:3; - /** cap_sync_sw : WT; bitpos: [5]; default: 0; - * Configures the generation of a capture timer sync when reg_cap_synci_en is 1. - * 0: Invalid, No effect - * 1: Trigger a capture timer sync, capture timer is loaded with value in phase - * register - */ - uint32_t cap_sync_sw:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} mcpwm_cap_timer_cfg_reg_t; - -/** Type of cap_timer_phase register - * Capture timer sync phase register - */ -typedef union { - struct { - /** cap_phase : R/W; bitpos: [31:0]; default: 0; - * Configures phase value for capture timer sync operation. - */ - uint32_t cap_phase:32; - }; - uint32_t val; -} mcpwm_cap_timer_phase_reg_t; - -/** Type of cap_chn_cfg register - * Capture channel n configuration register - */ -typedef union { - struct { - /** capn_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable capture on channel n. - * 0: Disable - * 1: Enable - */ - uint32_t capn_en:1; - /** capn_mode : R/W; bitpos: [2:1]; default: 0; - * Configures which edge of capture on channel n after prescaling is used. - * 0: None - * Bit0 is set to 1: Rnable capture on the negative edge - * Bit1 is set to 1: Enable capture on the positive edge - */ - uint32_t capn_mode:2; - /** capn_prescale : R/W; bitpos: [10:3]; default: 0; - * Configures prescale value on positive edge of CAPn. Prescale value = - * PWM_CAPn_PRESCALE + 1 - */ - uint32_t capn_prescale:8; - /** capn_in_invert : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert CAPn from GPIO matrix before prescale. - * 0: Normal - * 1: Invert - */ - uint32_t capn_in_invert:1; - /** capn_sw : WT; bitpos: [12]; default: 0; - * Configures the generation of software capture. - * 0: Invalid, No effect - * 1: Trigger a software forced capture on channel n - */ - uint32_t capn_sw:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} mcpwm_cap_chn_cfg_reg_t; - -/** Type of update_cfg register - * Generator Update configuration register - */ -typedef union { - struct { - /** global_up_en : R/W; bitpos: [0]; default: 1; - * Configures whether or not to enable global update for all active registers in MCPWM - * module. - * 0: Disable - * 1: Enable - */ - uint32_t global_up_en:1; - /** global_force_up : R/W; bitpos: [1]; default: 0; - * Configures the generation of global forced update for all active registers in MCPWM - * module. A toggle (software invert its value) will trigger a global forced update. - * Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1. - */ - uint32_t global_force_up:1; - /** op0_up_en : R/W; bitpos: [2]; default: 1; - * Configures whether or not to enable update of active registers in PWM operator0. - * Valid only when PWM_GLOBAL_UP_EN is set to 1. - * 0: Disable - * 1: Enable - */ - uint32_t op0_up_en:1; - /** op0_force_up : R/W; bitpos: [3]; default: 0; - * Configures the generation of forced update for active registers in PWM operator0. A - * toggle (software invert its value) will trigger a forced update. Valid only when - * MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1. - */ - uint32_t op0_force_up:1; - /** op1_up_en : R/W; bitpos: [4]; default: 1; - * Configures whether or not to enable update of active registers in PWM operator1. - * Valid only when PWM_GLOBAL_UP_EN is set to 1. - * 0: Disable - * 1: Enable - */ - uint32_t op1_up_en:1; - /** op1_force_up : R/W; bitpos: [5]; default: 0; - * Configures the generation of forced update for active registers in PWM operator1. A - * toggle (software invert its value) will trigger a forced update. Valid only when - * MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1. - */ - uint32_t op1_force_up:1; - /** op2_up_en : R/W; bitpos: [6]; default: 1; - * Configures whether or not to enable update of active registers in PWM operator2. - * Valid only when PWM_GLOBAL_UP_EN is set to 1. - * 0: Disable - * 1: Enable - */ - uint32_t op2_up_en:1; - /** op2_force_up : R/W; bitpos: [7]; default: 0; - * Configures the generation of forced update for active registers in PWM operator2. A - * toggle (software invert its value) will trigger a forced update. Valid only when - * MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1. - */ - uint32_t op2_force_up:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} mcpwm_update_cfg_reg_t; - -/** Type of evt_en register - * Event enable register - */ -typedef union { - struct { - /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable timer0 stop event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_timer0_stop_en:1; - /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable timer1 stop event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_timer1_stop_en:1; - /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable timer2 stop event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_timer2_stop_en:1; - /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable timer0 equal zero event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_timer0_tez_en:1; - /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable timer1 equal zero event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_timer1_tez_en:1; - /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable timer2 equal zero event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_timer2_tez_en:1; - /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable timer0 equal period event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_timer0_tep_en:1; - /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable timer1 equal period event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_timer1_tep_en:1; - /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable timer2 equal period event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_timer2_tep_en:1; - /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable PWM generator0 timer equal a event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_op0_tea_en:1; - /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable PWM generator1 timer equal a event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_op1_tea_en:1; - /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable PWM generator2 timer equal a event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_op2_tea_en:1; - /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable PWM generator0 timer equal b event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_op0_teb_en:1; - /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable PWM generator1 timer equal b event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_op1_teb_en:1; - /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable PWM generator2 timer equal b event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_op2_teb_en:1; - /** evt_f0_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable fault0 event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_f0_en:1; - /** evt_f1_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable fault1 event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_f1_en:1; - /** evt_f2_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable fault2 event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_f2_en:1; - /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable fault0 clear event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_f0_clr_en:1; - /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable fault1 clear event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_f1_clr_en:1; - /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable fault2 clear event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_f2_clr_en:1; - /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable cycle-by-cycle trip0 event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_tz0_cbc_en:1; - /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0; - * Configures whether or not to enable cycle-by-cycle trip1 event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_tz1_cbc_en:1; - /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable cycle-by-cycle trip2 event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_tz2_cbc_en:1; - /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0; - * Configures whether or not to enable one-shot trip0 event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_tz0_ost_en:1; - /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0; - * Configures whether or not to enable one-shot trip1 event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_tz1_ost_en:1; - /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0; - * Configures whether or not to enable one-shot trip2 event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_tz2_ost_en:1; - /** evt_cap0_en : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable capture0 event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_cap0_en:1; - /** evt_cap1_en : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable capture1 event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_cap1_en:1; - /** evt_cap2_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable capture2 event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_cap2_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} mcpwm_evt_en_reg_t; - -/** Type of task_en register - * Task enable register - */ -typedef union { - struct { - /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable PWM generator0 timer stamp A's shadow register - * update task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_cmpr0_a_up_en:1; - /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable PWM generator1 timer stamp A's shadow register - * update task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_cmpr1_a_up_en:1; - /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable PWM generator2 timer stamp A's shadow register - * update task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_cmpr2_a_up_en:1; - /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable PWM generator0 timer stamp B's shadow register - * update task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_cmpr0_b_up_en:1; - /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable PWM generator1 timer stamp B's shadow register - * update task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_cmpr1_b_up_en:1; - /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable PWM generator2 timer stamp B's shadow register - * update task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_cmpr2_b_up_en:1; - /** task_gen_stop_en : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable all PWM generate stop task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_gen_stop_en:1; - /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable timer0 sync task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer0_sync_en:1; - /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable timer1 sync task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer1_sync_en:1; - /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable timer2 sync task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer2_sync_en:1; - /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable timer0 period update task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer0_period_up_en:1; - /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable timer1 period update task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer1_period_up_en:1; - /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable timer2 period update task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_timer2_period_up_en:1; - /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0; - * Configures whether or not to enable one shot trip0 task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_tz0_ost_en:1; - /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0; - * Configures whether or not to enable one shot trip1 task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_tz1_ost_en:1; - /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable one shot trip2 task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_tz2_ost_en:1; - /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable one shot trip0 clear task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_clr0_ost_en:1; - /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable one shot trip1 clear task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_clr1_ost_en:1; - /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0; - * Configures whether or not to enable one shot trip2 clear task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_clr2_ost_en:1; - /** task_cap0_en : R/W; bitpos: [19]; default: 0; - * Configures whether or not to enable capture0 task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_cap0_en:1; - /** task_cap1_en : R/W; bitpos: [20]; default: 0; - * Configures whether or not to enable capture1 task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_cap1_en:1; - /** task_cap2_en : R/W; bitpos: [21]; default: 0; - * Configures whether or not to enable capture2 task receive. - * 0: Disable - * 1: Enable - */ - uint32_t task_cap2_en:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} mcpwm_task_en_reg_t; - -/** Type of evt_en2 register - * Event enable register2 - */ -typedef union { - struct { - /** evt_op0_tee1_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG - * event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_op0_tee1_en:1; - /** evt_op1_tee1_en : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG - * event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_op1_tee1_en:1; - /** evt_op2_tee1_en : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG - * event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_op2_tee1_en:1; - /** evt_op0_tee2_en : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG - * event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_op0_tee2_en:1; - /** evt_op1_tee2_en : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG - * event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_op1_tee2_en:1; - /** evt_op2_tee2_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG - * event generate. - * 0: Disable - * 1: Enable - */ - uint32_t evt_op2_tee2_en:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} mcpwm_evt_en2_reg_t; - -/** Type of opn_tstmp_e1 register - * Generatorn timer stamp E1 value register - */ -typedef union { - struct { - /** opn_tstmp_e1 : R/W; bitpos: [15:0]; default: 0; - * Configures generatorn timer stamp E1 value register - */ - uint32_t opn_tstmp_e1:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_opn_tstmp_e1_reg_t; - -/** Type of opn_tstmp_e2 register - * Generatorn timer stamp E2 value register - */ -typedef union { - struct { - /** opn_tstmp_e2 : R/W; bitpos: [15:0]; default: 0; - * Configures generatorn timer stamp E2 value register - */ - uint32_t opn_tstmp_e2:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_opn_tstmp_e2_reg_t; - -/** Type of clk register - * Global configuration register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to open register clock gate. - * 0: Open the clock gate only when application writes registers - * 1: Force open the clock gate for register - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} mcpwm_clk_reg_t; - - -/** Group: Status register */ -/** Type of timern_status register - * PWM timern status register. - */ -typedef union { - struct { - /** timern_value : RO; bitpos: [15:0]; default: 0; - * Represents current PWM timern counter value. - */ - uint32_t timern_value:16; - /** timern_direction : RO; bitpos: [16]; default: 0; - * Represents current PWM timern counter direction. - * 0: Increment - * 1: Decrement - */ - uint32_t timern_direction:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} mcpwm_timern_status_reg_t; - -/** Type of fhn_status register - * Fault events status register - */ -typedef union { - struct { - /** tzn_cbc_on : RO; bitpos: [0]; default: 0; - * Represents whether or not an cycle-by-cycle mode action is on going. - * 0:No action - * 1: On going - */ - uint32_t tzn_cbc_on:1; - /** tzn_ost_on : RO; bitpos: [1]; default: 0; - * Represents whether or not an one-shot mode action is on going. - * 0:No action - * 1: On going - */ - uint32_t tzn_ost_on:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} mcpwm_fhn_status_reg_t; - -/** Type of cap_chn register - * CAPn capture value register - */ -typedef union { - struct { - /** capn_value : RO; bitpos: [31:0]; default: 0; - * Represents value of last capture on CAPn - */ - uint32_t capn_value:32; - }; - uint32_t val; -} mcpwm_cap_chn_reg_t; - -/** Type of cap_status register - * Last capture trigger edge information register - */ -typedef union { - struct { - /** cap0_edge : RO; bitpos: [0]; default: 0; - * Represents edge of last capture trigger on channel0. - * 0: Posedge - * 1: Negedge - */ - uint32_t cap0_edge:1; - /** cap1_edge : RO; bitpos: [1]; default: 0; - * Represents edge of last capture trigger on channel1. - * 0: Posedge - * 1: Negedge - */ - uint32_t cap1_edge:1; - /** cap2_edge : RO; bitpos: [2]; default: 0; - * Represents edge of last capture trigger on channel2. - * 0: Posedge - * 1: Negedge - */ - uint32_t cap2_edge:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} mcpwm_cap_status_reg_t; - - -/** Group: Interrupt register */ -/** Type of int_ena register - * Interrupt enable register - */ -typedef union { - struct { - /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops. - */ - uint32_t timer0_stop_int_ena:1; - /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops. - */ - uint32_t timer1_stop_int_ena:1; - /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops. - */ - uint32_t timer2_stop_int_ena:1; - /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event. - */ - uint32_t timer0_tez_int_ena:1; - /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event. - */ - uint32_t timer1_tez_int_ena:1; - /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event. - */ - uint32_t timer2_tez_int_ena:1; - /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event. - */ - uint32_t timer0_tep_int_ena:1; - /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event. - */ - uint32_t timer1_tep_int_ena:1; - /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event. - */ - uint32_t timer2_tep_int_ena:1; - /** fault0_int_ena : R/W; bitpos: [9]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts. - */ - uint32_t fault0_int_ena:1; - /** fault1_int_ena : R/W; bitpos: [10]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts. - */ - uint32_t fault1_int_ena:1; - /** fault2_int_ena : R/W; bitpos: [11]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts. - */ - uint32_t fault2_int_ena:1; - /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears. - */ - uint32_t fault0_clr_int_ena:1; - /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears. - */ - uint32_t fault1_clr_int_ena:1; - /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears. - */ - uint32_t fault2_clr_int_ena:1; - /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event. - */ - uint32_t cmpr0_tea_int_ena:1; - /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event. - */ - uint32_t cmpr1_tea_int_ena:1; - /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event. - */ - uint32_t cmpr2_tea_int_ena:1; - /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event. - */ - uint32_t cmpr0_teb_int_ena:1; - /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event. - */ - uint32_t cmpr1_teb_int_ena:1; - /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event. - */ - uint32_t cmpr2_teb_int_ena:1; - /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode - * action on PWM0. - */ - uint32_t tz0_cbc_int_ena:1; - /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode - * action on PWM1. - */ - uint32_t tz1_cbc_int_ena:1; - /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode - * action on PWM2. - */ - uint32_t tz2_cbc_int_ena:1; - /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on - * PWM0. - */ - uint32_t tz0_ost_int_ena:1; - /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on - * PWM1. - */ - uint32_t tz1_ost_int_ena:1; - /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on - * PWM2. - */ - uint32_t tz2_ost_int_ena:1; - /** cap0_int_ena : R/W; bitpos: [27]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0. - */ - uint32_t cap0_int_ena:1; - /** cap1_int_ena : R/W; bitpos: [28]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1. - */ - uint32_t cap1_int_ena:1; - /** cap2_int_ena : R/W; bitpos: [29]; default: 0; - * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2. - */ - uint32_t cap2_int_ena:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} mcpwm_int_ena_reg_t; - -/** Type of int_raw register - * Interrupt raw status register - */ -typedef union { - struct { - /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when the timer - * 0 stops. - */ - uint32_t timer0_stop_int_raw:1; - /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when the timer - * 1 stops. - */ - uint32_t timer1_stop_int_raw:1; - /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when the timer - * 2 stops. - */ - uint32_t timer2_stop_int_raw:1; - /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 0 TEZ event. - */ - uint32_t timer0_tez_int_raw:1; - /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 1 TEZ event. - */ - uint32_t timer1_tez_int_raw:1; - /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 2 TEZ event. - */ - uint32_t timer2_tez_int_raw:1; - /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 0 TEP event. - */ - uint32_t timer0_tep_int_raw:1; - /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 1 TEP event. - */ - uint32_t timer1_tep_int_raw:1; - /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer - * 2 TEP event. - */ - uint32_t timer2_tep_int_raw:1; - /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 - * starts. - */ - uint32_t fault0_int_raw:1; - /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 - * starts. - */ - uint32_t fault1_int_raw:1; - /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 - * starts. - */ - uint32_t fault2_int_raw:1; - /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 - * clears. - */ - uint32_t fault0_clr_int_raw:1; - /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 - * clears. - */ - uint32_t fault1_clr_int_raw:1; - /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 - * clears. - */ - uint32_t fault2_clr_int_raw:1; - /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 0 TEA event - */ - uint32_t cmpr0_tea_int_raw:1; - /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 1 TEA event - */ - uint32_t cmpr1_tea_int_raw:1; - /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 2 TEA event - */ - uint32_t cmpr2_tea_int_raw:1; - /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 0 TEB event - */ - uint32_t cmpr0_teb_int_raw:1; - /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 1 TEB event - */ - uint32_t cmpr1_teb_int_raw:1; - /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM - * operator 2 TEB event - */ - uint32_t cmpr2_teb_int_raw:1; - /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM0. - */ - uint32_t tz0_cbc_int_raw:1; - /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM1. - */ - uint32_t tz1_cbc_int_raw:1; - /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM2. - */ - uint32_t tz2_cbc_int_raw:1; - /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot - * mode action on PWM0. - */ - uint32_t tz0_ost_int_raw:1; - /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot - * mode action on PWM1. - */ - uint32_t tz1_ost_int_raw:1; - /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot - * mode action on PWM2. - */ - uint32_t tz2_ost_int_raw:1; - /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by capture on - * CAP0. - */ - uint32_t cap0_int_raw:1; - /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by capture on - * CAP1. - */ - uint32_t cap1_int_raw:1; - /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * Raw status bit: The raw interrupt status of the interrupt triggered by capture on - * CAP2. - */ - uint32_t cap2_int_raw:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} mcpwm_int_raw_reg_t; - -/** Type of int_st register - * Interrupt masked status register - */ -typedef union { - struct { - /** timer0_stop_int_st : RO; bitpos: [0]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when the - * timer 0 stops. - */ - uint32_t timer0_stop_int_st:1; - /** timer1_stop_int_st : RO; bitpos: [1]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when the - * timer 1 stops. - */ - uint32_t timer1_stop_int_st:1; - /** timer2_stop_int_st : RO; bitpos: [2]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when the - * timer 2 stops. - */ - uint32_t timer2_stop_int_st:1; - /** timer0_tez_int_st : RO; bitpos: [3]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 0 TEZ event. - */ - uint32_t timer0_tez_int_st:1; - /** timer1_tez_int_st : RO; bitpos: [4]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 1 TEZ event. - */ - uint32_t timer1_tez_int_st:1; - /** timer2_tez_int_st : RO; bitpos: [5]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 2 TEZ event. - */ - uint32_t timer2_tez_int_st:1; - /** timer0_tep_int_st : RO; bitpos: [6]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 0 TEP event. - */ - uint32_t timer0_tep_int_st:1; - /** timer1_tep_int_st : RO; bitpos: [7]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 1 TEP event. - */ - uint32_t timer1_tep_int_st:1; - /** timer2_tep_int_st : RO; bitpos: [8]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * timer 2 TEP event. - */ - uint32_t timer2_tep_int_st:1; - /** fault0_int_st : RO; bitpos: [9]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f0 starts. - */ - uint32_t fault0_int_st:1; - /** fault1_int_st : RO; bitpos: [10]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f1 starts. - */ - uint32_t fault1_int_st:1; - /** fault2_int_st : RO; bitpos: [11]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f2 starts. - */ - uint32_t fault2_int_st:1; - /** fault0_clr_int_st : RO; bitpos: [12]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f0 clears. - */ - uint32_t fault0_clr_int_st:1; - /** fault1_clr_int_st : RO; bitpos: [13]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f1 clears. - */ - uint32_t fault1_clr_int_st:1; - /** fault2_clr_int_st : RO; bitpos: [14]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered when - * event_f2 clears. - */ - uint32_t fault2_clr_int_st:1; - /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 0 TEA event - */ - uint32_t cmpr0_tea_int_st:1; - /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 1 TEA event - */ - uint32_t cmpr1_tea_int_st:1; - /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 2 TEA event - */ - uint32_t cmpr2_tea_int_st:1; - /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 0 TEB event - */ - uint32_t cmpr0_teb_int_st:1; - /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 1 TEB event - */ - uint32_t cmpr1_teb_int_st:1; - /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM - * operator 2 TEB event - */ - uint32_t cmpr2_teb_int_st:1; - /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM0. - */ - uint32_t tz0_cbc_int_st:1; - /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM1. - */ - uint32_t tz1_cbc_int_st:1; - /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * cycle-by-cycle mode action on PWM2. - */ - uint32_t tz2_cbc_int_st:1; - /** tz0_ost_int_st : RO; bitpos: [24]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * one-shot mode action on PWM0. - */ - uint32_t tz0_ost_int_st:1; - /** tz1_ost_int_st : RO; bitpos: [25]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * one-shot mode action on PWM1. - */ - uint32_t tz1_ost_int_st:1; - /** tz2_ost_int_st : RO; bitpos: [26]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by a - * one-shot mode action on PWM2. - */ - uint32_t tz2_ost_int_st:1; - /** cap0_int_st : RO; bitpos: [27]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by - * capture on CAP0. - */ - uint32_t cap0_int_st:1; - /** cap1_int_st : RO; bitpos: [28]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by - * capture on CAP1. - */ - uint32_t cap1_int_st:1; - /** cap2_int_st : RO; bitpos: [29]; default: 0; - * Masked status bit: The masked interrupt status of the interrupt triggered by - * capture on CAP2. - */ - uint32_t cap2_int_st:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} mcpwm_int_st_reg_t; - -/** Type of int_clr register - * Interrupt clear register - */ -typedef union { - struct { - /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops. - */ - uint32_t timer0_stop_int_clr:1; - /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops. - */ - uint32_t timer1_stop_int_clr:1; - /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops. - */ - uint32_t timer2_stop_int_clr:1; - /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event. - */ - uint32_t timer0_tez_int_clr:1; - /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event. - */ - uint32_t timer1_tez_int_clr:1; - /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event. - */ - uint32_t timer2_tez_int_clr:1; - /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event. - */ - uint32_t timer0_tep_int_clr:1; - /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event. - */ - uint32_t timer1_tep_int_clr:1; - /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event. - */ - uint32_t timer2_tep_int_clr:1; - /** fault0_int_clr : WT; bitpos: [9]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts. - */ - uint32_t fault0_int_clr:1; - /** fault1_int_clr : WT; bitpos: [10]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts. - */ - uint32_t fault1_int_clr:1; - /** fault2_int_clr : WT; bitpos: [11]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts. - */ - uint32_t fault2_int_clr:1; - /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears. - */ - uint32_t fault0_clr_int_clr:1; - /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears. - */ - uint32_t fault1_clr_int_clr:1; - /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears. - */ - uint32_t fault2_clr_int_clr:1; - /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event - */ - uint32_t cmpr0_tea_int_clr:1; - /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event - */ - uint32_t cmpr1_tea_int_clr:1; - /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event - */ - uint32_t cmpr2_tea_int_clr:1; - /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event - */ - uint32_t cmpr0_teb_int_clr:1; - /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event - */ - uint32_t cmpr1_teb_int_clr:1; - /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event - */ - uint32_t cmpr2_teb_int_clr:1; - /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action - * on PWM0. - */ - uint32_t tz0_cbc_int_clr:1; - /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action - * on PWM1. - */ - uint32_t tz1_cbc_int_clr:1; - /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action - * on PWM2. - */ - uint32_t tz2_cbc_int_clr:1; - /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on - * PWM0. - */ - uint32_t tz0_ost_int_clr:1; - /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on - * PWM1. - */ - uint32_t tz1_ost_int_clr:1; - /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on - * PWM2. - */ - uint32_t tz2_ost_int_clr:1; - /** cap0_int_clr : WT; bitpos: [27]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0. - */ - uint32_t cap0_int_clr:1; - /** cap1_int_clr : WT; bitpos: [28]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1. - */ - uint32_t cap1_int_clr:1; - /** cap2_int_clr : WT; bitpos: [29]; default: 0; - * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2. - */ - uint32_t cap2_int_clr:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} mcpwm_int_clr_reg_t; - - -/** Group: Version register */ -/** Type of version register - * Version register. - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 35725968; - * Configures the version. - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} mcpwm_version_reg_t; - - -typedef struct { - volatile mcpwm_clk_cfg_reg_t clk_cfg; - volatile mcpwm_timern_cfg0_reg_t timer0_cfg0; - volatile mcpwm_timern_cfg1_reg_t timer0_cfg1; - volatile mcpwm_timern_sync_reg_t timer0_sync; - volatile mcpwm_timern_status_reg_t timer0_status; - volatile mcpwm_timern_cfg0_reg_t timer1_cfg0; - volatile mcpwm_timern_cfg1_reg_t timer1_cfg1; - volatile mcpwm_timern_sync_reg_t timer1_sync; - volatile mcpwm_timern_status_reg_t timer1_status; - volatile mcpwm_timern_cfg0_reg_t timer2_cfg0; - volatile mcpwm_timern_cfg1_reg_t timer2_cfg1; - volatile mcpwm_timern_sync_reg_t timer2_sync; - volatile mcpwm_timern_status_reg_t timer2_status; - volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg; - volatile mcpwm_operator_timersel_reg_t operator_timersel; - volatile mcpwm_genn_stmp_cfg_reg_t gen0_stmp_cfg; - volatile mcpwm_genn_tstmp_a_reg_t gen0_tstmp_a; - volatile mcpwm_genn_tstmp_b_reg_t gen0_tstmp_b; - volatile mcpwm_genn_cfg0_reg_t gen0_cfg0; - volatile mcpwm_genn_force_reg_t gen0_force; - volatile mcpwm_genn_a_reg_t gen0_a; - volatile mcpwm_genn_b_reg_t gen0_b; - volatile mcpwm_dtn_cfg_reg_t dt0_cfg; - volatile mcpwm_dtn_fed_cfg_reg_t dt0_fed_cfg; - volatile mcpwm_dtn_red_cfg_reg_t dt0_red_cfg; - volatile mcpwm_carriern_cfg_reg_t carrier0_cfg; - volatile mcpwm_fhn_cfg0_reg_t fh0_cfg0; - volatile mcpwm_fhn_cfg1_reg_t fh0_cfg1; - volatile mcpwm_fhn_status_reg_t fh0_status; - volatile mcpwm_genn_stmp_cfg_reg_t gen1_stmp_cfg; - volatile mcpwm_genn_tstmp_a_reg_t gen1_tstmp_a; - volatile mcpwm_genn_tstmp_b_reg_t gen1_tstmp_b; - volatile mcpwm_genn_cfg0_reg_t gen1_cfg0; - volatile mcpwm_genn_force_reg_t gen1_force; - volatile mcpwm_genn_a_reg_t gen1_a; - volatile mcpwm_genn_b_reg_t gen1_b; - volatile mcpwm_dtn_cfg_reg_t dt1_cfg; - volatile mcpwm_dtn_fed_cfg_reg_t dt1_fed_cfg; - volatile mcpwm_dtn_red_cfg_reg_t dt1_red_cfg; - volatile mcpwm_carriern_cfg_reg_t carrier1_cfg; - volatile mcpwm_fhn_cfg0_reg_t fh1_cfg0; - volatile mcpwm_fhn_cfg1_reg_t fh1_cfg1; - volatile mcpwm_fhn_status_reg_t fh1_status; - volatile mcpwm_genn_stmp_cfg_reg_t gen2_stmp_cfg; - volatile mcpwm_genn_tstmp_a_reg_t gen2_tstmp_a; - volatile mcpwm_genn_tstmp_b_reg_t gen2_tstmp_b; - volatile mcpwm_genn_cfg0_reg_t gen2_cfg0; - volatile mcpwm_genn_force_reg_t gen2_force; - volatile mcpwm_genn_a_reg_t gen2_a; - volatile mcpwm_genn_b_reg_t gen2_b; - volatile mcpwm_dtn_cfg_reg_t dt2_cfg; - volatile mcpwm_dtn_fed_cfg_reg_t dt2_fed_cfg; - volatile mcpwm_dtn_red_cfg_reg_t dt2_red_cfg; - volatile mcpwm_carriern_cfg_reg_t carrier2_cfg; - volatile mcpwm_fhn_cfg0_reg_t fh2_cfg0; - volatile mcpwm_fhn_cfg1_reg_t fh2_cfg1; - volatile mcpwm_fhn_status_reg_t fh2_status; - volatile mcpwm_fault_detect_reg_t fault_detect; - volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg; - volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase; - volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3]; - volatile mcpwm_cap_chn_reg_t cap_chn[3]; - volatile mcpwm_cap_status_reg_t cap_status; - volatile mcpwm_update_cfg_reg_t update_cfg; - volatile mcpwm_int_ena_reg_t int_ena; - volatile mcpwm_int_raw_reg_t int_raw; - volatile mcpwm_int_st_reg_t int_st; - volatile mcpwm_int_clr_reg_t int_clr; - volatile mcpwm_evt_en_reg_t evt_en; - volatile mcpwm_task_en_reg_t task_en; - volatile mcpwm_evt_en2_reg_t evt_en2; - volatile mcpwm_opn_tstmp_e1_reg_t op0_tstmp_e1; - volatile mcpwm_opn_tstmp_e2_reg_t op0_tstmp_e2; - volatile mcpwm_opn_tstmp_e1_reg_t op1_tstmp_e1; - volatile mcpwm_opn_tstmp_e2_reg_t op1_tstmp_e2; - volatile mcpwm_opn_tstmp_e1_reg_t op2_tstmp_e1; - volatile mcpwm_opn_tstmp_e2_reg_t op2_tstmp_e2; - volatile mcpwm_clk_reg_t clk; - volatile mcpwm_version_reg_t version; -} mcpwm_dev_t; - -extern mcpwm_dev_t MCPWM0; -extern mcpwm_dev_t MCPWM1; - -#ifndef __cplusplus -_Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pcnt_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/pcnt_eco5_struct.h deleted file mode 100644 index ada36b8ff137..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/pcnt_eco5_struct.h +++ /dev/null @@ -1,504 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Register */ -/** Type of un_conf0 register - * Configuration register 0 for unit n - */ -typedef union { - struct { - /** filter_thres_un : R/W; bitpos: [9:0]; default: 16; - * This sets the maximum threshold, in APB_CLK cycles, for the filter. - * - * Any pulses with width less than this will be ignored when the filter is enabled. - */ - uint32_t filter_thres_un:10; - /** filter_en_un : R/W; bitpos: [10]; default: 1; - * This is the enable bit for unit n's input filter. - */ - uint32_t filter_en_un:1; - /** thr_zero_en_un : R/W; bitpos: [11]; default: 1; - * This is the enable bit for unit n's zero comparator. - */ - uint32_t thr_zero_en_un:1; - /** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1; - * This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable - * the high limit interrupt. - */ - uint32_t thr_h_lim_en_un:1; - /** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1; - * This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable - * the low limit interrupt. - */ - uint32_t thr_l_lim_en_un:1; - /** thr_thres0_en_un : R/W; bitpos: [14]; default: 0; - * This is the enable bit for unit n's thres0 comparator. - */ - uint32_t thr_thres0_en_un:1; - /** thr_thres1_en_un : R/W; bitpos: [15]; default: 0; - * This is the enable bit for unit n's thres1 comparator. - */ - uint32_t thr_thres1_en_un:1; - /** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0; - * This register sets the behavior when the signal input of channel 0 detects a - * negative edge. - * - * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter - */ - uint32_t ch0_neg_mode_un:2; - /** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0; - * This register sets the behavior when the signal input of channel 0 detects a - * positive edge. - * - * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter - */ - uint32_t ch0_pos_mode_un:2; - /** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0; - * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be - * modified when the control signal is high. - * - * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> - * increase).2, 3: Inhibit counter modification - */ - uint32_t ch0_hctrl_mode_un:2; - /** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0; - * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be - * modified when the control signal is low. - * - * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> - * increase).2, 3: Inhibit counter modification - */ - uint32_t ch0_lctrl_mode_un:2; - /** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0; - * This register sets the behavior when the signal input of channel 1 detects a - * negative edge. - * - * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter - */ - uint32_t ch1_neg_mode_un:2; - /** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0; - * This register sets the behavior when the signal input of channel 1 detects a - * positive edge. - * - * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter - */ - uint32_t ch1_pos_mode_un:2; - /** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0; - * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be - * modified when the control signal is high. - * - * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> - * increase).2, 3: Inhibit counter modification - */ - uint32_t ch1_hctrl_mode_un:2; - /** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0; - * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be - * modified when the control signal is low. - * - * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> - * increase).2, 3: Inhibit counter modification - */ - uint32_t ch1_lctrl_mode_un:2; - }; - uint32_t val; -} pcnt_un_conf0_reg_t; - -/** Type of un_conf1 register - * Configuration register 1 for unit n - */ -typedef union { - struct { - /** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0; - * This register is used to configure the thres0 value for unit n. - */ - uint32_t cnt_thres0_un:16; - /** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0; - * This register is used to configure the thres1 value for unit n. - */ - uint32_t cnt_thres1_un:16; - }; - uint32_t val; -} pcnt_un_conf1_reg_t; - -/** Type of un_conf2 register - * Configuration register 2 for unit n - */ -typedef union { - struct { - /** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0; - * This register is used to configure the thr_h_lim value for unit n. When pcnt - * reaches this value, the counter will be cleared to 0. - */ - uint32_t cnt_h_lim_un:16; - /** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0; - * This register is used to configure the thr_l_lim value for unit n. When pcnt - * reaches this value, the counter will be cleared to 0. - */ - uint32_t cnt_l_lim_un:16; - }; - uint32_t val; -} pcnt_un_conf2_reg_t; - -/** Type of ctrl register - * Control register for all counters - */ -typedef union { - struct { - /** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1; - * Set this bit to clear unit 0's counter. - */ - uint32_t pulse_cnt_rst_u0:1; - /** cnt_pause_u0 : R/W; bitpos: [1]; default: 0; - * Set this bit to freeze unit 0's counter. - */ - uint32_t cnt_pause_u0:1; - /** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1; - * Set this bit to clear unit 1's counter. - */ - uint32_t pulse_cnt_rst_u1:1; - /** cnt_pause_u1 : R/W; bitpos: [3]; default: 0; - * Set this bit to freeze unit 1's counter. - */ - uint32_t cnt_pause_u1:1; - /** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1; - * Set this bit to clear unit 2's counter. - */ - uint32_t pulse_cnt_rst_u2:1; - /** cnt_pause_u2 : R/W; bitpos: [5]; default: 0; - * Set this bit to freeze unit 2's counter. - */ - uint32_t cnt_pause_u2:1; - /** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1; - * Set this bit to clear unit 3's counter. - */ - uint32_t pulse_cnt_rst_u3:1; - /** cnt_pause_u3 : R/W; bitpos: [7]; default: 0; - * Set this bit to freeze unit 3's counter. - */ - uint32_t cnt_pause_u3:1; - /** dalta_change_en_u0 : R/W; bitpos: [8]; default: 0; - * Configures this bit to enable unit 0's step comparator. - */ - uint32_t dalta_change_en_u0:1; - /** dalta_change_en_u1 : R/W; bitpos: [9]; default: 0; - * Configures this bit to enable unit 1's step comparator. - */ - uint32_t dalta_change_en_u1:1; - /** dalta_change_en_u2 : R/W; bitpos: [10]; default: 0; - * Configures this bit to enable unit 2's step comparator. - */ - uint32_t dalta_change_en_u2:1; - /** dalta_change_en_u3 : R/W; bitpos: [11]; default: 0; - * Configures this bit to enable unit 3's step comparator. - */ - uint32_t dalta_change_en_u3:1; - uint32_t reserved_12:4; - /** clk_en : R/W; bitpos: [16]; default: 0; - * The registers clock gate enable signal of PCNT module. 1: the registers can be read - * and written by application. 0: the registers can not be read or written by - * application - */ - uint32_t clk_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} pcnt_ctrl_reg_t; - -/** Type of u3_change_conf register - * Configuration register for unit $n's step value. - */ -typedef union { - struct { - /** cnt_step_u3 : R/W; bitpos: [15:0]; default: 0; - * Configures the step value for unit 3. - */ - uint32_t cnt_step_u3:16; - /** cnt_step_lim_u3 : R/W; bitpos: [31:16]; default: 0; - * Configures the step limit value for unit 3. - */ - uint32_t cnt_step_lim_u3:16; - }; - uint32_t val; -} pcnt_u3_change_conf_reg_t; - -/** Type of u2_change_conf register - * Configuration register for unit $n's step value. - */ -typedef union { - struct { - /** cnt_step_u2 : R/W; bitpos: [15:0]; default: 0; - * Configures the step value for unit 2. - */ - uint32_t cnt_step_u2:16; - /** cnt_step_lim_u2 : R/W; bitpos: [31:16]; default: 0; - * Configures the step limit value for unit 2. - */ - uint32_t cnt_step_lim_u2:16; - }; - uint32_t val; -} pcnt_u2_change_conf_reg_t; - -/** Type of u1_change_conf register - * Configuration register for unit $n's step value. - */ -typedef union { - struct { - /** cnt_step_u1 : R/W; bitpos: [15:0]; default: 0; - * Configures the step value for unit 1. - */ - uint32_t cnt_step_u1:16; - /** cnt_step_lim_u1 : R/W; bitpos: [31:16]; default: 0; - * Configures the step limit value for unit 1. - */ - uint32_t cnt_step_lim_u1:16; - }; - uint32_t val; -} pcnt_u1_change_conf_reg_t; - -/** Type of u0_change_conf register - * Configuration register for unit $n's step value. - */ -typedef union { - struct { - /** cnt_step_u0 : R/W; bitpos: [15:0]; default: 0; - * Configures the step value for unit 0. - */ - uint32_t cnt_step_u0:16; - /** cnt_step_lim_u0 : R/W; bitpos: [31:16]; default: 0; - * Configures the step limit value for unit 0. - */ - uint32_t cnt_step_lim_u0:16; - }; - uint32_t val; -} pcnt_u0_change_conf_reg_t; - - -/** Group: Status Register */ -/** Type of un_cnt register - * Counter value for unit n - */ -typedef union { - struct { - /** pulse_cnt_un : RO; bitpos: [15:0]; default: 0; - * This register stores the current pulse count value for unit n. - */ - uint32_t pulse_cnt_un:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} pcnt_un_cnt_reg_t; - -/** Type of un_status register - * PNCT UNITn status register - */ -typedef union { - struct { - /** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0; - * The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases - * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter - * is negative. 3: pulse counter is positive. - */ - uint32_t cnt_thr_zero_mode_un:2; - /** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0; - * The latched value of thres1 event of PCNT_Un when threshold event interrupt is - * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: - * others - */ - uint32_t cnt_thr_thres1_lat_un:1; - /** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0; - * The latched value of thres0 event of PCNT_Un when threshold event interrupt is - * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: - * others - */ - uint32_t cnt_thr_thres0_lat_un:1; - /** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0; - * The latched value of low limit event of PCNT_Un when threshold event interrupt is - * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is - * valid. 0: others - */ - uint32_t cnt_thr_l_lim_lat_un:1; - /** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0; - * The latched value of high limit event of PCNT_Un when threshold event interrupt is - * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is - * valid. 0: others - */ - uint32_t cnt_thr_h_lim_lat_un:1; - /** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0; - * The latched value of zero threshold event of PCNT_Un when threshold event interrupt - * is valid. 1: the current pulse counter equals to 0 and zero threshold event is - * valid. 0: others - */ - uint32_t cnt_thr_zero_lat_un:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} pcnt_un_status_reg_t; - - -/** Group: Interrupt Register */ -/** Type of int_raw register - * Interrupt raw status register - */ -typedef union { - struct { - /** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. - */ - uint32_t cnt_thr_event_u0_int_raw:1; - /** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. - */ - uint32_t cnt_thr_event_u1_int_raw:1; - /** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. - */ - uint32_t cnt_thr_event_u2_int_raw:1; - /** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. - */ - uint32_t cnt_thr_event_u3_int_raw:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} pcnt_int_raw_reg_t; - -/** Type of int_st register - * Interrupt status register - */ -typedef union { - struct { - /** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. - */ - uint32_t cnt_thr_event_u0_int_st:1; - /** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. - */ - uint32_t cnt_thr_event_u1_int_st:1; - /** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. - */ - uint32_t cnt_thr_event_u2_int_st:1; - /** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. - */ - uint32_t cnt_thr_event_u3_int_st:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} pcnt_int_st_reg_t; - -/** Type of int_ena register - * Interrupt enable register - */ -typedef union { - struct { - /** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. - */ - uint32_t cnt_thr_event_u0_int_ena:1; - /** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. - */ - uint32_t cnt_thr_event_u1_int_ena:1; - /** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. - */ - uint32_t cnt_thr_event_u2_int_ena:1; - /** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. - */ - uint32_t cnt_thr_event_u3_int_ena:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} pcnt_int_ena_reg_t; - -/** Type of int_clr register - * Interrupt clear register - */ -typedef union { - struct { - /** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. - */ - uint32_t cnt_thr_event_u0_int_clr:1; - /** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. - */ - uint32_t cnt_thr_event_u1_int_clr:1; - /** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. - */ - uint32_t cnt_thr_event_u2_int_clr:1; - /** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. - */ - uint32_t cnt_thr_event_u3_int_clr:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} pcnt_int_clr_reg_t; - - -/** Group: Version Register */ -/** Type of date register - * PCNT version control register - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 35721985; - * This is the PCNT version control register. - */ - uint32_t date:32; - }; - uint32_t val; -} pcnt_date_reg_t; - - -typedef struct { - volatile pcnt_un_conf0_reg_t u0_conf0; - volatile pcnt_un_conf1_reg_t u0_conf1; - volatile pcnt_un_conf2_reg_t u0_conf2; - volatile pcnt_un_conf0_reg_t u1_conf0; - volatile pcnt_un_conf1_reg_t u1_conf1; - volatile pcnt_un_conf2_reg_t u1_conf2; - volatile pcnt_un_conf0_reg_t u2_conf0; - volatile pcnt_un_conf1_reg_t u2_conf1; - volatile pcnt_un_conf2_reg_t u2_conf2; - volatile pcnt_un_conf0_reg_t u3_conf0; - volatile pcnt_un_conf1_reg_t u3_conf1; - volatile pcnt_un_conf2_reg_t u3_conf2; - volatile pcnt_un_cnt_reg_t un_cnt[4]; - volatile pcnt_int_raw_reg_t int_raw; - volatile pcnt_int_st_reg_t int_st; - volatile pcnt_int_ena_reg_t int_ena; - volatile pcnt_int_clr_reg_t int_clr; - volatile pcnt_un_status_reg_t un_status[4]; - volatile pcnt_ctrl_reg_t ctrl; - volatile pcnt_u3_change_conf_reg_t u3_change_conf; - volatile pcnt_u2_change_conf_reg_t u2_change_conf; - volatile pcnt_u1_change_conf_reg_t u1_change_conf; - volatile pcnt_u0_change_conf_reg_t u0_change_conf; - uint32_t reserved_074[34]; - volatile pcnt_date_reg_t date; -} pcnt_dev_t; - -extern pcnt_dev_t PCNT; - -#ifndef __cplusplus -_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pcnt_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/pcnt_struct.h index 03b63407cf26..bd13068ac5ac 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/pcnt_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/pcnt_struct.h @@ -405,7 +405,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [31:0]; default: 571021568; + /** date : R/W; bitpos: [31:0]; default: 35721985; * This is the PCNT version control register. */ uint32_t date:32; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ppa_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ppa_eco5_struct.h deleted file mode 100644 index 4d0f664733cd..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/ppa_eco5_struct.h +++ /dev/null @@ -1,1025 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of blend0_clut_data register - * CLUT sram data read/write register in background plane of blender - */ -typedef union { - struct { - /** rdwr_word_blend0_clut : R/W; bitpos: [31:0]; default: 0; - * Write and read data to/from CLUT RAM in background plane of blender engine through - * this field in fifo mode. - */ - uint32_t rdwr_word_blend0_clut:32; - }; - uint32_t val; -} ppa_blend0_clut_data_reg_t; - -/** Type of blend1_clut_data register - * CLUT sram data read/write register in foreground plane of blender - */ -typedef union { - struct { - /** rdwr_word_blend1_clut : R/W; bitpos: [31:0]; default: 0; - * Write and read data to/from CLUT RAM in foreground plane of blender engine through - * this field in fifo mode. - */ - uint32_t rdwr_word_blend1_clut:32; - }; - uint32_t val; -} ppa_blend1_clut_data_reg_t; - -/** Type of clut_conf register - * CLUT configure register - */ -typedef union { - struct { - /** apb_fifo_mask : R/W; bitpos: [0]; default: 0; - * 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register - * PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: - * memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr - * should be 01 to access sr clut and should be 10 to access blend0 clut and should be - * 11 to access blend 1 clut in memory mode. - */ - uint32_t apb_fifo_mask:1; - /** blend0_clut_mem_rst : R/W; bitpos: [1]; default: 0; - * Write 1 then write 0 to this bit to reset BLEND0 CLUT. - */ - uint32_t blend0_clut_mem_rst:1; - /** blend1_clut_mem_rst : R/W; bitpos: [2]; default: 0; - * Write 1 then write 0 to this bit to reset BLEND1 CLUT. - */ - uint32_t blend1_clut_mem_rst:1; - /** blend0_clut_mem_rdaddr_rst : R/W; bitpos: [3]; default: 0; - * Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode. - */ - uint32_t blend0_clut_mem_rdaddr_rst:1; - /** blend1_clut_mem_rdaddr_rst : R/W; bitpos: [4]; default: 0; - * Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode. - */ - uint32_t blend1_clut_mem_rdaddr_rst:1; - /** blend0_clut_mem_force_pd : R/W; bitpos: [5]; default: 0; - * 1: force power down BLEND CLUT memory. - */ - uint32_t blend0_clut_mem_force_pd:1; - /** blend0_clut_mem_force_pu : R/W; bitpos: [6]; default: 0; - * 1: force power up BLEND CLUT memory. - */ - uint32_t blend0_clut_mem_force_pu:1; - /** blend0_clut_mem_clk_ena : R/W; bitpos: [7]; default: 0; - * 1: Force clock on for BLEND CLUT memory. - */ - uint32_t blend0_clut_mem_clk_ena:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ppa_clut_conf_reg_t; - -/** Type of sr_color_mode register - * Scaling and rotating engine color mode register - */ -typedef union { - struct { - /** sr_rx_cm : R/W; bitpos: [3:0]; default: 0; - * The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: - * RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. - */ - uint32_t sr_rx_cm:4; - /** sr_tx_cm : R/W; bitpos: [7:4]; default: 0; - * The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. - * 1: RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. - */ - uint32_t sr_tx_cm:4; - /** yuv_rx_range : R/W; bitpos: [8]; default: 0; - * YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range - */ - uint32_t yuv_rx_range:1; - /** yuv_tx_range : R/W; bitpos: [9]; default: 0; - * YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range - */ - uint32_t yuv_tx_range:1; - /** yuv2rgb_protocal : R/W; bitpos: [10]; default: 0; - * YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709 - */ - uint32_t yuv2rgb_protocal:1; - /** rgb2yuv_protocal : R/W; bitpos: [11]; default: 0; - * RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 - */ - uint32_t rgb2yuv_protocal:1; - /** yuv422_rx_byte_order : R/W; bitpos: [13:12]; default: 0; - * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY - */ - uint32_t yuv422_rx_byte_order:2; - uint32_t reserved_14:18; - }; - uint32_t val; -} ppa_sr_color_mode_reg_t; - -/** Type of blend_color_mode register - * blending engine color mode register - */ -typedef union { - struct { - /** blend0_rx_cm : R/W; bitpos: [3:0]; default: 0; - * The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: - * RGB565. 3: Reserved. 4: L8. 5: L4. 8: YUV420. 9: YUV422. 12:GRAY - */ - uint32_t blend0_rx_cm:4; - /** blend1_rx_cm : R/W; bitpos: [7:4]; default: 0; - * The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2: - * RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4. - */ - uint32_t blend1_rx_cm:4; - /** blend_tx_cm : R/W; bitpos: [11:8]; default: 0; - * The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: - * RGB565. 3: Reserved. 8: YUV420. 9: YUV422. 12:GRAY - */ - uint32_t blend_tx_cm:4; - /** blend0_rx_yuv_range : R/W; bitpos: [12]; default: 0; - * YUV input range when blend0 rx cm is yuv. 0: limit range. 1: full range - */ - uint32_t blend0_rx_yuv_range:1; - /** blend_tx_yuv_range : R/W; bitpos: [13]; default: 0; - * YUV output range when blend tx cm is yuv. 0: limit range. 1: full range - */ - uint32_t blend_tx_yuv_range:1; - /** blend0_rx_yuv2rgb_protocal : R/W; bitpos: [14]; default: 0; - * YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709 - */ - uint32_t blend0_rx_yuv2rgb_protocal:1; - /** blend_tx_rgb2yuv_protocal : R/W; bitpos: [15]; default: 0; - * RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709 - */ - uint32_t blend_tx_rgb2yuv_protocal:1; - /** blend0_rx_yuv422_byte_order : R/W; bitpos: [17:16]; default: 0; - * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY - */ - uint32_t blend0_rx_yuv422_byte_order:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} ppa_blend_color_mode_reg_t; - -/** Type of sr_byte_order register - * Scaling and rotating engine byte order register - */ -typedef union { - struct { - /** sr_rx_byte_swap_en : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 - * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. - */ - uint32_t sr_rx_byte_swap_en:1; - /** sr_rx_rgb_swap_en : R/W; bitpos: [1]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb - * would be swap to bgr. - */ - uint32_t sr_rx_rgb_swap_en:1; - /** sr_macro_bk_ro_bypass : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to bypass the macro block order function. This function is used - * to improve efficient accessing external memory. - */ - uint32_t sr_macro_bk_ro_bypass:1; - /** sr_bk_size_sel : R/W; bitpos: [3]; default: 0; - * sel srm pix_blk size, 0:32x32, 1:16x16 - */ - uint32_t sr_bk_size_sel:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_sr_byte_order_reg_t; - -/** Type of blend_byte_order register - * Blending engine byte order register - */ -typedef union { - struct { - /** blend0_rx_byte_swap_en : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 - * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. - */ - uint32_t blend0_rx_byte_swap_en:1; - /** blend1_rx_byte_swap_en : R/W; bitpos: [1]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 - * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. - */ - uint32_t blend1_rx_byte_swap_en:1; - /** blend0_rx_rgb_swap_en : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb - * would be swap to bgr. - */ - uint32_t blend0_rx_rgb_swap_en:1; - /** blend1_rx_rgb_swap_en : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb - * would be swap to bgr. - */ - uint32_t blend1_rx_rgb_swap_en:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_blend_byte_order_reg_t; - -/** Type of blend_trans_mode register - * Blending engine mode configure register - */ -typedef union { - struct { - /** blend_en : R/W; bitpos: [0]; default: 0; - * Set this bit to enable alpha blending. - */ - uint32_t blend_en:1; - /** blend_bypass : R/W; bitpos: [1]; default: 0; - * Set this bit to bypass blender. Then background date would be output. - */ - uint32_t blend_bypass:1; - /** blend_fix_pixel_fill_en : R/W; bitpos: [2]; default: 0; - * This bit is used to enable fix pixel filling. When this mode is enable only Tx - * channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL. - */ - uint32_t blend_fix_pixel_fill_en:1; - /** blend_trans_mode_update : WT; bitpos: [3]; default: 0; - * Set this bit to update the transfer mode. Only the bit is set the transfer mode is - * valid. - */ - uint32_t blend_trans_mode_update:1; - /** blend_rst : R/W; bitpos: [4]; default: 0; - * write 1 then write 0 to reset blending engine. - */ - uint32_t blend_rst:1; - /** blend_tx_inf_sel : R/W; bitpos: [6:5]; default: 0; - * unused ! Configures blend tx interface. 0: dma2d only, 1: le_enc only, 2: dma2d and - * ls_enc - */ - uint32_t blend_tx_inf_sel:2; - uint32_t reserved_7:25; - }; - uint32_t val; -} ppa_blend_trans_mode_reg_t; - -/** Type of sr_fix_alpha register - * Scaling and rotating engine alpha override register - */ -typedef union { - struct { - /** sr_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128; - * The value would replace the alpha value in received pixel for Scaling and Rotating - * engine when PPA_SR_RX_ALPHA_CONF_EN is enabled. - */ - uint32_t sr_rx_fix_alpha:8; - /** sr_rx_alpha_mod : R/W; bitpos: [9:8]; default: 0; - * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. - */ - uint32_t sr_rx_alpha_mod:2; - /** sr_rx_alpha_inv : R/W; bitpos: [10]; default: 0; - * Set this bit to invert the original alpha value. When RX color mode is - * RGB565/RGB88. The original alpha value is 255. - */ - uint32_t sr_rx_alpha_inv:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} ppa_sr_fix_alpha_reg_t; - -/** Type of blend_tx_size register - * Fix pixel filling mode image size register - */ -typedef union { - struct { - /** blend_hb : R/W; bitpos: [13:0]; default: 0; - * The horizontal width of image block that would be filled in fix pixel filling mode - * or blend mode. The unit is pixel. Must be even num when YUV422 or YUV420 - */ - uint32_t blend_hb:14; - /** blend_vb : R/W; bitpos: [27:14]; default: 0; - * The vertical width of image block that would be filled in fix pixel filling mode or - * blend mode. The unit is pixel. Must be even num when YUV420 - */ - uint32_t blend_vb:14; - uint32_t reserved_28:4; - }; - uint32_t val; -} ppa_blend_tx_size_reg_t; - -/** Type of blend_fix_alpha register - * Blending engine alpha override register - */ -typedef union { - struct { - /** blend0_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128; - * The value would replace the alpha value in received pixel for background plane of - * blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled. - */ - uint32_t blend0_rx_fix_alpha:8; - /** blend1_rx_fix_alpha : R/W; bitpos: [15:8]; default: 128; - * The value would replace the alpha value in received pixel for foreground plane of - * blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled. - */ - uint32_t blend1_rx_fix_alpha:8; - /** blend0_rx_alpha_mod : R/W; bitpos: [17:16]; default: 0; - * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. - */ - uint32_t blend0_rx_alpha_mod:2; - /** blend1_rx_alpha_mod : R/W; bitpos: [19:18]; default: 0; - * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. - */ - uint32_t blend1_rx_alpha_mod:2; - /** blend0_rx_alpha_inv : R/W; bitpos: [20]; default: 0; - * Set this bit to invert the original alpha value. When RX color mode is - * RGB565/RGB88. The original alpha value is 255. - */ - uint32_t blend0_rx_alpha_inv:1; - /** blend1_rx_alpha_inv : R/W; bitpos: [21]; default: 0; - * Set this bit to invert the original alpha value. When RX color mode is - * RGB565/RGB88. The original alpha value is 255. - */ - uint32_t blend1_rx_alpha_inv:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} ppa_blend_fix_alpha_reg_t; - -/** Type of blend_rgb register - * RGB color register - */ -typedef union { - struct { - /** blend1_rx_b : R/W; bitpos: [7:0]; default: 128; - * blue color for A4/A8 mode. - */ - uint32_t blend1_rx_b:8; - /** blend1_rx_g : R/W; bitpos: [15:8]; default: 128; - * green color for A4/A8 mode. - */ - uint32_t blend1_rx_g:8; - /** blend1_rx_r : R/W; bitpos: [23:16]; default: 128; - * red color for A4/A8 mode. - */ - uint32_t blend1_rx_r:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_blend_rgb_reg_t; - -/** Type of blend_fix_pixel register - * Blending engine fix pixel register - */ -typedef union { - struct { - /** blend_tx_fix_pixel : R/W; bitpos: [31:0]; default: 0; - * The configure fix pixel in fix pixel filling mode for blender engine. - */ - uint32_t blend_tx_fix_pixel:32; - }; - uint32_t val; -} ppa_blend_fix_pixel_reg_t; - -/** Type of ck_fg_low register - * foreground color key lower threshold - */ -typedef union { - struct { - /** colorkey_fg_b_low : R/W; bitpos: [7:0]; default: 255; - * color key lower threshold of foreground b channel - */ - uint32_t colorkey_fg_b_low:8; - /** colorkey_fg_g_low : R/W; bitpos: [15:8]; default: 255; - * color key lower threshold of foreground g channel - */ - uint32_t colorkey_fg_g_low:8; - /** colorkey_fg_r_low : R/W; bitpos: [23:16]; default: 255; - * color key lower threshold of foreground r channel - */ - uint32_t colorkey_fg_r_low:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_ck_fg_low_reg_t; - -/** Type of ck_fg_high register - * foreground color key higher threshold - */ -typedef union { - struct { - /** colorkey_fg_b_high : R/W; bitpos: [7:0]; default: 0; - * color key higher threshold of foreground b channel - */ - uint32_t colorkey_fg_b_high:8; - /** colorkey_fg_g_high : R/W; bitpos: [15:8]; default: 0; - * color key higher threshold of foreground g channel - */ - uint32_t colorkey_fg_g_high:8; - /** colorkey_fg_r_high : R/W; bitpos: [23:16]; default: 0; - * color key higher threshold of foreground r channel - */ - uint32_t colorkey_fg_r_high:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_ck_fg_high_reg_t; - -/** Type of ck_bg_low register - * background color key lower threshold - */ -typedef union { - struct { - /** colorkey_bg_b_low : R/W; bitpos: [7:0]; default: 255; - * color key lower threshold of background b channel - */ - uint32_t colorkey_bg_b_low:8; - /** colorkey_bg_g_low : R/W; bitpos: [15:8]; default: 255; - * color key lower threshold of background g channel - */ - uint32_t colorkey_bg_g_low:8; - /** colorkey_bg_r_low : R/W; bitpos: [23:16]; default: 255; - * color key lower threshold of background r channel - */ - uint32_t colorkey_bg_r_low:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_ck_bg_low_reg_t; - -/** Type of ck_bg_high register - * background color key higher threshold - */ -typedef union { - struct { - /** colorkey_bg_b_high : R/W; bitpos: [7:0]; default: 0; - * color key higher threshold of background b channel - */ - uint32_t colorkey_bg_b_high:8; - /** colorkey_bg_g_high : R/W; bitpos: [15:8]; default: 0; - * color key higher threshold of background g channel - */ - uint32_t colorkey_bg_g_high:8; - /** colorkey_bg_r_high : R/W; bitpos: [23:16]; default: 0; - * color key higher threshold of background r channel - */ - uint32_t colorkey_bg_r_high:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_ck_bg_high_reg_t; - -/** Type of ck_default register - * default value when foreground and background both in color key range - */ -typedef union { - struct { - /** colorkey_default_b : R/W; bitpos: [7:0]; default: 0; - * default B channel value of color key - */ - uint32_t colorkey_default_b:8; - /** colorkey_default_g : R/W; bitpos: [15:8]; default: 0; - * default G channel value of color key - */ - uint32_t colorkey_default_g:8; - /** colorkey_default_r : R/W; bitpos: [23:16]; default: 0; - * default R channel value of color key - */ - uint32_t colorkey_default_r:8; - /** colorkey_fg_bg_reverse : R/W; bitpos: [24]; default: 0; - * when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the - * result is fg - */ - uint32_t colorkey_fg_bg_reverse:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} ppa_ck_default_reg_t; - -/** Type of sr_scal_rotate register - * Scaling and rotating coefficient register - */ -typedef union { - struct { - /** sr_scal_x_int : R/W; bitpos: [7:0]; default: 1; - * The integrated part of scaling coefficient in X direction. - */ - uint32_t sr_scal_x_int:8; - /** sr_scal_x_frag : R/W; bitpos: [11:8]; default: 0; - * The fragment part of scaling coefficient in X direction. - */ - uint32_t sr_scal_x_frag:4; - /** sr_scal_y_int : R/W; bitpos: [19:12]; default: 1; - * The integrated part of scaling coefficient in Y direction. - */ - uint32_t sr_scal_y_int:8; - /** sr_scal_y_frag : R/W; bitpos: [23:20]; default: 0; - * The fragment part of scaling coefficient in Y direction. - */ - uint32_t sr_scal_y_frag:4; - /** sr_rotate_angle : R/W; bitpos: [25:24]; default: 0; - * The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree. - */ - uint32_t sr_rotate_angle:2; - /** scal_rotate_rst : R/W; bitpos: [26]; default: 0; - * Write 1 then write 0 to this bit to reset scaling and rotating engine. - */ - uint32_t scal_rotate_rst:1; - /** scal_rotate_start : WT; bitpos: [27]; default: 0; - * Write 1 to enable scaling and rotating engine after parameter is configured. - */ - uint32_t scal_rotate_start:1; - /** sr_mirror_x : R/W; bitpos: [28]; default: 0; - * Image mirror in X direction. 0: disable, 1: enable - */ - uint32_t sr_mirror_x:1; - /** sr_mirror_y : R/W; bitpos: [29]; default: 0; - * Image mirror in Y direction. 0: disable, 1: enable - */ - uint32_t sr_mirror_y:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} ppa_sr_scal_rotate_reg_t; - -/** Type of sr_mem_pd register - * SR memory power done register - */ -typedef union { - struct { - /** sr_mem_clk_ena : R/W; bitpos: [0]; default: 0; - * Set this bit to force clock enable of scaling and rotating engine's data memory. - */ - uint32_t sr_mem_clk_ena:1; - /** sr_mem_force_pd : R/W; bitpos: [1]; default: 0; - * Set this bit to force power down scaling and rotating engine's data memory. - */ - uint32_t sr_mem_force_pd:1; - /** sr_mem_force_pu : R/W; bitpos: [2]; default: 0; - * Set this bit to force power up scaling and rotating engine's data memory. - */ - uint32_t sr_mem_force_pu:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} ppa_sr_mem_pd_reg_t; - -/** Type of reg_conf register - * Register clock enable register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * PPA register clock gate enable signal. - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ppa_reg_conf_reg_t; - -/** Type of eco_low register - * Reserved. - */ -typedef union { - struct { - /** rnd_eco_low : R/W; bitpos: [31:0]; default: 0; - * Reserved. - */ - uint32_t rnd_eco_low:32; - }; - uint32_t val; -} ppa_eco_low_reg_t; - -/** Type of eco_high register - * Reserved. - */ -typedef union { - struct { - /** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295; - * Reserved. - */ - uint32_t rnd_eco_high:32; - }; - uint32_t val; -} ppa_eco_high_reg_t; - -/** Type of sram_ctrl register - * PPA SRAM Control Register - */ -typedef union { - struct { - /** mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; - * Control signals - */ - uint32_t mem_aux_ctrl:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} ppa_sram_ctrl_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of int_raw register - * Raw status interrupt - */ -typedef union { - struct { - /** sr_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when scaling and rotating engine - * calculate one frame image. - */ - uint32_t sr_eof_int_raw:1; - /** blend_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when blending engine calculate one frame - * image. - */ - uint32_t blend_eof_int_raw:1; - /** sr_param_cfg_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the configured scaling and rotating - * coefficient is wrong. User can check the reasons through register - * PPA_SR_PARAM_ERR_ST_REG. - */ - uint32_t sr_param_cfg_err_int_raw:1; - /** blend_param_cfg_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when the configured blending coefficient - * is wrong. User can check the reasons through register PPA_BLEND_ST_REG. - */ - uint32_t blend_param_cfg_err_int_raw:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_int_raw_reg_t; - -/** Type of int_st register - * Masked interrupt - */ -typedef union { - struct { - /** sr_eof_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the PPA_SR_EOF_INT interrupt. - */ - uint32_t sr_eof_int_st:1; - /** blend_eof_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt. - */ - uint32_t blend_eof_int_st:1; - /** sr_param_cfg_err_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. - */ - uint32_t sr_param_cfg_err_int_st:1; - /** blend_param_cfg_err_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. - */ - uint32_t blend_param_cfg_err_int_st:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_int_st_reg_t; - -/** Type of int_ena register - * Interrupt enable bits - */ -typedef union { - struct { - /** sr_eof_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the PPA_SR_EOF_INT interrupt. - */ - uint32_t sr_eof_int_ena:1; - /** blend_eof_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt. - */ - uint32_t blend_eof_int_ena:1; - /** sr_param_cfg_err_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. - */ - uint32_t sr_param_cfg_err_int_ena:1; - /** blend_param_cfg_err_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. - */ - uint32_t blend_param_cfg_err_int_ena:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_int_ena_reg_t; - -/** Type of int_clr register - * Interrupt clear bits - */ -typedef union { - struct { - /** sr_eof_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the PPA_SR_EOF_INT interrupt. - */ - uint32_t sr_eof_int_clr:1; - /** blend_eof_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the PPA_BLEND_EOF_INT interrupt. - */ - uint32_t blend_eof_int_clr:1; - /** sr_param_cfg_err_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. - */ - uint32_t sr_param_cfg_err_int_clr:1; - /** blend_param_cfg_err_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. - */ - uint32_t blend_param_cfg_err_int_clr:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_int_clr_reg_t; - - -/** Group: Status Registers */ -/** Type of clut_cnt register - * BLEND CLUT write counter register - */ -typedef union { - struct { - /** blend0_clut_cnt : RO; bitpos: [8:0]; default: 0; - * The write data counter of BLEND0 CLUT in fifo mode. - */ - uint32_t blend0_clut_cnt:9; - /** blend1_clut_cnt : RO; bitpos: [17:9]; default: 0; - * The write data counter of BLEND1 CLUT in fifo mode. - */ - uint32_t blend1_clut_cnt:9; - uint32_t reserved_18:14; - }; - uint32_t val; -} ppa_clut_cnt_reg_t; - -/** Type of blend_st register - * Blending engine status register - */ -typedef union { - struct { - /** blend_size_diff_st : RO; bitpos: [0]; default: 0; - * 1: indicate the size of two image is different. - */ - uint32_t blend_size_diff_st:1; - /** blend_yuv_x_scale_err_st : RO; bitpos: [1]; default: 0; - * Represents that x param is an odd num when enable yuv422 or yuv420 - */ - uint32_t blend_yuv_x_scale_err_st:1; - /** blend_yuv_y_scale_err_st : RO; bitpos: [2]; default: 0; - * Represents that y param is an odd num when enable yuv420 - */ - uint32_t blend_yuv_y_scale_err_st:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} ppa_blend_st_reg_t; - -/** Type of sr_param_err_st register - * Scaling and rotating coefficient error register - */ -typedef union { - struct { - /** tx_dscr_vb_err_st : RO; bitpos: [0]; default: 0; - * The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive - * descriptor is larger than VA in 2DDMA receive descriptor. - */ - uint32_t tx_dscr_vb_err_st:1; - /** tx_dscr_hb_err_st : RO; bitpos: [1]; default: 0; - * The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive - * descriptor is larger than HA in 2DDMA receive descriptor. - */ - uint32_t tx_dscr_hb_err_st:1; - /** y_rx_scal_equal_0_err_st : RO; bitpos: [2]; default: 0; - * The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0. - */ - uint32_t y_rx_scal_equal_0_err_st:1; - /** rx_dscr_vb_err_st : RO; bitpos: [3]; default: 0; - * The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in - * 2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor - */ - uint32_t rx_dscr_vb_err_st:1; - /** ydst_len_too_samll_err_st : RO; bitpos: [4]; default: 0; - * The error is that the scaled image width is 0. For example. when source width is - * 14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as - * the result would be floored. - */ - uint32_t ydst_len_too_samll_err_st:1; - /** ydst_len_too_large_err_st : RO; bitpos: [5]; default: 0; - * The error is that the scaled width is larger than (2^13 - 1). - */ - uint32_t ydst_len_too_large_err_st:1; - /** x_rx_scal_equal_0_err_st : RO; bitpos: [6]; default: 0; - * The error is that the scaled image height is 0. - */ - uint32_t x_rx_scal_equal_0_err_st:1; - /** rx_dscr_hb_err_st : RO; bitpos: [7]; default: 0; - * The error is that the HB in 2DDMA transmit descriptor plus the offset of X - * coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit - * descriptor. - */ - uint32_t rx_dscr_hb_err_st:1; - /** xdst_len_too_samll_err_st : RO; bitpos: [8]; default: 0; - * The error is that the scaled image height is 0. For example. when source height is - * 14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as - * the result would be floored. - */ - uint32_t xdst_len_too_samll_err_st:1; - /** xdst_len_too_large_err_st : RO; bitpos: [9]; default: 0; - * The error is that the scaled image height is larger than (2^13 - 1). - */ - uint32_t xdst_len_too_large_err_st:1; - /** x_yuv420_rx_scale_err_st : RO; bitpos: [10]; default: 0; - * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable - * yuv422 or yuv420 rx - */ - uint32_t x_yuv420_rx_scale_err_st:1; - /** y_yuv420_rx_scale_err_st : RO; bitpos: [11]; default: 0; - * The error is that the va/vb/y param in dma2d descriptor is an odd num when enable - * yuv420 rx - */ - uint32_t y_yuv420_rx_scale_err_st:1; - /** x_yuv420_tx_scale_err_st : RO; bitpos: [12]; default: 0; - * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable - * yuv422 or yuv420 tx - */ - uint32_t x_yuv420_tx_scale_err_st:1; - /** y_yuv420_tx_scale_err_st : RO; bitpos: [13]; default: 0; - * The error is that the va/vb/y param in dma2d descriptor is an odd num when enable - * yuv420 tx - */ - uint32_t y_yuv420_tx_scale_err_st:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} ppa_sr_param_err_st_reg_t; - -/** Type of sr_status register - * SR FSM register - */ -typedef union { - struct { - /** sr_rx_dscr_sample_state : RO; bitpos: [1:0]; default: 0; - * Reserved. - */ - uint32_t sr_rx_dscr_sample_state:2; - /** sr_rx_scan_state : RO; bitpos: [3:2]; default: 0; - * Reserved. - */ - uint32_t sr_rx_scan_state:2; - /** sr_tx_dscr_sample_state : RO; bitpos: [5:4]; default: 0; - * Reserved. - */ - uint32_t sr_tx_dscr_sample_state:2; - /** sr_tx_scan_state : RO; bitpos: [8:6]; default: 0; - * Reserved. - */ - uint32_t sr_tx_scan_state:3; - uint32_t reserved_9:23; - }; - uint32_t val; -} ppa_sr_status_reg_t; - -/** Type of eco_cell_ctrl register - * Reserved. - */ -typedef union { - struct { - /** rdn_result : RO; bitpos: [0]; default: 0; - * Reserved. - */ - uint32_t rdn_result:1; - /** rdn_ena : R/W; bitpos: [1]; default: 0; - * Reserved. - */ - uint32_t rdn_ena:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} ppa_eco_cell_ctrl_reg_t; - - -/** Group: Debug Register */ -/** Type of debug_ctrl0 register - * debug register - */ -typedef union { - struct { - /** dbg_replace_sel : R/W; bitpos: [2:0]; default: 0; - * Configures the data replace location. 0: not replace, 1: srm rx input, 2: srm rx - * bilin interpolation, 3: srm tx output, 4: blend fg input, 5: blend bg input, 6: - * blend output - */ - uint32_t dbg_replace_sel:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} ppa_debug_ctrl0_reg_t; - -/** Type of debug_ctrl1 register - * debug register - */ -typedef union { - struct { - /** dbg_replace_data : R/W; bitpos: [31:0]; default: 0; - * Configures the replace data - */ - uint32_t dbg_replace_data:32; - }; - uint32_t val; -} ppa_debug_ctrl1_reg_t; - - -/** Group: Configuration Register */ -/** Type of rgb2gray register - * rgb2gray register - */ -typedef union { - struct { - /** rgb2gray_b : R/W; bitpos: [7:0]; default: 85; - * Configures the b parameter for rgb2gray - */ - uint32_t rgb2gray_b:8; - /** rgb2gray_g : R/W; bitpos: [15:8]; default: 86; - * Configures the g parameter for rgb2gray - */ - uint32_t rgb2gray_g:8; - /** rgb2gray_r : R/W; bitpos: [23:16]; default: 85; - * Configures the r parameter for rgb2gray - */ - uint32_t rgb2gray_r:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_rgb2gray_reg_t; - - -/** Group: Version Register */ -/** Type of date register - * PPA Version register - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 539234848; - * register version. - */ - uint32_t date:32; - }; - uint32_t val; -} ppa_date_reg_t; - - -typedef struct ppa_dev_t { - volatile ppa_blend0_clut_data_reg_t blend0_clut_data; - volatile ppa_blend1_clut_data_reg_t blend1_clut_data; - uint32_t reserved_008; - volatile ppa_clut_conf_reg_t clut_conf; - volatile ppa_int_raw_reg_t int_raw; - volatile ppa_int_st_reg_t int_st; - volatile ppa_int_ena_reg_t int_ena; - volatile ppa_int_clr_reg_t int_clr; - volatile ppa_sr_color_mode_reg_t sr_color_mode; - volatile ppa_blend_color_mode_reg_t blend_color_mode; - volatile ppa_sr_byte_order_reg_t sr_byte_order; - volatile ppa_blend_byte_order_reg_t blend_byte_order; - uint32_t reserved_030; - volatile ppa_blend_trans_mode_reg_t blend_trans_mode; - volatile ppa_sr_fix_alpha_reg_t sr_fix_alpha; - volatile ppa_blend_tx_size_reg_t blend_tx_size; - volatile ppa_blend_fix_alpha_reg_t blend_fix_alpha; - uint32_t reserved_044; - volatile ppa_blend_rgb_reg_t blend_rgb; - volatile ppa_blend_fix_pixel_reg_t blend_fix_pixel; - volatile ppa_ck_fg_low_reg_t ck_fg_low; - volatile ppa_ck_fg_high_reg_t ck_fg_high; - volatile ppa_ck_bg_low_reg_t ck_bg_low; - volatile ppa_ck_bg_high_reg_t ck_bg_high; - volatile ppa_ck_default_reg_t ck_default; - volatile ppa_sr_scal_rotate_reg_t sr_scal_rotate; - volatile ppa_sr_mem_pd_reg_t sr_mem_pd; - volatile ppa_reg_conf_reg_t reg_conf; - volatile ppa_clut_cnt_reg_t clut_cnt; - volatile ppa_blend_st_reg_t blend_st; - volatile ppa_sr_param_err_st_reg_t sr_param_err_st; - volatile ppa_sr_status_reg_t sr_status; - volatile ppa_eco_low_reg_t eco_low; - volatile ppa_eco_high_reg_t eco_high; - volatile ppa_eco_cell_ctrl_reg_t eco_cell_ctrl; - volatile ppa_sram_ctrl_reg_t sram_ctrl; - volatile ppa_debug_ctrl0_reg_t debug_ctrl0; - volatile ppa_debug_ctrl1_reg_t debug_ctrl1; - volatile ppa_rgb2gray_reg_t rgb2gray; - uint32_t reserved_09c[25]; - volatile ppa_date_reg_t date; -} ppa_dev_t; - -extern ppa_dev_t PPA; - -#ifndef __cplusplus -_Static_assert(sizeof(ppa_dev_t) == 0x104, "Invalid size of ppa_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h index f843b5b49d83..a1ae216013e8 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h @@ -43,10 +43,9 @@ extern "C" { #define PPA_CLUT_CONF_REG (DR_REG_PPA_BASE + 0xc) /** PPA_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0; * 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register - * PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: - * memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr - * should be 01 to access sr clut and should be 10 to access blend0 clut and should be - * 11 to access blend 1 clut in memory mode. + * PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: + * memory mode to wr/rd blend0/blend1 clut RAM. The bit 11 and 10 of the waddr + * should be 01 to access blend0 clut and should be 10 to access blend1 clut in memory mode. */ #define PPA_APB_FIFO_MASK (BIT(0)) #define PPA_APB_FIFO_MASK_M (PPA_APB_FIFO_MASK_V << PPA_APB_FIFO_MASK_S) @@ -225,7 +224,7 @@ extern "C" { #define PPA_BLEND_EOF_INT_CLR_V 0x00000001U #define PPA_BLEND_EOF_INT_CLR_S 1 /** PPA_SR_PARAM_CFG_ERR_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. + * Set this bit to clear the PPA_SR_PARAM_CFG_ERR_INT interrupt. */ #define PPA_SR_PARAM_CFG_ERR_INT_CLR (BIT(2)) #define PPA_SR_PARAM_CFG_ERR_INT_CLR_M (PPA_SR_PARAM_CFG_ERR_INT_CLR_V << PPA_SR_PARAM_CFG_ERR_INT_CLR_S) @@ -273,22 +272,22 @@ extern "C" { #define PPA_YUV_TX_RANGE_M (PPA_YUV_TX_RANGE_V << PPA_YUV_TX_RANGE_S) #define PPA_YUV_TX_RANGE_V 0x00000001U #define PPA_YUV_TX_RANGE_S 9 -/** PPA_YUV2RGB_PROTOCAL : R/W; bitpos: [10]; default: 0; +/** PPA_YUV2RGB_PROTOCOL : R/W; bitpos: [10]; default: 0; * YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709 */ -#define PPA_YUV2RGB_PROTOCAL (BIT(10)) -#define PPA_YUV2RGB_PROTOCAL_M (PPA_YUV2RGB_PROTOCAL_V << PPA_YUV2RGB_PROTOCAL_S) -#define PPA_YUV2RGB_PROTOCAL_V 0x00000001U -#define PPA_YUV2RGB_PROTOCAL_S 10 -/** PPA_RGB2YUV_PROTOCAL : R/W; bitpos: [11]; default: 0; +#define PPA_YUV2RGB_PROTOCOL (BIT(10)) +#define PPA_YUV2RGB_PROTOCOL_M (PPA_YUV2RGB_PROTOCOL_V << PPA_YUV2RGB_PROTOCOL_S) +#define PPA_YUV2RGB_PROTOCOL_V 0x00000001U +#define PPA_YUV2RGB_PROTOCOL_S 10 +/** PPA_RGB2YUV_PROTOCOL : R/W; bitpos: [11]; default: 0; * RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 */ -#define PPA_RGB2YUV_PROTOCAL (BIT(11)) -#define PPA_RGB2YUV_PROTOCAL_M (PPA_RGB2YUV_PROTOCAL_V << PPA_RGB2YUV_PROTOCAL_S) -#define PPA_RGB2YUV_PROTOCAL_V 0x00000001U -#define PPA_RGB2YUV_PROTOCAL_S 11 +#define PPA_RGB2YUV_PROTOCOL (BIT(11)) +#define PPA_RGB2YUV_PROTOCOL_M (PPA_RGB2YUV_PROTOCOL_V << PPA_RGB2YUV_PROTOCOL_S) +#define PPA_RGB2YUV_PROTOCOL_V 0x00000001U +#define PPA_RGB2YUV_PROTOCOL_S 11 /** PPA_YUV422_RX_BYTE_ORDER : R/W; bitpos: [13:12]; default: 0; - * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr) */ #define PPA_YUV422_RX_BYTE_ORDER 0x00000003U #define PPA_YUV422_RX_BYTE_ORDER_M (PPA_YUV422_RX_BYTE_ORDER_V << PPA_YUV422_RX_BYTE_ORDER_S) @@ -337,22 +336,22 @@ extern "C" { #define PPA_BLEND_TX_YUV_RANGE_M (PPA_BLEND_TX_YUV_RANGE_V << PPA_BLEND_TX_YUV_RANGE_S) #define PPA_BLEND_TX_YUV_RANGE_V 0x00000001U #define PPA_BLEND_TX_YUV_RANGE_S 13 -/** PPA_BLEND0_RX_YUV2RGB_PROTOCAL : R/W; bitpos: [14]; default: 0; +/** PPA_BLEND0_RX_YUV2RGB_PROTOCOL : R/W; bitpos: [14]; default: 0; * YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709 */ -#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL (BIT(14)) -#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_M (PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V << PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S) -#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V 0x00000001U -#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S 14 -/** PPA_BLEND_TX_RGB2YUV_PROTOCAL : R/W; bitpos: [15]; default: 0; +#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL (BIT(14)) +#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_M (PPA_BLEND0_RX_YUV2RGB_PROTOCOL_V << PPA_BLEND0_RX_YUV2RGB_PROTOCOL_S) +#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_V 0x00000001U +#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_S 14 +/** PPA_BLEND_TX_RGB2YUV_PROTOCOL : R/W; bitpos: [15]; default: 0; * RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709 */ -#define PPA_BLEND_TX_RGB2YUV_PROTOCAL (BIT(15)) -#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_M (PPA_BLEND_TX_RGB2YUV_PROTOCAL_V << PPA_BLEND_TX_RGB2YUV_PROTOCAL_S) -#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_V 0x00000001U -#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_S 15 +#define PPA_BLEND_TX_RGB2YUV_PROTOCOL (BIT(15)) +#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_M (PPA_BLEND_TX_RGB2YUV_PROTOCOL_V << PPA_BLEND_TX_RGB2YUV_PROTOCOL_S) +#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_V 0x00000001U +#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_S 15 /** PPA_BLEND0_RX_YUV422_BYTE_ORDER : R/W; bitpos: [17:16]; default: 0; - * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr) */ #define PPA_BLEND0_RX_YUV422_BYTE_ORDER 0x00000003U #define PPA_BLEND0_RX_YUV422_BYTE_ORDER_M (PPA_BLEND0_RX_YUV422_BYTE_ORDER_V << PPA_BLEND0_RX_YUV422_BYTE_ORDER_S) @@ -554,7 +553,7 @@ extern "C" { #define PPA_BLEND1_RX_FIX_ALPHA_S 8 /** PPA_BLEND0_RX_ALPHA_MOD : R/W; bitpos: [17:16]; default: 0; * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + * Original alpha multiply with PPA_SR_BLEND0_ALPHA/256. */ #define PPA_BLEND0_RX_ALPHA_MOD 0x00000003U #define PPA_BLEND0_RX_ALPHA_MOD_M (PPA_BLEND0_RX_ALPHA_MOD_V << PPA_BLEND0_RX_ALPHA_MOD_S) @@ -562,7 +561,7 @@ extern "C" { #define PPA_BLEND0_RX_ALPHA_MOD_S 16 /** PPA_BLEND1_RX_ALPHA_MOD : R/W; bitpos: [19:18]; default: 0; * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + * Original alpha multiply with PPA_SR_BLEND1_ALPHA/256. */ #define PPA_BLEND1_RX_ALPHA_MOD 0x00000003U #define PPA_BLEND1_RX_ALPHA_MOD_M (PPA_BLEND1_RX_ALPHA_MOD_V << PPA_BLEND1_RX_ALPHA_MOD_S) diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h index fe85942a62d3..b65bff4e4b99 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h @@ -91,12 +91,12 @@ typedef union { struct { /** sr_rx_cm : R/W; bitpos: [3:0]; default: 0; * The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: - * RGB888. 2: RGB565. 8: YUV420. others: Reserved. + * RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. */ uint32_t sr_rx_cm:4; /** sr_tx_cm : R/W; bitpos: [7:4]; default: 0; * The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. - * 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved. + * 1: RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. */ uint32_t sr_tx_cm:4; /** yuv_rx_range : R/W; bitpos: [8]; default: 0; @@ -115,7 +115,11 @@ typedef union { * RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 */ uint32_t rgb2yuv_protocol:1; - uint32_t reserved_12:20; + /** yuv422_rx_byte_order : R/W; bitpos: [13:12]; default: 0; + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr) + */ + uint32_t yuv422_rx_byte_order:2; + uint32_t reserved_14:18; }; uint32_t val; } ppa_sr_color_mode_reg_t; @@ -127,7 +131,7 @@ typedef union { struct { /** blend0_rx_cm : R/W; bitpos: [3:0]; default: 0; * The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: - * RGB565. 3: Reserved. 4: L8. 5: L4. + * RGB565. 3: Reserved. 4: L8. 5: L4. 8: YUV420. 9: YUV422. 12:GRAY */ uint32_t blend0_rx_cm:4; /** blend1_rx_cm : R/W; bitpos: [7:4]; default: 0; @@ -137,10 +141,30 @@ typedef union { uint32_t blend1_rx_cm:4; /** blend_tx_cm : R/W; bitpos: [11:8]; default: 0; * The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: - * RGB565. 3: Reserved.. + * RGB565. 3: Reserved. 8: YUV420. 9: YUV422. 12:GRAY */ uint32_t blend_tx_cm:4; - uint32_t reserved_12:20; + /** blend0_rx_yuv_range : R/W; bitpos: [12]; default: 0; + * YUV input range when blend0 rx cm is yuv. 0: limit range. 1: full range + */ + uint32_t blend0_rx_yuv_range:1; + /** blend_tx_yuv_range : R/W; bitpos: [13]; default: 0; + * YUV output range when blend tx cm is yuv. 0: limit range. 1: full range + */ + uint32_t blend_tx_yuv_range:1; + /** blend0_rx_yuv2rgb_protocol : R/W; bitpos: [14]; default: 0; + * YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709 + */ + uint32_t blend0_rx_yuv2rgb_protocol:1; + /** blend_tx_rgb2yuv_protocol : R/W; bitpos: [15]; default: 0; + * RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709 + */ + uint32_t blend_tx_rgb2yuv_protocol:1; + /** blend0_rx_yuv422_byte_order : R/W; bitpos: [17:16]; default: 0; + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr) + */ + uint32_t blend0_rx_yuv422_byte_order:2; + uint32_t reserved_18:14; }; uint32_t val; } ppa_blend_color_mode_reg_t; @@ -165,7 +189,11 @@ typedef union { * to improve efficient accessing external memory. */ uint32_t sr_macro_bk_ro_bypass:1; - uint32_t reserved_3:29; + /** sr_bk_size_sel : R/W; bitpos: [3]; default: 0; + * sel srm pix_blk size, 0:32x32, 1:16x16 + */ + uint32_t sr_bk_size_sel:1; + uint32_t reserved_4:28; }; uint32_t val; } ppa_sr_byte_order_reg_t; @@ -227,7 +255,12 @@ typedef union { * write 1 then write 0 to reset blending engine. */ uint32_t blend_rst:1; - uint32_t reserved_5:27; + /** blend_tx_inf_sel : R/W; bitpos: [6:5]; default: 0; + * unused ! Configures blend tx interface. 0: dma2d only, 1: le_enc only, 2: dma2d and + * ls_enc + */ + uint32_t blend_tx_inf_sel:2; + uint32_t reserved_7:25; }; uint32_t val; } ppa_blend_trans_mode_reg_t; @@ -263,13 +296,13 @@ typedef union { typedef union { struct { /** blend_hb : R/W; bitpos: [13:0]; default: 0; - * The horizontal width of image block that would be filled in fix pixel filling mode. - * The unit is pixel + * The horizontal width of image block that would be filled in fix pixel filling mode + * or blend mode. The unit is pixel. Must be even num when YUV422 or YUV420 */ uint32_t blend_hb:14; /** blend_vb : R/W; bitpos: [27:14]; default: 0; - * The vertical width of image block that would be filled in fix pixel filling mode. - * The unit is pixel + * The vertical width of image block that would be filled in fix pixel filling mode or + * blend mode. The unit is pixel. Must be even num when YUV420 */ uint32_t blend_vb:14; uint32_t reserved_28:4; @@ -293,13 +326,13 @@ typedef union { */ uint32_t blend1_rx_fix_alpha:8; /** blend0_rx_alpha_mod : R/W; bitpos: [17:16]; default: 0; - * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2: + * Original alpha multiply with PPA_BLEND0_FIX_ALPHA/256. */ uint32_t blend0_rx_alpha_mod:2; /** blend1_rx_alpha_mod : R/W; bitpos: [19:18]; default: 0; - * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2: + * Original alpha multiply with PPA_BLEND1_FIX_ALPHA/256. */ uint32_t blend1_rx_alpha_mod:2; /** blend0_rx_alpha_inv : R/W; bitpos: [20]; default: 0; @@ -612,7 +645,12 @@ typedef union { * PPA_SR_PARAM_ERR_ST_REG. */ uint32_t sr_param_cfg_err_int_raw:1; - uint32_t reserved_3:29; + /** blend_param_cfg_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when the configured blending coefficient + * is wrong. User can check the reasons through register PPA_BLEND_ST_REG. + */ + uint32_t blend_param_cfg_err_int_raw:1; + uint32_t reserved_4:28; }; uint32_t val; } ppa_int_raw_reg_t; @@ -631,10 +669,14 @@ typedef union { */ uint32_t blend_eof_int_st:1; /** sr_param_cfg_err_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + * The raw interrupt status bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. */ uint32_t sr_param_cfg_err_int_st:1; - uint32_t reserved_3:29; + /** blend_param_cfg_err_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. + */ + uint32_t blend_param_cfg_err_int_st:1; + uint32_t reserved_4:28; }; uint32_t val; } ppa_int_st_reg_t; @@ -653,10 +695,14 @@ typedef union { */ uint32_t blend_eof_int_ena:1; /** sr_param_cfg_err_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + * The interrupt enable bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. */ uint32_t sr_param_cfg_err_int_ena:1; - uint32_t reserved_3:29; + /** blend_param_cfg_err_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. + */ + uint32_t blend_param_cfg_err_int_ena:1; + uint32_t reserved_4:28; }; uint32_t val; } ppa_int_ena_reg_t; @@ -675,10 +721,14 @@ typedef union { */ uint32_t blend_eof_int_clr:1; /** sr_param_cfg_err_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. + * Set this bit to clear the PPA_SR_PARAM_CFG_ERR_INT interrupt. */ uint32_t sr_param_cfg_err_int_clr:1; - uint32_t reserved_3:29; + /** blend_param_cfg_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. + */ + uint32_t blend_param_cfg_err_int_clr:1; + uint32_t reserved_4:28; }; uint32_t val; } ppa_int_clr_reg_t; @@ -712,7 +762,15 @@ typedef union { * 1: indicate the size of two image is different. */ uint32_t blend_size_diff_st:1; - uint32_t reserved_1:31; + /** blend_yuv_x_scale_err_st : RO; bitpos: [1]; default: 0; + * Represents that x param is an odd num when enable yuv422 or yuv420 + */ + uint32_t blend_yuv_x_scale_err_st:1; + /** blend_yuv_y_scale_err_st : RO; bitpos: [2]; default: 0; + * Represents that y param is an odd num when enable yuv420 + */ + uint32_t blend_yuv_y_scale_err_st:1; + uint32_t reserved_3:29; }; uint32_t val; } ppa_blend_st_reg_t; @@ -773,7 +831,7 @@ typedef union { uint32_t xdst_len_too_large_err_st:1; /** x_yuv420_rx_scale_err_st : RO; bitpos: [10]; default: 0; * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable - * yuv420 rx + * yuv422 or yuv420 rx */ uint32_t x_yuv420_rx_scale_err_st:1; /** y_yuv420_rx_scale_err_st : RO; bitpos: [11]; default: 0; @@ -783,7 +841,7 @@ typedef union { uint32_t y_yuv420_rx_scale_err_st:1; /** x_yuv420_tx_scale_err_st : RO; bitpos: [12]; default: 0; * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable - * yuv420 tx + * yuv422 or yuv420 tx */ uint32_t x_yuv420_tx_scale_err_st:1; /** y_yuv420_tx_scale_err_st : RO; bitpos: [13]; default: 0; @@ -841,13 +899,68 @@ typedef union { } ppa_eco_cell_ctrl_reg_t; +/** Group: Debug Register */ +/** Type of debug_ctrl0 register + * debug register + */ +typedef union { + struct { + /** dbg_replace_sel : R/W; bitpos: [2:0]; default: 0; + * Configures the data replace location. 0: not replace, 1: srm rx input, 2: srm rx + * bilin interpolation, 3: srm tx output, 4: blend fg input, 5: blend bg input, 6: + * blend output + */ + uint32_t dbg_replace_sel:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} ppa_debug_ctrl0_reg_t; + +/** Type of debug_ctrl1 register + * debug register + */ +typedef union { + struct { + /** dbg_replace_data : R/W; bitpos: [31:0]; default: 0; + * Configures the replace data + */ + uint32_t dbg_replace_data:32; + }; + uint32_t val; +} ppa_debug_ctrl1_reg_t; + + +/** Group: Configuration Register */ +/** Type of rgb2gray register + * rgb2gray register + */ +typedef union { + struct { + /** rgb2gray_b : R/W; bitpos: [7:0]; default: 85; + * Configures the b parameter for rgb2gray + */ + uint32_t rgb2gray_b:8; + /** rgb2gray_g : R/W; bitpos: [15:8]; default: 86; + * Configures the g parameter for rgb2gray + */ + uint32_t rgb2gray_g:8; + /** rgb2gray_r : R/W; bitpos: [23:16]; default: 85; + * Configures the r parameter for rgb2gray + */ + uint32_t rgb2gray_r:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} ppa_rgb2gray_reg_t; + + /** Group: Version Register */ /** Type of date register * PPA Version register */ typedef union { struct { - /** date : R/W; bitpos: [31:0]; default: 36716609; + /** date : R/W; bitpos: [31:0]; default: 539234848; * register version. */ uint32_t date:32; @@ -893,7 +1006,10 @@ typedef struct ppa_dev_t { volatile ppa_eco_high_reg_t eco_high; volatile ppa_eco_cell_ctrl_reg_t eco_cell_ctrl; volatile ppa_sram_ctrl_reg_t sram_ctrl; - uint32_t reserved_090[28]; + volatile ppa_debug_ctrl0_reg_t debug_ctrl0; + volatile ppa_debug_ctrl1_reg_t debug_ctrl1; + volatile ppa_rgb2gray_reg_t rgb2gray; + uint32_t reserved_09c[25]; volatile ppa_date_reg_t date; } ppa_dev_t; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/rmt_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/rmt_eco5_struct.h deleted file mode 100644 index bd665b84be4e..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/rmt_eco5_struct.h +++ /dev/null @@ -1,1077 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: FIFO R/W registers */ -/** Type of chndata register - * The read and write data register for CHANNELn by apb fifo access. - */ -typedef union { - struct { - /** chndata : HRO; bitpos: [31:0]; default: 0; - * Read and write data for channel n via APB FIFO. - */ - uint32_t chndata:32; - }; - uint32_t val; -} rmt_chndata_reg_t; - -/** Type of chmdata register - * The read and write data register for CHANNEL$n by apb fifo access. - */ -typedef union { - struct { - /** chmdata : HRO; bitpos: [31:0]; default: 0; - * Read and write data for channel $n via APB FIFO. - */ - uint32_t chmdata:32; - }; - uint32_t val; -} rmt_chmdata_reg_t; - - -/** Group: Configuration registers */ -/** Type of chnconf0 register - * Channel n configure register 0 - */ -typedef union { - struct { - /** tx_start_chn : WT; bitpos: [0]; default: 0; - * Set this bit to start sending data on CHANNELn. - */ - uint32_t tx_start_chn:1; - /** mem_rd_rst_chn : WT; bitpos: [1]; default: 0; - * Set this bit to reset read ram address for CHANNELn by accessing transmitter. - */ - uint32_t mem_rd_rst_chn:1; - /** apb_mem_rst_chn : WT; bitpos: [2]; default: 0; - * Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo. - */ - uint32_t apb_mem_rst_chn:1; - /** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0; - * Set this bit to restart transmission from the first data to the last data in - * CHANNELn. - */ - uint32_t tx_conti_mode_chn:1; - /** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0; - * This is the channel n enable bit for wraparound mode: it will resume sending at the - * start when the data to be sent is more than its memory size. - */ - uint32_t mem_tx_wrap_en_chn:1; - /** idle_out_lv_chn : R/W; bitpos: [5]; default: 0; - * This bit configures the level of output signal in CHANNELn when the latter is in - * IDLE state. - */ - uint32_t idle_out_lv_chn:1; - /** idle_out_en_chn : R/W; bitpos: [6]; default: 0; - * This is the output enable-control bit for CHANNELn in IDLE state. - */ - uint32_t idle_out_en_chn:1; - /** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0; - * Set this bit to stop the transmitter of CHANNELn sending data out. - */ - uint32_t tx_stop_chn:1; - /** div_cnt_chn : R/W; bitpos: [15:8]; default: 2; - * This register is used to configure the divider for clock of CHANNELn. - */ - uint32_t div_cnt_chn:8; - /** mem_size_chn : R/W; bitpos: [19:16]; default: 1; - * This register is used to configure the maximum size of memory allocated to CHANNELn. - */ - uint32_t mem_size_chn:4; - /** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1; - * 1: Add carrier modulation on the output signal only at the send data state for - * CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn. - * Only valid when RMT_CARRIER_EN_CHn is 1. - */ - uint32_t carrier_eff_en_chn:1; - /** carrier_en_chn : R/W; bitpos: [21]; default: 1; - * This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier - * modulation in the output signal. 0: No carrier modulation in sig_out. - */ - uint32_t carrier_en_chn:1; - /** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1; - * This bit is used to configure the position of carrier wave for CHANNELn.1'h0: add - * carrier wave on low level.1'h1: add carrier wave on high level. - */ - uint32_t carrier_out_lv_chn:1; - uint32_t reserved_23:1; - /** conf_update_chn : WT; bitpos: [24]; default: 0; - * synchronization bit for CHANNELn - */ - uint32_t conf_update_chn:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} rmt_chnconf0_reg_t; - -/** Type of chmconf0 register - * Channel m configure register 0 - */ -typedef union { - struct { - /** div_cnt_chm : R/W; bitpos: [7:0]; default: 2; - * This register is used to configure the divider for clock of CHANNELm. - */ - uint32_t div_cnt_chm:8; - /** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767; - * When no edge is detected on the input signal and continuous clock cycles is longer - * than this register value, received process is finished. - */ - uint32_t idle_thres_chm:15; - uint32_t reserved_23:1; - /** mem_size_chm : R/W; bitpos: [27:24]; default: 1; - * This register is used to configure the maximum size of memory allocated to CHANNELm. - */ - uint32_t mem_size_chm:4; - /** carrier_en_chm : R/W; bitpos: [28]; default: 1; - * This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier - * modulation in the output signal. 0: No carrier modulation in sig_out. - */ - uint32_t carrier_en_chm:1; - /** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1; - * This bit is used to configure the position of carrier wave for CHANNELm.1'h0: add - * carrier wave on low level.1'h1: add carrier wave on high level. - */ - uint32_t carrier_out_lv_chm:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} rmt_chmconf0_reg_t; - -/** Type of chmconf1 register - * Channel m configure register 1 - */ -typedef union { - struct { - /** rx_en_chm : R/W; bitpos: [0]; default: 0; - * Set this bit to enable receiver to receive data on CHANNELm. - */ - uint32_t rx_en_chm:1; - /** mem_wr_rst_chm : WT; bitpos: [1]; default: 0; - * Set this bit to reset write ram address for CHANNELm by accessing receiver. - */ - uint32_t mem_wr_rst_chm:1; - /** apb_mem_rst_chm : WT; bitpos: [2]; default: 0; - * Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo. - */ - uint32_t apb_mem_rst_chm:1; - /** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1; - * This register marks the ownership of CHANNELm's ram block.1'h1: Receiver is using - * the ram. 1'h0: APB bus is using the ram. - */ - uint32_t mem_owner_chm:1; - /** rx_filter_en_chm : R/W; bitpos: [4]; default: 0; - * This is the receive filter's enable bit for CHANNELm. - */ - uint32_t rx_filter_en_chm:1; - /** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15; - * Ignores the input pulse when its width is smaller than this register value in APB - * clock periods (in receive mode). - */ - uint32_t rx_filter_thres_chm:8; - /** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0; - * This is the channel m enable bit for wraparound mode: it will resume receiving at - * the start when the data to be received is more than its memory size. - */ - uint32_t mem_rx_wrap_en_chm:1; - uint32_t reserved_14:1; - /** conf_update_chm : WT; bitpos: [15]; default: 0; - * synchronization bit for CHANNELm - */ - uint32_t conf_update_chm:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} rmt_chmconf1_reg_t; - -/** Type of chm_rx_carrier_rm register - * Channel m carrier remove register - */ -typedef union { - struct { - /** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0; - * The low level period in a carrier modulation mode is - * (REG_RMT_REG_CARRIER_LOW_THRES_CHm + 1) for channel m. - */ - uint32_t carrier_low_thres_chm:16; - /** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0; - * The high level period in a carrier modulation mode is - * (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m. - */ - uint32_t carrier_high_thres_chm:16; - }; - uint32_t val; -} rmt_chm_rx_carrier_rm_reg_t; - -/** Type of sys_conf register - * RMT apb configuration register - */ -typedef union { - struct { - /** apb_fifo_mask : R/W; bitpos: [0]; default: 0; - * 1'h1: access memory directly. 1'h0: access memory by FIFO. - */ - uint32_t apb_fifo_mask:1; - /** mem_clk_force_on : R/W; bitpos: [1]; default: 0; - * Set this bit to enable the clock for RMT memory. - */ - uint32_t mem_clk_force_on:1; - /** mem_force_pd : R/W; bitpos: [2]; default: 0; - * Set this bit to power down RMT memory. - */ - uint32_t mem_force_pd:1; - /** mem_force_pu : R/W; bitpos: [3]; default: 0; - * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory - * when RMT is in light sleep mode. - */ - uint32_t mem_force_pu:1; - /** sclk_div_num : R/W; bitpos: [11:4]; default: 1; - * the integral part of the fractional divisor - */ - uint32_t sclk_div_num:8; - /** sclk_div_a : R/W; bitpos: [17:12]; default: 0; - * the numerator of the fractional part of the fractional divisor - */ - uint32_t sclk_div_a:6; - /** sclk_div_b : R/W; bitpos: [23:18]; default: 0; - * the denominator of the fractional part of the fractional divisor - */ - uint32_t sclk_div_b:6; - /** sclk_sel : R/W; bitpos: [25:24]; default: 1; - * choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL - */ - uint32_t sclk_sel:2; - /** sclk_active : R/W; bitpos: [26]; default: 1; - * rmt_sclk switch - */ - uint32_t sclk_active:1; - uint32_t reserved_27:4; - /** clk_en : R/W; bitpos: [31]; default: 0; - * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: - * Power down the drive clock of registers - */ - uint32_t clk_en:1; - }; - uint32_t val; -} rmt_sys_conf_reg_t; - -/** Type of ref_cnt_rst register - * RMT clock divider reset register - */ -typedef union { - struct { - /** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0; - * This register is used to reset the clock divider of CHANNEL0. - */ - uint32_t ref_cnt_rst_ch0:1; - /** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0; - * This register is used to reset the clock divider of CHANNEL1. - */ - uint32_t ref_cnt_rst_ch1:1; - /** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0; - * This register is used to reset the clock divider of CHANNEL2. - */ - uint32_t ref_cnt_rst_ch2:1; - /** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0; - * This register is used to reset the clock divider of CHANNEL3. - */ - uint32_t ref_cnt_rst_ch3:1; - /** ref_cnt_rst_ch4 : WT; bitpos: [4]; default: 0; - * This register is used to reset the clock divider of CHANNEL4. - */ - uint32_t ref_cnt_rst_ch4:1; - /** ref_cnt_rst_ch5 : WT; bitpos: [5]; default: 0; - * This register is used to reset the clock divider of CHANNEL5. - */ - uint32_t ref_cnt_rst_ch5:1; - /** ref_cnt_rst_ch6 : WT; bitpos: [6]; default: 0; - * This register is used to reset the clock divider of CHANNEL6. - */ - uint32_t ref_cnt_rst_ch6:1; - /** ref_cnt_rst_ch7 : WT; bitpos: [7]; default: 0; - * This register is used to reset the clock divider of CHANNEL7. - */ - uint32_t ref_cnt_rst_ch7:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} rmt_ref_cnt_rst_reg_t; - - -/** Group: Status registers */ -/** Type of chnstatus register - * Channel n status register - */ -typedef union { - struct { - /** mem_raddr_ex_chn : RO; bitpos: [9:0]; default: 0; - * This register records the memory address offset when transmitter of CHANNELn is - * using the RAM. - */ - uint32_t mem_raddr_ex_chn:10; - uint32_t reserved_10:1; - /** apb_mem_waddr_chn : RO; bitpos: [20:11]; default: 0; - * This register records the memory address offset when writes RAM over APB bus. - */ - uint32_t apb_mem_waddr_chn:10; - uint32_t reserved_21:1; - /** state_chn : RO; bitpos: [24:22]; default: 0; - * This register records the FSM status of CHANNELn. - */ - uint32_t state_chn:3; - /** mem_empty_chn : RO; bitpos: [25]; default: 0; - * This status bit will be set when the data to be set is more than memory size and - * the wraparound mode is disabled. - */ - uint32_t mem_empty_chn:1; - /** apb_mem_wr_err_chn : RO; bitpos: [26]; default: 0; - * This status bit will be set if the offset address out of memory size when writes - * via APB bus. - */ - uint32_t apb_mem_wr_err_chn:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} rmt_chnstatus_reg_t; - -/** Type of chmstatus register - * Channel m status register - */ -typedef union { - struct { - /** mem_waddr_ex_chm : RO; bitpos: [9:0]; default: 192; - * This register records the memory address offset when receiver of CHANNELm is using - * the RAM. - */ - uint32_t mem_waddr_ex_chm:10; - uint32_t reserved_10:1; - /** apb_mem_raddr_chm : RO; bitpos: [20:11]; default: 192; - * This register records the memory address offset when reads RAM over APB bus. - */ - uint32_t apb_mem_raddr_chm:10; - uint32_t reserved_21:1; - /** state_chm : RO; bitpos: [24:22]; default: 0; - * This register records the FSM status of CHANNELm. - */ - uint32_t state_chm:3; - /** mem_owner_err_chm : RO; bitpos: [25]; default: 0; - * This status bit will be set when the ownership of memory block is wrong. - */ - uint32_t mem_owner_err_chm:1; - /** mem_full_chm : RO; bitpos: [26]; default: 0; - * This status bit will be set if the receiver receives more data than the memory size. - */ - uint32_t mem_full_chm:1; - /** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0; - * This status bit will be set if the offset address out of memory size when reads via - * APB bus. - */ - uint32_t apb_mem_rd_err_chm:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} rmt_chmstatus_reg_t; - - -/** Group: Interrupt registers */ -/** Type of int_raw register - * Raw interrupt status - */ -typedef union { - struct { - /** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The interrupt raw bit for CHANNEL0. Triggered when transmission done. - */ - uint32_t ch0_tx_end_int_raw:1; - /** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The interrupt raw bit for CHANNEL1. Triggered when transmission done. - */ - uint32_t ch1_tx_end_int_raw:1; - /** ch2_tx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The interrupt raw bit for CHANNEL2. Triggered when transmission done. - */ - uint32_t ch2_tx_end_int_raw:1; - /** ch3_tx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The interrupt raw bit for CHANNEL3. Triggered when transmission done. - */ - uint32_t ch3_tx_end_int_raw:1; - /** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The interrupt raw bit for CHANNEL0. Triggered when error occurs. - */ - uint32_t ch0_err_int_raw:1; - /** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The interrupt raw bit for CHANNEL1. Triggered when error occurs. - */ - uint32_t ch1_err_int_raw:1; - /** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The interrupt raw bit for CHANNEL2. Triggered when error occurs. - */ - uint32_t ch2_err_int_raw:1; - /** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The interrupt raw bit for CHANNEL3. Triggered when error occurs. - */ - uint32_t ch3_err_int_raw:1; - /** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than - * configured value. - */ - uint32_t ch0_tx_thr_event_int_raw:1; - /** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than - * configured value. - */ - uint32_t ch1_tx_thr_event_int_raw:1; - /** ch2_tx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than - * configured value. - */ - uint32_t ch2_tx_thr_event_int_raw:1; - /** ch3_tx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than - * configured value. - */ - uint32_t ch3_tx_thr_event_int_raw:1; - /** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the - * configured threshold value. - */ - uint32_t ch0_tx_loop_int_raw:1; - /** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the - * configured threshold value. - */ - uint32_t ch1_tx_loop_int_raw:1; - /** ch2_tx_loop_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the - * configured threshold value. - */ - uint32_t ch2_tx_loop_int_raw:1; - /** ch3_tx_loop_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the - * configured threshold value. - */ - uint32_t ch3_tx_loop_int_raw:1; - /** ch4_rx_end_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * The interrupt raw bit for CHANNEL4. Triggered when reception done. - */ - uint32_t ch4_rx_end_int_raw:1; - /** ch5_rx_end_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * The interrupt raw bit for CHANNEL5. Triggered when reception done. - */ - uint32_t ch5_rx_end_int_raw:1; - /** ch6_rx_end_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * The interrupt raw bit for CHANNEL6. Triggered when reception done. - */ - uint32_t ch6_rx_end_int_raw:1; - /** ch7_rx_end_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * The interrupt raw bit for CHANNEL7. Triggered when reception done. - */ - uint32_t ch7_rx_end_int_raw:1; - /** ch4_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * The interrupt raw bit for CHANNEL4. Triggered when error occurs. - */ - uint32_t ch4_err_int_raw:1; - /** ch5_err_int_raw : R/WTC/SS; bitpos: [21]; default: 0; - * The interrupt raw bit for CHANNEL5. Triggered when error occurs. - */ - uint32_t ch5_err_int_raw:1; - /** ch6_err_int_raw : R/WTC/SS; bitpos: [22]; default: 0; - * The interrupt raw bit for CHANNEL6. Triggered when error occurs. - */ - uint32_t ch6_err_int_raw:1; - /** ch7_err_int_raw : R/WTC/SS; bitpos: [23]; default: 0; - * The interrupt raw bit for CHANNEL7. Triggered when error occurs. - */ - uint32_t ch7_err_int_raw:1; - /** ch4_rx_thr_event_int_raw : R/WTC/SS; bitpos: [24]; default: 0; - * The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than - * configured value. - */ - uint32_t ch4_rx_thr_event_int_raw:1; - /** ch5_rx_thr_event_int_raw : R/WTC/SS; bitpos: [25]; default: 0; - * The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than - * configured value. - */ - uint32_t ch5_rx_thr_event_int_raw:1; - /** ch6_rx_thr_event_int_raw : R/WTC/SS; bitpos: [26]; default: 0; - * The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than - * configured value. - */ - uint32_t ch6_rx_thr_event_int_raw:1; - /** ch7_rx_thr_event_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than - * configured value. - */ - uint32_t ch7_rx_thr_event_int_raw:1; - /** ch3_dma_access_fail_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. - */ - uint32_t ch3_dma_access_fail_int_raw:1; - /** ch7_dma_access_fail_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. - */ - uint32_t ch7_dma_access_fail_int_raw:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} rmt_int_raw_reg_t; - -/** Type of int_st register - * Masked interrupt status - */ -typedef union { - struct { - /** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for CH0_TX_END_INT. - */ - uint32_t ch0_tx_end_int_st:1; - /** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for CH1_TX_END_INT. - */ - uint32_t ch1_tx_end_int_st:1; - /** ch2_tx_end_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for CH2_TX_END_INT. - */ - uint32_t ch2_tx_end_int_st:1; - /** ch3_tx_end_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status bit for CH3_TX_END_INT. - */ - uint32_t ch3_tx_end_int_st:1; - /** ch0_err_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status bit for CH0_ERR_INT. - */ - uint32_t ch0_err_int_st:1; - /** ch1_err_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status bit for CH1_ERR_INT. - */ - uint32_t ch1_err_int_st:1; - /** ch2_err_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status bit for CH2_ERR_INT. - */ - uint32_t ch2_err_int_st:1; - /** ch3_err_int_st : RO; bitpos: [7]; default: 0; - * The masked interrupt status bit for CH3_ERR_INT. - */ - uint32_t ch3_err_int_st:1; - /** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0; - * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. - */ - uint32_t ch0_tx_thr_event_int_st:1; - /** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0; - * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. - */ - uint32_t ch1_tx_thr_event_int_st:1; - /** ch2_tx_thr_event_int_st : RO; bitpos: [10]; default: 0; - * The masked interrupt status bit for CH2_TX_THR_EVENT_INT. - */ - uint32_t ch2_tx_thr_event_int_st:1; - /** ch3_tx_thr_event_int_st : RO; bitpos: [11]; default: 0; - * The masked interrupt status bit for CH3_TX_THR_EVENT_INT. - */ - uint32_t ch3_tx_thr_event_int_st:1; - /** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0; - * The masked interrupt status bit for CH0_TX_LOOP_INT. - */ - uint32_t ch0_tx_loop_int_st:1; - /** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0; - * The masked interrupt status bit for CH1_TX_LOOP_INT. - */ - uint32_t ch1_tx_loop_int_st:1; - /** ch2_tx_loop_int_st : RO; bitpos: [14]; default: 0; - * The masked interrupt status bit for CH2_TX_LOOP_INT. - */ - uint32_t ch2_tx_loop_int_st:1; - /** ch3_tx_loop_int_st : RO; bitpos: [15]; default: 0; - * The masked interrupt status bit for CH3_TX_LOOP_INT. - */ - uint32_t ch3_tx_loop_int_st:1; - /** ch4_rx_end_int_st : RO; bitpos: [16]; default: 0; - * The masked interrupt status bit for CH4_RX_END_INT. - */ - uint32_t ch4_rx_end_int_st:1; - /** ch5_rx_end_int_st : RO; bitpos: [17]; default: 0; - * The masked interrupt status bit for CH5_RX_END_INT. - */ - uint32_t ch5_rx_end_int_st:1; - /** ch6_rx_end_int_st : RO; bitpos: [18]; default: 0; - * The masked interrupt status bit for CH6_RX_END_INT. - */ - uint32_t ch6_rx_end_int_st:1; - /** ch7_rx_end_int_st : RO; bitpos: [19]; default: 0; - * The masked interrupt status bit for CH7_RX_END_INT. - */ - uint32_t ch7_rx_end_int_st:1; - /** ch4_err_int_st : RO; bitpos: [20]; default: 0; - * The masked interrupt status bit for CH4_ERR_INT. - */ - uint32_t ch4_err_int_st:1; - /** ch5_err_int_st : RO; bitpos: [21]; default: 0; - * The masked interrupt status bit for CH5_ERR_INT. - */ - uint32_t ch5_err_int_st:1; - /** ch6_err_int_st : RO; bitpos: [22]; default: 0; - * The masked interrupt status bit for CH6_ERR_INT. - */ - uint32_t ch6_err_int_st:1; - /** ch7_err_int_st : RO; bitpos: [23]; default: 0; - * The masked interrupt status bit for CH7_ERR_INT. - */ - uint32_t ch7_err_int_st:1; - /** ch4_rx_thr_event_int_st : RO; bitpos: [24]; default: 0; - * The masked interrupt status bit for CH4_RX_THR_EVENT_INT. - */ - uint32_t ch4_rx_thr_event_int_st:1; - /** ch5_rx_thr_event_int_st : RO; bitpos: [25]; default: 0; - * The masked interrupt status bit for CH5_RX_THR_EVENT_INT. - */ - uint32_t ch5_rx_thr_event_int_st:1; - /** ch6_rx_thr_event_int_st : RO; bitpos: [26]; default: 0; - * The masked interrupt status bit for CH6_RX_THR_EVENT_INT. - */ - uint32_t ch6_rx_thr_event_int_st:1; - /** ch7_rx_thr_event_int_st : RO; bitpos: [27]; default: 0; - * The masked interrupt status bit for CH7_RX_THR_EVENT_INT. - */ - uint32_t ch7_rx_thr_event_int_st:1; - /** ch3_dma_access_fail_int_st : RO; bitpos: [28]; default: 0; - * The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. - */ - uint32_t ch3_dma_access_fail_int_st:1; - /** ch7_dma_access_fail_int_st : RO; bitpos: [29]; default: 0; - * The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. - */ - uint32_t ch7_dma_access_fail_int_st:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} rmt_int_st_reg_t; - -/** Type of int_ena register - * Interrupt enable bits - */ -typedef union { - struct { - /** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for CH0_TX_END_INT. - */ - uint32_t ch0_tx_end_int_ena:1; - /** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for CH1_TX_END_INT. - */ - uint32_t ch1_tx_end_int_ena:1; - /** ch2_tx_end_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for CH2_TX_END_INT. - */ - uint32_t ch2_tx_end_int_ena:1; - /** ch3_tx_end_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for CH3_TX_END_INT. - */ - uint32_t ch3_tx_end_int_ena:1; - /** ch0_err_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for CH0_ERR_INT. - */ - uint32_t ch0_err_int_ena:1; - /** ch1_err_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for CH1_ERR_INT. - */ - uint32_t ch1_err_int_ena:1; - /** ch2_err_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for CH2_ERR_INT. - */ - uint32_t ch2_err_int_ena:1; - /** ch3_err_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for CH3_ERR_INT. - */ - uint32_t ch3_err_int_ena:1; - /** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for CH0_TX_THR_EVENT_INT. - */ - uint32_t ch0_tx_thr_event_int_ena:1; - /** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for CH1_TX_THR_EVENT_INT. - */ - uint32_t ch1_tx_thr_event_int_ena:1; - /** ch2_tx_thr_event_int_ena : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for CH2_TX_THR_EVENT_INT. - */ - uint32_t ch2_tx_thr_event_int_ena:1; - /** ch3_tx_thr_event_int_ena : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for CH3_TX_THR_EVENT_INT. - */ - uint32_t ch3_tx_thr_event_int_ena:1; - /** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for CH0_TX_LOOP_INT. - */ - uint32_t ch0_tx_loop_int_ena:1; - /** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for CH1_TX_LOOP_INT. - */ - uint32_t ch1_tx_loop_int_ena:1; - /** ch2_tx_loop_int_ena : R/W; bitpos: [14]; default: 0; - * The interrupt enable bit for CH2_TX_LOOP_INT. - */ - uint32_t ch2_tx_loop_int_ena:1; - /** ch3_tx_loop_int_ena : R/W; bitpos: [15]; default: 0; - * The interrupt enable bit for CH3_TX_LOOP_INT. - */ - uint32_t ch3_tx_loop_int_ena:1; - /** ch4_rx_end_int_ena : R/W; bitpos: [16]; default: 0; - * The interrupt enable bit for CH4_RX_END_INT. - */ - uint32_t ch4_rx_end_int_ena:1; - /** ch5_rx_end_int_ena : R/W; bitpos: [17]; default: 0; - * The interrupt enable bit for CH5_RX_END_INT. - */ - uint32_t ch5_rx_end_int_ena:1; - /** ch6_rx_end_int_ena : R/W; bitpos: [18]; default: 0; - * The interrupt enable bit for CH6_RX_END_INT. - */ - uint32_t ch6_rx_end_int_ena:1; - /** ch7_rx_end_int_ena : R/W; bitpos: [19]; default: 0; - * The interrupt enable bit for CH7_RX_END_INT. - */ - uint32_t ch7_rx_end_int_ena:1; - /** ch4_err_int_ena : R/W; bitpos: [20]; default: 0; - * The interrupt enable bit for CH4_ERR_INT. - */ - uint32_t ch4_err_int_ena:1; - /** ch5_err_int_ena : R/W; bitpos: [21]; default: 0; - * The interrupt enable bit for CH5_ERR_INT. - */ - uint32_t ch5_err_int_ena:1; - /** ch6_err_int_ena : R/W; bitpos: [22]; default: 0; - * The interrupt enable bit for CH6_ERR_INT. - */ - uint32_t ch6_err_int_ena:1; - /** ch7_err_int_ena : R/W; bitpos: [23]; default: 0; - * The interrupt enable bit for CH7_ERR_INT. - */ - uint32_t ch7_err_int_ena:1; - /** ch4_rx_thr_event_int_ena : R/W; bitpos: [24]; default: 0; - * The interrupt enable bit for CH4_RX_THR_EVENT_INT. - */ - uint32_t ch4_rx_thr_event_int_ena:1; - /** ch5_rx_thr_event_int_ena : R/W; bitpos: [25]; default: 0; - * The interrupt enable bit for CH5_RX_THR_EVENT_INT. - */ - uint32_t ch5_rx_thr_event_int_ena:1; - /** ch6_rx_thr_event_int_ena : R/W; bitpos: [26]; default: 0; - * The interrupt enable bit for CH6_RX_THR_EVENT_INT. - */ - uint32_t ch6_rx_thr_event_int_ena:1; - /** ch7_rx_thr_event_int_ena : R/W; bitpos: [27]; default: 0; - * The interrupt enable bit for CH7_RX_THR_EVENT_INT. - */ - uint32_t ch7_rx_thr_event_int_ena:1; - /** ch3_dma_access_fail_int_ena : R/W; bitpos: [28]; default: 0; - * The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. - */ - uint32_t ch3_dma_access_fail_int_ena:1; - /** ch7_dma_access_fail_int_ena : R/W; bitpos: [29]; default: 0; - * The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. - */ - uint32_t ch7_dma_access_fail_int_ena:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} rmt_int_ena_reg_t; - -/** Type of int_clr register - * Interrupt clear bits - */ -typedef union { - struct { - /** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear theCH0_TX_END_INT interrupt. - */ - uint32_t ch0_tx_end_int_clr:1; - /** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear theCH1_TX_END_INT interrupt. - */ - uint32_t ch1_tx_end_int_clr:1; - /** ch2_tx_end_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear theCH2_TX_END_INT interrupt. - */ - uint32_t ch2_tx_end_int_clr:1; - /** ch3_tx_end_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear theCH3_TX_END_INT interrupt. - */ - uint32_t ch3_tx_end_int_clr:1; - /** ch0_err_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear theCH0_ERR_INT interrupt. - */ - uint32_t ch0_err_int_clr:1; - /** ch1_err_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear theCH1_ERR_INT interrupt. - */ - uint32_t ch1_err_int_clr:1; - /** ch2_err_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear theCH2_ERR_INT interrupt. - */ - uint32_t ch2_err_int_clr:1; - /** ch3_err_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear theCH3_ERR_INT interrupt. - */ - uint32_t ch3_err_int_clr:1; - /** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. - */ - uint32_t ch0_tx_thr_event_int_clr:1; - /** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. - */ - uint32_t ch1_tx_thr_event_int_clr:1; - /** ch2_tx_thr_event_int_clr : WT; bitpos: [10]; default: 0; - * Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt. - */ - uint32_t ch2_tx_thr_event_int_clr:1; - /** ch3_tx_thr_event_int_clr : WT; bitpos: [11]; default: 0; - * Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt. - */ - uint32_t ch3_tx_thr_event_int_clr:1; - /** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0; - * Set this bit to clear theCH0_TX_LOOP_INT interrupt. - */ - uint32_t ch0_tx_loop_int_clr:1; - /** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0; - * Set this bit to clear theCH1_TX_LOOP_INT interrupt. - */ - uint32_t ch1_tx_loop_int_clr:1; - /** ch2_tx_loop_int_clr : WT; bitpos: [14]; default: 0; - * Set this bit to clear theCH2_TX_LOOP_INT interrupt. - */ - uint32_t ch2_tx_loop_int_clr:1; - /** ch3_tx_loop_int_clr : WT; bitpos: [15]; default: 0; - * Set this bit to clear theCH3_TX_LOOP_INT interrupt. - */ - uint32_t ch3_tx_loop_int_clr:1; - /** ch4_rx_end_int_clr : WT; bitpos: [16]; default: 0; - * Set this bit to clear theCH4_RX_END_INT interrupt. - */ - uint32_t ch4_rx_end_int_clr:1; - /** ch5_rx_end_int_clr : WT; bitpos: [17]; default: 0; - * Set this bit to clear theCH5_RX_END_INT interrupt. - */ - uint32_t ch5_rx_end_int_clr:1; - /** ch6_rx_end_int_clr : WT; bitpos: [18]; default: 0; - * Set this bit to clear theCH6_RX_END_INT interrupt. - */ - uint32_t ch6_rx_end_int_clr:1; - /** ch7_rx_end_int_clr : WT; bitpos: [19]; default: 0; - * Set this bit to clear theCH7_RX_END_INT interrupt. - */ - uint32_t ch7_rx_end_int_clr:1; - /** ch4_err_int_clr : WT; bitpos: [20]; default: 0; - * Set this bit to clear theCH4_ERR_INT interrupt. - */ - uint32_t ch4_err_int_clr:1; - /** ch5_err_int_clr : WT; bitpos: [21]; default: 0; - * Set this bit to clear theCH5_ERR_INT interrupt. - */ - uint32_t ch5_err_int_clr:1; - /** ch6_err_int_clr : WT; bitpos: [22]; default: 0; - * Set this bit to clear theCH6_ERR_INT interrupt. - */ - uint32_t ch6_err_int_clr:1; - /** ch7_err_int_clr : WT; bitpos: [23]; default: 0; - * Set this bit to clear theCH7_ERR_INT interrupt. - */ - uint32_t ch7_err_int_clr:1; - /** ch4_rx_thr_event_int_clr : WT; bitpos: [24]; default: 0; - * Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. - */ - uint32_t ch4_rx_thr_event_int_clr:1; - /** ch5_rx_thr_event_int_clr : WT; bitpos: [25]; default: 0; - * Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. - */ - uint32_t ch5_rx_thr_event_int_clr:1; - /** ch6_rx_thr_event_int_clr : WT; bitpos: [26]; default: 0; - * Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. - */ - uint32_t ch6_rx_thr_event_int_clr:1; - /** ch7_rx_thr_event_int_clr : WT; bitpos: [27]; default: 0; - * Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. - */ - uint32_t ch7_rx_thr_event_int_clr:1; - /** ch3_dma_access_fail_int_clr : WT; bitpos: [28]; default: 0; - * Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. - */ - uint32_t ch3_dma_access_fail_int_clr:1; - /** ch7_dma_access_fail_int_clr : WT; bitpos: [29]; default: 0; - * Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. - */ - uint32_t ch7_dma_access_fail_int_clr:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} rmt_int_clr_reg_t; - - -/** Group: Carrier wave duty cycle registers */ -/** Type of chncarrier_duty register - * Channel n duty cycle configuration register - */ -typedef union { - struct { - /** carrier_low_chn : R/W; bitpos: [15:0]; default: 64; - * This register is used to configure carrier wave 's low level clock period for - * CHANNELn. - */ - uint32_t carrier_low_chn:16; - /** carrier_high_chn : R/W; bitpos: [31:16]; default: 64; - * This register is used to configure carrier wave 's high level clock period for - * CHANNELn. - */ - uint32_t carrier_high_chn:16; - }; - uint32_t val; -} rmt_chncarrier_duty_reg_t; - - -/** Group: Tx event configuration registers */ -/** Type of chn_tx_lim register - * Channel n Tx event configuration register - */ -typedef union { - struct { - /** tx_lim_chn : R/W; bitpos: [8:0]; default: 128; - * This register is used to configure the maximum entries that CHANNELn can send out. - */ - uint32_t tx_lim_chn:9; - /** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0; - * This register is used to configure the maximum loop count when tx_conti_mode is - * valid. - */ - uint32_t tx_loop_num_chn:10; - /** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0; - * This register is the enabled bit for loop count. - */ - uint32_t tx_loop_cnt_en_chn:1; - /** loop_count_reset_chn : WT; bitpos: [20]; default: 0; - * This register is used to reset the loop count when tx_conti_mode is valid. - */ - uint32_t loop_count_reset_chn:1; - /** loop_stop_en_chn : R/W; bitpos: [21]; default: 0; - * This bit is used to enable the loop send stop function after the loop counter - * counts to loop number for CHANNELn. - */ - uint32_t loop_stop_en_chn:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} rmt_chn_tx_lim_reg_t; - -/** Type of tx_sim register - * RMT TX synchronous register - */ -typedef union { - struct { - /** tx_sim_ch0 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable CHANNEL0 to start sending data synchronously with other - * enabled channels. - */ - uint32_t tx_sim_ch0:1; - /** tx_sim_ch1 : R/W; bitpos: [1]; default: 0; - * Set this bit to enable CHANNEL1 to start sending data synchronously with other - * enabled channels. - */ - uint32_t tx_sim_ch1:1; - /** tx_sim_ch2 : R/W; bitpos: [2]; default: 0; - * Set this bit to enable CHANNEL2 to start sending data synchronously with other - * enabled channels. - */ - uint32_t tx_sim_ch2:1; - /** tx_sim_ch3 : R/W; bitpos: [3]; default: 0; - * Set this bit to enable CHANNEL3 to start sending data synchronously with other - * enabled channels. - */ - uint32_t tx_sim_ch3:1; - /** tx_sim_en : R/W; bitpos: [4]; default: 0; - * This register is used to enable multiple of channels to start sending data - * synchronously. - */ - uint32_t tx_sim_en:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} rmt_tx_sim_reg_t; - - -/** Group: Rx event configuration registers */ -/** Type of chm_rx_lim register - * Channel m Rx event configuration register - */ -typedef union { - struct { - /** chm_rx_lim_reg : R/W; bitpos: [8:0]; default: 128; - * This register is used to configure the maximum entries that CHANNELm can receive. - */ - uint32_t chm_rx_lim_reg:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} rmt_chm_rx_lim_reg_t; - - -/** Group: Version register */ -/** Type of date register - * RMT version register - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 35655953; - * This is the version register. - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} rmt_date_reg_t; - - -typedef struct { - volatile rmt_chndata_reg_t chndata[4]; - volatile rmt_chmdata_reg_t chmdata[4]; - volatile rmt_chnconf0_reg_t chnconf0[4]; - volatile rmt_chmconf0_reg_t ch4conf0; - volatile rmt_chmconf1_reg_t ch4conf1; - volatile rmt_chmconf0_reg_t ch5conf0; - volatile rmt_chmconf1_reg_t ch5conf1; - volatile rmt_chmconf0_reg_t ch6conf0; - volatile rmt_chmconf1_reg_t ch6conf1; - volatile rmt_chmconf0_reg_t ch7conf0; - volatile rmt_chmconf1_reg_t ch7conf1; - volatile rmt_chnstatus_reg_t chnstatus[4]; - volatile rmt_chmstatus_reg_t chmstatus[4]; - volatile rmt_int_raw_reg_t int_raw; - volatile rmt_int_st_reg_t int_st; - volatile rmt_int_ena_reg_t int_ena; - volatile rmt_int_clr_reg_t int_clr; - volatile rmt_chncarrier_duty_reg_t chncarrier_duty[4]; - volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[4]; - volatile rmt_chn_tx_lim_reg_t chn_tx_lim[4]; - volatile rmt_chm_rx_lim_reg_t chm_rx_lim[4]; - volatile rmt_sys_conf_reg_t sys_conf; - volatile rmt_tx_sim_reg_t tx_sim; - volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst; - volatile rmt_date_reg_t date; -} rmt_dev_t; - -extern rmt_dev_t RMT; - -#ifndef __cplusplus -_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/touch_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/touch_reg.h index d3173425c535..f6265c42f681 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/touch_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/touch_reg.h @@ -11,8 +11,6 @@ extern "C" { #endif -// TODO: IDF-13423 - /** RTC_TOUCH_INT_RAW_REG register * need_des */ @@ -59,6 +57,13 @@ extern "C" { #define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S) #define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x00000001U #define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 5 +/** RTC_TOUCH_BENCHMARK_UPDATE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * need_des + */ +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_RAW (BIT(6)) +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_RAW_M (RTC_TOUCH_BENCHMARK_UPDATE_INT_RAW_V << RTC_TOUCH_BENCHMARK_UPDATE_INT_RAW_S) +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_RAW_V 0x00000001U +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_RAW_S 6 /** RTC_TOUCH_INT_ST_REG register * need_des @@ -106,6 +111,13 @@ extern "C" { #define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S) #define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x00000001U #define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 5 +/** RTC_TOUCH_BENCHMARK_UPDATE_INT_ST : RO; bitpos: [6]; default: 0; + * need_des + */ +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ST (BIT(6)) +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ST_M (RTC_TOUCH_BENCHMARK_UPDATE_INT_ST_V << RTC_TOUCH_BENCHMARK_UPDATE_INT_ST_S) +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ST_V 0x00000001U +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ST_S 6 /** RTC_TOUCH_INT_ENA_REG register * need_des @@ -153,6 +165,13 @@ extern "C" { #define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S) #define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x00000001U #define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 5 +/** RTC_TOUCH_BENCHMARK_UPDATE_INT_ENA : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ENA (BIT(6)) +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ENA_M (RTC_TOUCH_BENCHMARK_UPDATE_INT_ENA_V << RTC_TOUCH_BENCHMARK_UPDATE_INT_ENA_S) +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ENA_V 0x00000001U +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ENA_S 6 /** RTC_TOUCH_INT_CLR_REG register * need_des @@ -200,6 +219,13 @@ extern "C" { #define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S) #define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x00000001U #define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 5 +/** RTC_TOUCH_BENCHMARK_UPDATE_INT_CLR : WT; bitpos: [6]; default: 0; + * need_des + */ +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_CLR (BIT(6)) +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_CLR_M (RTC_TOUCH_BENCHMARK_UPDATE_INT_CLR_V << RTC_TOUCH_BENCHMARK_UPDATE_INT_CLR_S) +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_CLR_V 0x00000001U +#define RTC_TOUCH_BENCHMARK_UPDATE_INT_CLR_S 6 /** RTC_TOUCH_CHN_STATUS_REG register * need_des @@ -219,7 +245,7 @@ extern "C" { #define RTC_TOUCH_MEAS_DONE_M (RTC_TOUCH_MEAS_DONE_V << RTC_TOUCH_MEAS_DONE_S) #define RTC_TOUCH_MEAS_DONE_V 0x00000001U #define RTC_TOUCH_MEAS_DONE_S 15 -/** RTC_TOUCH_SCAN_CURR : RO; bitpos: [19:16]; default: 0; +/** RTC_TOUCH_SCAN_CURR : RO; bitpos: [19:16]; default: 15; * need_des */ #define RTC_TOUCH_SCAN_CURR 0x0000000FU @@ -746,13 +772,6 @@ extern "C" { * need_des */ #define RTC_TOUCH_DATE_REG (DR_REG_LP_TOUCH_BASE + 0x100) -/** RTC_TOUCH_DATE : R/W; bitpos: [27:0]; default: 2294548; - * need_des - */ -#define RTC_TOUCH_DATE 0x0FFFFFFFU -#define RTC_TOUCH_DATE_M (RTC_TOUCH_DATE_V << RTC_TOUCH_DATE_S) -#define RTC_TOUCH_DATE_V 0x0FFFFFFFU -#define RTC_TOUCH_DATE_S 0 /** RTC_TOUCH_CLK_EN : R/W; bitpos: [31]; default: 0; * need_des */ diff --git a/components/soc/esp32p4/register/hw_ver3/soc/touch_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/touch_struct.h index 876919bf98fa..1581e548a90f 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/touch_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/touch_struct.h @@ -10,8 +10,6 @@ extern "C" { #endif -// TODO: IDF-13423 - /** Group: configure_register */ /** Type of int_raw register * need_des @@ -42,7 +40,11 @@ typedef union { * need_des */ uint32_t approach_loop_done_int_raw:1; - uint32_t reserved_6:26; + /** benchmark_update_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * need_des + */ + uint32_t benchmark_update_int_raw:1; + uint32_t reserved_7:25; }; uint32_t val; } rtc_touch_int_raw_reg_t; @@ -76,7 +78,11 @@ typedef union { * need_des */ uint32_t approach_loop_done_int_st:1; - uint32_t reserved_6:26; + /** benchmark_update_int_st : RO; bitpos: [6]; default: 0; + * need_des + */ + uint32_t benchmark_update_int_st:1; + uint32_t reserved_7:25; }; uint32_t val; } rtc_touch_int_st_reg_t; @@ -110,7 +116,11 @@ typedef union { * need_des */ uint32_t approach_loop_done_int_ena:1; - uint32_t reserved_6:26; + /** benchmark_update_int_ena : R/W; bitpos: [6]; default: 0; + * need_des + */ + uint32_t benchmark_update_int_ena:1; + uint32_t reserved_7:25; }; uint32_t val; } rtc_touch_int_ena_reg_t; @@ -144,7 +154,11 @@ typedef union { * need_des */ uint32_t approach_loop_done_int_clr:1; - uint32_t reserved_6:26; + /** benchmark_update_int_clr : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t benchmark_update_int_clr:1; + uint32_t reserved_7:25; }; uint32_t val; } rtc_touch_int_clr_reg_t; @@ -162,7 +176,7 @@ typedef union { * need_des */ uint32_t meas_done:1; - /** scan_curr : RO; bitpos: [19:16]; default: 0; + /** scan_curr : RO; bitpos: [19:16]; default: 15; * need_des */ uint32_t scan_curr:4; @@ -299,11 +313,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 2294548; - * need_des - */ - uint32_t date:28; - uint32_t reserved_28:3; + uint32_t reserved_0:31; /** clk_en : R/W; bitpos: [31]; default: 0; * need_des */ diff --git a/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_reg.h deleted file mode 100644 index c782014e86f5..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_reg.h +++ /dev/null @@ -1,1579 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** UART_FIFO_REG register - * FIFO data register - */ -#define UART_FIFO_REG(i) (DR_REG_UART_BASE(i) + 0x0) -/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; - * UART $n accesses FIFO via this register. - */ -#define UART_RXFIFO_RD_BYTE 0x000000FFU -#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S) -#define UART_RXFIFO_RD_BYTE_V 0x000000FFU -#define UART_RXFIFO_RD_BYTE_S 0 - -/** UART_INT_RAW_REG register - * Raw interrupt status - */ -#define UART_INT_RAW_REG(i) (DR_REG_UART_BASE(i) + 0x4) -/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * This interrupt raw bit turns to high level when receiver receives more data than - * what rxfifo_full_thrhd specifies. - */ -#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) -#define UART_RXFIFO_FULL_INT_RAW_M (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S) -#define UART_RXFIFO_FULL_INT_RAW_V 0x00000001U -#define UART_RXFIFO_FULL_INT_RAW_S 0 -/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; - * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is - * less than what txfifo_empty_thrhd specifies . - */ -#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_RAW_M (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S) -#define UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001U -#define UART_TXFIFO_EMPTY_INT_RAW_S 1 -/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a parity error in - * the data. - */ -#define UART_PARITY_ERR_INT_RAW (BIT(2)) -#define UART_PARITY_ERR_INT_RAW_M (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S) -#define UART_PARITY_ERR_INT_RAW_V 0x00000001U -#define UART_PARITY_ERR_INT_RAW_S 2 -/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a data frame error - * . - */ -#define UART_FRM_ERR_INT_RAW (BIT(3)) -#define UART_FRM_ERR_INT_RAW_M (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S) -#define UART_FRM_ERR_INT_RAW_V 0x00000001U -#define UART_FRM_ERR_INT_RAW_S 3 -/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * This interrupt raw bit turns to high level when receiver receives more data than - * the FIFO can store. - */ -#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) -#define UART_RXFIFO_OVF_INT_RAW_M (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S) -#define UART_RXFIFO_OVF_INT_RAW_V 0x00000001U -#define UART_RXFIFO_OVF_INT_RAW_S 4 -/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * This interrupt raw bit turns to high level when receiver detects the edge change of - * DSRn signal. - */ -#define UART_DSR_CHG_INT_RAW (BIT(5)) -#define UART_DSR_CHG_INT_RAW_M (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S) -#define UART_DSR_CHG_INT_RAW_V 0x00000001U -#define UART_DSR_CHG_INT_RAW_S 5 -/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * This interrupt raw bit turns to high level when receiver detects the edge change of - * CTSn signal. - */ -#define UART_CTS_CHG_INT_RAW (BIT(6)) -#define UART_CTS_CHG_INT_RAW_M (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S) -#define UART_CTS_CHG_INT_RAW_V 0x00000001U -#define UART_CTS_CHG_INT_RAW_S 6 -/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a 0 after the stop - * bit. - */ -#define UART_BRK_DET_INT_RAW (BIT(7)) -#define UART_BRK_DET_INT_RAW_M (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S) -#define UART_BRK_DET_INT_RAW_V 0x00000001U -#define UART_BRK_DET_INT_RAW_S 7 -/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * This interrupt raw bit turns to high level when receiver takes more time than - * rx_tout_thrhd to receive a byte. - */ -#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) -#define UART_RXFIFO_TOUT_INT_RAW_M (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S) -#define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U -#define UART_RXFIFO_TOUT_INT_RAW_S 8 -/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver receives Xon char when - * uart_sw_flow_con_en is set to 1. - */ -#define UART_SW_XON_INT_RAW (BIT(9)) -#define UART_SW_XON_INT_RAW_M (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S) -#define UART_SW_XON_INT_RAW_V 0x00000001U -#define UART_SW_XON_INT_RAW_S 9 -/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * This interrupt raw bit turns to high level when receiver receives Xoff char when - * uart_sw_flow_con_en is set to 1. - */ -#define UART_SW_XOFF_INT_RAW (BIT(10)) -#define UART_SW_XOFF_INT_RAW_M (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S) -#define UART_SW_XOFF_INT_RAW_V 0x00000001U -#define UART_SW_XOFF_INT_RAW_S 10 -/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a glitch in the - * middle of a start bit. - */ -#define UART_GLITCH_DET_INT_RAW (BIT(11)) -#define UART_GLITCH_DET_INT_RAW_M (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S) -#define UART_GLITCH_DET_INT_RAW_V 0x00000001U -#define UART_GLITCH_DET_INT_RAW_S 11 -/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * This interrupt raw bit turns to high level when transmitter completes sending - * NULL characters after all data in Tx-FIFO are sent. - */ -#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) -#define UART_TX_BRK_DONE_INT_RAW_M (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S) -#define UART_TX_BRK_DONE_INT_RAW_V 0x00000001U -#define UART_TX_BRK_DONE_INT_RAW_S 12 -/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * This interrupt raw bit turns to high level when transmitter has kept the shortest - * duration after sending the last data. - */ -#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S) -#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001U -#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 -/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; - * This interrupt raw bit turns to high level when transmitter has send out all data - * in FIFO. - */ -#define UART_TX_DONE_INT_RAW (BIT(14)) -#define UART_TX_DONE_INT_RAW_M (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S) -#define UART_TX_DONE_INT_RAW_V 0x00000001U -#define UART_TX_DONE_INT_RAW_S 14 -/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a parity error - * from the echo of transmitter in rs485 mode. - */ -#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_RAW_M (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S) -#define UART_RS485_PARITY_ERR_INT_RAW_V 0x00000001U -#define UART_RS485_PARITY_ERR_INT_RAW_S 15 -/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a data frame error - * from the echo of transmitter in rs485 mode. - */ -#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) -#define UART_RS485_FRM_ERR_INT_RAW_M (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S) -#define UART_RS485_FRM_ERR_INT_RAW_V 0x00000001U -#define UART_RS485_FRM_ERR_INT_RAW_S 16 -/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; - * This interrupt raw bit turns to high level when detects a clash between transmitter - * and receiver in rs485 mode. - */ -#define UART_RS485_CLASH_INT_RAW (BIT(17)) -#define UART_RS485_CLASH_INT_RAW_M (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S) -#define UART_RS485_CLASH_INT_RAW_V 0x00000001U -#define UART_RS485_CLASH_INT_RAW_S 17 -/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; - * This interrupt raw bit turns to high level when receiver detects the configured - * at_cmd char. - */ -#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_RAW_M (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S) -#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001U -#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 -/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; - * This interrupt raw bit turns to high level when input rxd edge changes more times - * than what reg_active_threshold specifies in light sleeping mode. - */ -#define UART_WAKEUP_INT_RAW (BIT(19)) -#define UART_WAKEUP_INT_RAW_M (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S) -#define UART_WAKEUP_INT_RAW_V 0x00000001U -#define UART_WAKEUP_INT_RAW_S 19 - -/** UART_INT_ST_REG register - * Masked interrupt status - */ -#define UART_INT_ST_REG(i) (DR_REG_UART_BASE(i) + 0x8) -/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; - * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. - */ -#define UART_RXFIFO_FULL_INT_ST (BIT(0)) -#define UART_RXFIFO_FULL_INT_ST_M (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S) -#define UART_RXFIFO_FULL_INT_ST_V 0x00000001U -#define UART_RXFIFO_FULL_INT_ST_S 0 -/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; - * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set - * to 1. - */ -#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ST_M (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S) -#define UART_TXFIFO_EMPTY_INT_ST_V 0x00000001U -#define UART_TXFIFO_EMPTY_INT_ST_S 1 -/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; - * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. - */ -#define UART_PARITY_ERR_INT_ST (BIT(2)) -#define UART_PARITY_ERR_INT_ST_M (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S) -#define UART_PARITY_ERR_INT_ST_V 0x00000001U -#define UART_PARITY_ERR_INT_ST_S 2 -/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; - * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. - */ -#define UART_FRM_ERR_INT_ST (BIT(3)) -#define UART_FRM_ERR_INT_ST_M (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S) -#define UART_FRM_ERR_INT_ST_V 0x00000001U -#define UART_FRM_ERR_INT_ST_S 3 -/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; - * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. - */ -#define UART_RXFIFO_OVF_INT_ST (BIT(4)) -#define UART_RXFIFO_OVF_INT_ST_M (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S) -#define UART_RXFIFO_OVF_INT_ST_V 0x00000001U -#define UART_RXFIFO_OVF_INT_ST_S 4 -/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; - * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. - */ -#define UART_DSR_CHG_INT_ST (BIT(5)) -#define UART_DSR_CHG_INT_ST_M (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S) -#define UART_DSR_CHG_INT_ST_V 0x00000001U -#define UART_DSR_CHG_INT_ST_S 5 -/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; - * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. - */ -#define UART_CTS_CHG_INT_ST (BIT(6)) -#define UART_CTS_CHG_INT_ST_M (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S) -#define UART_CTS_CHG_INT_ST_V 0x00000001U -#define UART_CTS_CHG_INT_ST_S 6 -/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; - * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. - */ -#define UART_BRK_DET_INT_ST (BIT(7)) -#define UART_BRK_DET_INT_ST_M (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S) -#define UART_BRK_DET_INT_ST_V 0x00000001U -#define UART_BRK_DET_INT_ST_S 7 -/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; - * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. - */ -#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ST_M (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S) -#define UART_RXFIFO_TOUT_INT_ST_V 0x00000001U -#define UART_RXFIFO_TOUT_INT_ST_S 8 -/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; - * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. - */ -#define UART_SW_XON_INT_ST (BIT(9)) -#define UART_SW_XON_INT_ST_M (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S) -#define UART_SW_XON_INT_ST_V 0x00000001U -#define UART_SW_XON_INT_ST_S 9 -/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; - * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. - */ -#define UART_SW_XOFF_INT_ST (BIT(10)) -#define UART_SW_XOFF_INT_ST_M (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S) -#define UART_SW_XOFF_INT_ST_V 0x00000001U -#define UART_SW_XOFF_INT_ST_S 10 -/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; - * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. - */ -#define UART_GLITCH_DET_INT_ST (BIT(11)) -#define UART_GLITCH_DET_INT_ST_M (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S) -#define UART_GLITCH_DET_INT_ST_V 0x00000001U -#define UART_GLITCH_DET_INT_ST_S 11 -/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; - * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. - */ -#define UART_TX_BRK_DONE_INT_ST (BIT(12)) -#define UART_TX_BRK_DONE_INT_ST_M (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S) -#define UART_TX_BRK_DONE_INT_ST_V 0x00000001U -#define UART_TX_BRK_DONE_INT_ST_S 12 -/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; - * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena - * is set to 1. - */ -#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ST_M (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S) -#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001U -#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 -/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; - * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. - */ -#define UART_TX_DONE_INT_ST (BIT(14)) -#define UART_TX_DONE_INT_ST_M (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S) -#define UART_TX_DONE_INT_ST_V 0x00000001U -#define UART_TX_DONE_INT_ST_S 14 -/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0; - * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is - * set to 1. - */ -#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ST_M (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S) -#define UART_RS485_PARITY_ERR_INT_ST_V 0x00000001U -#define UART_RS485_PARITY_ERR_INT_ST_S 15 -/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0; - * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set - * to 1. - */ -#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ST_M (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S) -#define UART_RS485_FRM_ERR_INT_ST_V 0x00000001U -#define UART_RS485_FRM_ERR_INT_ST_S 16 -/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0; - * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. - */ -#define UART_RS485_CLASH_INT_ST (BIT(17)) -#define UART_RS485_CLASH_INT_ST_M (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S) -#define UART_RS485_CLASH_INT_ST_V 0x00000001U -#define UART_RS485_CLASH_INT_ST_S 17 -/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; - * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set - * to 1. - */ -#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ST_M (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S) -#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001U -#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 -/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; - * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. - */ -#define UART_WAKEUP_INT_ST (BIT(19)) -#define UART_WAKEUP_INT_ST_M (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S) -#define UART_WAKEUP_INT_ST_V 0x00000001U -#define UART_WAKEUP_INT_ST_S 19 - -/** UART_INT_ENA_REG register - * Interrupt enable bits - */ -#define UART_INT_ENA_REG(i) (DR_REG_UART_BASE(i) + 0xc) -/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; - * This is the enable bit for rxfifo_full_int_st register. - */ -#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) -#define UART_RXFIFO_FULL_INT_ENA_M (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S) -#define UART_RXFIFO_FULL_INT_ENA_V 0x00000001U -#define UART_RXFIFO_FULL_INT_ENA_S 0 -/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; - * This is the enable bit for txfifo_empty_int_st register. - */ -#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ENA_M (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S) -#define UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001U -#define UART_TXFIFO_EMPTY_INT_ENA_S 1 -/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; - * This is the enable bit for parity_err_int_st register. - */ -#define UART_PARITY_ERR_INT_ENA (BIT(2)) -#define UART_PARITY_ERR_INT_ENA_M (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S) -#define UART_PARITY_ERR_INT_ENA_V 0x00000001U -#define UART_PARITY_ERR_INT_ENA_S 2 -/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; - * This is the enable bit for frm_err_int_st register. - */ -#define UART_FRM_ERR_INT_ENA (BIT(3)) -#define UART_FRM_ERR_INT_ENA_M (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S) -#define UART_FRM_ERR_INT_ENA_V 0x00000001U -#define UART_FRM_ERR_INT_ENA_S 3 -/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; - * This is the enable bit for rxfifo_ovf_int_st register. - */ -#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) -#define UART_RXFIFO_OVF_INT_ENA_M (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S) -#define UART_RXFIFO_OVF_INT_ENA_V 0x00000001U -#define UART_RXFIFO_OVF_INT_ENA_S 4 -/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; - * This is the enable bit for dsr_chg_int_st register. - */ -#define UART_DSR_CHG_INT_ENA (BIT(5)) -#define UART_DSR_CHG_INT_ENA_M (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S) -#define UART_DSR_CHG_INT_ENA_V 0x00000001U -#define UART_DSR_CHG_INT_ENA_S 5 -/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; - * This is the enable bit for cts_chg_int_st register. - */ -#define UART_CTS_CHG_INT_ENA (BIT(6)) -#define UART_CTS_CHG_INT_ENA_M (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S) -#define UART_CTS_CHG_INT_ENA_V 0x00000001U -#define UART_CTS_CHG_INT_ENA_S 6 -/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; - * This is the enable bit for brk_det_int_st register. - */ -#define UART_BRK_DET_INT_ENA (BIT(7)) -#define UART_BRK_DET_INT_ENA_M (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S) -#define UART_BRK_DET_INT_ENA_V 0x00000001U -#define UART_BRK_DET_INT_ENA_S 7 -/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; - * This is the enable bit for rxfifo_tout_int_st register. - */ -#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ENA_M (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S) -#define UART_RXFIFO_TOUT_INT_ENA_V 0x00000001U -#define UART_RXFIFO_TOUT_INT_ENA_S 8 -/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; - * This is the enable bit for sw_xon_int_st register. - */ -#define UART_SW_XON_INT_ENA (BIT(9)) -#define UART_SW_XON_INT_ENA_M (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S) -#define UART_SW_XON_INT_ENA_V 0x00000001U -#define UART_SW_XON_INT_ENA_S 9 -/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; - * This is the enable bit for sw_xoff_int_st register. - */ -#define UART_SW_XOFF_INT_ENA (BIT(10)) -#define UART_SW_XOFF_INT_ENA_M (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S) -#define UART_SW_XOFF_INT_ENA_V 0x00000001U -#define UART_SW_XOFF_INT_ENA_S 10 -/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; - * This is the enable bit for glitch_det_int_st register. - */ -#define UART_GLITCH_DET_INT_ENA (BIT(11)) -#define UART_GLITCH_DET_INT_ENA_M (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S) -#define UART_GLITCH_DET_INT_ENA_V 0x00000001U -#define UART_GLITCH_DET_INT_ENA_S 11 -/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; - * This is the enable bit for tx_brk_done_int_st register. - */ -#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) -#define UART_TX_BRK_DONE_INT_ENA_M (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S) -#define UART_TX_BRK_DONE_INT_ENA_V 0x00000001U -#define UART_TX_BRK_DONE_INT_ENA_S 12 -/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; - * This is the enable bit for tx_brk_idle_done_int_st register. - */ -#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S) -#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001U -#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 -/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; - * This is the enable bit for tx_done_int_st register. - */ -#define UART_TX_DONE_INT_ENA (BIT(14)) -#define UART_TX_DONE_INT_ENA_M (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S) -#define UART_TX_DONE_INT_ENA_V 0x00000001U -#define UART_TX_DONE_INT_ENA_S 14 -/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; - * This is the enable bit for rs485_parity_err_int_st register. - */ -#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ENA_M (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S) -#define UART_RS485_PARITY_ERR_INT_ENA_V 0x00000001U -#define UART_RS485_PARITY_ERR_INT_ENA_S 15 -/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; - * This is the enable bit for rs485_parity_err_int_st register. - */ -#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ENA_M (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S) -#define UART_RS485_FRM_ERR_INT_ENA_V 0x00000001U -#define UART_RS485_FRM_ERR_INT_ENA_S 16 -/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0; - * This is the enable bit for rs485_clash_int_st register. - */ -#define UART_RS485_CLASH_INT_ENA (BIT(17)) -#define UART_RS485_CLASH_INT_ENA_M (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S) -#define UART_RS485_CLASH_INT_ENA_V 0x00000001U -#define UART_RS485_CLASH_INT_ENA_S 17 -/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; - * This is the enable bit for at_cmd_char_det_int_st register. - */ -#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ENA_M (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S) -#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001U -#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 -/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; - * This is the enable bit for uart_wakeup_int_st register. - */ -#define UART_WAKEUP_INT_ENA (BIT(19)) -#define UART_WAKEUP_INT_ENA_M (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S) -#define UART_WAKEUP_INT_ENA_V 0x00000001U -#define UART_WAKEUP_INT_ENA_S 19 - -/** UART_INT_CLR_REG register - * Interrupt clear bits - */ -#define UART_INT_CLR_REG(i) (DR_REG_UART_BASE(i) + 0x10) -/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the rxfifo_full_int_raw interrupt. - */ -#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) -#define UART_RXFIFO_FULL_INT_CLR_M (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S) -#define UART_RXFIFO_FULL_INT_CLR_V 0x00000001U -#define UART_RXFIFO_FULL_INT_CLR_S 0 -/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear txfifo_empty_int_raw interrupt. - */ -#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_CLR_M (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S) -#define UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001U -#define UART_TXFIFO_EMPTY_INT_CLR_S 1 -/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear parity_err_int_raw interrupt. - */ -#define UART_PARITY_ERR_INT_CLR (BIT(2)) -#define UART_PARITY_ERR_INT_CLR_M (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S) -#define UART_PARITY_ERR_INT_CLR_V 0x00000001U -#define UART_PARITY_ERR_INT_CLR_S 2 -/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear frm_err_int_raw interrupt. - */ -#define UART_FRM_ERR_INT_CLR (BIT(3)) -#define UART_FRM_ERR_INT_CLR_M (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S) -#define UART_FRM_ERR_INT_CLR_V 0x00000001U -#define UART_FRM_ERR_INT_CLR_S 3 -/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear rxfifo_ovf_int_raw interrupt. - */ -#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) -#define UART_RXFIFO_OVF_INT_CLR_M (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S) -#define UART_RXFIFO_OVF_INT_CLR_V 0x00000001U -#define UART_RXFIFO_OVF_INT_CLR_S 4 -/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the dsr_chg_int_raw interrupt. - */ -#define UART_DSR_CHG_INT_CLR (BIT(5)) -#define UART_DSR_CHG_INT_CLR_M (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S) -#define UART_DSR_CHG_INT_CLR_V 0x00000001U -#define UART_DSR_CHG_INT_CLR_S 5 -/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the cts_chg_int_raw interrupt. - */ -#define UART_CTS_CHG_INT_CLR (BIT(6)) -#define UART_CTS_CHG_INT_CLR_M (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S) -#define UART_CTS_CHG_INT_CLR_V 0x00000001U -#define UART_CTS_CHG_INT_CLR_S 6 -/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the brk_det_int_raw interrupt. - */ -#define UART_BRK_DET_INT_CLR (BIT(7)) -#define UART_BRK_DET_INT_CLR_M (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S) -#define UART_BRK_DET_INT_CLR_V 0x00000001U -#define UART_BRK_DET_INT_CLR_S 7 -/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the rxfifo_tout_int_raw interrupt. - */ -#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) -#define UART_RXFIFO_TOUT_INT_CLR_M (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S) -#define UART_RXFIFO_TOUT_INT_CLR_V 0x00000001U -#define UART_RXFIFO_TOUT_INT_CLR_S 8 -/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the sw_xon_int_raw interrupt. - */ -#define UART_SW_XON_INT_CLR (BIT(9)) -#define UART_SW_XON_INT_CLR_M (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S) -#define UART_SW_XON_INT_CLR_V 0x00000001U -#define UART_SW_XON_INT_CLR_S 9 -/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the sw_xoff_int_raw interrupt. - */ -#define UART_SW_XOFF_INT_CLR (BIT(10)) -#define UART_SW_XOFF_INT_CLR_M (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S) -#define UART_SW_XOFF_INT_CLR_V 0x00000001U -#define UART_SW_XOFF_INT_CLR_S 10 -/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the glitch_det_int_raw interrupt. - */ -#define UART_GLITCH_DET_INT_CLR (BIT(11)) -#define UART_GLITCH_DET_INT_CLR_M (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S) -#define UART_GLITCH_DET_INT_CLR_V 0x00000001U -#define UART_GLITCH_DET_INT_CLR_S 11 -/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the tx_brk_done_int_raw interrupt.. - */ -#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) -#define UART_TX_BRK_DONE_INT_CLR_M (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S) -#define UART_TX_BRK_DONE_INT_CLR_V 0x00000001U -#define UART_TX_BRK_DONE_INT_CLR_S 12 -/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. - */ -#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S) -#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001U -#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 -/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; - * Set this bit to clear the tx_done_int_raw interrupt. - */ -#define UART_TX_DONE_INT_CLR (BIT(14)) -#define UART_TX_DONE_INT_CLR_M (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S) -#define UART_TX_DONE_INT_CLR_V 0x00000001U -#define UART_TX_DONE_INT_CLR_S 14 -/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0; - * Set this bit to clear the rs485_parity_err_int_raw interrupt. - */ -#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_CLR_M (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S) -#define UART_RS485_PARITY_ERR_INT_CLR_V 0x00000001U -#define UART_RS485_PARITY_ERR_INT_CLR_S 15 -/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0; - * Set this bit to clear the rs485_frm_err_int_raw interrupt. - */ -#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) -#define UART_RS485_FRM_ERR_INT_CLR_M (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S) -#define UART_RS485_FRM_ERR_INT_CLR_V 0x00000001U -#define UART_RS485_FRM_ERR_INT_CLR_S 16 -/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0; - * Set this bit to clear the rs485_clash_int_raw interrupt. - */ -#define UART_RS485_CLASH_INT_CLR (BIT(17)) -#define UART_RS485_CLASH_INT_CLR_M (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S) -#define UART_RS485_CLASH_INT_CLR_V 0x00000001U -#define UART_RS485_CLASH_INT_CLR_S 17 -/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; - * Set this bit to clear the at_cmd_char_det_int_raw interrupt. - */ -#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_CLR_M (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S) -#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001U -#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 -/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; - * Set this bit to clear the uart_wakeup_int_raw interrupt. - */ -#define UART_WAKEUP_INT_CLR (BIT(19)) -#define UART_WAKEUP_INT_CLR_M (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S) -#define UART_WAKEUP_INT_CLR_V 0x00000001U -#define UART_WAKEUP_INT_CLR_S 19 - -/** UART_CLKDIV_SYNC_REG register - * Clock divider configuration - */ -#define UART_CLKDIV_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x14) -/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; - * The integral part of the frequency divider factor. - */ -#define UART_CLKDIV 0x00000FFFU -#define UART_CLKDIV_M (UART_CLKDIV_V << UART_CLKDIV_S) -#define UART_CLKDIV_V 0x00000FFFU -#define UART_CLKDIV_S 0 -/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; - * The decimal part of the frequency divider factor. - */ -#define UART_CLKDIV_FRAG 0x0000000FU -#define UART_CLKDIV_FRAG_M (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S) -#define UART_CLKDIV_FRAG_V 0x0000000FU -#define UART_CLKDIV_FRAG_S 20 - -/** UART_RX_FILT_REG register - * Rx Filter configuration - */ -#define UART_RX_FILT_REG(i) (DR_REG_UART_BASE(i) + 0x18) -/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; - * when input pulse width is lower than this value the pulse is ignored. - */ -#define UART_GLITCH_FILT 0x000000FFU -#define UART_GLITCH_FILT_M (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S) -#define UART_GLITCH_FILT_V 0x000000FFU -#define UART_GLITCH_FILT_S 0 -/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; - * Set this bit to enable Rx signal filter. - */ -#define UART_GLITCH_FILT_EN (BIT(8)) -#define UART_GLITCH_FILT_EN_M (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S) -#define UART_GLITCH_FILT_EN_V 0x00000001U -#define UART_GLITCH_FILT_EN_S 8 - -/** UART_STATUS_REG register - * UART status register - */ -#define UART_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x1c) -/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0; - * Stores the byte number of valid data in Rx-FIFO. - */ -#define UART_RXFIFO_CNT 0x000000FFU -#define UART_RXFIFO_CNT_M (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S) -#define UART_RXFIFO_CNT_V 0x000000FFU -#define UART_RXFIFO_CNT_S 0 -/** UART_DSRN : RO; bitpos: [13]; default: 0; - * The register represent the level value of the internal uart dsr signal. - */ -#define UART_DSRN (BIT(13)) -#define UART_DSRN_M (UART_DSRN_V << UART_DSRN_S) -#define UART_DSRN_V 0x00000001U -#define UART_DSRN_S 13 -/** UART_CTSN : RO; bitpos: [14]; default: 1; - * This register represent the level value of the internal uart cts signal. - */ -#define UART_CTSN (BIT(14)) -#define UART_CTSN_M (UART_CTSN_V << UART_CTSN_S) -#define UART_CTSN_V 0x00000001U -#define UART_CTSN_S 14 -/** UART_RXD : RO; bitpos: [15]; default: 1; - * This register represent the level value of the internal uart rxd signal. - */ -#define UART_RXD (BIT(15)) -#define UART_RXD_M (UART_RXD_V << UART_RXD_S) -#define UART_RXD_V 0x00000001U -#define UART_RXD_S 15 -/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0; - * Stores the byte number of data in Tx-FIFO. - */ -#define UART_TXFIFO_CNT 0x000000FFU -#define UART_TXFIFO_CNT_M (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S) -#define UART_TXFIFO_CNT_V 0x000000FFU -#define UART_TXFIFO_CNT_S 16 -/** UART_DTRN : RO; bitpos: [29]; default: 1; - * This bit represents the level of the internal uart dtr signal. - */ -#define UART_DTRN (BIT(29)) -#define UART_DTRN_M (UART_DTRN_V << UART_DTRN_S) -#define UART_DTRN_V 0x00000001U -#define UART_DTRN_S 29 -/** UART_RTSN : RO; bitpos: [30]; default: 1; - * This bit represents the level of the internal uart rts signal. - */ -#define UART_RTSN (BIT(30)) -#define UART_RTSN_M (UART_RTSN_V << UART_RTSN_S) -#define UART_RTSN_V 0x00000001U -#define UART_RTSN_S 30 -/** UART_TXD : RO; bitpos: [31]; default: 1; - * This bit represents the level of the internal uart txd signal. - */ -#define UART_TXD (BIT(31)) -#define UART_TXD_M (UART_TXD_V << UART_TXD_S) -#define UART_TXD_V 0x00000001U -#define UART_TXD_S 31 - -/** UART_CONF0_SYNC_REG register - * a - */ -#define UART_CONF0_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x20) -/** UART_PARITY : R/W; bitpos: [0]; default: 0; - * This register is used to configure the parity check mode. - */ -#define UART_PARITY (BIT(0)) -#define UART_PARITY_M (UART_PARITY_V << UART_PARITY_S) -#define UART_PARITY_V 0x00000001U -#define UART_PARITY_S 0 -/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0; - * Set this bit to enable uart parity check. - */ -#define UART_PARITY_EN (BIT(1)) -#define UART_PARITY_EN_M (UART_PARITY_EN_V << UART_PARITY_EN_S) -#define UART_PARITY_EN_V 0x00000001U -#define UART_PARITY_EN_S 1 -/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; - * This register is used to set the length of data. - */ -#define UART_BIT_NUM 0x00000003U -#define UART_BIT_NUM_M (UART_BIT_NUM_V << UART_BIT_NUM_S) -#define UART_BIT_NUM_V 0x00000003U -#define UART_BIT_NUM_S 2 -/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; - * This register is used to set the length of stop bit. - */ -#define UART_STOP_BIT_NUM 0x00000003U -#define UART_STOP_BIT_NUM_M (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S) -#define UART_STOP_BIT_NUM_V 0x00000003U -#define UART_STOP_BIT_NUM_S 4 -/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0; - * Set this bit to enable transmitter to send NULL when the process of sending data - * is done. - */ -#define UART_TXD_BRK (BIT(6)) -#define UART_TXD_BRK_M (UART_TXD_BRK_V << UART_TXD_BRK_S) -#define UART_TXD_BRK_V 0x00000001U -#define UART_TXD_BRK_S 6 -/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0; - * Set this bit to enable IrDA loopback mode. - */ -#define UART_IRDA_DPLX (BIT(7)) -#define UART_IRDA_DPLX_M (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S) -#define UART_IRDA_DPLX_V 0x00000001U -#define UART_IRDA_DPLX_S 7 -/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0; - * This is the start enable bit for IrDA transmitter. - */ -#define UART_IRDA_TX_EN (BIT(8)) -#define UART_IRDA_TX_EN_M (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S) -#define UART_IRDA_TX_EN_V 0x00000001U -#define UART_IRDA_TX_EN_S 8 -/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0; - * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA - * transmitter's 11th bit to 0. - */ -#define UART_IRDA_WCTL (BIT(9)) -#define UART_IRDA_WCTL_M (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S) -#define UART_IRDA_WCTL_V 0x00000001U -#define UART_IRDA_WCTL_S 9 -/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0; - * Set this bit to invert the level of IrDA transmitter. - */ -#define UART_IRDA_TX_INV (BIT(10)) -#define UART_IRDA_TX_INV_M (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S) -#define UART_IRDA_TX_INV_V 0x00000001U -#define UART_IRDA_TX_INV_S 10 -/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0; - * Set this bit to invert the level of IrDA receiver. - */ -#define UART_IRDA_RX_INV (BIT(11)) -#define UART_IRDA_RX_INV_M (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S) -#define UART_IRDA_RX_INV_V 0x00000001U -#define UART_IRDA_RX_INV_S 11 -/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0; - * Set this bit to enable uart loopback test mode. - */ -#define UART_LOOPBACK (BIT(12)) -#define UART_LOOPBACK_M (UART_LOOPBACK_V << UART_LOOPBACK_S) -#define UART_LOOPBACK_V 0x00000001U -#define UART_LOOPBACK_S 12 -/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; - * Set this bit to enable flow control function for transmitter. - */ -#define UART_TX_FLOW_EN (BIT(13)) -#define UART_TX_FLOW_EN_M (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S) -#define UART_TX_FLOW_EN_V 0x00000001U -#define UART_TX_FLOW_EN_S 13 -/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0; - * Set this bit to enable IrDA protocol. - */ -#define UART_IRDA_EN (BIT(14)) -#define UART_IRDA_EN_M (UART_IRDA_EN_V << UART_IRDA_EN_S) -#define UART_IRDA_EN_V 0x00000001U -#define UART_IRDA_EN_S 14 -/** UART_RXD_INV : R/W; bitpos: [15]; default: 0; - * Set this bit to inverse the level value of uart rxd signal. - */ -#define UART_RXD_INV (BIT(15)) -#define UART_RXD_INV_M (UART_RXD_INV_V << UART_RXD_INV_S) -#define UART_RXD_INV_V 0x00000001U -#define UART_RXD_INV_S 15 -/** UART_TXD_INV : R/W; bitpos: [16]; default: 0; - * Set this bit to inverse the level value of uart txd signal. - */ -#define UART_TXD_INV (BIT(16)) -#define UART_TXD_INV_M (UART_TXD_INV_V << UART_TXD_INV_S) -#define UART_TXD_INV_V 0x00000001U -#define UART_TXD_INV_S 16 -/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; - * Disable UART Rx data overflow detect. - */ -#define UART_DIS_RX_DAT_OVF (BIT(17)) -#define UART_DIS_RX_DAT_OVF_M (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S) -#define UART_DIS_RX_DAT_OVF_V 0x00000001U -#define UART_DIS_RX_DAT_OVF_S 17 -/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; - * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver - * stores the data even if the received data is wrong. - */ -#define UART_ERR_WR_MASK (BIT(18)) -#define UART_ERR_WR_MASK_M (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S) -#define UART_ERR_WR_MASK_V 0x00000001U -#define UART_ERR_WR_MASK_S 18 -/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0; - * This is the enable bit for detecting baudrate. - */ -#define UART_AUTOBAUD_EN (BIT(19)) -#define UART_AUTOBAUD_EN_M (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S) -#define UART_AUTOBAUD_EN_V 0x00000001U -#define UART_AUTOBAUD_EN_S 19 -/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0; - * UART memory clock gate enable signal. - */ -#define UART_MEM_CLK_EN (BIT(20)) -#define UART_MEM_CLK_EN_M (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S) -#define UART_MEM_CLK_EN_V 0x00000001U -#define UART_MEM_CLK_EN_S 20 -/** UART_SW_RTS : R/W; bitpos: [21]; default: 0; - * This register is used to configure the software rts signal which is used in - * software flow control. - */ -#define UART_SW_RTS (BIT(21)) -#define UART_SW_RTS_M (UART_SW_RTS_V << UART_SW_RTS_S) -#define UART_SW_RTS_V 0x00000001U -#define UART_SW_RTS_S 21 -/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; - * Set this bit to reset the uart receive-FIFO. - */ -#define UART_RXFIFO_RST (BIT(22)) -#define UART_RXFIFO_RST_M (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S) -#define UART_RXFIFO_RST_V 0x00000001U -#define UART_RXFIFO_RST_S 22 -/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; - * Set this bit to reset the uart transmit-FIFO. - */ -#define UART_TXFIFO_RST (BIT(23)) -#define UART_TXFIFO_RST_M (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S) -#define UART_TXFIFO_RST_V 0x00000001U -#define UART_TXFIFO_RST_S 23 - -/** UART_CONF1_REG register - * Configuration register 1 - */ -#define UART_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x24) -/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96; - * It will produce rxfifo_full_int interrupt when receiver receives more data than - * this register value. - */ -#define UART_RXFIFO_FULL_THRHD 0x000000FFU -#define UART_RXFIFO_FULL_THRHD_M (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S) -#define UART_RXFIFO_FULL_THRHD_V 0x000000FFU -#define UART_RXFIFO_FULL_THRHD_S 0 -/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96; - * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less - * than this register value. - */ -#define UART_TXFIFO_EMPTY_THRHD 0x000000FFU -#define UART_TXFIFO_EMPTY_THRHD_M (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S) -#define UART_TXFIFO_EMPTY_THRHD_V 0x000000FFU -#define UART_TXFIFO_EMPTY_THRHD_S 8 -/** UART_CTS_INV : R/W; bitpos: [16]; default: 0; - * Set this bit to inverse the level value of uart cts signal. - */ -#define UART_CTS_INV (BIT(16)) -#define UART_CTS_INV_M (UART_CTS_INV_V << UART_CTS_INV_S) -#define UART_CTS_INV_V 0x00000001U -#define UART_CTS_INV_S 16 -/** UART_DSR_INV : R/W; bitpos: [17]; default: 0; - * Set this bit to inverse the level value of uart dsr signal. - */ -#define UART_DSR_INV (BIT(17)) -#define UART_DSR_INV_M (UART_DSR_INV_V << UART_DSR_INV_S) -#define UART_DSR_INV_V 0x00000001U -#define UART_DSR_INV_S 17 -/** UART_RTS_INV : R/W; bitpos: [18]; default: 0; - * Set this bit to inverse the level value of uart rts signal. - */ -#define UART_RTS_INV (BIT(18)) -#define UART_RTS_INV_M (UART_RTS_INV_V << UART_RTS_INV_S) -#define UART_RTS_INV_V 0x00000001U -#define UART_RTS_INV_S 18 -/** UART_DTR_INV : R/W; bitpos: [19]; default: 0; - * Set this bit to inverse the level value of uart dtr signal. - */ -#define UART_DTR_INV (BIT(19)) -#define UART_DTR_INV_M (UART_DTR_INV_V << UART_DTR_INV_S) -#define UART_DTR_INV_V 0x00000001U -#define UART_DTR_INV_S 19 -/** UART_SW_DTR : R/W; bitpos: [20]; default: 0; - * This register is used to configure the software dtr signal which is used in - * software flow control. - */ -#define UART_SW_DTR (BIT(20)) -#define UART_SW_DTR_M (UART_SW_DTR_V << UART_SW_DTR_S) -#define UART_SW_DTR_V 0x00000001U -#define UART_SW_DTR_S 20 -/** UART_CLK_EN : R/W; bitpos: [21]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes - * registers. - */ -#define UART_CLK_EN (BIT(21)) -#define UART_CLK_EN_M (UART_CLK_EN_V << UART_CLK_EN_S) -#define UART_CLK_EN_V 0x00000001U -#define UART_CLK_EN_S 21 - -/** UART_HWFC_CONF_SYNC_REG register - * Hardware flow-control configuration - */ -#define UART_HWFC_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x2c) -/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0; - * This register is used to configure the maximum amount of data that can be received - * when hardware flow control works. - */ -#define UART_RX_FLOW_THRHD 0x000000FFU -#define UART_RX_FLOW_THRHD_M (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S) -#define UART_RX_FLOW_THRHD_V 0x000000FFU -#define UART_RX_FLOW_THRHD_S 0 -/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; - * This is the flow enable bit for UART receiver. - */ -#define UART_RX_FLOW_EN (BIT(8)) -#define UART_RX_FLOW_EN_M (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S) -#define UART_RX_FLOW_EN_V 0x00000001U -#define UART_RX_FLOW_EN_S 8 - -/** UART_SLEEP_CONF0_REG register - * UART sleep configure register 0 - */ -#define UART_SLEEP_CONF0_REG(i) (DR_REG_UART_BASE(i) + 0x30) -/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; - * This register restores the specified wake up char1 to wake up - */ -#define UART_WK_CHAR1 0x000000FFU -#define UART_WK_CHAR1_M (UART_WK_CHAR1_V << UART_WK_CHAR1_S) -#define UART_WK_CHAR1_V 0x000000FFU -#define UART_WK_CHAR1_S 0 -/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0; - * This register restores the specified wake up char2 to wake up - */ -#define UART_WK_CHAR2 0x000000FFU -#define UART_WK_CHAR2_M (UART_WK_CHAR2_V << UART_WK_CHAR2_S) -#define UART_WK_CHAR2_V 0x000000FFU -#define UART_WK_CHAR2_S 8 -/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0; - * This register restores the specified wake up char3 to wake up - */ -#define UART_WK_CHAR3 0x000000FFU -#define UART_WK_CHAR3_M (UART_WK_CHAR3_V << UART_WK_CHAR3_S) -#define UART_WK_CHAR3_V 0x000000FFU -#define UART_WK_CHAR3_S 16 -/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0; - * This register restores the specified wake up char4 to wake up - */ -#define UART_WK_CHAR4 0x000000FFU -#define UART_WK_CHAR4_M (UART_WK_CHAR4_V << UART_WK_CHAR4_S) -#define UART_WK_CHAR4_V 0x000000FFU -#define UART_WK_CHAR4_S 24 - -/** UART_SLEEP_CONF1_REG register - * UART sleep configure register 1 - */ -#define UART_SLEEP_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x34) -/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; - * This register restores the specified char0 to wake up - */ -#define UART_WK_CHAR0 0x000000FFU -#define UART_WK_CHAR0_M (UART_WK_CHAR0_V << UART_WK_CHAR0_S) -#define UART_WK_CHAR0_V 0x000000FFU -#define UART_WK_CHAR0_S 0 - -/** UART_SLEEP_CONF2_REG register - * UART sleep configure register 2 - */ -#define UART_SLEEP_CONF2_REG(i) (DR_REG_UART_BASE(i) + 0x38) -/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; - * The uart is activated from light sleeping mode when the input rxd edge changes more - * times than this register value. - */ -#define UART_ACTIVE_THRESHOLD 0x000003FFU -#define UART_ACTIVE_THRESHOLD_M (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S) -#define UART_ACTIVE_THRESHOLD_V 0x000003FFU -#define UART_ACTIVE_THRESHOLD_S 0 -/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1; - * In wake up mode 1 this field is used to set the received data number threshold to - * wake up chip. - */ -#define UART_RX_WAKE_UP_THRHD 0x000000FFU -#define UART_RX_WAKE_UP_THRHD_M (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S) -#define UART_RX_WAKE_UP_THRHD_V 0x000000FFU -#define UART_RX_WAKE_UP_THRHD_S 10 -/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5; - * This register is used to select number of wake up char. - */ -#define UART_WK_CHAR_NUM 0x00000007U -#define UART_WK_CHAR_NUM_M (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S) -#define UART_WK_CHAR_NUM_V 0x00000007U -#define UART_WK_CHAR_NUM_S 18 -/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; - * This register is used to mask wake up char. - */ -#define UART_WK_CHAR_MASK 0x0000001FU -#define UART_WK_CHAR_MASK_M (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S) -#define UART_WK_CHAR_MASK_V 0x0000001FU -#define UART_WK_CHAR_MASK_S 21 -/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; - * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: - * received data number larger than - */ -#define UART_WK_MODE_SEL 0x00000003U -#define UART_WK_MODE_SEL_M (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S) -#define UART_WK_MODE_SEL_V 0x00000003U -#define UART_WK_MODE_SEL_S 26 - -/** UART_SWFC_CONF0_SYNC_REG register - * Software flow-control character configuration - */ -#define UART_SWFC_CONF0_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x3c) -/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; - * This register stores the Xon flow control char. - */ -#define UART_XON_CHAR 0x000000FFU -#define UART_XON_CHAR_M (UART_XON_CHAR_V << UART_XON_CHAR_S) -#define UART_XON_CHAR_V 0x000000FFU -#define UART_XON_CHAR_S 0 -/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19; - * This register stores the Xoff flow control char. - */ -#define UART_XOFF_CHAR 0x000000FFU -#define UART_XOFF_CHAR_M (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S) -#define UART_XOFF_CHAR_V 0x000000FFU -#define UART_XOFF_CHAR_S 8 -/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; - * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In - * this status, UART Tx can not transmit XOFF even the received data number is larger - * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when - * UART Tx is disabled. - */ -#define UART_XON_XOFF_STILL_SEND (BIT(16)) -#define UART_XON_XOFF_STILL_SEND_M (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S) -#define UART_XON_XOFF_STILL_SEND_V 0x00000001U -#define UART_XON_XOFF_STILL_SEND_S 16 -/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; - * Set this bit to enable software flow control. It is used with register sw_xon or - * sw_xoff. - */ -#define UART_SW_FLOW_CON_EN (BIT(17)) -#define UART_SW_FLOW_CON_EN_M (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S) -#define UART_SW_FLOW_CON_EN_V 0x00000001U -#define UART_SW_FLOW_CON_EN_S 17 -/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; - * Set this bit to remove flow control char from the received data. - */ -#define UART_XONOFF_DEL (BIT(18)) -#define UART_XONOFF_DEL_M (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S) -#define UART_XONOFF_DEL_V 0x00000001U -#define UART_XONOFF_DEL_S 18 -/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0; - * Set this bit to enable the transmitter to go on sending data. - */ -#define UART_FORCE_XON (BIT(19)) -#define UART_FORCE_XON_M (UART_FORCE_XON_V << UART_FORCE_XON_S) -#define UART_FORCE_XON_V 0x00000001U -#define UART_FORCE_XON_S 19 -/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; - * Set this bit to stop the transmitter from sending data. - */ -#define UART_FORCE_XOFF (BIT(20)) -#define UART_FORCE_XOFF_M (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S) -#define UART_FORCE_XOFF_V 0x00000001U -#define UART_FORCE_XOFF_S 20 -/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; - * Set this bit to send Xon char. It is cleared by hardware automatically. - */ -#define UART_SEND_XON (BIT(21)) -#define UART_SEND_XON_M (UART_SEND_XON_V << UART_SEND_XON_S) -#define UART_SEND_XON_V 0x00000001U -#define UART_SEND_XON_S 21 -/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; - * Set this bit to send Xoff char. It is cleared by hardware automatically. - */ -#define UART_SEND_XOFF (BIT(22)) -#define UART_SEND_XOFF_M (UART_SEND_XOFF_V << UART_SEND_XOFF_S) -#define UART_SEND_XOFF_V 0x00000001U -#define UART_SEND_XOFF_S 22 - -/** UART_SWFC_CONF1_REG register - * Software flow-control character configuration - */ -#define UART_SWFC_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x40) -/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0; - * When the data amount in Rx-FIFO is less than this register value with - * uart_sw_flow_con_en set to 1 it will send a Xon char. - */ -#define UART_XON_THRESHOLD 0x000000FFU -#define UART_XON_THRESHOLD_M (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S) -#define UART_XON_THRESHOLD_V 0x000000FFU -#define UART_XON_THRESHOLD_S 0 -/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224; - * When the data amount in Rx-FIFO is more than this register value with - * uart_sw_flow_con_en set to 1 it will send a Xoff char. - */ -#define UART_XOFF_THRESHOLD 0x000000FFU -#define UART_XOFF_THRESHOLD_M (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S) -#define UART_XOFF_THRESHOLD_V 0x000000FFU -#define UART_XOFF_THRESHOLD_S 8 - -/** UART_TXBRK_CONF_SYNC_REG register - * Tx Break character configuration - */ -#define UART_TXBRK_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x44) -/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; - * This register is used to configure the number of 0 to be sent after the process of - * sending data is done. It is active when txd_brk is set to 1. - */ -#define UART_TX_BRK_NUM 0x000000FFU -#define UART_TX_BRK_NUM_M (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S) -#define UART_TX_BRK_NUM_V 0x000000FFU -#define UART_TX_BRK_NUM_S 0 - -/** UART_IDLE_CONF_SYNC_REG register - * Frame-end idle configuration - */ -#define UART_IDLE_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x48) -/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; - * It will produce frame end signal when receiver takes more time to receive one byte - * data than this register value. - */ -#define UART_RX_IDLE_THRHD 0x000003FFU -#define UART_RX_IDLE_THRHD_M (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S) -#define UART_RX_IDLE_THRHD_V 0x000003FFU -#define UART_RX_IDLE_THRHD_S 0 -/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; - * This register is used to configure the duration time between transfers. - */ -#define UART_TX_IDLE_NUM 0x000003FFU -#define UART_TX_IDLE_NUM_M (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S) -#define UART_TX_IDLE_NUM_V 0x000003FFU -#define UART_TX_IDLE_NUM_S 10 - -/** UART_RS485_CONF_SYNC_REG register - * RS485 mode configuration - */ -#define UART_RS485_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x4c) -/** UART_RS485_EN : R/W; bitpos: [0]; default: 0; - * Set this bit to choose the rs485 mode. - */ -#define UART_RS485_EN (BIT(0)) -#define UART_RS485_EN_M (UART_RS485_EN_V << UART_RS485_EN_S) -#define UART_RS485_EN_V 0x00000001U -#define UART_RS485_EN_S 0 -/** UART_DL0_EN : R/W; bitpos: [1]; default: 0; - * Set this bit to delay the stop bit by 1 bit. - */ -#define UART_DL0_EN (BIT(1)) -#define UART_DL0_EN_M (UART_DL0_EN_V << UART_DL0_EN_S) -#define UART_DL0_EN_V 0x00000001U -#define UART_DL0_EN_S 1 -/** UART_DL1_EN : R/W; bitpos: [2]; default: 0; - * Set this bit to delay the stop bit by 1 bit. - */ -#define UART_DL1_EN (BIT(2)) -#define UART_DL1_EN_M (UART_DL1_EN_V << UART_DL1_EN_S) -#define UART_DL1_EN_V 0x00000001U -#define UART_DL1_EN_S 2 -/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0; - * Set this bit to enable receiver could receive data when the transmitter is - * transmitting data in rs485 mode. - */ -#define UART_RS485TX_RX_EN (BIT(3)) -#define UART_RS485TX_RX_EN_M (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S) -#define UART_RS485TX_RX_EN_V 0x00000001U -#define UART_RS485TX_RX_EN_S 3 -/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0; - * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. - */ -#define UART_RS485RXBY_TX_EN (BIT(4)) -#define UART_RS485RXBY_TX_EN_M (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S) -#define UART_RS485RXBY_TX_EN_V 0x00000001U -#define UART_RS485RXBY_TX_EN_S 4 -/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0; - * This register is used to delay the receiver's internal data signal. - */ -#define UART_RS485_RX_DLY_NUM (BIT(5)) -#define UART_RS485_RX_DLY_NUM_M (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S) -#define UART_RS485_RX_DLY_NUM_V 0x00000001U -#define UART_RS485_RX_DLY_NUM_S 5 -/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0; - * This register is used to delay the transmitter's internal data signal. - */ -#define UART_RS485_TX_DLY_NUM 0x0000000FU -#define UART_RS485_TX_DLY_NUM_M (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S) -#define UART_RS485_TX_DLY_NUM_V 0x0000000FU -#define UART_RS485_TX_DLY_NUM_S 6 - -/** UART_AT_CMD_PRECNT_SYNC_REG register - * Pre-sequence timing configuration - */ -#define UART_AT_CMD_PRECNT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x50) -/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; - * This register is used to configure the idle duration time before the first at_cmd - * is received by receiver. - */ -#define UART_PRE_IDLE_NUM 0x0000FFFFU -#define UART_PRE_IDLE_NUM_M (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S) -#define UART_PRE_IDLE_NUM_V 0x0000FFFFU -#define UART_PRE_IDLE_NUM_S 0 - -/** UART_AT_CMD_POSTCNT_SYNC_REG register - * Post-sequence timing configuration - */ -#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x54) -/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; - * This register is used to configure the duration time between the last at_cmd and - * the next data. - */ -#define UART_POST_IDLE_NUM 0x0000FFFFU -#define UART_POST_IDLE_NUM_M (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S) -#define UART_POST_IDLE_NUM_V 0x0000FFFFU -#define UART_POST_IDLE_NUM_S 0 - -/** UART_AT_CMD_GAPTOUT_SYNC_REG register - * Timeout configuration - */ -#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x58) -/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; - * This register is used to configure the duration time between the at_cmd chars. - */ -#define UART_RX_GAP_TOUT 0x0000FFFFU -#define UART_RX_GAP_TOUT_M (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S) -#define UART_RX_GAP_TOUT_V 0x0000FFFFU -#define UART_RX_GAP_TOUT_S 0 - -/** UART_AT_CMD_CHAR_SYNC_REG register - * AT escape sequence detection configuration - */ -#define UART_AT_CMD_CHAR_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x5c) -/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; - * This register is used to configure the content of at_cmd char. - */ -#define UART_AT_CMD_CHAR 0x000000FFU -#define UART_AT_CMD_CHAR_M (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S) -#define UART_AT_CMD_CHAR_V 0x000000FFU -#define UART_AT_CMD_CHAR_S 0 -/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; - * This register is used to configure the num of continuous at_cmd chars received by - * receiver. - */ -#define UART_CHAR_NUM 0x000000FFU -#define UART_CHAR_NUM_M (UART_CHAR_NUM_V << UART_CHAR_NUM_S) -#define UART_CHAR_NUM_V 0x000000FFU -#define UART_CHAR_NUM_S 8 - -/** UART_MEM_CONF_REG register - * UART memory power configuration - */ -#define UART_MEM_CONF_REG(i) (DR_REG_UART_BASE(i) + 0x60) -/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; - * Set this bit to force power down UART memory. - */ -#define UART_MEM_FORCE_PD (BIT(25)) -#define UART_MEM_FORCE_PD_M (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S) -#define UART_MEM_FORCE_PD_V 0x00000001U -#define UART_MEM_FORCE_PD_S 25 -/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0; - * Set this bit to force power up UART memory. - */ -#define UART_MEM_FORCE_PU (BIT(26)) -#define UART_MEM_FORCE_PU_M (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S) -#define UART_MEM_FORCE_PU_V 0x00000001U -#define UART_MEM_FORCE_PU_S 26 - -/** UART_TOUT_CONF_SYNC_REG register - * UART threshold and allocation configuration - */ -#define UART_TOUT_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x64) -/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; - * This is the enable bit for uart receiver's timeout function. - */ -#define UART_RX_TOUT_EN (BIT(0)) -#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) -#define UART_RX_TOUT_EN_V 0x00000001U -#define UART_RX_TOUT_EN_S 0 -/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0; - * Set this bit to stop accumulating idle_cnt when hardware flow control works. - */ -#define UART_RX_TOUT_FLOW_DIS (BIT(1)) -#define UART_RX_TOUT_FLOW_DIS_M (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S) -#define UART_RX_TOUT_FLOW_DIS_V 0x00000001U -#define UART_RX_TOUT_FLOW_DIS_S 1 -/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; - * This register is used to configure the threshold time that receiver takes to - * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver - * takes more time to receive one byte with rx_tout_en set to 1. - */ -#define UART_RX_TOUT_THRHD 0x000003FFU -#define UART_RX_TOUT_THRHD_M (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S) -#define UART_RX_TOUT_THRHD_V 0x000003FFU -#define UART_RX_TOUT_THRHD_S 2 - -/** UART_MEM_TX_STATUS_REG register - * Tx-SRAM write and read offset address. - */ -#define UART_MEM_TX_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x68) -/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0; - * This register stores the offset write address in Tx-SRAM. - */ -#define UART_TX_SRAM_WADDR 0x000000FFU -#define UART_TX_SRAM_WADDR_M (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S) -#define UART_TX_SRAM_WADDR_V 0x000000FFU -#define UART_TX_SRAM_WADDR_S 0 -/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0; - * This register stores the offset read address in Tx-SRAM. - */ -#define UART_TX_SRAM_RADDR 0x000000FFU -#define UART_TX_SRAM_RADDR_M (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S) -#define UART_TX_SRAM_RADDR_V 0x000000FFU -#define UART_TX_SRAM_RADDR_S 9 - -/** UART_MEM_RX_STATUS_REG register - * Rx-SRAM write and read offset address. - */ -#define UART_MEM_RX_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x6c) -/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128; - * This register stores the offset read address in RX-SRAM. - */ -#define UART_RX_SRAM_RADDR 0x000000FFU -#define UART_RX_SRAM_RADDR_M (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S) -#define UART_RX_SRAM_RADDR_V 0x000000FFU -#define UART_RX_SRAM_RADDR_S 0 -/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128; - * This register stores the offset write address in Rx-SRAM. - */ -#define UART_RX_SRAM_WADDR 0x000000FFU -#define UART_RX_SRAM_WADDR_M (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S) -#define UART_RX_SRAM_WADDR_V 0x000000FFU -#define UART_RX_SRAM_WADDR_S 9 - -/** UART_FSM_STATUS_REG register - * UART transmit and receive status. - */ -#define UART_FSM_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x70) -/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; - * This is the status register of receiver. - */ -#define UART_ST_URX_OUT 0x0000000FU -#define UART_ST_URX_OUT_M (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S) -#define UART_ST_URX_OUT_V 0x0000000FU -#define UART_ST_URX_OUT_S 0 -/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; - * This is the status register of transmitter. - */ -#define UART_ST_UTX_OUT 0x0000000FU -#define UART_ST_UTX_OUT_M (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S) -#define UART_ST_UTX_OUT_V 0x0000000FU -#define UART_ST_UTX_OUT_S 4 - -/** UART_POSPULSE_REG register - * Autobaud high pulse register - */ -#define UART_POSPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x74) -/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the minimal input clock count between two positive edges. It - * is used in boudrate-detect process. - */ -#define UART_POSEDGE_MIN_CNT 0x00000FFFU -#define UART_POSEDGE_MIN_CNT_M (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S) -#define UART_POSEDGE_MIN_CNT_V 0x00000FFFU -#define UART_POSEDGE_MIN_CNT_S 0 - -/** UART_NEGPULSE_REG register - * Autobaud low pulse register - */ -#define UART_NEGPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x78) -/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the minimal input clock count between two negative edges. It - * is used in boudrate-detect process. - */ -#define UART_NEGEDGE_MIN_CNT 0x00000FFFU -#define UART_NEGEDGE_MIN_CNT_M (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S) -#define UART_NEGEDGE_MIN_CNT_V 0x00000FFFU -#define UART_NEGEDGE_MIN_CNT_S 0 - -/** UART_LOWPULSE_REG register - * Autobaud minimum low pulse duration register - */ -#define UART_LOWPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x7c) -/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the minimum duration time of the low level pulse. - * It is used in baud rate-detect process. - */ -#define UART_LOWPULSE_MIN_CNT 0x00000FFFU -#define UART_LOWPULSE_MIN_CNT_M (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S) -#define UART_LOWPULSE_MIN_CNT_V 0x00000FFFU -#define UART_LOWPULSE_MIN_CNT_S 0 - -/** UART_HIGHPULSE_REG register - * Autobaud minimum high pulse duration register - */ -#define UART_HIGHPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x80) -/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maximum duration time for the high level - * pulse. It is used in baud rate-detect process. - */ -#define UART_HIGHPULSE_MIN_CNT 0x00000FFFU -#define UART_HIGHPULSE_MIN_CNT_M (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S) -#define UART_HIGHPULSE_MIN_CNT_V 0x00000FFFU -#define UART_HIGHPULSE_MIN_CNT_S 0 - -/** UART_RXD_CNT_REG register - * Autobaud edge change count register - */ -#define UART_RXD_CNT_REG(i) (DR_REG_UART_BASE(i) + 0x84) -/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; - * This register stores the count of rxd edge change. It is used in baud rate-detect - * process. - */ -#define UART_RXD_EDGE_CNT 0x000003FFU -#define UART_RXD_EDGE_CNT_M (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S) -#define UART_RXD_EDGE_CNT_V 0x000003FFU -#define UART_RXD_EDGE_CNT_S 0 - -/** UART_CLK_CONF_REG register - * UART core clock configuration - */ -#define UART_CLK_CONF_REG(i) (DR_REG_UART_BASE(i) + 0x88) -/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; - * Set this bit to enable UART Tx clock. - */ -#define UART_TX_SCLK_EN (BIT(24)) -#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S) -#define UART_TX_SCLK_EN_V 0x00000001U -#define UART_TX_SCLK_EN_S 24 -/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; - * Set this bit to enable UART Rx clock. - */ -#define UART_RX_SCLK_EN (BIT(25)) -#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S) -#define UART_RX_SCLK_EN_V 0x00000001U -#define UART_RX_SCLK_EN_S 25 -/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx. - */ -#define UART_TX_RST_CORE (BIT(26)) -#define UART_TX_RST_CORE_M (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S) -#define UART_TX_RST_CORE_V 0x00000001U -#define UART_TX_RST_CORE_S 26 -/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; - * Write 1 then write 0 to this bit to reset UART Rx. - */ -#define UART_RX_RST_CORE (BIT(27)) -#define UART_RX_RST_CORE_M (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S) -#define UART_RX_RST_CORE_V 0x00000001U -#define UART_RX_RST_CORE_S 27 - -/** UART_DATE_REG register - * UART Version register - */ -#define UART_DATE_REG(i) (DR_REG_UART_BASE(i) + 0x8c) -/** UART_DATE : R/W; bitpos: [31:0]; default: 36720720; - * This is the version register. - */ -#define UART_DATE 0xFFFFFFFFU -#define UART_DATE_M (UART_DATE_V << UART_DATE_S) -#define UART_DATE_V 0xFFFFFFFFU -#define UART_DATE_S 0 - -/** UART_AFIFO_STATUS_REG register - * UART AFIFO Status - */ -#define UART_AFIFO_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x90) -/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; - * Full signal of APB TX AFIFO. - */ -#define UART_TX_AFIFO_FULL (BIT(0)) -#define UART_TX_AFIFO_FULL_M (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S) -#define UART_TX_AFIFO_FULL_V 0x00000001U -#define UART_TX_AFIFO_FULL_S 0 -/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; - * Empty signal of APB TX AFIFO. - */ -#define UART_TX_AFIFO_EMPTY (BIT(1)) -#define UART_TX_AFIFO_EMPTY_M (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S) -#define UART_TX_AFIFO_EMPTY_V 0x00000001U -#define UART_TX_AFIFO_EMPTY_S 1 -/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; - * Full signal of APB RX AFIFO. - */ -#define UART_RX_AFIFO_FULL (BIT(2)) -#define UART_RX_AFIFO_FULL_M (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S) -#define UART_RX_AFIFO_FULL_V 0x00000001U -#define UART_RX_AFIFO_FULL_S 2 -/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; - * Empty signal of APB RX AFIFO. - */ -#define UART_RX_AFIFO_EMPTY (BIT(3)) -#define UART_RX_AFIFO_EMPTY_M (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S) -#define UART_RX_AFIFO_EMPTY_V 0x00000001U -#define UART_RX_AFIFO_EMPTY_S 3 - -/** UART_REG_UPDATE_REG register - * UART Registers Configuration Update register - */ -#define UART_REG_UPDATE_REG(i) (DR_REG_UART_BASE(i) + 0x98) -/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; - * Software write 1 would synchronize registers into UART Core clock domain and would - * be cleared by hardware after synchronization is done. - */ -#define UART_REG_UPDATE (BIT(0)) -#define UART_REG_UPDATE_M (UART_REG_UPDATE_V << UART_REG_UPDATE_S) -#define UART_REG_UPDATE_V 0x00000001U -#define UART_REG_UPDATE_S 0 - -/** UART_ID_REG register - * UART ID register - */ -#define UART_ID_REG(i) (DR_REG_UART_BASE(i) + 0x9c) -/** UART_ID : R/W; bitpos: [31:0]; default: 1280; - * This register is used to configure the uart_id. - */ -#define UART_ID 0xFFFFFFFFU -#define UART_ID_M (UART_ID_V << UART_ID_S) -#define UART_ID_V 0xFFFFFFFFU -#define UART_ID_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_struct.h deleted file mode 100644 index c49c9b58ba6b..000000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_struct.h +++ /dev/null @@ -1,1274 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: FIFO Configuration */ -/** Type of fifo register - * FIFO data register - */ -typedef union { - struct { - /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; - * UART $n accesses FIFO via this register. - */ - uint32_t rxfifo_rd_byte:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} uart_fifo_reg_t; - -/** Type of mem_conf register - * UART memory power configuration - */ -typedef union { - struct { - uint32_t reserved_0:25; - /** mem_force_pd : R/W; bitpos: [25]; default: 0; - * Set this bit to force power down UART memory. - */ - uint32_t mem_force_pd:1; - /** mem_force_pu : R/W; bitpos: [26]; default: 0; - * Set this bit to force power up UART memory. - */ - uint32_t mem_force_pu:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} uart_mem_conf_reg_t; - -/** Type of tout_conf_sync register - * UART threshold and allocation configuration - */ -typedef union { - struct { - /** rx_tout_en : R/W; bitpos: [0]; default: 0; - * This is the enable bit for uart receiver's timeout function. - */ - uint32_t rx_tout_en:1; - /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; - * Set this bit to stop accumulating idle_cnt when hardware flow control works. - */ - uint32_t rx_tout_flow_dis:1; - /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; - * This register is used to configure the threshold time that receiver takes to - * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver - * takes more time to receive one byte with rx_tout_en set to 1. - */ - uint32_t rx_tout_thrhd:10; - uint32_t reserved_12:20; - }; - uint32_t val; -} uart_tout_conf_sync_reg_t; - - -/** Group: Interrupt Register */ -/** Type of int_raw register - * Raw interrupt status - */ -typedef union { - struct { - /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * This interrupt raw bit turns to high level when receiver receives more data than - * what rxfifo_full_thrhd specifies. - */ - uint32_t rxfifo_full_int_raw:1; - /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1; - * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is - * less than what txfifo_empty_thrhd specifies . - */ - uint32_t txfifo_empty_int_raw:1; - /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a parity error in - * the data. - */ - uint32_t parity_err_int_raw:1; - /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a data frame error - * . - */ - uint32_t frm_err_int_raw:1; - /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * This interrupt raw bit turns to high level when receiver receives more data than - * the FIFO can store. - */ - uint32_t rxfifo_ovf_int_raw:1; - /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * This interrupt raw bit turns to high level when receiver detects the edge change of - * DSRn signal. - */ - uint32_t dsr_chg_int_raw:1; - /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * This interrupt raw bit turns to high level when receiver detects the edge change of - * CTSn signal. - */ - uint32_t cts_chg_int_raw:1; - /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a 0 after the stop - * bit. - */ - uint32_t brk_det_int_raw:1; - /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * This interrupt raw bit turns to high level when receiver takes more time than - * rx_tout_thrhd to receive a byte. - */ - uint32_t rxfifo_tout_int_raw:1; - /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver receives Xon char when - * uart_sw_flow_con_en is set to 1. - */ - uint32_t sw_xon_int_raw:1; - /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * This interrupt raw bit turns to high level when receiver receives Xoff char when - * uart_sw_flow_con_en is set to 1. - */ - uint32_t sw_xoff_int_raw:1; - /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a glitch in the - * middle of a start bit. - */ - uint32_t glitch_det_int_raw:1; - /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * This interrupt raw bit turns to high level when transmitter completes sending - * NULL characters after all data in Tx-FIFO are sent. - */ - uint32_t tx_brk_done_int_raw:1; - /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * This interrupt raw bit turns to high level when transmitter has kept the shortest - * duration after sending the last data. - */ - uint32_t tx_brk_idle_done_int_raw:1; - /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * This interrupt raw bit turns to high level when transmitter has send out all data - * in FIFO. - */ - uint32_t tx_done_int_raw:1; - /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a parity error - * from the echo of transmitter in rs485 mode. - */ - uint32_t rs485_parity_err_int_raw:1; - /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a data frame error - * from the echo of transmitter in rs485 mode. - */ - uint32_t rs485_frm_err_int_raw:1; - /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0; - * This interrupt raw bit turns to high level when detects a clash between transmitter - * and receiver in rs485 mode. - */ - uint32_t rs485_clash_int_raw:1; - /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0; - * This interrupt raw bit turns to high level when receiver detects the configured - * at_cmd char. - */ - uint32_t at_cmd_char_det_int_raw:1; - /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0; - * This interrupt raw bit turns to high level when input rxd edge changes more times - * than what reg_active_threshold specifies in light sleeping mode. - */ - uint32_t wakeup_int_raw:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} uart_int_raw_reg_t; - -/** Type of int_st register - * Masked interrupt status - */ -typedef union { - struct { - /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0; - * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. - */ - uint32_t rxfifo_full_int_st:1; - /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0; - * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set - * to 1. - */ - uint32_t txfifo_empty_int_st:1; - /** parity_err_int_st : RO; bitpos: [2]; default: 0; - * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. - */ - uint32_t parity_err_int_st:1; - /** frm_err_int_st : RO; bitpos: [3]; default: 0; - * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. - */ - uint32_t frm_err_int_st:1; - /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0; - * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. - */ - uint32_t rxfifo_ovf_int_st:1; - /** dsr_chg_int_st : RO; bitpos: [5]; default: 0; - * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. - */ - uint32_t dsr_chg_int_st:1; - /** cts_chg_int_st : RO; bitpos: [6]; default: 0; - * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. - */ - uint32_t cts_chg_int_st:1; - /** brk_det_int_st : RO; bitpos: [7]; default: 0; - * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. - */ - uint32_t brk_det_int_st:1; - /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0; - * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. - */ - uint32_t rxfifo_tout_int_st:1; - /** sw_xon_int_st : RO; bitpos: [9]; default: 0; - * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. - */ - uint32_t sw_xon_int_st:1; - /** sw_xoff_int_st : RO; bitpos: [10]; default: 0; - * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. - */ - uint32_t sw_xoff_int_st:1; - /** glitch_det_int_st : RO; bitpos: [11]; default: 0; - * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. - */ - uint32_t glitch_det_int_st:1; - /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0; - * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. - */ - uint32_t tx_brk_done_int_st:1; - /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; - * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena - * is set to 1. - */ - uint32_t tx_brk_idle_done_int_st:1; - /** tx_done_int_st : RO; bitpos: [14]; default: 0; - * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. - */ - uint32_t tx_done_int_st:1; - /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0; - * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is - * set to 1. - */ - uint32_t rs485_parity_err_int_st:1; - /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0; - * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set - * to 1. - */ - uint32_t rs485_frm_err_int_st:1; - /** rs485_clash_int_st : RO; bitpos: [17]; default: 0; - * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. - */ - uint32_t rs485_clash_int_st:1; - /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0; - * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set - * to 1. - */ - uint32_t at_cmd_char_det_int_st:1; - /** wakeup_int_st : RO; bitpos: [19]; default: 0; - * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. - */ - uint32_t wakeup_int_st:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} uart_int_st_reg_t; - -/** Type of int_ena register - * Interrupt enable bits - */ -typedef union { - struct { - /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0; - * This is the enable bit for rxfifo_full_int_st register. - */ - uint32_t rxfifo_full_int_ena:1; - /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0; - * This is the enable bit for txfifo_empty_int_st register. - */ - uint32_t txfifo_empty_int_ena:1; - /** parity_err_int_ena : R/W; bitpos: [2]; default: 0; - * This is the enable bit for parity_err_int_st register. - */ - uint32_t parity_err_int_ena:1; - /** frm_err_int_ena : R/W; bitpos: [3]; default: 0; - * This is the enable bit for frm_err_int_st register. - */ - uint32_t frm_err_int_ena:1; - /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; - * This is the enable bit for rxfifo_ovf_int_st register. - */ - uint32_t rxfifo_ovf_int_ena:1; - /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0; - * This is the enable bit for dsr_chg_int_st register. - */ - uint32_t dsr_chg_int_ena:1; - /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0; - * This is the enable bit for cts_chg_int_st register. - */ - uint32_t cts_chg_int_ena:1; - /** brk_det_int_ena : R/W; bitpos: [7]; default: 0; - * This is the enable bit for brk_det_int_st register. - */ - uint32_t brk_det_int_ena:1; - /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0; - * This is the enable bit for rxfifo_tout_int_st register. - */ - uint32_t rxfifo_tout_int_ena:1; - /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0; - * This is the enable bit for sw_xon_int_st register. - */ - uint32_t sw_xon_int_ena:1; - /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0; - * This is the enable bit for sw_xoff_int_st register. - */ - uint32_t sw_xoff_int_ena:1; - /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0; - * This is the enable bit for glitch_det_int_st register. - */ - uint32_t glitch_det_int_ena:1; - /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0; - * This is the enable bit for tx_brk_done_int_st register. - */ - uint32_t tx_brk_done_int_ena:1; - /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0; - * This is the enable bit for tx_brk_idle_done_int_st register. - */ - uint32_t tx_brk_idle_done_int_ena:1; - /** tx_done_int_ena : R/W; bitpos: [14]; default: 0; - * This is the enable bit for tx_done_int_st register. - */ - uint32_t tx_done_int_ena:1; - /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0; - * This is the enable bit for rs485_parity_err_int_st register. - */ - uint32_t rs485_parity_err_int_ena:1; - /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0; - * This is the enable bit for rs485_parity_err_int_st register. - */ - uint32_t rs485_frm_err_int_ena:1; - /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0; - * This is the enable bit for rs485_clash_int_st register. - */ - uint32_t rs485_clash_int_ena:1; - /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0; - * This is the enable bit for at_cmd_char_det_int_st register. - */ - uint32_t at_cmd_char_det_int_ena:1; - /** wakeup_int_ena : R/W; bitpos: [19]; default: 0; - * This is the enable bit for uart_wakeup_int_st register. - */ - uint32_t wakeup_int_ena:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} uart_int_ena_reg_t; - -/** Type of int_clr register - * Interrupt clear bits - */ -typedef union { - struct { - /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the rxfifo_full_int_raw interrupt. - */ - uint32_t rxfifo_full_int_clr:1; - /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear txfifo_empty_int_raw interrupt. - */ - uint32_t txfifo_empty_int_clr:1; - /** parity_err_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear parity_err_int_raw interrupt. - */ - uint32_t parity_err_int_clr:1; - /** frm_err_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear frm_err_int_raw interrupt. - */ - uint32_t frm_err_int_clr:1; - /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear rxfifo_ovf_int_raw interrupt. - */ - uint32_t rxfifo_ovf_int_clr:1; - /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the dsr_chg_int_raw interrupt. - */ - uint32_t dsr_chg_int_clr:1; - /** cts_chg_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the cts_chg_int_raw interrupt. - */ - uint32_t cts_chg_int_clr:1; - /** brk_det_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the brk_det_int_raw interrupt. - */ - uint32_t brk_det_int_clr:1; - /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the rxfifo_tout_int_raw interrupt. - */ - uint32_t rxfifo_tout_int_clr:1; - /** sw_xon_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the sw_xon_int_raw interrupt. - */ - uint32_t sw_xon_int_clr:1; - /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0; - * Set this bit to clear the sw_xoff_int_raw interrupt. - */ - uint32_t sw_xoff_int_clr:1; - /** glitch_det_int_clr : WT; bitpos: [11]; default: 0; - * Set this bit to clear the glitch_det_int_raw interrupt. - */ - uint32_t glitch_det_int_clr:1; - /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0; - * Set this bit to clear the tx_brk_done_int_raw interrupt.. - */ - uint32_t tx_brk_done_int_clr:1; - /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0; - * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. - */ - uint32_t tx_brk_idle_done_int_clr:1; - /** tx_done_int_clr : WT; bitpos: [14]; default: 0; - * Set this bit to clear the tx_done_int_raw interrupt. - */ - uint32_t tx_done_int_clr:1; - /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0; - * Set this bit to clear the rs485_parity_err_int_raw interrupt. - */ - uint32_t rs485_parity_err_int_clr:1; - /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0; - * Set this bit to clear the rs485_frm_err_int_raw interrupt. - */ - uint32_t rs485_frm_err_int_clr:1; - /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0; - * Set this bit to clear the rs485_clash_int_raw interrupt. - */ - uint32_t rs485_clash_int_clr:1; - /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0; - * Set this bit to clear the at_cmd_char_det_int_raw interrupt. - */ - uint32_t at_cmd_char_det_int_clr:1; - /** wakeup_int_clr : WT; bitpos: [19]; default: 0; - * Set this bit to clear the uart_wakeup_int_raw interrupt. - */ - uint32_t wakeup_int_clr:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} uart_int_clr_reg_t; - - -/** Group: Configuration Register */ -/** Type of clkdiv_sync register - * Clock divider configuration - */ -typedef union { - struct { - /** clkdiv : R/W; bitpos: [11:0]; default: 694; - * The integral part of the frequency divider factor. - */ - uint32_t clkdiv:12; - uint32_t reserved_12:8; - /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; - * The decimal part of the frequency divider factor. - */ - uint32_t clkdiv_frag:4; - uint32_t reserved_24:8; - }; - uint32_t val; -} uart_clkdiv_sync_reg_t; - -/** Type of rx_filt register - * Rx Filter configuration - */ -typedef union { - struct { - /** glitch_filt : R/W; bitpos: [7:0]; default: 8; - * when input pulse width is lower than this value the pulse is ignored. - */ - uint32_t glitch_filt:8; - /** glitch_filt_en : R/W; bitpos: [8]; default: 0; - * Set this bit to enable Rx signal filter. - */ - uint32_t glitch_filt_en:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} uart_rx_filt_reg_t; - -/** Type of conf0_sync register - * a - */ -typedef union { - struct { - /** parity : R/W; bitpos: [0]; default: 0; - * This register is used to configure the parity check mode. - */ - uint32_t parity:1; - /** parity_en : R/W; bitpos: [1]; default: 0; - * Set this bit to enable uart parity check. - */ - uint32_t parity_en:1; - /** bit_num : R/W; bitpos: [3:2]; default: 3; - * This register is used to set the length of data. - */ - uint32_t bit_num:2; - /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; - * This register is used to set the length of stop bit. - */ - uint32_t stop_bit_num:2; - /** txd_brk : R/W; bitpos: [6]; default: 0; - * Set this bit to enable transmitter to send NULL when the process of sending data - * is done. - */ - uint32_t txd_brk:1; - /** irda_dplx : R/W; bitpos: [7]; default: 0; - * Set this bit to enable IrDA loopback mode. - */ - uint32_t irda_dplx:1; - /** irda_tx_en : R/W; bitpos: [8]; default: 0; - * This is the start enable bit for IrDA transmitter. - */ - uint32_t irda_tx_en:1; - /** irda_wctl : R/W; bitpos: [9]; default: 0; - * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA - * transmitter's 11th bit to 0. - */ - uint32_t irda_wctl:1; - /** irda_tx_inv : R/W; bitpos: [10]; default: 0; - * Set this bit to invert the level of IrDA transmitter. - */ - uint32_t irda_tx_inv:1; - /** irda_rx_inv : R/W; bitpos: [11]; default: 0; - * Set this bit to invert the level of IrDA receiver. - */ - uint32_t irda_rx_inv:1; - /** loopback : R/W; bitpos: [12]; default: 0; - * Set this bit to enable uart loopback test mode. - */ - uint32_t loopback:1; - /** tx_flow_en : R/W; bitpos: [13]; default: 0; - * Set this bit to enable flow control function for transmitter. - */ - uint32_t tx_flow_en:1; - /** irda_en : R/W; bitpos: [14]; default: 0; - * Set this bit to enable IrDA protocol. - */ - uint32_t irda_en:1; - /** rxd_inv : R/W; bitpos: [15]; default: 0; - * Set this bit to inverse the level value of uart rxd signal. - */ - uint32_t rxd_inv:1; - /** txd_inv : R/W; bitpos: [16]; default: 0; - * Set this bit to inverse the level value of uart txd signal. - */ - uint32_t txd_inv:1; - /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; - * Disable UART Rx data overflow detect. - */ - uint32_t dis_rx_dat_ovf:1; - /** err_wr_mask : R/W; bitpos: [18]; default: 0; - * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver - * stores the data even if the received data is wrong. - */ - uint32_t err_wr_mask:1; - /** autobaud_en : R/W; bitpos: [19]; default: 0; - * This is the enable bit for detecting baudrate. - */ - uint32_t autobaud_en:1; - /** mem_clk_en : R/W; bitpos: [20]; default: 0; - * UART memory clock gate enable signal. - */ - uint32_t mem_clk_en:1; - /** sw_rts : R/W; bitpos: [21]; default: 0; - * This register is used to configure the software rts signal which is used in - * software flow control. - */ - uint32_t sw_rts:1; - /** rxfifo_rst : R/W; bitpos: [22]; default: 0; - * Set this bit to reset the uart receive-FIFO. - */ - uint32_t rxfifo_rst:1; - /** txfifo_rst : R/W; bitpos: [23]; default: 0; - * Set this bit to reset the uart transmit-FIFO. - */ - uint32_t txfifo_rst:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} uart_conf0_sync_reg_t; - -/** Type of conf1 register - * Configuration register 1 - */ -typedef union { - struct { - /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96; - * It will produce rxfifo_full_int interrupt when receiver receives more data than - * this register value. - */ - uint32_t rxfifo_full_thrhd:8; - /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96; - * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less - * than this register value. - */ - uint32_t txfifo_empty_thrhd:8; - /** cts_inv : R/W; bitpos: [16]; default: 0; - * Set this bit to inverse the level value of uart cts signal. - */ - uint32_t cts_inv:1; - /** dsr_inv : R/W; bitpos: [17]; default: 0; - * Set this bit to inverse the level value of uart dsr signal. - */ - uint32_t dsr_inv:1; - /** rts_inv : R/W; bitpos: [18]; default: 0; - * Set this bit to inverse the level value of uart rts signal. - */ - uint32_t rts_inv:1; - /** dtr_inv : R/W; bitpos: [19]; default: 0; - * Set this bit to inverse the level value of uart dtr signal. - */ - uint32_t dtr_inv:1; - /** sw_dtr : R/W; bitpos: [20]; default: 0; - * This register is used to configure the software dtr signal which is used in - * software flow control. - */ - uint32_t sw_dtr:1; - /** clk_en : R/W; bitpos: [21]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes - * registers. - */ - uint32_t clk_en:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} uart_conf1_reg_t; - -/** Type of hwfc_conf_sync register - * Hardware flow-control configuration - */ -typedef union { - struct { - /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0; - * This register is used to configure the maximum amount of data that can be received - * when hardware flow control works. - */ - uint32_t rx_flow_thrhd:8; - /** rx_flow_en : R/W; bitpos: [8]; default: 0; - * This is the flow enable bit for UART receiver. - */ - uint32_t rx_flow_en:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} uart_hwfc_conf_sync_reg_t; - -/** Type of sleep_conf0 register - * UART sleep configure register 0 - */ -typedef union { - struct { - /** wk_char1 : R/W; bitpos: [7:0]; default: 0; - * This register restores the specified wake up char1 to wake up - */ - uint32_t wk_char1:8; - /** wk_char2 : R/W; bitpos: [15:8]; default: 0; - * This register restores the specified wake up char2 to wake up - */ - uint32_t wk_char2:8; - /** wk_char3 : R/W; bitpos: [23:16]; default: 0; - * This register restores the specified wake up char3 to wake up - */ - uint32_t wk_char3:8; - /** wk_char4 : R/W; bitpos: [31:24]; default: 0; - * This register restores the specified wake up char4 to wake up - */ - uint32_t wk_char4:8; - }; - uint32_t val; -} uart_sleep_conf0_reg_t; - -/** Type of sleep_conf1 register - * UART sleep configure register 1 - */ -typedef union { - struct { - /** wk_char0 : R/W; bitpos: [7:0]; default: 0; - * This register restores the specified char0 to wake up - */ - uint32_t wk_char0:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} uart_sleep_conf1_reg_t; - -/** Type of sleep_conf2 register - * UART sleep configure register 2 - */ -typedef union { - struct { - /** active_threshold : R/W; bitpos: [9:0]; default: 240; - * The uart is activated from light sleeping mode when the input rxd edge changes more - * times than this register value. - */ - uint32_t active_threshold:10; - /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1; - * In wake up mode 1 this field is used to set the received data number threshold to - * wake up chip. - */ - uint32_t rx_wake_up_thrhd:8; - /** wk_char_num : R/W; bitpos: [20:18]; default: 5; - * This register is used to select number of wake up char. - */ - uint32_t wk_char_num:3; - /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; - * This register is used to mask wake up char. - */ - uint32_t wk_char_mask:5; - /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; - * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: - * received data number larger than - */ - uint32_t wk_mode_sel:2; - uint32_t reserved_28:4; - }; - uint32_t val; -} uart_sleep_conf2_reg_t; - -/** Type of swfc_conf0_sync register - * Software flow-control character configuration - */ -typedef union { - struct { - /** xon_char : R/W; bitpos: [7:0]; default: 17; - * This register stores the Xon flow control char. - */ - uint32_t xon_char:8; - /** xoff_char : R/W; bitpos: [15:8]; default: 19; - * This register stores the Xoff flow control char. - */ - uint32_t xoff_char:8; - /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; - * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In - * this status, UART Tx can not transmit XOFF even the received data number is larger - * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when - * UART Tx is disabled. - */ - uint32_t xon_xoff_still_send:1; - /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; - * Set this bit to enable software flow control. It is used with register sw_xon or - * sw_xoff. - */ - uint32_t sw_flow_con_en:1; - /** xonoff_del : R/W; bitpos: [18]; default: 0; - * Set this bit to remove flow control char from the received data. - */ - uint32_t xonoff_del:1; - /** force_xon : R/W; bitpos: [19]; default: 0; - * Set this bit to enable the transmitter to go on sending data. - */ - uint32_t force_xon:1; - /** force_xoff : R/W; bitpos: [20]; default: 0; - * Set this bit to stop the transmitter from sending data. - */ - uint32_t force_xoff:1; - /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; - * Set this bit to send Xon char. It is cleared by hardware automatically. - */ - uint32_t send_xon:1; - /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; - * Set this bit to send Xoff char. It is cleared by hardware automatically. - */ - uint32_t send_xoff:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} uart_swfc_conf0_sync_reg_t; - -/** Type of swfc_conf1 register - * Software flow-control character configuration - */ -typedef union { - struct { - /** xon_threshold : R/W; bitpos: [7:0]; default: 0; - * When the data amount in Rx-FIFO is less than this register value with - * uart_sw_flow_con_en set to 1 it will send a Xon char. - */ - uint32_t xon_threshold:8; - /** xoff_threshold : R/W; bitpos: [15:8]; default: 224; - * When the data amount in Rx-FIFO is more than this register value with - * uart_sw_flow_con_en set to 1 it will send a Xoff char. - */ - uint32_t xoff_threshold:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} uart_swfc_conf1_reg_t; - -/** Type of txbrk_conf_sync register - * Tx Break character configuration - */ -typedef union { - struct { - /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; - * This register is used to configure the number of 0 to be sent after the process of - * sending data is done. It is active when txd_brk is set to 1. - */ - uint32_t tx_brk_num:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} uart_txbrk_conf_sync_reg_t; - -/** Type of idle_conf_sync register - * Frame-end idle configuration - */ -typedef union { - struct { - /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; - * It will produce frame end signal when receiver takes more time to receive one byte - * data than this register value. - */ - uint32_t rx_idle_thrhd:10; - /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; - * This register is used to configure the duration time between transfers. - */ - uint32_t tx_idle_num:10; - uint32_t reserved_20:12; - }; - uint32_t val; -} uart_idle_conf_sync_reg_t; - -/** Type of rs485_conf_sync register - * RS485 mode configuration - */ -typedef union { - struct { - /** rs485_en : R/W; bitpos: [0]; default: 0; - * Set this bit to choose the rs485 mode. - */ - uint32_t rs485_en:1; - /** dl0_en : R/W; bitpos: [1]; default: 0; - * Set this bit to delay the stop bit by 1 bit. - */ - uint32_t dl0_en:1; - /** dl1_en : R/W; bitpos: [2]; default: 0; - * Set this bit to delay the stop bit by 1 bit. - */ - uint32_t dl1_en:1; - /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0; - * Set this bit to enable receiver could receive data when the transmitter is - * transmitting data in rs485 mode. - */ - uint32_t rs485tx_rx_en:1; - /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0; - * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. - */ - uint32_t rs485rxby_tx_en:1; - /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0; - * This register is used to delay the receiver's internal data signal. - */ - uint32_t rs485_rx_dly_num:1; - /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0; - * This register is used to delay the transmitter's internal data signal. - */ - uint32_t rs485_tx_dly_num:4; - uint32_t reserved_10:22; - }; - uint32_t val; -} uart_rs485_conf_sync_reg_t; - -/** Type of clk_conf register - * UART core clock configuration - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** tx_sclk_en : R/W; bitpos: [24]; default: 1; - * Set this bit to enable UART Tx clock. - */ - uint32_t tx_sclk_en:1; - /** rx_sclk_en : R/W; bitpos: [25]; default: 1; - * Set this bit to enable UART Rx clock. - */ - uint32_t rx_sclk_en:1; - /** tx_rst_core : R/W; bitpos: [26]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx. - */ - uint32_t tx_rst_core:1; - /** rx_rst_core : R/W; bitpos: [27]; default: 0; - * Write 1 then write 0 to this bit to reset UART Rx. - */ - uint32_t rx_rst_core:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} uart_clk_conf_reg_t; - - -/** Group: Status Register */ -/** Type of status register - * UART status register - */ -typedef union { - struct { - /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0; - * Stores the byte number of valid data in Rx-FIFO. - */ - uint32_t rxfifo_cnt:8; - uint32_t reserved_8:5; - /** dsrn : RO; bitpos: [13]; default: 0; - * The register represent the level value of the internal uart dsr signal. - */ - uint32_t dsrn:1; - /** ctsn : RO; bitpos: [14]; default: 1; - * This register represent the level value of the internal uart cts signal. - */ - uint32_t ctsn:1; - /** rxd : RO; bitpos: [15]; default: 1; - * This register represent the level value of the internal uart rxd signal. - */ - uint32_t rxd:1; - /** txfifo_cnt : RO; bitpos: [23:16]; default: 0; - * Stores the byte number of data in Tx-FIFO. - */ - uint32_t txfifo_cnt:8; - uint32_t reserved_24:5; - /** dtrn : RO; bitpos: [29]; default: 1; - * This bit represents the level of the internal uart dtr signal. - */ - uint32_t dtrn:1; - /** rtsn : RO; bitpos: [30]; default: 1; - * This bit represents the level of the internal uart rts signal. - */ - uint32_t rtsn:1; - /** txd : RO; bitpos: [31]; default: 1; - * This bit represents the level of the internal uart txd signal. - */ - uint32_t txd:1; - }; - uint32_t val; -} uart_status_reg_t; - -/** Type of mem_tx_status register - * Tx-SRAM write and read offset address. - */ -typedef union { - struct { - /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0; - * This register stores the offset write address in Tx-SRAM. - */ - uint32_t tx_sram_waddr:8; - uint32_t reserved_8:1; - /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0; - * This register stores the offset read address in Tx-SRAM. - */ - uint32_t tx_sram_raddr:8; - uint32_t reserved_17:15; - }; - uint32_t val; -} uart_mem_tx_status_reg_t; - -/** Type of mem_rx_status register - * Rx-SRAM write and read offset address. - */ -typedef union { - struct { - /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128; - * This register stores the offset read address in RX-SRAM. - */ - uint32_t rx_sram_raddr:8; - uint32_t reserved_8:1; - /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128; - * This register stores the offset write address in Rx-SRAM. - */ - uint32_t rx_sram_waddr:8; - uint32_t reserved_17:15; - }; - uint32_t val; -} uart_mem_rx_status_reg_t; - -/** Type of fsm_status register - * UART transmit and receive status. - */ -typedef union { - struct { - /** st_urx_out : RO; bitpos: [3:0]; default: 0; - * This is the status register of receiver. - */ - uint32_t st_urx_out:4; - /** st_utx_out : RO; bitpos: [7:4]; default: 0; - * This is the status register of transmitter. - */ - uint32_t st_utx_out:4; - uint32_t reserved_8:24; - }; - uint32_t val; -} uart_fsm_status_reg_t; - -/** Type of afifo_status register - * UART AFIFO Status - */ -typedef union { - struct { - /** tx_afifo_full : RO; bitpos: [0]; default: 0; - * Full signal of APB TX AFIFO. - */ - uint32_t tx_afifo_full:1; - /** tx_afifo_empty : RO; bitpos: [1]; default: 1; - * Empty signal of APB TX AFIFO. - */ - uint32_t tx_afifo_empty:1; - /** rx_afifo_full : RO; bitpos: [2]; default: 0; - * Full signal of APB RX AFIFO. - */ - uint32_t rx_afifo_full:1; - /** rx_afifo_empty : RO; bitpos: [3]; default: 1; - * Empty signal of APB RX AFIFO. - */ - uint32_t rx_afifo_empty:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} uart_afifo_status_reg_t; - - -/** Group: AT Escape Sequence Selection Configuration */ -/** Type of at_cmd_precnt_sync register - * Pre-sequence timing configuration - */ -typedef union { - struct { - /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; - * This register is used to configure the idle duration time before the first at_cmd - * is received by receiver. - */ - uint32_t pre_idle_num:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} uart_at_cmd_precnt_sync_reg_t; - -/** Type of at_cmd_postcnt_sync register - * Post-sequence timing configuration - */ -typedef union { - struct { - /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; - * This register is used to configure the duration time between the last at_cmd and - * the next data. - */ - uint32_t post_idle_num:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} uart_at_cmd_postcnt_sync_reg_t; - -/** Type of at_cmd_gaptout_sync register - * Timeout configuration - */ -typedef union { - struct { - /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; - * This register is used to configure the duration time between the at_cmd chars. - */ - uint32_t rx_gap_tout:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} uart_at_cmd_gaptout_sync_reg_t; - -/** Type of at_cmd_char_sync register - * AT escape sequence detection configuration - */ -typedef union { - struct { - /** at_cmd_char : R/W; bitpos: [7:0]; default: 43; - * This register is used to configure the content of at_cmd char. - */ - uint32_t at_cmd_char:8; - /** char_num : R/W; bitpos: [15:8]; default: 3; - * This register is used to configure the num of continuous at_cmd chars received by - * receiver. - */ - uint32_t char_num:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} uart_at_cmd_char_sync_reg_t; - - -/** Group: Autobaud Register */ -/** Type of pospulse register - * Autobaud high pulse register - */ -typedef union { - struct { - /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095; - * This register stores the minimal input clock count between two positive edges. It - * is used in boudrate-detect process. - */ - uint32_t posedge_min_cnt:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} uart_pospulse_reg_t; - -/** Type of negpulse register - * Autobaud low pulse register - */ -typedef union { - struct { - /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095; - * This register stores the minimal input clock count between two negative edges. It - * is used in boudrate-detect process. - */ - uint32_t negedge_min_cnt:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} uart_negpulse_reg_t; - -/** Type of lowpulse register - * Autobaud minimum low pulse duration register - */ -typedef union { - struct { - /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the minimum duration time of the low level pulse. - * It is used in baud rate-detect process. - */ - uint32_t lowpulse_min_cnt:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} uart_lowpulse_reg_t; - -/** Type of highpulse register - * Autobaud minimum high pulse duration register - */ -typedef union { - struct { - /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maximum duration time for the high level - * pulse. It is used in baud rate-detect process. - */ - uint32_t highpulse_min_cnt:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} uart_highpulse_reg_t; - -/** Type of rxd_cnt register - * Autobaud edge change count register - */ -typedef union { - struct { - /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0; - * This register stores the count of rxd edge change. It is used in baud rate-detect - * process. - */ - uint32_t rxd_edge_cnt:10; - uint32_t reserved_10:22; - }; - uint32_t val; -} uart_rxd_cnt_reg_t; - - -/** Group: Version Register */ -/** Type of date register - * UART Version register - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 36720720; - * This is the version register. - */ - uint32_t date:32; - }; - uint32_t val; -} uart_date_reg_t; - -/** Type of reg_update register - * UART Registers Configuration Update register - */ -typedef union { - struct { - /** reg_update : R/W/SC; bitpos: [0]; default: 0; - * Software write 1 would synchronize registers into UART Core clock domain and would - * be cleared by hardware after synchronization is done. - */ - uint32_t reg_update:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} uart_reg_update_reg_t; - -/** Type of id register - * UART ID register - */ -typedef union { - struct { - /** id : R/W; bitpos: [31:0]; default: 1280; - * This register is used to configure the uart_id. - */ - uint32_t id:32; - }; - uint32_t val; -} uart_id_reg_t; - - -typedef struct { - volatile uart_fifo_reg_t fifo; - volatile uart_int_raw_reg_t int_raw; - volatile uart_int_st_reg_t int_st; - volatile uart_int_ena_reg_t int_ena; - volatile uart_int_clr_reg_t int_clr; - volatile uart_clkdiv_sync_reg_t clkdiv_sync; - volatile uart_rx_filt_reg_t rx_filt; - volatile uart_status_reg_t status; - volatile uart_conf0_sync_reg_t conf0_sync; - volatile uart_conf1_reg_t conf1; - uint32_t reserved_028; - volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync; - volatile uart_sleep_conf0_reg_t sleep_conf0; - volatile uart_sleep_conf1_reg_t sleep_conf1; - volatile uart_sleep_conf2_reg_t sleep_conf2; - volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync; - volatile uart_swfc_conf1_reg_t swfc_conf1; - volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync; - volatile uart_idle_conf_sync_reg_t idle_conf_sync; - volatile uart_rs485_conf_sync_reg_t rs485_conf_sync; - volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync; - volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync; - volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync; - volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync; - volatile uart_mem_conf_reg_t mem_conf; - volatile uart_tout_conf_sync_reg_t tout_conf_sync; - volatile uart_mem_tx_status_reg_t mem_tx_status; - volatile uart_mem_rx_status_reg_t mem_rx_status; - volatile uart_fsm_status_reg_t fsm_status; - volatile uart_pospulse_reg_t pospulse; - volatile uart_negpulse_reg_t negpulse; - volatile uart_lowpulse_reg_t lowpulse; - volatile uart_highpulse_reg_t highpulse; - volatile uart_rxd_cnt_reg_t rxd_cnt; - volatile uart_clk_conf_reg_t clk_conf; - volatile uart_date_reg_t date; - volatile uart_afifo_status_reg_t afifo_status; - uint32_t reserved_094; - volatile uart_reg_update_reg_t reg_update; - volatile uart_id_reg_t id; -} uart_dev_t; - -extern uart_dev_t UART0; -extern uart_dev_t UART1; -extern uart_dev_t UART2; -extern uart_dev_t UART3; -extern uart_dev_t UART4; - -#ifndef __cplusplus -_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/uart_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/uart_reg.h index 66c4081a9677..ba938dfb8b65 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/uart_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/uart_reg.h @@ -11,8 +11,6 @@ extern "C" { #endif -// TODO: IDF-13425 - /** UART_FIFO_REG register * FIFO data register */ diff --git a/components/soc/esp32p4/register/hw_ver3/soc/uart_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/uart_struct.h index 5b98af7cebc9..3fc2f5ed87b2 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/uart_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/uart_struct.h @@ -10,8 +10,6 @@ extern "C" { #endif -// TODO: IDF-13425 - /** Group: FIFO Configuration */ /** Type of fifo register * FIFO data register @@ -21,7 +19,8 @@ typedef union { /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; * UART $n accesses FIFO via this register. */ - uint32_t rxfifo_rd_byte:32; + uint32_t rxfifo_rd_byte:8; + uint32_t reserved_8:24; }; uint32_t val; } uart_fifo_reg_t; diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index b23b5fc831d6..a6cdc87befc8 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -407,10 +407,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM int default 8 diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index f8b90d978de7..09a5e2d6682b 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -182,9 +182,6 @@ #define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) -// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) - /*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index 73fb80a89ae5..1b9e5ab80d34 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -507,10 +507,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM int default 8 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index 7b93b97f6e41..5e61125992b5 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -197,9 +197,6 @@ #define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) -// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) - /*-------------------------- Dedicated GPIO CAPS -----------------------------*/ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ diff --git a/components/ulp/test_apps/ulp_fsm/main/test_ulp.c b/components/ulp/test_apps/ulp_fsm/main/test_ulp.c index ee4ae12f88bd..faa44964f6d0 100644 --- a/components/ulp/test_apps/ulp_fsm/main/test_ulp.c +++ b/components/ulp/test_apps/ulp_fsm/main/test_ulp.c @@ -362,7 +362,7 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]") TEST_ESP_OK(ulp_run(0)); /* Wait for the ULP co-processor to finish up */ - vTaskDelay(10 / portTICK_PERIOD_MS); + vTaskDelay(50 / portTICK_PERIOD_MS); /* Verify the test results */ uint32_t clear = REG_READ(RTC_CNTL_STORE0_REG); diff --git a/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-bignum.c b/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-bignum.c index 8ef5e37c57dc..6328136a9117 100644 --- a/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-bignum.c +++ b/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-bignum.c @@ -7,6 +7,7 @@ #ifdef ESP_PLATFORM #include "esp_system.h" #include "mbedtls/bignum.h" +#include "mbedtls/esp_mbedtls_random.h" #endif #include "utils/includes.h" @@ -16,11 +17,6 @@ #include "sha256.h" #include "mbedtls/pk.h" -static int crypto_rng_wrapper(void *ctx, unsigned char *buf, size_t len) -{ - return random_get_bytes(buf, len); -} - struct crypto_bignum *crypto_bignum_init(void) { mbedtls_mpi *bn = os_zalloc(sizeof(mbedtls_mpi)); @@ -220,7 +216,7 @@ int crypto_bignum_is_odd(const struct crypto_bignum *a) int crypto_bignum_rand(struct crypto_bignum *r, const struct crypto_bignum *m) { return ((mbedtls_mpi_random((mbedtls_mpi *) r, 0, (const mbedtls_mpi *) m, - crypto_rng_wrapper, NULL) != 0) ? -1 : 0); + mbedtls_esp_random, NULL) != 0) ? -1 : 0); } int crypto_bignum_legendre(const struct crypto_bignum *a, diff --git a/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-ec.c b/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-ec.c index cde8323fdd00..24c31b06b5ff 100644 --- a/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-ec.c +++ b/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-ec.c @@ -7,6 +7,7 @@ #ifdef ESP_PLATFORM #include "esp_system.h" #include "mbedtls/bignum.h" +#include "mbedtls/esp_mbedtls_random.h" #endif #include "utils/includes.h" @@ -16,8 +17,6 @@ #include "random.h" #include "mbedtls/ecp.h" -#include "mbedtls/entropy.h" -#include "mbedtls/ctr_drbg.h" #include "mbedtls/pk.h" #include "mbedtls/ecdh.h" @@ -36,10 +35,6 @@ #endif #ifdef CONFIG_ECC -static int crypto_rng_wrapper(void *ctx, unsigned char *buf, size_t len) -{ - return random_get_bytes(buf, len); -} struct crypto_ec *crypto_ec_init(int group) { @@ -258,24 +253,14 @@ int crypto_ec_point_mul(struct crypto_ec *e, const struct crypto_ec_point *p, struct crypto_ec_point *res) { int ret; - mbedtls_entropy_context entropy; - mbedtls_ctr_drbg_context ctr_drbg; - - mbedtls_entropy_init(&entropy); - mbedtls_ctr_drbg_init(&ctr_drbg); - - MBEDTLS_MPI_CHK(mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy, - NULL, 0)); - MBEDTLS_MPI_CHK(mbedtls_ecp_mul((mbedtls_ecp_group *)e, (mbedtls_ecp_point *) res, (const mbedtls_mpi *)b, (const mbedtls_ecp_point *)p, - mbedtls_ctr_drbg_random, - &ctr_drbg)); + mbedtls_esp_random, + NULL)); + cleanup: - mbedtls_ctr_drbg_free(&ctr_drbg); - mbedtls_entropy_free(&entropy); return ret ? -1 : 0; } @@ -455,23 +440,10 @@ int crypto_ec_point_cmp(const struct crypto_ec *e, int crypto_ec_key_compare(struct crypto_ec_key *key1, struct crypto_ec_key *key2) { - int ret = 0; - mbedtls_entropy_context entropy; - mbedtls_ctr_drbg_context ctr_drbg; - - mbedtls_entropy_init(&entropy); - mbedtls_ctr_drbg_init(&ctr_drbg); - - MBEDTLS_MPI_CHK(mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy, NULL, 0)); - if (mbedtls_pk_check_pair((mbedtls_pk_context *)key1, (mbedtls_pk_context *)key2, mbedtls_ctr_drbg_random, &ctr_drbg) < 0) { - goto cleanup; + if (mbedtls_pk_check_pair((mbedtls_pk_context *)key1, (mbedtls_pk_context *)key2, mbedtls_esp_random, NULL) < 0) { + return 0; } - - ret = 1; -cleanup: - mbedtls_ctr_drbg_free(&ctr_drbg); - mbedtls_entropy_free(&entropy); - return ret; + return 1; } void crypto_debug_print_point(const char *title, struct crypto_ec *e, @@ -671,7 +643,7 @@ struct crypto_ec_key *crypto_ec_key_parse_priv(const u8 *privkey, size_t privkey wpa_printf(MSG_ERROR, "memory allocation failed"); return NULL; } - ret = mbedtls_pk_parse_key(kctx, privkey, privkey_len, NULL, 0, crypto_rng_wrapper, NULL); + ret = mbedtls_pk_parse_key(kctx, privkey, privkey_len, NULL, 0, mbedtls_esp_random, NULL); if (ret < 0) { //crypto_print_error_string(ret); @@ -727,17 +699,8 @@ int crypto_ecdh(struct crypto_ec_key *key_own, struct crypto_ec_key *key_peer, mbedtls_ecdh_context *ctx = NULL; mbedtls_pk_context *own = (mbedtls_pk_context *)key_own; mbedtls_pk_context *peer = (mbedtls_pk_context *)key_peer; - mbedtls_entropy_context entropy; - mbedtls_ctr_drbg_context ctr_drbg; int ret = -1; - mbedtls_entropy_init(&entropy); - mbedtls_ctr_drbg_init(&ctr_drbg); - - if (mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy, NULL, 0) < 0) { - goto fail; - } - *secret_len = 0; ctx = os_malloc(sizeof(*ctx)); if (!ctx) { @@ -765,7 +728,7 @@ int crypto_ecdh(struct crypto_ec_key *key_own, struct crypto_ec_key *key_peer, } if (mbedtls_ecdh_calc_secret(ctx, secret_len, secret, DPP_MAX_SHARED_SECRET_LEN, - mbedtls_ctr_drbg_random, &ctr_drbg) < 0) { + mbedtls_esp_random, NULL) < 0) { wpa_printf(MSG_ERROR, "failed to calculate secret"); goto fail; } @@ -778,8 +741,6 @@ int crypto_ecdh(struct crypto_ec_key *key_own, struct crypto_ec_key *key_peer, ret = 0; fail: - mbedtls_ctr_drbg_free(&ctr_drbg); - mbedtls_entropy_free(&entropy); if (ctx) { mbedtls_ecdh_free(ctx); os_free(ctx); @@ -804,7 +765,7 @@ int crypto_ecdsa_get_sign(unsigned char *hash, goto fail; } ret = mbedtls_ecdsa_sign(&ctx->MBEDTLS_PRIVATE(grp), (mbedtls_mpi *)r, (mbedtls_mpi *)s, - &ctx->MBEDTLS_PRIVATE(d), hash, SHA256_MAC_LEN, crypto_rng_wrapper, NULL); + &ctx->MBEDTLS_PRIVATE(d), hash, SHA256_MAC_LEN, mbedtls_esp_random, NULL); fail: mbedtls_ecdsa_free(ctx); @@ -901,7 +862,7 @@ struct crypto_ec_key * crypto_ec_key_gen(u16 ike_group) } mbedtls_ecp_gen_key(MBEDTLS_ECP_DP_SECP256R1, mbedtls_pk_ec(*kctx), //get this from argument - crypto_rng_wrapper, NULL); + mbedtls_esp_random, NULL); return (struct crypto_ec_key *)kctx; fail: @@ -1081,8 +1042,6 @@ void crypto_ecdh_deinit(struct crypto_ecdh *ecdh) struct crypto_ecdh * crypto_ecdh_init(int group) { - mbedtls_ctr_drbg_context ctr_drbg; - mbedtls_entropy_context entropy; mbedtls_ecdh_context *ctx; ctx = os_zalloc(sizeof(*ctx)); @@ -1100,24 +1059,12 @@ struct crypto_ecdh * crypto_ecdh_init(int group) goto fail; } - /* Initialize CTR_DRBG context */ - mbedtls_ctr_drbg_init(&ctr_drbg); - mbedtls_entropy_init(&entropy); - - /* Seed and setup CTR_DRBG entropy source for future reseeds */ - if (mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy, NULL, 0) != 0) { - wpa_printf(MSG_ERROR, "Seeding entropy source failed"); - goto fail; - } - /* Generates ECDH keypair on elliptic curve */ - if (mbedtls_ecdh_gen_public(ACCESS_ECDH(&ctx, grp), ACCESS_ECDH(&ctx, d), ACCESS_ECDH(&ctx, Q), mbedtls_ctr_drbg_random, &ctr_drbg) != 0) { + if (mbedtls_ecdh_gen_public(ACCESS_ECDH(&ctx, grp), ACCESS_ECDH(&ctx, d), ACCESS_ECDH(&ctx, Q), mbedtls_esp_random, NULL) != 0) { wpa_printf(MSG_ERROR, "ECDH keypair on curve failed"); goto fail; } - mbedtls_ctr_drbg_free(&ctr_drbg); - mbedtls_entropy_free(&entropy); return (struct crypto_ecdh *)ctx; fail: if (ctx) { @@ -1125,8 +1072,6 @@ struct crypto_ecdh * crypto_ecdh_init(int group) os_free(ctx); ctx = NULL; } - mbedtls_ctr_drbg_free(&ctr_drbg); - mbedtls_entropy_free(&entropy); return NULL; } @@ -1174,18 +1119,6 @@ struct wpabuf * crypto_ecdh_set_peerkey(struct crypto_ecdh *ecdh, int inc_y, return 0; } - mbedtls_ctr_drbg_context ctr_drbg; - mbedtls_entropy_context entropy; - - /* Initialize CTR_DRBG context */ - mbedtls_ctr_drbg_init(&ctr_drbg); - mbedtls_entropy_init(&entropy); - - /* Seed and setup CTR_DRBG entropy source for future reseeds */ - if (mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy, NULL, 0) != 0) { - wpa_printf(MSG_ERROR, "Seeding entropy source failed"); - goto cleanup; - } len_prime = ACCESS_ECDH(ctx, grp).pbits / 8; bn_x = crypto_bignum_init_set(key, len); @@ -1244,7 +1177,7 @@ struct wpabuf * crypto_ecdh_set_peerkey(struct crypto_ecdh *ecdh, int inc_y, /* Calculate secret z = F(DH(x,Y)) */ - secret_key = mbedtls_ecdh_calc_secret(ctx, &olen, secret, len_prime, mbedtls_ctr_drbg_random, &ctr_drbg); + secret_key = mbedtls_ecdh_calc_secret(ctx, &olen, secret, len_prime, mbedtls_esp_random, NULL); if (secret_key != 0) { wpa_printf(MSG_ERROR, "Calculation of secret failed"); goto cleanup; @@ -1259,8 +1192,6 @@ struct wpabuf * crypto_ecdh_set_peerkey(struct crypto_ecdh *ecdh, int inc_y, crypto_ec_key_deinit(pkey); crypto_bignum_deinit(bn_x, 1); crypto_ec_point_deinit(ec_pt, 1); - mbedtls_ctr_drbg_free(&ctr_drbg); - mbedtls_entropy_free(&entropy); return sh_secret; } diff --git a/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-rsa.c b/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-rsa.c index 5eb0220fd0cb..649e860a3c24 100644 --- a/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-rsa.c +++ b/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-rsa.c @@ -6,6 +6,7 @@ #ifdef ESP_PLATFORM #include "mbedtls/bignum.h" +#include "mbedtls/esp_mbedtls_random.h" #endif #include "utils/includes.h" @@ -14,9 +15,6 @@ #include "common/defs.h" #ifdef CONFIG_CRYPTO_MBEDTLS -#include "mbedtls/entropy.h" -#include "mbedtls/ctr_drbg.h" - #include #include #include @@ -38,11 +36,6 @@ static void crypto_dump_verify_info(u32 flags) static void crypto_dump_verify_info(u32 flags) { } #endif -static int crypto_rng_wrapper(void *ctx, unsigned char *buf, size_t len) -{ - return os_get_random(buf, len); -} - int crypto_verify_cert(const u8 *cert_start, int certlen, const u8 *ca_cert_start, int ca_certlen) { int ret; @@ -125,7 +118,7 @@ struct crypto_private_key * crypto_private_key_import(const u8 *key, mbedtls_pk_init(pkey); ret = mbedtls_pk_parse_key(pkey, key, len, (const unsigned char *)passwd, - passwd ? os_strlen(passwd) : 0, crypto_rng_wrapper, NULL); + passwd ? os_strlen(passwd) : 0, mbedtls_esp_random, NULL); if (ret < 0) { wpa_printf(MSG_ERROR, "failed to parse private key"); @@ -190,35 +183,13 @@ int crypto_public_key_encrypt_pkcs1_v15(struct crypto_public_key *key, { int ret; mbedtls_pk_context *pkey = (mbedtls_pk_context *)key; - const char *pers = "rsa_encrypt"; - mbedtls_entropy_context *entropy = os_zalloc(sizeof(*entropy)); - mbedtls_ctr_drbg_context *ctr_drbg = os_zalloc(sizeof(*ctr_drbg)); - if (!pkey || !entropy || !ctr_drbg) { - if (entropy) { - os_free(entropy); - } - if (ctr_drbg) { - os_free(ctr_drbg); - } - wpa_printf(MSG_ERROR, "failed to allocate memory"); + if (!pkey) { return -1; } - mbedtls_entropy_init(entropy); - mbedtls_ctr_drbg_init(ctr_drbg); - - ret = mbedtls_ctr_drbg_seed(ctr_drbg, mbedtls_entropy_func, - entropy, (const unsigned char *) pers, - strlen(pers)); - if (ret != 0) { - wpa_printf(MSG_ERROR, " failed ! mbedtls_ctr_drbg_seed returned %d", - ret); - goto cleanup; - } - - ret = mbedtls_rsa_pkcs1_encrypt(mbedtls_pk_rsa(*pkey), mbedtls_ctr_drbg_random, - ctr_drbg, inlen, in, out); + ret = mbedtls_rsa_pkcs1_encrypt(mbedtls_pk_rsa(*pkey), mbedtls_esp_random, + NULL, inlen, in, out); if (ret != 0) { wpa_printf(MSG_ERROR, " failed ! mbedtls_rsa_pkcs1_encrypt returned -0x%04x", -ret); @@ -227,11 +198,6 @@ int crypto_public_key_encrypt_pkcs1_v15(struct crypto_public_key *key, *outlen = mbedtls_rsa_get_len(mbedtls_pk_rsa(*pkey)); cleanup: - mbedtls_ctr_drbg_free(ctr_drbg); - mbedtls_entropy_free(entropy); - os_free(entropy); - os_free(ctr_drbg); - return ret; } @@ -242,40 +208,18 @@ int crypto_private_key_decrypt_pkcs1_v15(struct crypto_private_key *key, int ret; size_t i; mbedtls_pk_context *pkey = (mbedtls_pk_context *)key; - const char *pers = "rsa_decrypt"; - mbedtls_entropy_context *entropy = os_malloc(sizeof(*entropy)); - mbedtls_ctr_drbg_context *ctr_drbg = os_malloc(sizeof(*ctr_drbg)); - if (!pkey || !entropy || !ctr_drbg) { - if (entropy) { - os_free(entropy); - } - if (ctr_drbg) { - os_free(ctr_drbg); - } + if (!pkey) { return -1; } - mbedtls_ctr_drbg_init(ctr_drbg); - mbedtls_entropy_init(entropy); - ret = mbedtls_ctr_drbg_seed(ctr_drbg, mbedtls_entropy_func, - entropy, (const unsigned char *) pers, - strlen(pers)); - - if (ret < 0) { - goto cleanup; - } i = mbedtls_rsa_get_len(mbedtls_pk_rsa(*pkey)); - ret = mbedtls_rsa_rsaes_pkcs1_v15_decrypt(mbedtls_pk_rsa(*pkey), mbedtls_ctr_drbg_random, - ctr_drbg, &i, in, out, *outlen); + ret = mbedtls_rsa_rsaes_pkcs1_v15_decrypt(mbedtls_pk_rsa(*pkey), mbedtls_esp_random, + NULL, &i, in, out, *outlen); - *outlen = i; - -cleanup: - mbedtls_ctr_drbg_free(ctr_drbg); - mbedtls_entropy_free(entropy); - os_free(entropy); - os_free(ctr_drbg); + if (ret == 0) { + *outlen = i; + } return ret; } @@ -285,27 +229,13 @@ int crypto_private_key_sign_pkcs1(struct crypto_private_key *key, u8 *out, size_t *outlen) { int ret; - const char *pers = "rsa_encrypt"; mbedtls_pk_context *pkey = (mbedtls_pk_context *)key; - mbedtls_entropy_context *entropy = os_malloc(sizeof(*entropy)); - mbedtls_ctr_drbg_context *ctr_drbg = os_malloc(sizeof(*ctr_drbg)); - if (!pkey || !entropy || !ctr_drbg) { - if (entropy) { - os_free(entropy); - } - if (ctr_drbg) { - os_free(ctr_drbg); - } + if (!pkey) { return -1; } - mbedtls_ctr_drbg_init(ctr_drbg); - mbedtls_entropy_init(entropy); - ret = mbedtls_ctr_drbg_seed(ctr_drbg, mbedtls_entropy_func, - entropy, (const unsigned char *) pers, - strlen(pers)); - if ((ret = mbedtls_rsa_pkcs1_sign(mbedtls_pk_rsa(*pkey), mbedtls_ctr_drbg_random, ctr_drbg, + if ((ret = mbedtls_rsa_pkcs1_sign(mbedtls_pk_rsa(*pkey), mbedtls_esp_random, NULL, (mbedtls_pk_rsa(*pkey))->MBEDTLS_PRIVATE(hash_id), inlen, in, out)) != 0) { wpa_printf(MSG_ERROR, " failed ! mbedtls_rsa_pkcs1_sign returned %d", ret); @@ -314,10 +244,6 @@ int crypto_private_key_sign_pkcs1(struct crypto_private_key *key, *outlen = mbedtls_rsa_get_len(mbedtls_pk_rsa(*pkey)); cleanup: - mbedtls_ctr_drbg_free(ctr_drbg); - mbedtls_entropy_free(entropy); - os_free(entropy); - os_free(ctr_drbg); return ret; } diff --git a/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls.c b/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls.c index 73addce23b07..46570e6b7d59 100644 --- a/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls.c +++ b/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls.c @@ -15,8 +15,6 @@ #include "sha256.h" #include "mbedtls/ecp.h" -#include "mbedtls/entropy.h" -#include "mbedtls/ctr_drbg.h" #include "mbedtls/md.h" #include "mbedtls/aes.h" #include "mbedtls/bignum.h" diff --git a/components/wpa_supplicant/esp_supplicant/src/crypto/tls_mbedtls.c b/components/wpa_supplicant/esp_supplicant/src/crypto/tls_mbedtls.c index 803bcc74afb9..4eef749d73dc 100644 --- a/components/wpa_supplicant/esp_supplicant/src/crypto/tls_mbedtls.c +++ b/components/wpa_supplicant/esp_supplicant/src/crypto/tls_mbedtls.c @@ -13,6 +13,8 @@ #include "crypto/sha256.h" #include "crypto/sha384.h" +#include "mbedtls/esp_mbedtls_random.h" + /* TODO: Remove this once the appropriate solution is found * * ssl_misc.h header uses private elements from @@ -24,8 +26,6 @@ // located at mbedtls/library/ssl_misc.h #include "ssl_misc.h" -#include "mbedtls/ctr_drbg.h" -#include "mbedtls/entropy.h" #include "mbedtls/debug.h" #include "mbedtls/oid.h" #ifdef ESPRESSIF_USE @@ -75,8 +75,6 @@ struct tls_data { typedef struct tls_context { mbedtls_ssl_context ssl; /*!< TLS/SSL context */ - mbedtls_entropy_context entropy; /*!< mbedTLS entropy context structure */ - mbedtls_ctr_drbg_context ctr_drbg; /*!< mbedTLS ctr drbg context structure */ mbedtls_ssl_config conf; /*!< TLS/SSL config to be shared structures */ mbedtls_x509_crt cacert; /*!< Container for X.509 CA certificate */ mbedtls_x509_crt *cacert_ptr; /*!< Pointer to the cacert being used. */ @@ -105,9 +103,7 @@ static void tls_mbedtls_cleanup(tls_context_t *tls) mbedtls_x509_crt_free(&tls->cacert); mbedtls_x509_crt_free(&tls->clientcert); mbedtls_pk_free(&tls->clientkey); - mbedtls_entropy_free(&tls->entropy); mbedtls_ssl_config_free(&tls->conf); - mbedtls_ctr_drbg_free(&tls->ctr_drbg); mbedtls_ssl_free(&tls->ssl); } @@ -181,7 +177,7 @@ static int set_pki_context(tls_context_t *tls, const struct tls_connection_param ret = mbedtls_pk_parse_key(&tls->clientkey, cfg->private_key_blob, cfg->private_key_blob_len, (const unsigned char *)cfg->private_key_passwd, - cfg->private_key_passwd ? os_strlen(cfg->private_key_passwd) : 0, mbedtls_ctr_drbg_random, &tls->ctr_drbg); + cfg->private_key_passwd ? os_strlen(cfg->private_key_passwd) : 0, mbedtls_esp_random, NULL); if (ret < 0) { wpa_printf(MSG_ERROR, "mbedtls_pk_parse_keyfile returned -0x%x", -ret); return ret; @@ -599,9 +595,7 @@ static int tls_create_mbedtls_handle(struct tls_connection *conn, assert(tls != NULL); mbedtls_ssl_init(&tls->ssl); - mbedtls_ctr_drbg_init(&tls->ctr_drbg); mbedtls_ssl_config_init(&tls->conf); - mbedtls_entropy_init(&tls->entropy); ret = set_client_config(params, tls); if (ret != 0) { @@ -609,14 +603,7 @@ static int tls_create_mbedtls_handle(struct tls_connection *conn, goto exit; } - ret = mbedtls_ctr_drbg_seed(&tls->ctr_drbg, mbedtls_entropy_func, - &tls->entropy, NULL, 0); - if (ret != 0) { - wpa_printf(MSG_ERROR, "mbedtls_ctr_drbg_seed returned -0x%x", -ret); - goto exit; - } - - mbedtls_ssl_conf_rng(&tls->conf, mbedtls_ctr_drbg_random, &tls->ctr_drbg); + mbedtls_ssl_conf_rng(&tls->conf, mbedtls_esp_random, NULL); #if defined(CONFIG_MBEDTLS_SSL_PROTO_TLS1_3) && !defined(CONFIG_TLSV13) /* Disable TLSv1.3 even when enabled in MbedTLS and not enabled in WiFi config. diff --git a/components/wpa_supplicant/test_apps/main/test_offchannel.c b/components/wpa_supplicant/test_apps/main/test_offchannel.c index e0ded0b572b8..720d26102bdb 100644 --- a/components/wpa_supplicant/test_apps/main/test_offchannel.c +++ b/components/wpa_supplicant/test_apps/main/test_offchannel.c @@ -264,4 +264,4 @@ static void test_wifi_roc(void) } } -TEST_CASE_MULTIPLE_DEVICES("test ROC and Offchannel Action Frame Tx", "[Offchan][test_env=wifi_two_dut][timeout=90]", test_wifi_roc, test_wifi_offchan_tx); +TEST_CASE_MULTIPLE_DEVICES("test ROC and Offchannel Action Frame Tx", "[Offchan][test_env=two_duts][timeout=90]", test_wifi_roc, test_wifi_offchan_tx); diff --git a/components/wpa_supplicant/test_apps/pytest_wpa_supplicant_ut.py b/components/wpa_supplicant/test_apps/pytest_wpa_supplicant_ut.py index 576624e8395d..03abfd134030 100644 --- a/components/wpa_supplicant/test_apps/pytest_wpa_supplicant_ut.py +++ b/components/wpa_supplicant/test_apps/pytest_wpa_supplicant_ut.py @@ -25,7 +25,7 @@ def test_wpa_supplicant_ut(dut: Dut) -> None: @pytest.mark.esp32c5 @pytest.mark.esp32c6 @pytest.mark.esp32c61 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count', [ @@ -35,11 +35,11 @@ def test_wpa_supplicant_ut(dut: Dut) -> None: ) def test_wpa_supplicant_ut_offchan(case_tester: CaseTester) -> None: for case in case_tester.test_menu: - if case.attributes.get('test_env') == 'wifi_two_dut': + if case.attributes.get('test_env') == 'two_duts': case_tester.run_multi_dev_case(case=case, reset=True) -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.esp32c2eco4 @pytest.mark.xtal_26mhz @pytest.mark.parametrize( @@ -56,11 +56,11 @@ def test_wpa_supplicant_ut_offchan(case_tester: CaseTester) -> None: ) def test_wpa_supplicant_esp32c2eco4_xtal26mhz(case_tester: CaseTester) -> None: for case in case_tester.test_menu: - if case.attributes.get('test_env') == 'wifi_two_dut': + if case.attributes.get('test_env') == 'two_duts': case_tester.run_multi_dev_case(case=case, reset=True) -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.esp32c3eco7 @pytest.mark.parametrize( 'count, config, target', @@ -75,5 +75,5 @@ def test_wpa_supplicant_esp32c2eco4_xtal26mhz(case_tester: CaseTester) -> None: ) def test_wpa_supplicant_esp32c3eco7(case_tester: CaseTester) -> None: for case in case_tester.test_menu: - if case.attributes.get('test_env') == 'wifi_two_dut': + if case.attributes.get('test_env') == 'two_duts': case_tester.run_multi_dev_case(case=case, reset=True) diff --git a/conftest.py b/conftest.py index 35bf868261a2..167472038619 100644 --- a/conftest.py +++ b/conftest.py @@ -371,27 +371,33 @@ def set_dut_log_url(record_xml_attribute: t.Callable[[str, object], None], _pexp # Record the "dut_log_url" attribute in the XML report once test execution finished yield - if not isinstance(_pexpect_logfile, str): - record_xml_attribute('dut_log_url', 'No log URL found') - return + def _attach_log_url_to_xml_attribute(log_file_path: str) -> str: + if not isinstance(log_file_path, str): + return 'No log URL found' - ci_pages_url = os.getenv('CI_PAGES_URL') - logdir_pattern = re.compile(rf'({DEFAULT_LOGDIR}/.*)') - match = logdir_pattern.search(_pexpect_logfile) + ci_pages_url = os.getenv('CI_PAGES_URL') + logdir_pattern = re.compile(rf'({DEFAULT_LOGDIR}/.*)') + match = logdir_pattern.search(log_file_path) - if not match: - record_xml_attribute('dut_log_url', 'No log URL found') - return + if not match: + return 'No log URL found' - if not ci_pages_url: - record_xml_attribute('dut_log_url', _pexpect_logfile) - return + if not ci_pages_url: + return log_file_path - job_id = os.getenv('CI_JOB_ID', '0') - modified_ci_pages_url = ci_pages_url.replace('esp-idf', '-/esp-idf') - log_url = f'{modified_ci_pages_url}/-/jobs/{job_id}/artifacts/{match.group(1)}' + job_id = os.getenv('CI_JOB_ID', '0') + modified_ci_pages_url = ci_pages_url.replace('esp-idf', '-/esp-idf') + log_url = f'{modified_ci_pages_url}/-/jobs/{job_id}/artifacts/{match.group(1)}' - record_xml_attribute('dut_log_url', log_url) + return log_url + + xml_attribute = [] + if isinstance(_pexpect_logfile, str): + xml_attribute.append(_attach_log_url_to_xml_attribute(_pexpect_logfile)) + if isinstance(_pexpect_logfile, tuple): + for i, log_file in enumerate(_pexpect_logfile): + xml_attribute.append(_attach_log_url_to_xml_attribute(log_file)) + record_xml_attribute('dut_log_url', ';'.join(xml_attribute)) ###################### diff --git a/docs/doxygen/Doxyfile_esp32p4 b/docs/doxygen/Doxyfile_esp32p4 index 66146f1ed765..d366e6ca0acf 100644 --- a/docs/doxygen/Doxyfile_esp32p4 +++ b/docs/doxygen/Doxyfile_esp32p4 @@ -35,6 +35,7 @@ INPUT += \ $(PROJECT_PATH)/components/esp_driver_isp/include/driver/isp_awb.h \ $(PROJECT_PATH)/components/esp_driver_isp/include/driver/isp_ccm.h \ $(PROJECT_PATH)/components/esp_driver_isp/include/driver/isp_bf.h \ + $(PROJECT_PATH)/components/esp_driver_isp/include/driver/isp_blc.h \ $(PROJECT_PATH)/components/esp_driver_isp/include/driver/isp_lsc.h \ $(PROJECT_PATH)/components/esp_driver_isp/include/driver/isp_demosaic.h \ $(PROJECT_PATH)/components/esp_driver_isp/include/driver/isp_sharpen.h \ diff --git a/docs/en/api-reference/peripherals/isp.rst b/docs/en/api-reference/peripherals/isp.rst index 6ce6c570082d..5d787b42a7d1 100644 --- a/docs/en/api-reference/peripherals/isp.rst +++ b/docs/en/api-reference/peripherals/isp.rst @@ -18,6 +18,7 @@ Terminology - AF: Auto-focus - AWB: Auto-white balance - BF: Bayer noise filter + - BLC: Black Level Correction - CCM: Color correction matrix ISP Pipeline @@ -653,7 +654,7 @@ Calling :cpp:func:`esp_isp_demosaic_configure` to configure Demosaic function, y ... }; - ESP_ERROR_CHECK(esp_isp_demosaic_configure(isp_proc, &sharpen_config)); + ESP_ERROR_CHECK(esp_isp_demosaic_configure(isp_proc, &demosaic_config)); ESP_ERROR_CHECK(esp_isp_demosaic_enable(isp_proc)); After calling :cpp:func:`esp_isp_demosaic_configure`, you need to enable the ISP Sharpen processor, by calling :cpp:func:`esp_isp_demosaic_enable`. This function: diff --git a/docs/en/api-reference/peripherals/ledc.rst b/docs/en/api-reference/peripherals/ledc.rst index 0a39a4e0c089..f1f2a924273a 100644 --- a/docs/en/api-reference/peripherals/ledc.rst +++ b/docs/en/api-reference/peripherals/ledc.rst @@ -279,6 +279,10 @@ The range of the duty cycle values passed to functions depends on selected ``dut The hardware limitation above only applies to chip revision before v1.2. + .. only:: esp32p4 + + The hardware limitation above only applies to chip revision before v3.0. + Change PWM Duty Cycle Using Hardware """""""""""""""""""""""""""""""""""" diff --git a/docs/en/api-reference/protocols/mbedtls.rst b/docs/en/api-reference/protocols/mbedtls.rst index 7179397414d6..d444db109eb0 100644 --- a/docs/en/api-reference/protocols/mbedtls.rst +++ b/docs/en/api-reference/protocols/mbedtls.rst @@ -118,5 +118,5 @@ Reducing Binary Size Under ``Component Config -> mbedTLS``, there are multiple Mbed TLS features which are enabled by default but can be disabled if not needed to save code size. More information can be about this can be found in :ref:`Minimizing Binary Size ` docs. -.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.6.4/ +.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.6.5/ .. _`Knowledge Base`: https://mbed-tls.readthedocs.io/en/latest/kb/ diff --git a/docs/en/security/flash-encryption.rst b/docs/en/security/flash-encryption.rst index 5ff16ab44d84..4606cbaa7571 100644 --- a/docs/en/security/flash-encryption.rst +++ b/docs/en/security/flash-encryption.rst @@ -510,6 +510,9 @@ If all partitions needs to be updated in encrypted format, run: idf.py encrypted-flash monitor +.. note:: + + The above operations are only applicable when the ``DIS_DOWNLOAD_MANUAL_ENCRYPT`` eFuse bit has not been programmed. If this eFuse bit has been programmed, you must flash the pre-encrypted ciphertext image instead. .. _flash-enc-release-mode: diff --git a/docs/en/security/security-features-enablement-workflows.rst b/docs/en/security/security-features-enablement-workflows.rst index 0a9a7966421b..062f9df92dc8 100644 --- a/docs/en/security/security-features-enablement-workflows.rst +++ b/docs/en/security/security-features-enablement-workflows.rst @@ -318,6 +318,10 @@ In this case all the eFuses related to Flash Encryption are written with help of espsecure.py encrypt_flash_data {IDF_TARGET_FLASH_ENC_ARGS} --keyfile my_flash_encryption_key.bin --address 0x10000 --output my-app-enc.bin build/my-app.bin + .. note:: + + If secure boot is enabled, perform secure boot signing of the firmware before carrying out the above encryption operation. + In the above command, the offsets are used for a sample firmware, and the actual offset for your firmware can be obtained by checking the partition table entry or by running `idf.py partition-table`. Please note that not all the binaries need to be encrypted, the encryption applies only to those generated from the partitions which are marked as ``encrypted`` in the partition table definition file. Other binaries are flashed unencrypted, i.e., as a plain output of the build process. The above files can then be flashed to their respective offset using ``esptool.py``. To see all of the command line options recommended for ``esptool.py``, see the output printed when ``idf.py build`` succeeds. @@ -669,7 +673,7 @@ The details about NVS encryption and related schemes can be found at :doc:`NVS E * CSV file name - In this case, ``sample_singlepage_blob.csv`` is the CSV file which contains the NVS data. Please replace this with the file you wish to choose. - * NVS partition offset - This is the offset at which that NVS partition shall be stored in the flash of {IDF_TARGET_NAME}. The offset of your NVS partition can be found by executing ``idf.py partition-table`` in the projtect directory. Please update the sample value of ``0x3000`` in the above-provided command to the correct offset. + * NVS partition size - This is the size of the NVS partition in bytes. Please update the sample value of ``0x3000`` in the above-provided command to the correct size of your NVS partition. 4. Configure the project @@ -718,7 +722,7 @@ In this case we generate NVS Encryption keys on a host. This key is then flashed * CSV file name - In this case `sample_singlepage_blob.csv` is the CSV file which contains the NVS data. Please replace it with the file you wish to choose. - * NVS partition offset - This is the offset at which the NVS partition shall be stored in the flash of {IDF_TARGET_NAME}. The offset of your NVS partition can be found by executing ``idf.py partition-table`` in the projtect directory. Please update the sample value of ``0x3000`` in the above-provided command to the correct offset. + * NVS partition size - This is the size of the NVS partition in bytes. Please update the sample value of ``0x3000`` in the above-provided command to the correct size of your NVS partition. 3. Configure the project @@ -729,4 +733,4 @@ In this case we generate NVS Encryption keys on a host. This key is then flashed The NVS partition (``nvs_encr_partition.bin``) and NVS encryption key (``nvs_encr_key.bin``) can then be flashed to their respective offset using ``esptool.py``. To see all of the command line options recommended for ``esptool.py``, check the output print when ``idf.py build`` succeeds. - If Flash Encryption is enabled for the chip, then please encrypt the partition first before flashing. You may refer the flashing related steps of `Flash Encryption workflow `_. + If Flash Encryption is enabled for the chip, then please encrypt the NVS key partition first before flashing. You may refer the flashing related steps of `Flash Encryption workflow `_. diff --git a/docs/en/security/security.rst b/docs/en/security/security.rst index bc0a5f71aef9..49b398925986 100644 --- a/docs/en/security/security.rst +++ b/docs/en/security/security.rst @@ -75,7 +75,7 @@ Please refer to :doc:`flash-encryption` for detailed information about this feat Flash Encryption Best Practices ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -* It is recommended to use flash Encryption release mode for the production use-cases. +* It is recommended to use :ref:`flash-enc-release-mode` for the production use-cases. * It is recommended to have a unique flash encryption key per device. * Enable :ref:`secure_boot-guide` as an extra layer of protection, and to prevent an attacker from selectively corrupting any part of the flash before boot. diff --git a/docs/zh_CN/api-reference/peripherals/ledc.rst b/docs/zh_CN/api-reference/peripherals/ledc.rst index 192efee467bd..f8aa2e348166 100644 --- a/docs/zh_CN/api-reference/peripherals/ledc.rst +++ b/docs/zh_CN/api-reference/peripherals/ledc.rst @@ -279,6 +279,10 @@ LEDC 驱动提供了一个辅助函数 :cpp:func:`ledc_find_suitable_duty_resolu 以上硬件限制仅在芯片版本低于 v1.2 的 ESP32H2 上存在。 + .. only:: esp32p4 + + 以上硬件限制仅在芯片版本低于 v3.0 的 ESP32P4 上存在。 + 使用硬件改变 PWM 占空比 """""""""""""""""""""""""""""""""""" diff --git a/docs/zh_CN/api-reference/protocols/mbedtls.rst b/docs/zh_CN/api-reference/protocols/mbedtls.rst index 42a1622143c7..affcf46acedc 100644 --- a/docs/zh_CN/api-reference/protocols/mbedtls.rst +++ b/docs/zh_CN/api-reference/protocols/mbedtls.rst @@ -118,5 +118,5 @@ ESP-IDF 中的示例使用 :doc:`/api-reference/protocols/esp_tls`，为访问 在 ``Component Config -> mbedTLS`` 中，有多个 Mbed TLS 功能默认为启用状态。如果不需要这些功能，可将其禁用以减小固件大小。要了解更多信息，请参考 :ref:`Minimizing Binary Size ` 文档。 -.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.6.4/ +.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.6.5/ .. _`Knowledge Base`: https://mbed-tls.readthedocs.io/en/latest/kb/ diff --git a/docs/zh_CN/security/flash-encryption.rst b/docs/zh_CN/security/flash-encryption.rst index 37771c4c6351..ba48561907ce 100644 --- a/docs/zh_CN/security/flash-encryption.rst +++ b/docs/zh_CN/security/flash-encryption.rst @@ -510,6 +510,9 @@ flash 加密设置 idf.py encrypted-flash monitor +.. note:: + + 上述操作仅适用于 ``DIS_DOWNLOAD_MANUAL_ENCRYPT`` eFuse 位未被烧录的情况。如果该 eFuse 位已被烧录，则需要烧录加密后的密文镜像。 .. _flash-enc-release-mode: diff --git a/docs/zh_CN/security/secure-boot-v2.rst b/docs/zh_CN/security/secure-boot-v2.rst index 202322dffb2b..563513792125 100644 --- a/docs/zh_CN/security/secure-boot-v2.rst +++ b/docs/zh_CN/security/secure-boot-v2.rst @@ -128,7 +128,7 @@ 5. 引导加载程序验证应用程序镜像的签名块，请参阅 :ref:`verify_signature-block`。如果验证失败，启动过程将中止。 -6. 引导加载程序使用原始镜像数据、相应的签名块以及 eFuse 验证引导加载程序镜像，请参阅 :ref:`verify_image`。如果验证失败，启动过程将中止。如果验证失败，但发现了其他应用程序镜像，引导加载程序将使用步骤 5 到 7 验证另一个镜像。该过程将重复，直至找到有效镜像，或所有镜像验证完毕。 +6. 引导加载程序使用原始镜像数据、相应的签名块以及 eFuse 验证应用程序镜像，请参阅 :ref:`verify_image`。如果验证失败，启动过程将中止。如果验证失败，但发现了其他应用程序镜像，引导加载程序将使用步骤 5 到 7 验证另一个镜像。该过程将重复，直至找到有效镜像，或所有镜像验证完毕。 7. 引导加载程序执行经验证的应用程序镜像。 diff --git a/docs/zh_CN/security/security-features-enablement-workflows.rst b/docs/zh_CN/security/security-features-enablement-workflows.rst index 9e2ec82a0359..e91b975bff11 100644 --- a/docs/zh_CN/security/security-features-enablement-workflows.rst +++ b/docs/zh_CN/security/security-features-enablement-workflows.rst @@ -318,6 +318,10 @@ espsecure.py encrypt_flash_data {IDF_TARGET_FLASH_ENC_ARGS} --keyfile my_flash_encryption_key.bin --address 0x10000 --output my-app-enc.bin build/my-app.bin + .. note:: + + 如果同时启用了安全启动功能，请先对固件进行安全启动签名，再执行上述加密操作。 + 上述命令中的偏移量仅适用于示例固件，请通过检查分区表条目或运行 `idf.py partition-table` 来获取你固件的实际偏移量。请注意，不需要加密所有二进制文件，只需加密在分区表定义文件中带有 ``encrypted`` 标记的文件，其他二进制文件只作为构建过程的普通输出进行烧录。 使用 ``esptool.py`` 可以将上述文件烧写到各自的偏移地址。要查看所有推荐的 ``esptool.py`` 命令行选项，请查阅 ``idf.py build`` 构建成功后打印的输出。 @@ -669,7 +673,7 @@ Secure Boot v2 指南 * CSV 文件名 - 此命令中，``sample_singlepage_blob.csv`` 是指包含 NVS 数据的 CSV 文件，请将其替换为所选择的文件。 - * NVS 分区偏移量 - 这是 {IDF_TARGET_NAME} flash 中存储 NVS 分区的偏移地址。通过在项目目录下执行 ``idf.py partition-table`` 命令，可以找到 NVS 分区偏移地址。请将上述命令中的示例值 ``0x3000`` 调整为正确的偏移量。 + * NVS 分区大小 - 这是 NVS 分区的大小（以字节为单位）。请将上述命令中的示例值 ``0x3000`` 更新为你实际 NVS 分区的正确大小。 4. 配置项目 @@ -718,7 +722,7 @@ Secure Boot v2 指南 * CSV 文件名 - 上述命名中的 `sample_singlepage_blob.csv` 是指包含 NVS 数据的 CSV 文件，请将其替换为所选文件。 - * NVS 分区偏移量 - 这是 NVS 分区在 {IDF_TARGET_NAME} 的 flash 中存储时的偏移地址。在项目目录中执行 ``idf.py partition-table`` 命令，可以找到 NVS 分区的偏移量。请将上述命令中的示例值 ``0x3000`` 替换为正确的偏移量。 + * NVS 分区大小 - 这是 NVS 分区的大小（以字节为单位）。请将上述命令中的示例值 ``0x3000`` 更新为你实际 NVS 分区的正确大小。 3. 配置项目 @@ -729,4 +733,4 @@ Secure Boot v2 指南 使用 ``esptool.py`` 命令，将 NVS 分区 (``nvs_encr_partition.bin``) 和 NVS 加密密钥 (``nvs_encr_key.bin``) 烧录到各自的偏移地址。通过 ``idf.py build`` 成功后打印的输出，可查看所有推荐的 ``esptool.py`` 命令行选项。 - 若芯片启用了 flash 加密，请在烧录之前先加密分区。详情请参阅 `flash 加密工作流程 `_ 中与烧录相关的步骤。 + 若芯片启用了 flash 加密，请在烧录前先对 NVS 加密密钥分区进行加密。详情请参阅 `flash 加密工作流程 `_ 中与烧录相关的步骤。 diff --git a/docs/zh_CN/security/security.rst b/docs/zh_CN/security/security.rst index 6bdbfcec1b47..3037e4dc64a9 100644 --- a/docs/zh_CN/security/security.rst +++ b/docs/zh_CN/security/security.rst @@ -75,7 +75,7 @@ flash 加密功能可以加密外部 flash 中的内容，从而保护存储在 flash 加密最佳实践 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -* 建议在生产环境中使用 flash 加密的发布模式。 +* 建议在生产环境中使用 flash 加密的 :ref:`flash-enc-release-mode`。 * 建议为每个设备生成唯一的 flash 加密密钥。 * 启用 :ref:`secure_boot-guide` 作为额外保护层，防止 flash 在启动前遭受恶意攻击。 diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/pytest_ble_throughput_test.py b/examples/bluetooth/bluedroid/ble/ble_throughput/pytest_ble_throughput_test.py index f7194312ec80..9e9d83006476 100644 --- a/examples/bluetooth/bluedroid/ble/ble_throughput/pytest_ble_throughput_test.py +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/pytest_ble_throughput_test.py @@ -1,4 +1,4 @@ -# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 import os.path import time @@ -16,7 +16,7 @@ @pytest.mark.esp32c5 @pytest.mark.esp32h2 @pytest.mark.esp32s3 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count, app_path, config, erase_all', [ (2, @@ -50,7 +50,7 @@ def test_gatt_write_throughput(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> Non # Case 2: gatt write throughput test for ESP32C2 26mhz xtal @pytest.mark.esp32c2 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.xtal_26mhz @pytest.mark.parametrize( 'count, target, baud, app_path, config, erase_all', [ @@ -91,7 +91,7 @@ def test_c2_26mhz_xtal_write_throughput(app_path: str, dut: Tuple[IdfDut, IdfDut @pytest.mark.esp32c5 @pytest.mark.esp32h2 @pytest.mark.esp32s3 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count, app_path, config, erase_all', [ (2, @@ -127,7 +127,7 @@ def test_gatt_notify_throughput(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> No # Case 4: gatt notify throughput test for ESP32C2 26mhz xtal @pytest.mark.esp32c2 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.xtal_26mhz @pytest.mark.parametrize( 'count, target, baud, app_path, config, erase_all', [ diff --git a/examples/bluetooth/bluedroid/ble/pytest_ble_test.py b/examples/bluetooth/bluedroid/ble/pytest_ble_test.py index 9de955b30014..776d9d4cf23f 100644 --- a/examples/bluetooth/bluedroid/ble/pytest_ble_test.py +++ b/examples/bluetooth/bluedroid/ble/pytest_ble_test.py @@ -1,4 +1,4 @@ -# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 import os.path from typing import Tuple @@ -16,7 +16,7 @@ @pytest.mark.esp32h2 @pytest.mark.esp32s3 @pytest.mark.esp32c61 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count, app_path, config, erase_all', [ (2, @@ -54,7 +54,7 @@ def test_gatt_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: # Case 2: gatt client and gatt server test for ESP32C2 26mhz xtal @pytest.mark.esp32c2 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.xtal_26mhz @pytest.mark.parametrize( 'count, target, baud, app_path, config, erase_all', [ @@ -99,7 +99,7 @@ def test_c2_26mhz_xtal_gatt_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> N @pytest.mark.esp32h2 @pytest.mark.esp32s3 @pytest.mark.esp32c61 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count, app_path, config, erase_all', [ (2, @@ -154,7 +154,7 @@ def test_gatt_security_func(app_path: str, dut: Tuple[IdfDut, IdfDut], target: T # Case 4: gatt security server and gatt security client test for ESP32C2 26mhz xtal @pytest.mark.esp32c2 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.xtal_26mhz @pytest.mark.parametrize( 'count, target, baud, app_path, config, erase_all', [ @@ -210,7 +210,7 @@ def test_c2_26mhz_xtal_gatt_security_func(app_path: str, dut: Tuple[IdfDut, IdfD @pytest.mark.esp32h2 @pytest.mark.esp32s3 @pytest.mark.esp32c61 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count, app_path, config, erase_all', [ (2, @@ -238,7 +238,7 @@ def test_ble_ibeacon_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: # Case 5: ble ibeacon test for ESP32C2 26mhz xtal @pytest.mark.esp32c2 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.xtal_26mhz @pytest.mark.parametrize( 'count, target, baud, app_path, config, erase_all', [ diff --git a/examples/bluetooth/bluedroid/ble_50/pytest_ble50_test.py b/examples/bluetooth/bluedroid/ble_50/pytest_ble50_test.py index b5b02e87f809..d1c8d0afac6a 100644 --- a/examples/bluetooth/bluedroid/ble_50/pytest_ble50_test.py +++ b/examples/bluetooth/bluedroid/ble_50/pytest_ble50_test.py @@ -1,4 +1,4 @@ -# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 import os.path from typing import Tuple @@ -14,7 +14,7 @@ @pytest.mark.esp32h2 @pytest.mark.esp32s3 @pytest.mark.esp32c61 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count, app_path, config, erase_all', [ (2, @@ -47,7 +47,7 @@ def test_ble50_security_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: # Case 2: ble50 security client and ble50 security server test for ESP32C2 26mhz xtal @pytest.mark.esp32c2 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.xtal_26mhz @pytest.mark.parametrize( 'count, target, baud, app_path, config, erase_all', [ @@ -86,7 +86,7 @@ def test_c2_26mhz_xtal_ble50_security_func(app_path: str, dut: Tuple[IdfDut, Idf @pytest.mark.esp32h2 @pytest.mark.esp32s3 @pytest.mark.esp32c61 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count, app_path, config, erase_all', [ (2, @@ -115,7 +115,7 @@ def test_period_adv_sync_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None # Case 4: period_adv and period_sync test for ESP32C2 26mhz xtal @pytest.mark.esp32c2 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.xtal_26mhz @pytest.mark.parametrize( 'count, target, baud, app_path, config, erase_all', [ diff --git a/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_hf.c b/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_hf.c index c60bde9997cf..d4b0defcc4e5 100644 --- a/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_hf.c +++ b/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_hf.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -25,7 +25,6 @@ #include "sdkconfig.h" #include "bt_app_core.h" #include "bt_app_hf.h" -#include "osi/allocator.h" const char *c_hf_evt_str[] = { "CONNECTION_STATE_EVT", /*!< SERVICE LEVEL CONNECTION STATE CONTROL */ @@ -231,7 +230,7 @@ static void bt_app_send_data_task(void *arg) if (frame_data_num == 0) { continue; } - buf = osi_malloc(frame_data_num); + buf = (uint8_t *)malloc(frame_data_num); if (!buf) { ESP_LOGE(BT_HF_TAG, "%s, no mem", __FUNCTION__); continue; @@ -241,7 +240,7 @@ static void bt_app_send_data_task(void *arg) if (!done) { ESP_LOGE(BT_HF_TAG, "rb send fail"); } - osi_free(buf); + free(buf); vRingbufferGetInfo(s_m_rb, NULL, NULL, NULL, NULL, &item_size); if(s_audio_code == ESP_HF_AUDIO_STATE_CONNECTED_MSBC) { diff --git a/examples/bluetooth/bluedroid/classic_bt/pytest_classic_bt_test.py b/examples/bluetooth/bluedroid/classic_bt/pytest_classic_bt_test.py index 07e1e27f316b..a3f7e59f6899 100644 --- a/examples/bluetooth/bluedroid/classic_bt/pytest_classic_bt_test.py +++ b/examples/bluetooth/bluedroid/classic_bt/pytest_classic_bt_test.py @@ -1,4 +1,4 @@ -# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 import os.path from typing import Tuple @@ -10,7 +10,7 @@ # Case 1: SPP @pytest.mark.esp32 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count, app_path, target, erase_all, config', [ (2, @@ -40,7 +40,7 @@ def test_bt_spp_only(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: # Case 2: SPP_VFS @pytest.mark.esp32 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count, app_path, target, config', [ (2, @@ -65,7 +65,7 @@ def test_bt_spp_vfs(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: # Case 3: A2DP @pytest.mark.esp32 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count, app_path, target, config', [ (2, @@ -88,7 +88,7 @@ def test_bt_a2dp(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: # Case 4: HFP @pytest.mark.esp32 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count, app_path, target, config', [ (2, @@ -110,7 +110,7 @@ def test_bt_hfp(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: # # Case 5: HID @pytest.mark.esp32 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count, app_path, target, config', [ (2, @@ -136,7 +136,7 @@ def test_bt_hid(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: # Case 6: L2CAP @pytest.mark.esp32 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count, app_path, target, config', [ (2, @@ -150,8 +150,11 @@ def test_bt_l2cap(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: client = dut[1] server.expect_exact('ESP_BT_L2CAP_INIT_EVT: status:0', timeout=30) - server.expect_exact('ESP_BT_L2CAP_START_EVT: status:0', timeout=30) - server.expect_exact('ESP_SDP_CREATE_RECORD_COMP_EVT: status:0', timeout=30) + server.expect( + r'(?s)(ESP_BT_L2CAP_START_EVT: status:0.*ESP_SDP_CREATE_RECORD_COMP_EVT: status:0|' + r'ESP_SDP_CREATE_RECORD_COMP_EVT: status:0.*ESP_BT_L2CAP_START_EVT: status:0)', + timeout=30, + ) client.expect_exact('ESP_BT_L2CAP_INIT_EVT: status:0', timeout=30) client.expect_exact('ESP_SDP_SEARCH_COMP_EVT: status:0', timeout=30) client.expect_exact('ESP_BT_L2CAP_OPEN_EVT: status:0', timeout=30) diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/main/main.c b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/main/main.c index 6b816d6d846f..dcfdab25ae20 100644 --- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/main/main.c +++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/main/main.c @@ -2,7 +2,7 @@ /* * SPDX-FileCopyrightText: 2017 Intel Corporation - * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -353,26 +353,22 @@ static void example_ble_mesh_parse_node_comp_data(esp_ble_mesh_node_info_t* node node->sig_model_num = (uint8_t *)calloc(node->elem_num, sizeof(uint8_t)); if (!node->sig_model_num) { - ESP_LOGW(TAG, "No Free memory to store composition data"); - return; + goto calloc_fail; } node->vnd_model_num = (uint8_t *)calloc(node->elem_num, sizeof(uint8_t)); if (!node->vnd_model_num) { - ESP_LOGW(TAG, "No Free memory to store composition data"); - return; + goto vnd_model_num_fail; } node->sig_models = (uint16_t **)calloc(node->elem_num, sizeof(uint16_t*)); if (!node->sig_models) { - ESP_LOGW(TAG, "No Free memory to store composition data"); - return; + goto sig_models_fail; } node->vnd_models = (uint32_t **)calloc(node->elem_num, sizeof(uint32_t*)); - if (!node->sig_models) { - ESP_LOGW(TAG, "No Free memory to store composition data"); - return; + if (!node->vnd_models) { + goto vnd_models_fail; } ESP_LOGI(TAG, "********************** Composition Data Start **********************"); @@ -387,8 +383,7 @@ static void example_ble_mesh_parse_node_comp_data(esp_ble_mesh_node_info_t* node if (nums) { node->sig_models[seq] = (uint16_t *)calloc(nums, sizeof(uint16_t)); if (!(node->sig_models[seq])) { - ESP_LOGW(TAG, "No Free memory to store composition data"); - return; + goto sig_mode_seq_fail; } } else { node->sig_models[seq] = NULL; @@ -397,8 +392,7 @@ static void example_ble_mesh_parse_node_comp_data(esp_ble_mesh_node_info_t* node if (numv) { node->vnd_models[seq] = (uint32_t *)calloc(numv, sizeof(uint32_t)); if (!(node->vnd_models[seq])) { - ESP_LOGW(TAG, "No Free memory to store composition data"); - return; + goto vnd_model_seq_fail; } } else { node->vnd_models[seq] = NULL; @@ -422,6 +416,32 @@ static void example_ble_mesh_parse_node_comp_data(esp_ble_mesh_node_info_t* node seq++; } ESP_LOGI(TAG, "*********************** Composition Data End ***********************"); + return; + +vnd_model_seq_fail: + free(node->sig_models[seq]); + node->sig_models[seq] = NULL; +sig_mode_seq_fail: + for (int j = 0; j < seq; j++) { + free(node->sig_models[j]); + free(node->vnd_models[j]); + node->sig_models[j] = NULL; + node->vnd_models[j] = NULL; + } + free(node->vnd_models); + node->vnd_models = NULL; +vnd_models_fail: + free(node->sig_models); + node->sig_models = NULL; +sig_models_fail: + free(node->vnd_model_num); + node->vnd_model_num = NULL; +vnd_model_num_fail: + free(node->sig_model_num); + node->sig_model_num = NULL; +calloc_fail: + ESP_LOGW(TAG, "No Free memory to store composition data"); + return; } static bool example_ble_mesh_query_element_have_model(uint16_t elem_addr, uint16_t model_id, uint16_t company_id) @@ -435,6 +455,10 @@ static bool example_ble_mesh_query_element_have_model(uint16_t elem_addr, uint16 elem_idx = elem_addr - node->unicast; + if (node->sig_model_num == NULL) { + return false; + } + if (company_id == CID_NVAL) { model_num = node->sig_model_num[elem_idx]; for (i = 0; i < model_num; i++) { diff --git a/examples/bluetooth/nimble/pytest_nimble_test.py b/examples/bluetooth/nimble/pytest_nimble_test.py index cb479c771ac1..ae336a928155 100644 --- a/examples/bluetooth/nimble/pytest_nimble_test.py +++ b/examples/bluetooth/nimble/pytest_nimble_test.py @@ -16,7 +16,7 @@ @pytest.mark.esp32c5 @pytest.mark.esp32c61 @pytest.mark.esp32 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count, app_path', [ (2, @@ -40,7 +40,7 @@ def test_power_save_conn(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None: # Case 2: BLE power save test for ESP32C2 @pytest.mark.esp32c2 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.xtal_26mhz @pytest.mark.parametrize( 'config, count, app_path, baud', [ @@ -65,7 +65,7 @@ def test_power_save_conn_esp32c2_26mhz(dut: Tuple[IdfDut, IdfDut]) -> None: # Case 2: BLE power save test for ESP32C2ECO4 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.xtal_26mhz @pytest.mark.esp32c2eco4 @pytest.mark.parametrize( @@ -96,7 +96,7 @@ def test_power_save_conn_esp32c2eco4(dut: Tuple[IdfDut, IdfDut]) -> None: # Case 2: BLE power save test for ESP32C3ECO7 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.esp32c3eco7 @pytest.mark.parametrize( 'config, count, target, app_path', diff --git a/examples/network/bridge/pytest_example_bridge.py b/examples/network/bridge/pytest_example_bridge.py index 09b94ce51361..073d4e9a7218 100644 --- a/examples/network/bridge/pytest_example_bridge.py +++ b/examples/network/bridge/pytest_example_bridge.py @@ -1,4 +1,4 @@ -# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 import base64 import io @@ -55,7 +55,7 @@ def exec_cmd(self, cmd: str) -> str: error = stderr.read().decode().strip() if error: out = '' - logging.error('ssh_endnode_exec error: {}'.format(error)) + logging.error(f'ssh_endnode_exec error: {error}') return out # type: ignore @@ -101,7 +101,7 @@ def exec_cmd(self, cmd: Union[str, List[str]]) -> str: error = stderr.read().decode().strip() if error != 'TSW Init OK!': - raise Exception('switch_5xp exec_cmd error: {}'.format(error)) + raise Exception(f'switch_5xp exec_cmd error: {error}') else: out = self.ssh_client.send_config_set(cmd, cmd_verify=False, exit_config_mode=False) return out # type: ignore @@ -158,7 +158,7 @@ def get_host_interface_name_in_same_net(ip_addr: str) -> str: def get_host_mac_by_interface(interface_name: str, addr_type: int = netifaces.AF_LINK) -> str: for _addr in netifaces.ifaddresses(interface_name)[addr_type]: - host_mac = _addr['addr'].replace('%{}'.format(interface_name), '') + host_mac = _addr['addr'].replace(f'%{interface_name}', '') assert isinstance(host_mac, str) return host_mac return '' @@ -166,7 +166,7 @@ def get_host_mac_by_interface(interface_name: str, addr_type: int = netifaces.AF def get_host_brcast_ip_by_interface(interface_name: str, ip_type: int = netifaces.AF_INET) -> str: for _addr in netifaces.ifaddresses(interface_name)[ip_type]: - host_ip = _addr['broadcast'].replace('%{}'.format(interface_name), '') + host_ip = _addr['broadcast'].replace(f'%{interface_name}', '') assert isinstance(host_ip, str) return host_ip return '' @@ -180,21 +180,31 @@ def run_iperf(proto: str, endnode: EndnodeSsh, server_ip: str, bandwidth_lim:int if ipaddress.ip_address(server_ip).is_multicast: # Configure Multicast Server - server_proc = subprocess.Popen(['iperf', '-u', '-s', '-i', '1', '-t', '%i' % interval, '-B', '%s%%%s' - % (server_ip, server_if)], text=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE) + server_proc = subprocess.Popen( + ['iperf', '-u', '-s', '-i', '1', '-t', str(interval), '-B', f'{server_ip}%{server_if}'], + text=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + ) # Configure Multicast Client endnode_ip = get_endnode_ip_by_interface(endnode, client_if) if endnode_ip == '': raise RuntimeError('End node IP address not found') - client_res = endnode.exec_cmd('iperf -u -c %s -t %i -i 1 -b %iM --ttl 5 -B %s' % (server_ip, interval, bandwidth_lim, endnode_ip)) + client_res = endnode.exec_cmd( + f'iperf -u -c {server_ip} -t {interval} -i 1 -b {bandwidth_lim}M --ttl 5 -B {endnode_ip}' + ) if server_proc.wait(10) is None: # Process did not finish. server_proc.terminate() else: # Configure Server - server_proc = subprocess.Popen(['iperf', '%s' % proto, '-s', '-i', '1', '-t', '%i' % interval], text=True, - stdout=subprocess.PIPE, stderr=subprocess.PIPE) + server_proc = subprocess.Popen( + ['iperf', proto, '-s', '-i', '1', '-t', str(interval)], + text=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + ) # Configure Client - client_res = endnode.exec_cmd('iperf %s -c %s -t %i -i 1 -b %iM' % (proto, server_ip, interval, bandwidth_lim)) + client_res = endnode.exec_cmd(f'iperf {proto} -c {server_ip} -t {interval} -i 1 -b {bandwidth_lim}M') if server_proc.wait(10) is None: # Process did not finish. server_proc.terminate() @@ -224,8 +234,8 @@ def send_brcast_msg_host_to_endnode(endnode: EndnodeSsh, host_brcast_ip: str, te try: sock.setsockopt(socket.SOL_SOCKET, socket.SO_BROADCAST, 1) sock.sendto(test_msg.encode('utf-8'), (host_brcast_ip, 5100)) - except socket.error as e: - raise Exception('Host brcast send failed %s' % e) + except OSError as e: + raise Exception(f'Host brcast send failed {e}') nc_endnode_out = endnode.get_async_res() sock.close() @@ -234,18 +244,24 @@ def send_brcast_msg_host_to_endnode(endnode: EndnodeSsh, host_brcast_ip: str, te def send_brcast_msg_endnode_to_host(endnode: EndnodeSsh, host_brcast_ip: str, test_msg: str) -> str: sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) + sock.setsockopt(socket.SOL_SOCKET, socket.SO_REUSEADDR, 1) # Allow binding if port still in TIME_WAIT sock.settimeout(5) try: sock.bind(('', 5100)) - except socket.error as e: - raise Exception('Host bind failed %s' % e) + # Give socket time to be fully ready to receive before we tell endnode to send. + # Even with SSH latency, there's a small window where a fast-received packet could be dropped. + time.sleep(0.1) + except OSError as e: + raise Exception(f'Host bind failed {e}') - endnode.exec_cmd('echo -n "%s" | nc -b -w0 -u %s 5100' % (test_msg, host_brcast_ip)) + endnode.exec_cmd(f'echo -n "{test_msg}" | nc -b -w0 -u {host_brcast_ip} 5100') try: nc_host_out = sock.recv(1500).decode('utf-8') - except socket.error as e: - raise Exception('Host recv failed %s', e) + except TimeoutError: + raise Exception('Host recv timed out after 5 seconds') + except OSError as e: + raise Exception(f'Host recv failed {e}') sock.close() return nc_host_out @@ -408,11 +424,17 @@ def test_esp_eth_bridge( logging.info('Multicast UDP average bandwidth: %s Mbits/s', bandwidth_mcast_udp) if bandwidth_udp < MIN_UDP_THROUGHPUT: - raise RuntimeError('Unicast UDP throughput expected %.2f, actual %.2f' % (MIN_UDP_THROUGHPUT, bandwidth_udp) + ' Mbits/s') + raise RuntimeError( + f'Unicast UDP throughput expected {MIN_UDP_THROUGHPUT:.2f}, actual {bandwidth_udp:.2f} Mbits/s' + ) if bandwidth_tcp < MIN_TCP_THROUGHPUT: - raise RuntimeError('Unicast TCP throughput expected %.2f, actual %.2f' % (MIN_TCP_THROUGHPUT, bandwidth_tcp) + ' Mbits/s') + raise RuntimeError( + f'Unicast TCP throughput expected {MIN_TCP_THROUGHPUT:.2f}, actual {bandwidth_tcp:.2f} Mbits/s' + ) if bandwidth_mcast_udp < MIN_UDP_THROUGHPUT: - raise RuntimeError('Multicast UDP throughput expected %.2f, actual %.2f' % (MIN_UDP_THROUGHPUT, bandwidth_mcast_udp) + ' Mbits/s') + raise RuntimeError( + f'Multicast UDP throughput expected {MIN_UDP_THROUGHPUT:.2f}, actual {bandwidth_mcast_udp:.2f} Mbits/s' + ) # ------------------------------------------------ # TEST Objective 4: adding/deleting entries in FDB @@ -465,7 +487,7 @@ def test_esp_eth_bridge( # try to add more FDB entries than configured max number for i in range(BR_PORTS_NUM + 1): - dut.write('add --addr=01:02:03:00:00:%02x' % i + ' -d') + dut.write(f'add --addr=01:02:03:00:00:{i:02x} -d') if i < BR_PORTS_NUM: dut.expect_exact('Bridge Config OK!') else: @@ -479,7 +501,7 @@ def test_esp_eth_bridge( # remove dummy entries for i in range(BR_PORTS_NUM): - dut.write('remove --addr=01:02:03:00:00:%02x' % i) + dut.write(f'remove --addr=01:02:03:00:00:{i:02x}') dut.expect_exact('Bridge Config OK!') # valid multiple ports at once diff --git a/examples/openthread/ot_ci_function.py b/examples/openthread/ot_ci_function.py index bc32af980cb7..25fd9cd556f1 100644 --- a/examples/openthread/ot_ci_function.py +++ b/examples/openthread/ot_ci_function.py @@ -141,11 +141,15 @@ def joinThreadNetwork(dut: IdfDut, thread: thread_parameter) -> None: def wait_for_join(dut: IdfDut, role: str) -> bool: + clean_buffer(dut) for _ in range(1, 30): - if getDeviceRole(dut) == role: - wait(dut, 5) + time.sleep(1) + execute_command(dut, 'state') + try: + dut.expect(re.compile(role), timeout=5) return True - wait(dut, 1) + except Exception: + continue return False diff --git a/examples/openthread/pytest_otbr.py b/examples/openthread/pytest_otbr.py index 670f6bd8eed1..1de1ccee26ec 100644 --- a/examples/openthread/pytest_otbr.py +++ b/examples/openthread/pytest_otbr.py @@ -234,11 +234,14 @@ def test_Bidirectional_IPv6_connectivity(Init_interface: bool, dut: Tuple[IdfDut onlinkprefix = ocf.get_onlinkprefix(br) pattern = rf'\W+({onlinkprefix}(?:\w+:){{3}}\w+)\W+' host_global_unicast_addr = re.findall(pattern, out_str) + logging.info(f'host_global_unicast_addr: {host_global_unicast_addr}') + if host_global_unicast_addr is None: + raise Exception(f'onlinkprefix: {onlinkprefix}, host_global_unicast_addr: {host_global_unicast_addr}') rx_nums = 0 for ip_addr in host_global_unicast_addr: txrx_nums = ocf.ot_ping(cli, str(ip_addr), count=10) rx_nums = rx_nums + int(txrx_nums[1]) - logging.debug(f'rx_nums: {rx_nums}') + logging.info(f'rx_nums: {rx_nums}') assert rx_nums != 0 finally: ocf.stop_thread(cli) diff --git a/examples/peripherals/isp/multi_pipelines/README.md b/examples/peripherals/isp/multi_pipelines/README.md index 840176ea5c11..e8fa72ba54a7 100644 --- a/examples/peripherals/isp/multi_pipelines/README.md +++ b/examples/peripherals/isp/multi_pipelines/README.md @@ -10,6 +10,7 @@ This example demonstrates how to use the ISP (image signal processor) to work wi - ISP AF (auto-focus) feature - ISP BF (bayer denoise) feature +- ISP BLC (black level correction) feature - ISP Sharpen feature - ISP Demosaic feature - ISP GAMMA feature diff --git a/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c b/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c index 018f522d6174..79ac25707403 100644 --- a/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c +++ b/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c @@ -303,6 +303,49 @@ void app_main(void) ESP_ERROR_CHECK(esp_isp_bf_configure(isp_proc, &bf_config)); ESP_ERROR_CHECK(esp_isp_bf_enable(isp_proc)); +#if CONFIG_ESP32P4_REV_MIN_FULL >= 300 + /** + * This piece of BLC code is to show how to use the BLC related APIs. + * Suggested way to calibrate the BLC is by covering the lens and record the raw data. + * Then, use the recorded data to calibrate the BLC. + */ + esp_isp_blc_config_t blc_config = { + .window = { + .top_left = { + .x = 0, + .y = 0, + }, + .btm_right = { + .x = CONFIG_EXAMPLE_MIPI_CSI_DISP_HRES, + .y = CONFIG_EXAMPLE_MIPI_CSI_DISP_VRES, + }, + }, + .filter_enable = true, + .filter_threshold = { + .top_left_chan_thresh = 128, + .top_right_chan_thresh = 128, + .bottom_left_chan_thresh = 128, + .bottom_right_chan_thresh = 128, + }, + .stretch = { + .top_left_chan_stretch_en = true, + .top_right_chan_stretch_en = true, + .bottom_left_chan_stretch_en = true, + .bottom_right_chan_stretch_en = true, + }, + }; + ESP_ERROR_CHECK(esp_isp_blc_configure(isp_proc, &blc_config)); + ESP_ERROR_CHECK(esp_isp_blc_enable(isp_proc)); + + esp_isp_blc_offset_t blc_offset = { + .top_left_chan_offset = 20, + .top_right_chan_offset = 20, + .bottom_left_chan_offset = 20, + .bottom_right_chan_offset = 20, + }; + ESP_ERROR_CHECK(esp_isp_blc_set_correction_offset(isp_proc, &blc_offset)); +#endif + esp_isp_demosaic_config_t demosaic_config = { .grad_ratio = { .integer = 2, diff --git a/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c b/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c index c3ce8d240f80..60ba69b059ff 100644 --- a/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c +++ b/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c @@ -19,7 +19,7 @@ #define LEDC_FREQUENCY (4000) // Frequency in Hertz. Set frequency at 4 kHz /* Warning: - * For ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4 targets, + * For ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4 (rev < 3.0) targets, * when LEDC_DUTY_RES selects the maximum duty resolution (i.e. value equal to SOC_LEDC_TIMER_BIT_WIDTH), * 100% duty cycle is not reachable (duty cannot be set to (2 ** SOC_LEDC_TIMER_BIT_WIDTH)). */ diff --git a/examples/system/light_sleep/main/uart_wakeup.c b/examples/system/light_sleep/main/uart_wakeup.c index a5753b43d678..40da34ded6bb 100644 --- a/examples/system/light_sleep/main/uart_wakeup.c +++ b/examples/system/light_sleep/main/uart_wakeup.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -12,12 +12,18 @@ #include "driver/gpio.h" #include "sdkconfig.h" -#define EXAMPLE_UART_NUM 0 +#define EXAMPLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM /* Notice that ESP32 has to use the iomux input to configure uart as wakeup source * Please use 'UxRXD_GPIO_NUM' as uart rx pin. No limitation to the other target */ #define EXAMPLE_UART_TX_IO_NUM U0TXD_GPIO_NUM #define EXAMPLE_UART_RX_IO_NUM U0RXD_GPIO_NUM +#if CONFIG_ESP_CONSOLE_UART +#define EXAMPLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE +#else +#define EXAMPLE_UART_BAUDRATE 115200 +#endif + #define EXAMPLE_UART_WAKEUP_THRESHOLD 3 #define EXAMPLE_READ_BUF_SIZE 1024 @@ -97,7 +103,7 @@ static void uart_wakeup_task(void *arg) static esp_err_t uart_initialization(void) { uart_config_t uart_cfg = { - .baud_rate = CONFIG_ESP_CONSOLE_UART_BAUDRATE, + .baud_rate = EXAMPLE_UART_BAUDRATE, .data_bits = UART_DATA_8_BITS, .parity = UART_PARITY_DISABLE, .stop_bits = UART_STOP_BITS_1, diff --git a/examples/wifi/getting_started/pytest_wifi_getting_started.py b/examples/wifi/getting_started/pytest_wifi_getting_started.py index 3b4c0259b53c..3ce6e5d655a6 100644 --- a/examples/wifi/getting_started/pytest_wifi_getting_started.py +++ b/examples/wifi/getting_started/pytest_wifi_getting_started.py @@ -27,7 +27,7 @@ @pytest.mark.esp32c5 @pytest.mark.esp32c6 @pytest.mark.esp32c61 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize( 'count, app_path', [ (2, @@ -50,7 +50,7 @@ def test_wifi_getting_started(dut: Tuple[IdfDut, IdfDut]) -> None: @pytest.mark.esp32c2 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.xtal_26mhz @pytest.mark.parametrize( 'count, config, baud, app_path', [ @@ -74,7 +74,7 @@ def test_wifi_getting_started_esp32c2_xtal_26mhz(dut: Tuple[IdfDut, IdfDut]) -> softap.expect('station .+ join, AID=', timeout=60) -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.xtal_26mhz @pytest.mark.esp32c2eco4 @pytest.mark.parametrize( @@ -106,7 +106,7 @@ def test_wifi_getting_started_esp32c2eco4_xtal_26mhz(dut: Tuple[IdfDut, IdfDut]) softap.expect('station .+ join, AID=', timeout=60) -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.esp32c3eco7 @pytest.mark.parametrize( 'count, config, target, app_path', diff --git a/examples/wifi/getting_started/softAP/sdkconfig.ci b/examples/wifi/getting_started/softAP/sdkconfig.ci index b416e9f87cbb..9633644b4669 100644 --- a/examples/wifi/getting_started/softAP/sdkconfig.ci +++ b/examples/wifi/getting_started/softAP/sdkconfig.ci @@ -1,2 +1,3 @@ +# build xxx_default CONFIG_ESP_WIFI_SSID="ssid_${IDF_TARGET}_${CI_PIPELINE_ID}" CONFIG_ESP_WIFI_PASSWORD="password_${IDF_TARGET}_${CI_PIPELINE_ID}" diff --git a/examples/wifi/getting_started/softAP/sdkconfig.ci.c3eco7 b/examples/wifi/getting_started/softAP/sdkconfig.ci.c3eco7 index ad055155c9bf..badfbca2bde0 100644 --- a/examples/wifi/getting_started/softAP/sdkconfig.ci.c3eco7 +++ b/examples/wifi/getting_started/softAP/sdkconfig.ci.c3eco7 @@ -1,2 +1,4 @@ CONFIG_IDF_TARGET="esp32c3" CONFIG_ESP32C3_REV_MIN_101=y +CONFIG_ESP_WIFI_SSID="ssid_${IDF_TARGET}_${CI_PIPELINE_ID}" +CONFIG_ESP_WIFI_PASSWORD="password_${IDF_TARGET}_${CI_PIPELINE_ID}" diff --git a/examples/wifi/getting_started/softAP/sdkconfig.ci.esp32c2_xtal26m b/examples/wifi/getting_started/softAP/sdkconfig.ci.esp32c2_xtal26m index 172f022b67ea..814241b72fcf 100644 --- a/examples/wifi/getting_started/softAP/sdkconfig.ci.esp32c2_xtal26m +++ b/examples/wifi/getting_started/softAP/sdkconfig.ci.esp32c2_xtal26m @@ -1,2 +1,4 @@ CONFIG_IDF_TARGET="esp32c2" CONFIG_XTAL_FREQ_26=y +CONFIG_ESP_WIFI_SSID="ssid_${IDF_TARGET}_${CI_PIPELINE_ID}" +CONFIG_ESP_WIFI_PASSWORD="password_${IDF_TARGET}_${CI_PIPELINE_ID}" diff --git a/examples/wifi/getting_started/softAP/sdkconfig.ci.esp32c2eco4_xtal26m b/examples/wifi/getting_started/softAP/sdkconfig.ci.esp32c2eco4_xtal26m index 651a6cc578b7..db99cc188f5c 100644 --- a/examples/wifi/getting_started/softAP/sdkconfig.ci.esp32c2eco4_xtal26m +++ b/examples/wifi/getting_started/softAP/sdkconfig.ci.esp32c2eco4_xtal26m @@ -1,3 +1,5 @@ CONFIG_IDF_TARGET="esp32c2" CONFIG_XTAL_FREQ_26=y CONFIG_ESP32C2_REV_MIN_200=y +CONFIG_ESP_WIFI_SSID="ssid_${IDF_TARGET}_${CI_PIPELINE_ID}" +CONFIG_ESP_WIFI_PASSWORD="password_${IDF_TARGET}_${CI_PIPELINE_ID}" diff --git a/examples/wifi/getting_started/softAP/sdkconfig.ci.wpa_psk b/examples/wifi/getting_started/softAP/sdkconfig.ci.wpa_psk index 4fee0b0352a3..240bb635e6a3 100644 --- a/examples/wifi/getting_started/softAP/sdkconfig.ci.wpa_psk +++ b/examples/wifi/getting_started/softAP/sdkconfig.ci.wpa_psk @@ -1 +1,3 @@ CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=n +CONFIG_ESP_WIFI_SSID="ssid_${IDF_TARGET}_${CI_PIPELINE_ID}" +CONFIG_ESP_WIFI_PASSWORD="password_${IDF_TARGET}_${CI_PIPELINE_ID}" diff --git a/examples/wifi/getting_started/station/sdkconfig.ci b/examples/wifi/getting_started/station/sdkconfig.ci index b416e9f87cbb..9633644b4669 100644 --- a/examples/wifi/getting_started/station/sdkconfig.ci +++ b/examples/wifi/getting_started/station/sdkconfig.ci @@ -1,2 +1,3 @@ +# build xxx_default CONFIG_ESP_WIFI_SSID="ssid_${IDF_TARGET}_${CI_PIPELINE_ID}" CONFIG_ESP_WIFI_PASSWORD="password_${IDF_TARGET}_${CI_PIPELINE_ID}" diff --git a/examples/wifi/getting_started/station/sdkconfig.ci.c3eco7 b/examples/wifi/getting_started/station/sdkconfig.ci.c3eco7 index ad055155c9bf..badfbca2bde0 100644 --- a/examples/wifi/getting_started/station/sdkconfig.ci.c3eco7 +++ b/examples/wifi/getting_started/station/sdkconfig.ci.c3eco7 @@ -1,2 +1,4 @@ CONFIG_IDF_TARGET="esp32c3" CONFIG_ESP32C3_REV_MIN_101=y +CONFIG_ESP_WIFI_SSID="ssid_${IDF_TARGET}_${CI_PIPELINE_ID}" +CONFIG_ESP_WIFI_PASSWORD="password_${IDF_TARGET}_${CI_PIPELINE_ID}" diff --git a/examples/wifi/getting_started/station/sdkconfig.ci.esp32c2_xtal26m b/examples/wifi/getting_started/station/sdkconfig.ci.esp32c2_xtal26m index 172f022b67ea..814241b72fcf 100644 --- a/examples/wifi/getting_started/station/sdkconfig.ci.esp32c2_xtal26m +++ b/examples/wifi/getting_started/station/sdkconfig.ci.esp32c2_xtal26m @@ -1,2 +1,4 @@ CONFIG_IDF_TARGET="esp32c2" CONFIG_XTAL_FREQ_26=y +CONFIG_ESP_WIFI_SSID="ssid_${IDF_TARGET}_${CI_PIPELINE_ID}" +CONFIG_ESP_WIFI_PASSWORD="password_${IDF_TARGET}_${CI_PIPELINE_ID}" diff --git a/examples/wifi/getting_started/station/sdkconfig.ci.esp32c2eco4_xtal26m b/examples/wifi/getting_started/station/sdkconfig.ci.esp32c2eco4_xtal26m index 651a6cc578b7..db99cc188f5c 100644 --- a/examples/wifi/getting_started/station/sdkconfig.ci.esp32c2eco4_xtal26m +++ b/examples/wifi/getting_started/station/sdkconfig.ci.esp32c2eco4_xtal26m @@ -1,3 +1,5 @@ CONFIG_IDF_TARGET="esp32c2" CONFIG_XTAL_FREQ_26=y CONFIG_ESP32C2_REV_MIN_200=y +CONFIG_ESP_WIFI_SSID="ssid_${IDF_TARGET}_${CI_PIPELINE_ID}" +CONFIG_ESP_WIFI_PASSWORD="password_${IDF_TARGET}_${CI_PIPELINE_ID}" diff --git a/examples/wifi/getting_started/station/sdkconfig.ci.ft b/examples/wifi/getting_started/station/sdkconfig.ci.ft index 10169bbff279..83cd86bfbeb2 100644 --- a/examples/wifi/getting_started/station/sdkconfig.ci.ft +++ b/examples/wifi/getting_started/station/sdkconfig.ci.ft @@ -1 +1,3 @@ CONFIG_ESP_WIFI_11R_SUPPORT=y +CONFIG_ESP_WIFI_SSID="ssid_${IDF_TARGET}_${CI_PIPELINE_ID}" +CONFIG_ESP_WIFI_PASSWORD="password_${IDF_TARGET}_${CI_PIPELINE_ID}" diff --git a/examples/wifi/getting_started/station/sdkconfig.ci.rrm b/examples/wifi/getting_started/station/sdkconfig.ci.rrm index 61c172f52369..a7a05f2a17cb 100644 --- a/examples/wifi/getting_started/station/sdkconfig.ci.rrm +++ b/examples/wifi/getting_started/station/sdkconfig.ci.rrm @@ -1,2 +1,4 @@ CONFIG_ESP_WIFI_11KV_SUPPORT=y CONFIG_ESP_WIFI_RRM_SUPPORT=y +CONFIG_ESP_WIFI_SSID="ssid_${IDF_TARGET}_${CI_PIPELINE_ID}" +CONFIG_ESP_WIFI_PASSWORD="password_${IDF_TARGET}_${CI_PIPELINE_ID}" diff --git a/examples/wifi/getting_started/station/sdkconfig.ci.wnm b/examples/wifi/getting_started/station/sdkconfig.ci.wnm index 9f87bf640e19..91c8f2d58762 100644 --- a/examples/wifi/getting_started/station/sdkconfig.ci.wnm +++ b/examples/wifi/getting_started/station/sdkconfig.ci.wnm @@ -1,2 +1,4 @@ CONFIG_ESP_WIFI_11KV_SUPPORT=y CONFIG_ESP_WIFI_WNM_SUPPORT=y +CONFIG_ESP_WIFI_SSID="ssid_${IDF_TARGET}_${CI_PIPELINE_ID}" +CONFIG_ESP_WIFI_PASSWORD="password_${IDF_TARGET}_${CI_PIPELINE_ID}" diff --git a/examples/wifi/getting_started/station/sdkconfig.ci.wpa_psk b/examples/wifi/getting_started/station/sdkconfig.ci.wpa_psk index bc969e6b4de1..af2ee3f36aaf 100644 --- a/examples/wifi/getting_started/station/sdkconfig.ci.wpa_psk +++ b/examples/wifi/getting_started/station/sdkconfig.ci.wpa_psk @@ -1 +1,3 @@ CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=n +CONFIG_ESP_WIFI_SSID="ssid_${IDF_TARGET}_${CI_PIPELINE_ID}" +CONFIG_ESP_WIFI_PASSWORD="password_${IDF_TARGET}_${CI_PIPELINE_ID}" diff --git a/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml b/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml index c9314a7b59f5..8e6449998e4a 100644 --- a/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml +++ b/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml @@ -23,7 +23,7 @@ no_runner_tags: - esp32c5,wifi_ap - esp32c5,wifi_router - esp32c5_2,generic_multi_device - - esp32c5_2,wifi_two_dut + - esp32c5_2,two_duts - esp32c6,jtag - esp32c61,generic - esp32c61,jtag diff --git a/tools/ci/idf_pytest/constants.py b/tools/ci/idf_pytest/constants.py index 88a66142fd35..3a0d7bdd781a 100644 --- a/tools/ci/idf_pytest/constants.py +++ b/tools/ci/idf_pytest/constants.py @@ -116,7 +116,7 @@ 'openthread_bbr': 'tests should be used for openthread border router linked to Internet.', 'openthread_sleep': 'tests should be used for openthread sleepy device.', 'zigbee_multi_dut': 'zigbee runner which have multiple duts.', - 'wifi_two_dut': 'tests should be run on runners which has two wifi duts connected.', + 'two_duts': 'tests should be run on runners which has two wifi duts connected.', 'generic_multi_device': 'generic multiple devices whose corresponding gpio pins are connected to each other.', 'twai_network': 'multiple runners form a TWAI network.', 'sdio_master_slave': 'Test sdio multi board, esp32+esp32', diff --git a/tools/ci/idf_pytest/plugin.py b/tools/ci/idf_pytest/plugin.py index 5660c8c7305a..cc29b0c798ef 100644 --- a/tools/ci/idf_pytest/plugin.py +++ b/tools/ci/idf_pytest/plugin.py @@ -326,7 +326,7 @@ def pytest_runtest_makereport(self, item: Function, call: CallInfo[None]) -> Non res.extend( [ ChildCase( - format_case_id(target, config, case.name + f' {i}', is_qemu=is_qemu), + format_case_id(target, config, case.name, is_qemu=is_qemu), self.UNITY_RESULT_MAPPINGS[case.result], ) for case in _dut.testsuite.testcases diff --git a/tools/test_apps/phy/phy_tsens/pytest_phy_tsens.py b/tools/test_apps/phy/phy_tsens/pytest_phy_tsens.py index fcf55699c6e7..98cf8de02dfe 100644 --- a/tools/test_apps/phy/phy_tsens/pytest_phy_tsens.py +++ b/tools/test_apps/phy/phy_tsens/pytest_phy_tsens.py @@ -148,7 +148,7 @@ def run_phy_tsens_test_with_light_sleep(dut: Tuple[Dut, Dut]) -> None: @pytest.mark.esp32c5 @pytest.mark.esp32s2 @pytest.mark.esp32s3 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.parametrize('count', [2], indirect=True) def test_phy_tsens_coexist(dut: Tuple[Dut, Dut]) -> None: for _dut in dut: @@ -167,7 +167,7 @@ def test_phy_tsens_coexist(dut: Tuple[Dut, Dut]) -> None: @pytest.mark.esp32c2 -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.xtal_26mhz @pytest.mark.parametrize( 'count, config, baud', @@ -192,7 +192,7 @@ def test_phy_tsens_coexist_c2_xtal26m(dut: Tuple[Dut, Dut]) -> None: run_phy_tsens_test_with_light_sleep(dut) -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.xtal_26mhz @pytest.mark.esp32c2eco4 @pytest.mark.parametrize( @@ -218,7 +218,7 @@ def test_phy_tsens_coexist_c2eco4_xtal26m(dut: Tuple[Dut, Dut]) -> None: run_phy_tsens_test_with_light_sleep(dut) -@pytest.mark.wifi_two_dut +@pytest.mark.two_duts @pytest.mark.esp32c3eco7 @pytest.mark.parametrize( 'count, config, target', diff --git a/tools/test_apps/system/g0_components/CMakeLists.txt b/tools/test_apps/system/g0_components/CMakeLists.txt index 4751f860e995..ed83187265ce 100644 --- a/tools/test_apps/system/g0_components/CMakeLists.txt +++ b/tools/test_apps/system/g0_components/CMakeLists.txt @@ -26,6 +26,10 @@ idf_build_set_property(__BUILD_COMPONENT_DEPGRAPH_ENABLED 1) project(g0_components) +if(CONFIG_IDF_TARGET_ESP32P4) + idf_build_set_property(C_COMPILE_OPTIONS "-DCONFIG_ESP_REV_MIN_FULL=300" APPEND) +endif() + if(CONFIG_IDF_TARGET_ESP32C2) # clk_tree hal-driver needs CONFIG_XTAL_FREQ idf_build_set_property(C_COMPILE_OPTIONS "-DCONFIG_XTAL_FREQ=26" APPEND) diff --git a/tools/test_idf_tools/test_idf_tools.py b/tools/test_idf_tools/test_idf_tools.py index 4966311a7763..998500ba23d0 100755 --- a/tools/test_idf_tools/test_idf_tools.py +++ b/tools/test_idf_tools/test_idf_tools.py @@ -111,7 +111,7 @@ class TestUsageBase(unittest.TestCase): @classmethod def setUpClass(cls): - with open(os.path.join(os.getenv('IDF_PATH'), 'tools/tools.json'), 'r') as json_file: + with open(os.path.join(os.getenv('IDF_PATH'), 'tools/tools.json')) as json_file: tools_dict = json.load(json_file) cls.tools_dict = tools_dict @@ -133,7 +133,7 @@ def setUpClass(cls): cls.temp_tools_dir = tempfile.mkdtemp(prefix='idf_tools_tmp') - print('Using IDF_TOOLS_PATH={}'.format(cls.temp_tools_dir)) + print(f'Using IDF_TOOLS_PATH={cls.temp_tools_dir}') os.environ['IDF_TOOLS_PATH'] = cls.temp_tools_dir cls.idf_env_json = os.path.join(cls.temp_tools_dir, 'idf-env.json') @@ -154,13 +154,13 @@ def tearDown(self): def assert_tool_installed(self, output, tool, tool_version, tool_archive_name=None): if tool_archive_name is None: tool_archive_name = tool - self.assertIn('Installing %s@' % tool + tool_version, output) + self.assertIn(f'Installing {tool}@{tool_version}', output) self.assertRegex(output, re.compile(rf'Downloading \S+{tool_archive_name}')) def assert_tool_not_installed(self, output, tool, tool_version, tool_archive_name=None): if tool_archive_name is None: tool_archive_name = tool - self.assertNotIn('Installing %s@' % tool + tool_version, output) + self.assertNotIn(f'Installing {tool}@{tool_version}', output) self.assertNotRegex(output, re.compile(rf'Downloading \S+{tool_archive_name}')) def run_idf_tools_with_action(self, action): @@ -265,8 +265,8 @@ def test_deactivate(self): output = self.run_idf_tools_with_action(['export']) self.assertIn('export IDF_DEACTIVATE_FILE_PATH=', output, 'No IDF_DEACTIVATE_FILE_PATH exported into environment') deactivate_file = re.findall(r'(?:IDF_DEACTIVATE_FILE_PATH=")(.*)(?:")', output)[0] - self.assertTrue(os.path.isfile(deactivate_file), 'File {} was not found. '.format(deactivate_file)) - self.assertNotEqual(os.stat(self.idf_env_json).st_size, 0, 'File {} is empty. '.format(deactivate_file)) + self.assertTrue(os.path.isfile(deactivate_file), f'File {deactivate_file} was not found. ') + self.assertNotEqual(os.stat(self.idf_env_json).st_size, 0, f'File {deactivate_file} is empty. ') def test_export_recommended_version(self): always_install_and_recommended_tools = [] @@ -358,14 +358,14 @@ class TestUsageUnix(TestUsage): def test_usage_basic(self): output = self.run_idf_tools_with_action(['list']) - self.assertIn('* %s:' % ESP32ULP, output) - self.assertIn('- %s (recommended)' % ESP32ULP_VERSION, output) - self.assertIn('* %s:' % OPENOCD, output) - self.assertIn('- %s (recommended)' % OPENOCD_VERSION, output) - self.assertIn('* %s:' % RISCV_ELF, output) - self.assertIn('- %s (recommended)' % RISCV_ELF_VERSION, output) - self.assertIn('* %s:' % XTENSA_ELF, output) - self.assertIn('- %s (recommended)' % XTENSA_ELF_VERSION, output) + self.assertIn(f'* {ESP32ULP}:', output) + self.assertIn(f'- {ESP32ULP_VERSION} (recommended)', output) + self.assertIn(f'* {OPENOCD}:', output) + self.assertIn(f'- {OPENOCD_VERSION} (recommended)', output) + self.assertIn(f'* {RISCV_ELF}:', output) + self.assertIn(f'- {RISCV_ELF_VERSION} (recommended)', output) + self.assertIn(f'* {XTENSA_ELF}:', output) + self.assertIn(f'- {XTENSA_ELF_VERSION} (recommended)', output) required_tools_installed = 7 output = self.run_idf_tools_with_action(['install']) @@ -385,20 +385,19 @@ def test_usage_basic(self): self.assertIn('version installed in tools directory: ' + tool_version, output) output = self.run_idf_tools_with_action(['export']) - self.assertIn('%s/tools/esp32ulp-elf/%s/esp32ulp-elf/bin' % - (self.temp_tools_dir, ESP32ULP_VERSION), output) - self.assertIn('%s/tools/xtensa-esp-elf/%s/xtensa-esp-elf/bin' % - (self.temp_tools_dir, XTENSA_ELF_VERSION), output) - self.assertIn('%s/tools/openocd-esp32/%s/openocd-esp32/bin' % - (self.temp_tools_dir, OPENOCD_VERSION), output) - self.assertIn('%s/tools/riscv32-esp-elf/%s/riscv32-esp-elf/bin' % - (self.temp_tools_dir, RISCV_ELF_VERSION), output) - self.assertIn('%s/tools/xtensa-esp-elf-gdb/%s/xtensa-esp-elf-gdb/bin' % - (self.temp_tools_dir, XTENSA_ESP_GDB_VERSION), output) - self.assertIn('%s/tools/riscv32-esp-elf-gdb/%s/riscv32-esp-elf-gdb/bin' % - (self.temp_tools_dir, RISCV_ESP_GDB_VERSION), output) - self.assertIn('%s/tools/esp-rom-elfs/%s/' % - (self.temp_tools_dir, ESP_ROM_ELFS_VERSION), output) + self.assertIn(f'{self.temp_tools_dir}/tools/esp32ulp-elf/{ESP32ULP_VERSION}/esp32ulp-elf/bin', output) + self.assertIn(f'{self.temp_tools_dir}/tools/xtensa-esp-elf/{XTENSA_ELF_VERSION}/xtensa-esp-elf/bin', output) + self.assertIn(f'{self.temp_tools_dir}/tools/openocd-esp32/{OPENOCD_VERSION}/openocd-esp32/bin', output) + self.assertIn(f'{self.temp_tools_dir}/tools/riscv32-esp-elf/{RISCV_ELF_VERSION}/riscv32-esp-elf/bin', output) + self.assertIn( + f'{self.temp_tools_dir}/tools/xtensa-esp-elf-gdb/{XTENSA_ESP_GDB_VERSION}/xtensa-esp-elf-gdb/bin', + output, + ) + self.assertIn( + f'{self.temp_tools_dir}/tools/riscv32-esp-elf-gdb/{RISCV_ESP_GDB_VERSION}/riscv32-esp-elf-gdb/bin', + output, + ) + self.assertIn(f'{self.temp_tools_dir}/tools/esp-rom-elfs/{ESP_ROM_ELFS_VERSION}/', output) output = self.run_idf_tools_with_action(['list', '--outdated']) self.assertEqual('', output) @@ -450,20 +449,19 @@ def test_tools_for_esp32(self): self.assertIn('version installed in tools directory: ' + tool_version, output) output = self.run_idf_tools_with_action(['export']) - self.assertIn('%s/tools/esp32ulp-elf/%s/esp32ulp-elf/bin' % - (self.temp_tools_dir, ESP32ULP_VERSION), output) - self.assertIn('%s/tools/xtensa-esp-elf/%s/xtensa-esp-elf/bin' % - (self.temp_tools_dir, XTENSA_ELF_VERSION), output) - self.assertIn('%s/tools/openocd-esp32/%s/openocd-esp32/bin' % - (self.temp_tools_dir, OPENOCD_VERSION), output) - self.assertIn('%s/tools/xtensa-esp-elf-gdb/%s/xtensa-esp-elf-gdb/bin' % - (self.temp_tools_dir, XTENSA_ESP_GDB_VERSION), output) - self.assertNotIn('%s/tools/riscv32-esp-elf/%s/riscv32-esp-elf/bin' % - (self.temp_tools_dir, RISCV_ELF_VERSION), output) - self.assertNotIn('%s/tools/riscv32-esp-elf-gdb/%s/riscv32-esp-elf-gdb/bin' % - (self.temp_tools_dir, RISCV_ESP_GDB_VERSION), output) - self.assertIn('%s/tools/esp-rom-elfs/%s/' % - (self.temp_tools_dir, ESP_ROM_ELFS_VERSION), output) + self.assertIn(f'{self.temp_tools_dir}/tools/esp32ulp-elf/{ESP32ULP_VERSION}/esp32ulp-elf/bin', output) + self.assertIn(f'{self.temp_tools_dir}/tools/xtensa-esp-elf/{XTENSA_ELF_VERSION}/xtensa-esp-elf/bin', output) + self.assertIn(f'{self.temp_tools_dir}/tools/openocd-esp32/{OPENOCD_VERSION}/openocd-esp32/bin', output) + self.assertIn( + f'{self.temp_tools_dir}/tools/xtensa-esp-elf-gdb/{XTENSA_ESP_GDB_VERSION}/xtensa-esp-elf-gdb/bin', + output, + ) + self.assertNotIn(f'{self.temp_tools_dir}/tools/riscv32-esp-elf/{RISCV_ELF_VERSION}/riscv32-esp-elf/bin', output) + self.assertNotIn( + f'{self.temp_tools_dir}/tools/riscv32-esp-elf-gdb/{RISCV_ESP_GDB_VERSION}/riscv32-esp-elf-gdb/bin', + output, + ) + self.assertIn(f'{self.temp_tools_dir}/tools/esp-rom-elfs/{ESP_ROM_ELFS_VERSION}/', output) def test_tools_for_esp32c3(self): required_tools_installed = 4 @@ -483,18 +481,15 @@ def test_tools_for_esp32c3(self): self.assertIn('version installed in tools directory: ' + tool_version, output) output = self.run_idf_tools_with_action(['export']) - self.assertIn('%s/tools/openocd-esp32/%s/openocd-esp32/bin' % - (self.temp_tools_dir, OPENOCD_VERSION), output) - self.assertIn('%s/tools/riscv32-esp-elf/%s/riscv32-esp-elf/bin' % - (self.temp_tools_dir, RISCV_ELF_VERSION), output) - self.assertNotIn('%s/tools/esp32ulp-elf/%s/esp32ulp-elf/bin' % - (self.temp_tools_dir, ESP32ULP_VERSION), output) - self.assertNotIn('%s/tools/xtensa-esp-elf/%s/xtensa-esp-elf/bin' % - (self.temp_tools_dir, XTENSA_ELF_VERSION), output) - self.assertNotIn('%s/tools/xtensa-esp-elf-gdb/%s/xtensa-esp-elf-gdb/bin' % - (self.temp_tools_dir, XTENSA_ESP_GDB_VERSION), output) - self.assertIn('%s/tools/esp-rom-elfs/%s/' % - (self.temp_tools_dir, ESP_ROM_ELFS_VERSION), output) + self.assertIn(f'{self.temp_tools_dir}/tools/openocd-esp32/{OPENOCD_VERSION}/openocd-esp32/bin', output) + self.assertIn(f'{self.temp_tools_dir}/tools/riscv32-esp-elf/{RISCV_ELF_VERSION}/riscv32-esp-elf/bin', output) + self.assertNotIn(f'{self.temp_tools_dir}/tools/esp32ulp-elf/{ESP32ULP_VERSION}/esp32ulp-elf/bin', output) + self.assertNotIn(f'{self.temp_tools_dir}/tools/xtensa-esp-elf/{XTENSA_ELF_VERSION}/xtensa-esp-elf/bin', output) + self.assertNotIn( + f'{self.temp_tools_dir}/tools/xtensa-esp-elf-gdb/{XTENSA_ESP_GDB_VERSION}/xtensa-esp-elf-gdb/bin', + output, + ) + self.assertIn(f'{self.temp_tools_dir}/tools/esp-rom-elfs/{ESP_ROM_ELFS_VERSION}/', output) def test_tools_for_esp32s2(self): required_tools_installed = 6 @@ -514,20 +509,19 @@ def test_tools_for_esp32s2(self): self.assertIn('version installed in tools directory: ' + tool_version, output) output = self.run_idf_tools_with_action(['export']) - self.assertIn('%s/tools/xtensa-esp-elf/%s/xtensa-esp-elf/bin' % - (self.temp_tools_dir, XTENSA_ELF_VERSION), output) - self.assertIn('%s/tools/openocd-esp32/%s/openocd-esp32/bin' % - (self.temp_tools_dir, OPENOCD_VERSION), output) - self.assertIn('%s/tools/esp32ulp-elf/%s/esp32ulp-elf/bin' % - (self.temp_tools_dir, ESP32ULP_VERSION), output) - self.assertIn('%s/tools/riscv32-esp-elf/%s/riscv32-esp-elf/bin' % - (self.temp_tools_dir, RISCV_ELF_VERSION), output) - self.assertIn('%s/tools/xtensa-esp-elf-gdb/%s/xtensa-esp-elf-gdb/bin' % - (self.temp_tools_dir, XTENSA_ESP_GDB_VERSION), output) - self.assertNotIn('%s/tools/riscv32-esp-elf-gdb/%s/riscv32-esp-elf-gdb/bin' % - (self.temp_tools_dir, RISCV_ESP_GDB_VERSION), output) - self.assertIn('%s/tools/esp-rom-elfs/%s/' % - (self.temp_tools_dir, ESP_ROM_ELFS_VERSION), output) + self.assertIn(f'{self.temp_tools_dir}/tools/xtensa-esp-elf/{XTENSA_ELF_VERSION}/xtensa-esp-elf/bin', output) + self.assertIn(f'{self.temp_tools_dir}/tools/openocd-esp32/{OPENOCD_VERSION}/openocd-esp32/bin', output) + self.assertIn(f'{self.temp_tools_dir}/tools/esp32ulp-elf/{ESP32ULP_VERSION}/esp32ulp-elf/bin', output) + self.assertIn(f'{self.temp_tools_dir}/tools/riscv32-esp-elf/{RISCV_ELF_VERSION}/riscv32-esp-elf/bin', output) + self.assertIn( + f'{self.temp_tools_dir}/tools/xtensa-esp-elf-gdb/{XTENSA_ESP_GDB_VERSION}/xtensa-esp-elf-gdb/bin', + output, + ) + self.assertNotIn( + f'{self.temp_tools_dir}/tools/riscv32-esp-elf-gdb/{RISCV_ESP_GDB_VERSION}/riscv32-esp-elf-gdb/bin', + output, + ) + self.assertIn(f'{self.temp_tools_dir}/tools/esp-rom-elfs/{ESP_ROM_ELFS_VERSION}/', output) def test_tools_for_esp32s3(self): required_tools_installed = 6 @@ -548,20 +542,19 @@ def test_tools_for_esp32s3(self): self.assertIn('version installed in tools directory: ' + tool_version, output) output = self.run_idf_tools_with_action(['export']) - self.assertIn('%s/tools/openocd-esp32/%s/openocd-esp32/bin' % - (self.temp_tools_dir, OPENOCD_VERSION), output) - self.assertIn('%s/tools/xtensa-esp-elf/%s/xtensa-esp-elf/bin' % - (self.temp_tools_dir, XTENSA_ELF_VERSION), output) - self.assertIn('%s/tools/esp32ulp-elf/%s/esp32ulp-elf/bin' % - (self.temp_tools_dir, ESP32ULP_VERSION), output) - self.assertIn('%s/tools/riscv32-esp-elf/%s/riscv32-esp-elf/bin' % - (self.temp_tools_dir, RISCV_ELF_VERSION), output) - self.assertIn('%s/tools/xtensa-esp-elf-gdb/%s/xtensa-esp-elf-gdb/bin' % - (self.temp_tools_dir, XTENSA_ESP_GDB_VERSION), output) - self.assertNotIn('%s/tools/riscv32-esp-elf-gdb/%s/riscv32-esp-elf-gdb/bin' % - (self.temp_tools_dir, RISCV_ESP_GDB_VERSION), output) - self.assertIn('%s/tools/esp-rom-elfs/%s/' % - (self.temp_tools_dir, ESP_ROM_ELFS_VERSION), output) + self.assertIn(f'{self.temp_tools_dir}/tools/openocd-esp32/{OPENOCD_VERSION}/openocd-esp32/bin', output) + self.assertIn(f'{self.temp_tools_dir}/tools/xtensa-esp-elf/{XTENSA_ELF_VERSION}/xtensa-esp-elf/bin', output) + self.assertIn(f'{self.temp_tools_dir}/tools/esp32ulp-elf/{ESP32ULP_VERSION}/esp32ulp-elf/bin', output) + self.assertIn(f'{self.temp_tools_dir}/tools/riscv32-esp-elf/{RISCV_ELF_VERSION}/riscv32-esp-elf/bin', output) + self.assertIn( + f'{self.temp_tools_dir}/tools/xtensa-esp-elf-gdb/{XTENSA_ESP_GDB_VERSION}/xtensa-esp-elf-gdb/bin', + output, + ) + self.assertNotIn( + f'{self.temp_tools_dir}/tools/riscv32-esp-elf-gdb/{RISCV_ESP_GDB_VERSION}/riscv32-esp-elf-gdb/bin', + output, + ) + self.assertIn(f'{self.temp_tools_dir}/tools/esp-rom-elfs/{ESP_ROM_ELFS_VERSION}/', output) def test_tools_for_esp32p4(self): required_tools_installed = 4 @@ -618,14 +611,14 @@ class TestUsageWin(TestUsage): def test_usage_basic_win(self): output = self.run_idf_tools_with_action(['list']) - self.assertIn('* %s:' % ESP32ULP, output) - self.assertIn('- %s (recommended)' % ESP32ULP_VERSION, output) - self.assertIn('* %s:' % OPENOCD, output) - self.assertIn('- %s (recommended)' % OPENOCD_VERSION, output) - self.assertIn('* %s:' % RISCV_ELF, output) - self.assertIn('- %s (recommended)' % RISCV_ELF_VERSION, output) - self.assertIn('* %s:' % XTENSA_ELF, output) - self.assertIn('- %s (recommended)' % XTENSA_ELF_VERSION, output) + self.assertIn(f'* {ESP32ULP}:', output) + self.assertIn(f'- {ESP32ULP_VERSION} (recommended)', output) + self.assertIn(f'* {OPENOCD}:', output) + self.assertIn(f'- {OPENOCD_VERSION} (recommended)', output) + self.assertIn(f'* {RISCV_ELF}:', output) + self.assertIn(f'- {RISCV_ELF_VERSION} (recommended)', output) + self.assertIn(f'* {XTENSA_ELF}:', output) + self.assertIn(f'- {XTENSA_ELF_VERSION} (recommended)', output) required_tools_installed = 12 output = self.run_idf_tools_with_action(['install']) @@ -682,7 +675,7 @@ def test_usage_basic_win(self): self.assertIn(os.path.join(self.temp_tools_dir, 'tools', NINJA, NINJA_VERSION), output) self.assertIn(os.path.join(self.temp_tools_dir, 'tools', IDF_EXE, IDF_EXE_VERSION), output) self.assertIn( - os.path.join(self.temp_tools_dir, 'tools', CCACHE, CCACHE_VERSION, 'ccache-4.11.2-windows-x86_64'), output + os.path.join(self.temp_tools_dir, 'tools', CCACHE, CCACHE_VERSION, 'ccache-4.12.1-windows-x86_64'), output ) self.assertIn( os.path.join(self.temp_tools_dir, 'tools', DFU_UTIL, DFU_UTIL_VERSION, 'dfu-util-0.11-win64'), output @@ -783,7 +776,7 @@ def test_tools_for_esp32_win(self): self.assertIn(os.path.join(self.temp_tools_dir, 'tools', NINJA, NINJA_VERSION), output) self.assertIn(os.path.join(self.temp_tools_dir, 'tools', IDF_EXE, IDF_EXE_VERSION), output) self.assertIn( - os.path.join(self.temp_tools_dir, 'tools', CCACHE, CCACHE_VERSION, 'ccache-4.11.2-windows-x86_64'), output + os.path.join(self.temp_tools_dir, 'tools', CCACHE, CCACHE_VERSION, 'ccache-4.12.1-windows-x86_64'), output ) self.assertNotIn( os.path.join(self.temp_tools_dir, 'tools', DFU_UTIL, DFU_UTIL_VERSION, 'dfu-util-0.11-win64'), output @@ -847,7 +840,7 @@ def test_tools_for_esp32c3_win(self): self.assertIn(os.path.join(self.temp_tools_dir, 'tools', NINJA, NINJA_VERSION), output) self.assertIn(os.path.join(self.temp_tools_dir, 'tools', IDF_EXE, IDF_EXE_VERSION), output) self.assertIn( - os.path.join(self.temp_tools_dir, 'tools', CCACHE, CCACHE_VERSION, 'ccache-4.11.2-windows-x86_64'), output + os.path.join(self.temp_tools_dir, 'tools', CCACHE, CCACHE_VERSION, 'ccache-4.12.1-windows-x86_64'), output ) self.assertNotIn( os.path.join(self.temp_tools_dir, 'tools', DFU_UTIL, DFU_UTIL_VERSION, 'dfu-util-0.11-win64'), output @@ -916,7 +909,7 @@ def test_tools_for_esp32s2_win(self): self.assertIn(os.path.join(self.temp_tools_dir, 'tools', NINJA, NINJA_VERSION), output) self.assertIn(os.path.join(self.temp_tools_dir, 'tools', IDF_EXE, IDF_EXE_VERSION), output) self.assertIn( - os.path.join(self.temp_tools_dir, 'tools', CCACHE, CCACHE_VERSION, 'ccache-4.11.2-windows-x86_64'), output + os.path.join(self.temp_tools_dir, 'tools', CCACHE, CCACHE_VERSION, 'ccache-4.12.1-windows-x86_64'), output ) self.assertIn( os.path.join(self.temp_tools_dir, 'tools', DFU_UTIL, DFU_UTIL_VERSION, 'dfu-util-0.11-win64'), output @@ -987,7 +980,7 @@ def test_tools_for_esp32s3_win(self): self.assertIn(os.path.join(self.temp_tools_dir, 'tools', NINJA, NINJA_VERSION), output) self.assertIn(os.path.join(self.temp_tools_dir, 'tools', IDF_EXE, IDF_EXE_VERSION), output) self.assertIn( - os.path.join(self.temp_tools_dir, 'tools', CCACHE, CCACHE_VERSION, 'ccache-4.11.2-windows-x86_64'), output + os.path.join(self.temp_tools_dir, 'tools', CCACHE, CCACHE_VERSION, 'ccache-4.12.1-windows-x86_64'), output ) self.assertIn( os.path.join(self.temp_tools_dir, 'tools', DFU_UTIL, DFU_UTIL_VERSION, 'dfu-util-0.11-win64'), output @@ -1024,7 +1017,7 @@ def test_tools_for_esp32p4_win(self): self.assertIn(os.path.join(self.temp_tools_dir, 'tools', NINJA, NINJA_VERSION), output) self.assertIn(os.path.join(self.temp_tools_dir, 'tools', IDF_EXE, IDF_EXE_VERSION), output) self.assertIn( - os.path.join(self.temp_tools_dir, 'tools', CCACHE, CCACHE_VERSION, 'ccache-4.11.2-windows-x86_64'), output + os.path.join(self.temp_tools_dir, 'tools', CCACHE, CCACHE_VERSION, 'ccache-4.12.1-windows-x86_64'), output ) self.assertNotIn( os.path.join(self.temp_tools_dir, 'tools', XTENSA_ELF, XTENSA_ELF_VERSION, XTENSA_ELF, 'bin'), output @@ -1077,16 +1070,16 @@ def test_validation(self): def test_json_rewrite(self): idf_tools.main(['rewrite']) - with open(self.tools_old, 'r') as f: + with open(self.tools_old) as f: json_old = f.read() - with open(self.tools_new, 'r') as f: + with open(self.tools_new) as f: json_new = f.read() self.assertEqual(json_old, json_new, "Please check 'tools/tools.new.json' to find a cause!") def add_version_get_expected_json(self, addition_file, replace=False): - with open(self.tools_old, 'r') as f: + with open(self.tools_old) as f: expected_json = json.load(f) - with open(addition_file, 'r') as f: + with open(addition_file) as f: addition_json = json.load(f) for tool in expected_json['tools']: if tool['name'] == self.test_tool_name: @@ -1099,7 +1092,7 @@ def add_version_get_expected_json(self, addition_file, replace=False): def test_add_version_artifact_addition(self): filenames = [] - with open('add_version/artifact_input.json', 'r') as f: + with open('add_version/artifact_input.json') as f: add_tools_info = json.load(f) for tool in add_tools_info: filenames.append(tool['filename']) @@ -1119,7 +1112,7 @@ def test_add_version_artifact_addition(self): ] + filenames ) expected_json = self.add_version_get_expected_json('add_version/artifact_expected_addition.json') - with open(self.tools_new, 'r') as f1: + with open(self.tools_new) as f1: self.assertEqual(json.load(f1), expected_json, "Please check 'tools/tools.new.json' to find a cause!") def test_add_version_checksum_addition(self): @@ -1137,7 +1130,7 @@ def test_add_version_checksum_addition(self): ] ) expected_json = self.add_version_get_expected_json('add_version/checksum_expected_addition.json') - with open(self.tools_new, 'r') as f1: + with open(self.tools_new) as f1: self.assertEqual(json.load(f1), expected_json, "Please check 'tools/tools.new.json' to find a cause!") def test_add_version_checksum_with_override(self): @@ -1156,7 +1149,7 @@ def test_add_version_checksum_with_override(self): ] ) expected_json = self.add_version_get_expected_json('add_version/checksum_expected_override.json', True) - with open(self.tools_new, 'r') as f1: + with open(self.tools_new) as f1: self.assertEqual(json.load(f1), expected_json, "Please check 'tools/tools.new.json' to find a cause!") diff --git a/tools/tools.json b/tools/tools.json index 26fea74f4c78..9265cc46a007 100644 --- a/tools/tools.json +++ b/tools/tools.json @@ -759,7 +759,7 @@ "description": "Ccache (compiler cache)", "export_paths": [ [ - "ccache-4.11.2-windows-x86_64" + "ccache-4.12.1-windows-x86_64" ] ], "export_vars": { @@ -787,12 +787,12 @@ "version_regex": "ccache version ([0-9.]+)", "versions": [ { - "name": "4.11.2", + "name": "4.12.1", "status": "recommended", "win64": { - "sha256": "1f39f3ad5aae3fe915e99ad1302633bc8f6718e58fa7c0de2b0ba7e080f0f08c", - "size": 1642225, - "url": "https://github.com/ccache/ccache/releases/download/v4.11.2/ccache-4.11.2-windows-x86_64.zip" + "sha256": "98aea520d66905b8ba7a8e648a4cc0ca941d5e119d441f1e879a4a9045bf18f6", + "size": 1710234, + "url": "https://github.com/ccache/ccache/releases/download/v4.12.1/ccache-4.12.1-windows-x86_64.zip" } } ]