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lines changed Original file line number Diff line number Diff line change @@ -23,10 +23,12 @@ RUN wget https://github.com/tensil-ai/tensil-models/archive/main.tar.gz && tar x
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FROM azul/zulu-openjdk:11
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RUN mkdir -p /demo/models
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+ RUN mkdir -p /demo/models/data
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COPY --from=models /work/tensil-models-main/resnet20v2_cifar.* /demo/models/
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COPY --from=models /work/tensil-models-main/resnet50v2_imagenet.* /demo/models/
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COPY --from=models /work/tensil-models-main/yolov4_tiny_192.* /demo/models/
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COPY --from=models /work/tensil-models-main/yolov4_tiny_416.* /demo/models/
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+ COPY --from=models /work/tensil-models-main/data/* /demo/models/data/
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RUN mkdir -p /demo/arch
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COPY ./arch/* /demo/arch/
Original file line number Diff line number Diff line change @@ -58,7 +58,7 @@ tensil compile -a /demo/arch/pynqz1.tarch -m /demo/models/resnet20v2_cifar.pb -o
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## Run bit accurate Tensil emulator
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```
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- tensil emulate -m resnet20v2_cifar_onnx_pynqz1.tmodel -i . /models/data/resnet_input_1x32x32x8.csv
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+ tensil emulate -m resnet20v2_cifar_onnx_pynqz1.tmodel -i /demo /models/data/resnet_input_1x32x32x8.csv
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```
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## Make Verilog RTL
You can’t perform that action at this time.
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