bus: Do cycle advancements AFTER reading/writing, rather than before

Passes a few more mooneye tests.

Author: tgsm

src/bus.cpp

@@ -23,86 +23,86 @@ void Bus::LoadInitialValues() {
 }
 
 u8 Bus::Read8(u16 addr, bool affect_timer) {
-    if (affect_timer) {
-        timer.AdvanceCycles(4);
-    }
-
-    switch (addr) {
-        case 0x0000 ... 0x7FFF:
-            if (addr < 0x0100 && boot_rom_enabled) {
-                return bootrom.Read(addr);
-            }
+    const u8 value = [&]() -> u8 {
+        switch (addr) {
+            case 0x0000 ... 0x7FFF:
+                if (addr < 0x0100 && boot_rom_enabled) {
+                    return bootrom.Read(addr);
+                }
 
 #define CART_IS_MBC1() (mbc_type >= 0x01 && mbc_type <= 0x03)
 #define CART_IS_MBC3() (mbc_type >= 0x0F && mbc_type <= 0x13)
 
-            if (addr >= 0x4000) {
-                u8 mbc_type = cartridge.GetMBCType();
-                u16 rom_bank = 0x001;
-                if (CART_IS_MBC1()) {
-                    rom_bank = ((mbc1_bank2 & 3) << 5) | (mbc1_bank1 & 0x1F);
-                } else if (CART_IS_MBC3()) {
-                    rom_bank = mbc3_rom_bank;
+                if (addr >= 0x4000) {
+                    u8 mbc_type = cartridge.GetMBCType();
+                    u16 rom_bank = 0x001;
+                    if (CART_IS_MBC1()) {
+                        rom_bank = ((mbc1_bank2 & 3) << 5) | (mbc1_bank1 & 0x1F);
+                    } else if (CART_IS_MBC3()) {
+                        rom_bank = mbc3_rom_bank;
+                    }
+                    return cartridge.Read((addr & 0x3FFF) + rom_bank * 0x4000);
                 }
-                return cartridge.Read((addr & 0x3FFF) + rom_bank * 0x4000);
-            }
 
-            return cartridge.Read(addr);
+                return cartridge.Read(addr);
 
-        case 0x8000 ... 0x9FFF:
-            // LDEBUG("bus: reading 0x{:02X} from 0x{:04X} (VRAM)", vram[addr - 0x8000], addr);
-            return vram[addr - 0x8000];
+            case 0x8000 ... 0x9FFF:
+                // LDEBUG("bus: reading 0x{:02X} from 0x{:04X} (VRAM)", vram[addr - 0x8000], addr);
+                return vram[addr - 0x8000];
 
-        case 0xA000 ... 0xBFFF:
-            if (!mbc_ram_enabled) {
-                // LWARN("bus: attempted to read from cartridge RAM while it is disabled (from 0x{:04X})", addr);
-                return 0xFF;
-            }
+            case 0xA000 ... 0xBFFF:
+                if (!mbc_ram_enabled) {
+                    // LWARN("bus: attempted to read from cartridge RAM while it is disabled (from 0x{:04X})", addr);
+                    return 0xFF;
+                }
 
-            LDEBUG("bus: reading 0x{:02X} from 0x{:04X} (Cartridge RAM)", cartridge_ram[addr - 0xA000], addr);
-            return cartridge_ram[addr - 0xA000];
+                LDEBUG("bus: reading 0x{:02X} from 0x{:04X} (Cartridge RAM)", cartridge_ram[addr - 0xA000], addr);
+                return cartridge_ram[addr - 0xA000];
 
-        case 0xC000 ... 0xDFFF:
-            // LDEBUG("bus: reading 0x{:02X} from 0x{:04X} (WRAM)", wram[addr - 0xC000], addr);
-            return wram[addr - 0xC000];
+            case 0xC000 ... 0xDFFF:
+                // LDEBUG("bus: reading 0x{:02X} from 0x{:04X} (WRAM)", wram[addr - 0xC000], addr);
+                return wram[addr - 0xC000];
 
-        case 0xE000 ... 0xFDFF:
-            // LWARN("bus: reading from echo RAM (0x{:02X} from 0x{:04X})", wram[addr - 0xE000], addr);
-            return wram[addr - 0xE000];
+            case 0xE000 ... 0xFDFF:
+                // LWARN("bus: reading from echo RAM (0x{:02X} from 0x{:04X})", wram[addr - 0xE000], addr);
+                return wram[addr - 0xE000];
 
-        case 0xFE00 ... 0xFE9F:
-            if (oam_dma.active) {
-                return 0xFF;
-            }
+            case 0xFE00 ... 0xFE9F:
+                if (oam_dma.active) {
+                    return 0xFF;
+                }
 
-            // LDEBUG("bus: reading 0x{:02X} to 0x{:04X} (OAM / Sprite Attribute Table)", oam[0xFE00], addr);
-            return oam[addr - 0xFE00];
+                // LDEBUG("bus: reading 0x{:02X} to 0x{:04X} (OAM / Sprite Attribute Table)", oam[0xFE00], addr);
+                return oam[addr - 0xFE00];
 
-        case 0xFEA0 ... 0xFEFF:
-            // LWARN("bus: attempted to read from unusable memory (0x{:04X})", addr);
-            return 0x00;
+            case 0xFEA0 ... 0xFEFF:
+                // LWARN("bus: attempted to read from unusable memory (0x{:04X})", addr);
+                return 0x00;
 
-        case 0xFF00 ... 0xFF7F:
-            return ReadIO(addr & 0xFF);
+            case 0xFF00 ... 0xFF7F:
+                return ReadIO(addr & 0xFF);
 
-        case 0xFF80 ... 0xFFFE:
-            // LDEBUG("bus: reading 0x{:02X} from 0x{:04X} (Zero Page)", hram[addr - 0xFF80], addr);
-            return hram[addr - 0xFF80];
+            case 0xFF80 ... 0xFFFE:
+                // LDEBUG("bus: reading 0x{:02X} from 0x{:04X} (Zero Page)", hram[addr - 0xFF80], addr);
+                return hram[addr - 0xFF80];
 
-        case 0xFFFF:
-            // Interrupt enable
-            return ie;
+            case 0xFFFF:
+                // Interrupt enable
+                return ie;
 
-        default:
-            UNREACHABLE();
-    }
-}
+            default:
+                UNREACHABLE();
+        }
+    }();
 
-void Bus::Write8(u16 addr, u8 value, bool affect_timer) {
     if (affect_timer) {
         timer.AdvanceCycles(4);
     }
 
+    return value;
+}
+
+void Bus::Write8(u16 addr, u8 value, bool affect_timer) {
     switch (addr) {
         case 0x0000 ... 0x7FFF:
         {
@@ -171,6 +171,10 @@ void Bus::Write8(u16 addr, u8 value, bool affect_timer) {
         default:
             UNREACHABLE();
     }
+
+    if (affect_timer) {
+        timer.AdvanceCycles(4);
+    }
 }
 
 void Bus::WriteMBC(u8 mbc_type, u16 addr, u8 value) {