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[SymbiFlow] Add support for Spartan 6 parts #45

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mithro opened this issue Feb 12, 2018 · 1 comment
Open

[SymbiFlow] Add support for Spartan 6 parts #45

mithro opened this issue Feb 12, 2018 · 1 comment

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@mithro
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mithro commented Feb 12, 2018

[SymbiFlow #10] Add support for Spartan 6 parts

More technical details at SymbiFlow Idea #10

Brief explanation

Spartan 6 is a hugely popular part which would be awesome to have support for in open source FPGA toolchain - SymbiFlow

Expected results

  • Documentation of the bitstream for Spartan 6 parts.
  • Support for using Spartan 6 in the SymbiFlow.

Detailed Explanation

SymbiFlow will be a FOSS Verilog-to-Bitstream FPGA synthesis flow for Xilinx 7-Series FPGAs and iCE40. SymbiFlow currently only supports Xilinx Series 7 parts and the Lattice iCE40 parts.

While the Spartan 6 has mostly be superseded by the Artix 7 and Spartan 7 there are still a huge number of boards out there with Spartan 6 parts. Due to its huge popularity it will be a long time until the part is no longer in use (people still start new designs with Spartan 3!).

To make it even more important Spartan 6 designs you still have to use ISE which is significantly worse then Vivado in many ways. Having an non-ISE toolchain for that would be awesome.

Spartan 6 is used heavily by a number of open source projects;

Further reading

Knowledge Prerequisites

  • List of
  • what knowledge is required
  • to complete this project.
@fanoush
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fanoush commented Nov 5, 2019

There is also the amazingly cheap Pano Logic G2 (and G1 with Spartan 3E)

BTW there is interesting paper https://pdfs.semanticscholar.org/64c7/a8f1dc7b513aca6eea387d9c319c0b358506.pdf (3rd hit for https://www.google.com/search?q=open+source+bitstream+xilinx) that discusses methods of merging pregenerated combinations of basic bitstream files to get desired functionality. Using the method to generate desired bitsream looks more complicated than reverse engineering it but as a procedure/methodology to understand the bitstream it is a good read.

Also found this Recent Advances in FPGA Reverse Engineering which references the paper mentioned above but also describes other tools.

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