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vtype-format.adoc

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{reg: [
  {bits: 3, name: 'vlmul[2:0]'},
  {bits: 3, name: 'vsew[2:0]'},
  {bits: 1, name: 'vta'},
  {bits: 1, name: 'vma'},
  {bits: 23, name: 'reserved'},
  {bits: 1, name: 'vill'},
]}
Note
This diagram shows the layout for RV32 systems, whereas in general vill should be at bit XLEN-1.
Table 1. vtype register layout
Bits Name Description

XLEN-1

vill

Illegal value if set

XLEN-2:8

0

Reserved if non-zero

7

vma

Vector mask agnostic

6

vta

Vector tail agnostic

5:3

vsew[2:0]

Selected element width (SEW) setting

2:0

vlmul[2:0]

Vector register group multiplier (LMUL) setting