Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Attempting to Flash SPI PROM of a custom board - Dragon-L #460

Closed
AnantaSrikar opened this issue May 28, 2024 · 24 comments
Closed

Attempting to Flash SPI PROM of a custom board - Dragon-L #460

AnantaSrikar opened this issue May 28, 2024 · 24 comments

Comments

@AnantaSrikar
Copy link

I am attempting to flash a bitstream to a custom FPGA board, called the Dragon-L. It has a Spartan-6 XC6SLX25T-CSG324 FPGA on board. I am using an Altera USB Blaster as the JTAG adapter.

I have built and tried the latest openFPGALoader. Upon trying to flash a bitstream, I got the following error:

❯ openFPGALoader -c usb-blaster ledblink.bit
empty
JTAG init failed with: Unknown device with IDCODE: 0x24024093 (manufacturer: 0x049 (Xilinx), part: 0x20 vers: 0x2

Then, I did some research and figured out I could add my the IDCODE to src/part.hpp. I added the following and recompiled:

        {0x04004093, {"xilinx", "spartan6", "xc6slx25",        6}},
+       {0x24024093, {"xilinx", "spartan6", "xc6slx25T",       6}},
        {0x04008093, {"xilinx", "spartan6", "xc6slx45",        6}},

Then, I was able to flash to the SRAM of the FPGA with the following output:

❯ ./openFPGALoader -c usb-blaster ledblink.bit --verbose 
empty
found 1 devices
index 0:
	idcode 0x24024093
	manufacturer xilinx
	family spartan6
	model  xc6slx25T
	irlength 6
File type : bit
Open file DONE
Parse file DONE
bitstream header infos
date: 2024/05/22
design_name: ledblink.ncd
hour: 10:26:28
part_name: 6slx25tcsg324
toolVersion: 0xFFFFFFFF
userID: 0xFFFFFFFF
load program
Load SRAM: [==================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1

I wanted to take it a step ahead and see if I could flash the same onto the onboard SPI flash, and tried adding the -f flag, and errored out with the following output:

❯ ./openFPGALoader -c usb-blaster -f ledblink.bit --verbose
empty
write to flash
found 1 devices
index 0:
	idcode 0x24024093
	manufacturer xilinx
	family spartan6
	model  xc6slx25T
	irlength 6
File type : bit
Open file DONE
Parse file DONE
bitstream header infos
date: 2024/05/22
design_name: ledblink.ncd
hour: 10:26:28
part_name: 6slx25tcsg324
toolVersion: 0xFFFFFFFF
userID: 0xFFFFFFFF
Can't program SPI flash: missing device-package information

I did some more research and I figured out I could add the --fpga-part flag, and ran the same, but I still got an error:

❯ ./openFPGALoader -c usb-blaster --fpga-part xc6slx9csg324 -f ../../fpgaconf/captures/ledblink.bit --verbose
empty
write to flash
found 1 devices
index 0:
	idcode 0x24024093
	manufacturer xilinx
	family spartan6
	model  xc6slx25T
	irlength 6
File type : bit
Open file DONE
Parse file DONE
bitstream header infos
date: 2024/05/22
design_name: ledblink.ncd
hour: 10:26:28
part_name: 6slx25tcsg324
toolVersion: 0xFFFFFFFF
userID: 0xFFFFFFFF
use: /home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/spiOverJtag_xc6slx9csg324.bit.gz
load program
Load SRAM: [==================================================] 100.00%
Done
Shift IR 11
ir: 1 isc_done 0 isc_ena 0 init 1 done 0
Register raw value: 0x0
CRC Error      No CRC error
Part Secured   0
MMCM lock      0
DCI match      0
EOS            0
GTS CFG B      0
GWE            0
GHIGH B        0
MODE           0
INIT Complete  0
INIT B         0
Release Done   0
Done           0
ID Error       No ID error
DEC Error      0
XADC Over temp 0
STARTUP State  0
Reserved       0
BUS Width      x1
Reserved       0
cd 96 76 80 read cd967680
Detail: 
Jedec ID          : cd
memory type       : 96
memory capacity   : 76
RDSR : 68
WIP  : 0
WEL  : 0
BP   : a
TB   : 1
SRWD : 0
flash chip unknown: use basic protection detection
unlock blocks
Error: block protection is set
       can't unlock without --unprotect-flash

Since the error mentioned the flag --uprotect-flash, I tried that too, but still failed with a timeout error:

❯ ./openFPGALoader -c usb-blaster --fpga-part xc6slx9csg324 -f ../../fpgaconf/captures/ledblink.bit --unprotect-flash --verbose 
empty
write to flash
found 1 devices
index 0:
	idcode 0x24024093
	manufacturer xilinx
	family spartan6
	model  xc6slx25T
	irlength 6
File type : bit
Open file DONE
Parse file DONE
bitstream header infos
date: 2024/05/22
design_name: ledblink.ncd
hour: 10:26:28
part_name: 6slx25tcsg324
toolVersion: 0xFFFFFFFF
userID: 0xFFFFFFFF
use: /home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/spiOverJtag_xc6slx9csg324.bit.gz
load program
Load SRAM: [==================================================] 100.00%
Done
Shift IR 11
ir: 1 isc_done 0 isc_ena 0 init 1 done 0
Register raw value: 0x0
CRC Error      No CRC error
Part Secured   0
MMCM lock      0
DCI match      0
EOS            0
GTS CFG B      0
GWE            0
GHIGH B        0
MODE           0
INIT Complete  0
INIT B         0
Release Done   0
Done           0
ID Error       No ID error
DEC Error      0
XADC Over temp 0
STARTUP State  0
Reserved       0
BUS Width      x1
Reserved       0
ad b4 40 80 read adb44080
Detail: 
Jedec ID          : ad
memory type       : b4
memory capacity   : 40
RDSR : 2c
WIP  : 0
WEL  : 0
BP   : 3
TB   : 1
SRWD : 0
flash chip unknown: use basic protection detection
unlock blocks
timeout: ff ff ff
ff
wait: Error

I've double checked the pinout for the SPI PROM and it should be fine. I am not sure what I'm missing here, and I hope to make some changes and add official support to this board.

The flash chip in use is an 25P80VP by STMicroelectronics. I believe this is the datasheet for the same.

I'm not sure what I'm missing here, hope to find some insights and direction for the same. Thanks!
@trabucayre
Copy link
Owner

Yes. To be able to use openFPGALoader with a FPGA not already supported you have to update list of idcode (Yes, A better way is to import for some family all variants to avoid this type of issue).

But to update the flash with a bitstream you needs a sort of bridge (called spiOverJtag). For Xilinx you can't directly have access to the flash by using JTAG and you needs to load a gateware to interconnect these two interfaces. But unfortunately one bitstream is required by FPGA type (family, size, package), this why spiOverJtag directory contains a bunch of bitstreams.
Here you have tried to load a bitstream dedicated to another model (size/model) this why openFPGALoader is unable to access FLASH chip.

For this step you have to follow approach similar to this commit

@AnantaSrikar
Copy link
Author

Thank you so much for getting back to me. The way Xilinx accesses the SPI over JTAG is interesting. I will try looking around and getting the bitstream for xc6slx25tcsg324.bit.gz. I think it should be pretty straightforward after that. Any idea where I should be looking for the same?

@AnantaSrikar
Copy link
Author

I figured out how to generate the bitstream:

  • Make a new file named constr_xc6s_t_csg324.ucf with the same contents of spiOverJtag/constr_xc6s_csg324.ucf since the pinout is the same (I triple checked it here).
  • Made the appropriate changes to the spiOverJtag/build.py to accomodate for the new chip.
  • Setup a python virtual environment with edalize and appended the $PATH with the Xilinx ISE binaries
  • Ran python3 build.py xc6slx25tcsg324. This generated the spiOverJtag.bit file in the tmp_xc6slx25tcsg324
  • Ran gzip -9 -c tmp_xc6slx25tcsg324/spiOverJtag.bit > spiOverJtag_xc6slx25tcsg324.bit.gz to get the .bit.gz version of the bitstream.
  • Finally, I ran the flash command to get a similar error:
❯ ./openFPGALoader -c usb-blaster --fpga-part xc6slx25tcsg324 -f ledblink.bit --verbose --unprotect-flash
empty
write to flash
found 1 devices
index 0:
	idcode 0x24024093
	manufacturer xilinx
	family spartan6
	model  xc6slx25T
	irlength 6
File type : bit
Open file DONE
Parse file DONE
bitstream header infos
date: 2024/05/22
design_name: ledblink.ncd
hour: 10:26:28
part_name: 6slx25tcsg324
toolVersion: 0xFFFFFFFF
userID: 0xFFFFFFFF
use: /home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/spiOverJtag_xc6slx25tcsg324.bit.gz
load program
Load SRAM: [==================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1
a1 3d bb 80 read a13dbb80
Detail: 
Jedec ID          : a1
memory type       : 3d
memory capacity   : bb
RDSR : bc
WIP  : 0
WEL  : 0
BP   : 7
TB   : 1
SRWD : 1
flash chip unknown: use basic protection detection
unlock blocks
timeout: ff ff ff
ff
wait: Error

I've pushed all the changes I've made here for your reference.
Any idea what I'm missing here?

@trabucayre
Copy link
Owner

Jedec ID seems wrong must be 0x2014. There is a problem with communication but I suspect the chip is in quad mode instead of SPI mode. But I must check if it's possible for your board.
Maybe I have to order one, but it's a bit expensive.

@trabucayre
Copy link
Owner

In fact there is no schematics available... Could you also try with other JTAG cable? like ftdi?

@AnantaSrikar
Copy link
Author

I'm not too sure about quad mode. I will also contact the board manufacturer to see if I can get more details and maybe the schematic. Regarding another JTAG cable, I'll have to order one.

Regarding another JTAG cable, do you think I can use this to program the FPGA? I've never worked with FPGAs before, so I'm a little unsure about how I should go ahead.

@AnantaSrikar
Copy link
Author

I've contacted the Dragon-L board developer regarding the SPI pinout. I'm attaching the schematic for the same. The board does not support the quad mode.

image

@trabucayre
Copy link
Owner

any FTDI do the job, the only you have to check is the pin voltage: usually for a jtag probe, jtag pins are powered by a power pins from the board.
Your schematics confirms constraints file pinout, it's weird openFPGALoader and spiOverJtag are perfectly compatible with spartan6...

@AnantaSrikar
Copy link
Author

That is weird. I will try dirty JTAG on Bluepill, an ST-Link v2 clone and a Raspberry Pi pico to see if I can get it to work. In the event it doesn't, I will purchase this FTDI cable and try again.

In the meantime, is there any signal that you would want me to verify by using an oscilloscope?

@trabucayre
Copy link
Owner

I think the best way is I have a physical to a similar board. Its not always easy to see reasons why an issue like here.

@AnantaSrikar
Copy link
Author

I flashed a Bluepill board I had lying around with the dirtyJtag firmware. The SRAM flashing works just fine, like the USB Blaster. It fails whenever I try to flash to SPI flash.

I'm starting to think this is because I'm not using all the JTAG pins. I'm only using the TCK, TDO, TDI, and TMS pins that can be easily connected by the 2.54 headers. The JTAG port uses a smaller form factor 14-pin connector, which I'm still on the hunt for.

I will try buying a smaller 14-pin connector and connecting the remaining pins (TRST and SRST) to see if it works. Either that or the generated bitfile is somehow not the right one.

Attaching a picture for your reference.

signal-2024-06-04-111123

@trabucayre
Copy link
Owner

Don't buy anything: it's not required. Tests with altera blaster and dirtyJTAG are enough: the problem isn't related to the cable...

@AnantaSrikar
Copy link
Author

Oh okay. Do you think its because the spiOverJtag_xc6slx25tcsg324.bit.gz is not the correct bitfile, maybe due to the Xilinx version or something?

Pasting the output of python3 build.py xc6slx25tcsg324 for your reference

❯ export PATH=$PATH:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64
                                                                                
❯ python3 build.py xc6slx25tcsg324                       
Successfully created the directory tmp_xc6slx25tcsg324 
xtclsh spiOverJtag.tcl
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/xilinx_spiOverJtag
   .v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
xtclsh spiOverJtag_run.tcl spiOverJtag.xise
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/xilinx_spiOverJtag
   .v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/tmp_xc6slx25tcsg324/spiOverJtag.xst" -ofn "/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/tmp_xc6slx25tcsg324/spiOverJtag.syr"
Reading design: spiOverJtag.prj

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/xilinx_spiOverJtag.v" into library work
Parsing module <spiOverJtag>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <spiOverJtag>.

Elaborating module <BSCAN_SPARTAN6(JTAG_CHAIN=1)>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <spiOverJtag>.
    Related source file is "/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/xilinx_spiOverJtag.v".
    Found 1-bit register for signal <csn>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <spiOverJtag> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 1
 1-bit register                                        : 1
# Multiplexers                                         : 1
 1-bit 2-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 1
 Flip-Flops                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <spiOverJtag> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block spiOverJtag, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 1
 Flip-Flops                                            : 1

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
sck_OBUF                           | NONE(fsm_csn)          | 1     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: No path found
   Minimum input arrival time before clock: 1.985ns
   Maximum output required time after clock: 3.597ns
   Maximum combinational path delay: 3.187ns

=========================================================================

Process "Synthesize - XST" completed successfully

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc /home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/constr_xc6s_t_csg324.ucf -p xc6slx25t-csg324-3 spiOverJtag.ngc spiOverJtag.ngd

Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
ise -dd _ngo -nt timestamp -uc
/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/constr_xc6s_t_csg324.u
cf -p xc6slx25t-csg324-3 spiOverJtag.ngc spiOverJtag.ngd

Reading NGO file
"/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/tmp_xc6slx25tcsg324/s
piOverJtag.ngc" ...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file
"/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/constr_xc6s_t_csg324.
ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "spiOverJtag.ngd" ...
Total REAL time to NGDBUILD completion:  1 sec
Total CPU time to NGDBUILD completion:   1 sec

Writing NGDBUILD log file "spiOverJtag.bld"...

NGDBUILD done.

Process "Translate" completed successfully

Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc6slx25t-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -detail -ir off -pr off -lc off -power off -o spiOverJtag_map.ncd spiOverJtag.ngd spiOverJtag.pcf
Using target part "6slx25tcsg324-3".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 2 secs 
Total CPU  time at the beginning of Placer: 2 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:2d6449dc) REAL time: 2 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:2d6449dc) REAL time: 2 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:d656dd77) REAL time: 2 secs 

Phase 4.2  Initial Placement for Architecture Specific Features
Phase 4.2  Initial Placement for Architecture Specific Features
(Checksum:d656dd77) REAL time: 2 secs 

Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:d656dd77) REAL time: 2 secs 

Phase 6.30  Global Clock Region Assignment
Phase 6.30  Global Clock Region Assignment (Checksum:d656dd77) REAL time: 2 secs 

Phase 7.3  Local Placement Optimization
Phase 7.3  Local Placement Optimization (Checksum:d656dd77) REAL time: 2 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:d656dd77) REAL time: 2 secs 

Phase 9.8  Global Placement
..
..
Phase 9.8  Global Placement (Checksum:e414247b) REAL time: 2 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:e414247b) REAL time: 2 secs 

Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:887b616b) REAL time: 2 secs 

Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:887b616b) REAL time: 2 secs 

Phase 13.34  Placement Validation
Phase 13.34  Placement Validation (Checksum:887b616b) REAL time: 2 secs 

Total REAL time to Placer completion: 2 secs 
Total CPU  time to Placer completion: 2 secs 
Running post-placement packing...
Writing output files...

Design Summary:
Number of errors:      0
Number of warnings:    0
Slice Logic Utilization:
  Number of Slice Registers:                     0 out of  30,064    0%
  Number of Slice LUTs:                          2 out of  15,032    1%
    Number used as logic:                        2 out of  15,032    1%
      Number using O6 output only:               1
      Number using O5 output only:               0
      Number using O5 and O6:                    1
      Number used as ROM:                        0
    Number used as Memory:                       0 out of   3,664    0%

Slice Logic Distribution:
  Number of occupied Slices:                     2 out of   3,758    1%
  Number of MUXCYs used:                         0 out of   7,516    0%
  Number of LUT Flip Flop pairs used:            2
    Number with an unused Flip Flop:             2 out of       2  100%
    Number with an unused LUT:                   0 out of       2    0%
    Number of fully used LUT-FF pairs:           0 out of       2    0%
    Number of slice register sites lost
      to control set restrictions:               0 out of  30,064    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                         6 out of     190    3%
    Number of LOCed IOBs:                        6 out of       6  100%
    IOB Flip Flops:                              1

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      52    0%
  Number of RAMB8BWERs:                          0 out of     104    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       0 out of      16    0%
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     272    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     272    0%
  Number of OLOGIC2/OSERDES2s:                   1 out of     272    1%
    Number used as OLOGIC2s:                     1
    Number used as OSERDES2s:                    0
  Number of BSCANs:                              1 out of       4   25%
  Number of BUFHs:                               0 out of     160    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      38    0%
  Number of GTPA1_DUALs:                         0 out of       1    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCIE_A1s:                            0 out of       1    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                1.10

Peak Memory Usage:  680 MB
Total REAL time to MAP completion:  2 secs 
Total CPU time to MAP completion:   2 secs 

Mapping completed.
See MAP report file "spiOverJtag_map.mrp" for details.

Process "Map" completed successfully

Started : "Place & Route".
Running par...
Command Line: par -w -intstyle ise -ol high -mt off spiOverJtag_map.ncd spiOverJtag.ncd spiOverJtag.pcf



Constraints file: spiOverJtag.pcf.
Loading device for application Rf_Device from file '6slx25t.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
   "spiOverJtag" is an NCD, version 3.2, device xc6slx25t, package csg324, speed -3

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".

Device speed data version:  "PRODUCTION 1.23 2013-10-13".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                     0 out of  30,064    0%
  Number of Slice LUTs:                          2 out of  15,032    1%
    Number used as logic:                        2 out of  15,032    1%
      Number using O6 output only:               1
      Number using O5 output only:               0
      Number using O5 and O6:                    1
      Number used as ROM:                        0
    Number used as Memory:                       0 out of   3,664    0%

Slice Logic Distribution:
  Number of occupied Slices:                     2 out of   3,758    1%
  Number of MUXCYs used:                         0 out of   7,516    0%
  Number of LUT Flip Flop pairs used:            2
    Number with an unused Flip Flop:             2 out of       2  100%
    Number with an unused LUT:                   0 out of       2    0%
    Number of fully used LUT-FF pairs:           0 out of       2    0%
    Number of slice register sites lost
      to control set restrictions:               0 out of  30,064    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                         6 out of     190    3%
    Number of LOCed IOBs:                        6 out of       6  100%
    IOB Flip Flops:                              1

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      52    0%
  Number of RAMB8BWERs:                          0 out of     104    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       0 out of      16    0%
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     272    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     272    0%
  Number of OLOGIC2/OSERDES2s:                   1 out of     272    1%
    Number used as OLOGIC2s:                     1
    Number used as OSERDES2s:                    0
  Number of BSCANs:                              1 out of       4   25%
  Number of BUFHs:                               0 out of     160    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      38    0%
  Number of GTPA1_DUALs:                         0 out of       1    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCIE_A1s:                            0 out of       1    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 1 secs 
Finished initial Timing Analysis.  REAL time: 1 secs 

Starting Router


Phase  1  : 17 unrouted;      REAL time: 2 secs 

Phase  2  : 15 unrouted;      REAL time: 2 secs 

Phase  3  : 1 unrouted;      REAL time: 2 secs 

Phase  4  : 1 unrouted; (Par is working to improve performance)     REAL time: 2 secs 

Updating file: spiOverJtag.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 2 secs 

Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 2 secs 

Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 2 secs 

Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 2 secs 

Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 2 secs 

Phase 10  : 0 unrouted; (Par is working to improve performance)     REAL time: 2 secs 
Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 2 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of
                                            |            |            | Levels | Slack      |errors   
------------------------------------------------------------------------------------------------------


All constraints were met.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  626 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 2

Writing design to file spiOverJtag.ncd



PAR done!

Process "Place & Route" completed successfully

Started : "Generate Post-Place & Route Static Timing".
Running trce...
Command Line: trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml spiOverJtag.twx spiOverJtag.ncd -o spiOverJtag.twr spiOverJtag.pcf
Loading device for application Rf_Device from file '6slx25t.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/.
   "spiOverJtag" is an NCD, version 3.2, device xc6slx25t, package csg324, speed
-3

Analysis completed Tue Jun  4 12:39:53 2024
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 1 secs 

Process "Generate Post-Place & Route Static Timing" completed successfully

Started : "Generate Programming File".
Running bitgen...
Command Line: bitgen -intstyle ise -f spiOverJtag.ut spiOverJtag.ncd

Process "Generate Programming File" completed successfully
INFO:TclTasksC:1850 - process run : Generate Programming File is done.

@trabucayre
Copy link
Owner

I must admit its hard to said. Flow looks good and your constraints file too... Maybe trying to disable flash at powerup time using a wire between CS and VCC to have an empty FPGA (flash be reserved by gateware loaded at boot time).

@AnantaSrikar
Copy link
Author

AnantaSrikar commented Jun 8, 2024 •
edited
Loading

I will try disabling the flash as the FPGA powers up and let you know how that works.

Besides that, I've had success flashing the SPI of the FPGA using the KNJN USBFX2-JTAG development board and the KNJN JTAG cable along with the FPGAconf portable executable. That exe application allows me to select the bitfile I want to flash, and click on flash boot for it to write it to SPI. So what I can also try writing the SpiOverJtag.bit to the flash and see how openFPGALoader works with that.

@AnantaSrikar
Copy link
Author

A small update on this. I was trying to get OpenOCD running with the altera blaster and my FPGA. I think the Altera Blaster is at fault here, but I'm not sure.

Flashing to SRAM works perfectly as expected.

Here is dragon-l-sram.cfg

source [find interface/altera-usb-blaster.cfg]
source [find cpld/xilinx-xc6s.cfg]

adapter speed 10000

init

xc6s_program xc6s.tap

pld load 0 ledglow.bit
shutdown

The command run for the above is as follows:

openocd -f dragon-l-sram.cfg
Open On-Chip Debugger 0.12.0
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
Info : usb blaster interface using libftdi
Info : This adapter doesn't support configurable speed
Info : JTAG tap: xc6s.tap tap/device found: 0x24024093 (mfg: 0x049 (Xilinx), part: 0x4024, ver: 0x2)
Warn : gdb services need one or more targets defined
shutdown command invoke

Now, I have a configuration that is probably working, since the SPI flash gets corrupted as after running the command, and the SPI flash is detected correctly.

Below is configuration

source [find interface/altera-usb-blaster.cfg]
source [find cpld/xilinx-xc6s.cfg]
source [find cpld/jtagspi.cfg]

adapter speed 100

init
jtagspi_init 0 bscan_spi_xc6slx25t.bit
jtagspi_program ledglow.bit 0x0
xc6s_program xc6s.tap
flash verify_bank 0 ledglow.bit
shutdown

This is the output of the same:

openocd -f dragon-l-spi.cfg
Open On-Chip Debugger 0.12.0
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
Info : usb blaster interface using libftdi
Info : This adapter doesn't support configurable speed
Info : JTAG tap: xc6s.tap tap/device found: 0x24024093 (mfg: 0x049 (Xilinx), part: 0x4024, ver: 0x2)
Info : JTAG tap: xc6s.tap tap/device found: 0x24024093 (mfg: 0x049 (Xilinx), part: 0x4024, ver: 0x2)
Info : Found flash device 'st m25p80' (ID 0x142020)
Info : sector 0 took 636 ms
Info : sector 1 took 591 ms
Info : sector 2 took 558 ms
Info : sector 3 took 576 ms
read 244520 bytes from file ledglow.bit and flash bank 0 at offset 0x00000000 in 2.178538s (109.610 KiB/s)
contents differ
diff 0 address 0x00000001. Was 0x00 instead of 0x09
diff 1 address 0x00000002. Was 0x00 instead of 0x0f
diff 2 address 0x00000003. Was 0x00 instead of 0xf0
diff 3 address 0x00000004. Was 0x00 instead of 0x0f
diff 4 address 0x00000005. Was 0x00 instead of 0xf0
diff 5 address 0x00000006. Was 0x00 instead of 0x0f
diff 6 address 0x00000007. Was 0x00 instead of 0xf0
diff 7 address 0x00000008. Was 0x00 instead of 0x0f
diff 8 address 0x00000009. Was 0x00 instead of 0xf0
diff 9 address 0x0000000c. Was 0x00 instead of 0x01
diff 10 address 0x0000000d. Was 0x00 instead of 0x61
diff 11 address 0x0000000f. Was 0x00 instead of 0x1e
diff 12 address 0x00000010. Was 0x00 instead of 0x4c
diff 13 address 0x00000011. Was 0x00 instead of 0x45
diff 14 address 0x00000012. Was 0x00 instead of 0x44
diff 15 address 0x00000013. Was 0x00 instead of 0x67
diff 16 address 0x00000014. Was 0x00 instead of 0x6c
diff 17 address 0x00000015. Was 0x00 instead of 0x6f
diff 18 address 0x00000016. Was 0x00 instead of 0x77
diff 19 address 0x00000017. Was 0x00 instead of 0x2e
diff 20 address 0x00000018. Was 0x00 instead of 0x6e
diff 21 address 0x00000019. Was 0x00 instead of 0x63
diff 22 address 0x0000001a. Was 0x00 instead of 0x64
diff 23 address 0x0000001b. Was 0x00 instead of 0x3b
diff 24 address 0x0000001c. Was 0x00 instead of 0x55
diff 25 address 0x0000001d. Was 0x00 instead of 0x73
diff 26 address 0x0000001e. Was 0x00 instead of 0x65
diff 27 address 0x0000001f. Was 0x00 instead of 0x72
diff 28 address 0x00000020. Was 0x00 instead of 0x49
diff 29 address 0x00000021. Was 0x00 instead of 0x44
diff 30 address 0x00000022. Was 0x00 instead of 0x3d
diff 31 address 0x00000023. Was 0x00 instead of 0x30
diff 32 address 0x00000024. Was 0x00 instead of 0x78
diff 33 address 0x00000025. Was 0x00 instead of 0x46
diff 34 address 0x00000026. Was 0x00 instead of 0x46
diff 35 address 0x00000027. Was 0x00 instead of 0x46
diff 36 address 0x00000028. Was 0x00 instead of 0x46
diff 37 address 0x00000029. Was 0x00 instead of 0x46
diff 38 address 0x0000002a. Was 0x00 instead of 0x46
diff 39 address 0x0000002b. Was 0x00 instead of 0x46
diff 40 address 0x0000002c. Was 0x00 instead of 0x46
diff 41 address 0x0000002e. Was 0x00 instead of 0x62
diff 42 address 0x00000030. Was 0x00 instead of 0x0e
diff 43 address 0x00000031. Was 0x00 instead of 0x36
diff 44 address 0x00000032. Was 0x00 instead of 0x73
diff 45 address 0x00000033. Was 0x00 instead of 0x6c
diff 46 address 0x00000034. Was 0x00 instead of 0x78
diff 47 address 0x00000035. Was 0x00 instead of 0x32
diff 48 address 0x00000036. Was 0x00 instead of 0x35
diff 49 address 0x00000037. Was 0x00 instead of 0x74
diff 50 address 0x00000038. Was 0x00 instead of 0x63
diff 51 address 0x00000039. Was 0x00 instead of 0x73
diff 52 address 0x0000003a. Was 0x00 instead of 0x67
diff 53 address 0x0000003b. Was 0x00 instead of 0x33
diff 54 address 0x0000003c. Was 0x00 instead of 0x32
diff 55 address 0x0000003d. Was 0x00 instead of 0x34
diff 56 address 0x0000003f. Was 0x00 instead of 0x63
diff 57 address 0x00000041. Was 0x00 instead of 0x0b
diff 58 address 0x00000042. Was 0x00 instead of 0x32
diff 59 address 0x00000043. Was 0x00 instead of 0x30
diff 60 address 0x00000044. Was 0x00 instead of 0x31
diff 61 address 0x00000045. Was 0x00 instead of 0x35
diff 62 address 0x00000046. Was 0x00 instead of 0x2f
diff 63 address 0x00000047. Was 0x00 instead of 0x31
diff 64 address 0x00000048. Was 0x00 instead of 0x32
diff 65 address 0x00000049. Was 0x00 instead of 0x2f
diff 66 address 0x0000004a. Was 0x00 instead of 0x31
diff 67 address 0x0000004b. Was 0x00 instead of 0x31
diff 68 address 0x0000004d. Was 0x00 instead of 0x64
diff 69 address 0x0000004f. Was 0x00 instead of 0x09
diff 70 address 0x00000050. Was 0x00 instead of 0x30
diff 71 address 0x00000051. Was 0x00 instead of 0x39
diff 72 address 0x00000052. Was 0x00 instead of 0x3a
diff 73 address 0x00000053. Was 0x00 instead of 0x30
diff 74 address 0x00000054. Was 0x00 instead of 0x39
diff 75 address 0x00000055. Was 0x00 instead of 0x3a
diff 76 address 0x00000056. Was 0x00 instead of 0x34
diff 77 address 0x00000057. Was 0x00 instead of 0x34
diff 78 address 0x00000059. Was 0x00 instead of 0x65
diff 79 address 0x0000005b. Was 0x00 instead of 0x03
diff 80 address 0x0000005c. Was 0x00 instead of 0xba
diff 81 address 0x0000005d. Was 0x00 instead of 0xca
diff 82 address 0x0000005e. Was 0x00 instead of 0xff
diff 83 address 0x0000005f. Was 0x00 instead of 0xff
diff 84 address 0x00000060. Was 0x00 instead of 0xff
diff 85 address 0x00000061. Was 0x00 instead of 0xff
diff 86 address 0x00000062. Was 0x00 instead of 0xff
diff 87 address 0x00000063. Was 0x00 instead of 0xff
diff 88 address 0x00000064. Was 0x00 instead of 0xff
diff 89 address 0x00000065. Was 0x00 instead of 0xff
diff 90 address 0x00000066. Was 0x00 instead of 0xff
diff 91 address 0x00000067. Was 0x00 instead of 0xff
diff 92 address 0x00000068. Was 0x00 instead of 0xff
diff 93 address 0x00000069. Was 0x00 instead of 0xff
diff 94 address 0x0000006a. Was 0x00 instead of 0xff
diff 95 address 0x0000006b. Was 0x00 instead of 0xff
diff 96 address 0x0000006c. Was 0x00 instead of 0xff
diff 97 address 0x0000006d. Was 0x00 instead of 0xff
diff 98 address 0x0000006e. Was 0x00 instead of 0xaa
diff 99 address 0x0000006f. Was 0x00 instead of 0x99
diff 100 address 0x00000070. Was 0x00 instead of 0x55
diff 101 address 0x00000071. Was 0x00 instead of 0x66
diff 102 address 0x00000072. Was 0x00 instead of 0x30
diff 103 address 0x00000073. Was 0x00 instead of 0xa1
diff 104 address 0x00000075. Was 0x00 instead of 0x07
diff 105 address 0x00000076. Was 0x00 instead of 0x20
diff 106 address 0x00000078. Was 0x00 instead of 0x31
diff 107 address 0x00000079. Was 0x00 instead of 0xa1
diff 108 address 0x0000007a. Was 0x00 instead of 0x04
diff 109 address 0x0000007b. Was 0x00 instead of 0x88
diff 110 address 0x0000007c. Was 0x00 instead of 0x31
diff 111 address 0x0000007d. Was 0x00 instead of 0x41
diff 112 address 0x0000007e. Was 0x00 instead of 0x3d
diff 113 address 0x0000007f. Was 0x00 instead of 0x08
diff 114 address 0x00000080. Was 0x00 instead of 0x31
diff 115 address 0x00000081. Was 0x00 instead of 0x61
diff 116 address 0x00000082. Was 0x00 instead of 0x09
diff 117 address 0x00000083. Was 0x00 instead of 0xee
diff 118 address 0x00000084. Was 0x00 instead of 0x31
diff 119 address 0x00000085. Was 0x00 instead of 0xc2
diff 120 address 0x00000086. Was 0x00 instead of 0x04
diff 121 address 0x00000087. Was 0x00 instead of 0x02
diff 122 address 0x00000088. Was 0x00 instead of 0x40
diff 123 address 0x00000089. Was 0x00 instead of 0x93
diff 124 address 0x0000008a. Was 0x00 instead of 0x30
diff 125 address 0x0000008b. Was 0x00 instead of 0xe1
diff 126 address 0x0000008d. Was 0x00 instead of 0xcf
diff 127 address 0x0000008e. Was 0x00 instead of 0x30
More than 128 errors, the rest are not printed.

I'm not sure what I'm missing here, but I'm able to detect the flash chip, and I'm able to (sort of) wipe it. Any idea what the issue might be?

I got the bscan_spi_xc6slx25t.bit from here.

@AnantaSrikar
Copy link
Author

I think I figured out why its happening. I modified the configuration file as follows:

source [find interface/altera-usb-blaster.cfg]
source [find cpld/xilinx-xc6s.cfg]
source [find cpld/jtagspi.cfg]

adapter speed 100

init
jtagspi_init 0 bscan_spi_xc6slx25t.bit
xc6s_program xc6s.tap
flash write_image erase ledglow.bit 0;
flash verify_bank 0 ledglow.bit
shutdown

and upon running the above configuration, I got the following output:

openocd -f dragon-l-spi.cfg
Open On-Chip Debugger 0.12.0
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
Info : usb blaster interface using libftdi
Info : This adapter doesn't support configurable speed
Info : JTAG tap: xc6s.tap tap/device found: 0x24024093 (mfg: 0x049 (Xilinx), part: 0x4024, ver: 0x2)
Info : JTAG tap: xc6s.tap tap/device found: 0x24024093 (mfg: 0x049 (Xilinx), part: 0x4024, ver: 0x2)
Info : Found flash device 'st m25p80' (ID 0x142020)
Error: Cannot enable write to flash. Status=0x00
Error: Sector erase failed.
Error: failed erasing sectors 0 to 3
auto erase enabled

I think we have to send a WREN (Write enable) instruction before we attempt to write to the flash (as per the datasheet)

@trabucayre
Copy link
Owner

Hi,
I have received a board to do some tests, but unfortunately I have an issue with this board (maybe around the USB connector).
the WREN bit is always set before erasing or writing a sector. But this command (and many others) needs to have exactly 8bits (no more, no less), otherwise command is discarded.

@AnantaSrikar
Copy link
Author

Thank you for the update. I'm glad you received a board for testing, as that should indeed help with faster debugging. It's interesting that the WREN bit is always set before erasing or writing a sector.

Since you mentioned that the WREN isn't the issue, could you elaborate on what you think might be causing the problem?

Any additional information you can provide would be helpful in understanding the issue better. Let me know how else I can assist in troubleshooting this problem.

@trabucayre
Copy link
Owner

Hi Sorry for late answer: Issue with my board was related to a wrong USB connector (VCC connected to GND, and GND to VCC).
After some tests I have observed the FPGA immediately reboot after spiOverJtag's bitstream load. And managed to test some different bitstream with a classic flow instead of using edalize: to conclude the issue was related to bitgen's configuration where Unused Pins was not set to float.
With bdaba6e I'm able to detect and program the SPI flash.

Next step: adding spiflash and board definition, and a edalize's PR to allows user to provides more configurations.

@trabucayre
Copy link
Owner

  • spi flash definition added with 0d657f0
  • board definition added with 9edf1ed

@epoch101codes
Copy link

This is such good news! Thank you so much for debugging and finding a fix. However, I still have one small issue. I'm trying to use the -B dragonL flag and it doesn't seem to be working well with the -f flag. I'm able to flash to SPI ROM if i mention the fpga-part seperately. Below is the log file for your reference:

srikar@testboi:~/bitfiles $ sudo openFPGALoader -c usb-blaster -B dragonL ledglow.bit --verbose
empty
found 1 devices
index 0:
	idcode 0x24024093
	manufacturer xilinx
	family spartan6
	model  xc6slx25T
	irlength 6
File type : bit
Open file DONE
Parse file DONE
bitstream header infos
date: 2015/12/11
design_name: LEDglow.ncd
hour: 09:09:44
part_name: 6slx25tcsg324
toolVersion: 0xFFFFFFFF
userID: 0xFFFFFFFF
load program
Load SRAM: [==================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1
srikar@testboi:~/bitfiles $ sudo openFPGALoader -c usb-blaster --fpga-part xc6slx25tcsg324 -f ledblink.bit --verbose
empty
write to flash
found 1 devices
index 0:
	idcode 0x24024093
	manufacturer xilinx
	family spartan6
	model  xc6slx25T
	irlength 6
File type : bit
Open file DONE
Parse file DONE
bitstream header infos
date: 2024/05/22
design_name: ledblink.ncd
hour: 10:26:28
part_name: 6slx25tcsg324
toolVersion: 0xFFFFFFFF
userID: 0xFFFFFFFF
use: /usr/local/share/openFPGALoader/spiOverJtag_xc6slx25tcsg324.bit.gz
load program
Load SRAM: [==================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1
20 20 14 10 read 20201410
JEDEC ID: 0x202014
Detected: ST M25P80 16 sectors size: 8Mb
RDSR : 0x00
WIP  : 0
WEL  : 0
BP   : 0
TB   : 0
SRWD : 0
00000000 00000000 00000000 00
start addr: 00000000, end_addr: 000d0000
Erasing: [==================================================] 100.00%
Done
Writing: [==================================================] 100.00%
Done
srikar@testboi:~/bitfiles $ sudo openFPGALoader -c usb-blaster -B dragonL -f ledglow.bit --verbose
empty
write to flash
found 1 devices
index 0:
	idcode 0x24024093
	manufacturer xilinx
	family spartan6
	model  xc6slx25T
	irlength 6
File type : bit
Open file DONE
Parse file DONE
bitstream header infos
date: 2015/12/11
design_name: LEDglow.ncd
hour: 09:09:44
part_name: 6slx25tcsg324
toolVersion: 0xFFFFFFFF
userID: 0xFFFFFFFF
use: dragonL
Error: fail to open dragonL
Error: Failed to program FPGA: Error: fail to open dragonL
srikar@testboi:~/bitfiles $

Please let me know if I'm missing something. Thank you once again!

@trabucayre
Copy link
Owner

  • -B(upper 'b') is to specify the bitstream to you use as bridge. openFPGALoader will try to open the corresponding bitstream, and here, fails because there is no file called dragonL in the current directory.
  • -b (lower 'b') is to specify the board

To program the dragonL you have simply to use:

openFPGALoader -c usb-blaster -b dragonL -f YourBitStream

@epoch101codes
Copy link

Oh got it, that works perfectly. Thank you!

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
3 participants
@trabucayre @AnantaSrikar @epoch101codes