sim.tcl

# Copyright (c) 2016, Robert Eady
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#
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# modification, are permitted provided that the following conditions are met:
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vlib work

# used to enable trace by passing TRACE as an argument
if {$argc == 2} {
    vlog clarvi.sv +define+$2
} else {
    vlog clarvi.sv
}

vlog clarvi_avalon.sv
vlog bram.sv
vlog sim.sv

if {$argc > 0} {
    vsim work.clarvi_sim -GINIT_FILE=$1 -t ns -voptargs=+acc=npr
} else {
    vsim work.clarvi_sim -t ns -voptargs=+acc=npr
}

add wave -position insertpoint \
{/clarvi_sim/clock}