From 69bfef4fce04a1c00c0ca89a92305bc55020d3a6 Mon Sep 17 00:00:00 2001 From: Lux Zhang <78457898+iansseijelly@users.noreply.github.com> Date: Fri, 7 Feb 2025 17:31:15 -0800 Subject: [PATCH] ADD: submodule tacit & tacit decoder (#2172) * ADD: submodule tacit decoder * ADD: submodule tacit * ADD: config fragment for creating tacit rocket and shuttle designs * ADD: CI for tacit --- .github/scripts/check-commit.sh | 2 +- .github/scripts/defaults.sh | 3 +- .github/scripts/run-tests.sh | 3 ++ .github/workflows/chipyard-run-tests.yml | 26 ++++++++++- .gitmodules | 6 +++ build.sbt | 7 ++- .../chipyard/src/main/scala/DigitalTop.scala | 2 + .../src/main/scala/config/RocketConfigs.scala | 11 +++++ .../main/scala/config/ShuttleConfigs.scala | 10 +++++ .../config/fragments/TileFragments.scala | 45 ++++++++++++++++++- generators/shuttle | 2 +- generators/tacit | 1 + software/baremetal-ide | 2 +- software/tacit_decoder | 1 + 14 files changed, 114 insertions(+), 7 deletions(-) create mode 160000 generators/tacit create mode 160000 software/tacit_decoder diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index 8c3ed2a584..be880e7b25 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -46,7 +46,7 @@ search () { } -submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara" "vexiiriscv") +submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara" "vexiiriscv" "tacit") dir="generators" branches=("master" "main" "dev") search diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index f53e79830c..f2665bc8df 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -25,7 +25,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache # key value store to get the build groups declare -A grouping -grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle chipyard-shuttle3 chipyard-vexiiriscv" +grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle chipyard-shuttle3 chipyard-vexiiriscv chipyard-tacit-rocket" grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet" grouping["group-accels"]="chipyard-compressacc chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc chipyard-rocketvector chipyard-shuttlevector chipyard-hlsacc" # chipyard-shuttleara - Add when Ara works again grouping["group-constellation"]="chipyard-constellation" @@ -70,6 +70,7 @@ mapping["tracegen-boomv4"]=" CONFIG=BoomV4TraceGenConfig" mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig" mapping["chipyard-shuttle"]=" CONFIG=ShuttleConfig" mapping["chipyard-shuttle3"]=" CONFIG=Shuttle3WideConfig" +mapping["chipyard-tacit-rocket"]=" CONFIG=TacitRocketConfig" mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig" mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig" mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 2bf07feda0..117217337a 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -169,6 +169,9 @@ case $1 in chipyard-constellation) run_binary LOADMEM=1 BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv ;; + chipyard-tacit-rocket) + run_binary LOADMEM=1 BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv + ;; icenet) run_binary BINARY=none ;; diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index d08c402992..787352a9c0 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -534,6 +534,29 @@ jobs: with: group-key: "group-cores" project-key: "chipyard-shuttle3" + + chipyard-tacit-rocket-run-tests: + name: chipyard-tacit-rocket-run-tests + needs: prepare-chipyard-cores + runs-on: as4 + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v4 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-cores" + project-key: "chipyard-tacit-rocket" chipyard-cva6-run-tests: name: chipyard-cva6-run-tests @@ -1232,7 +1255,8 @@ jobs: chipyard-boomv3-run-tests, chipyard-boomv4-run-tests, chipyard-shuttle-run-tests, - chipyard-shuttle3-run-tests, + chipyard-shuttle3-run-tests, + chipyard-tacit-rocket-run-tests, chipyard-cva6-run-tests, chipyard-ibex-run-tests, chipyard-vexiiriscv-run-tests, diff --git a/.gitmodules b/.gitmodules index f9601158ec..90d327f8e1 100644 --- a/.gitmodules +++ b/.gitmodules @@ -151,3 +151,9 @@ [submodule "generators/vexiiriscv"] path = generators/vexiiriscv url = https://github.com/ucb-bar/vexiiriscv-tile.git +[submodule "software/tacit_decoder"] + path = software/tacit_decoder + url = https://github.com/ucb-bar/tacit_decoder.git +[submodule "generators/tacit"] + path = generators/tacit + url = https://github.com/ucb-bar/tacit.git diff --git a/build.sbt b/build.sbt index f50564e647..cb9e5709a8 100644 --- a/build.sbt +++ b/build.sbt @@ -158,7 +158,7 @@ lazy val chipyard = (project in file("generators/chipyard")) dsptools, rocket_dsp_utils, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, constellation, mempress, barf, shuttle, caliptra_aes, rerocc, - compressacc, saturn, ara, firrtl2_bridge, vexiiriscv) + compressacc, saturn, ara, firrtl2_bridge, vexiiriscv, tacit) .settings(libraryDependencies ++= rocketLibDeps.value) .settings( libraryDependencies ++= Seq( @@ -253,6 +253,11 @@ lazy val nvdla = (project in file("generators/nvdla")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) +lazy val tacit = (project in file("generators/tacit")) + .dependsOn(rocketchip, shuttle) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(commonSettings) + lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc")) .dependsOn(rocketchip, rocc_acc_utils, testchipip) .settings(libraryDependencies ++= rocketLibDeps.value) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index c4fa17aafa..f72d78ccb9 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -4,6 +4,7 @@ import chisel3._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ +import freechips.rocketchip.trace._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.tilelink._ @@ -13,6 +14,7 @@ import freechips.rocketchip.devices.tilelink._ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem + with tacit.CanHaveTraceSinkDMA with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index e9e4b2c4b5..d989f8cc5f 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -115,3 +115,14 @@ class SV48RocketConfig extends Config( new freechips.rocketchip.rocket.WithSV48 ++ new freechips.rocketchip.rocket.WithNHugeCores(1) ++ new chipyard.config.AbstractConfig) + +// Rocket with Tacit encoder and trace sinks +class TacitRocketConfig extends Config( + new tacit.WithTraceSinkDMA(1) ++ + new tacit.WithTraceSinkAlways(0) ++ + new chipyard.config.WithTraceArbiterMonitor ++ + new chipyard.config.WithTacitEncoder ++ + new chipyard.config.WithNPerfCounters(29) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.rocket.WithNHugeCores(1) ++ + new chipyard.config.AbstractConfig) \ No newline at end of file diff --git a/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala b/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala index 3f08de9fa5..9253b61dbc 100644 --- a/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala @@ -42,3 +42,13 @@ class GemminiShuttleConfig extends Config( new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accel new shuttle.common.WithNShuttleCores ++ new chipyard.config.AbstractConfig) + +// Shuttle with Tacit encoder and trace sinks +class TacitShuttleConfig extends Config( + new tacit.WithTraceSinkDMA(1) ++ + new tacit.WithTraceSinkAlways(0) ++ + new chipyard.config.WithTraceArbiterMonitor ++ + new chipyard.config.WithTacitEncoder ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new shuttle.common.WithNShuttleCores ++ + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala index 2f07ab9c53..0e24001215 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -6,6 +6,7 @@ import org.chipsalliance.cde.config.{Field, Parameters, Config} import freechips.rocketchip.tile._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} +import freechips.rocketchip.diplomacy._ import cva6.{CVA6TileAttachParams} import sodor.common.{SodorTileAttachParams} @@ -13,7 +14,9 @@ import ibex.{IbexTileAttachParams} import vexiiriscv.{VexiiRiscvTileAttachParams} import testchipip.cosim.{TracePortKey, TracePortParams} import barf.{TilePrefetchingMasterPortParams} - +import freechips.rocketchip.trace.{TraceEncoderParams, TraceCoreParams} +import tacit.{TacitEncoder} +import shuttle.common.{ShuttleTileAttachParams} class WithL2TLBs(entries: Int) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( @@ -64,6 +67,46 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => { } }) +// Add a Tacit encoder to each tile +class WithTacitEncoder extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + traceParams = Some(TraceEncoderParams( + encoderBaseAddr = 0x3000000 + tp.tileParams.tileId * 0x1000, + buildEncoder = (p: Parameters) => LazyModule(new TacitEncoder(new TraceCoreParams( + nGroups = 1, + xlen = tp.tileParams.core.xLen, + iaddrWidth = tp.tileParams.core.xLen + ), + bufferDepth = 16, + coreStages = 5)(p)), + useArbiterMonitor = false + )), + core = tp.tileParams.core.copy(enableTraceCoreIngress=true))) + case tp: ShuttleTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + traceParams = Some(TraceEncoderParams( + encoderBaseAddr = 0x3000000 + tp.tileParams.tileId * 0x1000, + buildEncoder = (p: Parameters) => LazyModule(new TacitEncoder(new TraceCoreParams( + nGroups = tp.tileParams.core.retireWidth, + xlen = tp.tileParams.core.xLen, + iaddrWidth = tp.tileParams.core.xLen + ), bufferDepth = 16, coreStages = 7)(p)), + useArbiterMonitor = false + )), + core = tp.tileParams.core.copy(enableTraceCoreIngress=true))) + } + }) + +// Add a monitor to RTL print the sinked packets into a file for debugging +class WithTraceArbiterMonitor extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + traceParams = Some(tp.tileParams.traceParams.get.copy(useArbiterMonitor = true)))) + case tp: ShuttleTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + traceParams = Some(tp.tileParams.traceParams.get.copy(useArbiterMonitor = true)))) + } +}) + class WithNPMPs(n: Int = 8) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( diff --git a/generators/shuttle b/generators/shuttle index 30fac1afa8..e37ce14416 160000 --- a/generators/shuttle +++ b/generators/shuttle @@ -1 +1 @@ -Subproject commit 30fac1afa8e16e93583da2ac01d9f82dadcc6df0 +Subproject commit e37ce144166a903861dfd7a8e9c8c7ae1714fc4a diff --git a/generators/tacit b/generators/tacit new file mode 160000 index 0000000000..73923941a9 --- /dev/null +++ b/generators/tacit @@ -0,0 +1 @@ +Subproject commit 73923941a9ef62eb24fb3fef2f0e1494db7f8cf5 diff --git a/software/baremetal-ide b/software/baremetal-ide index 7e423fb08e..1d3c44bb12 160000 --- a/software/baremetal-ide +++ b/software/baremetal-ide @@ -1 +1 @@ -Subproject commit 7e423fb08ea3ad5204bdd8398b68557a52f6e36a +Subproject commit 1d3c44bb120fc0e0a3df3a44b58f6c41c2a5106a diff --git a/software/tacit_decoder b/software/tacit_decoder new file mode 160000 index 0000000000..db38ff14bc --- /dev/null +++ b/software/tacit_decoder @@ -0,0 +1 @@ +Subproject commit db38ff14bc2a1285b17d106bfaa5909622a6092f