From 1d4fcdff2e8bd69e1a4a2ce96f625c142296262f Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Thu, 12 Dec 2024 22:20:18 -0800 Subject: [PATCH] comment out layout codegen --- codegen/src/lib.rs | 3 +- substrate/src/layout/conv.rs | 24 ++++----- substrate/src/types/mod.rs | 94 ++++++++++++++++++------------------ 3 files changed, 60 insertions(+), 61 deletions(-) diff --git a/codegen/src/lib.rs b/codegen/src/lib.rs index a48fb6ff..fd29f6b8 100644 --- a/codegen/src/lib.rs +++ b/codegen/src/lib.rs @@ -151,12 +151,11 @@ pub fn derive_io(input: TokenStream) -> TokenStream { let parsed = parse_macro_input!(input as DeriveInput); let input = handle_error!(IoInputReceiver::from_derive_input(&parsed)); let schematic = schematic_io(&input); - let layout = layout_io(&input); + // let layout = layout_io(&input); let io_core_impl = io_core_impl(&input, true); quote!( #io_core_impl #schematic - #layout ) .into() } diff --git a/substrate/src/layout/conv.rs b/substrate/src/layout/conv.rs index 8f732098..b4c42c04 100644 --- a/substrate/src/layout/conv.rs +++ b/substrate/src/layout/conv.rs @@ -26,13 +26,13 @@ pub(crate) struct LayirLibExportContext { conv: LayirLibConversion, } -/// An SCIR library with associated conversion metadata. +/// A LayIR library with associated conversion metadata. pub struct RawLib { - /// The SCIR library. + /// The LayIR library. pub layir: layir::Library, /// Associated conversion metadata. /// - /// Can be used to retrieve SCIR objects from their corresponding Substrate IDs. + /// Can be used to retrieve LayIR objects from their corresponding Substrate IDs. pub conv: LayirLibConversion, } @@ -58,12 +58,12 @@ impl LayirLibExportContext { pub struct LayirExportError; impl RawCell { - /// Export this cell and all subcells as a SCIR library. + /// Export this cell and all subcells as a LayIR library. /// - /// Returns the SCIR library and metadata for converting between SCIR and Substrate formats. + /// Returns the LayIR library and metadata for converting between LayIR and Substrate formats. /// - /// Consider using [`export_multi_top_scir_lib`] if you need to export multiple cells - /// to the same SCIR library. + /// Consider using [`export_multi_top_layir_lib`] if you need to export multiple cells + /// to the same LayIR library. pub(crate) fn to_layir_lib(&self) -> Result, LayirExportError> { let mut lib_ctx = LayirLibExportContext::new(); @@ -73,7 +73,7 @@ impl RawCell { }) } - /// Exports this [`RawCell`] to a SCIR cell if it has not already been exported. Should only be called + /// Exports this [`RawCell`] to a LayIR cell if it has not already been exported. Should only be called /// on top cells or un-flattened cells. fn to_layir_cell( &self, @@ -121,11 +121,11 @@ impl RawCell { } } -/// Export a collection of cells and all their subcells as a SCIR library. +/// Export a collection of cells and all their subcells as a LayIR library. /// -/// Returns the SCIR library and metadata for converting between SCIR and Substrate formats. -/// The resulting SCIR library will **not** have a top cell set. -/// If you want a SCIR library with a known top cell, consider using [`RawCell::to_scir_lib`] instead. +/// Returns the LayIR library and metadata for converting between LayIR and Substrate formats. +/// The resulting LayIR library will **not** have a top cell set. +/// If you want a LayIR library with a known top cell, consider using [`RawCell::to_layir_lib`] instead. pub(crate) fn export_multi_top_layir_lib( cells: &[&RawCell], ) -> Result, LayirExportError> { diff --git a/substrate/src/types/mod.rs b/substrate/src/types/mod.rs index aeb906c4..39f287f8 100644 --- a/substrate/src/types/mod.rs +++ b/substrate/src/types/mod.rs @@ -208,52 +208,52 @@ pub struct ArrayBundle { // BEGIN COMMON IO TYPES -// /// The interface to a standard 4-terminal MOSFET. -// #[derive(Debug, Default, Clone, Io)] -// pub struct MosIo { -// /// The drain. -// pub d: InOut, -// /// The gate. -// pub g: Input, -// /// The source. -// pub s: InOut, -// /// The body. -// pub b: InOut, -// } -// -// /// The interface to which simulation testbenches should conform. -// #[derive(Debug, Default, Clone, Io, PartialEq, Eq)] -// pub struct TestbenchIo { -// /// The global ground net. -// pub vss: InOut, -// } -// -// /// The interface for 2-terminal blocks. -// #[derive(Debug, Default, Clone, Io)] -// pub struct TwoTerminalIo { -// /// The positive terminal. -// pub p: InOut, -// /// The negative terminal. -// pub n: InOut, -// } -// -// /// The interface for VDD and VSS rails. -// #[derive(Debug, Default, Clone, Io)] -// pub struct PowerIo { -// /// The VDD rail. -// pub vdd: InOut, -// /// The VSS rail. -// pub vss: InOut, -// } -// -// /// A pair of differential signals. -// // TODO: Create proc macro for defining un-directioned (non-IO) bundle types directly. -// #[derive(Debug, Default, Copy, Clone, Io)] -// pub struct DiffPair { -// /// The positive signal. -// pub p: InOut, -// /// The negative signal. -// pub n: InOut, -// } +/// The interface to a standard 4-terminal MOSFET. +#[derive(Debug, Default, Clone, Io)] +pub struct MosIo { + /// The drain. + pub d: InOut, + /// The gate. + pub g: Input, + /// The source. + pub s: InOut, + /// The body. + pub b: InOut, +} + +/// The interface to which simulation testbenches should conform. +#[derive(Debug, Default, Clone, Io, PartialEq, Eq)] +pub struct TestbenchIo { + /// The global ground net. + pub vss: InOut, +} + +/// The interface for 2-terminal blocks. +#[derive(Debug, Default, Clone, Io)] +pub struct TwoTerminalIo { + /// The positive terminal. + pub p: InOut, + /// The negative terminal. + pub n: InOut, +} + +/// The interface for VDD and VSS rails. +#[derive(Debug, Default, Clone, Io)] +pub struct PowerIo { + /// The VDD rail. + pub vdd: InOut, + /// The VSS rail. + pub vss: InOut, +} + +/// A pair of differential signals. +// TODO: Create proc macro for defining un-directioned (non-IO) bundle types directly. +#[derive(Debug, Default, Copy, Clone, Io)] +pub struct DiffPair { + /// The positive signal. + pub p: InOut, + /// The negative signal. + pub n: InOut, +} // END COMMON IO TYPES