D2D adapter CRC calculation

[rahulk29]

Relevant spec sections: 3.7
The CRC module accepts a 128 byte message and produces a 2 byte CRC according to the CRC polynomial in the spec. The two CRC bytes are called CRC 0 and 1, respectively.

The UCIe spec provides a reference CRC implementation in SystemVerilog. For whatever reason, this reference implementation is only in the UCIe 1.0 spec (look for crc_gen in the 1.0 spec).
Request the UCIe 1.0 spec here.

Since the reference implementation is in SystemVerilog, which has limited parametrization ability, it is pretty ugly. We should re-implement it cleanly in Chisel.

• Define the CRC Generator IOs in Chisel
• Implement CRC computation in Chisel
• Set up testbench to ensure Chisel CRC output matches reference implementation