diff --git a/src/main/resources/vsrc/AsyncFifoCustomCore.sv b/src/main/resources/vsrc/AsyncFifoCustomCore.sv new file mode 100644 index 0000000..cfca7e7 --- /dev/null +++ b/src/main/resources/vsrc/AsyncFifoCustomCore.sv @@ -0,0 +1,200 @@ +// Code your design here +module AsyncFifoCustomCore #( + parameter DEPTH = 16, + parameter WIDTH = 8 +)( + input rst, + + input clk_w, + input valid_w, + output ready_w, + input [WIDTH-1:0] data_w, + + input clk_r, + output valid_r, + input ready_r, + output [WIDTH-1:0] data_r +); + localparam PTR_WIDTH = $clog2(DEPTH); + + + wire [PTR_WIDTH:0] b_wptr; + wire [PTR_WIDTH:0] b_rptr; + wire [PTR_WIDTH:0] g_wptr; + wire [PTR_WIDTH:0] g_rptr; + wire [PTR_WIDTH:0] g_wptr_sync; + wire [PTR_WIDTH:0] g_rptr_sync; + wire full, empty; + + Sync2Flop #(PTR_WIDTH + 1) wptrSync (.clk(clk_w), .rst(rst), .in(g_wptr), .out(g_wptr_sync)); + Sync2Flop #(PTR_WIDTH + 1) rptrSync (.clk(clk_r), .rst(rst), .in(g_rptr), .out(g_rptr_sync)); + WptrHandler #(PTR_WIDTH) wptrHandler (.clk(clk_w), .rst(rst), .en(valid_w), .g_rptr_sync(g_rptr_sync), + .g_wptr(g_wptr), .b_wptr(b_wptr), .full(full)); + RptrHandler #(PTR_WIDTH) rptrHandler (.clk(clk_r), .rst(rst), .en(ready_r), .g_wptr_sync(g_wptr_sync), + .g_rptr(g_rptr), .b_rptr(b_rptr), .empty(empty)); + Fifo #(PTR_WIDTH, WIDTH) fifo (.rst(rst), + .clk_w(clk_w), .en_w(valid_w), .data_w(data_w), .b_wptr(b_wptr), .full(full), + .clk_r(clk_r), .en_r(ready_r), .data_r(data_r), .b_rptr(b_rptr), .empty(empty)); + assign valid_r = ~empty; + assign ready_w = ~full; + +endmodule + +module Sync2Flop #( + parameter PTR_WIDTH = 8 +)( + input clk, + input rst, + input [PTR_WIDTH-1:0] in, + output reg [PTR_WIDTH-1:0] out +); + reg [PTR_WIDTH-1:0] mid; + always_ff @(posedge clk, negedge rst) begin + if (~rst) begin + out <= '0; + mid <= '0; + end else begin + out <= mid; + mid <= in; + end + end +endmodule + +module WptrHandler #( + parameter PTR_WIDTH = 8 +)( + input clk, + input rst, + input en, + input [PTR_WIDTH:0] g_rptr_sync, + output reg [PTR_WIDTH:0] g_wptr, b_wptr, + output reg full +); + wire [PTR_WIDTH:0] g_wptr_next; + wire [PTR_WIDTH:0] b_wptr_next; + wire full_next; + + assign b_wptr_next = b_wptr + (en & ~full); + assign g_wptr_next = b_wptr_next ^ (b_wptr_next >> 1); + assign full_next = g_wptr_next == {~g_rptr_sync[PTR_WIDTH:PTR_WIDTH-1], g_rptr_sync[PTR_WIDTH-2:0]}; + + always_ff @(posedge clk, negedge rst) begin + if(~rst) begin + g_wptr <= '0; + b_wptr <= '0; + full <= '0; + // g_wptr <= g_wptr_next; + // b_wptr <= b_wptr_next; + // full <= full_next; + end else begin + g_wptr <= g_wptr_next; + b_wptr <= b_wptr_next; + full <= full_next; + end + end + +endmodule + +module RptrHandler #( + parameter PTR_WIDTH = 8 +)( + input clk, + input rst, + input en, + input [PTR_WIDTH:0] g_wptr_sync, + output reg [PTR_WIDTH:0] g_rptr, b_rptr, + output reg empty +); + wire [PTR_WIDTH:0] g_rptr_next; + wire [PTR_WIDTH:0] b_rptr_next; + wire empty_next; + + assign b_rptr_next = b_rptr + (en & ~empty); + assign g_rptr_next = b_rptr_next ^ (b_rptr_next >> 1); + assign empty_next = g_rptr_next == g_wptr_sync; + + always_ff @(posedge clk, negedge rst) begin + if(~rst) begin + g_rptr <= '0; + b_rptr <= '0; + empty <= '1; + end else begin + g_rptr <= g_rptr_next; + b_rptr <= b_rptr_next; + empty <= empty_next; + end + end + +endmodule + +module Fifo #( + parameter PTR_WIDTH = 8, + parameter WIDTH = 8 +)( + input rst, + // Write + input [WIDTH-1:0] data_w, + input clk_w, + input en_w, + input [PTR_WIDTH:0] b_wptr, + input full, + // Read + output reg [WIDTH-1:0] data_r, + input clk_r, + input en_r, + input [PTR_WIDTH:0] b_rptr, + input empty +); + localparam ENTRIES = 2**PTR_WIDTH; + integer i; + reg [WIDTH-1:0] fifoBank [0:ENTRIES-1]; + always_ff @(posedge clk_w, negedge rst) begin + if(~rst) begin + for(i = 0; i < ENTRIES; i++) begin + fifoBank[i] <= 'b0; + end + end else if (en_w & ~full) begin + fifoBank[b_wptr[PTR_WIDTH-1:0]] <= data_w; + end else begin + for(i = 0; i < ENTRIES; i++) begin + fifoBank[i] <= fifoBank[i]; + end + end + end + + // always_ff @(posedge clk_r) begin + // if(en_r & ~empty) begin + // data_r <= fifoBank[b_rptr[PTR_WIDTH-1:0]]; + // end + // end + + assign data_r = fifoBank[b_rptr[PTR_WIDTH-1:0]]; +endmodule + +module BinaryToGray #( + parameter WIDTH = 8 +)( + input [WIDTH-1:0] in, + output [WIDTH-1:0] out +); + +genvar i; +assign out[WIDTH-1] = in[WIDTH - 1]; +for(i = WIDTH - 2; i >= 0; i--) begin + assign out[i] = in[i] ^ in[i + 1]; +end + +endmodule + +module GrayToBinary #( + parameter WIDTH = 8 +)( + input [WIDTH-1:0] in, + output [WIDTH-1:0] out +); +genvar i; +assign out[WIDTH-1] = in[WIDTH - 1]; +for(i = WIDTH - 2; i >= 0; i--) begin + assign out[i] = ^(in >> i); +end +endmodule \ No newline at end of file diff --git a/src/main/resources/vsrc/ClockSelector.v b/src/main/resources/vsrc/ClockSelector.v new file mode 100644 index 0000000..7b8b2b5 --- /dev/null +++ b/src/main/resources/vsrc/ClockSelector.v @@ -0,0 +1,14 @@ +module ClockMux2 ( + input clocksIn_0, + input clocksIn_1, + input sel, + output clockOut +); + + // REPLACE ME WITH A CLOCK CELL IF DESIRED + + // XXX be careful with this! You can get really nasty short edges if you + // don't switch carefully + assign clockOut = sel ? clocksIn_1 : clocksIn_0; + +endmodule \ No newline at end of file diff --git a/src/main/resources/vsrc/SBDeserializer.v b/src/main/resources/vsrc/SBDeserializer.v new file mode 100644 index 0000000..d27bd52 --- /dev/null +++ b/src/main/resources/vsrc/SBDeserializer.v @@ -0,0 +1,45 @@ +module SBDeserializerBlackBox #( + parameter WIDTH = 128, + parameter WIDTH_W = $clog2(WIDTH) +) ( + input clk, + input rst, + input in_data, + output [WIDTH - 1:0] out_data, + output out_data_valid + +); + +reg [WIDTH_W-1:0] counter; +reg [WIDTH-1:0] data_reg; +reg receiving; +wire recvDone; + +assign out_data = data_reg; +assign recvDone = counter == (WIDTH - 1); +assign out_data_valid = !receiving; + +always @(negedge clk or posedge rst) begin + if (rst) begin + counter <= 0; + receiving <= 1'b1; + end else begin + if (recvDone) begin + counter <= 0; + receiving <= 1'b0; + end else begin + counter <= counter + 1'b1; + receiving <= 1'b1; + end + + // if (out_data_valid && out_data_ready) begin + // receiving <= 1'b1; + // end + + data_reg[counter] <= in_data; + + end + +end + +endmodule \ No newline at end of file diff --git a/src/main/resources/vsrc/SBSerializer.v b/src/main/resources/vsrc/SBSerializer.v new file mode 100644 index 0000000..b1e8322 --- /dev/null +++ b/src/main/resources/vsrc/SBSerializer.v @@ -0,0 +1,13 @@ +module SBSerializerBlackBox #( + parameter WIDTH = 128, + parameter WIDTH_W = $clog2(WIDTH) +) ( + + input clk, + input rst, + input [WIDTH - 1:0] in_data, + output out_data + + ); + +endmodule \ No newline at end of file diff --git a/src/main/scala/d2dadapter/D2DSidebandModule.scala b/src/main/scala/d2dadapter/D2DSidebandModule.scala index 3f3ccac..55fd0cc 100644 --- a/src/main/scala/d2dadapter/D2DSidebandModule.scala +++ b/src/main/scala/d2dadapter/D2DSidebandModule.scala @@ -65,39 +65,39 @@ class D2DSidebandModule(val fdiParams: FdiParams, val sbParams: SidebandParams) sideband_switch.io.inner.layer_to_node_above.bits := 0.U(sbParams.sbNodeMsgWidth.W) sideband_switch.io.inner.layer_to_node_above.valid := false.B - sideband_switch.io.inner.node_to_layer_below.ready := false.B + sideband_switch.io.inner.node_to_layer_below.ready := true.B sideband_switch.io.inner.node_to_layer_above.ready := true.B - when(sideband_switch.io.inner.node_to_layer_above.valid && sideband_switch.io.inner.node_to_layer_above.ready){ - when(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_REQ_ACTIVE){ + when(sideband_switch.io.inner.node_to_layer_below.valid && sideband_switch.io.inner.node_to_layer_below.ready){ + when(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_REQ_ACTIVE){ io.sideband_rcv := SideBandMessage.REQ_ACTIVE - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_REQ_L1){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_REQ_L1){ io.sideband_rcv := SideBandMessage.REQ_L1 - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_REQ_L2){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_REQ_L2){ io.sideband_rcv := SideBandMessage.REQ_L2 - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_REQ_LINK_RESET){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_REQ_LINK_RESET){ io.sideband_rcv := SideBandMessage.REQ_LINKRESET - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_REQ_DISABLE){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_REQ_DISABLE){ io.sideband_rcv := SideBandMessage.REQ_DISABLED - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_RSP_ACTIVE){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_RSP_ACTIVE){ io.sideband_rcv := SideBandMessage.RSP_ACTIVE - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_RSP_PM_NAK){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_RSP_PM_NAK){ io.sideband_rcv := SideBandMessage.RSP_PMNAK - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_RSP_L1){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_RSP_L1){ io.sideband_rcv := SideBandMessage.RSP_L1 - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_RSP_L2){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_RSP_L2){ io.sideband_rcv := SideBandMessage.RSP_L2 - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_RSP_LINK_RESET){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_RSP_LINK_RESET){ io.sideband_rcv := SideBandMessage.RSP_LINKRESET - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_RSP_DISABLE){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_RSP_DISABLE){ io.sideband_rcv := SideBandMessage.RSP_DISABLED - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.PARITY_FEATURE_REQ){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.PARITY_FEATURE_REQ){ io.sideband_rcv := SideBandMessage.PARITY_FEATURE_REQ - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.PARITY_FEATURE_ACK){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.PARITY_FEATURE_ACK){ io.sideband_rcv := SideBandMessage.PARITY_FEATURE_ACK - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.PARITY_FEATURE_NAK){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.PARITY_FEATURE_NAK){ io.sideband_rcv := SideBandMessage.PARITY_FEATURE_NAK - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.ADV_CAP){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.ADV_CAP){ io.sideband_rcv := SideBandMessage.ADV_CAP }.otherwise{ io.sideband_rcv := SideBandMessage.NOP diff --git a/src/main/scala/d2dadapter/LinkInitSubmodule.scala b/src/main/scala/d2dadapter/LinkInitSubmodule.scala index c5b443a..0dee3a5 100644 --- a/src/main/scala/d2dadapter/LinkInitSubmodule.scala +++ b/src/main/scala/d2dadapter/LinkInitSubmodule.scala @@ -195,6 +195,14 @@ class LinkInitSubmodule() extends Module { linkinit_state_reg := LinkInitState.INIT_DONE } } + }.elsewhen(io.link_state === PhyState.active){ + io.active_entry := true.B + io.linkinit_fdi_pl_state_sts := PhyState.active + io.linkinit_fdi_pl_rxactive_req := true.B + io.linkinit_fdi_pl_inband_pres := true.B + io.linkinit_rdi_lp_state_req := PhyStateReq.active + io.linkinit_sb_snd := SideBandMessage.NOP + linkinit_state_reg := LinkInitState.INIT_DONE }.otherwise{ linkinit_state_reg := LinkInitState.INIT_START io.active_entry := false.B diff --git a/src/main/scala/e2e/UCITop.scala b/src/main/scala/e2e/UCITop.scala index f8058d0..6f4245b 100644 --- a/src/main/scala/e2e/UCITop.scala +++ b/src/main/scala/e2e/UCITop.scala @@ -4,6 +4,7 @@ package e2e import chisel3._ import chisel3.util._ +import afe._ import interfaces._ import sideband._ import protocol._ @@ -11,46 +12,61 @@ import d2dadapter._ import logphy._ import freechips.rocketchip.util.AsyncQueueParams -/** - * UCITop is the main class which instantiates all the three - * layers of the UCIe protocol stack - * +/** UCITop is the main class which instantiates all the three layers of the UCIe + * protocol stack */ -class UCITop(val fdiParams: FdiParams, val rdiParams: RdiParams, - val sbParams: SidebandParams, val myId: BigInt, - val linkTrainingParams: LinkTrainingParams, - val afeParams: AfeParams, - val laneAsyncQueueParams: AsyncQueueParams) extends Module { - val io = IO(new Bundle{ - // IOs for connecting to the protocol layer - //val fdi = new Fdi(fdiParams) - val fdi_lpConfig = Valid(Bits(fdiParams.sbWidth.W)) - val fdi_lpConfigCredit = Input(Bool()) - val fdi_plConfig = Flipped(Valid(Bits(fdiParams.sbWidth.W))) - val fdi_plConfigCredit = Output(Bool()) - val fdi_lpStallAck = Output(Bool()) - val TLplStateStatus = Output(PhyState()) +class UCITop( + val fdiParams: FdiParams, + val rdiParams: RdiParams, + val sbParams: SidebandParams, + val linkTrainingParams: LinkTrainingParams, + val afeParams: AfeParams, + val laneAsyncQueueParams: AsyncQueueParams, +) extends Module { + val io = IO(new Bundle { + // IOs for connecting to the protocol layer + // val fdi = new Fdi(fdiParams) + val fdi_lpConfig = Valid(Bits(fdiParams.sbWidth.W)) + val fdi_lpConfigCredit = Input(Bool()) + val fdi_plConfig = Flipped(Valid(Bits(fdiParams.sbWidth.W))) + val fdi_plConfigCredit = Output(Bool()) + val fdi_lpStallAck = Output(Bool()) + val TLplStateStatus = Output(PhyState()) - val TLlpData_valid = Input(Bool()) - val TLlpData_bits = Input(Bits((8 * fdiParams.width).W)) - val TLlpData_irdy = Input(Bool()) - val TLlpData_ready = Output(Bool()) - val TLplData_bits = Output(Bits((8 * fdiParams.width).W)) - val TLplData_valid = Output(Bool()) - val TLready_to_rcv = Input(Bool()) - val fault = Input(Bool()) - val soft_reset = Input(Bool()) - // IOs for connecting to the AFE - val mbAfe = new MainbandAfeIo(afeParams) - val sbAfe = new SidebandAfeIo(afeParams) - }) + val TLlpData_valid = Input(Bool()) + val TLlpData_bits = Input(Bits((8 * fdiParams.width).W)) + val TLlpData_irdy = Input(Bool()) + val TLlpData_ready = Output(Bool()) + val TLplData_bits = Output(Bits((8 * fdiParams.width).W)) + val TLplData_valid = Output(Bool()) + val TLready_to_rcv = Input(Bool()) + val fault = Input(Bool()) + val soft_reset = Input(Bool()) + // IOs for connecting to the AFE + // val mbAfe = new MainbandAfeIo(afeParams) + val mbAfe_tx = Output(new MainbandIo(afeParams.mbLanes)) + val mbAfe_rx = Input(new MainbandIo(afeParams.mbLanes)) + val sbTxIO = Output(new SidebandIo) + val sbRxIO = Input(new SidebandIo) + }) // Instantiate the agnostic protocol layer val protocol = Module(new ProtocolLayer(fdiParams)) // Instantiate the D2D adapter val d2dadapter = Module(new D2DAdapter(fdiParams, rdiParams, sbParams)) // Instantiate the logPhy - val logPhy = Module(new LogicalPhy(myId, linkTrainingParams, afeParams, rdiParams, fdiParams, sbParams, laneAsyncQueueParams)) + val logPhy = Module( + new LogicalPhy( + linkTrainingParams, + afeParams, + rdiParams, + fdiParams, + sbParams, + laneAsyncQueueParams, + ), + ) + + val dafe = Module(new MbAfe(afeParams)) // Connect the FDI interface of Protocol layer to D2D adapter protocol.io.fdi <> d2dadapter.io.fdi @@ -58,19 +74,33 @@ class UCITop(val fdiParams: FdiParams, val rdiParams: RdiParams, // Connect the RDI interface of D2D adapter to logPhy d2dadapter.io.rdi <> logPhy.io.rdi - // Connect the AFE interface from logPhy to the top - io.mbAfe <> logPhy.io.mbAfe - io.sbAfe <> logPhy.io.sbAfe + /** Sideband AFE connections (ser/des in logphy) + */ + io.sbTxIO.clk := logPhy.io.sbAfe.txClock + io.sbTxIO.data := logPhy.io.sbAfe.txData + logPhy.io.sbAfe.pllLock := true.B + logPhy.io.sbAfe.rxClock := io.sbRxIO.clk + logPhy.io.sbAfe.rxData := io.sbRxIO.data + + /** Mainband AFE connections to toplevel IOs + */ + io.mbAfe_tx <> dafe.io.mbTxData + io.mbAfe_rx <> dafe.io.mbRxData - // Connect the protocol IOs to the top for connections to the tilelink interface - //io.fdi <> protocol.io.fdi + /** Logphy connections to Digital AFE + */ + logPhy.io.mbAfe <> dafe.io.mbAfeIo + + /* Connect the protocol IOs to the top for connections to the tilelink + * interface */ + // io.fdi <> protocol.io.fdi io.fdi_lpConfig <> protocol.io.fdi.lpConfig io.fdi_lpConfigCredit <> protocol.io.fdi.lpConfigCredit io.fdi_plConfig <> protocol.io.fdi.plConfig io.fdi_plConfigCredit <> protocol.io.fdi.plConfigCredit io.fdi_lpStallAck <> protocol.io.fdi.lpStallAck io.TLplStateStatus <> protocol.io.TLplStateStatus - + protocol.io.TLlpData_valid := io.TLlpData_valid protocol.io.TLlpData_bits := io.TLlpData_bits protocol.io.TLlpData_irdy := io.TLlpData_irdy @@ -81,4 +111,4 @@ class UCITop(val fdiParams: FdiParams, val rdiParams: RdiParams, protocol.io.fault := io.fault protocol.io.soft_reset := io.soft_reset -} \ No newline at end of file +} diff --git a/src/main/scala/interfaces/Afe.scala b/src/main/scala/interfaces/Afe.scala index 88b62ce..e5e3b64 100644 --- a/src/main/scala/interfaces/Afe.scala +++ b/src/main/scala/interfaces/Afe.scala @@ -25,7 +25,7 @@ class MainbandIo(lanes: Int = 16) extends Bundle { */ class SidebandIo extends Bundle { val data = Bool() - val clk = Clock() + val clk = Bool() } /** The pins (mainband and sideband) exposed by a standard package UCIe module @@ -62,8 +62,6 @@ class SidebandAfeIo( afeParams: AfeParams, ) extends Bundle { - val fifoParams = Input(new FifoParams()) - /** Data to transmit on the sideband. * * Output from the async FIFO. diff --git a/src/main/scala/logphy/Lanes.scala b/src/main/scala/logphy/Lanes.scala index 7be48ce..c8ccd09 100644 --- a/src/main/scala/logphy/Lanes.scala +++ b/src/main/scala/logphy/Lanes.scala @@ -55,12 +55,12 @@ class Lanes( ) for (i <- 0 until afeParams.mbLanes) { for (j <- 0 until ratioBytes) { - txDataVec(afeParams.mbLanes - 1 - i)(j) := io.mainbandLaneIO.txData + txDataVec(i)(ratioBytes - 1 - j) := io.mainbandLaneIO.txData .bits( afeParams.mbLanes * 8 * j + (i * 8) + 7, afeParams.mbLanes * 8 * j + (i * 8), ) - rxDataVec(j)(afeParams.mbLanes - 1 - i) := rxMBFifo.io.deq + rxDataVec(ratioBytes - 1 - j)(i) := rxMBFifo.io.deq .bits(i)((j + 1) * 8 - 1, j * 8) } txMBFifo.io.enq.bits(i) := txDataVec(i).asUInt @@ -121,12 +121,12 @@ class SimLanes( ) for (i <- 0 until afeParams.mbLanes) { for (j <- 0 until ratioBytes) { - txDataVec(afeParams.mbLanes - 1 - i)(j) := io.mainbandLaneIO.txData + txDataVec(i)(ratioBytes - 1 - j) := io.mainbandLaneIO.txData .bits( afeParams.mbLanes * 8 * j + (i * 8) + 7, afeParams.mbLanes * 8 * j + (i * 8), ) - rxDataVec(j)(afeParams.mbLanes - 1 - i) := rxMBFifo.io.deq + rxDataVec(ratioBytes - 1 - j)(i) := rxMBFifo.io.deq .bits(i)((j + 1) * 8 - 1, j * 8) } txMBFifo.io.enq.bits(i) := txDataVec(i).asUInt diff --git a/src/main/scala/logphy/LinkTrainingFSM.scala b/src/main/scala/logphy/LinkTrainingFSM.scala index 699c1eb..09f6d7d 100644 --- a/src/main/scala/logphy/LinkTrainingFSM.scala +++ b/src/main/scala/logphy/LinkTrainingFSM.scala @@ -72,14 +72,23 @@ class LinkTrainingFSM( sbMsgWrapper.io.trainIO.msgReq.noenq() sbMsgWrapper.io.trainIO.msgReqStatus.nodeq() - io.sidebandFSMIO.patternTxData <> patternGenerator.io.sidebandLaneIO.txData - io.sidebandFSMIO.packetTxData <> sbMsgWrapper.io.laneIO.txData when(msgSource === MsgSource.PATTERN_GENERATOR) { io.sidebandFSMIO.rxData <> patternGenerator.io.sidebandLaneIO.rxData sbMsgWrapper.io.laneIO.rxData.noenq() + sbMsgWrapper.io.laneIO.txData.nodeq() + io.sidebandFSMIO.patternTxData <> patternGenerator.io.sidebandLaneIO.txData + io.sidebandFSMIO.packetTxData.noenq() }.otherwise { io.sidebandFSMIO.rxData <> sbMsgWrapper.io.laneIO.rxData patternGenerator.io.sidebandLaneIO.rxData.noenq() + patternGenerator.io.sidebandLaneIO.txData.nodeq() + when(io.sidebandFSMIO.rxMode === RXTXMode.RAW) { + io.sidebandFSMIO.patternTxData <> sbMsgWrapper.io.laneIO.txData + io.sidebandFSMIO.packetTxData.noenq() + }.otherwise { + io.sidebandFSMIO.patternTxData.noenq() + io.sidebandFSMIO.packetTxData <> sbMsgWrapper.io.laneIO.txData + } } private val currentState = RegInit(LinkTrainingState.reset) @@ -268,6 +277,7 @@ class LinkTrainingFSM( true, "PHY", ) + sbMsgWrapper.io.trainIO.msgReq.bits.repeat := true.B /* sbMsgWrapper.io.trainIO.msgReq.bits.reqType := * MessageRequestType.MSG_EXCH */ // sbMsgWrapper.io.trainIO.msgReq.bits.msgTypeHasData := false.B @@ -302,9 +312,7 @@ class LinkTrainingFSM( true, "PHY", ) - /* sbMsgWrapper.io.trainIO.msgReq.bits.reqType := - * MessageRequestType.MSG_REQ */ - // sbMsgWrapper.io.trainIO.msgReq.bits.msgTypeHasData := false.B + sbMsgWrapper.io.trainIO.msgReq.bits.repeat := false.B sbMsgWrapper.io.trainIO.msgReq.valid := true.B sbMsgWrapper.io.trainIO.msgReq.bits.timeoutCycles := ( 0.008 * sbClockFreq, @@ -335,8 +343,7 @@ class LinkTrainingFSM( remote = true, "PHY", ) - /* sbMsgWrapper.io.trainIO.msgReq.bits.reqType := - * MessageRequestType.MSG_RESP */ + sbMsgWrapper.io.trainIO.msgReq.bits.repeat := false.B sbMsgWrapper.io.trainIO.msgReq.valid := true.B // sbMsgWrapper.io.trainIO.msgReq.bits.msgTypeHasData := false.B msgSource := MsgSource.SB_MSG_WRAPPER diff --git a/src/main/scala/logphy/LogPhyTypes.scala b/src/main/scala/logphy/LogPhyTypes.scala index 0cc764c..3ac9e3b 100644 --- a/src/main/scala/logphy/LogPhyTypes.scala +++ b/src/main/scala/logphy/LogPhyTypes.scala @@ -31,7 +31,7 @@ class SBReqMsg extends Bundle { class MessageRequest extends Bundle { val msg = UInt(128.W) val timeoutCycles = UInt(64.W) - // val msgTypeHasData = Bool() + val repeat = Bool() } class MessageRequestStatus extends Bundle { diff --git a/src/main/scala/logphy/LogicalPhy.scala b/src/main/scala/logphy/LogicalPhy.scala index 75f3409..0715cc3 100644 --- a/src/main/scala/logphy/LogicalPhy.scala +++ b/src/main/scala/logphy/LogicalPhy.scala @@ -7,7 +7,6 @@ import chisel3._ import freechips.rocketchip.util.AsyncQueueParams class LogicalPhy( - myId: BigInt, linkTrainingParams: LinkTrainingParams, afeParams: AfeParams, rdiParams: RdiParams, @@ -63,7 +62,7 @@ class LogicalPhy( io.rdi.lpLinkError <> trainingModule.io.rdi.rdiBringupIO.lpLinkError /** TODO: is this correct behavior, look at spec */ - io.rdi.plInbandPres := trainingModule.io.currentState === LinkTrainingState.active + io.rdi.plInbandPres := trainingModule.io.currentState === LinkTrainingState.linkInit || trainingModule.io.currentState === LinkTrainingState.active val rdiDataMapper = Module(new RdiDataMapper(rdiParams, afeParams)) @@ -80,7 +79,7 @@ class LogicalPhy( io.rdi.plData <> rdiDataMapper.io.rdi.plData private val sidebandChannel = - Module(new PHYSidebandChannel(myId, sbParams, fdiParams)) + Module(new PHYSidebandChannel(sbParams = sbParams, fdiParams = fdiParams)) assert( afeParams.sbSerializerRatio == 1, "connecting sideband module directly to training module, sb serializer ratio must be 1!", diff --git a/src/main/scala/logphy/MBInitFSM.scala b/src/main/scala/logphy/MBInitFSM.scala index 1b88d61..8d28601 100644 --- a/src/main/scala/logphy/MBInitFSM.scala +++ b/src/main/scala/logphy/MBInitFSM.scala @@ -113,6 +113,7 @@ class MBInitFSM( "PHY", data, ) + msgReq.repeat := false.B // msgReq.msgTypeHasData := true.B msgReq.timeoutCycles := (0.008 * sbClockFreq).toInt.U diff --git a/src/main/scala/logphy/RdiBringup.scala b/src/main/scala/logphy/RdiBringup.scala index 6c98fc7..3854389 100644 --- a/src/main/scala/logphy/RdiBringup.scala +++ b/src/main/scala/logphy/RdiBringup.scala @@ -52,6 +52,7 @@ class RdiBringup extends Module { private val nextState = WireInit(state) io.active := state === PhyState.active io.sbTrainIO.msgReq.noenq() + io.sbTrainIO.msgReq.bits.repeat := false.B io.sbTrainIO.msgReqStatus.nodeq() state := nextState when(io.internalError || io.rdiIO.lpLinkError) { @@ -122,7 +123,7 @@ class RdiBringup extends Module { /** TODO: how many timeout cycles here? */ io.sbTrainIO.msgReq.bits.timeoutCycles := 1_000_000.U - when(io.sbTrainIO.msgReqStatus.fire) { + when(io.sbTrainIO.msgReq.fire) { resetSubstate := ResetSubState.RESP_ACTIVE_WAIT } } diff --git a/src/main/scala/logphy/SBMsgWrapper.scala b/src/main/scala/logphy/SBMsgWrapper.scala index 79a6bbe..e18039a 100644 --- a/src/main/scala/logphy/SBMsgWrapper.scala +++ b/src/main/scala/logphy/SBMsgWrapper.scala @@ -48,6 +48,7 @@ class SBMsgWrapper( // private val currentReqHasData = RegInit(false.B) private val currentReqTimeoutMax = RegInit(0.U(64.W)) private val currentStatus = RegInit(MessageRequestStatusType.ERR) + private val repeat = RegInit(false.B) private val dataOut = RegInit(0.U(64.W)) io.trainIO.msgReqStatus.bits.data := dataOut @@ -62,20 +63,9 @@ class SBMsgWrapper( io.trainIO.msgReq.ready := true.B when(io.trainIO.msgReq.fire) { currentReq := io.trainIO.msgReq.bits.msg - // currentReqHasData := io.trainIO.msgReq.bits.msgTypeHasData currentReqTimeoutMax := io.trainIO.msgReq.bits.timeoutCycles + repeat := io.trainIO.msgReq.bits.repeat nextState := State.EXCHANGE - // switch(io.trainIO.msgReq.bits.reqType) { - // is(MessageRequestType.MSG_REQ) { - // nextState := State.EXCHANGE - // } - // is(MessageRequestType.MSG_RESP) { - // nextState := State.EXCHANGE - // } - // is(MessageRequestType.MSG_EXCH) { - // nextState := State.EXCHANGE - // } - // } } } is(State.EXCHANGE) { @@ -95,7 +85,7 @@ class SBMsgWrapper( } /** send message over sideband */ - io.laneIO.txData.valid := true.B + io.laneIO.txData.valid := !sentMsg || repeat io.laneIO.txData.bits := currentReq val hasSentMsg = WireInit(io.laneIO.txData.fire || sentMsg) val justReceivedMsg = Wire(Bool()) diff --git a/src/main/scala/mbafe/AsyncFifoCustom.scala b/src/main/scala/mbafe/AsyncFifoCustom.scala new file mode 100644 index 0000000..7b156d4 --- /dev/null +++ b/src/main/scala/mbafe/AsyncFifoCustom.scala @@ -0,0 +1,51 @@ +package edu.berkeley.cs.ucie.digital +package afe + +import chisel3._ +import chisel3.util._ + + + +class AsyncFifoCustom(depth: Int, width: Int) extends Module { + val io = IO(new Bundle { + val deq_clock = Input(Clock()) + val deq = Flipped(Flipped(Decoupled(UInt(width.W)))) + val deq_reset = Input(Bool()) + val enq_reset = Input(Bool()) + val enq_clock = Input(Clock()) + val enq = Flipped(Decoupled(UInt(width.W))) + }) + val fifo_inst = Module (new AsyncFifoCustomCore(depth, width)) + + fifo_inst.io.rst := ~io.enq_reset + fifo_inst.io.clk_w := io.enq_clock + fifo_inst.io.valid_w := io.enq.valid + io.enq.ready := fifo_inst.io.ready_w + fifo_inst.io.data_w := io.enq.bits + + // fifo_inst.io.clk_r := io.deq_clock + // fifo_inst.io.ready_r := io.deq.ready + // io.deq.bits := fifo_inst.io.data_r + // io.deq.valid := fifo_inst.io.valid_r + io.deq.valid := fifo_inst.io.valid_r + fifo_inst.io.clk_r := io.deq_clock + fifo_inst.io.ready_r := io.deq.ready + io.deq.bits := fifo_inst.io.data_r +} + +class AsyncFifoCustomCore (depth: Int, width: Int) extends BlackBox( + Map("DEPTH" -> depth, "WIDTH" -> width) +) with HasBlackBoxResource { + val io = IO(new Bundle { + val rst = Input(Bool()) + val clk_w = Input(Clock()) + val valid_w = Input(Bool()) + val ready_w = Output(Bool()) + val data_w = Input(Bits(width.W)) + val clk_r = Input(Clock()) + val valid_r = Output(Bool()) + val ready_r = Input(Bool()) + val data_r = Output(Bits(width.W)) + }) + addResource("/vsrc/AsyncFifoCustomCore.sv") +} \ No newline at end of file diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala new file mode 100644 index 0000000..441ba05 --- /dev/null +++ b/src/main/scala/mbafe/MbAfe.scala @@ -0,0 +1,107 @@ +package edu.berkeley.cs.ucie.digital +package afe + +import chisel3._ +import chisel3.util._ +import chisel3.stage.ChiselStage +import interfaces._ +import chisel3.experimental.DataMirror +import freechips.rocketchip.util.{AsyncQueue, AsyncQueueParams} + +// This module receives data from logphy and sends to analog +class TxMainbandSerializer(afeParams: AfeParams) extends Module { + val io = IO(new Bundle { + val txInData = Flipped( + Decoupled(Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W))), + ) + val txMbIo = Output(new MainbandIo()) + }) + + val lanes = afeParams.mbLanes + val width = afeParams.mbSerializerRatio + val hasData = Wire(Bool()) + hasData := io.txInData.valid + + // receive data + + val txMbShiftRegs = Seq.fill(lanes)(RegInit(0.U(width.W))) + val sending = RegInit(false.B) + val (txMbUICounter, uiCountDone) = Counter(sending, width) + + io.txInData.ready := !sending + when(io.txInData.fire) { + sending := true.B + }.elsewhen(uiCountDone) { + sending := false.B + } + + val shift = RegInit(false.B) + + io.txMbIo.clkn := (!clock.asBool).asClock + io.txMbIo.clkp := clock + + // Assign each async fifo individually + io.txInData.bits.zipWithIndex.foreach { case (laneData, i) => + // Valid framing, up for first 4 ui, down for last 4 ui + when(io.txInData.fire) { + txMbShiftRegs(i) := laneData + }.otherwise { + txMbShiftRegs(i) := txMbShiftRegs(i) >> 1.U + } + } + + io.txMbIo.data := VecInit(txMbShiftRegs.map(_(0))).asUInt + io.txMbIo.valid := sending + io.txMbIo.track := false.B +} + +// This module accepts data from analog and send to adapter +class RxMainbandDeserializer( + afeParams: AfeParams, +) extends Module { + val io = IO(new Bundle { + val rxMbIo = Input(new MainbandIo()) + val rxOutData = + Decoupled(Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W))) + }) + + private val width = afeParams.mbSerializerRatio + private val lanes = afeParams.mbLanes + + val rxMbShiftRegs = Seq.fill(lanes)(RegInit(0.U(width.W))) + val (_, done_sending) = Counter(io.rxMbIo.valid, width) + val out_valid = RegNext(done_sending) + + rxMbShiftRegs.zipWithIndex.foreach { case (rxMbShiftReg, i) => + when(io.rxMbIo.valid) { + rxMbShiftReg := (rxMbShiftReg << 1.U) | io.rxMbIo.data(i) + } + io.rxOutData.bits(i) := Reverse(rxMbShiftReg) + } + io.rxOutData.valid := out_valid +} + +class MbAfe(afeParams: AfeParams) extends Module { + val io = IO(new Bundle { + val mbAfeIo = Flipped(new MainbandAfeIo(AfeParams())) + val mbTxData = Output(new MainbandIo(afeParams.mbLanes)) + val mbRxData = Input(new MainbandIo(afeParams.mbLanes)) + }) + + val txMainband = Module(new TxMainbandSerializer(afeParams)) + val rxMainband = + withClockAndReset(io.mbRxData.clkp, reset.asAsyncReset)( + Module(new RxMainbandDeserializer(afeParams)), + ) + + /** Connect to LogPhy AFE IO */ + io.mbAfeIo.fifoParams.clk := io.mbRxData.clkp + io.mbAfeIo.fifoParams.reset := reset.asBool + io.mbAfeIo.txData <> txMainband.io.txInData + io.mbAfeIo.rxData <> rxMainband.io.rxOutData + io.mbAfeIo.pllLock := true.B + + /** Connect to Mainband IO */ + io.mbTxData <> txMainband.io.txMbIo + io.mbRxData <> rxMainband.io.rxMbIo +} diff --git a/src/main/scala/protocol/ProtocolLayer.scala b/src/main/scala/protocol/ProtocolLayer.scala index 1fc72fa..5fd15de 100644 --- a/src/main/scala/protocol/ProtocolLayer.scala +++ b/src/main/scala/protocol/ProtocolLayer.scala @@ -67,16 +67,18 @@ class ProtocolLayer(val fdiParams: FdiParams) extends Module { // io.fdi.plStateStatus === PhyState.active) val lp_rx_active_pl_state = (io.fdi.plStateStatus === PhyState.active) - when(io.fdi.plRxActiveReq && io.TLready_to_rcv && lp_rx_active_pl_state) { + when(io.fdi.plRxActiveReq && io.TLready_to_rcv){//&& lp_rx_active_pl_state) { lp_rx_active_sts_reg := true.B } io.fdi.lpRxActiveStatus := lp_rx_active_sts_reg // Refer to section 8.2.8 for FDI bringup and state req logic val lp_state_req_reg = RegInit(PhyStateReq.nop) + //val lp_state_req_prev = RegInit(PhyState.nop) + //lp_state_req_prev := io.fdi.plStateStatus + // Removed: lp_state_req_prev === PhyState.nop & val reqActive = ((io.fdi.plStateStatus === PhyState.reset & - lp_state_req_reg === PhyStateReq.nop & io.fdi.plInbandPres) || io.fdi.plStateStatus === PhyState.linkReset) when(reqActive) { diff --git a/src/main/scala/sideband/sidebandChannel.scala b/src/main/scala/sideband/sidebandChannel.scala index 734ad51..2bf3782 100644 --- a/src/main/scala/sideband/sidebandChannel.scala +++ b/src/main/scala/sideband/sidebandChannel.scala @@ -57,9 +57,22 @@ class PHYSidebandChannel( switcher.io.outer.layer_to_node_below.nodeq() lower_node.io.inner.layer_to_node <> io.inner.rawInput } - lower_node.io.inner.node_to_layer <> switcher.io.outer.node_to_layer_below + + when(io.inner.rxMode === RXTXMode.RAW) { + switcher.io.outer.node_to_layer_below.noenq() + switcher.io.inner.node_to_layer_below.nodeq() + + lower_node.io.inner.node_to_layer <> io.inner.switcherBundle.node_to_layer_below + switcher.io.inner.layer_to_node_below <> io.inner.switcherBundle.layer_to_node_below + switcher.io.inner.node_to_layer_above <> io.inner.switcherBundle.node_to_layer_above + switcher.io.inner.layer_to_node_above <> io.inner.switcherBundle.layer_to_node_above + + }.otherwise { + lower_node.io.inner.node_to_layer <> switcher.io.outer.node_to_layer_below + io.inner.switcherBundle <> switcher.io.inner + } lower_node.io.rxMode := io.inner.rxMode // Connect inner signals - io.inner.switcherBundle <> switcher.io.inner + // io.inner.switcherBundle <> switcher.io.inner } diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index f1d154a..973b65b 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -2,8 +2,9 @@ package edu.berkeley.cs.ucie.digital package sideband import chisel3._ +import chisel3.experimental._ import chisel3.util._ - +import freechips.rocketchip.util.{AsyncQueue, AsyncResetReg, ClockGate} import interfaces._ //TODO: 1) L317-318 needs to be revisited @@ -262,12 +263,17 @@ class SidebandLinkSerializer( val sending = RegInit(false.B) val done = RegInit(false.B) val waited = RegInit(true.B) + val sendNext = RegInit(false.B) val (sendCount, sendDone) = Counter(sending, dataBeats) val isComplete = RegInit(false.B) io.in.ready := (waited) // wait for 32 cycles between SB messages - io.out.clock := Mux(sending, clock.asUInt, false.B) + + val sendNegEdge = withClock((!clock.asBool).asClock)(RegInit(false.B)) + sendNegEdge := sendNext || sending && (sendCount =/= (dataBeats - 1).U) + + io.out.clock := Mux(sendNegEdge, clock.asUInt, false.B) io.out.bits := data(sb_w - 1, 0) counter_en := false.B @@ -276,9 +282,15 @@ class SidebandLinkSerializer( when(io.in.fire) { data := io.in.bits.asUInt + sendNext := true.B + } + + when(sendNext) { + sendNext := false.B sending := true.B - waited := false.B counter_next := 0.U + done := false.B + waited := false.B } when(sending) { data := data >> sb_w.U } @@ -312,22 +324,44 @@ class SidebandLinkDeserializer( val dataBits = msg_w val dataBeats = (dataBits - 1) / sb_w + 1 - val data = Reg(Vec(dataBeats, UInt(sb_w.W))) + val sbDeserBlackBox = Module(new SBDeserializerBlackBox(msg_w)) - val receiving = RegInit(true.B) + val valid_sync_1 = RegNext(sbDeserBlackBox.io.out_data_valid) + val valid_sync = RegNext(valid_sync_1) + val data_sync_1 = RegNext(sbDeserBlackBox.io.out_data) + val data_sync = RegNext(data_sync_1) - withClock(remote_clock) { + val flag = RegInit(true.B) + when(valid_sync) { + flag := false.B + }.otherwise { + flag := true.B + } - val (recvCount, recvDone) = Counter(true.B, dataBeats) + io.out.valid := valid_sync && flag + io.out.bits := data_sync - val recvCount_delay = RegInit(0.U(log2Ceil(dataBeats).W)) - recvCount_delay := recvCount + sbDeserBlackBox.io.clk := remote_clock + sbDeserBlackBox.io.rst := reset.asAsyncReset + sbDeserBlackBox.io.in_data := io.in.bits - data(recvCount_delay) := io.in.bits - when(recvDone) { receiving := false.B } - when(io.out.fire) { receiving := true.B } - io.out.valid := !receiving +} - io.out.bits := data.asUInt - } +class SBDeserializerBlackBox(val width: Int) + extends BlackBox( + Map( + "WIDTH" -> IntParam(width), + "WIDTH_W" -> IntParam(log2Ceil(width) + 1), + ), + ) + with HasBlackBoxResource { + val io = IO(new Bundle { + val clk = Input(Clock()) + val rst = Input(Reset()) + val in_data = Input(UInt(1.W)) + val out_data = Output(UInt(width.W)) + val out_data_valid = Output(Bool()) + }) + + addResource("/vsrc/SBDeserializer.v") } diff --git a/src/main/scala/tilelink/Configs.scala b/src/main/scala/tilelink/Configs.scala index 675cb2e..3594e41 100644 --- a/src/main/scala/tilelink/Configs.scala +++ b/src/main/scala/tilelink/Configs.scala @@ -21,7 +21,6 @@ case class UCITLParams ( val fdiParams: FdiParams, val rdiParams: RdiParams, val sbParams: SidebandParams, - val myId: BigInt, val linkTrainingParams: LinkTrainingParams, val afeParams: AfeParams, val laneAsyncQueueParams: AsyncQueueParams @@ -38,7 +37,6 @@ trait CanHaveTLUCIAdapter { this: BaseSubsystem => fdiParams = params.fdiParams, rdiParams = params.rdiParams, sbParams = params.sbParams, - myId = params.myId, linkTrainingParams = params.linkTrainingParams, afeParams = params.afeParams, laneAsyncQueueParams = params.laneAsyncQueueParams diff --git a/src/main/scala/tilelink/UCITLFront.scala b/src/main/scala/tilelink/UCITLFront.scala index bb0afac..88f9b0a 100644 --- a/src/main/scala/tilelink/UCITLFront.scala +++ b/src/main/scala/tilelink/UCITLFront.scala @@ -19,15 +19,15 @@ import logphy.{LinkTrainingParams} // TODO: Sideband messaging /** Main class to generate manager, client and register nodes on the tilelink diplomacy. - * These needs to get connected to the chipyard system. The class converts tilelink - * packets to UCIe Raw 64B flit. It also instantiates the protocol layer which acts as + * These needs to get connected to the chipyard system. The class converts tilelink + * packets to UCIe Raw 64B flit. It also instantiates the protocol layer which acts as * an agnostic interface to generate FDI signalling. */ class UCITLFront(val tlParams: TileLinkParams, val protoParams: ProtocolLayerParams, val fdiParams: FdiParams, val rdiParams: RdiParams, - val sbParams: SidebandParams, val myId: BigInt, + val sbParams: SidebandParams, val linkTrainingParams: LinkTrainingParams, - val afeParams: AfeParams, + val afeParams: AfeParams, val laneAsyncQueueParams: AsyncQueueParams) (implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) { @@ -37,7 +37,7 @@ class UCITLFront(val tlParams: TileLinkParams, val protoParams: ProtocolLayerPar // MMIO registers controlled by the sideband module val regNode = LazyModule(new UCIConfigRF(beatBytes = tlParams.CONFIG_BEAT_BYTES, address = tlParams.CONFIG_ADDRESS)) - + // Manager node to send and acquire traffic to partner die val managerNode: TLManagerNode = TLManagerNode(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( @@ -67,25 +67,29 @@ class UCITLFrontImp extends Impl { // FDI interface for testing purposes only //val fdi = new Fdi(fdiParams) // IOs for connecting to the AFE - val mbAfe = new MainbandAfeIo(afeParams) - val sbAfe = new SidebandAfeIo(afeParams) + //val mbAfe = new MainbandAfeIo(afeParams) + val mbAfe_tx = Output(new MainbandIo(afeParams.mbLanes)) + val mbAfe_rx = Input (new MainbandIo(afeParams.mbLanes)) + val sbTxIo = Output(new SidebandIo) + val sbRxIo = Input(new SidebandIo) }) withClockAndReset(clock, reset) { - withClockAndReset(clock, reset) { - val fault = RegInit(false.B) // if fault in ecc code // Instantiate the agnostic protocol layer //val protocol = Module(new ProtocolLayer(fdiParams)) val ucietop = Module(new UCITop(fdiParams, rdiParams, - sbParams, myId, + sbParams, linkTrainingParams, afeParams, laneAsyncQueueParams)) //io.fdi <> ucietop.io.fdi ucietop.io.fault := fault - io.mbAfe <> ucietop.io.mbAfe - io.sbAfe <> ucietop.io.sbAfe + //io.mbAfe <> ucietop.io.mbAfe + io.mbAfe_tx <> ucietop.io.mbAfe_tx + io.mbAfe_rx <> ucietop.io.mbAfe_rx + io.sbTxIo <> ucietop.io.sbTxIO + io.sbRxIo <> ucietop.io.sbRxIO // Hamming encode and decode val hammingEncoder = Module(new HammingEncode(protoParams)) @@ -106,12 +110,12 @@ class UCITLFrontImp extends Impl { ucietop.io.fdi_plConfig.valid := protocol_sb_node.io.outer.tx.valid protocol_sb_node.io.outer.tx.credit := ucietop.io.fdi_plConfigCredit - protocol_sb_node.io.inner.layer_to_node.bits := Cat(regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_high, + protocol_sb_node.io.inner.layer_to_node.bits := Cat(regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_high, regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_low, regNode.module.io.sb_csrs.sidebank_mailbox_sw_to_node_index_high, regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_index_low) protocol_sb_node.io.inner.layer_to_node.valid := regNode.module.io.sb_csrs.sideband_mailbox_sw_valid - + regNode.module.io.sb_csrs.sideband_mailbox_index_low := protocol_sb_node.io.inner.node_to_layer.bits(31, 0) regNode.module.io.sb_csrs.sideband_mailbox_index_high := protocol_sb_node.io.inner.node_to_layer.bits(63, 32) regNode.module.io.sb_csrs.sideband_mailbox_data_low := protocol_sb_node.io.inner.node_to_layer.bits(95, 64) @@ -123,8 +127,8 @@ class UCITLFrontImp extends Impl { dataBits = tlParams.dataWidth, sourceBits = tlParams.sourceIDWidth, sinkBits = tlParams.sinkIDWidth, - sizeBits = tlParams.sizeWidth, - echoFields = Nil, + sizeBits = tlParams.sizeWidth, + echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) @@ -170,14 +174,14 @@ class UCITLFrontImp extends Impl { txDTLPayload := 0.U.asTypeOf(new TLBundleAUnionD(tlParams)) /* - manager_tl.a.ready = (inward.io.enq.ready & ~ucietop.io.fdi_lpStallAck & + manager_tl.a.ready = (inward.io.enq.ready & ~ucietop.io.fdi_lpStallAck & (ucietop.io.TLplStateStatus === PhyState.active)) inward.io.enq.valid := manager_tl.a.fire */ // A request to partner die logic // enqueue on the A channel queue - manager_tl.a.ready := (inwardA.io.enq.ready & ~ucietop.io.fdi_lpStallAck & + manager_tl.a.ready := (inwardA.io.enq.ready & ~ucietop.io.fdi_lpStallAck & (ucietop.io.TLplStateStatus === PhyState.active)) inwardA.io.enq.valid := manager_tl.a.fire inwardA.io.enq.bits <> manager_tl.a.bits @@ -190,7 +194,7 @@ class UCITLFrontImp extends Impl { creditedMsgA.io.credit.bits := uciRxPayload.cmd.tlACredit // D response to partner die's A request logic - client_tl.d.ready := (inwardD.io.enq.ready & ~ucietop.io.fdi_lpStallAck & + client_tl.d.ready := (inwardD.io.enq.ready & ~ucietop.io.fdi_lpStallAck & (ucietop.io.TLplStateStatus === PhyState.active)) inwardD.io.enq.valid := client_tl.d.fire inwardD.io.enq.bits <> client_tl.d.bits @@ -246,15 +250,16 @@ class UCITLFrontImp extends Impl { // ============ Below code should run on the UCIe clock? ============== val checksum_reg = RegInit(0.U(64.W)) checksum_reg := hammingEncoder.io.checksum - - val tx_pipe = Module(new Pipe(new UCIRawPayloadFormat(tlParams, protoParams), 1)) + + val tx_pipe = Module(new Queue(new UCIRawPayloadFormat(tlParams, protoParams), 1)) tx_pipe.io.enq.bits := uciTxPayload tx_pipe.io.enq.valid := txArbiter.io.out.fire // Dequeue the TX TL packets and translate to UCIe flit - txArbiter.io.out.ready := ucietop.io.TLlpData_ready // if pl_trdy is asserted + txArbiter.io.out.ready := tx_pipe.io.enq.ready + tx_pipe.io.deq.ready := ucietop.io.TLlpData_ready // if pl_trdy is asserted // specs implies that these needs to be asserted at the same time - ucietop.io.TLlpData_valid := tx_pipe.io.deq.valid & (~ucietop.io.fdi_lpStallAck) - ucietop.io.TLlpData_irdy := tx_pipe.io.deq.valid & (~ucietop.io.fdi_lpStallAck) + ucietop.io.TLlpData_valid := tx_pipe.io.deq.fire & (~ucietop.io.fdi_lpStallAck) + ucietop.io.TLlpData_irdy := tx_pipe.io.deq.fire & (~ucietop.io.fdi_lpStallAck) ucietop.io.TLlpData_bits := Cat(tx_pipe.io.deq.bits.asUInt(511,64), checksum_reg.asUInt) // assign uciTXPayload to the FDI lp data signa val creditA = (txArbiter.io.out.bits.msgType === UCIProtoMsgTypes.TLA) @@ -263,12 +268,12 @@ class UCITLFrontImp extends Impl { val creditD = (txArbiter.io.out.bits.msgType === UCIProtoMsgTypes.TLD) val creditE = (txArbiter.io.out.bits.msgType === UCIProtoMsgTypes.TLE) - outwardA.io.credit.ready := tx_pipe.io.deq.valid && creditA - outwardD.io.credit.ready := tx_pipe.io.deq.valid && creditD + outwardA.io.credit.ready := tx_pipe.io.deq.fire && creditA + outwardD.io.credit.ready := tx_pipe.io.deq.fire && creditD val txACredit = WireDefault(0.U(protoParams.creditWidth.W)) val txDCredit = WireDefault(0.U(protoParams.creditWidth.W)) - + when(outwardA.io.credit.valid){ txACredit := outwardA.io.credit.bits }.elsewhen(outwardD.io.credit.valid){ @@ -284,7 +289,7 @@ class UCITLFrontImp extends Impl { uciTxPayload.cmd.tlACredit := txACredit uciTxPayload.cmd.tlBCredit := 0.U //& outwardB.io.credit.valid & creditB uciTxPayload.cmd.tlCCredit := 0.U //& outwardC.io.credit.valid & creditC - uciTxPayload.cmd.tlDCredit := txDCredit + uciTxPayload.cmd.tlDCredit := txDCredit uciTxPayload.cmd.tlECredit := 0.U //& outwardE.io.credit.valid & creditE uciTxPayload.cmd.reservedCmd := 0.U // header 1 @@ -335,7 +340,7 @@ class UCITLFrontImp extends Impl { uciRxPayload.ecc := ucietop.io.TLplData_bits(63,0) hammingDecoder.io.data := ucietop.io.TLplData_bits(511,64) hammingDecoder.io.checksum := ucietop.io.TLplData_bits(63,0) - + // map the uciRxPayload to the rxTLPayload rxTLPayload.address := uciRxPayload.header1.address rxTLPayload.opcode := uciRxPayload.header2.opcode @@ -385,6 +390,6 @@ class UCITLFrontImp extends Impl { // soft resets: can be reset or flush and reset, in flush and reset, the packets are // sent out before triggering reset - ucietop.io.soft_reset := (regNode.module.io.d2d_csrs.d2d_state_can_reset | + ucietop.io.soft_reset := (regNode.module.io.d2d_csrs.d2d_state_can_reset | regNode.module.io.d2d_csrs.d2d_flush_and_reset) -}}}} \ No newline at end of file +}}} \ No newline at end of file diff --git a/src/main/scala/utils/ClockMux.scala b/src/main/scala/utils/ClockMux.scala new file mode 100644 index 0000000..ce2afc6 --- /dev/null +++ b/src/main/scala/utils/ClockMux.scala @@ -0,0 +1,16 @@ +package edu.berkeley.cs.ucie.digital +package utils + +import chisel3._ +import chisel3.util._ + +class ClockMux2 extends BlackBox with HasBlackBoxResource { + + val io = IO(new Bundle { + val clocksIn = Input(Vec(2, Clock())) + val sel = Input(Bool()) + val clockOut = Output(Clock()) + }) + + addResource("/vsrc/ClockSelector.v") +} diff --git a/src/test/scala/e2e/AfeLoopback.scala b/src/test/scala/e2e/AfeLoopback.scala index 1f9c321..4ca591e 100644 --- a/src/test/scala/e2e/AfeLoopback.scala +++ b/src/test/scala/e2e/AfeLoopback.scala @@ -5,7 +5,12 @@ import chisel3._ import chisel3.util._ import interfaces._ import org.chipsalliance.cde.config.{Field, Parameters, Config} -import chisel3.experimental.hierarchy.{Definition, Instance, instantiable, public} +import chisel3.experimental.hierarchy.{ + Definition, + Instance, + instantiable, + public, +} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink.{TLTestRAM} @@ -13,31 +18,55 @@ import protocol._ // @instantiable class AfeLoopback(val afeParams: AfeParams) extends Module { - val io = IO(new Bundle { - // val finished = Output(Bool()) - val mbAfe = Flipped(new MainbandAfeIo(afeParams)) - val sbAfe = Flipped(new SidebandAfeIo(afeParams)) - }) + val io = IO(new Bundle { + // val finished = Output(Bool()) + // val mbAfe = Flipped(new MainbandAfeIo(afeParams)) + val mbAfe_tx = Input(new MainbandIo(afeParams.mbLanes)) + val mbAfe_rx = Output(new MainbandIo(afeParams.mbLanes)) + val sbAfe_tx = Input(new SidebandIo) + val sbAfe_rx = Output(new SidebandIo) + }) - val latency = 2 - val delayerMb = Module(new Pipe(chiselTypeOf(io.mbAfe.txData.bits), latency)) - val delayerSb = Module(new Pipe(chiselTypeOf(io.sbAfe.txData), latency)) - - delayerMb.io.enq.valid := io.mbAfe.txData.valid - delayerMb.io.enq.bits := io.mbAfe.txData.bits - io.mbAfe.rxData.bits := delayerMb.io.deq.bits - io.mbAfe.rxData.valid := delayerMb.io.deq.valid - io.mbAfe.txData.ready := true.B - io.mbAfe.fifoParams.clk := clock - io.mbAfe.fifoParams.reset := reset - io.mbAfe.pllLock := true.B + val latency = 2 + /* val delayerMb = Module(new Pipe(chiselTypeOf(io.mbAfe.txData.bits), + * latency)) */ + val delayerMbTx = Module(new Pipe(chiselTypeOf(io.mbAfe_tx.data), latency)) + val delayerSb = Module(new Pipe(chiselTypeOf(io.sbAfe_tx.data), latency)) + val delayerSb_clock = Module( + new Pipe(chiselTypeOf(io.sbAfe_tx.clk), latency), + ) + val delayerMbTx_clockn = Module( + new Pipe(chiselTypeOf(io.mbAfe_tx.clkn.asBool), latency), + ) + val delayerMbTx_clockp = Module( + new Pipe(chiselTypeOf(io.mbAfe_tx.clkp.asBool), latency), + ) - delayerSb.io.enq.valid := true.B //io.sbAfe.txData.valid - delayerSb.io.enq.bits := io.sbAfe.txData - io.sbAfe.rxData := delayerSb.io.deq.bits - //io.sbAfe.rxData.valid := delayerSb.io.deq.valid - io.sbAfe.rxClock := io.sbAfe.txClock - io.sbAfe.fifoParams.clk := clock - io.sbAfe.fifoParams.reset := reset - io.sbAfe.pllLock := true.B - } \ No newline at end of file + /** TODO: ansa fix delayed signals -- not delayed */ + delayerMbTx.io.enq.valid := io.mbAfe_tx.valid + delayerMbTx.io.enq.bits := io.mbAfe_tx.data + io.mbAfe_rx.data := delayerMbTx.io.deq.bits + io.mbAfe_rx.valid := delayerMbTx.io.deq.valid + delayerMbTx_clockn.io.enq.valid := true.B + delayerMbTx_clockn.io.enq.bits := io.mbAfe_tx.clkn.asBool + delayerMbTx_clockp.io.enq.valid := true.B + delayerMbTx_clockp.io.enq.bits := io.mbAfe_tx.clkp.asBool + + io.mbAfe_rx.clkn := io.mbAfe_tx.clkn + io.mbAfe_rx.clkp := io.mbAfe_tx.clkp + io.mbAfe_rx.track := false.B + + delayerSb.io.enq.valid := true.B // io.sbAfe.txData.valid + delayerSb.io.enq.bits := io.sbAfe_tx.data + delayerSb_clock.io.enq.valid := true.B + delayerSb_clock.io.enq.bits := io.sbAfe_tx.clk + + io.sbAfe_rx.data := delayerSb.io.deq.bits + val delayNegEdge = withClock((!clock.asBool).asClock)(RegInit(false.B)) + delayNegEdge := delayerSb_clock.io.deq.bits.asBool && delayerSb_clock.io.deq.valid + io.sbAfe_rx.clk := Mux( + delayNegEdge, + clock.asBool, + false.B, + ) +} diff --git a/src/test/scala/e2e/AfeLoopbackTest.scala b/src/test/scala/e2e/AfeLoopbackTest.scala index e865cca..40667fb 100644 --- a/src/test/scala/e2e/AfeLoopbackTest.scala +++ b/src/test/scala/e2e/AfeLoopbackTest.scala @@ -20,81 +20,108 @@ import interfaces._ import protocol.{ProtocolLayerParams} import java.util.ResourceBundle -class AfeLoopbackTester (implicit p: Parameters) extends LazyModule { - val protoParams = ProtocolLayerParams() - val tlParams = TileLinkParams(address=0x0, addressRange=0xffff, configAddress=0x40000, inwardQueueDepth=8, outwardQueueDepth=8) - val fdiParams = FdiParams(width=64, dllpWidth=64, sbWidth=32) - val rdiParams = RdiParams(width=64, sbWidth=32) - val sbParams = SidebandParams() - val myId = 1 - val linkTrainingParams = LinkTrainingParams() - val afeParams = AfeParams() - val laneAsyncQueueParams = AsyncQueueParams() - val delay = 0.0 - val txns = 10 +class AfeLoopbackTester(implicit p: Parameters) extends LazyModule { + val protoParams = ProtocolLayerParams() + val tlParams = TileLinkParams( + address = 0x0, + addressRange = 0xffff, + configAddress = 0x40000, + inwardQueueDepth = 8, + outwardQueueDepth = 8, + ) + val fdiParams = FdiParams(width = 64, dllpWidth = 64, sbWidth = 32) + val rdiParams = RdiParams(width = 64, sbWidth = 32) + val sbParams = SidebandParams() + val myId = 1 + val linkTrainingParams = LinkTrainingParams() + val afeParams = AfeParams() + val laneAsyncQueueParams = AsyncQueueParams() + val delay = 0.0 + val txns = 100 - // Create clock source - val clockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) + // Create clock source + val clockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) - val csrfuzz = LazyModule(new TLFuzzer(txns)) - val fuzz = LazyModule(new TLFuzzer(txns)) - val tlUcieDie1 = LazyModule(new UCITLFront(tlParams=tlParams, - protoParams=protoParams, fdiParams=fdiParams, - rdiParams = rdiParams, - sbParams = sbParams, - myId = myId, - linkTrainingParams = linkTrainingParams, - afeParams = afeParams, - laneAsyncQueueParams = laneAsyncQueueParams)) - tlUcieDie1.clockNode := clockSourceNode - val ram = LazyModule(new TLRAM(AddressSet(tlParams.ADDRESS, tlParams.addressRange), beatBytes=tlParams.BEAT_BYTES)) + val csrfuzz = LazyModule(new TLFuzzer(txns)) + val fuzz = LazyModule(new TLFuzzer(txns)) + val tlUcieDie1 = LazyModule( + new UCITLFront( + tlParams = tlParams, + protoParams = protoParams, + fdiParams = fdiParams, + rdiParams = rdiParams, + sbParams = sbParams, + linkTrainingParams = linkTrainingParams, + afeParams = afeParams, + laneAsyncQueueParams = laneAsyncQueueParams, + ), + ) + tlUcieDie1.clockNode := clockSourceNode + val ram = LazyModule( + new TLRAM( + AddressSet(tlParams.ADDRESS, tlParams.addressRange), + beatBytes = tlParams.BEAT_BYTES, + ), + ) - // CSR node - tlUcieDie1.regNode.node := csrfuzz.node - // connect data nodes - tlUcieDie1.managerNode := TLSourceShrinker(tlParams.sourceIDWidth) := fuzz.node - ram.node := tlUcieDie1.clientNode - lazy val module = new Impl - class Impl extends LazyModuleImp(this) { - val io = IO(new Bundle { - val uci_clock = Input(new ClockBundle(ClockBundleParameters())) - val finished = Output(Bool()) - }) - // connect IOs - io.finished := fuzz.module.io.finished - val AfeLoopback = Module(new AfeLoopback(afeParams)) - io.uci_clock <> clockSourceNode.out(0)._1 - // inputs to tlUcieDie1 - tlUcieDie1.module.io.mbAfe <> AfeLoopback.io.mbAfe - tlUcieDie1.module.io.sbAfe <> AfeLoopback.io.sbAfe - } + // CSR node + tlUcieDie1.regNode.node := csrfuzz.node + // connect data nodes + tlUcieDie1.managerNode := TLSourceShrinker( + tlParams.sourceIDWidth, + ) := fuzz.node + ram.node := tlUcieDie1.clientNode + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { + val io = IO(new Bundle { + val uci_clock = Input(new ClockBundle(ClockBundleParameters())) + val finished = Output(Bool()) + }) + // connect IOs + io.finished := fuzz.module.io.finished + val AfeLoopback = Module(new AfeLoopback(afeParams)) + io.uci_clock <> clockSourceNode.out(0)._1 + // inputs to tlUcieDie1 + // tlUcieDie1.module.io.mbAfe <> AfeLoopback.io.mbAfe + tlUcieDie1.module.io.mbAfe_tx <> AfeLoopback.io.mbAfe_tx + tlUcieDie1.module.io.mbAfe_rx <> AfeLoopback.io.mbAfe_rx + tlUcieDie1.module.io.sbTxIo <> AfeLoopback.io.sbAfe_tx + tlUcieDie1.module.io.sbRxIo <> AfeLoopback.io.sbAfe_rx + + } } class AfeTLTestHarness(implicit val p: Parameters) extends Module { - val io = IO(new Bundle{val success = Output(Bool())}) + val io = IO(new Bundle { val success = Output(Bool()) }) val tester = Module(LazyModule(new AfeLoopbackTester).module) tester.io.uci_clock.clock := clock tester.io.uci_clock.reset := reset io.success := tester.io.finished // Dummy plusarg to avoid breaking verilator builds with emulator.cc - val useless_plusarg = PlusArg("useless_plusarg", width=1) + val useless_plusarg = PlusArg("useless_plusarg", width = 1) dontTouch(useless_plusarg) ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader) } class AfeLoopbackTest extends AnyFlatSpec with ChiselScalatestTester { - behavior of "AfeLoopback" - val txns = 2 - val timeout = 1000 - implicit val p: Parameters = Parameters.empty - ignore should "finish request and response before timeout" in { - test(new AfeTLTestHarness()).withAnnotations(Seq(VcsBackendAnnotation, WriteVcdAnnotation)) {c => //.withAnnotations(Seq(VcsBackendAnnotation, WriteVcdAnnotation)) - println("start Afe Loopback Test") - c.clock.setTimeout(timeout+10) - c.clock.step(timeout) - c.io.success.expect(true.B) - println("Afe Loopback Test finished? " + c.io.success.peek()) - } + behavior of "AfeLoopback" + val txns = 2 + val timeout = 100000 + implicit val p: Parameters = Parameters.empty + it should "finish request and response before timeout" in { + test(new AfeTLTestHarness()).withAnnotations( + Seq(VcsBackendAnnotation, WriteFsdbAnnotation), + ) { c => // .withAnnotations(Seq(VcsBackendAnnotation, WriteVcdAnnotation)) + + println("start Afe Loopback Test") + c.reset.poke(true.B) + c.clock.step(3) + c.reset.poke(false.B) + c.clock.setTimeout(timeout + 10) + c.clock.step(timeout) + c.io.success.expect(true.B) + println("Afe Loopback Test finished? " + c.io.success.peek()) } + } } diff --git a/src/test/scala/logphy/LogPhyLaneTest.scala b/src/test/scala/logphy/LogPhyLaneTest.scala index e8bb8ee..90ee798 100644 --- a/src/test/scala/logphy/LogPhyLaneTest.scala +++ b/src/test/scala/logphy/LogPhyLaneTest.scala @@ -22,6 +22,41 @@ class LogPhyLaneTest extends AnyFlatSpec with ChiselScalatestTester { c.io.mainbandLaneIO.txData.enqueueNow( "h1234_5678_9abc_def0_0fed_cba9_8765_4321_1111_2222_3333_4444_5555_6666_7777_8888".U, ) + c.io.mainbandIo.txData + .expectDequeueNow( + Vec.Lit( + "h8821".U, + "h8843".U, + "h7765".U, + "h7787".U, + "h66a9".U, + "h66cb".U, + "h55ed".U, + "h550f".U, + "h44f0".U, + "h44de".U, + "h33bc".U, + "h339a".U, + "h2278".U, + "h2256".U, + "h1134".U, + "h1112".U, + ), + ) + } + } + + behavior of "log phy TX lanes" + ignore should "correctly map TX bytes to their lanes - test 2" in { + test(new SimLanes(afeParams, queueParams)) { c => + c.io.mainbandLaneIO.txData.initSource() + c.io.mainbandLaneIO.txData.setSourceClock(c.clock) + c.io.mainbandIo.txData.initSink() + c.io.mainbandIo.txData.setSinkClock(c.clock) + + c.io.mainbandLaneIO.txData.enqueueNow( + "h7840_80a0_001f_ffff_ffe0_0000_0000_0000_0000".U, + ) c.io.mainbandIo.txData .expectDequeueNow( Vec.Lit( @@ -83,4 +118,5 @@ class LogPhyLaneTest extends AnyFlatSpec with ChiselScalatestTester { } } + } diff --git a/src/test/scala/logphy/LogPhyTest.scala b/src/test/scala/logphy/LogPhyTest.scala index 6d82948..f62eb6d 100644 --- a/src/test/scala/logphy/LogPhyTest.scala +++ b/src/test/scala/logphy/LogPhyTest.scala @@ -19,18 +19,17 @@ class LogPhyTest extends AnyFlatSpec with ChiselScalatestTester { * actual top-level test because Chiseltest does not support multiple clock * domains. */ - // behavior of "logical phy" - // it should "" in { - // test( - // new LogicalPhy( - // 0, - // linkTrainingParams = linkTrainingParams, - // afeParams = afeParams, - // rdiParams = rdiParams, - // fdiParams = fdiParams, - // sbParams = sbParams, - // laneAsyncQueueParams = laneAsyncQueueParams, - // ), - // ) { c => } - // } + behavior of "logical phy" + ignore should "" in { + test( + new LogicalPhy( + linkTrainingParams = linkTrainingParams, + afeParams = afeParams, + rdiParams = rdiParams, + fdiParams = fdiParams, + sbParams = sbParams, + laneAsyncQueueParams = laneAsyncQueueParams, + ), + ) { c => } + } }