From 8928bfc3693451e1ffc975c1021169cabb3490ae Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 2 May 2024 22:15:10 -0700 Subject: [PATCH 001/106] change to fsdb --- src/test/scala/e2e/AfeLoopbackTest.scala | 138 +++++++++++++---------- 1 file changed, 79 insertions(+), 59 deletions(-) diff --git a/src/test/scala/e2e/AfeLoopbackTest.scala b/src/test/scala/e2e/AfeLoopbackTest.scala index e865cca..50abf52 100644 --- a/src/test/scala/e2e/AfeLoopbackTest.scala +++ b/src/test/scala/e2e/AfeLoopbackTest.scala @@ -20,81 +20,101 @@ import interfaces._ import protocol.{ProtocolLayerParams} import java.util.ResourceBundle -class AfeLoopbackTester (implicit p: Parameters) extends LazyModule { - val protoParams = ProtocolLayerParams() - val tlParams = TileLinkParams(address=0x0, addressRange=0xffff, configAddress=0x40000, inwardQueueDepth=8, outwardQueueDepth=8) - val fdiParams = FdiParams(width=64, dllpWidth=64, sbWidth=32) - val rdiParams = RdiParams(width=64, sbWidth=32) - val sbParams = SidebandParams() - val myId = 1 - val linkTrainingParams = LinkTrainingParams() - val afeParams = AfeParams() - val laneAsyncQueueParams = AsyncQueueParams() - val delay = 0.0 - val txns = 10 +class AfeLoopbackTester(implicit p: Parameters) extends LazyModule { + val protoParams = ProtocolLayerParams() + val tlParams = TileLinkParams( + address = 0x0, + addressRange = 0xffff, + configAddress = 0x40000, + inwardQueueDepth = 8, + outwardQueueDepth = 8, + ) + val fdiParams = FdiParams(width = 64, dllpWidth = 64, sbWidth = 32) + val rdiParams = RdiParams(width = 64, sbWidth = 32) + val sbParams = SidebandParams() + val myId = 1 + val linkTrainingParams = LinkTrainingParams() + val afeParams = AfeParams() + val laneAsyncQueueParams = AsyncQueueParams() + val delay = 0.0 + val txns = 10 - // Create clock source - val clockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) + // Create clock source + val clockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) - val csrfuzz = LazyModule(new TLFuzzer(txns)) - val fuzz = LazyModule(new TLFuzzer(txns)) - val tlUcieDie1 = LazyModule(new UCITLFront(tlParams=tlParams, - protoParams=protoParams, fdiParams=fdiParams, - rdiParams = rdiParams, - sbParams = sbParams, - myId = myId, - linkTrainingParams = linkTrainingParams, - afeParams = afeParams, - laneAsyncQueueParams = laneAsyncQueueParams)) - tlUcieDie1.clockNode := clockSourceNode - val ram = LazyModule(new TLRAM(AddressSet(tlParams.ADDRESS, tlParams.addressRange), beatBytes=tlParams.BEAT_BYTES)) + val csrfuzz = LazyModule(new TLFuzzer(txns)) + val fuzz = LazyModule(new TLFuzzer(txns)) + val tlUcieDie1 = LazyModule( + new UCITLFront( + tlParams = tlParams, + protoParams = protoParams, + fdiParams = fdiParams, + rdiParams = rdiParams, + sbParams = sbParams, + myId = myId, + linkTrainingParams = linkTrainingParams, + afeParams = afeParams, + laneAsyncQueueParams = laneAsyncQueueParams, + ), + ) + tlUcieDie1.clockNode := clockSourceNode + val ram = LazyModule( + new TLRAM( + AddressSet(tlParams.ADDRESS, tlParams.addressRange), + beatBytes = tlParams.BEAT_BYTES, + ), + ) - // CSR node - tlUcieDie1.regNode.node := csrfuzz.node - // connect data nodes - tlUcieDie1.managerNode := TLSourceShrinker(tlParams.sourceIDWidth) := fuzz.node - ram.node := tlUcieDie1.clientNode - lazy val module = new Impl - class Impl extends LazyModuleImp(this) { - val io = IO(new Bundle { - val uci_clock = Input(new ClockBundle(ClockBundleParameters())) - val finished = Output(Bool()) - }) - // connect IOs - io.finished := fuzz.module.io.finished - val AfeLoopback = Module(new AfeLoopback(afeParams)) - io.uci_clock <> clockSourceNode.out(0)._1 - // inputs to tlUcieDie1 - tlUcieDie1.module.io.mbAfe <> AfeLoopback.io.mbAfe - tlUcieDie1.module.io.sbAfe <> AfeLoopback.io.sbAfe - } + // CSR node + tlUcieDie1.regNode.node := csrfuzz.node + // connect data nodes + tlUcieDie1.managerNode := TLSourceShrinker( + tlParams.sourceIDWidth, + ) := fuzz.node + ram.node := tlUcieDie1.clientNode + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { + val io = IO(new Bundle { + val uci_clock = Input(new ClockBundle(ClockBundleParameters())) + val finished = Output(Bool()) + }) + // connect IOs + io.finished := fuzz.module.io.finished + val AfeLoopback = Module(new AfeLoopback(afeParams)) + io.uci_clock <> clockSourceNode.out(0)._1 + // inputs to tlUcieDie1 + tlUcieDie1.module.io.mbAfe <> AfeLoopback.io.mbAfe + tlUcieDie1.module.io.sbAfe <> AfeLoopback.io.sbAfe + } } class AfeTLTestHarness(implicit val p: Parameters) extends Module { - val io = IO(new Bundle{val success = Output(Bool())}) + val io = IO(new Bundle { val success = Output(Bool()) }) val tester = Module(LazyModule(new AfeLoopbackTester).module) tester.io.uci_clock.clock := clock tester.io.uci_clock.reset := reset io.success := tester.io.finished // Dummy plusarg to avoid breaking verilator builds with emulator.cc - val useless_plusarg = PlusArg("useless_plusarg", width=1) + val useless_plusarg = PlusArg("useless_plusarg", width = 1) dontTouch(useless_plusarg) ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader) } class AfeLoopbackTest extends AnyFlatSpec with ChiselScalatestTester { - behavior of "AfeLoopback" - val txns = 2 - val timeout = 1000 - implicit val p: Parameters = Parameters.empty - ignore should "finish request and response before timeout" in { - test(new AfeTLTestHarness()).withAnnotations(Seq(VcsBackendAnnotation, WriteVcdAnnotation)) {c => //.withAnnotations(Seq(VcsBackendAnnotation, WriteVcdAnnotation)) - println("start Afe Loopback Test") - c.clock.setTimeout(timeout+10) - c.clock.step(timeout) - c.io.success.expect(true.B) - println("Afe Loopback Test finished? " + c.io.success.peek()) - } + behavior of "AfeLoopback" + val txns = 2 + val timeout = 1000 + implicit val p: Parameters = Parameters.empty + it should "finish request and response before timeout" in { + test(new AfeTLTestHarness()).withAnnotations( + Seq(VcsBackendAnnotation, WriteFsdbAnnotation), + ) { c => // .withAnnotations(Seq(VcsBackendAnnotation, WriteVcdAnnotation)) + println("start Afe Loopback Test") + c.clock.setTimeout(timeout + 10) + c.clock.step(timeout) + c.io.success.expect(true.B) + println("Afe Loopback Test finished? " + c.io.success.peek()) } + } } From 399ebcda55b9ea6ffa5a07b0ab6035fba2a4246d Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 00:04:01 -0700 Subject: [PATCH 002/106] update sb raw tx --- src/main/scala/sideband/sidebandChannel.scala | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandChannel.scala b/src/main/scala/sideband/sidebandChannel.scala index 734ad51..337ca41 100644 --- a/src/main/scala/sideband/sidebandChannel.scala +++ b/src/main/scala/sideband/sidebandChannel.scala @@ -57,7 +57,14 @@ class PHYSidebandChannel( switcher.io.outer.layer_to_node_below.nodeq() lower_node.io.inner.layer_to_node <> io.inner.rawInput } - lower_node.io.inner.node_to_layer <> switcher.io.outer.node_to_layer_below + io.inner.switcherBundle <> switcher.io.inner + when(io.inner.rxMode === RXTXMode.RAW) { + switcher.io.outer.node_to_layer_below.noenq() + lower_node.io.inner.node_to_layer <> io.inner.switcherBundle.node_to_layer_below + + }.otherwise { + lower_node.io.inner.node_to_layer <> switcher.io.outer.node_to_layer_below + } lower_node.io.rxMode := io.inner.rxMode // Connect inner signals From ad50bfdd93738817cd61d0d5033b9b7a8871d51e Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 00:33:14 -0700 Subject: [PATCH 003/106] update sb raw rx --- src/main/scala/sideband/sidebandChannel.scala | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandChannel.scala b/src/main/scala/sideband/sidebandChannel.scala index 337ca41..6fdc3af 100644 --- a/src/main/scala/sideband/sidebandChannel.scala +++ b/src/main/scala/sideband/sidebandChannel.scala @@ -57,13 +57,17 @@ class PHYSidebandChannel( switcher.io.outer.layer_to_node_below.nodeq() lower_node.io.inner.layer_to_node <> io.inner.rawInput } - io.inner.switcherBundle <> switcher.io.inner + when(io.inner.rxMode === RXTXMode.RAW) { switcher.io.outer.node_to_layer_below.noenq() lower_node.io.inner.node_to_layer <> io.inner.switcherBundle.node_to_layer_below + switcher.io.inner.layer_to_node_below <> io.inner.switcherBundle.layer_to_node_below + switcher.io.inner.node_to_layer_above <> io.inner.switcherBundle.node_to_layer_above + switcher.io.inner.layer_to_node_above <> io.inner.switcherBundle.layer_to_node_above }.otherwise { lower_node.io.inner.node_to_layer <> switcher.io.outer.node_to_layer_below + io.inner.switcherBundle <> switcher.io.inner } lower_node.io.rxMode := io.inner.rxMode From 9bcf715cce8dc847af4738e638fc451e10925d44 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 00:58:32 -0700 Subject: [PATCH 004/106] update sb raw rx --- src/main/scala/sideband/sidebandChannel.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandChannel.scala b/src/main/scala/sideband/sidebandChannel.scala index 6fdc3af..99d2ce0 100644 --- a/src/main/scala/sideband/sidebandChannel.scala +++ b/src/main/scala/sideband/sidebandChannel.scala @@ -72,5 +72,5 @@ class PHYSidebandChannel( lower_node.io.rxMode := io.inner.rxMode // Connect inner signals - io.inner.switcherBundle <> switcher.io.inner + // io.inner.switcherBundle <> switcher.io.inner } From e545d8e34abbf31f31efb12b72f75414f552ff58 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 01:02:06 -0700 Subject: [PATCH 005/106] update sb raw rx --- src/main/scala/sideband/sidebandChannel.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/sideband/sidebandChannel.scala b/src/main/scala/sideband/sidebandChannel.scala index 99d2ce0..2bf3782 100644 --- a/src/main/scala/sideband/sidebandChannel.scala +++ b/src/main/scala/sideband/sidebandChannel.scala @@ -60,6 +60,8 @@ class PHYSidebandChannel( when(io.inner.rxMode === RXTXMode.RAW) { switcher.io.outer.node_to_layer_below.noenq() + switcher.io.inner.node_to_layer_below.nodeq() + lower_node.io.inner.node_to_layer <> io.inner.switcherBundle.node_to_layer_below switcher.io.inner.layer_to_node_below <> io.inner.switcherBundle.layer_to_node_below switcher.io.inner.node_to_layer_above <> io.inner.switcherBundle.node_to_layer_above From dee4b27e7b8ef4b599e297035c395042fa4b9cf6 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 01:19:19 -0700 Subject: [PATCH 006/106] delay sb rx clock --- src/test/scala/e2e/AfeLoopback.scala | 62 ++++++++++++++++------------ 1 file changed, 35 insertions(+), 27 deletions(-) diff --git a/src/test/scala/e2e/AfeLoopback.scala b/src/test/scala/e2e/AfeLoopback.scala index 1f9c321..75f4dbe 100644 --- a/src/test/scala/e2e/AfeLoopback.scala +++ b/src/test/scala/e2e/AfeLoopback.scala @@ -5,7 +5,12 @@ import chisel3._ import chisel3.util._ import interfaces._ import org.chipsalliance.cde.config.{Field, Parameters, Config} -import chisel3.experimental.hierarchy.{Definition, Instance, instantiable, public} +import chisel3.experimental.hierarchy.{ + Definition, + Instance, + instantiable, + public, +} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink.{TLTestRAM} @@ -13,31 +18,34 @@ import protocol._ // @instantiable class AfeLoopback(val afeParams: AfeParams) extends Module { - val io = IO(new Bundle { - // val finished = Output(Bool()) - val mbAfe = Flipped(new MainbandAfeIo(afeParams)) - val sbAfe = Flipped(new SidebandAfeIo(afeParams)) - }) + val io = IO(new Bundle { + // val finished = Output(Bool()) + val mbAfe = Flipped(new MainbandAfeIo(afeParams)) + val sbAfe = Flipped(new SidebandAfeIo(afeParams)) + }) - val latency = 2 - val delayerMb = Module(new Pipe(chiselTypeOf(io.mbAfe.txData.bits), latency)) - val delayerSb = Module(new Pipe(chiselTypeOf(io.sbAfe.txData), latency)) - - delayerMb.io.enq.valid := io.mbAfe.txData.valid - delayerMb.io.enq.bits := io.mbAfe.txData.bits - io.mbAfe.rxData.bits := delayerMb.io.deq.bits - io.mbAfe.rxData.valid := delayerMb.io.deq.valid - io.mbAfe.txData.ready := true.B - io.mbAfe.fifoParams.clk := clock - io.mbAfe.fifoParams.reset := reset - io.mbAfe.pllLock := true.B + val latency = 2 + val delayerMb = Module(new Pipe(chiselTypeOf(io.mbAfe.txData.bits), latency)) + val delayerSb = Module(new Pipe(chiselTypeOf(io.sbAfe.txData), latency)) + val delayerSb_clock = Module( + new Pipe(chiselTypeOf(io.sbAfe.txClock), latency), + ) - delayerSb.io.enq.valid := true.B //io.sbAfe.txData.valid - delayerSb.io.enq.bits := io.sbAfe.txData - io.sbAfe.rxData := delayerSb.io.deq.bits - //io.sbAfe.rxData.valid := delayerSb.io.deq.valid - io.sbAfe.rxClock := io.sbAfe.txClock - io.sbAfe.fifoParams.clk := clock - io.sbAfe.fifoParams.reset := reset - io.sbAfe.pllLock := true.B - } \ No newline at end of file + delayerMb.io.enq.valid := io.mbAfe.txData.valid + delayerMb.io.enq.bits := io.mbAfe.txData.bits + io.mbAfe.rxData.bits := delayerMb.io.deq.bits + io.mbAfe.rxData.valid := delayerMb.io.deq.valid + io.mbAfe.txData.ready := true.B + io.mbAfe.fifoParams.clk := clock + io.mbAfe.fifoParams.reset := reset + io.mbAfe.pllLock := true.B + + delayerSb.io.enq.valid := true.B // io.sbAfe.txData.valid + delayerSb.io.enq.bits := io.sbAfe.txData + io.sbAfe.rxData := delayerSb.io.deq.bits + // io.sbAfe.rxData.valid := delayerSb.io.deq.valid + io.sbAfe.rxClock := delayerSb_clock.io.deq.bits + io.sbAfe.fifoParams.clk := clock + io.sbAfe.fifoParams.reset := reset + io.sbAfe.pllLock := true.B +} From 20f8f90eeab520c57f18c2ecf182fc48d4a87782 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 01:20:47 -0700 Subject: [PATCH 007/106] delay sb rx clock --- src/test/scala/e2e/AfeLoopback.scala | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/test/scala/e2e/AfeLoopback.scala b/src/test/scala/e2e/AfeLoopback.scala index 75f4dbe..91d0c28 100644 --- a/src/test/scala/e2e/AfeLoopback.scala +++ b/src/test/scala/e2e/AfeLoopback.scala @@ -42,6 +42,9 @@ class AfeLoopback(val afeParams: AfeParams) extends Module { delayerSb.io.enq.valid := true.B // io.sbAfe.txData.valid delayerSb.io.enq.bits := io.sbAfe.txData + delayerSb_clock.io.enq.valid := true.B + delayerSb_clock.io.enq.bits := io.sbAfe.txClock + io.sbAfe.rxData := delayerSb.io.deq.bits // io.sbAfe.rxData.valid := delayerSb.io.deq.valid io.sbAfe.rxClock := delayerSb_clock.io.deq.bits From 0af0db2bdd1f10e5547f669aba0037bb418841ca Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 01:29:07 -0700 Subject: [PATCH 008/106] questionable clock hack attempt 1 --- src/test/scala/e2e/AfeLoopback.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/test/scala/e2e/AfeLoopback.scala b/src/test/scala/e2e/AfeLoopback.scala index 91d0c28..98d9a7b 100644 --- a/src/test/scala/e2e/AfeLoopback.scala +++ b/src/test/scala/e2e/AfeLoopback.scala @@ -47,7 +47,7 @@ class AfeLoopback(val afeParams: AfeParams) extends Module { io.sbAfe.rxData := delayerSb.io.deq.bits // io.sbAfe.rxData.valid := delayerSb.io.deq.valid - io.sbAfe.rxClock := delayerSb_clock.io.deq.bits + io.sbAfe.rxClock := Mux(delayerSb_clock.io.deq.bits, clock, false.asBool) io.sbAfe.fifoParams.clk := clock io.sbAfe.fifoParams.reset := reset io.sbAfe.pllLock := true.B From 209f9276e655b6bbd073879ccc93cd78fa3de484 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 01:32:55 -0700 Subject: [PATCH 009/106] questionable clock hack attempt 1 --- src/test/scala/e2e/AfeLoopback.scala | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/test/scala/e2e/AfeLoopback.scala b/src/test/scala/e2e/AfeLoopback.scala index 98d9a7b..789467e 100644 --- a/src/test/scala/e2e/AfeLoopback.scala +++ b/src/test/scala/e2e/AfeLoopback.scala @@ -47,7 +47,11 @@ class AfeLoopback(val afeParams: AfeParams) extends Module { io.sbAfe.rxData := delayerSb.io.deq.bits // io.sbAfe.rxData.valid := delayerSb.io.deq.valid - io.sbAfe.rxClock := Mux(delayerSb_clock.io.deq.bits, clock, false.asBool) + io.sbAfe.rxClock := Mux( + delayerSb_clock.io.deq.bits, + clock.asBool, + false.asBool, + ) io.sbAfe.fifoParams.clk := clock io.sbAfe.fifoParams.reset := reset io.sbAfe.pllLock := true.B From 663c3dc691f368704b85a6c843471ab9058aaa0f Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 01:44:43 -0700 Subject: [PATCH 010/106] correct msg source --- src/main/scala/logphy/LinkTrainingFSM.scala | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/main/scala/logphy/LinkTrainingFSM.scala b/src/main/scala/logphy/LinkTrainingFSM.scala index 699c1eb..5a7cd44 100644 --- a/src/main/scala/logphy/LinkTrainingFSM.scala +++ b/src/main/scala/logphy/LinkTrainingFSM.scala @@ -145,11 +145,7 @@ class LinkTrainingFSM( * Mux(plStateStatus === )), */ // ) io.sidebandFSMIO.rxMode := Mux( - currentState === LinkTrainingState.sbInit && - (sbInitSubState === SBInitSubState.SEND_CLOCK || - sbInitSubState === SBInitSubState.WAIT_CLOCK || - sbInitSubState === SBInitSubState.SB_OUT_OF_RESET_EXCH || - sbInitSubState === SBInitSubState.SB_OUT_OF_RESET_WAIT), + msgSource === MsgSource.PATTERN_GENERATOR, RXTXMode.RAW, RXTXMode.PACKET, ) From c0768f2c8ebe6d2408b33040f17607be083fbf61 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 02:03:10 -0700 Subject: [PATCH 011/106] correct msg source --- src/main/scala/logphy/LinkTrainingFSM.scala | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/main/scala/logphy/LinkTrainingFSM.scala b/src/main/scala/logphy/LinkTrainingFSM.scala index 5a7cd44..417e1a2 100644 --- a/src/main/scala/logphy/LinkTrainingFSM.scala +++ b/src/main/scala/logphy/LinkTrainingFSM.scala @@ -72,14 +72,20 @@ class LinkTrainingFSM( sbMsgWrapper.io.trainIO.msgReq.noenq() sbMsgWrapper.io.trainIO.msgReqStatus.nodeq() - io.sidebandFSMIO.patternTxData <> patternGenerator.io.sidebandLaneIO.txData - io.sidebandFSMIO.packetTxData <> sbMsgWrapper.io.laneIO.txData when(msgSource === MsgSource.PATTERN_GENERATOR) { io.sidebandFSMIO.rxData <> patternGenerator.io.sidebandLaneIO.rxData sbMsgWrapper.io.laneIO.rxData.noenq() + io.sidebandFSMIO.patternTxData <> patternGenerator.io.sidebandLaneIO.txData }.otherwise { io.sidebandFSMIO.rxData <> sbMsgWrapper.io.laneIO.rxData patternGenerator.io.sidebandLaneIO.rxData.noenq() + when(io.sidebandFSMIO.rxMode === RXTXMode.RAW) { + io.sidebandFSMIO.patternTxData <> sbMsgWrapper.io.laneIO.txData + io.sidebandFSMIO.packetTxData.noenq() + }.otherwise { + io.sidebandFSMIO.patternTxData.noenq() + io.sidebandFSMIO.packetTxData <> sbMsgWrapper.io.laneIO.txData + } } private val currentState = RegInit(LinkTrainingState.reset) @@ -145,7 +151,11 @@ class LinkTrainingFSM( * Mux(plStateStatus === )), */ // ) io.sidebandFSMIO.rxMode := Mux( - msgSource === MsgSource.PATTERN_GENERATOR, + currentState === LinkTrainingState.sbInit && + (sbInitSubState === SBInitSubState.SEND_CLOCK || + sbInitSubState === SBInitSubState.WAIT_CLOCK || + sbInitSubState === SBInitSubState.SB_OUT_OF_RESET_EXCH || + sbInitSubState === SBInitSubState.SB_OUT_OF_RESET_WAIT), RXTXMode.RAW, RXTXMode.PACKET, ) From 9cfa8dbe104e19830ec8e2419936187a4e376f38 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 02:04:34 -0700 Subject: [PATCH 012/106] correct msg source --- src/main/scala/logphy/LinkTrainingFSM.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/logphy/LinkTrainingFSM.scala b/src/main/scala/logphy/LinkTrainingFSM.scala index 417e1a2..e1e7e71 100644 --- a/src/main/scala/logphy/LinkTrainingFSM.scala +++ b/src/main/scala/logphy/LinkTrainingFSM.scala @@ -75,10 +75,12 @@ class LinkTrainingFSM( when(msgSource === MsgSource.PATTERN_GENERATOR) { io.sidebandFSMIO.rxData <> patternGenerator.io.sidebandLaneIO.rxData sbMsgWrapper.io.laneIO.rxData.noenq() + sbMsgWrapper.io.laneIO.txData.nodeq() io.sidebandFSMIO.patternTxData <> patternGenerator.io.sidebandLaneIO.txData }.otherwise { io.sidebandFSMIO.rxData <> sbMsgWrapper.io.laneIO.rxData patternGenerator.io.sidebandLaneIO.rxData.noenq() + patternGenerator.io.sidebandLaneIO.txData.nodeq() when(io.sidebandFSMIO.rxMode === RXTXMode.RAW) { io.sidebandFSMIO.patternTxData <> sbMsgWrapper.io.laneIO.txData io.sidebandFSMIO.packetTxData.noenq() From d80a4517787e8e70c4ee8755040367b8401f461d Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 02:05:31 -0700 Subject: [PATCH 013/106] correct msg source --- src/main/scala/logphy/LinkTrainingFSM.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/logphy/LinkTrainingFSM.scala b/src/main/scala/logphy/LinkTrainingFSM.scala index e1e7e71..9fdd038 100644 --- a/src/main/scala/logphy/LinkTrainingFSM.scala +++ b/src/main/scala/logphy/LinkTrainingFSM.scala @@ -77,6 +77,7 @@ class LinkTrainingFSM( sbMsgWrapper.io.laneIO.rxData.noenq() sbMsgWrapper.io.laneIO.txData.nodeq() io.sidebandFSMIO.patternTxData <> patternGenerator.io.sidebandLaneIO.txData + io.sidebandFSMIO.packetTxData.noenq() }.otherwise { io.sidebandFSMIO.rxData <> sbMsgWrapper.io.laneIO.rxData patternGenerator.io.sidebandLaneIO.rxData.noenq() From e83da098fa4dc51980862d2bf1cc51c1d7fa9483 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 02:16:38 -0700 Subject: [PATCH 014/106] unsure -- sb timing issue --- src/main/scala/sideband/sidebandNode.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index f1d154a..ea7f5b6 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -322,9 +322,11 @@ class SidebandLinkDeserializer( val recvCount_delay = RegInit(0.U(log2Ceil(dataBeats).W)) recvCount_delay := recvCount + val recvDone_delay = RegInit(false.B) + recvDone_delay := recvDone data(recvCount_delay) := io.in.bits - when(recvDone) { receiving := false.B } + when(recvDone_delay) { receiving := false.B } when(io.out.fire) { receiving := true.B } io.out.valid := !receiving From 22c1fcbea34bc0832071e3db91063fa2b9c5006a Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 14:31:39 -0700 Subject: [PATCH 015/106] add async fifo --- src/main/scala/sideband/sidebandNode.scala | 30 ++++++++++++++-------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index ea7f5b6..7ee854c 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -3,7 +3,7 @@ package sideband import chisel3._ import chisel3.util._ - +import freechips.rocketchip.util.AsyncQueue import interfaces._ //TODO: 1) L317-318 needs to be revisited @@ -316,20 +316,30 @@ class SidebandLinkDeserializer( val receiving = RegInit(true.B) + val asyncFifo = Module( + new AsyncQueue( + UInt(msg_w.W), + ), + ) + + asyncFifo.io.deq <> io.out + asyncFifo.io.deq_clock := clock + asyncFifo.io.deq_reset := reset + asyncFifo.io.enq_clock := remote_clock + asyncFifo.io.enq_reset := reset + withClock(remote_clock) { val (recvCount, recvDone) = Counter(true.B, dataBeats) - val recvCount_delay = RegInit(0.U(log2Ceil(dataBeats).W)) - recvCount_delay := recvCount - val recvDone_delay = RegInit(false.B) - recvDone_delay := recvDone + // val recvCount_delay = RegInit(0.U(log2Ceil(dataBeats).W)) + // recvCount_delay := recvCount - data(recvCount_delay) := io.in.bits - when(recvDone_delay) { receiving := false.B } - when(io.out.fire) { receiving := true.B } - io.out.valid := !receiving + data(recvCount) := io.in.bits + when(recvDone) { receiving := false.B } + when(asyncFifo.io.enq.fire) { receiving := true.B } + asyncFifo.io.enq.valid := !receiving - io.out.bits := data.asUInt + asyncFifo.io.enq.bits := data.asUInt } } From 68ea5b6a571628aa9c485c5032340bc731ff986a Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 14:53:48 -0700 Subject: [PATCH 016/106] weird clock hacks pt 2 --- src/test/scala/e2e/AfeLoopback.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/test/scala/e2e/AfeLoopback.scala b/src/test/scala/e2e/AfeLoopback.scala index 789467e..3302d15 100644 --- a/src/test/scala/e2e/AfeLoopback.scala +++ b/src/test/scala/e2e/AfeLoopback.scala @@ -48,7 +48,7 @@ class AfeLoopback(val afeParams: AfeParams) extends Module { io.sbAfe.rxData := delayerSb.io.deq.bits // io.sbAfe.rxData.valid := delayerSb.io.deq.valid io.sbAfe.rxClock := Mux( - delayerSb_clock.io.deq.bits, + delayerSb_clock.io.deq.bits && delayerSb_clock.io.deq.valid, clock.asBool, false.asBool, ) From 368a95009944ac70d71403f7e6a46fc63564a55d Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 15:23:00 -0700 Subject: [PATCH 017/106] clock mux? --- src/main/scala/sideband/sidebandNode.scala | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 7ee854c..14d1309 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -314,8 +314,6 @@ class SidebandLinkDeserializer( val dataBeats = (dataBits - 1) / sb_w + 1 val data = Reg(Vec(dataBeats, UInt(sb_w.W))) - val receiving = RegInit(true.B) - val asyncFifo = Module( new AsyncQueue( UInt(msg_w.W), @@ -328,9 +326,10 @@ class SidebandLinkDeserializer( asyncFifo.io.enq_clock := remote_clock asyncFifo.io.enq_reset := reset - withClock(remote_clock) { + withClock(Mux(reset.asBool, clock, remote_clock)) { val (recvCount, recvDone) = Counter(true.B, dataBeats) + val receiving = RegInit(true.B) // val recvCount_delay = RegInit(0.U(log2Ceil(dataBeats).W)) // recvCount_delay := recvCount From 0b8838a54dae503ec2b9b72ac276cd1c4ed6bb37 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 15:26:02 -0700 Subject: [PATCH 018/106] clock mux? --- src/main/scala/sideband/sidebandNode.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 14d1309..216aa01 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -326,7 +326,7 @@ class SidebandLinkDeserializer( asyncFifo.io.enq_clock := remote_clock asyncFifo.io.enq_reset := reset - withClock(Mux(reset.asBool, clock, remote_clock)) { + withClock(Mux(reset.asBool, clock.asBool, remote_clock.asBool).asClock) { val (recvCount, recvDone) = Counter(true.B, dataBeats) val receiving = RegInit(true.B) From 0b0bc4417d5768edb11a2df481918f12ecdbdf8d Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 15:43:44 -0700 Subject: [PATCH 019/106] mux clocks --- src/main/resources/vsrc/ClockSelector.v | 14 ++++++++++++++ src/main/scala/sideband/sidebandNode.scala | 8 +++++++- src/main/scala/utils/ClockMux.scala | 16 ++++++++++++++++ 3 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 src/main/resources/vsrc/ClockSelector.v create mode 100644 src/main/scala/utils/ClockMux.scala diff --git a/src/main/resources/vsrc/ClockSelector.v b/src/main/resources/vsrc/ClockSelector.v new file mode 100644 index 0000000..7b8b2b5 --- /dev/null +++ b/src/main/resources/vsrc/ClockSelector.v @@ -0,0 +1,14 @@ +module ClockMux2 ( + input clocksIn_0, + input clocksIn_1, + input sel, + output clockOut +); + + // REPLACE ME WITH A CLOCK CELL IF DESIRED + + // XXX be careful with this! You can get really nasty short edges if you + // don't switch carefully + assign clockOut = sel ? clocksIn_1 : clocksIn_0; + +endmodule \ No newline at end of file diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 216aa01..d4efc11 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -5,6 +5,7 @@ import chisel3._ import chisel3.util._ import freechips.rocketchip.util.AsyncQueue import interfaces._ +import utils.ClockMux2 //TODO: 1) L317-318 needs to be revisited // 2) SidebandLinkDeserializer needs to have CDC crossings @@ -326,7 +327,12 @@ class SidebandLinkDeserializer( asyncFifo.io.enq_clock := remote_clock asyncFifo.io.enq_reset := reset - withClock(Mux(reset.asBool, clock.asBool, remote_clock.asBool).asClock) { + val clockMux2 = Module(new ClockMux2) + clockMux2.io.clocksIn(0) := clock + clockMux2.io.clocksIn(1) := remote_clock + clockMux2.io.sel := reset.asBool + + withClock(clockMux2.io.clockOut) { val (recvCount, recvDone) = Counter(true.B, dataBeats) val receiving = RegInit(true.B) diff --git a/src/main/scala/utils/ClockMux.scala b/src/main/scala/utils/ClockMux.scala new file mode 100644 index 0000000..64adef3 --- /dev/null +++ b/src/main/scala/utils/ClockMux.scala @@ -0,0 +1,16 @@ +package edu.berkeley.cs.ucie.digital +package utils + +import chisel3._ +import chisel3.util._ + +class ClockMux2 extends BlackBox with HasBlackBoxResource { + + val io = IO(new Bundle { + val clocksIn = Input(Vec(2, Clock())) + val sel = Input(Bool()) + val clockOut = Output(Clock()) + }) + + addResource("/uciedigital/src/main/resources/vsrc/ClockSelector.v") +} From f95d872740cf7033add2f6be8500561100c04b2a Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 15:45:56 -0700 Subject: [PATCH 020/106] mux clocks --- src/main/scala/utils/ClockMux.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/utils/ClockMux.scala b/src/main/scala/utils/ClockMux.scala index 64adef3..ce2afc6 100644 --- a/src/main/scala/utils/ClockMux.scala +++ b/src/main/scala/utils/ClockMux.scala @@ -12,5 +12,5 @@ class ClockMux2 extends BlackBox with HasBlackBoxResource { val clockOut = Output(Clock()) }) - addResource("/uciedigital/src/main/resources/vsrc/ClockSelector.v") + addResource("/vsrc/ClockSelector.v") } From ab3fe15d5fda64c2fe42362e19b3da6ec7738cf0 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 15:54:48 -0700 Subject: [PATCH 021/106] update test reset --- src/test/scala/e2e/AfeLoopbackTest.scala | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/test/scala/e2e/AfeLoopbackTest.scala b/src/test/scala/e2e/AfeLoopbackTest.scala index 50abf52..c45529c 100644 --- a/src/test/scala/e2e/AfeLoopbackTest.scala +++ b/src/test/scala/e2e/AfeLoopbackTest.scala @@ -110,7 +110,11 @@ class AfeLoopbackTest extends AnyFlatSpec with ChiselScalatestTester { test(new AfeTLTestHarness()).withAnnotations( Seq(VcsBackendAnnotation, WriteFsdbAnnotation), ) { c => // .withAnnotations(Seq(VcsBackendAnnotation, WriteVcdAnnotation)) + println("start Afe Loopback Test") + c.reset.poke(true.B) + c.clock.step(3) + c.reset.poke(false.B) c.clock.setTimeout(timeout + 10) c.clock.step(timeout) c.io.success.expect(true.B) From 5761196275733830ee066dfd9cc15457eca4c4fd Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 16:01:15 -0700 Subject: [PATCH 022/106] clock mux --- src/main/scala/sideband/sidebandNode.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index d4efc11..09a5fa4 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -328,8 +328,8 @@ class SidebandLinkDeserializer( asyncFifo.io.enq_reset := reset val clockMux2 = Module(new ClockMux2) - clockMux2.io.clocksIn(0) := clock - clockMux2.io.clocksIn(1) := remote_clock + clockMux2.io.clocksIn(0) := remote_clock + clockMux2.io.clocksIn(1) := clock clockMux2.io.sel := reset.asBool withClock(clockMux2.io.clockOut) { From 13a7554145ac2fbf03f1d2878fafbe755e2faa30 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 16:23:48 -0700 Subject: [PATCH 023/106] async reset --- src/main/scala/sideband/sidebandNode.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 09a5fa4..7553b8d 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -327,12 +327,12 @@ class SidebandLinkDeserializer( asyncFifo.io.enq_clock := remote_clock asyncFifo.io.enq_reset := reset - val clockMux2 = Module(new ClockMux2) - clockMux2.io.clocksIn(0) := remote_clock - clockMux2.io.clocksIn(1) := clock - clockMux2.io.sel := reset.asBool + // val clockMux2 = Module(new ClockMux2) + // clockMux2.io.clocksIn(0) := remote_clock + // clockMux2.io.clocksIn(1) := clock + // clockMux2.io.sel := reset.asBool - withClock(clockMux2.io.clockOut) { + withClockAndReset(remote_clock, reset.asAsyncReset) { val (recvCount, recvDone) = Counter(true.B, dataBeats) val receiving = RegInit(true.B) From 3c689b8a779dc15fd306a0037fe599aa6029a49e Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 16:39:47 -0700 Subject: [PATCH 024/106] make own counter --- src/main/scala/sideband/sidebandNode.scala | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 7553b8d..f3b6534 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -334,7 +334,12 @@ class SidebandLinkDeserializer( withClockAndReset(remote_clock, reset.asAsyncReset) { - val (recvCount, recvDone) = Counter(true.B, dataBeats) + // val (recvCount, recvDone) = Counter(true.B, dataBeats) + val recvCount = RegInit(0.U(dataBeats.W)) + val recvDone = WireInit(recvCount === (dataBeats - 1).U) + when(recvDone) { + recvCount := 0.U + } val receiving = RegInit(true.B) // val recvCount_delay = RegInit(0.U(log2Ceil(dataBeats).W)) From 3afae52ea17ec7e27b0135ba023408acf6e83e73 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 16:44:06 -0700 Subject: [PATCH 025/106] make own counter --- src/main/scala/sideband/sidebandNode.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index f3b6534..a308608 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -339,6 +339,8 @@ class SidebandLinkDeserializer( val recvDone = WireInit(recvCount === (dataBeats - 1).U) when(recvDone) { recvCount := 0.U + }.otherwise { + recvCount := recvCount + 1 } val receiving = RegInit(true.B) From ce91b17c35b7a4f9dcffaaedaec90d0bc7535302 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 16:45:04 -0700 Subject: [PATCH 026/106] make own counter --- src/main/scala/sideband/sidebandNode.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index a308608..7e0068f 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -340,7 +340,7 @@ class SidebandLinkDeserializer( when(recvDone) { recvCount := 0.U }.otherwise { - recvCount := recvCount + 1 + recvCount := recvCount + 1.U } val receiving = RegInit(true.B) From 052b07fb9d0c01c716665d0544402bc6a2236862 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 17:13:52 -0700 Subject: [PATCH 027/106] counter reset value hacks --- src/main/scala/sideband/sidebandNode.scala | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 7e0068f..0c6e8da 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -3,7 +3,7 @@ package sideband import chisel3._ import chisel3.util._ -import freechips.rocketchip.util.AsyncQueue +import freechips.rocketchip.util.{AsyncQueue, AsyncResetReg} import interfaces._ import utils.ClockMux2 @@ -335,14 +335,15 @@ class SidebandLinkDeserializer( withClockAndReset(remote_clock, reset.asAsyncReset) { // val (recvCount, recvDone) = Counter(true.B, dataBeats) - val recvCount = RegInit(0.U(dataBeats.W)) + val recvCount = RegInit((dataBeats - 1).U(log2Ceil(dataBeats + 2).W)) val recvDone = WireInit(recvCount === (dataBeats - 1).U) - when(recvDone) { + val receiving = RegInit(true.B) + + when(recvCount === dataBeats) { recvCount := 0.U - }.otherwise { + }.elsewhen(receiving) { recvCount := recvCount + 1.U } - val receiving = RegInit(true.B) // val recvCount_delay = RegInit(0.U(log2Ceil(dataBeats).W)) // recvCount_delay := recvCount From c273448a587e282de0ed8dbda4e7fbdf9f8330cb Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 17:16:46 -0700 Subject: [PATCH 028/106] counter reset value hacks --- src/main/scala/sideband/sidebandNode.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 0c6e8da..aad52be 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -335,11 +335,11 @@ class SidebandLinkDeserializer( withClockAndReset(remote_clock, reset.asAsyncReset) { // val (recvCount, recvDone) = Counter(true.B, dataBeats) - val recvCount = RegInit((dataBeats - 1).U(log2Ceil(dataBeats + 2).W)) + val recvCount = RegInit(0.U(log2Ceil(dataBeats + 1).W)) val recvDone = WireInit(recvCount === (dataBeats - 1).U) val receiving = RegInit(true.B) - when(recvCount === dataBeats) { + when(recvCount === (dataBeats - 1).U) { recvCount := 0.U }.elsewhen(receiving) { recvCount := recvCount + 1.U From 386ae40f5c5c0b9ffd602062c4e4a352007be368 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 17:35:41 -0700 Subject: [PATCH 029/106] move data inside clock block --- src/main/scala/sideband/sidebandNode.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index aad52be..5631cf9 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -313,7 +313,6 @@ class SidebandLinkDeserializer( val dataBits = msg_w val dataBeats = (dataBits - 1) / sb_w + 1 - val data = Reg(Vec(dataBeats, UInt(sb_w.W))) val asyncFifo = Module( new AsyncQueue( @@ -333,6 +332,7 @@ class SidebandLinkDeserializer( // clockMux2.io.sel := reset.asBool withClockAndReset(remote_clock, reset.asAsyncReset) { + val data = Reg(Vec(dataBeats, UInt(sb_w.W))) // val (recvCount, recvDone) = Counter(true.B, dataBeats) val recvCount = RegInit(0.U(log2Ceil(dataBeats + 1).W)) From 4389f3c6f76669811895b27ae37fbbb9abba1bdd Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 18:25:55 -0700 Subject: [PATCH 030/106] use negedge clock --- src/main/scala/sideband/sidebandNode.scala | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 5631cf9..004dc2d 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -331,19 +331,19 @@ class SidebandLinkDeserializer( // clockMux2.io.clocksIn(1) := clock // clockMux2.io.sel := reset.asBool - withClockAndReset(remote_clock, reset.asAsyncReset) { + withClockAndReset((!remote_clock.asBool).asClock, reset.asAsyncReset) { val data = Reg(Vec(dataBeats, UInt(sb_w.W))) - // val (recvCount, recvDone) = Counter(true.B, dataBeats) - val recvCount = RegInit(0.U(log2Ceil(dataBeats + 1).W)) - val recvDone = WireInit(recvCount === (dataBeats - 1).U) + val (recvCount, recvDone) = Counter(true.B, dataBeats) + // val recvCount = RegInit(0.U(log2Ceil(dataBeats + 1).W)) + // val recvDone = WireInit(recvCount === (dataBeats - 1).U) val receiving = RegInit(true.B) - when(recvCount === (dataBeats - 1).U) { - recvCount := 0.U - }.elsewhen(receiving) { - recvCount := recvCount + 1.U - } + // when(recvCount === (dataBeats - 1).U) { + // recvCount := 0.U + // }.elsewhen(receiving) { + // recvCount := recvCount + 1.U + // } // val recvCount_delay = RegInit(0.U(log2Ceil(dataBeats).W)) // recvCount_delay := recvCount From 7ae41c55f76f2058cb3f7ded0853429b42bc8c1f Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 18:50:55 -0700 Subject: [PATCH 031/106] negedge?? --- src/main/scala/sideband/sidebandNode.scala | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 004dc2d..894b49b 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -331,13 +331,21 @@ class SidebandLinkDeserializer( // clockMux2.io.clocksIn(1) := clock // clockMux2.io.sel := reset.asBool - withClockAndReset((!remote_clock.asBool).asClock, reset.asAsyncReset) { - val data = Reg(Vec(dataBeats, UInt(sb_w.W))) + withClockAndReset(remote_clock, reset.asAsyncReset) { - val (recvCount, recvDone) = Counter(true.B, dataBeats) + val inv_clock = (!remote_clock.asBool).asClock + val data = withClockAndReset(inv_clock, reset.asAsyncReset)( + Reg(Vec(dataBeats, UInt(sb_w.W))), + ) + + val (recvCount, recvDone) = + withClockAndReset(inv_clock, reset.asAsyncReset)( + Counter(true.B, dataBeats), + ) // val recvCount = RegInit(0.U(log2Ceil(dataBeats + 1).W)) // val recvDone = WireInit(recvCount === (dataBeats - 1).U) - val receiving = RegInit(true.B) + val receiving = + withClockAndReset(inv_clock, reset.asAsyncReset)(RegInit(true.B)) // when(recvCount === (dataBeats - 1).U) { // recvCount := 0.U From 6068bf26c77f89ed085deba01742455dec6eff1b Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 18:59:05 -0700 Subject: [PATCH 032/106] negedge?? --- src/main/scala/sideband/sidebandNode.scala | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 894b49b..9f8a539 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -331,21 +331,15 @@ class SidebandLinkDeserializer( // clockMux2.io.clocksIn(1) := clock // clockMux2.io.sel := reset.asBool - withClockAndReset(remote_clock, reset.asAsyncReset) { + val inv_clock = (!remote_clock.asBool).asClock + withClockAndReset(inv_clock, reset.asAsyncReset) { - val inv_clock = (!remote_clock.asBool).asClock - val data = withClockAndReset(inv_clock, reset.asAsyncReset)( - Reg(Vec(dataBeats, UInt(sb_w.W))), - ) + val data = Reg(Vec(dataBeats, UInt(sb_w.W))) - val (recvCount, recvDone) = - withClockAndReset(inv_clock, reset.asAsyncReset)( - Counter(true.B, dataBeats), - ) + val (recvCount, recvDone) = Counter(true.B, dataBeats) // val recvCount = RegInit(0.U(log2Ceil(dataBeats + 1).W)) // val recvDone = WireInit(recvCount === (dataBeats - 1).U) - val receiving = - withClockAndReset(inv_clock, reset.asAsyncReset)(RegInit(true.B)) + val receiving = RegInit(true.B) // when(recvCount === (dataBeats - 1).U) { // recvCount := 0.U From 6f4e7bed5d35021cf2e1b0cad0ed695090fbd722 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 19:41:34 -0700 Subject: [PATCH 033/106] attempt black box resource --- src/main/resources/vsrc/SBDeserializer.v | 44 ++++++++++++++++++++ src/main/scala/sideband/sidebandNode.scala | 48 +++++++++++++--------- 2 files changed, 72 insertions(+), 20 deletions(-) create mode 100644 src/main/resources/vsrc/SBDeserializer.v diff --git a/src/main/resources/vsrc/SBDeserializer.v b/src/main/resources/vsrc/SBDeserializer.v new file mode 100644 index 0000000..7947d24 --- /dev/null +++ b/src/main/resources/vsrc/SBDeserializer.v @@ -0,0 +1,44 @@ +module SBDeserializer #( + parameter WIDTH, + parameter WIDTH_W, +) ( + input clk, + input rst, + input in_data, + input out_data_ready, + output [WIDTH - 1:0] out_data, + output out_data_valid, + +); + +reg [WIDTH_W-1:0] counter; +reg [WIDTH-1:0] data_reg; +reg receiving; +wire recvDone; + +assign out_data = data_reg; +assign recvDone = counter == (WIDTH - 1); +assign out_data_valid = !receiving; + +always @(negedge clk or posedge rst) begin + if (rst) begin + counter <= 0; + receiving <= 1'b1; + end else begin + if (recvDone) begin + counter <= 0; + receiving <= 1'b0; + end else begin + counter <= counter + 1'b1; + end + if (out_data_valid && out_data_ready) begin + receiving <= 1'b1; + end + + data_reg[counter] <= in_data; + + end + +end + +endmodule \ No newline at end of file diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 9f8a539..91577dd 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -331,30 +331,38 @@ class SidebandLinkDeserializer( // clockMux2.io.clocksIn(1) := clock // clockMux2.io.sel := reset.asBool - val inv_clock = (!remote_clock.asBool).asClock - withClockAndReset(inv_clock, reset.asAsyncReset) { + // val inv_clock = (!remote_clock.asBool).asClock + withClockAndReset(remote_clock, reset.asAsyncReset) { - val data = Reg(Vec(dataBeats, UInt(sb_w.W))) + val sbDeserBlackBox = Module(new SBDeserializerBlackBox(msg_w)) + asyncFifo.io.enq.valid := sbDeserBlackBox.io.out_data_valid + asyncFifo.io.enq.bits := sbDeserBlackBox.io.out_data + sbDeserBlackBox.io.out_data_ready := asyncFifo.io.enq.ready + sbDeserBlackBox.io.in_data := io.in.bits - val (recvCount, recvDone) = Counter(true.B, dataBeats) - // val recvCount = RegInit(0.U(log2Ceil(dataBeats + 1).W)) - // val recvDone = WireInit(recvCount === (dataBeats - 1).U) - val receiving = RegInit(true.B) + // val data = Reg(Vec(dataBeats, UInt(sb_w.W))) - // when(recvCount === (dataBeats - 1).U) { - // recvCount := 0.U - // }.elsewhen(receiving) { - // recvCount := recvCount + 1.U - // } + // val (recvCount, recvDone) = Counter(true.B, dataBeats) + // val receiving = RegInit(true.B) - // val recvCount_delay = RegInit(0.U(log2Ceil(dataBeats).W)) - // recvCount_delay := recvCount + // data(recvCount) := io.in.bits + // when(recvDone) { receiving := false.B } + // when(asyncFifo.io.enq.fire) { receiving := true.B } + // asyncFifo.io.enq.valid := !receiving - data(recvCount) := io.in.bits - when(recvDone) { receiving := false.B } - when(asyncFifo.io.enq.fire) { receiving := true.B } - asyncFifo.io.enq.valid := !receiving - - asyncFifo.io.enq.bits := data.asUInt + // asyncFifo.io.enq.bits := data.asUInt } } + +class SBDeserializerBlackBox(val width: Int) + extends BlackBox(Map("WIDTH" -> width, "WIDTH_W" -> log2Ceil(width))) + with HasBlackBoxResource { + val io = IO(new Bundle { + val in_data = Input(Wire(UInt(1.W))) + val out_data_ready = Input(Bool()) + val out_data = Output(Wire(UInt(128.W))) + val out_data_valid = Output(Bool()) + }) + + addResource("/vsrc/SBDeserializer.v") +} From 3517b09ce70191b4c1552b9eb3d0e7d1744b91c7 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 19:45:19 -0700 Subject: [PATCH 034/106] attempt black box resource --- src/main/scala/sideband/sidebandNode.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 91577dd..43e86f4 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -358,9 +358,9 @@ class SBDeserializerBlackBox(val width: Int) extends BlackBox(Map("WIDTH" -> width, "WIDTH_W" -> log2Ceil(width))) with HasBlackBoxResource { val io = IO(new Bundle { - val in_data = Input(Wire(UInt(1.W))) + val in_data = Input(UInt(1.W)) val out_data_ready = Input(Bool()) - val out_data = Output(Wire(UInt(128.W))) + val out_data = Output(UInt(width.W)) val out_data_valid = Output(Bool()) }) From bf6891312ba335b32bae718044f2ce86ce8274d2 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 19:46:55 -0700 Subject: [PATCH 035/106] attempt black box resource --- src/main/resources/vsrc/SBDeserializer.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/resources/vsrc/SBDeserializer.v b/src/main/resources/vsrc/SBDeserializer.v index 7947d24..4d41abe 100644 --- a/src/main/resources/vsrc/SBDeserializer.v +++ b/src/main/resources/vsrc/SBDeserializer.v @@ -1,13 +1,13 @@ module SBDeserializer #( parameter WIDTH, - parameter WIDTH_W, + parameter WIDTH_W ) ( input clk, input rst, input in_data, input out_data_ready, output [WIDTH - 1:0] out_data, - output out_data_valid, + output out_data_valid ); From a5acb205a1542814ac9fa85ff8a005cc6e5ba746 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 19:49:13 -0700 Subject: [PATCH 036/106] attempt black box resource --- src/main/scala/sideband/sidebandNode.scala | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 43e86f4..e54e649 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -2,10 +2,10 @@ package edu.berkeley.cs.ucie.digital package sideband import chisel3._ +import chisel3.experimental._ import chisel3.util._ import freechips.rocketchip.util.{AsyncQueue, AsyncResetReg} import interfaces._ -import utils.ClockMux2 //TODO: 1) L317-318 needs to be revisited // 2) SidebandLinkDeserializer needs to have CDC crossings @@ -355,7 +355,9 @@ class SidebandLinkDeserializer( } class SBDeserializerBlackBox(val width: Int) - extends BlackBox(Map("WIDTH" -> width, "WIDTH_W" -> log2Ceil(width))) + extends BlackBox( + Map("WIDTH" -> IntParam(width), "WIDTH_W" -> IntParam(log2Ceil(width))), + ) with HasBlackBoxResource { val io = IO(new Bundle { val in_data = Input(UInt(1.W)) From 986f4c8e18edae149847ef16049b241999e7a5c0 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 19:53:10 -0700 Subject: [PATCH 037/106] attempt black box resource --- src/main/resources/vsrc/SBDeserializer.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/resources/vsrc/SBDeserializer.v b/src/main/resources/vsrc/SBDeserializer.v index 4d41abe..416f303 100644 --- a/src/main/resources/vsrc/SBDeserializer.v +++ b/src/main/resources/vsrc/SBDeserializer.v @@ -1,6 +1,6 @@ module SBDeserializer #( - parameter WIDTH, - parameter WIDTH_W + parameter WIDTH = 128, + parameter WIDTH_W = 8 ) ( input clk, input rst, From 27eb7d78c30681eb583197f89b1ae32a8a2b6134 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 19:56:54 -0700 Subject: [PATCH 038/106] attempt black box resource --- src/main/scala/sideband/sidebandNode.scala | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index e54e649..018b67c 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -335,6 +335,8 @@ class SidebandLinkDeserializer( withClockAndReset(remote_clock, reset.asAsyncReset) { val sbDeserBlackBox = Module(new SBDeserializerBlackBox(msg_w)) + sbDeserBlackBox.io.clk := clock + sbDeserBlackBox.io.rst := reset.asAsyncReset asyncFifo.io.enq.valid := sbDeserBlackBox.io.out_data_valid asyncFifo.io.enq.bits := sbDeserBlackBox.io.out_data sbDeserBlackBox.io.out_data_ready := asyncFifo.io.enq.ready @@ -356,10 +358,15 @@ class SidebandLinkDeserializer( class SBDeserializerBlackBox(val width: Int) extends BlackBox( - Map("WIDTH" -> IntParam(width), "WIDTH_W" -> IntParam(log2Ceil(width))), + Map( + "WIDTH" -> IntParam(width), + "WIDTH_W" -> IntParam(log2Ceil(width) + 1), + ), ) with HasBlackBoxResource { val io = IO(new Bundle { + val clk = Input(Clock()) + val rst = Input(Reset()) val in_data = Input(UInt(1.W)) val out_data_ready = Input(Bool()) val out_data = Output(UInt(width.W)) From e54aeb4bcf62b13074ab558d8dc90647dc17266e Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 19:58:45 -0700 Subject: [PATCH 039/106] attempt black box resource --- src/main/resources/vsrc/SBDeserializer.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/resources/vsrc/SBDeserializer.v b/src/main/resources/vsrc/SBDeserializer.v index 416f303..924f61a 100644 --- a/src/main/resources/vsrc/SBDeserializer.v +++ b/src/main/resources/vsrc/SBDeserializer.v @@ -1,4 +1,4 @@ -module SBDeserializer #( +module SBDeserializerBlackBox #( parameter WIDTH = 128, parameter WIDTH_W = 8 ) ( From 4e7b9c88fbf763fb35308bf97c041463102923e8 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 20:02:07 -0700 Subject: [PATCH 040/106] attempt black box resource --- src/main/scala/sideband/sidebandNode.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 018b67c..2118578 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -335,7 +335,7 @@ class SidebandLinkDeserializer( withClockAndReset(remote_clock, reset.asAsyncReset) { val sbDeserBlackBox = Module(new SBDeserializerBlackBox(msg_w)) - sbDeserBlackBox.io.clk := clock + sbDeserBlackBox.io.clk := remote_clock sbDeserBlackBox.io.rst := reset.asAsyncReset asyncFifo.io.enq.valid := sbDeserBlackBox.io.out_data_valid asyncFifo.io.enq.bits := sbDeserBlackBox.io.out_data From 733589546b8d3834cd37e404078c2d65b0c84742 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 20:06:18 -0700 Subject: [PATCH 041/106] system clock test --- src/main/scala/sideband/sidebandNode.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 2118578..38eed83 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -332,7 +332,7 @@ class SidebandLinkDeserializer( // clockMux2.io.sel := reset.asBool // val inv_clock = (!remote_clock.asBool).asClock - withClockAndReset(remote_clock, reset.asAsyncReset) { + withClockAndReset(clock, reset.asAsyncReset) { val sbDeserBlackBox = Module(new SBDeserializerBlackBox(msg_w)) sbDeserBlackBox.io.clk := remote_clock From 6de79dda9664224e0a28e8279207bbe616e8bb3a Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 20:11:02 -0700 Subject: [PATCH 042/106] system clock test --- src/main/scala/sideband/sidebandNode.scala | 34 +++++++++++----------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 38eed83..c7a7faa 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -332,28 +332,28 @@ class SidebandLinkDeserializer( // clockMux2.io.sel := reset.asBool // val inv_clock = (!remote_clock.asBool).asClock - withClockAndReset(clock, reset.asAsyncReset) { + // withClockAndReset(clock, reset.asAsyncReset) { - val sbDeserBlackBox = Module(new SBDeserializerBlackBox(msg_w)) - sbDeserBlackBox.io.clk := remote_clock - sbDeserBlackBox.io.rst := reset.asAsyncReset - asyncFifo.io.enq.valid := sbDeserBlackBox.io.out_data_valid - asyncFifo.io.enq.bits := sbDeserBlackBox.io.out_data - sbDeserBlackBox.io.out_data_ready := asyncFifo.io.enq.ready - sbDeserBlackBox.io.in_data := io.in.bits + val sbDeserBlackBox = Module(new SBDeserializerBlackBox(msg_w)) + sbDeserBlackBox.io.clk := remote_clock + sbDeserBlackBox.io.rst := reset.asAsyncReset + asyncFifo.io.enq.valid := sbDeserBlackBox.io.out_data_valid + asyncFifo.io.enq.bits := sbDeserBlackBox.io.out_data + sbDeserBlackBox.io.out_data_ready := asyncFifo.io.enq.ready + sbDeserBlackBox.io.in_data := io.in.bits - // val data = Reg(Vec(dataBeats, UInt(sb_w.W))) + // val data = Reg(Vec(dataBeats, UInt(sb_w.W))) - // val (recvCount, recvDone) = Counter(true.B, dataBeats) - // val receiving = RegInit(true.B) + // val (recvCount, recvDone) = Counter(true.B, dataBeats) + // val receiving = RegInit(true.B) - // data(recvCount) := io.in.bits - // when(recvDone) { receiving := false.B } - // when(asyncFifo.io.enq.fire) { receiving := true.B } - // asyncFifo.io.enq.valid := !receiving + // data(recvCount) := io.in.bits + // when(recvDone) { receiving := false.B } + // when(asyncFifo.io.enq.fire) { receiving := true.B } + // asyncFifo.io.enq.valid := !receiving - // asyncFifo.io.enq.bits := data.asUInt - } + // asyncFifo.io.enq.bits := data.asUInt + // } } class SBDeserializerBlackBox(val width: Int) From 43d2a9eac506319184417ae93387d6a072b67c00 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 20:17:19 -0700 Subject: [PATCH 043/106] system clock test --- src/main/scala/sideband/sidebandNode.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index c7a7faa..23168d8 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -335,7 +335,7 @@ class SidebandLinkDeserializer( // withClockAndReset(clock, reset.asAsyncReset) { val sbDeserBlackBox = Module(new SBDeserializerBlackBox(msg_w)) - sbDeserBlackBox.io.clk := remote_clock + sbDeserBlackBox.io.clk := clock sbDeserBlackBox.io.rst := reset.asAsyncReset asyncFifo.io.enq.valid := sbDeserBlackBox.io.out_data_valid asyncFifo.io.enq.bits := sbDeserBlackBox.io.out_data From a448fdf2eafdaa4ce0917fc21d6892b358c06fb6 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 20:22:44 -0700 Subject: [PATCH 044/106] revert system clock test --- src/main/scala/sideband/sidebandNode.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 23168d8..c7a7faa 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -335,7 +335,7 @@ class SidebandLinkDeserializer( // withClockAndReset(clock, reset.asAsyncReset) { val sbDeserBlackBox = Module(new SBDeserializerBlackBox(msg_w)) - sbDeserBlackBox.io.clk := clock + sbDeserBlackBox.io.clk := remote_clock sbDeserBlackBox.io.rst := reset.asAsyncReset asyncFifo.io.enq.valid := sbDeserBlackBox.io.out_data_valid asyncFifo.io.enq.bits := sbDeserBlackBox.io.out_data From 58541b404bec229e7fb17419b51fd0431b1f1b64 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 3 May 2024 20:29:25 -0700 Subject: [PATCH 045/106] undelayed clock test --- src/test/scala/e2e/AfeLoopback.scala | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/test/scala/e2e/AfeLoopback.scala b/src/test/scala/e2e/AfeLoopback.scala index 3302d15..0cf5945 100644 --- a/src/test/scala/e2e/AfeLoopback.scala +++ b/src/test/scala/e2e/AfeLoopback.scala @@ -47,11 +47,12 @@ class AfeLoopback(val afeParams: AfeParams) extends Module { io.sbAfe.rxData := delayerSb.io.deq.bits // io.sbAfe.rxData.valid := delayerSb.io.deq.valid - io.sbAfe.rxClock := Mux( - delayerSb_clock.io.deq.bits && delayerSb_clock.io.deq.valid, - clock.asBool, - false.asBool, - ) + io.sbAfe.rxClock := io.sbAfe.txClock + // io.sbAfe.rxClock := Mux( + // delayerSb_clock.io.deq.bits && delayerSb_clock.io.deq.valid, + // clock.asBool, + // false.asBool, + // ) io.sbAfe.fifoParams.clk := clock io.sbAfe.fifoParams.reset := reset io.sbAfe.pllLock := true.B From 21a271cbee99c959901b5dd5295de1d45b895677 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 01:26:34 -0700 Subject: [PATCH 046/106] sb serializer negedge? --- src/main/resources/vsrc/SBSerializer.v | 0 src/main/scala/sideband/sidebandNode.scala | 8 ++++++-- 2 files changed, 6 insertions(+), 2 deletions(-) create mode 100644 src/main/resources/vsrc/SBSerializer.v diff --git a/src/main/resources/vsrc/SBSerializer.v b/src/main/resources/vsrc/SBSerializer.v new file mode 100644 index 0000000..e69de29 diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index c7a7faa..2f8390a 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -4,7 +4,7 @@ package sideband import chisel3._ import chisel3.experimental._ import chisel3.util._ -import freechips.rocketchip.util.{AsyncQueue, AsyncResetReg} +import freechips.rocketchip.util.{AsyncQueue, AsyncResetReg, ClockGate} import interfaces._ //TODO: 1) L317-318 needs to be revisited @@ -268,7 +268,11 @@ class SidebandLinkSerializer( val isComplete = RegInit(false.B) io.in.ready := (waited) // wait for 32 cycles between SB messages - io.out.clock := Mux(sending, clock.asUInt, false.B) + + val sendNegEdge = withClock((!clock.asBool).asClock)(RegInit(false.B)) + sendNegEdge := sending + + io.out.clock := Mux(sendNegEdge, clock.asUInt, false.B) io.out.bits := data(sb_w - 1, 0) counter_en := false.B From ced197917287eca66aeeb50b4389e4850c24b0a3 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 01:33:46 -0700 Subject: [PATCH 047/106] undo un-delay in afe loopback --- src/test/scala/e2e/AfeLoopback.scala | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/test/scala/e2e/AfeLoopback.scala b/src/test/scala/e2e/AfeLoopback.scala index 0cf5945..3302d15 100644 --- a/src/test/scala/e2e/AfeLoopback.scala +++ b/src/test/scala/e2e/AfeLoopback.scala @@ -47,12 +47,11 @@ class AfeLoopback(val afeParams: AfeParams) extends Module { io.sbAfe.rxData := delayerSb.io.deq.bits // io.sbAfe.rxData.valid := delayerSb.io.deq.valid - io.sbAfe.rxClock := io.sbAfe.txClock - // io.sbAfe.rxClock := Mux( - // delayerSb_clock.io.deq.bits && delayerSb_clock.io.deq.valid, - // clock.asBool, - // false.asBool, - // ) + io.sbAfe.rxClock := Mux( + delayerSb_clock.io.deq.bits && delayerSb_clock.io.deq.valid, + clock.asBool, + false.asBool, + ) io.sbAfe.fifoParams.clk := clock io.sbAfe.fifoParams.reset := reset io.sbAfe.pllLock := true.B From 430522d874b50a6ab4b042bf145e37c58f23d744 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 01:39:18 -0700 Subject: [PATCH 048/106] negedge afe loopback test --- src/test/scala/e2e/AfeLoopback.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/test/scala/e2e/AfeLoopback.scala b/src/test/scala/e2e/AfeLoopback.scala index 3302d15..e6071da 100644 --- a/src/test/scala/e2e/AfeLoopback.scala +++ b/src/test/scala/e2e/AfeLoopback.scala @@ -47,8 +47,10 @@ class AfeLoopback(val afeParams: AfeParams) extends Module { io.sbAfe.rxData := delayerSb.io.deq.bits // io.sbAfe.rxData.valid := delayerSb.io.deq.valid + val delayNegEdge = withClock((!clock.asBool).asClock)(RegInit(false.B)) + delayNegEdge := delayerSb_clock.io.deq.bits && delayerSb_clock.io.deq.valid io.sbAfe.rxClock := Mux( - delayerSb_clock.io.deq.bits && delayerSb_clock.io.deq.valid, + delayNegEdge, clock.asBool, false.asBool, ) From 78e1a87defd43bca4dc03fb4da50e7c6ea221e40 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 01:52:27 -0700 Subject: [PATCH 049/106] hacky serializer cycle delay fix --- src/main/scala/sideband/sidebandNode.scala | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 2f8390a..eff7ea2 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -278,12 +278,18 @@ class SidebandLinkSerializer( counter_en := false.B io.counter := counter + val cycDelay = RegInit(false.B) when(io.in.fire) { + cycDelay := true.B + } + + when(cycDelay) { data := io.in.bits.asUInt sending := true.B waited := false.B counter_next := 0.U + cycDelay := false.B } when(sending) { data := data >> sb_w.U } From 1d26025c2514f653f4776a255ef4291019f77448 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 01:57:12 -0700 Subject: [PATCH 050/106] hacky serializer cycle delay fix --- src/main/scala/sideband/sidebandNode.scala | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index eff7ea2..b5745f6 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -270,7 +270,8 @@ class SidebandLinkSerializer( io.in.ready := (waited) // wait for 32 cycles between SB messages val sendNegEdge = withClock((!clock.asBool).asClock)(RegInit(false.B)) - sendNegEdge := sending + val sendEarly = RegInit(false.B) + sendNegEdge := sending || sendEarly io.out.clock := Mux(sendNegEdge, clock.asUInt, false.B) io.out.bits := data(sb_w - 1, 0) @@ -278,18 +279,17 @@ class SidebandLinkSerializer( counter_en := false.B io.counter := counter - val cycDelay = RegInit(false.B) when(io.in.fire) { - cycDelay := true.B + data := io.in.bits.asUInt + sendEarly := true.B } - when(cycDelay) { - data := io.in.bits.asUInt + when(sendEarly) { sending := true.B waited := false.B counter_next := 0.U - cycDelay := false.B + sendEarly := false.B } when(sending) { data := data >> sb_w.U } From c0a06e90d0a0ac6c76db131648f4f293b18d5608 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 02:05:59 -0700 Subject: [PATCH 051/106] hacky serializer cycle delay fix --- src/main/scala/sideband/sidebandNode.scala | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index b5745f6..e284251 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -263,15 +263,15 @@ class SidebandLinkSerializer( val sending = RegInit(false.B) val done = RegInit(false.B) val waited = RegInit(true.B) - val (sendCount, sendDone) = Counter(sending, dataBeats) + val (sendCount, sendDone) = Counter(sending && !delay, dataBeats) val isComplete = RegInit(false.B) io.in.ready := (waited) // wait for 32 cycles between SB messages val sendNegEdge = withClock((!clock.asBool).asClock)(RegInit(false.B)) - val sendEarly = RegInit(false.B) - sendNegEdge := sending || sendEarly + val delay = RegInit(false.B) + sendNegEdge := sending io.out.clock := Mux(sendNegEdge, clock.asUInt, false.B) io.out.bits := data(sb_w - 1, 0) @@ -282,17 +282,17 @@ class SidebandLinkSerializer( when(io.in.fire) { data := io.in.bits.asUInt - sendEarly := true.B - } - - when(sendEarly) { + delay := true.B sending := true.B waited := false.B counter_next := 0.U - sendEarly := false.B } - when(sending) { data := data >> sb_w.U } + when(delay) { + delay := false.B + } + + when(sending && !delay) { data := data >> sb_w.U } when(sendDone) { sending := false.B From e8da256e12033b4652144014c81fd871c4c01a9b Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 02:06:49 -0700 Subject: [PATCH 052/106] hacky serializer cycle delay fix --- src/main/scala/sideband/sidebandNode.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index e284251..95a7ba9 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -263,6 +263,7 @@ class SidebandLinkSerializer( val sending = RegInit(false.B) val done = RegInit(false.B) val waited = RegInit(true.B) + val delay = RegInit(false.B) val (sendCount, sendDone) = Counter(sending && !delay, dataBeats) val isComplete = RegInit(false.B) @@ -270,7 +271,6 @@ class SidebandLinkSerializer( io.in.ready := (waited) // wait for 32 cycles between SB messages val sendNegEdge = withClock((!clock.asBool).asClock)(RegInit(false.B)) - val delay = RegInit(false.B) sendNegEdge := sending io.out.clock := Mux(sendNegEdge, clock.asUInt, false.B) From e4fc25646331dc13ee7723cfcb40d16dab8f8c6b Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 02:14:04 -0700 Subject: [PATCH 053/106] hacky serializer cycle delay fix --- src/main/scala/sideband/sidebandNode.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 95a7ba9..d6f6beb 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -271,7 +271,7 @@ class SidebandLinkSerializer( io.in.ready := (waited) // wait for 32 cycles between SB messages val sendNegEdge = withClock((!clock.asBool).asClock)(RegInit(false.B)) - sendNegEdge := sending + sendNegEdge := sending && (sendCount =/= (dataBeats - 1).U) io.out.clock := Mux(sendNegEdge, clock.asUInt, false.B) io.out.bits := data(sb_w - 1, 0) From 7b4b87bf74921c34961cbe4c13ed59d40f869374 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 14:11:55 -0700 Subject: [PATCH 054/106] add one cycle delay after latching data --- src/main/scala/sideband/sidebandNode.scala | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index d6f6beb..d46b1d2 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -263,15 +263,15 @@ class SidebandLinkSerializer( val sending = RegInit(false.B) val done = RegInit(false.B) val waited = RegInit(true.B) - val delay = RegInit(false.B) - val (sendCount, sendDone) = Counter(sending && !delay, dataBeats) + val sendNext = RegInit(false.B) + val (sendCount, sendDone) = Counter(sending && !sendNext, dataBeats) val isComplete = RegInit(false.B) io.in.ready := (waited) // wait for 32 cycles between SB messages val sendNegEdge = withClock((!clock.asBool).asClock)(RegInit(false.B)) - sendNegEdge := sending && (sendCount =/= (dataBeats - 1).U) + sendNegEdge := sendNext || sending && (sendCount =/= (dataBeats - 1).U) io.out.clock := Mux(sendNegEdge, clock.asUInt, false.B) io.out.bits := data(sb_w - 1, 0) @@ -282,14 +282,14 @@ class SidebandLinkSerializer( when(io.in.fire) { data := io.in.bits.asUInt - delay := true.B - sending := true.B - waited := false.B - counter_next := 0.U + sendNext := true.B } - when(delay) { - delay := false.B + when(sendNext) { + sendNext := false.B + sending := true.B + counter_next := 0.U + waited := false.B } when(sending && !delay) { data := data >> sb_w.U } From a741c36fc9b76cb5a3d67f723d3723cbba97f8c9 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 14:13:03 -0700 Subject: [PATCH 055/106] add one cycle delay after latching data --- src/main/scala/sideband/sidebandNode.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index d46b1d2..e8ab371 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -264,7 +264,7 @@ class SidebandLinkSerializer( val done = RegInit(false.B) val waited = RegInit(true.B) val sendNext = RegInit(false.B) - val (sendCount, sendDone) = Counter(sending && !sendNext, dataBeats) + val (sendCount, sendDone) = Counter(sending, dataBeats) val isComplete = RegInit(false.B) @@ -292,7 +292,7 @@ class SidebandLinkSerializer( waited := false.B } - when(sending && !delay) { data := data >> sb_w.U } + when(sending) { data := data >> sb_w.U } when(sendDone) { sending := false.B From a36c4620d5ccb962c5f7ab855894b571ac4e3c4e Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 14:39:05 -0700 Subject: [PATCH 056/106] add back counter disable? --- src/main/scala/sideband/sidebandNode.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index e8ab371..78d8f95 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -283,6 +283,7 @@ class SidebandLinkSerializer( when(io.in.fire) { data := io.in.bits.asUInt sendNext := true.B + counter_en := false.B } when(sendNext) { From c06d406bc3d0704dc9963fe10215e62f1f196bd4 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 14:44:27 -0700 Subject: [PATCH 057/106] add back counter disable? --- src/main/scala/sideband/sidebandNode.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 78d8f95..c5ec4c3 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -283,7 +283,7 @@ class SidebandLinkSerializer( when(io.in.fire) { data := io.in.bits.asUInt sendNext := true.B - counter_en := false.B + done := false.B } when(sendNext) { From fd8c8efbf77d7e4da8c1a27111fc20e3d673d881 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 14:49:38 -0700 Subject: [PATCH 058/106] counter disable reset --- src/main/scala/sideband/sidebandNode.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index c5ec4c3..ec85ca0 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -283,13 +283,13 @@ class SidebandLinkSerializer( when(io.in.fire) { data := io.in.bits.asUInt sendNext := true.B - done := false.B } when(sendNext) { sendNext := false.B sending := true.B counter_next := 0.U + done := false.B waited := false.B } From 1fd615aa97c6507948200d31f31a778b6b5fa9fa Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 15:16:12 -0700 Subject: [PATCH 059/106] remove myid from phy params --- src/main/resources/vsrc/SBDeserializer.v | 2 +- src/main/resources/vsrc/SBSerializer.v | 13 +++++++++ src/main/scala/e2e/UCITop.scala | 12 ++++---- src/main/scala/logphy/LogicalPhy.scala | 3 +- src/main/scala/tilelink/UCITLFront.scala | 36 ++++++++++++------------ src/test/scala/e2e/AfeLoopbackTest.scala | 1 - 6 files changed, 39 insertions(+), 28 deletions(-) diff --git a/src/main/resources/vsrc/SBDeserializer.v b/src/main/resources/vsrc/SBDeserializer.v index 924f61a..5dc1999 100644 --- a/src/main/resources/vsrc/SBDeserializer.v +++ b/src/main/resources/vsrc/SBDeserializer.v @@ -1,6 +1,6 @@ module SBDeserializerBlackBox #( parameter WIDTH = 128, - parameter WIDTH_W = 8 + parameter WIDTH_W = $log2(WIDTH), ) ( input clk, input rst, diff --git a/src/main/resources/vsrc/SBSerializer.v b/src/main/resources/vsrc/SBSerializer.v index e69de29..e16bb26 100644 --- a/src/main/resources/vsrc/SBSerializer.v +++ b/src/main/resources/vsrc/SBSerializer.v @@ -0,0 +1,13 @@ +module SBSerializerBlackBox #( + parameter WIDTH = 128, + parameter WIDTH_W = $log2(WIDTH), +) ( + + input clk, + input rst, + input [WIDTH - 1:0] in_data, + output out_data + + ); + +endmodule \ No newline at end of file diff --git a/src/main/scala/e2e/UCITop.scala b/src/main/scala/e2e/UCITop.scala index f8058d0..eced09f 100644 --- a/src/main/scala/e2e/UCITop.scala +++ b/src/main/scala/e2e/UCITop.scala @@ -14,12 +14,12 @@ import freechips.rocketchip.util.AsyncQueueParams /** * UCITop is the main class which instantiates all the three * layers of the UCIe protocol stack - * + * */ class UCITop(val fdiParams: FdiParams, val rdiParams: RdiParams, - val sbParams: SidebandParams, val myId: BigInt, + val sbParams: SidebandParams, val linkTrainingParams: LinkTrainingParams, - val afeParams: AfeParams, + val afeParams: AfeParams, val laneAsyncQueueParams: AsyncQueueParams) extends Module { val io = IO(new Bundle{ // IOs for connecting to the protocol layer @@ -32,7 +32,7 @@ class UCITop(val fdiParams: FdiParams, val rdiParams: RdiParams, val TLplStateStatus = Output(PhyState()) val TLlpData_valid = Input(Bool()) - val TLlpData_bits = Input(Bits((8 * fdiParams.width).W)) + val TLlpData_bits = Input(Bits((8 * fdiParams.width).W)) val TLlpData_irdy = Input(Bool()) val TLlpData_ready = Output(Bool()) val TLplData_bits = Output(Bits((8 * fdiParams.width).W)) @@ -50,7 +50,7 @@ class UCITop(val fdiParams: FdiParams, val rdiParams: RdiParams, // Instantiate the D2D adapter val d2dadapter = Module(new D2DAdapter(fdiParams, rdiParams, sbParams)) // Instantiate the logPhy - val logPhy = Module(new LogicalPhy(myId, linkTrainingParams, afeParams, rdiParams, fdiParams, sbParams, laneAsyncQueueParams)) + val logPhy = Module(new LogicalPhy(linkTrainingParams, afeParams, rdiParams, fdiParams, sbParams, laneAsyncQueueParams)) // Connect the FDI interface of Protocol layer to D2D adapter protocol.io.fdi <> d2dadapter.io.fdi @@ -70,7 +70,7 @@ class UCITop(val fdiParams: FdiParams, val rdiParams: RdiParams, io.fdi_plConfigCredit <> protocol.io.fdi.plConfigCredit io.fdi_lpStallAck <> protocol.io.fdi.lpStallAck io.TLplStateStatus <> protocol.io.TLplStateStatus - + protocol.io.TLlpData_valid := io.TLlpData_valid protocol.io.TLlpData_bits := io.TLlpData_bits protocol.io.TLlpData_irdy := io.TLlpData_irdy diff --git a/src/main/scala/logphy/LogicalPhy.scala b/src/main/scala/logphy/LogicalPhy.scala index 75f3409..2ef9bd8 100644 --- a/src/main/scala/logphy/LogicalPhy.scala +++ b/src/main/scala/logphy/LogicalPhy.scala @@ -7,7 +7,6 @@ import chisel3._ import freechips.rocketchip.util.AsyncQueueParams class LogicalPhy( - myId: BigInt, linkTrainingParams: LinkTrainingParams, afeParams: AfeParams, rdiParams: RdiParams, @@ -80,7 +79,7 @@ class LogicalPhy( io.rdi.plData <> rdiDataMapper.io.rdi.plData private val sidebandChannel = - Module(new PHYSidebandChannel(myId, sbParams, fdiParams)) + Module(new PHYSidebandChannel(sbParams = sbParams, fdiParams = fdiParams)) assert( afeParams.sbSerializerRatio == 1, "connecting sideband module directly to training module, sb serializer ratio must be 1!", diff --git a/src/main/scala/tilelink/UCITLFront.scala b/src/main/scala/tilelink/UCITLFront.scala index bb0afac..dd884bd 100644 --- a/src/main/scala/tilelink/UCITLFront.scala +++ b/src/main/scala/tilelink/UCITLFront.scala @@ -19,15 +19,15 @@ import logphy.{LinkTrainingParams} // TODO: Sideband messaging /** Main class to generate manager, client and register nodes on the tilelink diplomacy. - * These needs to get connected to the chipyard system. The class converts tilelink - * packets to UCIe Raw 64B flit. It also instantiates the protocol layer which acts as + * These needs to get connected to the chipyard system. The class converts tilelink + * packets to UCIe Raw 64B flit. It also instantiates the protocol layer which acts as * an agnostic interface to generate FDI signalling. */ class UCITLFront(val tlParams: TileLinkParams, val protoParams: ProtocolLayerParams, val fdiParams: FdiParams, val rdiParams: RdiParams, - val sbParams: SidebandParams, val myId: BigInt, + val sbParams: SidebandParams, val linkTrainingParams: LinkTrainingParams, - val afeParams: AfeParams, + val afeParams: AfeParams, val laneAsyncQueueParams: AsyncQueueParams) (implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) { @@ -37,7 +37,7 @@ class UCITLFront(val tlParams: TileLinkParams, val protoParams: ProtocolLayerPar // MMIO registers controlled by the sideband module val regNode = LazyModule(new UCIConfigRF(beatBytes = tlParams.CONFIG_BEAT_BYTES, address = tlParams.CONFIG_ADDRESS)) - + // Manager node to send and acquire traffic to partner die val managerNode: TLManagerNode = TLManagerNode(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( @@ -79,7 +79,7 @@ class UCITLFrontImp extends Impl { // Instantiate the agnostic protocol layer //val protocol = Module(new ProtocolLayer(fdiParams)) val ucietop = Module(new UCITop(fdiParams, rdiParams, - sbParams, myId, + sbParams, linkTrainingParams, afeParams, laneAsyncQueueParams)) //io.fdi <> ucietop.io.fdi @@ -106,12 +106,12 @@ class UCITLFrontImp extends Impl { ucietop.io.fdi_plConfig.valid := protocol_sb_node.io.outer.tx.valid protocol_sb_node.io.outer.tx.credit := ucietop.io.fdi_plConfigCredit - protocol_sb_node.io.inner.layer_to_node.bits := Cat(regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_high, + protocol_sb_node.io.inner.layer_to_node.bits := Cat(regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_high, regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_low, regNode.module.io.sb_csrs.sidebank_mailbox_sw_to_node_index_high, regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_index_low) protocol_sb_node.io.inner.layer_to_node.valid := regNode.module.io.sb_csrs.sideband_mailbox_sw_valid - + regNode.module.io.sb_csrs.sideband_mailbox_index_low := protocol_sb_node.io.inner.node_to_layer.bits(31, 0) regNode.module.io.sb_csrs.sideband_mailbox_index_high := protocol_sb_node.io.inner.node_to_layer.bits(63, 32) regNode.module.io.sb_csrs.sideband_mailbox_data_low := protocol_sb_node.io.inner.node_to_layer.bits(95, 64) @@ -123,8 +123,8 @@ class UCITLFrontImp extends Impl { dataBits = tlParams.dataWidth, sourceBits = tlParams.sourceIDWidth, sinkBits = tlParams.sinkIDWidth, - sizeBits = tlParams.sizeWidth, - echoFields = Nil, + sizeBits = tlParams.sizeWidth, + echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) @@ -170,14 +170,14 @@ class UCITLFrontImp extends Impl { txDTLPayload := 0.U.asTypeOf(new TLBundleAUnionD(tlParams)) /* - manager_tl.a.ready = (inward.io.enq.ready & ~ucietop.io.fdi_lpStallAck & + manager_tl.a.ready = (inward.io.enq.ready & ~ucietop.io.fdi_lpStallAck & (ucietop.io.TLplStateStatus === PhyState.active)) inward.io.enq.valid := manager_tl.a.fire */ // A request to partner die logic // enqueue on the A channel queue - manager_tl.a.ready := (inwardA.io.enq.ready & ~ucietop.io.fdi_lpStallAck & + manager_tl.a.ready := (inwardA.io.enq.ready & ~ucietop.io.fdi_lpStallAck & (ucietop.io.TLplStateStatus === PhyState.active)) inwardA.io.enq.valid := manager_tl.a.fire inwardA.io.enq.bits <> manager_tl.a.bits @@ -190,7 +190,7 @@ class UCITLFrontImp extends Impl { creditedMsgA.io.credit.bits := uciRxPayload.cmd.tlACredit // D response to partner die's A request logic - client_tl.d.ready := (inwardD.io.enq.ready & ~ucietop.io.fdi_lpStallAck & + client_tl.d.ready := (inwardD.io.enq.ready & ~ucietop.io.fdi_lpStallAck & (ucietop.io.TLplStateStatus === PhyState.active)) inwardD.io.enq.valid := client_tl.d.fire inwardD.io.enq.bits <> client_tl.d.bits @@ -246,7 +246,7 @@ class UCITLFrontImp extends Impl { // ============ Below code should run on the UCIe clock? ============== val checksum_reg = RegInit(0.U(64.W)) checksum_reg := hammingEncoder.io.checksum - + val tx_pipe = Module(new Pipe(new UCIRawPayloadFormat(tlParams, protoParams), 1)) tx_pipe.io.enq.bits := uciTxPayload tx_pipe.io.enq.valid := txArbiter.io.out.fire @@ -268,7 +268,7 @@ class UCITLFrontImp extends Impl { val txACredit = WireDefault(0.U(protoParams.creditWidth.W)) val txDCredit = WireDefault(0.U(protoParams.creditWidth.W)) - + when(outwardA.io.credit.valid){ txACredit := outwardA.io.credit.bits }.elsewhen(outwardD.io.credit.valid){ @@ -284,7 +284,7 @@ class UCITLFrontImp extends Impl { uciTxPayload.cmd.tlACredit := txACredit uciTxPayload.cmd.tlBCredit := 0.U //& outwardB.io.credit.valid & creditB uciTxPayload.cmd.tlCCredit := 0.U //& outwardC.io.credit.valid & creditC - uciTxPayload.cmd.tlDCredit := txDCredit + uciTxPayload.cmd.tlDCredit := txDCredit uciTxPayload.cmd.tlECredit := 0.U //& outwardE.io.credit.valid & creditE uciTxPayload.cmd.reservedCmd := 0.U // header 1 @@ -335,7 +335,7 @@ class UCITLFrontImp extends Impl { uciRxPayload.ecc := ucietop.io.TLplData_bits(63,0) hammingDecoder.io.data := ucietop.io.TLplData_bits(511,64) hammingDecoder.io.checksum := ucietop.io.TLplData_bits(63,0) - + // map the uciRxPayload to the rxTLPayload rxTLPayload.address := uciRxPayload.header1.address rxTLPayload.opcode := uciRxPayload.header2.opcode @@ -385,6 +385,6 @@ class UCITLFrontImp extends Impl { // soft resets: can be reset or flush and reset, in flush and reset, the packets are // sent out before triggering reset - ucietop.io.soft_reset := (regNode.module.io.d2d_csrs.d2d_state_can_reset | + ucietop.io.soft_reset := (regNode.module.io.d2d_csrs.d2d_state_can_reset | regNode.module.io.d2d_csrs.d2d_flush_and_reset) }}}} \ No newline at end of file diff --git a/src/test/scala/e2e/AfeLoopbackTest.scala b/src/test/scala/e2e/AfeLoopbackTest.scala index c45529c..871c1f7 100644 --- a/src/test/scala/e2e/AfeLoopbackTest.scala +++ b/src/test/scala/e2e/AfeLoopbackTest.scala @@ -51,7 +51,6 @@ class AfeLoopbackTester(implicit p: Parameters) extends LazyModule { fdiParams = fdiParams, rdiParams = rdiParams, sbParams = sbParams, - myId = myId, linkTrainingParams = linkTrainingParams, afeParams = afeParams, laneAsyncQueueParams = laneAsyncQueueParams, From cf2fc376e002d69fbde7efa8c451acfaee96da95 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 15:18:22 -0700 Subject: [PATCH 060/106] remove myid from phy params --- src/main/scala/tilelink/Configs.scala | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/main/scala/tilelink/Configs.scala b/src/main/scala/tilelink/Configs.scala index 675cb2e..3594e41 100644 --- a/src/main/scala/tilelink/Configs.scala +++ b/src/main/scala/tilelink/Configs.scala @@ -21,7 +21,6 @@ case class UCITLParams ( val fdiParams: FdiParams, val rdiParams: RdiParams, val sbParams: SidebandParams, - val myId: BigInt, val linkTrainingParams: LinkTrainingParams, val afeParams: AfeParams, val laneAsyncQueueParams: AsyncQueueParams @@ -38,7 +37,6 @@ trait CanHaveTLUCIAdapter { this: BaseSubsystem => fdiParams = params.fdiParams, rdiParams = params.rdiParams, sbParams = params.sbParams, - myId = params.myId, linkTrainingParams = params.linkTrainingParams, afeParams = params.afeParams, laneAsyncQueueParams = params.laneAsyncQueueParams From 8cc8bb5d6eb20a3bfdb1bb8017a9598c25e56d74 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 15:21:32 -0700 Subject: [PATCH 061/106] make clog2 --- src/main/resources/vsrc/SBDeserializer.v | 2 +- src/main/resources/vsrc/SBSerializer.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/resources/vsrc/SBDeserializer.v b/src/main/resources/vsrc/SBDeserializer.v index 5dc1999..3daa3c0 100644 --- a/src/main/resources/vsrc/SBDeserializer.v +++ b/src/main/resources/vsrc/SBDeserializer.v @@ -1,6 +1,6 @@ module SBDeserializerBlackBox #( parameter WIDTH = 128, - parameter WIDTH_W = $log2(WIDTH), + parameter WIDTH_W = $clog2(WIDTH), ) ( input clk, input rst, diff --git a/src/main/resources/vsrc/SBSerializer.v b/src/main/resources/vsrc/SBSerializer.v index e16bb26..85883d8 100644 --- a/src/main/resources/vsrc/SBSerializer.v +++ b/src/main/resources/vsrc/SBSerializer.v @@ -1,6 +1,6 @@ module SBSerializerBlackBox #( parameter WIDTH = 128, - parameter WIDTH_W = $log2(WIDTH), + parameter WIDTH_W = $clog2(WIDTH), ) ( input clk, From 7ea7829b9c2263e74849f793eb8c054881934ecc Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 15:24:23 -0700 Subject: [PATCH 062/106] make clog2 --- src/main/resources/vsrc/SBDeserializer.v | 2 +- src/main/resources/vsrc/SBSerializer.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/resources/vsrc/SBDeserializer.v b/src/main/resources/vsrc/SBDeserializer.v index 3daa3c0..31b3dc7 100644 --- a/src/main/resources/vsrc/SBDeserializer.v +++ b/src/main/resources/vsrc/SBDeserializer.v @@ -1,6 +1,6 @@ module SBDeserializerBlackBox #( parameter WIDTH = 128, - parameter WIDTH_W = $clog2(WIDTH), + parameter WIDTH_W = $clog2(WIDTH) ) ( input clk, input rst, diff --git a/src/main/resources/vsrc/SBSerializer.v b/src/main/resources/vsrc/SBSerializer.v index 85883d8..b1e8322 100644 --- a/src/main/resources/vsrc/SBSerializer.v +++ b/src/main/resources/vsrc/SBSerializer.v @@ -1,6 +1,6 @@ module SBSerializerBlackBox #( parameter WIDTH = 128, - parameter WIDTH_W = $clog2(WIDTH), + parameter WIDTH_W = $clog2(WIDTH) ) ( input clk, From 4418d62b52116008b2428e560da4e7ec27c0885b Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 15:41:49 -0700 Subject: [PATCH 063/106] increase test timeout --- src/test/scala/e2e/AfeLoopbackTest.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/test/scala/e2e/AfeLoopbackTest.scala b/src/test/scala/e2e/AfeLoopbackTest.scala index 871c1f7..0bf85bc 100644 --- a/src/test/scala/e2e/AfeLoopbackTest.scala +++ b/src/test/scala/e2e/AfeLoopbackTest.scala @@ -103,7 +103,7 @@ class AfeTLTestHarness(implicit val p: Parameters) extends Module { class AfeLoopbackTest extends AnyFlatSpec with ChiselScalatestTester { behavior of "AfeLoopback" val txns = 2 - val timeout = 1000 + val timeout = 4000 implicit val p: Parameters = Parameters.empty it should "finish request and response before timeout" in { test(new AfeTLTestHarness()).withAnnotations( From cc1bfadfadb99abca3299e9be2d4b3c4b06caa75 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 15:55:35 -0700 Subject: [PATCH 064/106] update inbandpres --- src/main/scala/logphy/LogicalPhy.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/logphy/LogicalPhy.scala b/src/main/scala/logphy/LogicalPhy.scala index 2ef9bd8..4d3ea9f 100644 --- a/src/main/scala/logphy/LogicalPhy.scala +++ b/src/main/scala/logphy/LogicalPhy.scala @@ -62,7 +62,7 @@ class LogicalPhy( io.rdi.lpLinkError <> trainingModule.io.rdi.rdiBringupIO.lpLinkError /** TODO: is this correct behavior, look at spec */ - io.rdi.plInbandPres := trainingModule.io.currentState === LinkTrainingState.active + io.rdi.plInbandPres := trainingModule.io.currentState === LinkTrainingState.linkInit val rdiDataMapper = Module(new RdiDataMapper(rdiParams, afeParams)) From 1d0b9db5937c6da8b0cec336a06464018da1b38a Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 15:56:05 -0700 Subject: [PATCH 065/106] update inbandpres --- src/main/scala/logphy/LogicalPhy.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/logphy/LogicalPhy.scala b/src/main/scala/logphy/LogicalPhy.scala index 4d3ea9f..0715cc3 100644 --- a/src/main/scala/logphy/LogicalPhy.scala +++ b/src/main/scala/logphy/LogicalPhy.scala @@ -62,7 +62,7 @@ class LogicalPhy( io.rdi.lpLinkError <> trainingModule.io.rdi.rdiBringupIO.lpLinkError /** TODO: is this correct behavior, look at spec */ - io.rdi.plInbandPres := trainingModule.io.currentState === LinkTrainingState.linkInit + io.rdi.plInbandPres := trainingModule.io.currentState === LinkTrainingState.linkInit || trainingModule.io.currentState === LinkTrainingState.active val rdiDataMapper = Module(new RdiDataMapper(rdiParams, afeParams)) From 6f1e8c83fe2bf528c37b5e3e891590cc9fb18665 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Mon, 6 May 2024 16:07:03 -0700 Subject: [PATCH 066/106] fix rdi bringup fsm --- src/main/scala/logphy/RdiBringup.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/logphy/RdiBringup.scala b/src/main/scala/logphy/RdiBringup.scala index 6c98fc7..e25acda 100644 --- a/src/main/scala/logphy/RdiBringup.scala +++ b/src/main/scala/logphy/RdiBringup.scala @@ -122,7 +122,7 @@ class RdiBringup extends Module { /** TODO: how many timeout cycles here? */ io.sbTrainIO.msgReq.bits.timeoutCycles := 1_000_000.U - when(io.sbTrainIO.msgReqStatus.fire) { + when(io.sbTrainIO.msgReq.fire) { resetSubstate := ResetSubState.RESP_ACTIVE_WAIT } } From 03ec15674017504aa8189492c770a96cb43684a6 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Tue, 7 May 2024 19:11:10 -0700 Subject: [PATCH 067/106] ignore logphy test --- src/test/scala/logphy/LogPhyTest.scala | 28 +++++++++++++------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/test/scala/logphy/LogPhyTest.scala b/src/test/scala/logphy/LogPhyTest.scala index 6d82948..492935e 100644 --- a/src/test/scala/logphy/LogPhyTest.scala +++ b/src/test/scala/logphy/LogPhyTest.scala @@ -19,18 +19,18 @@ class LogPhyTest extends AnyFlatSpec with ChiselScalatestTester { * actual top-level test because Chiseltest does not support multiple clock * domains. */ - // behavior of "logical phy" - // it should "" in { - // test( - // new LogicalPhy( - // 0, - // linkTrainingParams = linkTrainingParams, - // afeParams = afeParams, - // rdiParams = rdiParams, - // fdiParams = fdiParams, - // sbParams = sbParams, - // laneAsyncQueueParams = laneAsyncQueueParams, - // ), - // ) { c => } - // } + behavior of "logical phy" + ignore should "" in { + test( + new LogicalPhy( + 0, + linkTrainingParams = linkTrainingParams, + afeParams = afeParams, + rdiParams = rdiParams, + fdiParams = fdiParams, + sbParams = sbParams, + laneAsyncQueueParams = laneAsyncQueueParams, + ), + ) { c => } + } } From 84457780adac380b501550377d74b2203d6817f9 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Tue, 7 May 2024 19:24:55 -0700 Subject: [PATCH 068/106] try no async fifo --- src/main/resources/vsrc/SBDeserializer.v | 7 ++-- src/main/scala/sideband/sidebandNode.scala | 47 ++++++---------------- 2 files changed, 17 insertions(+), 37 deletions(-) diff --git a/src/main/resources/vsrc/SBDeserializer.v b/src/main/resources/vsrc/SBDeserializer.v index 31b3dc7..d27bd52 100644 --- a/src/main/resources/vsrc/SBDeserializer.v +++ b/src/main/resources/vsrc/SBDeserializer.v @@ -5,7 +5,6 @@ module SBDeserializerBlackBox #( input clk, input rst, input in_data, - input out_data_ready, output [WIDTH - 1:0] out_data, output out_data_valid @@ -30,11 +29,13 @@ always @(negedge clk or posedge rst) begin receiving <= 1'b0; end else begin counter <= counter + 1'b1; - end - if (out_data_valid && out_data_ready) begin receiving <= 1'b1; end + // if (out_data_valid && out_data_ready) begin + // receiving <= 1'b1; + // end + data_reg[counter] <= in_data; end diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index ec85ca0..67cef44 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -325,46 +325,26 @@ class SidebandLinkDeserializer( val dataBits = msg_w val dataBeats = (dataBits - 1) / sb_w + 1 - val asyncFifo = Module( - new AsyncQueue( - UInt(msg_w.W), - ), - ) - - asyncFifo.io.deq <> io.out - asyncFifo.io.deq_clock := clock - asyncFifo.io.deq_reset := reset - asyncFifo.io.enq_clock := remote_clock - asyncFifo.io.enq_reset := reset - - // val clockMux2 = Module(new ClockMux2) - // clockMux2.io.clocksIn(0) := remote_clock - // clockMux2.io.clocksIn(1) := clock - // clockMux2.io.sel := reset.asBool + val valid_sync_1 = RegNext(sbDeserBlackBox.io.out_data_valid) + val valid_sync = RegNext(valid_sync_1) + val data_sync_1 = RegNext(sbDeserBlackBox.io.out_data) + val data_sync = RegNext(data_sync_1) + + val flag = RegInit(true.B) + when(valid_sync) { + flag := false.B + }.otherwise { + flag := true.B + } - // val inv_clock = (!remote_clock.asBool).asClock - // withClockAndReset(clock, reset.asAsyncReset) { + io.out.valid := valid_sync && flag + io.out.bits := data_sync val sbDeserBlackBox = Module(new SBDeserializerBlackBox(msg_w)) sbDeserBlackBox.io.clk := remote_clock sbDeserBlackBox.io.rst := reset.asAsyncReset - asyncFifo.io.enq.valid := sbDeserBlackBox.io.out_data_valid - asyncFifo.io.enq.bits := sbDeserBlackBox.io.out_data - sbDeserBlackBox.io.out_data_ready := asyncFifo.io.enq.ready sbDeserBlackBox.io.in_data := io.in.bits - // val data = Reg(Vec(dataBeats, UInt(sb_w.W))) - - // val (recvCount, recvDone) = Counter(true.B, dataBeats) - // val receiving = RegInit(true.B) - - // data(recvCount) := io.in.bits - // when(recvDone) { receiving := false.B } - // when(asyncFifo.io.enq.fire) { receiving := true.B } - // asyncFifo.io.enq.valid := !receiving - - // asyncFifo.io.enq.bits := data.asUInt - // } } class SBDeserializerBlackBox(val width: Int) @@ -379,7 +359,6 @@ class SBDeserializerBlackBox(val width: Int) val clk = Input(Clock()) val rst = Input(Reset()) val in_data = Input(UInt(1.W)) - val out_data_ready = Input(Bool()) val out_data = Output(UInt(width.W)) val out_data_valid = Output(Bool()) }) From d690f1657ba762510d56cb6455760e7a0cb824eb Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Tue, 7 May 2024 19:27:46 -0700 Subject: [PATCH 069/106] fix logphy test --- src/test/scala/logphy/LogPhyTest.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/src/test/scala/logphy/LogPhyTest.scala b/src/test/scala/logphy/LogPhyTest.scala index 492935e..f62eb6d 100644 --- a/src/test/scala/logphy/LogPhyTest.scala +++ b/src/test/scala/logphy/LogPhyTest.scala @@ -23,7 +23,6 @@ class LogPhyTest extends AnyFlatSpec with ChiselScalatestTester { ignore should "" in { test( new LogicalPhy( - 0, linkTrainingParams = linkTrainingParams, afeParams = afeParams, rdiParams = rdiParams, From 87f982e03a2525a625fa0c3310ffb9de1dcbe591 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Tue, 7 May 2024 19:29:10 -0700 Subject: [PATCH 070/106] compilation bug --- src/main/scala/sideband/sidebandNode.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/sideband/sidebandNode.scala b/src/main/scala/sideband/sidebandNode.scala index 67cef44..973b65b 100644 --- a/src/main/scala/sideband/sidebandNode.scala +++ b/src/main/scala/sideband/sidebandNode.scala @@ -324,6 +324,7 @@ class SidebandLinkDeserializer( val dataBits = msg_w val dataBeats = (dataBits - 1) / sb_w + 1 + val sbDeserBlackBox = Module(new SBDeserializerBlackBox(msg_w)) val valid_sync_1 = RegNext(sbDeserBlackBox.io.out_data_valid) val valid_sync = RegNext(valid_sync_1) @@ -340,7 +341,6 @@ class SidebandLinkDeserializer( io.out.valid := valid_sync && flag io.out.bits := data_sync - val sbDeserBlackBox = Module(new SBDeserializerBlackBox(msg_w)) sbDeserBlackBox.io.clk := remote_clock sbDeserBlackBox.io.rst := reset.asAsyncReset sbDeserBlackBox.io.in_data := io.in.bits From e69956d33b736942c17975884891c5abecfd97f6 Mon Sep 17 00:00:00 2001 From: Vikram Jain Date: Wed, 8 May 2024 13:27:57 -0700 Subject: [PATCH 071/106] fixed the handshake --- .../scala/d2dadapter/D2DSidebandModule.scala | 34 +++++++++---------- .../scala/d2dadapter/LinkInitSubmodule.scala | 8 +++++ src/main/scala/protocol/ProtocolLayer.scala | 6 ++-- 3 files changed, 29 insertions(+), 19 deletions(-) diff --git a/src/main/scala/d2dadapter/D2DSidebandModule.scala b/src/main/scala/d2dadapter/D2DSidebandModule.scala index 3f3ccac..55fd0cc 100644 --- a/src/main/scala/d2dadapter/D2DSidebandModule.scala +++ b/src/main/scala/d2dadapter/D2DSidebandModule.scala @@ -65,39 +65,39 @@ class D2DSidebandModule(val fdiParams: FdiParams, val sbParams: SidebandParams) sideband_switch.io.inner.layer_to_node_above.bits := 0.U(sbParams.sbNodeMsgWidth.W) sideband_switch.io.inner.layer_to_node_above.valid := false.B - sideband_switch.io.inner.node_to_layer_below.ready := false.B + sideband_switch.io.inner.node_to_layer_below.ready := true.B sideband_switch.io.inner.node_to_layer_above.ready := true.B - when(sideband_switch.io.inner.node_to_layer_above.valid && sideband_switch.io.inner.node_to_layer_above.ready){ - when(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_REQ_ACTIVE){ + when(sideband_switch.io.inner.node_to_layer_below.valid && sideband_switch.io.inner.node_to_layer_below.ready){ + when(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_REQ_ACTIVE){ io.sideband_rcv := SideBandMessage.REQ_ACTIVE - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_REQ_L1){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_REQ_L1){ io.sideband_rcv := SideBandMessage.REQ_L1 - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_REQ_L2){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_REQ_L2){ io.sideband_rcv := SideBandMessage.REQ_L2 - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_REQ_LINK_RESET){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_REQ_LINK_RESET){ io.sideband_rcv := SideBandMessage.REQ_LINKRESET - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_REQ_DISABLE){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_REQ_DISABLE){ io.sideband_rcv := SideBandMessage.REQ_DISABLED - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_RSP_ACTIVE){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_RSP_ACTIVE){ io.sideband_rcv := SideBandMessage.RSP_ACTIVE - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_RSP_PM_NAK){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_RSP_PM_NAK){ io.sideband_rcv := SideBandMessage.RSP_PMNAK - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_RSP_L1){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_RSP_L1){ io.sideband_rcv := SideBandMessage.RSP_L1 - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_RSP_L2){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_RSP_L2){ io.sideband_rcv := SideBandMessage.RSP_L2 - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_RSP_LINK_RESET){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_RSP_LINK_RESET){ io.sideband_rcv := SideBandMessage.RSP_LINKRESET - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.LINK_MGMT_ADAPTER0_RSP_DISABLE){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.LINK_MGMT_ADAPTER0_RSP_DISABLE){ io.sideband_rcv := SideBandMessage.RSP_DISABLED - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.PARITY_FEATURE_REQ){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.PARITY_FEATURE_REQ){ io.sideband_rcv := SideBandMessage.PARITY_FEATURE_REQ - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.PARITY_FEATURE_ACK){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.PARITY_FEATURE_ACK){ io.sideband_rcv := SideBandMessage.PARITY_FEATURE_ACK - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.PARITY_FEATURE_NAK){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.PARITY_FEATURE_NAK){ io.sideband_rcv := SideBandMessage.PARITY_FEATURE_NAK - }.elsewhen(sideband_switch.io.inner.node_to_layer_above.bits === SBM.ADV_CAP){ + }.elsewhen(sideband_switch.io.inner.node_to_layer_below.bits === SBM.ADV_CAP){ io.sideband_rcv := SideBandMessage.ADV_CAP }.otherwise{ io.sideband_rcv := SideBandMessage.NOP diff --git a/src/main/scala/d2dadapter/LinkInitSubmodule.scala b/src/main/scala/d2dadapter/LinkInitSubmodule.scala index c5b443a..0dee3a5 100644 --- a/src/main/scala/d2dadapter/LinkInitSubmodule.scala +++ b/src/main/scala/d2dadapter/LinkInitSubmodule.scala @@ -195,6 +195,14 @@ class LinkInitSubmodule() extends Module { linkinit_state_reg := LinkInitState.INIT_DONE } } + }.elsewhen(io.link_state === PhyState.active){ + io.active_entry := true.B + io.linkinit_fdi_pl_state_sts := PhyState.active + io.linkinit_fdi_pl_rxactive_req := true.B + io.linkinit_fdi_pl_inband_pres := true.B + io.linkinit_rdi_lp_state_req := PhyStateReq.active + io.linkinit_sb_snd := SideBandMessage.NOP + linkinit_state_reg := LinkInitState.INIT_DONE }.otherwise{ linkinit_state_reg := LinkInitState.INIT_START io.active_entry := false.B diff --git a/src/main/scala/protocol/ProtocolLayer.scala b/src/main/scala/protocol/ProtocolLayer.scala index 1fc72fa..5fd15de 100644 --- a/src/main/scala/protocol/ProtocolLayer.scala +++ b/src/main/scala/protocol/ProtocolLayer.scala @@ -67,16 +67,18 @@ class ProtocolLayer(val fdiParams: FdiParams) extends Module { // io.fdi.plStateStatus === PhyState.active) val lp_rx_active_pl_state = (io.fdi.plStateStatus === PhyState.active) - when(io.fdi.plRxActiveReq && io.TLready_to_rcv && lp_rx_active_pl_state) { + when(io.fdi.plRxActiveReq && io.TLready_to_rcv){//&& lp_rx_active_pl_state) { lp_rx_active_sts_reg := true.B } io.fdi.lpRxActiveStatus := lp_rx_active_sts_reg // Refer to section 8.2.8 for FDI bringup and state req logic val lp_state_req_reg = RegInit(PhyStateReq.nop) + //val lp_state_req_prev = RegInit(PhyState.nop) + //lp_state_req_prev := io.fdi.plStateStatus + // Removed: lp_state_req_prev === PhyState.nop & val reqActive = ((io.fdi.plStateStatus === PhyState.reset & - lp_state_req_reg === PhyStateReq.nop & io.fdi.plInbandPres) || io.fdi.plStateStatus === PhyState.linkReset) when(reqActive) { From b70fdf9948666d9f125016b4d08c37d294220cf7 Mon Sep 17 00:00:00 2001 From: Vikram Jain Date: Wed, 8 May 2024 15:33:28 -0700 Subject: [PATCH 072/106] first pass mb serdes --- src/main/scala/e2e/UCITop.scala | 41 ++++++++++++++++++- src/main/scala/tilelink/UCITLFront.scala | 8 +++- src/test/scala/e2e/AfeLoopback.scala | 52 +++++++++++++++++++----- src/test/scala/e2e/AfeLoopbackTest.scala | 6 ++- 4 files changed, 90 insertions(+), 17 deletions(-) diff --git a/src/main/scala/e2e/UCITop.scala b/src/main/scala/e2e/UCITop.scala index eced09f..ed3a3e0 100644 --- a/src/main/scala/e2e/UCITop.scala +++ b/src/main/scala/e2e/UCITop.scala @@ -4,6 +4,7 @@ package e2e import chisel3._ import chisel3.util._ +import afe._ import interfaces._ import sideband._ import protocol._ @@ -41,7 +42,9 @@ class UCITop(val fdiParams: FdiParams, val rdiParams: RdiParams, val fault = Input(Bool()) val soft_reset = Input(Bool()) // IOs for connecting to the AFE - val mbAfe = new MainbandAfeIo(afeParams) + //val mbAfe = new MainbandAfeIo(afeParams) + val mbAfe_tx = Output(new MainbandIo(afeParams.mbLanes)) + val mbAfe_rx = Input (new MainbandIo(afeParams.mbLanes)) val sbAfe = new SidebandAfeIo(afeParams) }) @@ -52,6 +55,8 @@ class UCITop(val fdiParams: FdiParams, val rdiParams: RdiParams, // Instantiate the logPhy val logPhy = Module(new LogicalPhy(linkTrainingParams, afeParams, rdiParams, fdiParams, sbParams, laneAsyncQueueParams)) + val dafe = Module(new MbAfe(afeParams, AsyncQueueParams())) + // Connect the FDI interface of Protocol layer to D2D adapter protocol.io.fdi <> d2dadapter.io.fdi @@ -59,9 +64,41 @@ class UCITop(val fdiParams: FdiParams, val rdiParams: RdiParams, d2dadapter.io.rdi <> logPhy.io.rdi // Connect the AFE interface from logPhy to the top - io.mbAfe <> logPhy.io.mbAfe + //io.mbAfe <> logPhy.io.mbAfe + // logphy.io.mbAfe. + logPhy.io.mbAfe.txData <> dafe.io.mbAfeIo.rxData + logPhy.io.mbAfe.rxData <> dafe.io.mbAfeIo.txData + // dafe.io. + io.mbAfe_tx <> dafe.io.stdIo.tx.mainband + io.mbAfe_rx <> dafe.io.stdIo.rx.mainband + // io.mbAfe <> dafe.io.stdIo.tx.mainband io.sbAfe <> logPhy.io.sbAfe + dafe.io.clkp := clock + dafe.io.clkn := clock + dafe.io.clk_800 := clock + dafe.io.sbAfeIo.fifoParams.clk := clock + dafe.io.clk_800 := clock + dafe.io.sbAfeIo.rxData := 0.U + dafe.io.mbAfeIo.fifoParams.clk := clock + // dafe.io.stdIo.rx.mainband.valid := false.B + // dafe.io.stdIo.rx.mainband.clkn := clock + // dafe.io.stdIo.rx.mainband.data := 0.U + dafe.io.clkp := clock + dafe.io.stdIo.rx.sideband.clk := clock + dafe.io.mbAfeIo.fifoParams.reset := false.B + logPhy.io.mbAfe.fifoParams.clk := clock + dafe.io.sbAfeIo.rxClock := false.B + // dafe.io.stdIo.rx.mainband.clkp := clock + // dafe.io.stdIo.rx.mainband.track := false.B + dafe.io.clkn := clock + logPhy.io.mbAfe.pllLock := false.B + dafe.io.mbAfeIo.pllLock := false.B + dafe.io.stdIo.rx.sideband.data := 0.U + dafe.io.sbAfeIo.pllLock := false.B + dafe.io.sbAfeIo.fifoParams.reset := false.B + logPhy.io.mbAfe.fifoParams.reset := false.B + // Connect the protocol IOs to the top for connections to the tilelink interface //io.fdi <> protocol.io.fdi io.fdi_lpConfig <> protocol.io.fdi.lpConfig diff --git a/src/main/scala/tilelink/UCITLFront.scala b/src/main/scala/tilelink/UCITLFront.scala index dd884bd..8800d54 100644 --- a/src/main/scala/tilelink/UCITLFront.scala +++ b/src/main/scala/tilelink/UCITLFront.scala @@ -67,7 +67,9 @@ class UCITLFrontImp extends Impl { // FDI interface for testing purposes only //val fdi = new Fdi(fdiParams) // IOs for connecting to the AFE - val mbAfe = new MainbandAfeIo(afeParams) + //val mbAfe = new MainbandAfeIo(afeParams) + val mbAfe_tx = Output(new MainbandIo(afeParams.mbLanes)) + val mbAfe_rx = Input (new MainbandIo(afeParams.mbLanes)) val sbAfe = new SidebandAfeIo(afeParams) }) withClockAndReset(clock, reset) { @@ -84,7 +86,9 @@ class UCITLFrontImp extends Impl { afeParams, laneAsyncQueueParams)) //io.fdi <> ucietop.io.fdi ucietop.io.fault := fault - io.mbAfe <> ucietop.io.mbAfe + //io.mbAfe <> ucietop.io.mbAfe + io.mbAfe_tx <> ucietop.io.mbAfe_tx + io.mbAfe_rx <> ucietop.io.mbAfe_rx io.sbAfe <> ucietop.io.sbAfe // Hamming encode and decode diff --git a/src/test/scala/e2e/AfeLoopback.scala b/src/test/scala/e2e/AfeLoopback.scala index e6071da..ef01222 100644 --- a/src/test/scala/e2e/AfeLoopback.scala +++ b/src/test/scala/e2e/AfeLoopback.scala @@ -20,25 +20,55 @@ import protocol._ class AfeLoopback(val afeParams: AfeParams) extends Module { val io = IO(new Bundle { // val finished = Output(Bool()) - val mbAfe = Flipped(new MainbandAfeIo(afeParams)) + //val mbAfe = Flipped(new MainbandAfeIo(afeParams)) + val mbAfe_tx = Input(new MainbandIo(afeParams.mbLanes)) + val mbAfe_rx = Output (new MainbandIo(afeParams.mbLanes)) val sbAfe = Flipped(new SidebandAfeIo(afeParams)) }) val latency = 2 - val delayerMb = Module(new Pipe(chiselTypeOf(io.mbAfe.txData.bits), latency)) + //val delayerMb = Module(new Pipe(chiselTypeOf(io.mbAfe.txData.bits), latency)) + val delayerMbTx = Module(new Pipe(chiselTypeOf(io.mbAfe_tx.data), latency)) val delayerSb = Module(new Pipe(chiselTypeOf(io.sbAfe.txData), latency)) val delayerSb_clock = Module( new Pipe(chiselTypeOf(io.sbAfe.txClock), latency), ) - - delayerMb.io.enq.valid := io.mbAfe.txData.valid - delayerMb.io.enq.bits := io.mbAfe.txData.bits - io.mbAfe.rxData.bits := delayerMb.io.deq.bits - io.mbAfe.rxData.valid := delayerMb.io.deq.valid - io.mbAfe.txData.ready := true.B - io.mbAfe.fifoParams.clk := clock - io.mbAfe.fifoParams.reset := reset - io.mbAfe.pllLock := true.B + val delayerMbTx_clockn = Module( + new Pipe(chiselTypeOf(io.mbAfe_tx.clkn.asBool), latency), + ) + val delayerMbTx_clockp = Module( + new Pipe(chiselTypeOf(io.mbAfe_tx.clkp.asBool), latency), + ) + + delayerMbTx.io.enq.valid := io.mbAfe_tx.valid + delayerMbTx.io.enq.bits := io.mbAfe_tx.data + io.mbAfe_rx.data := delayerMbTx.io.deq.bits + io.mbAfe_rx.valid := delayerMbTx.io.deq.valid + delayerMbTx_clockn.io.enq.valid := true.B + delayerMbTx_clockn.io.enq.bits := io.mbAfe_tx.clkn.asBool + delayerMbTx_clockp.io.enq.valid := true.B + delayerMbTx_clockp.io.enq.bits := io.mbAfe_tx.clkp.asBool + // val delayNegEdgeMbClkN = withClock((!clock.asBool).asClock)(RegInit(false.B)) + // delayNegEdgeMbClkN := delayerMbTx_clockn.io.deq.bits && delayerMbTx_clockn.io.deq.valid + // io.mbAfe_rx.clkn := Mux( + // delayNegEdgeMbClkN.asBool, + // clock.asBool, + // false.asBool, + // ) + io.mbAfe_rx.clkn := io.mbAfe_tx.clkn + // val delayNegEdgeMbClkP = withClock((!clock.asBool).asClock)(RegInit(false.B)) + // delayNegEdgeMbClkP := delayerMbTx_clockp.io.deq.bits && delayerMbTx_clockp.io.deq.valid + // io.mbAfe_rx.clkp := Mux( + // delayNegEdgeMbClkP.asBool, + // clock.asBool, + // false.asBool, + // ) + io.mbAfe_rx.clkp := io.mbAfe_tx.clkp + //io.mbAfe.txData.ready := true.B + //io.mbAfe.fifoParams.clk := clock + //io.mbAfe.fifoParams.reset := reset + //io.mbAfe.pllLock := true.B + io.mbAfe_rx.track := false.B delayerSb.io.enq.valid := true.B // io.sbAfe.txData.valid delayerSb.io.enq.bits := io.sbAfe.txData diff --git a/src/test/scala/e2e/AfeLoopbackTest.scala b/src/test/scala/e2e/AfeLoopbackTest.scala index 0bf85bc..3abfc9d 100644 --- a/src/test/scala/e2e/AfeLoopbackTest.scala +++ b/src/test/scala/e2e/AfeLoopbackTest.scala @@ -37,7 +37,7 @@ class AfeLoopbackTester(implicit p: Parameters) extends LazyModule { val afeParams = AfeParams() val laneAsyncQueueParams = AsyncQueueParams() val delay = 0.0 - val txns = 10 + val txns = 100 // Create clock source val clockSourceNode = ClockSourceNode(Seq(ClockSourceParameters())) @@ -82,7 +82,9 @@ class AfeLoopbackTester(implicit p: Parameters) extends LazyModule { val AfeLoopback = Module(new AfeLoopback(afeParams)) io.uci_clock <> clockSourceNode.out(0)._1 // inputs to tlUcieDie1 - tlUcieDie1.module.io.mbAfe <> AfeLoopback.io.mbAfe + //tlUcieDie1.module.io.mbAfe <> AfeLoopback.io.mbAfe + tlUcieDie1.module.io.mbAfe_tx <> AfeLoopback.io.mbAfe_tx + tlUcieDie1.module.io.mbAfe_rx <> AfeLoopback.io.mbAfe_rx tlUcieDie1.module.io.sbAfe <> AfeLoopback.io.sbAfe } } From ae99f9ebf4b66451f6ddb94d5e935ba5856dd2a8 Mon Sep 17 00:00:00 2001 From: Vikram Jain Date: Wed, 8 May 2024 18:12:25 -0700 Subject: [PATCH 073/106] adding mbafe --- .../resources/vsrc/AsyncFifoCustomCore.sv | 200 ++++++++ src/main/scala/mbafe/AsyncFifoCustom.scala | 51 ++ src/main/scala/mbafe/MbAfe.scala | 459 ++++++++++++++++++ 3 files changed, 710 insertions(+) create mode 100644 src/main/resources/vsrc/AsyncFifoCustomCore.sv create mode 100644 src/main/scala/mbafe/AsyncFifoCustom.scala create mode 100644 src/main/scala/mbafe/MbAfe.scala diff --git a/src/main/resources/vsrc/AsyncFifoCustomCore.sv b/src/main/resources/vsrc/AsyncFifoCustomCore.sv new file mode 100644 index 0000000..cfca7e7 --- /dev/null +++ b/src/main/resources/vsrc/AsyncFifoCustomCore.sv @@ -0,0 +1,200 @@ +// Code your design here +module AsyncFifoCustomCore #( + parameter DEPTH = 16, + parameter WIDTH = 8 +)( + input rst, + + input clk_w, + input valid_w, + output ready_w, + input [WIDTH-1:0] data_w, + + input clk_r, + output valid_r, + input ready_r, + output [WIDTH-1:0] data_r +); + localparam PTR_WIDTH = $clog2(DEPTH); + + + wire [PTR_WIDTH:0] b_wptr; + wire [PTR_WIDTH:0] b_rptr; + wire [PTR_WIDTH:0] g_wptr; + wire [PTR_WIDTH:0] g_rptr; + wire [PTR_WIDTH:0] g_wptr_sync; + wire [PTR_WIDTH:0] g_rptr_sync; + wire full, empty; + + Sync2Flop #(PTR_WIDTH + 1) wptrSync (.clk(clk_w), .rst(rst), .in(g_wptr), .out(g_wptr_sync)); + Sync2Flop #(PTR_WIDTH + 1) rptrSync (.clk(clk_r), .rst(rst), .in(g_rptr), .out(g_rptr_sync)); + WptrHandler #(PTR_WIDTH) wptrHandler (.clk(clk_w), .rst(rst), .en(valid_w), .g_rptr_sync(g_rptr_sync), + .g_wptr(g_wptr), .b_wptr(b_wptr), .full(full)); + RptrHandler #(PTR_WIDTH) rptrHandler (.clk(clk_r), .rst(rst), .en(ready_r), .g_wptr_sync(g_wptr_sync), + .g_rptr(g_rptr), .b_rptr(b_rptr), .empty(empty)); + Fifo #(PTR_WIDTH, WIDTH) fifo (.rst(rst), + .clk_w(clk_w), .en_w(valid_w), .data_w(data_w), .b_wptr(b_wptr), .full(full), + .clk_r(clk_r), .en_r(ready_r), .data_r(data_r), .b_rptr(b_rptr), .empty(empty)); + assign valid_r = ~empty; + assign ready_w = ~full; + +endmodule + +module Sync2Flop #( + parameter PTR_WIDTH = 8 +)( + input clk, + input rst, + input [PTR_WIDTH-1:0] in, + output reg [PTR_WIDTH-1:0] out +); + reg [PTR_WIDTH-1:0] mid; + always_ff @(posedge clk, negedge rst) begin + if (~rst) begin + out <= '0; + mid <= '0; + end else begin + out <= mid; + mid <= in; + end + end +endmodule + +module WptrHandler #( + parameter PTR_WIDTH = 8 +)( + input clk, + input rst, + input en, + input [PTR_WIDTH:0] g_rptr_sync, + output reg [PTR_WIDTH:0] g_wptr, b_wptr, + output reg full +); + wire [PTR_WIDTH:0] g_wptr_next; + wire [PTR_WIDTH:0] b_wptr_next; + wire full_next; + + assign b_wptr_next = b_wptr + (en & ~full); + assign g_wptr_next = b_wptr_next ^ (b_wptr_next >> 1); + assign full_next = g_wptr_next == {~g_rptr_sync[PTR_WIDTH:PTR_WIDTH-1], g_rptr_sync[PTR_WIDTH-2:0]}; + + always_ff @(posedge clk, negedge rst) begin + if(~rst) begin + g_wptr <= '0; + b_wptr <= '0; + full <= '0; + // g_wptr <= g_wptr_next; + // b_wptr <= b_wptr_next; + // full <= full_next; + end else begin + g_wptr <= g_wptr_next; + b_wptr <= b_wptr_next; + full <= full_next; + end + end + +endmodule + +module RptrHandler #( + parameter PTR_WIDTH = 8 +)( + input clk, + input rst, + input en, + input [PTR_WIDTH:0] g_wptr_sync, + output reg [PTR_WIDTH:0] g_rptr, b_rptr, + output reg empty +); + wire [PTR_WIDTH:0] g_rptr_next; + wire [PTR_WIDTH:0] b_rptr_next; + wire empty_next; + + assign b_rptr_next = b_rptr + (en & ~empty); + assign g_rptr_next = b_rptr_next ^ (b_rptr_next >> 1); + assign empty_next = g_rptr_next == g_wptr_sync; + + always_ff @(posedge clk, negedge rst) begin + if(~rst) begin + g_rptr <= '0; + b_rptr <= '0; + empty <= '1; + end else begin + g_rptr <= g_rptr_next; + b_rptr <= b_rptr_next; + empty <= empty_next; + end + end + +endmodule + +module Fifo #( + parameter PTR_WIDTH = 8, + parameter WIDTH = 8 +)( + input rst, + // Write + input [WIDTH-1:0] data_w, + input clk_w, + input en_w, + input [PTR_WIDTH:0] b_wptr, + input full, + // Read + output reg [WIDTH-1:0] data_r, + input clk_r, + input en_r, + input [PTR_WIDTH:0] b_rptr, + input empty +); + localparam ENTRIES = 2**PTR_WIDTH; + integer i; + reg [WIDTH-1:0] fifoBank [0:ENTRIES-1]; + always_ff @(posedge clk_w, negedge rst) begin + if(~rst) begin + for(i = 0; i < ENTRIES; i++) begin + fifoBank[i] <= 'b0; + end + end else if (en_w & ~full) begin + fifoBank[b_wptr[PTR_WIDTH-1:0]] <= data_w; + end else begin + for(i = 0; i < ENTRIES; i++) begin + fifoBank[i] <= fifoBank[i]; + end + end + end + + // always_ff @(posedge clk_r) begin + // if(en_r & ~empty) begin + // data_r <= fifoBank[b_rptr[PTR_WIDTH-1:0]]; + // end + // end + + assign data_r = fifoBank[b_rptr[PTR_WIDTH-1:0]]; +endmodule + +module BinaryToGray #( + parameter WIDTH = 8 +)( + input [WIDTH-1:0] in, + output [WIDTH-1:0] out +); + +genvar i; +assign out[WIDTH-1] = in[WIDTH - 1]; +for(i = WIDTH - 2; i >= 0; i--) begin + assign out[i] = in[i] ^ in[i + 1]; +end + +endmodule + +module GrayToBinary #( + parameter WIDTH = 8 +)( + input [WIDTH-1:0] in, + output [WIDTH-1:0] out +); +genvar i; +assign out[WIDTH-1] = in[WIDTH - 1]; +for(i = WIDTH - 2; i >= 0; i--) begin + assign out[i] = ^(in >> i); +end +endmodule \ No newline at end of file diff --git a/src/main/scala/mbafe/AsyncFifoCustom.scala b/src/main/scala/mbafe/AsyncFifoCustom.scala new file mode 100644 index 0000000..7b156d4 --- /dev/null +++ b/src/main/scala/mbafe/AsyncFifoCustom.scala @@ -0,0 +1,51 @@ +package edu.berkeley.cs.ucie.digital +package afe + +import chisel3._ +import chisel3.util._ + + + +class AsyncFifoCustom(depth: Int, width: Int) extends Module { + val io = IO(new Bundle { + val deq_clock = Input(Clock()) + val deq = Flipped(Flipped(Decoupled(UInt(width.W)))) + val deq_reset = Input(Bool()) + val enq_reset = Input(Bool()) + val enq_clock = Input(Clock()) + val enq = Flipped(Decoupled(UInt(width.W))) + }) + val fifo_inst = Module (new AsyncFifoCustomCore(depth, width)) + + fifo_inst.io.rst := ~io.enq_reset + fifo_inst.io.clk_w := io.enq_clock + fifo_inst.io.valid_w := io.enq.valid + io.enq.ready := fifo_inst.io.ready_w + fifo_inst.io.data_w := io.enq.bits + + // fifo_inst.io.clk_r := io.deq_clock + // fifo_inst.io.ready_r := io.deq.ready + // io.deq.bits := fifo_inst.io.data_r + // io.deq.valid := fifo_inst.io.valid_r + io.deq.valid := fifo_inst.io.valid_r + fifo_inst.io.clk_r := io.deq_clock + fifo_inst.io.ready_r := io.deq.ready + io.deq.bits := fifo_inst.io.data_r +} + +class AsyncFifoCustomCore (depth: Int, width: Int) extends BlackBox( + Map("DEPTH" -> depth, "WIDTH" -> width) +) with HasBlackBoxResource { + val io = IO(new Bundle { + val rst = Input(Bool()) + val clk_w = Input(Clock()) + val valid_w = Input(Bool()) + val ready_w = Output(Bool()) + val data_w = Input(Bits(width.W)) + val clk_r = Input(Clock()) + val valid_r = Output(Bool()) + val ready_r = Input(Bool()) + val data_r = Output(Bits(width.W)) + }) + addResource("/vsrc/AsyncFifoCustomCore.sv") +} \ No newline at end of file diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala new file mode 100644 index 0000000..279b9cd --- /dev/null +++ b/src/main/scala/mbafe/MbAfe.scala @@ -0,0 +1,459 @@ +package edu.berkeley.cs.ucie.digital +package afe + +import chisel3._ +import chisel3.util._ +import chisel3.stage.ChiselStage +import interfaces._ +import chisel3.experimental.DataMirror +import freechips.rocketchip.util.{AsyncQueue, AsyncQueueParams} + +// This module receives data from adapter and sends to analog +class TxMainband(afeParams: AfeParams, queueParams: AsyncQueueParams, BYTE: Int = 8) extends Module { + val io = IO(new Bundle { + // should use rx of mbafeIo + // val mbAfeIo = new MainbandAfeIo(AfeParams()) + val rxMbAfe = Flipped(Decoupled(Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W)))) + val txMbIo = Output(new MainbandIo()) + + val clkp = Input(Clock()) + val clkn = Input(Clock()) + val track = Input(Bool()) + // val output_clkp = Output(Clock()) + // Dummy signals for testing + }) + val lanes = afeParams.mbLanes + val width = afeParams.mbSerializerRatio + + // io.mbAfeIo.txData.bits := Seq.fill(lanes)(0.U) + // io.mbAfeIo.txData.valid := false.B + + // receive data + // val rxMbAfeData = io.mbAfeIo.rxData + val rxMbAfeData = io.rxMbAfe + + // Default fifo has problem: when deq starts, data is XXXX for at least 10 cycles, not sure why + // Use custom async fifo, this one works + // val txMbFifos = Seq.fill(lanes)(Module (new AsyncFifoStefan(depth, width))) + // val txMbFifos = Seq.fill(lanes)(Module ( + // new AsyncQueue( + // Bits(afeParams.mbSerializerRatio.W), + // queueParams) + // ) + // ) + val txMbFifos = Seq.fill(lanes)(Module ( + new AsyncFifoCustom(32, afeParams.mbSerializerRatio) + )) + + withClock(io.clkp) { + val outValid = Wire(Bool()) + val outTrack = Wire(Bool()) + val txMbShiftRegs = Seq.fill(lanes)(RegInit(0.U(width.W))) + val txMbUICounter = RegInit(0.U(log2Ceil(width).W)) + // val txMbUICounter_next = RegNext(txMbUICounter, (BYTE/2-1).U) // To synchronize mbio valid signal + val txMbUICounter_next = RegNext(txMbUICounter, 0.U) // To synchronize mbio valid signal + val hasData = Wire(Bool()) + val clockGateCounter = RegInit(0.U(log2Ceil(width).W)) + val fifoValid_next = RegNext(txMbFifos.map(_.io.deq.valid).reduce(_ && _)) + // val txMbUICounter_next = RegNext(txMbUICounter, (BYTE/2-1).U) // To synchronize mbio valid signal + + val shift = RegInit(false.B) + val outValid_next = RegNext(outValid) + hasData := ~(txMbFifos.map(_.io.deq.valid).reduce(_ && _) ^ fifoValid_next ) & fifoValid_next + when(outValid){ + clockGateCounter := 0.U + }.elsewhen(~outValid && clockGateCounter < width.U) { + clockGateCounter := clockGateCounter + 1.U + } + + io.txMbIo.clkn := Mux((clockGateCounter >= width.U && ~outValid), false.B, io.clkn.asBool).asClock + io.txMbIo.clkp := Mux((clockGateCounter >= width.U && ~outValid), false.B, io.clkp.asBool).asClock + // io.output_clkp := Mux((clockGateCounter >= 8.U && ~outValid), 0.U, io.clkp.asUInt) + // Assign each async fifo individually + txMbFifos.zipWithIndex.foreach{ case (txMbFifo, i) => + // Enqueue end from adapter + txMbFifo.io.enq_clock := clock //enq is from afe, use system clock + txMbFifo.io.enq_reset := reset // use system reset + txMbFifo.io.enq.bits := rxMbAfeData.bits(i) + txMbFifo.io.enq.valid := rxMbAfeData.valid + + // Dequeue end to analog + txMbFifo.io.deq_clock := io.clkp + txMbFifo.io.deq_reset := reset + txMbFifo.io.deq.ready := false.B + // Valid framing, up for first 4 ui, down for last 4 ui + // outValid := false.B + outTrack := false.B + when( txMbUICounter_next =/= txMbUICounter && (txMbUICounter_next % BYTE.U) <= (BYTE/2-1).U){ + outValid := true.B + }.otherwise{ + outValid := false.B + } + when(hasData){ + when(txMbUICounter === 0.U) { + txMbFifo.io.deq.ready := true.B + txMbShiftRegs(i) := txMbFifo.io.deq.bits + }.otherwise{ + txMbShiftRegs(i) := txMbShiftRegs(i) << 1.U + } + txMbUICounter := txMbUICounter + 1.U + } + when(txMbUICounter === 0.U && ~hasData){ + txMbUICounter := 0.U + shift := false.B + }.otherwise{ + txMbUICounter := txMbUICounter + 1.U + shift := true.B + } + when(shift){ + when(txMbUICounter === 0.U) { + txMbFifo.io.deq.ready := true.B + txMbShiftRegs(i) := txMbFifo.io.deq.bits + }.otherwise{ + txMbShiftRegs(i) := txMbShiftRegs(i) << 1.U + } + } + } + io.txMbIo.data := VecInit(txMbShiftRegs.map(_.head(1))).asUInt + rxMbAfeData.ready := txMbFifos.map(_.io.enq.ready).reduce(_ && _) + + io.txMbIo.track := outTrack + io.txMbIo.valid := outValid + } + + + withClock(clock) { + txMbFifos.zipWithIndex.foreach{ case (txMbFifo, i) => + // Enqueue end from adapter + txMbFifo.io.enq_clock := clock //enq is from afe, use system clock + txMbFifo.io.enq_reset := reset // use system reset + txMbFifo.io.enq.bits := rxMbAfeData.bits(i) + txMbFifo.io.enq.valid := rxMbAfeData.valid + + } + } +} + +// This module accepts data from analog and send to adapter +class RxMainband(afeParams: AfeParams, queueParams: AsyncQueueParams, BYTE: Int = 8) extends Module { + val io = IO(new Bundle { + // should use rx of mbafeIo + // val mbAfeIo = new MainbandAfeIo(AfeParams()) + val rxMbIo = Input(new MainbandIo()) + val txMbAfe = Decoupled(Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W))) + // Dummy signals for testing + val clkn_out = Output(Clock()) + + }) + + private val width = afeParams.mbSerializerRatio + private val lanes = afeParams.mbLanes + // Since sending data to adapter, + // This module Should drive mbAfeIo tx data + // io.mbAfeIo.rxData.ready := false.B + io.clkn_out := io.rxMbIo.clkn + // io.mbAfeIo.rxData.bits := Seq.fill(lanes)(0.U) + // val txMbAfeData = io.mbAfeIo.txData + val txMbAfeData = io.txMbAfe + + // This module receives data from analog, and store into async buffer + // val rxMbFifos = Seq.fill(lanes)(Module (new AsyncFifoStefan(depth, width))) + + // val rxMbFifos = Seq.fill(lanes)(Module ( + // new AsyncQueue( + // Bits(afeParams.mbSerializerRatio.W), + // queueParams) + // ) + // ) + val rxMbFifos = Seq.fill(lanes)(Module ( + new AsyncFifoCustom(32, afeParams.mbSerializerRatio) + )) + + // Enqueue end from analog + withClock(io.rxMbIo.clkp) { + val mbIoValid_pipe_0 = RegNext(io.rxMbIo.valid) + val mbIoValid_pipe_1 = RegNext(mbIoValid_pipe_0) + val mbIoValid_pipe_2 = RegNext(mbIoValid_pipe_1) + val mbIoValid_next = RegNext(mbIoValid_pipe_2) + + // Shiftregs to deserialize and store into the async buffer + val rxMbShiftRegs = Seq.fill(lanes)(RegInit(0.U(width.W))) + val rxMbShiftRegs_next = Seq.fill(lanes)(RegInit(0.U(width.W))) + val rxMbShiftRegs_xor = Seq.fill(lanes)(WireInit(0.U(width.W))) + + val rxMbUICounter = RegInit(0.U(log2Ceil(width).W)) + + val rxMbUICounter_next = RegNext(rxMbUICounter) + + // val rxMbIoData_next = RegNext(io.rxMbIo.data) + val rxMbIoData_next = RegInit(0.U(width.W)) + val fifo_enq_valid_next = RegNext(rxMbUICounter_next === (width-1).U && rxMbUICounter === 0.U) + val internal_valid = (mbIoValid_next ^ io.rxMbIo.valid) | (mbIoValid_next & io.rxMbIo.valid) + + rxMbFifos.zipWithIndex.foreach{ case(rxMbFifo, i) => + + rxMbFifo.io.enq_clock := io.rxMbIo.clkp + rxMbFifo.io.enq_reset := reset + rxMbFifo.io.enq.valid := false.B + // For clear testing visuals, should always connect to signal path for minimal delay + rxMbFifo.io.enq.bits := 0.U + // rxMbFifo.io.enq.bits := Cat(rxMbShiftRegs.reverse) + // There's a little overlap of assert high of io.rxMbIo.valid and last stage pipeline + // + when(internal_valid){ + rxMbIoData_next := io.rxMbIo.data + when(rxMbUICounter === 0.U) { + for(i <- 0 until lanes) { + rxMbShiftRegs(i) := 0.U | io.rxMbIo.data (i) + } + rxMbShiftRegs_next(i) := rxMbShiftRegs(i) + + }.otherwise { + for(i <- 0 until lanes) { + rxMbShiftRegs(i) := rxMbShiftRegs(i) << 1.U | io.rxMbIo.data (i) + } + rxMbShiftRegs_next(i) := 0.U + + } + rxMbUICounter := rxMbUICounter + 1.U + } + rxMbShiftRegs_xor(i) := rxMbShiftRegs(i) ^ rxMbShiftRegs_next(i) + when((rxMbUICounter_next === (width-1).U && rxMbUICounter === 0.U) + ^ fifo_enq_valid_next + ) { + rxMbFifo.io.enq.valid := true.B + rxMbFifo.io.enq.bits := Cat(rxMbShiftRegs_xor.reverse) + } + } + } + withClock(clock) { + + rxMbFifos.zipWithIndex.foreach{ case(rxMbFifo, i) => + + // Dequeue end to drive + rxMbFifo.io.deq_clock := clock + rxMbFifo.io.deq_reset := reset + txMbAfeData.bits(i) := rxMbFifo.io.deq.bits + txMbAfeData.valid := rxMbFifo.io.deq.valid + rxMbFifo.io.deq.ready := txMbAfeData.ready + } + } +} + +// class RxSideband(depth:Int, width: Int = 1, afeParams: AfeParams = AfeParams()) extends Module { +// val io = IO(new Bundle{ +// // val sbAfeIo = new SidebandAfeIo(AfeParams()) +// val txSbAfe = Decoupled(Bits(afeParams.sbSerializerRatio.W)) +// val clk_800 = Input(Clock()) +// val rxSbIo = Input(new SidebandIo()) +// }) +// private val bw = afeParams.sbSerializerRatio +// // private val bw = 8 +// val fifo = Module(new AsyncFifoStefan(depth, bw)) +// // val txMbFifos = Seq.fill(lanes)(Module (new AsyncFifoStefan(depth, BYTE))) +// io.txSbAfe.valid := fifo.io.deq.valid +// io.txSbAfe.bits := fifo.io.deq.bits +// fifo.io.deq.ready := io.txSbAfe.ready +// fifo.io.deq_clock := clock +// fifo.io.deq_reset := reset + +// withClock(io.clk_800){ +// val shiftReg = RegInit(0.U(bw.W)) +// val shiftReg_pipe_1 = RegNext(shiftReg) +// val shiftReg_xor = WireInit(0.U(bw.W)) + +// val rxCounter = RegInit(0.U(log2Ceil(bw).W)) +// val rxCounter_pipe_1 = RegNext(rxCounter) +// val rxCounter_pipe_2 = RegNext(rxCounter_pipe_1) +// val fifo_enq_valid_pipe_1 = RegNext(rxCounter_pipe_2 === (bw-1).U && rxCounter_pipe_1 === 0.U) + +// val data_pipe_1 = RegNext(io.rxSbIo.data) +// val data_pipe_2 = RegNext(data_pipe_1) +// val clock_pipe_1 = RegNext(io.rxSbIo.clk) +// val clock_pipe_2 = RegNext(clock_pipe_1) +// val enable = WireInit(false.B) +// val enable_counter = RegInit(0.U(2.W)) + +// enable := clock_pipe_1.asBool ^ clock_pipe_2.asBool +// shiftReg_xor := shiftReg ^ shiftReg_pipe_1 + +// when(enable){ +// enable_counter := 2.U +// }.elsewhen(enable_counter > 0.U){ +// enable_counter := enable_counter - 1.U +// } + +// fifo.io.enq.valid := false.B +// fifo.io.enq.bits := 0.U +// fifo.io.enq_clock := io.clk_800 +// fifo.io.enq_reset := reset +// when(enable_counter.orR){ +// when(rxCounter_pipe_2 === (bw-1).U){ +// shiftReg := 0.U | (data_pipe_2 << (bw-1).U) +// shiftReg_pipe_1 := shiftReg +// }.otherwise{ +// shiftReg := (shiftReg >> 1.U) | (data_pipe_2 << (bw-1).U) +// shiftReg_pipe_1 := 0.U +// } +// rxCounter := rxCounter + 1.U +// } +// when((rxCounter_pipe_2 === (bw-1).U && rxCounter_pipe_1 === 0.U) +// ^ fifo_enq_valid_pipe_1) { +// fifo.io.enq.valid := true.B +// fifo.io.enq.bits := shiftReg_xor +// } + +// } +// } + +// class TxSideband(depth:Int, width: Int = 1, afeParams: AfeParams=AfeParams()) extends Module { +// val io = IO(new Bundle { +// // sbAfeIo bw 64 bit +// // val sbAfeIo = new SidebandAfeIo(AfeParams()) +// val rxSbAfe = Flipped(Decoupled(Bits(afeParams.sbSerializerRatio.W))) +// val clk_800 = Input(Clock()) +// val txSbIo = Output(new SidebandIo()) +// }) +// private val bw = afeParams.sbSerializerRatio +// val fifo = Module(new AsyncFifoStefan(depth, bw)) + +// io.txSbIo.clk := io.clk_800 + +// fifo.io.enq.valid := io.rxSbAfe.valid +// fifo.io.enq.bits := io.rxSbAfe.bits +// io.rxSbAfe.ready := fifo.io.enq.ready +// fifo.io.enq_clock := clock +// fifo.io.enq_reset := reset + +// withClock(io.clk_800){ +// val txCounter = RegInit(0.U(log2Ceil(64).W)) +// val txIng = RegInit(false.B) // 0 is idle for 32 UI, 1 is transmitting 64 UI +// val shiftReg = RegInit(0.U(bw.W)) + +// fifo.io.deq.ready := false.B // always set to true for io.deq +// fifo.io.deq_clock := io.clk_800 +// fifo.io.deq_reset := reset +// // when(fifo.io.deq.ready){ +// when(txCounter === 31.U && txIng === false.B){ +// shiftReg := fifo.io.deq.bits +// fifo.io.deq.ready := true.B +// txIng := true.B +// txCounter := 0.U +// }.elsewhen(txCounter === 63.U && txIng === true.B){ +// txIng := false.B +// txCounter := 0.U +// }.otherwise{ +// txCounter := txCounter + 1.U +// } +// when(txIng === true.B){ +// shiftReg := shiftReg >> 1.U +// } +// io.txSbIo.data := shiftReg(0) +// io.txSbIo.clk := Mux(txIng, io.clk_800.asBool, false.B).asClock +// } +// } + +class PhyTest extends Module { + val io = IO(new Bundle { + val tx_user = new MainbandAfeIo(AfeParams()) + val rx_user = new MainbandAfeIo(AfeParams()) + val clkp = Input(Clock()) + val clkn = Input(Clock()) + // val startDeq = Input(Bool()) + // val startEnq = Input(Bool()) + val clkn_out = Output(Clock()) + }) + + + val sender = Module(new TxMainband(AfeParams(), AsyncQueueParams())) + val receiver = Module(new RxMainband(AfeParams(), AsyncQueueParams())) + sender.io.rxMbAfe <> io.tx_user.rxData + sender.io.txMbIo <> receiver.io.rxMbIo + sender.io.clkp := io.clkp + sender.io.clkn := io.clkn + sender.io.track := 0.U + + // sender.io.startDeq := io.startDeq + + receiver.io.txMbAfe <> io.rx_user.txData + // receiver.io.startEnq := io.startEnq + io.clkn_out := receiver.io.clkn_out + + io.tx_user.txData.bits := Seq.fill(16)(0.U) + io.tx_user.txData.valid := false.B + io.rx_user.rxData.ready := false.B + + io.tx_user.txFreqSel := SpeedMode.speed16 + io.tx_user.rxEn := false.B + io.rx_user.txFreqSel := SpeedMode.speed16 + io.rx_user.rxEn := false.B +} + +class MbAfe (afeParams: AfeParams, queueParams: AsyncQueueParams) extends Module { + val io = IO(new Bundle { + val mbAfeIo = new MainbandAfeIo(AfeParams()) + val sbAfeIo = new SidebandAfeIo(AfeParams()) + val stdIo = new StandardPackageIo() + // The following differential clock comes from pll + val clkp = Input(Clock()) + val clkn = Input(Clock()) + val clk_800 = Input(Clock()) + }) + + +// This module accepts data from analog and send to adapter +// class RxMainband(afeParams: AfeParams, queueParams: AsyncQueueParams, BYTE: Int = 8) extends Module { + val txMainband = Module(new TxMainband(afeParams, queueParams)) + val rxMainband = Module(new RxMainband(afeParams, queueParams)) + // val txSideband = Module(new TxSideband(depth)) + // val rxSideband = Module(new RxSideband(depth)) + + // txMainband + txMainband.io.rxMbAfe <> io.mbAfeIo.rxData + io.stdIo.tx.mainband := txMainband.io.txMbIo + txMainband.io.clkp := io.clkp + txMainband.io.clkn := io.clkn + txMainband.io.track := false.B + + rxMainband.io.txMbAfe <> io.mbAfeIo.txData + rxMainband.io.rxMbIo := io.stdIo.rx.mainband + io.stdIo.tx.sideband.data := 0.U + io.sbAfeIo.rxEn := false.B + io.mbAfeIo.txFreqSel := SpeedMode.speed16 + io.sbAfeIo.txData := 0.U + io.mbAfeIo.rxEn := false.B + io.sbAfeIo.txClock := false.B + io.stdIo.tx.sideband.clk := clock +} + +// To execute do: +// runMain edu.berkeley.cs.ucie.digital.afe.TxMainbandVerilog +object TxMainbandVerilog extends App { + (new ChiselStage).emitSystemVerilog(new TxMainband(AfeParams(), AsyncQueueParams()) + ) +} + +// To execute do: +// runMain edu.berkeley.cs.ucie.digital.afe.TxMainbandVerilog +object RxMainbandVerilog extends App { + (new ChiselStage).emitSystemVerilog(new RxMainband(AfeParams(), AsyncQueueParams()) + ) +} + +object PhyTestVerilog extends App { + (new ChiselStage).emitSystemVerilog(new PhyTest()) +} + +// object TxSidebandVerilog extends App { +// (new ChiselStage).emitSystemVerilog(new TxSideband(16)) +// } + + +// object RxSidebandVerilog extends App { +// (new ChiselStage).emitSystemVerilog(new RxSideband(16)) +// } + + +object MbAfeVerilog extends App { + (new ChiselStage).emitSystemVerilog(new MbAfe(AfeParams(), AsyncQueueParams())) +} \ No newline at end of file From eae32e27ea6608f8ade78d5af2e330c6d8121ed9 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Wed, 8 May 2024 18:24:37 -0700 Subject: [PATCH 074/106] pll lock set to true --- src/main/scala/e2e/UCITop.scala | 101 ++++++++++++++++++-------------- 1 file changed, 56 insertions(+), 45 deletions(-) diff --git a/src/main/scala/e2e/UCITop.scala b/src/main/scala/e2e/UCITop.scala index ed3a3e0..811b862 100644 --- a/src/main/scala/e2e/UCITop.scala +++ b/src/main/scala/e2e/UCITop.scala @@ -12,48 +12,58 @@ import d2dadapter._ import logphy._ import freechips.rocketchip.util.AsyncQueueParams -/** - * UCITop is the main class which instantiates all the three - * layers of the UCIe protocol stack - * +/** UCITop is the main class which instantiates all the three layers of the UCIe + * protocol stack */ -class UCITop(val fdiParams: FdiParams, val rdiParams: RdiParams, - val sbParams: SidebandParams, - val linkTrainingParams: LinkTrainingParams, - val afeParams: AfeParams, - val laneAsyncQueueParams: AsyncQueueParams) extends Module { - val io = IO(new Bundle{ - // IOs for connecting to the protocol layer - //val fdi = new Fdi(fdiParams) - val fdi_lpConfig = Valid(Bits(fdiParams.sbWidth.W)) - val fdi_lpConfigCredit = Input(Bool()) - val fdi_plConfig = Flipped(Valid(Bits(fdiParams.sbWidth.W))) - val fdi_plConfigCredit = Output(Bool()) - val fdi_lpStallAck = Output(Bool()) - val TLplStateStatus = Output(PhyState()) +class UCITop( + val fdiParams: FdiParams, + val rdiParams: RdiParams, + val sbParams: SidebandParams, + val linkTrainingParams: LinkTrainingParams, + val afeParams: AfeParams, + val laneAsyncQueueParams: AsyncQueueParams, +) extends Module { + val io = IO(new Bundle { + // IOs for connecting to the protocol layer + // val fdi = new Fdi(fdiParams) + val fdi_lpConfig = Valid(Bits(fdiParams.sbWidth.W)) + val fdi_lpConfigCredit = Input(Bool()) + val fdi_plConfig = Flipped(Valid(Bits(fdiParams.sbWidth.W))) + val fdi_plConfigCredit = Output(Bool()) + val fdi_lpStallAck = Output(Bool()) + val TLplStateStatus = Output(PhyState()) - val TLlpData_valid = Input(Bool()) - val TLlpData_bits = Input(Bits((8 * fdiParams.width).W)) - val TLlpData_irdy = Input(Bool()) - val TLlpData_ready = Output(Bool()) - val TLplData_bits = Output(Bits((8 * fdiParams.width).W)) - val TLplData_valid = Output(Bool()) - val TLready_to_rcv = Input(Bool()) - val fault = Input(Bool()) - val soft_reset = Input(Bool()) - // IOs for connecting to the AFE - //val mbAfe = new MainbandAfeIo(afeParams) - val mbAfe_tx = Output(new MainbandIo(afeParams.mbLanes)) - val mbAfe_rx = Input (new MainbandIo(afeParams.mbLanes)) - val sbAfe = new SidebandAfeIo(afeParams) - }) + val TLlpData_valid = Input(Bool()) + val TLlpData_bits = Input(Bits((8 * fdiParams.width).W)) + val TLlpData_irdy = Input(Bool()) + val TLlpData_ready = Output(Bool()) + val TLplData_bits = Output(Bits((8 * fdiParams.width).W)) + val TLplData_valid = Output(Bool()) + val TLready_to_rcv = Input(Bool()) + val fault = Input(Bool()) + val soft_reset = Input(Bool()) + // IOs for connecting to the AFE + // val mbAfe = new MainbandAfeIo(afeParams) + val mbAfe_tx = Output(new MainbandIo(afeParams.mbLanes)) + val mbAfe_rx = Input(new MainbandIo(afeParams.mbLanes)) + val sbAfe = new SidebandAfeIo(afeParams) + }) // Instantiate the agnostic protocol layer val protocol = Module(new ProtocolLayer(fdiParams)) // Instantiate the D2D adapter val d2dadapter = Module(new D2DAdapter(fdiParams, rdiParams, sbParams)) // Instantiate the logPhy - val logPhy = Module(new LogicalPhy(linkTrainingParams, afeParams, rdiParams, fdiParams, sbParams, laneAsyncQueueParams)) + val logPhy = Module( + new LogicalPhy( + linkTrainingParams, + afeParams, + rdiParams, + fdiParams, + sbParams, + laneAsyncQueueParams, + ), + ) val dafe = Module(new MbAfe(afeParams, AsyncQueueParams())) @@ -64,18 +74,18 @@ class UCITop(val fdiParams: FdiParams, val rdiParams: RdiParams, d2dadapter.io.rdi <> logPhy.io.rdi // Connect the AFE interface from logPhy to the top - //io.mbAfe <> logPhy.io.mbAfe + // io.mbAfe <> logPhy.io.mbAfe // logphy.io.mbAfe. - logPhy.io.mbAfe.txData <> dafe.io.mbAfeIo.rxData - logPhy.io.mbAfe.rxData <> dafe.io.mbAfeIo.txData + logPhy.io.mbAfe.txData <> dafe.io.mbAfeIo.rxData + logPhy.io.mbAfe.rxData <> dafe.io.mbAfeIo.txData // dafe.io. - io.mbAfe_tx <> dafe.io.stdIo.tx.mainband + io.mbAfe_tx <> dafe.io.stdIo.tx.mainband io.mbAfe_rx <> dafe.io.stdIo.rx.mainband // io.mbAfe <> dafe.io.stdIo.tx.mainband io.sbAfe <> logPhy.io.sbAfe - dafe.io.clkp := clock - dafe.io.clkn := clock + dafe.io.clkp := clock + dafe.io.clkn := clock dafe.io.clk_800 := clock dafe.io.sbAfeIo.fifoParams.clk := clock dafe.io.clk_800 := clock @@ -92,15 +102,16 @@ class UCITop(val fdiParams: FdiParams, val rdiParams: RdiParams, // dafe.io.stdIo.rx.mainband.clkp := clock // dafe.io.stdIo.rx.mainband.track := false.B dafe.io.clkn := clock - logPhy.io.mbAfe.pllLock := false.B - dafe.io.mbAfeIo.pllLock := false.B + logPhy.io.mbAfe.pllLock := true.B + dafe.io.mbAfeIo.pllLock := true.B dafe.io.stdIo.rx.sideband.data := 0.U dafe.io.sbAfeIo.pllLock := false.B dafe.io.sbAfeIo.fifoParams.reset := false.B logPhy.io.mbAfe.fifoParams.reset := false.B - // Connect the protocol IOs to the top for connections to the tilelink interface - //io.fdi <> protocol.io.fdi + /* Connect the protocol IOs to the top for connections to the tilelink + * interface */ + // io.fdi <> protocol.io.fdi io.fdi_lpConfig <> protocol.io.fdi.lpConfig io.fdi_lpConfigCredit <> protocol.io.fdi.lpConfigCredit io.fdi_plConfig <> protocol.io.fdi.plConfig @@ -118,4 +129,4 @@ class UCITop(val fdiParams: FdiParams, val rdiParams: RdiParams, protocol.io.fault := io.fault protocol.io.soft_reset := io.soft_reset -} \ No newline at end of file +} From a97d0e0c5bc489862150411c17d51ec2779c786c Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Wed, 8 May 2024 18:57:32 -0700 Subject: [PATCH 075/106] correct byte ordering mapping --- src/main/scala/logphy/Lanes.scala | 8 ++--- src/test/scala/logphy/LogPhyLaneTest.scala | 36 ++++++++++++++++++++++ 2 files changed, 40 insertions(+), 4 deletions(-) diff --git a/src/main/scala/logphy/Lanes.scala b/src/main/scala/logphy/Lanes.scala index 7be48ce..c8ccd09 100644 --- a/src/main/scala/logphy/Lanes.scala +++ b/src/main/scala/logphy/Lanes.scala @@ -55,12 +55,12 @@ class Lanes( ) for (i <- 0 until afeParams.mbLanes) { for (j <- 0 until ratioBytes) { - txDataVec(afeParams.mbLanes - 1 - i)(j) := io.mainbandLaneIO.txData + txDataVec(i)(ratioBytes - 1 - j) := io.mainbandLaneIO.txData .bits( afeParams.mbLanes * 8 * j + (i * 8) + 7, afeParams.mbLanes * 8 * j + (i * 8), ) - rxDataVec(j)(afeParams.mbLanes - 1 - i) := rxMBFifo.io.deq + rxDataVec(ratioBytes - 1 - j)(i) := rxMBFifo.io.deq .bits(i)((j + 1) * 8 - 1, j * 8) } txMBFifo.io.enq.bits(i) := txDataVec(i).asUInt @@ -121,12 +121,12 @@ class SimLanes( ) for (i <- 0 until afeParams.mbLanes) { for (j <- 0 until ratioBytes) { - txDataVec(afeParams.mbLanes - 1 - i)(j) := io.mainbandLaneIO.txData + txDataVec(i)(ratioBytes - 1 - j) := io.mainbandLaneIO.txData .bits( afeParams.mbLanes * 8 * j + (i * 8) + 7, afeParams.mbLanes * 8 * j + (i * 8), ) - rxDataVec(j)(afeParams.mbLanes - 1 - i) := rxMBFifo.io.deq + rxDataVec(ratioBytes - 1 - j)(i) := rxMBFifo.io.deq .bits(i)((j + 1) * 8 - 1, j * 8) } txMBFifo.io.enq.bits(i) := txDataVec(i).asUInt diff --git a/src/test/scala/logphy/LogPhyLaneTest.scala b/src/test/scala/logphy/LogPhyLaneTest.scala index e8bb8ee..90ee798 100644 --- a/src/test/scala/logphy/LogPhyLaneTest.scala +++ b/src/test/scala/logphy/LogPhyLaneTest.scala @@ -22,6 +22,41 @@ class LogPhyLaneTest extends AnyFlatSpec with ChiselScalatestTester { c.io.mainbandLaneIO.txData.enqueueNow( "h1234_5678_9abc_def0_0fed_cba9_8765_4321_1111_2222_3333_4444_5555_6666_7777_8888".U, ) + c.io.mainbandIo.txData + .expectDequeueNow( + Vec.Lit( + "h8821".U, + "h8843".U, + "h7765".U, + "h7787".U, + "h66a9".U, + "h66cb".U, + "h55ed".U, + "h550f".U, + "h44f0".U, + "h44de".U, + "h33bc".U, + "h339a".U, + "h2278".U, + "h2256".U, + "h1134".U, + "h1112".U, + ), + ) + } + } + + behavior of "log phy TX lanes" + ignore should "correctly map TX bytes to their lanes - test 2" in { + test(new SimLanes(afeParams, queueParams)) { c => + c.io.mainbandLaneIO.txData.initSource() + c.io.mainbandLaneIO.txData.setSourceClock(c.clock) + c.io.mainbandIo.txData.initSink() + c.io.mainbandIo.txData.setSinkClock(c.clock) + + c.io.mainbandLaneIO.txData.enqueueNow( + "h7840_80a0_001f_ffff_ffe0_0000_0000_0000_0000".U, + ) c.io.mainbandIo.txData .expectDequeueNow( Vec.Lit( @@ -83,4 +118,5 @@ class LogPhyLaneTest extends AnyFlatSpec with ChiselScalatestTester { } } + } From 82d020f8be15174b504827360d810a216e54ca1d Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Wed, 8 May 2024 19:15:56 -0700 Subject: [PATCH 076/106] remove async fifo afe --- src/main/scala/mbafe/MbAfe.scala | 581 +++++++++++++++---------------- 1 file changed, 277 insertions(+), 304 deletions(-) diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala index 279b9cd..8f90f69 100644 --- a/src/main/scala/mbafe/MbAfe.scala +++ b/src/main/scala/mbafe/MbAfe.scala @@ -2,242 +2,214 @@ package edu.berkeley.cs.ucie.digital package afe import chisel3._ -import chisel3.util._ +import chisel3.util._ import chisel3.stage.ChiselStage import interfaces._ import chisel3.experimental.DataMirror import freechips.rocketchip.util.{AsyncQueue, AsyncQueueParams} // This module receives data from adapter and sends to analog -class TxMainband(afeParams: AfeParams, queueParams: AsyncQueueParams, BYTE: Int = 8) extends Module { - val io = IO(new Bundle { - // should use rx of mbafeIo - // val mbAfeIo = new MainbandAfeIo(AfeParams()) - val rxMbAfe = Flipped(Decoupled(Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W)))) - val txMbIo = Output(new MainbandIo()) - - val clkp = Input(Clock()) - val clkn = Input(Clock()) - val track = Input(Bool()) - // val output_clkp = Output(Clock()) - // Dummy signals for testing - }) - val lanes = afeParams.mbLanes - val width = afeParams.mbSerializerRatio - - // io.mbAfeIo.txData.bits := Seq.fill(lanes)(0.U) - // io.mbAfeIo.txData.valid := false.B - - // receive data - // val rxMbAfeData = io.mbAfeIo.rxData - val rxMbAfeData = io.rxMbAfe - - // Default fifo has problem: when deq starts, data is XXXX for at least 10 cycles, not sure why - // Use custom async fifo, this one works - // val txMbFifos = Seq.fill(lanes)(Module (new AsyncFifoStefan(depth, width))) - // val txMbFifos = Seq.fill(lanes)(Module ( - // new AsyncQueue( - // Bits(afeParams.mbSerializerRatio.W), - // queueParams) - // ) - // ) - val txMbFifos = Seq.fill(lanes)(Module ( - new AsyncFifoCustom(32, afeParams.mbSerializerRatio) - )) - - withClock(io.clkp) { - val outValid = Wire(Bool()) - val outTrack = Wire(Bool()) - val txMbShiftRegs = Seq.fill(lanes)(RegInit(0.U(width.W))) - val txMbUICounter = RegInit(0.U(log2Ceil(width).W)) - // val txMbUICounter_next = RegNext(txMbUICounter, (BYTE/2-1).U) // To synchronize mbio valid signal - val txMbUICounter_next = RegNext(txMbUICounter, 0.U) // To synchronize mbio valid signal - val hasData = Wire(Bool()) - val clockGateCounter = RegInit(0.U(log2Ceil(width).W)) - val fifoValid_next = RegNext(txMbFifos.map(_.io.deq.valid).reduce(_ && _)) - // val txMbUICounter_next = RegNext(txMbUICounter, (BYTE/2-1).U) // To synchronize mbio valid signal - - val shift = RegInit(false.B) - val outValid_next = RegNext(outValid) - hasData := ~(txMbFifos.map(_.io.deq.valid).reduce(_ && _) ^ fifoValid_next ) & fifoValid_next - when(outValid){ - clockGateCounter := 0.U - }.elsewhen(~outValid && clockGateCounter < width.U) { - clockGateCounter := clockGateCounter + 1.U - } - - io.txMbIo.clkn := Mux((clockGateCounter >= width.U && ~outValid), false.B, io.clkn.asBool).asClock - io.txMbIo.clkp := Mux((clockGateCounter >= width.U && ~outValid), false.B, io.clkp.asBool).asClock - // io.output_clkp := Mux((clockGateCounter >= 8.U && ~outValid), 0.U, io.clkp.asUInt) - // Assign each async fifo individually - txMbFifos.zipWithIndex.foreach{ case (txMbFifo, i) => - // Enqueue end from adapter - txMbFifo.io.enq_clock := clock //enq is from afe, use system clock - txMbFifo.io.enq_reset := reset // use system reset - txMbFifo.io.enq.bits := rxMbAfeData.bits(i) - txMbFifo.io.enq.valid := rxMbAfeData.valid - - // Dequeue end to analog - txMbFifo.io.deq_clock := io.clkp - txMbFifo.io.deq_reset := reset - txMbFifo.io.deq.ready := false.B - // Valid framing, up for first 4 ui, down for last 4 ui - // outValid := false.B - outTrack := false.B - when( txMbUICounter_next =/= txMbUICounter && (txMbUICounter_next % BYTE.U) <= (BYTE/2-1).U){ - outValid := true.B - }.otherwise{ - outValid := false.B - } - when(hasData){ - when(txMbUICounter === 0.U) { - txMbFifo.io.deq.ready := true.B - txMbShiftRegs(i) := txMbFifo.io.deq.bits - }.otherwise{ - txMbShiftRegs(i) := txMbShiftRegs(i) << 1.U - } - txMbUICounter := txMbUICounter + 1.U - } - when(txMbUICounter === 0.U && ~hasData){ - txMbUICounter := 0.U - shift := false.B - }.otherwise{ - txMbUICounter := txMbUICounter + 1.U - shift := true.B - } - when(shift){ - when(txMbUICounter === 0.U) { - txMbFifo.io.deq.ready := true.B - txMbShiftRegs(i) := txMbFifo.io.deq.bits - }.otherwise{ - txMbShiftRegs(i) := txMbShiftRegs(i) << 1.U - } - } - } - io.txMbIo.data := VecInit(txMbShiftRegs.map(_.head(1))).asUInt - rxMbAfeData.ready := txMbFifos.map(_.io.enq.ready).reduce(_ && _) - - io.txMbIo.track := outTrack - io.txMbIo.valid := outValid +class TxMainband(afeParams: AfeParams, BYTE: Int = 8) extends Module { + val io = IO(new Bundle { + val rxMbAfe = Flipped( + Decoupled(Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W))), + ) + val txMbIo = Output(new MainbandIo()) + + val clkp = Input(Clock()) + val clkn = Input(Clock()) + val track = Input(Bool()) + }) + val lanes = afeParams.mbLanes + val width = afeParams.mbSerializerRatio + + // receive data + val rxMbAfeData = io.rxMbAfe.bits + + withClock(io.clkp) { + val outValid = Wire(Bool()) + val outTrack = Wire(Bool()) + val txMbShiftRegs = Seq.fill(lanes)(RegInit(0.U(width.W))) + val txMbUICounter = RegInit(0.U(log2Ceil(width).W)) + val txMbUICounter_next = + RegNext(txMbUICounter, 0.U) // To synchronize mbio valid signal + val hasData = Wire(Bool()) + val clockGateCounter = RegInit(0.U(log2Ceil(width).W)) + + val shift = RegInit(false.B) + when(outValid) { + clockGateCounter := 0.U + }.elsewhen(~outValid && clockGateCounter < width.U) { + clockGateCounter := clockGateCounter + 1.U } - - withClock(clock) { - txMbFifos.zipWithIndex.foreach{ case (txMbFifo, i) => - // Enqueue end from adapter - txMbFifo.io.enq_clock := clock //enq is from afe, use system clock - txMbFifo.io.enq_reset := reset // use system reset - txMbFifo.io.enq.bits := rxMbAfeData.bits(i) - txMbFifo.io.enq.valid := rxMbAfeData.valid - + io.txMbIo.clkn := Mux( + (clockGateCounter >= width.U && ~outValid), + false.B, + io.clkn.asBool, + ).asClock + io.txMbIo.clkp := Mux( + (clockGateCounter >= width.U && ~outValid), + false.B, + io.clkp.asBool, + ).asClock + + // Assign each async fifo individually + rxMbAfeData.zipWithIndex.foreach { case (data, i) => + // Valid framing, up for first 4 ui, down for last 4 ui + outTrack := false.B + when( + txMbUICounter_next =/= txMbUICounter && (txMbUICounter_next % BYTE.U) <= (BYTE / 2 - 1).U, + ) { + outValid := true.B + }.otherwise { + outValid := false.B + } + when(hasData) { + when(txMbUICounter === 0.U) { + txMbShiftRegs(i) := data + }.otherwise { + txMbShiftRegs(i) := txMbShiftRegs(i) << 1.U + } + txMbUICounter := txMbUICounter + 1.U + } + when(txMbUICounter === 0.U && ~hasData) { + txMbUICounter := 0.U + shift := false.B + }.otherwise { + txMbUICounter := txMbUICounter + 1.U + shift := true.B + } + when(shift) { + when(txMbUICounter === 0.U) { + txMbShiftRegs(i) := data + }.otherwise { + txMbShiftRegs(i) := txMbShiftRegs(i) << 1.U } + } } + io.txMbIo.data := VecInit(txMbShiftRegs.map(_.head(1))).asUInt + io.txMbIo.track := outTrack + io.txMbIo.valid := outValid + + io.rxMbAfe.ready := txMbUICounter === 0.U + } } // This module accepts data from analog and send to adapter -class RxMainband(afeParams: AfeParams, queueParams: AsyncQueueParams, BYTE: Int = 8) extends Module { - val io = IO(new Bundle { - // should use rx of mbafeIo - // val mbAfeIo = new MainbandAfeIo(AfeParams()) - val rxMbIo = Input(new MainbandIo()) - val txMbAfe = Decoupled(Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W))) - // Dummy signals for testing - val clkn_out = Output(Clock()) - - }) - - private val width = afeParams.mbSerializerRatio - private val lanes = afeParams.mbLanes - // Since sending data to adapter, - // This module Should drive mbAfeIo tx data - // io.mbAfeIo.rxData.ready := false.B - io.clkn_out := io.rxMbIo.clkn - // io.mbAfeIo.rxData.bits := Seq.fill(lanes)(0.U) - // val txMbAfeData = io.mbAfeIo.txData - val txMbAfeData = io.txMbAfe - - // This module receives data from analog, and store into async buffer - // val rxMbFifos = Seq.fill(lanes)(Module (new AsyncFifoStefan(depth, width))) - - // val rxMbFifos = Seq.fill(lanes)(Module ( - // new AsyncQueue( - // Bits(afeParams.mbSerializerRatio.W), - // queueParams) - // ) - // ) - val rxMbFifos = Seq.fill(lanes)(Module ( - new AsyncFifoCustom(32, afeParams.mbSerializerRatio) - )) - - // Enqueue end from analog - withClock(io.rxMbIo.clkp) { - val mbIoValid_pipe_0 = RegNext(io.rxMbIo.valid) - val mbIoValid_pipe_1 = RegNext(mbIoValid_pipe_0) - val mbIoValid_pipe_2 = RegNext(mbIoValid_pipe_1) - val mbIoValid_next = RegNext(mbIoValid_pipe_2) - - // Shiftregs to deserialize and store into the async buffer - val rxMbShiftRegs = Seq.fill(lanes)(RegInit(0.U(width.W))) - val rxMbShiftRegs_next = Seq.fill(lanes)(RegInit(0.U(width.W))) - val rxMbShiftRegs_xor = Seq.fill(lanes)(WireInit(0.U(width.W))) - - val rxMbUICounter = RegInit(0.U(log2Ceil(width).W)) - - val rxMbUICounter_next = RegNext(rxMbUICounter) - - // val rxMbIoData_next = RegNext(io.rxMbIo.data) - val rxMbIoData_next = RegInit(0.U(width.W)) - val fifo_enq_valid_next = RegNext(rxMbUICounter_next === (width-1).U && rxMbUICounter === 0.U) - val internal_valid = (mbIoValid_next ^ io.rxMbIo.valid) | (mbIoValid_next & io.rxMbIo.valid) - - rxMbFifos.zipWithIndex.foreach{ case(rxMbFifo, i) => - - rxMbFifo.io.enq_clock := io.rxMbIo.clkp - rxMbFifo.io.enq_reset := reset - rxMbFifo.io.enq.valid := false.B - // For clear testing visuals, should always connect to signal path for minimal delay - rxMbFifo.io.enq.bits := 0.U - // rxMbFifo.io.enq.bits := Cat(rxMbShiftRegs.reverse) - // There's a little overlap of assert high of io.rxMbIo.valid and last stage pipeline - // - when(internal_valid){ - rxMbIoData_next := io.rxMbIo.data - when(rxMbUICounter === 0.U) { - for(i <- 0 until lanes) { - rxMbShiftRegs(i) := 0.U | io.rxMbIo.data (i) - } - rxMbShiftRegs_next(i) := rxMbShiftRegs(i) - - }.otherwise { - for(i <- 0 until lanes) { - rxMbShiftRegs(i) := rxMbShiftRegs(i) << 1.U | io.rxMbIo.data (i) - } - rxMbShiftRegs_next(i) := 0.U - - } - rxMbUICounter := rxMbUICounter + 1.U - } - rxMbShiftRegs_xor(i) := rxMbShiftRegs(i) ^ rxMbShiftRegs_next(i) - when((rxMbUICounter_next === (width-1).U && rxMbUICounter === 0.U) - ^ fifo_enq_valid_next - ) { - rxMbFifo.io.enq.valid := true.B - rxMbFifo.io.enq.bits := Cat(rxMbShiftRegs_xor.reverse) - } - } - } - withClock(clock) { - - rxMbFifos.zipWithIndex.foreach{ case(rxMbFifo, i) => +class RxMainband( + afeParams: AfeParams, + queueParams: AsyncQueueParams, + BYTE: Int = 8, +) extends Module { + val io = IO(new Bundle { + // should use rx of mbafeIo + // val mbAfeIo = new MainbandAfeIo(AfeParams()) + val rxMbIo = Input(new MainbandIo()) + val txMbAfe = + Decoupled(Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W))) + // Dummy signals for testing + val clkn_out = Output(Clock()) + + }) + + private val width = afeParams.mbSerializerRatio + private val lanes = afeParams.mbLanes + // Since sending data to adapter, + // This module Should drive mbAfeIo tx data + // io.mbAfeIo.rxData.ready := false.B + io.clkn_out := io.rxMbIo.clkn + // io.mbAfeIo.rxData.bits := Seq.fill(lanes)(0.U) + // val txMbAfeData = io.mbAfeIo.txData + val txMbAfeData = io.txMbAfe + + // This module receives data from analog, and store into async buffer + // val rxMbFifos = Seq.fill(lanes)(Module (new AsyncFifoStefan(depth, width))) + + // val rxMbFifos = Seq.fill(lanes)(Module ( + // new AsyncQueue( + // Bits(afeParams.mbSerializerRatio.W), + // queueParams) + // ) + // ) + val rxMbFifos = Seq.fill(lanes)( + Module( + new AsyncFifoCustom(32, afeParams.mbSerializerRatio), + ), + ) + + // Enqueue end from analog + withClock(io.rxMbIo.clkp) { + val mbIoValid_pipe_0 = RegNext(io.rxMbIo.valid) + val mbIoValid_pipe_1 = RegNext(mbIoValid_pipe_0) + val mbIoValid_pipe_2 = RegNext(mbIoValid_pipe_1) + val mbIoValid_next = RegNext(mbIoValid_pipe_2) + + // Shiftregs to deserialize and store into the async buffer + val rxMbShiftRegs = Seq.fill(lanes)(RegInit(0.U(width.W))) + val rxMbShiftRegs_next = Seq.fill(lanes)(RegInit(0.U(width.W))) + val rxMbShiftRegs_xor = Seq.fill(lanes)(WireInit(0.U(width.W))) + + val rxMbUICounter = RegInit(0.U(log2Ceil(width).W)) + + val rxMbUICounter_next = RegNext(rxMbUICounter) + + // val rxMbIoData_next = RegNext(io.rxMbIo.data) + val rxMbIoData_next = RegInit(0.U(width.W)) + val fifo_enq_valid_next = + RegNext(rxMbUICounter_next === (width - 1).U && rxMbUICounter === 0.U) + val internal_valid = + (mbIoValid_next ^ io.rxMbIo.valid) | (mbIoValid_next & io.rxMbIo.valid) + + rxMbFifos.zipWithIndex.foreach { case (rxMbFifo, i) => + rxMbFifo.io.enq_clock := io.rxMbIo.clkp + rxMbFifo.io.enq_reset := reset + rxMbFifo.io.enq.valid := false.B + /* For clear testing visuals, should always connect to signal path for + * minimal delay */ + rxMbFifo.io.enq.bits := 0.U + // rxMbFifo.io.enq.bits := Cat(rxMbShiftRegs.reverse) + /* There's a little overlap of assert high of io.rxMbIo.valid and last + * stage pipeline */ + // + when(internal_valid) { + rxMbIoData_next := io.rxMbIo.data + when(rxMbUICounter === 0.U) { + for (i <- 0 until lanes) { + rxMbShiftRegs(i) := 0.U | io.rxMbIo.data(i) + } + rxMbShiftRegs_next(i) := rxMbShiftRegs(i) + + }.otherwise { + for (i <- 0 until lanes) { + rxMbShiftRegs(i) := rxMbShiftRegs(i) << 1.U | io.rxMbIo.data(i) + } + rxMbShiftRegs_next(i) := 0.U - // Dequeue end to drive - rxMbFifo.io.deq_clock := clock - rxMbFifo.io.deq_reset := reset - txMbAfeData.bits(i) := rxMbFifo.io.deq.bits - txMbAfeData.valid := rxMbFifo.io.deq.valid - rxMbFifo.io.deq.ready := txMbAfeData.ready } + rxMbUICounter := rxMbUICounter + 1.U + } + rxMbShiftRegs_xor(i) := rxMbShiftRegs(i) ^ rxMbShiftRegs_next(i) + when( + (rxMbUICounter_next === (width - 1).U && rxMbUICounter === 0.U) + ^ fifo_enq_valid_next, + ) { + rxMbFifo.io.enq.valid := true.B + rxMbFifo.io.enq.bits := Cat(rxMbShiftRegs_xor.reverse) + } + } + } + withClock(clock) { + + rxMbFifos.zipWithIndex.foreach { case (rxMbFifo, i) => + // Dequeue end to drive + rxMbFifo.io.deq_clock := clock + rxMbFifo.io.deq_reset := reset + txMbAfeData.bits(i) := rxMbFifo.io.deq.bits + txMbAfeData.valid := rxMbFifo.io.deq.valid + rxMbFifo.io.deq.ready := txMbAfeData.ready } + } } // class RxSideband(depth:Int, width: Int = 1, afeParams: AfeParams = AfeParams()) extends Module { @@ -249,9 +221,9 @@ class RxMainband(afeParams: AfeParams, queueParams: AsyncQueueParams, BYTE: Int // }) // private val bw = afeParams.sbSerializerRatio // // private val bw = 8 -// val fifo = Module(new AsyncFifoStefan(depth, bw)) +// val fifo = Module(new AsyncFifoStefan(depth, bw)) // // val txMbFifos = Seq.fill(lanes)(Module (new AsyncFifoStefan(depth, BYTE))) -// io.txSbAfe.valid := fifo.io.deq.valid +// io.txSbAfe.valid := fifo.io.deq.valid // io.txSbAfe.bits := fifo.io.deq.bits // fifo.io.deq.ready := io.txSbAfe.ready // fifo.io.deq_clock := clock @@ -265,7 +237,7 @@ class RxMainband(afeParams: AfeParams, queueParams: AsyncQueueParams, BYTE: Int // val rxCounter = RegInit(0.U(log2Ceil(bw).W)) // val rxCounter_pipe_1 = RegNext(rxCounter) // val rxCounter_pipe_2 = RegNext(rxCounter_pipe_1) -// val fifo_enq_valid_pipe_1 = RegNext(rxCounter_pipe_2 === (bw-1).U && rxCounter_pipe_1 === 0.U) +// val fifo_enq_valid_pipe_1 = RegNext(rxCounter_pipe_2 === (bw-1).U && rxCounter_pipe_1 === 0.U) // val data_pipe_1 = RegNext(io.rxSbIo.data) // val data_pipe_2 = RegNext(data_pipe_1) @@ -283,7 +255,7 @@ class RxMainband(afeParams: AfeParams, queueParams: AsyncQueueParams, BYTE: Int // enable_counter := enable_counter - 1.U // } -// fifo.io.enq.valid := false.B +// fifo.io.enq.valid := false.B // fifo.io.enq.bits := 0.U // fifo.io.enq_clock := io.clk_800 // fifo.io.enq_reset := reset @@ -300,7 +272,7 @@ class RxMainband(afeParams: AfeParams, queueParams: AsyncQueueParams, BYTE: Int // when((rxCounter_pipe_2 === (bw-1).U && rxCounter_pipe_1 === 0.U) // ^ fifo_enq_valid_pipe_1) { // fifo.io.enq.valid := true.B -// fifo.io.enq.bits := shiftReg_xor +// fifo.io.enq.bits := shiftReg_xor // } // } @@ -331,12 +303,12 @@ class RxMainband(afeParams: AfeParams, queueParams: AsyncQueueParams, BYTE: Int // val shiftReg = RegInit(0.U(bw.W)) // fifo.io.deq.ready := false.B // always set to true for io.deq -// fifo.io.deq_clock := io.clk_800 -// fifo.io.deq_reset := reset +// fifo.io.deq_clock := io.clk_800 +// fifo.io.deq_reset := reset // // when(fifo.io.deq.ready){ // when(txCounter === 31.U && txIng === false.B){ // shiftReg := fifo.io.deq.bits -// fifo.io.deq.ready := true.B +// fifo.io.deq.ready := true.B // txIng := true.B // txCounter := 0.U // }.elsewhen(txCounter === 63.U && txIng === true.B){ @@ -354,106 +326,107 @@ class RxMainband(afeParams: AfeParams, queueParams: AsyncQueueParams, BYTE: Int // } class PhyTest extends Module { - val io = IO(new Bundle { - val tx_user = new MainbandAfeIo(AfeParams()) - val rx_user = new MainbandAfeIo(AfeParams()) - val clkp = Input(Clock()) - val clkn = Input(Clock()) - // val startDeq = Input(Bool()) - // val startEnq = Input(Bool()) - val clkn_out = Output(Clock()) - }) - - - val sender = Module(new TxMainband(AfeParams(), AsyncQueueParams())) - val receiver = Module(new RxMainband(AfeParams(), AsyncQueueParams())) - sender.io.rxMbAfe <> io.tx_user.rxData - sender.io.txMbIo <> receiver.io.rxMbIo - sender.io.clkp := io.clkp - sender.io.clkn := io.clkn - sender.io.track := 0.U - - // sender.io.startDeq := io.startDeq - - receiver.io.txMbAfe <> io.rx_user.txData - // receiver.io.startEnq := io.startEnq - io.clkn_out := receiver.io.clkn_out - - io.tx_user.txData.bits := Seq.fill(16)(0.U) - io.tx_user.txData.valid := false.B - io.rx_user.rxData.ready := false.B - - io.tx_user.txFreqSel := SpeedMode.speed16 - io.tx_user.rxEn := false.B - io.rx_user.txFreqSel := SpeedMode.speed16 - io.rx_user.rxEn := false.B + val io = IO(new Bundle { + val tx_user = new MainbandAfeIo(AfeParams()) + val rx_user = new MainbandAfeIo(AfeParams()) + val clkp = Input(Clock()) + val clkn = Input(Clock()) + // val startDeq = Input(Bool()) + // val startEnq = Input(Bool()) + val clkn_out = Output(Clock()) + }) + + val sender = Module(new TxMainband(AfeParams(), AsyncQueueParams())) + val receiver = Module(new RxMainband(AfeParams(), AsyncQueueParams())) + sender.io.rxMbAfe <> io.tx_user.rxData + sender.io.txMbIo <> receiver.io.rxMbIo + sender.io.clkp := io.clkp + sender.io.clkn := io.clkn + sender.io.track := 0.U + + // sender.io.startDeq := io.startDeq + + receiver.io.txMbAfe <> io.rx_user.txData + // receiver.io.startEnq := io.startEnq + io.clkn_out := receiver.io.clkn_out + + io.tx_user.txData.bits := Seq.fill(16)(0.U) + io.tx_user.txData.valid := false.B + io.rx_user.rxData.ready := false.B + + io.tx_user.txFreqSel := SpeedMode.speed16 + io.tx_user.rxEn := false.B + io.rx_user.txFreqSel := SpeedMode.speed16 + io.rx_user.rxEn := false.B } -class MbAfe (afeParams: AfeParams, queueParams: AsyncQueueParams) extends Module { - val io = IO(new Bundle { - val mbAfeIo = new MainbandAfeIo(AfeParams()) - val sbAfeIo = new SidebandAfeIo(AfeParams()) - val stdIo = new StandardPackageIo() - // The following differential clock comes from pll - val clkp = Input(Clock()) - val clkn = Input(Clock()) - val clk_800 = Input(Clock()) - }) - +class MbAfe(afeParams: AfeParams, queueParams: AsyncQueueParams) + extends Module { + val io = IO(new Bundle { + val mbAfeIo = new MainbandAfeIo(AfeParams()) + val sbAfeIo = new SidebandAfeIo(AfeParams()) + val stdIo = new StandardPackageIo() + // The following differential clock comes from pll + val clkp = Input(Clock()) + val clkn = Input(Clock()) + val clk_800 = Input(Clock()) + }) // This module accepts data from analog and send to adapter // class RxMainband(afeParams: AfeParams, queueParams: AsyncQueueParams, BYTE: Int = 8) extends Module { - val txMainband = Module(new TxMainband(afeParams, queueParams)) - val rxMainband = Module(new RxMainband(afeParams, queueParams)) - // val txSideband = Module(new TxSideband(depth)) - // val rxSideband = Module(new RxSideband(depth)) - - // txMainband - txMainband.io.rxMbAfe <> io.mbAfeIo.rxData - io.stdIo.tx.mainband := txMainband.io.txMbIo - txMainband.io.clkp := io.clkp - txMainband.io.clkn := io.clkn - txMainband.io.track := false.B - - rxMainband.io.txMbAfe <> io.mbAfeIo.txData - rxMainband.io.rxMbIo := io.stdIo.rx.mainband - io.stdIo.tx.sideband.data := 0.U - io.sbAfeIo.rxEn := false.B - io.mbAfeIo.txFreqSel := SpeedMode.speed16 - io.sbAfeIo.txData := 0.U - io.mbAfeIo.rxEn := false.B - io.sbAfeIo.txClock := false.B - io.stdIo.tx.sideband.clk := clock + val txMainband = Module(new TxMainband(afeParams, queueParams)) + val rxMainband = Module(new RxMainband(afeParams, queueParams)) + // val txSideband = Module(new TxSideband(depth)) + // val rxSideband = Module(new RxSideband(depth)) + + // txMainband + txMainband.io.rxMbAfe <> io.mbAfeIo.rxData + io.stdIo.tx.mainband := txMainband.io.txMbIo + txMainband.io.clkp := io.clkp + txMainband.io.clkn := io.clkn + txMainband.io.track := false.B + + rxMainband.io.txMbAfe <> io.mbAfeIo.txData + rxMainband.io.rxMbIo := io.stdIo.rx.mainband + io.stdIo.tx.sideband.data := 0.U + io.sbAfeIo.rxEn := false.B + io.mbAfeIo.txFreqSel := SpeedMode.speed16 + io.sbAfeIo.txData := 0.U + io.mbAfeIo.rxEn := false.B + io.sbAfeIo.txClock := false.B + io.stdIo.tx.sideband.clk := clock } // To execute do: -// runMain edu.berkeley.cs.ucie.digital.afe.TxMainbandVerilog +// runMain edu.berkeley.cs.ucie.digital.afe.TxMainbandVerilog object TxMainbandVerilog extends App { - (new ChiselStage).emitSystemVerilog(new TxMainband(AfeParams(), AsyncQueueParams()) - ) + (new ChiselStage).emitSystemVerilog( + new TxMainband(AfeParams(), AsyncQueueParams()), + ) } // To execute do: -// runMain edu.berkeley.cs.ucie.digital.afe.TxMainbandVerilog +// runMain edu.berkeley.cs.ucie.digital.afe.TxMainbandVerilog object RxMainbandVerilog extends App { - (new ChiselStage).emitSystemVerilog(new RxMainband(AfeParams(), AsyncQueueParams()) - ) + (new ChiselStage).emitSystemVerilog( + new RxMainband(AfeParams(), AsyncQueueParams()), + ) } object PhyTestVerilog extends App { - (new ChiselStage).emitSystemVerilog(new PhyTest()) + (new ChiselStage).emitSystemVerilog(new PhyTest()) } // object TxSidebandVerilog extends App { // (new ChiselStage).emitSystemVerilog(new TxSideband(16)) // } - // object RxSidebandVerilog extends App { // (new ChiselStage).emitSystemVerilog(new RxSideband(16)) // } - object MbAfeVerilog extends App { - (new ChiselStage).emitSystemVerilog(new MbAfe(AfeParams(), AsyncQueueParams())) -} \ No newline at end of file + (new ChiselStage).emitSystemVerilog( + new MbAfe(AfeParams(), AsyncQueueParams()), + ) +} From bd042fa0dd5594e29383dbe7da120b35aa1bc564 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Wed, 8 May 2024 19:18:14 -0700 Subject: [PATCH 077/106] remove async fifo afe --- src/main/scala/mbafe/MbAfe.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala index 8f90f69..966c060 100644 --- a/src/main/scala/mbafe/MbAfe.scala +++ b/src/main/scala/mbafe/MbAfe.scala @@ -336,7 +336,7 @@ class PhyTest extends Module { val clkn_out = Output(Clock()) }) - val sender = Module(new TxMainband(AfeParams(), AsyncQueueParams())) + val sender = Module(new TxMainband(AfeParams())) val receiver = Module(new RxMainband(AfeParams(), AsyncQueueParams())) sender.io.rxMbAfe <> io.tx_user.rxData sender.io.txMbIo <> receiver.io.rxMbIo From d1a66ce6b6b84bd952ffa64a0cd920cd19c7f975 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Wed, 8 May 2024 19:19:47 -0700 Subject: [PATCH 078/106] remove async fifo afe --- src/main/scala/mbafe/MbAfe.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala index 966c060..5bf3eed 100644 --- a/src/main/scala/mbafe/MbAfe.scala +++ b/src/main/scala/mbafe/MbAfe.scala @@ -374,7 +374,7 @@ class MbAfe(afeParams: AfeParams, queueParams: AsyncQueueParams) // This module accepts data from analog and send to adapter // class RxMainband(afeParams: AfeParams, queueParams: AsyncQueueParams, BYTE: Int = 8) extends Module { - val txMainband = Module(new TxMainband(afeParams, queueParams)) + val txMainband = Module(new TxMainband(afeParams)) val rxMainband = Module(new RxMainband(afeParams, queueParams)) // val txSideband = Module(new TxSideband(depth)) // val rxSideband = Module(new RxSideband(depth)) @@ -401,7 +401,7 @@ class MbAfe(afeParams: AfeParams, queueParams: AsyncQueueParams) // runMain edu.berkeley.cs.ucie.digital.afe.TxMainbandVerilog object TxMainbandVerilog extends App { (new ChiselStage).emitSystemVerilog( - new TxMainband(AfeParams(), AsyncQueueParams()), + new TxMainband(AfeParams()), ) } From 51189908c5b825adee7c74835164eda491633560 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Wed, 8 May 2024 19:29:18 -0700 Subject: [PATCH 079/106] update hasData --- src/main/scala/mbafe/MbAfe.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala index 5bf3eed..7d315ef 100644 --- a/src/main/scala/mbafe/MbAfe.scala +++ b/src/main/scala/mbafe/MbAfe.scala @@ -22,6 +22,9 @@ class TxMainband(afeParams: AfeParams, BYTE: Int = 8) extends Module { }) val lanes = afeParams.mbLanes val width = afeParams.mbSerializerRatio + val dataValidNext = RegNext(io.rxMbAfe.valid) + val hasData = Wire(Bool()) + hasData := (io.rxMbAfe.valid) & dataValidNext // receive data val rxMbAfeData = io.rxMbAfe.bits @@ -33,7 +36,6 @@ class TxMainband(afeParams: AfeParams, BYTE: Int = 8) extends Module { val txMbUICounter = RegInit(0.U(log2Ceil(width).W)) val txMbUICounter_next = RegNext(txMbUICounter, 0.U) // To synchronize mbio valid signal - val hasData = Wire(Bool()) val clockGateCounter = RegInit(0.U(log2Ceil(width).W)) val shift = RegInit(false.B) From 1fa8adf1ff3b229102d7b74615c3deeda64981aa Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Wed, 8 May 2024 20:18:22 -0700 Subject: [PATCH 080/106] update mb serializer --- src/main/scala/mbafe/MbAfe.scala | 238 ++++++------------------------- 1 file changed, 44 insertions(+), 194 deletions(-) diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala index 7d315ef..7991e95 100644 --- a/src/main/scala/mbafe/MbAfe.scala +++ b/src/main/scala/mbafe/MbAfe.scala @@ -8,94 +8,65 @@ import interfaces._ import chisel3.experimental.DataMirror import freechips.rocketchip.util.{AsyncQueue, AsyncQueueParams} -// This module receives data from adapter and sends to analog +// This module receives data from logphy and sends to analog class TxMainband(afeParams: AfeParams, BYTE: Int = 8) extends Module { val io = IO(new Bundle { val rxMbAfe = Flipped( Decoupled(Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W))), ) val txMbIo = Output(new MainbandIo()) - - val clkp = Input(Clock()) - val clkn = Input(Clock()) - val track = Input(Bool()) }) + val lanes = afeParams.mbLanes val width = afeParams.mbSerializerRatio - val dataValidNext = RegNext(io.rxMbAfe.valid) val hasData = Wire(Bool()) - hasData := (io.rxMbAfe.valid) & dataValidNext + hasData := io.rxMbAfe.valid // receive data - val rxMbAfeData = io.rxMbAfe.bits - - withClock(io.clkp) { - val outValid = Wire(Bool()) - val outTrack = Wire(Bool()) - val txMbShiftRegs = Seq.fill(lanes)(RegInit(0.U(width.W))) - val txMbUICounter = RegInit(0.U(log2Ceil(width).W)) - val txMbUICounter_next = - RegNext(txMbUICounter, 0.U) // To synchronize mbio valid signal - val clockGateCounter = RegInit(0.U(log2Ceil(width).W)) - - val shift = RegInit(false.B) - when(outValid) { - clockGateCounter := 0.U - }.elsewhen(~outValid && clockGateCounter < width.U) { - clockGateCounter := clockGateCounter + 1.U - } - io.txMbIo.clkn := Mux( - (clockGateCounter >= width.U && ~outValid), - false.B, - io.clkn.asBool, - ).asClock - io.txMbIo.clkp := Mux( - (clockGateCounter >= width.U && ~outValid), - false.B, - io.clkp.asBool, - ).asClock - - // Assign each async fifo individually - rxMbAfeData.zipWithIndex.foreach { case (data, i) => - // Valid framing, up for first 4 ui, down for last 4 ui - outTrack := false.B - when( - txMbUICounter_next =/= txMbUICounter && (txMbUICounter_next % BYTE.U) <= (BYTE / 2 - 1).U, - ) { - outValid := true.B - }.otherwise { - outValid := false.B - } - when(hasData) { - when(txMbUICounter === 0.U) { - txMbShiftRegs(i) := data - }.otherwise { - txMbShiftRegs(i) := txMbShiftRegs(i) << 1.U - } - txMbUICounter := txMbUICounter + 1.U - } - when(txMbUICounter === 0.U && ~hasData) { - txMbUICounter := 0.U - shift := false.B - }.otherwise { - txMbUICounter := txMbUICounter + 1.U - shift := true.B - } - when(shift) { - when(txMbUICounter === 0.U) { - txMbShiftRegs(i) := data - }.otherwise { - txMbShiftRegs(i) := txMbShiftRegs(i) << 1.U - } - } - } - io.txMbIo.data := VecInit(txMbShiftRegs.map(_.head(1))).asUInt - io.txMbIo.track := outTrack - io.txMbIo.valid := outValid + val txMbShiftRegs = Seq.fill(lanes)(RegInit(0.U(width.W))) + val sending = RegInit(false.B) + val clockGated = RegInit(false.B) + val (txMbUICounter, uiCountDone) = Counter(sending, width) + val (clockGateCounter, clockGateDone) = Counter(!sending, width) + + io.rxMbAfe.ready := !sending && !clockGated + when(io.rxMbAfe.fire) { + sending := true.B + }.elsewhen(uiCountDone) { + sending := false.B + clockGated := true.B + }.elsewhen(clockGateDone) { + clockGated := false.B + } - io.rxMbAfe.ready := txMbUICounter === 0.U + val shift = RegInit(false.B) + + io.txMbIo.clkn := Mux( + !clockGated, + false.B, + !clock.asBool, + ).asClock + + io.txMbIo.clkp := Mux( + !clockGated, + false.B, + clock.asBool, + ).asClock + + // Assign each async fifo individually + io.rxMbAfe.bits.zipWithIndex.foreach { case (data, i) => + // Valid framing, up for first 4 ui, down for last 4 ui + when(io.rxMbAfe.fire) { + txMbShiftRegs(i) := data + }.otherwise { + txMbShiftRegs(i) := txMbShiftRegs(i) << 1.U + } } + + io.txMbIo.data := VecInit(txMbShiftRegs.map(_.head(1))).asUInt + io.txMbIo.valid := sending + io.txMbIo.track := false.B } // This module accepts data from analog and send to adapter @@ -214,119 +185,6 @@ class RxMainband( } } -// class RxSideband(depth:Int, width: Int = 1, afeParams: AfeParams = AfeParams()) extends Module { -// val io = IO(new Bundle{ -// // val sbAfeIo = new SidebandAfeIo(AfeParams()) -// val txSbAfe = Decoupled(Bits(afeParams.sbSerializerRatio.W)) -// val clk_800 = Input(Clock()) -// val rxSbIo = Input(new SidebandIo()) -// }) -// private val bw = afeParams.sbSerializerRatio -// // private val bw = 8 -// val fifo = Module(new AsyncFifoStefan(depth, bw)) -// // val txMbFifos = Seq.fill(lanes)(Module (new AsyncFifoStefan(depth, BYTE))) -// io.txSbAfe.valid := fifo.io.deq.valid -// io.txSbAfe.bits := fifo.io.deq.bits -// fifo.io.deq.ready := io.txSbAfe.ready -// fifo.io.deq_clock := clock -// fifo.io.deq_reset := reset - -// withClock(io.clk_800){ -// val shiftReg = RegInit(0.U(bw.W)) -// val shiftReg_pipe_1 = RegNext(shiftReg) -// val shiftReg_xor = WireInit(0.U(bw.W)) - -// val rxCounter = RegInit(0.U(log2Ceil(bw).W)) -// val rxCounter_pipe_1 = RegNext(rxCounter) -// val rxCounter_pipe_2 = RegNext(rxCounter_pipe_1) -// val fifo_enq_valid_pipe_1 = RegNext(rxCounter_pipe_2 === (bw-1).U && rxCounter_pipe_1 === 0.U) - -// val data_pipe_1 = RegNext(io.rxSbIo.data) -// val data_pipe_2 = RegNext(data_pipe_1) -// val clock_pipe_1 = RegNext(io.rxSbIo.clk) -// val clock_pipe_2 = RegNext(clock_pipe_1) -// val enable = WireInit(false.B) -// val enable_counter = RegInit(0.U(2.W)) - -// enable := clock_pipe_1.asBool ^ clock_pipe_2.asBool -// shiftReg_xor := shiftReg ^ shiftReg_pipe_1 - -// when(enable){ -// enable_counter := 2.U -// }.elsewhen(enable_counter > 0.U){ -// enable_counter := enable_counter - 1.U -// } - -// fifo.io.enq.valid := false.B -// fifo.io.enq.bits := 0.U -// fifo.io.enq_clock := io.clk_800 -// fifo.io.enq_reset := reset -// when(enable_counter.orR){ -// when(rxCounter_pipe_2 === (bw-1).U){ -// shiftReg := 0.U | (data_pipe_2 << (bw-1).U) -// shiftReg_pipe_1 := shiftReg -// }.otherwise{ -// shiftReg := (shiftReg >> 1.U) | (data_pipe_2 << (bw-1).U) -// shiftReg_pipe_1 := 0.U -// } -// rxCounter := rxCounter + 1.U -// } -// when((rxCounter_pipe_2 === (bw-1).U && rxCounter_pipe_1 === 0.U) -// ^ fifo_enq_valid_pipe_1) { -// fifo.io.enq.valid := true.B -// fifo.io.enq.bits := shiftReg_xor -// } - -// } -// } - -// class TxSideband(depth:Int, width: Int = 1, afeParams: AfeParams=AfeParams()) extends Module { -// val io = IO(new Bundle { -// // sbAfeIo bw 64 bit -// // val sbAfeIo = new SidebandAfeIo(AfeParams()) -// val rxSbAfe = Flipped(Decoupled(Bits(afeParams.sbSerializerRatio.W))) -// val clk_800 = Input(Clock()) -// val txSbIo = Output(new SidebandIo()) -// }) -// private val bw = afeParams.sbSerializerRatio -// val fifo = Module(new AsyncFifoStefan(depth, bw)) - -// io.txSbIo.clk := io.clk_800 - -// fifo.io.enq.valid := io.rxSbAfe.valid -// fifo.io.enq.bits := io.rxSbAfe.bits -// io.rxSbAfe.ready := fifo.io.enq.ready -// fifo.io.enq_clock := clock -// fifo.io.enq_reset := reset - -// withClock(io.clk_800){ -// val txCounter = RegInit(0.U(log2Ceil(64).W)) -// val txIng = RegInit(false.B) // 0 is idle for 32 UI, 1 is transmitting 64 UI -// val shiftReg = RegInit(0.U(bw.W)) - -// fifo.io.deq.ready := false.B // always set to true for io.deq -// fifo.io.deq_clock := io.clk_800 -// fifo.io.deq_reset := reset -// // when(fifo.io.deq.ready){ -// when(txCounter === 31.U && txIng === false.B){ -// shiftReg := fifo.io.deq.bits -// fifo.io.deq.ready := true.B -// txIng := true.B -// txCounter := 0.U -// }.elsewhen(txCounter === 63.U && txIng === true.B){ -// txIng := false.B -// txCounter := 0.U -// }.otherwise{ -// txCounter := txCounter + 1.U -// } -// when(txIng === true.B){ -// shiftReg := shiftReg >> 1.U -// } -// io.txSbIo.data := shiftReg(0) -// io.txSbIo.clk := Mux(txIng, io.clk_800.asBool, false.B).asClock -// } -// } - class PhyTest extends Module { val io = IO(new Bundle { val tx_user = new MainbandAfeIo(AfeParams()) @@ -419,14 +277,6 @@ object PhyTestVerilog extends App { (new ChiselStage).emitSystemVerilog(new PhyTest()) } -// object TxSidebandVerilog extends App { -// (new ChiselStage).emitSystemVerilog(new TxSideband(16)) -// } - -// object RxSidebandVerilog extends App { -// (new ChiselStage).emitSystemVerilog(new RxSideband(16)) -// } - object MbAfeVerilog extends App { (new ChiselStage).emitSystemVerilog( new MbAfe(AfeParams(), AsyncQueueParams()), From ce125232e3dc096a181af364b5343ada3c70c3ba Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Wed, 8 May 2024 20:19:43 -0700 Subject: [PATCH 081/106] update mb serializer --- src/main/scala/mbafe/MbAfe.scala | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala index 7991e95..1301bec 100644 --- a/src/main/scala/mbafe/MbAfe.scala +++ b/src/main/scala/mbafe/MbAfe.scala @@ -200,9 +200,6 @@ class PhyTest extends Module { val receiver = Module(new RxMainband(AfeParams(), AsyncQueueParams())) sender.io.rxMbAfe <> io.tx_user.rxData sender.io.txMbIo <> receiver.io.rxMbIo - sender.io.clkp := io.clkp - sender.io.clkn := io.clkn - sender.io.track := 0.U // sender.io.startDeq := io.startDeq @@ -242,9 +239,6 @@ class MbAfe(afeParams: AfeParams, queueParams: AsyncQueueParams) // txMainband txMainband.io.rxMbAfe <> io.mbAfeIo.rxData io.stdIo.tx.mainband := txMainband.io.txMbIo - txMainband.io.clkp := io.clkp - txMainband.io.clkn := io.clkn - txMainband.io.track := false.B rxMainband.io.txMbAfe <> io.mbAfeIo.txData rxMainband.io.rxMbIo := io.stdIo.rx.mainband From ed3d728b50e1775b331401c6788638dc6224d9bf Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Wed, 8 May 2024 20:29:03 -0700 Subject: [PATCH 082/106] no clock parking --- src/main/scala/mbafe/MbAfe.scala | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala index 1301bec..3f7a160 100644 --- a/src/main/scala/mbafe/MbAfe.scala +++ b/src/main/scala/mbafe/MbAfe.scala @@ -42,17 +42,8 @@ class TxMainband(afeParams: AfeParams, BYTE: Int = 8) extends Module { val shift = RegInit(false.B) - io.txMbIo.clkn := Mux( - !clockGated, - false.B, - !clock.asBool, - ).asClock - - io.txMbIo.clkp := Mux( - !clockGated, - false.B, - clock.asBool, - ).asClock + io.txMbIo.clkn := (!clock.asBool).asClock + io.txMbIo.clkp := clock // Assign each async fifo individually io.rxMbAfe.bits.zipWithIndex.foreach { case (data, i) => From 0bea641fb9f548af0660b3bbcb1966c087a51919 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Wed, 8 May 2024 20:36:48 -0700 Subject: [PATCH 083/106] serialize lsb first --- src/main/scala/mbafe/MbAfe.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala index 3f7a160..f29e01e 100644 --- a/src/main/scala/mbafe/MbAfe.scala +++ b/src/main/scala/mbafe/MbAfe.scala @@ -46,16 +46,16 @@ class TxMainband(afeParams: AfeParams, BYTE: Int = 8) extends Module { io.txMbIo.clkp := clock // Assign each async fifo individually - io.rxMbAfe.bits.zipWithIndex.foreach { case (data, i) => + io.rxMbAfe.bits.zipWithIndex.foreach { case (laneData, i) => // Valid framing, up for first 4 ui, down for last 4 ui when(io.rxMbAfe.fire) { - txMbShiftRegs(i) := data + txMbShiftRegs(i) := laneData }.otherwise { - txMbShiftRegs(i) := txMbShiftRegs(i) << 1.U + txMbShiftRegs(i) := txMbShiftRegs(i) >> 1.U } } - io.txMbIo.data := VecInit(txMbShiftRegs.map(_.head(1))).asUInt + io.txMbIo.data := VecInit(txMbShiftRegs.map(_(0))).asUInt io.txMbIo.valid := sending io.txMbIo.track := false.B } From 80f63431209e6e7448a2bdd5c59eb3387380c011 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Wed, 8 May 2024 21:18:30 -0700 Subject: [PATCH 084/106] remove async fifo rx --- src/main/scala/e2e/UCITop.scala | 11 -- src/main/scala/mbafe/MbAfe.scala | 205 ++++--------------------------- 2 files changed, 24 insertions(+), 192 deletions(-) diff --git a/src/main/scala/e2e/UCITop.scala b/src/main/scala/e2e/UCITop.scala index 811b862..c297d06 100644 --- a/src/main/scala/e2e/UCITop.scala +++ b/src/main/scala/e2e/UCITop.scala @@ -84,24 +84,13 @@ class UCITop( // io.mbAfe <> dafe.io.stdIo.tx.mainband io.sbAfe <> logPhy.io.sbAfe - dafe.io.clkp := clock - dafe.io.clkn := clock - dafe.io.clk_800 := clock dafe.io.sbAfeIo.fifoParams.clk := clock - dafe.io.clk_800 := clock dafe.io.sbAfeIo.rxData := 0.U dafe.io.mbAfeIo.fifoParams.clk := clock - // dafe.io.stdIo.rx.mainband.valid := false.B - // dafe.io.stdIo.rx.mainband.clkn := clock - // dafe.io.stdIo.rx.mainband.data := 0.U - dafe.io.clkp := clock dafe.io.stdIo.rx.sideband.clk := clock dafe.io.mbAfeIo.fifoParams.reset := false.B logPhy.io.mbAfe.fifoParams.clk := clock dafe.io.sbAfeIo.rxClock := false.B - // dafe.io.stdIo.rx.mainband.clkp := clock - // dafe.io.stdIo.rx.mainband.track := false.B - dafe.io.clkn := clock logPhy.io.mbAfe.pllLock := true.B dafe.io.mbAfeIo.pllLock := true.B dafe.io.stdIo.rx.sideband.data := 0.U diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala index f29e01e..86ea4d9 100644 --- a/src/main/scala/mbafe/MbAfe.scala +++ b/src/main/scala/mbafe/MbAfe.scala @@ -9,9 +9,9 @@ import chisel3.experimental.DataMirror import freechips.rocketchip.util.{AsyncQueue, AsyncQueueParams} // This module receives data from logphy and sends to analog -class TxMainband(afeParams: AfeParams, BYTE: Int = 8) extends Module { +class TxMainbandSerializer(afeParams: AfeParams) extends Module { val io = IO(new Bundle { - val rxMbAfe = Flipped( + val txInData = Flipped( Decoupled(Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W))), ) val txMbIo = Output(new MainbandIo()) @@ -20,24 +20,19 @@ class TxMainband(afeParams: AfeParams, BYTE: Int = 8) extends Module { val lanes = afeParams.mbLanes val width = afeParams.mbSerializerRatio val hasData = Wire(Bool()) - hasData := io.rxMbAfe.valid + hasData := io.txInData.valid // receive data val txMbShiftRegs = Seq.fill(lanes)(RegInit(0.U(width.W))) val sending = RegInit(false.B) - val clockGated = RegInit(false.B) val (txMbUICounter, uiCountDone) = Counter(sending, width) - val (clockGateCounter, clockGateDone) = Counter(!sending, width) - io.rxMbAfe.ready := !sending && !clockGated - when(io.rxMbAfe.fire) { + io.txInData.ready := !sending + when(io.txInData.fire) { sending := true.B }.elsewhen(uiCountDone) { sending := false.B - clockGated := true.B - }.elsewhen(clockGateDone) { - clockGated := false.B } val shift = RegInit(false.B) @@ -46,9 +41,9 @@ class TxMainband(afeParams: AfeParams, BYTE: Int = 8) extends Module { io.txMbIo.clkp := clock // Assign each async fifo individually - io.rxMbAfe.bits.zipWithIndex.foreach { case (laneData, i) => + io.txInData.bits.zipWithIndex.foreach { case (laneData, i) => // Valid framing, up for first 4 ui, down for last 4 ui - when(io.rxMbAfe.fire) { + when(io.txInData.fire) { txMbShiftRegs(i) := laneData }.otherwise { txMbShiftRegs(i) := txMbShiftRegs(i) >> 1.U @@ -61,151 +56,30 @@ class TxMainband(afeParams: AfeParams, BYTE: Int = 8) extends Module { } // This module accepts data from analog and send to adapter -class RxMainband( +class RxMainbandDeserializer( afeParams: AfeParams, - queueParams: AsyncQueueParams, - BYTE: Int = 8, ) extends Module { val io = IO(new Bundle { - // should use rx of mbafeIo - // val mbAfeIo = new MainbandAfeIo(AfeParams()) val rxMbIo = Input(new MainbandIo()) - val txMbAfe = + val rxOutData = Decoupled(Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W))) - // Dummy signals for testing - val clkn_out = Output(Clock()) - }) private val width = afeParams.mbSerializerRatio private val lanes = afeParams.mbLanes - // Since sending data to adapter, - // This module Should drive mbAfeIo tx data - // io.mbAfeIo.rxData.ready := false.B - io.clkn_out := io.rxMbIo.clkn - // io.mbAfeIo.rxData.bits := Seq.fill(lanes)(0.U) - // val txMbAfeData = io.mbAfeIo.txData - val txMbAfeData = io.txMbAfe - - // This module receives data from analog, and store into async buffer - // val rxMbFifos = Seq.fill(lanes)(Module (new AsyncFifoStefan(depth, width))) - - // val rxMbFifos = Seq.fill(lanes)(Module ( - // new AsyncQueue( - // Bits(afeParams.mbSerializerRatio.W), - // queueParams) - // ) - // ) - val rxMbFifos = Seq.fill(lanes)( - Module( - new AsyncFifoCustom(32, afeParams.mbSerializerRatio), - ), - ) - - // Enqueue end from analog - withClock(io.rxMbIo.clkp) { - val mbIoValid_pipe_0 = RegNext(io.rxMbIo.valid) - val mbIoValid_pipe_1 = RegNext(mbIoValid_pipe_0) - val mbIoValid_pipe_2 = RegNext(mbIoValid_pipe_1) - val mbIoValid_next = RegNext(mbIoValid_pipe_2) - - // Shiftregs to deserialize and store into the async buffer - val rxMbShiftRegs = Seq.fill(lanes)(RegInit(0.U(width.W))) - val rxMbShiftRegs_next = Seq.fill(lanes)(RegInit(0.U(width.W))) - val rxMbShiftRegs_xor = Seq.fill(lanes)(WireInit(0.U(width.W))) - - val rxMbUICounter = RegInit(0.U(log2Ceil(width).W)) - - val rxMbUICounter_next = RegNext(rxMbUICounter) - - // val rxMbIoData_next = RegNext(io.rxMbIo.data) - val rxMbIoData_next = RegInit(0.U(width.W)) - val fifo_enq_valid_next = - RegNext(rxMbUICounter_next === (width - 1).U && rxMbUICounter === 0.U) - val internal_valid = - (mbIoValid_next ^ io.rxMbIo.valid) | (mbIoValid_next & io.rxMbIo.valid) - rxMbFifos.zipWithIndex.foreach { case (rxMbFifo, i) => - rxMbFifo.io.enq_clock := io.rxMbIo.clkp - rxMbFifo.io.enq_reset := reset - rxMbFifo.io.enq.valid := false.B - /* For clear testing visuals, should always connect to signal path for - * minimal delay */ - rxMbFifo.io.enq.bits := 0.U - // rxMbFifo.io.enq.bits := Cat(rxMbShiftRegs.reverse) - /* There's a little overlap of assert high of io.rxMbIo.valid and last - * stage pipeline */ - // - when(internal_valid) { - rxMbIoData_next := io.rxMbIo.data - when(rxMbUICounter === 0.U) { - for (i <- 0 until lanes) { - rxMbShiftRegs(i) := 0.U | io.rxMbIo.data(i) - } - rxMbShiftRegs_next(i) := rxMbShiftRegs(i) + val rxMbShiftRegs = Seq.fill(lanes)(RegInit(0.U(width.W))) + val (_, done_sending) = Counter(io.rxMbIo.valid, width) - }.otherwise { - for (i <- 0 until lanes) { - rxMbShiftRegs(i) := rxMbShiftRegs(i) << 1.U | io.rxMbIo.data(i) - } - rxMbShiftRegs_next(i) := 0.U - - } - rxMbUICounter := rxMbUICounter + 1.U - } - rxMbShiftRegs_xor(i) := rxMbShiftRegs(i) ^ rxMbShiftRegs_next(i) - when( - (rxMbUICounter_next === (width - 1).U && rxMbUICounter === 0.U) - ^ fifo_enq_valid_next, - ) { - rxMbFifo.io.enq.valid := true.B - rxMbFifo.io.enq.bits := Cat(rxMbShiftRegs_xor.reverse) + rxMbShiftRegs.zipWithIndex.foreach { case (rxMbShiftReg, i) => + when(io.rxMbIo.valid) { + for (i <- 0 until lanes) { + rxMbShiftReg := (rxMbShiftReg << 1.U) | io.rxMbIo.data(i) } } + io.rxOutData.bits(i) := rxMbShiftReg } - withClock(clock) { - - rxMbFifos.zipWithIndex.foreach { case (rxMbFifo, i) => - // Dequeue end to drive - rxMbFifo.io.deq_clock := clock - rxMbFifo.io.deq_reset := reset - txMbAfeData.bits(i) := rxMbFifo.io.deq.bits - txMbAfeData.valid := rxMbFifo.io.deq.valid - rxMbFifo.io.deq.ready := txMbAfeData.ready - } - } -} - -class PhyTest extends Module { - val io = IO(new Bundle { - val tx_user = new MainbandAfeIo(AfeParams()) - val rx_user = new MainbandAfeIo(AfeParams()) - val clkp = Input(Clock()) - val clkn = Input(Clock()) - // val startDeq = Input(Bool()) - // val startEnq = Input(Bool()) - val clkn_out = Output(Clock()) - }) - - val sender = Module(new TxMainband(AfeParams())) - val receiver = Module(new RxMainband(AfeParams(), AsyncQueueParams())) - sender.io.rxMbAfe <> io.tx_user.rxData - sender.io.txMbIo <> receiver.io.rxMbIo - - // sender.io.startDeq := io.startDeq - - receiver.io.txMbAfe <> io.rx_user.txData - // receiver.io.startEnq := io.startEnq - io.clkn_out := receiver.io.clkn_out - - io.tx_user.txData.bits := Seq.fill(16)(0.U) - io.tx_user.txData.valid := false.B - io.rx_user.rxData.ready := false.B - - io.tx_user.txFreqSel := SpeedMode.speed16 - io.tx_user.rxEn := false.B - io.rx_user.txFreqSel := SpeedMode.speed16 - io.rx_user.rxEn := false.B + io.rxOutData.valid := done_sending } class MbAfe(afeParams: AfeParams, queueParams: AsyncQueueParams) @@ -214,24 +88,19 @@ class MbAfe(afeParams: AfeParams, queueParams: AsyncQueueParams) val mbAfeIo = new MainbandAfeIo(AfeParams()) val sbAfeIo = new SidebandAfeIo(AfeParams()) val stdIo = new StandardPackageIo() - // The following differential clock comes from pll - val clkp = Input(Clock()) - val clkn = Input(Clock()) - val clk_800 = Input(Clock()) }) -// This module accepts data from analog and send to adapter -// class RxMainband(afeParams: AfeParams, queueParams: AsyncQueueParams, BYTE: Int = 8) extends Module { - val txMainband = Module(new TxMainband(afeParams)) - val rxMainband = Module(new RxMainband(afeParams, queueParams)) - // val txSideband = Module(new TxSideband(depth)) - // val rxSideband = Module(new RxSideband(depth)) + val txMainband = Module(new TxMainbandSerializer(afeParams)) + val rxMainband = + withClockAndReset(io.stdIo.rx.mainband.clkp, reset.asAsyncReset)( + Module(new RxMainbandDeserializer(afeParams)), + ) // txMainband - txMainband.io.rxMbAfe <> io.mbAfeIo.rxData + txMainband.io.txInData <> io.mbAfeIo.rxData io.stdIo.tx.mainband := txMainband.io.txMbIo - rxMainband.io.txMbAfe <> io.mbAfeIo.txData + rxMainband.io.rxOutData <> io.mbAfeIo.txData rxMainband.io.rxMbIo := io.stdIo.rx.mainband io.stdIo.tx.sideband.data := 0.U io.sbAfeIo.rxEn := false.B @@ -241,29 +110,3 @@ class MbAfe(afeParams: AfeParams, queueParams: AsyncQueueParams) io.sbAfeIo.txClock := false.B io.stdIo.tx.sideband.clk := clock } - -// To execute do: -// runMain edu.berkeley.cs.ucie.digital.afe.TxMainbandVerilog -object TxMainbandVerilog extends App { - (new ChiselStage).emitSystemVerilog( - new TxMainband(AfeParams()), - ) -} - -// To execute do: -// runMain edu.berkeley.cs.ucie.digital.afe.TxMainbandVerilog -object RxMainbandVerilog extends App { - (new ChiselStage).emitSystemVerilog( - new RxMainband(AfeParams(), AsyncQueueParams()), - ) -} - -object PhyTestVerilog extends App { - (new ChiselStage).emitSystemVerilog(new PhyTest()) -} - -object MbAfeVerilog extends App { - (new ChiselStage).emitSystemVerilog( - new MbAfe(AfeParams(), AsyncQueueParams()), - ) -} From c9a93acf73f6cdb6d99f931f84879d3d597352c6 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Wed, 8 May 2024 21:24:14 -0700 Subject: [PATCH 085/106] change lane update --- src/main/scala/mbafe/MbAfe.scala | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala index 86ea4d9..f5614d9 100644 --- a/src/main/scala/mbafe/MbAfe.scala +++ b/src/main/scala/mbafe/MbAfe.scala @@ -73,9 +73,7 @@ class RxMainbandDeserializer( rxMbShiftRegs.zipWithIndex.foreach { case (rxMbShiftReg, i) => when(io.rxMbIo.valid) { - for (i <- 0 until lanes) { - rxMbShiftReg := (rxMbShiftReg << 1.U) | io.rxMbIo.data(i) - } + rxMbShiftReg := (rxMbShiftReg << 1.U) | io.rxMbIo.data(i) } io.rxOutData.bits(i) := rxMbShiftReg } From a0d6aa5f1ad865d9451f628c98424e16308b8e9b Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Wed, 8 May 2024 21:30:53 -0700 Subject: [PATCH 086/106] reverse bit direction rx --- src/main/scala/mbafe/MbAfe.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala index f5614d9..5c4f222 100644 --- a/src/main/scala/mbafe/MbAfe.scala +++ b/src/main/scala/mbafe/MbAfe.scala @@ -75,7 +75,7 @@ class RxMainbandDeserializer( when(io.rxMbIo.valid) { rxMbShiftReg := (rxMbShiftReg << 1.U) | io.rxMbIo.data(i) } - io.rxOutData.bits(i) := rxMbShiftReg + io.rxOutData.bits(i) := Reverse(rxMbShiftReg) } io.rxOutData.valid := done_sending } From 002d01237a502928914cff3f32948119f8f1b6b9 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Wed, 8 May 2024 21:35:03 -0700 Subject: [PATCH 087/106] update out_valid to have cycle delay --- src/main/scala/mbafe/MbAfe.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala index 5c4f222..46f7dd1 100644 --- a/src/main/scala/mbafe/MbAfe.scala +++ b/src/main/scala/mbafe/MbAfe.scala @@ -70,6 +70,7 @@ class RxMainbandDeserializer( val rxMbShiftRegs = Seq.fill(lanes)(RegInit(0.U(width.W))) val (_, done_sending) = Counter(io.rxMbIo.valid, width) + val out_valid = RegNext(done_sending) rxMbShiftRegs.zipWithIndex.foreach { case (rxMbShiftReg, i) => when(io.rxMbIo.valid) { @@ -77,7 +78,7 @@ class RxMainbandDeserializer( } io.rxOutData.bits(i) := Reverse(rxMbShiftReg) } - io.rxOutData.valid := done_sending + io.rxOutData.valid := out_valid } class MbAfe(afeParams: AfeParams, queueParams: AsyncQueueParams) From c98cc19d3bf00816b5aabfafa1e33c689b62d191 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Wed, 8 May 2024 21:50:48 -0700 Subject: [PATCH 088/106] try increase timeout --- src/test/scala/e2e/AfeLoopbackTest.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/test/scala/e2e/AfeLoopbackTest.scala b/src/test/scala/e2e/AfeLoopbackTest.scala index 3abfc9d..d221d88 100644 --- a/src/test/scala/e2e/AfeLoopbackTest.scala +++ b/src/test/scala/e2e/AfeLoopbackTest.scala @@ -82,7 +82,7 @@ class AfeLoopbackTester(implicit p: Parameters) extends LazyModule { val AfeLoopback = Module(new AfeLoopback(afeParams)) io.uci_clock <> clockSourceNode.out(0)._1 // inputs to tlUcieDie1 - //tlUcieDie1.module.io.mbAfe <> AfeLoopback.io.mbAfe + // tlUcieDie1.module.io.mbAfe <> AfeLoopback.io.mbAfe tlUcieDie1.module.io.mbAfe_tx <> AfeLoopback.io.mbAfe_tx tlUcieDie1.module.io.mbAfe_rx <> AfeLoopback.io.mbAfe_rx tlUcieDie1.module.io.sbAfe <> AfeLoopback.io.sbAfe @@ -105,7 +105,7 @@ class AfeTLTestHarness(implicit val p: Parameters) extends Module { class AfeLoopbackTest extends AnyFlatSpec with ChiselScalatestTester { behavior of "AfeLoopback" val txns = 2 - val timeout = 4000 + val timeout = 100000 implicit val p: Parameters = Parameters.empty it should "finish request and response before timeout" in { test(new AfeTLTestHarness()).withAnnotations( From dafd44cc68922227dad63a7d1228687af39c8de3 Mon Sep 17 00:00:00 2001 From: Vikram Jain Date: Wed, 8 May 2024 22:30:09 -0700 Subject: [PATCH 089/106] fixing the pl_trdy --- src/main/scala/tilelink/UCITLFront.scala | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/src/main/scala/tilelink/UCITLFront.scala b/src/main/scala/tilelink/UCITLFront.scala index 8800d54..b26241b 100644 --- a/src/main/scala/tilelink/UCITLFront.scala +++ b/src/main/scala/tilelink/UCITLFront.scala @@ -74,8 +74,6 @@ class UCITLFrontImp extends Impl { }) withClockAndReset(clock, reset) { - withClockAndReset(clock, reset) { - val fault = RegInit(false.B) // if fault in ecc code // Instantiate the agnostic protocol layer @@ -251,14 +249,15 @@ class UCITLFrontImp extends Impl { val checksum_reg = RegInit(0.U(64.W)) checksum_reg := hammingEncoder.io.checksum - val tx_pipe = Module(new Pipe(new UCIRawPayloadFormat(tlParams, protoParams), 1)) + val tx_pipe = Module(new Queue(new UCIRawPayloadFormat(tlParams, protoParams), 1)) tx_pipe.io.enq.bits := uciTxPayload tx_pipe.io.enq.valid := txArbiter.io.out.fire // Dequeue the TX TL packets and translate to UCIe flit - txArbiter.io.out.ready := ucietop.io.TLlpData_ready // if pl_trdy is asserted + txArbiter.io.out.ready := tx_pipe.io.enq.ready + tx_pipe.io.deq.ready := ucietop.io.TLlpData_ready // if pl_trdy is asserted // specs implies that these needs to be asserted at the same time - ucietop.io.TLlpData_valid := tx_pipe.io.deq.valid & (~ucietop.io.fdi_lpStallAck) - ucietop.io.TLlpData_irdy := tx_pipe.io.deq.valid & (~ucietop.io.fdi_lpStallAck) + ucietop.io.TLlpData_valid := tx_pipe.io.deq.fire & (~ucietop.io.fdi_lpStallAck) + ucietop.io.TLlpData_irdy := tx_pipe.io.deq.fire & (~ucietop.io.fdi_lpStallAck) ucietop.io.TLlpData_bits := Cat(tx_pipe.io.deq.bits.asUInt(511,64), checksum_reg.asUInt) // assign uciTXPayload to the FDI lp data signa val creditA = (txArbiter.io.out.bits.msgType === UCIProtoMsgTypes.TLA) @@ -267,8 +266,8 @@ class UCITLFrontImp extends Impl { val creditD = (txArbiter.io.out.bits.msgType === UCIProtoMsgTypes.TLD) val creditE = (txArbiter.io.out.bits.msgType === UCIProtoMsgTypes.TLE) - outwardA.io.credit.ready := tx_pipe.io.deq.valid && creditA - outwardD.io.credit.ready := tx_pipe.io.deq.valid && creditD + outwardA.io.credit.ready := tx_pipe.io.deq.fire && creditA + outwardD.io.credit.ready := tx_pipe.io.deq.fire && creditD val txACredit = WireDefault(0.U(protoParams.creditWidth.W)) val txDCredit = WireDefault(0.U(protoParams.creditWidth.W)) @@ -391,4 +390,4 @@ class UCITLFrontImp extends Impl { // sent out before triggering reset ucietop.io.soft_reset := (regNode.module.io.d2d_csrs.d2d_state_can_reset | regNode.module.io.d2d_csrs.d2d_flush_and_reset) -}}}} \ No newline at end of file +}}} \ No newline at end of file From bfdf0c600b0ef6d5244ca2b3b2c9c8f92ca713d3 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 9 May 2024 12:40:33 -0700 Subject: [PATCH 090/106] fix IO directions --- src/main/scala/e2e/UCITop.scala | 22 +++++++++++++-------- src/main/scala/mbafe/MbAfe.scala | 33 ++++++++++++++------------------ 2 files changed, 28 insertions(+), 27 deletions(-) diff --git a/src/main/scala/e2e/UCITop.scala b/src/main/scala/e2e/UCITop.scala index c297d06..881094c 100644 --- a/src/main/scala/e2e/UCITop.scala +++ b/src/main/scala/e2e/UCITop.scala @@ -46,7 +46,8 @@ class UCITop( // val mbAfe = new MainbandAfeIo(afeParams) val mbAfe_tx = Output(new MainbandIo(afeParams.mbLanes)) val mbAfe_rx = Input(new MainbandIo(afeParams.mbLanes)) - val sbAfe = new SidebandAfeIo(afeParams) + val sbTxIO = Output(new SidebandIo) + val sbRxIO = Input(new SidebandIo) }) // Instantiate the agnostic protocol layer @@ -65,7 +66,7 @@ class UCITop( ), ) - val dafe = Module(new MbAfe(afeParams, AsyncQueueParams())) + val dafe = Module(new MbAfe(afeParams)) // Connect the FDI interface of Protocol layer to D2D adapter protocol.io.fdi <> d2dadapter.io.fdi @@ -73,17 +74,22 @@ class UCITop( // Connect the RDI interface of D2D adapter to logPhy d2dadapter.io.rdi <> logPhy.io.rdi - // Connect the AFE interface from logPhy to the top - // io.mbAfe <> logPhy.io.mbAfe - // logphy.io.mbAfe. + /** Sideband AFE connections (ser/des in logphy) + */ logPhy.io.mbAfe.txData <> dafe.io.mbAfeIo.rxData logPhy.io.mbAfe.rxData <> dafe.io.mbAfeIo.txData - // dafe.io. io.mbAfe_tx <> dafe.io.stdIo.tx.mainband io.mbAfe_rx <> dafe.io.stdIo.rx.mainband - // io.mbAfe <> dafe.io.stdIo.tx.mainband - io.sbAfe <> logPhy.io.sbAfe + io.sbTxIO.clk := logPhy.io.sbAfe.txClock + io.sbTxIO.data := logPhy.io.sbAfe.txData + logPhy.io.sbAfe.rxClock := io.sbRxIO.clk + logPhy.io.sbAfe.rxData := io.sbRxIO.data + /** Mainband AFE connections to toplevel IOs + */ + + /** Logphy connections to Digital AFE + * */ dafe.io.sbAfeIo.fifoParams.clk := clock dafe.io.sbAfeIo.rxData := 0.U dafe.io.mbAfeIo.fifoParams.clk := clock diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala index 46f7dd1..0866992 100644 --- a/src/main/scala/mbafe/MbAfe.scala +++ b/src/main/scala/mbafe/MbAfe.scala @@ -81,31 +81,26 @@ class RxMainbandDeserializer( io.rxOutData.valid := out_valid } -class MbAfe(afeParams: AfeParams, queueParams: AsyncQueueParams) - extends Module { +class MbAfe(afeParams: AfeParams) extends Module { val io = IO(new Bundle { - val mbAfeIo = new MainbandAfeIo(AfeParams()) - val sbAfeIo = new SidebandAfeIo(AfeParams()) - val stdIo = new StandardPackageIo() + val mbAfeIo = Flipped(new MainbandAfeIo(AfeParams())) + val mbTxData = Output(new MainbandIo(afeParams.mbLanes)) + val mbRxData = Input(new MainbandIo(afeParams.mbLanes)) }) val txMainband = Module(new TxMainbandSerializer(afeParams)) val rxMainband = - withClockAndReset(io.stdIo.rx.mainband.clkp, reset.asAsyncReset)( + withClockAndReset(io.mbRxData.clkp, reset.asAsyncReset)( Module(new RxMainbandDeserializer(afeParams)), ) - // txMainband - txMainband.io.txInData <> io.mbAfeIo.rxData - io.stdIo.tx.mainband := txMainband.io.txMbIo - - rxMainband.io.rxOutData <> io.mbAfeIo.txData - rxMainband.io.rxMbIo := io.stdIo.rx.mainband - io.stdIo.tx.sideband.data := 0.U - io.sbAfeIo.rxEn := false.B - io.mbAfeIo.txFreqSel := SpeedMode.speed16 - io.sbAfeIo.txData := 0.U - io.mbAfeIo.rxEn := false.B - io.sbAfeIo.txClock := false.B - io.stdIo.tx.sideband.clk := clock + /** Connect to LogPhy AFE IO */ + io.mbAfeIo.fifoParams.clk := io.mbRxData.clkp + io.mbAfeIo.fifoParams.reset := reset.asAsyncReset + io.mbAfeIo.txData <> txMainband.io.txInData + io.mbAfeIo.rxData <> rxMainband.io.rxOutData + + /** Connect to Mainband IO */ + io.mbTxData <> txMainband.io.txMbIo + io.mbRxData <> rxMainband.io.rxMbIo } From e73ea777aa82bc1d3dd07572e824f528c93b80a8 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 9 May 2024 12:52:22 -0700 Subject: [PATCH 091/106] update IO in UCI top --- src/main/scala/e2e/UCITop.scala | 23 +++++------------------ src/main/scala/tilelink/UCITLFront.scala | 6 ++++-- 2 files changed, 9 insertions(+), 20 deletions(-) diff --git a/src/main/scala/e2e/UCITop.scala b/src/main/scala/e2e/UCITop.scala index 881094c..22335fc 100644 --- a/src/main/scala/e2e/UCITop.scala +++ b/src/main/scala/e2e/UCITop.scala @@ -76,10 +76,6 @@ class UCITop( /** Sideband AFE connections (ser/des in logphy) */ - logPhy.io.mbAfe.txData <> dafe.io.mbAfeIo.rxData - logPhy.io.mbAfe.rxData <> dafe.io.mbAfeIo.txData - io.mbAfe_tx <> dafe.io.stdIo.tx.mainband - io.mbAfe_rx <> dafe.io.stdIo.rx.mainband io.sbTxIO.clk := logPhy.io.sbAfe.txClock io.sbTxIO.data := logPhy.io.sbAfe.txData logPhy.io.sbAfe.rxClock := io.sbRxIO.clk @@ -87,22 +83,13 @@ class UCITop( /** Mainband AFE connections to toplevel IOs */ + io.mbAfe_tx <> dafe.io.mbTxData + io.mbAfe_rx <> dafe.io.mbRxData /** Logphy connections to Digital AFE - * */ - dafe.io.sbAfeIo.fifoParams.clk := clock - dafe.io.sbAfeIo.rxData := 0.U - dafe.io.mbAfeIo.fifoParams.clk := clock - dafe.io.stdIo.rx.sideband.clk := clock - dafe.io.mbAfeIo.fifoParams.reset := false.B - logPhy.io.mbAfe.fifoParams.clk := clock - dafe.io.sbAfeIo.rxClock := false.B - logPhy.io.mbAfe.pllLock := true.B - dafe.io.mbAfeIo.pllLock := true.B - dafe.io.stdIo.rx.sideband.data := 0.U - dafe.io.sbAfeIo.pllLock := false.B - dafe.io.sbAfeIo.fifoParams.reset := false.B - logPhy.io.mbAfe.fifoParams.reset := false.B + */ + logPhy.io.mbAfe.txData <> dafe.io.mbAfeIo.rxData + logPhy.io.mbAfe.rxData <> dafe.io.mbAfeIo.txData /* Connect the protocol IOs to the top for connections to the tilelink * interface */ diff --git a/src/main/scala/tilelink/UCITLFront.scala b/src/main/scala/tilelink/UCITLFront.scala index b26241b..88f9b0a 100644 --- a/src/main/scala/tilelink/UCITLFront.scala +++ b/src/main/scala/tilelink/UCITLFront.scala @@ -70,7 +70,8 @@ class UCITLFrontImp extends Impl { //val mbAfe = new MainbandAfeIo(afeParams) val mbAfe_tx = Output(new MainbandIo(afeParams.mbLanes)) val mbAfe_rx = Input (new MainbandIo(afeParams.mbLanes)) - val sbAfe = new SidebandAfeIo(afeParams) + val sbTxIo = Output(new SidebandIo) + val sbRxIo = Input(new SidebandIo) }) withClockAndReset(clock, reset) { @@ -87,7 +88,8 @@ class UCITLFrontImp extends Impl { //io.mbAfe <> ucietop.io.mbAfe io.mbAfe_tx <> ucietop.io.mbAfe_tx io.mbAfe_rx <> ucietop.io.mbAfe_rx - io.sbAfe <> ucietop.io.sbAfe + io.sbTxIo <> ucietop.io.sbTxIO + io.sbRxIo <> ucietop.io.sbRxIO // Hamming encode and decode val hammingEncoder = Module(new HammingEncode(protoParams)) From 9ffc634ec54d0077d50ed534893bdb182b61ce70 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 9 May 2024 13:04:24 -0700 Subject: [PATCH 092/106] fix AFE loopback tests IOs --- src/test/scala/e2e/AfeLoopback.scala | 50 ++++++++---------------- src/test/scala/e2e/AfeLoopbackTest.scala | 4 +- 2 files changed, 19 insertions(+), 35 deletions(-) diff --git a/src/test/scala/e2e/AfeLoopback.scala b/src/test/scala/e2e/AfeLoopback.scala index ef01222..978d953 100644 --- a/src/test/scala/e2e/AfeLoopback.scala +++ b/src/test/scala/e2e/AfeLoopback.scala @@ -20,18 +20,20 @@ import protocol._ class AfeLoopback(val afeParams: AfeParams) extends Module { val io = IO(new Bundle { // val finished = Output(Bool()) - //val mbAfe = Flipped(new MainbandAfeIo(afeParams)) + // val mbAfe = Flipped(new MainbandAfeIo(afeParams)) val mbAfe_tx = Input(new MainbandIo(afeParams.mbLanes)) - val mbAfe_rx = Output (new MainbandIo(afeParams.mbLanes)) - val sbAfe = Flipped(new SidebandAfeIo(afeParams)) + val mbAfe_rx = Output(new MainbandIo(afeParams.mbLanes)) + val sbAfe_tx = Flipped(new SidebandIo) + val sbAfe_rx = Flipped(new SidebandIo) }) val latency = 2 - //val delayerMb = Module(new Pipe(chiselTypeOf(io.mbAfe.txData.bits), latency)) + /* val delayerMb = Module(new Pipe(chiselTypeOf(io.mbAfe.txData.bits), + * latency)) */ val delayerMbTx = Module(new Pipe(chiselTypeOf(io.mbAfe_tx.data), latency)) - val delayerSb = Module(new Pipe(chiselTypeOf(io.sbAfe.txData), latency)) + val delayerSb = Module(new Pipe(chiselTypeOf(io.sbAfe_tx.data), latency)) val delayerSb_clock = Module( - new Pipe(chiselTypeOf(io.sbAfe.txClock), latency), + new Pipe(chiselTypeOf(io.sbAfe_tx.clk), latency), ) val delayerMbTx_clockn = Module( new Pipe(chiselTypeOf(io.mbAfe_tx.clkn.asBool), latency), @@ -39,7 +41,8 @@ class AfeLoopback(val afeParams: AfeParams) extends Module { val delayerMbTx_clockp = Module( new Pipe(chiselTypeOf(io.mbAfe_tx.clkp.asBool), latency), ) - + + /** TODO: ansa fix delayed signals -- not delayed */ delayerMbTx.io.enq.valid := io.mbAfe_tx.valid delayerMbTx.io.enq.bits := io.mbAfe_tx.data io.mbAfe_rx.data := delayerMbTx.io.deq.bits @@ -48,43 +51,22 @@ class AfeLoopback(val afeParams: AfeParams) extends Module { delayerMbTx_clockn.io.enq.bits := io.mbAfe_tx.clkn.asBool delayerMbTx_clockp.io.enq.valid := true.B delayerMbTx_clockp.io.enq.bits := io.mbAfe_tx.clkp.asBool - // val delayNegEdgeMbClkN = withClock((!clock.asBool).asClock)(RegInit(false.B)) - // delayNegEdgeMbClkN := delayerMbTx_clockn.io.deq.bits && delayerMbTx_clockn.io.deq.valid - // io.mbAfe_rx.clkn := Mux( - // delayNegEdgeMbClkN.asBool, - // clock.asBool, - // false.asBool, - // ) + io.mbAfe_rx.clkn := io.mbAfe_tx.clkn - // val delayNegEdgeMbClkP = withClock((!clock.asBool).asClock)(RegInit(false.B)) - // delayNegEdgeMbClkP := delayerMbTx_clockp.io.deq.bits && delayerMbTx_clockp.io.deq.valid - // io.mbAfe_rx.clkp := Mux( - // delayNegEdgeMbClkP.asBool, - // clock.asBool, - // false.asBool, - // ) io.mbAfe_rx.clkp := io.mbAfe_tx.clkp - //io.mbAfe.txData.ready := true.B - //io.mbAfe.fifoParams.clk := clock - //io.mbAfe.fifoParams.reset := reset - //io.mbAfe.pllLock := true.B io.mbAfe_rx.track := false.B delayerSb.io.enq.valid := true.B // io.sbAfe.txData.valid - delayerSb.io.enq.bits := io.sbAfe.txData + delayerSb.io.enq.bits := io.sbAfe_tx.data delayerSb_clock.io.enq.valid := true.B - delayerSb_clock.io.enq.bits := io.sbAfe.txClock + delayerSb_clock.io.enq.bits := io.sbAfe_tx.clk - io.sbAfe.rxData := delayerSb.io.deq.bits - // io.sbAfe.rxData.valid := delayerSb.io.deq.valid + io.sbAfe_rx.data := delayerSb.io.deq.bits val delayNegEdge = withClock((!clock.asBool).asClock)(RegInit(false.B)) - delayNegEdge := delayerSb_clock.io.deq.bits && delayerSb_clock.io.deq.valid - io.sbAfe.rxClock := Mux( + delayNegEdge := delayerSb_clock.io.deq.bits.asBool && delayerSb_clock.io.deq.valid + io.sbAfe_rx.clk := Mux( delayNegEdge, clock.asBool, false.asBool, ) - io.sbAfe.fifoParams.clk := clock - io.sbAfe.fifoParams.reset := reset - io.sbAfe.pllLock := true.B } diff --git a/src/test/scala/e2e/AfeLoopbackTest.scala b/src/test/scala/e2e/AfeLoopbackTest.scala index d221d88..40667fb 100644 --- a/src/test/scala/e2e/AfeLoopbackTest.scala +++ b/src/test/scala/e2e/AfeLoopbackTest.scala @@ -85,7 +85,9 @@ class AfeLoopbackTester(implicit p: Parameters) extends LazyModule { // tlUcieDie1.module.io.mbAfe <> AfeLoopback.io.mbAfe tlUcieDie1.module.io.mbAfe_tx <> AfeLoopback.io.mbAfe_tx tlUcieDie1.module.io.mbAfe_rx <> AfeLoopback.io.mbAfe_rx - tlUcieDie1.module.io.sbAfe <> AfeLoopback.io.sbAfe + tlUcieDie1.module.io.sbTxIo <> AfeLoopback.io.sbAfe_tx + tlUcieDie1.module.io.sbRxIo <> AfeLoopback.io.sbAfe_rx + } } From 4eb2cf5807f3407bdfa7e5e4bfbd6fbde35d90cc Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 9 May 2024 13:09:41 -0700 Subject: [PATCH 093/106] update reset type --- src/main/scala/interfaces/Afe.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/interfaces/Afe.scala b/src/main/scala/interfaces/Afe.scala index 88b62ce..4d1d993 100644 --- a/src/main/scala/interfaces/Afe.scala +++ b/src/main/scala/interfaces/Afe.scala @@ -6,7 +6,7 @@ import chisel3.util._ class FifoParams extends Bundle { val clk = Clock() - val reset = Bool() + val reset = AsyncReset() } /** The mainband pins exposed by a standard package UCIe module in one From 8cd052d5781f2904e114a5a6bcec496566e293ca Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 9 May 2024 13:11:26 -0700 Subject: [PATCH 094/106] update reset type --- src/main/scala/interfaces/Afe.scala | 2 +- src/main/scala/mbafe/MbAfe.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/interfaces/Afe.scala b/src/main/scala/interfaces/Afe.scala index 4d1d993..88b62ce 100644 --- a/src/main/scala/interfaces/Afe.scala +++ b/src/main/scala/interfaces/Afe.scala @@ -6,7 +6,7 @@ import chisel3.util._ class FifoParams extends Bundle { val clk = Clock() - val reset = AsyncReset() + val reset = Bool() } /** The mainband pins exposed by a standard package UCIe module in one diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala index 0866992..9a06521 100644 --- a/src/main/scala/mbafe/MbAfe.scala +++ b/src/main/scala/mbafe/MbAfe.scala @@ -96,7 +96,7 @@ class MbAfe(afeParams: AfeParams) extends Module { /** Connect to LogPhy AFE IO */ io.mbAfeIo.fifoParams.clk := io.mbRxData.clkp - io.mbAfeIo.fifoParams.reset := reset.asAsyncReset + io.mbAfeIo.fifoParams.reset := reset.asBool io.mbAfeIo.txData <> txMainband.io.txInData io.mbAfeIo.rxData <> rxMainband.io.rxOutData From 9f045e084b41cfd4437b2d4ff7e52e7a04aea1f1 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 9 May 2024 13:13:37 -0700 Subject: [PATCH 095/106] convert clock types --- src/main/scala/e2e/UCITop.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/e2e/UCITop.scala b/src/main/scala/e2e/UCITop.scala index 22335fc..943f8ba 100644 --- a/src/main/scala/e2e/UCITop.scala +++ b/src/main/scala/e2e/UCITop.scala @@ -76,9 +76,9 @@ class UCITop( /** Sideband AFE connections (ser/des in logphy) */ - io.sbTxIO.clk := logPhy.io.sbAfe.txClock + io.sbTxIO.clk := logPhy.io.sbAfe.txClock.asClock io.sbTxIO.data := logPhy.io.sbAfe.txData - logPhy.io.sbAfe.rxClock := io.sbRxIO.clk + logPhy.io.sbAfe.rxClock := io.sbRxIO.clk.asBool logPhy.io.sbAfe.rxData := io.sbRxIO.data /** Mainband AFE connections to toplevel IOs From a4f86a5e014122de84282c8caae5ff62d04317df Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 9 May 2024 13:15:04 -0700 Subject: [PATCH 096/106] connect tx signals correctly --- src/main/scala/e2e/UCITop.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/e2e/UCITop.scala b/src/main/scala/e2e/UCITop.scala index 943f8ba..ef4e0d2 100644 --- a/src/main/scala/e2e/UCITop.scala +++ b/src/main/scala/e2e/UCITop.scala @@ -88,8 +88,8 @@ class UCITop( /** Logphy connections to Digital AFE */ - logPhy.io.mbAfe.txData <> dafe.io.mbAfeIo.rxData - logPhy.io.mbAfe.rxData <> dafe.io.mbAfeIo.txData + logPhy.io.mbAfe.txData <> dafe.io.mbAfeIo.txData + logPhy.io.mbAfe.rxData <> dafe.io.mbAfeIo.rxData /* Connect the protocol IOs to the top for connections to the tilelink * interface */ From b37831528aa699386f2adf59148537bc5bf24e39 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 9 May 2024 13:19:38 -0700 Subject: [PATCH 097/106] loopback afe IO directions --- src/test/scala/e2e/AfeLoopback.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/test/scala/e2e/AfeLoopback.scala b/src/test/scala/e2e/AfeLoopback.scala index 978d953..db40cf7 100644 --- a/src/test/scala/e2e/AfeLoopback.scala +++ b/src/test/scala/e2e/AfeLoopback.scala @@ -23,8 +23,8 @@ class AfeLoopback(val afeParams: AfeParams) extends Module { // val mbAfe = Flipped(new MainbandAfeIo(afeParams)) val mbAfe_tx = Input(new MainbandIo(afeParams.mbLanes)) val mbAfe_rx = Output(new MainbandIo(afeParams.mbLanes)) - val sbAfe_tx = Flipped(new SidebandIo) - val sbAfe_rx = Flipped(new SidebandIo) + val sbAfe_tx = Input(new SidebandIo) + val sbAfe_rx = Output(new SidebandIo) }) val latency = 2 From e2fae7de289be5b92d56bbb6af4de5d22fb42def Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 9 May 2024 13:21:10 -0700 Subject: [PATCH 098/106] bool to clock --- src/test/scala/e2e/AfeLoopback.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/test/scala/e2e/AfeLoopback.scala b/src/test/scala/e2e/AfeLoopback.scala index db40cf7..d1f2b44 100644 --- a/src/test/scala/e2e/AfeLoopback.scala +++ b/src/test/scala/e2e/AfeLoopback.scala @@ -67,6 +67,6 @@ class AfeLoopback(val afeParams: AfeParams) extends Module { io.sbAfe_rx.clk := Mux( delayNegEdge, clock.asBool, - false.asBool, - ) + false.B, + ).asClock } From 40771af8b5be5ee5010d690ff584f93b5cf281de Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 9 May 2024 13:25:23 -0700 Subject: [PATCH 099/106] connect full logphy AFE --- src/main/scala/e2e/UCITop.scala | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/main/scala/e2e/UCITop.scala b/src/main/scala/e2e/UCITop.scala index ef4e0d2..deb05e2 100644 --- a/src/main/scala/e2e/UCITop.scala +++ b/src/main/scala/e2e/UCITop.scala @@ -88,8 +88,7 @@ class UCITop( /** Logphy connections to Digital AFE */ - logPhy.io.mbAfe.txData <> dafe.io.mbAfeIo.txData - logPhy.io.mbAfe.rxData <> dafe.io.mbAfeIo.rxData + logPhy.io.mbAfe <> dafe.io.mbAfeIo /* Connect the protocol IOs to the top for connections to the tilelink * interface */ From 12bf86338da0f1415648fc82853ad3867b6a3002 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 9 May 2024 13:29:24 -0700 Subject: [PATCH 100/106] initialize pll lock --- src/main/scala/mbafe/MbAfe.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/mbafe/MbAfe.scala b/src/main/scala/mbafe/MbAfe.scala index 9a06521..441ba05 100644 --- a/src/main/scala/mbafe/MbAfe.scala +++ b/src/main/scala/mbafe/MbAfe.scala @@ -99,6 +99,7 @@ class MbAfe(afeParams: AfeParams) extends Module { io.mbAfeIo.fifoParams.reset := reset.asBool io.mbAfeIo.txData <> txMainband.io.txInData io.mbAfeIo.rxData <> rxMainband.io.rxOutData + io.mbAfeIo.pllLock := true.B /** Connect to Mainband IO */ io.mbTxData <> txMainband.io.txMbIo From 3a8eb93ca8e97b99cd2c2bc517da7556f50db964 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 9 May 2024 13:31:40 -0700 Subject: [PATCH 101/106] remove fifoparams from sb afe --- src/main/scala/interfaces/Afe.scala | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/main/scala/interfaces/Afe.scala b/src/main/scala/interfaces/Afe.scala index 88b62ce..d29e347 100644 --- a/src/main/scala/interfaces/Afe.scala +++ b/src/main/scala/interfaces/Afe.scala @@ -62,8 +62,6 @@ class SidebandAfeIo( afeParams: AfeParams, ) extends Bundle { - val fifoParams = Input(new FifoParams()) - /** Data to transmit on the sideband. * * Output from the async FIFO. From 23147759e45a9ad09b12ee55f8330c79328c2b50 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 9 May 2024 13:33:14 -0700 Subject: [PATCH 102/106] lock PLL --- src/main/scala/e2e/UCITop.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/e2e/UCITop.scala b/src/main/scala/e2e/UCITop.scala index deb05e2..0d7e5bf 100644 --- a/src/main/scala/e2e/UCITop.scala +++ b/src/main/scala/e2e/UCITop.scala @@ -78,6 +78,7 @@ class UCITop( */ io.sbTxIO.clk := logPhy.io.sbAfe.txClock.asClock io.sbTxIO.data := logPhy.io.sbAfe.txData + logPhy.io.sbAfe.pllLock := true.B logPhy.io.sbAfe.rxClock := io.sbRxIO.clk.asBool logPhy.io.sbAfe.rxData := io.sbRxIO.data From b4c16ba3bd2c5563bf5f0068c217dcde2b417938 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 9 May 2024 13:35:17 -0700 Subject: [PATCH 103/106] get rid of clock mux --- src/main/scala/interfaces/Afe.scala | 2 +- src/test/scala/e2e/AfeLoopback.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/interfaces/Afe.scala b/src/main/scala/interfaces/Afe.scala index d29e347..e5e3b64 100644 --- a/src/main/scala/interfaces/Afe.scala +++ b/src/main/scala/interfaces/Afe.scala @@ -25,7 +25,7 @@ class MainbandIo(lanes: Int = 16) extends Bundle { */ class SidebandIo extends Bundle { val data = Bool() - val clk = Clock() + val clk = Bool() } /** The pins (mainband and sideband) exposed by a standard package UCIe module diff --git a/src/test/scala/e2e/AfeLoopback.scala b/src/test/scala/e2e/AfeLoopback.scala index d1f2b44..4ca591e 100644 --- a/src/test/scala/e2e/AfeLoopback.scala +++ b/src/test/scala/e2e/AfeLoopback.scala @@ -68,5 +68,5 @@ class AfeLoopback(val afeParams: AfeParams) extends Module { delayNegEdge, clock.asBool, false.B, - ).asClock + ) } From 95faa61eef99870af061c72e15337af749488cf4 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Thu, 9 May 2024 13:36:48 -0700 Subject: [PATCH 104/106] get rid of clock mux --- src/main/scala/e2e/UCITop.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/e2e/UCITop.scala b/src/main/scala/e2e/UCITop.scala index 0d7e5bf..6f4245b 100644 --- a/src/main/scala/e2e/UCITop.scala +++ b/src/main/scala/e2e/UCITop.scala @@ -76,10 +76,10 @@ class UCITop( /** Sideband AFE connections (ser/des in logphy) */ - io.sbTxIO.clk := logPhy.io.sbAfe.txClock.asClock + io.sbTxIO.clk := logPhy.io.sbAfe.txClock io.sbTxIO.data := logPhy.io.sbAfe.txData logPhy.io.sbAfe.pllLock := true.B - logPhy.io.sbAfe.rxClock := io.sbRxIO.clk.asBool + logPhy.io.sbAfe.rxClock := io.sbRxIO.clk logPhy.io.sbAfe.rxData := io.sbRxIO.data /** Mainband AFE connections to toplevel IOs From db8a7c2451d439059f6e8163f7e83a7b1d94b9f2 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 10 May 2024 11:45:56 -0700 Subject: [PATCH 105/106] only resent msg in init --- src/main/scala/logphy/LinkTrainingFSM.scala | 8 +++----- src/main/scala/logphy/LogPhyTypes.scala | 2 +- src/main/scala/logphy/MBInitFSM.scala | 1 + src/main/scala/logphy/RdiBringup.scala | 1 + src/main/scala/logphy/SBMsgWrapper.scala | 16 +++------------- 5 files changed, 9 insertions(+), 19 deletions(-) diff --git a/src/main/scala/logphy/LinkTrainingFSM.scala b/src/main/scala/logphy/LinkTrainingFSM.scala index 9fdd038..09f6d7d 100644 --- a/src/main/scala/logphy/LinkTrainingFSM.scala +++ b/src/main/scala/logphy/LinkTrainingFSM.scala @@ -277,6 +277,7 @@ class LinkTrainingFSM( true, "PHY", ) + sbMsgWrapper.io.trainIO.msgReq.bits.repeat := true.B /* sbMsgWrapper.io.trainIO.msgReq.bits.reqType := * MessageRequestType.MSG_EXCH */ // sbMsgWrapper.io.trainIO.msgReq.bits.msgTypeHasData := false.B @@ -311,9 +312,7 @@ class LinkTrainingFSM( true, "PHY", ) - /* sbMsgWrapper.io.trainIO.msgReq.bits.reqType := - * MessageRequestType.MSG_REQ */ - // sbMsgWrapper.io.trainIO.msgReq.bits.msgTypeHasData := false.B + sbMsgWrapper.io.trainIO.msgReq.bits.repeat := false.B sbMsgWrapper.io.trainIO.msgReq.valid := true.B sbMsgWrapper.io.trainIO.msgReq.bits.timeoutCycles := ( 0.008 * sbClockFreq, @@ -344,8 +343,7 @@ class LinkTrainingFSM( remote = true, "PHY", ) - /* sbMsgWrapper.io.trainIO.msgReq.bits.reqType := - * MessageRequestType.MSG_RESP */ + sbMsgWrapper.io.trainIO.msgReq.bits.repeat := false.B sbMsgWrapper.io.trainIO.msgReq.valid := true.B // sbMsgWrapper.io.trainIO.msgReq.bits.msgTypeHasData := false.B msgSource := MsgSource.SB_MSG_WRAPPER diff --git a/src/main/scala/logphy/LogPhyTypes.scala b/src/main/scala/logphy/LogPhyTypes.scala index 0cc764c..3ac9e3b 100644 --- a/src/main/scala/logphy/LogPhyTypes.scala +++ b/src/main/scala/logphy/LogPhyTypes.scala @@ -31,7 +31,7 @@ class SBReqMsg extends Bundle { class MessageRequest extends Bundle { val msg = UInt(128.W) val timeoutCycles = UInt(64.W) - // val msgTypeHasData = Bool() + val repeat = Bool() } class MessageRequestStatus extends Bundle { diff --git a/src/main/scala/logphy/MBInitFSM.scala b/src/main/scala/logphy/MBInitFSM.scala index 1b88d61..16b8c6d 100644 --- a/src/main/scala/logphy/MBInitFSM.scala +++ b/src/main/scala/logphy/MBInitFSM.scala @@ -52,6 +52,7 @@ class MBInitFSM( state := nextState io.sbTrainIO.msgReq.noenq() + io.sbTrainIO.msgReq.bits.repeat := false.B io.sbTrainIO.msgReqStatus.nodeq() io.patternGeneratorIO.transmitReq.noenq() io.patternGeneratorIO.transmitPatternStatus.nodeq() diff --git a/src/main/scala/logphy/RdiBringup.scala b/src/main/scala/logphy/RdiBringup.scala index e25acda..3854389 100644 --- a/src/main/scala/logphy/RdiBringup.scala +++ b/src/main/scala/logphy/RdiBringup.scala @@ -52,6 +52,7 @@ class RdiBringup extends Module { private val nextState = WireInit(state) io.active := state === PhyState.active io.sbTrainIO.msgReq.noenq() + io.sbTrainIO.msgReq.bits.repeat := false.B io.sbTrainIO.msgReqStatus.nodeq() state := nextState when(io.internalError || io.rdiIO.lpLinkError) { diff --git a/src/main/scala/logphy/SBMsgWrapper.scala b/src/main/scala/logphy/SBMsgWrapper.scala index 79a6bbe..e18039a 100644 --- a/src/main/scala/logphy/SBMsgWrapper.scala +++ b/src/main/scala/logphy/SBMsgWrapper.scala @@ -48,6 +48,7 @@ class SBMsgWrapper( // private val currentReqHasData = RegInit(false.B) private val currentReqTimeoutMax = RegInit(0.U(64.W)) private val currentStatus = RegInit(MessageRequestStatusType.ERR) + private val repeat = RegInit(false.B) private val dataOut = RegInit(0.U(64.W)) io.trainIO.msgReqStatus.bits.data := dataOut @@ -62,20 +63,9 @@ class SBMsgWrapper( io.trainIO.msgReq.ready := true.B when(io.trainIO.msgReq.fire) { currentReq := io.trainIO.msgReq.bits.msg - // currentReqHasData := io.trainIO.msgReq.bits.msgTypeHasData currentReqTimeoutMax := io.trainIO.msgReq.bits.timeoutCycles + repeat := io.trainIO.msgReq.bits.repeat nextState := State.EXCHANGE - // switch(io.trainIO.msgReq.bits.reqType) { - // is(MessageRequestType.MSG_REQ) { - // nextState := State.EXCHANGE - // } - // is(MessageRequestType.MSG_RESP) { - // nextState := State.EXCHANGE - // } - // is(MessageRequestType.MSG_EXCH) { - // nextState := State.EXCHANGE - // } - // } } } is(State.EXCHANGE) { @@ -95,7 +85,7 @@ class SBMsgWrapper( } /** send message over sideband */ - io.laneIO.txData.valid := true.B + io.laneIO.txData.valid := !sentMsg || repeat io.laneIO.txData.bits := currentReq val hasSentMsg = WireInit(io.laneIO.txData.fire || sentMsg) val justReceivedMsg = Wire(Bool()) From 558c184042f924a5ffed65612cf731281eb2b313 Mon Sep 17 00:00:00 2001 From: Viansa Schmulbach Date: Fri, 10 May 2024 11:48:04 -0700 Subject: [PATCH 106/106] only resent msg in init --- src/main/scala/logphy/MBInitFSM.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/logphy/MBInitFSM.scala b/src/main/scala/logphy/MBInitFSM.scala index 16b8c6d..8d28601 100644 --- a/src/main/scala/logphy/MBInitFSM.scala +++ b/src/main/scala/logphy/MBInitFSM.scala @@ -52,7 +52,6 @@ class MBInitFSM( state := nextState io.sbTrainIO.msgReq.noenq() - io.sbTrainIO.msgReq.bits.repeat := false.B io.sbTrainIO.msgReqStatus.nodeq() io.patternGeneratorIO.transmitReq.noenq() io.patternGeneratorIO.transmitPatternStatus.nodeq() @@ -114,6 +113,7 @@ class MBInitFSM( "PHY", data, ) + msgReq.repeat := false.B // msgReq.msgTypeHasData := true.B msgReq.timeoutCycles := (0.008 * sbClockFreq).toInt.U