Interleaved memory

[hphphphp3]

I have a research on memory, and need a interleaved memory system that can access more than one request simultaneous if there is no bank conflict. I have noticed in DRAMsim2, it will go through the command queue to find the command which accesses the idle bank and issue it every cycle. Is this the real behavior in interleaved memory system? Thanks.

[dramninjasUMD]

I believe so -- this is just an implementation of a First Ready First Come First Serve scheduling policy where ready requests are pushed ahead of stalled requests if there are no dependencies. This seems to me to be consistent with the behavior you describe in the first part of your question. What do you think the proper behavior should be?

[hphphphp3]

Thanks for reply.
There are many different ways that can use single-port memory to form dual-port by interleaved memory banks. So is it possible that "issue" more than one request to different banks at the same time?

[mal0415]

How does the DRAMSim2 realize the FR-FCFS in source code? Is it in CommandQueue.cpp?