Does DRAMsim2 use watermark to select between read and write?

[allencho1222]

It seems that DRAMsim2 does not use watermark values to switch request queue or command queue between read and write.

This is commonly known issues in scheduling requests to remove overheads from READ to WRITE latency or WRITE to READ latency.

Is there any specific reasons to ignore this problem in DRAMsim2?