SystemVerilog reports 'type' rather than port name

[t0mj0nes]

The name of the parser:

SystemVerilog

The command line you used to run ctags:

$ ctags --language-force=SystemVerilog *.sv

The content of input files:

pack.sv:
package PACK;
    localparam N = 100;
    typedef logic [N-1:0] PORT_TYPE_T;
endpackage // PACK

port.sv:
import PACK::*;

module port (
    input  PORT_TYPE_T  port,
    input  PORT_TYPE_T  port2);
endmodule // port

The tags output you are not satisfied with:

// lines 13 & 14 report the type (PORT_TYPE_T), not the port name (porta, portb):
13 PORT_TYPE_T port.sv /^    input  PORT_TYPE_T  porta,$/;" p   module:port
14 PORT_TYPE_T port.sv /^    input  PORT_TYPE_T  portb);$/;"   p   module:port...

The tags output you expect:

13 porta port.sv /^    input  PORT_TYPE_T  porta,$/;" p   module:port
14 portb port.sv /^    input  PORT_TYPE_T  portb);$/;"   p   module:port...

The version of ctags:

$ ctags --version
Universal Ctags 0.0.0, Copyright (C) 2015 Universal Ctags Team
Universal Ctags is derived from Exuberant Ctags.
Exuberant Ctags 5.8, Copyright (C) 1996-2009 Darren Hiebert
  Compiled: Jun 15 2020, 20:00:21
  URL: https://ctags.io/
  Optional compiled features: +wildcards, +regex, +iconv, +option-directory, +packcc

How do you get ctags binary:

(
a) Building it locally, via GNU/Linux distribution, as BSD's package,
b) win32 binary taken from Universal-ctags/ctags-win32 project
a) and b) - fails same
)

Here's another wrinkle: When I concatenate both pack.sv and port.sv into a single-file it works correctly!
pack.sv.txt
port.sv.txt

[masatake]

Thank you for reporting.
The limitation behind the SystemVerilog parser causes the unsatisfied result was already reported and discussed in #2413. Rewriting the parser is needed.

[masatake]

Watch #2413.

[masatake]

You can help the development with your knowledge about SystemVerilog.
See #2494.

[t0mj0nes]

I don't feel qualified based on #2494. So there is currently no dedicated SystemVerilog parser owner? There will be a lot of adoption when it is more reliable. It's already much better than the Exuberant + hacks.

[masatake]

So there is currently no dedicated SystemVerilog parser owner?

Yes. We have no active maintainer for the parser other than I (but not dedicated).
My knowledge about the target language is very limited; I bought a book a month ago.