From ce35b793efa6f69f7079c3ee4ebe24d640aadf49 Mon Sep 17 00:00:00 2001
From: Vincent Ollivier <v@vinc.cc>
Date: Mon, 21 Oct 2024 11:34:59 +0200
Subject: [PATCH] Refactor sync functions

---
 src/sys/ata.rs                    |  4 ++--
 src/sys/clk/mod.rs                |  4 ++--
 src/sys/clk/{sleep.rs => sync.rs} | 16 +++++++++++++---
 src/sys/clk/timer.rs              |  4 ++--
 src/sys/net/nic/e1000.rs          |  2 +-
 5 files changed, 20 insertions(+), 10 deletions(-)
 rename src/sys/clk/{sleep.rs => sync.rs} (51%)

diff --git a/src/sys/ata.rs b/src/sys/ata.rs
index 56d4fb5f..ac4e4443 100644
--- a/src/sys/ata.rs
+++ b/src/sys/ata.rs
@@ -100,7 +100,7 @@ impl Bus {
     }
 
     fn wait(&mut self, ns: u64) {
-        sys::clk::nanowait(ns);
+        sys::clk::wait(ns);
     }
 
     fn clear_interrupt(&mut self) -> u8 {
@@ -164,7 +164,7 @@ impl Bus {
             // Bit 7 => 1
             self.drive_register.write(0xA0 | (drive << 4))
         }
-        sys::clk::nanowait(400); // Wait at least 400 ns
+        sys::clk::wait(400); // Wait at least 400 ns
         self.poll(Status::BSY, false)?;
         self.poll(Status::DRQ, false)?;
         Ok(())
diff --git a/src/sys/clk/mod.rs b/src/sys/clk/mod.rs
index 8993d681..47c5f320 100644
--- a/src/sys/clk/mod.rs
+++ b/src/sys/clk/mod.rs
@@ -2,13 +2,13 @@ mod cmos;
 mod boot;
 mod epoch;
 mod rtc;
-mod sleep;
+mod sync;
 mod timer;
 
 pub use boot::{boot_time, BootTime};
 pub use epoch::{epoch_time, EpochTime};
 pub use rtc::RTC;
-pub use sleep::{sleep, nanowait, halt};
+pub use sync::{halt, sleep, wait};
 pub use timer::{ticks, pit_frequency, set_pit_frequency};
 
 use crate::api;
diff --git a/src/sys/clk/sleep.rs b/src/sys/clk/sync.rs
similarity index 51%
rename from src/sys/clk/sleep.rs
rename to src/sys/clk/sync.rs
index f76af0e2..ed006f2b 100644
--- a/src/sys/clk/sleep.rs
+++ b/src/sys/clk/sync.rs
@@ -3,6 +3,9 @@ use super::timer;
 
 use x86_64::instructions::interrupts;
 
+/// Halts the CPU until the next interrupt.
+///
+/// This function preserves interrupt state.
 pub fn halt() {
     let disabled = !interrupts::are_enabled();
     interrupts::enable_and_hlt();
@@ -11,6 +14,10 @@ pub fn halt() {
     }
 }
 
+/// Sleeps for the specified number of seconds.
+///
+/// This function works by repeatedly halting the CPU until the time is
+/// elapsed.
 pub fn sleep(seconds: f64) {
     let start = boot::boot_time();
     while boot::boot_time() - start < seconds {
@@ -18,10 +25,13 @@ pub fn sleep(seconds: f64) {
     }
 }
 
-pub fn nanowait(nanoseconds: u64) {
+/// Waits for the specified number of nanoseconds.
+///
+/// This function use a busy-wait loop with the `RDTSC` and `PAUSE`
+/// instructions.
+pub fn wait(nanoseconds: u64) {
+    let delta = nanoseconds * timer::tsc_frequency();
     let start = timer::tsc();
-    let freq = timer::tsc_frequency();
-    let delta = nanoseconds * freq;
     while timer::tsc() - start < delta {
         core::hint::spin_loop();
     }
diff --git a/src/sys/clk/timer.rs b/src/sys/clk/timer.rs
index 6db40185..5381cb3a 100644
--- a/src/sys/clk/timer.rs
+++ b/src/sys/clk/timer.rs
@@ -1,4 +1,4 @@
-use super::sleep;
+use super::sync;
 use super::cmos::CMOS;
 
 use crate::sys;
@@ -86,7 +86,7 @@ pub fn init() {
     // TSC timmer
     let calibration_time = 250_000; // 0.25 seconds
     let a = tsc();
-    sleep::sleep(calibration_time as f64 / 1e6);
+    sync::sleep(calibration_time as f64 / 1e6);
     let b = tsc();
     TSC_FREQUENCY.store((b - a) / calibration_time, Ordering::Relaxed);
 }
diff --git a/src/sys/net/nic/e1000.rs b/src/sys/net/nic/e1000.rs
index 5ca856e3..83a27e31 100644
--- a/src/sys/net/nic/e1000.rs
+++ b/src/sys/net/nic/e1000.rs
@@ -168,7 +168,7 @@ impl Device {
         // Reset device
         let ctrl = self.read(REG_CTRL);
         self.write(REG_CTRL, ctrl | CTRL_RST); // Reset
-        sys::clk::nanowait(500); // TODO: How long should we wait?
+        sys::clk::wait(500); // TODO: How long should we wait?
 
         // Disable interrupts again
         self.write(REG_IMC, 0xFFFF);