MIR has been ported to **RISCV** #188
vnmakarov
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MIR now supports RISCV (including MIR generator). Minimal requirement of MIR for RISCV CPU is
If RISCV supports C standard (compressed insns), MIR-generator will generate them too. It is important for better generated code size and performance.
There is still a room for RISCV generated code improvements but basically RISCV MIR generator already emits a decent code.
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