Question about porting process.

[TehLeo]

Hi, I've got a question about the porting process.
Is this process manual or are you using llvm to help generate some of the data.
If not would it be possible to use llvm/target info to generate new ports?
Eg.: automatically fill in registers data/instructions etc.

[vnmakarov]

The process is manual. The process is described in https://github.com/vnmakarov/mir/blob/master/HOW-TO-PORT-MIR.md. MIR target data format is very different from LLVM or GCC. I think automatic generation of MIR target from LLVM (or GCC) is impossible in practice. If it were possible, missed LLVM targets could be automatically generated from GCC which supports more targets.

I also don't see how llvm target data can helps me. I use target architecture and ABI manuals and in case of questions I look at GCC target descriptions as I am a GCC developer.