VX_config.toml

# Each `VX_CFG_X_ENABLE` boolean auto-generates its integer mirror `VX_CFG_X_ENABLED` (0/1); author only the boolean.

[platform]
VX_CFG_NUM_CLUSTERS = 1
VX_CFG_NUM_CORES = 1
VX_CFG_SOCKET_SIZE = 1

VX_CFG_RESET_DELAY = 8

# lowercase = private helper, not emitted as a VX_CFG_ macro
dpi_is_enabled = "expr: $SV_DPI"

VX_CFG_ICACHE_ENABLE = true
VX_CFG_DCACHE_ENABLE = true
VX_CFG_LMEM_ENABLE = true
VX_CFG_L2_ENABLE = false
VX_CFG_L3_ENABLE = false


[isa]

VX_CFG_VM_ENABLE = false

VX_CFG_EXT_D_ENABLE = "expr: $VX_CFG_XLEN_64"
VX_CFG_FLEN = "expr: 64 if $VX_CFG_EXT_D_ENABLE else 32"

VX_CFG_EXT_M_ENABLE = true
VX_CFG_EXT_F_ENABLE = true
VX_CFG_EXT_C_ENABLE = false
VX_CFG_EXT_A_ENABLE = false
# Zacas: native compare-and-swap (amocas). Requires the A extension -- it adds
# an atomic, it does not replace the set. Off by default because it widens the
# memory request with a comparand operand.
VX_CFG_EXT_ZACAS_ENABLE = false

VX_CFG_EXT_ZICOND_ENABLE = true
VX_CFG_EXT_TCU_ENABLE = false
VX_CFG_EXT_DMA_ENABLE = false
VX_CFG_EXT_DXA_ENABLE = false
VX_CFG_EXT_TEX_ENABLE = false
VX_CFG_EXT_RASTER_ENABLE = false
VX_CFG_EXT_OM_ENABLE = false
VX_CFG_EXT_RTU_ENABLE = false
VX_CFG_VLEN = "expr: $VX_CFG_XLEN * 4"

[pipeline]
VX_CFG_NUM_WARPS = 4
VX_CFG_NUM_THREADS = 4
VX_CFG_NUM_BARRIERS = 8
VX_CFG_MAX_BAR_EVENTS = 32

VX_CFG_IBUF_SIZE = 4
VX_CFG_DISPATCH_QUEUE_SIZE = 4
VX_CFG_ISSUE_WIDTH = "expr: up($VX_CFG_NUM_WARPS / 16)"
VX_CFG_SIMD_WIDTH = "expr: $VX_CFG_NUM_THREADS"
VX_CFG_NUM_OPCS = "expr: up($VX_CFG_NUM_WARPS / (4 * $VX_CFG_ISSUE_WIDTH))"

VX_CFG_NUM_GPR_BANKS = 4
VX_CFG_NUM_VGPR_BANKS = 2

[memory]
VX_CFG_MEM_BLOCK_SIZE = 64
VX_CFG_MEM_ADDR_WIDTH = "expr: 48 if $VX_CFG_XLEN_64 else 32"

# L1 block = memory bus (MEM_BLOCK), shared by icache/dcache/gfx + L2 input word.
# L2/L3 are sectored: a doubled line halves tags while the sector (= MEM_BLOCK)
# stays the fill/transaction granule. When a level is disabled it is a passthrough
# and forwards the upstream granule unchanged.
VX_CFG_L1_LINE_SIZE   = "expr: $VX_CFG_MEM_BLOCK_SIZE"
VX_CFG_L2_LINE_SIZE   = "expr: (2 * $VX_CFG_MEM_BLOCK_SIZE) if $VX_CFG_L2_ENABLE else $VX_CFG_L1_LINE_SIZE"
VX_CFG_L2_SECTOR_SIZE = "expr: $VX_CFG_MEM_BLOCK_SIZE if $VX_CFG_L2_ENABLE else $VX_CFG_L1_LINE_SIZE"
VX_CFG_L3_LINE_SIZE   = "expr: (2 * $VX_CFG_MEM_BLOCK_SIZE) if $VX_CFG_L3_ENABLE else $VX_CFG_L2_SECTOR_SIZE"
VX_CFG_L3_SECTOR_SIZE = "expr: $VX_CFG_MEM_BLOCK_SIZE if $VX_CFG_L3_ENABLE else $VX_CFG_L2_SECTOR_SIZE"

[platform_memory]
VX_CFG_PLATFORM_MEMORY_NUM_BANKS = 2
VX_CFG_PLATFORM_MEMORY_ADDR_WIDTH = "expr: 48 if $VX_CFG_XLEN_64 else 32"
VX_CFG_PLATFORM_MEMORY_DATA_SIZE = 64
VX_CFG_PLATFORM_MEMORY_INTERLEAVE = 1
VX_CFG_PLATFORM_MEMORY_PEAK_BW = 460000 # 460 GB/s
VX_CFG_PLATFORM_CLOCK_RATE = 400

[alu]
VX_CFG_NUM_ALU_LANES = "expr: $VX_CFG_SIMD_WIDTH"
VX_CFG_NUM_ALU_BLOCKS = 1

[sfu]
VX_CFG_NUM_SFU_LANES = "expr: $VX_CFG_SIMD_WIDTH"
VX_CFG_NUM_SFU_BLOCKS = 1

[lsu]
VX_CFG_NUM_LSU_LANES = "expr: $VX_CFG_SIMD_WIDTH"
VX_CFG_NUM_LSU_BLOCKS = 1

VX_CFG_LSU_LINE_SIZE = "expr: min($VX_CFG_NUM_LSU_LANES * ($VX_CFG_XLEN / 8), $VX_CFG_L1_LINE_SIZE)"
VX_CFG_LSU_QUEUE_IN_SIZE = "expr: max(4, 2 * ($VX_CFG_SIMD_WIDTH // $VX_CFG_NUM_LSU_LANES))"
# Outstanding-load pool (MLP depth): decoupled from the input staging queue and
# provisioned for miss-latency hiding (~2 in-flight loads per warp), clamped so
# the slot id stays cheap in the dcache tag.
VX_CFG_LSU_PENDING_SIZE = "expr: min(32, max(8, 2 * $VX_CFG_NUM_WARPS * ($VX_CFG_SIMD_WIDTH // $VX_CFG_NUM_LSU_LANES)))"
# The mem-side queue depth is not a knob: it sets the dcache-facing tag-id
# width and must cover the outstanding pool, so each implementation derives
# it internally from the pool size.

[fpu]
# string enum: 'DPI'|'DSP'|'FPNEW'|'STD'; synth ASIC=>STD FPGA=>DSP, sim DPI/STD
VX_CFG_FPU_TYPE = "expr: ('STD' if $ASIC else 'DSP') if $SYNTHESIS else ('DPI' if $dpi_is_enabled else 'STD')"

VX_CFG_NUM_FPU_LANES = "expr: $VX_CFG_SIMD_WIDTH"
VX_CFG_NUM_FPU_BLOCKS = 1
VX_CFG_FPU_QUEUE_SIZE = "expr: 2 * ($VX_CFG_SIMD_WIDTH // $VX_CFG_NUM_FPU_LANES)"
# Map the soft FPU (STD) mantissa multipliers onto DSP48: on for FPGA synth, off
# for ASIC/sim (mirrors VX_CFG_TCU_USE_DSP). Single source of truth.
VX_CFG_FPU_USE_DSP = "expr: 1 if ($SYNTHESIS and not $ASIC) else 0"

fpu_dsp_quartus = "expr: $VX_CFG_FPU_TYPE_DSP and $QUARTUS"
fpu_dsp_vivado  = "expr: $VX_CFG_FPU_TYPE_DSP and $VIVADO"

# STD: FDIV_LATENCY must equal FSQRT_LATENCY (shared serializer in VX_fpu_std)
VX_CFG_FMA_LATENCY  = "expr: 16 if $fpu_dsp_vivado else (4 if $fpu_dsp_quartus else (12 if $VX_CFG_EXT_D_ENABLE else 8))"
VX_CFG_FDIV_LATENCY = "expr: 15 if $VX_CFG_FPU_TYPE_DPI else (16 if $VX_CFG_FPU_TYPE_FPNEW else ((32 if $VX_CFG_EXT_D_ENABLE else 17) if $VX_CFG_FPU_TYPE_STD else (15 if $fpu_dsp_quartus else (28 if $fpu_dsp_vivado else (32 if $VX_CFG_EXT_D_ENABLE else 17)))))"
VX_CFG_FSQRT_LATENCY= "expr: 10 if $VX_CFG_FPU_TYPE_DPI else (16 if $VX_CFG_FPU_TYPE_FPNEW else ((32 if $VX_CFG_EXT_D_ENABLE else 17) if $VX_CFG_FPU_TYPE_STD else (10 if $fpu_dsp_quartus else (28 if $fpu_dsp_vivado else (32 if $VX_CFG_EXT_D_ENABLE else 17)))))"
VX_CFG_FNCP_LATENCY = 2
VX_CFG_FCVT_LATENCY = 5

VX_CFG_FMA_PE_RATIO  = 1
VX_CFG_FDIV_PE_RATIO = 1
VX_CFG_FSQRT_PE_RATIO= 1
VX_CFG_FCVT_PE_RATIO = 1
VX_CFG_FNCP_PE_RATIO = 1

[amo]
# LR/SC reservation stations per LLC bank; line-indexed in BRAM, eviction yields legal spurious SC failures
VX_CFG_AMO_RS_SIZE = "expr: max($VX_CFG_NUM_WARPS, up($VX_CFG_NUM_CORES * $VX_CFG_NUM_WARPS / $VX_CFG_L2_NUM_BANKS))"

[vpu]
VX_CFG_NUM_VPU_LANES = "expr: $VX_CFG_SIMD_WIDTH"
VX_CFG_NUM_VPU_BLOCKS = 1

[vm]
# VM page-table format is a HW<->SW contract, moved to VX_types.toml [vm]; TLB depth stays here.
VX_CFG_TLB_SIZE = 32

# L1 TLB stage (per core): D-side / I-side entries and the per-instance
# miss station depth (distinct outstanding VPN misses).
VX_CFG_DTLB_SIZE        = 16
VX_CFG_ITLB_SIZE        = 8
VX_CFG_L1_TLB_MSHR_SIZE = 4

# Shared cluster TLB and page-table walker complex.
VX_CFG_L2_TLB_SIZE         = 512
VX_CFG_L2_TLB_NUM_WAYS     = 4
VX_CFG_L2_TLB_MEGA_SIZE    = 8
VX_CFG_L2_TLB_MSHR_SIZE    = 8
VX_CFG_L2_TLB_LATENCY      = 4
VX_CFG_PTW_NUM_WALKERS     = 2
VX_CFG_PTW_WALK_CACHE_SIZE = 16

VX_CFG_VM_PINNED_REGION_SIZE = 0x10000000   # 256 MB

[cache]
# Cache replacement-policy enums + LLC/topology helpers, consumed by the
# per-level cache sections below and by [amo].
__cache_repl_random = 0
__cache_repl_fifo   = 1
__cache_repl_plru   = 2

# Write-back only at a cache level that is BOTH the LLC AND the single coherence
# point for all cores. A private cache acting as the LLC across multiple
# cores/clusters has no shared coherence point, so its dirty data never becomes
# visible to the other cores and it must stay write-through (stores reach shared
# memory). The dcache is per-core and L2 is per-cluster, so each is a valid
# write-back LLC only when there is exactly one instance; L3 is always global.
l2_is_llc = "expr: $VX_CFG_L2_ENABLED == 1 and $VX_CFG_L3_ENABLED == 0"
dcache_is_llc = "expr: $VX_CFG_L2_ENABLED == 0 and $VX_CFG_L3_ENABLED == 0"
l3_is_llc = "expr: $VX_CFG_L3_ENABLED == 1"
single_core = "expr: $VX_CFG_NUM_CORES == 1 and $VX_CFG_NUM_CLUSTERS == 1"
single_cluster = "expr: $VX_CFG_NUM_CLUSTERS == 1"

[l1cache]
VX_CFG_ICACHE_SIZE = 16384
VX_CFG_ICACHE_NUM_WAYS = 4
VX_CFG_ICACHE_REPL_POLICY = "expr: $__cache_repl_fifo"
VX_CFG_ICACHE_MSHR_SIZE = 16
VX_CFG_ICACHE_MRSQ_SIZE = 0
# mem-request queue depth override; 0 = bank-derived minimum, raise to add slots
VX_CFG_ICACHE_MREQ_SIZE = 0
VX_CFG_ICACHE_CRSQ_SIZE = 0
VX_CFG_ICACHE_MEM_PORTS = 1
VX_CFG_ICACHE_LATENCY = "expr: 2 + max(0, clog2($VX_CFG_ICACHE_SIZE) - clog2(16384))"

VX_CFG_DCACHE_SIZE = 16384
VX_CFG_DCACHE_NUM_WAYS = 4
# Coalescer/bank granule (banks = footprint/word, NUM_BANKS = NUM_REQS). Word is
# reduced ~sqrt(lanes) below the block so banks scale for MLP while the word/bus
# stays moderate: NT 1/2/4/8/16/32/64 -> word 4/8/8/16/16/32/32, banks 1/1/2/2/4/4/8.
VX_CFG_DCACHE_WORD_SIZE = "expr: min($VX_CFG_L1_LINE_SIZE, min($VX_CFG_MEM_BLOCK_SIZE, ($VX_CFG_XLEN / 8) * pow(2, (clog2($VX_CFG_NUM_LSU_LANES) + 1) / 2)))"
VX_CFG_DCACHE_WRITEBACK = "expr: int($dcache_is_llc and $single_core)"
VX_CFG_DCACHE_DIRTYBYTES = 0
VX_CFG_DCACHE_REPL_POLICY = "expr: $__cache_repl_fifo"
VX_CFG_DCACHE_MSHR_SIZE = 16
# dcache is unsectored: line = sector = mem transaction granule = L1_LINE (which
# defaults to MEM_BLOCK but can be configured smaller). Banking comes from the
# reduced WORD above (>= sector is clamped), not the line. Deriving from L1_LINE
# (rather than hardcoding MEM_BLOCK) keeps line/sector/word/mem-bus consistent
# when L1_LINE is overridden, so a sub-block line stays a valid sectored config.
VX_CFG_DCACHE_LINE_SIZE = "expr: $VX_CFG_L1_LINE_SIZE"
VX_CFG_DCACHE_SECTOR_SIZE = "expr: $VX_CFG_L1_LINE_SIZE"
VX_CFG_DCACHE_LATENCY = "expr: 2 + max(0, clog2($VX_CFG_DCACHE_SIZE) - clog2(16384))"
VX_CFG_DCACHE_MRSQ_SIZE = 4
VX_CFG_DCACHE_MREQ_SIZE = 0
VX_CFG_DCACHE_CRSQ_SIZE = 0

VX_CFG_NUM_ICACHES = "expr: up($VX_CFG_SOCKET_SIZE / 4) if $VX_CFG_ICACHE_ENABLE else 0"
VX_CFG_NUM_DCACHES = "expr: up($VX_CFG_SOCKET_SIZE / 4) if $VX_CFG_DCACHE_ENABLE else 0"

VX_CFG_DCACHE_NUM_BANKS = "expr: pow(2, clog2(min($VX_CFG_DCACHE_NUM_REQS, 16)))"

VX_CFG_L1_MEM_PORTS = "expr: min($VX_CFG_DCACHE_NUM_BANKS, $VX_CFG_PLATFORM_MEMORY_NUM_BANKS) if ($VX_CFG_ICACHE_ENABLE or $VX_CFG_DCACHE_ENABLE) else min($VX_CFG_DCACHE_NUM_REQS, $VX_CFG_PLATFORM_MEMORY_NUM_BANKS)"

[l2cache]
VX_CFG_L2_SIZE = 1048576
VX_CFG_L2_NUM_WAYS = 8
VX_CFG_L2_WRITEBACK = "expr: int($l2_is_llc and $single_cluster)"
VX_CFG_L2_DIRTYBYTES = 0
VX_CFG_L2_REPL_POLICY = "expr: $__cache_repl_fifo"
VX_CFG_L2_MSHR_SIZE = 16
VX_CFG_L2_LATENCY = "expr: 4 + max(0, clog2($VX_CFG_L2_SIZE) - clog2(1048576))"
VX_CFG_L2_MRSQ_SIZE = 4
VX_CFG_L2_MREQ_SIZE = 0
VX_CFG_L2_CRSQ_SIZE = 0

VX_CFG_L2_NUM_BANKS = "expr: pow(2, clog2(min($VX_CFG_L2_NUM_REQS, 16)))"
VX_CFG_L2_MEM_PORTS = "expr: min($VX_CFG_L2_NUM_BANKS, $VX_CFG_PLATFORM_MEMORY_NUM_BANKS) if $VX_CFG_L2_ENABLE else min($VX_CFG_L2_NUM_REQS, $VX_CFG_PLATFORM_MEMORY_NUM_BANKS)"

[l3cache]
VX_CFG_L3_SIZE = 2097152
VX_CFG_L3_NUM_WAYS = 8
VX_CFG_L3_WRITEBACK = "expr: int($l3_is_llc)"
VX_CFG_L3_DIRTYBYTES = 0
VX_CFG_L3_REPL_POLICY = "expr: $__cache_repl_fifo"
VX_CFG_L3_MSHR_SIZE = 16
VX_CFG_L3_LATENCY = "expr: 4 + max(0, clog2($VX_CFG_L3_SIZE) - clog2(2097152))"
VX_CFG_L3_MRSQ_SIZE = 4
VX_CFG_L3_MREQ_SIZE = 0
VX_CFG_L3_CRSQ_SIZE = 0

VX_CFG_L3_NUM_BANKS = "expr: pow(2, clog2(min($VX_CFG_L3_NUM_REQS, 16)))"
VX_CFG_L3_MEM_PORTS = "expr: min($VX_CFG_L3_NUM_BANKS, $VX_CFG_PLATFORM_MEMORY_NUM_BANKS) if $VX_CFG_L3_ENABLE else min($VX_CFG_L3_NUM_REQS, $VX_CFG_PLATFORM_MEMORY_NUM_BANKS)"

[lmem]
VX_CFG_LMEM_LOG_SIZE = 14
VX_CFG_LMEM_NUM_BANKS = "expr: $VX_CFG_NUM_LSU_LANES"

[tcu]
# string enum: 'DPI'|'DSP'|'BHF'|'TFR'|'FPNEW'; TFR is the universal default. On
# FPGA its FEDP multipliers map onto DSP48 via VX_CFG_TCU_USE_DSP below.
VX_CFG_TCU_TYPE = "TFR"
VX_CFG_NUM_TCU_LANES = "expr: $VX_CFG_NUM_THREADS"
VX_CFG_NUM_TCU_BLOCKS = "expr: $VX_CFG_ISSUE_WIDTH"
# Map FEDP multipliers onto DSP48: on for FPGA synth, off for ASIC/sim.
VX_CFG_TCU_USE_DSP = "expr: 1 if ($SYNTHESIS and not $ASIC) else 0"
# Block-geometry K (mirrors VX_tcu_pkg's TCU_TC_K derivation).
tcu_tc_k = "expr: 1 << (clog2($VX_CFG_NUM_THREADS) // 2)"
# Per-type FEDP pipeline latency; each FEDP variant asserts the selected
# value against its internal stage structure at elaboration.
tcu_latency_dsp   = "expr: 1 + 8 + clog2(2 * $tcu_tc_k + 1) * 11"
tcu_latency_bhf   = "expr: 4 + clog2(2 * $tcu_tc_k + 1) * 3"
tcu_latency_fpnew = "expr: 14 + clog2(2 * $tcu_tc_k) * 7"
tcu_latency_dpi   = 4
# TFR = mul stages + align + accumulate + round: 5 = 2-stage multiply
# (DSP48 PREG on FPGA), 4 = single-cycle multiply used in simulation.
tcu_latency_tfr   = "expr: 5 if ($VIVADO or $QUARTUS) else 4"
VX_CFG_TCU_LATENCY = "expr: $tcu_latency_dsp if $VX_CFG_TCU_TYPE_DSP else ($tcu_latency_bhf if $VX_CFG_TCU_TYPE_BHF else ($tcu_latency_fpnew if $VX_CFG_TCU_TYPE_FPNEW else ($tcu_latency_dpi if $VX_CFG_TCU_TYPE_DPI else $tcu_latency_tfr)))"
VX_CFG_TCU_TF32_ENABLE = false
VX_CFG_TCU_FP16_ENABLE = true
VX_CFG_TCU_FP8_ENABLE = false
VX_CFG_TCU_FP4_ENABLE = false
VX_CFG_TCU_INT8_ENABLE = false
VX_CFG_TCU_INT4_ENABLE = false
VX_CFG_TCU_MX_ENABLE = false
VX_CFG_TCU_MXFP4_ENABLE = false
VX_CFG_TCU_NVFP4_ENABLE = false
VX_CFG_TCU_SPARSE_ENABLE = false
VX_CFG_TCU_DSM_ENABLE = false
VX_CFG_TCU_WGMMA_ENABLE = false
VX_CFG_TCU_FEDP2K = false

[dxa]
# Cluster-level DXA engine count, decoupled from cores/socket size.
VX_CFG_NUM_DXA_CORES = "expr: max(1, up($VX_CFG_NUM_CORES / 8))"
VX_CFG_DXA_MEM_PORTS = "expr: min($VX_CFG_NUM_DXA_CORES, up($VX_CFG_NUM_CORES / $VX_CFG_SOCKET_SIZE) * $VX_CFG_L1_MEM_PORTS)"
VX_CFG_DXA_QUEUE_SIZE = 16
VX_CFG_DXA_MAX_INFLIGHT = 8

[rtu]
# RTU (Ray-Tracing Unit)
VX_CFG_NUM_RTU_CORES       = "expr: up($VX_CFG_SOCKET_SIZE / 4)"
VX_CFG_RTU_BVH_WIDTH       = 4    # CW-BVH4
# Flat-walker (BVH_WIDTH=0) TLAS/instancing path. Off by default: the CW-BVH4
# walker descends LEAF_INST natively, so this is only needed in a flat (WIDTH=0)
# build. Made explicit so the ifdef has a defined producer instead of resolving
# to always-false.
VX_CFG_RTU_TLAS_ENABLE     = false
VX_CFG_RTU_STACK_DEPTH     = 16   # short-stack depth per context
VX_CFG_RTU_RECIP_DSP_SEED  = 0    # inv_d reciprocal backend: 0=LUT-NR, 1=BRAM seed + DSP Newton-Raphson
# Map the geometry-PE F32 FMAs/FDIVs onto the hardened vendor FP IP: on for FPGA
# synth, off for ASIC/sim (mirrors VX_CFG_FPU_USE_DSP).
VX_CFG_RTU_USE_DSP         = "expr: 1 if ($SYNTHESIS and not $ASIC) else 0"
# RTU divide latency. Unlike the flexible-latency soft FMA, VX_fdiv_unit has a FIXED
# depth per backend, so this is BACKEND-keyed like VX_CFG_FMA_LATENCY — NOT FPU-type
# keyed like VX_CFG_FDIV_LATENCY (which would hand the RTL divider the DPI/FPNEW
# model's 15/16 that the RTU never uses). Vendor xil_fdiv=28 on Vivado, altera=15 on
# Quartus, soft VX_fdiv_unit_rtl F32=17 in sim/ASIC. Matches VX_fdiv_unit's own
# USE_VENDOR_IP = USE_DSP(=RTU_USE_DSP) && (VIVADO||QUARTUS).
VX_CFG_RTU_FDIV_LATENCY    = "expr: 28 if $VIVADO else (15 if $QUARTUS else 17)"
# Slot pool: resident traces. A slot stages one vx_rt_wtrace (its rays, its
# control state and its result record) from issue to terminal; a context is one
# ray's live BVH walk. The two are independent axes: slots buy residency,
# contexts buy traversal parallelism. Slots partition statically across the
# cores an RTU serves (CORES_PER_RTU = SOCKET_SIZE / NUM_RTU_CORES), so the
# count must be a whole multiple of that — the expression below is one slot per
# core at every socket size. A kernel that keeps more traces in flight per warp
# than its core owns slots needs a larger pool (see tests/raytracing).
VX_CFG_RTU_NUM_SLOTS       = "expr: $VX_CFG_SOCKET_SIZE / $VX_CFG_NUM_RTU_CORES"
# In-flight ray contexts. DERIVED, not a free knob: a SLOT OWNS ITS CONTEXTS (one per
# thread of the warp it is tracing), so the two cannot be set independently. They used to
# be, and the "extra contexts idle" configuration that allowed was a machine in which
# slots bought residency but never traversal parallelism.
# Raising slots past 1 MEASURES WORSE (rt_raycast, rtlsim: 1 slot 197,404 cy; 2 slots
# +3.7%; 4 slots +28.5%) — more contexts spread a saturated front end across more
# claimants and lengthen every ray's serial chain. Widen the front end before revisiting.
VX_CFG_RTU_NUM_CTX         = "expr: $VX_CFG_RTU_NUM_SLOTS * $VX_CFG_NUM_THREADS"
# RTU MSHR file: distinct node fetches the traversal front end may keep in
# flight, and the table that merges duplicate ones. Near the BVH root every
# context wants the same node, so one entry can serve many. 0 disables merging
# (per-context tags — one request per context per fetch).
VX_CFG_RTU_MERGE_DEPTH     = 0
VX_CFG_NUM_RTU_BLOCKS      = 2    # parallel memory request ports per RtuCore

[tex]
VX_CFG_NUM_TEX_CORES = "expr: max(1, up($VX_CFG_NUM_CORES / 8))"
# Texture memory-level parallelism: the request queue is the hard limit on how
# many texture instructions a core can have in flight, so it must be sized by
# the latency to hide, not by the SIMD-group count (which was 1 in every
# graphics config, capping the unit at 2 outstanding requests).
VX_CFG_TEX_REQ_QUEUE_SIZE = "expr: max(8, 2 * up($VX_CFG_NUM_THREADS / $VX_CFG_NUM_SFU_LANES))"
VX_CFG_TEX_MEM_QUEUE_SIZE = "expr: $VX_CFG_TEX_REQ_QUEUE_SIZE"

[raster]
VX_CFG_NUM_RASTER_CORES       = "expr: max(1, up($VX_CFG_NUM_CORES / 16))"
VX_CFG_RASTER_NUM_SLICES      = 1
VX_CFG_RASTER_TILE_LOG_SIZE    = 5
# Coarse bin: on-device binning groups prims into 128 px bins and
# the RASTER front end descends bin -> block -> quad, re-evaluating edges. Far
# fewer coverage entries than 32 px tiles; identical pixel coverage.
VX_CFG_RASTER_BIN_LOG_SIZE     = 7
VX_CFG_RASTER_BLOCK_LOG_SIZE   = 2
VX_CFG_RASTER_MEM_FIFO_DEPTH  = 8
VX_CFG_RASTER_QUAD_FIFO_DEPTH = 32
VX_CFG_RASTER_MEM_QUEUE_SIZE  = 4
VX_CFG_RASTER_EARLYZ_ENABLE          = false

[om]
VX_CFG_NUM_OM_CORES       = "expr: max(1, up($VX_CFG_NUM_CORES / 8))"
VX_CFG_OM_MEM_QUEUE_SIZE  = 4

[tcache]
VX_CFG_TCACHE_SIZE      = 8192
VX_CFG_TCACHE_NUM_BANKS = 1
VX_CFG_TCACHE_NUM_WAYS  = 2
VX_CFG_TCACHE_CRSQ_SIZE = 0
VX_CFG_TCACHE_MSHR_SIZE = 16
VX_CFG_TCACHE_MRSQ_SIZE = 0
VX_CFG_TCACHE_MREQ_SIZE = 0
VX_CFG_NUM_TCACHES      = "expr: max(1, up($VX_CFG_NUM_TEX_CORES / 4))"

[rcache]
VX_CFG_RCACHE_SIZE      = 4096
VX_CFG_RCACHE_NUM_BANKS = 1
VX_CFG_RCACHE_NUM_WAYS  = 2
VX_CFG_RCACHE_CRSQ_SIZE = 0
VX_CFG_RCACHE_MSHR_SIZE = 16
VX_CFG_RCACHE_MRSQ_SIZE = 0
VX_CFG_RCACHE_MREQ_SIZE = 0
VX_CFG_NUM_RCACHES      = "expr: max(1, up($VX_CFG_NUM_RASTER_CORES / 4))"

[rtcache]
# RTU-private L1 BVH/scene cache. Mirrors the rcache shape
# (raster cache) — RtuCore goes direct to L2 today; this cache sits
# between them so cross-ray reuse of the same BVH nodes (root,
# upper-level internals) hits in L1 instead of thrashing L2.
# Sized larger than rcache because BVH walks touch many more lines
# per ray (root + a couple internals + leaf + tri data ≈ 5-8 lines
# per primary ray; secondary rays reuse the upper-level set).
VX_CFG_RTCACHE_SIZE      = 8192
VX_CFG_RTCACHE_NUM_BANKS = 1
VX_CFG_RTCACHE_NUM_WAYS  = 2
VX_CFG_RTCACHE_CRSQ_SIZE = 2
VX_CFG_RTCACHE_MSHR_SIZE = 16
VX_CFG_RTCACHE_MREQ_SIZE = 4
VX_CFG_RTCACHE_MRSQ_SIZE = 0
VX_CFG_NUM_RTCACHES      = "expr: max(1, up($VX_CFG_NUM_RTU_CORES / 4))"

[ocache]
VX_CFG_OCACHE_SIZE      = 16384
VX_CFG_OCACHE_NUM_BANKS = 1
VX_CFG_OCACHE_NUM_WAYS  = 2
VX_CFG_OCACHE_CRSQ_SIZE = 0
VX_CFG_OCACHE_MSHR_SIZE = 16
VX_CFG_OCACHE_MRSQ_SIZE = 0
VX_CFG_OCACHE_MREQ_SIZE = 0
VX_CFG_NUM_OCACHES      = "expr: max(1, up($VX_CFG_NUM_OM_CORES / 4))"

[isa_signatures]

# Standard extension signature
VX_CFG_MISA_STD = "expr: ($VX_CFG_EXT_A_ENABLED << 0) | (0 << 1) | ($VX_CFG_EXT_C_ENABLED << 2) | ($VX_CFG_EXT_D_ENABLED << 3) | (0 << 4) | ($VX_CFG_EXT_F_ENABLED << 5) | (0 << 6) | (0 << 7) | (1 << 8) | (0 << 9) | (0 << 10) | (0 << 11) | ($VX_CFG_EXT_M_ENABLED << 12) | (0 << 13) | (0 << 14) | (0 << 15) | (0 << 16) | (0 << 17) | (0 << 18) | (0 << 19) | (1 << 20) | (0 << 21) | (0 << 22) | (1 << 23) | (0 << 24) | (0 << 25)"

# Custom extensions signature
VX_CFG_MISA_EXT = "expr: ($VX_CFG_ICACHE_ENABLED << 0) | ($VX_CFG_DCACHE_ENABLED << 1) | ($VX_CFG_L2_ENABLED << 2) | ($VX_CFG_L3_ENABLED << 3) | ($VX_CFG_LMEM_ENABLED << 4) | ($VX_CFG_EXT_ZICOND_ENABLED << 5) | ($VX_CFG_EXT_TCU_ENABLED << 9) | ($VX_CFG_EXT_DXA_ENABLED << 10) | ($VX_CFG_EXT_TEX_ENABLED << 6) | ($VX_CFG_EXT_RASTER_ENABLED << 7) | ($VX_CFG_EXT_OM_ENABLED << 8) | ($VX_CFG_EXT_RTU_ENABLED << 11)"

[toolchain]
ASIC = false
SYNTHESIS = false
VIVADO = false
QUARTUS = false
YOSYS = false
SYNOPSYS = false
SV_DPI = false

[debug]
VX_DBG_STALL_TIMEOUT = "expr: (100000 * (1 << ($VX_CFG_L2_ENABLED + $VX_CFG_L3_ENABLED)))"
VX_DBG_DEBUG_LEVEL = 3

[[enum]]
VX_CFG_XLEN = [32, 64]
VX_CFG_FLEN = [32, 64]
VX_CFG_FPU_TYPE = ["DPI", "DSP", "FPNEW", "STD"]
VX_CFG_TCU_TYPE = ["DPI", "DSP", "BHF", "TFR", "FPNEW"]

[[param]]
VX_CFG_DCACHE_NUM_REQS = "int"
VX_CFG_L2_NUM_REQS = "int"
VX_CFG_L3_NUM_REQS = "int"

[[builtin]]
__FILE__ = "string"
__LINE__ = "int"