{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":690153319,"defaultBranch":"master","name":"DigitalLogicDesignExp_verilog","ownerLogin":"wang-hsiu-cheng","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2023-09-11T16:24:10.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/83440242?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1719310794.0","currentOid":""},"activityList":{"items":[{"before":"48bb92be56832e6651c7f3395a3a388720794353","after":"d3f81044c7a1f7c7d244539ac3d27f33c479b25c","ref":"refs/heads/master","pushedAt":"2024-07-13T06:49:53.000Z","pushType":"push","commitsCount":7,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"Merge branch 'master' of https://github.com/Wang-hsiu-chen/DigitalLogicDesignExp_verilog","shortMessageHtmlLink":"Merge branch 'master' of <a href=\"https://github.com/Wang-hsiu-chen/DigitalLogicDesignExp_verilog\">https://github.com/Wang-hsiu-chen/DigitalLog…</a>"}},{"before":"679ba8a0fd5eb04cbaae8a213fac406e21439174","after":"48bb92be56832e6651c7f3395a3a388720794353","ref":"refs/heads/master","pushedAt":"2024-06-25T10:23:27.000Z","pushType":"pr_merge","commitsCount":5,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"Merge pull request #1 from wang-hsiu-cheng/final-project\n\nFinal project","shortMessageHtmlLink":"Merge pull request <a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2372304844\" data-permission-text=\"Title is private\" data-url=\"https://github.com/wang-hsiu-cheng/DigitalLogicDesignExp_verilog/issues/1\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/wang-hsiu-cheng/DigitalLogicDesignExp_verilog/pull/1/hovercard\" href=\"https://github.com/wang-hsiu-cheng/DigitalLogicDesignExp_verilog/pull/1\">#1</a> from wang-hsiu-cheng/final-project"}},{"before":"84e500149ca34422091494e88d79c2276ccd57ce","after":"1ee3264d483e83f6c78c1faff11b7e84628fa80b","ref":"refs/heads/final-project","pushedAt":"2024-06-25T10:22:11.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"final project version 2","shortMessageHtmlLink":"final project version 2"}},{"before":null,"after":"84e500149ca34422091494e88d79c2276ccd57ce","ref":"refs/heads/final-project","pushedAt":"2024-06-25T10:19:54.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"final project version 0","shortMessageHtmlLink":"final project version 0"}},{"before":"4a8e4ece5e81ba73c7b164edba8bdb0e58661553","after":"679ba8a0fd5eb04cbaae8a213fac406e21439174","ref":"refs/heads/master","pushedAt":"2024-06-25T10:17:43.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"update lab4","shortMessageHtmlLink":"update lab4"}},{"before":"b49867b7981c88d2d0496417e7d00d84ab46df70","after":"4a8e4ece5e81ba73c7b164edba8bdb0e58661553","ref":"refs/heads/master","pushedAt":"2023-09-18T17:30:03.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"add lab4-1: down counter\nclock, counter, topmodule\nadd the describtion","shortMessageHtmlLink":"add lab4-1: down counter"}},{"before":"e172de8ff7e4ba6e5ad2d2b88cdbca3256dcc2d1","after":"b49867b7981c88d2d0496417e7d00d84ab46df70","ref":"refs/heads/master","pushedAt":"2023-09-18T17:24:43.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"add the describtion for lab3","shortMessageHtmlLink":"add the describtion for lab3"}},{"before":"7c3d4e832371f4df242bf2f0e2763eb89747ac41","after":"e172de8ff7e4ba6e5ad2d2b88cdbca3256dcc2d1","ref":"refs/heads/master","pushedAt":"2023-09-15T17:34:32.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"add lab3-5: Marquee\nincluded:\nparam_file freqdiv topmodule ringcounter(to move the words)","shortMessageHtmlLink":"add lab3-5: Marquee"}},{"before":"373a3b6aa3bc07f341eb2d4f53a25eddc4c5c700","after":"7c3d4e832371f4df242bf2f0e2763eb89747ac41","ref":"refs/heads/master","pushedAt":"2023-09-15T17:30:27.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"add lab3-4: Ring Counter","shortMessageHtmlLink":"add lab3-4: Ring Counter"}},{"before":"a8a9ce382599d9f9a064432d37b6e4100385f108","after":"373a3b6aa3bc07f341eb2d4f53a25eddc4c5c700","ref":"refs/heads/master","pushedAt":"2023-09-15T17:29:40.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"add lab3-3: Synchronize Counter","shortMessageHtmlLink":"add lab3-3: Synchronize Counter"}},{"before":"03fcca6deec14b0a974b71c5a0259f168c6dee23","after":"a8a9ce382599d9f9a064432d37b6e4100385f108","ref":"refs/heads/master","pushedAt":"2023-09-14T04:58:49.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"add lab3-2 hw\nfrequency divider 50million Hz","shortMessageHtmlLink":"add lab3-2 hw"}},{"before":"e58b39f27780dffb2dd55c48135c1a8f59fd56d5","after":"03fcca6deec14b0a974b71c5a0259f168c6dee23","ref":"refs/heads/master","pushedAt":"2023-09-14T04:56:22.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"add lab3-1 hw\nfrequency divider approximate to 1sec.","shortMessageHtmlLink":"add lab3-1 hw"}},{"before":"bc035408f813224c43bd61146ac2c472a7814b88","after":"e58b39f27780dffb2dd55c48135c1a8f59fd56d5","ref":"refs/heads/master","pushedAt":"2023-09-13T06:52:13.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"add lab2-3 homework and lab2 instruction file\ninclude emulation file","shortMessageHtmlLink":"add lab2-3 homework and lab2 instruction file"}},{"before":"e0e7fac39054ddc882d626b539c3524dd50bb97f","after":"bc035408f813224c43bd61146ac2c472a7814b88","ref":"refs/heads/master","pushedAt":"2023-09-13T06:50:53.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"add lab2-2 homework, include emulation file","shortMessageHtmlLink":"add lab2-2 homework, include emulation file"}},{"before":"30c98673952517b66c4f3489c7fbfc40ee09a752","after":"e0e7fac39054ddc882d626b539c3524dd50bb97f","ref":"refs/heads/master","pushedAt":"2023-09-13T06:50:27.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"add lab2-1 homework, include emulation file","shortMessageHtmlLink":"add lab2-1 homework, include emulation file"}},{"before":"8c59d6bea2e52fae2782e4f87f49a3fdda3d4ed8","after":"30c98673952517b66c4f3489c7fbfc40ee09a752","ref":"refs/heads/master","pushedAt":"2023-09-11T16:29:03.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"lab1-1","shortMessageHtmlLink":"lab1-1"}},{"before":null,"after":"8c59d6bea2e52fae2782e4f87f49a3fdda3d4ed8","ref":"refs/heads/master","pushedAt":"2023-09-11T16:24:15.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"wang-hsiu-cheng","name":"WANG, HSIU-CHENG","path":"/wang-hsiu-cheng","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/83440242?s=80&v=4"},"commit":{"message":"lab1 instruction","shortMessageHtmlLink":"lab1 instruction"}}],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEfm0GjgA","startCursor":null,"endCursor":null}},"title":"Activity · wang-hsiu-cheng/DigitalLogicDesignExp_verilog"}