Many post-synthesis functional and especially post-routing timing simulations currently fail due to startup and initialization problems. Cause is MMCM/PLL startup, which is not properly reflected in the test bench. Will be resolved in an upcoming release.
Note: behavioral simulations work fine, and the real FPGA too.
originally filed as issue V0.73-2 on 2016-06-26
Many post-synthesis functional and especially post-routing timing simulations currently fail due to startup and initialization problems. Cause is MMCM/PLL startup, which is not properly reflected in the test bench. Will be resolved in an upcoming release.
Note: behavioral simulations work fine, and the real FPGA too.
originally filed as issue V0.73-2 on 2016-06-26