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philljjphilljj
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Merge pull request #508 from danielinux/atsama5d3
Fixes for SAMA5D3
2 parents b97abd4 + cb77e42 commit 7891960

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8 files changed

+125
-48
lines changed

8 files changed

+125
-48
lines changed

‎arch.mk

+6-2
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,8 @@ endif
6868

6969
ifeq ($(ARCH),ARM)
7070
CROSS_COMPILE?=arm-none-eabi-
71-
CFLAGS+=-mthumb -mlittle-endian -mthumb-interwork -DARCH_ARM
71+
CFLAGS+=-DARCH_ARM
72+
CFLAGS+=-mthumb -mlittle-endian -mthumb-interwork
7273
LDFLAGS+=-mthumb -mlittle-endian -mthumb-interwork
7374

7475
## Target specific configuration
@@ -194,7 +195,10 @@ ifeq ($(CORTEX_A5),1)
194195
MATH_OBJS+=./lib/wolfssl/wolfcrypt/src/sp_c32.o
195196
else
196197
MATH_OBJS+=./lib/wolfssl/wolfcrypt/src/sp_arm32.o
197-
CFLAGS+=-DWOLFSSL_SP_ARM32_ASM
198+
OBJS+=./lib/wolfssl/wolfcrypt/src/port/arm/armv8-sha256.o
199+
OBJS+=./lib/wolfssl/wolfcrypt/src/port/arm/armv8-32-sha256-asm.o
200+
OBJS+=./lib/wolfssl/wolfcrypt/src/port/arm/armv8-32-sha256-asm_c.o
201+
CFLAGS+=-DWOLFSSL_SP_ARM32_ASM -DWOLFSSL_ARMASM -DWOLFSSL_ARMASM_NO_HW_CRYPTO -DWOLFSSL_ARM_ARCH=7 -DWOLFSSL_ARMASM_INLINE -DWOLFSSL_ARMASM_NO_NEON
198202
endif
199203
else
200204
# All others use boot_arm.o

‎config/examples/sama5d3.config

+3-4
Original file line numberDiff line numberDiff line change
@@ -5,17 +5,16 @@ HASH?=SHA256
55
DEBUG?=0
66
VTOR?=1
77
CORTEX_M0?=0
8-
NO_ASM?=0
98
EXT_FLASH?=1
109
NAND_FLASH?=1
1110
SPI_FLASH?=0
1211
V?=0
1312
SPMATH?=1
14-
WOLFBOOT_PARTITION_SIZE?=0x1000000
13+
WOLFBOOT_PARTITION_SIZE?=0x8000000
1514
WOLFBOOT_NO_PARTITIONS=0
1615
WOLFBOOT_SECTOR_SIZE?=0x1000
17-
WOLFBOOT_LOAD_ADDRESS=0x20100800
18-
WOLFBOOT_LOAD_DTS_ADDRESS=0x21100800
16+
WOLFBOOT_LOAD_ADDRESS=0x20100000
17+
WOLFBOOT_LOAD_DTS_ADDRESS=0x21100000
1918
WOLFBOOT_PARTITION_BOOT_ADDRESS=0x400000
2019
WOLFBOOT_PARTITION_UPDATE_ADDRESS=0x800000
2120
WOLFBOOT_PARTITION_SWAP_ADDRESS=0x0

‎hal/sama5d3.c

+52-9
Original file line numberDiff line numberDiff line change
@@ -195,6 +195,31 @@ static void pll_init(void)
195195
master_clock_set(PRESCALER_PLLA_CLOCK);
196196
}
197197

198+
/* GMAC PINS: PB8, PB11, PB16, PB18 */
199+
/* EMAC PINS: PC7, PC8 */
200+
#define GMAC_PINS ( (1 << 8) | (1 << 11) | (1 << 16) | (1 << 18) )
201+
#define EMAC_PINS ( (1 << 7) | (1 << 8) )
202+
#define GPIO_GMAC GPIOB
203+
#define GPIO_EMAC GPIOC
204+
205+
static void mac_init(void)
206+
{
207+
PMC_CLOCK_EN(GPIOB_PMCID);
208+
PMC_CLOCK_EN(GPIOC_PMCID);
209+
210+
GPIO_PPUDR(GPIO_GMAC) = GMAC_PINS;
211+
GPIO_PPDDR(GPIO_GMAC) = GMAC_PINS;
212+
GPIO_PER(GPIO_GMAC) = GMAC_PINS;
213+
GPIO_OER(GPIO_GMAC) = GMAC_PINS;
214+
GPIO_CODR(GPIO_GMAC) = GMAC_PINS;
215+
216+
GPIO_PPUDR(GPIO_EMAC) = EMAC_PINS;
217+
GPIO_PPDDR(GPIO_EMAC) = EMAC_PINS;
218+
GPIO_PER(GPIO_EMAC) = EMAC_PINS;
219+
GPIO_OER(GPIO_EMAC) = EMAC_PINS;
220+
GPIO_CODR(GPIO_EMAC) = EMAC_PINS;
221+
}
222+
198223

199224
static void ddr_init(void)
200225
{
@@ -245,10 +270,7 @@ static void ddr_init(void)
245270
*
246271
*/
247272
/* Turn on the DDRAM controller peripheral clock */
248-
PMC_PCR = MPDDRC_PMCID;
249-
pmc_pcr = PMC_PCR & (~PMC_PCR_DIV_MASK);
250-
pmc_pcr |= PMC_PCR_CMD | PMC_PCR_EN;
251-
PMC_PCR = pmc_pcr;
273+
PMC_CLOCK_EN(MPDDRC_PMCID);
252274

253275
/* Enable DDR in system clock */
254276
PMC_SCER = MPDDRC_SCERID;
@@ -644,15 +666,12 @@ int ext_flash_read(uintptr_t address, uint8_t *data, int len)
644666
return len;
645667
}
646668

647-
void pit_init(void)
669+
static void pit_init(void)
648670
{
649671
uint32_t pmc_pcr;
650672

651673
/* Turn on clock for PIT */
652-
PMC_PCR = PIT_PMCID;
653-
pmc_pcr = PMC_PCR & (~PMC_PCR_DIV_MASK);
654-
pmc_pcr |= PMC_PCR_CMD | PMC_PCR_EN;
655-
PMC_PCR = pmc_pcr;
674+
PMC_CLOCK_EN(PIT_PMCID);
656675

657676
/* Set clock source to MCK/2 */
658677
PIT_MR = MAX_PIV | PIT_MR_EN;
@@ -678,6 +697,29 @@ void sleep_us(uint32_t usec)
678697
} while (current < delay);
679698
}
680699

700+
/* Set up DBGU.
701+
* Assume baud rate is correcly set by RomBoot
702+
*/
703+
static void dbgu_init(void) {
704+
/* Set up pins */
705+
PMC_CLOCK_EN(GPIOB_PMCID);
706+
707+
/* Disable Pull */
708+
GPIO_PPUDR(DBGU_GPIO) = (1U << DBGU_PIN_TX) | (1U << DBGU_PIN_RX);
709+
GPIO_PPDDR(DBGU_GPIO) = (1U << DBGU_PIN_TX) | (1U << DBGU_PIN_RX);
710+
711+
/* Set "Peripheral A" */
712+
GPIO_ASR(DBGU_GPIO) = (1U << DBGU_PIN_TX) | (1U << DBGU_PIN_RX);
713+
714+
/* Enable the peripheral clock for the DBGU */
715+
PMC_CLOCK_EN(DBGU_PMCID);
716+
717+
/* Enable the transmitter and receiver */
718+
DBGU_CR = DBGU_CR_TXEN | DBGU_CR_RXEN;
719+
}
720+
721+
722+
681723
int ext_flash_write(uintptr_t address, const uint8_t *data, int len)
682724
{
683725
/* TODO */
@@ -723,6 +765,7 @@ void hal_init(void)
723765
pit_init();
724766
watchdog_disable();
725767
ddr_init();
768+
dbgu_init();
726769
nand_read_info();
727770
}
728771

‎hal/sama5d3.h

+52-24
Original file line numberDiff line numberDiff line change
@@ -93,8 +93,6 @@
9393
#define PMC_PCR_DIV_SHIFT 13
9494
#define PMC_PCR_DIV_MASK (0x3 << PMC_PCR_DIV_SHIFT)
9595

96-
97-
9896
/* Specific configuration for 264/132/12 MHz */
9997

10098
#define PLL_PCK (((CRYSTAL_FREQ * (PLLA_MULA + 1)) / 2))
@@ -110,23 +108,33 @@
110108

111109
#define PLLICPR_CONFIG (0x0 << PMC_PLLICPR_ICPPLLA_SHIFT | 0x3 << PMC_PLLICPR_IPLLA_SHIFT)
112110

111+
/* DBGU
112+
*
113+
*/
114+
#define DBGU_BASE 0xFFFFEE00
115+
#define DBGU_CR *(volatile uint32_t *)(DBGU_BASE + 0x00)
116+
#define DBGU_BRGR *(volatile uint32_t *)(DBGU_BASE + 0x20)
117+
#define DBGU_CR_RXEN (1 << 4)
118+
#define DBGU_CR_TXEN (1 << 6)
119+
#define DBGU_PMCID 0x02 /* dec: 2 for SAMA5D3 */
120+
121+
/* Associated pins : GPIOB 30 - 31*/
122+
#define DBGU_PIN_RX 30
123+
#define DBGU_PIN_TX 31
124+
#define DBGU_GPIO GPIOB
113125

114126
/* PIT
115127
*
116128
*/
117-
118129
#define PIT_BASE 0xFFFFFE30
119130
#define PIT_MR *(volatile uint32_t *)(PIT_BASE + 0x00)
120131
#define PIT_SR *(volatile uint32_t *)(PIT_BASE + 0x04)
121132
#define PIT_PIVR *(volatile uint32_t *)(PIT_BASE + 0x08)
122133
#define PIT_PIIR *(volatile uint32_t *)(PIT_BASE + 0x0C)
123134

124-
125-
126-
127135
/* DRAM setup
136+
*
128137
*/
129-
130138
#define MPDDRC_BASE 0xFFFFEA00
131139
#define MPDDRC_MR *(volatile uint32_t *)(MPDDRC_BASE + 0x00) /* Mode Register */
132140
#define MPDDRC_RTR *(volatile uint32_t *)(MPDDRC_BASE + 0x04) /* Refresh Timer Register */
@@ -159,7 +167,6 @@
159167
#define MPDDRC_WPMR *(volatile uint32_t *)(MPDDRC_BASE + 0xE4) /* Write Protection Mode Register */
160168
#define MPDDRC_WPSR *(volatile uint32_t *)(MPDDRC_BASE + 0xE8) /* Write Protection Status Register */
161169

162-
163170
/* MPDDRC_CR: shift, mask, values */
164171
#define MPDDRC_NC_SHIFT 0 /* Number of Column Bits */
165172
#define MPDDRC_NC_MASK (0x3 << MPDDRC_NC_SHIFT)
@@ -278,6 +285,12 @@
278285
#define MAX_PIV 0xfffff
279286
#define PIT_MR_EN (1 << 24)
280287

288+
/* GPIO PMC IDs */
289+
#define GPIOA_PMCID 0x06
290+
#define GPIOB_PMCID 0x07
291+
#define GPIOC_PMCID 0x08
292+
#define GPIOD_PMCID 0x09
293+
#define GPIOE_PMCID 0x0A
281294

282295
struct dram {
283296
struct dram_timing {
@@ -302,6 +315,7 @@ struct dram {
302315
};
303316

304317
/* Watchdog
318+
*
305319
*/
306320
#define WDT_BASE 0xFFFFFD40
307321
#define WDT_CR *(volatile uint32_t *)(WDT_BASE + 0x00)
@@ -427,22 +441,36 @@ extern void *kernel_addr, *update_addr, *dts_addr;
427441
#define MAX_ECC_BYTES 8
428442
#endif
429443

430-
#define GPIOE_BASE 0xFFFFFA00
431-
432-
#define GPIOE_PER *(volatile uint32_t *)(GPIOE_BASE + 0x00)
433-
#define GPIOE_PDR *(volatile uint32_t *)(GPIOE_BASE + 0x04)
434-
#define GPIOE_PSR *(volatile uint32_t *)(GPIOE_BASE + 0x08)
435-
#define GPIOE_OER *(volatile uint32_t *)(GPIOE_BASE + 0x10)
436-
#define GPIOE_ODR *(volatile uint32_t *)(GPIOE_BASE + 0x14)
437-
#define GPIOE_OSR *(volatile uint32_t *)(GPIOE_BASE + 0x18)
438-
#define GPIOE_SODR *(volatile uint32_t *)(GPIOE_BASE + 0x30)
439-
#define GPIOE_CODR *(volatile uint32_t *)(GPIOE_BASE + 0x34)
440-
#define GPIOE_IER *(volatile uint32_t *)(GPIOE_BASE + 0x40)
441-
#define GPIOE_IDR *(volatile uint32_t *)(GPIOE_BASE + 0x44)
442-
#define GPIOE_MDER *(volatile uint32_t *)(GPIOE_BASE + 0x50)
443-
#define GPIOE_MDDR *(volatile uint32_t *)(GPIOE_BASE + 0x54)
444-
#define GPIOE_PPUDR *(volatile uint32_t *)(GPIOE_BASE + 0x60)
445-
#define GPIOE_PPUER *(volatile uint32_t *)(GPIOE_BASE + 0x64)
444+
#define GPIOB 0xFFFFF400
445+
#define GPIOC 0xFFFFF600
446+
#define GPIOE 0xFFFFFA00
447+
448+
#define GPIO_PER(base) *(volatile uint32_t *)(base + 0x00)
449+
#define GPIO_PDR(base) *(volatile uint32_t *)(base + 0x04)
450+
#define GPIO_PSR(base) *(volatile uint32_t *)(base + 0x08)
451+
#define GPIO_OER(base) *(volatile uint32_t *)(base + 0x10)
452+
#define GPIO_ODR(base) *(volatile uint32_t *)(base + 0x14)
453+
#define GPIO_OSR(base) *(volatile uint32_t *)(base + 0x18)
454+
#define GPIO_SODR(base) *(volatile uint32_t *)(base + 0x30)
455+
#define GPIO_CODR(base) *(volatile uint32_t *)(base + 0x34)
456+
#define GPIO_IER(base) *(volatile uint32_t *)(base + 0x40)
457+
#define GPIO_IDR(base) *(volatile uint32_t *)(base + 0x44)
458+
#define GPIO_MDER(base) *(volatile uint32_t *)(base + 0x50)
459+
#define GPIO_MDDR(base) *(volatile uint32_t *)(base + 0x54)
460+
#define GPIO_PPUDR(base) *(volatile uint32_t *)(base + 0x60)
461+
#define GPIO_PPUER(base) *(volatile uint32_t *)(base + 0x64)
462+
#define GPIO_ASR(base) *(volatile uint32_t *)(base + 0x70)
463+
#define GPIO_PPDDR(base) *(volatile uint32_t *)(base + 0x90)
464+
465+
466+
/* PMC Macro to enable clock */
467+
#define PMC_CLOCK_EN(id) { \
468+
register uint32_t pmc_pcr; \
469+
PMC_PCR = id; \
470+
pmc_pcr = PMC_PCR & (~PMC_PCR_DIV_MASK); \
471+
pmc_pcr |= PMC_PCR_CMD | PMC_PCR_EN; \
472+
PMC_PCR = pmc_pcr; \
473+
}
446474

447475

448476
#endif

‎hal/sama5d3.ld

+1-1
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ OUTPUT_ARCH(arm)
33

44
MEMORY
55
{
6-
DDR_MEM(rwx): ORIGIN = 0x00000000, LENGTH = 0x0000F000
6+
DDR_MEM(rwx): ORIGIN = 0x00000000, LENGTH = 0x000100000
77
}
88

99
ENTRY(reset_vector_entry)

‎include/user_settings.h

+3
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,8 @@
4141

4242
/* Stdlib Types */
4343
#define CTYPE_USER /* don't let wolfCrypt types.h include ctype.h */
44+
45+
#ifndef WOLFSSL_ARMASM
4446
#ifndef toupper
4547
extern int toupper(int c);
4648
#endif
@@ -49,6 +51,7 @@ extern int tolower(int c);
4951
#endif
5052
#define XTOUPPER(c) toupper((c))
5153
#define XTOLOWER(c) tolower((c))
54+
#endif
5255

5356
#ifdef USE_FAST_MATH
5457
/* wolfBoot only does public asymmetric operations,

‎test-app/ARM-sama5d3.ld

+1-1
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ OUTPUT_ARCH(arm)
33

44
MEMORY
55
{
6-
DDR_MEM(rwx): ORIGIN = 0x20100800, LENGTH = 0x100000
6+
DDR_MEM(rwx): ORIGIN = 0x20100000, LENGTH = 0x100000
77
STACK_MEM(rw): ORIGIN = 0x20000000, LENGTH = 0x00100000
88
}
99

‎test-app/app_sama5d3.c

+7-7
Original file line numberDiff line numberDiff line change
@@ -37,20 +37,20 @@
3737
void led_init(uint32_t pin)
3838
{
3939
uint32_t mask = 1U << pin;
40-
GPIOE_MDDR |= mask;
41-
GPIOE_PER |= mask;
42-
GPIOE_IDR |= mask;
43-
GPIOE_PPUDR |= mask;
44-
GPIOE_CODR |= mask;
40+
GPIO_MDDR(GPIOE) |= mask;
41+
GPIO_PER(GPIOE) |= mask;
42+
GPIO_IDR(GPIOE) |= mask;
43+
GPIO_PPUDR(GPIOE) |= mask;
44+
GPIO_CODR(GPIOE) |= mask;
4545
}
4646

4747
void led_put(uint32_t pin, int val)
4848
{
4949
uint32_t mask = 1U << pin;
5050
if (val)
51-
GPIOE_SODR |= mask;
51+
GPIO_SODR(GPIOE) |= mask;
5252
else
53-
GPIOE_CODR |= mask;
53+
GPIO_CODR(GPIOE) |= mask;
5454
}
5555

5656
volatile uint32_t time_elapsed = 0;

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