From d8700cb53cb253203c7314e2a45e0f2ccd91cfd7 Mon Sep 17 00:00:00 2001 From: Frank Duerr Date: Wed, 8 Oct 2025 13:47:21 +0200 Subject: [PATCH] drivers: ptp clock: ptp_clock_nxp_enet: extended pulse width of 1 PPS pulse Extended the pulse width of the 1 PPS output from 1 clock cycle to the maximum length (32 clock cycles). Signed-off-by: Frank Duerr --- drivers/ptp_clock/ptp_clock_nxp_enet.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/ptp_clock/ptp_clock_nxp_enet.c b/drivers/ptp_clock/ptp_clock_nxp_enet.c index f80d25bf8e18b..de716066ffdac 100644 --- a/drivers/ptp_clock/ptp_clock_nxp_enet.c +++ b/drivers/ptp_clock/ptp_clock_nxp_enet.c @@ -179,6 +179,16 @@ void nxp_enet_ptp_clock_callback(const struct device *dev, ENET_Ptp1588SetChannelMode(data->base, kENET_PtpTimerChannel3, kENET_PtpChannelPulseHighonCompare, true); + + /* Set 1PPS pulse width to 32 clock cycles of PTP clock. + * At 25 MHz clock frequency, this amounts to a pulse width of 1.28 us. + * Note that this is still orders of magnitude shorter than the 1PPS + * pulse width of many devices, which are often in the range of milliseconds. + * However, 32 clock cycles is the upper limit. + */ + ENET_Ptp1588SetChannelOutputPulseWidth(data->base, kENET_PtpTimerChannel3, false, + 31, true); + ENET_Ptp1588StartTimer(data->base, ptp_config.ptp1588ClockSrc_Hz); ENET_EnableInterrupts(data->base, ENET_TS_INTERRUPT); }