ForgeEDA_Dataset/03_sub_aug.py at main · zshi0616/ForgeEDA_Dataset · GitHub

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import os
import numpy as np
import random
import glob
import shutil
import utils.aiger_utils as aiger_utils
import utils.circuit_utils as circuit_utils
from utils.utils import hash_arr, run_command
import argparse
import time

gate_to_index = {'PI': 0, 'AND': 1, 'NOT': 2}
aig_dir = './data/raw_aig'
abccrc_path = '/Users/zhengyuanshi/opt/abc/abc.rc'
save_aig_path = './data/sub_aug_aig'
save_bench_path = './data/sub_bench'
NO_TRANS = 10

def parse_aig_head(aig_path):
    f = open(aig_path, 'r', encoding='ISO-8859-1')
    lines = f.readlines()
    f.close()
    for line in lines:
        header = line.replace('\n', '').split(' ')
        if header[0] == 'aig' or header[0] == 'aag':
            if len(header) == 7:
                # “M”, “I”, “L”, “O”, “A” separated by spaces.
                n_variables = eval(header[1])
                n_inputs = eval(header[2])
                n_latch = eval(header[3])
                unknown = eval(header[4])
                n_and = eval(header[5])
                n_outputs = eval(header[6])
            elif len(header) == 6:
                n_variables = eval(header[1])
                n_inputs = eval(header[2])
                n_outputs = eval(header[4])
                n_and = eval(header[5])
                n_latch = eval(header[3])
            else:
                n_variables, n_inputs, n_latch, n_outputs, n_and = 0, 0, 0, 0, 0
            return n_variables, n_inputs, n_latch, n_outputs, n_and
    return 0, 0, 0, 0, 0

def get_syn_command(no_syn):
    res = ''
    for _ in range(no_syn):
        action = random.randint(0, 6)
        if action == 0:
            res += 'balance'
            if random.randint(0, 1) == 0:
                res += ' -l'
            if random.randint(0, 1) == 0:
                res += ' -d'
            if random.randint(0, 1) == 0:
                res += ' -s'
            if random.randint(0, 1) == 0:
                res += ' -x'
            res += ';'
        elif action == 1:
            res += 'rewrite'
            if random.randint(0, 1) == 0:
                res += ' -l'
            if random.randint(0, 1) == 0:
                res += ' -z'
            res += ';'
        elif action == 2:
            res += 'resub'
            if random.randint(0, 1) == 0:
                res += ' -l'
            if random.randint(0, 1) == 0:
                res += ' -z'
            attr_K = random.randint(4, 16)
            res += ' -K {}'.format(attr_K)
            attr_N = random.randint(0, 3)
            res += ' -N {}'.format(attr_N)
            res += ';'
        elif action == 3:
            res += 'refactor'
            if random.randint(0, 1) == 0:
                res += ' -l'
            if random.randint(0, 1) == 0:
                res += ' -z'
            attr_N = random.randint(4, 15)
            res += ' -N {}'.format(attr_N)
            res += ';'
        elif action == 4:
            res += 'retime; strash; '
        elif action == 5:
            res += 'lcorr; '
        elif action == 6:
            res += 'scleanup; '

    return res

if __name__ == '__main__':
    # Convert to AIG
    no_sub_circuits = 0
    if not os.path.exists(save_aig_path):
        os.mkdir(save_aig_path)
    tot_time = 0
    tot_sub_ckt = 0
    bench_list = glob.glob(os.path.join(save_bench_path, '*/*.bench'))

    for bench_idx, bench_path in enumerate(bench_list):
        start_time = time.time()
        no_sub_circuits += 1
        arr = bench_path.replace('.bench', '').split('/')
        design_name = arr[-2]
        module_name = arr[-1]
        output_dir = os.path.join(save_aig_path, design_name)
        if not os.path.exists(output_dir):
            os.mkdir(output_dir)

        print('Parse: {} ({:} / {:}), Time: {:.2f}s, ETA: {:.2f}s, Tot: {:}'.format(
            module_name, bench_idx, len(bench_list),
            tot_time, tot_time / ((bench_idx + 1) / len(bench_list)) - tot_time,
            tot_sub_ckt
        ))

        output_aig_path = os.path.join(output_dir, '{}_0.aig').format(module_name)
        abc_cmd = 'abc -c "read_bench {}; source {}; st; resyn2; write_aiger {}"'.format(bench_path, abccrc_path, output_aig_path)
        stdout, _ = run_command(abc_cmd)
        if not os.path.exists(output_aig_path):
            continue
        ori_n_variables, ori_n_inputs, ori_n_latch, ori_n_outputs, ori_n_and = parse_aig_head(output_aig_path)
        if ori_n_variables == 0:
            continue

        for trans_time in range(1, NO_TRANS+1):
            tmp_aig_path = './tmp/{}_{}.aig'.format(design_name, module_name)
            abc_cmd = 'abc -c "read_bench {}; source {}; st; {}; write_aiger {}"'.format(
                bench_path, abccrc_path, get_syn_command(random.randint(2, 5)), tmp_aig_path
            )
            stdout, _ = run_command(abc_cmd)
            if not os.path.exists(tmp_aig_path):
                continue
            n_variables, n_inputs, n_latch, n_outputs, n_and = parse_aig_head(tmp_aig_path)
            diff = abs(n_variables - ori_n_variables) + abs(n_and - ori_n_and)
            if diff < 10:
                os.remove(tmp_aig_path)
                continue
            output_aig_path = os.path.join(output_dir, '{}_{}.aig').format(module_name, trans_time)
            shutil.move(tmp_aig_path, output_aig_path)
            tot_sub_ckt += 1

        tot_time += time.time() - start_time

    print('[INFO] Total number of subcircuits: {}'.format(tot_sub_ckt))