ForgeEDA_Dataset/0_aig2v.py at main · zshi0616/ForgeEDA_Dataset · GitHub

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import os
import glob
from torch_geometric.data import Data, InMemoryDataset
import deepgate as dg
import torch
import random
import time
import threading
import copy
import numpy as np
import argparse

from utils.utils import run_command, hash_arr
from parse_graph import parse_sdf
import utils.circuit_utils as circuit_utils

aig_dir = './data/sub_aig'
v_dir = './data/sub_v'
abccrc_path = '/Users/zhengyuanshi/opt/abc/abc.rc'

OUT_LIST = False
RESYN = False

def get_args():
    parser = argparse.ArgumentParser(description='AIG to Verilog')
    parser.add_argument('--start_idx', type=int, default=0, help='Start index')
    parser.add_argument('--end_idx', type=int, default=100000, help='End index')
    args = parser.parse_args()
    return args

if __name__ == '__main__':
    if OUT_LIST:
        aig_list = glob.glob(os.path.join(aig_dir, '*/*.aig'))
        f = open('./aig_list.txt', 'w')
        for aig_path in aig_list:
            f.write('{}\n'.format(aig_path))
        f.close()
        print('List saved to aig_list.txt')
        exit()
    else:
        args = get_args()
        f = open('./aig_list.txt', 'r')
        aig_list = f.readlines()
        f.close()
        aig_list = [aig.replace('\n', '') for aig in aig_list]
        no_aigs = min(args.end_idx - args.start_idx, len(aig_list))

    tot_time = 0
    no_succ = 0
    failed_list = []
    if not os.path.exists(v_dir):
        os.makedirs(v_dir)

    for aig_k, aig_path in enumerate(aig_list):
        if aig_k < args.start_idx or aig_k >= args.end_idx:
            continue

        start_time = time.time()
        arr = aig_path.replace('.aig', '').split('/')
        design_name = arr[-2]
        module_name = arr[-1]
        circuit_name = '{}/{}'.format(design_name, module_name)
        if not os.path.exists(aig_path):
            print('[ERROR] File not found: {}'.format(aig_path))
            continue

        design_v_dir = os.path.join(v_dir, design_name)
        if not os.path.exists(design_v_dir):
            os.makedirs(design_v_dir)
        v_path = os.path.join(design_v_dir, '{}.v'.format(module_name))
        if not RESYN and os.path.exists(v_path):
            continue

        ###################################################
        # ABC
        ###################################################
        stdout, _ = run_command('abc -c "read_aiger {}; write_verilog {}"'.format(aig_path, v_path))
        if not os.path.exists(v_path):
            print('[ERROR] ABC failed: {}'.format(v_path))
            failed_list.append(aig_path)
            continue
        no_succ += 1

        # Statistics
        print('Parse: {} ({:} / {:}), Time: {:.2f}s, ETA: {:.2f}s'.format(
            circuit_name, aig_k, no_aigs,
            tot_time, tot_time / ((aig_k - args.start_idx + 1) / no_aigs) - tot_time
        ))
        tot_time += time.time() - start_time


    print()
    print('='*20)
    failed_path = './aig_to_v_{:}_{:}.txt'.format(args.start_idx, args.end_idx)
    f = open(failed_path, 'w')
    for failed in failed_list:
        f.write('{}\n'.format(failed))
        print(failed)
    f.close()
    print()

    print('Total: {}, Succ: {}'.format(no_aigs, no_succ))