抽象的数电挑战课（至少在20级的微电子专业非常抽象:sweat_smile:
Code of a simple FSM for ADD challenge course in Glasgow College
格院数电挑战课的简单Finite State Machine代码（有上板但不是我负责的部分所以没有验证到底能不能用
所以有错请不要打我 之后有空会再重新捋一遍
⚠DO NOT PLAGIARIZE
⚠可以用于理解代码，但请不要抄袭
After such a long shelve, updates for ADDs will get back on track , thanks to ECE550.
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32-bit CSA (see CheckPoint 1.)
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Full ALU (Specific operations are here in CP2.)
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Register
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Datapath
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Control
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Pipeline
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FPGA verification
- Flappy Bird
IP_core_ver folder contains code using Vivado IP core as ROM, which is automatically generated by Vivado when IP core is configured.
IP_core_ver文件夹包含了使用IP核做ROM的所有代码。代码会在IP核配置完成后自动生成。
Unsynthesizable folder contains code using a traditional method to establish ROM, but somehow failed to synthesize in Vivado 2017.4.
Unsynthesizable文件夹包含了使用代码构建的ROM但在Vivado2017.4里面综合失败，应该是写的有问题不推荐使用。
testbench folder contains testbench code for ALU and CPU top layer.
testbench文件夹包含了ALU和CPU顶层的tb代码，其他部分的tb代码根据源码可以轻松写出。
Writen by a green hand, mistakes could occur at any time.:cold_sweat: If you also wanna help the junior accomplish this course, welcome to opensource your code.
Skeleton Code, thanks to @yuzdoge
特别鸣谢不知名学长@yuzdoge提供的代码框架