Designed a specialized processor aimed at accelerating matrix processing featuring implemented functionalities for matrix multiplication addition and subtraction. The architecture is scalable accommodating new instructions seamlessly. Leveraged advanced digital system concepts including Direct Memory Access (DMA) and AXI Protocol to optimize performance. Successfully implemented and tested the processor on a Xilinx Artix 7 and Arm core (ZYNQ) FPGA.
Here're some of the project's best features:
- Matrix Multiplicatio
- Matrix Addition
- Matrix Substraction
- DDR3 RAM access
- Direct Memory Access Usage