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- prevent PSRAM use on ESP32 rev.1 without compile fix - add runtime selection for CCT IC (Athom 15W bulb)
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,6 +1,6 @@ | ||
# Name, Type, SubType, Offset, Size, Flags | ||
nvs, data, nvs, 0x9000, 0x5000, | ||
otadata, data, ota, 0xe000, 0x2000, | ||
app0, app, ota_0, 0x10000, 0x180000, | ||
app1, app, ota_1, 0x190000,0x180000, | ||
spiffs, data, spiffs, 0x310000,0xF0000, | ||
app0, app, ota_0, 0x10000, 0x1A0000, | ||
app1, app, ota_1, 0x1B0000,0x1A0000, | ||
spiffs, data, spiffs, 0x350000,0xB0000, |
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Original file line number | Diff line number | Diff line change |
---|---|---|
|
@@ -241,7 +241,7 @@ void WLED::loop() | |
DEBUG_PRINT(F("Unix time: ")); toki.printTime(toki.getTime()); | ||
DEBUG_PRINT(F("Free heap: ")); DEBUG_PRINTLN(ESP.getFreeHeap()); | ||
#if defined(ARDUINO_ARCH_ESP32) | ||
if (psramFound()) { | ||
if (psramSafe && psramFound()) { | ||
DEBUG_PRINT(F("Total PSRAM: ")); DEBUG_PRINT(ESP.getPsramSize()/1024); DEBUG_PRINTLN("kB"); | ||
DEBUG_PRINT(F("Free PSRAM: ")); DEBUG_PRINT(ESP.getFreePsram()/1024); DEBUG_PRINTLN("kB"); | ||
} | ||
|
@@ -367,9 +367,12 @@ void WLED::setup() | |
DEBUG_PRINT(F("heap ")); DEBUG_PRINTLN(ESP.getFreeHeap()); | ||
|
||
#if defined(ARDUINO_ARCH_ESP32) | ||
pDoc = new PSRAMDynamicJsonDocument((psramFound() ? 2 : 1)*JSON_BUFFER_SIZE); | ||
#ifndef BOARD_HAS_PSRAM | ||
if (psramFound() && ESP.getChipRevision() < 3) psramSafe = false; | ||
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blazoncek
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|
||
#endif | ||
pDoc = new PSRAMDynamicJsonDocument((psramSafe && psramFound() ? 2 : 1)*JSON_BUFFER_SIZE); | ||
// if the above fails requestJsonBufferLock() will always return false preventing crashes | ||
if (psramFound()) { | ||
if (psramSafe && psramFound()) { | ||
DEBUG_PRINT(F("Total PSRAM: ")); DEBUG_PRINT(ESP.getPsramSize()/1024); DEBUG_PRINTLN("kB"); | ||
DEBUG_PRINT(F("Free PSRAM : ")); DEBUG_PRINT(ESP.getFreePsram()/1024); DEBUG_PRINTLN("kB"); | ||
} | ||
|
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all esp32 boards (including S3, S2) have defined(ARDUINO_ARCH_ESP32).
Chip revision of S2 and S3 is either 0 or 1; so this line could (unnecessarily) disabled PSRAM on the new MCUs.