Verilog implementation of an ordinary differential equation solver accelerator chip
Solving ordinary differential equations is a crucial part of modeling and simulating systems. It is used in order to model how a system state changes over time. Simulating models help us with designing systems and controllers. Solving an ODE analytically can be a very hard and sometimes impossible approach. Therefore, it is a common practice to solve ODE using approximation numerical methods. This project is a synthesizable Verliog implementation of a detailed low-level design of a chip that provides multiple solvers for an ODE. It is a stand-alone chip that reads the system’s data from the user, applies the chosen solver, and generates the output. Solving complicated systems ODEs can be very costly.
The chip is designed to solve the following equation:
Where:
is a vector of size 
that represents the state of the system
is a matrix of size 
is a vector of size 
that represents external input to the system
is a matrix of size 
The chip consists of four main modules, IO module, forward Euler solver, interpolation module and step algorithm module.
- The IO module is responsible for loading the initial state of the system, the system parameters, and the solver options.
- The forward euler solver module is responsible for calculating of the next time step
. - The time step algorithm module is responsible for calculating the timer step depending on the chosen mode.
- The interpolation module is responsible for calculating at unknown timesteps.
- The coordinator orchestrates the execution of the chip through its different execution steps
