This repository provides characterization data collected over 96 DDR3 SO-DIMMs, related to the following papers.
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Lee et al., "Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms ", SIGMETRICS 2017
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Lee et al., "Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips", arXiv:1610.09604
- This directory contains the SPICE model of a DRAM array, which is used for the simulation data in APPENDIX B of the SIGMECTRISC 2017 paper. The tool used for the simulation is LTspice.
- This directory contains the data collected from our experiments.
- vendor/summary: contains a quick overview of how many error bits are observed at different DRAM test conditions.
- vendor/rawdata: contains detailed error information of the evaluated DIMMs, which is used for Sections 5 and 6 of the SITMECTRIC 2017 paper.
- vendor/analysis: contains the collected and analyzed data for the papers.