DE10Pro revE project

Makefile

@@ -14,5 +14,6 @@ clean:
 	make -C apps clean
 	make -C src clean
 	make -C de10-pro clean
+	make -C de10-pro-e clean
 	make -C sim clean
 	make -C pebbles clean

apps/Common/app.mk

@@ -66,7 +66,8 @@ link.ld: $(SIMTIGHT_APPS_ROOT)/Common/link.ld.h
 Run: checkenv code.v data.v $(RUN_CPP) $(RUN_H)
 	g++ -std=c++11 -O2 -I $(PEBBLES_ROOT)/inc \
     -I $(SIMTIGHT_ROOT)/inc -o Run $(RUN_CPP) \
-    -fno-exceptions -ljtag_atlantic -ljtag_client \
+    -fno-exceptions -ljtag_atlantic -lpthread \
+    -Wl,--no-as-needed -ljtag_client \
     -L $(QUARTUS_ROOTDIR)/linux64/ -Wl,-rpath,$(QUARTUS_ROOTDIR)/linux64
 
 RunSim: code.v data.v $(RUN_CPP) $(RUN_H)

apps/TestSuite/Makefile

@@ -99,7 +99,8 @@ StartSIMT.o: StartSIMT.cpp
 TestCPU: checkenv TestCPU.cpp
 	@g++ -std=c++11 -O2 -I $(PEBBLES_ROOT)/inc -o TestCPU TestCPU.cpp \
     -I $(SIMTIGHT_ROOT)/inc \
-    -fno-exceptions -ljtag_atlantic -ljtag_client \
+        -fno-exceptions -lpthread -ljtag_atlantic \
+    -Wl,--no-as-needed -ljtag_client \
     -L $(QUARTUS_ROOTDIR)/linux64/ -Wl,-rpath,$(QUARTUS_ROOTDIR)/linux64
 
 TestCPUSim: TestCPU.cpp
@@ -110,7 +111,8 @@ TestCPUSim: TestCPU.cpp
 TestSIMT: checkenv TestSIMT.cpp
 	@g++ -std=c++11 -O2 -I $(PEBBLES_ROOT)/inc -o TestSIMT TestSIMT.cpp \
     -I $(SIMTIGHT_ROOT)/inc \
-    -fno-exceptions -ljtag_atlantic -ljtag_client \
+    -fno-exceptions -lpthread -ljtag_atlantic \
+    -Wl,--no-as-needed -ljtag_client \
     -L $(QUARTUS_ROOTDIR)/linux64/ -Wl,-rpath,$(QUARTUS_ROOTDIR)/linux64
 
 TestSIMTSim: TestSIMT.cpp

boot/Makefile

@@ -56,7 +56,7 @@ LOG_INSTR_BYTES = $(shell echo -n CPUInstrMemLogWords \
 INSTR_BYTES = $(shell echo "3 * (2 ^ $(LOG_INSTR_BYTES))" | bc)
 
 .PHONY: all
-all: $(SIM)/boot.hex ../de10-pro/boot.mif
+all: $(SIM)/boot.hex ../de10-pro/boot.mif ../de10-pro-e/boot.mif
 
 link.ld: link.ld.h
 	cpp -P -I $(SIMTIGHT_ROOT)/inc link.ld.h > link.ld
@@ -69,6 +69,9 @@ $(SIM)/boot.hex: InstrMem.ihex
 	./ihex-to-img.py InstrMem.ihex mif $(INSTR_BASE) 4 $(INSTR_BYTES) 1 \
     > ../de10-pro/boot.mif
 
+../de10-pro-e/boot.mif: ../de10-pro/boot.mif
+	cp ../de10-pro/boot.mif ../de10-pro-e/boot.mif
+
 InstrMem.ihex: out.elf
 	$(RV_OBJCOPY) --only-section=.text -O ihex out.elf InstrMem.ihex
 

de10-pro-e/DE10_Pro.qpf

@@ -0,0 +1,6 @@
+DATE = "Wed Jan 31 14:15:58 2018"
+QUARTUS_VERSION = "17.1.0"
+
+# Revisions
+
+PROJECT_REVISION = "DE10_Pro"

de10-pro-e/DE10_Pro.sdc

@@ -0,0 +1,101 @@
+#**************************************************************
+# This .sdc file is created by Terasic Tool.
+# Users are recommended to modify this file to match users logic.
+#**************************************************************
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+# CLOCK
+create_clock -period 10 [get_ports CLK_100_B3I]
+create_clock -period 20 [get_ports CLK_50_B2C]
+create_clock -period 20 [get_ports CLK_50_B2L]
+create_clock -period 20 [get_ports CLK_50_B3C]
+create_clock -period 20 [get_ports CLK_50_B3I]
+create_clock -period 20 [get_ports CLK_50_B3L]
+
+create_clock -period "266.666666 MHz" [get_ports DDR4A_REFCLK_p]
+create_clock -period "166.666666 MHz" [get_ports DDR4B_REFCLK_p]
+create_clock -period "166.666666 MHz" [get_ports DDR4C_REFCLK_p]
+create_clock -period "166.666666 MHz" [get_ports DDR4D_REFCLK_p]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+set_clock_groups -asynchronous -group {[get_clocks { CLK_50_B3I }]}
+set_clock_groups -asynchronous -group {[get_clocks { DDR4A_REFCLK_p }]}
+set_clock_groups -asynchronous -group {[get_clocks { DDR4B_REFCLK_p }]}
+set_clock_groups -asynchronous -group {[get_clocks { DDR4C_REFCLK_p }]}
+set_clock_groups -asynchronous -group {[get_clocks { DDR4D_REFCLK_p }]}
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+set_false_path -from * -to [get_cells {DE10_Pro_QSYS_inst|ddr4_status|pio_0|readdata*} ]
+set_false_path -from [get_ports CPU_RESET_n*] -to *
+set_false_path -from [get_ports BUTTON*] -to *
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+
+
+

de10-pro-e/DE10_Pro.v

@@ -0,0 +1,117 @@
+module DE10_Pro(
+  input CLK_100_B3I,
+  input CLK_50_B2C,
+  input CLK_50_B2L,
+  input CLK_50_B3C,
+  input CLK_50_B3I,
+  input CLK_50_B3L,
+
+  input CPU_RESET_n,
+  input [1:0] BUTTON,
+  input [1:0] SW,
+  output [3:0] LED,
+
+  inout SI5340A0_I2C_SCL,
+  inout SI5340A0_I2C_SDA,
+  input SI5340A0_INTR,
+  output SI5340A0_OE_n,
+  output SI5340A0_RST_n,
+
+  inout SI5340A1_I2C_SCL,
+  inout SI5340A1_I2C_SDA,
+  input SI5340A1_INTR,
+  output SI5340A1_OE_n,
+  output SI5340A1_RST_n,
+
+  output FLASH_CLK,
+  output [27:1] FLASH_A,
+  inout [15:0] FLASH_D,
+  output FLASH_CE_n,
+  output FLASH_WE_n,
+  output FLASH_OE_n,
+  output FLASH_ADV_n,
+  output FLASH_RESET_n,
+  input FLASH_RDY_BSY_n,
+
+  input  DDR4B_REFCLK_p,
+  output [16:0] DDR4B_A,
+  output [1:0] DDR4B_BA,
+  output [1:0] DDR4B_BG,
+  output DDR4B_CK,
+  output DDR4B_CK_n,
+  output DDR4B_CKE,
+  inout  [8:0] DDR4B_DQS,
+  inout  [8:0] DDR4B_DQS_n,
+  inout  [71:0] DDR4B_DQ,
+  inout  [8:0] DDR4B_DBI_n,
+  output DDR4B_CS_n,
+  output DDR4B_RESET_n,
+  output DDR4B_ODT,
+  output DDR4B_PAR,
+  input DDR4B_ALERT_n,
+  output DDR4B_ACT_n,
+  input DDR4B_EVENT_n,
+  inout DDR4B_SCL,
+  inout DDR4B_SDA,
+  input DDR4B_RZQ,
+
+  input EXP_EN,
+
+  inout UFL_CLKIN_p,
+  inout UFL_CLKIN_n
+);
+
+wire reset_n;
+wire ddr4_local_reset_req;
+
+wire ddr4_b_local_reset_done;
+wire ddr4_b_status_local_cal_fail;
+wire ddr4_b_status_local_cal_success;
+
+wire [11:0] ddr4_status;
+
+// Reset release
+wire ninit_done;
+reset_release reset_release (
+        .ninit_done(ninit_done)
+        );
+
+assign reset_n = !ninit_done && CPU_RESET_n;
+assign ddr4_status =
+  {ddr4_b_status_local_cal_fail,
+     ddr4_b_status_local_cal_success,
+       ddr4_b_local_reset_done};
+
+DE10_Pro_QSYS DE10_Pro_QSYS_inst (
+        .clk_clk(CLK_50_B3I),
+        .reset_reset(~reset_n),
+        .emif_s10_ddr4_b_mem_mem_ck(DDR4B_CK),                          
+        .emif_s10_ddr4_b_mem_mem_ck_n(DDR4B_CK_n),                        
+        .emif_s10_ddr4_b_mem_mem_a(DDR4B_A),                           
+        .emif_s10_ddr4_b_mem_mem_act_n(DDR4B_ACT_n),                       
+        .emif_s10_ddr4_b_mem_mem_ba(DDR4B_BA),                          
+        .emif_s10_ddr4_b_mem_mem_bg(DDR4B_BG),                          
+        .emif_s10_ddr4_b_mem_mem_cke(DDR4B_CKE),                         
+        .emif_s10_ddr4_b_mem_mem_cs_n(DDR4B_CS_n),                        
+        .emif_s10_ddr4_b_mem_mem_odt(DDR4B_ODT),                         
+        .emif_s10_ddr4_b_mem_mem_reset_n(DDR4B_RESET_n),                     
+        .emif_s10_ddr4_b_mem_mem_par(DDR4B_PAR),                         
+        .emif_s10_ddr4_b_mem_mem_alert_n(DDR4B_ALERT_n),                     
+        .emif_s10_ddr4_b_mem_mem_dqs(DDR4B_DQS),                         
+        .emif_s10_ddr4_b_mem_mem_dqs_n(DDR4B_DQS_n),                       
+        .emif_s10_ddr4_b_mem_mem_dq(DDR4B_DQ),                          
+        .emif_s10_ddr4_b_mem_mem_dbi_n(DDR4B_DBI_n),                       
+        .emif_s10_ddr4_b_oct_oct_rzqin(DDR4B_RZQ),                       
+        .emif_s10_ddr4_b_pll_ref_clk_clk(DDR4B_REFCLK_p),                     
+        .emif_s10_ddr4_b_status_local_cal_success(ddr4_b_status_local_cal_success),            
+        .emif_s10_ddr4_b_status_local_cal_fail(ddr4_b_status_local_cal_fail),   
+        .iopll_0_locked_export()
+    );
+
+assign SI5340A0_RST_n = 1'b1;
+assign SI5340A1_RST_n = 1'b1;
+
+assign SI5340A0_OE_n = 1'b0;
+assign SI5340A1_OE_n = 1'b0;
+
+endmodule